1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 mips_emit_delays ();
2115 if (! ECOFF_DEBUGGING)
2120 md_assemble (char *str)
2122 struct mips_cl_insn insn;
2123 bfd_reloc_code_real_type unused_reloc[3]
2124 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2126 imm_expr.X_op = O_absent;
2127 imm2_expr.X_op = O_absent;
2128 offset_expr.X_op = O_absent;
2129 imm_reloc[0] = BFD_RELOC_UNUSED;
2130 imm_reloc[1] = BFD_RELOC_UNUSED;
2131 imm_reloc[2] = BFD_RELOC_UNUSED;
2132 offset_reloc[0] = BFD_RELOC_UNUSED;
2133 offset_reloc[1] = BFD_RELOC_UNUSED;
2134 offset_reloc[2] = BFD_RELOC_UNUSED;
2136 if (mips_opts.mips16)
2137 mips16_ip (str, &insn);
2140 mips_ip (str, &insn);
2141 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2142 str, insn.insn_opcode));
2147 as_bad ("%s `%s'", insn_error, str);
2151 if (insn.insn_mo->pinfo == INSN_MACRO)
2154 if (mips_opts.mips16)
2155 mips16_macro (&insn);
2162 if (imm_expr.X_op != O_absent)
2163 append_insn (&insn, &imm_expr, imm_reloc);
2164 else if (offset_expr.X_op != O_absent)
2165 append_insn (&insn, &offset_expr, offset_reloc);
2167 append_insn (&insn, NULL, unused_reloc);
2171 /* Convenience functions for abstracting away the differences between
2172 MIPS16 and non-MIPS16 relocations. */
2174 static inline bfd_boolean
2175 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2179 case BFD_RELOC_MIPS16_JMP:
2180 case BFD_RELOC_MIPS16_GPREL:
2181 case BFD_RELOC_MIPS16_GOT16:
2182 case BFD_RELOC_MIPS16_CALL16:
2183 case BFD_RELOC_MIPS16_HI16_S:
2184 case BFD_RELOC_MIPS16_HI16:
2185 case BFD_RELOC_MIPS16_LO16:
2193 static inline bfd_boolean
2194 got16_reloc_p (bfd_reloc_code_real_type reloc)
2196 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2199 static inline bfd_boolean
2200 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2202 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2205 static inline bfd_boolean
2206 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2208 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2211 /* Return true if the given relocation might need a matching %lo().
2212 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2213 need a matching %lo() when applied to local symbols. */
2215 static inline bfd_boolean
2216 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2218 return (HAVE_IN_PLACE_ADDENDS
2219 && (hi16_reloc_p (reloc)
2220 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2221 all GOT16 relocations evaluate to "G". */
2222 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2225 /* Return the type of %lo() reloc needed by RELOC, given that
2226 reloc_needs_lo_p. */
2228 static inline bfd_reloc_code_real_type
2229 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2231 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2234 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2237 static inline bfd_boolean
2238 fixup_has_matching_lo_p (fixS *fixp)
2240 return (fixp->fx_next != NULL
2241 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2242 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2243 && fixp->fx_offset == fixp->fx_next->fx_offset);
2246 /* This function returns true if modifying a register requires a
2250 reg_needs_delay (unsigned int reg)
2252 unsigned long prev_pinfo;
2254 prev_pinfo = history[0].insn_mo->pinfo;
2255 if (! mips_opts.noreorder
2256 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2257 && ! gpr_interlocks)
2258 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2259 && ! cop_interlocks)))
2261 /* A load from a coprocessor or from memory. All load delays
2262 delay the use of general register rt for one instruction. */
2263 /* Itbl support may require additional care here. */
2264 know (prev_pinfo & INSN_WRITE_GPR_T);
2265 if (reg == EXTRACT_OPERAND (RT, history[0]))
2272 /* Move all labels in insn_labels to the current insertion point. */
2275 mips_move_labels (void)
2277 segment_info_type *si = seg_info (now_seg);
2278 struct insn_label_list *l;
2281 for (l = si->label_list; l != NULL; l = l->next)
2283 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2284 symbol_set_frag (l->label, frag_now);
2285 val = (valueT) frag_now_fix ();
2286 /* mips16 text labels are stored as odd. */
2287 if (mips_opts.mips16)
2289 S_SET_VALUE (l->label, val);
2294 s_is_linkonce (symbolS *sym, segT from_seg)
2296 bfd_boolean linkonce = FALSE;
2297 segT symseg = S_GET_SEGMENT (sym);
2299 if (symseg != from_seg && !S_IS_LOCAL (sym))
2301 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2304 /* The GNU toolchain uses an extension for ELF: a section
2305 beginning with the magic string .gnu.linkonce is a
2306 linkonce section. */
2307 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2308 sizeof ".gnu.linkonce" - 1) == 0)
2315 /* Mark instruction labels in mips16 mode. This permits the linker to
2316 handle them specially, such as generating jalx instructions when
2317 needed. We also make them odd for the duration of the assembly, in
2318 order to generate the right sort of code. We will make them even
2319 in the adjust_symtab routine, while leaving them marked. This is
2320 convenient for the debugger and the disassembler. The linker knows
2321 to make them odd again. */
2324 mips16_mark_labels (void)
2326 segment_info_type *si = seg_info (now_seg);
2327 struct insn_label_list *l;
2329 if (!mips_opts.mips16)
2332 for (l = si->label_list; l != NULL; l = l->next)
2334 symbolS *label = l->label;
2336 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2338 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2340 if ((S_GET_VALUE (label) & 1) == 0
2341 /* Don't adjust the address if the label is global or weak, or
2342 in a link-once section, since we'll be emitting symbol reloc
2343 references to it which will be patched up by the linker, and
2344 the final value of the symbol may or may not be MIPS16. */
2345 && ! S_IS_WEAK (label)
2346 && ! S_IS_EXTERNAL (label)
2347 && ! s_is_linkonce (label, now_seg))
2348 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2352 /* End the current frag. Make it a variant frag and record the
2356 relax_close_frag (void)
2358 mips_macro_warning.first_frag = frag_now;
2359 frag_var (rs_machine_dependent, 0, 0,
2360 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2361 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2363 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2364 mips_relax.first_fixup = 0;
2367 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2368 See the comment above RELAX_ENCODE for more details. */
2371 relax_start (symbolS *symbol)
2373 gas_assert (mips_relax.sequence == 0);
2374 mips_relax.sequence = 1;
2375 mips_relax.symbol = symbol;
2378 /* Start generating the second version of a relaxable sequence.
2379 See the comment above RELAX_ENCODE for more details. */
2384 gas_assert (mips_relax.sequence == 1);
2385 mips_relax.sequence = 2;
2388 /* End the current relaxable sequence. */
2393 gas_assert (mips_relax.sequence == 2);
2394 relax_close_frag ();
2395 mips_relax.sequence = 0;
2398 /* Return the mask of core registers that IP reads. */
2401 gpr_read_mask (const struct mips_cl_insn *ip)
2403 unsigned long pinfo, pinfo2;
2407 pinfo = ip->insn_mo->pinfo;
2408 pinfo2 = ip->insn_mo->pinfo2;
2409 if (mips_opts.mips16)
2411 if (pinfo & MIPS16_INSN_READ_X)
2412 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2413 if (pinfo & MIPS16_INSN_READ_Y)
2414 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2415 if (pinfo & MIPS16_INSN_READ_T)
2417 if (pinfo & MIPS16_INSN_READ_SP)
2419 if (pinfo & MIPS16_INSN_READ_31)
2421 if (pinfo & MIPS16_INSN_READ_Z)
2422 mask |= 1 << (mips16_to_32_reg_map
2423 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2424 if (pinfo & MIPS16_INSN_READ_GPR_X)
2425 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2429 if (pinfo2 & INSN2_READ_GPR_D)
2430 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2431 if (pinfo & INSN_READ_GPR_T)
2432 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2433 if (pinfo & INSN_READ_GPR_S)
2434 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2435 if (pinfo2 & INSN2_READ_GPR_Z)
2436 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2441 /* Return the mask of core registers that IP writes. */
2444 gpr_write_mask (const struct mips_cl_insn *ip)
2446 unsigned long pinfo, pinfo2;
2450 pinfo = ip->insn_mo->pinfo;
2451 pinfo2 = ip->insn_mo->pinfo2;
2452 if (mips_opts.mips16)
2454 if (pinfo & MIPS16_INSN_WRITE_X)
2455 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2456 if (pinfo & MIPS16_INSN_WRITE_Y)
2457 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2458 if (pinfo & MIPS16_INSN_WRITE_Z)
2459 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2460 if (pinfo & MIPS16_INSN_WRITE_T)
2462 if (pinfo & MIPS16_INSN_WRITE_SP)
2464 if (pinfo & MIPS16_INSN_WRITE_31)
2466 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2467 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2471 if (pinfo & INSN_WRITE_GPR_D)
2472 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2473 if (pinfo & INSN_WRITE_GPR_T)
2474 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2475 if (pinfo & INSN_WRITE_GPR_31)
2477 if (pinfo2 & INSN2_WRITE_GPR_Z)
2478 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2483 /* Return the mask of floating-point registers that IP reads. */
2486 fpr_read_mask (const struct mips_cl_insn *ip)
2488 unsigned long pinfo, pinfo2;
2492 pinfo = ip->insn_mo->pinfo;
2493 pinfo2 = ip->insn_mo->pinfo2;
2494 if (!mips_opts.mips16)
2496 if (pinfo & INSN_READ_FPR_S)
2497 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2498 if (pinfo & INSN_READ_FPR_T)
2499 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2500 if (pinfo & INSN_READ_FPR_R)
2501 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2502 if (pinfo2 & INSN2_READ_FPR_Z)
2503 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2505 /* Conservatively treat all operands to an FP_D instruction are doubles.
2506 (This is overly pessimistic for things like cvt.d.s.) */
2507 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2512 /* Return the mask of floating-point registers that IP writes. */
2515 fpr_write_mask (const struct mips_cl_insn *ip)
2517 unsigned long pinfo, pinfo2;
2521 pinfo = ip->insn_mo->pinfo;
2522 pinfo2 = ip->insn_mo->pinfo2;
2523 if (!mips_opts.mips16)
2525 if (pinfo & INSN_WRITE_FPR_D)
2526 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2527 if (pinfo & INSN_WRITE_FPR_S)
2528 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2529 if (pinfo & INSN_WRITE_FPR_T)
2530 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2531 if (pinfo2 & INSN2_WRITE_FPR_Z)
2532 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2534 /* Conservatively treat all operands to an FP_D instruction are doubles.
2535 (This is overly pessimistic for things like cvt.s.d.) */
2536 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2541 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2542 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2543 by VR4120 errata. */
2546 classify_vr4120_insn (const char *name)
2548 if (strncmp (name, "macc", 4) == 0)
2549 return FIX_VR4120_MACC;
2550 if (strncmp (name, "dmacc", 5) == 0)
2551 return FIX_VR4120_DMACC;
2552 if (strncmp (name, "mult", 4) == 0)
2553 return FIX_VR4120_MULT;
2554 if (strncmp (name, "dmult", 5) == 0)
2555 return FIX_VR4120_DMULT;
2556 if (strstr (name, "div"))
2557 return FIX_VR4120_DIV;
2558 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2559 return FIX_VR4120_MTHILO;
2560 return NUM_FIX_VR4120_CLASSES;
2563 #define INSN_ERET 0x42000018
2564 #define INSN_DERET 0x4200001f
2566 /* Return the number of instructions that must separate INSN1 and INSN2,
2567 where INSN1 is the earlier instruction. Return the worst-case value
2568 for any INSN2 if INSN2 is null. */
2571 insns_between (const struct mips_cl_insn *insn1,
2572 const struct mips_cl_insn *insn2)
2574 unsigned long pinfo1, pinfo2;
2577 /* This function needs to know which pinfo flags are set for INSN2
2578 and which registers INSN2 uses. The former is stored in PINFO2 and
2579 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2580 will have every flag set and INSN2_USES_GPR will always return true. */
2581 pinfo1 = insn1->insn_mo->pinfo;
2582 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2584 #define INSN2_USES_GPR(REG) \
2585 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2587 /* For most targets, write-after-read dependencies on the HI and LO
2588 registers must be separated by at least two instructions. */
2589 if (!hilo_interlocks)
2591 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2593 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2597 /* If we're working around r7000 errata, there must be two instructions
2598 between an mfhi or mflo and any instruction that uses the result. */
2599 if (mips_7000_hilo_fix
2600 && MF_HILO_INSN (pinfo1)
2601 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2604 /* If we're working around 24K errata, one instruction is required
2605 if an ERET or DERET is followed by a branch instruction. */
2608 if (insn1->insn_opcode == INSN_ERET
2609 || insn1->insn_opcode == INSN_DERET)
2612 || insn2->insn_opcode == INSN_ERET
2613 || insn2->insn_opcode == INSN_DERET
2614 || (insn2->insn_mo->pinfo
2615 & (INSN_UNCOND_BRANCH_DELAY
2616 | INSN_COND_BRANCH_DELAY
2617 | INSN_COND_BRANCH_LIKELY)) != 0)
2622 /* If working around VR4120 errata, check for combinations that need
2623 a single intervening instruction. */
2624 if (mips_fix_vr4120)
2626 unsigned int class1, class2;
2628 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2629 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2633 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2634 if (vr4120_conflicts[class1] & (1 << class2))
2639 if (!mips_opts.mips16)
2641 /* Check for GPR or coprocessor load delays. All such delays
2642 are on the RT register. */
2643 /* Itbl support may require additional care here. */
2644 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2645 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2647 know (pinfo1 & INSN_WRITE_GPR_T);
2648 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2652 /* Check for generic coprocessor hazards.
2654 This case is not handled very well. There is no special
2655 knowledge of CP0 handling, and the coprocessors other than
2656 the floating point unit are not distinguished at all. */
2657 /* Itbl support may require additional care here. FIXME!
2658 Need to modify this to include knowledge about
2659 user specified delays! */
2660 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2661 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2663 /* Handle cases where INSN1 writes to a known general coprocessor
2664 register. There must be a one instruction delay before INSN2
2665 if INSN2 reads that register, otherwise no delay is needed. */
2666 mask = fpr_write_mask (insn1);
2669 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2674 /* Read-after-write dependencies on the control registers
2675 require a two-instruction gap. */
2676 if ((pinfo1 & INSN_WRITE_COND_CODE)
2677 && (pinfo2 & INSN_READ_COND_CODE))
2680 /* We don't know exactly what INSN1 does. If INSN2 is
2681 also a coprocessor instruction, assume there must be
2682 a one instruction gap. */
2683 if (pinfo2 & INSN_COP)
2688 /* Check for read-after-write dependencies on the coprocessor
2689 control registers in cases where INSN1 does not need a general
2690 coprocessor delay. This means that INSN1 is a floating point
2691 comparison instruction. */
2692 /* Itbl support may require additional care here. */
2693 else if (!cop_interlocks
2694 && (pinfo1 & INSN_WRITE_COND_CODE)
2695 && (pinfo2 & INSN_READ_COND_CODE))
2699 #undef INSN2_USES_GPR
2704 /* Return the number of nops that would be needed to work around the
2705 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2706 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2707 that are contained within the first IGNORE instructions of HIST. */
2710 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2711 const struct mips_cl_insn *insn)
2716 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2717 are not affected by the errata. */
2719 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2720 || strcmp (insn->insn_mo->name, "mtlo") == 0
2721 || strcmp (insn->insn_mo->name, "mthi") == 0))
2724 /* Search for the first MFLO or MFHI. */
2725 for (i = 0; i < MAX_VR4130_NOPS; i++)
2726 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2728 /* Extract the destination register. */
2729 mask = gpr_write_mask (&hist[i]);
2731 /* No nops are needed if INSN reads that register. */
2732 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2735 /* ...or if any of the intervening instructions do. */
2736 for (j = 0; j < i; j++)
2737 if (gpr_read_mask (&hist[j]) & mask)
2741 return MAX_VR4130_NOPS - i;
2746 #define BASE_REG_EQ(INSN1, INSN2) \
2747 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2748 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2750 /* Return the minimum alignment for this store instruction. */
2753 fix_24k_align_to (const struct mips_opcode *mo)
2755 if (strcmp (mo->name, "sh") == 0)
2758 if (strcmp (mo->name, "swc1") == 0
2759 || strcmp (mo->name, "swc2") == 0
2760 || strcmp (mo->name, "sw") == 0
2761 || strcmp (mo->name, "sc") == 0
2762 || strcmp (mo->name, "s.s") == 0)
2765 if (strcmp (mo->name, "sdc1") == 0
2766 || strcmp (mo->name, "sdc2") == 0
2767 || strcmp (mo->name, "s.d") == 0)
2774 struct fix_24k_store_info
2776 /* Immediate offset, if any, for this store instruction. */
2778 /* Alignment required by this store instruction. */
2780 /* True for register offsets. */
2781 int register_offset;
2784 /* Comparison function used by qsort. */
2787 fix_24k_sort (const void *a, const void *b)
2789 const struct fix_24k_store_info *pos1 = a;
2790 const struct fix_24k_store_info *pos2 = b;
2792 return (pos1->off - pos2->off);
2795 /* INSN is a store instruction. Try to record the store information
2796 in STINFO. Return false if the information isn't known. */
2799 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2800 const struct mips_cl_insn *insn)
2802 /* The instruction must have a known offset. */
2803 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2806 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2807 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2811 /* Return the number of nops that would be needed to work around the 24k
2812 "lost data on stores during refill" errata if instruction INSN
2813 immediately followed the 2 instructions described by HIST.
2814 Ignore hazards that are contained within the first IGNORE
2815 instructions of HIST.
2817 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2818 for the data cache refills and store data. The following describes
2819 the scenario where the store data could be lost.
2821 * A data cache miss, due to either a load or a store, causing fill
2822 data to be supplied by the memory subsystem
2823 * The first three doublewords of fill data are returned and written
2825 * A sequence of four stores occurs in consecutive cycles around the
2826 final doubleword of the fill:
2830 * Zero, One or more instructions
2833 The four stores A-D must be to different doublewords of the line that
2834 is being filled. The fourth instruction in the sequence above permits
2835 the fill of the final doubleword to be transferred from the FSB into
2836 the cache. In the sequence above, the stores may be either integer
2837 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2838 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2839 different doublewords on the line. If the floating point unit is
2840 running in 1:2 mode, it is not possible to create the sequence above
2841 using only floating point store instructions.
2843 In this case, the cache line being filled is incorrectly marked
2844 invalid, thereby losing the data from any store to the line that
2845 occurs between the original miss and the completion of the five
2846 cycle sequence shown above.
2848 The workarounds are:
2850 * Run the data cache in write-through mode.
2851 * Insert a non-store instruction between
2852 Store A and Store B or Store B and Store C. */
2855 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2856 const struct mips_cl_insn *insn)
2858 struct fix_24k_store_info pos[3];
2859 int align, i, base_offset;
2864 /* If the previous instruction wasn't a store, there's nothing to
2866 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2869 /* If the instructions after the previous one are unknown, we have
2870 to assume the worst. */
2874 /* Check whether we are dealing with three consecutive stores. */
2875 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2876 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2879 /* If we don't know the relationship between the store addresses,
2880 assume the worst. */
2881 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2882 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2885 if (!fix_24k_record_store_info (&pos[0], insn)
2886 || !fix_24k_record_store_info (&pos[1], &hist[0])
2887 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2890 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2892 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2893 X bytes and such that the base register + X is known to be aligned
2896 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2900 align = pos[0].align_to;
2901 base_offset = pos[0].off;
2902 for (i = 1; i < 3; i++)
2903 if (align < pos[i].align_to)
2905 align = pos[i].align_to;
2906 base_offset = pos[i].off;
2908 for (i = 0; i < 3; i++)
2909 pos[i].off -= base_offset;
2912 pos[0].off &= ~align + 1;
2913 pos[1].off &= ~align + 1;
2914 pos[2].off &= ~align + 1;
2916 /* If any two stores write to the same chunk, they also write to the
2917 same doubleword. The offsets are still sorted at this point. */
2918 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2921 /* A range of at least 9 bytes is needed for the stores to be in
2922 non-overlapping doublewords. */
2923 if (pos[2].off - pos[0].off <= 8)
2926 if (pos[2].off - pos[1].off >= 24
2927 || pos[1].off - pos[0].off >= 24
2928 || pos[2].off - pos[0].off >= 32)
2934 /* Return the number of nops that would be needed if instruction INSN
2935 immediately followed the MAX_NOPS instructions given by HIST,
2936 where HIST[0] is the most recent instruction. Ignore hazards
2937 between INSN and the first IGNORE instructions in HIST.
2939 If INSN is null, return the worse-case number of nops for any
2943 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2944 const struct mips_cl_insn *insn)
2946 int i, nops, tmp_nops;
2949 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2951 tmp_nops = insns_between (hist + i, insn) - i;
2952 if (tmp_nops > nops)
2956 if (mips_fix_vr4130)
2958 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2959 if (tmp_nops > nops)
2965 tmp_nops = nops_for_24k (ignore, hist, insn);
2966 if (tmp_nops > nops)
2973 /* The variable arguments provide NUM_INSNS extra instructions that
2974 might be added to HIST. Return the largest number of nops that
2975 would be needed after the extended sequence, ignoring hazards
2976 in the first IGNORE instructions. */
2979 nops_for_sequence (int num_insns, int ignore,
2980 const struct mips_cl_insn *hist, ...)
2983 struct mips_cl_insn buffer[MAX_NOPS];
2984 struct mips_cl_insn *cursor;
2987 va_start (args, hist);
2988 cursor = buffer + num_insns;
2989 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2990 while (cursor > buffer)
2991 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2993 nops = nops_for_insn (ignore, buffer, NULL);
2998 /* Like nops_for_insn, but if INSN is a branch, take into account the
2999 worst-case delay for the branch target. */
3002 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3003 const struct mips_cl_insn *insn)
3007 nops = nops_for_insn (ignore, hist, insn);
3008 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3009 | INSN_COND_BRANCH_DELAY
3010 | INSN_COND_BRANCH_LIKELY))
3012 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3013 hist, insn, NOP_INSN);
3014 if (tmp_nops > nops)
3017 else if (mips_opts.mips16
3018 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3019 | MIPS16_INSN_COND_BRANCH)))
3021 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3022 if (tmp_nops > nops)
3028 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3031 fix_loongson2f_nop (struct mips_cl_insn * ip)
3033 if (strcmp (ip->insn_mo->name, "nop") == 0)
3034 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3037 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3038 jr target pc &= 'hffff_ffff_cfff_ffff. */
3041 fix_loongson2f_jump (struct mips_cl_insn * ip)
3043 if (strcmp (ip->insn_mo->name, "j") == 0
3044 || strcmp (ip->insn_mo->name, "jr") == 0
3045 || strcmp (ip->insn_mo->name, "jalr") == 0)
3053 sreg = EXTRACT_OPERAND (RS, *ip);
3054 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3057 ep.X_op = O_constant;
3058 ep.X_add_number = 0xcfff0000;
3059 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3060 ep.X_add_number = 0xffff;
3061 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3062 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3067 fix_loongson2f (struct mips_cl_insn * ip)
3069 if (mips_fix_loongson2f_nop)
3070 fix_loongson2f_nop (ip);
3072 if (mips_fix_loongson2f_jump)
3073 fix_loongson2f_jump (ip);
3076 /* IP is a MIPS16 instruction whose opcode we have just changed.
3077 Point IP->insn_mo to the new opcode's definition. */
3080 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3082 const struct mips_opcode *mo, *end;
3084 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3085 for (mo = ip->insn_mo; mo < end; mo++)
3086 if ((ip->insn_opcode & mo->mask) == mo->match)
3094 /* Output an instruction. IP is the instruction information.
3095 ADDRESS_EXPR is an operand of the instruction to be used with
3099 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3100 bfd_reloc_code_real_type *reloc_type)
3102 unsigned long prev_pinfo, pinfo;
3103 unsigned long prev_pinfo2, pinfo2;
3104 relax_stateT prev_insn_frag_type = 0;
3105 bfd_boolean relaxed_branch = FALSE;
3106 segment_info_type *si = seg_info (now_seg);
3108 if (mips_fix_loongson2f)
3109 fix_loongson2f (ip);
3111 /* Mark instruction labels in mips16 mode. */
3112 mips16_mark_labels ();
3114 file_ase_mips16 |= mips_opts.mips16;
3116 prev_pinfo = history[0].insn_mo->pinfo;
3117 prev_pinfo2 = history[0].insn_mo->pinfo2;
3118 pinfo = ip->insn_mo->pinfo;
3119 pinfo2 = ip->insn_mo->pinfo2;
3121 if (address_expr == NULL)
3123 else if (*reloc_type <= BFD_RELOC_UNUSED
3124 && address_expr->X_op == O_constant)
3129 switch (*reloc_type)
3132 ip->insn_opcode |= address_expr->X_add_number;
3135 case BFD_RELOC_MIPS_HIGHEST:
3136 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3137 ip->insn_opcode |= tmp & 0xffff;
3140 case BFD_RELOC_MIPS_HIGHER:
3141 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3142 ip->insn_opcode |= tmp & 0xffff;
3145 case BFD_RELOC_HI16_S:
3146 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3147 ip->insn_opcode |= tmp & 0xffff;
3150 case BFD_RELOC_HI16:
3151 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3154 case BFD_RELOC_UNUSED:
3155 case BFD_RELOC_LO16:
3156 case BFD_RELOC_MIPS_GOT_DISP:
3157 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3160 case BFD_RELOC_MIPS_JMP:
3161 if ((address_expr->X_add_number & 3) != 0)
3162 as_bad (_("jump to misaligned address (0x%lx)"),
3163 (unsigned long) address_expr->X_add_number);
3164 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3168 case BFD_RELOC_MIPS16_JMP:
3169 if ((address_expr->X_add_number & 3) != 0)
3170 as_bad (_("jump to misaligned address (0x%lx)"),
3171 (unsigned long) address_expr->X_add_number);
3173 (((address_expr->X_add_number & 0x7c0000) << 3)
3174 | ((address_expr->X_add_number & 0xf800000) >> 7)
3175 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3179 case BFD_RELOC_16_PCREL_S2:
3180 if ((address_expr->X_add_number & 3) != 0)
3181 as_bad (_("branch to misaligned address (0x%lx)"),
3182 (unsigned long) address_expr->X_add_number);
3183 if (mips_relax_branch)
3185 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3186 as_bad (_("branch address range overflow (0x%lx)"),
3187 (unsigned long) address_expr->X_add_number);
3188 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3197 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3199 /* There are a lot of optimizations we could do that we don't.
3200 In particular, we do not, in general, reorder instructions.
3201 If you use gcc with optimization, it will reorder
3202 instructions and generally do much more optimization then we
3203 do here; repeating all that work in the assembler would only
3204 benefit hand written assembly code, and does not seem worth
3206 int nops = (mips_optimize == 0
3207 ? nops_for_insn (0, history, NULL)
3208 : nops_for_insn_or_target (0, history, ip));
3212 unsigned long old_frag_offset;
3215 old_frag = frag_now;
3216 old_frag_offset = frag_now_fix ();
3218 for (i = 0; i < nops; i++)
3223 listing_prev_line ();
3224 /* We may be at the start of a variant frag. In case we
3225 are, make sure there is enough space for the frag
3226 after the frags created by listing_prev_line. The
3227 argument to frag_grow here must be at least as large
3228 as the argument to all other calls to frag_grow in
3229 this file. We don't have to worry about being in the
3230 middle of a variant frag, because the variants insert
3231 all needed nop instructions themselves. */
3235 mips_move_labels ();
3237 #ifndef NO_ECOFF_DEBUGGING
3238 if (ECOFF_DEBUGGING)
3239 ecoff_fix_loc (old_frag, old_frag_offset);
3243 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3247 /* Work out how many nops in prev_nop_frag are needed by IP,
3248 ignoring hazards generated by the first prev_nop_frag_since
3250 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3251 gas_assert (nops <= prev_nop_frag_holds);
3253 /* Enforce NOPS as a minimum. */
3254 if (nops > prev_nop_frag_required)
3255 prev_nop_frag_required = nops;
3257 if (prev_nop_frag_holds == prev_nop_frag_required)
3259 /* Settle for the current number of nops. Update the history
3260 accordingly (for the benefit of any future .set reorder code). */
3261 prev_nop_frag = NULL;
3262 insert_into_history (prev_nop_frag_since,
3263 prev_nop_frag_holds, NOP_INSN);
3267 /* Allow this instruction to replace one of the nops that was
3268 tentatively added to prev_nop_frag. */
3269 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3270 prev_nop_frag_holds--;
3271 prev_nop_frag_since++;
3276 /* The value passed to dwarf2_emit_insn is the distance between
3277 the beginning of the current instruction and the address that
3278 should be recorded in the debug tables. For MIPS16 debug info
3279 we want to use ISA-encoded addresses, so we pass -1 for an
3280 address higher by one than the current. */
3281 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3284 /* Record the frag type before frag_var. */
3285 if (history[0].frag)
3286 prev_insn_frag_type = history[0].frag->fr_type;
3289 && *reloc_type == BFD_RELOC_16_PCREL_S2
3290 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3291 || pinfo & INSN_COND_BRANCH_LIKELY)
3292 && mips_relax_branch
3293 /* Don't try branch relaxation within .set nomacro, or within
3294 .set noat if we use $at for PIC computations. If it turns
3295 out that the branch was out-of-range, we'll get an error. */
3296 && !mips_opts.warn_about_macros
3297 && (mips_opts.at || mips_pic == NO_PIC)
3298 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3299 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3300 && !mips_opts.mips16)
3302 relaxed_branch = TRUE;
3303 add_relaxed_insn (ip, (relaxed_branch_length
3305 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3306 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3310 pinfo & INSN_UNCOND_BRANCH_DELAY,
3311 pinfo & INSN_COND_BRANCH_LIKELY,
3312 pinfo & INSN_WRITE_GPR_31,
3314 address_expr->X_add_symbol,
3315 address_expr->X_add_number);
3316 *reloc_type = BFD_RELOC_UNUSED;
3318 else if (*reloc_type > BFD_RELOC_UNUSED)
3320 /* We need to set up a variant frag. */
3321 gas_assert (mips_opts.mips16 && address_expr != NULL);
3322 add_relaxed_insn (ip, 4, 0,
3324 (*reloc_type - BFD_RELOC_UNUSED,
3325 mips16_small, mips16_ext,
3326 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3327 history[0].mips16_absolute_jump_p),
3328 make_expr_symbol (address_expr), 0);
3330 else if (mips_opts.mips16
3332 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3334 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3335 /* Make sure there is enough room to swap this instruction with
3336 a following jump instruction. */
3338 add_fixed_insn (ip);
3342 if (mips_opts.mips16
3343 && mips_opts.noreorder
3344 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3345 as_warn (_("extended instruction in delay slot"));
3347 if (mips_relax.sequence)
3349 /* If we've reached the end of this frag, turn it into a variant
3350 frag and record the information for the instructions we've
3352 if (frag_room () < 4)
3353 relax_close_frag ();
3354 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3357 if (mips_relax.sequence != 2)
3358 mips_macro_warning.sizes[0] += 4;
3359 if (mips_relax.sequence != 1)
3360 mips_macro_warning.sizes[1] += 4;
3362 if (mips_opts.mips16)
3365 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3367 add_fixed_insn (ip);
3370 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3373 && *reloc_type < BFD_RELOC_UNUSED)
3376 reloc_howto_type *howto;
3379 /* In a compound relocation, it is the final (outermost)
3380 operator that determines the relocated field. */
3381 for (i = 1; i < 3; i++)
3382 if (reloc_type[i] == BFD_RELOC_UNUSED)
3385 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3388 /* To reproduce this failure try assembling gas/testsuites/
3389 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3391 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3392 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3395 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3396 bfd_get_reloc_size (howto),
3398 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3401 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3402 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3403 && ip->fixp[0]->fx_addsy)
3404 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3406 /* These relocations can have an addend that won't fit in
3407 4 octets for 64bit assembly. */
3409 && ! howto->partial_inplace
3410 && (reloc_type[0] == BFD_RELOC_16
3411 || reloc_type[0] == BFD_RELOC_32
3412 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3413 || reloc_type[0] == BFD_RELOC_GPREL16
3414 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3415 || reloc_type[0] == BFD_RELOC_GPREL32
3416 || reloc_type[0] == BFD_RELOC_64
3417 || reloc_type[0] == BFD_RELOC_CTOR
3418 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3419 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3420 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3421 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3422 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3423 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3424 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3425 || hi16_reloc_p (reloc_type[0])
3426 || lo16_reloc_p (reloc_type[0])))
3427 ip->fixp[0]->fx_no_overflow = 1;
3429 if (mips_relax.sequence)
3431 if (mips_relax.first_fixup == 0)
3432 mips_relax.first_fixup = ip->fixp[0];
3434 else if (reloc_needs_lo_p (*reloc_type))
3436 struct mips_hi_fixup *hi_fixup;
3438 /* Reuse the last entry if it already has a matching %lo. */
3439 hi_fixup = mips_hi_fixup_list;
3441 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3443 hi_fixup = ((struct mips_hi_fixup *)
3444 xmalloc (sizeof (struct mips_hi_fixup)));
3445 hi_fixup->next = mips_hi_fixup_list;
3446 mips_hi_fixup_list = hi_fixup;
3448 hi_fixup->fixp = ip->fixp[0];
3449 hi_fixup->seg = now_seg;
3452 /* Add fixups for the second and third relocations, if given.
3453 Note that the ABI allows the second relocation to be
3454 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3455 moment we only use RSS_UNDEF, but we could add support
3456 for the others if it ever becomes necessary. */
3457 for (i = 1; i < 3; i++)
3458 if (reloc_type[i] != BFD_RELOC_UNUSED)
3460 ip->fixp[i] = fix_new (ip->frag, ip->where,
3461 ip->fixp[0]->fx_size, NULL, 0,
3462 FALSE, reloc_type[i]);
3464 /* Use fx_tcbit to mark compound relocs. */
3465 ip->fixp[0]->fx_tcbit = 1;
3466 ip->fixp[i]->fx_tcbit = 1;
3472 /* Update the register mask information. */
3473 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3474 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3476 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3478 /* Filling the branch delay slot is more complex. We try to
3479 switch the branch with the previous instruction, which we can
3480 do if the previous instruction does not set up a condition
3481 that the branch tests and if the branch is not itself the
3482 target of any branch. */
3483 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3484 || (pinfo & INSN_COND_BRANCH_DELAY))
3486 if (mips_optimize < 2
3487 /* If we have seen .set volatile or .set nomove, don't
3489 || mips_opts.nomove != 0
3490 /* We can't swap if the previous instruction's position
3492 || history[0].fixed_p
3493 /* If the previous previous insn was in a .set
3494 noreorder, we can't swap. Actually, the MIPS
3495 assembler will swap in this situation. However, gcc
3496 configured -with-gnu-as will generate code like
3502 in which we can not swap the bne and INSN. If gcc is
3503 not configured -with-gnu-as, it does not output the
3505 || history[1].noreorder_p
3506 /* If the branch is itself the target of a branch, we
3507 can not swap. We cheat on this; all we check for is
3508 whether there is a label on this instruction. If
3509 there are any branches to anything other than a
3510 label, users must use .set noreorder. */
3511 || si->label_list != NULL
3512 /* If the previous instruction is in a variant frag
3513 other than this branch's one, we cannot do the swap.
3514 This does not apply to the mips16, which uses variant
3515 frags for different purposes. */
3516 || (! mips_opts.mips16
3517 && prev_insn_frag_type == rs_machine_dependent)
3518 /* Check for conflicts between the branch and the instructions
3519 before the candidate delay slot. */
3520 || nops_for_insn (0, history + 1, ip) > 0
3521 /* Check for conflicts between the swapped sequence and the
3522 target of the branch. */
3523 || nops_for_sequence (2, 0, history + 1, ip, history) > 0
3524 /* We do not swap with a trap instruction, since it
3525 complicates trap handlers to have the trap
3526 instruction be in a delay slot. */
3527 || (prev_pinfo & INSN_TRAP)
3528 /* If the branch reads a register that the previous
3529 instruction sets, we can not swap. */
3530 || (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0
3531 /* If the branch writes a register that the previous
3532 instruction sets, we can not swap. */
3533 || (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0
3534 /* If the branch writes a register that the previous
3535 instruction reads, we can not swap. */
3536 || (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0
3537 /* If one instruction sets a condition code and the
3538 other one uses a condition code, we can not swap. */
3539 || ((pinfo & INSN_READ_COND_CODE)
3540 && (prev_pinfo & INSN_WRITE_COND_CODE))
3541 || ((pinfo & INSN_WRITE_COND_CODE)
3542 && (prev_pinfo & INSN_READ_COND_CODE))
3543 /* If the previous instruction uses the PC, we can not
3545 || (mips_opts.mips16
3546 && (prev_pinfo & MIPS16_INSN_READ_PC))
3547 /* If the previous instruction had a fixup in mips16
3548 mode, we can not swap. This normally means that the
3549 previous instruction was a 4 byte branch anyhow. */
3550 || (mips_opts.mips16 && history[0].fixp[0])
3551 /* If the previous instruction is a sync, sync.l, or
3552 sync.p, we can not swap. */
3553 || (prev_pinfo & INSN_SYNC)
3554 /* If the previous instruction is an ERET or
3555 DERET, avoid the swap. */
3556 || (history[0].insn_opcode == INSN_ERET)
3557 || (history[0].insn_opcode == INSN_DERET))
3559 if (mips_opts.mips16
3560 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3561 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3562 && ISA_SUPPORTS_MIPS16E)
3564 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3565 ip->insn_opcode |= 0x0080;
3566 find_altered_mips16_opcode (ip);
3568 insert_into_history (0, 1, ip);
3572 /* We could do even better for unconditional branches to
3573 portions of this object file; we could pick up the
3574 instruction at the destination, put it in the delay
3575 slot, and bump the destination address. */
3576 insert_into_history (0, 1, ip);
3580 if (mips_relax.sequence)
3581 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3585 /* It looks like we can actually do the swap. */
3586 struct mips_cl_insn delay = history[0];
3587 if (mips_opts.mips16)
3589 know (delay.frag == ip->frag);
3590 move_insn (ip, delay.frag, delay.where);
3591 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3593 else if (relaxed_branch)
3595 /* Add the delay slot instruction to the end of the
3596 current frag and shrink the fixed part of the
3597 original frag. If the branch occupies the tail of
3598 the latter, move it backwards to cover the gap. */
3599 delay.frag->fr_fix -= 4;
3600 if (delay.frag == ip->frag)
3601 move_insn (ip, ip->frag, ip->where - 4);
3602 add_fixed_insn (&delay);
3606 move_insn (&delay, ip->frag, ip->where);
3607 move_insn (ip, history[0].frag, history[0].where);
3611 insert_into_history (0, 1, &delay);
3614 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3616 /* We don't yet optimize a branch likely. What we should do
3617 is look at the target, copy the instruction found there
3618 into the delay slot, and increment the branch to jump to
3619 the next instruction. */
3620 insert_into_history (0, 1, ip);
3624 insert_into_history (0, 1, ip);
3627 insert_into_history (0, 1, ip);
3629 /* If we have just completed an unconditional branch, clear the history. */
3630 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
3631 || (mips_opts.mips16
3632 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
3633 mips_no_prev_insn ();
3635 /* We just output an insn, so the next one doesn't have a label. */
3636 mips_clear_insn_labels ();
3639 /* Forget that there was any previous instruction or label. */
3642 mips_no_prev_insn (void)
3644 prev_nop_frag = NULL;
3645 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3646 mips_clear_insn_labels ();
3649 /* This function must be called before we emit something other than
3650 instructions. It is like mips_no_prev_insn except that it inserts
3651 any NOPS that might be needed by previous instructions. */
3654 mips_emit_delays (void)
3656 if (! mips_opts.noreorder)
3658 int nops = nops_for_insn (0, history, NULL);
3662 add_fixed_insn (NOP_INSN);
3663 mips_move_labels ();
3666 mips_no_prev_insn ();
3669 /* Start a (possibly nested) noreorder block. */
3672 start_noreorder (void)
3674 if (mips_opts.noreorder == 0)
3679 /* None of the instructions before the .set noreorder can be moved. */
3680 for (i = 0; i < ARRAY_SIZE (history); i++)
3681 history[i].fixed_p = 1;
3683 /* Insert any nops that might be needed between the .set noreorder
3684 block and the previous instructions. We will later remove any
3685 nops that turn out not to be needed. */
3686 nops = nops_for_insn (0, history, NULL);
3689 if (mips_optimize != 0)
3691 /* Record the frag which holds the nop instructions, so
3692 that we can remove them if we don't need them. */
3693 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3694 prev_nop_frag = frag_now;
3695 prev_nop_frag_holds = nops;
3696 prev_nop_frag_required = 0;
3697 prev_nop_frag_since = 0;
3700 for (; nops > 0; --nops)
3701 add_fixed_insn (NOP_INSN);
3703 /* Move on to a new frag, so that it is safe to simply
3704 decrease the size of prev_nop_frag. */
3705 frag_wane (frag_now);
3707 mips_move_labels ();
3709 mips16_mark_labels ();
3710 mips_clear_insn_labels ();
3712 mips_opts.noreorder++;
3713 mips_any_noreorder = 1;
3716 /* End a nested noreorder block. */
3719 end_noreorder (void)
3722 mips_opts.noreorder--;
3723 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3725 /* Commit to inserting prev_nop_frag_required nops and go back to
3726 handling nop insertion the .set reorder way. */
3727 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3728 * (mips_opts.mips16 ? 2 : 4));
3729 insert_into_history (prev_nop_frag_since,
3730 prev_nop_frag_required, NOP_INSN);
3731 prev_nop_frag = NULL;
3735 /* Set up global variables for the start of a new macro. */
3740 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3741 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3742 && (history[0].insn_mo->pinfo
3743 & (INSN_UNCOND_BRANCH_DELAY
3744 | INSN_COND_BRANCH_DELAY
3745 | INSN_COND_BRANCH_LIKELY)) != 0);
3748 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3749 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3750 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3753 macro_warning (relax_substateT subtype)
3755 if (subtype & RELAX_DELAY_SLOT)
3756 return _("Macro instruction expanded into multiple instructions"
3757 " in a branch delay slot");
3758 else if (subtype & RELAX_NOMACRO)
3759 return _("Macro instruction expanded into multiple instructions");
3764 /* Finish up a macro. Emit warnings as appropriate. */
3769 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3771 relax_substateT subtype;
3773 /* Set up the relaxation warning flags. */
3775 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3776 subtype |= RELAX_SECOND_LONGER;
3777 if (mips_opts.warn_about_macros)
3778 subtype |= RELAX_NOMACRO;
3779 if (mips_macro_warning.delay_slot_p)
3780 subtype |= RELAX_DELAY_SLOT;
3782 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3784 /* Either the macro has a single implementation or both
3785 implementations are longer than 4 bytes. Emit the
3787 const char *msg = macro_warning (subtype);
3789 as_warn ("%s", msg);
3793 /* One implementation might need a warning but the other
3794 definitely doesn't. */
3795 mips_macro_warning.first_frag->fr_subtype |= subtype;
3800 /* Read a macro's relocation codes from *ARGS and store them in *R.
3801 The first argument in *ARGS will be either the code for a single
3802 relocation or -1 followed by the three codes that make up a
3803 composite relocation. */
3806 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3810 next = va_arg (*args, int);
3812 r[0] = (bfd_reloc_code_real_type) next;
3814 for (i = 0; i < 3; i++)
3815 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3818 /* Build an instruction created by a macro expansion. This is passed
3819 a pointer to the count of instructions created so far, an
3820 expression, the name of the instruction to build, an operand format
3821 string, and corresponding arguments. */
3824 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3826 const struct mips_opcode *mo;
3827 struct mips_cl_insn insn;
3828 bfd_reloc_code_real_type r[3];
3831 va_start (args, fmt);
3833 if (mips_opts.mips16)
3835 mips16_macro_build (ep, name, fmt, &args);
3840 r[0] = BFD_RELOC_UNUSED;
3841 r[1] = BFD_RELOC_UNUSED;
3842 r[2] = BFD_RELOC_UNUSED;
3843 mo = (struct mips_opcode *) hash_find (op_hash, name);
3845 gas_assert (strcmp (name, mo->name) == 0);
3849 /* Search until we get a match for NAME. It is assumed here that
3850 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3851 if (strcmp (fmt, mo->args) == 0
3852 && mo->pinfo != INSN_MACRO
3853 && is_opcode_valid (mo))
3857 gas_assert (mo->name);
3858 gas_assert (strcmp (name, mo->name) == 0);
3861 create_insn (&insn, mo);
3879 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3884 /* Note that in the macro case, these arguments are already
3885 in MSB form. (When handling the instruction in the
3886 non-macro case, these arguments are sizes from which
3887 MSB values must be calculated.) */
3888 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3894 /* Note that in the macro case, these arguments are already
3895 in MSBD form. (When handling the instruction in the
3896 non-macro case, these arguments are sizes from which
3897 MSBD values must be calculated.) */
3898 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3902 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3911 INSERT_OPERAND (BP, insn, va_arg (args, int));
3917 INSERT_OPERAND (RT, insn, va_arg (args, int));
3921 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3926 INSERT_OPERAND (FT, insn, va_arg (args, int));
3932 INSERT_OPERAND (RD, insn, va_arg (args, int));
3937 int tmp = va_arg (args, int);
3939 INSERT_OPERAND (RT, insn, tmp);
3940 INSERT_OPERAND (RD, insn, tmp);
3946 INSERT_OPERAND (FS, insn, va_arg (args, int));
3953 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3957 INSERT_OPERAND (FD, insn, va_arg (args, int));
3961 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3965 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3969 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3976 INSERT_OPERAND (RS, insn, va_arg (args, int));
3981 macro_read_relocs (&args, r);
3982 gas_assert (*r == BFD_RELOC_GPREL16
3983 || *r == BFD_RELOC_MIPS_HIGHER
3984 || *r == BFD_RELOC_HI16_S
3985 || *r == BFD_RELOC_LO16
3986 || *r == BFD_RELOC_MIPS_GOT_OFST);
3990 macro_read_relocs (&args, r);
3994 macro_read_relocs (&args, r);
3995 gas_assert (ep != NULL
3996 && (ep->X_op == O_constant
3997 || (ep->X_op == O_symbol
3998 && (*r == BFD_RELOC_MIPS_HIGHEST
3999 || *r == BFD_RELOC_HI16_S
4000 || *r == BFD_RELOC_HI16
4001 || *r == BFD_RELOC_GPREL16
4002 || *r == BFD_RELOC_MIPS_GOT_HI16
4003 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4007 gas_assert (ep != NULL);
4010 * This allows macro() to pass an immediate expression for
4011 * creating short branches without creating a symbol.
4013 * We don't allow branch relaxation for these branches, as
4014 * they should only appear in ".set nomacro" anyway.
4016 if (ep->X_op == O_constant)
4018 if ((ep->X_add_number & 3) != 0)
4019 as_bad (_("branch to misaligned address (0x%lx)"),
4020 (unsigned long) ep->X_add_number);
4021 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4022 as_bad (_("branch address range overflow (0x%lx)"),
4023 (unsigned long) ep->X_add_number);
4024 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4028 *r = BFD_RELOC_16_PCREL_S2;
4032 gas_assert (ep != NULL);
4033 *r = BFD_RELOC_MIPS_JMP;
4037 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4041 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4050 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4052 append_insn (&insn, ep, r);
4056 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4059 struct mips_opcode *mo;
4060 struct mips_cl_insn insn;
4061 bfd_reloc_code_real_type r[3]
4062 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4064 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4066 gas_assert (strcmp (name, mo->name) == 0);
4068 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4071 gas_assert (mo->name);
4072 gas_assert (strcmp (name, mo->name) == 0);
4075 create_insn (&insn, mo);
4093 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4098 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4102 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4106 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4116 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4123 regno = va_arg (*args, int);
4124 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4125 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4146 gas_assert (ep != NULL);
4148 if (ep->X_op != O_constant)
4149 *r = (int) BFD_RELOC_UNUSED + c;
4152 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4153 FALSE, &insn.insn_opcode, &insn.use_extend,
4156 *r = BFD_RELOC_UNUSED;
4162 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4169 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4171 append_insn (&insn, ep, r);
4175 * Sign-extend 32-bit mode constants that have bit 31 set and all
4176 * higher bits unset.
4179 normalize_constant_expr (expressionS *ex)
4181 if (ex->X_op == O_constant
4182 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4183 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4188 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4189 * all higher bits unset.
4192 normalize_address_expr (expressionS *ex)
4194 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4195 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4196 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4197 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4202 * Generate a "jalr" instruction with a relocation hint to the called
4203 * function. This occurs in NewABI PIC code.
4206 macro_build_jalr (expressionS *ep)
4210 if (MIPS_JALR_HINT_P (ep))
4215 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4216 if (MIPS_JALR_HINT_P (ep))
4217 fix_new_exp (frag_now, f - frag_now->fr_literal,
4218 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4222 * Generate a "lui" instruction.
4225 macro_build_lui (expressionS *ep, int regnum)
4227 expressionS high_expr;
4228 const struct mips_opcode *mo;
4229 struct mips_cl_insn insn;
4230 bfd_reloc_code_real_type r[3]
4231 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4232 const char *name = "lui";
4233 const char *fmt = "t,u";
4235 gas_assert (! mips_opts.mips16);
4239 if (high_expr.X_op == O_constant)
4241 /* We can compute the instruction now without a relocation entry. */
4242 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4244 *r = BFD_RELOC_UNUSED;
4248 gas_assert (ep->X_op == O_symbol);
4249 /* _gp_disp is a special case, used from s_cpload.
4250 __gnu_local_gp is used if mips_no_shared. */
4251 gas_assert (mips_pic == NO_PIC
4253 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4254 || (! mips_in_shared
4255 && strcmp (S_GET_NAME (ep->X_add_symbol),
4256 "__gnu_local_gp") == 0));
4257 *r = BFD_RELOC_HI16_S;
4260 mo = hash_find (op_hash, name);
4261 gas_assert (strcmp (name, mo->name) == 0);
4262 gas_assert (strcmp (fmt, mo->args) == 0);
4263 create_insn (&insn, mo);
4265 insn.insn_opcode = insn.insn_mo->match;
4266 INSERT_OPERAND (RT, insn, regnum);
4267 if (*r == BFD_RELOC_UNUSED)
4269 insn.insn_opcode |= high_expr.X_add_number;
4270 append_insn (&insn, NULL, r);
4273 append_insn (&insn, &high_expr, r);
4276 /* Generate a sequence of instructions to do a load or store from a constant
4277 offset off of a base register (breg) into/from a target register (treg),
4278 using AT if necessary. */
4280 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4281 int treg, int breg, int dbl)
4283 gas_assert (ep->X_op == O_constant);
4285 /* Sign-extending 32-bit constants makes their handling easier. */
4287 normalize_constant_expr (ep);
4289 /* Right now, this routine can only handle signed 32-bit constants. */
4290 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4291 as_warn (_("operand overflow"));
4293 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4295 /* Signed 16-bit offset will fit in the op. Easy! */
4296 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4300 /* 32-bit offset, need multiple instructions and AT, like:
4301 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4302 addu $tempreg,$tempreg,$breg
4303 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4304 to handle the complete offset. */
4305 macro_build_lui (ep, AT);
4306 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4307 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4310 as_bad (_("Macro used $at after \".set noat\""));
4315 * Generates code to set the $at register to true (one)
4316 * if reg is less than the immediate expression.
4319 set_at (int reg, int unsignedp)
4321 if (imm_expr.X_op == O_constant
4322 && imm_expr.X_add_number >= -0x8000
4323 && imm_expr.X_add_number < 0x8000)
4324 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4325 AT, reg, BFD_RELOC_LO16);
4328 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4329 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4333 /* Warn if an expression is not a constant. */
4336 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4338 if (ex->X_op == O_big)
4339 as_bad (_("unsupported large constant"));
4340 else if (ex->X_op != O_constant)
4341 as_bad (_("Instruction %s requires absolute expression"),
4344 if (HAVE_32BIT_GPRS)
4345 normalize_constant_expr (ex);
4348 /* Count the leading zeroes by performing a binary chop. This is a
4349 bulky bit of source, but performance is a LOT better for the
4350 majority of values than a simple loop to count the bits:
4351 for (lcnt = 0; (lcnt < 32); lcnt++)
4352 if ((v) & (1 << (31 - lcnt)))
4354 However it is not code size friendly, and the gain will drop a bit
4355 on certain cached systems.
4357 #define COUNT_TOP_ZEROES(v) \
4358 (((v) & ~0xffff) == 0 \
4359 ? ((v) & ~0xff) == 0 \
4360 ? ((v) & ~0xf) == 0 \
4361 ? ((v) & ~0x3) == 0 \
4362 ? ((v) & ~0x1) == 0 \
4367 : ((v) & ~0x7) == 0 \
4370 : ((v) & ~0x3f) == 0 \
4371 ? ((v) & ~0x1f) == 0 \
4374 : ((v) & ~0x7f) == 0 \
4377 : ((v) & ~0xfff) == 0 \
4378 ? ((v) & ~0x3ff) == 0 \
4379 ? ((v) & ~0x1ff) == 0 \
4382 : ((v) & ~0x7ff) == 0 \
4385 : ((v) & ~0x3fff) == 0 \
4386 ? ((v) & ~0x1fff) == 0 \
4389 : ((v) & ~0x7fff) == 0 \
4392 : ((v) & ~0xffffff) == 0 \
4393 ? ((v) & ~0xfffff) == 0 \
4394 ? ((v) & ~0x3ffff) == 0 \
4395 ? ((v) & ~0x1ffff) == 0 \
4398 : ((v) & ~0x7ffff) == 0 \
4401 : ((v) & ~0x3fffff) == 0 \
4402 ? ((v) & ~0x1fffff) == 0 \
4405 : ((v) & ~0x7fffff) == 0 \
4408 : ((v) & ~0xfffffff) == 0 \
4409 ? ((v) & ~0x3ffffff) == 0 \
4410 ? ((v) & ~0x1ffffff) == 0 \
4413 : ((v) & ~0x7ffffff) == 0 \
4416 : ((v) & ~0x3fffffff) == 0 \
4417 ? ((v) & ~0x1fffffff) == 0 \
4420 : ((v) & ~0x7fffffff) == 0 \
4425 * This routine generates the least number of instructions necessary to load
4426 * an absolute expression value into a register.
4429 load_register (int reg, expressionS *ep, int dbl)
4432 expressionS hi32, lo32;
4434 if (ep->X_op != O_big)
4436 gas_assert (ep->X_op == O_constant);
4438 /* Sign-extending 32-bit constants makes their handling easier. */
4440 normalize_constant_expr (ep);
4442 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4444 /* We can handle 16 bit signed values with an addiu to
4445 $zero. No need to ever use daddiu here, since $zero and
4446 the result are always correct in 32 bit mode. */
4447 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4450 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4452 /* We can handle 16 bit unsigned values with an ori to
4454 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4457 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4459 /* 32 bit values require an lui. */
4460 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4461 if ((ep->X_add_number & 0xffff) != 0)
4462 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4467 /* The value is larger than 32 bits. */
4469 if (!dbl || HAVE_32BIT_GPRS)
4473 sprintf_vma (value, ep->X_add_number);
4474 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4475 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4479 if (ep->X_op != O_big)
4482 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4483 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4484 hi32.X_add_number &= 0xffffffff;
4486 lo32.X_add_number &= 0xffffffff;
4490 gas_assert (ep->X_add_number > 2);
4491 if (ep->X_add_number == 3)
4492 generic_bignum[3] = 0;
4493 else if (ep->X_add_number > 4)
4494 as_bad (_("Number larger than 64 bits"));
4495 lo32.X_op = O_constant;
4496 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4497 hi32.X_op = O_constant;
4498 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4501 if (hi32.X_add_number == 0)
4506 unsigned long hi, lo;
4508 if (hi32.X_add_number == (offsetT) 0xffffffff)
4510 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4512 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4515 if (lo32.X_add_number & 0x80000000)
4517 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4518 if (lo32.X_add_number & 0xffff)
4519 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4524 /* Check for 16bit shifted constant. We know that hi32 is
4525 non-zero, so start the mask on the first bit of the hi32
4530 unsigned long himask, lomask;
4534 himask = 0xffff >> (32 - shift);
4535 lomask = (0xffff << shift) & 0xffffffff;
4539 himask = 0xffff << (shift - 32);
4542 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4543 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4547 tmp.X_op = O_constant;
4549 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4550 | (lo32.X_add_number >> shift));
4552 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4553 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4554 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4555 reg, reg, (shift >= 32) ? shift - 32 : shift);
4560 while (shift <= (64 - 16));
4562 /* Find the bit number of the lowest one bit, and store the
4563 shifted value in hi/lo. */
4564 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4565 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4569 while ((lo & 1) == 0)
4574 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4580 while ((hi & 1) == 0)
4589 /* Optimize if the shifted value is a (power of 2) - 1. */
4590 if ((hi == 0 && ((lo + 1) & lo) == 0)
4591 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4593 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4598 /* This instruction will set the register to be all
4600 tmp.X_op = O_constant;
4601 tmp.X_add_number = (offsetT) -1;
4602 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4606 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4607 reg, reg, (bit >= 32) ? bit - 32 : bit);
4609 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4610 reg, reg, (shift >= 32) ? shift - 32 : shift);
4615 /* Sign extend hi32 before calling load_register, because we can
4616 generally get better code when we load a sign extended value. */
4617 if ((hi32.X_add_number & 0x80000000) != 0)
4618 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4619 load_register (reg, &hi32, 0);
4622 if ((lo32.X_add_number & 0xffff0000) == 0)
4626 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4634 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4636 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4637 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4643 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4647 mid16.X_add_number >>= 16;
4648 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4649 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4652 if ((lo32.X_add_number & 0xffff) != 0)
4653 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4657 load_delay_nop (void)
4659 if (!gpr_interlocks)
4660 macro_build (NULL, "nop", "");
4663 /* Load an address into a register. */
4666 load_address (int reg, expressionS *ep, int *used_at)
4668 if (ep->X_op != O_constant
4669 && ep->X_op != O_symbol)
4671 as_bad (_("expression too complex"));
4672 ep->X_op = O_constant;
4675 if (ep->X_op == O_constant)
4677 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4681 if (mips_pic == NO_PIC)
4683 /* If this is a reference to a GP relative symbol, we want
4684 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4686 lui $reg,<sym> (BFD_RELOC_HI16_S)
4687 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4688 If we have an addend, we always use the latter form.
4690 With 64bit address space and a usable $at we want
4691 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4692 lui $at,<sym> (BFD_RELOC_HI16_S)
4693 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4694 daddiu $at,<sym> (BFD_RELOC_LO16)
4698 If $at is already in use, we use a path which is suboptimal
4699 on superscalar processors.
4700 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4701 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4703 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4705 daddiu $reg,<sym> (BFD_RELOC_LO16)
4707 For GP relative symbols in 64bit address space we can use
4708 the same sequence as in 32bit address space. */
4709 if (HAVE_64BIT_SYMBOLS)
4711 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4712 && !nopic_need_relax (ep->X_add_symbol, 1))
4714 relax_start (ep->X_add_symbol);
4715 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4716 mips_gp_register, BFD_RELOC_GPREL16);
4720 if (*used_at == 0 && mips_opts.at)
4722 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4723 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4724 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4725 BFD_RELOC_MIPS_HIGHER);
4726 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4727 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4728 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4733 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4734 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4735 BFD_RELOC_MIPS_HIGHER);
4736 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4737 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4738 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4739 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4742 if (mips_relax.sequence)
4747 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4748 && !nopic_need_relax (ep->X_add_symbol, 1))
4750 relax_start (ep->X_add_symbol);
4751 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4752 mips_gp_register, BFD_RELOC_GPREL16);
4755 macro_build_lui (ep, reg);
4756 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4757 reg, reg, BFD_RELOC_LO16);
4758 if (mips_relax.sequence)
4762 else if (!mips_big_got)
4766 /* If this is a reference to an external symbol, we want
4767 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4769 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4771 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4772 If there is a constant, it must be added in after.
4774 If we have NewABI, we want
4775 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4776 unless we're referencing a global symbol with a non-zero
4777 offset, in which case cst must be added separately. */
4780 if (ep->X_add_number)
4782 ex.X_add_number = ep->X_add_number;
4783 ep->X_add_number = 0;
4784 relax_start (ep->X_add_symbol);
4785 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4786 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4787 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4788 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4789 ex.X_op = O_constant;
4790 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4791 reg, reg, BFD_RELOC_LO16);
4792 ep->X_add_number = ex.X_add_number;
4795 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4796 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4797 if (mips_relax.sequence)
4802 ex.X_add_number = ep->X_add_number;
4803 ep->X_add_number = 0;
4804 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4805 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4807 relax_start (ep->X_add_symbol);
4809 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4813 if (ex.X_add_number != 0)
4815 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4816 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4817 ex.X_op = O_constant;
4818 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4819 reg, reg, BFD_RELOC_LO16);
4823 else if (mips_big_got)
4827 /* This is the large GOT case. If this is a reference to an
4828 external symbol, we want
4829 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4831 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4833 Otherwise, for a reference to a local symbol in old ABI, we want
4834 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4836 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4837 If there is a constant, it must be added in after.
4839 In the NewABI, for local symbols, with or without offsets, we want:
4840 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4841 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4845 ex.X_add_number = ep->X_add_number;
4846 ep->X_add_number = 0;
4847 relax_start (ep->X_add_symbol);
4848 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4849 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4850 reg, reg, mips_gp_register);
4851 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4852 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4853 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4854 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4855 else if (ex.X_add_number)
4857 ex.X_op = O_constant;
4858 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4862 ep->X_add_number = ex.X_add_number;
4864 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4865 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4866 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4867 BFD_RELOC_MIPS_GOT_OFST);
4872 ex.X_add_number = ep->X_add_number;
4873 ep->X_add_number = 0;
4874 relax_start (ep->X_add_symbol);
4875 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4876 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4877 reg, reg, mips_gp_register);
4878 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4879 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4881 if (reg_needs_delay (mips_gp_register))
4883 /* We need a nop before loading from $gp. This special
4884 check is required because the lui which starts the main
4885 instruction stream does not refer to $gp, and so will not
4886 insert the nop which may be required. */
4887 macro_build (NULL, "nop", "");
4889 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4890 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4892 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4896 if (ex.X_add_number != 0)
4898 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4899 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4900 ex.X_op = O_constant;
4901 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4909 if (!mips_opts.at && *used_at == 1)
4910 as_bad (_("Macro used $at after \".set noat\""));
4913 /* Move the contents of register SOURCE into register DEST. */
4916 move_register (int dest, int source)
4918 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4922 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4923 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4924 The two alternatives are:
4926 Global symbol Local sybmol
4927 ------------- ------------
4928 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4930 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4932 load_got_offset emits the first instruction and add_got_offset
4933 emits the second for a 16-bit offset or add_got_offset_hilo emits
4934 a sequence to add a 32-bit offset using a scratch register. */
4937 load_got_offset (int dest, expressionS *local)
4942 global.X_add_number = 0;
4944 relax_start (local->X_add_symbol);
4945 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4946 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4948 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4949 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4954 add_got_offset (int dest, expressionS *local)
4958 global.X_op = O_constant;
4959 global.X_op_symbol = NULL;
4960 global.X_add_symbol = NULL;
4961 global.X_add_number = local->X_add_number;
4963 relax_start (local->X_add_symbol);
4964 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4965 dest, dest, BFD_RELOC_LO16);
4967 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4972 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4975 int hold_mips_optimize;
4977 global.X_op = O_constant;
4978 global.X_op_symbol = NULL;
4979 global.X_add_symbol = NULL;
4980 global.X_add_number = local->X_add_number;
4982 relax_start (local->X_add_symbol);
4983 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4985 /* Set mips_optimize around the lui instruction to avoid
4986 inserting an unnecessary nop after the lw. */
4987 hold_mips_optimize = mips_optimize;
4989 macro_build_lui (&global, tmp);
4990 mips_optimize = hold_mips_optimize;
4991 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4994 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4999 * This routine implements the seemingly endless macro or synthesized
5000 * instructions and addressing modes in the mips assembly language. Many
5001 * of these macros are simple and are similar to each other. These could
5002 * probably be handled by some kind of table or grammar approach instead of
5003 * this verbose method. Others are not simple macros but are more like
5004 * optimizing code generation.
5005 * One interesting optimization is when several store macros appear
5006 * consecutively that would load AT with the upper half of the same address.
5007 * The ensuing load upper instructions are ommited. This implies some kind
5008 * of global optimization. We currently only optimize within a single macro.
5009 * For many of the load and store macros if the address is specified as a
5010 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5011 * first load register 'at' with zero and use it as the base register. The
5012 * mips assembler simply uses register $zero. Just one tiny optimization
5016 macro (struct mips_cl_insn *ip)
5018 unsigned int treg, sreg, dreg, breg;
5019 unsigned int tempreg;
5034 bfd_reloc_code_real_type r;
5035 int hold_mips_optimize;
5037 gas_assert (! mips_opts.mips16);
5039 treg = EXTRACT_OPERAND (RT, *ip);
5040 dreg = EXTRACT_OPERAND (RD, *ip);
5041 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5042 mask = ip->insn_mo->mask;
5044 expr1.X_op = O_constant;
5045 expr1.X_op_symbol = NULL;
5046 expr1.X_add_symbol = NULL;
5047 expr1.X_add_number = 1;
5061 expr1.X_add_number = 8;
5062 macro_build (&expr1, "bgez", "s,p", sreg);
5064 macro_build (NULL, "nop", "");
5066 move_register (dreg, sreg);
5067 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5090 if (imm_expr.X_op == O_constant
5091 && imm_expr.X_add_number >= -0x8000
5092 && imm_expr.X_add_number < 0x8000)
5094 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5098 load_register (AT, &imm_expr, dbl);
5099 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5118 if (imm_expr.X_op == O_constant
5119 && imm_expr.X_add_number >= 0
5120 && imm_expr.X_add_number < 0x10000)
5122 if (mask != M_NOR_I)
5123 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5126 macro_build (&imm_expr, "ori", "t,r,i",
5127 treg, sreg, BFD_RELOC_LO16);
5128 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5134 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5135 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5139 switch (imm_expr.X_add_number)
5142 macro_build (NULL, "nop", "");
5145 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5148 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5149 (int) imm_expr.X_add_number);
5168 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5170 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5174 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5175 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5183 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5188 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5192 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5193 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5199 /* Check for > max integer. */
5200 maxnum = 0x7fffffff;
5201 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5208 if (imm_expr.X_op == O_constant
5209 && imm_expr.X_add_number >= maxnum
5210 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5213 /* Result is always false. */
5215 macro_build (NULL, "nop", "");
5217 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5220 if (imm_expr.X_op != O_constant)
5221 as_bad (_("Unsupported large constant"));
5222 ++imm_expr.X_add_number;
5226 if (mask == M_BGEL_I)
5228 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5230 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5233 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5235 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5238 maxnum = 0x7fffffff;
5239 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5246 maxnum = - maxnum - 1;
5247 if (imm_expr.X_op == O_constant
5248 && imm_expr.X_add_number <= maxnum
5249 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5252 /* result is always true */
5253 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5254 macro_build (&offset_expr, "b", "p");
5259 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5269 macro_build (&offset_expr, likely ? "beql" : "beq",
5270 "s,t,p", ZERO, treg);
5274 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5275 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5283 && imm_expr.X_op == O_constant
5284 && imm_expr.X_add_number == -1))
5286 if (imm_expr.X_op != O_constant)
5287 as_bad (_("Unsupported large constant"));
5288 ++imm_expr.X_add_number;
5292 if (mask == M_BGEUL_I)
5294 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5296 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5298 macro_build (&offset_expr, likely ? "bnel" : "bne",
5299 "s,t,p", sreg, ZERO);
5304 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5312 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5317 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5321 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5322 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5330 macro_build (&offset_expr, likely ? "bnel" : "bne",
5331 "s,t,p", sreg, ZERO);
5337 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5338 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5346 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5351 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5355 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5356 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5362 maxnum = 0x7fffffff;
5363 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5370 if (imm_expr.X_op == O_constant
5371 && imm_expr.X_add_number >= maxnum
5372 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5374 if (imm_expr.X_op != O_constant)
5375 as_bad (_("Unsupported large constant"));
5376 ++imm_expr.X_add_number;
5380 if (mask == M_BLTL_I)
5382 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5384 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5389 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5394 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5402 macro_build (&offset_expr, likely ? "beql" : "beq",
5403 "s,t,p", sreg, ZERO);
5409 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5410 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5418 && imm_expr.X_op == O_constant
5419 && imm_expr.X_add_number == -1))
5421 if (imm_expr.X_op != O_constant)
5422 as_bad (_("Unsupported large constant"));
5423 ++imm_expr.X_add_number;
5427 if (mask == M_BLTUL_I)
5429 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5431 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5433 macro_build (&offset_expr, likely ? "beql" : "beq",
5434 "s,t,p", sreg, ZERO);
5439 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5447 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5452 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5456 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5457 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5467 macro_build (&offset_expr, likely ? "bnel" : "bne",
5468 "s,t,p", ZERO, treg);
5472 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5473 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5478 /* Use unsigned arithmetic. */
5482 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5484 as_bad (_("Unsupported large constant"));
5489 pos = imm_expr.X_add_number;
5490 size = imm2_expr.X_add_number;
5495 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5498 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5500 as_bad (_("Improper extract size (%lu, position %lu)"),
5501 (unsigned long) size, (unsigned long) pos);
5505 if (size <= 32 && pos < 32)
5510 else if (size <= 32)
5520 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5527 /* Use unsigned arithmetic. */
5531 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5533 as_bad (_("Unsupported large constant"));
5538 pos = imm_expr.X_add_number;
5539 size = imm2_expr.X_add_number;
5544 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5547 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5549 as_bad (_("Improper insert size (%lu, position %lu)"),
5550 (unsigned long) size, (unsigned long) pos);
5554 if (pos < 32 && (pos + size - 1) < 32)
5569 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5570 (int) (pos + size - 1));
5586 as_warn (_("Divide by zero."));
5588 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5590 macro_build (NULL, "break", "c", 7);
5597 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5598 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5602 expr1.X_add_number = 8;
5603 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5604 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5605 macro_build (NULL, "break", "c", 7);
5607 expr1.X_add_number = -1;
5609 load_register (AT, &expr1, dbl);
5610 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5611 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5614 expr1.X_add_number = 1;
5615 load_register (AT, &expr1, dbl);
5616 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5620 expr1.X_add_number = 0x80000000;
5621 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5625 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5626 /* We want to close the noreorder block as soon as possible, so
5627 that later insns are available for delay slot filling. */
5632 expr1.X_add_number = 8;
5633 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5634 macro_build (NULL, "nop", "");
5636 /* We want to close the noreorder block as soon as possible, so
5637 that later insns are available for delay slot filling. */
5640 macro_build (NULL, "break", "c", 6);
5642 macro_build (NULL, s, "d", dreg);
5681 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5683 as_warn (_("Divide by zero."));
5685 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5687 macro_build (NULL, "break", "c", 7);
5690 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5692 if (strcmp (s2, "mflo") == 0)
5693 move_register (dreg, sreg);
5695 move_register (dreg, ZERO);
5698 if (imm_expr.X_op == O_constant
5699 && imm_expr.X_add_number == -1
5700 && s[strlen (s) - 1] != 'u')
5702 if (strcmp (s2, "mflo") == 0)
5704 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5707 move_register (dreg, ZERO);
5712 load_register (AT, &imm_expr, dbl);
5713 macro_build (NULL, s, "z,s,t", sreg, AT);
5714 macro_build (NULL, s2, "d", dreg);
5736 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5737 macro_build (NULL, s, "z,s,t", sreg, treg);
5738 /* We want to close the noreorder block as soon as possible, so
5739 that later insns are available for delay slot filling. */
5744 expr1.X_add_number = 8;
5745 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5746 macro_build (NULL, s, "z,s,t", sreg, treg);
5748 /* We want to close the noreorder block as soon as possible, so
5749 that later insns are available for delay slot filling. */
5751 macro_build (NULL, "break", "c", 7);
5753 macro_build (NULL, s2, "d", dreg);
5765 /* Load the address of a symbol into a register. If breg is not
5766 zero, we then add a base register to it. */
5768 if (dbl && HAVE_32BIT_GPRS)
5769 as_warn (_("dla used to load 32-bit register"));
5771 if (!dbl && HAVE_64BIT_OBJECTS)
5772 as_warn (_("la used to load 64-bit address"));
5774 if (offset_expr.X_op == O_constant
5775 && offset_expr.X_add_number >= -0x8000
5776 && offset_expr.X_add_number < 0x8000)
5778 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5779 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5783 if (mips_opts.at && (treg == breg))
5793 if (offset_expr.X_op != O_symbol
5794 && offset_expr.X_op != O_constant)
5796 as_bad (_("Expression too complex"));
5797 offset_expr.X_op = O_constant;
5800 if (offset_expr.X_op == O_constant)
5801 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5802 else if (mips_pic == NO_PIC)
5804 /* If this is a reference to a GP relative symbol, we want
5805 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5807 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5808 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5809 If we have a constant, we need two instructions anyhow,
5810 so we may as well always use the latter form.
5812 With 64bit address space and a usable $at we want
5813 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5814 lui $at,<sym> (BFD_RELOC_HI16_S)
5815 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5816 daddiu $at,<sym> (BFD_RELOC_LO16)
5818 daddu $tempreg,$tempreg,$at
5820 If $at is already in use, we use a path which is suboptimal
5821 on superscalar processors.
5822 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5823 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5825 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5827 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5829 For GP relative symbols in 64bit address space we can use
5830 the same sequence as in 32bit address space. */
5831 if (HAVE_64BIT_SYMBOLS)
5833 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5834 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5836 relax_start (offset_expr.X_add_symbol);
5837 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5838 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5842 if (used_at == 0 && mips_opts.at)
5844 macro_build (&offset_expr, "lui", "t,u",
5845 tempreg, BFD_RELOC_MIPS_HIGHEST);
5846 macro_build (&offset_expr, "lui", "t,u",
5847 AT, BFD_RELOC_HI16_S);
5848 macro_build (&offset_expr, "daddiu", "t,r,j",
5849 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5850 macro_build (&offset_expr, "daddiu", "t,r,j",
5851 AT, AT, BFD_RELOC_LO16);
5852 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5853 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5858 macro_build (&offset_expr, "lui", "t,u",
5859 tempreg, BFD_RELOC_MIPS_HIGHEST);
5860 macro_build (&offset_expr, "daddiu", "t,r,j",
5861 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5862 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5863 macro_build (&offset_expr, "daddiu", "t,r,j",
5864 tempreg, tempreg, BFD_RELOC_HI16_S);
5865 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5866 macro_build (&offset_expr, "daddiu", "t,r,j",
5867 tempreg, tempreg, BFD_RELOC_LO16);
5870 if (mips_relax.sequence)
5875 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5876 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5878 relax_start (offset_expr.X_add_symbol);
5879 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5880 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5883 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5884 as_bad (_("Offset too large"));
5885 macro_build_lui (&offset_expr, tempreg);
5886 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5887 tempreg, tempreg, BFD_RELOC_LO16);
5888 if (mips_relax.sequence)
5892 else if (!mips_big_got && !HAVE_NEWABI)
5894 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5896 /* If this is a reference to an external symbol, and there
5897 is no constant, we want
5898 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5899 or for lca or if tempreg is PIC_CALL_REG
5900 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5901 For a local symbol, we want
5902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5904 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5906 If we have a small constant, and this is a reference to
5907 an external symbol, we want
5908 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5910 addiu $tempreg,$tempreg,<constant>
5911 For a local symbol, we want the same instruction
5912 sequence, but we output a BFD_RELOC_LO16 reloc on the
5915 If we have a large constant, and this is a reference to
5916 an external symbol, we want
5917 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5918 lui $at,<hiconstant>
5919 addiu $at,$at,<loconstant>
5920 addu $tempreg,$tempreg,$at
5921 For a local symbol, we want the same instruction
5922 sequence, but we output a BFD_RELOC_LO16 reloc on the
5926 if (offset_expr.X_add_number == 0)
5928 if (mips_pic == SVR4_PIC
5930 && (call || tempreg == PIC_CALL_REG))
5931 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5933 relax_start (offset_expr.X_add_symbol);
5934 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5935 lw_reloc_type, mips_gp_register);
5938 /* We're going to put in an addu instruction using
5939 tempreg, so we may as well insert the nop right
5944 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5945 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5947 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5948 tempreg, tempreg, BFD_RELOC_LO16);
5950 /* FIXME: If breg == 0, and the next instruction uses
5951 $tempreg, then if this variant case is used an extra
5952 nop will be generated. */
5954 else if (offset_expr.X_add_number >= -0x8000
5955 && offset_expr.X_add_number < 0x8000)
5957 load_got_offset (tempreg, &offset_expr);
5959 add_got_offset (tempreg, &offset_expr);
5963 expr1.X_add_number = offset_expr.X_add_number;
5964 offset_expr.X_add_number =
5965 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5966 load_got_offset (tempreg, &offset_expr);
5967 offset_expr.X_add_number = expr1.X_add_number;
5968 /* If we are going to add in a base register, and the
5969 target register and the base register are the same,
5970 then we are using AT as a temporary register. Since
5971 we want to load the constant into AT, we add our
5972 current AT (from the global offset table) and the
5973 register into the register now, and pretend we were
5974 not using a base register. */
5978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5983 add_got_offset_hilo (tempreg, &offset_expr, AT);
5987 else if (!mips_big_got && HAVE_NEWABI)
5989 int add_breg_early = 0;
5991 /* If this is a reference to an external, and there is no
5992 constant, or local symbol (*), with or without a
5994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5995 or for lca or if tempreg is PIC_CALL_REG
5996 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5998 If we have a small constant, and this is a reference to
5999 an external symbol, we want
6000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6001 addiu $tempreg,$tempreg,<constant>
6003 If we have a large constant, and this is a reference to
6004 an external symbol, we want
6005 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6006 lui $at,<hiconstant>
6007 addiu $at,$at,<loconstant>
6008 addu $tempreg,$tempreg,$at
6010 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6011 local symbols, even though it introduces an additional
6014 if (offset_expr.X_add_number)
6016 expr1.X_add_number = offset_expr.X_add_number;
6017 offset_expr.X_add_number = 0;
6019 relax_start (offset_expr.X_add_symbol);
6020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6021 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6023 if (expr1.X_add_number >= -0x8000
6024 && expr1.X_add_number < 0x8000)
6026 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6027 tempreg, tempreg, BFD_RELOC_LO16);
6029 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6031 /* If we are going to add in a base register, and the
6032 target register and the base register are the same,
6033 then we are using AT as a temporary register. Since
6034 we want to load the constant into AT, we add our
6035 current AT (from the global offset table) and the
6036 register into the register now, and pretend we were
6037 not using a base register. */
6042 gas_assert (tempreg == AT);
6043 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6049 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6056 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6059 offset_expr.X_add_number = expr1.X_add_number;
6061 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6062 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6066 treg, tempreg, breg);
6072 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6074 relax_start (offset_expr.X_add_symbol);
6075 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6076 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6078 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6079 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6084 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6085 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6088 else if (mips_big_got && !HAVE_NEWABI)
6091 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6092 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6093 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6095 /* This is the large GOT case. If this is a reference to an
6096 external symbol, and there is no constant, we want
6097 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6098 addu $tempreg,$tempreg,$gp
6099 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6100 or for lca or if tempreg is PIC_CALL_REG
6101 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6102 addu $tempreg,$tempreg,$gp
6103 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6104 For a local symbol, we want
6105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6107 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6109 If we have a small constant, and this is a reference to
6110 an external symbol, we want
6111 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6112 addu $tempreg,$tempreg,$gp
6113 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6115 addiu $tempreg,$tempreg,<constant>
6116 For a local symbol, we want
6117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6119 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6121 If we have a large constant, and this is a reference to
6122 an external symbol, we want
6123 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6124 addu $tempreg,$tempreg,$gp
6125 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6126 lui $at,<hiconstant>
6127 addiu $at,$at,<loconstant>
6128 addu $tempreg,$tempreg,$at
6129 For a local symbol, we want
6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6131 lui $at,<hiconstant>
6132 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6133 addu $tempreg,$tempreg,$at
6136 expr1.X_add_number = offset_expr.X_add_number;
6137 offset_expr.X_add_number = 0;
6138 relax_start (offset_expr.X_add_symbol);
6139 gpdelay = reg_needs_delay (mips_gp_register);
6140 if (expr1.X_add_number == 0 && breg == 0
6141 && (call || tempreg == PIC_CALL_REG))
6143 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6144 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6146 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6147 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6148 tempreg, tempreg, mips_gp_register);
6149 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6150 tempreg, lw_reloc_type, tempreg);
6151 if (expr1.X_add_number == 0)
6155 /* We're going to put in an addu instruction using
6156 tempreg, so we may as well insert the nop right
6161 else if (expr1.X_add_number >= -0x8000
6162 && expr1.X_add_number < 0x8000)
6165 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6166 tempreg, tempreg, BFD_RELOC_LO16);
6170 /* If we are going to add in a base register, and the
6171 target register and the base register are the same,
6172 then we are using AT as a temporary register. Since
6173 we want to load the constant into AT, we add our
6174 current AT (from the global offset table) and the
6175 register into the register now, and pretend we were
6176 not using a base register. */
6181 gas_assert (tempreg == AT);
6183 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6188 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6193 offset_expr.X_add_number =
6194 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6199 /* This is needed because this instruction uses $gp, but
6200 the first instruction on the main stream does not. */
6201 macro_build (NULL, "nop", "");
6204 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6205 local_reloc_type, mips_gp_register);
6206 if (expr1.X_add_number >= -0x8000
6207 && expr1.X_add_number < 0x8000)
6210 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6211 tempreg, tempreg, BFD_RELOC_LO16);
6212 /* FIXME: If add_number is 0, and there was no base
6213 register, the external symbol case ended with a load,
6214 so if the symbol turns out to not be external, and
6215 the next instruction uses tempreg, an unnecessary nop
6216 will be inserted. */
6222 /* We must add in the base register now, as in the
6223 external symbol case. */
6224 gas_assert (tempreg == AT);
6226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6229 /* We set breg to 0 because we have arranged to add
6230 it in in both cases. */
6234 macro_build_lui (&expr1, AT);
6235 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6236 AT, AT, BFD_RELOC_LO16);
6237 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6238 tempreg, tempreg, AT);
6243 else if (mips_big_got && HAVE_NEWABI)
6245 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6246 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6247 int add_breg_early = 0;
6249 /* This is the large GOT case. If this is a reference to an
6250 external symbol, and there is no constant, we want
6251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6252 add $tempreg,$tempreg,$gp
6253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6254 or for lca or if tempreg is PIC_CALL_REG
6255 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6256 add $tempreg,$tempreg,$gp
6257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6259 If we have a small constant, and this is a reference to
6260 an external symbol, we want
6261 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6262 add $tempreg,$tempreg,$gp
6263 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6264 addi $tempreg,$tempreg,<constant>
6266 If we have a large constant, and this is a reference to
6267 an external symbol, we want
6268 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6269 addu $tempreg,$tempreg,$gp
6270 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6271 lui $at,<hiconstant>
6272 addi $at,$at,<loconstant>
6273 add $tempreg,$tempreg,$at
6275 If we have NewABI, and we know it's a local symbol, we want
6276 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6277 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6278 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6280 relax_start (offset_expr.X_add_symbol);
6282 expr1.X_add_number = offset_expr.X_add_number;
6283 offset_expr.X_add_number = 0;
6285 if (expr1.X_add_number == 0 && breg == 0
6286 && (call || tempreg == PIC_CALL_REG))
6288 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6289 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6291 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6293 tempreg, tempreg, mips_gp_register);
6294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6295 tempreg, lw_reloc_type, tempreg);
6297 if (expr1.X_add_number == 0)
6299 else if (expr1.X_add_number >= -0x8000
6300 && expr1.X_add_number < 0x8000)
6302 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6303 tempreg, tempreg, BFD_RELOC_LO16);
6305 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6307 /* If we are going to add in a base register, and the
6308 target register and the base register are the same,
6309 then we are using AT as a temporary register. Since
6310 we want to load the constant into AT, we add our
6311 current AT (from the global offset table) and the
6312 register into the register now, and pretend we were
6313 not using a base register. */
6318 gas_assert (tempreg == AT);
6319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6325 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6326 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6331 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6334 offset_expr.X_add_number = expr1.X_add_number;
6335 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6336 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6337 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6338 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6341 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6342 treg, tempreg, breg);
6352 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6357 unsigned long temp = (treg << 16) | (0x01);
6358 macro_build (NULL, "c2", "C", temp);
6364 unsigned long temp = (0x02);
6365 macro_build (NULL, "c2", "C", temp);
6371 unsigned long temp = (treg << 16) | (0x02);
6372 macro_build (NULL, "c2", "C", temp);
6377 macro_build (NULL, "c2", "C", 3);
6382 unsigned long temp = (treg << 16) | 0x03;
6383 macro_build (NULL, "c2", "C", temp);
6388 /* The j instruction may not be used in PIC code, since it
6389 requires an absolute address. We convert it to a b
6391 if (mips_pic == NO_PIC)
6392 macro_build (&offset_expr, "j", "a");
6394 macro_build (&offset_expr, "b", "p");
6397 /* The jal instructions must be handled as macros because when
6398 generating PIC code they expand to multi-instruction
6399 sequences. Normally they are simple instructions. */
6404 if (mips_pic == NO_PIC)
6405 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6408 if (sreg != PIC_CALL_REG)
6409 as_warn (_("MIPS PIC call to register other than $25"));
6411 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6412 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6414 if (mips_cprestore_offset < 0)
6415 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6418 if (!mips_frame_reg_valid)
6420 as_warn (_("No .frame pseudo-op used in PIC code"));
6421 /* Quiet this warning. */
6422 mips_frame_reg_valid = 1;
6424 if (!mips_cprestore_valid)
6426 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6427 /* Quiet this warning. */
6428 mips_cprestore_valid = 1;
6430 if (mips_opts.noreorder)
6431 macro_build (NULL, "nop", "");
6432 expr1.X_add_number = mips_cprestore_offset;
6433 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6436 HAVE_64BIT_ADDRESSES);
6444 if (mips_pic == NO_PIC)
6445 macro_build (&offset_expr, "jal", "a");
6446 else if (mips_pic == SVR4_PIC)
6448 /* If this is a reference to an external symbol, and we are
6449 using a small GOT, we want
6450 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6454 lw $gp,cprestore($sp)
6455 The cprestore value is set using the .cprestore
6456 pseudo-op. If we are using a big GOT, we want
6457 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6459 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6463 lw $gp,cprestore($sp)
6464 If the symbol is not external, we want
6465 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6467 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6470 lw $gp,cprestore($sp)
6472 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6473 sequences above, minus nops, unless the symbol is local,
6474 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6480 relax_start (offset_expr.X_add_symbol);
6481 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6482 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6485 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6486 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6492 relax_start (offset_expr.X_add_symbol);
6493 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6494 BFD_RELOC_MIPS_CALL_HI16);
6495 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6496 PIC_CALL_REG, mips_gp_register);
6497 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6498 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6501 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6502 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6504 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6505 PIC_CALL_REG, PIC_CALL_REG,
6506 BFD_RELOC_MIPS_GOT_OFST);
6510 macro_build_jalr (&offset_expr);
6514 relax_start (offset_expr.X_add_symbol);
6517 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6518 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6527 gpdelay = reg_needs_delay (mips_gp_register);
6528 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6529 BFD_RELOC_MIPS_CALL_HI16);
6530 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6531 PIC_CALL_REG, mips_gp_register);
6532 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6533 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6538 macro_build (NULL, "nop", "");
6540 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6541 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6544 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6545 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6547 macro_build_jalr (&offset_expr);
6549 if (mips_cprestore_offset < 0)
6550 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6553 if (!mips_frame_reg_valid)
6555 as_warn (_("No .frame pseudo-op used in PIC code"));
6556 /* Quiet this warning. */
6557 mips_frame_reg_valid = 1;
6559 if (!mips_cprestore_valid)
6561 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6562 /* Quiet this warning. */
6563 mips_cprestore_valid = 1;
6565 if (mips_opts.noreorder)
6566 macro_build (NULL, "nop", "");
6567 expr1.X_add_number = mips_cprestore_offset;
6568 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6571 HAVE_64BIT_ADDRESSES);
6575 else if (mips_pic == VXWORKS_PIC)
6576 as_bad (_("Non-PIC jump used in PIC library"));
6599 /* Itbl support may require additional care here. */
6604 /* Itbl support may require additional care here. */
6609 /* Itbl support may require additional care here. */
6614 /* Itbl support may require additional care here. */
6627 /* Itbl support may require additional care here. */
6632 /* Itbl support may require additional care here. */
6637 /* Itbl support may require additional care here. */
6657 if (breg == treg || coproc || lr)
6678 /* Itbl support may require additional care here. */
6683 /* Itbl support may require additional care here. */
6688 /* Itbl support may require additional care here. */
6693 /* Itbl support may require additional care here. */
6717 /* Itbl support may require additional care here. */
6721 /* Itbl support may require additional care here. */
6726 /* Itbl support may require additional care here. */
6739 && NO_ISA_COP (mips_opts.arch)
6740 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6742 as_bad (_("Opcode not supported on this processor: %s"),
6743 mips_cpu_info_from_arch (mips_opts.arch)->name);
6747 /* Itbl support may require additional care here. */
6748 if (mask == M_LWC1_AB
6749 || mask == M_SWC1_AB
6750 || mask == M_LDC1_AB
6751 || mask == M_SDC1_AB
6755 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6762 if (offset_expr.X_op != O_constant
6763 && offset_expr.X_op != O_symbol)
6765 as_bad (_("Expression too complex"));
6766 offset_expr.X_op = O_constant;
6769 if (HAVE_32BIT_ADDRESSES
6770 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6774 sprintf_vma (value, offset_expr.X_add_number);
6775 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6778 /* A constant expression in PIC code can be handled just as it
6779 is in non PIC code. */
6780 if (offset_expr.X_op == O_constant)
6782 expr1.X_add_number = offset_expr.X_add_number;
6783 normalize_address_expr (&expr1);
6784 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6786 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6787 & ~(bfd_vma) 0xffff);
6788 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6790 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6791 tempreg, tempreg, breg);
6794 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6796 else if (mips_pic == NO_PIC)
6798 /* If this is a reference to a GP relative symbol, and there
6799 is no base register, we want
6800 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6801 Otherwise, if there is no base register, we want
6802 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6803 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6804 If we have a constant, we need two instructions anyhow,
6805 so we always use the latter form.
6807 If we have a base register, and this is a reference to a
6808 GP relative symbol, we want
6809 addu $tempreg,$breg,$gp
6810 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6812 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6813 addu $tempreg,$tempreg,$breg
6814 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6815 With a constant we always use the latter case.
6817 With 64bit address space and no base register and $at usable,
6819 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6820 lui $at,<sym> (BFD_RELOC_HI16_S)
6821 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6824 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6825 If we have a base register, we want
6826 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6827 lui $at,<sym> (BFD_RELOC_HI16_S)
6828 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6832 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6834 Without $at we can't generate the optimal path for superscalar
6835 processors here since this would require two temporary registers.
6836 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6837 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6839 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6841 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6842 If we have a base register, we want
6843 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6844 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6846 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6848 daddu $tempreg,$tempreg,$breg
6849 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6851 For GP relative symbols in 64bit address space we can use
6852 the same sequence as in 32bit address space. */
6853 if (HAVE_64BIT_SYMBOLS)
6855 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6856 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6858 relax_start (offset_expr.X_add_symbol);
6861 macro_build (&offset_expr, s, fmt, treg,
6862 BFD_RELOC_GPREL16, mips_gp_register);
6866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6867 tempreg, breg, mips_gp_register);
6868 macro_build (&offset_expr, s, fmt, treg,
6869 BFD_RELOC_GPREL16, tempreg);
6874 if (used_at == 0 && mips_opts.at)
6876 macro_build (&offset_expr, "lui", "t,u", tempreg,
6877 BFD_RELOC_MIPS_HIGHEST);
6878 macro_build (&offset_expr, "lui", "t,u", AT,
6880 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6881 tempreg, BFD_RELOC_MIPS_HIGHER);
6883 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6884 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6885 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6886 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6892 macro_build (&offset_expr, "lui", "t,u", tempreg,
6893 BFD_RELOC_MIPS_HIGHEST);
6894 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6895 tempreg, BFD_RELOC_MIPS_HIGHER);
6896 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6897 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6898 tempreg, BFD_RELOC_HI16_S);
6899 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6901 macro_build (NULL, "daddu", "d,v,t",
6902 tempreg, tempreg, breg);
6903 macro_build (&offset_expr, s, fmt, treg,
6904 BFD_RELOC_LO16, tempreg);
6907 if (mips_relax.sequence)
6914 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6915 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6917 relax_start (offset_expr.X_add_symbol);
6918 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6922 macro_build_lui (&offset_expr, tempreg);
6923 macro_build (&offset_expr, s, fmt, treg,
6924 BFD_RELOC_LO16, tempreg);
6925 if (mips_relax.sequence)
6930 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6931 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6933 relax_start (offset_expr.X_add_symbol);
6934 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6935 tempreg, breg, mips_gp_register);
6936 macro_build (&offset_expr, s, fmt, treg,
6937 BFD_RELOC_GPREL16, tempreg);
6940 macro_build_lui (&offset_expr, tempreg);
6941 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6942 tempreg, tempreg, breg);
6943 macro_build (&offset_expr, s, fmt, treg,
6944 BFD_RELOC_LO16, tempreg);
6945 if (mips_relax.sequence)
6949 else if (!mips_big_got)
6951 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6953 /* If this is a reference to an external symbol, we want
6954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6956 <op> $treg,0($tempreg)
6958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6961 <op> $treg,0($tempreg)
6964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6965 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6967 If there is a base register, we add it to $tempreg before
6968 the <op>. If there is a constant, we stick it in the
6969 <op> instruction. We don't handle constants larger than
6970 16 bits, because we have no way to load the upper 16 bits
6971 (actually, we could handle them for the subset of cases
6972 in which we are not using $at). */
6973 gas_assert (offset_expr.X_op == O_symbol);
6976 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6977 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6980 tempreg, tempreg, breg);
6981 macro_build (&offset_expr, s, fmt, treg,
6982 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6985 expr1.X_add_number = offset_expr.X_add_number;
6986 offset_expr.X_add_number = 0;
6987 if (expr1.X_add_number < -0x8000
6988 || expr1.X_add_number >= 0x8000)
6989 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6990 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6991 lw_reloc_type, mips_gp_register);
6993 relax_start (offset_expr.X_add_symbol);
6995 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6996 tempreg, BFD_RELOC_LO16);
6999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7000 tempreg, tempreg, breg);
7001 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7003 else if (mips_big_got && !HAVE_NEWABI)
7007 /* If this is a reference to an external symbol, we want
7008 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7009 addu $tempreg,$tempreg,$gp
7010 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7011 <op> $treg,0($tempreg)
7013 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7015 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7016 <op> $treg,0($tempreg)
7017 If there is a base register, we add it to $tempreg before
7018 the <op>. If there is a constant, we stick it in the
7019 <op> instruction. We don't handle constants larger than
7020 16 bits, because we have no way to load the upper 16 bits
7021 (actually, we could handle them for the subset of cases
7022 in which we are not using $at). */
7023 gas_assert (offset_expr.X_op == O_symbol);
7024 expr1.X_add_number = offset_expr.X_add_number;
7025 offset_expr.X_add_number = 0;
7026 if (expr1.X_add_number < -0x8000
7027 || expr1.X_add_number >= 0x8000)
7028 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7029 gpdelay = reg_needs_delay (mips_gp_register);
7030 relax_start (offset_expr.X_add_symbol);
7031 macro_build (&offset_expr, "lui", "t,u", tempreg,
7032 BFD_RELOC_MIPS_GOT_HI16);
7033 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7035 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7036 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7039 macro_build (NULL, "nop", "");
7040 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7041 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7043 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7044 tempreg, BFD_RELOC_LO16);
7048 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7049 tempreg, tempreg, breg);
7050 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7052 else if (mips_big_got && HAVE_NEWABI)
7054 /* If this is a reference to an external symbol, we want
7055 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7056 add $tempreg,$tempreg,$gp
7057 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7058 <op> $treg,<ofst>($tempreg)
7059 Otherwise, for local symbols, we want:
7060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7061 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7062 gas_assert (offset_expr.X_op == O_symbol);
7063 expr1.X_add_number = offset_expr.X_add_number;
7064 offset_expr.X_add_number = 0;
7065 if (expr1.X_add_number < -0x8000
7066 || expr1.X_add_number >= 0x8000)
7067 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7068 relax_start (offset_expr.X_add_symbol);
7069 macro_build (&offset_expr, "lui", "t,u", tempreg,
7070 BFD_RELOC_MIPS_GOT_HI16);
7071 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7073 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7074 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7076 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7077 tempreg, tempreg, breg);
7078 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7081 offset_expr.X_add_number = expr1.X_add_number;
7082 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7083 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7085 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7086 tempreg, tempreg, breg);
7087 macro_build (&offset_expr, s, fmt, treg,
7088 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7098 load_register (treg, &imm_expr, 0);
7102 load_register (treg, &imm_expr, 1);
7106 if (imm_expr.X_op == O_constant)
7109 load_register (AT, &imm_expr, 0);
7110 macro_build (NULL, "mtc1", "t,G", AT, treg);
7115 gas_assert (offset_expr.X_op == O_symbol
7116 && strcmp (segment_name (S_GET_SEGMENT
7117 (offset_expr.X_add_symbol)),
7119 && offset_expr.X_add_number == 0);
7120 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7121 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7126 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7127 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7128 order 32 bits of the value and the low order 32 bits are either
7129 zero or in OFFSET_EXPR. */
7130 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7132 if (HAVE_64BIT_GPRS)
7133 load_register (treg, &imm_expr, 1);
7138 if (target_big_endian)
7150 load_register (hreg, &imm_expr, 0);
7153 if (offset_expr.X_op == O_absent)
7154 move_register (lreg, 0);
7157 gas_assert (offset_expr.X_op == O_constant);
7158 load_register (lreg, &offset_expr, 0);
7165 /* We know that sym is in the .rdata section. First we get the
7166 upper 16 bits of the address. */
7167 if (mips_pic == NO_PIC)
7169 macro_build_lui (&offset_expr, AT);
7174 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7175 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7179 /* Now we load the register(s). */
7180 if (HAVE_64BIT_GPRS)
7183 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7188 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7191 /* FIXME: How in the world do we deal with the possible
7193 offset_expr.X_add_number += 4;
7194 macro_build (&offset_expr, "lw", "t,o(b)",
7195 treg + 1, BFD_RELOC_LO16, AT);
7201 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7202 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7203 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7204 the value and the low order 32 bits are either zero or in
7206 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7209 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7210 if (HAVE_64BIT_FPRS)
7212 gas_assert (HAVE_64BIT_GPRS);
7213 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7217 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7218 if (offset_expr.X_op == O_absent)
7219 macro_build (NULL, "mtc1", "t,G", 0, treg);
7222 gas_assert (offset_expr.X_op == O_constant);
7223 load_register (AT, &offset_expr, 0);
7224 macro_build (NULL, "mtc1", "t,G", AT, treg);
7230 gas_assert (offset_expr.X_op == O_symbol
7231 && offset_expr.X_add_number == 0);
7232 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7233 if (strcmp (s, ".lit8") == 0)
7235 if (mips_opts.isa != ISA_MIPS1)
7237 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7238 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7241 breg = mips_gp_register;
7242 r = BFD_RELOC_MIPS_LITERAL;
7247 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7249 if (mips_pic != NO_PIC)
7250 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7251 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7254 /* FIXME: This won't work for a 64 bit address. */
7255 macro_build_lui (&offset_expr, AT);
7258 if (mips_opts.isa != ISA_MIPS1)
7260 macro_build (&offset_expr, "ldc1", "T,o(b)",
7261 treg, BFD_RELOC_LO16, AT);
7270 /* Even on a big endian machine $fn comes before $fn+1. We have
7271 to adjust when loading from memory. */
7274 gas_assert (mips_opts.isa == ISA_MIPS1);
7275 macro_build (&offset_expr, "lwc1", "T,o(b)",
7276 target_big_endian ? treg + 1 : treg, r, breg);
7277 /* FIXME: A possible overflow which I don't know how to deal
7279 offset_expr.X_add_number += 4;
7280 macro_build (&offset_expr, "lwc1", "T,o(b)",
7281 target_big_endian ? treg : treg + 1, r, breg);
7285 gas_assert (mips_opts.isa == ISA_MIPS1);
7286 /* Even on a big endian machine $fn comes before $fn+1. We have
7287 to adjust when storing to memory. */
7288 macro_build (&offset_expr, "swc1", "T,o(b)",
7289 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7290 offset_expr.X_add_number += 4;
7291 macro_build (&offset_expr, "swc1", "T,o(b)",
7292 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7297 * The MIPS assembler seems to check for X_add_number not
7298 * being double aligned and generating:
7301 * addiu at,at,%lo(foo+1)
7304 * But, the resulting address is the same after relocation so why
7305 * generate the extra instruction?
7307 /* Itbl support may require additional care here. */
7309 if (mips_opts.isa != ISA_MIPS1)
7320 if (mips_opts.isa != ISA_MIPS1)
7328 /* Itbl support may require additional care here. */
7333 if (HAVE_64BIT_GPRS)
7344 if (HAVE_64BIT_GPRS)
7354 if (offset_expr.X_op != O_symbol
7355 && offset_expr.X_op != O_constant)
7357 as_bad (_("Expression too complex"));
7358 offset_expr.X_op = O_constant;
7361 if (HAVE_32BIT_ADDRESSES
7362 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7366 sprintf_vma (value, offset_expr.X_add_number);
7367 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7370 /* Even on a big endian machine $fn comes before $fn+1. We have
7371 to adjust when loading from memory. We set coproc if we must
7372 load $fn+1 first. */
7373 /* Itbl support may require additional care here. */
7374 if (!target_big_endian)
7377 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7379 /* If this is a reference to a GP relative symbol, we want
7380 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7381 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7382 If we have a base register, we use this
7384 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7385 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7386 If this is not a GP relative symbol, we want
7387 lui $at,<sym> (BFD_RELOC_HI16_S)
7388 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7389 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7390 If there is a base register, we add it to $at after the
7391 lui instruction. If there is a constant, we always use
7393 if (offset_expr.X_op == O_symbol
7394 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7395 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7397 relax_start (offset_expr.X_add_symbol);
7400 tempreg = mips_gp_register;
7404 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7405 AT, breg, mips_gp_register);
7410 /* Itbl support may require additional care here. */
7411 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7412 BFD_RELOC_GPREL16, tempreg);
7413 offset_expr.X_add_number += 4;
7415 /* Set mips_optimize to 2 to avoid inserting an
7417 hold_mips_optimize = mips_optimize;
7419 /* Itbl support may require additional care here. */
7420 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7421 BFD_RELOC_GPREL16, tempreg);
7422 mips_optimize = hold_mips_optimize;
7426 offset_expr.X_add_number -= 4;
7429 macro_build_lui (&offset_expr, AT);
7431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7432 /* Itbl support may require additional care here. */
7433 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7434 BFD_RELOC_LO16, AT);
7435 /* FIXME: How do we handle overflow here? */
7436 offset_expr.X_add_number += 4;
7437 /* Itbl support may require additional care here. */
7438 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7439 BFD_RELOC_LO16, AT);
7440 if (mips_relax.sequence)
7443 else if (!mips_big_got)
7445 /* If this is a reference to an external symbol, we want
7446 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7451 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7453 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7454 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7455 If there is a base register we add it to $at before the
7456 lwc1 instructions. If there is a constant we include it
7457 in the lwc1 instructions. */
7459 expr1.X_add_number = offset_expr.X_add_number;
7460 if (expr1.X_add_number < -0x8000
7461 || expr1.X_add_number >= 0x8000 - 4)
7462 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7463 load_got_offset (AT, &offset_expr);
7466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7468 /* Set mips_optimize to 2 to avoid inserting an undesired
7470 hold_mips_optimize = mips_optimize;
7473 /* Itbl support may require additional care here. */
7474 relax_start (offset_expr.X_add_symbol);
7475 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7476 BFD_RELOC_LO16, AT);
7477 expr1.X_add_number += 4;
7478 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7479 BFD_RELOC_LO16, AT);
7481 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7482 BFD_RELOC_LO16, AT);
7483 offset_expr.X_add_number += 4;
7484 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7485 BFD_RELOC_LO16, AT);
7488 mips_optimize = hold_mips_optimize;
7490 else if (mips_big_got)
7494 /* If this is a reference to an external symbol, we want
7495 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7497 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7502 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7504 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7505 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7506 If there is a base register we add it to $at before the
7507 lwc1 instructions. If there is a constant we include it
7508 in the lwc1 instructions. */
7510 expr1.X_add_number = offset_expr.X_add_number;
7511 offset_expr.X_add_number = 0;
7512 if (expr1.X_add_number < -0x8000
7513 || expr1.X_add_number >= 0x8000 - 4)
7514 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7515 gpdelay = reg_needs_delay (mips_gp_register);
7516 relax_start (offset_expr.X_add_symbol);
7517 macro_build (&offset_expr, "lui", "t,u",
7518 AT, BFD_RELOC_MIPS_GOT_HI16);
7519 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7520 AT, AT, mips_gp_register);
7521 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7522 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7525 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7526 /* Itbl support may require additional care here. */
7527 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7528 BFD_RELOC_LO16, AT);
7529 expr1.X_add_number += 4;
7531 /* Set mips_optimize to 2 to avoid inserting an undesired
7533 hold_mips_optimize = mips_optimize;
7535 /* Itbl support may require additional care here. */
7536 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7537 BFD_RELOC_LO16, AT);
7538 mips_optimize = hold_mips_optimize;
7539 expr1.X_add_number -= 4;
7542 offset_expr.X_add_number = expr1.X_add_number;
7544 macro_build (NULL, "nop", "");
7545 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7546 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7550 /* Itbl support may require additional care here. */
7551 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7552 BFD_RELOC_LO16, AT);
7553 offset_expr.X_add_number += 4;
7555 /* Set mips_optimize to 2 to avoid inserting an undesired
7557 hold_mips_optimize = mips_optimize;
7559 /* Itbl support may require additional care here. */
7560 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7561 BFD_RELOC_LO16, AT);
7562 mips_optimize = hold_mips_optimize;
7571 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7574 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7576 macro_build (&offset_expr, s, "t,o(b)", treg,
7577 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7579 if (!HAVE_64BIT_GPRS)
7581 offset_expr.X_add_number += 4;
7582 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7583 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7588 /* New code added to support COPZ instructions.
7589 This code builds table entries out of the macros in mip_opcodes.
7590 R4000 uses interlocks to handle coproc delays.
7591 Other chips (like the R3000) require nops to be inserted for delays.
7593 FIXME: Currently, we require that the user handle delays.
7594 In order to fill delay slots for non-interlocked chips,
7595 we must have a way to specify delays based on the coprocessor.
7596 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7597 What are the side-effects of the cop instruction?
7598 What cache support might we have and what are its effects?
7599 Both coprocessor & memory require delays. how long???
7600 What registers are read/set/modified?
7602 If an itbl is provided to interpret cop instructions,
7603 this knowledge can be encoded in the itbl spec. */
7617 if (NO_ISA_COP (mips_opts.arch)
7618 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7620 as_bad (_("opcode not supported on this processor: %s"),
7621 mips_cpu_info_from_arch (mips_opts.arch)->name);
7625 /* For now we just do C (same as Cz). The parameter will be
7626 stored in insn_opcode by mips_ip. */
7627 macro_build (NULL, s, "C", ip->insn_opcode);
7631 move_register (dreg, sreg);
7637 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7638 macro_build (NULL, "mflo", "d", dreg);
7644 /* The MIPS assembler some times generates shifts and adds. I'm
7645 not trying to be that fancy. GCC should do this for us
7648 load_register (AT, &imm_expr, dbl);
7649 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7650 macro_build (NULL, "mflo", "d", dreg);
7666 load_register (AT, &imm_expr, dbl);
7667 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7668 macro_build (NULL, "mflo", "d", dreg);
7669 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7670 macro_build (NULL, "mfhi", "d", AT);
7672 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7675 expr1.X_add_number = 8;
7676 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7677 macro_build (NULL, "nop", "");
7678 macro_build (NULL, "break", "c", 6);
7681 macro_build (NULL, "mflo", "d", dreg);
7697 load_register (AT, &imm_expr, dbl);
7698 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7699 sreg, imm ? AT : treg);
7700 macro_build (NULL, "mfhi", "d", AT);
7701 macro_build (NULL, "mflo", "d", dreg);
7703 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7706 expr1.X_add_number = 8;
7707 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7708 macro_build (NULL, "nop", "");
7709 macro_build (NULL, "break", "c", 6);
7715 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7726 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7727 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7731 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7732 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7733 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7734 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7738 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7749 macro_build (NULL, "negu", "d,w", tempreg, treg);
7750 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7754 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7755 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7756 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7757 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7766 if (imm_expr.X_op != O_constant)
7767 as_bad (_("Improper rotate count"));
7768 rot = imm_expr.X_add_number & 0x3f;
7769 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7771 rot = (64 - rot) & 0x3f;
7773 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7775 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7780 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7783 l = (rot < 0x20) ? "dsll" : "dsll32";
7784 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7787 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7788 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7789 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7797 if (imm_expr.X_op != O_constant)
7798 as_bad (_("Improper rotate count"));
7799 rot = imm_expr.X_add_number & 0x1f;
7800 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7802 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7807 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7811 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7812 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7813 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7818 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7820 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7824 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7825 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7826 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7827 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7831 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7833 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7837 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7838 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7839 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7840 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7849 if (imm_expr.X_op != O_constant)
7850 as_bad (_("Improper rotate count"));
7851 rot = imm_expr.X_add_number & 0x3f;
7852 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7855 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7857 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7862 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7865 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7866 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7869 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7870 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7871 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7879 if (imm_expr.X_op != O_constant)
7880 as_bad (_("Improper rotate count"));
7881 rot = imm_expr.X_add_number & 0x1f;
7882 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7884 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7889 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7893 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7894 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7895 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7901 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7903 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7906 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7907 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7912 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7914 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7919 as_warn (_("Instruction %s: result is always false"),
7921 move_register (dreg, 0);
7924 if (CPU_HAS_SEQ (mips_opts.arch)
7925 && -512 <= imm_expr.X_add_number
7926 && imm_expr.X_add_number < 512)
7928 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7929 (int) imm_expr.X_add_number);
7932 if (imm_expr.X_op == O_constant
7933 && imm_expr.X_add_number >= 0
7934 && imm_expr.X_add_number < 0x10000)
7936 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7938 else if (imm_expr.X_op == O_constant
7939 && imm_expr.X_add_number > -0x8000
7940 && imm_expr.X_add_number < 0)
7942 imm_expr.X_add_number = -imm_expr.X_add_number;
7943 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7944 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7946 else if (CPU_HAS_SEQ (mips_opts.arch))
7949 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7950 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7955 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7956 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7959 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7962 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7968 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7969 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7972 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7974 if (imm_expr.X_op == O_constant
7975 && imm_expr.X_add_number >= -0x8000
7976 && imm_expr.X_add_number < 0x8000)
7978 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7979 dreg, sreg, BFD_RELOC_LO16);
7983 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7984 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7988 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7991 case M_SGT: /* sreg > treg <==> treg < sreg */
7997 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8000 case M_SGT_I: /* sreg > I <==> I < sreg */
8007 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8008 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8011 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8017 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8018 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8021 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8028 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8029 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8030 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8034 if (imm_expr.X_op == O_constant
8035 && imm_expr.X_add_number >= -0x8000
8036 && imm_expr.X_add_number < 0x8000)
8038 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8042 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8043 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8047 if (imm_expr.X_op == O_constant
8048 && imm_expr.X_add_number >= -0x8000
8049 && imm_expr.X_add_number < 0x8000)
8051 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8056 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8057 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8062 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8064 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8067 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8068 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8073 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8075 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8080 as_warn (_("Instruction %s: result is always true"),
8082 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8083 dreg, 0, BFD_RELOC_LO16);
8086 if (CPU_HAS_SEQ (mips_opts.arch)
8087 && -512 <= imm_expr.X_add_number
8088 && imm_expr.X_add_number < 512)
8090 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8091 (int) imm_expr.X_add_number);
8094 if (imm_expr.X_op == O_constant
8095 && imm_expr.X_add_number >= 0
8096 && imm_expr.X_add_number < 0x10000)
8098 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8100 else if (imm_expr.X_op == O_constant
8101 && imm_expr.X_add_number > -0x8000
8102 && imm_expr.X_add_number < 0)
8104 imm_expr.X_add_number = -imm_expr.X_add_number;
8105 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8106 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8108 else if (CPU_HAS_SEQ (mips_opts.arch))
8111 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8112 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8117 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8118 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8121 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8127 if (imm_expr.X_op == O_constant
8128 && imm_expr.X_add_number > -0x8000
8129 && imm_expr.X_add_number <= 0x8000)
8131 imm_expr.X_add_number = -imm_expr.X_add_number;
8132 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8133 dreg, sreg, BFD_RELOC_LO16);
8137 load_register (AT, &imm_expr, dbl);
8138 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8144 if (imm_expr.X_op == O_constant
8145 && imm_expr.X_add_number > -0x8000
8146 && imm_expr.X_add_number <= 0x8000)
8148 imm_expr.X_add_number = -imm_expr.X_add_number;
8149 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8150 dreg, sreg, BFD_RELOC_LO16);
8154 load_register (AT, &imm_expr, dbl);
8155 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8177 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8178 macro_build (NULL, s, "s,t", sreg, AT);
8183 gas_assert (mips_opts.isa == ISA_MIPS1);
8185 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8186 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8189 * Is the double cfc1 instruction a bug in the mips assembler;
8190 * or is there a reason for it?
8193 macro_build (NULL, "cfc1", "t,G", treg, RA);
8194 macro_build (NULL, "cfc1", "t,G", treg, RA);
8195 macro_build (NULL, "nop", "");
8196 expr1.X_add_number = 3;
8197 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8198 expr1.X_add_number = 2;
8199 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8200 macro_build (NULL, "ctc1", "t,G", AT, RA);
8201 macro_build (NULL, "nop", "");
8202 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8204 macro_build (NULL, "ctc1", "t,G", treg, RA);
8205 macro_build (NULL, "nop", "");
8216 if (offset_expr.X_add_number >= 0x7fff)
8217 as_bad (_("Operand overflow"));
8218 if (!target_big_endian)
8219 ++offset_expr.X_add_number;
8220 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8221 if (!target_big_endian)
8222 --offset_expr.X_add_number;
8224 ++offset_expr.X_add_number;
8225 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8226 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8227 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8240 if (offset_expr.X_add_number >= 0x8000 - off)
8241 as_bad (_("Operand overflow"));
8249 if (!target_big_endian)
8250 offset_expr.X_add_number += off;
8251 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8252 if (!target_big_endian)
8253 offset_expr.X_add_number -= off;
8255 offset_expr.X_add_number += off;
8256 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8258 /* If necessary, move the result in tempreg to the final destination. */
8259 if (treg == tempreg)
8261 /* Protect second load's delay slot. */
8263 move_register (treg, tempreg);
8277 load_address (AT, &offset_expr, &used_at);
8279 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8280 if (!target_big_endian)
8281 expr1.X_add_number = off;
8283 expr1.X_add_number = 0;
8284 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8285 if (!target_big_endian)
8286 expr1.X_add_number = 0;
8288 expr1.X_add_number = off;
8289 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8295 load_address (AT, &offset_expr, &used_at);
8297 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8298 if (target_big_endian)
8299 expr1.X_add_number = 0;
8300 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8301 treg, BFD_RELOC_LO16, AT);
8302 if (target_big_endian)
8303 expr1.X_add_number = 1;
8305 expr1.X_add_number = 0;
8306 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8307 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8308 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8313 if (offset_expr.X_add_number >= 0x7fff)
8314 as_bad (_("Operand overflow"));
8315 if (target_big_endian)
8316 ++offset_expr.X_add_number;
8317 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8318 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8319 if (target_big_endian)
8320 --offset_expr.X_add_number;
8322 ++offset_expr.X_add_number;
8323 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8336 if (offset_expr.X_add_number >= 0x8000 - off)
8337 as_bad (_("Operand overflow"));
8338 if (!target_big_endian)
8339 offset_expr.X_add_number += off;
8340 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8341 if (!target_big_endian)
8342 offset_expr.X_add_number -= off;
8344 offset_expr.X_add_number += off;
8345 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8359 load_address (AT, &offset_expr, &used_at);
8361 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8362 if (!target_big_endian)
8363 expr1.X_add_number = off;
8365 expr1.X_add_number = 0;
8366 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8367 if (!target_big_endian)
8368 expr1.X_add_number = 0;
8370 expr1.X_add_number = off;
8371 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8376 load_address (AT, &offset_expr, &used_at);
8378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8379 if (!target_big_endian)
8380 expr1.X_add_number = 0;
8381 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8382 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8383 if (!target_big_endian)
8384 expr1.X_add_number = 1;
8386 expr1.X_add_number = 0;
8387 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8388 if (!target_big_endian)
8389 expr1.X_add_number = 0;
8391 expr1.X_add_number = 1;
8392 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8393 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8394 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8398 /* FIXME: Check if this is one of the itbl macros, since they
8399 are added dynamically. */
8400 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8403 if (!mips_opts.at && used_at)
8404 as_bad (_("Macro used $at after \".set noat\""));
8407 /* Implement macros in mips16 mode. */
8410 mips16_macro (struct mips_cl_insn *ip)
8413 int xreg, yreg, zreg, tmp;
8416 const char *s, *s2, *s3;
8418 mask = ip->insn_mo->mask;
8420 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8421 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8422 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8424 expr1.X_op = O_constant;
8425 expr1.X_op_symbol = NULL;
8426 expr1.X_add_symbol = NULL;
8427 expr1.X_add_number = 1;
8447 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8448 expr1.X_add_number = 2;
8449 macro_build (&expr1, "bnez", "x,p", yreg);
8450 macro_build (NULL, "break", "6", 7);
8452 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8453 since that causes an overflow. We should do that as well,
8454 but I don't see how to do the comparisons without a temporary
8457 macro_build (NULL, s, "x", zreg);
8477 macro_build (NULL, s, "0,x,y", xreg, yreg);
8478 expr1.X_add_number = 2;
8479 macro_build (&expr1, "bnez", "x,p", yreg);
8480 macro_build (NULL, "break", "6", 7);
8482 macro_build (NULL, s2, "x", zreg);
8488 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8489 macro_build (NULL, "mflo", "x", zreg);
8497 if (imm_expr.X_op != O_constant)
8498 as_bad (_("Unsupported large constant"));
8499 imm_expr.X_add_number = -imm_expr.X_add_number;
8500 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8504 if (imm_expr.X_op != O_constant)
8505 as_bad (_("Unsupported large constant"));
8506 imm_expr.X_add_number = -imm_expr.X_add_number;
8507 macro_build (&imm_expr, "addiu", "x,k", xreg);
8511 if (imm_expr.X_op != O_constant)
8512 as_bad (_("Unsupported large constant"));
8513 imm_expr.X_add_number = -imm_expr.X_add_number;
8514 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8536 goto do_reverse_branch;
8540 goto do_reverse_branch;
8552 goto do_reverse_branch;
8563 macro_build (NULL, s, "x,y", xreg, yreg);
8564 macro_build (&offset_expr, s2, "p");
8591 goto do_addone_branch_i;
8596 goto do_addone_branch_i;
8611 goto do_addone_branch_i;
8618 if (imm_expr.X_op != O_constant)
8619 as_bad (_("Unsupported large constant"));
8620 ++imm_expr.X_add_number;
8623 macro_build (&imm_expr, s, s3, xreg);
8624 macro_build (&offset_expr, s2, "p");
8628 expr1.X_add_number = 0;
8629 macro_build (&expr1, "slti", "x,8", yreg);
8631 move_register (xreg, yreg);
8632 expr1.X_add_number = 2;
8633 macro_build (&expr1, "bteqz", "p");
8634 macro_build (NULL, "neg", "x,w", xreg, xreg);
8638 /* For consistency checking, verify that all bits are specified either
8639 by the match/mask part of the instruction definition, or by the
8642 validate_mips_insn (const struct mips_opcode *opc)
8644 const char *p = opc->args;
8646 unsigned long used_bits = opc->mask;
8648 if ((used_bits & opc->match) != opc->match)
8650 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8651 opc->name, opc->args);
8654 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8664 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8665 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8666 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8667 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8668 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8669 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8670 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8671 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8672 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8673 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8674 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8675 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8676 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8678 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8679 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8680 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8681 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8682 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8683 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8684 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8685 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8686 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8687 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8688 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8689 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8690 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8691 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8692 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8695 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8696 c, opc->name, opc->args);
8700 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8701 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8703 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8704 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8705 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8706 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8708 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8709 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8711 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8712 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8714 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8715 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8716 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8717 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8718 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8719 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8720 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8721 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8722 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8723 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8724 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8725 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8726 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8727 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8728 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8729 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8730 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8732 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8733 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8734 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8735 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8737 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8738 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8739 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8740 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8741 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8742 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8743 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8744 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8745 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8748 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8749 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8750 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8751 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8752 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8755 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8756 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8757 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8758 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8759 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8760 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8761 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8762 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8763 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8764 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8765 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8766 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8767 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8768 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8769 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8770 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8771 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8772 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8774 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8775 c, opc->name, opc->args);
8779 if (used_bits != 0xffffffff)
8781 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8782 ~used_bits & 0xffffffff, opc->name, opc->args);
8788 /* UDI immediates. */
8796 static const struct mips_immed mips_immed[] = {
8797 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8798 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8799 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8800 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8804 /* Check whether an odd floating-point register is allowed. */
8806 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8808 const char *s = insn->name;
8810 if (insn->pinfo == INSN_MACRO)
8811 /* Let a macro pass, we'll catch it later when it is expanded. */
8814 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8816 /* Allow odd registers for single-precision ops. */
8817 switch (insn->pinfo & (FP_S | FP_D))
8821 return 1; /* both single precision - ok */
8823 return 0; /* both double precision - fail */
8828 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8829 s = strchr (insn->name, '.');
8831 s = s != NULL ? strchr (s + 1, '.') : NULL;
8832 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8835 /* Single-precision coprocessor loads and moves are OK too. */
8836 if ((insn->pinfo & FP_S)
8837 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8838 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8844 /* This routine assembles an instruction into its binary format. As a
8845 side effect, it sets one of the global variables imm_reloc or
8846 offset_reloc to the type of relocation to do if one of the operands
8847 is an address expression. */
8850 mips_ip (char *str, struct mips_cl_insn *ip)
8855 struct mips_opcode *insn;
8858 unsigned int lastregno;
8859 unsigned int lastpos = 0;
8860 unsigned int limlo, limhi;
8863 offsetT min_range, max_range;
8869 /* If the instruction contains a '.', we first try to match an instruction
8870 including the '.'. Then we try again without the '.'. */
8872 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8875 /* If we stopped on whitespace, then replace the whitespace with null for
8876 the call to hash_find. Save the character we replaced just in case we
8877 have to re-parse the instruction. */
8884 insn = (struct mips_opcode *) hash_find (op_hash, str);
8886 /* If we didn't find the instruction in the opcode table, try again, but
8887 this time with just the instruction up to, but not including the
8891 /* Restore the character we overwrite above (if any). */
8895 /* Scan up to the first '.' or whitespace. */
8897 *s != '\0' && *s != '.' && !ISSPACE (*s);
8901 /* If we did not find a '.', then we can quit now. */
8904 insn_error = _("Unrecognized opcode");
8908 /* Lookup the instruction in the hash table. */
8910 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8912 insn_error = _("Unrecognized opcode");
8922 gas_assert (strcmp (insn->name, str) == 0);
8924 ok = is_opcode_valid (insn);
8927 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8928 && strcmp (insn->name, insn[1].name) == 0)
8937 static char buf[100];
8939 _("opcode not supported on this processor: %s (%s)"),
8940 mips_cpu_info_from_arch (mips_opts.arch)->name,
8941 mips_cpu_info_from_isa (mips_opts.isa)->name);
8950 create_insn (ip, insn);
8953 lastregno = 0xffffffff;
8954 for (args = insn->args;; ++args)
8958 s += strspn (s, " \t");
8962 case '\0': /* end of args */
8967 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8968 my_getExpression (&imm_expr, s);
8969 check_absolute_expr (ip, &imm_expr);
8970 if ((unsigned long) imm_expr.X_add_number != 1
8971 && (unsigned long) imm_expr.X_add_number != 3)
8973 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8974 (unsigned long) imm_expr.X_add_number);
8976 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8977 imm_expr.X_op = O_absent;
8981 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8982 my_getExpression (&imm_expr, s);
8983 check_absolute_expr (ip, &imm_expr);
8984 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8986 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8987 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8989 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8990 imm_expr.X_op = O_absent;
8994 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8995 my_getExpression (&imm_expr, s);
8996 check_absolute_expr (ip, &imm_expr);
8997 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8999 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9000 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9002 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9003 imm_expr.X_op = O_absent;
9007 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9008 my_getExpression (&imm_expr, s);
9009 check_absolute_expr (ip, &imm_expr);
9010 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9012 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9013 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9015 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9016 imm_expr.X_op = O_absent;
9020 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9021 my_getExpression (&imm_expr, s);
9022 check_absolute_expr (ip, &imm_expr);
9023 if (imm_expr.X_add_number & ~OP_MASK_RS)
9025 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9026 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9028 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9029 imm_expr.X_op = O_absent;
9033 case '7': /* Four DSP accumulators in bits 11,12. */
9034 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9035 s[3] >= '0' && s[3] <= '3')
9039 INSERT_OPERAND (DSPACC, *ip, regno);
9043 as_bad (_("Invalid dsp acc register"));
9046 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9047 my_getExpression (&imm_expr, s);
9048 check_absolute_expr (ip, &imm_expr);
9049 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9051 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9053 (unsigned long) imm_expr.X_add_number);
9055 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9056 imm_expr.X_op = O_absent;
9060 case '9': /* Four DSP accumulators in bits 21,22. */
9061 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9062 s[3] >= '0' && s[3] <= '3')
9066 INSERT_OPERAND (DSPACC_S, *ip, regno);
9070 as_bad (_("Invalid dsp acc register"));
9073 case '0': /* DSP 6-bit signed immediate in bit 20. */
9074 my_getExpression (&imm_expr, s);
9075 check_absolute_expr (ip, &imm_expr);
9076 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9077 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9078 if (imm_expr.X_add_number < min_range ||
9079 imm_expr.X_add_number > max_range)
9081 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9082 (long) min_range, (long) max_range,
9083 (long) imm_expr.X_add_number);
9085 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9086 imm_expr.X_op = O_absent;
9090 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9091 my_getExpression (&imm_expr, s);
9092 check_absolute_expr (ip, &imm_expr);
9093 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9095 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9097 (unsigned long) imm_expr.X_add_number);
9099 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9100 imm_expr.X_op = O_absent;
9104 case ':': /* DSP 7-bit signed immediate in bit 19. */
9105 my_getExpression (&imm_expr, s);
9106 check_absolute_expr (ip, &imm_expr);
9107 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9108 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9109 if (imm_expr.X_add_number < min_range ||
9110 imm_expr.X_add_number > max_range)
9112 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9113 (long) min_range, (long) max_range,
9114 (long) imm_expr.X_add_number);
9116 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9117 imm_expr.X_op = O_absent;
9121 case '@': /* DSP 10-bit signed immediate in bit 16. */
9122 my_getExpression (&imm_expr, s);
9123 check_absolute_expr (ip, &imm_expr);
9124 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9125 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9126 if (imm_expr.X_add_number < min_range ||
9127 imm_expr.X_add_number > max_range)
9129 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9130 (long) min_range, (long) max_range,
9131 (long) imm_expr.X_add_number);
9133 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9134 imm_expr.X_op = O_absent;
9138 case '!': /* MT usermode flag bit. */
9139 my_getExpression (&imm_expr, s);
9140 check_absolute_expr (ip, &imm_expr);
9141 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9142 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9143 (unsigned long) imm_expr.X_add_number);
9144 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9145 imm_expr.X_op = O_absent;
9149 case '$': /* MT load high flag bit. */
9150 my_getExpression (&imm_expr, s);
9151 check_absolute_expr (ip, &imm_expr);
9152 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9153 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9154 (unsigned long) imm_expr.X_add_number);
9155 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9156 imm_expr.X_op = O_absent;
9160 case '*': /* Four DSP accumulators in bits 18,19. */
9161 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9162 s[3] >= '0' && s[3] <= '3')
9166 INSERT_OPERAND (MTACC_T, *ip, regno);
9170 as_bad (_("Invalid dsp/smartmips acc register"));
9173 case '&': /* Four DSP accumulators in bits 13,14. */
9174 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9175 s[3] >= '0' && s[3] <= '3')
9179 INSERT_OPERAND (MTACC_D, *ip, regno);
9183 as_bad (_("Invalid dsp/smartmips acc register"));
9195 INSERT_OPERAND (RS, *ip, lastregno);
9199 INSERT_OPERAND (RT, *ip, lastregno);
9203 INSERT_OPERAND (FT, *ip, lastregno);
9207 INSERT_OPERAND (FS, *ip, lastregno);
9213 /* Handle optional base register.
9214 Either the base register is omitted or
9215 we must have a left paren. */
9216 /* This is dependent on the next operand specifier
9217 is a base register specification. */
9218 gas_assert (args[1] == 'b');
9222 case ')': /* These must match exactly. */
9229 case '+': /* Opcode extension character. */
9232 case '1': /* UDI immediates. */
9237 const struct mips_immed *imm = mips_immed;
9239 while (imm->type && imm->type != *args)
9243 my_getExpression (&imm_expr, s);
9244 check_absolute_expr (ip, &imm_expr);
9245 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9247 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9248 imm->desc ? imm->desc : ip->insn_mo->name,
9249 (unsigned long) imm_expr.X_add_number,
9250 (unsigned long) imm_expr.X_add_number);
9251 imm_expr.X_add_number &= imm->mask;
9253 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9255 imm_expr.X_op = O_absent;
9260 case 'A': /* ins/ext position, becomes LSB. */
9269 my_getExpression (&imm_expr, s);
9270 check_absolute_expr (ip, &imm_expr);
9271 if ((unsigned long) imm_expr.X_add_number < limlo
9272 || (unsigned long) imm_expr.X_add_number > limhi)
9274 as_bad (_("Improper position (%lu)"),
9275 (unsigned long) imm_expr.X_add_number);
9276 imm_expr.X_add_number = limlo;
9278 lastpos = imm_expr.X_add_number;
9279 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9280 imm_expr.X_op = O_absent;
9284 case 'B': /* ins size, becomes MSB. */
9293 my_getExpression (&imm_expr, s);
9294 check_absolute_expr (ip, &imm_expr);
9295 /* Check for negative input so that small negative numbers
9296 will not succeed incorrectly. The checks against
9297 (pos+size) transitively check "size" itself,
9298 assuming that "pos" is reasonable. */
9299 if ((long) imm_expr.X_add_number < 0
9300 || ((unsigned long) imm_expr.X_add_number
9302 || ((unsigned long) imm_expr.X_add_number
9305 as_bad (_("Improper insert size (%lu, position %lu)"),
9306 (unsigned long) imm_expr.X_add_number,
9307 (unsigned long) lastpos);
9308 imm_expr.X_add_number = limlo - lastpos;
9310 INSERT_OPERAND (INSMSB, *ip,
9311 lastpos + imm_expr.X_add_number - 1);
9312 imm_expr.X_op = O_absent;
9316 case 'C': /* ext size, becomes MSBD. */
9329 my_getExpression (&imm_expr, s);
9330 check_absolute_expr (ip, &imm_expr);
9331 /* Check for negative input so that small negative numbers
9332 will not succeed incorrectly. The checks against
9333 (pos+size) transitively check "size" itself,
9334 assuming that "pos" is reasonable. */
9335 if ((long) imm_expr.X_add_number < 0
9336 || ((unsigned long) imm_expr.X_add_number
9338 || ((unsigned long) imm_expr.X_add_number
9341 as_bad (_("Improper extract size (%lu, position %lu)"),
9342 (unsigned long) imm_expr.X_add_number,
9343 (unsigned long) lastpos);
9344 imm_expr.X_add_number = limlo - lastpos;
9346 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9347 imm_expr.X_op = O_absent;
9352 /* +D is for disassembly only; never match. */
9356 /* "+I" is like "I", except that imm2_expr is used. */
9357 my_getExpression (&imm2_expr, s);
9358 if (imm2_expr.X_op != O_big
9359 && imm2_expr.X_op != O_constant)
9360 insn_error = _("absolute expression required");
9361 if (HAVE_32BIT_GPRS)
9362 normalize_constant_expr (&imm2_expr);
9366 case 'T': /* Coprocessor register. */
9367 /* +T is for disassembly only; never match. */
9370 case 't': /* Coprocessor register number. */
9371 if (s[0] == '$' && ISDIGIT (s[1]))
9381 while (ISDIGIT (*s));
9383 as_bad (_("Invalid register number (%d)"), regno);
9386 INSERT_OPERAND (RT, *ip, regno);
9391 as_bad (_("Invalid coprocessor 0 register number"));
9395 /* bbit[01] and bbit[01]32 bit index. Give error if index
9396 is not in the valid range. */
9397 my_getExpression (&imm_expr, s);
9398 check_absolute_expr (ip, &imm_expr);
9399 if ((unsigned) imm_expr.X_add_number > 31)
9401 as_bad (_("Improper bit index (%lu)"),
9402 (unsigned long) imm_expr.X_add_number);
9403 imm_expr.X_add_number = 0;
9405 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9406 imm_expr.X_op = O_absent;
9411 /* bbit[01] bit index when bbit is used but we generate
9412 bbit[01]32 because the index is over 32. Move to the
9413 next candidate if index is not in the valid range. */
9414 my_getExpression (&imm_expr, s);
9415 check_absolute_expr (ip, &imm_expr);
9416 if ((unsigned) imm_expr.X_add_number < 32
9417 || (unsigned) imm_expr.X_add_number > 63)
9419 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9420 imm_expr.X_op = O_absent;
9425 /* cins, cins32, exts and exts32 position field. Give error
9426 if it's not in the valid range. */
9427 my_getExpression (&imm_expr, s);
9428 check_absolute_expr (ip, &imm_expr);
9429 if ((unsigned) imm_expr.X_add_number > 31)
9431 as_bad (_("Improper position (%lu)"),
9432 (unsigned long) imm_expr.X_add_number);
9433 imm_expr.X_add_number = 0;
9435 /* Make the pos explicit to simplify +S. */
9436 lastpos = imm_expr.X_add_number + 32;
9437 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9438 imm_expr.X_op = O_absent;
9443 /* cins, cins32, exts and exts32 position field. Move to
9444 the next candidate if it's not in the valid range. */
9445 my_getExpression (&imm_expr, s);
9446 check_absolute_expr (ip, &imm_expr);
9447 if ((unsigned) imm_expr.X_add_number < 32
9448 || (unsigned) imm_expr.X_add_number > 63)
9450 lastpos = imm_expr.X_add_number;
9451 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9452 imm_expr.X_op = O_absent;
9457 /* cins and exts length-minus-one field. */
9458 my_getExpression (&imm_expr, s);
9459 check_absolute_expr (ip, &imm_expr);
9460 if ((unsigned long) imm_expr.X_add_number > 31)
9462 as_bad (_("Improper size (%lu)"),
9463 (unsigned long) imm_expr.X_add_number);
9464 imm_expr.X_add_number = 0;
9466 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9467 imm_expr.X_op = O_absent;
9472 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9473 length-minus-one field. */
9474 my_getExpression (&imm_expr, s);
9475 check_absolute_expr (ip, &imm_expr);
9476 if ((long) imm_expr.X_add_number < 0
9477 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9479 as_bad (_("Improper size (%lu)"),
9480 (unsigned long) imm_expr.X_add_number);
9481 imm_expr.X_add_number = 0;
9483 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9484 imm_expr.X_op = O_absent;
9489 /* seqi/snei immediate field. */
9490 my_getExpression (&imm_expr, s);
9491 check_absolute_expr (ip, &imm_expr);
9492 if ((long) imm_expr.X_add_number < -512
9493 || (long) imm_expr.X_add_number >= 512)
9495 as_bad (_("Improper immediate (%ld)"),
9496 (long) imm_expr.X_add_number);
9497 imm_expr.X_add_number = 0;
9499 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9500 imm_expr.X_op = O_absent;
9504 case 'a': /* 8-bit signed offset in bit 6 */
9505 my_getExpression (&imm_expr, s);
9506 check_absolute_expr (ip, &imm_expr);
9507 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9508 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9509 if (imm_expr.X_add_number < min_range
9510 || imm_expr.X_add_number > max_range)
9512 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9513 (long) min_range, (long) max_range,
9514 (long) imm_expr.X_add_number);
9516 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9517 imm_expr.X_op = O_absent;
9521 case 'b': /* 8-bit signed offset in bit 3 */
9522 my_getExpression (&imm_expr, s);
9523 check_absolute_expr (ip, &imm_expr);
9524 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9525 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9526 if (imm_expr.X_add_number < min_range
9527 || imm_expr.X_add_number > max_range)
9529 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9530 (long) min_range, (long) max_range,
9531 (long) imm_expr.X_add_number);
9533 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9534 imm_expr.X_op = O_absent;
9538 case 'c': /* 9-bit signed offset in bit 6 */
9539 my_getExpression (&imm_expr, s);
9540 check_absolute_expr (ip, &imm_expr);
9541 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9542 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9543 /* We check the offset range before adjusted. */
9546 if (imm_expr.X_add_number < min_range
9547 || imm_expr.X_add_number > max_range)
9549 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9550 (long) min_range, (long) max_range,
9551 (long) imm_expr.X_add_number);
9553 if (imm_expr.X_add_number & 0xf)
9555 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9556 (long) imm_expr.X_add_number);
9558 /* Right shift 4 bits to adjust the offset operand. */
9559 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9560 imm_expr.X_op = O_absent;
9565 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9567 if (regno == AT && mips_opts.at)
9569 if (mips_opts.at == ATREG)
9570 as_warn (_("used $at without \".set noat\""));
9572 as_warn (_("used $%u with \".set at=$%u\""),
9573 regno, mips_opts.at);
9575 INSERT_OPERAND (RZ, *ip, regno);
9579 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9581 INSERT_OPERAND (FZ, *ip, regno);
9585 as_bad (_("Internal error: bad mips opcode "
9586 "(unknown extension operand type `+%c'): %s %s"),
9587 *args, insn->name, insn->args);
9588 /* Further processing is fruitless. */
9593 case '<': /* must be at least one digit */
9595 * According to the manual, if the shift amount is greater
9596 * than 31 or less than 0, then the shift amount should be
9597 * mod 32. In reality the mips assembler issues an error.
9598 * We issue a warning and mask out all but the low 5 bits.
9600 my_getExpression (&imm_expr, s);
9601 check_absolute_expr (ip, &imm_expr);
9602 if ((unsigned long) imm_expr.X_add_number > 31)
9603 as_warn (_("Improper shift amount (%lu)"),
9604 (unsigned long) imm_expr.X_add_number);
9605 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9606 imm_expr.X_op = O_absent;
9610 case '>': /* shift amount minus 32 */
9611 my_getExpression (&imm_expr, s);
9612 check_absolute_expr (ip, &imm_expr);
9613 if ((unsigned long) imm_expr.X_add_number < 32
9614 || (unsigned long) imm_expr.X_add_number > 63)
9616 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9617 imm_expr.X_op = O_absent;
9621 case 'k': /* CACHE code. */
9622 case 'h': /* PREFX code. */
9623 case '1': /* SYNC type. */
9624 my_getExpression (&imm_expr, s);
9625 check_absolute_expr (ip, &imm_expr);
9626 if ((unsigned long) imm_expr.X_add_number > 31)
9627 as_warn (_("Invalid value for `%s' (%lu)"),
9629 (unsigned long) imm_expr.X_add_number);
9632 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9633 switch (imm_expr.X_add_number)
9642 case 31: /* These are ok. */
9645 default: /* The rest must be changed to 28. */
9646 imm_expr.X_add_number = 28;
9649 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9651 else if (*args == 'h')
9652 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9654 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9655 imm_expr.X_op = O_absent;
9659 case 'c': /* BREAK code. */
9660 my_getExpression (&imm_expr, s);
9661 check_absolute_expr (ip, &imm_expr);
9662 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9663 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9665 (unsigned long) imm_expr.X_add_number);
9666 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9667 imm_expr.X_op = O_absent;
9671 case 'q': /* Lower BREAK code. */
9672 my_getExpression (&imm_expr, s);
9673 check_absolute_expr (ip, &imm_expr);
9674 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9675 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9677 (unsigned long) imm_expr.X_add_number);
9678 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9679 imm_expr.X_op = O_absent;
9683 case 'B': /* 20-bit SYSCALL/BREAK code. */
9684 my_getExpression (&imm_expr, s);
9685 check_absolute_expr (ip, &imm_expr);
9686 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9687 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9689 (unsigned long) imm_expr.X_add_number);
9690 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9691 imm_expr.X_op = O_absent;
9695 case 'C': /* Coprocessor code. */
9696 my_getExpression (&imm_expr, s);
9697 check_absolute_expr (ip, &imm_expr);
9698 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9700 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9701 (unsigned long) imm_expr.X_add_number);
9702 imm_expr.X_add_number &= OP_MASK_COPZ;
9704 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9705 imm_expr.X_op = O_absent;
9709 case 'J': /* 19-bit WAIT code. */
9710 my_getExpression (&imm_expr, s);
9711 check_absolute_expr (ip, &imm_expr);
9712 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9714 as_warn (_("Illegal 19-bit code (%lu)"),
9715 (unsigned long) imm_expr.X_add_number);
9716 imm_expr.X_add_number &= OP_MASK_CODE19;
9718 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9719 imm_expr.X_op = O_absent;
9723 case 'P': /* Performance register. */
9724 my_getExpression (&imm_expr, s);
9725 check_absolute_expr (ip, &imm_expr);
9726 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9727 as_warn (_("Invalid performance register (%lu)"),
9728 (unsigned long) imm_expr.X_add_number);
9729 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9730 imm_expr.X_op = O_absent;
9734 case 'G': /* Coprocessor destination register. */
9735 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9736 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9738 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9739 INSERT_OPERAND (RD, *ip, regno);
9748 case 'b': /* Base register. */
9749 case 'd': /* Destination register. */
9750 case 's': /* Source register. */
9751 case 't': /* Target register. */
9752 case 'r': /* Both target and source. */
9753 case 'v': /* Both dest and source. */
9754 case 'w': /* Both dest and target. */
9755 case 'E': /* Coprocessor target register. */
9756 case 'K': /* RDHWR destination register. */
9757 case 'x': /* Ignore register name. */
9758 case 'z': /* Must be zero register. */
9759 case 'U': /* Destination register (CLO/CLZ). */
9760 case 'g': /* Coprocessor destination register. */
9762 if (*args == 'E' || *args == 'K')
9763 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9766 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9767 if (regno == AT && mips_opts.at)
9769 if (mips_opts.at == ATREG)
9770 as_warn (_("Used $at without \".set noat\""));
9772 as_warn (_("Used $%u with \".set at=$%u\""),
9773 regno, mips_opts.at);
9783 if (c == 'r' || c == 'v' || c == 'w')
9790 /* 'z' only matches $0. */
9791 if (c == 'z' && regno != 0)
9794 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9796 if (regno == lastregno)
9799 = _("Source and destination must be different");
9802 if (regno == 31 && lastregno == 0xffffffff)
9805 = _("A destination register must be supplied");
9809 /* Now that we have assembled one operand, we use the args
9810 string to figure out where it goes in the instruction. */
9817 INSERT_OPERAND (RS, *ip, regno);
9822 INSERT_OPERAND (RD, *ip, regno);
9825 INSERT_OPERAND (RD, *ip, regno);
9826 INSERT_OPERAND (RT, *ip, regno);
9831 INSERT_OPERAND (RT, *ip, regno);
9834 /* This case exists because on the r3000 trunc
9835 expands into a macro which requires a gp
9836 register. On the r6000 or r4000 it is
9837 assembled into a single instruction which
9838 ignores the register. Thus the insn version
9839 is MIPS_ISA2 and uses 'x', and the macro
9840 version is MIPS_ISA1 and uses 't'. */
9843 /* This case is for the div instruction, which
9844 acts differently if the destination argument
9845 is $0. This only matches $0, and is checked
9846 outside the switch. */
9856 INSERT_OPERAND (RS, *ip, lastregno);
9859 INSERT_OPERAND (RT, *ip, lastregno);
9864 case 'O': /* MDMX alignment immediate constant. */
9865 my_getExpression (&imm_expr, s);
9866 check_absolute_expr (ip, &imm_expr);
9867 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9868 as_warn (_("Improper align amount (%ld), using low bits"),
9869 (long) imm_expr.X_add_number);
9870 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9871 imm_expr.X_op = O_absent;
9875 case 'Q': /* MDMX vector, element sel, or const. */
9878 /* MDMX Immediate. */
9879 my_getExpression (&imm_expr, s);
9880 check_absolute_expr (ip, &imm_expr);
9881 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9882 as_warn (_("Invalid MDMX Immediate (%ld)"),
9883 (long) imm_expr.X_add_number);
9884 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9885 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9886 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9888 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9889 imm_expr.X_op = O_absent;
9893 /* Not MDMX Immediate. Fall through. */
9894 case 'X': /* MDMX destination register. */
9895 case 'Y': /* MDMX source register. */
9896 case 'Z': /* MDMX target register. */
9898 case 'D': /* Floating point destination register. */
9899 case 'S': /* Floating point source register. */
9900 case 'T': /* Floating point target register. */
9901 case 'R': /* Floating point source register. */
9906 || (mips_opts.ase_mdmx
9907 && (ip->insn_mo->pinfo & FP_D)
9908 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9909 | INSN_COPROC_MEMORY_DELAY
9910 | INSN_LOAD_COPROC_DELAY
9911 | INSN_LOAD_MEMORY_DELAY
9912 | INSN_STORE_MEMORY))))
9915 if (reg_lookup (&s, rtype, ®no))
9917 if ((regno & 1) != 0
9919 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9920 as_warn (_("Float register should be even, was %d"),
9928 if (c == 'V' || c == 'W')
9939 INSERT_OPERAND (FD, *ip, regno);
9944 INSERT_OPERAND (FS, *ip, regno);
9947 /* This is like 'Z', but also needs to fix the MDMX
9948 vector/scalar select bits. Note that the
9949 scalar immediate case is handled above. */
9952 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9953 int max_el = (is_qh ? 3 : 7);
9955 my_getExpression(&imm_expr, s);
9956 check_absolute_expr (ip, &imm_expr);
9958 if (imm_expr.X_add_number > max_el)
9959 as_bad (_("Bad element selector %ld"),
9960 (long) imm_expr.X_add_number);
9961 imm_expr.X_add_number &= max_el;
9962 ip->insn_opcode |= (imm_expr.X_add_number
9965 imm_expr.X_op = O_absent;
9967 as_warn (_("Expecting ']' found '%s'"), s);
9973 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9974 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9977 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9984 INSERT_OPERAND (FT, *ip, regno);
9987 INSERT_OPERAND (FR, *ip, regno);
9997 INSERT_OPERAND (FS, *ip, lastregno);
10000 INSERT_OPERAND (FT, *ip, lastregno);
10006 my_getExpression (&imm_expr, s);
10007 if (imm_expr.X_op != O_big
10008 && imm_expr.X_op != O_constant)
10009 insn_error = _("absolute expression required");
10010 if (HAVE_32BIT_GPRS)
10011 normalize_constant_expr (&imm_expr);
10016 my_getExpression (&offset_expr, s);
10017 normalize_address_expr (&offset_expr);
10018 *imm_reloc = BFD_RELOC_32;
10031 unsigned char temp[8];
10033 unsigned int length;
10038 /* These only appear as the last operand in an
10039 instruction, and every instruction that accepts
10040 them in any variant accepts them in all variants.
10041 This means we don't have to worry about backing out
10042 any changes if the instruction does not match.
10044 The difference between them is the size of the
10045 floating point constant and where it goes. For 'F'
10046 and 'L' the constant is 64 bits; for 'f' and 'l' it
10047 is 32 bits. Where the constant is placed is based
10048 on how the MIPS assembler does things:
10051 f -- immediate value
10054 The .lit4 and .lit8 sections are only used if
10055 permitted by the -G argument.
10057 The code below needs to know whether the target register
10058 is 32 or 64 bits wide. It relies on the fact 'f' and
10059 'F' are used with GPR-based instructions and 'l' and
10060 'L' are used with FPR-based instructions. */
10062 f64 = *args == 'F' || *args == 'L';
10063 using_gprs = *args == 'F' || *args == 'f';
10065 save_in = input_line_pointer;
10066 input_line_pointer = s;
10067 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10069 s = input_line_pointer;
10070 input_line_pointer = save_in;
10071 if (err != NULL && *err != '\0')
10073 as_bad (_("Bad floating point constant: %s"), err);
10074 memset (temp, '\0', sizeof temp);
10075 length = f64 ? 8 : 4;
10078 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10082 && (g_switch_value < 4
10083 || (temp[0] == 0 && temp[1] == 0)
10084 || (temp[2] == 0 && temp[3] == 0))))
10086 imm_expr.X_op = O_constant;
10087 if (!target_big_endian)
10088 imm_expr.X_add_number = bfd_getl32 (temp);
10090 imm_expr.X_add_number = bfd_getb32 (temp);
10092 else if (length > 4
10093 && !mips_disable_float_construction
10094 /* Constants can only be constructed in GPRs and
10095 copied to FPRs if the GPRs are at least as wide
10096 as the FPRs. Force the constant into memory if
10097 we are using 64-bit FPRs but the GPRs are only
10100 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10101 && ((temp[0] == 0 && temp[1] == 0)
10102 || (temp[2] == 0 && temp[3] == 0))
10103 && ((temp[4] == 0 && temp[5] == 0)
10104 || (temp[6] == 0 && temp[7] == 0)))
10106 /* The value is simple enough to load with a couple of
10107 instructions. If using 32-bit registers, set
10108 imm_expr to the high order 32 bits and offset_expr to
10109 the low order 32 bits. Otherwise, set imm_expr to
10110 the entire 64 bit constant. */
10111 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10113 imm_expr.X_op = O_constant;
10114 offset_expr.X_op = O_constant;
10115 if (!target_big_endian)
10117 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10118 offset_expr.X_add_number = bfd_getl32 (temp);
10122 imm_expr.X_add_number = bfd_getb32 (temp);
10123 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10125 if (offset_expr.X_add_number == 0)
10126 offset_expr.X_op = O_absent;
10128 else if (sizeof (imm_expr.X_add_number) > 4)
10130 imm_expr.X_op = O_constant;
10131 if (!target_big_endian)
10132 imm_expr.X_add_number = bfd_getl64 (temp);
10134 imm_expr.X_add_number = bfd_getb64 (temp);
10138 imm_expr.X_op = O_big;
10139 imm_expr.X_add_number = 4;
10140 if (!target_big_endian)
10142 generic_bignum[0] = bfd_getl16 (temp);
10143 generic_bignum[1] = bfd_getl16 (temp + 2);
10144 generic_bignum[2] = bfd_getl16 (temp + 4);
10145 generic_bignum[3] = bfd_getl16 (temp + 6);
10149 generic_bignum[0] = bfd_getb16 (temp + 6);
10150 generic_bignum[1] = bfd_getb16 (temp + 4);
10151 generic_bignum[2] = bfd_getb16 (temp + 2);
10152 generic_bignum[3] = bfd_getb16 (temp);
10158 const char *newname;
10161 /* Switch to the right section. */
10163 subseg = now_subseg;
10166 default: /* unused default case avoids warnings. */
10168 newname = RDATA_SECTION_NAME;
10169 if (g_switch_value >= 8)
10173 newname = RDATA_SECTION_NAME;
10176 gas_assert (g_switch_value >= 4);
10180 new_seg = subseg_new (newname, (subsegT) 0);
10182 bfd_set_section_flags (stdoutput, new_seg,
10187 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10188 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10189 record_alignment (new_seg, 4);
10191 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10192 if (seg == now_seg)
10193 as_bad (_("Can't use floating point insn in this section"));
10195 /* Set the argument to the current address in the
10197 offset_expr.X_op = O_symbol;
10198 offset_expr.X_add_symbol = symbol_temp_new_now ();
10199 offset_expr.X_add_number = 0;
10201 /* Put the floating point number into the section. */
10202 p = frag_more ((int) length);
10203 memcpy (p, temp, length);
10205 /* Switch back to the original section. */
10206 subseg_set (seg, subseg);
10211 case 'i': /* 16-bit unsigned immediate. */
10212 case 'j': /* 16-bit signed immediate. */
10213 *imm_reloc = BFD_RELOC_LO16;
10214 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10217 offsetT minval, maxval;
10219 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10220 && strcmp (insn->name, insn[1].name) == 0);
10222 /* If the expression was written as an unsigned number,
10223 only treat it as signed if there are no more
10227 && sizeof (imm_expr.X_add_number) <= 4
10228 && imm_expr.X_op == O_constant
10229 && imm_expr.X_add_number < 0
10230 && imm_expr.X_unsigned
10231 && HAVE_64BIT_GPRS)
10234 /* For compatibility with older assemblers, we accept
10235 0x8000-0xffff as signed 16-bit numbers when only
10236 signed numbers are allowed. */
10238 minval = 0, maxval = 0xffff;
10240 minval = -0x8000, maxval = 0x7fff;
10242 minval = -0x8000, maxval = 0xffff;
10244 if (imm_expr.X_op != O_constant
10245 || imm_expr.X_add_number < minval
10246 || imm_expr.X_add_number > maxval)
10250 if (imm_expr.X_op == O_constant
10251 || imm_expr.X_op == O_big)
10252 as_bad (_("Expression out of range"));
10258 case 'o': /* 16-bit offset. */
10259 offset_reloc[0] = BFD_RELOC_LO16;
10260 offset_reloc[1] = BFD_RELOC_UNUSED;
10261 offset_reloc[2] = BFD_RELOC_UNUSED;
10263 /* Check whether there is only a single bracketed expression
10264 left. If so, it must be the base register and the
10265 constant must be zero. */
10266 if (*s == '(' && strchr (s + 1, '(') == 0)
10268 offset_expr.X_op = O_constant;
10269 offset_expr.X_add_number = 0;
10273 /* If this value won't fit into a 16 bit offset, then go
10274 find a macro that will generate the 32 bit offset
10276 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10277 && (offset_expr.X_op != O_constant
10278 || offset_expr.X_add_number >= 0x8000
10279 || offset_expr.X_add_number < -0x8000))
10285 case 'p': /* PC-relative offset. */
10286 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10287 my_getExpression (&offset_expr, s);
10291 case 'u': /* Upper 16 bits. */
10292 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10293 && imm_expr.X_op == O_constant
10294 && (imm_expr.X_add_number < 0
10295 || imm_expr.X_add_number >= 0x10000))
10296 as_bad (_("lui expression (%lu) not in range 0..65535"),
10297 (unsigned long) imm_expr.X_add_number);
10301 case 'a': /* 26-bit address. */
10302 my_getExpression (&offset_expr, s);
10304 *offset_reloc = BFD_RELOC_MIPS_JMP;
10307 case 'N': /* 3-bit branch condition code. */
10308 case 'M': /* 3-bit compare condition code. */
10310 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10311 rtype |= RTYPE_FCC;
10312 if (!reg_lookup (&s, rtype, ®no))
10314 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10315 || strcmp (str + strlen (str) - 5, "any2f") == 0
10316 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10317 && (regno & 1) != 0)
10318 as_warn (_("Condition code register should be even for %s, "
10321 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10322 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10323 && (regno & 3) != 0)
10324 as_warn (_("Condition code register should be 0 or 4 for %s, "
10328 INSERT_OPERAND (BCC, *ip, regno);
10330 INSERT_OPERAND (CCC, *ip, regno);
10334 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10345 while (ISDIGIT (*s));
10348 c = 8; /* Invalid sel value. */
10351 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10352 ip->insn_opcode |= c;
10356 /* Must be at least one digit. */
10357 my_getExpression (&imm_expr, s);
10358 check_absolute_expr (ip, &imm_expr);
10360 if ((unsigned long) imm_expr.X_add_number
10361 > (unsigned long) OP_MASK_VECBYTE)
10363 as_bad (_("bad byte vector index (%ld)"),
10364 (long) imm_expr.X_add_number);
10365 imm_expr.X_add_number = 0;
10368 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10369 imm_expr.X_op = O_absent;
10374 my_getExpression (&imm_expr, s);
10375 check_absolute_expr (ip, &imm_expr);
10377 if ((unsigned long) imm_expr.X_add_number
10378 > (unsigned long) OP_MASK_VECALIGN)
10380 as_bad (_("bad byte vector index (%ld)"),
10381 (long) imm_expr.X_add_number);
10382 imm_expr.X_add_number = 0;
10385 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10386 imm_expr.X_op = O_absent;
10391 as_bad (_("Bad char = '%c'\n"), *args);
10396 /* Args don't match. */
10397 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10398 !strcmp (insn->name, insn[1].name))
10402 insn_error = _("Illegal operands");
10406 *(--argsStart) = save_c;
10407 insn_error = _("Illegal operands");
10412 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10414 /* This routine assembles an instruction into its binary format when
10415 assembling for the mips16. As a side effect, it sets one of the
10416 global variables imm_reloc or offset_reloc to the type of
10417 relocation to do if one of the operands is an address expression.
10418 It also sets mips16_small and mips16_ext if the user explicitly
10419 requested a small or extended instruction. */
10422 mips16_ip (char *str, struct mips_cl_insn *ip)
10426 struct mips_opcode *insn;
10428 unsigned int regno;
10429 unsigned int lastregno = 0;
10435 mips16_small = FALSE;
10436 mips16_ext = FALSE;
10438 for (s = str; ISLOWER (*s); ++s)
10450 if (s[1] == 't' && s[2] == ' ')
10453 mips16_small = TRUE;
10457 else if (s[1] == 'e' && s[2] == ' ')
10464 /* Fall through. */
10466 insn_error = _("unknown opcode");
10470 if (mips_opts.noautoextend && ! mips16_ext)
10471 mips16_small = TRUE;
10473 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10475 insn_error = _("unrecognized opcode");
10484 gas_assert (strcmp (insn->name, str) == 0);
10486 ok = is_opcode_valid_16 (insn);
10489 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10490 && strcmp (insn->name, insn[1].name) == 0)
10499 static char buf[100];
10501 _("opcode not supported on this processor: %s (%s)"),
10502 mips_cpu_info_from_arch (mips_opts.arch)->name,
10503 mips_cpu_info_from_isa (mips_opts.isa)->name);
10510 create_insn (ip, insn);
10511 imm_expr.X_op = O_absent;
10512 imm_reloc[0] = BFD_RELOC_UNUSED;
10513 imm_reloc[1] = BFD_RELOC_UNUSED;
10514 imm_reloc[2] = BFD_RELOC_UNUSED;
10515 imm2_expr.X_op = O_absent;
10516 offset_expr.X_op = O_absent;
10517 offset_reloc[0] = BFD_RELOC_UNUSED;
10518 offset_reloc[1] = BFD_RELOC_UNUSED;
10519 offset_reloc[2] = BFD_RELOC_UNUSED;
10520 for (args = insn->args; 1; ++args)
10527 /* In this switch statement we call break if we did not find
10528 a match, continue if we did find a match, or return if we
10537 /* Stuff the immediate value in now, if we can. */
10538 if (imm_expr.X_op == O_constant
10539 && *imm_reloc > BFD_RELOC_UNUSED
10540 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10541 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10542 && insn->pinfo != INSN_MACRO)
10546 switch (*offset_reloc)
10548 case BFD_RELOC_MIPS16_HI16_S:
10549 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10552 case BFD_RELOC_MIPS16_HI16:
10553 tmp = imm_expr.X_add_number >> 16;
10556 case BFD_RELOC_MIPS16_LO16:
10557 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10561 case BFD_RELOC_UNUSED:
10562 tmp = imm_expr.X_add_number;
10568 *offset_reloc = BFD_RELOC_UNUSED;
10570 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10571 tmp, TRUE, mips16_small,
10572 mips16_ext, &ip->insn_opcode,
10573 &ip->use_extend, &ip->extend);
10574 imm_expr.X_op = O_absent;
10575 *imm_reloc = BFD_RELOC_UNUSED;
10589 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10592 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10608 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10610 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10614 /* Fall through. */
10625 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10627 if (c == 'v' || c == 'w')
10630 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10632 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10643 if (c == 'v' || c == 'w')
10645 regno = mips16_to_32_reg_map[lastregno];
10659 regno = mips32_to_16_reg_map[regno];
10664 regno = ILLEGAL_REG;
10669 regno = ILLEGAL_REG;
10674 regno = ILLEGAL_REG;
10679 if (regno == AT && mips_opts.at)
10681 if (mips_opts.at == ATREG)
10682 as_warn (_("used $at without \".set noat\""));
10684 as_warn (_("used $%u with \".set at=$%u\""),
10685 regno, mips_opts.at);
10693 if (regno == ILLEGAL_REG)
10700 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10704 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10707 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10710 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10716 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10719 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10720 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10730 if (strncmp (s, "$pc", 3) == 0)
10747 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10750 if (imm_expr.X_op != O_constant)
10753 ip->use_extend = TRUE;
10758 /* We need to relax this instruction. */
10759 *offset_reloc = *imm_reloc;
10760 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10765 *imm_reloc = BFD_RELOC_UNUSED;
10766 /* Fall through. */
10773 my_getExpression (&imm_expr, s);
10774 if (imm_expr.X_op == O_register)
10776 /* What we thought was an expression turned out to
10779 if (s[0] == '(' && args[1] == '(')
10781 /* It looks like the expression was omitted
10782 before a register indirection, which means
10783 that the expression is implicitly zero. We
10784 still set up imm_expr, so that we handle
10785 explicit extensions correctly. */
10786 imm_expr.X_op = O_constant;
10787 imm_expr.X_add_number = 0;
10788 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10795 /* We need to relax this instruction. */
10796 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10805 /* We use offset_reloc rather than imm_reloc for the PC
10806 relative operands. This lets macros with both
10807 immediate and address operands work correctly. */
10808 my_getExpression (&offset_expr, s);
10810 if (offset_expr.X_op == O_register)
10813 /* We need to relax this instruction. */
10814 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10818 case '6': /* break code */
10819 my_getExpression (&imm_expr, s);
10820 check_absolute_expr (ip, &imm_expr);
10821 if ((unsigned long) imm_expr.X_add_number > 63)
10822 as_warn (_("Invalid value for `%s' (%lu)"),
10824 (unsigned long) imm_expr.X_add_number);
10825 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10826 imm_expr.X_op = O_absent;
10830 case 'a': /* 26 bit address */
10831 my_getExpression (&offset_expr, s);
10833 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10834 ip->insn_opcode <<= 16;
10837 case 'l': /* register list for entry macro */
10838 case 'L': /* register list for exit macro */
10848 unsigned int freg, reg1, reg2;
10850 while (*s == ' ' || *s == ',')
10852 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10854 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10858 as_bad (_("can't parse register list"));
10868 if (!reg_lookup (&s, freg ? RTYPE_FPU
10869 : (RTYPE_GP | RTYPE_NUM), ®2))
10871 as_bad (_("invalid register list"));
10875 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10877 mask &= ~ (7 << 3);
10880 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10882 mask &= ~ (7 << 3);
10885 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10886 mask |= (reg2 - 3) << 3;
10887 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10888 mask |= (reg2 - 15) << 1;
10889 else if (reg1 == RA && reg2 == RA)
10893 as_bad (_("invalid register list"));
10897 /* The mask is filled in in the opcode table for the
10898 benefit of the disassembler. We remove it before
10899 applying the actual mask. */
10900 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10901 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10905 case 'm': /* Register list for save insn. */
10906 case 'M': /* Register list for restore insn. */
10909 int framesz = 0, seen_framesz = 0;
10910 int nargs = 0, statics = 0, sregs = 0;
10914 unsigned int reg1, reg2;
10916 SKIP_SPACE_TABS (s);
10919 SKIP_SPACE_TABS (s);
10921 my_getExpression (&imm_expr, s);
10922 if (imm_expr.X_op == O_constant)
10924 /* Handle the frame size. */
10927 as_bad (_("more than one frame size in list"));
10931 framesz = imm_expr.X_add_number;
10932 imm_expr.X_op = O_absent;
10937 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10939 as_bad (_("can't parse register list"));
10951 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10954 as_bad (_("can't parse register list"));
10959 while (reg1 <= reg2)
10961 if (reg1 >= 4 && reg1 <= 7)
10965 nargs |= 1 << (reg1 - 4);
10967 /* statics $a0-$a3 */
10968 statics |= 1 << (reg1 - 4);
10970 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10973 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10975 else if (reg1 == 31)
10977 /* Add $ra to insn. */
10982 as_bad (_("unexpected register in list"));
10990 /* Encode args/statics combination. */
10991 if (nargs & statics)
10992 as_bad (_("arg/static registers overlap"));
10993 else if (nargs == 0xf)
10994 /* All $a0-$a3 are args. */
10995 opcode |= MIPS16_ALL_ARGS << 16;
10996 else if (statics == 0xf)
10997 /* All $a0-$a3 are statics. */
10998 opcode |= MIPS16_ALL_STATICS << 16;
11001 int narg = 0, nstat = 0;
11003 /* Count arg registers. */
11004 while (nargs & 0x1)
11010 as_bad (_("invalid arg register list"));
11012 /* Count static registers. */
11013 while (statics & 0x8)
11015 statics = (statics << 1) & 0xf;
11019 as_bad (_("invalid static register list"));
11021 /* Encode args/statics. */
11022 opcode |= ((narg << 2) | nstat) << 16;
11025 /* Encode $s0/$s1. */
11026 if (sregs & (1 << 0)) /* $s0 */
11028 if (sregs & (1 << 1)) /* $s1 */
11034 /* Count regs $s2-$s8. */
11042 as_bad (_("invalid static register list"));
11043 /* Encode $s2-$s8. */
11044 opcode |= nsreg << 24;
11047 /* Encode frame size. */
11049 as_bad (_("missing frame size"));
11050 else if ((framesz & 7) != 0 || framesz < 0
11051 || framesz > 0xff * 8)
11052 as_bad (_("invalid frame size"));
11053 else if (framesz != 128 || (opcode >> 16) != 0)
11056 opcode |= (((framesz & 0xf0) << 16)
11057 | (framesz & 0x0f));
11060 /* Finally build the instruction. */
11061 if ((opcode >> 16) != 0 || framesz == 0)
11063 ip->use_extend = TRUE;
11064 ip->extend = opcode >> 16;
11066 ip->insn_opcode |= opcode & 0x7f;
11070 case 'e': /* extend code */
11071 my_getExpression (&imm_expr, s);
11072 check_absolute_expr (ip, &imm_expr);
11073 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11075 as_warn (_("Invalid value for `%s' (%lu)"),
11077 (unsigned long) imm_expr.X_add_number);
11078 imm_expr.X_add_number &= 0x7ff;
11080 ip->insn_opcode |= imm_expr.X_add_number;
11081 imm_expr.X_op = O_absent;
11091 /* Args don't match. */
11092 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11093 strcmp (insn->name, insn[1].name) == 0)
11100 insn_error = _("illegal operands");
11106 /* This structure holds information we know about a mips16 immediate
11109 struct mips16_immed_operand
11111 /* The type code used in the argument string in the opcode table. */
11113 /* The number of bits in the short form of the opcode. */
11115 /* The number of bits in the extended form of the opcode. */
11117 /* The amount by which the short form is shifted when it is used;
11118 for example, the sw instruction has a shift count of 2. */
11120 /* The amount by which the short form is shifted when it is stored
11121 into the instruction code. */
11123 /* Non-zero if the short form is unsigned. */
11125 /* Non-zero if the extended form is unsigned. */
11127 /* Non-zero if the value is PC relative. */
11131 /* The mips16 immediate operand types. */
11133 static const struct mips16_immed_operand mips16_immed_operands[] =
11135 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11136 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11137 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11138 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11139 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11140 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11141 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11142 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11143 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11144 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11145 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11146 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11147 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11148 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11149 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11150 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11151 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11152 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11153 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11154 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11155 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11158 #define MIPS16_NUM_IMMED \
11159 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11161 /* Handle a mips16 instruction with an immediate value. This or's the
11162 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11163 whether an extended value is needed; if one is needed, it sets
11164 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11165 If SMALL is true, an unextended opcode was explicitly requested.
11166 If EXT is true, an extended opcode was explicitly requested. If
11167 WARN is true, warn if EXT does not match reality. */
11170 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11171 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11172 unsigned long *insn, bfd_boolean *use_extend,
11173 unsigned short *extend)
11175 const struct mips16_immed_operand *op;
11176 int mintiny, maxtiny;
11177 bfd_boolean needext;
11179 op = mips16_immed_operands;
11180 while (op->type != type)
11183 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11188 if (type == '<' || type == '>' || type == '[' || type == ']')
11191 maxtiny = 1 << op->nbits;
11196 maxtiny = (1 << op->nbits) - 1;
11201 mintiny = - (1 << (op->nbits - 1));
11202 maxtiny = (1 << (op->nbits - 1)) - 1;
11205 /* Branch offsets have an implicit 0 in the lowest bit. */
11206 if (type == 'p' || type == 'q')
11209 if ((val & ((1 << op->shift) - 1)) != 0
11210 || val < (mintiny << op->shift)
11211 || val > (maxtiny << op->shift))
11216 if (warn && ext && ! needext)
11217 as_warn_where (file, line,
11218 _("extended operand requested but not required"));
11219 if (small && needext)
11220 as_bad_where (file, line, _("invalid unextended operand value"));
11222 if (small || (! ext && ! needext))
11226 *use_extend = FALSE;
11227 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11228 insnval <<= op->op_shift;
11233 long minext, maxext;
11239 maxext = (1 << op->extbits) - 1;
11243 minext = - (1 << (op->extbits - 1));
11244 maxext = (1 << (op->extbits - 1)) - 1;
11246 if (val < minext || val > maxext)
11247 as_bad_where (file, line,
11248 _("operand value out of range for instruction"));
11250 *use_extend = TRUE;
11251 if (op->extbits == 16)
11253 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11256 else if (op->extbits == 15)
11258 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11263 extval = ((val & 0x1f) << 6) | (val & 0x20);
11267 *extend = (unsigned short) extval;
11272 struct percent_op_match
11275 bfd_reloc_code_real_type reloc;
11278 static const struct percent_op_match mips_percent_op[] =
11280 {"%lo", BFD_RELOC_LO16},
11282 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11283 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11284 {"%call16", BFD_RELOC_MIPS_CALL16},
11285 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11286 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11287 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11288 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11289 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11290 {"%got", BFD_RELOC_MIPS_GOT16},
11291 {"%gp_rel", BFD_RELOC_GPREL16},
11292 {"%half", BFD_RELOC_16},
11293 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11294 {"%higher", BFD_RELOC_MIPS_HIGHER},
11295 {"%neg", BFD_RELOC_MIPS_SUB},
11296 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11297 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11298 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11299 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11300 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11301 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11302 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11304 {"%hi", BFD_RELOC_HI16_S}
11307 static const struct percent_op_match mips16_percent_op[] =
11309 {"%lo", BFD_RELOC_MIPS16_LO16},
11310 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11311 {"%got", BFD_RELOC_MIPS16_GOT16},
11312 {"%call16", BFD_RELOC_MIPS16_CALL16},
11313 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11317 /* Return true if *STR points to a relocation operator. When returning true,
11318 move *STR over the operator and store its relocation code in *RELOC.
11319 Leave both *STR and *RELOC alone when returning false. */
11322 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11324 const struct percent_op_match *percent_op;
11327 if (mips_opts.mips16)
11329 percent_op = mips16_percent_op;
11330 limit = ARRAY_SIZE (mips16_percent_op);
11334 percent_op = mips_percent_op;
11335 limit = ARRAY_SIZE (mips_percent_op);
11338 for (i = 0; i < limit; i++)
11339 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11341 int len = strlen (percent_op[i].str);
11343 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11346 *str += strlen (percent_op[i].str);
11347 *reloc = percent_op[i].reloc;
11349 /* Check whether the output BFD supports this relocation.
11350 If not, issue an error and fall back on something safe. */
11351 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11353 as_bad (_("relocation %s isn't supported by the current ABI"),
11354 percent_op[i].str);
11355 *reloc = BFD_RELOC_UNUSED;
11363 /* Parse string STR as a 16-bit relocatable operand. Store the
11364 expression in *EP and the relocations in the array starting
11365 at RELOC. Return the number of relocation operators used.
11367 On exit, EXPR_END points to the first character after the expression. */
11370 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11373 bfd_reloc_code_real_type reversed_reloc[3];
11374 size_t reloc_index, i;
11375 int crux_depth, str_depth;
11378 /* Search for the start of the main expression, recoding relocations
11379 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11380 of the main expression and with CRUX_DEPTH containing the number
11381 of open brackets at that point. */
11388 crux_depth = str_depth;
11390 /* Skip over whitespace and brackets, keeping count of the number
11392 while (*str == ' ' || *str == '\t' || *str == '(')
11397 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11398 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11400 my_getExpression (ep, crux);
11403 /* Match every open bracket. */
11404 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11408 if (crux_depth > 0)
11409 as_bad (_("unclosed '('"));
11413 if (reloc_index != 0)
11415 prev_reloc_op_frag = frag_now;
11416 for (i = 0; i < reloc_index; i++)
11417 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11420 return reloc_index;
11424 my_getExpression (expressionS *ep, char *str)
11428 save_in = input_line_pointer;
11429 input_line_pointer = str;
11431 expr_end = input_line_pointer;
11432 input_line_pointer = save_in;
11436 md_atof (int type, char *litP, int *sizeP)
11438 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11442 md_number_to_chars (char *buf, valueT val, int n)
11444 if (target_big_endian)
11445 number_to_chars_bigendian (buf, val, n);
11447 number_to_chars_littleendian (buf, val, n);
11451 static int support_64bit_objects(void)
11453 const char **list, **l;
11456 list = bfd_target_list ();
11457 for (l = list; *l != NULL; l++)
11458 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11459 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11461 yes = (*l != NULL);
11465 #endif /* OBJ_ELF */
11467 const char *md_shortopts = "O::g::G:";
11471 OPTION_MARCH = OPTION_MD_BASE,
11493 OPTION_NO_SMARTMIPS,
11496 OPTION_COMPAT_ARCH_BASE,
11505 OPTION_M7000_HILO_FIX,
11506 OPTION_MNO_7000_HILO_FIX,
11509 OPTION_FIX_LOONGSON2F_JUMP,
11510 OPTION_NO_FIX_LOONGSON2F_JUMP,
11511 OPTION_FIX_LOONGSON2F_NOP,
11512 OPTION_NO_FIX_LOONGSON2F_NOP,
11514 OPTION_NO_FIX_VR4120,
11516 OPTION_NO_FIX_VR4130,
11517 OPTION_FIX_CN63XXP1,
11518 OPTION_NO_FIX_CN63XXP1,
11525 OPTION_CONSTRUCT_FLOATS,
11526 OPTION_NO_CONSTRUCT_FLOATS,
11529 OPTION_RELAX_BRANCH,
11530 OPTION_NO_RELAX_BRANCH,
11537 OPTION_SINGLE_FLOAT,
11538 OPTION_DOUBLE_FLOAT,
11541 OPTION_CALL_SHARED,
11542 OPTION_CALL_NONPIC,
11552 OPTION_MVXWORKS_PIC,
11553 #endif /* OBJ_ELF */
11557 struct option md_longopts[] =
11559 /* Options which specify architecture. */
11560 {"march", required_argument, NULL, OPTION_MARCH},
11561 {"mtune", required_argument, NULL, OPTION_MTUNE},
11562 {"mips0", no_argument, NULL, OPTION_MIPS1},
11563 {"mips1", no_argument, NULL, OPTION_MIPS1},
11564 {"mips2", no_argument, NULL, OPTION_MIPS2},
11565 {"mips3", no_argument, NULL, OPTION_MIPS3},
11566 {"mips4", no_argument, NULL, OPTION_MIPS4},
11567 {"mips5", no_argument, NULL, OPTION_MIPS5},
11568 {"mips32", no_argument, NULL, OPTION_MIPS32},
11569 {"mips64", no_argument, NULL, OPTION_MIPS64},
11570 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11571 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11573 /* Options which specify Application Specific Extensions (ASEs). */
11574 {"mips16", no_argument, NULL, OPTION_MIPS16},
11575 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11576 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11577 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11578 {"mdmx", no_argument, NULL, OPTION_MDMX},
11579 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11580 {"mdsp", no_argument, NULL, OPTION_DSP},
11581 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11582 {"mmt", no_argument, NULL, OPTION_MT},
11583 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11584 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11585 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11586 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11587 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11589 /* Old-style architecture options. Don't add more of these. */
11590 {"m4650", no_argument, NULL, OPTION_M4650},
11591 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11592 {"m4010", no_argument, NULL, OPTION_M4010},
11593 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11594 {"m4100", no_argument, NULL, OPTION_M4100},
11595 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11596 {"m3900", no_argument, NULL, OPTION_M3900},
11597 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11599 /* Options which enable bug fixes. */
11600 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11601 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11602 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11603 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11604 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11605 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11606 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11607 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11608 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11609 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11610 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11611 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11612 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11613 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11614 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11616 /* Miscellaneous options. */
11617 {"trap", no_argument, NULL, OPTION_TRAP},
11618 {"no-break", no_argument, NULL, OPTION_TRAP},
11619 {"break", no_argument, NULL, OPTION_BREAK},
11620 {"no-trap", no_argument, NULL, OPTION_BREAK},
11621 {"EB", no_argument, NULL, OPTION_EB},
11622 {"EL", no_argument, NULL, OPTION_EL},
11623 {"mfp32", no_argument, NULL, OPTION_FP32},
11624 {"mgp32", no_argument, NULL, OPTION_GP32},
11625 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11626 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11627 {"mfp64", no_argument, NULL, OPTION_FP64},
11628 {"mgp64", no_argument, NULL, OPTION_GP64},
11629 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11630 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11631 {"mshared", no_argument, NULL, OPTION_MSHARED},
11632 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11633 {"msym32", no_argument, NULL, OPTION_MSYM32},
11634 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11635 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11636 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11637 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11638 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11640 /* Strictly speaking this next option is ELF specific,
11641 but we allow it for other ports as well in order to
11642 make testing easier. */
11643 {"32", no_argument, NULL, OPTION_32},
11645 /* ELF-specific options. */
11647 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11648 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11649 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11650 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11651 {"xgot", no_argument, NULL, OPTION_XGOT},
11652 {"mabi", required_argument, NULL, OPTION_MABI},
11653 {"n32", no_argument, NULL, OPTION_N32},
11654 {"64", no_argument, NULL, OPTION_64},
11655 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11656 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11657 {"mpdr", no_argument, NULL, OPTION_PDR},
11658 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11659 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11660 #endif /* OBJ_ELF */
11662 {NULL, no_argument, NULL, 0}
11664 size_t md_longopts_size = sizeof (md_longopts);
11666 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11667 NEW_VALUE. Warn if another value was already specified. Note:
11668 we have to defer parsing the -march and -mtune arguments in order
11669 to handle 'from-abi' correctly, since the ABI might be specified
11670 in a later argument. */
11673 mips_set_option_string (const char **string_ptr, const char *new_value)
11675 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11676 as_warn (_("A different %s was already specified, is now %s"),
11677 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11680 *string_ptr = new_value;
11684 md_parse_option (int c, char *arg)
11688 case OPTION_CONSTRUCT_FLOATS:
11689 mips_disable_float_construction = 0;
11692 case OPTION_NO_CONSTRUCT_FLOATS:
11693 mips_disable_float_construction = 1;
11705 target_big_endian = 1;
11709 target_big_endian = 0;
11715 else if (arg[0] == '0')
11717 else if (arg[0] == '1')
11727 mips_debug = atoi (arg);
11731 file_mips_isa = ISA_MIPS1;
11735 file_mips_isa = ISA_MIPS2;
11739 file_mips_isa = ISA_MIPS3;
11743 file_mips_isa = ISA_MIPS4;
11747 file_mips_isa = ISA_MIPS5;
11750 case OPTION_MIPS32:
11751 file_mips_isa = ISA_MIPS32;
11754 case OPTION_MIPS32R2:
11755 file_mips_isa = ISA_MIPS32R2;
11758 case OPTION_MIPS64R2:
11759 file_mips_isa = ISA_MIPS64R2;
11762 case OPTION_MIPS64:
11763 file_mips_isa = ISA_MIPS64;
11767 mips_set_option_string (&mips_tune_string, arg);
11771 mips_set_option_string (&mips_arch_string, arg);
11775 mips_set_option_string (&mips_arch_string, "4650");
11776 mips_set_option_string (&mips_tune_string, "4650");
11779 case OPTION_NO_M4650:
11783 mips_set_option_string (&mips_arch_string, "4010");
11784 mips_set_option_string (&mips_tune_string, "4010");
11787 case OPTION_NO_M4010:
11791 mips_set_option_string (&mips_arch_string, "4100");
11792 mips_set_option_string (&mips_tune_string, "4100");
11795 case OPTION_NO_M4100:
11799 mips_set_option_string (&mips_arch_string, "3900");
11800 mips_set_option_string (&mips_tune_string, "3900");
11803 case OPTION_NO_M3900:
11807 mips_opts.ase_mdmx = 1;
11810 case OPTION_NO_MDMX:
11811 mips_opts.ase_mdmx = 0;
11815 mips_opts.ase_dsp = 1;
11816 mips_opts.ase_dspr2 = 0;
11819 case OPTION_NO_DSP:
11820 mips_opts.ase_dsp = 0;
11821 mips_opts.ase_dspr2 = 0;
11825 mips_opts.ase_dspr2 = 1;
11826 mips_opts.ase_dsp = 1;
11829 case OPTION_NO_DSPR2:
11830 mips_opts.ase_dspr2 = 0;
11831 mips_opts.ase_dsp = 0;
11835 mips_opts.ase_mt = 1;
11839 mips_opts.ase_mt = 0;
11842 case OPTION_MIPS16:
11843 mips_opts.mips16 = 1;
11844 mips_no_prev_insn ();
11847 case OPTION_NO_MIPS16:
11848 mips_opts.mips16 = 0;
11849 mips_no_prev_insn ();
11852 case OPTION_MIPS3D:
11853 mips_opts.ase_mips3d = 1;
11856 case OPTION_NO_MIPS3D:
11857 mips_opts.ase_mips3d = 0;
11860 case OPTION_SMARTMIPS:
11861 mips_opts.ase_smartmips = 1;
11864 case OPTION_NO_SMARTMIPS:
11865 mips_opts.ase_smartmips = 0;
11868 case OPTION_FIX_24K:
11872 case OPTION_NO_FIX_24K:
11876 case OPTION_FIX_LOONGSON2F_JUMP:
11877 mips_fix_loongson2f_jump = TRUE;
11880 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11881 mips_fix_loongson2f_jump = FALSE;
11884 case OPTION_FIX_LOONGSON2F_NOP:
11885 mips_fix_loongson2f_nop = TRUE;
11888 case OPTION_NO_FIX_LOONGSON2F_NOP:
11889 mips_fix_loongson2f_nop = FALSE;
11892 case OPTION_FIX_VR4120:
11893 mips_fix_vr4120 = 1;
11896 case OPTION_NO_FIX_VR4120:
11897 mips_fix_vr4120 = 0;
11900 case OPTION_FIX_VR4130:
11901 mips_fix_vr4130 = 1;
11904 case OPTION_NO_FIX_VR4130:
11905 mips_fix_vr4130 = 0;
11908 case OPTION_FIX_CN63XXP1:
11909 mips_fix_cn63xxp1 = TRUE;
11912 case OPTION_NO_FIX_CN63XXP1:
11913 mips_fix_cn63xxp1 = FALSE;
11916 case OPTION_RELAX_BRANCH:
11917 mips_relax_branch = 1;
11920 case OPTION_NO_RELAX_BRANCH:
11921 mips_relax_branch = 0;
11924 case OPTION_MSHARED:
11925 mips_in_shared = TRUE;
11928 case OPTION_MNO_SHARED:
11929 mips_in_shared = FALSE;
11932 case OPTION_MSYM32:
11933 mips_opts.sym32 = TRUE;
11936 case OPTION_MNO_SYM32:
11937 mips_opts.sym32 = FALSE;
11941 /* When generating ELF code, we permit -KPIC and -call_shared to
11942 select SVR4_PIC, and -non_shared to select no PIC. This is
11943 intended to be compatible with Irix 5. */
11944 case OPTION_CALL_SHARED:
11947 as_bad (_("-call_shared is supported only for ELF format"));
11950 mips_pic = SVR4_PIC;
11951 mips_abicalls = TRUE;
11954 case OPTION_CALL_NONPIC:
11957 as_bad (_("-call_nonpic is supported only for ELF format"));
11961 mips_abicalls = TRUE;
11964 case OPTION_NON_SHARED:
11967 as_bad (_("-non_shared is supported only for ELF format"));
11971 mips_abicalls = FALSE;
11974 /* The -xgot option tells the assembler to use 32 bit offsets
11975 when accessing the got in SVR4_PIC mode. It is for Irix
11980 #endif /* OBJ_ELF */
11983 g_switch_value = atoi (arg);
11987 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11991 mips_abi = O32_ABI;
11992 /* We silently ignore -32 for non-ELF targets. This greatly
11993 simplifies the construction of the MIPS GAS test cases. */
12000 as_bad (_("-n32 is supported for ELF format only"));
12003 mips_abi = N32_ABI;
12009 as_bad (_("-64 is supported for ELF format only"));
12012 mips_abi = N64_ABI;
12013 if (!support_64bit_objects())
12014 as_fatal (_("No compiled in support for 64 bit object file format"));
12016 #endif /* OBJ_ELF */
12019 file_mips_gp32 = 1;
12023 file_mips_gp32 = 0;
12027 file_mips_fp32 = 1;
12031 file_mips_fp32 = 0;
12034 case OPTION_SINGLE_FLOAT:
12035 file_mips_single_float = 1;
12038 case OPTION_DOUBLE_FLOAT:
12039 file_mips_single_float = 0;
12042 case OPTION_SOFT_FLOAT:
12043 file_mips_soft_float = 1;
12046 case OPTION_HARD_FLOAT:
12047 file_mips_soft_float = 0;
12054 as_bad (_("-mabi is supported for ELF format only"));
12057 if (strcmp (arg, "32") == 0)
12058 mips_abi = O32_ABI;
12059 else if (strcmp (arg, "o64") == 0)
12060 mips_abi = O64_ABI;
12061 else if (strcmp (arg, "n32") == 0)
12062 mips_abi = N32_ABI;
12063 else if (strcmp (arg, "64") == 0)
12065 mips_abi = N64_ABI;
12066 if (! support_64bit_objects())
12067 as_fatal (_("No compiled in support for 64 bit object file "
12070 else if (strcmp (arg, "eabi") == 0)
12071 mips_abi = EABI_ABI;
12074 as_fatal (_("invalid abi -mabi=%s"), arg);
12078 #endif /* OBJ_ELF */
12080 case OPTION_M7000_HILO_FIX:
12081 mips_7000_hilo_fix = TRUE;
12084 case OPTION_MNO_7000_HILO_FIX:
12085 mips_7000_hilo_fix = FALSE;
12089 case OPTION_MDEBUG:
12090 mips_flag_mdebug = TRUE;
12093 case OPTION_NO_MDEBUG:
12094 mips_flag_mdebug = FALSE;
12098 mips_flag_pdr = TRUE;
12101 case OPTION_NO_PDR:
12102 mips_flag_pdr = FALSE;
12105 case OPTION_MVXWORKS_PIC:
12106 mips_pic = VXWORKS_PIC;
12108 #endif /* OBJ_ELF */
12114 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12119 /* Set up globals to generate code for the ISA or processor
12120 described by INFO. */
12123 mips_set_architecture (const struct mips_cpu_info *info)
12127 file_mips_arch = info->cpu;
12128 mips_opts.arch = info->cpu;
12129 mips_opts.isa = info->isa;
12134 /* Likewise for tuning. */
12137 mips_set_tune (const struct mips_cpu_info *info)
12140 mips_tune = info->cpu;
12145 mips_after_parse_args (void)
12147 const struct mips_cpu_info *arch_info = 0;
12148 const struct mips_cpu_info *tune_info = 0;
12150 /* GP relative stuff not working for PE */
12151 if (strncmp (TARGET_OS, "pe", 2) == 0)
12153 if (g_switch_seen && g_switch_value != 0)
12154 as_bad (_("-G not supported in this configuration."));
12155 g_switch_value = 0;
12158 if (mips_abi == NO_ABI)
12159 mips_abi = MIPS_DEFAULT_ABI;
12161 /* The following code determines the architecture and register size.
12162 Similar code was added to GCC 3.3 (see override_options() in
12163 config/mips/mips.c). The GAS and GCC code should be kept in sync
12164 as much as possible. */
12166 if (mips_arch_string != 0)
12167 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12169 if (file_mips_isa != ISA_UNKNOWN)
12171 /* Handle -mipsN. At this point, file_mips_isa contains the
12172 ISA level specified by -mipsN, while arch_info->isa contains
12173 the -march selection (if any). */
12174 if (arch_info != 0)
12176 /* -march takes precedence over -mipsN, since it is more descriptive.
12177 There's no harm in specifying both as long as the ISA levels
12179 if (file_mips_isa != arch_info->isa)
12180 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12181 mips_cpu_info_from_isa (file_mips_isa)->name,
12182 mips_cpu_info_from_isa (arch_info->isa)->name);
12185 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12188 if (arch_info == 0)
12189 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12191 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12192 as_bad (_("-march=%s is not compatible with the selected ABI"),
12195 mips_set_architecture (arch_info);
12197 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12198 if (mips_tune_string != 0)
12199 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12201 if (tune_info == 0)
12202 mips_set_tune (arch_info);
12204 mips_set_tune (tune_info);
12206 if (file_mips_gp32 >= 0)
12208 /* The user specified the size of the integer registers. Make sure
12209 it agrees with the ABI and ISA. */
12210 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12211 as_bad (_("-mgp64 used with a 32-bit processor"));
12212 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12213 as_bad (_("-mgp32 used with a 64-bit ABI"));
12214 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12215 as_bad (_("-mgp64 used with a 32-bit ABI"));
12219 /* Infer the integer register size from the ABI and processor.
12220 Restrict ourselves to 32-bit registers if that's all the
12221 processor has, or if the ABI cannot handle 64-bit registers. */
12222 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12223 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12226 switch (file_mips_fp32)
12230 /* No user specified float register size.
12231 ??? GAS treats single-float processors as though they had 64-bit
12232 float registers (although it complains when double-precision
12233 instructions are used). As things stand, saying they have 32-bit
12234 registers would lead to spurious "register must be even" messages.
12235 So here we assume float registers are never smaller than the
12237 if (file_mips_gp32 == 0)
12238 /* 64-bit integer registers implies 64-bit float registers. */
12239 file_mips_fp32 = 0;
12240 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12241 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12242 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12243 file_mips_fp32 = 0;
12245 /* 32-bit float registers. */
12246 file_mips_fp32 = 1;
12249 /* The user specified the size of the float registers. Check if it
12250 agrees with the ABI and ISA. */
12252 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12253 as_bad (_("-mfp64 used with a 32-bit fpu"));
12254 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12255 && !ISA_HAS_MXHC1 (mips_opts.isa))
12256 as_warn (_("-mfp64 used with a 32-bit ABI"));
12259 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12260 as_warn (_("-mfp32 used with a 64-bit ABI"));
12264 /* End of GCC-shared inference code. */
12266 /* This flag is set when we have a 64-bit capable CPU but use only
12267 32-bit wide registers. Note that EABI does not use it. */
12268 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12269 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12270 || mips_abi == O32_ABI))
12271 mips_32bitmode = 1;
12273 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12274 as_bad (_("trap exception not supported at ISA 1"));
12276 /* If the selected architecture includes support for ASEs, enable
12277 generation of code for them. */
12278 if (mips_opts.mips16 == -1)
12279 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12280 if (mips_opts.ase_mips3d == -1)
12281 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12282 && file_mips_fp32 == 0) ? 1 : 0;
12283 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12284 as_bad (_("-mfp32 used with -mips3d"));
12286 if (mips_opts.ase_mdmx == -1)
12287 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12288 && file_mips_fp32 == 0) ? 1 : 0;
12289 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12290 as_bad (_("-mfp32 used with -mdmx"));
12292 if (mips_opts.ase_smartmips == -1)
12293 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12294 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12295 as_warn (_("%s ISA does not support SmartMIPS"),
12296 mips_cpu_info_from_isa (mips_opts.isa)->name);
12298 if (mips_opts.ase_dsp == -1)
12299 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12300 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12301 as_warn (_("%s ISA does not support DSP ASE"),
12302 mips_cpu_info_from_isa (mips_opts.isa)->name);
12304 if (mips_opts.ase_dspr2 == -1)
12306 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12307 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12309 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12310 as_warn (_("%s ISA does not support DSP R2 ASE"),
12311 mips_cpu_info_from_isa (mips_opts.isa)->name);
12313 if (mips_opts.ase_mt == -1)
12314 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12315 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12316 as_warn (_("%s ISA does not support MT ASE"),
12317 mips_cpu_info_from_isa (mips_opts.isa)->name);
12319 file_mips_isa = mips_opts.isa;
12320 file_ase_mips3d = mips_opts.ase_mips3d;
12321 file_ase_mdmx = mips_opts.ase_mdmx;
12322 file_ase_smartmips = mips_opts.ase_smartmips;
12323 file_ase_dsp = mips_opts.ase_dsp;
12324 file_ase_dspr2 = mips_opts.ase_dspr2;
12325 file_ase_mt = mips_opts.ase_mt;
12326 mips_opts.gp32 = file_mips_gp32;
12327 mips_opts.fp32 = file_mips_fp32;
12328 mips_opts.soft_float = file_mips_soft_float;
12329 mips_opts.single_float = file_mips_single_float;
12331 if (mips_flag_mdebug < 0)
12333 #ifdef OBJ_MAYBE_ECOFF
12334 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12335 mips_flag_mdebug = 1;
12337 #endif /* OBJ_MAYBE_ECOFF */
12338 mips_flag_mdebug = 0;
12343 mips_init_after_args (void)
12345 /* initialize opcodes */
12346 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12347 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12351 md_pcrel_from (fixS *fixP)
12353 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12354 switch (fixP->fx_r_type)
12356 case BFD_RELOC_16_PCREL_S2:
12357 case BFD_RELOC_MIPS_JMP:
12358 /* Return the address of the delay slot. */
12361 /* We have no relocation type for PC relative MIPS16 instructions. */
12362 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12363 as_bad_where (fixP->fx_file, fixP->fx_line,
12364 _("PC relative MIPS16 instruction references a different section"));
12369 /* This is called before the symbol table is processed. In order to
12370 work with gcc when using mips-tfile, we must keep all local labels.
12371 However, in other cases, we want to discard them. If we were
12372 called with -g, but we didn't see any debugging information, it may
12373 mean that gcc is smuggling debugging information through to
12374 mips-tfile, in which case we must generate all local labels. */
12377 mips_frob_file_before_adjust (void)
12379 #ifndef NO_ECOFF_DEBUGGING
12380 if (ECOFF_DEBUGGING
12382 && ! ecoff_debugging_seen)
12383 flag_keep_locals = 1;
12387 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12388 the corresponding LO16 reloc. This is called before md_apply_fix and
12389 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12390 relocation operators.
12392 For our purposes, a %lo() expression matches a %got() or %hi()
12395 (a) it refers to the same symbol; and
12396 (b) the offset applied in the %lo() expression is no lower than
12397 the offset applied in the %got() or %hi().
12399 (b) allows us to cope with code like:
12402 lh $4,%lo(foo+2)($4)
12404 ...which is legal on RELA targets, and has a well-defined behaviour
12405 if the user knows that adding 2 to "foo" will not induce a carry to
12408 When several %lo()s match a particular %got() or %hi(), we use the
12409 following rules to distinguish them:
12411 (1) %lo()s with smaller offsets are a better match than %lo()s with
12414 (2) %lo()s with no matching %got() or %hi() are better than those
12415 that already have a matching %got() or %hi().
12417 (3) later %lo()s are better than earlier %lo()s.
12419 These rules are applied in order.
12421 (1) means, among other things, that %lo()s with identical offsets are
12422 chosen if they exist.
12424 (2) means that we won't associate several high-part relocations with
12425 the same low-part relocation unless there's no alternative. Having
12426 several high parts for the same low part is a GNU extension; this rule
12427 allows careful users to avoid it.
12429 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12430 with the last high-part relocation being at the front of the list.
12431 It therefore makes sense to choose the last matching low-part
12432 relocation, all other things being equal. It's also easier
12433 to code that way. */
12436 mips_frob_file (void)
12438 struct mips_hi_fixup *l;
12439 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12441 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12443 segment_info_type *seginfo;
12444 bfd_boolean matched_lo_p;
12445 fixS **hi_pos, **lo_pos, **pos;
12447 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12449 /* If a GOT16 relocation turns out to be against a global symbol,
12450 there isn't supposed to be a matching LO. */
12451 if (got16_reloc_p (l->fixp->fx_r_type)
12452 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12455 /* Check quickly whether the next fixup happens to be a matching %lo. */
12456 if (fixup_has_matching_lo_p (l->fixp))
12459 seginfo = seg_info (l->seg);
12461 /* Set HI_POS to the position of this relocation in the chain.
12462 Set LO_POS to the position of the chosen low-part relocation.
12463 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12464 relocation that matches an immediately-preceding high-part
12468 matched_lo_p = FALSE;
12469 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12471 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12473 if (*pos == l->fixp)
12476 if ((*pos)->fx_r_type == looking_for_rtype
12477 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12478 && (*pos)->fx_offset >= l->fixp->fx_offset
12480 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12482 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12485 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12486 && fixup_has_matching_lo_p (*pos));
12489 /* If we found a match, remove the high-part relocation from its
12490 current position and insert it before the low-part relocation.
12491 Make the offsets match so that fixup_has_matching_lo_p()
12494 We don't warn about unmatched high-part relocations since some
12495 versions of gcc have been known to emit dead "lui ...%hi(...)"
12497 if (lo_pos != NULL)
12499 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12500 if (l->fixp->fx_next != *lo_pos)
12502 *hi_pos = l->fixp->fx_next;
12503 l->fixp->fx_next = *lo_pos;
12510 /* We may have combined relocations without symbols in the N32/N64 ABI.
12511 We have to prevent gas from dropping them. */
12514 mips_force_relocation (fixS *fixp)
12516 if (generic_force_reloc (fixp))
12520 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12521 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12522 || hi16_reloc_p (fixp->fx_r_type)
12523 || lo16_reloc_p (fixp->fx_r_type)))
12529 /* Apply a fixup to the object file. */
12532 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12536 reloc_howto_type *howto;
12538 /* We ignore generic BFD relocations we don't know about. */
12539 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12543 gas_assert (fixP->fx_size == 4
12544 || fixP->fx_r_type == BFD_RELOC_16
12545 || fixP->fx_r_type == BFD_RELOC_64
12546 || fixP->fx_r_type == BFD_RELOC_CTOR
12547 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12548 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12549 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12550 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12552 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12554 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12556 /* Don't treat parts of a composite relocation as done. There are two
12559 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12560 should nevertheless be emitted if the first part is.
12562 (2) In normal usage, composite relocations are never assembly-time
12563 constants. The easiest way of dealing with the pathological
12564 exceptions is to generate a relocation against STN_UNDEF and
12565 leave everything up to the linker. */
12566 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12569 switch (fixP->fx_r_type)
12571 case BFD_RELOC_MIPS_TLS_GD:
12572 case BFD_RELOC_MIPS_TLS_LDM:
12573 case BFD_RELOC_MIPS_TLS_DTPREL32:
12574 case BFD_RELOC_MIPS_TLS_DTPREL64:
12575 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12576 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12577 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12578 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12579 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12580 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12583 case BFD_RELOC_MIPS_JMP:
12584 case BFD_RELOC_MIPS_SHIFT5:
12585 case BFD_RELOC_MIPS_SHIFT6:
12586 case BFD_RELOC_MIPS_GOT_DISP:
12587 case BFD_RELOC_MIPS_GOT_PAGE:
12588 case BFD_RELOC_MIPS_GOT_OFST:
12589 case BFD_RELOC_MIPS_SUB:
12590 case BFD_RELOC_MIPS_INSERT_A:
12591 case BFD_RELOC_MIPS_INSERT_B:
12592 case BFD_RELOC_MIPS_DELETE:
12593 case BFD_RELOC_MIPS_HIGHEST:
12594 case BFD_RELOC_MIPS_HIGHER:
12595 case BFD_RELOC_MIPS_SCN_DISP:
12596 case BFD_RELOC_MIPS_REL16:
12597 case BFD_RELOC_MIPS_RELGOT:
12598 case BFD_RELOC_MIPS_JALR:
12599 case BFD_RELOC_HI16:
12600 case BFD_RELOC_HI16_S:
12601 case BFD_RELOC_GPREL16:
12602 case BFD_RELOC_MIPS_LITERAL:
12603 case BFD_RELOC_MIPS_CALL16:
12604 case BFD_RELOC_MIPS_GOT16:
12605 case BFD_RELOC_GPREL32:
12606 case BFD_RELOC_MIPS_GOT_HI16:
12607 case BFD_RELOC_MIPS_GOT_LO16:
12608 case BFD_RELOC_MIPS_CALL_HI16:
12609 case BFD_RELOC_MIPS_CALL_LO16:
12610 case BFD_RELOC_MIPS16_GPREL:
12611 case BFD_RELOC_MIPS16_GOT16:
12612 case BFD_RELOC_MIPS16_CALL16:
12613 case BFD_RELOC_MIPS16_HI16:
12614 case BFD_RELOC_MIPS16_HI16_S:
12615 case BFD_RELOC_MIPS16_JMP:
12616 /* Nothing needed to do. The value comes from the reloc entry. */
12620 /* This is handled like BFD_RELOC_32, but we output a sign
12621 extended value if we are only 32 bits. */
12624 if (8 <= sizeof (valueT))
12625 md_number_to_chars ((char *) buf, *valP, 8);
12630 if ((*valP & 0x80000000) != 0)
12634 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12636 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12642 case BFD_RELOC_RVA:
12645 /* If we are deleting this reloc entry, we must fill in the
12646 value now. This can happen if we have a .word which is not
12647 resolved when it appears but is later defined. */
12649 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12652 case BFD_RELOC_LO16:
12653 case BFD_RELOC_MIPS16_LO16:
12654 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12655 may be safe to remove, but if so it's not obvious. */
12656 /* When handling an embedded PIC switch statement, we can wind
12657 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12660 if (*valP + 0x8000 > 0xffff)
12661 as_bad_where (fixP->fx_file, fixP->fx_line,
12662 _("relocation overflow"));
12663 if (target_big_endian)
12665 md_number_to_chars ((char *) buf, *valP, 2);
12669 case BFD_RELOC_16_PCREL_S2:
12670 if ((*valP & 0x3) != 0)
12671 as_bad_where (fixP->fx_file, fixP->fx_line,
12672 _("Branch to misaligned address (%lx)"), (long) *valP);
12674 /* We need to save the bits in the instruction since fixup_segment()
12675 might be deleting the relocation entry (i.e., a branch within
12676 the current segment). */
12677 if (! fixP->fx_done)
12680 /* Update old instruction data. */
12681 if (target_big_endian)
12682 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12684 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12686 if (*valP + 0x20000 <= 0x3ffff)
12688 insn |= (*valP >> 2) & 0xffff;
12689 md_number_to_chars ((char *) buf, insn, 4);
12691 else if (mips_pic == NO_PIC
12693 && fixP->fx_frag->fr_address >= text_section->vma
12694 && (fixP->fx_frag->fr_address
12695 < text_section->vma + bfd_get_section_size (text_section))
12696 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12697 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12698 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12700 /* The branch offset is too large. If this is an
12701 unconditional branch, and we are not generating PIC code,
12702 we can convert it to an absolute jump instruction. */
12703 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12704 insn = 0x0c000000; /* jal */
12706 insn = 0x08000000; /* j */
12707 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12709 fixP->fx_addsy = section_symbol (text_section);
12710 *valP += md_pcrel_from (fixP);
12711 md_number_to_chars ((char *) buf, insn, 4);
12715 /* If we got here, we have branch-relaxation disabled,
12716 and there's nothing we can do to fix this instruction
12717 without turning it into a longer sequence. */
12718 as_bad_where (fixP->fx_file, fixP->fx_line,
12719 _("Branch out of range"));
12723 case BFD_RELOC_VTABLE_INHERIT:
12726 && !S_IS_DEFINED (fixP->fx_addsy)
12727 && !S_IS_WEAK (fixP->fx_addsy))
12728 S_SET_WEAK (fixP->fx_addsy);
12731 case BFD_RELOC_VTABLE_ENTRY:
12739 /* Remember value for tc_gen_reloc. */
12740 fixP->fx_addnumber = *valP;
12750 name = input_line_pointer;
12751 c = get_symbol_end ();
12752 p = (symbolS *) symbol_find_or_make (name);
12753 *input_line_pointer = c;
12757 /* Align the current frag to a given power of two. If a particular
12758 fill byte should be used, FILL points to an integer that contains
12759 that byte, otherwise FILL is null.
12761 The MIPS assembler also automatically adjusts any preceding
12765 mips_align (int to, int *fill, symbolS *label)
12767 mips_emit_delays ();
12768 mips_record_mips16_mode ();
12769 if (fill == NULL && subseg_text_p (now_seg))
12770 frag_align_code (to, 0);
12772 frag_align (to, fill ? *fill : 0, 0);
12773 record_alignment (now_seg, to);
12776 gas_assert (S_GET_SEGMENT (label) == now_seg);
12777 symbol_set_frag (label, frag_now);
12778 S_SET_VALUE (label, (valueT) frag_now_fix ());
12782 /* Align to a given power of two. .align 0 turns off the automatic
12783 alignment used by the data creating pseudo-ops. */
12786 s_align (int x ATTRIBUTE_UNUSED)
12788 int temp, fill_value, *fill_ptr;
12789 long max_alignment = 28;
12791 /* o Note that the assembler pulls down any immediately preceding label
12792 to the aligned address.
12793 o It's not documented but auto alignment is reinstated by
12794 a .align pseudo instruction.
12795 o Note also that after auto alignment is turned off the mips assembler
12796 issues an error on attempt to assemble an improperly aligned data item.
12799 temp = get_absolute_expression ();
12800 if (temp > max_alignment)
12801 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12804 as_warn (_("Alignment negative: 0 assumed."));
12807 if (*input_line_pointer == ',')
12809 ++input_line_pointer;
12810 fill_value = get_absolute_expression ();
12811 fill_ptr = &fill_value;
12817 segment_info_type *si = seg_info (now_seg);
12818 struct insn_label_list *l = si->label_list;
12819 /* Auto alignment should be switched on by next section change. */
12821 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12828 demand_empty_rest_of_line ();
12832 s_change_sec (int sec)
12837 /* The ELF backend needs to know that we are changing sections, so
12838 that .previous works correctly. We could do something like check
12839 for an obj_section_change_hook macro, but that might be confusing
12840 as it would not be appropriate to use it in the section changing
12841 functions in read.c, since obj-elf.c intercepts those. FIXME:
12842 This should be cleaner, somehow. */
12844 obj_elf_section_change_hook ();
12847 mips_emit_delays ();
12858 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12859 demand_empty_rest_of_line ();
12863 seg = subseg_new (RDATA_SECTION_NAME,
12864 (subsegT) get_absolute_expression ());
12867 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12868 | SEC_READONLY | SEC_RELOC
12870 if (strncmp (TARGET_OS, "elf", 3) != 0)
12871 record_alignment (seg, 4);
12873 demand_empty_rest_of_line ();
12877 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12880 bfd_set_section_flags (stdoutput, seg,
12881 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12882 if (strncmp (TARGET_OS, "elf", 3) != 0)
12883 record_alignment (seg, 4);
12885 demand_empty_rest_of_line ();
12889 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12892 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12893 if (strncmp (TARGET_OS, "elf", 3) != 0)
12894 record_alignment (seg, 4);
12896 demand_empty_rest_of_line ();
12904 s_change_section (int ignore ATTRIBUTE_UNUSED)
12907 char *section_name;
12912 int section_entry_size;
12913 int section_alignment;
12918 section_name = input_line_pointer;
12919 c = get_symbol_end ();
12921 next_c = *(input_line_pointer + 1);
12923 /* Do we have .section Name<,"flags">? */
12924 if (c != ',' || (c == ',' && next_c == '"'))
12926 /* just after name is now '\0'. */
12927 *input_line_pointer = c;
12928 input_line_pointer = section_name;
12929 obj_elf_section (ignore);
12932 input_line_pointer++;
12934 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12936 section_type = get_absolute_expression ();
12939 if (*input_line_pointer++ == ',')
12940 section_flag = get_absolute_expression ();
12943 if (*input_line_pointer++ == ',')
12944 section_entry_size = get_absolute_expression ();
12946 section_entry_size = 0;
12947 if (*input_line_pointer++ == ',')
12948 section_alignment = get_absolute_expression ();
12950 section_alignment = 0;
12951 /* FIXME: really ignore? */
12952 (void) section_alignment;
12954 section_name = xstrdup (section_name);
12956 /* When using the generic form of .section (as implemented by obj-elf.c),
12957 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12958 traditionally had to fall back on the more common @progbits instead.
12960 There's nothing really harmful in this, since bfd will correct
12961 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12962 means that, for backwards compatibility, the special_section entries
12963 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12965 Even so, we shouldn't force users of the MIPS .section syntax to
12966 incorrectly label the sections as SHT_PROGBITS. The best compromise
12967 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12968 generic type-checking code. */
12969 if (section_type == SHT_MIPS_DWARF)
12970 section_type = SHT_PROGBITS;
12972 obj_elf_change_section (section_name, section_type, section_flag,
12973 section_entry_size, 0, 0, 0);
12975 if (now_seg->name != section_name)
12976 free (section_name);
12977 #endif /* OBJ_ELF */
12981 mips_enable_auto_align (void)
12987 s_cons (int log_size)
12989 segment_info_type *si = seg_info (now_seg);
12990 struct insn_label_list *l = si->label_list;
12993 label = l != NULL ? l->label : NULL;
12994 mips_emit_delays ();
12995 if (log_size > 0 && auto_align)
12996 mips_align (log_size, 0, label);
12997 cons (1 << log_size);
12998 mips_clear_insn_labels ();
13002 s_float_cons (int type)
13004 segment_info_type *si = seg_info (now_seg);
13005 struct insn_label_list *l = si->label_list;
13008 label = l != NULL ? l->label : NULL;
13010 mips_emit_delays ();
13015 mips_align (3, 0, label);
13017 mips_align (2, 0, label);
13021 mips_clear_insn_labels ();
13024 /* Handle .globl. We need to override it because on Irix 5 you are
13027 where foo is an undefined symbol, to mean that foo should be
13028 considered to be the address of a function. */
13031 s_mips_globl (int x ATTRIBUTE_UNUSED)
13040 name = input_line_pointer;
13041 c = get_symbol_end ();
13042 symbolP = symbol_find_or_make (name);
13043 S_SET_EXTERNAL (symbolP);
13045 *input_line_pointer = c;
13046 SKIP_WHITESPACE ();
13048 /* On Irix 5, every global symbol that is not explicitly labelled as
13049 being a function is apparently labelled as being an object. */
13052 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13053 && (*input_line_pointer != ','))
13058 secname = input_line_pointer;
13059 c = get_symbol_end ();
13060 sec = bfd_get_section_by_name (stdoutput, secname);
13062 as_bad (_("%s: no such section"), secname);
13063 *input_line_pointer = c;
13065 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13066 flag = BSF_FUNCTION;
13069 symbol_get_bfdsym (symbolP)->flags |= flag;
13071 c = *input_line_pointer;
13074 input_line_pointer++;
13075 SKIP_WHITESPACE ();
13076 if (is_end_of_line[(unsigned char) *input_line_pointer])
13082 demand_empty_rest_of_line ();
13086 s_option (int x ATTRIBUTE_UNUSED)
13091 opt = input_line_pointer;
13092 c = get_symbol_end ();
13096 /* FIXME: What does this mean? */
13098 else if (strncmp (opt, "pic", 3) == 0)
13102 i = atoi (opt + 3);
13107 mips_pic = SVR4_PIC;
13108 mips_abicalls = TRUE;
13111 as_bad (_(".option pic%d not supported"), i);
13113 if (mips_pic == SVR4_PIC)
13115 if (g_switch_seen && g_switch_value != 0)
13116 as_warn (_("-G may not be used with SVR4 PIC code"));
13117 g_switch_value = 0;
13118 bfd_set_gp_size (stdoutput, 0);
13122 as_warn (_("Unrecognized option \"%s\""), opt);
13124 *input_line_pointer = c;
13125 demand_empty_rest_of_line ();
13128 /* This structure is used to hold a stack of .set values. */
13130 struct mips_option_stack
13132 struct mips_option_stack *next;
13133 struct mips_set_options options;
13136 static struct mips_option_stack *mips_opts_stack;
13138 /* Handle the .set pseudo-op. */
13141 s_mipsset (int x ATTRIBUTE_UNUSED)
13143 char *name = input_line_pointer, ch;
13145 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13146 ++input_line_pointer;
13147 ch = *input_line_pointer;
13148 *input_line_pointer = '\0';
13150 if (strcmp (name, "reorder") == 0)
13152 if (mips_opts.noreorder)
13155 else if (strcmp (name, "noreorder") == 0)
13157 if (!mips_opts.noreorder)
13158 start_noreorder ();
13160 else if (strncmp (name, "at=", 3) == 0)
13162 char *s = name + 3;
13164 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13165 as_bad (_("Unrecognized register name `%s'"), s);
13167 else if (strcmp (name, "at") == 0)
13169 mips_opts.at = ATREG;
13171 else if (strcmp (name, "noat") == 0)
13173 mips_opts.at = ZERO;
13175 else if (strcmp (name, "macro") == 0)
13177 mips_opts.warn_about_macros = 0;
13179 else if (strcmp (name, "nomacro") == 0)
13181 if (mips_opts.noreorder == 0)
13182 as_bad (_("`noreorder' must be set before `nomacro'"));
13183 mips_opts.warn_about_macros = 1;
13185 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13187 mips_opts.nomove = 0;
13189 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13191 mips_opts.nomove = 1;
13193 else if (strcmp (name, "bopt") == 0)
13195 mips_opts.nobopt = 0;
13197 else if (strcmp (name, "nobopt") == 0)
13199 mips_opts.nobopt = 1;
13201 else if (strcmp (name, "gp=default") == 0)
13202 mips_opts.gp32 = file_mips_gp32;
13203 else if (strcmp (name, "gp=32") == 0)
13204 mips_opts.gp32 = 1;
13205 else if (strcmp (name, "gp=64") == 0)
13207 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13208 as_warn (_("%s isa does not support 64-bit registers"),
13209 mips_cpu_info_from_isa (mips_opts.isa)->name);
13210 mips_opts.gp32 = 0;
13212 else if (strcmp (name, "fp=default") == 0)
13213 mips_opts.fp32 = file_mips_fp32;
13214 else if (strcmp (name, "fp=32") == 0)
13215 mips_opts.fp32 = 1;
13216 else if (strcmp (name, "fp=64") == 0)
13218 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13219 as_warn (_("%s isa does not support 64-bit floating point registers"),
13220 mips_cpu_info_from_isa (mips_opts.isa)->name);
13221 mips_opts.fp32 = 0;
13223 else if (strcmp (name, "softfloat") == 0)
13224 mips_opts.soft_float = 1;
13225 else if (strcmp (name, "hardfloat") == 0)
13226 mips_opts.soft_float = 0;
13227 else if (strcmp (name, "singlefloat") == 0)
13228 mips_opts.single_float = 1;
13229 else if (strcmp (name, "doublefloat") == 0)
13230 mips_opts.single_float = 0;
13231 else if (strcmp (name, "mips16") == 0
13232 || strcmp (name, "MIPS-16") == 0)
13233 mips_opts.mips16 = 1;
13234 else if (strcmp (name, "nomips16") == 0
13235 || strcmp (name, "noMIPS-16") == 0)
13236 mips_opts.mips16 = 0;
13237 else if (strcmp (name, "smartmips") == 0)
13239 if (!ISA_SUPPORTS_SMARTMIPS)
13240 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13241 mips_cpu_info_from_isa (mips_opts.isa)->name);
13242 mips_opts.ase_smartmips = 1;
13244 else if (strcmp (name, "nosmartmips") == 0)
13245 mips_opts.ase_smartmips = 0;
13246 else if (strcmp (name, "mips3d") == 0)
13247 mips_opts.ase_mips3d = 1;
13248 else if (strcmp (name, "nomips3d") == 0)
13249 mips_opts.ase_mips3d = 0;
13250 else if (strcmp (name, "mdmx") == 0)
13251 mips_opts.ase_mdmx = 1;
13252 else if (strcmp (name, "nomdmx") == 0)
13253 mips_opts.ase_mdmx = 0;
13254 else if (strcmp (name, "dsp") == 0)
13256 if (!ISA_SUPPORTS_DSP_ASE)
13257 as_warn (_("%s ISA does not support DSP ASE"),
13258 mips_cpu_info_from_isa (mips_opts.isa)->name);
13259 mips_opts.ase_dsp = 1;
13260 mips_opts.ase_dspr2 = 0;
13262 else if (strcmp (name, "nodsp") == 0)
13264 mips_opts.ase_dsp = 0;
13265 mips_opts.ase_dspr2 = 0;
13267 else if (strcmp (name, "dspr2") == 0)
13269 if (!ISA_SUPPORTS_DSPR2_ASE)
13270 as_warn (_("%s ISA does not support DSP R2 ASE"),
13271 mips_cpu_info_from_isa (mips_opts.isa)->name);
13272 mips_opts.ase_dspr2 = 1;
13273 mips_opts.ase_dsp = 1;
13275 else if (strcmp (name, "nodspr2") == 0)
13277 mips_opts.ase_dspr2 = 0;
13278 mips_opts.ase_dsp = 0;
13280 else if (strcmp (name, "mt") == 0)
13282 if (!ISA_SUPPORTS_MT_ASE)
13283 as_warn (_("%s ISA does not support MT ASE"),
13284 mips_cpu_info_from_isa (mips_opts.isa)->name);
13285 mips_opts.ase_mt = 1;
13287 else if (strcmp (name, "nomt") == 0)
13288 mips_opts.ase_mt = 0;
13289 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13293 /* Permit the user to change the ISA and architecture on the fly.
13294 Needless to say, misuse can cause serious problems. */
13295 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13298 mips_opts.isa = file_mips_isa;
13299 mips_opts.arch = file_mips_arch;
13301 else if (strncmp (name, "arch=", 5) == 0)
13303 const struct mips_cpu_info *p;
13305 p = mips_parse_cpu("internal use", name + 5);
13307 as_bad (_("unknown architecture %s"), name + 5);
13310 mips_opts.arch = p->cpu;
13311 mips_opts.isa = p->isa;
13314 else if (strncmp (name, "mips", 4) == 0)
13316 const struct mips_cpu_info *p;
13318 p = mips_parse_cpu("internal use", name);
13320 as_bad (_("unknown ISA level %s"), name + 4);
13323 mips_opts.arch = p->cpu;
13324 mips_opts.isa = p->isa;
13328 as_bad (_("unknown ISA or architecture %s"), name);
13330 switch (mips_opts.isa)
13338 mips_opts.gp32 = 1;
13339 mips_opts.fp32 = 1;
13346 mips_opts.gp32 = 0;
13347 mips_opts.fp32 = 0;
13350 as_bad (_("unknown ISA level %s"), name + 4);
13355 mips_opts.gp32 = file_mips_gp32;
13356 mips_opts.fp32 = file_mips_fp32;
13359 else if (strcmp (name, "autoextend") == 0)
13360 mips_opts.noautoextend = 0;
13361 else if (strcmp (name, "noautoextend") == 0)
13362 mips_opts.noautoextend = 1;
13363 else if (strcmp (name, "push") == 0)
13365 struct mips_option_stack *s;
13367 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13368 s->next = mips_opts_stack;
13369 s->options = mips_opts;
13370 mips_opts_stack = s;
13372 else if (strcmp (name, "pop") == 0)
13374 struct mips_option_stack *s;
13376 s = mips_opts_stack;
13378 as_bad (_(".set pop with no .set push"));
13381 /* If we're changing the reorder mode we need to handle
13382 delay slots correctly. */
13383 if (s->options.noreorder && ! mips_opts.noreorder)
13384 start_noreorder ();
13385 else if (! s->options.noreorder && mips_opts.noreorder)
13388 mips_opts = s->options;
13389 mips_opts_stack = s->next;
13393 else if (strcmp (name, "sym32") == 0)
13394 mips_opts.sym32 = TRUE;
13395 else if (strcmp (name, "nosym32") == 0)
13396 mips_opts.sym32 = FALSE;
13397 else if (strchr (name, ','))
13399 /* Generic ".set" directive; use the generic handler. */
13400 *input_line_pointer = ch;
13401 input_line_pointer = name;
13407 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13409 *input_line_pointer = ch;
13410 demand_empty_rest_of_line ();
13413 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13414 .option pic2. It means to generate SVR4 PIC calls. */
13417 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13419 mips_pic = SVR4_PIC;
13420 mips_abicalls = TRUE;
13422 if (g_switch_seen && g_switch_value != 0)
13423 as_warn (_("-G may not be used with SVR4 PIC code"));
13424 g_switch_value = 0;
13426 bfd_set_gp_size (stdoutput, 0);
13427 demand_empty_rest_of_line ();
13430 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13431 PIC code. It sets the $gp register for the function based on the
13432 function address, which is in the register named in the argument.
13433 This uses a relocation against _gp_disp, which is handled specially
13434 by the linker. The result is:
13435 lui $gp,%hi(_gp_disp)
13436 addiu $gp,$gp,%lo(_gp_disp)
13437 addu $gp,$gp,.cpload argument
13438 The .cpload argument is normally $25 == $t9.
13440 The -mno-shared option changes this to:
13441 lui $gp,%hi(__gnu_local_gp)
13442 addiu $gp,$gp,%lo(__gnu_local_gp)
13443 and the argument is ignored. This saves an instruction, but the
13444 resulting code is not position independent; it uses an absolute
13445 address for __gnu_local_gp. Thus code assembled with -mno-shared
13446 can go into an ordinary executable, but not into a shared library. */
13449 s_cpload (int ignore ATTRIBUTE_UNUSED)
13455 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13456 .cpload is ignored. */
13457 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13463 /* .cpload should be in a .set noreorder section. */
13464 if (mips_opts.noreorder == 0)
13465 as_warn (_(".cpload not in noreorder section"));
13467 reg = tc_get_register (0);
13469 /* If we need to produce a 64-bit address, we are better off using
13470 the default instruction sequence. */
13471 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13473 ex.X_op = O_symbol;
13474 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13476 ex.X_op_symbol = NULL;
13477 ex.X_add_number = 0;
13479 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13480 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13483 macro_build_lui (&ex, mips_gp_register);
13484 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13485 mips_gp_register, BFD_RELOC_LO16);
13487 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13488 mips_gp_register, reg);
13491 demand_empty_rest_of_line ();
13494 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13495 .cpsetup $reg1, offset|$reg2, label
13497 If offset is given, this results in:
13498 sd $gp, offset($sp)
13499 lui $gp, %hi(%neg(%gp_rel(label)))
13500 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13501 daddu $gp, $gp, $reg1
13503 If $reg2 is given, this results in:
13504 daddu $reg2, $gp, $0
13505 lui $gp, %hi(%neg(%gp_rel(label)))
13506 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13507 daddu $gp, $gp, $reg1
13508 $reg1 is normally $25 == $t9.
13510 The -mno-shared option replaces the last three instructions with
13512 addiu $gp,$gp,%lo(_gp) */
13515 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13517 expressionS ex_off;
13518 expressionS ex_sym;
13521 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13522 We also need NewABI support. */
13523 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13529 reg1 = tc_get_register (0);
13530 SKIP_WHITESPACE ();
13531 if (*input_line_pointer != ',')
13533 as_bad (_("missing argument separator ',' for .cpsetup"));
13537 ++input_line_pointer;
13538 SKIP_WHITESPACE ();
13539 if (*input_line_pointer == '$')
13541 mips_cpreturn_register = tc_get_register (0);
13542 mips_cpreturn_offset = -1;
13546 mips_cpreturn_offset = get_absolute_expression ();
13547 mips_cpreturn_register = -1;
13549 SKIP_WHITESPACE ();
13550 if (*input_line_pointer != ',')
13552 as_bad (_("missing argument separator ',' for .cpsetup"));
13556 ++input_line_pointer;
13557 SKIP_WHITESPACE ();
13558 expression (&ex_sym);
13561 if (mips_cpreturn_register == -1)
13563 ex_off.X_op = O_constant;
13564 ex_off.X_add_symbol = NULL;
13565 ex_off.X_op_symbol = NULL;
13566 ex_off.X_add_number = mips_cpreturn_offset;
13568 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13569 BFD_RELOC_LO16, SP);
13572 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13573 mips_gp_register, 0);
13575 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13577 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13578 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13581 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13582 mips_gp_register, -1, BFD_RELOC_GPREL16,
13583 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13585 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13586 mips_gp_register, reg1);
13592 ex.X_op = O_symbol;
13593 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13594 ex.X_op_symbol = NULL;
13595 ex.X_add_number = 0;
13597 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13598 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13600 macro_build_lui (&ex, mips_gp_register);
13601 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13602 mips_gp_register, BFD_RELOC_LO16);
13607 demand_empty_rest_of_line ();
13611 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13613 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13614 .cplocal is ignored. */
13615 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13621 mips_gp_register = tc_get_register (0);
13622 demand_empty_rest_of_line ();
13625 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13626 offset from $sp. The offset is remembered, and after making a PIC
13627 call $gp is restored from that location. */
13630 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13634 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13635 .cprestore is ignored. */
13636 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13642 mips_cprestore_offset = get_absolute_expression ();
13643 mips_cprestore_valid = 1;
13645 ex.X_op = O_constant;
13646 ex.X_add_symbol = NULL;
13647 ex.X_op_symbol = NULL;
13648 ex.X_add_number = mips_cprestore_offset;
13651 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13652 SP, HAVE_64BIT_ADDRESSES);
13655 demand_empty_rest_of_line ();
13658 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13659 was given in the preceding .cpsetup, it results in:
13660 ld $gp, offset($sp)
13662 If a register $reg2 was given there, it results in:
13663 daddu $gp, $reg2, $0 */
13666 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13670 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13671 We also need NewABI support. */
13672 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13679 if (mips_cpreturn_register == -1)
13681 ex.X_op = O_constant;
13682 ex.X_add_symbol = NULL;
13683 ex.X_op_symbol = NULL;
13684 ex.X_add_number = mips_cpreturn_offset;
13686 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13689 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13690 mips_cpreturn_register, 0);
13693 demand_empty_rest_of_line ();
13696 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13697 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13698 use in DWARF debug information. */
13701 s_dtprel_internal (size_t bytes)
13708 if (ex.X_op != O_symbol)
13710 as_bad (_("Unsupported use of %s"), (bytes == 8
13713 ignore_rest_of_line ();
13716 p = frag_more (bytes);
13717 md_number_to_chars (p, 0, bytes);
13718 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13720 ? BFD_RELOC_MIPS_TLS_DTPREL64
13721 : BFD_RELOC_MIPS_TLS_DTPREL32));
13723 demand_empty_rest_of_line ();
13726 /* Handle .dtprelword. */
13729 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13731 s_dtprel_internal (4);
13734 /* Handle .dtpreldword. */
13737 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13739 s_dtprel_internal (8);
13742 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13743 code. It sets the offset to use in gp_rel relocations. */
13746 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13748 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13749 We also need NewABI support. */
13750 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13756 mips_gprel_offset = get_absolute_expression ();
13758 demand_empty_rest_of_line ();
13761 /* Handle the .gpword pseudo-op. This is used when generating PIC
13762 code. It generates a 32 bit GP relative reloc. */
13765 s_gpword (int ignore ATTRIBUTE_UNUSED)
13767 segment_info_type *si;
13768 struct insn_label_list *l;
13773 /* When not generating PIC code, this is treated as .word. */
13774 if (mips_pic != SVR4_PIC)
13780 si = seg_info (now_seg);
13781 l = si->label_list;
13782 label = l != NULL ? l->label : NULL;
13783 mips_emit_delays ();
13785 mips_align (2, 0, label);
13788 mips_clear_insn_labels ();
13790 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13792 as_bad (_("Unsupported use of .gpword"));
13793 ignore_rest_of_line ();
13797 md_number_to_chars (p, 0, 4);
13798 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13799 BFD_RELOC_GPREL32);
13801 demand_empty_rest_of_line ();
13805 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13807 segment_info_type *si;
13808 struct insn_label_list *l;
13813 /* When not generating PIC code, this is treated as .dword. */
13814 if (mips_pic != SVR4_PIC)
13820 si = seg_info (now_seg);
13821 l = si->label_list;
13822 label = l != NULL ? l->label : NULL;
13823 mips_emit_delays ();
13825 mips_align (3, 0, label);
13828 mips_clear_insn_labels ();
13830 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13832 as_bad (_("Unsupported use of .gpdword"));
13833 ignore_rest_of_line ();
13837 md_number_to_chars (p, 0, 8);
13838 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13839 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13841 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13842 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13843 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13845 demand_empty_rest_of_line ();
13848 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13849 tables in SVR4 PIC code. */
13852 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13856 /* This is ignored when not generating SVR4 PIC code. */
13857 if (mips_pic != SVR4_PIC)
13863 /* Add $gp to the register named as an argument. */
13865 reg = tc_get_register (0);
13866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13869 demand_empty_rest_of_line ();
13872 /* Handle the .insn pseudo-op. This marks instruction labels in
13873 mips16 mode. This permits the linker to handle them specially,
13874 such as generating jalx instructions when needed. We also make
13875 them odd for the duration of the assembly, in order to generate the
13876 right sort of code. We will make them even in the adjust_symtab
13877 routine, while leaving them marked. This is convenient for the
13878 debugger and the disassembler. The linker knows to make them odd
13882 s_insn (int ignore ATTRIBUTE_UNUSED)
13884 mips16_mark_labels ();
13886 demand_empty_rest_of_line ();
13889 /* Handle a .stabn directive. We need these in order to mark a label
13890 as being a mips16 text label correctly. Sometimes the compiler
13891 will emit a label, followed by a .stabn, and then switch sections.
13892 If the label and .stabn are in mips16 mode, then the label is
13893 really a mips16 text label. */
13896 s_mips_stab (int type)
13899 mips16_mark_labels ();
13904 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13907 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13914 name = input_line_pointer;
13915 c = get_symbol_end ();
13916 symbolP = symbol_find_or_make (name);
13917 S_SET_WEAK (symbolP);
13918 *input_line_pointer = c;
13920 SKIP_WHITESPACE ();
13922 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13924 if (S_IS_DEFINED (symbolP))
13926 as_bad (_("ignoring attempt to redefine symbol %s"),
13927 S_GET_NAME (symbolP));
13928 ignore_rest_of_line ();
13932 if (*input_line_pointer == ',')
13934 ++input_line_pointer;
13935 SKIP_WHITESPACE ();
13939 if (exp.X_op != O_symbol)
13941 as_bad (_("bad .weakext directive"));
13942 ignore_rest_of_line ();
13945 symbol_set_value_expression (symbolP, &exp);
13948 demand_empty_rest_of_line ();
13951 /* Parse a register string into a number. Called from the ECOFF code
13952 to parse .frame. The argument is non-zero if this is the frame
13953 register, so that we can record it in mips_frame_reg. */
13956 tc_get_register (int frame)
13960 SKIP_WHITESPACE ();
13961 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13965 mips_frame_reg = reg != 0 ? reg : SP;
13966 mips_frame_reg_valid = 1;
13967 mips_cprestore_valid = 0;
13973 md_section_align (asection *seg, valueT addr)
13975 int align = bfd_get_section_alignment (stdoutput, seg);
13979 /* We don't need to align ELF sections to the full alignment.
13980 However, Irix 5 may prefer that we align them at least to a 16
13981 byte boundary. We don't bother to align the sections if we
13982 are targeted for an embedded system. */
13983 if (strncmp (TARGET_OS, "elf", 3) == 0)
13989 return ((addr + (1 << align) - 1) & (-1 << align));
13992 /* Utility routine, called from above as well. If called while the
13993 input file is still being read, it's only an approximation. (For
13994 example, a symbol may later become defined which appeared to be
13995 undefined earlier.) */
13998 nopic_need_relax (symbolS *sym, int before_relaxing)
14003 if (g_switch_value > 0)
14005 const char *symname;
14008 /* Find out whether this symbol can be referenced off the $gp
14009 register. It can be if it is smaller than the -G size or if
14010 it is in the .sdata or .sbss section. Certain symbols can
14011 not be referenced off the $gp, although it appears as though
14013 symname = S_GET_NAME (sym);
14014 if (symname != (const char *) NULL
14015 && (strcmp (symname, "eprol") == 0
14016 || strcmp (symname, "etext") == 0
14017 || strcmp (symname, "_gp") == 0
14018 || strcmp (symname, "edata") == 0
14019 || strcmp (symname, "_fbss") == 0
14020 || strcmp (symname, "_fdata") == 0
14021 || strcmp (symname, "_ftext") == 0
14022 || strcmp (symname, "end") == 0
14023 || strcmp (symname, "_gp_disp") == 0))
14025 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14027 #ifndef NO_ECOFF_DEBUGGING
14028 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14029 && (symbol_get_obj (sym)->ecoff_extern_size
14030 <= g_switch_value))
14032 /* We must defer this decision until after the whole
14033 file has been read, since there might be a .extern
14034 after the first use of this symbol. */
14035 || (before_relaxing
14036 #ifndef NO_ECOFF_DEBUGGING
14037 && symbol_get_obj (sym)->ecoff_extern_size == 0
14039 && S_GET_VALUE (sym) == 0)
14040 || (S_GET_VALUE (sym) != 0
14041 && S_GET_VALUE (sym) <= g_switch_value)))
14045 const char *segname;
14047 segname = segment_name (S_GET_SEGMENT (sym));
14048 gas_assert (strcmp (segname, ".lit8") != 0
14049 && strcmp (segname, ".lit4") != 0);
14050 change = (strcmp (segname, ".sdata") != 0
14051 && strcmp (segname, ".sbss") != 0
14052 && strncmp (segname, ".sdata.", 7) != 0
14053 && strncmp (segname, ".sbss.", 6) != 0
14054 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14055 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14060 /* We are not optimizing for the $gp register. */
14065 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14068 pic_need_relax (symbolS *sym, asection *segtype)
14072 /* Handle the case of a symbol equated to another symbol. */
14073 while (symbol_equated_reloc_p (sym))
14077 /* It's possible to get a loop here in a badly written program. */
14078 n = symbol_get_value_expression (sym)->X_add_symbol;
14084 if (symbol_section_p (sym))
14087 symsec = S_GET_SEGMENT (sym);
14089 /* This must duplicate the test in adjust_reloc_syms. */
14090 return (symsec != &bfd_und_section
14091 && symsec != &bfd_abs_section
14092 && !bfd_is_com_section (symsec)
14093 && !s_is_linkonce (sym, segtype)
14095 /* A global or weak symbol is treated as external. */
14096 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14102 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14103 extended opcode. SEC is the section the frag is in. */
14106 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14109 const struct mips16_immed_operand *op;
14111 int mintiny, maxtiny;
14115 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14117 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14120 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14121 op = mips16_immed_operands;
14122 while (op->type != type)
14125 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14130 if (type == '<' || type == '>' || type == '[' || type == ']')
14133 maxtiny = 1 << op->nbits;
14138 maxtiny = (1 << op->nbits) - 1;
14143 mintiny = - (1 << (op->nbits - 1));
14144 maxtiny = (1 << (op->nbits - 1)) - 1;
14147 sym_frag = symbol_get_frag (fragp->fr_symbol);
14148 val = S_GET_VALUE (fragp->fr_symbol);
14149 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14155 /* We won't have the section when we are called from
14156 mips_relax_frag. However, we will always have been called
14157 from md_estimate_size_before_relax first. If this is a
14158 branch to a different section, we mark it as such. If SEC is
14159 NULL, and the frag is not marked, then it must be a branch to
14160 the same section. */
14163 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14168 /* Must have been called from md_estimate_size_before_relax. */
14171 fragp->fr_subtype =
14172 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14174 /* FIXME: We should support this, and let the linker
14175 catch branches and loads that are out of range. */
14176 as_bad_where (fragp->fr_file, fragp->fr_line,
14177 _("unsupported PC relative reference to different section"));
14181 if (fragp != sym_frag && sym_frag->fr_address == 0)
14182 /* Assume non-extended on the first relaxation pass.
14183 The address we have calculated will be bogus if this is
14184 a forward branch to another frag, as the forward frag
14185 will have fr_address == 0. */
14189 /* In this case, we know for sure that the symbol fragment is in
14190 the same section. If the relax_marker of the symbol fragment
14191 differs from the relax_marker of this fragment, we have not
14192 yet adjusted the symbol fragment fr_address. We want to add
14193 in STRETCH in order to get a better estimate of the address.
14194 This particularly matters because of the shift bits. */
14196 && sym_frag->relax_marker != fragp->relax_marker)
14200 /* Adjust stretch for any alignment frag. Note that if have
14201 been expanding the earlier code, the symbol may be
14202 defined in what appears to be an earlier frag. FIXME:
14203 This doesn't handle the fr_subtype field, which specifies
14204 a maximum number of bytes to skip when doing an
14206 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14208 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14211 stretch = - ((- stretch)
14212 & ~ ((1 << (int) f->fr_offset) - 1));
14214 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14223 addr = fragp->fr_address + fragp->fr_fix;
14225 /* The base address rules are complicated. The base address of
14226 a branch is the following instruction. The base address of a
14227 PC relative load or add is the instruction itself, but if it
14228 is in a delay slot (in which case it can not be extended) use
14229 the address of the instruction whose delay slot it is in. */
14230 if (type == 'p' || type == 'q')
14234 /* If we are currently assuming that this frag should be
14235 extended, then, the current address is two bytes
14237 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14240 /* Ignore the low bit in the target, since it will be set
14241 for a text label. */
14242 if ((val & 1) != 0)
14245 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14247 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14250 val -= addr & ~ ((1 << op->shift) - 1);
14252 /* Branch offsets have an implicit 0 in the lowest bit. */
14253 if (type == 'p' || type == 'q')
14256 /* If any of the shifted bits are set, we must use an extended
14257 opcode. If the address depends on the size of this
14258 instruction, this can lead to a loop, so we arrange to always
14259 use an extended opcode. We only check this when we are in
14260 the main relaxation loop, when SEC is NULL. */
14261 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14263 fragp->fr_subtype =
14264 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14268 /* If we are about to mark a frag as extended because the value
14269 is precisely maxtiny + 1, then there is a chance of an
14270 infinite loop as in the following code:
14275 In this case when the la is extended, foo is 0x3fc bytes
14276 away, so the la can be shrunk, but then foo is 0x400 away, so
14277 the la must be extended. To avoid this loop, we mark the
14278 frag as extended if it was small, and is about to become
14279 extended with a value of maxtiny + 1. */
14280 if (val == ((maxtiny + 1) << op->shift)
14281 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14284 fragp->fr_subtype =
14285 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14289 else if (symsec != absolute_section && sec != NULL)
14290 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14292 if ((val & ((1 << op->shift) - 1)) != 0
14293 || val < (mintiny << op->shift)
14294 || val > (maxtiny << op->shift))
14300 /* Compute the length of a branch sequence, and adjust the
14301 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14302 worst-case length is computed, with UPDATE being used to indicate
14303 whether an unconditional (-1), branch-likely (+1) or regular (0)
14304 branch is to be computed. */
14306 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14308 bfd_boolean toofar;
14312 && S_IS_DEFINED (fragp->fr_symbol)
14313 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14318 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14320 addr = fragp->fr_address + fragp->fr_fix + 4;
14324 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14327 /* If the symbol is not defined or it's in a different segment,
14328 assume the user knows what's going on and emit a short
14334 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14336 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14337 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14338 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14339 RELAX_BRANCH_LINK (fragp->fr_subtype),
14345 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14348 if (mips_pic != NO_PIC)
14350 /* Additional space for PIC loading of target address. */
14352 if (mips_opts.isa == ISA_MIPS1)
14353 /* Additional space for $at-stabilizing nop. */
14357 /* If branch is conditional. */
14358 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14365 /* Estimate the size of a frag before relaxing. Unless this is the
14366 mips16, we are not really relaxing here, and the final size is
14367 encoded in the subtype information. For the mips16, we have to
14368 decide whether we are using an extended opcode or not. */
14371 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14375 if (RELAX_BRANCH_P (fragp->fr_subtype))
14378 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14380 return fragp->fr_var;
14383 if (RELAX_MIPS16_P (fragp->fr_subtype))
14384 /* We don't want to modify the EXTENDED bit here; it might get us
14385 into infinite loops. We change it only in mips_relax_frag(). */
14386 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14388 if (mips_pic == NO_PIC)
14389 change = nopic_need_relax (fragp->fr_symbol, 0);
14390 else if (mips_pic == SVR4_PIC)
14391 change = pic_need_relax (fragp->fr_symbol, segtype);
14392 else if (mips_pic == VXWORKS_PIC)
14393 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14400 fragp->fr_subtype |= RELAX_USE_SECOND;
14401 return -RELAX_FIRST (fragp->fr_subtype);
14404 return -RELAX_SECOND (fragp->fr_subtype);
14407 /* This is called to see whether a reloc against a defined symbol
14408 should be converted into a reloc against a section. */
14411 mips_fix_adjustable (fixS *fixp)
14413 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14414 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14417 if (fixp->fx_addsy == NULL)
14420 /* If symbol SYM is in a mergeable section, relocations of the form
14421 SYM + 0 can usually be made section-relative. The mergeable data
14422 is then identified by the section offset rather than by the symbol.
14424 However, if we're generating REL LO16 relocations, the offset is split
14425 between the LO16 and parterning high part relocation. The linker will
14426 need to recalculate the complete offset in order to correctly identify
14429 The linker has traditionally not looked for the parterning high part
14430 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14431 placed anywhere. Rather than break backwards compatibility by changing
14432 this, it seems better not to force the issue, and instead keep the
14433 original symbol. This will work with either linker behavior. */
14434 if ((lo16_reloc_p (fixp->fx_r_type)
14435 || reloc_needs_lo_p (fixp->fx_r_type))
14436 && HAVE_IN_PLACE_ADDENDS
14437 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14440 /* There is no place to store an in-place offset for JALR relocations.
14441 Likewise an in-range offset of PC-relative relocations may overflow
14442 the in-place relocatable field if recalculated against the start
14443 address of the symbol's containing section. */
14444 if (HAVE_IN_PLACE_ADDENDS
14445 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14449 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14450 to a floating-point stub. The same is true for non-R_MIPS16_26
14451 relocations against MIPS16 functions; in this case, the stub becomes
14452 the function's canonical address.
14454 Floating-point stubs are stored in unique .mips16.call.* or
14455 .mips16.fn.* sections. If a stub T for function F is in section S,
14456 the first relocation in section S must be against F; this is how the
14457 linker determines the target function. All relocations that might
14458 resolve to T must also be against F. We therefore have the following
14459 restrictions, which are given in an intentionally-redundant way:
14461 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14464 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14465 if that stub might be used.
14467 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14470 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14471 that stub might be used.
14473 There is a further restriction:
14475 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14476 on targets with in-place addends; the relocation field cannot
14477 encode the low bit.
14479 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14480 against a MIPS16 symbol.
14482 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14483 relocation against some symbol R, no relocation against R may be
14484 reduced. (Note that this deals with (2) as well as (1) because
14485 relocations against global symbols will never be reduced on ELF
14486 targets.) This approach is a little simpler than trying to detect
14487 stub sections, and gives the "all or nothing" per-symbol consistency
14488 that we have for MIPS16 symbols. */
14490 && fixp->fx_subsy == NULL
14491 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14492 || *symbol_get_tc (fixp->fx_addsy)))
14499 /* Translate internal representation of relocation info to BFD target
14503 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14505 static arelent *retval[4];
14507 bfd_reloc_code_real_type code;
14509 memset (retval, 0, sizeof(retval));
14510 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14511 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14512 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14513 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14515 if (fixp->fx_pcrel)
14517 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14519 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14520 Relocations want only the symbol offset. */
14521 reloc->addend = fixp->fx_addnumber + reloc->address;
14524 /* A gruesome hack which is a result of the gruesome gas
14525 reloc handling. What's worse, for COFF (as opposed to
14526 ECOFF), we might need yet another copy of reloc->address.
14527 See bfd_install_relocation. */
14528 reloc->addend += reloc->address;
14532 reloc->addend = fixp->fx_addnumber;
14534 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14535 entry to be used in the relocation's section offset. */
14536 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14538 reloc->address = reloc->addend;
14542 code = fixp->fx_r_type;
14544 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14545 if (reloc->howto == NULL)
14547 as_bad_where (fixp->fx_file, fixp->fx_line,
14548 _("Can not represent %s relocation in this object file format"),
14549 bfd_get_reloc_code_name (code));
14556 /* Relax a machine dependent frag. This returns the amount by which
14557 the current size of the frag should change. */
14560 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14562 if (RELAX_BRANCH_P (fragp->fr_subtype))
14564 offsetT old_var = fragp->fr_var;
14566 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14568 return fragp->fr_var - old_var;
14571 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14574 if (mips16_extended_frag (fragp, NULL, stretch))
14576 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14578 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14583 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14585 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14592 /* Convert a machine dependent frag. */
14595 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14597 if (RELAX_BRANCH_P (fragp->fr_subtype))
14600 unsigned long insn;
14604 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14606 if (target_big_endian)
14607 insn = bfd_getb32 (buf);
14609 insn = bfd_getl32 (buf);
14611 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14613 /* We generate a fixup instead of applying it right now
14614 because, if there are linker relaxations, we're going to
14615 need the relocations. */
14616 exp.X_op = O_symbol;
14617 exp.X_add_symbol = fragp->fr_symbol;
14618 exp.X_add_number = fragp->fr_offset;
14620 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14621 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14622 fixp->fx_file = fragp->fr_file;
14623 fixp->fx_line = fragp->fr_line;
14625 md_number_to_chars ((char *) buf, insn, 4);
14632 as_warn_where (fragp->fr_file, fragp->fr_line,
14633 _("Relaxed out-of-range branch into a jump"));
14635 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14638 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14640 /* Reverse the branch. */
14641 switch ((insn >> 28) & 0xf)
14644 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14645 have the condition reversed by tweaking a single
14646 bit, and their opcodes all have 0x4???????. */
14647 gas_assert ((insn & 0xf1000000) == 0x41000000);
14648 insn ^= 0x00010000;
14652 /* bltz 0x04000000 bgez 0x04010000
14653 bltzal 0x04100000 bgezal 0x04110000 */
14654 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14655 insn ^= 0x00010000;
14659 /* beq 0x10000000 bne 0x14000000
14660 blez 0x18000000 bgtz 0x1c000000 */
14661 insn ^= 0x04000000;
14669 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14671 /* Clear the and-link bit. */
14672 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14674 /* bltzal 0x04100000 bgezal 0x04110000
14675 bltzall 0x04120000 bgezall 0x04130000 */
14676 insn &= ~0x00100000;
14679 /* Branch over the branch (if the branch was likely) or the
14680 full jump (not likely case). Compute the offset from the
14681 current instruction to branch to. */
14682 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14686 /* How many bytes in instructions we've already emitted? */
14687 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14688 /* How many bytes in instructions from here to the end? */
14689 i = fragp->fr_var - i;
14691 /* Convert to instruction count. */
14693 /* Branch counts from the next instruction. */
14696 /* Branch over the jump. */
14697 md_number_to_chars ((char *) buf, insn, 4);
14701 md_number_to_chars ((char *) buf, 0, 4);
14704 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14706 /* beql $0, $0, 2f */
14708 /* Compute the PC offset from the current instruction to
14709 the end of the variable frag. */
14710 /* How many bytes in instructions we've already emitted? */
14711 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14712 /* How many bytes in instructions from here to the end? */
14713 i = fragp->fr_var - i;
14714 /* Convert to instruction count. */
14716 /* Don't decrement i, because we want to branch over the
14720 md_number_to_chars ((char *) buf, insn, 4);
14723 md_number_to_chars ((char *) buf, 0, 4);
14728 if (mips_pic == NO_PIC)
14731 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14732 ? 0x0c000000 : 0x08000000);
14733 exp.X_op = O_symbol;
14734 exp.X_add_symbol = fragp->fr_symbol;
14735 exp.X_add_number = fragp->fr_offset;
14737 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14738 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14739 fixp->fx_file = fragp->fr_file;
14740 fixp->fx_line = fragp->fr_line;
14742 md_number_to_chars ((char *) buf, insn, 4);
14747 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14749 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14750 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14751 insn |= at << OP_SH_RT;
14752 exp.X_op = O_symbol;
14753 exp.X_add_symbol = fragp->fr_symbol;
14754 exp.X_add_number = fragp->fr_offset;
14756 if (fragp->fr_offset)
14758 exp.X_add_symbol = make_expr_symbol (&exp);
14759 exp.X_add_number = 0;
14762 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14763 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14764 fixp->fx_file = fragp->fr_file;
14765 fixp->fx_line = fragp->fr_line;
14767 md_number_to_chars ((char *) buf, insn, 4);
14770 if (mips_opts.isa == ISA_MIPS1)
14773 md_number_to_chars ((char *) buf, 0, 4);
14777 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14778 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14779 insn |= at << OP_SH_RS | at << OP_SH_RT;
14781 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14782 4, &exp, FALSE, BFD_RELOC_LO16);
14783 fixp->fx_file = fragp->fr_file;
14784 fixp->fx_line = fragp->fr_line;
14786 md_number_to_chars ((char *) buf, insn, 4);
14790 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14794 insn |= at << OP_SH_RS;
14796 md_number_to_chars ((char *) buf, insn, 4);
14801 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14802 + fragp->fr_fix + fragp->fr_var);
14804 fragp->fr_fix += fragp->fr_var;
14809 if (RELAX_MIPS16_P (fragp->fr_subtype))
14812 const struct mips16_immed_operand *op;
14813 bfd_boolean small, ext;
14816 unsigned long insn;
14817 bfd_boolean use_extend;
14818 unsigned short extend;
14820 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14821 op = mips16_immed_operands;
14822 while (op->type != type)
14825 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14836 val = resolve_symbol_value (fragp->fr_symbol);
14841 addr = fragp->fr_address + fragp->fr_fix;
14843 /* The rules for the base address of a PC relative reloc are
14844 complicated; see mips16_extended_frag. */
14845 if (type == 'p' || type == 'q')
14850 /* Ignore the low bit in the target, since it will be
14851 set for a text label. */
14852 if ((val & 1) != 0)
14855 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14857 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14860 addr &= ~ (addressT) ((1 << op->shift) - 1);
14863 /* Make sure the section winds up with the alignment we have
14866 record_alignment (asec, op->shift);
14870 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14871 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14872 as_warn_where (fragp->fr_file, fragp->fr_line,
14873 _("extended instruction in delay slot"));
14875 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14877 if (target_big_endian)
14878 insn = bfd_getb16 (buf);
14880 insn = bfd_getl16 (buf);
14882 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14883 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14884 small, ext, &insn, &use_extend, &extend);
14888 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14889 fragp->fr_fix += 2;
14893 md_number_to_chars ((char *) buf, insn, 2);
14894 fragp->fr_fix += 2;
14902 first = RELAX_FIRST (fragp->fr_subtype);
14903 second = RELAX_SECOND (fragp->fr_subtype);
14904 fixp = (fixS *) fragp->fr_opcode;
14906 /* Possibly emit a warning if we've chosen the longer option. */
14907 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14908 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14910 const char *msg = macro_warning (fragp->fr_subtype);
14912 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14915 /* Go through all the fixups for the first sequence. Disable them
14916 (by marking them as done) if we're going to use the second
14917 sequence instead. */
14919 && fixp->fx_frag == fragp
14920 && fixp->fx_where < fragp->fr_fix - second)
14922 if (fragp->fr_subtype & RELAX_USE_SECOND)
14924 fixp = fixp->fx_next;
14927 /* Go through the fixups for the second sequence. Disable them if
14928 we're going to use the first sequence, otherwise adjust their
14929 addresses to account for the relaxation. */
14930 while (fixp && fixp->fx_frag == fragp)
14932 if (fragp->fr_subtype & RELAX_USE_SECOND)
14933 fixp->fx_where -= first;
14936 fixp = fixp->fx_next;
14939 /* Now modify the frag contents. */
14940 if (fragp->fr_subtype & RELAX_USE_SECOND)
14944 start = fragp->fr_literal + fragp->fr_fix - first - second;
14945 memmove (start, start + first, second);
14946 fragp->fr_fix -= first;
14949 fragp->fr_fix -= second;
14955 /* This function is called after the relocs have been generated.
14956 We've been storing mips16 text labels as odd. Here we convert them
14957 back to even for the convenience of the debugger. */
14960 mips_frob_file_after_relocs (void)
14963 unsigned int count, i;
14968 syms = bfd_get_outsymbols (stdoutput);
14969 count = bfd_get_symcount (stdoutput);
14970 for (i = 0; i < count; i++, syms++)
14972 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14973 && ((*syms)->value & 1) != 0)
14975 (*syms)->value &= ~1;
14976 /* If the symbol has an odd size, it was probably computed
14977 incorrectly, so adjust that as well. */
14978 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14979 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14986 /* This function is called whenever a label is defined, including fake
14987 labels instantiated off the dot special symbol. It is used when
14988 handling branch delays; if a branch has a label, we assume we cannot
14989 move it. This also bumps the value of the symbol by 1 in compressed
14993 mips_record_label (symbolS *sym)
14995 segment_info_type *si = seg_info (now_seg);
14996 struct insn_label_list *l;
14998 if (free_insn_labels == NULL)
14999 l = (struct insn_label_list *) xmalloc (sizeof *l);
15002 l = free_insn_labels;
15003 free_insn_labels = l->next;
15007 l->next = si->label_list;
15008 si->label_list = l;
15011 /* This function is called as tc_frob_label() whenever a label is defined
15012 and adds a DWARF-2 record we only want for true labels. */
15015 mips_define_label (symbolS *sym)
15017 mips_record_label (sym);
15019 dwarf2_emit_label (sym);
15023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15025 /* Some special processing for a MIPS ELF file. */
15028 mips_elf_final_processing (void)
15030 /* Write out the register information. */
15031 if (mips_abi != N64_ABI)
15035 s.ri_gprmask = mips_gprmask;
15036 s.ri_cprmask[0] = mips_cprmask[0];
15037 s.ri_cprmask[1] = mips_cprmask[1];
15038 s.ri_cprmask[2] = mips_cprmask[2];
15039 s.ri_cprmask[3] = mips_cprmask[3];
15040 /* The gp_value field is set by the MIPS ELF backend. */
15042 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15043 ((Elf32_External_RegInfo *)
15044 mips_regmask_frag));
15048 Elf64_Internal_RegInfo s;
15050 s.ri_gprmask = mips_gprmask;
15052 s.ri_cprmask[0] = mips_cprmask[0];
15053 s.ri_cprmask[1] = mips_cprmask[1];
15054 s.ri_cprmask[2] = mips_cprmask[2];
15055 s.ri_cprmask[3] = mips_cprmask[3];
15056 /* The gp_value field is set by the MIPS ELF backend. */
15058 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15059 ((Elf64_External_RegInfo *)
15060 mips_regmask_frag));
15063 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15064 sort of BFD interface for this. */
15065 if (mips_any_noreorder)
15066 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15067 if (mips_pic != NO_PIC)
15069 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15070 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15073 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15075 /* Set MIPS ELF flags for ASEs. */
15076 /* We may need to define a new flag for DSP ASE, and set this flag when
15077 file_ase_dsp is true. */
15078 /* Same for DSP R2. */
15079 /* We may need to define a new flag for MT ASE, and set this flag when
15080 file_ase_mt is true. */
15081 if (file_ase_mips16)
15082 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15083 #if 0 /* XXX FIXME */
15084 if (file_ase_mips3d)
15085 elf_elfheader (stdoutput)->e_flags |= ???;
15088 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15090 /* Set the MIPS ELF ABI flags. */
15091 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15092 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15093 else if (mips_abi == O64_ABI)
15094 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15095 else if (mips_abi == EABI_ABI)
15097 if (!file_mips_gp32)
15098 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15100 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15102 else if (mips_abi == N32_ABI)
15103 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15105 /* Nothing to do for N64_ABI. */
15107 if (mips_32bitmode)
15108 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15110 #if 0 /* XXX FIXME */
15111 /* 32 bit code with 64 bit FP registers. */
15112 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15113 elf_elfheader (stdoutput)->e_flags |= ???;
15117 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15119 typedef struct proc {
15121 symbolS *func_end_sym;
15122 unsigned long reg_mask;
15123 unsigned long reg_offset;
15124 unsigned long fpreg_mask;
15125 unsigned long fpreg_offset;
15126 unsigned long frame_offset;
15127 unsigned long frame_reg;
15128 unsigned long pc_reg;
15131 static procS cur_proc;
15132 static procS *cur_proc_ptr;
15133 static int numprocs;
15135 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15139 mips_nop_opcode (void)
15141 return seg_info (now_seg)->tc_segment_info_data.mips16;
15144 /* Fill in an rs_align_code fragment. This only needs to do something
15145 for MIPS16 code, where 0 is not a nop. */
15148 mips_handle_align (fragS *fragp)
15151 int bytes, size, excess;
15154 if (fragp->fr_type != rs_align_code)
15157 p = fragp->fr_literal + fragp->fr_fix;
15160 opcode = mips16_nop_insn.insn_opcode;
15165 opcode = nop_insn.insn_opcode;
15169 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15170 excess = bytes % size;
15173 /* If we're not inserting a whole number of instructions,
15174 pad the end of the fixed part of the frag with zeros. */
15175 memset (p, 0, excess);
15177 fragp->fr_fix += excess;
15180 md_number_to_chars (p, opcode, size);
15181 fragp->fr_var = size;
15185 md_obj_begin (void)
15192 /* Check for premature end, nesting errors, etc. */
15194 as_warn (_("missing .end at end of assembly"));
15203 if (*input_line_pointer == '-')
15205 ++input_line_pointer;
15208 if (!ISDIGIT (*input_line_pointer))
15209 as_bad (_("expected simple number"));
15210 if (input_line_pointer[0] == '0')
15212 if (input_line_pointer[1] == 'x')
15214 input_line_pointer += 2;
15215 while (ISXDIGIT (*input_line_pointer))
15218 val |= hex_value (*input_line_pointer++);
15220 return negative ? -val : val;
15224 ++input_line_pointer;
15225 while (ISDIGIT (*input_line_pointer))
15228 val |= *input_line_pointer++ - '0';
15230 return negative ? -val : val;
15233 if (!ISDIGIT (*input_line_pointer))
15235 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15236 *input_line_pointer, *input_line_pointer);
15237 as_warn (_("invalid number"));
15240 while (ISDIGIT (*input_line_pointer))
15243 val += *input_line_pointer++ - '0';
15245 return negative ? -val : val;
15248 /* The .file directive; just like the usual .file directive, but there
15249 is an initial number which is the ECOFF file index. In the non-ECOFF
15250 case .file implies DWARF-2. */
15253 s_mips_file (int x ATTRIBUTE_UNUSED)
15255 static int first_file_directive = 0;
15257 if (ECOFF_DEBUGGING)
15266 filename = dwarf2_directive_file (0);
15268 /* Versions of GCC up to 3.1 start files with a ".file"
15269 directive even for stabs output. Make sure that this
15270 ".file" is handled. Note that you need a version of GCC
15271 after 3.1 in order to support DWARF-2 on MIPS. */
15272 if (filename != NULL && ! first_file_directive)
15274 (void) new_logical_line (filename, -1);
15275 s_app_file_string (filename, 0);
15277 first_file_directive = 1;
15281 /* The .loc directive, implying DWARF-2. */
15284 s_mips_loc (int x ATTRIBUTE_UNUSED)
15286 if (!ECOFF_DEBUGGING)
15287 dwarf2_directive_loc (0);
15290 /* The .end directive. */
15293 s_mips_end (int x ATTRIBUTE_UNUSED)
15297 /* Following functions need their own .frame and .cprestore directives. */
15298 mips_frame_reg_valid = 0;
15299 mips_cprestore_valid = 0;
15301 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15304 demand_empty_rest_of_line ();
15309 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15310 as_warn (_(".end not in text section"));
15314 as_warn (_(".end directive without a preceding .ent directive."));
15315 demand_empty_rest_of_line ();
15321 gas_assert (S_GET_NAME (p));
15322 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15323 as_warn (_(".end symbol does not match .ent symbol."));
15325 if (debug_type == DEBUG_STABS)
15326 stabs_generate_asm_endfunc (S_GET_NAME (p),
15330 as_warn (_(".end directive missing or unknown symbol"));
15333 /* Create an expression to calculate the size of the function. */
15334 if (p && cur_proc_ptr)
15336 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15337 expressionS *exp = xmalloc (sizeof (expressionS));
15340 exp->X_op = O_subtract;
15341 exp->X_add_symbol = symbol_temp_new_now ();
15342 exp->X_op_symbol = p;
15343 exp->X_add_number = 0;
15345 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15348 /* Generate a .pdr section. */
15349 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15351 segT saved_seg = now_seg;
15352 subsegT saved_subseg = now_subseg;
15356 #ifdef md_flush_pending_output
15357 md_flush_pending_output ();
15360 gas_assert (pdr_seg);
15361 subseg_set (pdr_seg, 0);
15363 /* Write the symbol. */
15364 exp.X_op = O_symbol;
15365 exp.X_add_symbol = p;
15366 exp.X_add_number = 0;
15367 emit_expr (&exp, 4);
15369 fragp = frag_more (7 * 4);
15371 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15372 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15373 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15374 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15375 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15376 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15377 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15379 subseg_set (saved_seg, saved_subseg);
15381 #endif /* OBJ_ELF */
15383 cur_proc_ptr = NULL;
15386 /* The .aent and .ent directives. */
15389 s_mips_ent (int aent)
15393 symbolP = get_symbol ();
15394 if (*input_line_pointer == ',')
15395 ++input_line_pointer;
15396 SKIP_WHITESPACE ();
15397 if (ISDIGIT (*input_line_pointer)
15398 || *input_line_pointer == '-')
15401 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15402 as_warn (_(".ent or .aent not in text section."));
15404 if (!aent && cur_proc_ptr)
15405 as_warn (_("missing .end"));
15409 /* This function needs its own .frame and .cprestore directives. */
15410 mips_frame_reg_valid = 0;
15411 mips_cprestore_valid = 0;
15413 cur_proc_ptr = &cur_proc;
15414 memset (cur_proc_ptr, '\0', sizeof (procS));
15416 cur_proc_ptr->func_sym = symbolP;
15420 if (debug_type == DEBUG_STABS)
15421 stabs_generate_asm_func (S_GET_NAME (symbolP),
15422 S_GET_NAME (symbolP));
15425 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15427 demand_empty_rest_of_line ();
15430 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15431 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15432 s_mips_frame is used so that we can set the PDR information correctly.
15433 We can't use the ecoff routines because they make reference to the ecoff
15434 symbol table (in the mdebug section). */
15437 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15440 if (IS_ELF && !ECOFF_DEBUGGING)
15444 if (cur_proc_ptr == (procS *) NULL)
15446 as_warn (_(".frame outside of .ent"));
15447 demand_empty_rest_of_line ();
15451 cur_proc_ptr->frame_reg = tc_get_register (1);
15453 SKIP_WHITESPACE ();
15454 if (*input_line_pointer++ != ','
15455 || get_absolute_expression_and_terminator (&val) != ',')
15457 as_warn (_("Bad .frame directive"));
15458 --input_line_pointer;
15459 demand_empty_rest_of_line ();
15463 cur_proc_ptr->frame_offset = val;
15464 cur_proc_ptr->pc_reg = tc_get_register (0);
15466 demand_empty_rest_of_line ();
15469 #endif /* OBJ_ELF */
15473 /* The .fmask and .mask directives. If the mdebug section is present
15474 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15475 embedded targets, s_mips_mask is used so that we can set the PDR
15476 information correctly. We can't use the ecoff routines because they
15477 make reference to the ecoff symbol table (in the mdebug section). */
15480 s_mips_mask (int reg_type)
15483 if (IS_ELF && !ECOFF_DEBUGGING)
15487 if (cur_proc_ptr == (procS *) NULL)
15489 as_warn (_(".mask/.fmask outside of .ent"));
15490 demand_empty_rest_of_line ();
15494 if (get_absolute_expression_and_terminator (&mask) != ',')
15496 as_warn (_("Bad .mask/.fmask directive"));
15497 --input_line_pointer;
15498 demand_empty_rest_of_line ();
15502 off = get_absolute_expression ();
15504 if (reg_type == 'F')
15506 cur_proc_ptr->fpreg_mask = mask;
15507 cur_proc_ptr->fpreg_offset = off;
15511 cur_proc_ptr->reg_mask = mask;
15512 cur_proc_ptr->reg_offset = off;
15515 demand_empty_rest_of_line ();
15518 #endif /* OBJ_ELF */
15519 s_ignore (reg_type);
15522 /* A table describing all the processors gas knows about. Names are
15523 matched in the order listed.
15525 To ease comparison, please keep this table in the same order as
15526 gcc's mips_cpu_info_table[]. */
15527 static const struct mips_cpu_info mips_cpu_info_table[] =
15529 /* Entries for generic ISAs */
15530 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15531 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15532 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15533 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15534 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15535 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15536 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15537 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15538 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15541 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15542 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15543 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15546 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15549 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15550 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15551 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15552 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15553 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15554 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15555 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15556 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15557 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15558 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15559 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15560 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15561 /* ST Microelectronics Loongson 2E and 2F cores */
15562 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15563 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15566 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15567 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15568 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15569 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15570 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15571 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15572 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15573 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15574 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15575 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15576 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15577 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15578 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15579 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15580 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15583 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15584 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15585 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15586 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15588 /* MIPS 32 Release 2 */
15589 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15590 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15591 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15592 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15593 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15594 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15595 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15596 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15597 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15598 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15599 /* Deprecated forms of the above. */
15600 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15601 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15602 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15603 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15604 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15605 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15606 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15607 /* Deprecated forms of the above. */
15608 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15609 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15610 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15611 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15612 ISA_MIPS32R2, CPU_MIPS32R2 },
15613 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15614 ISA_MIPS32R2, CPU_MIPS32R2 },
15615 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15616 ISA_MIPS32R2, CPU_MIPS32R2 },
15617 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15618 ISA_MIPS32R2, CPU_MIPS32R2 },
15619 /* Deprecated forms of the above. */
15620 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15621 ISA_MIPS32R2, CPU_MIPS32R2 },
15622 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15623 ISA_MIPS32R2, CPU_MIPS32R2 },
15624 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15625 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15626 ISA_MIPS32R2, CPU_MIPS32R2 },
15627 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15628 ISA_MIPS32R2, CPU_MIPS32R2 },
15629 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15630 ISA_MIPS32R2, CPU_MIPS32R2 },
15631 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15632 ISA_MIPS32R2, CPU_MIPS32R2 },
15633 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15634 ISA_MIPS32R2, CPU_MIPS32R2 },
15635 /* Deprecated forms of the above. */
15636 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15637 ISA_MIPS32R2, CPU_MIPS32R2 },
15638 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15639 ISA_MIPS32R2, CPU_MIPS32R2 },
15640 /* 1004K cores are multiprocessor versions of the 34K. */
15641 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15642 ISA_MIPS32R2, CPU_MIPS32R2 },
15643 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15644 ISA_MIPS32R2, CPU_MIPS32R2 },
15645 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15646 ISA_MIPS32R2, CPU_MIPS32R2 },
15647 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15648 ISA_MIPS32R2, CPU_MIPS32R2 },
15651 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15652 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15653 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15654 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15656 /* Broadcom SB-1 CPU core */
15657 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15658 ISA_MIPS64, CPU_SB1 },
15659 /* Broadcom SB-1A CPU core */
15660 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15661 ISA_MIPS64, CPU_SB1 },
15663 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15665 /* MIPS 64 Release 2 */
15667 /* Cavium Networks Octeon CPU core */
15668 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15671 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15678 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15679 with a final "000" replaced by "k". Ignore case.
15681 Note: this function is shared between GCC and GAS. */
15684 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15686 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15687 given++, canonical++;
15689 return ((*given == 0 && *canonical == 0)
15690 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15694 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15695 CPU name. We've traditionally allowed a lot of variation here.
15697 Note: this function is shared between GCC and GAS. */
15700 mips_matching_cpu_name_p (const char *canonical, const char *given)
15702 /* First see if the name matches exactly, or with a final "000"
15703 turned into "k". */
15704 if (mips_strict_matching_cpu_name_p (canonical, given))
15707 /* If not, try comparing based on numerical designation alone.
15708 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15709 if (TOLOWER (*given) == 'r')
15711 if (!ISDIGIT (*given))
15714 /* Skip over some well-known prefixes in the canonical name,
15715 hoping to find a number there too. */
15716 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15718 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15720 else if (TOLOWER (canonical[0]) == 'r')
15723 return mips_strict_matching_cpu_name_p (canonical, given);
15727 /* Parse an option that takes the name of a processor as its argument.
15728 OPTION is the name of the option and CPU_STRING is the argument.
15729 Return the corresponding processor enumeration if the CPU_STRING is
15730 recognized, otherwise report an error and return null.
15732 A similar function exists in GCC. */
15734 static const struct mips_cpu_info *
15735 mips_parse_cpu (const char *option, const char *cpu_string)
15737 const struct mips_cpu_info *p;
15739 /* 'from-abi' selects the most compatible architecture for the given
15740 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15741 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15742 version. Look first at the -mgp options, if given, otherwise base
15743 the choice on MIPS_DEFAULT_64BIT.
15745 Treat NO_ABI like the EABIs. One reason to do this is that the
15746 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15747 architecture. This code picks MIPS I for 'mips' and MIPS III for
15748 'mips64', just as we did in the days before 'from-abi'. */
15749 if (strcasecmp (cpu_string, "from-abi") == 0)
15751 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15752 return mips_cpu_info_from_isa (ISA_MIPS1);
15754 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15755 return mips_cpu_info_from_isa (ISA_MIPS3);
15757 if (file_mips_gp32 >= 0)
15758 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15760 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15765 /* 'default' has traditionally been a no-op. Probably not very useful. */
15766 if (strcasecmp (cpu_string, "default") == 0)
15769 for (p = mips_cpu_info_table; p->name != 0; p++)
15770 if (mips_matching_cpu_name_p (p->name, cpu_string))
15773 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15777 /* Return the canonical processor information for ISA (a member of the
15778 ISA_MIPS* enumeration). */
15780 static const struct mips_cpu_info *
15781 mips_cpu_info_from_isa (int isa)
15785 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15786 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15787 && isa == mips_cpu_info_table[i].isa)
15788 return (&mips_cpu_info_table[i]);
15793 static const struct mips_cpu_info *
15794 mips_cpu_info_from_arch (int arch)
15798 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15799 if (arch == mips_cpu_info_table[i].cpu)
15800 return (&mips_cpu_info_table[i]);
15806 show (FILE *stream, const char *string, int *col_p, int *first_p)
15810 fprintf (stream, "%24s", "");
15815 fprintf (stream, ", ");
15819 if (*col_p + strlen (string) > 72)
15821 fprintf (stream, "\n%24s", "");
15825 fprintf (stream, "%s", string);
15826 *col_p += strlen (string);
15832 md_show_usage (FILE *stream)
15837 fprintf (stream, _("\
15839 -EB generate big endian output\n\
15840 -EL generate little endian output\n\
15841 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15842 -G NUM allow referencing objects up to NUM bytes\n\
15843 implicitly with the gp register [default 8]\n"));
15844 fprintf (stream, _("\
15845 -mips1 generate MIPS ISA I instructions\n\
15846 -mips2 generate MIPS ISA II instructions\n\
15847 -mips3 generate MIPS ISA III instructions\n\
15848 -mips4 generate MIPS ISA IV instructions\n\
15849 -mips5 generate MIPS ISA V instructions\n\
15850 -mips32 generate MIPS32 ISA instructions\n\
15851 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15852 -mips64 generate MIPS64 ISA instructions\n\
15853 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15854 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15858 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15859 show (stream, mips_cpu_info_table[i].name, &column, &first);
15860 show (stream, "from-abi", &column, &first);
15861 fputc ('\n', stream);
15863 fprintf (stream, _("\
15864 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15865 -no-mCPU don't generate code specific to CPU.\n\
15866 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15870 show (stream, "3900", &column, &first);
15871 show (stream, "4010", &column, &first);
15872 show (stream, "4100", &column, &first);
15873 show (stream, "4650", &column, &first);
15874 fputc ('\n', stream);
15876 fprintf (stream, _("\
15877 -mips16 generate mips16 instructions\n\
15878 -no-mips16 do not generate mips16 instructions\n"));
15879 fprintf (stream, _("\
15880 -msmartmips generate smartmips instructions\n\
15881 -mno-smartmips do not generate smartmips instructions\n"));
15882 fprintf (stream, _("\
15883 -mdsp generate DSP instructions\n\
15884 -mno-dsp do not generate DSP instructions\n"));
15885 fprintf (stream, _("\
15886 -mdspr2 generate DSP R2 instructions\n\
15887 -mno-dspr2 do not generate DSP R2 instructions\n"));
15888 fprintf (stream, _("\
15889 -mmt generate MT instructions\n\
15890 -mno-mt do not generate MT instructions\n"));
15891 fprintf (stream, _("\
15892 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15893 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15894 -mfix-vr4120 work around certain VR4120 errata\n\
15895 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15896 -mfix-24k insert a nop after ERET and DERET instructions\n\
15897 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15898 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15899 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15900 -msym32 assume all symbols have 32-bit values\n\
15901 -O0 remove unneeded NOPs, do not swap branches\n\
15902 -O remove unneeded NOPs and swap branches\n\
15903 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15904 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15905 fprintf (stream, _("\
15906 -mhard-float allow floating-point instructions\n\
15907 -msoft-float do not allow floating-point instructions\n\
15908 -msingle-float only allow 32-bit floating-point operations\n\
15909 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15910 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15913 fprintf (stream, _("\
15914 -KPIC, -call_shared generate SVR4 position independent code\n\
15915 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15916 -mvxworks-pic generate VxWorks position independent code\n\
15917 -non_shared do not generate code that can operate with DSOs\n\
15918 -xgot assume a 32 bit GOT\n\
15919 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15920 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15921 position dependent (non shared) code\n\
15922 -mabi=ABI create ABI conformant object file for:\n"));
15926 show (stream, "32", &column, &first);
15927 show (stream, "o64", &column, &first);
15928 show (stream, "n32", &column, &first);
15929 show (stream, "64", &column, &first);
15930 show (stream, "eabi", &column, &first);
15932 fputc ('\n', stream);
15934 fprintf (stream, _("\
15935 -32 create o32 ABI object file (default)\n\
15936 -n32 create n32 ABI object file\n\
15937 -64 create 64 ABI object file\n"));
15943 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15945 if (HAVE_64BIT_SYMBOLS)
15946 return dwarf2_format_64bit_irix;
15948 return dwarf2_format_32bit;
15953 mips_dwarf2_addr_size (void)
15955 if (HAVE_64BIT_OBJECTS)
15961 /* Standard calling conventions leave the CFA at SP on entry. */
15963 mips_cfi_frame_initial_instructions (void)
15965 cfi_add_CFA_def_cfa_register (SP);
15969 tc_mips_regname_to_dw2regnum (char *regname)
15971 unsigned int regnum = -1;
15974 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))