1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* Whether the processor uses hardware interlocks to protect
329 reads from the HI and LO registers, and thus does not
330 require nops to be inserted. */
332 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
333 || mips_opts.arch == CPU_VR5500 \
334 || mips_opts.arch == CPU_RM7000 \
335 || mips_opts.arch == CPU_SB1 \
338 /* Whether the processor uses hardware interlocks to protect reads
339 from the GPRs after they are loaded from memory, and thus does not
340 require nops to be inserted. This applies to instructions marked
341 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
343 #define gpr_interlocks \
344 (mips_opts.isa != ISA_MIPS1 \
345 || mips_opts.arch == CPU_VR5400 \
346 || mips_opts.arch == CPU_VR5500 \
347 || mips_opts.arch == CPU_R3900)
349 /* Whether the processor uses hardware interlocks to avoid delays
350 required by coprocessor instructions, and thus does not require
351 nops to be inserted. This applies to instructions marked
352 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
353 between instructions marked INSN_WRITE_COND_CODE and ones marked
354 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
355 levels I, II, and III. */
356 /* Itbl support may require additional care here. */
357 #define cop_interlocks \
358 ((mips_opts.isa != ISA_MIPS1 \
359 && mips_opts.isa != ISA_MIPS2 \
360 && mips_opts.isa != ISA_MIPS3) \
361 || mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Whether the processor uses hardware interlocks to protect reads
368 from coprocessor registers after they are loaded from memory, and
369 thus does not require nops to be inserted. This applies to
370 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
371 requires at MIPS ISA level I. */
372 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
374 /* Is this a mfhi or mflo instruction? */
375 #define MF_HILO_INSN(PINFO) \
376 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
378 /* MIPS PIC level. */
380 enum mips_pic_level mips_pic;
382 /* 1 if we should generate 32 bit offsets from the $gp register in
383 SVR4_PIC mode. Currently has no meaning in other modes. */
384 static int mips_big_got = 0;
386 /* 1 if trap instructions should used for overflow rather than break
388 static int mips_trap = 0;
390 /* 1 if double width floating point constants should not be constructed
391 by assembling two single width halves into two single width floating
392 point registers which just happen to alias the double width destination
393 register. On some architectures this aliasing can be disabled by a bit
394 in the status register, and the setting of this bit cannot be determined
395 automatically at assemble time. */
396 static int mips_disable_float_construction;
398 /* Non-zero if any .set noreorder directives were used. */
400 static int mips_any_noreorder;
402 /* Non-zero if nops should be inserted when the register referenced in
403 an mfhi/mflo instruction is read in the next two instructions. */
404 static int mips_7000_hilo_fix;
406 /* The size of the small data section. */
407 static unsigned int g_switch_value = 8;
408 /* Whether the -G option was used. */
409 static int g_switch_seen = 0;
414 /* If we can determine in advance that GP optimization won't be
415 possible, we can skip the relaxation stuff that tries to produce
416 GP-relative references. This makes delay slot optimization work
419 This function can only provide a guess, but it seems to work for
420 gcc output. It needs to guess right for gcc, otherwise gcc
421 will put what it thinks is a GP-relative instruction in a branch
424 I don't know if a fix is needed for the SVR4_PIC mode. I've only
425 fixed it for the non-PIC mode. KR 95/04/07 */
426 static int nopic_need_relax (symbolS *, int);
428 /* handle of the OPCODE hash table */
429 static struct hash_control *op_hash = NULL;
431 /* The opcode hash table we use for the mips16. */
432 static struct hash_control *mips16_op_hash = NULL;
434 /* This array holds the chars that always start a comment. If the
435 pre-processor is disabled, these aren't very useful */
436 const char comment_chars[] = "#";
438 /* This array holds the chars that only start a comment at the beginning of
439 a line. If the line seems to have the form '# 123 filename'
440 .line and .file directives will appear in the pre-processed output */
441 /* Note that input_file.c hand checks for '#' at the beginning of the
442 first line of the input file. This is because the compiler outputs
443 #NO_APP at the beginning of its output. */
444 /* Also note that C style comments are always supported. */
445 const char line_comment_chars[] = "#";
447 /* This array holds machine specific line separator characters. */
448 const char line_separator_chars[] = ";";
450 /* Chars that can be used to separate mant from exp in floating point nums */
451 const char EXP_CHARS[] = "eE";
453 /* Chars that mean this number is a floating point constant */
456 const char FLT_CHARS[] = "rRsSfFdDxXpP";
458 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
459 changed in read.c . Ideally it shouldn't have to know about it at all,
460 but nothing is ideal around here.
463 static char *insn_error;
465 static int auto_align = 1;
467 /* When outputting SVR4 PIC code, the assembler needs to know the
468 offset in the stack frame from which to restore the $gp register.
469 This is set by the .cprestore pseudo-op, and saved in this
471 static offsetT mips_cprestore_offset = -1;
473 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
474 more optimizations, it can use a register value instead of a memory-saved
475 offset and even an other register than $gp as global pointer. */
476 static offsetT mips_cpreturn_offset = -1;
477 static int mips_cpreturn_register = -1;
478 static int mips_gp_register = GP;
479 static int mips_gprel_offset = 0;
481 /* Whether mips_cprestore_offset has been set in the current function
482 (or whether it has already been warned about, if not). */
483 static int mips_cprestore_valid = 0;
485 /* This is the register which holds the stack frame, as set by the
486 .frame pseudo-op. This is needed to implement .cprestore. */
487 static int mips_frame_reg = SP;
489 /* Whether mips_frame_reg has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_frame_reg_valid = 0;
493 /* To output NOP instructions correctly, we need to keep information
494 about the previous two instructions. */
496 /* Whether we are optimizing. The default value of 2 means to remove
497 unneeded NOPs and swap branch instructions when possible. A value
498 of 1 means to not swap branches. A value of 0 means to always
500 static int mips_optimize = 2;
502 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
503 equivalent to seeing no -g option at all. */
504 static int mips_debug = 0;
506 /* The previous instruction. */
507 static struct mips_cl_insn prev_insn;
509 /* The instruction before prev_insn. */
510 static struct mips_cl_insn prev_prev_insn;
512 /* If we don't want information for prev_insn or prev_prev_insn, we
513 point the insn_mo field at this dummy integer. */
514 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
516 /* Non-zero if prev_insn is valid. */
517 static int prev_insn_valid;
519 /* The frag for the previous instruction. */
520 static struct frag *prev_insn_frag;
522 /* The offset into prev_insn_frag for the previous instruction. */
523 static long prev_insn_where;
525 /* The reloc type for the previous instruction, if any. */
526 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
528 /* The reloc for the previous instruction, if any. */
529 static fixS *prev_insn_fixp[3];
531 /* Non-zero if the previous instruction was in a delay slot. */
532 static int prev_insn_is_delay_slot;
534 /* Non-zero if the previous instruction was in a .set noreorder. */
535 static int prev_insn_unreordered;
537 /* Non-zero if the previous instruction uses an extend opcode (if
539 static int prev_insn_extended;
541 /* Non-zero if the previous previous instruction was in a .set
543 static int prev_prev_insn_unreordered;
545 /* If this is set, it points to a frag holding nop instructions which
546 were inserted before the start of a noreorder section. If those
547 nops turn out to be unnecessary, the size of the frag can be
549 static fragS *prev_nop_frag;
551 /* The number of nop instructions we created in prev_nop_frag. */
552 static int prev_nop_frag_holds;
554 /* The number of nop instructions that we know we need in
556 static int prev_nop_frag_required;
558 /* The number of instructions we've seen since prev_nop_frag. */
559 static int prev_nop_frag_since;
561 /* For ECOFF and ELF, relocations against symbols are done in two
562 parts, with a HI relocation and a LO relocation. Each relocation
563 has only 16 bits of space to store an addend. This means that in
564 order for the linker to handle carries correctly, it must be able
565 to locate both the HI and the LO relocation. This means that the
566 relocations must appear in order in the relocation table.
568 In order to implement this, we keep track of each unmatched HI
569 relocation. We then sort them so that they immediately precede the
570 corresponding LO relocation. */
575 struct mips_hi_fixup *next;
578 /* The section this fixup is in. */
582 /* The list of unmatched HI relocs. */
584 static struct mips_hi_fixup *mips_hi_fixup_list;
586 /* The frag containing the last explicit relocation operator.
587 Null if explicit relocations have not been used. */
589 static fragS *prev_reloc_op_frag;
591 /* Map normal MIPS register numbers to mips16 register numbers. */
593 #define X ILLEGAL_REG
594 static const int mips32_to_16_reg_map[] =
596 X, X, 2, 3, 4, 5, 6, 7,
597 X, X, X, X, X, X, X, X,
598 0, 1, X, X, X, X, X, X,
599 X, X, X, X, X, X, X, X
603 /* Map mips16 register numbers to normal MIPS register numbers. */
605 static const unsigned int mips16_to_32_reg_map[] =
607 16, 17, 2, 3, 4, 5, 6, 7
610 static int mips_fix_4122_bugs;
612 /* We don't relax branches by default, since this causes us to expand
613 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
614 fail to compute the offset before expanding the macro to the most
615 efficient expansion. */
617 static int mips_relax_branch;
619 /* Since the MIPS does not have multiple forms of PC relative
620 instructions, we do not have to do relaxing as is done on other
621 platforms. However, we do have to handle GP relative addressing
622 correctly, which turns out to be a similar problem.
624 Every macro that refers to a symbol can occur in (at least) two
625 forms, one with GP relative addressing and one without. For
626 example, loading a global variable into a register generally uses
627 a macro instruction like this:
629 If i can be addressed off the GP register (this is true if it is in
630 the .sbss or .sdata section, or if it is known to be smaller than
631 the -G argument) this will generate the following instruction:
633 This instruction will use a GPREL reloc. If i can not be addressed
634 off the GP register, the following instruction sequence will be used:
637 In this case the first instruction will have a HI16 reloc, and the
638 second reloc will have a LO16 reloc. Both relocs will be against
641 The issue here is that we may not know whether i is GP addressable
642 until after we see the instruction that uses it. Therefore, we
643 want to be able to choose the final instruction sequence only at
644 the end of the assembly. This is similar to the way other
645 platforms choose the size of a PC relative instruction only at the
648 When generating position independent code we do not use GP
649 addressing in quite the same way, but the issue still arises as
650 external symbols and local symbols must be handled differently.
652 We handle these issues by actually generating both possible
653 instruction sequences. The longer one is put in a frag_var with
654 type rs_machine_dependent. We encode what to do with the frag in
655 the subtype field. We encode (1) the number of existing bytes to
656 replace, (2) the number of new bytes to use, (3) the offset from
657 the start of the existing bytes to the first reloc we must generate
658 (that is, the offset is applied from the start of the existing
659 bytes after they are replaced by the new bytes, if any), (4) the
660 offset from the start of the existing bytes to the second reloc,
661 (5) whether a third reloc is needed (the third reloc is always four
662 bytes after the second reloc), and (6) whether to warn if this
663 variant is used (this is sometimes needed if .set nomacro or .set
664 noat is in effect). All these numbers are reasonably small.
666 Generating two instruction sequences must be handled carefully to
667 ensure that delay slots are handled correctly. Fortunately, there
668 are a limited number of cases. When the second instruction
669 sequence is generated, append_insn is directed to maintain the
670 existing delay slot information, so it continues to apply to any
671 code after the second instruction sequence. This means that the
672 second instruction sequence must not impose any requirements not
673 required by the first instruction sequence.
675 These variant frags are then handled in functions called by the
676 machine independent code. md_estimate_size_before_relax returns
677 the final size of the frag. md_convert_frag sets up the final form
678 of the frag. tc_gen_reloc adjust the first reloc and adds a second
680 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
684 | (((reloc1) + 64) << 9) \
685 | (((reloc2) + 64) << 2) \
686 | ((reloc3) ? (1 << 1) : 0) \
688 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
689 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
690 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
691 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
692 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
693 #define RELAX_WARN(i) ((i) & 1)
695 /* Branch without likely bit. If label is out of range, we turn:
697 beq reg1, reg2, label
707 with the following opcode replacements:
714 bltzal <-> bgezal (with jal label instead of j label)
716 Even though keeping the delay slot instruction in the delay slot of
717 the branch would be more efficient, it would be very tricky to do
718 correctly, because we'd have to introduce a variable frag *after*
719 the delay slot instruction, and expand that instead. Let's do it
720 the easy way for now, even if the branch-not-taken case now costs
721 one additional instruction. Out-of-range branches are not supposed
722 to be common, anyway.
724 Branch likely. If label is out of range, we turn:
726 beql reg1, reg2, label
727 delay slot (annulled if branch not taken)
736 delay slot (executed only if branch taken)
739 It would be possible to generate a shorter sequence by losing the
740 likely bit, generating something like:
745 delay slot (executed only if branch taken)
757 bltzall -> bgezal (with jal label instead of j label)
758 bgezall -> bltzal (ditto)
761 but it's not clear that it would actually improve performance. */
762 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
765 | ((toofar) ? 1 : 0) \
767 | ((likely) ? 4 : 0) \
768 | ((uncond) ? 8 : 0)))
769 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
770 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
771 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
772 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
773 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
775 /* For mips16 code, we use an entirely different form of relaxation.
776 mips16 supports two versions of most instructions which take
777 immediate values: a small one which takes some small value, and a
778 larger one which takes a 16 bit value. Since branches also follow
779 this pattern, relaxing these values is required.
781 We can assemble both mips16 and normal MIPS code in a single
782 object. Therefore, we need to support this type of relaxation at
783 the same time that we support the relaxation described above. We
784 use the high bit of the subtype field to distinguish these cases.
786 The information we store for this type of relaxation is the
787 argument code found in the opcode file for this relocation, whether
788 the user explicitly requested a small or extended form, and whether
789 the relocation is in a jump or jal delay slot. That tells us the
790 size of the value, and how it should be stored. We also store
791 whether the fragment is considered to be extended or not. We also
792 store whether this is known to be a branch to a different section,
793 whether we have tried to relax this frag yet, and whether we have
794 ever extended a PC relative fragment because of a shift count. */
795 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
798 | ((small) ? 0x100 : 0) \
799 | ((ext) ? 0x200 : 0) \
800 | ((dslot) ? 0x400 : 0) \
801 | ((jal_dslot) ? 0x800 : 0))
802 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
803 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
804 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
805 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
806 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
807 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
808 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
809 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
810 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
811 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
812 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
813 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
815 /* Is the given value a sign-extended 32-bit value? */
816 #define IS_SEXT_32BIT_NUM(x) \
817 (((x) &~ (offsetT) 0x7fffffff) == 0 \
818 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
820 /* Is the given value a sign-extended 16-bit value? */
821 #define IS_SEXT_16BIT_NUM(x) \
822 (((x) &~ (offsetT) 0x7fff) == 0 \
823 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
826 /* Prototypes for static functions. */
828 #define internalError() \
829 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
831 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
833 static void append_insn
834 (char *place, struct mips_cl_insn *ip, expressionS *p,
835 bfd_reloc_code_real_type *r);
836 static void mips_no_prev_insn (int);
837 static void mips16_macro_build
838 (char *, int *, expressionS *, const char *, const char *, va_list);
839 static void load_register (int *, int, expressionS *, int);
840 static void macro (struct mips_cl_insn * ip);
841 static void mips16_macro (struct mips_cl_insn * ip);
842 #ifdef LOSING_COMPILER
843 static void macro2 (struct mips_cl_insn * ip);
845 static void mips_ip (char *str, struct mips_cl_insn * ip);
846 static void mips16_ip (char *str, struct mips_cl_insn * ip);
847 static void mips16_immed
848 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
849 unsigned long *, bfd_boolean *, unsigned short *);
850 static size_t my_getSmallExpression
851 (expressionS *, bfd_reloc_code_real_type *, char *);
852 static void my_getExpression (expressionS *, char *);
853 static void s_align (int);
854 static void s_change_sec (int);
855 static void s_change_section (int);
856 static void s_cons (int);
857 static void s_float_cons (int);
858 static void s_mips_globl (int);
859 static void s_option (int);
860 static void s_mipsset (int);
861 static void s_abicalls (int);
862 static void s_cpload (int);
863 static void s_cpsetup (int);
864 static void s_cplocal (int);
865 static void s_cprestore (int);
866 static void s_cpreturn (int);
867 static void s_gpvalue (int);
868 static void s_gpword (int);
869 static void s_gpdword (int);
870 static void s_cpadd (int);
871 static void s_insn (int);
872 static void md_obj_begin (void);
873 static void md_obj_end (void);
874 static void s_mips_ent (int);
875 static void s_mips_end (int);
876 static void s_mips_frame (int);
877 static void s_mips_mask (int reg_type);
878 static void s_mips_stab (int);
879 static void s_mips_weakext (int);
880 static void s_mips_file (int);
881 static void s_mips_loc (int);
882 static bfd_boolean pic_need_relax (symbolS *, asection *);
883 static int relaxed_branch_length (fragS *, asection *, int);
884 static int validate_mips_insn (const struct mips_opcode *);
886 /* Table and functions used to map between CPU/ISA names, and
887 ISA levels, and CPU numbers. */
891 const char *name; /* CPU or ISA name. */
892 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
893 int isa; /* ISA level. */
894 int cpu; /* CPU number (default CPU if ISA). */
897 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
898 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
899 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
903 The following pseudo-ops from the Kane and Heinrich MIPS book
904 should be defined here, but are currently unsupported: .alias,
905 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
907 The following pseudo-ops from the Kane and Heinrich MIPS book are
908 specific to the type of debugging information being generated, and
909 should be defined by the object format: .aent, .begin, .bend,
910 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
913 The following pseudo-ops from the Kane and Heinrich MIPS book are
914 not MIPS CPU specific, but are also not specific to the object file
915 format. This file is probably the best place to define them, but
916 they are not currently supported: .asm0, .endr, .lab, .repeat,
919 static const pseudo_typeS mips_pseudo_table[] =
921 /* MIPS specific pseudo-ops. */
922 {"option", s_option, 0},
923 {"set", s_mipsset, 0},
924 {"rdata", s_change_sec, 'r'},
925 {"sdata", s_change_sec, 's'},
926 {"livereg", s_ignore, 0},
927 {"abicalls", s_abicalls, 0},
928 {"cpload", s_cpload, 0},
929 {"cpsetup", s_cpsetup, 0},
930 {"cplocal", s_cplocal, 0},
931 {"cprestore", s_cprestore, 0},
932 {"cpreturn", s_cpreturn, 0},
933 {"gpvalue", s_gpvalue, 0},
934 {"gpword", s_gpword, 0},
935 {"gpdword", s_gpdword, 0},
936 {"cpadd", s_cpadd, 0},
939 /* Relatively generic pseudo-ops that happen to be used on MIPS
941 {"asciiz", stringer, 1},
942 {"bss", s_change_sec, 'b'},
945 {"dword", s_cons, 3},
946 {"weakext", s_mips_weakext, 0},
948 /* These pseudo-ops are defined in read.c, but must be overridden
949 here for one reason or another. */
950 {"align", s_align, 0},
952 {"data", s_change_sec, 'd'},
953 {"double", s_float_cons, 'd'},
954 {"float", s_float_cons, 'f'},
955 {"globl", s_mips_globl, 0},
956 {"global", s_mips_globl, 0},
957 {"hword", s_cons, 1},
962 {"section", s_change_section, 0},
963 {"short", s_cons, 1},
964 {"single", s_float_cons, 'f'},
965 {"stabn", s_mips_stab, 'n'},
966 {"text", s_change_sec, 't'},
969 { "extern", ecoff_directive_extern, 0},
974 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
976 /* These pseudo-ops should be defined by the object file format.
977 However, a.out doesn't support them, so we have versions here. */
978 {"aent", s_mips_ent, 1},
979 {"bgnb", s_ignore, 0},
980 {"end", s_mips_end, 0},
981 {"endb", s_ignore, 0},
982 {"ent", s_mips_ent, 0},
983 {"file", s_mips_file, 0},
984 {"fmask", s_mips_mask, 'F'},
985 {"frame", s_mips_frame, 0},
986 {"loc", s_mips_loc, 0},
987 {"mask", s_mips_mask, 'R'},
988 {"verstamp", s_ignore, 0},
992 extern void pop_insert (const pseudo_typeS *);
995 mips_pop_insert (void)
997 pop_insert (mips_pseudo_table);
998 if (! ECOFF_DEBUGGING)
999 pop_insert (mips_nonecoff_pseudo_table);
1002 /* Symbols labelling the current insn. */
1004 struct insn_label_list
1006 struct insn_label_list *next;
1010 static struct insn_label_list *insn_labels;
1011 static struct insn_label_list *free_insn_labels;
1013 static void mips_clear_insn_labels (void);
1016 mips_clear_insn_labels (void)
1018 register struct insn_label_list **pl;
1020 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1026 static char *expr_end;
1028 /* Expressions which appear in instructions. These are set by
1031 static expressionS imm_expr;
1032 static expressionS imm2_expr;
1033 static expressionS offset_expr;
1035 /* Relocs associated with imm_expr and offset_expr. */
1037 static bfd_reloc_code_real_type imm_reloc[3]
1038 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1039 static bfd_reloc_code_real_type offset_reloc[3]
1040 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1042 /* These are set by mips16_ip if an explicit extension is used. */
1044 static bfd_boolean mips16_small, mips16_ext;
1047 /* The pdr segment for per procedure frame/regmask info. Not used for
1050 static segT pdr_seg;
1053 /* The default target format to use. */
1056 mips_target_format (void)
1058 switch (OUTPUT_FLAVOR)
1060 case bfd_target_aout_flavour:
1061 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1062 case bfd_target_ecoff_flavour:
1063 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1064 case bfd_target_coff_flavour:
1066 case bfd_target_elf_flavour:
1068 /* This is traditional mips. */
1069 return (target_big_endian
1070 ? (HAVE_64BIT_OBJECTS
1071 ? "elf64-tradbigmips"
1073 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1074 : (HAVE_64BIT_OBJECTS
1075 ? "elf64-tradlittlemips"
1077 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1079 return (target_big_endian
1080 ? (HAVE_64BIT_OBJECTS
1083 ? "elf32-nbigmips" : "elf32-bigmips"))
1084 : (HAVE_64BIT_OBJECTS
1085 ? "elf64-littlemips"
1087 ? "elf32-nlittlemips" : "elf32-littlemips")));
1095 /* This function is called once, at assembler startup time. It should
1096 set up all the tables, etc. that the MD part of the assembler will need. */
1101 register const char *retval = NULL;
1105 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1106 as_warn (_("Could not set architecture and machine"));
1108 op_hash = hash_new ();
1110 for (i = 0; i < NUMOPCODES;)
1112 const char *name = mips_opcodes[i].name;
1114 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1117 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1118 mips_opcodes[i].name, retval);
1119 /* Probably a memory allocation problem? Give up now. */
1120 as_fatal (_("Broken assembler. No assembly attempted."));
1124 if (mips_opcodes[i].pinfo != INSN_MACRO)
1126 if (!validate_mips_insn (&mips_opcodes[i]))
1131 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1134 mips16_op_hash = hash_new ();
1137 while (i < bfd_mips16_num_opcodes)
1139 const char *name = mips16_opcodes[i].name;
1141 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1143 as_fatal (_("internal: can't hash `%s': %s"),
1144 mips16_opcodes[i].name, retval);
1147 if (mips16_opcodes[i].pinfo != INSN_MACRO
1148 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1149 != mips16_opcodes[i].match))
1151 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1152 mips16_opcodes[i].name, mips16_opcodes[i].args);
1157 while (i < bfd_mips16_num_opcodes
1158 && strcmp (mips16_opcodes[i].name, name) == 0);
1162 as_fatal (_("Broken assembler. No assembly attempted."));
1164 /* We add all the general register names to the symbol table. This
1165 helps us detect invalid uses of them. */
1166 for (i = 0; i < 32; i++)
1170 sprintf (buf, "$%d", i);
1171 symbol_table_insert (symbol_new (buf, reg_section, i,
1172 &zero_address_frag));
1174 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1175 &zero_address_frag));
1176 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1177 &zero_address_frag));
1178 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1179 &zero_address_frag));
1180 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1181 &zero_address_frag));
1182 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1183 &zero_address_frag));
1184 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1185 &zero_address_frag));
1186 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1187 &zero_address_frag));
1188 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1189 &zero_address_frag));
1190 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1191 &zero_address_frag));
1193 /* If we don't add these register names to the symbol table, they
1194 may end up being added as regular symbols by operand(), and then
1195 make it to the object file as undefined in case they're not
1196 regarded as local symbols. They're local in o32, since `$' is a
1197 local symbol prefix, but not in n32 or n64. */
1198 for (i = 0; i < 8; i++)
1202 sprintf (buf, "$fcc%i", i);
1203 symbol_table_insert (symbol_new (buf, reg_section, -1,
1204 &zero_address_frag));
1207 mips_no_prev_insn (FALSE);
1210 mips_cprmask[0] = 0;
1211 mips_cprmask[1] = 0;
1212 mips_cprmask[2] = 0;
1213 mips_cprmask[3] = 0;
1215 /* set the default alignment for the text section (2**2) */
1216 record_alignment (text_section, 2);
1218 if (USE_GLOBAL_POINTER_OPT)
1219 bfd_set_gp_size (stdoutput, g_switch_value);
1221 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1223 /* On a native system, sections must be aligned to 16 byte
1224 boundaries. When configured for an embedded ELF target, we
1226 if (strcmp (TARGET_OS, "elf") != 0)
1228 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1229 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1230 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1233 /* Create a .reginfo section for register masks and a .mdebug
1234 section for debugging information. */
1242 subseg = now_subseg;
1244 /* The ABI says this section should be loaded so that the
1245 running program can access it. However, we don't load it
1246 if we are configured for an embedded target */
1247 flags = SEC_READONLY | SEC_DATA;
1248 if (strcmp (TARGET_OS, "elf") != 0)
1249 flags |= SEC_ALLOC | SEC_LOAD;
1251 if (mips_abi != N64_ABI)
1253 sec = subseg_new (".reginfo", (subsegT) 0);
1255 bfd_set_section_flags (stdoutput, sec, flags);
1256 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1259 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1264 /* The 64-bit ABI uses a .MIPS.options section rather than
1265 .reginfo section. */
1266 sec = subseg_new (".MIPS.options", (subsegT) 0);
1267 bfd_set_section_flags (stdoutput, sec, flags);
1268 bfd_set_section_alignment (stdoutput, sec, 3);
1271 /* Set up the option header. */
1273 Elf_Internal_Options opthdr;
1276 opthdr.kind = ODK_REGINFO;
1277 opthdr.size = (sizeof (Elf_External_Options)
1278 + sizeof (Elf64_External_RegInfo));
1281 f = frag_more (sizeof (Elf_External_Options));
1282 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1283 (Elf_External_Options *) f);
1285 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1290 if (ECOFF_DEBUGGING)
1292 sec = subseg_new (".mdebug", (subsegT) 0);
1293 (void) bfd_set_section_flags (stdoutput, sec,
1294 SEC_HAS_CONTENTS | SEC_READONLY);
1295 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1298 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1300 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1301 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1302 SEC_READONLY | SEC_RELOC
1304 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1308 subseg_set (seg, subseg);
1312 if (! ECOFF_DEBUGGING)
1319 if (! ECOFF_DEBUGGING)
1324 md_assemble (char *str)
1326 struct mips_cl_insn insn;
1327 bfd_reloc_code_real_type unused_reloc[3]
1328 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1330 imm_expr.X_op = O_absent;
1331 imm2_expr.X_op = O_absent;
1332 offset_expr.X_op = O_absent;
1333 imm_reloc[0] = BFD_RELOC_UNUSED;
1334 imm_reloc[1] = BFD_RELOC_UNUSED;
1335 imm_reloc[2] = BFD_RELOC_UNUSED;
1336 offset_reloc[0] = BFD_RELOC_UNUSED;
1337 offset_reloc[1] = BFD_RELOC_UNUSED;
1338 offset_reloc[2] = BFD_RELOC_UNUSED;
1340 if (mips_opts.mips16)
1341 mips16_ip (str, &insn);
1344 mips_ip (str, &insn);
1345 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1346 str, insn.insn_opcode));
1351 as_bad ("%s `%s'", insn_error, str);
1355 if (insn.insn_mo->pinfo == INSN_MACRO)
1357 if (mips_opts.mips16)
1358 mips16_macro (&insn);
1364 if (imm_expr.X_op != O_absent)
1365 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1366 else if (offset_expr.X_op != O_absent)
1367 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1369 append_insn (NULL, &insn, NULL, unused_reloc);
1373 /* Return true if the given relocation might need a matching %lo().
1374 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1375 applied to local symbols. */
1377 static inline bfd_boolean
1378 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1380 return (reloc == BFD_RELOC_HI16_S
1381 || reloc == BFD_RELOC_MIPS_GOT16);
1384 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1387 static inline bfd_boolean
1388 fixup_has_matching_lo_p (fixS *fixp)
1390 return (fixp->fx_next != NULL
1391 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1392 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1393 && fixp->fx_offset == fixp->fx_next->fx_offset);
1396 /* See whether instruction IP reads register REG. CLASS is the type
1400 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1401 enum mips_regclass class)
1403 if (class == MIPS16_REG)
1405 assert (mips_opts.mips16);
1406 reg = mips16_to_32_reg_map[reg];
1407 class = MIPS_GR_REG;
1410 /* Don't report on general register ZERO, since it never changes. */
1411 if (class == MIPS_GR_REG && reg == ZERO)
1414 if (class == MIPS_FP_REG)
1416 assert (! mips_opts.mips16);
1417 /* If we are called with either $f0 or $f1, we must check $f0.
1418 This is not optimal, because it will introduce an unnecessary
1419 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1420 need to distinguish reading both $f0 and $f1 or just one of
1421 them. Note that we don't have to check the other way,
1422 because there is no instruction that sets both $f0 and $f1
1423 and requires a delay. */
1424 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1425 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1426 == (reg &~ (unsigned) 1)))
1428 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1429 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1430 == (reg &~ (unsigned) 1)))
1433 else if (! mips_opts.mips16)
1435 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1436 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1438 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1439 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1444 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1445 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1446 & MIPS16OP_MASK_RX)]
1449 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1450 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1451 & MIPS16OP_MASK_RY)]
1454 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1455 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1456 & MIPS16OP_MASK_MOVE32Z)]
1459 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1461 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1463 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1465 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1466 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1467 & MIPS16OP_MASK_REGR32) == reg)
1474 /* This function returns true if modifying a register requires a
1478 reg_needs_delay (unsigned int reg)
1480 unsigned long prev_pinfo;
1482 prev_pinfo = prev_insn.insn_mo->pinfo;
1483 if (! mips_opts.noreorder
1484 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1485 && ! gpr_interlocks)
1486 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1487 && ! cop_interlocks)))
1489 /* A load from a coprocessor or from memory. All load delays
1490 delay the use of general register rt for one instruction. */
1491 /* Itbl support may require additional care here. */
1492 know (prev_pinfo & INSN_WRITE_GPR_T);
1493 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1500 /* Mark instruction labels in mips16 mode. This permits the linker to
1501 handle them specially, such as generating jalx instructions when
1502 needed. We also make them odd for the duration of the assembly, in
1503 order to generate the right sort of code. We will make them even
1504 in the adjust_symtab routine, while leaving them marked. This is
1505 convenient for the debugger and the disassembler. The linker knows
1506 to make them odd again. */
1509 mips16_mark_labels (void)
1511 if (mips_opts.mips16)
1513 struct insn_label_list *l;
1516 for (l = insn_labels; l != NULL; l = l->next)
1519 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1520 S_SET_OTHER (l->label, STO_MIPS16);
1522 val = S_GET_VALUE (l->label);
1524 S_SET_VALUE (l->label, val + 1);
1529 /* Output an instruction. PLACE is where to put the instruction; if
1530 it is NULL, this uses frag_more to get room. IP is the instruction
1531 information. ADDRESS_EXPR is an operand of the instruction to be
1532 used with RELOC_TYPE. */
1535 append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
1536 bfd_reloc_code_real_type *reloc_type)
1538 register unsigned long prev_pinfo, pinfo;
1542 relax_stateT prev_insn_frag_type = 0;
1543 bfd_boolean relaxed_branch = FALSE;
1544 bfd_boolean force_new_frag = FALSE;
1546 /* Mark instruction labels in mips16 mode. */
1547 mips16_mark_labels ();
1549 prev_pinfo = prev_insn.insn_mo->pinfo;
1550 pinfo = ip->insn_mo->pinfo;
1552 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1556 /* If the previous insn required any delay slots, see if we need
1557 to insert a NOP or two. There are eight kinds of possible
1558 hazards, of which an instruction can have at most one type.
1559 (1) a load from memory delay
1560 (2) a load from a coprocessor delay
1561 (3) an unconditional branch delay
1562 (4) a conditional branch delay
1563 (5) a move to coprocessor register delay
1564 (6) a load coprocessor register from memory delay
1565 (7) a coprocessor condition code delay
1566 (8) a HI/LO special register delay
1568 There are a lot of optimizations we could do that we don't.
1569 In particular, we do not, in general, reorder instructions.
1570 If you use gcc with optimization, it will reorder
1571 instructions and generally do much more optimization then we
1572 do here; repeating all that work in the assembler would only
1573 benefit hand written assembly code, and does not seem worth
1576 /* This is how a NOP is emitted. */
1577 #define emit_nop() \
1579 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1580 : md_number_to_chars (frag_more (4), 0, 4))
1582 /* The previous insn might require a delay slot, depending upon
1583 the contents of the current insn. */
1584 if (! mips_opts.mips16
1585 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1586 && ! gpr_interlocks)
1587 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1588 && ! cop_interlocks)))
1590 /* A load from a coprocessor or from memory. All load
1591 delays delay the use of general register rt for one
1593 /* Itbl support may require additional care here. */
1594 know (prev_pinfo & INSN_WRITE_GPR_T);
1595 if (mips_optimize == 0
1596 || insn_uses_reg (ip,
1597 ((prev_insn.insn_opcode >> OP_SH_RT)
1602 else if (! mips_opts.mips16
1603 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1604 && ! cop_interlocks)
1605 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1606 && ! cop_mem_interlocks)))
1608 /* A generic coprocessor delay. The previous instruction
1609 modified a coprocessor general or control register. If
1610 it modified a control register, we need to avoid any
1611 coprocessor instruction (this is probably not always
1612 required, but it sometimes is). If it modified a general
1613 register, we avoid using that register.
1615 This case is not handled very well. There is no special
1616 knowledge of CP0 handling, and the coprocessors other
1617 than the floating point unit are not distinguished at
1619 /* Itbl support may require additional care here. FIXME!
1620 Need to modify this to include knowledge about
1621 user specified delays! */
1622 if (prev_pinfo & INSN_WRITE_FPR_T)
1624 if (mips_optimize == 0
1625 || insn_uses_reg (ip,
1626 ((prev_insn.insn_opcode >> OP_SH_FT)
1631 else if (prev_pinfo & INSN_WRITE_FPR_S)
1633 if (mips_optimize == 0
1634 || insn_uses_reg (ip,
1635 ((prev_insn.insn_opcode >> OP_SH_FS)
1642 /* We don't know exactly what the previous instruction
1643 does. If the current instruction uses a coprocessor
1644 register, we must insert a NOP. If previous
1645 instruction may set the condition codes, and the
1646 current instruction uses them, we must insert two
1648 /* Itbl support may require additional care here. */
1649 if (mips_optimize == 0
1650 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1651 && (pinfo & INSN_READ_COND_CODE)))
1653 else if (pinfo & INSN_COP)
1657 else if (! mips_opts.mips16
1658 && (prev_pinfo & INSN_WRITE_COND_CODE)
1659 && ! cop_interlocks)
1661 /* The previous instruction sets the coprocessor condition
1662 codes, but does not require a general coprocessor delay
1663 (this means it is a floating point comparison
1664 instruction). If this instruction uses the condition
1665 codes, we need to insert a single NOP. */
1666 /* Itbl support may require additional care here. */
1667 if (mips_optimize == 0
1668 || (pinfo & INSN_READ_COND_CODE))
1672 /* If we're fixing up mfhi/mflo for the r7000 and the
1673 previous insn was an mfhi/mflo and the current insn
1674 reads the register that the mfhi/mflo wrote to, then
1677 else if (mips_7000_hilo_fix
1678 && MF_HILO_INSN (prev_pinfo)
1679 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1686 /* If we're fixing up mfhi/mflo for the r7000 and the
1687 2nd previous insn was an mfhi/mflo and the current insn
1688 reads the register that the mfhi/mflo wrote to, then
1691 else if (mips_7000_hilo_fix
1692 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1693 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1701 else if (prev_pinfo & INSN_READ_LO)
1703 /* The previous instruction reads the LO register; if the
1704 current instruction writes to the LO register, we must
1705 insert two NOPS. Some newer processors have interlocks.
1706 Also the tx39's multiply instructions can be executed
1707 immediately after a read from HI/LO (without the delay),
1708 though the tx39's divide insns still do require the
1710 if (! (hilo_interlocks
1711 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1712 && (mips_optimize == 0
1713 || (pinfo & INSN_WRITE_LO)))
1715 /* Most mips16 branch insns don't have a delay slot.
1716 If a read from LO is immediately followed by a branch
1717 to a write to LO we have a read followed by a write
1718 less than 2 insns away. We assume the target of
1719 a branch might be a write to LO, and insert a nop
1720 between a read and an immediately following branch. */
1721 else if (mips_opts.mips16
1722 && (mips_optimize == 0
1723 || (pinfo & MIPS16_INSN_BRANCH)))
1726 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1728 /* The previous instruction reads the HI register; if the
1729 current instruction writes to the HI register, we must
1730 insert a NOP. Some newer processors have interlocks.
1731 Also the note tx39's multiply above. */
1732 if (! (hilo_interlocks
1733 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1734 && (mips_optimize == 0
1735 || (pinfo & INSN_WRITE_HI)))
1737 /* Most mips16 branch insns don't have a delay slot.
1738 If a read from HI is immediately followed by a branch
1739 to a write to HI we have a read followed by a write
1740 less than 2 insns away. We assume the target of
1741 a branch might be a write to HI, and insert a nop
1742 between a read and an immediately following branch. */
1743 else if (mips_opts.mips16
1744 && (mips_optimize == 0
1745 || (pinfo & MIPS16_INSN_BRANCH)))
1749 /* If the previous instruction was in a noreorder section, then
1750 we don't want to insert the nop after all. */
1751 /* Itbl support may require additional care here. */
1752 if (prev_insn_unreordered)
1755 /* There are two cases which require two intervening
1756 instructions: 1) setting the condition codes using a move to
1757 coprocessor instruction which requires a general coprocessor
1758 delay and then reading the condition codes 2) reading the HI
1759 or LO register and then writing to it (except on processors
1760 which have interlocks). If we are not already emitting a NOP
1761 instruction, we must check for these cases compared to the
1762 instruction previous to the previous instruction. */
1763 if ((! mips_opts.mips16
1764 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1765 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1766 && (pinfo & INSN_READ_COND_CODE)
1767 && ! cop_interlocks)
1768 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1769 && (pinfo & INSN_WRITE_LO)
1770 && ! (hilo_interlocks
1771 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1772 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1773 && (pinfo & INSN_WRITE_HI)
1774 && ! (hilo_interlocks
1775 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1780 if (prev_prev_insn_unreordered)
1783 if (prev_prev_nop && nops == 0)
1786 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1788 /* We're out of bits in pinfo, so we must resort to string
1789 ops here. Shortcuts are selected based on opcodes being
1790 limited to the VR4122 instruction set. */
1792 const char *pn = prev_insn.insn_mo->name;
1793 const char *tn = ip->insn_mo->name;
1794 if (strncmp(pn, "macc", 4) == 0
1795 || strncmp(pn, "dmacc", 5) == 0)
1797 /* Errata 21 - [D]DIV[U] after [D]MACC */
1798 if (strstr (tn, "div"))
1803 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1804 if (pn[0] == 'd' /* dmacc */
1805 && (strncmp(tn, "dmult", 5) == 0
1806 || strncmp(tn, "dmacc", 5) == 0))
1811 /* Errata 24 - MT{LO,HI} after [D]MACC */
1812 if (strcmp (tn, "mtlo") == 0
1813 || strcmp (tn, "mthi") == 0)
1819 else if (strncmp(pn, "dmult", 5) == 0
1820 && (strncmp(tn, "dmult", 5) == 0
1821 || strncmp(tn, "dmacc", 5) == 0))
1823 /* Here is the rest of errata 23. */
1826 if (nops < min_nops)
1830 /* If we are being given a nop instruction, don't bother with
1831 one of the nops we would otherwise output. This will only
1832 happen when a nop instruction is used with mips_optimize set
1835 && ! mips_opts.noreorder
1836 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1839 /* Now emit the right number of NOP instructions. */
1840 if (nops > 0 && ! mips_opts.noreorder)
1843 unsigned long old_frag_offset;
1845 struct insn_label_list *l;
1847 old_frag = frag_now;
1848 old_frag_offset = frag_now_fix ();
1850 for (i = 0; i < nops; i++)
1855 listing_prev_line ();
1856 /* We may be at the start of a variant frag. In case we
1857 are, make sure there is enough space for the frag
1858 after the frags created by listing_prev_line. The
1859 argument to frag_grow here must be at least as large
1860 as the argument to all other calls to frag_grow in
1861 this file. We don't have to worry about being in the
1862 middle of a variant frag, because the variants insert
1863 all needed nop instructions themselves. */
1867 for (l = insn_labels; l != NULL; l = l->next)
1871 assert (S_GET_SEGMENT (l->label) == now_seg);
1872 symbol_set_frag (l->label, frag_now);
1873 val = (valueT) frag_now_fix ();
1874 /* mips16 text labels are stored as odd. */
1875 if (mips_opts.mips16)
1877 S_SET_VALUE (l->label, val);
1880 #ifndef NO_ECOFF_DEBUGGING
1881 if (ECOFF_DEBUGGING)
1882 ecoff_fix_loc (old_frag, old_frag_offset);
1885 else if (prev_nop_frag != NULL)
1887 /* We have a frag holding nops we may be able to remove. If
1888 we don't need any nops, we can decrease the size of
1889 prev_nop_frag by the size of one instruction. If we do
1890 need some nops, we count them in prev_nops_required. */
1891 if (prev_nop_frag_since == 0)
1895 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1896 --prev_nop_frag_holds;
1899 prev_nop_frag_required += nops;
1903 if (prev_prev_nop == 0)
1905 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1906 --prev_nop_frag_holds;
1909 ++prev_nop_frag_required;
1912 if (prev_nop_frag_holds <= prev_nop_frag_required)
1913 prev_nop_frag = NULL;
1915 ++prev_nop_frag_since;
1917 /* Sanity check: by the time we reach the second instruction
1918 after prev_nop_frag, we should have used up all the nops
1919 one way or another. */
1920 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1924 /* Record the frag type before frag_var. */
1926 prev_insn_frag_type = prev_insn_frag->fr_type;
1930 && *reloc_type == BFD_RELOC_16_PCREL_S2
1931 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1932 || pinfo & INSN_COND_BRANCH_LIKELY)
1933 && mips_relax_branch
1934 /* Don't try branch relaxation within .set nomacro, or within
1935 .set noat if we use $at for PIC computations. If it turns
1936 out that the branch was out-of-range, we'll get an error. */
1937 && !mips_opts.warn_about_macros
1938 && !(mips_opts.noat && mips_pic != NO_PIC)
1939 && !mips_opts.mips16)
1941 relaxed_branch = TRUE;
1942 f = frag_var (rs_machine_dependent,
1943 relaxed_branch_length
1945 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1946 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1948 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1949 pinfo & INSN_COND_BRANCH_LIKELY,
1950 pinfo & INSN_WRITE_GPR_31,
1952 address_expr->X_add_symbol,
1953 address_expr->X_add_number,
1955 *reloc_type = BFD_RELOC_UNUSED;
1957 else if (*reloc_type > BFD_RELOC_UNUSED)
1959 /* We need to set up a variant frag. */
1960 assert (mips_opts.mips16 && address_expr != NULL);
1961 f = frag_var (rs_machine_dependent, 4, 0,
1962 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1963 mips16_small, mips16_ext,
1965 & INSN_UNCOND_BRANCH_DELAY),
1966 (*prev_insn_reloc_type
1967 == BFD_RELOC_MIPS16_JMP)),
1968 make_expr_symbol (address_expr), 0, NULL);
1970 else if (place != NULL)
1972 else if (mips_opts.mips16
1974 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1976 /* Make sure there is enough room to swap this instruction with
1977 a following jump instruction. */
1983 if (mips_opts.mips16
1984 && mips_opts.noreorder
1985 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1986 as_warn (_("extended instruction in delay slot"));
1991 fixp[0] = fixp[1] = fixp[2] = NULL;
1992 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1994 if (address_expr->X_op == O_constant)
1998 switch (*reloc_type)
2001 ip->insn_opcode |= address_expr->X_add_number;
2004 case BFD_RELOC_MIPS_HIGHEST:
2005 tmp = (address_expr->X_add_number
2006 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2008 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2011 case BFD_RELOC_MIPS_HIGHER:
2012 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2013 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2016 case BFD_RELOC_HI16_S:
2017 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2021 case BFD_RELOC_HI16:
2022 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2025 case BFD_RELOC_LO16:
2026 case BFD_RELOC_MIPS_GOT_DISP:
2027 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2030 case BFD_RELOC_MIPS_JMP:
2031 if ((address_expr->X_add_number & 3) != 0)
2032 as_bad (_("jump to misaligned address (0x%lx)"),
2033 (unsigned long) address_expr->X_add_number);
2034 if (address_expr->X_add_number & ~0xfffffff)
2035 as_bad (_("jump address range overflow (0x%lx)"),
2036 (unsigned long) address_expr->X_add_number);
2037 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2040 case BFD_RELOC_MIPS16_JMP:
2041 if ((address_expr->X_add_number & 3) != 0)
2042 as_bad (_("jump to misaligned address (0x%lx)"),
2043 (unsigned long) address_expr->X_add_number);
2044 if (address_expr->X_add_number & ~0xfffffff)
2045 as_bad (_("jump address range overflow (0x%lx)"),
2046 (unsigned long) address_expr->X_add_number);
2048 (((address_expr->X_add_number & 0x7c0000) << 3)
2049 | ((address_expr->X_add_number & 0xf800000) >> 7)
2050 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2053 case BFD_RELOC_16_PCREL_S2:
2063 /* Don't generate a reloc if we are writing into a variant frag. */
2066 reloc_howto_type *howto;
2069 /* In a compound relocation, it is the final (outermost)
2070 operator that determines the relocated field. */
2071 for (i = 1; i < 3; i++)
2072 if (reloc_type[i] == BFD_RELOC_UNUSED)
2075 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2076 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2077 bfd_get_reloc_size(howto),
2079 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2082 /* These relocations can have an addend that won't fit in
2083 4 octets for 64bit assembly. */
2085 && ! howto->partial_inplace
2086 && (reloc_type[0] == BFD_RELOC_16
2087 || reloc_type[0] == BFD_RELOC_32
2088 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2089 || reloc_type[0] == BFD_RELOC_HI16_S
2090 || reloc_type[0] == BFD_RELOC_LO16
2091 || reloc_type[0] == BFD_RELOC_GPREL16
2092 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2093 || reloc_type[0] == BFD_RELOC_GPREL32
2094 || reloc_type[0] == BFD_RELOC_64
2095 || reloc_type[0] == BFD_RELOC_CTOR
2096 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2097 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2098 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2099 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2100 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2101 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2102 fixp[0]->fx_no_overflow = 1;
2104 if (reloc_needs_lo_p (*reloc_type))
2106 struct mips_hi_fixup *hi_fixup;
2108 /* Reuse the last entry if it already has a matching %lo. */
2109 hi_fixup = mips_hi_fixup_list;
2111 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2113 hi_fixup = ((struct mips_hi_fixup *)
2114 xmalloc (sizeof (struct mips_hi_fixup)));
2115 hi_fixup->next = mips_hi_fixup_list;
2116 mips_hi_fixup_list = hi_fixup;
2118 hi_fixup->fixp = fixp[0];
2119 hi_fixup->seg = now_seg;
2122 /* Add fixups for the second and third relocations, if given.
2123 Note that the ABI allows the second relocation to be
2124 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2125 moment we only use RSS_UNDEF, but we could add support
2126 for the others if it ever becomes necessary. */
2127 for (i = 1; i < 3; i++)
2128 if (reloc_type[i] != BFD_RELOC_UNUSED)
2130 address_expr->X_op = O_absent;
2131 address_expr->X_add_symbol = 0;
2132 address_expr->X_add_number = 0;
2134 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2135 fixp[0]->fx_size, address_expr,
2136 FALSE, reloc_type[i]);
2142 if (! mips_opts.mips16)
2144 md_number_to_chars (f, ip->insn_opcode, 4);
2146 dwarf2_emit_insn (4);
2149 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2151 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2152 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2154 dwarf2_emit_insn (4);
2161 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2164 md_number_to_chars (f, ip->insn_opcode, 2);
2166 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2170 /* Update the register mask information. */
2171 if (! mips_opts.mips16)
2173 if (pinfo & INSN_WRITE_GPR_D)
2174 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2175 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2176 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2177 if (pinfo & INSN_READ_GPR_S)
2178 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2179 if (pinfo & INSN_WRITE_GPR_31)
2180 mips_gprmask |= 1 << RA;
2181 if (pinfo & INSN_WRITE_FPR_D)
2182 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2183 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2184 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2185 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2186 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2187 if ((pinfo & INSN_READ_FPR_R) != 0)
2188 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2189 if (pinfo & INSN_COP)
2191 /* We don't keep enough information to sort these cases out.
2192 The itbl support does keep this information however, although
2193 we currently don't support itbl fprmats as part of the cop
2194 instruction. May want to add this support in the future. */
2196 /* Never set the bit for $0, which is always zero. */
2197 mips_gprmask &= ~1 << 0;
2201 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2202 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2203 & MIPS16OP_MASK_RX);
2204 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2205 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2206 & MIPS16OP_MASK_RY);
2207 if (pinfo & MIPS16_INSN_WRITE_Z)
2208 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2209 & MIPS16OP_MASK_RZ);
2210 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2211 mips_gprmask |= 1 << TREG;
2212 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2213 mips_gprmask |= 1 << SP;
2214 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2215 mips_gprmask |= 1 << RA;
2216 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2217 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2218 if (pinfo & MIPS16_INSN_READ_Z)
2219 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2220 & MIPS16OP_MASK_MOVE32Z);
2221 if (pinfo & MIPS16_INSN_READ_GPR_X)
2222 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2223 & MIPS16OP_MASK_REGR32);
2226 if (place == NULL && ! mips_opts.noreorder)
2228 /* Filling the branch delay slot is more complex. We try to
2229 switch the branch with the previous instruction, which we can
2230 do if the previous instruction does not set up a condition
2231 that the branch tests and if the branch is not itself the
2232 target of any branch. */
2233 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2234 || (pinfo & INSN_COND_BRANCH_DELAY))
2236 if (mips_optimize < 2
2237 /* If we have seen .set volatile or .set nomove, don't
2239 || mips_opts.nomove != 0
2240 /* If we had to emit any NOP instructions, then we
2241 already know we can not swap. */
2243 /* If we don't even know the previous insn, we can not
2245 || ! prev_insn_valid
2246 /* If the previous insn is already in a branch delay
2247 slot, then we can not swap. */
2248 || prev_insn_is_delay_slot
2249 /* If the previous previous insn was in a .set
2250 noreorder, we can't swap. Actually, the MIPS
2251 assembler will swap in this situation. However, gcc
2252 configured -with-gnu-as will generate code like
2258 in which we can not swap the bne and INSN. If gcc is
2259 not configured -with-gnu-as, it does not output the
2260 .set pseudo-ops. We don't have to check
2261 prev_insn_unreordered, because prev_insn_valid will
2262 be 0 in that case. We don't want to use
2263 prev_prev_insn_valid, because we do want to be able
2264 to swap at the start of a function. */
2265 || prev_prev_insn_unreordered
2266 /* If the branch is itself the target of a branch, we
2267 can not swap. We cheat on this; all we check for is
2268 whether there is a label on this instruction. If
2269 there are any branches to anything other than a
2270 label, users must use .set noreorder. */
2271 || insn_labels != NULL
2272 /* If the previous instruction is in a variant frag
2273 other than this branch's one, we cannot do the swap.
2274 This does not apply to the mips16, which uses variant
2275 frags for different purposes. */
2276 || (! mips_opts.mips16
2277 && prev_insn_frag_type == rs_machine_dependent)
2278 /* If the branch reads the condition codes, we don't
2279 even try to swap, because in the sequence
2284 we can not swap, and I don't feel like handling that
2286 || (! mips_opts.mips16
2287 && (pinfo & INSN_READ_COND_CODE)
2288 && ! cop_interlocks)
2289 /* We can not swap with an instruction that requires a
2290 delay slot, because the target of the branch might
2291 interfere with that instruction. */
2292 || (! mips_opts.mips16
2294 /* Itbl support may require additional care here. */
2295 & (INSN_LOAD_COPROC_DELAY
2296 | INSN_COPROC_MOVE_DELAY
2297 | INSN_WRITE_COND_CODE))
2298 && ! cop_interlocks)
2299 || (! (hilo_interlocks
2300 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2304 || (! mips_opts.mips16
2305 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2306 && ! gpr_interlocks)
2307 || (! mips_opts.mips16
2308 /* Itbl support may require additional care here. */
2309 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2310 && ! cop_mem_interlocks)
2311 /* We can not swap with a branch instruction. */
2313 & (INSN_UNCOND_BRANCH_DELAY
2314 | INSN_COND_BRANCH_DELAY
2315 | INSN_COND_BRANCH_LIKELY))
2316 /* We do not swap with a trap instruction, since it
2317 complicates trap handlers to have the trap
2318 instruction be in a delay slot. */
2319 || (prev_pinfo & INSN_TRAP)
2320 /* If the branch reads a register that the previous
2321 instruction sets, we can not swap. */
2322 || (! mips_opts.mips16
2323 && (prev_pinfo & INSN_WRITE_GPR_T)
2324 && insn_uses_reg (ip,
2325 ((prev_insn.insn_opcode >> OP_SH_RT)
2328 || (! mips_opts.mips16
2329 && (prev_pinfo & INSN_WRITE_GPR_D)
2330 && insn_uses_reg (ip,
2331 ((prev_insn.insn_opcode >> OP_SH_RD)
2334 || (mips_opts.mips16
2335 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2336 && insn_uses_reg (ip,
2337 ((prev_insn.insn_opcode
2339 & MIPS16OP_MASK_RX),
2341 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2342 && insn_uses_reg (ip,
2343 ((prev_insn.insn_opcode
2345 & MIPS16OP_MASK_RY),
2347 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2348 && insn_uses_reg (ip,
2349 ((prev_insn.insn_opcode
2351 & MIPS16OP_MASK_RZ),
2353 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2354 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2355 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2356 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2357 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2358 && insn_uses_reg (ip,
2359 MIPS16OP_EXTRACT_REG32R (prev_insn.
2362 /* If the branch writes a register that the previous
2363 instruction sets, we can not swap (we know that
2364 branches write only to RD or to $31). */
2365 || (! mips_opts.mips16
2366 && (prev_pinfo & INSN_WRITE_GPR_T)
2367 && (((pinfo & INSN_WRITE_GPR_D)
2368 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2369 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2370 || ((pinfo & INSN_WRITE_GPR_31)
2371 && (((prev_insn.insn_opcode >> OP_SH_RT)
2374 || (! mips_opts.mips16
2375 && (prev_pinfo & INSN_WRITE_GPR_D)
2376 && (((pinfo & INSN_WRITE_GPR_D)
2377 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2378 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2379 || ((pinfo & INSN_WRITE_GPR_31)
2380 && (((prev_insn.insn_opcode >> OP_SH_RD)
2383 || (mips_opts.mips16
2384 && (pinfo & MIPS16_INSN_WRITE_31)
2385 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2386 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2387 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2389 /* If the branch writes a register that the previous
2390 instruction reads, we can not swap (we know that
2391 branches only write to RD or to $31). */
2392 || (! mips_opts.mips16
2393 && (pinfo & INSN_WRITE_GPR_D)
2394 && insn_uses_reg (&prev_insn,
2395 ((ip->insn_opcode >> OP_SH_RD)
2398 || (! mips_opts.mips16
2399 && (pinfo & INSN_WRITE_GPR_31)
2400 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2401 || (mips_opts.mips16
2402 && (pinfo & MIPS16_INSN_WRITE_31)
2403 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2404 /* If we are generating embedded PIC code, the branch
2405 might be expanded into a sequence which uses $at, so
2406 we can't swap with an instruction which reads it. */
2407 || (mips_pic == EMBEDDED_PIC
2408 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2409 /* If the previous previous instruction has a load
2410 delay, and sets a register that the branch reads, we
2412 || (! mips_opts.mips16
2413 /* Itbl support may require additional care here. */
2414 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2415 && ! cop_interlocks)
2416 || ((prev_prev_insn.insn_mo->pinfo
2417 & INSN_LOAD_MEMORY_DELAY)
2418 && ! gpr_interlocks))
2419 && insn_uses_reg (ip,
2420 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2423 /* If one instruction sets a condition code and the
2424 other one uses a condition code, we can not swap. */
2425 || ((pinfo & INSN_READ_COND_CODE)
2426 && (prev_pinfo & INSN_WRITE_COND_CODE))
2427 || ((pinfo & INSN_WRITE_COND_CODE)
2428 && (prev_pinfo & INSN_READ_COND_CODE))
2429 /* If the previous instruction uses the PC, we can not
2431 || (mips_opts.mips16
2432 && (prev_pinfo & MIPS16_INSN_READ_PC))
2433 /* If the previous instruction was extended, we can not
2435 || (mips_opts.mips16 && prev_insn_extended)
2436 /* If the previous instruction had a fixup in mips16
2437 mode, we can not swap. This normally means that the
2438 previous instruction was a 4 byte branch anyhow. */
2439 || (mips_opts.mips16 && prev_insn_fixp[0])
2440 /* If the previous instruction is a sync, sync.l, or
2441 sync.p, we can not swap. */
2442 || (prev_pinfo & INSN_SYNC))
2444 /* We could do even better for unconditional branches to
2445 portions of this object file; we could pick up the
2446 instruction at the destination, put it in the delay
2447 slot, and bump the destination address. */
2449 /* Update the previous insn information. */
2450 prev_prev_insn = *ip;
2451 prev_insn.insn_mo = &dummy_opcode;
2455 /* It looks like we can actually do the swap. */
2456 if (! mips_opts.mips16)
2461 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2462 if (!relaxed_branch)
2464 /* If this is not a relaxed branch, then just
2465 swap the instructions. */
2466 memcpy (temp, prev_f, 4);
2467 memcpy (prev_f, f, 4);
2468 memcpy (f, temp, 4);
2472 /* If this is a relaxed branch, then we move the
2473 instruction to be placed in the delay slot to
2474 the current frag, shrinking the fixed part of
2475 the originating frag. If the branch occupies
2476 the tail of the latter, we move it backwards,
2477 into the space freed by the moved instruction. */
2479 memcpy (f, prev_f, 4);
2480 prev_insn_frag->fr_fix -= 4;
2481 if (prev_insn_frag->fr_type == rs_machine_dependent)
2482 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2485 if (prev_insn_fixp[0])
2487 prev_insn_fixp[0]->fx_frag = frag_now;
2488 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2490 if (prev_insn_fixp[1])
2492 prev_insn_fixp[1]->fx_frag = frag_now;
2493 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2495 if (prev_insn_fixp[2])
2497 prev_insn_fixp[2]->fx_frag = frag_now;
2498 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2500 if (prev_insn_fixp[0] && HAVE_NEWABI
2501 && prev_insn_frag != frag_now
2502 && (prev_insn_fixp[0]->fx_r_type
2503 == BFD_RELOC_MIPS_GOT_DISP
2504 || (prev_insn_fixp[0]->fx_r_type
2505 == BFD_RELOC_MIPS_CALL16)))
2507 /* To avoid confusion in tc_gen_reloc, we must
2508 ensure that this does not become a variant
2510 force_new_frag = TRUE;
2513 if (!relaxed_branch)
2517 fixp[0]->fx_frag = prev_insn_frag;
2518 fixp[0]->fx_where = prev_insn_where;
2522 fixp[1]->fx_frag = prev_insn_frag;
2523 fixp[1]->fx_where = prev_insn_where;
2527 fixp[2]->fx_frag = prev_insn_frag;
2528 fixp[2]->fx_where = prev_insn_where;
2531 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2534 fixp[0]->fx_where -= 4;
2536 fixp[1]->fx_where -= 4;
2538 fixp[2]->fx_where -= 4;
2546 assert (prev_insn_fixp[0] == NULL);
2547 assert (prev_insn_fixp[1] == NULL);
2548 assert (prev_insn_fixp[2] == NULL);
2549 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2550 memcpy (temp, prev_f, 2);
2551 memcpy (prev_f, f, 2);
2552 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2554 assert (*reloc_type == BFD_RELOC_UNUSED);
2555 memcpy (f, temp, 2);
2559 memcpy (f, f + 2, 2);
2560 memcpy (f + 2, temp, 2);
2564 fixp[0]->fx_frag = prev_insn_frag;
2565 fixp[0]->fx_where = prev_insn_where;
2569 fixp[1]->fx_frag = prev_insn_frag;
2570 fixp[1]->fx_where = prev_insn_where;
2574 fixp[2]->fx_frag = prev_insn_frag;
2575 fixp[2]->fx_where = prev_insn_where;
2579 /* Update the previous insn information; leave prev_insn
2581 prev_prev_insn = *ip;
2583 prev_insn_is_delay_slot = 1;
2585 /* If that was an unconditional branch, forget the previous
2586 insn information. */
2587 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2589 prev_prev_insn.insn_mo = &dummy_opcode;
2590 prev_insn.insn_mo = &dummy_opcode;
2593 prev_insn_fixp[0] = NULL;
2594 prev_insn_fixp[1] = NULL;
2595 prev_insn_fixp[2] = NULL;
2596 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2597 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2598 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2599 prev_insn_extended = 0;
2601 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2603 /* We don't yet optimize a branch likely. What we should do
2604 is look at the target, copy the instruction found there
2605 into the delay slot, and increment the branch to jump to
2606 the next instruction. */
2608 /* Update the previous insn information. */
2609 prev_prev_insn = *ip;
2610 prev_insn.insn_mo = &dummy_opcode;
2611 prev_insn_fixp[0] = NULL;
2612 prev_insn_fixp[1] = NULL;
2613 prev_insn_fixp[2] = NULL;
2614 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2615 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2616 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2617 prev_insn_extended = 0;
2621 /* Update the previous insn information. */
2623 prev_prev_insn.insn_mo = &dummy_opcode;
2625 prev_prev_insn = prev_insn;
2628 /* Any time we see a branch, we always fill the delay slot
2629 immediately; since this insn is not a branch, we know it
2630 is not in a delay slot. */
2631 prev_insn_is_delay_slot = 0;
2633 prev_insn_fixp[0] = fixp[0];
2634 prev_insn_fixp[1] = fixp[1];
2635 prev_insn_fixp[2] = fixp[2];
2636 prev_insn_reloc_type[0] = reloc_type[0];
2637 prev_insn_reloc_type[1] = reloc_type[1];
2638 prev_insn_reloc_type[2] = reloc_type[2];
2639 if (mips_opts.mips16)
2640 prev_insn_extended = (ip->use_extend
2641 || *reloc_type > BFD_RELOC_UNUSED);
2644 prev_prev_insn_unreordered = prev_insn_unreordered;
2645 prev_insn_unreordered = 0;
2646 prev_insn_frag = frag_now;
2647 prev_insn_where = f - frag_now->fr_literal;
2648 prev_insn_valid = 1;
2650 else if (place == NULL)
2652 /* We need to record a bit of information even when we are not
2653 reordering, in order to determine the base address for mips16
2654 PC relative relocs. */
2655 prev_prev_insn = prev_insn;
2657 prev_insn_reloc_type[0] = reloc_type[0];
2658 prev_insn_reloc_type[1] = reloc_type[1];
2659 prev_insn_reloc_type[2] = reloc_type[2];
2660 prev_prev_insn_unreordered = prev_insn_unreordered;
2661 prev_insn_unreordered = 1;
2664 /* We just output an insn, so the next one doesn't have a label. */
2665 mips_clear_insn_labels ();
2667 /* We must ensure that the frag to which an instruction that was
2668 moved from a non-variant frag doesn't become a variant frag,
2669 otherwise tc_gen_reloc may get confused. */
2672 frag_wane (frag_now);
2677 /* This function forgets that there was any previous instruction or
2678 label. If PRESERVE is non-zero, it remembers enough information to
2679 know whether nops are needed before a noreorder section. */
2682 mips_no_prev_insn (int preserve)
2686 prev_insn.insn_mo = &dummy_opcode;
2687 prev_prev_insn.insn_mo = &dummy_opcode;
2688 prev_nop_frag = NULL;
2689 prev_nop_frag_holds = 0;
2690 prev_nop_frag_required = 0;
2691 prev_nop_frag_since = 0;
2693 prev_insn_valid = 0;
2694 prev_insn_is_delay_slot = 0;
2695 prev_insn_unreordered = 0;
2696 prev_insn_extended = 0;
2697 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2698 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2699 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2700 prev_prev_insn_unreordered = 0;
2701 mips_clear_insn_labels ();
2704 /* This function must be called whenever we turn on noreorder or emit
2705 something other than instructions. It inserts any NOPS which might
2706 be needed by the previous instruction, and clears the information
2707 kept for the previous instructions. The INSNS parameter is true if
2708 instructions are to follow. */
2711 mips_emit_delays (bfd_boolean insns)
2713 if (! mips_opts.noreorder)
2718 if ((! mips_opts.mips16
2719 && ((prev_insn.insn_mo->pinfo
2720 & (INSN_LOAD_COPROC_DELAY
2721 | INSN_COPROC_MOVE_DELAY
2722 | INSN_WRITE_COND_CODE))
2723 && ! cop_interlocks))
2724 || (! hilo_interlocks
2725 && (prev_insn.insn_mo->pinfo
2728 || (! mips_opts.mips16
2729 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2730 && ! gpr_interlocks)
2731 || (! mips_opts.mips16
2732 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2733 && ! cop_mem_interlocks))
2735 /* Itbl support may require additional care here. */
2737 if ((! mips_opts.mips16
2738 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2739 && ! cop_interlocks))
2740 || (! hilo_interlocks
2741 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2742 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2745 if (prev_insn_unreordered)
2748 else if ((! mips_opts.mips16
2749 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2750 && ! cop_interlocks))
2751 || (! hilo_interlocks
2752 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2753 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2755 /* Itbl support may require additional care here. */
2756 if (! prev_prev_insn_unreordered)
2760 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2763 const char *pn = prev_insn.insn_mo->name;
2764 if (strncmp(pn, "macc", 4) == 0
2765 || strncmp(pn, "dmacc", 5) == 0
2766 || strncmp(pn, "dmult", 5) == 0)
2770 if (nops < min_nops)
2776 struct insn_label_list *l;
2780 /* Record the frag which holds the nop instructions, so
2781 that we can remove them if we don't need them. */
2782 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2783 prev_nop_frag = frag_now;
2784 prev_nop_frag_holds = nops;
2785 prev_nop_frag_required = 0;
2786 prev_nop_frag_since = 0;
2789 for (; nops > 0; --nops)
2794 /* Move on to a new frag, so that it is safe to simply
2795 decrease the size of prev_nop_frag. */
2796 frag_wane (frag_now);
2800 for (l = insn_labels; l != NULL; l = l->next)
2804 assert (S_GET_SEGMENT (l->label) == now_seg);
2805 symbol_set_frag (l->label, frag_now);
2806 val = (valueT) frag_now_fix ();
2807 /* mips16 text labels are stored as odd. */
2808 if (mips_opts.mips16)
2810 S_SET_VALUE (l->label, val);
2815 /* Mark instruction labels in mips16 mode. */
2817 mips16_mark_labels ();
2819 mips_no_prev_insn (insns);
2822 /* Build an instruction created by a macro expansion. This is passed
2823 a pointer to the count of instructions created so far, an
2824 expression, the name of the instruction to build, an operand format
2825 string, and corresponding arguments. */
2828 macro_build (char *place, int *counter, expressionS *ep, const char *name,
2829 const char *fmt, ...)
2831 struct mips_cl_insn insn;
2832 bfd_reloc_code_real_type r[3];
2835 va_start (args, fmt);
2838 * If the macro is about to expand into a second instruction,
2839 * print a warning if needed. We need to pass ip as a parameter
2840 * to generate a better warning message here...
2842 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2843 as_warn (_("Macro instruction expanded into multiple instructions"));
2846 * If the macro is about to expand into a second instruction,
2847 * and it is in a delay slot, print a warning.
2851 && mips_opts.noreorder
2852 && (prev_prev_insn.insn_mo->pinfo
2853 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2854 | INSN_COND_BRANCH_LIKELY)) != 0)
2855 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2858 ++*counter; /* bump instruction counter */
2860 if (mips_opts.mips16)
2862 mips16_macro_build (place, counter, ep, name, fmt, args);
2867 r[0] = BFD_RELOC_UNUSED;
2868 r[1] = BFD_RELOC_UNUSED;
2869 r[2] = BFD_RELOC_UNUSED;
2870 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2871 assert (insn.insn_mo);
2872 assert (strcmp (name, insn.insn_mo->name) == 0);
2874 /* Search until we get a match for NAME. */
2877 /* It is assumed here that macros will never generate
2878 MDMX or MIPS-3D instructions. */
2879 if (strcmp (fmt, insn.insn_mo->args) == 0
2880 && insn.insn_mo->pinfo != INSN_MACRO
2881 && OPCODE_IS_MEMBER (insn.insn_mo,
2883 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2885 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2889 assert (insn.insn_mo->name);
2890 assert (strcmp (name, insn.insn_mo->name) == 0);
2893 insn.insn_opcode = insn.insn_mo->match;
2911 insn.insn_opcode |= (va_arg (args, int)
2912 & OP_MASK_SHAMT) << OP_SH_SHAMT;
2917 /* Note that in the macro case, these arguments are already
2918 in MSB form. (When handling the instruction in the
2919 non-macro case, these arguments are sizes from which
2920 MSB values must be calculated.) */
2921 insn.insn_opcode |= (va_arg (args, int)
2922 & OP_MASK_INSMSB) << OP_SH_INSMSB;
2928 /* Note that in the macro case, these arguments are already
2929 in MSBD form. (When handling the instruction in the
2930 non-macro case, these arguments are sizes from which
2931 MSBD values must be calculated.) */
2932 insn.insn_opcode |= (va_arg (args, int)
2933 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
2944 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2948 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2953 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2959 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2964 int tmp = va_arg (args, int);
2966 insn.insn_opcode |= tmp << OP_SH_RT;
2967 insn.insn_opcode |= tmp << OP_SH_RD;
2973 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2980 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2984 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2988 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2992 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2996 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3003 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3009 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3010 assert (*r == BFD_RELOC_GPREL16
3011 || *r == BFD_RELOC_MIPS_LITERAL
3012 || *r == BFD_RELOC_MIPS_HIGHER
3013 || *r == BFD_RELOC_HI16_S
3014 || *r == BFD_RELOC_LO16
3015 || *r == BFD_RELOC_MIPS_GOT16
3016 || *r == BFD_RELOC_MIPS_CALL16
3017 || *r == BFD_RELOC_MIPS_GOT_DISP
3018 || *r == BFD_RELOC_MIPS_GOT_PAGE
3019 || *r == BFD_RELOC_MIPS_GOT_OFST
3020 || *r == BFD_RELOC_MIPS_GOT_LO16
3021 || *r == BFD_RELOC_MIPS_CALL_LO16
3022 || (ep->X_op == O_subtract
3023 && *r == BFD_RELOC_PCREL_LO16));
3027 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3029 && (ep->X_op == O_constant
3030 || (ep->X_op == O_symbol
3031 && (*r == BFD_RELOC_MIPS_HIGHEST
3032 || *r == BFD_RELOC_HI16_S
3033 || *r == BFD_RELOC_HI16
3034 || *r == BFD_RELOC_GPREL16
3035 || *r == BFD_RELOC_MIPS_GOT_HI16
3036 || *r == BFD_RELOC_MIPS_CALL_HI16))
3037 || (ep->X_op == O_subtract
3038 && *r == BFD_RELOC_PCREL_HI16_S)));
3042 assert (ep != NULL);
3044 * This allows macro() to pass an immediate expression for
3045 * creating short branches without creating a symbol.
3046 * Note that the expression still might come from the assembly
3047 * input, in which case the value is not checked for range nor
3048 * is a relocation entry generated (yuck).
3050 if (ep->X_op == O_constant)
3052 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3056 *r = BFD_RELOC_16_PCREL_S2;
3060 assert (ep != NULL);
3061 *r = BFD_RELOC_MIPS_JMP;
3065 insn.insn_opcode |= va_arg (args, unsigned long);
3074 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3076 append_insn (place, &insn, ep, r);
3080 mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
3081 expressionS *ep, const char *name, const char *fmt,
3084 struct mips_cl_insn insn;
3085 bfd_reloc_code_real_type r[3]
3086 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3088 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3089 assert (insn.insn_mo);
3090 assert (strcmp (name, insn.insn_mo->name) == 0);
3092 while (strcmp (fmt, insn.insn_mo->args) != 0
3093 || insn.insn_mo->pinfo == INSN_MACRO)
3096 assert (insn.insn_mo->name);
3097 assert (strcmp (name, insn.insn_mo->name) == 0);
3100 insn.insn_opcode = insn.insn_mo->match;
3101 insn.use_extend = FALSE;
3120 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3125 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3129 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3133 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3143 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3150 regno = va_arg (args, int);
3151 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3152 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3173 assert (ep != NULL);
3175 if (ep->X_op != O_constant)
3176 *r = (int) BFD_RELOC_UNUSED + c;
3179 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3180 FALSE, &insn.insn_opcode, &insn.use_extend,
3183 *r = BFD_RELOC_UNUSED;
3189 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3196 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3198 append_insn (place, &insn, ep, r);
3202 * Generate a "jalr" instruction with a relocation hint to the called
3203 * function. This occurs in NewABI PIC code.
3206 macro_build_jalr (int icnt, expressionS *ep)
3215 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3217 fix_new_exp (frag_now, f - frag_now->fr_literal,
3218 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3222 * Generate a "lui" instruction.
3225 macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
3227 expressionS high_expr;
3228 struct mips_cl_insn insn;
3229 bfd_reloc_code_real_type r[3]
3230 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3231 const char *name = "lui";
3232 const char *fmt = "t,u";
3234 assert (! mips_opts.mips16);
3240 high_expr.X_op = O_constant;
3241 high_expr.X_add_number = ep->X_add_number;
3244 if (high_expr.X_op == O_constant)
3246 /* we can compute the instruction now without a relocation entry */
3247 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3249 *r = BFD_RELOC_UNUSED;
3253 assert (ep->X_op == O_symbol);
3254 /* _gp_disp is a special case, used from s_cpload. */
3255 assert (mips_pic == NO_PIC
3257 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3258 *r = BFD_RELOC_HI16_S;
3262 * If the macro is about to expand into a second instruction,
3263 * print a warning if needed. We need to pass ip as a parameter
3264 * to generate a better warning message here...
3266 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3267 as_warn (_("Macro instruction expanded into multiple instructions"));
3270 ++*counter; /* bump instruction counter */
3272 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3273 assert (insn.insn_mo);
3274 assert (strcmp (name, insn.insn_mo->name) == 0);
3275 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3277 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3278 if (*r == BFD_RELOC_UNUSED)
3280 insn.insn_opcode |= high_expr.X_add_number;
3281 append_insn (place, &insn, NULL, r);
3284 append_insn (place, &insn, &high_expr, r);
3287 /* Generate a sequence of instructions to do a load or store from a constant
3288 offset off of a base register (breg) into/from a target register (treg),
3289 using AT if necessary. */
3291 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3292 const char *op, int treg, int breg, int dbl)
3294 assert (ep->X_op == O_constant);
3296 /* Sign-extending 32-bit constants makes their handling easier. */
3297 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3298 == ~((bfd_vma) 0x7fffffff)))
3300 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3301 as_bad (_("constant too large"));
3303 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3307 /* Right now, this routine can only handle signed 32-bit constants. */
3308 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3309 as_warn (_("operand overflow"));
3311 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3313 /* Signed 16-bit offset will fit in the op. Easy! */
3314 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3319 /* 32-bit offset, need multiple instructions and AT, like:
3320 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3321 addu $tempreg,$tempreg,$breg
3322 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3323 to handle the complete offset. */
3324 macro_build_lui (place, counter, ep, AT);
3327 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3331 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3335 as_warn (_("Macro used $at after \".set noat\""));
3340 * Generates code to set the $at register to true (one)
3341 * if reg is less than the immediate expression.
3344 set_at (int *counter, int reg, int unsignedp)
3346 if (imm_expr.X_op == O_constant
3347 && imm_expr.X_add_number >= -0x8000
3348 && imm_expr.X_add_number < 0x8000)
3349 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3350 "t,r,j", AT, reg, BFD_RELOC_LO16);
3353 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3354 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3355 "d,v,t", AT, reg, AT);
3360 normalize_constant_expr (expressionS *ex)
3362 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3363 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3367 /* Warn if an expression is not a constant. */
3370 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3372 if (ex->X_op == O_big)
3373 as_bad (_("unsupported large constant"));
3374 else if (ex->X_op != O_constant)
3375 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3377 normalize_constant_expr (ex);
3380 /* Count the leading zeroes by performing a binary chop. This is a
3381 bulky bit of source, but performance is a LOT better for the
3382 majority of values than a simple loop to count the bits:
3383 for (lcnt = 0; (lcnt < 32); lcnt++)
3384 if ((v) & (1 << (31 - lcnt)))
3386 However it is not code size friendly, and the gain will drop a bit
3387 on certain cached systems.
3389 #define COUNT_TOP_ZEROES(v) \
3390 (((v) & ~0xffff) == 0 \
3391 ? ((v) & ~0xff) == 0 \
3392 ? ((v) & ~0xf) == 0 \
3393 ? ((v) & ~0x3) == 0 \
3394 ? ((v) & ~0x1) == 0 \
3399 : ((v) & ~0x7) == 0 \
3402 : ((v) & ~0x3f) == 0 \
3403 ? ((v) & ~0x1f) == 0 \
3406 : ((v) & ~0x7f) == 0 \
3409 : ((v) & ~0xfff) == 0 \
3410 ? ((v) & ~0x3ff) == 0 \
3411 ? ((v) & ~0x1ff) == 0 \
3414 : ((v) & ~0x7ff) == 0 \
3417 : ((v) & ~0x3fff) == 0 \
3418 ? ((v) & ~0x1fff) == 0 \
3421 : ((v) & ~0x7fff) == 0 \
3424 : ((v) & ~0xffffff) == 0 \
3425 ? ((v) & ~0xfffff) == 0 \
3426 ? ((v) & ~0x3ffff) == 0 \
3427 ? ((v) & ~0x1ffff) == 0 \
3430 : ((v) & ~0x7ffff) == 0 \
3433 : ((v) & ~0x3fffff) == 0 \
3434 ? ((v) & ~0x1fffff) == 0 \
3437 : ((v) & ~0x7fffff) == 0 \
3440 : ((v) & ~0xfffffff) == 0 \
3441 ? ((v) & ~0x3ffffff) == 0 \
3442 ? ((v) & ~0x1ffffff) == 0 \
3445 : ((v) & ~0x7ffffff) == 0 \
3448 : ((v) & ~0x3fffffff) == 0 \
3449 ? ((v) & ~0x1fffffff) == 0 \
3452 : ((v) & ~0x7fffffff) == 0 \
3457 * This routine generates the least number of instructions necessary to load
3458 * an absolute expression value into a register.
3461 load_register (int *counter, int reg, expressionS *ep, int dbl)
3464 expressionS hi32, lo32;
3466 if (ep->X_op != O_big)
3468 assert (ep->X_op == O_constant);
3470 /* Sign-extending 32-bit constants makes their handling easier. */
3471 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3472 == ~((bfd_vma) 0x7fffffff)))
3474 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3475 as_bad (_("constant too large"));
3477 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3481 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3483 /* We can handle 16 bit signed values with an addiu to
3484 $zero. No need to ever use daddiu here, since $zero and
3485 the result are always correct in 32 bit mode. */
3486 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3490 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3492 /* We can handle 16 bit unsigned values with an ori to
3494 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3498 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3500 /* 32 bit values require an lui. */
3501 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3502 if ((ep->X_add_number & 0xffff) != 0)
3503 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3509 /* The value is larger than 32 bits. */
3511 if (HAVE_32BIT_GPRS)
3513 as_bad (_("Number (0x%lx) larger than 32 bits"),
3514 (unsigned long) ep->X_add_number);
3515 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3520 if (ep->X_op != O_big)
3523 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3524 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3525 hi32.X_add_number &= 0xffffffff;
3527 lo32.X_add_number &= 0xffffffff;
3531 assert (ep->X_add_number > 2);
3532 if (ep->X_add_number == 3)
3533 generic_bignum[3] = 0;
3534 else if (ep->X_add_number > 4)
3535 as_bad (_("Number larger than 64 bits"));
3536 lo32.X_op = O_constant;
3537 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3538 hi32.X_op = O_constant;
3539 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3542 if (hi32.X_add_number == 0)
3547 unsigned long hi, lo;
3549 if (hi32.X_add_number == (offsetT) 0xffffffff)
3551 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3553 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3557 if (lo32.X_add_number & 0x80000000)
3559 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3561 if (lo32.X_add_number & 0xffff)
3562 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3568 /* Check for 16bit shifted constant. We know that hi32 is
3569 non-zero, so start the mask on the first bit of the hi32
3574 unsigned long himask, lomask;
3578 himask = 0xffff >> (32 - shift);
3579 lomask = (0xffff << shift) & 0xffffffff;
3583 himask = 0xffff << (shift - 32);
3586 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3587 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3591 tmp.X_op = O_constant;
3593 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3594 | (lo32.X_add_number >> shift));
3596 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3597 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3599 macro_build (NULL, counter, NULL,
3600 (shift >= 32) ? "dsll32" : "dsll",
3602 (shift >= 32) ? shift - 32 : shift);
3607 while (shift <= (64 - 16));
3609 /* Find the bit number of the lowest one bit, and store the
3610 shifted value in hi/lo. */
3611 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3612 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3616 while ((lo & 1) == 0)
3621 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3627 while ((hi & 1) == 0)
3636 /* Optimize if the shifted value is a (power of 2) - 1. */
3637 if ((hi == 0 && ((lo + 1) & lo) == 0)
3638 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3640 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3645 /* This instruction will set the register to be all
3647 tmp.X_op = O_constant;
3648 tmp.X_add_number = (offsetT) -1;
3649 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3654 macro_build (NULL, counter, NULL,
3655 (bit >= 32) ? "dsll32" : "dsll",
3657 (bit >= 32) ? bit - 32 : bit);
3659 macro_build (NULL, counter, NULL,
3660 (shift >= 32) ? "dsrl32" : "dsrl",
3662 (shift >= 32) ? shift - 32 : shift);
3667 /* Sign extend hi32 before calling load_register, because we can
3668 generally get better code when we load a sign extended value. */
3669 if ((hi32.X_add_number & 0x80000000) != 0)
3670 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3671 load_register (counter, reg, &hi32, 0);
3674 if ((lo32.X_add_number & 0xffff0000) == 0)
3678 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3686 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3688 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3690 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3696 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3700 mid16.X_add_number >>= 16;
3701 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3703 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3706 if ((lo32.X_add_number & 0xffff) != 0)
3707 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3711 /* Load an address into a register. */
3714 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3718 if (ep->X_op != O_constant
3719 && ep->X_op != O_symbol)
3721 as_bad (_("expression too complex"));
3722 ep->X_op = O_constant;
3725 if (ep->X_op == O_constant)
3727 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3731 if (mips_pic == NO_PIC)
3733 /* If this is a reference to a GP relative symbol, we want
3734 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3736 lui $reg,<sym> (BFD_RELOC_HI16_S)
3737 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3738 If we have an addend, we always use the latter form.
3740 With 64bit address space and a usable $at we want
3741 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3742 lui $at,<sym> (BFD_RELOC_HI16_S)
3743 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3744 daddiu $at,<sym> (BFD_RELOC_LO16)
3748 If $at is already in use, we use a path which is suboptimal
3749 on superscalar processors.
3750 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3751 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3753 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3755 daddiu $reg,<sym> (BFD_RELOC_LO16)
3757 if (HAVE_64BIT_ADDRESSES)
3759 /* We don't do GP optimization for now because RELAX_ENCODE can't
3760 hold the data for such large chunks. */
3762 if (*used_at == 0 && ! mips_opts.noat)
3764 macro_build (p, counter, ep, "lui", "t,u",
3765 reg, BFD_RELOC_MIPS_HIGHEST);
3766 macro_build (p, counter, ep, "lui", "t,u",
3767 AT, BFD_RELOC_HI16_S);
3768 macro_build (p, counter, ep, "daddiu", "t,r,j",
3769 reg, reg, BFD_RELOC_MIPS_HIGHER);
3770 macro_build (p, counter, ep, "daddiu", "t,r,j",
3771 AT, AT, BFD_RELOC_LO16);
3772 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3773 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3778 macro_build (p, counter, ep, "lui", "t,u",
3779 reg, BFD_RELOC_MIPS_HIGHEST);
3780 macro_build (p, counter, ep, "daddiu", "t,r,j",
3781 reg, reg, BFD_RELOC_MIPS_HIGHER);
3782 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3783 macro_build (p, counter, ep, "daddiu", "t,r,j",
3784 reg, reg, BFD_RELOC_HI16_S);
3785 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3786 macro_build (p, counter, ep, "daddiu", "t,r,j",
3787 reg, reg, BFD_RELOC_LO16);
3792 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3793 && ! nopic_need_relax (ep->X_add_symbol, 1))
3796 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3797 mips_gp_register, BFD_RELOC_GPREL16);
3798 p = frag_var (rs_machine_dependent, 8, 0,
3799 RELAX_ENCODE (4, 8, 0, 4, 0,
3800 mips_opts.warn_about_macros),
3801 ep->X_add_symbol, 0, NULL);
3803 macro_build_lui (p, counter, ep, reg);
3806 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3810 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3814 /* If this is a reference to an external symbol, we want
3815 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3817 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3819 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3820 If there is a constant, it must be added in after.
3822 If we have NewABI, we want
3823 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3824 unless we're referencing a global symbol with a non-zero
3825 offset, in which case cst must be added separately. */
3830 if (ep->X_add_number)
3832 frag_now->tc_frag_data.tc_fr_offset =
3833 ex.X_add_number = ep->X_add_number;
3834 ep->X_add_number = 0;
3835 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3836 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3837 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3838 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3839 ex.X_op = O_constant;
3840 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3841 reg, reg, BFD_RELOC_LO16);
3842 p = frag_var (rs_machine_dependent, 8, 0,
3843 RELAX_ENCODE (8, 4, 0, 0, 0,
3844 mips_opts.warn_about_macros),
3845 ep->X_add_symbol, 0, NULL);
3846 ep->X_add_number = ex.X_add_number;
3849 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3850 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3854 /* To avoid confusion in tc_gen_reloc, we must ensure
3855 that this does not become a variant frag. */
3856 frag_wane (frag_now);
3862 ex.X_add_number = ep->X_add_number;
3863 ep->X_add_number = 0;
3865 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3866 BFD_RELOC_MIPS_GOT16,
3868 macro_build (NULL, counter, NULL, "nop", "");
3869 p = frag_var (rs_machine_dependent, 4, 0,
3870 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3871 ep->X_add_symbol, 0, NULL);
3872 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3875 if (ex.X_add_number != 0)
3877 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3878 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3879 ex.X_op = O_constant;
3880 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3881 reg, reg, BFD_RELOC_LO16);
3885 else if (mips_pic == SVR4_PIC)
3890 /* This is the large GOT case. If this is a reference to an
3891 external symbol, we want
3892 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3894 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3896 Otherwise, for a reference to a local symbol in old ABI, we want
3897 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3899 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3900 If there is a constant, it must be added in after.
3902 In the NewABI, for local symbols, with or without offsets, we want:
3903 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3904 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3910 frag_now->tc_frag_data.tc_fr_offset =
3911 ex.X_add_number = ep->X_add_number;
3912 ep->X_add_number = 0;
3913 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3914 BFD_RELOC_MIPS_GOT_HI16);
3915 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3916 reg, mips_gp_register);
3917 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3918 BFD_RELOC_MIPS_GOT_LO16, reg);
3919 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3920 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3921 else if (ex.X_add_number)
3923 ex.X_op = O_constant;
3924 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3925 reg, reg, BFD_RELOC_LO16);
3928 ep->X_add_number = ex.X_add_number;
3929 p = frag_var (rs_machine_dependent, 8, 0,
3930 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
3931 mips_opts.warn_about_macros),
3932 ep->X_add_symbol, 0, NULL);
3933 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3934 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3935 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3936 reg, BFD_RELOC_MIPS_GOT_OFST);
3940 ex.X_add_number = ep->X_add_number;
3941 ep->X_add_number = 0;
3942 if (reg_needs_delay (mips_gp_register))
3947 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3948 BFD_RELOC_MIPS_GOT_HI16);
3949 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3950 reg, mips_gp_register);
3951 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3952 BFD_RELOC_MIPS_GOT_LO16, reg);
3953 p = frag_var (rs_machine_dependent, 12 + off, 0,
3954 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3955 mips_opts.warn_about_macros),
3956 ep->X_add_symbol, 0, NULL);
3959 /* We need a nop before loading from $gp. This special
3960 check is required because the lui which starts the main
3961 instruction stream does not refer to $gp, and so will not
3962 insert the nop which may be required. */
3963 macro_build (p, counter, NULL, "nop", "");
3966 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3967 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3969 macro_build (p, counter, NULL, "nop", "");
3971 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3974 if (ex.X_add_number != 0)
3976 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3977 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3978 ex.X_op = O_constant;
3979 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3980 reg, reg, BFD_RELOC_LO16);
3984 else if (mips_pic == EMBEDDED_PIC)
3987 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3989 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3990 mips_gp_register, BFD_RELOC_GPREL16);
3996 /* Move the contents of register SOURCE into register DEST. */
3999 move_register (int *counter, int dest, int source)
4001 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
4002 "d,v,t", dest, source, 0);
4007 * This routine implements the seemingly endless macro or synthesized
4008 * instructions and addressing modes in the mips assembly language. Many
4009 * of these macros are simple and are similar to each other. These could
4010 * probably be handled by some kind of table or grammar approach instead of
4011 * this verbose method. Others are not simple macros but are more like
4012 * optimizing code generation.
4013 * One interesting optimization is when several store macros appear
4014 * consecutively that would load AT with the upper half of the same address.
4015 * The ensuing load upper instructions are ommited. This implies some kind
4016 * of global optimization. We currently only optimize within a single macro.
4017 * For many of the load and store macros if the address is specified as a
4018 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4019 * first load register 'at' with zero and use it as the base register. The
4020 * mips assembler simply uses register $zero. Just one tiny optimization
4024 macro (struct mips_cl_insn *ip)
4026 register int treg, sreg, dreg, breg;
4043 bfd_reloc_code_real_type r;
4044 int hold_mips_optimize;
4046 assert (! mips_opts.mips16);
4048 treg = (ip->insn_opcode >> 16) & 0x1f;
4049 dreg = (ip->insn_opcode >> 11) & 0x1f;
4050 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4051 mask = ip->insn_mo->mask;
4053 expr1.X_op = O_constant;
4054 expr1.X_op_symbol = NULL;
4055 expr1.X_add_symbol = NULL;
4056 expr1.X_add_number = 1;
4058 /* Unmatched fixups should not be put in the same frag as a relaxable
4059 macro. For example, suppose we have:
4063 addiu $4,$4,%lo(l1) # 3
4065 If instructions 1 and 2 were put in the same frag, md_frob_file would
4066 move the fixup for #1 after the fixups for the "unrelaxed" version of
4067 #2. This would confuse tc_gen_reloc, which expects the relocations
4068 for #2 to be the last for that frag.
4070 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4071 it assumes that they belong to a relaxable macro. We mustn't put
4072 other uses of such relocations into a variant frag.
4074 To avoid both problems, finish the current frag it contains a
4075 %reloc() operator. The macro then goes into a new frag. */
4076 if (prev_reloc_op_frag == frag_now)
4078 frag_wane (frag_now);
4092 mips_emit_delays (TRUE);
4093 ++mips_opts.noreorder;
4094 mips_any_noreorder = 1;
4096 expr1.X_add_number = 8;
4097 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4099 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4101 move_register (&icnt, dreg, sreg);
4102 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4105 --mips_opts.noreorder;
4126 if (imm_expr.X_op == O_constant
4127 && imm_expr.X_add_number >= -0x8000
4128 && imm_expr.X_add_number < 0x8000)
4130 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4134 load_register (&icnt, AT, &imm_expr, dbl);
4135 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4154 if (imm_expr.X_op == O_constant
4155 && imm_expr.X_add_number >= 0
4156 && imm_expr.X_add_number < 0x10000)
4158 if (mask != M_NOR_I)
4159 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4163 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4165 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4170 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4171 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4188 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4190 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4193 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4194 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4202 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4208 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4212 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4213 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4220 /* check for > max integer */
4221 maxnum = 0x7fffffff;
4222 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4229 if (imm_expr.X_op == O_constant
4230 && imm_expr.X_add_number >= maxnum
4231 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4234 /* result is always false */
4236 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4238 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4241 if (imm_expr.X_op != O_constant)
4242 as_bad (_("Unsupported large constant"));
4243 ++imm_expr.X_add_number;
4247 if (mask == M_BGEL_I)
4249 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4251 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4255 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4257 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4261 maxnum = 0x7fffffff;
4262 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4269 maxnum = - maxnum - 1;
4270 if (imm_expr.X_op == O_constant
4271 && imm_expr.X_add_number <= maxnum
4272 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4275 /* result is always true */
4276 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4277 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4280 set_at (&icnt, sreg, 0);
4281 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4292 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4296 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4297 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4306 && imm_expr.X_op == O_constant
4307 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4309 if (imm_expr.X_op != O_constant)
4310 as_bad (_("Unsupported large constant"));
4311 ++imm_expr.X_add_number;
4315 if (mask == M_BGEUL_I)
4317 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4319 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4321 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4325 set_at (&icnt, sreg, 1);
4326 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4335 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4341 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4345 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4346 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4355 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4361 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4362 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4371 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4377 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4381 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4382 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4389 maxnum = 0x7fffffff;
4390 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4397 if (imm_expr.X_op == O_constant
4398 && imm_expr.X_add_number >= maxnum
4399 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4401 if (imm_expr.X_op != O_constant)
4402 as_bad (_("Unsupported large constant"));
4403 ++imm_expr.X_add_number;
4407 if (mask == M_BLTL_I)
4409 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4411 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4415 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4417 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4421 set_at (&icnt, sreg, 0);
4422 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4431 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4437 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4438 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4447 && imm_expr.X_op == O_constant
4448 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4450 if (imm_expr.X_op != O_constant)
4451 as_bad (_("Unsupported large constant"));
4452 ++imm_expr.X_add_number;
4456 if (mask == M_BLTUL_I)
4458 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4460 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4462 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4466 set_at (&icnt, sreg, 1);
4467 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4476 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4482 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4486 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4487 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4498 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4502 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4503 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4512 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4514 as_bad (_("Unsupported large constant"));
4519 pos = (unsigned long) imm_expr.X_add_number;
4520 size = (unsigned long) imm2_expr.X_add_number;
4525 as_bad (_("Improper position (%lu)"), pos);
4528 if (size == 0 || size > 64
4529 || (pos + size - 1) > 63)
4531 as_bad (_("Improper extract size (%lu, position %lu)"),
4536 if (size <= 32 && pos < 32)
4541 else if (size <= 32)
4551 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4552 fmt, treg, sreg, pos, size - 1);
4561 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4563 as_bad (_("Unsupported large constant"));
4568 pos = (unsigned long) imm_expr.X_add_number;
4569 size = (unsigned long) imm2_expr.X_add_number;
4574 as_bad (_("Improper position (%lu)"), pos);
4577 if (size == 0 || size > 64
4578 || (pos + size - 1) > 63)
4580 as_bad (_("Improper insert size (%lu, position %lu)"),
4585 if (pos < 32 && (pos + size - 1) < 32)
4600 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4601 fmt, treg, sreg, pos, pos + size - 1);
4617 as_warn (_("Divide by zero."));
4619 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4621 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4625 mips_emit_delays (TRUE);
4626 ++mips_opts.noreorder;
4627 mips_any_noreorder = 1;
4630 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4631 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4636 expr1.X_add_number = 8;
4637 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4638 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4640 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4642 expr1.X_add_number = -1;
4643 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4644 AT, 0, BFD_RELOC_LO16);
4645 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4646 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4649 expr1.X_add_number = 1;
4650 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4652 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4656 expr1.X_add_number = 0x80000000;
4657 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4662 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4663 /* We want to close the noreorder block as soon as possible, so
4664 that later insns are available for delay slot filling. */
4665 --mips_opts.noreorder;
4669 expr1.X_add_number = 8;
4670 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4671 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4673 /* We want to close the noreorder block as soon as possible, so
4674 that later insns are available for delay slot filling. */
4675 --mips_opts.noreorder;
4677 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4679 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4718 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4720 as_warn (_("Divide by zero."));
4722 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4724 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4727 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4729 if (strcmp (s2, "mflo") == 0)
4730 move_register (&icnt, dreg, sreg);
4732 move_register (&icnt, dreg, 0);
4735 if (imm_expr.X_op == O_constant
4736 && imm_expr.X_add_number == -1
4737 && s[strlen (s) - 1] != 'u')
4739 if (strcmp (s2, "mflo") == 0)
4741 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4745 move_register (&icnt, dreg, 0);
4749 load_register (&icnt, AT, &imm_expr, dbl);
4750 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4751 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4770 mips_emit_delays (TRUE);
4771 ++mips_opts.noreorder;
4772 mips_any_noreorder = 1;
4775 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4776 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4777 /* We want to close the noreorder block as soon as possible, so
4778 that later insns are available for delay slot filling. */
4779 --mips_opts.noreorder;
4783 expr1.X_add_number = 8;
4784 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4785 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4787 /* We want to close the noreorder block as soon as possible, so
4788 that later insns are available for delay slot filling. */
4789 --mips_opts.noreorder;
4790 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4792 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4804 /* Load the address of a symbol into a register. If breg is not
4805 zero, we then add a base register to it. */
4807 if (dbl && HAVE_32BIT_GPRS)
4808 as_warn (_("dla used to load 32-bit register"));
4810 if (! dbl && HAVE_64BIT_OBJECTS)
4811 as_warn (_("la used to load 64-bit address"));
4813 if (offset_expr.X_op == O_constant
4814 && offset_expr.X_add_number >= -0x8000
4815 && offset_expr.X_add_number < 0x8000)
4817 macro_build (NULL, &icnt, &offset_expr,
4818 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4819 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4834 /* When generating embedded PIC code, we permit expressions of
4837 la $treg,foo-bar($breg)
4838 where bar is an address in the current section. These are used
4839 when getting the addresses of functions. We don't permit
4840 X_add_number to be non-zero, because if the symbol is
4841 external the relaxing code needs to know that any addend is
4842 purely the offset to X_op_symbol. */
4843 if (mips_pic == EMBEDDED_PIC
4844 && offset_expr.X_op == O_subtract
4845 && (symbol_constant_p (offset_expr.X_op_symbol)
4846 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4847 : (symbol_equated_p (offset_expr.X_op_symbol)
4849 (symbol_get_value_expression (offset_expr.X_op_symbol)
4852 && (offset_expr.X_add_number == 0
4853 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4859 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4860 BFD_RELOC_PCREL_HI16_S);
4864 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4865 BFD_RELOC_PCREL_HI16_S);
4866 macro_build (NULL, &icnt, NULL,
4867 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4868 "d,v,t", tempreg, tempreg, breg);
4870 macro_build (NULL, &icnt, &offset_expr,
4871 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4872 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4878 if (offset_expr.X_op != O_symbol
4879 && offset_expr.X_op != O_constant)
4881 as_bad (_("expression too complex"));
4882 offset_expr.X_op = O_constant;
4885 if (offset_expr.X_op == O_constant)
4886 load_register (&icnt, tempreg, &offset_expr,
4887 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4888 ? (dbl || HAVE_64BIT_ADDRESSES)
4889 : HAVE_64BIT_ADDRESSES));
4890 else if (mips_pic == NO_PIC)
4892 /* If this is a reference to a GP relative symbol, we want
4893 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4895 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4896 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4897 If we have a constant, we need two instructions anyhow,
4898 so we may as well always use the latter form.
4900 With 64bit address space and a usable $at we want
4901 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4902 lui $at,<sym> (BFD_RELOC_HI16_S)
4903 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4904 daddiu $at,<sym> (BFD_RELOC_LO16)
4906 daddu $tempreg,$tempreg,$at
4908 If $at is already in use, we use a path which is suboptimal
4909 on superscalar processors.
4910 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4911 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4913 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4915 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4918 if (HAVE_64BIT_ADDRESSES)
4920 /* We don't do GP optimization for now because RELAX_ENCODE can't
4921 hold the data for such large chunks. */
4923 if (used_at == 0 && ! mips_opts.noat)
4925 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4926 tempreg, BFD_RELOC_MIPS_HIGHEST);
4927 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4928 AT, BFD_RELOC_HI16_S);
4929 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4930 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4931 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4932 AT, AT, BFD_RELOC_LO16);
4933 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4934 tempreg, tempreg, 0);
4935 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4936 tempreg, tempreg, AT);
4941 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4942 tempreg, BFD_RELOC_MIPS_HIGHEST);
4943 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4944 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4945 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4946 tempreg, tempreg, 16);
4947 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4948 tempreg, tempreg, BFD_RELOC_HI16_S);
4949 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4950 tempreg, tempreg, 16);
4951 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4952 tempreg, tempreg, BFD_RELOC_LO16);
4957 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4958 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4961 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4962 "t,r,j", tempreg, mips_gp_register,
4964 p = frag_var (rs_machine_dependent, 8, 0,
4965 RELAX_ENCODE (4, 8, 0, 4, 0,
4966 mips_opts.warn_about_macros),
4967 offset_expr.X_add_symbol, 0, NULL);
4969 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4972 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4973 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4976 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4978 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4980 /* If this is a reference to an external symbol, and there
4981 is no constant, we want
4982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4983 or for lca or if tempreg is PIC_CALL_REG
4984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4985 For a local symbol, we want
4986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4988 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4990 If we have a small constant, and this is a reference to
4991 an external symbol, we want
4992 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4994 addiu $tempreg,$tempreg,<constant>
4995 For a local symbol, we want the same instruction
4996 sequence, but we output a BFD_RELOC_LO16 reloc on the
4999 If we have a large constant, and this is a reference to
5000 an external symbol, we want
5001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5002 lui $at,<hiconstant>
5003 addiu $at,$at,<loconstant>
5004 addu $tempreg,$tempreg,$at
5005 For a local symbol, we want the same instruction
5006 sequence, but we output a BFD_RELOC_LO16 reloc on the
5010 expr1.X_add_number = offset_expr.X_add_number;
5011 offset_expr.X_add_number = 0;
5013 if (expr1.X_add_number == 0 && breg == 0
5014 && (call || tempreg == PIC_CALL_REG))
5015 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5016 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5017 tempreg, lw_reloc_type, mips_gp_register);
5018 if (expr1.X_add_number == 0)
5027 /* We're going to put in an addu instruction using
5028 tempreg, so we may as well insert the nop right
5030 macro_build (NULL, &icnt, NULL, "nop", "");
5033 p = frag_var (rs_machine_dependent, 8 - off, 0,
5034 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
5036 ? mips_opts.warn_about_macros
5038 offset_expr.X_add_symbol, 0, NULL);
5041 macro_build (p, &icnt, NULL, "nop", "");
5044 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5045 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5046 /* FIXME: If breg == 0, and the next instruction uses
5047 $tempreg, then if this variant case is used an extra
5048 nop will be generated. */
5050 else if (expr1.X_add_number >= -0x8000
5051 && expr1.X_add_number < 0x8000)
5053 macro_build (NULL, &icnt, NULL, "nop", "");
5054 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5055 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5056 frag_var (rs_machine_dependent, 0, 0,
5057 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5058 offset_expr.X_add_symbol, 0, NULL);
5064 /* If we are going to add in a base register, and the
5065 target register and the base register are the same,
5066 then we are using AT as a temporary register. Since
5067 we want to load the constant into AT, we add our
5068 current AT (from the global offset table) and the
5069 register into the register now, and pretend we were
5070 not using a base register. */
5075 macro_build (NULL, &icnt, NULL, "nop", "");
5076 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5083 /* Set mips_optimize around the lui instruction to avoid
5084 inserting an unnecessary nop after the lw. */
5085 hold_mips_optimize = mips_optimize;
5087 macro_build_lui (NULL, &icnt, &expr1, AT);
5088 mips_optimize = hold_mips_optimize;
5090 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5091 AT, AT, BFD_RELOC_LO16);
5092 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5093 tempreg, tempreg, AT);
5094 frag_var (rs_machine_dependent, 0, 0,
5095 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5096 offset_expr.X_add_symbol, 0, NULL);
5100 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5103 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5106 /* If this is a reference to an external, and there is no
5107 constant, or local symbol (*), with or without a
5109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5110 or for lca or if tempreg is PIC_CALL_REG
5111 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5113 If we have a small constant, and this is a reference to
5114 an external symbol, we want
5115 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5116 addiu $tempreg,$tempreg,<constant>
5118 If we have a large constant, and this is a reference to
5119 an external symbol, we want
5120 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5121 lui $at,<hiconstant>
5122 addiu $at,$at,<loconstant>
5123 addu $tempreg,$tempreg,$at
5125 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5126 local symbols, even though it introduces an additional
5130 if (offset_expr.X_add_number == 0 && breg == 0
5131 && (call || tempreg == PIC_CALL_REG))
5132 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5133 if (offset_expr.X_add_number)
5135 frag_now->tc_frag_data.tc_fr_offset =
5136 expr1.X_add_number = offset_expr.X_add_number;
5137 offset_expr.X_add_number = 0;
5139 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5140 "t,o(b)", tempreg, lw_reloc_type,
5143 if (expr1.X_add_number >= -0x8000
5144 && expr1.X_add_number < 0x8000)
5146 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5147 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5148 p = frag_var (rs_machine_dependent, 4, 0,
5149 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5150 offset_expr.X_add_symbol, 0, NULL);
5152 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5156 /* If we are going to add in a base register, and the
5157 target register and the base register are the same,
5158 then we are using AT as a temporary register. Since
5159 we want to load the constant into AT, we add our
5160 current AT (from the global offset table) and the
5161 register into the register now, and pretend we were
5162 not using a base register. */
5167 assert (tempreg == AT);
5168 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN,
5169 "d,v,t", treg, AT, breg);
5174 macro_build_lui (NULL, &icnt, &expr1, AT);
5175 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5176 "t,r,j", AT, AT, BFD_RELOC_LO16);
5177 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5180 p = frag_var (rs_machine_dependent, 4 + adj, 0,
5181 RELAX_ENCODE (16 + adj, 4 + adj,
5183 offset_expr.X_add_symbol, 0, NULL);
5188 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5190 offset_expr.X_add_number = expr1.X_add_number;
5192 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5193 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5197 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5198 treg, tempreg, breg);
5205 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5206 "t,o(b)", tempreg, lw_reloc_type,
5208 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5209 p = frag_var (rs_machine_dependent, 0, 0,
5210 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5211 offset_expr.X_add_symbol, 0, NULL);
5216 /* To avoid confusion in tc_gen_reloc, we must ensure
5217 that this does not become a variant frag. */
5218 frag_wane (frag_now);
5222 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5226 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5227 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5228 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5230 /* This is the large GOT case. If this is a reference to an
5231 external symbol, and there is no constant, we want
5232 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5233 addu $tempreg,$tempreg,$gp
5234 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5235 or for lca or if tempreg is PIC_CALL_REG
5236 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5237 addu $tempreg,$tempreg,$gp
5238 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5239 For a local symbol, we want
5240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5242 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5244 If we have a small constant, and this is a reference to
5245 an external symbol, we want
5246 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5247 addu $tempreg,$tempreg,$gp
5248 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5250 addiu $tempreg,$tempreg,<constant>
5251 For a local symbol, we want
5252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5254 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5256 If we have a large constant, and this is a reference to
5257 an external symbol, we want
5258 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5259 addu $tempreg,$tempreg,$gp
5260 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5261 lui $at,<hiconstant>
5262 addiu $at,$at,<loconstant>
5263 addu $tempreg,$tempreg,$at
5264 For a local symbol, we want
5265 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5266 lui $at,<hiconstant>
5267 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5268 addu $tempreg,$tempreg,$at
5271 expr1.X_add_number = offset_expr.X_add_number;
5272 offset_expr.X_add_number = 0;
5274 if (reg_needs_delay (mips_gp_register))
5278 if (expr1.X_add_number == 0 && breg == 0
5279 && (call || tempreg == PIC_CALL_REG))
5281 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5282 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5284 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5285 tempreg, lui_reloc_type);
5286 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5287 tempreg, tempreg, mips_gp_register);
5288 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5289 tempreg, lw_reloc_type, tempreg);
5290 if (expr1.X_add_number == 0)
5298 /* We're going to put in an addu instruction using
5299 tempreg, so we may as well insert the nop right
5301 macro_build (NULL, &icnt, NULL, "nop", "");
5305 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5306 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5309 ? mips_opts.warn_about_macros
5311 offset_expr.X_add_symbol, 0, NULL);
5313 else if (expr1.X_add_number >= -0x8000
5314 && expr1.X_add_number < 0x8000)
5316 macro_build (NULL, &icnt, NULL, "nop", "");
5317 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5318 tempreg, tempreg, BFD_RELOC_LO16);
5320 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5321 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5323 ? mips_opts.warn_about_macros
5325 offset_expr.X_add_symbol, 0, NULL);
5331 /* If we are going to add in a base register, and the
5332 target register and the base register are the same,
5333 then we are using AT as a temporary register. Since
5334 we want to load the constant into AT, we add our
5335 current AT (from the global offset table) and the
5336 register into the register now, and pretend we were
5337 not using a base register. */
5345 assert (tempreg == AT);
5346 macro_build (NULL, &icnt, NULL, "nop", "");
5347 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5353 /* Set mips_optimize around the lui instruction to avoid
5354 inserting an unnecessary nop after the lw. */
5355 hold_mips_optimize = mips_optimize;
5357 macro_build_lui (NULL, &icnt, &expr1, AT);
5358 mips_optimize = hold_mips_optimize;
5360 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5361 AT, AT, BFD_RELOC_LO16);
5362 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5365 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5366 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5369 ? mips_opts.warn_about_macros
5371 offset_expr.X_add_symbol, 0, NULL);
5378 /* This is needed because this instruction uses $gp, but
5379 the first instruction on the main stream does not. */
5380 macro_build (p, &icnt, NULL, "nop", "");
5384 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5385 tempreg, local_reloc_type, mips_gp_register);
5387 if (expr1.X_add_number >= -0x8000
5388 && expr1.X_add_number < 0x8000)
5390 macro_build (p, &icnt, NULL, "nop", "");
5392 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5393 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5394 /* FIXME: If add_number is 0, and there was no base
5395 register, the external symbol case ended with a load,
5396 so if the symbol turns out to not be external, and
5397 the next instruction uses tempreg, an unnecessary nop
5398 will be inserted. */
5404 /* We must add in the base register now, as in the
5405 external symbol case. */
5406 assert (tempreg == AT);
5407 macro_build (p, &icnt, NULL, "nop", "");
5409 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5413 /* We set breg to 0 because we have arranged to add
5414 it in in both cases. */
5418 macro_build_lui (p, &icnt, &expr1, AT);
5420 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5421 AT, AT, BFD_RELOC_LO16);
5423 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5424 tempreg, tempreg, AT);
5428 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5431 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5432 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5435 /* This is the large GOT case. If this is a reference to an
5436 external symbol, and there is no constant, we want
5437 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5438 add $tempreg,$tempreg,$gp
5439 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5440 or for lca or if tempreg is PIC_CALL_REG
5441 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5442 add $tempreg,$tempreg,$gp
5443 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5445 If we have a small constant, and this is a reference to
5446 an external symbol, we want
5447 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5448 add $tempreg,$tempreg,$gp
5449 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5450 addi $tempreg,$tempreg,<constant>
5452 If we have a large constant, and this is a reference to
5453 an external symbol, we want
5454 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5455 addu $tempreg,$tempreg,$gp
5456 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5457 lui $at,<hiconstant>
5458 addi $at,$at,<loconstant>
5459 add $tempreg,$tempreg,$at
5461 If we have NewABI, and we know it's a local symbol, we want
5462 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5463 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5464 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5468 frag_now->tc_frag_data.tc_fr_offset =
5469 expr1.X_add_number = offset_expr.X_add_number;
5470 offset_expr.X_add_number = 0;
5472 if (expr1.X_add_number == 0 && breg == 0
5473 && (call || tempreg == PIC_CALL_REG))
5475 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5476 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5478 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5479 tempreg, lui_reloc_type);
5480 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5481 tempreg, tempreg, mips_gp_register);
5482 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5483 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5485 if (expr1.X_add_number == 0)
5487 p = frag_var (rs_machine_dependent, 8, 0,
5488 RELAX_ENCODE (12, 8, 0, 4, 0,
5489 mips_opts.warn_about_macros),
5490 offset_expr.X_add_symbol, 0, NULL);
5492 else if (expr1.X_add_number >= -0x8000
5493 && expr1.X_add_number < 0x8000)
5495 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5496 tempreg, tempreg, BFD_RELOC_LO16);
5497 p = frag_var (rs_machine_dependent, 8, 0,
5498 RELAX_ENCODE (16, 8, 0, 4, 0,
5499 mips_opts.warn_about_macros),
5500 offset_expr.X_add_symbol, 0, NULL);
5502 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5506 /* If we are going to add in a base register, and the
5507 target register and the base register are the same,
5508 then we are using AT as a temporary register. Since
5509 we want to load the constant into AT, we add our
5510 current AT (from the global offset table) and the
5511 register into the register now, and pretend we were
5512 not using a base register. */
5517 assert (tempreg == AT);
5518 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5524 /* Set mips_optimize around the lui instruction to avoid
5525 inserting an unnecessary nop after the lw. */
5526 macro_build_lui (NULL, &icnt, &expr1, AT);
5527 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5528 "t,r,j", AT, AT, BFD_RELOC_LO16);
5529 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5532 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5533 RELAX_ENCODE (24 + adj, 8 + adj,
5536 ? mips_opts.warn_about_macros
5538 offset_expr.X_add_symbol, 0, NULL);
5543 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5545 offset_expr.X_add_number = expr1.X_add_number;
5546 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5547 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5548 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5549 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5552 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5553 treg, tempreg, breg);
5558 else if (mips_pic == EMBEDDED_PIC)
5561 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5563 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5564 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5573 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5574 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5576 s = ADDRESS_ADD_INSN;
5578 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5587 /* The j instruction may not be used in PIC code, since it
5588 requires an absolute address. We convert it to a b
5590 if (mips_pic == NO_PIC)
5591 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5593 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5596 /* The jal instructions must be handled as macros because when
5597 generating PIC code they expand to multi-instruction
5598 sequences. Normally they are simple instructions. */
5603 if (mips_pic == NO_PIC
5604 || mips_pic == EMBEDDED_PIC)
5605 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5606 else if (mips_pic == SVR4_PIC)
5608 if (sreg != PIC_CALL_REG)
5609 as_warn (_("MIPS PIC call to register other than $25"));
5611 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5614 if (mips_cprestore_offset < 0)
5615 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5618 if (! mips_frame_reg_valid)
5620 as_warn (_("No .frame pseudo-op used in PIC code"));
5621 /* Quiet this warning. */
5622 mips_frame_reg_valid = 1;
5624 if (! mips_cprestore_valid)
5626 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5627 /* Quiet this warning. */
5628 mips_cprestore_valid = 1;
5630 expr1.X_add_number = mips_cprestore_offset;
5631 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5635 HAVE_64BIT_ADDRESSES);
5645 if (mips_pic == NO_PIC)
5646 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5647 else if (mips_pic == SVR4_PIC)
5651 /* If this is a reference to an external symbol, and we are
5652 using a small GOT, we want
5653 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5657 lw $gp,cprestore($sp)
5658 The cprestore value is set using the .cprestore
5659 pseudo-op. If we are using a big GOT, we want
5660 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5662 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5666 lw $gp,cprestore($sp)
5667 If the symbol is not external, we want
5668 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5670 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5673 lw $gp,cprestore($sp)
5675 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5676 sequences above, minus nops, unless the symbol is local,
5677 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5684 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5685 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5687 frag_var (rs_machine_dependent, 0, 0,
5688 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5689 offset_expr.X_add_symbol, 0, NULL);
5694 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5695 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5696 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5697 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5698 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5699 "t,o(b)", PIC_CALL_REG,
5700 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5701 p = frag_var (rs_machine_dependent, 8, 0,
5702 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5703 offset_expr.X_add_symbol, 0, NULL);
5704 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5705 "t,o(b)", PIC_CALL_REG,
5706 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5707 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5708 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5709 BFD_RELOC_MIPS_GOT_OFST);
5712 macro_build_jalr (icnt, &offset_expr);
5719 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5720 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5722 macro_build (NULL, &icnt, NULL, "nop", "");
5723 p = frag_var (rs_machine_dependent, 4, 0,
5724 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5725 offset_expr.X_add_symbol, 0, NULL);
5731 if (reg_needs_delay (mips_gp_register))
5735 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5736 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5737 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5738 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5739 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5740 "t,o(b)", PIC_CALL_REG,
5741 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5742 macro_build (NULL, &icnt, NULL, "nop", "");
5743 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5744 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5746 offset_expr.X_add_symbol, 0, NULL);
5749 macro_build (p, &icnt, NULL, "nop", "");
5752 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5753 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5756 macro_build (p, &icnt, NULL, "nop", "");
5759 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5760 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5762 macro_build_jalr (icnt, &offset_expr);
5764 if (mips_cprestore_offset < 0)
5765 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5768 if (! mips_frame_reg_valid)
5770 as_warn (_("No .frame pseudo-op used in PIC code"));
5771 /* Quiet this warning. */
5772 mips_frame_reg_valid = 1;
5774 if (! mips_cprestore_valid)
5776 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5777 /* Quiet this warning. */
5778 mips_cprestore_valid = 1;
5780 if (mips_opts.noreorder)
5781 macro_build (NULL, &icnt, NULL, "nop", "");
5782 expr1.X_add_number = mips_cprestore_offset;
5783 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5787 HAVE_64BIT_ADDRESSES);
5791 else if (mips_pic == EMBEDDED_PIC)
5793 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5794 /* The linker may expand the call to a longer sequence which
5795 uses $at, so we must break rather than return. */
5820 /* Itbl support may require additional care here. */
5825 /* Itbl support may require additional care here. */
5830 /* Itbl support may require additional care here. */
5835 /* Itbl support may require additional care here. */
5847 if (mips_opts.arch == CPU_R4650)
5849 as_bad (_("opcode not supported on this processor"));
5853 /* Itbl support may require additional care here. */
5858 /* Itbl support may require additional care here. */
5863 /* Itbl support may require additional care here. */
5883 if (breg == treg || coproc || lr)
5905 /* Itbl support may require additional care here. */
5910 /* Itbl support may require additional care here. */
5915 /* Itbl support may require additional care here. */
5920 /* Itbl support may require additional care here. */
5936 if (mips_opts.arch == CPU_R4650)
5938 as_bad (_("opcode not supported on this processor"));
5943 /* Itbl support may require additional care here. */
5947 /* Itbl support may require additional care here. */
5952 /* Itbl support may require additional care here. */
5964 /* Itbl support may require additional care here. */
5965 if (mask == M_LWC1_AB
5966 || mask == M_SWC1_AB
5967 || mask == M_LDC1_AB
5968 || mask == M_SDC1_AB
5977 /* Sign-extending 32-bit constants makes their handling easier.
5978 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5980 if ((! HAVE_64BIT_ADDRESSES
5981 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5982 && (offset_expr.X_op == O_constant)
5983 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5984 == ~((bfd_vma) 0x7fffffff)))
5986 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5987 as_bad (_("constant too large"));
5989 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5990 ^ 0x80000000) - 0x80000000);
5993 /* For embedded PIC, we allow loads where the offset is calculated
5994 by subtracting a symbol in the current segment from an unknown
5995 symbol, relative to a base register, e.g.:
5996 <op> $treg, <sym>-<localsym>($breg)
5997 This is used by the compiler for switch statements. */
5998 if (mips_pic == EMBEDDED_PIC
5999 && offset_expr.X_op == O_subtract
6000 && (symbol_constant_p (offset_expr.X_op_symbol)
6001 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
6002 : (symbol_equated_p (offset_expr.X_op_symbol)
6004 (symbol_get_value_expression (offset_expr.X_op_symbol)
6008 && (offset_expr.X_add_number == 0
6009 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
6011 /* For this case, we output the instructions:
6012 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6013 addiu $tempreg,$tempreg,$breg
6014 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6015 If the relocation would fit entirely in 16 bits, it would be
6017 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6018 instead, but that seems quite difficult. */
6019 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6020 BFD_RELOC_PCREL_HI16_S);
6021 macro_build (NULL, &icnt, NULL,
6022 ((bfd_arch_bits_per_address (stdoutput) == 32
6023 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
6024 ? "addu" : "daddu"),
6025 "d,v,t", tempreg, tempreg, breg);
6026 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6027 BFD_RELOC_PCREL_LO16, tempreg);
6033 if (offset_expr.X_op != O_constant
6034 && offset_expr.X_op != O_symbol)
6036 as_bad (_("expression too complex"));
6037 offset_expr.X_op = O_constant;
6040 /* A constant expression in PIC code can be handled just as it
6041 is in non PIC code. */
6042 if (mips_pic == NO_PIC
6043 || offset_expr.X_op == O_constant)
6047 /* If this is a reference to a GP relative symbol, and there
6048 is no base register, we want
6049 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6050 Otherwise, if there is no base register, we want
6051 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6052 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6053 If we have a constant, we need two instructions anyhow,
6054 so we always use the latter form.
6056 If we have a base register, and this is a reference to a
6057 GP relative symbol, we want
6058 addu $tempreg,$breg,$gp
6059 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6061 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6062 addu $tempreg,$tempreg,$breg
6063 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6064 With a constant we always use the latter case.
6066 With 64bit address space and no base register and $at usable,
6068 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6069 lui $at,<sym> (BFD_RELOC_HI16_S)
6070 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6073 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6074 If we have a base register, we want
6075 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6076 lui $at,<sym> (BFD_RELOC_HI16_S)
6077 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6081 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6083 Without $at we can't generate the optimal path for superscalar
6084 processors here since this would require two temporary registers.
6085 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6086 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6088 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6090 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6091 If we have a base register, we want
6092 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6093 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6095 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6097 daddu $tempreg,$tempreg,$breg
6098 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6100 If we have 64-bit addresses, as an optimization, for
6101 addresses which are 32-bit constants (e.g. kseg0/kseg1
6102 addresses) we fall back to the 32-bit address generation
6103 mechanism since it is more efficient. Note that due to
6104 the signed offset used by memory operations, the 32-bit
6105 range is shifted down by 32768 here. This code should
6106 probably attempt to generate 64-bit constants more
6107 efficiently in general.
6109 As an extension for architectures with 64-bit registers,
6110 we don't truncate 64-bit addresses given as literal
6111 constants down to 32 bits, to support existing practice
6112 in the mips64 Linux (the kernel), that compiles source
6113 files with -mabi=64, assembling them as o32 or n32 (with
6114 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6115 the whole kernel is loaded into a memory region that is
6116 addressable with sign-extended 32-bit addresses, it is
6117 wasteful to compute the upper 32 bits of every
6118 non-literal address, that takes more space and time.
6119 Some day this should probably be implemented as an
6120 assembler option, such that the kernel doesn't have to
6121 use such ugly hacks, even though it will still have to
6122 end up converting the binary to ELF32 for a number of
6123 platforms whose boot loaders don't support ELF64
6125 if ((HAVE_64BIT_ADDRESSES
6126 && ! (offset_expr.X_op == O_constant
6127 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6129 && offset_expr.X_op == O_constant
6130 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6134 /* We don't do GP optimization for now because RELAX_ENCODE can't
6135 hold the data for such large chunks. */
6137 if (used_at == 0 && ! mips_opts.noat)
6139 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6140 tempreg, BFD_RELOC_MIPS_HIGHEST);
6141 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6142 AT, BFD_RELOC_HI16_S);
6143 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6144 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6146 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6148 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
6149 tempreg, tempreg, 0);
6150 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6151 tempreg, tempreg, AT);
6152 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6153 BFD_RELOC_LO16, tempreg);
6158 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6159 tempreg, BFD_RELOC_MIPS_HIGHEST);
6160 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6161 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6162 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6163 tempreg, tempreg, 16);
6164 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6165 tempreg, tempreg, BFD_RELOC_HI16_S);
6166 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6167 tempreg, tempreg, 16);
6169 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6170 tempreg, tempreg, breg);
6171 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6172 BFD_RELOC_LO16, tempreg);
6178 if (offset_expr.X_op == O_constant
6179 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6180 as_bad (_("load/store address overflow (max 32 bits)"));
6184 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6185 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6190 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6191 BFD_RELOC_GPREL16, mips_gp_register);
6192 p = frag_var (rs_machine_dependent, 8, 0,
6193 RELAX_ENCODE (4, 8, 0, 4, 0,
6194 (mips_opts.warn_about_macros
6196 && mips_opts.noat))),
6197 offset_expr.X_add_symbol, 0, NULL);
6200 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6203 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6204 BFD_RELOC_LO16, tempreg);
6208 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6209 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6214 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6215 tempreg, breg, mips_gp_register);
6216 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6217 BFD_RELOC_GPREL16, tempreg);
6218 p = frag_var (rs_machine_dependent, 12, 0,
6219 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6220 offset_expr.X_add_symbol, 0, NULL);
6222 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6225 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6226 tempreg, tempreg, breg);
6229 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6230 BFD_RELOC_LO16, tempreg);
6233 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6236 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6238 /* If this is a reference to an external symbol, we want
6239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6241 <op> $treg,0($tempreg)
6243 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6245 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6246 <op> $treg,0($tempreg)
6249 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6250 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6252 If there is a base register, we add it to $tempreg before
6253 the <op>. If there is a constant, we stick it in the
6254 <op> instruction. We don't handle constants larger than
6255 16 bits, because we have no way to load the upper 16 bits
6256 (actually, we could handle them for the subset of cases
6257 in which we are not using $at). */
6258 assert (offset_expr.X_op == O_symbol);
6261 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6262 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6265 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6266 tempreg, tempreg, breg);
6267 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6268 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6275 expr1.X_add_number = offset_expr.X_add_number;
6276 offset_expr.X_add_number = 0;
6277 if (expr1.X_add_number < -0x8000
6278 || expr1.X_add_number >= 0x8000)
6279 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6281 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6282 tempreg, lw_reloc_type, mips_gp_register);
6283 macro_build (NULL, &icnt, NULL, "nop", "");
6284 p = frag_var (rs_machine_dependent, 4, 0,
6285 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6286 offset_expr.X_add_symbol, 0, NULL);
6287 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6288 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6290 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6291 tempreg, tempreg, breg);
6292 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6295 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6300 /* If this is a reference to an external symbol, we want
6301 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6302 addu $tempreg,$tempreg,$gp
6303 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6304 <op> $treg,0($tempreg)
6306 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6308 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6309 <op> $treg,0($tempreg)
6310 If there is a base register, we add it to $tempreg before
6311 the <op>. If there is a constant, we stick it in the
6312 <op> instruction. We don't handle constants larger than
6313 16 bits, because we have no way to load the upper 16 bits
6314 (actually, we could handle them for the subset of cases
6315 in which we are not using $at). */
6316 assert (offset_expr.X_op == O_symbol);
6317 expr1.X_add_number = offset_expr.X_add_number;
6318 offset_expr.X_add_number = 0;
6319 if (expr1.X_add_number < -0x8000
6320 || expr1.X_add_number >= 0x8000)
6321 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6322 if (reg_needs_delay (mips_gp_register))
6327 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6328 BFD_RELOC_MIPS_GOT_HI16);
6329 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6330 tempreg, tempreg, mips_gp_register);
6331 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6332 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6333 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6334 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6335 offset_expr.X_add_symbol, 0, NULL);
6338 macro_build (p, &icnt, NULL, "nop", "");
6341 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6342 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6344 macro_build (p, &icnt, NULL, "nop", "");
6346 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6347 tempreg, tempreg, BFD_RELOC_LO16);
6349 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6350 tempreg, tempreg, breg);
6351 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6354 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6357 int bregsz = breg != 0 ? 4 : 0;
6359 /* If this is a reference to an external symbol, we want
6360 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6361 add $tempreg,$tempreg,$gp
6362 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6363 <op> $treg,<ofst>($tempreg)
6364 Otherwise, for local symbols, we want:
6365 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6366 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6367 assert (offset_expr.X_op == O_symbol);
6369 frag_now->tc_frag_data.tc_fr_offset =
6370 expr1.X_add_number = offset_expr.X_add_number;
6371 offset_expr.X_add_number = 0;
6372 if (expr1.X_add_number < -0x8000
6373 || expr1.X_add_number >= 0x8000)
6374 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6375 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6376 BFD_RELOC_MIPS_GOT_HI16);
6377 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6378 tempreg, tempreg, mips_gp_register);
6379 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6380 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6382 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6383 tempreg, tempreg, breg);
6384 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6387 offset_expr.X_add_number = expr1.X_add_number;
6388 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6389 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6390 0, 4 + bregsz, 0, 0),
6391 offset_expr.X_add_symbol, 0, NULL);
6392 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6393 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6395 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6396 tempreg, tempreg, breg);
6397 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6398 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6400 else if (mips_pic == EMBEDDED_PIC)
6402 /* If there is no base register, we want
6403 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6404 If there is a base register, we want
6405 addu $tempreg,$breg,$gp
6406 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6408 assert (offset_expr.X_op == O_symbol);
6411 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6412 BFD_RELOC_GPREL16, mips_gp_register);
6417 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6418 tempreg, breg, mips_gp_register);
6419 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6420 BFD_RELOC_GPREL16, tempreg);
6433 load_register (&icnt, treg, &imm_expr, 0);
6437 load_register (&icnt, treg, &imm_expr, 1);
6441 if (imm_expr.X_op == O_constant)
6443 load_register (&icnt, AT, &imm_expr, 0);
6444 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6449 assert (offset_expr.X_op == O_symbol
6450 && strcmp (segment_name (S_GET_SEGMENT
6451 (offset_expr.X_add_symbol)),
6453 && offset_expr.X_add_number == 0);
6454 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6455 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6460 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6461 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6462 order 32 bits of the value and the low order 32 bits are either
6463 zero or in OFFSET_EXPR. */
6464 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6466 if (HAVE_64BIT_GPRS)
6467 load_register (&icnt, treg, &imm_expr, 1);
6472 if (target_big_endian)
6484 load_register (&icnt, hreg, &imm_expr, 0);
6487 if (offset_expr.X_op == O_absent)
6488 move_register (&icnt, lreg, 0);
6491 assert (offset_expr.X_op == O_constant);
6492 load_register (&icnt, lreg, &offset_expr, 0);
6499 /* We know that sym is in the .rdata section. First we get the
6500 upper 16 bits of the address. */
6501 if (mips_pic == NO_PIC)
6503 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6505 else if (mips_pic == SVR4_PIC)
6507 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6508 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6510 else if (mips_pic == EMBEDDED_PIC)
6512 /* For embedded PIC we pick up the entire address off $gp in
6513 a single instruction. */
6514 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6515 AT, mips_gp_register, BFD_RELOC_GPREL16);
6516 offset_expr.X_op = O_constant;
6517 offset_expr.X_add_number = 0;
6522 /* Now we load the register(s). */
6523 if (HAVE_64BIT_GPRS)
6524 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6525 BFD_RELOC_LO16, AT);
6528 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6529 BFD_RELOC_LO16, AT);
6532 /* FIXME: How in the world do we deal with the possible
6534 offset_expr.X_add_number += 4;
6535 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6536 treg + 1, BFD_RELOC_LO16, AT);
6540 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6541 does not become a variant frag. */
6542 frag_wane (frag_now);
6548 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6549 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6550 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6551 the value and the low order 32 bits are either zero or in
6553 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6555 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6556 if (HAVE_64BIT_FPRS)
6558 assert (HAVE_64BIT_GPRS);
6559 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6563 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6564 if (offset_expr.X_op == O_absent)
6565 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6568 assert (offset_expr.X_op == O_constant);
6569 load_register (&icnt, AT, &offset_expr, 0);
6570 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6576 assert (offset_expr.X_op == O_symbol
6577 && offset_expr.X_add_number == 0);
6578 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6579 if (strcmp (s, ".lit8") == 0)
6581 if (mips_opts.isa != ISA_MIPS1)
6583 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6584 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6587 breg = mips_gp_register;
6588 r = BFD_RELOC_MIPS_LITERAL;
6593 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6594 if (mips_pic == SVR4_PIC)
6595 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6596 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6600 /* FIXME: This won't work for a 64 bit address. */
6601 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6604 if (mips_opts.isa != ISA_MIPS1)
6606 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6607 BFD_RELOC_LO16, AT);
6609 /* To avoid confusion in tc_gen_reloc, we must ensure
6610 that this does not become a variant frag. */
6611 frag_wane (frag_now);
6622 if (mips_opts.arch == CPU_R4650)
6624 as_bad (_("opcode not supported on this processor"));
6627 /* Even on a big endian machine $fn comes before $fn+1. We have
6628 to adjust when loading from memory. */
6631 assert (mips_opts.isa == ISA_MIPS1);
6632 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6633 target_big_endian ? treg + 1 : treg, r, breg);
6634 /* FIXME: A possible overflow which I don't know how to deal
6636 offset_expr.X_add_number += 4;
6637 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6638 target_big_endian ? treg : treg + 1, r, breg);
6640 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6641 does not become a variant frag. */
6642 frag_wane (frag_now);
6651 * The MIPS assembler seems to check for X_add_number not
6652 * being double aligned and generating:
6655 * addiu at,at,%lo(foo+1)
6658 * But, the resulting address is the same after relocation so why
6659 * generate the extra instruction?
6661 if (mips_opts.arch == CPU_R4650)
6663 as_bad (_("opcode not supported on this processor"));
6666 /* Itbl support may require additional care here. */
6668 if (mips_opts.isa != ISA_MIPS1)
6679 if (mips_opts.arch == CPU_R4650)
6681 as_bad (_("opcode not supported on this processor"));
6685 if (mips_opts.isa != ISA_MIPS1)
6693 /* Itbl support may require additional care here. */
6698 if (HAVE_64BIT_GPRS)
6709 if (HAVE_64BIT_GPRS)
6719 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6720 loads for the case of doing a pair of loads to simulate an 'ld'.
6721 This is not currently done by the compiler, and assembly coders
6722 writing embedded-pic code can cope. */
6724 if (offset_expr.X_op != O_symbol
6725 && offset_expr.X_op != O_constant)
6727 as_bad (_("expression too complex"));
6728 offset_expr.X_op = O_constant;
6731 /* Even on a big endian machine $fn comes before $fn+1. We have
6732 to adjust when loading from memory. We set coproc if we must
6733 load $fn+1 first. */
6734 /* Itbl support may require additional care here. */
6735 if (! target_big_endian)
6738 if (mips_pic == NO_PIC
6739 || offset_expr.X_op == O_constant)
6743 /* If this is a reference to a GP relative symbol, we want
6744 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6745 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6746 If we have a base register, we use this
6748 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6749 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6750 If this is not a GP relative symbol, we want
6751 lui $at,<sym> (BFD_RELOC_HI16_S)
6752 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6753 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6754 If there is a base register, we add it to $at after the
6755 lui instruction. If there is a constant, we always use
6757 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6758 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6770 tempreg = mips_gp_register;
6777 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6778 AT, breg, mips_gp_register);
6784 /* Itbl support may require additional care here. */
6785 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6786 coproc ? treg + 1 : treg,
6787 BFD_RELOC_GPREL16, tempreg);
6788 offset_expr.X_add_number += 4;
6790 /* Set mips_optimize to 2 to avoid inserting an
6792 hold_mips_optimize = mips_optimize;
6794 /* Itbl support may require additional care here. */
6795 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6796 coproc ? treg : treg + 1,
6797 BFD_RELOC_GPREL16, tempreg);
6798 mips_optimize = hold_mips_optimize;
6800 p = frag_var (rs_machine_dependent, 12 + off, 0,
6801 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6802 used_at && mips_opts.noat),
6803 offset_expr.X_add_symbol, 0, NULL);
6805 /* We just generated two relocs. When tc_gen_reloc
6806 handles this case, it will skip the first reloc and
6807 handle the second. The second reloc already has an
6808 extra addend of 4, which we added above. We must
6809 subtract it out, and then subtract another 4 to make
6810 the first reloc come out right. The second reloc
6811 will come out right because we are going to add 4 to
6812 offset_expr when we build its instruction below.
6814 If we have a symbol, then we don't want to include
6815 the offset, because it will wind up being included
6816 when we generate the reloc. */
6818 if (offset_expr.X_op == O_constant)
6819 offset_expr.X_add_number -= 8;
6822 offset_expr.X_add_number = -4;
6823 offset_expr.X_op = O_constant;
6826 macro_build_lui (p, &icnt, &offset_expr, AT);
6831 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6836 /* Itbl support may require additional care here. */
6837 macro_build (p, &icnt, &offset_expr, s, fmt,
6838 coproc ? treg + 1 : treg,
6839 BFD_RELOC_LO16, AT);
6842 /* FIXME: How do we handle overflow here? */
6843 offset_expr.X_add_number += 4;
6844 /* Itbl support may require additional care here. */
6845 macro_build (p, &icnt, &offset_expr, s, fmt,
6846 coproc ? treg : treg + 1,
6847 BFD_RELOC_LO16, AT);
6849 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6853 /* If this is a reference to an external symbol, we want
6854 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6859 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6861 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6862 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6863 If there is a base register we add it to $at before the
6864 lwc1 instructions. If there is a constant we include it
6865 in the lwc1 instructions. */
6867 expr1.X_add_number = offset_expr.X_add_number;
6868 offset_expr.X_add_number = 0;
6869 if (expr1.X_add_number < -0x8000
6870 || expr1.X_add_number >= 0x8000 - 4)
6871 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6876 frag_grow (24 + off);
6877 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6878 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6879 macro_build (NULL, &icnt, NULL, "nop", "");
6881 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6883 /* Itbl support may require additional care here. */
6884 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6885 BFD_RELOC_LO16, AT);
6886 expr1.X_add_number += 4;
6888 /* Set mips_optimize to 2 to avoid inserting an undesired
6890 hold_mips_optimize = mips_optimize;
6892 /* Itbl support may require additional care here. */
6893 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6894 BFD_RELOC_LO16, AT);
6895 mips_optimize = hold_mips_optimize;
6897 (void) frag_var (rs_machine_dependent, 0, 0,
6898 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6899 offset_expr.X_add_symbol, 0, NULL);
6901 else if (mips_pic == SVR4_PIC)
6906 /* If this is a reference to an external symbol, we want
6907 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6909 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6914 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6916 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6917 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6918 If there is a base register we add it to $at before the
6919 lwc1 instructions. If there is a constant we include it
6920 in the lwc1 instructions. */
6922 expr1.X_add_number = offset_expr.X_add_number;
6923 offset_expr.X_add_number = 0;
6924 if (expr1.X_add_number < -0x8000
6925 || expr1.X_add_number >= 0x8000 - 4)
6926 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6927 if (reg_needs_delay (mips_gp_register))
6936 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6937 BFD_RELOC_MIPS_GOT_HI16);
6938 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6939 AT, AT, mips_gp_register);
6940 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6941 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6942 macro_build (NULL, &icnt, NULL, "nop", "");
6944 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6946 /* Itbl support may require additional care here. */
6947 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6948 BFD_RELOC_LO16, AT);
6949 expr1.X_add_number += 4;
6951 /* Set mips_optimize to 2 to avoid inserting an undesired
6953 hold_mips_optimize = mips_optimize;
6955 /* Itbl support may require additional care here. */
6956 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6957 BFD_RELOC_LO16, AT);
6958 mips_optimize = hold_mips_optimize;
6959 expr1.X_add_number -= 4;
6961 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6962 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6963 8 + gpdel + off, 1, 0),
6964 offset_expr.X_add_symbol, 0, NULL);
6967 macro_build (p, &icnt, NULL, "nop", "");
6970 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6971 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6973 macro_build (p, &icnt, NULL, "nop", "");
6977 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6981 /* Itbl support may require additional care here. */
6982 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6983 BFD_RELOC_LO16, AT);
6985 expr1.X_add_number += 4;
6987 /* Set mips_optimize to 2 to avoid inserting an undesired
6989 hold_mips_optimize = mips_optimize;
6991 /* Itbl support may require additional care here. */
6992 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6993 BFD_RELOC_LO16, AT);
6994 mips_optimize = hold_mips_optimize;
6996 else if (mips_pic == EMBEDDED_PIC)
6998 /* If there is no base register, we use
6999 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7000 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7001 If we have a base register, we use
7003 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7004 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7008 tempreg = mips_gp_register;
7013 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7014 AT, breg, mips_gp_register);
7019 /* Itbl support may require additional care here. */
7020 macro_build (NULL, &icnt, &offset_expr, s, fmt,
7021 coproc ? treg + 1 : treg,
7022 BFD_RELOC_GPREL16, tempreg);
7023 offset_expr.X_add_number += 4;
7024 /* Itbl support may require additional care here. */
7025 macro_build (NULL, &icnt, &offset_expr, s, fmt,
7026 coproc ? treg : treg + 1,
7027 BFD_RELOC_GPREL16, tempreg);
7043 assert (HAVE_32BIT_ADDRESSES);
7044 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7045 BFD_RELOC_LO16, breg);
7046 offset_expr.X_add_number += 4;
7047 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
7048 BFD_RELOC_LO16, breg);
7051 /* New code added to support COPZ instructions.
7052 This code builds table entries out of the macros in mip_opcodes.
7053 R4000 uses interlocks to handle coproc delays.
7054 Other chips (like the R3000) require nops to be inserted for delays.
7056 FIXME: Currently, we require that the user handle delays.
7057 In order to fill delay slots for non-interlocked chips,
7058 we must have a way to specify delays based on the coprocessor.
7059 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7060 What are the side-effects of the cop instruction?
7061 What cache support might we have and what are its effects?
7062 Both coprocessor & memory require delays. how long???
7063 What registers are read/set/modified?
7065 If an itbl is provided to interpret cop instructions,
7066 this knowledge can be encoded in the itbl spec. */
7080 /* For now we just do C (same as Cz). The parameter will be
7081 stored in insn_opcode by mips_ip. */
7082 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
7086 move_register (&icnt, dreg, sreg);
7089 #ifdef LOSING_COMPILER
7091 /* Try and see if this is a new itbl instruction.
7092 This code builds table entries out of the macros in mip_opcodes.
7093 FIXME: For now we just assemble the expression and pass it's
7094 value along as a 32-bit immediate.
7095 We may want to have the assembler assemble this value,
7096 so that we gain the assembler's knowledge of delay slots,
7098 Would it be more efficient to use mask (id) here? */
7099 if (itbl_have_entries
7100 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7102 s = ip->insn_mo->name;
7104 coproc = ITBL_DECODE_PNUM (immed_expr);;
7105 macro_build (NULL, &icnt, &immed_expr, s, "C");
7112 as_warn (_("Macro used $at after \".set noat\""));
7116 macro2 (struct mips_cl_insn *ip)
7118 register int treg, sreg, dreg, breg;
7134 bfd_reloc_code_real_type r;
7137 treg = (ip->insn_opcode >> 16) & 0x1f;
7138 dreg = (ip->insn_opcode >> 11) & 0x1f;
7139 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7140 mask = ip->insn_mo->mask;
7142 expr1.X_op = O_constant;
7143 expr1.X_op_symbol = NULL;
7144 expr1.X_add_symbol = NULL;
7145 expr1.X_add_number = 1;
7149 #endif /* LOSING_COMPILER */
7154 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7156 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7162 /* The MIPS assembler some times generates shifts and adds. I'm
7163 not trying to be that fancy. GCC should do this for us
7165 load_register (&icnt, AT, &imm_expr, dbl);
7166 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7168 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7181 mips_emit_delays (TRUE);
7182 ++mips_opts.noreorder;
7183 mips_any_noreorder = 1;
7185 load_register (&icnt, AT, &imm_expr, dbl);
7186 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7187 sreg, imm ? AT : treg);
7188 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7189 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
7191 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7193 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7196 expr1.X_add_number = 8;
7197 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7198 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7199 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7201 --mips_opts.noreorder;
7202 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7215 mips_emit_delays (TRUE);
7216 ++mips_opts.noreorder;
7217 mips_any_noreorder = 1;
7219 load_register (&icnt, AT, &imm_expr, dbl);
7220 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7221 sreg, imm ? AT : treg);
7222 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7223 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7225 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7228 expr1.X_add_number = 8;
7229 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7230 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7231 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7233 --mips_opts.noreorder;
7237 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7249 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7250 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7256 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7257 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7258 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7259 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7263 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7275 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7276 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7282 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7283 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7284 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7285 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7293 if (imm_expr.X_op != O_constant)
7294 as_bad (_("Improper rotate count"));
7295 rot = imm_expr.X_add_number & 0x3f;
7296 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7298 rot = (64 - rot) & 0x3f;
7300 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7301 dreg, sreg, rot - 32);
7303 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7309 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7312 l = (rot < 0x20) ? "dsll" : "dsll32";
7313 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7315 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7316 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7317 (0x20 - rot) & 0x1f);
7318 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7326 if (imm_expr.X_op != O_constant)
7327 as_bad (_("Improper rotate count"));
7328 rot = imm_expr.X_add_number & 0x1f;
7329 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7331 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7337 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7340 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7341 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7342 (0x20 - rot) & 0x1f);
7343 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7348 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7350 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7353 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7354 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7355 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7356 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7360 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7362 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7365 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7366 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7367 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7368 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7376 if (imm_expr.X_op != O_constant)
7377 as_bad (_("Improper rotate count"));
7378 rot = imm_expr.X_add_number & 0x3f;
7379 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7382 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7383 dreg, sreg, rot - 32);
7385 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7391 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7394 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7395 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7397 macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot);
7398 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7399 (0x20 - rot) & 0x1f);
7400 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7408 if (imm_expr.X_op != O_constant)
7409 as_bad (_("Improper rotate count"));
7410 rot = imm_expr.X_add_number & 0x1f;
7411 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7413 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7418 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7421 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7422 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7423 (0x20 - rot) & 0x1f);
7424 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7429 if (mips_opts.arch == CPU_R4650)
7431 as_bad (_("opcode not supported on this processor"));
7434 assert (mips_opts.isa == ISA_MIPS1);
7435 /* Even on a big endian machine $fn comes before $fn+1. We have
7436 to adjust when storing to memory. */
7437 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7438 target_big_endian ? treg + 1 : treg,
7439 BFD_RELOC_LO16, breg);
7440 offset_expr.X_add_number += 4;
7441 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7442 target_big_endian ? treg : treg + 1,
7443 BFD_RELOC_LO16, breg);
7448 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7451 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7455 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7456 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7462 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7464 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7470 as_warn (_("Instruction %s: result is always false"),
7472 move_register (&icnt, dreg, 0);
7475 if (imm_expr.X_op == O_constant
7476 && imm_expr.X_add_number >= 0
7477 && imm_expr.X_add_number < 0x10000)
7479 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7483 else if (imm_expr.X_op == O_constant
7484 && imm_expr.X_add_number > -0x8000
7485 && imm_expr.X_add_number < 0)
7487 imm_expr.X_add_number = -imm_expr.X_add_number;
7488 macro_build (NULL, &icnt, &imm_expr,
7489 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7490 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7495 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7496 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7499 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7505 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7511 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7512 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7516 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7518 if (imm_expr.X_op == O_constant
7519 && imm_expr.X_add_number >= -0x8000
7520 && imm_expr.X_add_number < 0x8000)
7522 macro_build (NULL, &icnt, &imm_expr,
7523 mask == M_SGE_I ? "slti" : "sltiu",
7524 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7529 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7530 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7531 "d,v,t", dreg, sreg, AT);
7534 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7540 case M_SGT: /* sreg > treg <==> treg < sreg */
7546 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7549 case M_SGT_I: /* sreg > I <==> I < sreg */
7555 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7556 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7559 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7565 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7566 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7570 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7576 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7577 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7578 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7583 if (imm_expr.X_op == O_constant
7584 && imm_expr.X_add_number >= -0x8000
7585 && imm_expr.X_add_number < 0x8000)
7587 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7591 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7592 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7596 if (imm_expr.X_op == O_constant
7597 && imm_expr.X_add_number >= -0x8000
7598 && imm_expr.X_add_number < 0x8000)
7600 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7604 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7605 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7610 macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg);
7612 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7615 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7616 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7621 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7623 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7628 as_warn (_("Instruction %s: result is always true"),
7630 macro_build (NULL, &icnt, &expr1,
7631 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7632 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7635 if (imm_expr.X_op == O_constant
7636 && imm_expr.X_add_number >= 0
7637 && imm_expr.X_add_number < 0x10000)
7639 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7643 else if (imm_expr.X_op == O_constant
7644 && imm_expr.X_add_number > -0x8000
7645 && imm_expr.X_add_number < 0)
7647 imm_expr.X_add_number = -imm_expr.X_add_number;
7648 macro_build (NULL, &icnt, &imm_expr,
7649 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7650 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7655 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7656 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7659 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7667 if (imm_expr.X_op == O_constant
7668 && imm_expr.X_add_number > -0x8000
7669 && imm_expr.X_add_number <= 0x8000)
7671 imm_expr.X_add_number = -imm_expr.X_add_number;
7672 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7673 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7676 load_register (&icnt, AT, &imm_expr, dbl);
7677 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7684 if (imm_expr.X_op == O_constant
7685 && imm_expr.X_add_number > -0x8000
7686 && imm_expr.X_add_number <= 0x8000)
7688 imm_expr.X_add_number = -imm_expr.X_add_number;
7689 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7690 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7693 load_register (&icnt, AT, &imm_expr, dbl);
7694 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7716 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7717 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7722 assert (mips_opts.isa == ISA_MIPS1);
7723 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7724 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7727 * Is the double cfc1 instruction a bug in the mips assembler;
7728 * or is there a reason for it?
7730 mips_emit_delays (TRUE);
7731 ++mips_opts.noreorder;
7732 mips_any_noreorder = 1;
7733 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7734 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7735 macro_build (NULL, &icnt, NULL, "nop", "");
7736 expr1.X_add_number = 3;
7737 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7739 expr1.X_add_number = 2;
7740 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7742 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7743 macro_build (NULL, &icnt, NULL, "nop", "");
7744 macro_build (NULL, &icnt, NULL,
7745 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7747 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7748 macro_build (NULL, &icnt, NULL, "nop", "");
7749 --mips_opts.noreorder;
7758 if (offset_expr.X_add_number >= 0x7fff)
7759 as_bad (_("operand overflow"));
7760 if (! target_big_endian)
7761 ++offset_expr.X_add_number;
7762 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7763 BFD_RELOC_LO16, breg);
7764 if (! target_big_endian)
7765 --offset_expr.X_add_number;
7767 ++offset_expr.X_add_number;
7768 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7769 BFD_RELOC_LO16, breg);
7770 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7771 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7784 if (offset_expr.X_add_number >= 0x8000 - off)
7785 as_bad (_("operand overflow"));
7790 if (! target_big_endian)
7791 offset_expr.X_add_number += off;
7792 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7793 BFD_RELOC_LO16, breg);
7794 if (! target_big_endian)
7795 offset_expr.X_add_number -= off;
7797 offset_expr.X_add_number += off;
7798 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7799 BFD_RELOC_LO16, breg);
7801 /* If necessary, move the result in tempreg the final destination. */
7802 if (treg == tempreg)
7804 /* Protect second load's delay slot. */
7805 if (!gpr_interlocks)
7806 macro_build (NULL, &icnt, NULL, "nop", "");
7807 move_register (&icnt, treg, tempreg);
7821 load_address (&icnt, AT, &offset_expr, &used_at);
7823 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7825 if (! target_big_endian)
7826 expr1.X_add_number = off;
7828 expr1.X_add_number = 0;
7829 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7830 BFD_RELOC_LO16, AT);
7831 if (! target_big_endian)
7832 expr1.X_add_number = 0;
7834 expr1.X_add_number = off;
7835 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7836 BFD_RELOC_LO16, AT);
7842 load_address (&icnt, AT, &offset_expr, &used_at);
7844 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7846 if (target_big_endian)
7847 expr1.X_add_number = 0;
7848 macro_build (NULL, &icnt, &expr1,
7849 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7850 treg, BFD_RELOC_LO16, AT);
7851 if (target_big_endian)
7852 expr1.X_add_number = 1;
7854 expr1.X_add_number = 0;
7855 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7856 AT, BFD_RELOC_LO16, AT);
7857 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7858 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7862 if (offset_expr.X_add_number >= 0x7fff)
7863 as_bad (_("operand overflow"));
7864 if (target_big_endian)
7865 ++offset_expr.X_add_number;
7866 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7867 BFD_RELOC_LO16, breg);
7868 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7869 if (target_big_endian)
7870 --offset_expr.X_add_number;
7872 ++offset_expr.X_add_number;
7873 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7874 BFD_RELOC_LO16, breg);
7887 if (offset_expr.X_add_number >= 0x8000 - off)
7888 as_bad (_("operand overflow"));
7889 if (! target_big_endian)
7890 offset_expr.X_add_number += off;
7891 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7892 BFD_RELOC_LO16, breg);
7893 if (! target_big_endian)
7894 offset_expr.X_add_number -= off;
7896 offset_expr.X_add_number += off;
7897 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7898 BFD_RELOC_LO16, breg);
7912 load_address (&icnt, AT, &offset_expr, &used_at);
7914 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7916 if (! target_big_endian)
7917 expr1.X_add_number = off;
7919 expr1.X_add_number = 0;
7920 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7921 BFD_RELOC_LO16, AT);
7922 if (! target_big_endian)
7923 expr1.X_add_number = 0;
7925 expr1.X_add_number = off;
7926 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7927 BFD_RELOC_LO16, AT);
7932 load_address (&icnt, AT, &offset_expr, &used_at);
7934 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7936 if (! target_big_endian)
7937 expr1.X_add_number = 0;
7938 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7939 BFD_RELOC_LO16, AT);
7940 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7941 if (! target_big_endian)
7942 expr1.X_add_number = 1;
7944 expr1.X_add_number = 0;
7945 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7946 BFD_RELOC_LO16, AT);
7947 if (! target_big_endian)
7948 expr1.X_add_number = 0;
7950 expr1.X_add_number = 1;
7951 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7952 BFD_RELOC_LO16, AT);
7953 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7954 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7958 /* FIXME: Check if this is one of the itbl macros, since they
7959 are added dynamically. */
7960 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7964 as_warn (_("Macro used $at after \".set noat\""));
7967 /* Implement macros in mips16 mode. */
7970 mips16_macro (struct mips_cl_insn *ip)
7973 int xreg, yreg, zreg, tmp;
7977 const char *s, *s2, *s3;
7979 mask = ip->insn_mo->mask;
7981 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7982 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7983 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7987 expr1.X_op = O_constant;
7988 expr1.X_op_symbol = NULL;
7989 expr1.X_add_symbol = NULL;
7990 expr1.X_add_number = 1;
8009 mips_emit_delays (TRUE);
8010 ++mips_opts.noreorder;
8011 mips_any_noreorder = 1;
8012 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
8014 expr1.X_add_number = 2;
8015 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8016 macro_build (NULL, &icnt, NULL, "break", "6", 7);
8018 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8019 since that causes an overflow. We should do that as well,
8020 but I don't see how to do the comparisons without a temporary
8022 --mips_opts.noreorder;
8023 macro_build (NULL, &icnt, NULL, s, "x", zreg);
8042 mips_emit_delays (TRUE);
8043 ++mips_opts.noreorder;
8044 mips_any_noreorder = 1;
8045 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
8046 expr1.X_add_number = 2;
8047 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8048 macro_build (NULL, &icnt, NULL, "break", "6", 7);
8049 --mips_opts.noreorder;
8050 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
8056 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
8058 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
8066 if (imm_expr.X_op != O_constant)
8067 as_bad (_("Unsupported large constant"));
8068 imm_expr.X_add_number = -imm_expr.X_add_number;
8069 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
8074 if (imm_expr.X_op != O_constant)
8075 as_bad (_("Unsupported large constant"));
8076 imm_expr.X_add_number = -imm_expr.X_add_number;
8077 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
8081 if (imm_expr.X_op != O_constant)
8082 as_bad (_("Unsupported large constant"));
8083 imm_expr.X_add_number = -imm_expr.X_add_number;
8084 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
8106 goto do_reverse_branch;
8110 goto do_reverse_branch;
8122 goto do_reverse_branch;
8133 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
8134 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8161 goto do_addone_branch_i;
8166 goto do_addone_branch_i;
8181 goto do_addone_branch_i;
8188 if (imm_expr.X_op != O_constant)
8189 as_bad (_("Unsupported large constant"));
8190 ++imm_expr.X_add_number;
8193 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8194 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8198 expr1.X_add_number = 0;
8199 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8201 move_register (&icnt, xreg, yreg);
8202 expr1.X_add_number = 2;
8203 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8204 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8208 /* For consistency checking, verify that all bits are specified either
8209 by the match/mask part of the instruction definition, or by the
8212 validate_mips_insn (const struct mips_opcode *opc)
8214 const char *p = opc->args;
8216 unsigned long used_bits = opc->mask;
8218 if ((used_bits & opc->match) != opc->match)
8220 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8221 opc->name, opc->args);
8224 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8234 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8235 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8236 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8237 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8238 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8239 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8240 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8241 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8242 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8245 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8246 c, opc->name, opc->args);
8250 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8251 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8253 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8254 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8255 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8256 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8258 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8259 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8261 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8262 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8264 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8265 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8266 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8267 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8268 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8269 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8270 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8271 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8272 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8273 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8274 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8275 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8276 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8277 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8278 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8279 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8280 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8282 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8283 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8284 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8285 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8287 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8288 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8289 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8290 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8291 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8292 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8293 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8294 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8295 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8298 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8299 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8300 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8301 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8302 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8306 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8307 c, opc->name, opc->args);
8311 if (used_bits != 0xffffffff)
8313 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8314 ~used_bits & 0xffffffff, opc->name, opc->args);
8320 /* This routine assembles an instruction into its binary format. As a
8321 side effect, it sets one of the global variables imm_reloc or
8322 offset_reloc to the type of relocation to do if one of the operands
8323 is an address expression. */
8326 mips_ip (char *str, struct mips_cl_insn *ip)
8331 struct mips_opcode *insn;
8334 unsigned int lastregno = 0;
8335 unsigned int lastpos = 0;
8336 unsigned int limlo, limhi;
8342 /* If the instruction contains a '.', we first try to match an instruction
8343 including the '.'. Then we try again without the '.'. */
8345 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8348 /* If we stopped on whitespace, then replace the whitespace with null for
8349 the call to hash_find. Save the character we replaced just in case we
8350 have to re-parse the instruction. */
8357 insn = (struct mips_opcode *) hash_find (op_hash, str);
8359 /* If we didn't find the instruction in the opcode table, try again, but
8360 this time with just the instruction up to, but not including the
8364 /* Restore the character we overwrite above (if any). */
8368 /* Scan up to the first '.' or whitespace. */
8370 *s != '\0' && *s != '.' && !ISSPACE (*s);
8374 /* If we did not find a '.', then we can quit now. */
8377 insn_error = "unrecognized opcode";
8381 /* Lookup the instruction in the hash table. */
8383 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8385 insn_error = "unrecognized opcode";
8395 assert (strcmp (insn->name, str) == 0);
8397 if (OPCODE_IS_MEMBER (insn,
8399 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8400 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8401 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8407 if (insn->pinfo != INSN_MACRO)
8409 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8415 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8416 && strcmp (insn->name, insn[1].name) == 0)
8425 static char buf[100];
8427 _("opcode not supported on this processor: %s (%s)"),
8428 mips_cpu_info_from_arch (mips_opts.arch)->name,
8429 mips_cpu_info_from_isa (mips_opts.isa)->name);
8439 ip->insn_opcode = insn->match;
8441 for (args = insn->args;; ++args)
8445 s += strspn (s, " \t");
8449 case '\0': /* end of args */
8462 ip->insn_opcode |= lastregno << OP_SH_RS;
8466 ip->insn_opcode |= lastregno << OP_SH_RT;
8470 ip->insn_opcode |= lastregno << OP_SH_FT;
8474 ip->insn_opcode |= lastregno << OP_SH_FS;
8480 /* Handle optional base register.
8481 Either the base register is omitted or
8482 we must have a left paren. */
8483 /* This is dependent on the next operand specifier
8484 is a base register specification. */
8485 assert (args[1] == 'b' || args[1] == '5'
8486 || args[1] == '-' || args[1] == '4');
8490 case ')': /* these must match exactly */
8497 case '+': /* Opcode extension character. */
8500 case 'A': /* ins/ext position, becomes LSB. */
8509 my_getExpression (&imm_expr, s);
8510 check_absolute_expr (ip, &imm_expr);
8511 if ((unsigned long) imm_expr.X_add_number < limlo
8512 || (unsigned long) imm_expr.X_add_number > limhi)
8514 as_bad (_("Improper position (%lu)"),
8515 (unsigned long) imm_expr.X_add_number);
8516 imm_expr.X_add_number = limlo;
8518 lastpos = imm_expr.X_add_number;
8519 ip->insn_opcode |= (imm_expr.X_add_number
8520 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8521 imm_expr.X_op = O_absent;
8525 case 'B': /* ins size, becomes MSB. */
8534 my_getExpression (&imm_expr, s);
8535 check_absolute_expr (ip, &imm_expr);
8536 /* Check for negative input so that small negative numbers
8537 will not succeed incorrectly. The checks against
8538 (pos+size) transitively check "size" itself,
8539 assuming that "pos" is reasonable. */
8540 if ((long) imm_expr.X_add_number < 0
8541 || ((unsigned long) imm_expr.X_add_number
8543 || ((unsigned long) imm_expr.X_add_number
8546 as_bad (_("Improper insert size (%lu, position %lu)"),
8547 (unsigned long) imm_expr.X_add_number,
8548 (unsigned long) lastpos);
8549 imm_expr.X_add_number = limlo - lastpos;
8551 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8552 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8553 imm_expr.X_op = O_absent;
8557 case 'C': /* ext size, becomes MSBD. */
8570 my_getExpression (&imm_expr, s);
8571 check_absolute_expr (ip, &imm_expr);
8572 /* Check for negative input so that small negative numbers
8573 will not succeed incorrectly. The checks against
8574 (pos+size) transitively check "size" itself,
8575 assuming that "pos" is reasonable. */
8576 if ((long) imm_expr.X_add_number < 0
8577 || ((unsigned long) imm_expr.X_add_number
8579 || ((unsigned long) imm_expr.X_add_number
8582 as_bad (_("Improper extract size (%lu, position %lu)"),
8583 (unsigned long) imm_expr.X_add_number,
8584 (unsigned long) lastpos);
8585 imm_expr.X_add_number = limlo - lastpos;
8587 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8588 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8589 imm_expr.X_op = O_absent;
8594 /* +D is for disassembly only; never match. */
8598 /* "+I" is like "I", except that imm2_expr is used. */
8599 my_getExpression (&imm2_expr, s);
8600 if (imm2_expr.X_op != O_big
8601 && imm2_expr.X_op != O_constant)
8602 insn_error = _("absolute expression required");
8603 normalize_constant_expr (&imm2_expr);
8608 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8609 *args, insn->name, insn->args);
8610 /* Further processing is fruitless. */
8615 case '<': /* must be at least one digit */
8617 * According to the manual, if the shift amount is greater
8618 * than 31 or less than 0, then the shift amount should be
8619 * mod 32. In reality the mips assembler issues an error.
8620 * We issue a warning and mask out all but the low 5 bits.
8622 my_getExpression (&imm_expr, s);
8623 check_absolute_expr (ip, &imm_expr);
8624 if ((unsigned long) imm_expr.X_add_number > 31)
8626 as_warn (_("Improper shift amount (%lu)"),
8627 (unsigned long) imm_expr.X_add_number);
8628 imm_expr.X_add_number &= OP_MASK_SHAMT;
8630 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8631 imm_expr.X_op = O_absent;
8635 case '>': /* shift amount minus 32 */
8636 my_getExpression (&imm_expr, s);
8637 check_absolute_expr (ip, &imm_expr);
8638 if ((unsigned long) imm_expr.X_add_number < 32
8639 || (unsigned long) imm_expr.X_add_number > 63)
8641 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8642 imm_expr.X_op = O_absent;
8646 case 'k': /* cache code */
8647 case 'h': /* prefx code */
8648 my_getExpression (&imm_expr, s);
8649 check_absolute_expr (ip, &imm_expr);
8650 if ((unsigned long) imm_expr.X_add_number > 31)
8652 as_warn (_("Invalid value for `%s' (%lu)"),
8654 (unsigned long) imm_expr.X_add_number);
8655 imm_expr.X_add_number &= 0x1f;
8658 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8660 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8661 imm_expr.X_op = O_absent;
8665 case 'c': /* break code */
8666 my_getExpression (&imm_expr, s);
8667 check_absolute_expr (ip, &imm_expr);
8668 if ((unsigned long) imm_expr.X_add_number > 1023)
8670 as_warn (_("Illegal break code (%lu)"),
8671 (unsigned long) imm_expr.X_add_number);
8672 imm_expr.X_add_number &= OP_MASK_CODE;
8674 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8675 imm_expr.X_op = O_absent;
8679 case 'q': /* lower break code */
8680 my_getExpression (&imm_expr, s);
8681 check_absolute_expr (ip, &imm_expr);
8682 if ((unsigned long) imm_expr.X_add_number > 1023)
8684 as_warn (_("Illegal lower break code (%lu)"),
8685 (unsigned long) imm_expr.X_add_number);
8686 imm_expr.X_add_number &= OP_MASK_CODE2;
8688 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8689 imm_expr.X_op = O_absent;
8693 case 'B': /* 20-bit syscall/break code. */
8694 my_getExpression (&imm_expr, s);
8695 check_absolute_expr (ip, &imm_expr);
8696 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8697 as_warn (_("Illegal 20-bit code (%lu)"),
8698 (unsigned long) imm_expr.X_add_number);
8699 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8700 imm_expr.X_op = O_absent;
8704 case 'C': /* Coprocessor code */
8705 my_getExpression (&imm_expr, s);
8706 check_absolute_expr (ip, &imm_expr);
8707 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8709 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8710 (unsigned long) imm_expr.X_add_number);
8711 imm_expr.X_add_number &= ((1 << 25) - 1);
8713 ip->insn_opcode |= imm_expr.X_add_number;
8714 imm_expr.X_op = O_absent;
8718 case 'J': /* 19-bit wait code. */
8719 my_getExpression (&imm_expr, s);
8720 check_absolute_expr (ip, &imm_expr);
8721 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8722 as_warn (_("Illegal 19-bit code (%lu)"),
8723 (unsigned long) imm_expr.X_add_number);
8724 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8725 imm_expr.X_op = O_absent;
8729 case 'P': /* Performance register */
8730 my_getExpression (&imm_expr, s);
8731 check_absolute_expr (ip, &imm_expr);
8732 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8734 as_warn (_("Invalid performance register (%lu)"),
8735 (unsigned long) imm_expr.X_add_number);
8736 imm_expr.X_add_number &= OP_MASK_PERFREG;
8738 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8739 imm_expr.X_op = O_absent;
8743 case 'b': /* base register */
8744 case 'd': /* destination register */
8745 case 's': /* source register */
8746 case 't': /* target register */
8747 case 'r': /* both target and source */
8748 case 'v': /* both dest and source */
8749 case 'w': /* both dest and target */
8750 case 'E': /* coprocessor target register */
8751 case 'G': /* coprocessor destination register */
8752 case 'K': /* 'rdhwr' destination register */
8753 case 'x': /* ignore register name */
8754 case 'z': /* must be zero register */
8755 case 'U': /* destination register (clo/clz). */
8770 while (ISDIGIT (*s));
8772 as_bad (_("Invalid register number (%d)"), regno);
8774 else if (*args == 'E' || *args == 'G' || *args == 'K')
8778 if (s[1] == 'r' && s[2] == 'a')
8783 else if (s[1] == 'f' && s[2] == 'p')
8788 else if (s[1] == 's' && s[2] == 'p')
8793 else if (s[1] == 'g' && s[2] == 'p')
8798 else if (s[1] == 'a' && s[2] == 't')
8803 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8808 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8813 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8818 else if (itbl_have_entries)
8823 p = s + 1; /* advance past '$' */
8824 n = itbl_get_field (&p); /* n is name */
8826 /* See if this is a register defined in an
8828 if (itbl_get_reg_val (n, &r))
8830 /* Get_field advances to the start of
8831 the next field, so we need to back
8832 rack to the end of the last field. */
8836 s = strchr (s, '\0');
8850 as_warn (_("Used $at without \".set noat\""));
8856 if (c == 'r' || c == 'v' || c == 'w')
8863 /* 'z' only matches $0. */
8864 if (c == 'z' && regno != 0)
8867 /* Now that we have assembled one operand, we use the args string
8868 * to figure out where it goes in the instruction. */
8875 ip->insn_opcode |= regno << OP_SH_RS;
8880 ip->insn_opcode |= regno << OP_SH_RD;
8883 ip->insn_opcode |= regno << OP_SH_RD;
8884 ip->insn_opcode |= regno << OP_SH_RT;
8889 ip->insn_opcode |= regno << OP_SH_RT;
8892 /* This case exists because on the r3000 trunc
8893 expands into a macro which requires a gp
8894 register. On the r6000 or r4000 it is
8895 assembled into a single instruction which
8896 ignores the register. Thus the insn version
8897 is MIPS_ISA2 and uses 'x', and the macro
8898 version is MIPS_ISA1 and uses 't'. */
8901 /* This case is for the div instruction, which
8902 acts differently if the destination argument
8903 is $0. This only matches $0, and is checked
8904 outside the switch. */
8907 /* Itbl operand; not yet implemented. FIXME ?? */
8909 /* What about all other operands like 'i', which
8910 can be specified in the opcode table? */
8920 ip->insn_opcode |= lastregno << OP_SH_RS;
8923 ip->insn_opcode |= lastregno << OP_SH_RT;
8928 case 'O': /* MDMX alignment immediate constant. */
8929 my_getExpression (&imm_expr, s);
8930 check_absolute_expr (ip, &imm_expr);
8931 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8933 as_warn ("Improper align amount (%ld), using low bits",
8934 (long) imm_expr.X_add_number);
8935 imm_expr.X_add_number &= OP_MASK_ALN;
8937 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8938 imm_expr.X_op = O_absent;
8942 case 'Q': /* MDMX vector, element sel, or const. */
8945 /* MDMX Immediate. */
8946 my_getExpression (&imm_expr, s);
8947 check_absolute_expr (ip, &imm_expr);
8948 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8950 as_warn (_("Invalid MDMX Immediate (%ld)"),
8951 (long) imm_expr.X_add_number);
8952 imm_expr.X_add_number &= OP_MASK_FT;
8954 imm_expr.X_add_number &= OP_MASK_FT;
8955 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8956 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8958 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8959 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8960 imm_expr.X_op = O_absent;
8964 /* Not MDMX Immediate. Fall through. */
8965 case 'X': /* MDMX destination register. */
8966 case 'Y': /* MDMX source register. */
8967 case 'Z': /* MDMX target register. */
8969 case 'D': /* floating point destination register */
8970 case 'S': /* floating point source register */
8971 case 'T': /* floating point target register */
8972 case 'R': /* floating point source register */
8976 /* Accept $fN for FP and MDMX register numbers, and in
8977 addition accept $vN for MDMX register numbers. */
8978 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8979 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8990 while (ISDIGIT (*s));
8993 as_bad (_("Invalid float register number (%d)"), regno);
8995 if ((regno & 1) != 0
8997 && ! (strcmp (str, "mtc1") == 0
8998 || strcmp (str, "mfc1") == 0
8999 || strcmp (str, "lwc1") == 0
9000 || strcmp (str, "swc1") == 0
9001 || strcmp (str, "l.s") == 0
9002 || strcmp (str, "s.s") == 0))
9003 as_warn (_("Float register should be even, was %d"),
9011 if (c == 'V' || c == 'W')
9022 ip->insn_opcode |= regno << OP_SH_FD;
9027 ip->insn_opcode |= regno << OP_SH_FS;
9030 /* This is like 'Z', but also needs to fix the MDMX
9031 vector/scalar select bits. Note that the
9032 scalar immediate case is handled above. */
9035 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9036 int max_el = (is_qh ? 3 : 7);
9038 my_getExpression(&imm_expr, s);
9039 check_absolute_expr (ip, &imm_expr);
9041 if (imm_expr.X_add_number > max_el)
9042 as_bad(_("Bad element selector %ld"),
9043 (long) imm_expr.X_add_number);
9044 imm_expr.X_add_number &= max_el;
9045 ip->insn_opcode |= (imm_expr.X_add_number
9049 as_warn(_("Expecting ']' found '%s'"), s);
9055 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9056 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9059 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9066 ip->insn_opcode |= regno << OP_SH_FT;
9069 ip->insn_opcode |= regno << OP_SH_FR;
9079 ip->insn_opcode |= lastregno << OP_SH_FS;
9082 ip->insn_opcode |= lastregno << OP_SH_FT;
9088 my_getExpression (&imm_expr, s);
9089 if (imm_expr.X_op != O_big
9090 && imm_expr.X_op != O_constant)
9091 insn_error = _("absolute expression required");
9092 normalize_constant_expr (&imm_expr);
9097 my_getExpression (&offset_expr, s);
9098 *imm_reloc = BFD_RELOC_32;
9111 unsigned char temp[8];
9113 unsigned int length;
9118 /* These only appear as the last operand in an
9119 instruction, and every instruction that accepts
9120 them in any variant accepts them in all variants.
9121 This means we don't have to worry about backing out
9122 any changes if the instruction does not match.
9124 The difference between them is the size of the
9125 floating point constant and where it goes. For 'F'
9126 and 'L' the constant is 64 bits; for 'f' and 'l' it
9127 is 32 bits. Where the constant is placed is based
9128 on how the MIPS assembler does things:
9131 f -- immediate value
9134 The .lit4 and .lit8 sections are only used if
9135 permitted by the -G argument.
9137 When generating embedded PIC code, we use the
9138 .lit8 section but not the .lit4 section (we can do
9139 .lit4 inline easily; we need to put .lit8
9140 somewhere in the data segment, and using .lit8
9141 permits the linker to eventually combine identical
9144 The code below needs to know whether the target register
9145 is 32 or 64 bits wide. It relies on the fact 'f' and
9146 'F' are used with GPR-based instructions and 'l' and
9147 'L' are used with FPR-based instructions. */
9149 f64 = *args == 'F' || *args == 'L';
9150 using_gprs = *args == 'F' || *args == 'f';
9152 save_in = input_line_pointer;
9153 input_line_pointer = s;
9154 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9156 s = input_line_pointer;
9157 input_line_pointer = save_in;
9158 if (err != NULL && *err != '\0')
9160 as_bad (_("Bad floating point constant: %s"), err);
9161 memset (temp, '\0', sizeof temp);
9162 length = f64 ? 8 : 4;
9165 assert (length == (unsigned) (f64 ? 8 : 4));
9169 && (! USE_GLOBAL_POINTER_OPT
9170 || mips_pic == EMBEDDED_PIC
9171 || g_switch_value < 4
9172 || (temp[0] == 0 && temp[1] == 0)
9173 || (temp[2] == 0 && temp[3] == 0))))
9175 imm_expr.X_op = O_constant;
9176 if (! target_big_endian)
9177 imm_expr.X_add_number = bfd_getl32 (temp);
9179 imm_expr.X_add_number = bfd_getb32 (temp);
9182 && ! mips_disable_float_construction
9183 /* Constants can only be constructed in GPRs and
9184 copied to FPRs if the GPRs are at least as wide
9185 as the FPRs. Force the constant into memory if
9186 we are using 64-bit FPRs but the GPRs are only
9189 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9190 && ((temp[0] == 0 && temp[1] == 0)
9191 || (temp[2] == 0 && temp[3] == 0))
9192 && ((temp[4] == 0 && temp[5] == 0)
9193 || (temp[6] == 0 && temp[7] == 0)))
9195 /* The value is simple enough to load with a couple of
9196 instructions. If using 32-bit registers, set
9197 imm_expr to the high order 32 bits and offset_expr to
9198 the low order 32 bits. Otherwise, set imm_expr to
9199 the entire 64 bit constant. */
9200 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9202 imm_expr.X_op = O_constant;
9203 offset_expr.X_op = O_constant;
9204 if (! target_big_endian)
9206 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9207 offset_expr.X_add_number = bfd_getl32 (temp);
9211 imm_expr.X_add_number = bfd_getb32 (temp);
9212 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9214 if (offset_expr.X_add_number == 0)
9215 offset_expr.X_op = O_absent;
9217 else if (sizeof (imm_expr.X_add_number) > 4)
9219 imm_expr.X_op = O_constant;
9220 if (! target_big_endian)
9221 imm_expr.X_add_number = bfd_getl64 (temp);
9223 imm_expr.X_add_number = bfd_getb64 (temp);
9227 imm_expr.X_op = O_big;
9228 imm_expr.X_add_number = 4;
9229 if (! target_big_endian)
9231 generic_bignum[0] = bfd_getl16 (temp);
9232 generic_bignum[1] = bfd_getl16 (temp + 2);
9233 generic_bignum[2] = bfd_getl16 (temp + 4);
9234 generic_bignum[3] = bfd_getl16 (temp + 6);
9238 generic_bignum[0] = bfd_getb16 (temp + 6);
9239 generic_bignum[1] = bfd_getb16 (temp + 4);
9240 generic_bignum[2] = bfd_getb16 (temp + 2);
9241 generic_bignum[3] = bfd_getb16 (temp);
9247 const char *newname;
9250 /* Switch to the right section. */
9252 subseg = now_subseg;
9255 default: /* unused default case avoids warnings. */
9257 newname = RDATA_SECTION_NAME;
9258 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9259 || mips_pic == EMBEDDED_PIC)
9263 if (mips_pic == EMBEDDED_PIC)
9266 newname = RDATA_SECTION_NAME;
9269 assert (!USE_GLOBAL_POINTER_OPT
9270 || g_switch_value >= 4);
9274 new_seg = subseg_new (newname, (subsegT) 0);
9275 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9276 bfd_set_section_flags (stdoutput, new_seg,
9281 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9282 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9283 && strcmp (TARGET_OS, "elf") != 0)
9284 record_alignment (new_seg, 4);
9286 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9288 as_bad (_("Can't use floating point insn in this section"));
9290 /* Set the argument to the current address in the
9292 offset_expr.X_op = O_symbol;
9293 offset_expr.X_add_symbol =
9294 symbol_new ("L0\001", now_seg,
9295 (valueT) frag_now_fix (), frag_now);
9296 offset_expr.X_add_number = 0;
9298 /* Put the floating point number into the section. */
9299 p = frag_more ((int) length);
9300 memcpy (p, temp, length);
9302 /* Switch back to the original section. */
9303 subseg_set (seg, subseg);
9308 case 'i': /* 16 bit unsigned immediate */
9309 case 'j': /* 16 bit signed immediate */
9310 *imm_reloc = BFD_RELOC_LO16;
9311 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9314 offsetT minval, maxval;
9316 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9317 && strcmp (insn->name, insn[1].name) == 0);
9319 /* If the expression was written as an unsigned number,
9320 only treat it as signed if there are no more
9324 && sizeof (imm_expr.X_add_number) <= 4
9325 && imm_expr.X_op == O_constant
9326 && imm_expr.X_add_number < 0
9327 && imm_expr.X_unsigned
9331 /* For compatibility with older assemblers, we accept
9332 0x8000-0xffff as signed 16-bit numbers when only
9333 signed numbers are allowed. */
9335 minval = 0, maxval = 0xffff;
9337 minval = -0x8000, maxval = 0x7fff;
9339 minval = -0x8000, maxval = 0xffff;
9341 if (imm_expr.X_op != O_constant
9342 || imm_expr.X_add_number < minval
9343 || imm_expr.X_add_number > maxval)
9347 if (imm_expr.X_op == O_constant
9348 || imm_expr.X_op == O_big)
9349 as_bad (_("expression out of range"));
9355 case 'o': /* 16 bit offset */
9356 /* Check whether there is only a single bracketed expression
9357 left. If so, it must be the base register and the
9358 constant must be zero. */
9359 if (*s == '(' && strchr (s + 1, '(') == 0)
9361 offset_expr.X_op = O_constant;
9362 offset_expr.X_add_number = 0;
9366 /* If this value won't fit into a 16 bit offset, then go
9367 find a macro that will generate the 32 bit offset
9369 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9370 && (offset_expr.X_op != O_constant
9371 || offset_expr.X_add_number >= 0x8000
9372 || offset_expr.X_add_number < -0x8000))
9378 case 'p': /* pc relative offset */
9379 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9380 my_getExpression (&offset_expr, s);
9384 case 'u': /* upper 16 bits */
9385 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9386 && imm_expr.X_op == O_constant
9387 && (imm_expr.X_add_number < 0
9388 || imm_expr.X_add_number >= 0x10000))
9389 as_bad (_("lui expression not in range 0..65535"));
9393 case 'a': /* 26 bit address */
9394 my_getExpression (&offset_expr, s);
9396 *offset_reloc = BFD_RELOC_MIPS_JMP;
9399 case 'N': /* 3 bit branch condition code */
9400 case 'M': /* 3 bit compare condition code */
9401 if (strncmp (s, "$fcc", 4) != 0)
9411 while (ISDIGIT (*s));
9413 as_bad (_("Invalid condition code register $fcc%d"), regno);
9414 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9415 || strcmp(str + strlen(str) - 5, "any2f") == 0
9416 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9417 && (regno & 1) != 0)
9418 as_warn(_("Condition code register should be even for %s, was %d"),
9420 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9421 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9422 && (regno & 3) != 0)
9423 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9426 ip->insn_opcode |= regno << OP_SH_BCC;
9428 ip->insn_opcode |= regno << OP_SH_CCC;
9432 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9443 while (ISDIGIT (*s));
9446 c = 8; /* Invalid sel value. */
9449 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9450 ip->insn_opcode |= c;
9454 /* Must be at least one digit. */
9455 my_getExpression (&imm_expr, s);
9456 check_absolute_expr (ip, &imm_expr);
9458 if ((unsigned long) imm_expr.X_add_number
9459 > (unsigned long) OP_MASK_VECBYTE)
9461 as_bad (_("bad byte vector index (%ld)"),
9462 (long) imm_expr.X_add_number);
9463 imm_expr.X_add_number = 0;
9466 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9467 imm_expr.X_op = O_absent;
9472 my_getExpression (&imm_expr, s);
9473 check_absolute_expr (ip, &imm_expr);
9475 if ((unsigned long) imm_expr.X_add_number
9476 > (unsigned long) OP_MASK_VECALIGN)
9478 as_bad (_("bad byte vector index (%ld)"),
9479 (long) imm_expr.X_add_number);
9480 imm_expr.X_add_number = 0;
9483 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9484 imm_expr.X_op = O_absent;
9489 as_bad (_("bad char = '%c'\n"), *args);
9494 /* Args don't match. */
9495 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9496 !strcmp (insn->name, insn[1].name))
9500 insn_error = _("illegal operands");
9505 insn_error = _("illegal operands");
9510 /* This routine assembles an instruction into its binary format when
9511 assembling for the mips16. As a side effect, it sets one of the
9512 global variables imm_reloc or offset_reloc to the type of
9513 relocation to do if one of the operands is an address expression.
9514 It also sets mips16_small and mips16_ext if the user explicitly
9515 requested a small or extended instruction. */
9518 mips16_ip (char *str, struct mips_cl_insn *ip)
9522 struct mips_opcode *insn;
9525 unsigned int lastregno = 0;
9530 mips16_small = FALSE;
9533 for (s = str; ISLOWER (*s); ++s)
9545 if (s[1] == 't' && s[2] == ' ')
9548 mips16_small = TRUE;
9552 else if (s[1] == 'e' && s[2] == ' ')
9561 insn_error = _("unknown opcode");
9565 if (mips_opts.noautoextend && ! mips16_ext)
9566 mips16_small = TRUE;
9568 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9570 insn_error = _("unrecognized opcode");
9577 assert (strcmp (insn->name, str) == 0);
9580 ip->insn_opcode = insn->match;
9581 ip->use_extend = FALSE;
9582 imm_expr.X_op = O_absent;
9583 imm_reloc[0] = BFD_RELOC_UNUSED;
9584 imm_reloc[1] = BFD_RELOC_UNUSED;
9585 imm_reloc[2] = BFD_RELOC_UNUSED;
9586 imm2_expr.X_op = O_absent;
9587 offset_expr.X_op = O_absent;
9588 offset_reloc[0] = BFD_RELOC_UNUSED;
9589 offset_reloc[1] = BFD_RELOC_UNUSED;
9590 offset_reloc[2] = BFD_RELOC_UNUSED;
9591 for (args = insn->args; 1; ++args)
9598 /* In this switch statement we call break if we did not find
9599 a match, continue if we did find a match, or return if we
9608 /* Stuff the immediate value in now, if we can. */
9609 if (imm_expr.X_op == O_constant
9610 && *imm_reloc > BFD_RELOC_UNUSED
9611 && insn->pinfo != INSN_MACRO)
9613 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9614 imm_expr.X_add_number, TRUE, mips16_small,
9615 mips16_ext, &ip->insn_opcode,
9616 &ip->use_extend, &ip->extend);
9617 imm_expr.X_op = O_absent;
9618 *imm_reloc = BFD_RELOC_UNUSED;
9632 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9635 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9651 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9653 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9680 while (ISDIGIT (*s));
9683 as_bad (_("invalid register number (%d)"), regno);
9689 if (s[1] == 'r' && s[2] == 'a')
9694 else if (s[1] == 'f' && s[2] == 'p')
9699 else if (s[1] == 's' && s[2] == 'p')
9704 else if (s[1] == 'g' && s[2] == 'p')
9709 else if (s[1] == 'a' && s[2] == 't')
9714 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9719 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9724 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9737 if (c == 'v' || c == 'w')
9739 regno = mips16_to_32_reg_map[lastregno];
9753 regno = mips32_to_16_reg_map[regno];
9758 regno = ILLEGAL_REG;
9763 regno = ILLEGAL_REG;
9768 regno = ILLEGAL_REG;
9773 if (regno == AT && ! mips_opts.noat)
9774 as_warn (_("used $at without \".set noat\""));
9781 if (regno == ILLEGAL_REG)
9788 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9792 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9795 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9798 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9804 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9807 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9808 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9818 if (strncmp (s, "$pc", 3) == 0)
9842 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9844 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9845 and generate the appropriate reloc. If the text
9846 inside %gprel is not a symbol name with an
9847 optional offset, then we generate a normal reloc
9848 and will probably fail later. */
9849 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9850 if (imm_expr.X_op == O_symbol)
9853 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9855 ip->use_extend = TRUE;
9862 /* Just pick up a normal expression. */
9863 my_getExpression (&imm_expr, s);
9866 if (imm_expr.X_op == O_register)
9868 /* What we thought was an expression turned out to
9871 if (s[0] == '(' && args[1] == '(')
9873 /* It looks like the expression was omitted
9874 before a register indirection, which means
9875 that the expression is implicitly zero. We
9876 still set up imm_expr, so that we handle
9877 explicit extensions correctly. */
9878 imm_expr.X_op = O_constant;
9879 imm_expr.X_add_number = 0;
9880 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9887 /* We need to relax this instruction. */
9888 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9897 /* We use offset_reloc rather than imm_reloc for the PC
9898 relative operands. This lets macros with both
9899 immediate and address operands work correctly. */
9900 my_getExpression (&offset_expr, s);
9902 if (offset_expr.X_op == O_register)
9905 /* We need to relax this instruction. */
9906 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9910 case '6': /* break code */
9911 my_getExpression (&imm_expr, s);
9912 check_absolute_expr (ip, &imm_expr);
9913 if ((unsigned long) imm_expr.X_add_number > 63)
9915 as_warn (_("Invalid value for `%s' (%lu)"),
9917 (unsigned long) imm_expr.X_add_number);
9918 imm_expr.X_add_number &= 0x3f;
9920 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9921 imm_expr.X_op = O_absent;
9925 case 'a': /* 26 bit address */
9926 my_getExpression (&offset_expr, s);
9928 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9929 ip->insn_opcode <<= 16;
9932 case 'l': /* register list for entry macro */
9933 case 'L': /* register list for exit macro */
9943 int freg, reg1, reg2;
9945 while (*s == ' ' || *s == ',')
9949 as_bad (_("can't parse register list"));
9961 while (ISDIGIT (*s))
9983 as_bad (_("invalid register list"));
9988 while (ISDIGIT (*s))
9995 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10000 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10002 mask &= ~ (7 << 3);
10005 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10006 mask |= (reg2 - 3) << 3;
10007 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10008 mask |= (reg2 - 15) << 1;
10009 else if (reg1 == RA && reg2 == RA)
10013 as_bad (_("invalid register list"));
10017 /* The mask is filled in in the opcode table for the
10018 benefit of the disassembler. We remove it before
10019 applying the actual mask. */
10020 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10021 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10025 case 'e': /* extend code */
10026 my_getExpression (&imm_expr, s);
10027 check_absolute_expr (ip, &imm_expr);
10028 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10030 as_warn (_("Invalid value for `%s' (%lu)"),
10032 (unsigned long) imm_expr.X_add_number);
10033 imm_expr.X_add_number &= 0x7ff;
10035 ip->insn_opcode |= imm_expr.X_add_number;
10036 imm_expr.X_op = O_absent;
10046 /* Args don't match. */
10047 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10048 strcmp (insn->name, insn[1].name) == 0)
10055 insn_error = _("illegal operands");
10061 /* This structure holds information we know about a mips16 immediate
10064 struct mips16_immed_operand
10066 /* The type code used in the argument string in the opcode table. */
10068 /* The number of bits in the short form of the opcode. */
10070 /* The number of bits in the extended form of the opcode. */
10072 /* The amount by which the short form is shifted when it is used;
10073 for example, the sw instruction has a shift count of 2. */
10075 /* The amount by which the short form is shifted when it is stored
10076 into the instruction code. */
10078 /* Non-zero if the short form is unsigned. */
10080 /* Non-zero if the extended form is unsigned. */
10082 /* Non-zero if the value is PC relative. */
10086 /* The mips16 immediate operand types. */
10088 static const struct mips16_immed_operand mips16_immed_operands[] =
10090 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10091 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10092 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10093 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10094 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10095 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10096 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10097 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10098 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10099 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10100 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10101 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10102 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10103 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10104 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10105 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10106 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10107 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10108 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10109 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10110 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10113 #define MIPS16_NUM_IMMED \
10114 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10116 /* Handle a mips16 instruction with an immediate value. This or's the
10117 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10118 whether an extended value is needed; if one is needed, it sets
10119 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10120 If SMALL is true, an unextended opcode was explicitly requested.
10121 If EXT is true, an extended opcode was explicitly requested. If
10122 WARN is true, warn if EXT does not match reality. */
10125 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10126 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10127 unsigned long *insn, bfd_boolean *use_extend,
10128 unsigned short *extend)
10130 register const struct mips16_immed_operand *op;
10131 int mintiny, maxtiny;
10132 bfd_boolean needext;
10134 op = mips16_immed_operands;
10135 while (op->type != type)
10138 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10143 if (type == '<' || type == '>' || type == '[' || type == ']')
10146 maxtiny = 1 << op->nbits;
10151 maxtiny = (1 << op->nbits) - 1;
10156 mintiny = - (1 << (op->nbits - 1));
10157 maxtiny = (1 << (op->nbits - 1)) - 1;
10160 /* Branch offsets have an implicit 0 in the lowest bit. */
10161 if (type == 'p' || type == 'q')
10164 if ((val & ((1 << op->shift) - 1)) != 0
10165 || val < (mintiny << op->shift)
10166 || val > (maxtiny << op->shift))
10171 if (warn && ext && ! needext)
10172 as_warn_where (file, line,
10173 _("extended operand requested but not required"));
10174 if (small && needext)
10175 as_bad_where (file, line, _("invalid unextended operand value"));
10177 if (small || (! ext && ! needext))
10181 *use_extend = FALSE;
10182 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10183 insnval <<= op->op_shift;
10188 long minext, maxext;
10194 maxext = (1 << op->extbits) - 1;
10198 minext = - (1 << (op->extbits - 1));
10199 maxext = (1 << (op->extbits - 1)) - 1;
10201 if (val < minext || val > maxext)
10202 as_bad_where (file, line,
10203 _("operand value out of range for instruction"));
10205 *use_extend = TRUE;
10206 if (op->extbits == 16)
10208 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10211 else if (op->extbits == 15)
10213 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10218 extval = ((val & 0x1f) << 6) | (val & 0x20);
10222 *extend = (unsigned short) extval;
10227 static const struct percent_op_match
10230 bfd_reloc_code_real_type reloc;
10233 {"%lo", BFD_RELOC_LO16},
10235 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10236 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10237 {"%call16", BFD_RELOC_MIPS_CALL16},
10238 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10239 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10240 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10241 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10242 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10243 {"%got", BFD_RELOC_MIPS_GOT16},
10244 {"%gp_rel", BFD_RELOC_GPREL16},
10245 {"%half", BFD_RELOC_16},
10246 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10247 {"%higher", BFD_RELOC_MIPS_HIGHER},
10248 {"%neg", BFD_RELOC_MIPS_SUB},
10250 {"%hi", BFD_RELOC_HI16_S}
10254 /* Return true if *STR points to a relocation operator. When returning true,
10255 move *STR over the operator and store its relocation code in *RELOC.
10256 Leave both *STR and *RELOC alone when returning false. */
10259 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10263 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10264 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10266 *str += strlen (percent_op[i].str);
10267 *reloc = percent_op[i].reloc;
10269 /* Check whether the output BFD supports this relocation.
10270 If not, issue an error and fall back on something safe. */
10271 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10273 as_bad ("relocation %s isn't supported by the current ABI",
10274 percent_op[i].str);
10275 *reloc = BFD_RELOC_LO16;
10283 /* Parse string STR as a 16-bit relocatable operand. Store the
10284 expression in *EP and the relocations in the array starting
10285 at RELOC. Return the number of relocation operators used.
10287 On exit, EXPR_END points to the first character after the expression.
10288 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10291 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10294 bfd_reloc_code_real_type reversed_reloc[3];
10295 size_t reloc_index, i;
10296 int crux_depth, str_depth;
10299 /* Search for the start of the main expression, recoding relocations
10300 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10301 of the main expression and with CRUX_DEPTH containing the number
10302 of open brackets at that point. */
10309 crux_depth = str_depth;
10311 /* Skip over whitespace and brackets, keeping count of the number
10313 while (*str == ' ' || *str == '\t' || *str == '(')
10318 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10319 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10321 my_getExpression (ep, crux);
10324 /* Match every open bracket. */
10325 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10329 if (crux_depth > 0)
10330 as_bad ("unclosed '('");
10334 if (reloc_index == 0)
10335 reloc[0] = BFD_RELOC_LO16;
10338 prev_reloc_op_frag = frag_now;
10339 for (i = 0; i < reloc_index; i++)
10340 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10343 return reloc_index;
10347 my_getExpression (expressionS *ep, char *str)
10352 save_in = input_line_pointer;
10353 input_line_pointer = str;
10355 expr_end = input_line_pointer;
10356 input_line_pointer = save_in;
10358 /* If we are in mips16 mode, and this is an expression based on `.',
10359 then we bump the value of the symbol by 1 since that is how other
10360 text symbols are handled. We don't bother to handle complex
10361 expressions, just `.' plus or minus a constant. */
10362 if (mips_opts.mips16
10363 && ep->X_op == O_symbol
10364 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10365 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10366 && symbol_get_frag (ep->X_add_symbol) == frag_now
10367 && symbol_constant_p (ep->X_add_symbol)
10368 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10369 S_SET_VALUE (ep->X_add_symbol, val + 1);
10372 /* Turn a string in input_line_pointer into a floating point constant
10373 of type TYPE, and store the appropriate bytes in *LITP. The number
10374 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10375 returned, or NULL on OK. */
10378 md_atof (int type, char *litP, int *sizeP)
10381 LITTLENUM_TYPE words[4];
10397 return _("bad call to md_atof");
10400 t = atof_ieee (input_line_pointer, type, words);
10402 input_line_pointer = t;
10406 if (! target_big_endian)
10408 for (i = prec - 1; i >= 0; i--)
10410 md_number_to_chars (litP, words[i], 2);
10416 for (i = 0; i < prec; i++)
10418 md_number_to_chars (litP, words[i], 2);
10427 md_number_to_chars (char *buf, valueT val, int n)
10429 if (target_big_endian)
10430 number_to_chars_bigendian (buf, val, n);
10432 number_to_chars_littleendian (buf, val, n);
10436 static int support_64bit_objects(void)
10438 const char **list, **l;
10441 list = bfd_target_list ();
10442 for (l = list; *l != NULL; l++)
10444 /* This is traditional mips */
10445 if (strcmp (*l, "elf64-tradbigmips") == 0
10446 || strcmp (*l, "elf64-tradlittlemips") == 0)
10448 if (strcmp (*l, "elf64-bigmips") == 0
10449 || strcmp (*l, "elf64-littlemips") == 0)
10452 yes = (*l != NULL);
10456 #endif /* OBJ_ELF */
10458 const char *md_shortopts = "O::g::G:";
10460 struct option md_longopts[] =
10462 /* Options which specify architecture. */
10463 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10464 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10465 {"march", required_argument, NULL, OPTION_MARCH},
10466 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10467 {"mtune", required_argument, NULL, OPTION_MTUNE},
10468 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10469 {"mips0", no_argument, NULL, OPTION_MIPS1},
10470 {"mips1", no_argument, NULL, OPTION_MIPS1},
10471 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10472 {"mips2", no_argument, NULL, OPTION_MIPS2},
10473 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10474 {"mips3", no_argument, NULL, OPTION_MIPS3},
10475 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10476 {"mips4", no_argument, NULL, OPTION_MIPS4},
10477 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10478 {"mips5", no_argument, NULL, OPTION_MIPS5},
10479 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10480 {"mips32", no_argument, NULL, OPTION_MIPS32},
10481 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10482 {"mips64", no_argument, NULL, OPTION_MIPS64},
10483 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10484 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10485 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10486 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10488 /* Options which specify Application Specific Extensions (ASEs). */
10489 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10490 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10491 {"mips16", no_argument, NULL, OPTION_MIPS16},
10492 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10493 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10494 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10495 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10496 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10497 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10498 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10499 {"mdmx", no_argument, NULL, OPTION_MDMX},
10500 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10501 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10503 /* Old-style architecture options. Don't add more of these. */
10504 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10505 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10506 {"m4650", no_argument, NULL, OPTION_M4650},
10507 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10508 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10509 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10510 {"m4010", no_argument, NULL, OPTION_M4010},
10511 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10512 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10513 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10514 {"m4100", no_argument, NULL, OPTION_M4100},
10515 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10516 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10517 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10518 {"m3900", no_argument, NULL, OPTION_M3900},
10519 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10520 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10522 /* Options which enable bug fixes. */
10523 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10524 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10525 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10526 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10527 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10528 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10529 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10530 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10531 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10532 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10534 /* Miscellaneous options. */
10535 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10536 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10537 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10538 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10539 {"trap", no_argument, NULL, OPTION_TRAP},
10540 {"no-break", no_argument, NULL, OPTION_TRAP},
10541 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10542 {"break", no_argument, NULL, OPTION_BREAK},
10543 {"no-trap", no_argument, NULL, OPTION_BREAK},
10544 #define OPTION_EB (OPTION_MISC_BASE + 3)
10545 {"EB", no_argument, NULL, OPTION_EB},
10546 #define OPTION_EL (OPTION_MISC_BASE + 4)
10547 {"EL", no_argument, NULL, OPTION_EL},
10548 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10549 {"mfp32", no_argument, NULL, OPTION_FP32},
10550 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10551 {"mgp32", no_argument, NULL, OPTION_GP32},
10552 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10553 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10554 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10555 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10556 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10557 {"mfp64", no_argument, NULL, OPTION_FP64},
10558 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10559 {"mgp64", no_argument, NULL, OPTION_GP64},
10560 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10561 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10562 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10563 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10565 /* ELF-specific options. */
10567 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10568 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10569 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10570 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10571 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10572 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10573 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10574 {"xgot", no_argument, NULL, OPTION_XGOT},
10575 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10576 {"mabi", required_argument, NULL, OPTION_MABI},
10577 #define OPTION_32 (OPTION_ELF_BASE + 4)
10578 {"32", no_argument, NULL, OPTION_32},
10579 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10580 {"n32", no_argument, NULL, OPTION_N32},
10581 #define OPTION_64 (OPTION_ELF_BASE + 6)
10582 {"64", no_argument, NULL, OPTION_64},
10583 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10584 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10585 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10586 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10587 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10588 {"mpdr", no_argument, NULL, OPTION_PDR},
10589 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10590 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10591 #endif /* OBJ_ELF */
10593 {NULL, no_argument, NULL, 0}
10595 size_t md_longopts_size = sizeof (md_longopts);
10597 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10598 NEW_VALUE. Warn if another value was already specified. Note:
10599 we have to defer parsing the -march and -mtune arguments in order
10600 to handle 'from-abi' correctly, since the ABI might be specified
10601 in a later argument. */
10604 mips_set_option_string (const char **string_ptr, const char *new_value)
10606 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10607 as_warn (_("A different %s was already specified, is now %s"),
10608 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10611 *string_ptr = new_value;
10615 md_parse_option (int c, char *arg)
10619 case OPTION_CONSTRUCT_FLOATS:
10620 mips_disable_float_construction = 0;
10623 case OPTION_NO_CONSTRUCT_FLOATS:
10624 mips_disable_float_construction = 1;
10636 target_big_endian = 1;
10640 target_big_endian = 0;
10644 if (arg && arg[1] == '0')
10654 mips_debug = atoi (arg);
10655 /* When the MIPS assembler sees -g or -g2, it does not do
10656 optimizations which limit full symbolic debugging. We take
10657 that to be equivalent to -O0. */
10658 if (mips_debug == 2)
10663 file_mips_isa = ISA_MIPS1;
10667 file_mips_isa = ISA_MIPS2;
10671 file_mips_isa = ISA_MIPS3;
10675 file_mips_isa = ISA_MIPS4;
10679 file_mips_isa = ISA_MIPS5;
10682 case OPTION_MIPS32:
10683 file_mips_isa = ISA_MIPS32;
10686 case OPTION_MIPS32R2:
10687 file_mips_isa = ISA_MIPS32R2;
10690 case OPTION_MIPS64R2:
10691 file_mips_isa = ISA_MIPS64R2;
10694 case OPTION_MIPS64:
10695 file_mips_isa = ISA_MIPS64;
10699 mips_set_option_string (&mips_tune_string, arg);
10703 mips_set_option_string (&mips_arch_string, arg);
10707 mips_set_option_string (&mips_arch_string, "4650");
10708 mips_set_option_string (&mips_tune_string, "4650");
10711 case OPTION_NO_M4650:
10715 mips_set_option_string (&mips_arch_string, "4010");
10716 mips_set_option_string (&mips_tune_string, "4010");
10719 case OPTION_NO_M4010:
10723 mips_set_option_string (&mips_arch_string, "4100");
10724 mips_set_option_string (&mips_tune_string, "4100");
10727 case OPTION_NO_M4100:
10731 mips_set_option_string (&mips_arch_string, "3900");
10732 mips_set_option_string (&mips_tune_string, "3900");
10735 case OPTION_NO_M3900:
10739 mips_opts.ase_mdmx = 1;
10742 case OPTION_NO_MDMX:
10743 mips_opts.ase_mdmx = 0;
10746 case OPTION_MIPS16:
10747 mips_opts.mips16 = 1;
10748 mips_no_prev_insn (FALSE);
10751 case OPTION_NO_MIPS16:
10752 mips_opts.mips16 = 0;
10753 mips_no_prev_insn (FALSE);
10756 case OPTION_MIPS3D:
10757 mips_opts.ase_mips3d = 1;
10760 case OPTION_NO_MIPS3D:
10761 mips_opts.ase_mips3d = 0;
10764 case OPTION_MEMBEDDED_PIC:
10765 mips_pic = EMBEDDED_PIC;
10766 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10768 as_bad (_("-G may not be used with embedded PIC code"));
10771 g_switch_value = 0x7fffffff;
10774 case OPTION_FIX_VR4122:
10775 mips_fix_4122_bugs = 1;
10778 case OPTION_NO_FIX_VR4122:
10779 mips_fix_4122_bugs = 0;
10782 case OPTION_RELAX_BRANCH:
10783 mips_relax_branch = 1;
10786 case OPTION_NO_RELAX_BRANCH:
10787 mips_relax_branch = 0;
10791 /* When generating ELF code, we permit -KPIC and -call_shared to
10792 select SVR4_PIC, and -non_shared to select no PIC. This is
10793 intended to be compatible with Irix 5. */
10794 case OPTION_CALL_SHARED:
10795 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10797 as_bad (_("-call_shared is supported only for ELF format"));
10800 mips_pic = SVR4_PIC;
10801 mips_abicalls = TRUE;
10802 if (g_switch_seen && g_switch_value != 0)
10804 as_bad (_("-G may not be used with SVR4 PIC code"));
10807 g_switch_value = 0;
10810 case OPTION_NON_SHARED:
10811 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10813 as_bad (_("-non_shared is supported only for ELF format"));
10817 mips_abicalls = FALSE;
10820 /* The -xgot option tells the assembler to use 32 offsets when
10821 accessing the got in SVR4_PIC mode. It is for Irix
10826 #endif /* OBJ_ELF */
10829 if (! USE_GLOBAL_POINTER_OPT)
10831 as_bad (_("-G is not supported for this configuration"));
10834 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10836 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10840 g_switch_value = atoi (arg);
10845 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10848 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10850 as_bad (_("-32 is supported for ELF format only"));
10853 mips_abi = O32_ABI;
10857 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10859 as_bad (_("-n32 is supported for ELF format only"));
10862 mips_abi = N32_ABI;
10866 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10868 as_bad (_("-64 is supported for ELF format only"));
10871 mips_abi = N64_ABI;
10872 if (! support_64bit_objects())
10873 as_fatal (_("No compiled in support for 64 bit object file format"));
10875 #endif /* OBJ_ELF */
10878 file_mips_gp32 = 1;
10882 file_mips_gp32 = 0;
10886 file_mips_fp32 = 1;
10890 file_mips_fp32 = 0;
10895 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10897 as_bad (_("-mabi is supported for ELF format only"));
10900 if (strcmp (arg, "32") == 0)
10901 mips_abi = O32_ABI;
10902 else if (strcmp (arg, "o64") == 0)
10903 mips_abi = O64_ABI;
10904 else if (strcmp (arg, "n32") == 0)
10905 mips_abi = N32_ABI;
10906 else if (strcmp (arg, "64") == 0)
10908 mips_abi = N64_ABI;
10909 if (! support_64bit_objects())
10910 as_fatal (_("No compiled in support for 64 bit object file "
10913 else if (strcmp (arg, "eabi") == 0)
10914 mips_abi = EABI_ABI;
10917 as_fatal (_("invalid abi -mabi=%s"), arg);
10921 #endif /* OBJ_ELF */
10923 case OPTION_M7000_HILO_FIX:
10924 mips_7000_hilo_fix = TRUE;
10927 case OPTION_MNO_7000_HILO_FIX:
10928 mips_7000_hilo_fix = FALSE;
10932 case OPTION_MDEBUG:
10933 mips_flag_mdebug = TRUE;
10936 case OPTION_NO_MDEBUG:
10937 mips_flag_mdebug = FALSE;
10941 mips_flag_pdr = TRUE;
10944 case OPTION_NO_PDR:
10945 mips_flag_pdr = FALSE;
10947 #endif /* OBJ_ELF */
10956 /* Set up globals to generate code for the ISA or processor
10957 described by INFO. */
10960 mips_set_architecture (const struct mips_cpu_info *info)
10964 file_mips_arch = info->cpu;
10965 mips_opts.arch = info->cpu;
10966 mips_opts.isa = info->isa;
10971 /* Likewise for tuning. */
10974 mips_set_tune (const struct mips_cpu_info *info)
10977 mips_tune = info->cpu;
10982 mips_after_parse_args (void)
10984 const struct mips_cpu_info *arch_info = 0;
10985 const struct mips_cpu_info *tune_info = 0;
10987 /* GP relative stuff not working for PE */
10988 if (strncmp (TARGET_OS, "pe", 2) == 0
10989 && g_switch_value != 0)
10992 as_bad (_("-G not supported in this configuration."));
10993 g_switch_value = 0;
10996 if (mips_abi == NO_ABI)
10997 mips_abi = MIPS_DEFAULT_ABI;
10999 /* The following code determines the architecture and register size.
11000 Similar code was added to GCC 3.3 (see override_options() in
11001 config/mips/mips.c). The GAS and GCC code should be kept in sync
11002 as much as possible. */
11004 if (mips_arch_string != 0)
11005 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11007 if (file_mips_isa != ISA_UNKNOWN)
11009 /* Handle -mipsN. At this point, file_mips_isa contains the
11010 ISA level specified by -mipsN, while arch_info->isa contains
11011 the -march selection (if any). */
11012 if (arch_info != 0)
11014 /* -march takes precedence over -mipsN, since it is more descriptive.
11015 There's no harm in specifying both as long as the ISA levels
11017 if (file_mips_isa != arch_info->isa)
11018 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11019 mips_cpu_info_from_isa (file_mips_isa)->name,
11020 mips_cpu_info_from_isa (arch_info->isa)->name);
11023 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11026 if (arch_info == 0)
11027 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11029 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11030 as_bad ("-march=%s is not compatible with the selected ABI",
11033 mips_set_architecture (arch_info);
11035 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11036 if (mips_tune_string != 0)
11037 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11039 if (tune_info == 0)
11040 mips_set_tune (arch_info);
11042 mips_set_tune (tune_info);
11044 if (file_mips_gp32 >= 0)
11046 /* The user specified the size of the integer registers. Make sure
11047 it agrees with the ABI and ISA. */
11048 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11049 as_bad (_("-mgp64 used with a 32-bit processor"));
11050 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11051 as_bad (_("-mgp32 used with a 64-bit ABI"));
11052 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11053 as_bad (_("-mgp64 used with a 32-bit ABI"));
11057 /* Infer the integer register size from the ABI and processor.
11058 Restrict ourselves to 32-bit registers if that's all the
11059 processor has, or if the ABI cannot handle 64-bit registers. */
11060 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11061 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11064 /* ??? GAS treats single-float processors as though they had 64-bit
11065 float registers (although it complains when double-precision
11066 instructions are used). As things stand, saying they have 32-bit
11067 registers would lead to spurious "register must be even" messages.
11068 So here we assume float registers are always the same size as
11069 integer ones, unless the user says otherwise. */
11070 if (file_mips_fp32 < 0)
11071 file_mips_fp32 = file_mips_gp32;
11073 /* End of GCC-shared inference code. */
11075 /* This flag is set when we have a 64-bit capable CPU but use only
11076 32-bit wide registers. Note that EABI does not use it. */
11077 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11078 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11079 || mips_abi == O32_ABI))
11080 mips_32bitmode = 1;
11082 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11083 as_bad (_("trap exception not supported at ISA 1"));
11085 /* If the selected architecture includes support for ASEs, enable
11086 generation of code for them. */
11087 if (mips_opts.mips16 == -1)
11088 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11089 if (mips_opts.ase_mips3d == -1)
11090 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11091 if (mips_opts.ase_mdmx == -1)
11092 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11094 file_mips_isa = mips_opts.isa;
11095 file_ase_mips16 = mips_opts.mips16;
11096 file_ase_mips3d = mips_opts.ase_mips3d;
11097 file_ase_mdmx = mips_opts.ase_mdmx;
11098 mips_opts.gp32 = file_mips_gp32;
11099 mips_opts.fp32 = file_mips_fp32;
11101 if (mips_flag_mdebug < 0)
11103 #ifdef OBJ_MAYBE_ECOFF
11104 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11105 mips_flag_mdebug = 1;
11107 #endif /* OBJ_MAYBE_ECOFF */
11108 mips_flag_mdebug = 0;
11113 mips_init_after_args (void)
11115 /* initialize opcodes */
11116 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11117 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11121 md_pcrel_from (fixS *fixP)
11123 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11124 switch (fixP->fx_r_type)
11126 case BFD_RELOC_16_PCREL_S2:
11127 case BFD_RELOC_MIPS_JMP:
11128 /* Return the address of the delay slot. */
11135 /* This is called before the symbol table is processed. In order to
11136 work with gcc when using mips-tfile, we must keep all local labels.
11137 However, in other cases, we want to discard them. If we were
11138 called with -g, but we didn't see any debugging information, it may
11139 mean that gcc is smuggling debugging information through to
11140 mips-tfile, in which case we must generate all local labels. */
11143 mips_frob_file_before_adjust (void)
11145 #ifndef NO_ECOFF_DEBUGGING
11146 if (ECOFF_DEBUGGING
11148 && ! ecoff_debugging_seen)
11149 flag_keep_locals = 1;
11153 /* Sort any unmatched HI16_S relocs so that they immediately precede
11154 the corresponding LO reloc. This is called before md_apply_fix3 and
11155 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11156 explicit use of the %hi modifier. */
11159 mips_frob_file (void)
11161 struct mips_hi_fixup *l;
11163 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11165 segment_info_type *seginfo;
11168 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11170 /* If a GOT16 relocation turns out to be against a global symbol,
11171 there isn't supposed to be a matching LO. */
11172 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11173 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11176 /* Check quickly whether the next fixup happens to be a matching %lo. */
11177 if (fixup_has_matching_lo_p (l->fixp))
11180 /* Look through the fixups for this segment for a matching %lo.
11181 When we find one, move the %hi just in front of it. We do
11182 this in two passes. In the first pass, we try to find a
11183 unique %lo. In the second pass, we permit multiple %hi
11184 relocs for a single %lo (this is a GNU extension). */
11185 seginfo = seg_info (l->seg);
11186 for (pass = 0; pass < 2; pass++)
11191 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
11193 /* Check whether this is a %lo fixup which matches l->fixp. */
11194 if (f->fx_r_type == BFD_RELOC_LO16
11195 && f->fx_addsy == l->fixp->fx_addsy
11196 && f->fx_offset == l->fixp->fx_offset
11199 || !reloc_needs_lo_p (prev->fx_r_type)
11200 || !fixup_has_matching_lo_p (prev)))
11204 /* Move l->fixp before f. */
11205 for (pf = &seginfo->fix_root;
11207 pf = &(*pf)->fx_next)
11208 assert (*pf != NULL);
11210 *pf = l->fixp->fx_next;
11212 l->fixp->fx_next = f;
11214 seginfo->fix_root = l->fixp;
11216 prev->fx_next = l->fixp;
11227 #if 0 /* GCC code motion plus incomplete dead code elimination
11228 can leave a %hi without a %lo. */
11230 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11231 _("Unmatched %%hi reloc"));
11237 /* When generating embedded PIC code we need to use a special
11238 relocation to represent the difference of two symbols in the .text
11239 section (switch tables use a difference of this sort). See
11240 include/coff/mips.h for details. This macro checks whether this
11241 fixup requires the special reloc. */
11242 #define SWITCH_TABLE(fixp) \
11243 ((fixp)->fx_r_type == BFD_RELOC_32 \
11244 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11245 && (fixp)->fx_addsy != NULL \
11246 && (fixp)->fx_subsy != NULL \
11247 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11248 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11250 /* When generating embedded PIC code we must keep all PC relative
11251 relocations, in case the linker has to relax a call. We also need
11252 to keep relocations for switch table entries.
11254 We may have combined relocations without symbols in the N32/N64 ABI.
11255 We have to prevent gas from dropping them. */
11258 mips_force_relocation (fixS *fixp)
11260 if (generic_force_reloc (fixp))
11264 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11265 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11266 || fixp->fx_r_type == BFD_RELOC_HI16_S
11267 || fixp->fx_r_type == BFD_RELOC_LO16))
11270 return (mips_pic == EMBEDDED_PIC
11272 || SWITCH_TABLE (fixp)
11273 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11274 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11277 /* This hook is called before a fix is simplified. We don't really
11278 decide whether to skip a fix here. Rather, we turn global symbols
11279 used as branch targets into local symbols, such that they undergo
11280 simplification. We can only do this if the symbol is defined and
11281 it is in the same section as the branch. If this doesn't hold, we
11282 emit a better error message than just saying the relocation is not
11283 valid for the selected object format.
11285 FIXP is the fix-up we're going to try to simplify, SEG is the
11286 segment in which the fix up occurs. The return value should be
11287 non-zero to indicate the fix-up is valid for further
11288 simplifications. */
11291 mips_validate_fix (struct fix *fixP, asection *seg)
11293 /* There's a lot of discussion on whether it should be possible to
11294 use R_MIPS_PC16 to represent branch relocations. The outcome
11295 seems to be that it can, but gas/bfd are very broken in creating
11296 RELA relocations for this, so for now we only accept branches to
11297 symbols in the same section. Anything else is of dubious value,
11298 since there's no guarantee that at link time the symbol would be
11299 in range. Even for branches to local symbols this is arguably
11300 wrong, since it we assume the symbol is not going to be
11301 overridden, which should be possible per ELF library semantics,
11302 but then, there isn't a dynamic relocation that could be used to
11303 this effect, and the target would likely be out of range as well.
11305 Unfortunately, it seems that there is too much code out there
11306 that relies on branches to symbols that are global to be resolved
11307 as if they were local, like the IRIX tools do, so we do it as
11308 well, but with a warning so that people are reminded to fix their
11309 code. If we ever get back to using R_MIPS_PC16 for branch
11310 targets, this entire block should go away (and probably the
11311 whole function). */
11313 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11314 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11315 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11316 && mips_pic != EMBEDDED_PIC)
11317 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11320 if (! S_IS_DEFINED (fixP->fx_addsy))
11322 as_bad_where (fixP->fx_file, fixP->fx_line,
11323 _("Cannot branch to undefined symbol."));
11324 /* Avoid any further errors about this fixup. */
11327 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11329 as_bad_where (fixP->fx_file, fixP->fx_line,
11330 _("Cannot branch to symbol in another section."));
11333 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11335 symbolS *sym = fixP->fx_addsy;
11337 if (mips_pic == SVR4_PIC)
11338 as_warn_where (fixP->fx_file, fixP->fx_line,
11339 _("Pretending global symbol used as branch target is local."));
11341 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11342 S_GET_SEGMENT (sym),
11344 symbol_get_frag (sym));
11345 copy_symbol_attributes (fixP->fx_addsy, sym);
11346 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11347 assert (symbol_resolved_p (sym));
11348 symbol_mark_resolved (fixP->fx_addsy);
11355 /* Apply a fixup to the object file. */
11358 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11362 static int previous_fx_r_type = 0;
11363 reloc_howto_type *howto;
11365 /* We ignore generic BFD relocations we don't know about. */
11366 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11370 assert (fixP->fx_size == 4
11371 || fixP->fx_r_type == BFD_RELOC_16
11372 || fixP->fx_r_type == BFD_RELOC_64
11373 || fixP->fx_r_type == BFD_RELOC_CTOR
11374 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11375 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11376 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11378 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11380 /* We are not done if this is a composite relocation to set up gp. */
11381 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11382 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11383 || (fixP->fx_r_type == BFD_RELOC_64
11384 && (previous_fx_r_type == BFD_RELOC_GPREL32
11385 || previous_fx_r_type == BFD_RELOC_GPREL16))
11386 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11387 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11388 || fixP->fx_r_type == BFD_RELOC_LO16))))
11390 previous_fx_r_type = fixP->fx_r_type;
11392 switch (fixP->fx_r_type)
11394 case BFD_RELOC_MIPS_JMP:
11395 case BFD_RELOC_MIPS_SHIFT5:
11396 case BFD_RELOC_MIPS_SHIFT6:
11397 case BFD_RELOC_MIPS_GOT_DISP:
11398 case BFD_RELOC_MIPS_GOT_PAGE:
11399 case BFD_RELOC_MIPS_GOT_OFST:
11400 case BFD_RELOC_MIPS_SUB:
11401 case BFD_RELOC_MIPS_INSERT_A:
11402 case BFD_RELOC_MIPS_INSERT_B:
11403 case BFD_RELOC_MIPS_DELETE:
11404 case BFD_RELOC_MIPS_HIGHEST:
11405 case BFD_RELOC_MIPS_HIGHER:
11406 case BFD_RELOC_MIPS_SCN_DISP:
11407 case BFD_RELOC_MIPS_REL16:
11408 case BFD_RELOC_MIPS_RELGOT:
11409 case BFD_RELOC_MIPS_JALR:
11410 case BFD_RELOC_HI16:
11411 case BFD_RELOC_HI16_S:
11412 case BFD_RELOC_GPREL16:
11413 case BFD_RELOC_MIPS_LITERAL:
11414 case BFD_RELOC_MIPS_CALL16:
11415 case BFD_RELOC_MIPS_GOT16:
11416 case BFD_RELOC_GPREL32:
11417 case BFD_RELOC_MIPS_GOT_HI16:
11418 case BFD_RELOC_MIPS_GOT_LO16:
11419 case BFD_RELOC_MIPS_CALL_HI16:
11420 case BFD_RELOC_MIPS_CALL_LO16:
11421 case BFD_RELOC_MIPS16_GPREL:
11422 if (fixP->fx_pcrel)
11423 as_bad_where (fixP->fx_file, fixP->fx_line,
11424 _("Invalid PC relative reloc"));
11425 /* Nothing needed to do. The value comes from the reloc entry */
11428 case BFD_RELOC_MIPS16_JMP:
11429 /* We currently always generate a reloc against a symbol, which
11430 means that we don't want an addend even if the symbol is
11435 case BFD_RELOC_PCREL_HI16_S:
11436 /* The addend for this is tricky if it is internal, so we just
11437 do everything here rather than in bfd_install_relocation. */
11438 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11441 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11443 /* For an external symbol adjust by the address to make it
11444 pcrel_offset. We use the address of the RELLO reloc
11445 which follows this one. */
11446 *valP += (fixP->fx_next->fx_frag->fr_address
11447 + fixP->fx_next->fx_where);
11449 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11450 if (target_big_endian)
11452 md_number_to_chars (buf, *valP, 2);
11455 case BFD_RELOC_PCREL_LO16:
11456 /* The addend for this is tricky if it is internal, so we just
11457 do everything here rather than in bfd_install_relocation. */
11458 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11461 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11462 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11463 if (target_big_endian)
11465 md_number_to_chars (buf, *valP, 2);
11469 /* This is handled like BFD_RELOC_32, but we output a sign
11470 extended value if we are only 32 bits. */
11472 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11474 if (8 <= sizeof (valueT))
11475 md_number_to_chars (buf, *valP, 8);
11480 if ((*valP & 0x80000000) != 0)
11484 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11486 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11492 case BFD_RELOC_RVA:
11494 /* If we are deleting this reloc entry, we must fill in the
11495 value now. This can happen if we have a .word which is not
11496 resolved when it appears but is later defined. We also need
11497 to fill in the value if this is an embedded PIC switch table
11500 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11501 md_number_to_chars (buf, *valP, 4);
11505 /* If we are deleting this reloc entry, we must fill in the
11507 assert (fixP->fx_size == 2);
11509 md_number_to_chars (buf, *valP, 2);
11512 case BFD_RELOC_LO16:
11513 /* When handling an embedded PIC switch statement, we can wind
11514 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11517 if (*valP + 0x8000 > 0xffff)
11518 as_bad_where (fixP->fx_file, fixP->fx_line,
11519 _("relocation overflow"));
11520 if (target_big_endian)
11522 md_number_to_chars (buf, *valP, 2);
11526 case BFD_RELOC_16_PCREL_S2:
11527 if ((*valP & 0x3) != 0)
11528 as_bad_where (fixP->fx_file, fixP->fx_line,
11529 _("Branch to odd address (%lx)"), (long) *valP);
11532 * We need to save the bits in the instruction since fixup_segment()
11533 * might be deleting the relocation entry (i.e., a branch within
11534 * the current segment).
11536 if (! fixP->fx_done)
11539 /* update old instruction data */
11540 if (target_big_endian)
11541 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11543 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11545 if (*valP + 0x20000 <= 0x3ffff)
11547 insn |= (*valP >> 2) & 0xffff;
11548 md_number_to_chars (buf, insn, 4);
11550 else if (mips_pic == NO_PIC
11552 && fixP->fx_frag->fr_address >= text_section->vma
11553 && (fixP->fx_frag->fr_address
11554 < text_section->vma + text_section->_raw_size)
11555 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11556 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11557 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11559 /* The branch offset is too large. If this is an
11560 unconditional branch, and we are not generating PIC code,
11561 we can convert it to an absolute jump instruction. */
11562 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11563 insn = 0x0c000000; /* jal */
11565 insn = 0x08000000; /* j */
11566 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11568 fixP->fx_addsy = section_symbol (text_section);
11569 *valP += md_pcrel_from (fixP);
11570 md_number_to_chars (buf, insn, 4);
11574 /* If we got here, we have branch-relaxation disabled,
11575 and there's nothing we can do to fix this instruction
11576 without turning it into a longer sequence. */
11577 as_bad_where (fixP->fx_file, fixP->fx_line,
11578 _("Branch out of range"));
11582 case BFD_RELOC_VTABLE_INHERIT:
11585 && !S_IS_DEFINED (fixP->fx_addsy)
11586 && !S_IS_WEAK (fixP->fx_addsy))
11587 S_SET_WEAK (fixP->fx_addsy);
11590 case BFD_RELOC_VTABLE_ENTRY:
11598 /* Remember value for tc_gen_reloc. */
11599 fixP->fx_addnumber = *valP;
11604 printInsn (unsigned long oc)
11606 const struct mips_opcode *p;
11607 int treg, sreg, dreg, shamt;
11612 for (i = 0; i < NUMOPCODES; ++i)
11614 p = &mips_opcodes[i];
11615 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11617 printf ("%08lx %s\t", oc, p->name);
11618 treg = (oc >> 16) & 0x1f;
11619 sreg = (oc >> 21) & 0x1f;
11620 dreg = (oc >> 11) & 0x1f;
11621 shamt = (oc >> 6) & 0x1f;
11623 for (args = p->args;; ++args)
11634 printf ("%c", *args);
11638 assert (treg == sreg);
11639 printf ("$%d,$%d", treg, sreg);
11644 printf ("$%d", dreg);
11649 printf ("$%d", treg);
11653 printf ("0x%x", treg);
11658 printf ("$%d", sreg);
11662 printf ("0x%08lx", oc & 0x1ffffff);
11669 printf ("%d", imm);
11674 printf ("$%d", shamt);
11685 printf (_("%08lx UNDEFINED\n"), oc);
11696 name = input_line_pointer;
11697 c = get_symbol_end ();
11698 p = (symbolS *) symbol_find_or_make (name);
11699 *input_line_pointer = c;
11703 /* Align the current frag to a given power of two. The MIPS assembler
11704 also automatically adjusts any preceding label. */
11707 mips_align (int to, int fill, symbolS *label)
11709 mips_emit_delays (FALSE);
11710 frag_align (to, fill, 0);
11711 record_alignment (now_seg, to);
11714 assert (S_GET_SEGMENT (label) == now_seg);
11715 symbol_set_frag (label, frag_now);
11716 S_SET_VALUE (label, (valueT) frag_now_fix ());
11720 /* Align to a given power of two. .align 0 turns off the automatic
11721 alignment used by the data creating pseudo-ops. */
11724 s_align (int x ATTRIBUTE_UNUSED)
11727 register long temp_fill;
11728 long max_alignment = 15;
11732 o Note that the assembler pulls down any immediately preceding label
11733 to the aligned address.
11734 o It's not documented but auto alignment is reinstated by
11735 a .align pseudo instruction.
11736 o Note also that after auto alignment is turned off the mips assembler
11737 issues an error on attempt to assemble an improperly aligned data item.
11742 temp = get_absolute_expression ();
11743 if (temp > max_alignment)
11744 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11747 as_warn (_("Alignment negative: 0 assumed."));
11750 if (*input_line_pointer == ',')
11752 ++input_line_pointer;
11753 temp_fill = get_absolute_expression ();
11760 mips_align (temp, (int) temp_fill,
11761 insn_labels != NULL ? insn_labels->label : NULL);
11768 demand_empty_rest_of_line ();
11772 mips_flush_pending_output (void)
11774 mips_emit_delays (FALSE);
11775 mips_clear_insn_labels ();
11779 s_change_sec (int sec)
11783 /* When generating embedded PIC code, we only use the .text, .lit8,
11784 .sdata and .sbss sections. We change the .data and .rdata
11785 pseudo-ops to use .sdata. */
11786 if (mips_pic == EMBEDDED_PIC
11787 && (sec == 'd' || sec == 'r'))
11791 /* The ELF backend needs to know that we are changing sections, so
11792 that .previous works correctly. We could do something like check
11793 for an obj_section_change_hook macro, but that might be confusing
11794 as it would not be appropriate to use it in the section changing
11795 functions in read.c, since obj-elf.c intercepts those. FIXME:
11796 This should be cleaner, somehow. */
11797 obj_elf_section_change_hook ();
11800 mips_emit_delays (FALSE);
11810 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11811 demand_empty_rest_of_line ();
11815 if (USE_GLOBAL_POINTER_OPT)
11817 seg = subseg_new (RDATA_SECTION_NAME,
11818 (subsegT) get_absolute_expression ());
11819 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11821 bfd_set_section_flags (stdoutput, seg,
11827 if (strcmp (TARGET_OS, "elf") != 0)
11828 record_alignment (seg, 4);
11830 demand_empty_rest_of_line ();
11834 as_bad (_("No read only data section in this object file format"));
11835 demand_empty_rest_of_line ();
11841 if (USE_GLOBAL_POINTER_OPT)
11843 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11844 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11846 bfd_set_section_flags (stdoutput, seg,
11847 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11849 if (strcmp (TARGET_OS, "elf") != 0)
11850 record_alignment (seg, 4);
11852 demand_empty_rest_of_line ();
11857 as_bad (_("Global pointers not supported; recompile -G 0"));
11858 demand_empty_rest_of_line ();
11867 s_change_section (int ignore ATTRIBUTE_UNUSED)
11870 char *section_name;
11875 int section_entry_size;
11876 int section_alignment;
11878 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11881 section_name = input_line_pointer;
11882 c = get_symbol_end ();
11884 next_c = *(input_line_pointer + 1);
11886 /* Do we have .section Name<,"flags">? */
11887 if (c != ',' || (c == ',' && next_c == '"'))
11889 /* just after name is now '\0'. */
11890 *input_line_pointer = c;
11891 input_line_pointer = section_name;
11892 obj_elf_section (ignore);
11895 input_line_pointer++;
11897 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11899 section_type = get_absolute_expression ();
11902 if (*input_line_pointer++ == ',')
11903 section_flag = get_absolute_expression ();
11906 if (*input_line_pointer++ == ',')
11907 section_entry_size = get_absolute_expression ();
11909 section_entry_size = 0;
11910 if (*input_line_pointer++ == ',')
11911 section_alignment = get_absolute_expression ();
11913 section_alignment = 0;
11915 section_name = xstrdup (section_name);
11917 /* When using the generic form of .section (as implemented by obj-elf.c),
11918 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11919 traditionally had to fall back on the more common @progbits instead.
11921 There's nothing really harmful in this, since bfd will correct
11922 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11923 means that, for backwards compatibiltiy, the special_section entries
11924 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11926 Even so, we shouldn't force users of the MIPS .section syntax to
11927 incorrectly label the sections as SHT_PROGBITS. The best compromise
11928 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11929 generic type-checking code. */
11930 if (section_type == SHT_MIPS_DWARF)
11931 section_type = SHT_PROGBITS;
11933 obj_elf_change_section (section_name, section_type, section_flag,
11934 section_entry_size, 0, 0, 0);
11936 if (now_seg->name != section_name)
11937 free (section_name);
11938 #endif /* OBJ_ELF */
11942 mips_enable_auto_align (void)
11948 s_cons (int log_size)
11952 label = insn_labels != NULL ? insn_labels->label : NULL;
11953 mips_emit_delays (FALSE);
11954 if (log_size > 0 && auto_align)
11955 mips_align (log_size, 0, label);
11956 mips_clear_insn_labels ();
11957 cons (1 << log_size);
11961 s_float_cons (int type)
11965 label = insn_labels != NULL ? insn_labels->label : NULL;
11967 mips_emit_delays (FALSE);
11972 mips_align (3, 0, label);
11974 mips_align (2, 0, label);
11977 mips_clear_insn_labels ();
11982 /* Handle .globl. We need to override it because on Irix 5 you are
11985 where foo is an undefined symbol, to mean that foo should be
11986 considered to be the address of a function. */
11989 s_mips_globl (int x ATTRIBUTE_UNUSED)
11996 name = input_line_pointer;
11997 c = get_symbol_end ();
11998 symbolP = symbol_find_or_make (name);
11999 *input_line_pointer = c;
12000 SKIP_WHITESPACE ();
12002 /* On Irix 5, every global symbol that is not explicitly labelled as
12003 being a function is apparently labelled as being an object. */
12006 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12011 secname = input_line_pointer;
12012 c = get_symbol_end ();
12013 sec = bfd_get_section_by_name (stdoutput, secname);
12015 as_bad (_("%s: no such section"), secname);
12016 *input_line_pointer = c;
12018 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12019 flag = BSF_FUNCTION;
12022 symbol_get_bfdsym (symbolP)->flags |= flag;
12024 S_SET_EXTERNAL (symbolP);
12025 demand_empty_rest_of_line ();
12029 s_option (int x ATTRIBUTE_UNUSED)
12034 opt = input_line_pointer;
12035 c = get_symbol_end ();
12039 /* FIXME: What does this mean? */
12041 else if (strncmp (opt, "pic", 3) == 0)
12045 i = atoi (opt + 3);
12050 mips_pic = SVR4_PIC;
12051 mips_abicalls = TRUE;
12054 as_bad (_(".option pic%d not supported"), i);
12056 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
12058 if (g_switch_seen && g_switch_value != 0)
12059 as_warn (_("-G may not be used with SVR4 PIC code"));
12060 g_switch_value = 0;
12061 bfd_set_gp_size (stdoutput, 0);
12065 as_warn (_("Unrecognized option \"%s\""), opt);
12067 *input_line_pointer = c;
12068 demand_empty_rest_of_line ();
12071 /* This structure is used to hold a stack of .set values. */
12073 struct mips_option_stack
12075 struct mips_option_stack *next;
12076 struct mips_set_options options;
12079 static struct mips_option_stack *mips_opts_stack;
12081 /* Handle the .set pseudo-op. */
12084 s_mipsset (int x ATTRIBUTE_UNUSED)
12086 char *name = input_line_pointer, ch;
12088 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12089 ++input_line_pointer;
12090 ch = *input_line_pointer;
12091 *input_line_pointer = '\0';
12093 if (strcmp (name, "reorder") == 0)
12095 if (mips_opts.noreorder && prev_nop_frag != NULL)
12097 /* If we still have pending nops, we can discard them. The
12098 usual nop handling will insert any that are still
12100 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12101 * (mips_opts.mips16 ? 2 : 4));
12102 prev_nop_frag = NULL;
12104 mips_opts.noreorder = 0;
12106 else if (strcmp (name, "noreorder") == 0)
12108 mips_emit_delays (TRUE);
12109 mips_opts.noreorder = 1;
12110 mips_any_noreorder = 1;
12112 else if (strcmp (name, "at") == 0)
12114 mips_opts.noat = 0;
12116 else if (strcmp (name, "noat") == 0)
12118 mips_opts.noat = 1;
12120 else if (strcmp (name, "macro") == 0)
12122 mips_opts.warn_about_macros = 0;
12124 else if (strcmp (name, "nomacro") == 0)
12126 if (mips_opts.noreorder == 0)
12127 as_bad (_("`noreorder' must be set before `nomacro'"));
12128 mips_opts.warn_about_macros = 1;
12130 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12132 mips_opts.nomove = 0;
12134 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12136 mips_opts.nomove = 1;
12138 else if (strcmp (name, "bopt") == 0)
12140 mips_opts.nobopt = 0;
12142 else if (strcmp (name, "nobopt") == 0)
12144 mips_opts.nobopt = 1;
12146 else if (strcmp (name, "mips16") == 0
12147 || strcmp (name, "MIPS-16") == 0)
12148 mips_opts.mips16 = 1;
12149 else if (strcmp (name, "nomips16") == 0
12150 || strcmp (name, "noMIPS-16") == 0)
12151 mips_opts.mips16 = 0;
12152 else if (strcmp (name, "mips3d") == 0)
12153 mips_opts.ase_mips3d = 1;
12154 else if (strcmp (name, "nomips3d") == 0)
12155 mips_opts.ase_mips3d = 0;
12156 else if (strcmp (name, "mdmx") == 0)
12157 mips_opts.ase_mdmx = 1;
12158 else if (strcmp (name, "nomdmx") == 0)
12159 mips_opts.ase_mdmx = 0;
12160 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12164 /* Permit the user to change the ISA and architecture on the fly.
12165 Needless to say, misuse can cause serious problems. */
12166 if (strcmp (name, "mips0") == 0)
12169 mips_opts.isa = file_mips_isa;
12171 else if (strcmp (name, "mips1") == 0)
12172 mips_opts.isa = ISA_MIPS1;
12173 else if (strcmp (name, "mips2") == 0)
12174 mips_opts.isa = ISA_MIPS2;
12175 else if (strcmp (name, "mips3") == 0)
12176 mips_opts.isa = ISA_MIPS3;
12177 else if (strcmp (name, "mips4") == 0)
12178 mips_opts.isa = ISA_MIPS4;
12179 else if (strcmp (name, "mips5") == 0)
12180 mips_opts.isa = ISA_MIPS5;
12181 else if (strcmp (name, "mips32") == 0)
12182 mips_opts.isa = ISA_MIPS32;
12183 else if (strcmp (name, "mips32r2") == 0)
12184 mips_opts.isa = ISA_MIPS32R2;
12185 else if (strcmp (name, "mips64") == 0)
12186 mips_opts.isa = ISA_MIPS64;
12187 else if (strcmp (name, "mips64r2") == 0)
12188 mips_opts.isa = ISA_MIPS64R2;
12189 else if (strcmp (name, "arch=default") == 0)
12192 mips_opts.arch = file_mips_arch;
12193 mips_opts.isa = file_mips_isa;
12195 else if (strncmp (name, "arch=", 5) == 0)
12197 const struct mips_cpu_info *p;
12199 p = mips_parse_cpu("internal use", name + 5);
12201 as_bad (_("unknown architecture %s"), name + 5);
12204 mips_opts.arch = p->cpu;
12205 mips_opts.isa = p->isa;
12209 as_bad (_("unknown ISA level %s"), name + 4);
12211 switch (mips_opts.isa)
12219 mips_opts.gp32 = 1;
12220 mips_opts.fp32 = 1;
12227 mips_opts.gp32 = 0;
12228 mips_opts.fp32 = 0;
12231 as_bad (_("unknown ISA level %s"), name + 4);
12236 mips_opts.gp32 = file_mips_gp32;
12237 mips_opts.fp32 = file_mips_fp32;
12240 else if (strcmp (name, "autoextend") == 0)
12241 mips_opts.noautoextend = 0;
12242 else if (strcmp (name, "noautoextend") == 0)
12243 mips_opts.noautoextend = 1;
12244 else if (strcmp (name, "push") == 0)
12246 struct mips_option_stack *s;
12248 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12249 s->next = mips_opts_stack;
12250 s->options = mips_opts;
12251 mips_opts_stack = s;
12253 else if (strcmp (name, "pop") == 0)
12255 struct mips_option_stack *s;
12257 s = mips_opts_stack;
12259 as_bad (_(".set pop with no .set push"));
12262 /* If we're changing the reorder mode we need to handle
12263 delay slots correctly. */
12264 if (s->options.noreorder && ! mips_opts.noreorder)
12265 mips_emit_delays (TRUE);
12266 else if (! s->options.noreorder && mips_opts.noreorder)
12268 if (prev_nop_frag != NULL)
12270 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12271 * (mips_opts.mips16 ? 2 : 4));
12272 prev_nop_frag = NULL;
12276 mips_opts = s->options;
12277 mips_opts_stack = s->next;
12283 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12285 *input_line_pointer = ch;
12286 demand_empty_rest_of_line ();
12289 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12290 .option pic2. It means to generate SVR4 PIC calls. */
12293 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12295 mips_pic = SVR4_PIC;
12296 mips_abicalls = TRUE;
12297 if (USE_GLOBAL_POINTER_OPT)
12299 if (g_switch_seen && g_switch_value != 0)
12300 as_warn (_("-G may not be used with SVR4 PIC code"));
12301 g_switch_value = 0;
12303 bfd_set_gp_size (stdoutput, 0);
12304 demand_empty_rest_of_line ();
12307 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12308 PIC code. It sets the $gp register for the function based on the
12309 function address, which is in the register named in the argument.
12310 This uses a relocation against _gp_disp, which is handled specially
12311 by the linker. The result is:
12312 lui $gp,%hi(_gp_disp)
12313 addiu $gp,$gp,%lo(_gp_disp)
12314 addu $gp,$gp,.cpload argument
12315 The .cpload argument is normally $25 == $t9. */
12318 s_cpload (int ignore ATTRIBUTE_UNUSED)
12323 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12324 .cpload is ignored. */
12325 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12331 /* .cpload should be in a .set noreorder section. */
12332 if (mips_opts.noreorder == 0)
12333 as_warn (_(".cpload not in noreorder section"));
12335 ex.X_op = O_symbol;
12336 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12337 ex.X_op_symbol = NULL;
12338 ex.X_add_number = 0;
12340 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12341 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12343 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12344 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12345 mips_gp_register, BFD_RELOC_LO16);
12347 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12348 mips_gp_register, tc_get_register (0));
12350 demand_empty_rest_of_line ();
12353 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12354 .cpsetup $reg1, offset|$reg2, label
12356 If offset is given, this results in:
12357 sd $gp, offset($sp)
12358 lui $gp, %hi(%neg(%gp_rel(label)))
12359 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12360 daddu $gp, $gp, $reg1
12362 If $reg2 is given, this results in:
12363 daddu $reg2, $gp, $0
12364 lui $gp, %hi(%neg(%gp_rel(label)))
12365 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12366 daddu $gp, $gp, $reg1
12367 $reg1 is normally $25 == $t9. */
12369 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12371 expressionS ex_off;
12372 expressionS ex_sym;
12377 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12378 We also need NewABI support. */
12379 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12385 reg1 = tc_get_register (0);
12386 SKIP_WHITESPACE ();
12387 if (*input_line_pointer != ',')
12389 as_bad (_("missing argument separator ',' for .cpsetup"));
12393 ++input_line_pointer;
12394 SKIP_WHITESPACE ();
12395 if (*input_line_pointer == '$')
12397 mips_cpreturn_register = tc_get_register (0);
12398 mips_cpreturn_offset = -1;
12402 mips_cpreturn_offset = get_absolute_expression ();
12403 mips_cpreturn_register = -1;
12405 SKIP_WHITESPACE ();
12406 if (*input_line_pointer != ',')
12408 as_bad (_("missing argument separator ',' for .cpsetup"));
12412 ++input_line_pointer;
12413 SKIP_WHITESPACE ();
12414 expression (&ex_sym);
12416 if (mips_cpreturn_register == -1)
12418 ex_off.X_op = O_constant;
12419 ex_off.X_add_symbol = NULL;
12420 ex_off.X_op_symbol = NULL;
12421 ex_off.X_add_number = mips_cpreturn_offset;
12423 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12424 BFD_RELOC_LO16, SP);
12427 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12428 mips_gp_register, 0);
12430 /* Ensure there's room for the next two instructions, so that `f'
12431 doesn't end up with an address in the wrong frag. */
12434 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12435 BFD_RELOC_GPREL16);
12436 fix_new (frag_now, f - frag_now->fr_literal,
12437 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12438 fix_new (frag_now, f - frag_now->fr_literal,
12439 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12442 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12443 mips_gp_register, BFD_RELOC_GPREL16);
12444 fix_new (frag_now, f - frag_now->fr_literal,
12445 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12446 fix_new (frag_now, f - frag_now->fr_literal,
12447 4, NULL, 0, 0, BFD_RELOC_LO16);
12449 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12450 mips_gp_register, reg1);
12452 demand_empty_rest_of_line ();
12456 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12458 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12459 .cplocal is ignored. */
12460 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12466 mips_gp_register = tc_get_register (0);
12467 demand_empty_rest_of_line ();
12470 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12471 offset from $sp. The offset is remembered, and after making a PIC
12472 call $gp is restored from that location. */
12475 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12480 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12481 .cprestore is ignored. */
12482 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12488 mips_cprestore_offset = get_absolute_expression ();
12489 mips_cprestore_valid = 1;
12491 ex.X_op = O_constant;
12492 ex.X_add_symbol = NULL;
12493 ex.X_op_symbol = NULL;
12494 ex.X_add_number = mips_cprestore_offset;
12496 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12497 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12499 demand_empty_rest_of_line ();
12502 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12503 was given in the preceding .cpsetup, it results in:
12504 ld $gp, offset($sp)
12506 If a register $reg2 was given there, it results in:
12507 daddu $gp, $reg2, $0
12510 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12515 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12516 We also need NewABI support. */
12517 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12523 if (mips_cpreturn_register == -1)
12525 ex.X_op = O_constant;
12526 ex.X_add_symbol = NULL;
12527 ex.X_op_symbol = NULL;
12528 ex.X_add_number = mips_cpreturn_offset;
12530 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12531 BFD_RELOC_LO16, SP);
12534 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12535 mips_cpreturn_register, 0);
12537 demand_empty_rest_of_line ();
12540 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12541 code. It sets the offset to use in gp_rel relocations. */
12544 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12546 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12547 We also need NewABI support. */
12548 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12554 mips_gprel_offset = get_absolute_expression ();
12556 demand_empty_rest_of_line ();
12559 /* Handle the .gpword pseudo-op. This is used when generating PIC
12560 code. It generates a 32 bit GP relative reloc. */
12563 s_gpword (int ignore ATTRIBUTE_UNUSED)
12569 /* When not generating PIC code, this is treated as .word. */
12570 if (mips_pic != SVR4_PIC)
12576 label = insn_labels != NULL ? insn_labels->label : NULL;
12577 mips_emit_delays (TRUE);
12579 mips_align (2, 0, label);
12580 mips_clear_insn_labels ();
12584 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12586 as_bad (_("Unsupported use of .gpword"));
12587 ignore_rest_of_line ();
12591 md_number_to_chars (p, 0, 4);
12592 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12593 BFD_RELOC_GPREL32);
12595 demand_empty_rest_of_line ();
12599 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12605 /* When not generating PIC code, this is treated as .dword. */
12606 if (mips_pic != SVR4_PIC)
12612 label = insn_labels != NULL ? insn_labels->label : NULL;
12613 mips_emit_delays (TRUE);
12615 mips_align (3, 0, label);
12616 mips_clear_insn_labels ();
12620 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12622 as_bad (_("Unsupported use of .gpdword"));
12623 ignore_rest_of_line ();
12627 md_number_to_chars (p, 0, 8);
12628 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12629 BFD_RELOC_GPREL32);
12631 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12632 ex.X_op = O_absent;
12633 ex.X_add_symbol = 0;
12634 ex.X_add_number = 0;
12635 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12638 demand_empty_rest_of_line ();
12641 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12642 tables in SVR4 PIC code. */
12645 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12650 /* This is ignored when not generating SVR4 PIC code. */
12651 if (mips_pic != SVR4_PIC)
12657 /* Add $gp to the register named as an argument. */
12658 reg = tc_get_register (0);
12659 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12660 reg, reg, mips_gp_register);
12662 demand_empty_rest_of_line ();
12665 /* Handle the .insn pseudo-op. This marks instruction labels in
12666 mips16 mode. This permits the linker to handle them specially,
12667 such as generating jalx instructions when needed. We also make
12668 them odd for the duration of the assembly, in order to generate the
12669 right sort of code. We will make them even in the adjust_symtab
12670 routine, while leaving them marked. This is convenient for the
12671 debugger and the disassembler. The linker knows to make them odd
12675 s_insn (int ignore ATTRIBUTE_UNUSED)
12677 mips16_mark_labels ();
12679 demand_empty_rest_of_line ();
12682 /* Handle a .stabn directive. We need these in order to mark a label
12683 as being a mips16 text label correctly. Sometimes the compiler
12684 will emit a label, followed by a .stabn, and then switch sections.
12685 If the label and .stabn are in mips16 mode, then the label is
12686 really a mips16 text label. */
12689 s_mips_stab (int type)
12692 mips16_mark_labels ();
12697 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12701 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12708 name = input_line_pointer;
12709 c = get_symbol_end ();
12710 symbolP = symbol_find_or_make (name);
12711 S_SET_WEAK (symbolP);
12712 *input_line_pointer = c;
12714 SKIP_WHITESPACE ();
12716 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12718 if (S_IS_DEFINED (symbolP))
12720 as_bad ("ignoring attempt to redefine symbol %s",
12721 S_GET_NAME (symbolP));
12722 ignore_rest_of_line ();
12726 if (*input_line_pointer == ',')
12728 ++input_line_pointer;
12729 SKIP_WHITESPACE ();
12733 if (exp.X_op != O_symbol)
12735 as_bad ("bad .weakext directive");
12736 ignore_rest_of_line ();
12739 symbol_set_value_expression (symbolP, &exp);
12742 demand_empty_rest_of_line ();
12745 /* Parse a register string into a number. Called from the ECOFF code
12746 to parse .frame. The argument is non-zero if this is the frame
12747 register, so that we can record it in mips_frame_reg. */
12750 tc_get_register (int frame)
12754 SKIP_WHITESPACE ();
12755 if (*input_line_pointer++ != '$')
12757 as_warn (_("expected `$'"));
12760 else if (ISDIGIT (*input_line_pointer))
12762 reg = get_absolute_expression ();
12763 if (reg < 0 || reg >= 32)
12765 as_warn (_("Bad register number"));
12771 if (strncmp (input_line_pointer, "ra", 2) == 0)
12774 input_line_pointer += 2;
12776 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12779 input_line_pointer += 2;
12781 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12784 input_line_pointer += 2;
12786 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12789 input_line_pointer += 2;
12791 else if (strncmp (input_line_pointer, "at", 2) == 0)
12794 input_line_pointer += 2;
12796 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12799 input_line_pointer += 3;
12801 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12804 input_line_pointer += 3;
12806 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12809 input_line_pointer += 4;
12813 as_warn (_("Unrecognized register name"));
12815 while (ISALNUM(*input_line_pointer))
12816 input_line_pointer++;
12821 mips_frame_reg = reg != 0 ? reg : SP;
12822 mips_frame_reg_valid = 1;
12823 mips_cprestore_valid = 0;
12829 md_section_align (asection *seg, valueT addr)
12831 int align = bfd_get_section_alignment (stdoutput, seg);
12834 /* We don't need to align ELF sections to the full alignment.
12835 However, Irix 5 may prefer that we align them at least to a 16
12836 byte boundary. We don't bother to align the sections if we are
12837 targeted for an embedded system. */
12838 if (strcmp (TARGET_OS, "elf") == 0)
12844 return ((addr + (1 << align) - 1) & (-1 << align));
12847 /* Utility routine, called from above as well. If called while the
12848 input file is still being read, it's only an approximation. (For
12849 example, a symbol may later become defined which appeared to be
12850 undefined earlier.) */
12853 nopic_need_relax (symbolS *sym, int before_relaxing)
12858 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12860 const char *symname;
12863 /* Find out whether this symbol can be referenced off the $gp
12864 register. It can be if it is smaller than the -G size or if
12865 it is in the .sdata or .sbss section. Certain symbols can
12866 not be referenced off the $gp, although it appears as though
12868 symname = S_GET_NAME (sym);
12869 if (symname != (const char *) NULL
12870 && (strcmp (symname, "eprol") == 0
12871 || strcmp (symname, "etext") == 0
12872 || strcmp (symname, "_gp") == 0
12873 || strcmp (symname, "edata") == 0
12874 || strcmp (symname, "_fbss") == 0
12875 || strcmp (symname, "_fdata") == 0
12876 || strcmp (symname, "_ftext") == 0
12877 || strcmp (symname, "end") == 0
12878 || strcmp (symname, "_gp_disp") == 0))
12880 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12882 #ifndef NO_ECOFF_DEBUGGING
12883 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12884 && (symbol_get_obj (sym)->ecoff_extern_size
12885 <= g_switch_value))
12887 /* We must defer this decision until after the whole
12888 file has been read, since there might be a .extern
12889 after the first use of this symbol. */
12890 || (before_relaxing
12891 #ifndef NO_ECOFF_DEBUGGING
12892 && symbol_get_obj (sym)->ecoff_extern_size == 0
12894 && S_GET_VALUE (sym) == 0)
12895 || (S_GET_VALUE (sym) != 0
12896 && S_GET_VALUE (sym) <= g_switch_value)))
12900 const char *segname;
12902 segname = segment_name (S_GET_SEGMENT (sym));
12903 assert (strcmp (segname, ".lit8") != 0
12904 && strcmp (segname, ".lit4") != 0);
12905 change = (strcmp (segname, ".sdata") != 0
12906 && strcmp (segname, ".sbss") != 0
12907 && strncmp (segname, ".sdata.", 7) != 0
12908 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12913 /* We are not optimizing for the $gp register. */
12918 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12921 pic_need_relax (symbolS *sym, asection *segtype)
12924 bfd_boolean linkonce;
12926 /* Handle the case of a symbol equated to another symbol. */
12927 while (symbol_equated_reloc_p (sym))
12931 /* It's possible to get a loop here in a badly written
12933 n = symbol_get_value_expression (sym)->X_add_symbol;
12939 symsec = S_GET_SEGMENT (sym);
12941 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12943 if (symsec != segtype && ! S_IS_LOCAL (sym))
12945 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12949 /* The GNU toolchain uses an extension for ELF: a section
12950 beginning with the magic string .gnu.linkonce is a linkonce
12952 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12953 sizeof ".gnu.linkonce" - 1) == 0)
12957 /* This must duplicate the test in adjust_reloc_syms. */
12958 return (symsec != &bfd_und_section
12959 && symsec != &bfd_abs_section
12960 && ! bfd_is_com_section (symsec)
12963 /* A global or weak symbol is treated as external. */
12964 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12965 || (! S_IS_WEAK (sym)
12966 && (! S_IS_EXTERNAL (sym)
12967 || mips_pic == EMBEDDED_PIC)))
12973 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12974 extended opcode. SEC is the section the frag is in. */
12977 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12980 register const struct mips16_immed_operand *op;
12982 int mintiny, maxtiny;
12986 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12988 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12991 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12992 op = mips16_immed_operands;
12993 while (op->type != type)
12996 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13001 if (type == '<' || type == '>' || type == '[' || type == ']')
13004 maxtiny = 1 << op->nbits;
13009 maxtiny = (1 << op->nbits) - 1;
13014 mintiny = - (1 << (op->nbits - 1));
13015 maxtiny = (1 << (op->nbits - 1)) - 1;
13018 sym_frag = symbol_get_frag (fragp->fr_symbol);
13019 val = S_GET_VALUE (fragp->fr_symbol);
13020 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13026 /* We won't have the section when we are called from
13027 mips_relax_frag. However, we will always have been called
13028 from md_estimate_size_before_relax first. If this is a
13029 branch to a different section, we mark it as such. If SEC is
13030 NULL, and the frag is not marked, then it must be a branch to
13031 the same section. */
13034 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13039 /* Must have been called from md_estimate_size_before_relax. */
13042 fragp->fr_subtype =
13043 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13045 /* FIXME: We should support this, and let the linker
13046 catch branches and loads that are out of range. */
13047 as_bad_where (fragp->fr_file, fragp->fr_line,
13048 _("unsupported PC relative reference to different section"));
13052 if (fragp != sym_frag && sym_frag->fr_address == 0)
13053 /* Assume non-extended on the first relaxation pass.
13054 The address we have calculated will be bogus if this is
13055 a forward branch to another frag, as the forward frag
13056 will have fr_address == 0. */
13060 /* In this case, we know for sure that the symbol fragment is in
13061 the same section. If the relax_marker of the symbol fragment
13062 differs from the relax_marker of this fragment, we have not
13063 yet adjusted the symbol fragment fr_address. We want to add
13064 in STRETCH in order to get a better estimate of the address.
13065 This particularly matters because of the shift bits. */
13067 && sym_frag->relax_marker != fragp->relax_marker)
13071 /* Adjust stretch for any alignment frag. Note that if have
13072 been expanding the earlier code, the symbol may be
13073 defined in what appears to be an earlier frag. FIXME:
13074 This doesn't handle the fr_subtype field, which specifies
13075 a maximum number of bytes to skip when doing an
13077 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13079 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13082 stretch = - ((- stretch)
13083 & ~ ((1 << (int) f->fr_offset) - 1));
13085 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13094 addr = fragp->fr_address + fragp->fr_fix;
13096 /* The base address rules are complicated. The base address of
13097 a branch is the following instruction. The base address of a
13098 PC relative load or add is the instruction itself, but if it
13099 is in a delay slot (in which case it can not be extended) use
13100 the address of the instruction whose delay slot it is in. */
13101 if (type == 'p' || type == 'q')
13105 /* If we are currently assuming that this frag should be
13106 extended, then, the current address is two bytes
13108 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13111 /* Ignore the low bit in the target, since it will be set
13112 for a text label. */
13113 if ((val & 1) != 0)
13116 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13118 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13121 val -= addr & ~ ((1 << op->shift) - 1);
13123 /* Branch offsets have an implicit 0 in the lowest bit. */
13124 if (type == 'p' || type == 'q')
13127 /* If any of the shifted bits are set, we must use an extended
13128 opcode. If the address depends on the size of this
13129 instruction, this can lead to a loop, so we arrange to always
13130 use an extended opcode. We only check this when we are in
13131 the main relaxation loop, when SEC is NULL. */
13132 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13134 fragp->fr_subtype =
13135 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13139 /* If we are about to mark a frag as extended because the value
13140 is precisely maxtiny + 1, then there is a chance of an
13141 infinite loop as in the following code:
13146 In this case when the la is extended, foo is 0x3fc bytes
13147 away, so the la can be shrunk, but then foo is 0x400 away, so
13148 the la must be extended. To avoid this loop, we mark the
13149 frag as extended if it was small, and is about to become
13150 extended with a value of maxtiny + 1. */
13151 if (val == ((maxtiny + 1) << op->shift)
13152 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13155 fragp->fr_subtype =
13156 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13160 else if (symsec != absolute_section && sec != NULL)
13161 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13163 if ((val & ((1 << op->shift) - 1)) != 0
13164 || val < (mintiny << op->shift)
13165 || val > (maxtiny << op->shift))
13171 /* Compute the length of a branch sequence, and adjust the
13172 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13173 worst-case length is computed, with UPDATE being used to indicate
13174 whether an unconditional (-1), branch-likely (+1) or regular (0)
13175 branch is to be computed. */
13177 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13179 bfd_boolean toofar;
13183 && S_IS_DEFINED (fragp->fr_symbol)
13184 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13189 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13191 addr = fragp->fr_address + fragp->fr_fix + 4;
13195 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13198 /* If the symbol is not defined or it's in a different segment,
13199 assume the user knows what's going on and emit a short
13205 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13207 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13208 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13209 RELAX_BRANCH_LINK (fragp->fr_subtype),
13215 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13218 if (mips_pic != NO_PIC)
13220 /* Additional space for PIC loading of target address. */
13222 if (mips_opts.isa == ISA_MIPS1)
13223 /* Additional space for $at-stabilizing nop. */
13227 /* If branch is conditional. */
13228 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13235 /* Estimate the size of a frag before relaxing. Unless this is the
13236 mips16, we are not really relaxing here, and the final size is
13237 encoded in the subtype information. For the mips16, we have to
13238 decide whether we are using an extended opcode or not. */
13241 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13245 if (RELAX_BRANCH_P (fragp->fr_subtype))
13248 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13250 return fragp->fr_var;
13253 if (RELAX_MIPS16_P (fragp->fr_subtype))
13254 /* We don't want to modify the EXTENDED bit here; it might get us
13255 into infinite loops. We change it only in mips_relax_frag(). */
13256 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13258 if (mips_pic == NO_PIC)
13259 change = nopic_need_relax (fragp->fr_symbol, 0);
13260 else if (mips_pic == SVR4_PIC)
13261 change = pic_need_relax (fragp->fr_symbol, segtype);
13267 /* Record the offset to the first reloc in the fr_opcode field.
13268 This lets md_convert_frag and tc_gen_reloc know that the code
13269 must be expanded. */
13270 fragp->fr_opcode = (fragp->fr_literal
13272 - RELAX_OLD (fragp->fr_subtype)
13273 + RELAX_RELOC1 (fragp->fr_subtype));
13274 /* FIXME: This really needs as_warn_where. */
13275 if (RELAX_WARN (fragp->fr_subtype))
13276 as_warn (_("AT used after \".set noat\" or macro used after "
13277 "\".set nomacro\""));
13279 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13285 /* This is called to see whether a reloc against a defined symbol
13286 should be converted into a reloc against a section. Don't adjust
13287 MIPS16 jump relocations, so we don't have to worry about the format
13288 of the offset in the .o file. Don't adjust relocations against
13289 mips16 symbols, so that the linker can find them if it needs to set
13293 mips_fix_adjustable (fixS *fixp)
13295 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13298 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13299 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13302 if (fixp->fx_addsy == NULL)
13306 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13307 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13308 && fixp->fx_subsy == NULL)
13315 /* Translate internal representation of relocation info to BFD target
13319 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13321 static arelent *retval[4];
13323 bfd_reloc_code_real_type code;
13325 memset (retval, 0, sizeof(retval));
13326 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13327 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13328 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13329 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13331 if (mips_pic == EMBEDDED_PIC
13332 && SWITCH_TABLE (fixp))
13334 /* For a switch table entry we use a special reloc. The addend
13335 is actually the difference between the reloc address and the
13337 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13338 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13339 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13340 fixp->fx_r_type = BFD_RELOC_GPREL32;
13342 else if (fixp->fx_pcrel)
13344 bfd_vma pcrel_address;
13346 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13347 high-part relocs is the address of the low-part reloc. */
13348 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13350 assert (fixp->fx_next != NULL
13351 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13352 pcrel_address = (fixp->fx_next->fx_where
13353 + fixp->fx_next->fx_frag->fr_address);
13356 pcrel_address = reloc->address;
13358 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13360 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13361 Relocations want only the symbol offset. */
13362 reloc->addend = fixp->fx_addnumber + pcrel_address;
13364 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13365 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13367 /* We use a special addend for an internal RELLO or RELHI reloc. */
13368 if (symbol_section_p (fixp->fx_addsy))
13369 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13371 reloc->addend = fixp->fx_addnumber + pcrel_address;
13375 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13376 /* A gruesome hack which is a result of the gruesome gas reloc
13378 reloc->addend = pcrel_address;
13380 reloc->addend = -pcrel_address;
13384 reloc->addend = fixp->fx_addnumber;
13386 /* If this is a variant frag, we may need to adjust the existing
13387 reloc and generate a new one. */
13388 if (fixp->fx_frag->fr_opcode != NULL
13389 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13391 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13393 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13394 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13395 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13396 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13397 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13398 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13403 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13405 /* If this is not the last reloc in this frag, then we have two
13406 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13407 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13408 the second one handle all of them. */
13409 if (fixp->fx_next != NULL
13410 && fixp->fx_frag == fixp->fx_next->fx_frag)
13412 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13413 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13414 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13415 && (fixp->fx_next->fx_r_type
13416 == BFD_RELOC_MIPS_GOT_LO16))
13417 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13418 && (fixp->fx_next->fx_r_type
13419 == BFD_RELOC_MIPS_CALL_LO16)));
13424 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13425 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13426 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13427 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13428 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13429 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13430 reloc2->address = (reloc->address
13431 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13432 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13433 reloc2->addend = reloc->addend;
13434 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13435 assert (reloc2->howto != NULL);
13437 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13441 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13443 reloc3->address += 4;
13446 if (mips_pic == NO_PIC)
13448 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13449 fixp->fx_r_type = BFD_RELOC_HI16_S;
13451 else if (mips_pic == SVR4_PIC)
13453 switch (fixp->fx_r_type)
13457 case BFD_RELOC_MIPS_GOT16:
13459 case BFD_RELOC_MIPS_GOT_LO16:
13460 case BFD_RELOC_MIPS_CALL_LO16:
13463 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13464 reloc2->howto = bfd_reloc_type_lookup
13465 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13468 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13470 case BFD_RELOC_MIPS_CALL16:
13471 case BFD_RELOC_MIPS_GOT_OFST:
13472 case BFD_RELOC_MIPS_GOT_DISP:
13475 /* It may seem nonsensical to relax GOT_DISP to
13476 GOT_DISP, but we're actually turning a GOT_DISP
13477 without offset into a GOT_DISP with an offset,
13478 getting rid of the separate addition, which we can
13479 do when the symbol is found to be local. */
13480 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13484 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13492 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13493 entry to be used in the relocation's section offset. */
13494 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13496 reloc->address = reloc->addend;
13500 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13501 fixup_segment converted a non-PC relative reloc into a PC
13502 relative reloc. In such a case, we need to convert the reloc
13504 code = fixp->fx_r_type;
13505 if (fixp->fx_pcrel)
13510 code = BFD_RELOC_8_PCREL;
13513 code = BFD_RELOC_16_PCREL;
13516 code = BFD_RELOC_32_PCREL;
13519 code = BFD_RELOC_64_PCREL;
13521 case BFD_RELOC_8_PCREL:
13522 case BFD_RELOC_16_PCREL:
13523 case BFD_RELOC_32_PCREL:
13524 case BFD_RELOC_64_PCREL:
13525 case BFD_RELOC_16_PCREL_S2:
13526 case BFD_RELOC_PCREL_HI16_S:
13527 case BFD_RELOC_PCREL_LO16:
13530 as_bad_where (fixp->fx_file, fixp->fx_line,
13531 _("Cannot make %s relocation PC relative"),
13532 bfd_get_reloc_code_name (code));
13536 /* To support a PC relative reloc when generating embedded PIC code
13537 for ECOFF, we use a Cygnus extension. We check for that here to
13538 make sure that we don't let such a reloc escape normally. */
13539 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13540 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13541 && code == BFD_RELOC_16_PCREL_S2
13542 && mips_pic != EMBEDDED_PIC)
13543 reloc->howto = NULL;
13545 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13547 if (reloc->howto == NULL)
13549 as_bad_where (fixp->fx_file, fixp->fx_line,
13550 _("Can not represent %s relocation in this object file format"),
13551 bfd_get_reloc_code_name (code));
13558 /* Relax a machine dependent frag. This returns the amount by which
13559 the current size of the frag should change. */
13562 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13564 if (RELAX_BRANCH_P (fragp->fr_subtype))
13566 offsetT old_var = fragp->fr_var;
13568 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13570 return fragp->fr_var - old_var;
13573 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13576 if (mips16_extended_frag (fragp, NULL, stretch))
13578 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13580 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13585 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13587 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13594 /* Convert a machine dependent frag. */
13597 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13602 if (RELAX_BRANCH_P (fragp->fr_subtype))
13605 unsigned long insn;
13609 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13611 if (target_big_endian)
13612 insn = bfd_getb32 (buf);
13614 insn = bfd_getl32 (buf);
13616 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13618 /* We generate a fixup instead of applying it right now
13619 because, if there are linker relaxations, we're going to
13620 need the relocations. */
13621 exp.X_op = O_symbol;
13622 exp.X_add_symbol = fragp->fr_symbol;
13623 exp.X_add_number = fragp->fr_offset;
13625 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13627 BFD_RELOC_16_PCREL_S2);
13628 fixp->fx_file = fragp->fr_file;
13629 fixp->fx_line = fragp->fr_line;
13631 md_number_to_chars (buf, insn, 4);
13638 as_warn_where (fragp->fr_file, fragp->fr_line,
13639 _("relaxed out-of-range branch into a jump"));
13641 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13644 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13646 /* Reverse the branch. */
13647 switch ((insn >> 28) & 0xf)
13650 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13651 have the condition reversed by tweaking a single
13652 bit, and their opcodes all have 0x4???????. */
13653 assert ((insn & 0xf1000000) == 0x41000000);
13654 insn ^= 0x00010000;
13658 /* bltz 0x04000000 bgez 0x04010000
13659 bltzal 0x04100000 bgezal 0x04110000 */
13660 assert ((insn & 0xfc0e0000) == 0x04000000);
13661 insn ^= 0x00010000;
13665 /* beq 0x10000000 bne 0x14000000
13666 blez 0x18000000 bgtz 0x1c000000 */
13667 insn ^= 0x04000000;
13675 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13677 /* Clear the and-link bit. */
13678 assert ((insn & 0xfc1c0000) == 0x04100000);
13680 /* bltzal 0x04100000 bgezal 0x04110000
13681 bltzall 0x04120000 bgezall 0x04130000 */
13682 insn &= ~0x00100000;
13685 /* Branch over the branch (if the branch was likely) or the
13686 full jump (not likely case). Compute the offset from the
13687 current instruction to branch to. */
13688 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13692 /* How many bytes in instructions we've already emitted? */
13693 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13694 /* How many bytes in instructions from here to the end? */
13695 i = fragp->fr_var - i;
13697 /* Convert to instruction count. */
13699 /* Branch counts from the next instruction. */
13702 /* Branch over the jump. */
13703 md_number_to_chars (buf, insn, 4);
13707 md_number_to_chars (buf, 0, 4);
13710 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13712 /* beql $0, $0, 2f */
13714 /* Compute the PC offset from the current instruction to
13715 the end of the variable frag. */
13716 /* How many bytes in instructions we've already emitted? */
13717 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13718 /* How many bytes in instructions from here to the end? */
13719 i = fragp->fr_var - i;
13720 /* Convert to instruction count. */
13722 /* Don't decrement i, because we want to branch over the
13726 md_number_to_chars (buf, insn, 4);
13729 md_number_to_chars (buf, 0, 4);
13734 if (mips_pic == NO_PIC)
13737 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13738 ? 0x0c000000 : 0x08000000);
13739 exp.X_op = O_symbol;
13740 exp.X_add_symbol = fragp->fr_symbol;
13741 exp.X_add_number = fragp->fr_offset;
13743 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13744 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13745 fixp->fx_file = fragp->fr_file;
13746 fixp->fx_line = fragp->fr_line;
13748 md_number_to_chars (buf, insn, 4);
13753 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13754 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13755 exp.X_op = O_symbol;
13756 exp.X_add_symbol = fragp->fr_symbol;
13757 exp.X_add_number = fragp->fr_offset;
13759 if (fragp->fr_offset)
13761 exp.X_add_symbol = make_expr_symbol (&exp);
13762 exp.X_add_number = 0;
13765 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13766 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13767 fixp->fx_file = fragp->fr_file;
13768 fixp->fx_line = fragp->fr_line;
13770 md_number_to_chars (buf, insn, 4);
13773 if (mips_opts.isa == ISA_MIPS1)
13776 md_number_to_chars (buf, 0, 4);
13780 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13781 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13783 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13784 4, &exp, 0, BFD_RELOC_LO16);
13785 fixp->fx_file = fragp->fr_file;
13786 fixp->fx_line = fragp->fr_line;
13788 md_number_to_chars (buf, insn, 4);
13792 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13797 md_number_to_chars (buf, insn, 4);
13802 assert (buf == (bfd_byte *)fragp->fr_literal
13803 + fragp->fr_fix + fragp->fr_var);
13805 fragp->fr_fix += fragp->fr_var;
13810 if (RELAX_MIPS16_P (fragp->fr_subtype))
13813 register const struct mips16_immed_operand *op;
13814 bfd_boolean small, ext;
13817 unsigned long insn;
13818 bfd_boolean use_extend;
13819 unsigned short extend;
13821 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13822 op = mips16_immed_operands;
13823 while (op->type != type)
13826 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13837 resolve_symbol_value (fragp->fr_symbol);
13838 val = S_GET_VALUE (fragp->fr_symbol);
13843 addr = fragp->fr_address + fragp->fr_fix;
13845 /* The rules for the base address of a PC relative reloc are
13846 complicated; see mips16_extended_frag. */
13847 if (type == 'p' || type == 'q')
13852 /* Ignore the low bit in the target, since it will be
13853 set for a text label. */
13854 if ((val & 1) != 0)
13857 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13859 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13862 addr &= ~ (addressT) ((1 << op->shift) - 1);
13865 /* Make sure the section winds up with the alignment we have
13868 record_alignment (asec, op->shift);
13872 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13873 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13874 as_warn_where (fragp->fr_file, fragp->fr_line,
13875 _("extended instruction in delay slot"));
13877 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13879 if (target_big_endian)
13880 insn = bfd_getb16 (buf);
13882 insn = bfd_getl16 (buf);
13884 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13885 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13886 small, ext, &insn, &use_extend, &extend);
13890 md_number_to_chars (buf, 0xf000 | extend, 2);
13891 fragp->fr_fix += 2;
13895 md_number_to_chars (buf, insn, 2);
13896 fragp->fr_fix += 2;
13901 if (fragp->fr_opcode == NULL)
13904 old = RELAX_OLD (fragp->fr_subtype);
13905 new = RELAX_NEW (fragp->fr_subtype);
13906 fixptr = fragp->fr_literal + fragp->fr_fix;
13909 memmove (fixptr - old, fixptr, new);
13911 fragp->fr_fix += new - old;
13917 /* This function is called after the relocs have been generated.
13918 We've been storing mips16 text labels as odd. Here we convert them
13919 back to even for the convenience of the debugger. */
13922 mips_frob_file_after_relocs (void)
13925 unsigned int count, i;
13927 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13930 syms = bfd_get_outsymbols (stdoutput);
13931 count = bfd_get_symcount (stdoutput);
13932 for (i = 0; i < count; i++, syms++)
13934 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13935 && ((*syms)->value & 1) != 0)
13937 (*syms)->value &= ~1;
13938 /* If the symbol has an odd size, it was probably computed
13939 incorrectly, so adjust that as well. */
13940 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13941 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13948 /* This function is called whenever a label is defined. It is used
13949 when handling branch delays; if a branch has a label, we assume we
13950 can not move it. */
13953 mips_define_label (symbolS *sym)
13955 struct insn_label_list *l;
13957 if (free_insn_labels == NULL)
13958 l = (struct insn_label_list *) xmalloc (sizeof *l);
13961 l = free_insn_labels;
13962 free_insn_labels = l->next;
13966 l->next = insn_labels;
13970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13972 /* Some special processing for a MIPS ELF file. */
13975 mips_elf_final_processing (void)
13977 /* Write out the register information. */
13978 if (mips_abi != N64_ABI)
13982 s.ri_gprmask = mips_gprmask;
13983 s.ri_cprmask[0] = mips_cprmask[0];
13984 s.ri_cprmask[1] = mips_cprmask[1];
13985 s.ri_cprmask[2] = mips_cprmask[2];
13986 s.ri_cprmask[3] = mips_cprmask[3];
13987 /* The gp_value field is set by the MIPS ELF backend. */
13989 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13990 ((Elf32_External_RegInfo *)
13991 mips_regmask_frag));
13995 Elf64_Internal_RegInfo s;
13997 s.ri_gprmask = mips_gprmask;
13999 s.ri_cprmask[0] = mips_cprmask[0];
14000 s.ri_cprmask[1] = mips_cprmask[1];
14001 s.ri_cprmask[2] = mips_cprmask[2];
14002 s.ri_cprmask[3] = mips_cprmask[3];
14003 /* The gp_value field is set by the MIPS ELF backend. */
14005 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14006 ((Elf64_External_RegInfo *)
14007 mips_regmask_frag));
14010 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14011 sort of BFD interface for this. */
14012 if (mips_any_noreorder)
14013 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14014 if (mips_pic != NO_PIC)
14016 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14017 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14020 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14022 /* Set MIPS ELF flags for ASEs. */
14023 if (file_ase_mips16)
14024 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14025 #if 0 /* XXX FIXME */
14026 if (file_ase_mips3d)
14027 elf_elfheader (stdoutput)->e_flags |= ???;
14030 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14032 /* Set the MIPS ELF ABI flags. */
14033 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14034 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14035 else if (mips_abi == O64_ABI)
14036 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14037 else if (mips_abi == EABI_ABI)
14039 if (!file_mips_gp32)
14040 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14042 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14044 else if (mips_abi == N32_ABI)
14045 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14047 /* Nothing to do for N64_ABI. */
14049 if (mips_32bitmode)
14050 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14053 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14055 typedef struct proc {
14057 unsigned long reg_mask;
14058 unsigned long reg_offset;
14059 unsigned long fpreg_mask;
14060 unsigned long fpreg_offset;
14061 unsigned long frame_offset;
14062 unsigned long frame_reg;
14063 unsigned long pc_reg;
14066 static procS cur_proc;
14067 static procS *cur_proc_ptr;
14068 static int numprocs;
14070 /* Fill in an rs_align_code fragment. */
14073 mips_handle_align (fragS *fragp)
14075 if (fragp->fr_type != rs_align_code)
14078 if (mips_opts.mips16)
14080 static const unsigned char be_nop[] = { 0x65, 0x00 };
14081 static const unsigned char le_nop[] = { 0x00, 0x65 };
14086 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14087 p = fragp->fr_literal + fragp->fr_fix;
14095 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14099 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14103 md_obj_begin (void)
14110 /* check for premature end, nesting errors, etc */
14112 as_warn (_("missing .end at end of assembly"));
14121 if (*input_line_pointer == '-')
14123 ++input_line_pointer;
14126 if (!ISDIGIT (*input_line_pointer))
14127 as_bad (_("expected simple number"));
14128 if (input_line_pointer[0] == '0')
14130 if (input_line_pointer[1] == 'x')
14132 input_line_pointer += 2;
14133 while (ISXDIGIT (*input_line_pointer))
14136 val |= hex_value (*input_line_pointer++);
14138 return negative ? -val : val;
14142 ++input_line_pointer;
14143 while (ISDIGIT (*input_line_pointer))
14146 val |= *input_line_pointer++ - '0';
14148 return negative ? -val : val;
14151 if (!ISDIGIT (*input_line_pointer))
14153 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14154 *input_line_pointer, *input_line_pointer);
14155 as_warn (_("invalid number"));
14158 while (ISDIGIT (*input_line_pointer))
14161 val += *input_line_pointer++ - '0';
14163 return negative ? -val : val;
14166 /* The .file directive; just like the usual .file directive, but there
14167 is an initial number which is the ECOFF file index. In the non-ECOFF
14168 case .file implies DWARF-2. */
14171 s_mips_file (int x ATTRIBUTE_UNUSED)
14173 static int first_file_directive = 0;
14175 if (ECOFF_DEBUGGING)
14184 filename = dwarf2_directive_file (0);
14186 /* Versions of GCC up to 3.1 start files with a ".file"
14187 directive even for stabs output. Make sure that this
14188 ".file" is handled. Note that you need a version of GCC
14189 after 3.1 in order to support DWARF-2 on MIPS. */
14190 if (filename != NULL && ! first_file_directive)
14192 (void) new_logical_line (filename, -1);
14193 s_app_file_string (filename);
14195 first_file_directive = 1;
14199 /* The .loc directive, implying DWARF-2. */
14202 s_mips_loc (int x ATTRIBUTE_UNUSED)
14204 if (!ECOFF_DEBUGGING)
14205 dwarf2_directive_loc (0);
14208 /* The .end directive. */
14211 s_mips_end (int x ATTRIBUTE_UNUSED)
14215 /* Following functions need their own .frame and .cprestore directives. */
14216 mips_frame_reg_valid = 0;
14217 mips_cprestore_valid = 0;
14219 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14222 demand_empty_rest_of_line ();
14227 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14228 as_warn (_(".end not in text section"));
14232 as_warn (_(".end directive without a preceding .ent directive."));
14233 demand_empty_rest_of_line ();
14239 assert (S_GET_NAME (p));
14240 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14241 as_warn (_(".end symbol does not match .ent symbol."));
14243 if (debug_type == DEBUG_STABS)
14244 stabs_generate_asm_endfunc (S_GET_NAME (p),
14248 as_warn (_(".end directive missing or unknown symbol"));
14251 /* Generate a .pdr section. */
14252 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14255 segT saved_seg = now_seg;
14256 subsegT saved_subseg = now_subseg;
14261 dot = frag_now_fix ();
14263 #ifdef md_flush_pending_output
14264 md_flush_pending_output ();
14268 subseg_set (pdr_seg, 0);
14270 /* Write the symbol. */
14271 exp.X_op = O_symbol;
14272 exp.X_add_symbol = p;
14273 exp.X_add_number = 0;
14274 emit_expr (&exp, 4);
14276 fragp = frag_more (7 * 4);
14278 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14279 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14280 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14281 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14282 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14283 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14284 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14286 subseg_set (saved_seg, saved_subseg);
14288 #endif /* OBJ_ELF */
14290 cur_proc_ptr = NULL;
14293 /* The .aent and .ent directives. */
14296 s_mips_ent (int aent)
14300 symbolP = get_symbol ();
14301 if (*input_line_pointer == ',')
14302 ++input_line_pointer;
14303 SKIP_WHITESPACE ();
14304 if (ISDIGIT (*input_line_pointer)
14305 || *input_line_pointer == '-')
14308 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14309 as_warn (_(".ent or .aent not in text section."));
14311 if (!aent && cur_proc_ptr)
14312 as_warn (_("missing .end"));
14316 /* This function needs its own .frame and .cprestore directives. */
14317 mips_frame_reg_valid = 0;
14318 mips_cprestore_valid = 0;
14320 cur_proc_ptr = &cur_proc;
14321 memset (cur_proc_ptr, '\0', sizeof (procS));
14323 cur_proc_ptr->isym = symbolP;
14325 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14329 if (debug_type == DEBUG_STABS)
14330 stabs_generate_asm_func (S_GET_NAME (symbolP),
14331 S_GET_NAME (symbolP));
14334 demand_empty_rest_of_line ();
14337 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14338 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14339 s_mips_frame is used so that we can set the PDR information correctly.
14340 We can't use the ecoff routines because they make reference to the ecoff
14341 symbol table (in the mdebug section). */
14344 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14347 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14351 if (cur_proc_ptr == (procS *) NULL)
14353 as_warn (_(".frame outside of .ent"));
14354 demand_empty_rest_of_line ();
14358 cur_proc_ptr->frame_reg = tc_get_register (1);
14360 SKIP_WHITESPACE ();
14361 if (*input_line_pointer++ != ','
14362 || get_absolute_expression_and_terminator (&val) != ',')
14364 as_warn (_("Bad .frame directive"));
14365 --input_line_pointer;
14366 demand_empty_rest_of_line ();
14370 cur_proc_ptr->frame_offset = val;
14371 cur_proc_ptr->pc_reg = tc_get_register (0);
14373 demand_empty_rest_of_line ();
14376 #endif /* OBJ_ELF */
14380 /* The .fmask and .mask directives. If the mdebug section is present
14381 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14382 embedded targets, s_mips_mask is used so that we can set the PDR
14383 information correctly. We can't use the ecoff routines because they
14384 make reference to the ecoff symbol table (in the mdebug section). */
14387 s_mips_mask (int reg_type)
14390 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14394 if (cur_proc_ptr == (procS *) NULL)
14396 as_warn (_(".mask/.fmask outside of .ent"));
14397 demand_empty_rest_of_line ();
14401 if (get_absolute_expression_and_terminator (&mask) != ',')
14403 as_warn (_("Bad .mask/.fmask directive"));
14404 --input_line_pointer;
14405 demand_empty_rest_of_line ();
14409 off = get_absolute_expression ();
14411 if (reg_type == 'F')
14413 cur_proc_ptr->fpreg_mask = mask;
14414 cur_proc_ptr->fpreg_offset = off;
14418 cur_proc_ptr->reg_mask = mask;
14419 cur_proc_ptr->reg_offset = off;
14422 demand_empty_rest_of_line ();
14425 #endif /* OBJ_ELF */
14426 s_ignore (reg_type);
14429 /* The .loc directive. */
14439 assert (now_seg == text_section);
14441 lineno = get_number ();
14442 addroff = frag_now_fix ();
14444 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14445 S_SET_TYPE (symbolP, N_SLINE);
14446 S_SET_OTHER (symbolP, 0);
14447 S_SET_DESC (symbolP, lineno);
14448 symbolP->sy_segment = now_seg;
14452 /* A table describing all the processors gas knows about. Names are
14453 matched in the order listed.
14455 To ease comparison, please keep this table in the same order as
14456 gcc's mips_cpu_info_table[]. */
14457 static const struct mips_cpu_info mips_cpu_info_table[] =
14459 /* Entries for generic ISAs */
14460 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14461 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14462 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14463 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14464 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14465 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14466 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14467 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14468 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14471 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14472 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14473 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14476 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14479 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14480 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14481 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14482 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14483 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14484 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14485 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14486 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14487 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14488 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14489 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14490 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14493 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14494 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14495 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14496 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14497 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14498 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14499 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14500 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14501 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14502 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14503 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14504 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14505 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14508 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14509 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14510 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14513 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14514 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14516 /* Broadcom SB-1 CPU core */
14517 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14524 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14525 with a final "000" replaced by "k". Ignore case.
14527 Note: this function is shared between GCC and GAS. */
14530 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14532 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14533 given++, canonical++;
14535 return ((*given == 0 && *canonical == 0)
14536 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14540 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14541 CPU name. We've traditionally allowed a lot of variation here.
14543 Note: this function is shared between GCC and GAS. */
14546 mips_matching_cpu_name_p (const char *canonical, const char *given)
14548 /* First see if the name matches exactly, or with a final "000"
14549 turned into "k". */
14550 if (mips_strict_matching_cpu_name_p (canonical, given))
14553 /* If not, try comparing based on numerical designation alone.
14554 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14555 if (TOLOWER (*given) == 'r')
14557 if (!ISDIGIT (*given))
14560 /* Skip over some well-known prefixes in the canonical name,
14561 hoping to find a number there too. */
14562 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14564 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14566 else if (TOLOWER (canonical[0]) == 'r')
14569 return mips_strict_matching_cpu_name_p (canonical, given);
14573 /* Parse an option that takes the name of a processor as its argument.
14574 OPTION is the name of the option and CPU_STRING is the argument.
14575 Return the corresponding processor enumeration if the CPU_STRING is
14576 recognized, otherwise report an error and return null.
14578 A similar function exists in GCC. */
14580 static const struct mips_cpu_info *
14581 mips_parse_cpu (const char *option, const char *cpu_string)
14583 const struct mips_cpu_info *p;
14585 /* 'from-abi' selects the most compatible architecture for the given
14586 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14587 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14588 version. Look first at the -mgp options, if given, otherwise base
14589 the choice on MIPS_DEFAULT_64BIT.
14591 Treat NO_ABI like the EABIs. One reason to do this is that the
14592 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14593 architecture. This code picks MIPS I for 'mips' and MIPS III for
14594 'mips64', just as we did in the days before 'from-abi'. */
14595 if (strcasecmp (cpu_string, "from-abi") == 0)
14597 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14598 return mips_cpu_info_from_isa (ISA_MIPS1);
14600 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14601 return mips_cpu_info_from_isa (ISA_MIPS3);
14603 if (file_mips_gp32 >= 0)
14604 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14606 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14611 /* 'default' has traditionally been a no-op. Probably not very useful. */
14612 if (strcasecmp (cpu_string, "default") == 0)
14615 for (p = mips_cpu_info_table; p->name != 0; p++)
14616 if (mips_matching_cpu_name_p (p->name, cpu_string))
14619 as_bad ("Bad value (%s) for %s", cpu_string, option);
14623 /* Return the canonical processor information for ISA (a member of the
14624 ISA_MIPS* enumeration). */
14626 static const struct mips_cpu_info *
14627 mips_cpu_info_from_isa (int isa)
14631 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14632 if (mips_cpu_info_table[i].is_isa
14633 && isa == mips_cpu_info_table[i].isa)
14634 return (&mips_cpu_info_table[i]);
14639 static const struct mips_cpu_info *
14640 mips_cpu_info_from_arch (int arch)
14644 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14645 if (arch == mips_cpu_info_table[i].cpu)
14646 return (&mips_cpu_info_table[i]);
14652 show (FILE *stream, const char *string, int *col_p, int *first_p)
14656 fprintf (stream, "%24s", "");
14661 fprintf (stream, ", ");
14665 if (*col_p + strlen (string) > 72)
14667 fprintf (stream, "\n%24s", "");
14671 fprintf (stream, "%s", string);
14672 *col_p += strlen (string);
14678 md_show_usage (FILE *stream)
14683 fprintf (stream, _("\
14685 -membedded-pic generate embedded position independent code\n\
14686 -EB generate big endian output\n\
14687 -EL generate little endian output\n\
14688 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14689 -G NUM allow referencing objects up to NUM bytes\n\
14690 implicitly with the gp register [default 8]\n"));
14691 fprintf (stream, _("\
14692 -mips1 generate MIPS ISA I instructions\n\
14693 -mips2 generate MIPS ISA II instructions\n\
14694 -mips3 generate MIPS ISA III instructions\n\
14695 -mips4 generate MIPS ISA IV instructions\n\
14696 -mips5 generate MIPS ISA V instructions\n\
14697 -mips32 generate MIPS32 ISA instructions\n\
14698 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14699 -mips64 generate MIPS64 ISA instructions\n\
14700 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14701 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14705 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14706 show (stream, mips_cpu_info_table[i].name, &column, &first);
14707 show (stream, "from-abi", &column, &first);
14708 fputc ('\n', stream);
14710 fprintf (stream, _("\
14711 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14712 -no-mCPU don't generate code specific to CPU.\n\
14713 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14717 show (stream, "3900", &column, &first);
14718 show (stream, "4010", &column, &first);
14719 show (stream, "4100", &column, &first);
14720 show (stream, "4650", &column, &first);
14721 fputc ('\n', stream);
14723 fprintf (stream, _("\
14724 -mips16 generate mips16 instructions\n\
14725 -no-mips16 do not generate mips16 instructions\n"));
14726 fprintf (stream, _("\
14727 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14728 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14729 -O0 remove unneeded NOPs, do not swap branches\n\
14730 -O remove unneeded NOPs and swap branches\n\
14731 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14732 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14733 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14735 fprintf (stream, _("\
14736 -KPIC, -call_shared generate SVR4 position independent code\n\
14737 -non_shared do not generate position independent code\n\
14738 -xgot assume a 32 bit GOT\n\
14739 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14740 -mabi=ABI create ABI conformant object file for:\n"));
14744 show (stream, "32", &column, &first);
14745 show (stream, "o64", &column, &first);
14746 show (stream, "n32", &column, &first);
14747 show (stream, "64", &column, &first);
14748 show (stream, "eabi", &column, &first);
14750 fputc ('\n', stream);
14752 fprintf (stream, _("\
14753 -32 create o32 ABI object file (default)\n\
14754 -n32 create n32 ABI object file\n\
14755 -64 create 64 ABI object file\n"));
14760 mips_dwarf2_format (void)
14762 if (mips_abi == N64_ABI)
14765 return dwarf2_format_64bit_irix;
14767 return dwarf2_format_64bit;
14771 return dwarf2_format_32bit;