1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error;
635 static int auto_align = 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset = -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset = -1;
647 static int mips_cpreturn_register = -1;
648 static int mips_gp_register = GP;
649 static int mips_gprel_offset = 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid = 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg = SP;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid = 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize = 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug = 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history[1 + MAX_NOPS];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 6
694 struct mips_operand_array {
695 const struct mips_operand *operand[MAX_OPERANDS];
697 static struct mips_operand_array *mips_operands;
698 static struct mips_operand_array *mips16_operands;
699 static struct mips_operand_array *micromips_operands;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn;
703 static struct mips_cl_insn mips16_nop_insn;
704 static struct mips_cl_insn micromips_nop16_insn;
705 static struct mips_cl_insn micromips_nop32_insn;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS *prev_nop_frag;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup *next;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup *mips_hi_fixup_list;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS *prev_reloc_op_frag;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro = FALSE;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1190 static void append_insn
1191 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1192 bfd_boolean expansionp);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS *, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS *, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS *, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn *ip, char *str);
1201 static void mips16_macro (struct mips_cl_insn * ip);
1202 static void mips_ip (char *str, struct mips_cl_insn * ip);
1203 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS *, bfd_reloc_code_real_type *, char *);
1209 static void my_getExpression (expressionS *, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean pic_need_relax (symbolS *, asection *);
1246 static int relaxed_branch_length (fragS *, asection *, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name; /* CPU or ISA name. */
1256 int flags; /* MIPS_CPU_* flags. */
1257 int ase; /* Set of ASEs implemented by the CPU. */
1258 int isa; /* ISA level. */
1259 int cpu; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts = "O::g::G:";
1273 OPTION_MARCH = OPTION_MD_BASE,
1297 OPTION_NO_SMARTMIPS,
1303 OPTION_NO_MICROMIPS,
1306 OPTION_COMPAT_ARCH_BASE,
1315 OPTION_M7000_HILO_FIX,
1316 OPTION_MNO_7000_HILO_FIX,
1319 OPTION_FIX_LOONGSON2F_JUMP,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP,
1321 OPTION_FIX_LOONGSON2F_NOP,
1322 OPTION_NO_FIX_LOONGSON2F_NOP,
1324 OPTION_NO_FIX_VR4120,
1326 OPTION_NO_FIX_VR4130,
1327 OPTION_FIX_CN63XXP1,
1328 OPTION_NO_FIX_CN63XXP1,
1335 OPTION_CONSTRUCT_FLOATS,
1336 OPTION_NO_CONSTRUCT_FLOATS,
1339 OPTION_RELAX_BRANCH,
1340 OPTION_NO_RELAX_BRANCH,
1349 OPTION_SINGLE_FLOAT,
1350 OPTION_DOUBLE_FLOAT,
1363 OPTION_MVXWORKS_PIC,
1368 struct option md_longopts[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument, NULL, OPTION_MARCH},
1372 {"mtune", required_argument, NULL, OPTION_MTUNE},
1373 {"mips0", no_argument, NULL, OPTION_MIPS1},
1374 {"mips1", no_argument, NULL, OPTION_MIPS1},
1375 {"mips2", no_argument, NULL, OPTION_MIPS2},
1376 {"mips3", no_argument, NULL, OPTION_MIPS3},
1377 {"mips4", no_argument, NULL, OPTION_MIPS4},
1378 {"mips5", no_argument, NULL, OPTION_MIPS5},
1379 {"mips32", no_argument, NULL, OPTION_MIPS32},
1380 {"mips64", no_argument, NULL, OPTION_MIPS64},
1381 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1382 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument, NULL, OPTION_MIPS16},
1386 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1387 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1388 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1389 {"mdmx", no_argument, NULL, OPTION_MDMX},
1390 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1391 {"mdsp", no_argument, NULL, OPTION_DSP},
1392 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1393 {"mmt", no_argument, NULL, OPTION_MT},
1394 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1395 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1396 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1397 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1398 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1399 {"meva", no_argument, NULL, OPTION_EVA},
1400 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1401 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1402 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1403 {"mmcu", no_argument, NULL, OPTION_MCU},
1404 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1405 {"mvirt", no_argument, NULL, OPTION_VIRT},
1406 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument, NULL, OPTION_M4650},
1410 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1411 {"m4010", no_argument, NULL, OPTION_M4010},
1412 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1413 {"m4100", no_argument, NULL, OPTION_M4100},
1414 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1415 {"m3900", no_argument, NULL, OPTION_M3900},
1416 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1420 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1421 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1422 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1423 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1424 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1425 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1426 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1427 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1428 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1429 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1430 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1431 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1432 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1433 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument, NULL, OPTION_TRAP},
1437 {"no-break", no_argument, NULL, OPTION_TRAP},
1438 {"break", no_argument, NULL, OPTION_BREAK},
1439 {"no-trap", no_argument, NULL, OPTION_BREAK},
1440 {"EB", no_argument, NULL, OPTION_EB},
1441 {"EL", no_argument, NULL, OPTION_EL},
1442 {"mfp32", no_argument, NULL, OPTION_FP32},
1443 {"mgp32", no_argument, NULL, OPTION_GP32},
1444 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1445 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1446 {"mfp64", no_argument, NULL, OPTION_FP64},
1447 {"mgp64", no_argument, NULL, OPTION_GP64},
1448 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1449 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1450 {"minsn32", no_argument, NULL, OPTION_INSN32},
1451 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1452 {"mshared", no_argument, NULL, OPTION_MSHARED},
1453 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1454 {"msym32", no_argument, NULL, OPTION_MSYM32},
1455 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1456 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1457 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1458 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1459 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument, NULL, OPTION_32},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1468 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1469 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1470 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1471 {"xgot", no_argument, NULL, OPTION_XGOT},
1472 {"mabi", required_argument, NULL, OPTION_MABI},
1473 {"n32", no_argument, NULL, OPTION_N32},
1474 {"64", no_argument, NULL, OPTION_64},
1475 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1476 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1477 {"mpdr", no_argument, NULL, OPTION_PDR},
1478 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1479 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1480 {"mnan", required_argument, NULL, OPTION_NAN},
1482 {NULL, no_argument, NULL, 0}
1484 size_t md_longopts_size = sizeof (md_longopts);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev;
1512 int micromips64_rev;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases[] = {
1517 { "dsp", ASE_DSP, ASE_DSP64,
1518 OPTION_DSP, OPTION_NO_DSP,
1521 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1522 OPTION_DSPR2, OPTION_NO_DSPR2,
1525 { "eva", ASE_EVA, 0,
1526 OPTION_EVA, OPTION_NO_EVA,
1529 { "mcu", ASE_MCU, 0,
1530 OPTION_MCU, OPTION_NO_MCU,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX, 0,
1535 OPTION_MDMX, OPTION_NO_MDMX,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D, 0,
1540 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1544 OPTION_MT, OPTION_NO_MT,
1547 { "smartmips", ASE_SMARTMIPS, 0,
1548 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1551 { "virt", ASE_VIRT, ASE_VIRT64,
1552 OPTION_VIRT, OPTION_NO_VIRT,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option, 0},
1585 {"set", s_mipsset, 0},
1586 {"rdata", s_change_sec, 'r'},
1587 {"sdata", s_change_sec, 's'},
1588 {"livereg", s_ignore, 0},
1589 {"abicalls", s_abicalls, 0},
1590 {"cpload", s_cpload, 0},
1591 {"cpsetup", s_cpsetup, 0},
1592 {"cplocal", s_cplocal, 0},
1593 {"cprestore", s_cprestore, 0},
1594 {"cpreturn", s_cpreturn, 0},
1595 {"dtprelword", s_dtprelword, 0},
1596 {"dtpreldword", s_dtpreldword, 0},
1597 {"tprelword", s_tprelword, 0},
1598 {"tpreldword", s_tpreldword, 0},
1599 {"gpvalue", s_gpvalue, 0},
1600 {"gpword", s_gpword, 0},
1601 {"gpdword", s_gpdword, 0},
1602 {"ehword", s_ehword, 0},
1603 {"cpadd", s_cpadd, 0},
1604 {"insn", s_insn, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer, 8 + 1},
1610 {"bss", s_change_sec, 'b'},
1612 {"half", s_cons, 1},
1613 {"dword", s_cons, 3},
1614 {"weakext", s_mips_weakext, 0},
1615 {"origin", s_org, 0},
1616 {"repeat", s_rept, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align, 0},
1624 {"byte", s_cons, 0},
1625 {"data", s_change_sec, 'd'},
1626 {"double", s_float_cons, 'd'},
1627 {"float", s_float_cons, 'f'},
1628 {"globl", s_mips_globl, 0},
1629 {"global", s_mips_globl, 0},
1630 {"hword", s_cons, 1},
1632 {"long", s_cons, 2},
1633 {"octa", s_cons, 4},
1634 {"quad", s_cons, 3},
1635 {"section", s_change_section, 0},
1636 {"short", s_cons, 1},
1637 {"single", s_float_cons, 'f'},
1638 {"stabd", s_mips_stab, 'd'},
1639 {"stabn", s_mips_stab, 'n'},
1640 {"stabs", s_mips_stab, 's'},
1641 {"text", s_change_sec, 't'},
1642 {"word", s_cons, 2},
1644 { "extern", ecoff_directive_extern, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent, 1},
1654 {"bgnb", s_ignore, 0},
1655 {"end", s_mips_end, 0},
1656 {"endb", s_ignore, 0},
1657 {"ent", s_mips_ent, 0},
1658 {"file", s_mips_file, 0},
1659 {"fmask", s_mips_mask, 'F'},
1660 {"frame", s_mips_frame, 0},
1661 {"loc", s_mips_loc, 0},
1662 {"mask", s_mips_mask, 'R'},
1663 {"verstamp", s_ignore, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS *);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table);
1682 if (! ECOFF_DEBUGGING)
1683 pop_insert (mips_nonecoff_pseudo_table);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list *next;
1694 static struct insn_label_list *free_insn_labels;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list **pl;
1705 segment_info_type *si;
1709 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1712 si = seg_info (now_seg);
1713 *pl = si->label_list;
1714 si->label_list = NULL;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr;
1733 static expressionS imm2_expr;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr;
1741 static bfd_reloc_code_real_type offset_reloc[3]
1742 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR)
1775 case bfd_target_elf_flavour:
1777 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts.micromips)
1812 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags)
1825 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1826 if (flags & mips_ase_groups[i])
1827 flags |= mips_ase_groups[i];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase *ase)
1839 static unsigned int warned_isa;
1840 static unsigned int warned_fp32;
1842 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1843 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1845 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1846 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1847 && (warned_isa & ase->flags) != ase->flags)
1849 warned_isa |= ase->flags;
1850 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1851 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size, base, ase->name);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase->name, base, size, min_rev);
1859 if ((ase->flags & FP64_ASES)
1861 && (warned_fp32 & ase->flags) != ase->flags)
1863 warned_fp32 |= ase->flags;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i, mask;
1876 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1878 mask = mips_ase_mask (mips_ases[i].flags);
1879 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1880 mips_check_isa_supports_ase (&mips_ases[i]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1892 mask = mips_ase_mask (ase->flags);
1893 mips_opts.ase &= ~mask;
1895 mips_opts.ase |= ase->flags;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase *
1902 mips_lookup_ase (const char *name)
1906 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1907 if (strcmp (name, mips_ases[i].name) == 0)
1908 return &mips_ases[i];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode *mo)
1921 return (mo->mask >> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode)
1929 return (opcode >> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn *insn)
1937 if (mips_opts.micromips)
1938 return micromips_insn_length (insn->insn_mo);
1939 else if (mips_opts.mips16)
1940 return mips16_opcode_length (insn->insn_opcode);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1953 insn->insn_opcode = mo->match;
1956 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1957 insn->fixp[i] = NULL;
1958 insn->fixed_p = (mips_opts.noreorder > 0);
1959 insn->noreorder_p = (mips_opts.noreorder > 0);
1960 insn->mips16_absolute_jump_p = 0;
1961 insn->complete_p = 0;
1962 insn->cleared_p = 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array *
1968 insn_operands (const struct mips_cl_insn *insn)
1970 if (insn->insn_mo >= &mips_opcodes[0]
1971 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
1972 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
1974 if (insn->insn_mo >= &mips16_opcodes[0]
1975 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
1976 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
1978 if (insn->insn_mo >= µmips_opcodes[0]
1979 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
1980 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand *
1988 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
1990 const struct mips_operand_array *operands;
1992 operands = insn_operands (insn);
1993 if (opno >= MAX_OPERANDS || !operands->operand[opno])
1995 return operands->operand[opno];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn *insn,
2002 const struct mips_operand *operand, unsigned int uval)
2004 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn *insn,
2011 const struct mips_operand *operand)
2013 return mips_extract_operand (operand, insn->insn_opcode);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type *si;
2023 si = seg_info (now_seg);
2024 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2025 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2026 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2027 si->tc_segment_info_data.micromips = mips_opts.micromips;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf)
2035 if (target_big_endian)
2036 return bfd_getb32 ((bfd_byte *) buf);
2038 return bfd_getl32 ((bfd_byte *) buf);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf, unsigned int insn)
2047 md_number_to_chars (buf, insn, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf, unsigned int length)
2061 for (i = 0; i < length; i += 2)
2064 if (target_big_endian)
2065 insn |= bfd_getb16 ((char *) buf);
2067 insn |= bfd_getl16 ((char *) buf);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2081 for (i = 0; i < length; i += 2)
2082 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2083 return buf + length;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn *insn)
2091 char *f = insn->frag->fr_literal + insn->where;
2092 if (HAVE_CODE_COMPRESSION)
2093 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2095 write_insn (f, insn->insn_opcode);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2108 insn->where = where;
2109 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2110 if (insn->fixp[i] != NULL)
2112 insn->fixp[i]->fx_frag = frag;
2113 insn->fixp[i]->fx_where = where;
2115 install_insn (insn);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn *insn)
2123 char *f = frag_more (insn_length (insn));
2124 move_insn (insn, frag_now, f - frag_now->fr_literal);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2132 relax_substateT subtype, symbolS *symbol, offsetT offset)
2134 frag_grow (max_chars);
2135 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2137 frag_var (rs_machine_dependent, max_chars, var,
2138 subtype, symbol, offset, NULL);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first, unsigned int n,
2146 const struct mips_cl_insn *insn)
2148 if (mips_relax.sequence != 2)
2152 for (i = ARRAY_SIZE (history); i-- > first;)
2154 history[i] = history[i - n];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC, DIV);
2172 CONFLICT (DMACC, DIV);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT, DMULT);
2176 CONFLICT (DMULT, DMACC);
2177 CONFLICT (DMACC, DMULT);
2178 CONFLICT (DMACC, DMACC);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC, MTHILO);
2182 CONFLICT (DMACC, MTHILO);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC, MULT);
2188 CONFLICT (MACC, DMULT);
2189 CONFLICT (DMACC, MULT);
2190 CONFLICT (DMACC, DMULT);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT, MACC);
2197 CONFLICT (DMULT, DMACC);
2198 CONFLICT (DIV, MACC);
2199 CONFLICT (DIV, DMACC);
2209 #define RNUM_MASK 0x00000ff
2210 #define RTYPE_MASK 0x0efff00
2211 #define RTYPE_NUM 0x0000100
2212 #define RTYPE_FPU 0x0000200
2213 #define RTYPE_FCC 0x0000400
2214 #define RTYPE_VEC 0x0000800
2215 #define RTYPE_GP 0x0001000
2216 #define RTYPE_CP0 0x0002000
2217 #define RTYPE_PC 0x0004000
2218 #define RTYPE_ACC 0x0008000
2219 #define RTYPE_CCC 0x0010000
2220 #define RTYPE_VI 0x0020000
2221 #define RTYPE_VF 0x0040000
2222 #define RTYPE_R5900_I 0x0080000
2223 #define RTYPE_R5900_Q 0x0100000
2224 #define RTYPE_R5900_R 0x0200000
2225 #define RTYPE_R5900_ACC 0x0400000
2226 #define RWARN 0x8000000
2228 #define GENERIC_REGISTER_NUMBERS \
2229 {"$0", RTYPE_NUM | 0}, \
2230 {"$1", RTYPE_NUM | 1}, \
2231 {"$2", RTYPE_NUM | 2}, \
2232 {"$3", RTYPE_NUM | 3}, \
2233 {"$4", RTYPE_NUM | 4}, \
2234 {"$5", RTYPE_NUM | 5}, \
2235 {"$6", RTYPE_NUM | 6}, \
2236 {"$7", RTYPE_NUM | 7}, \
2237 {"$8", RTYPE_NUM | 8}, \
2238 {"$9", RTYPE_NUM | 9}, \
2239 {"$10", RTYPE_NUM | 10}, \
2240 {"$11", RTYPE_NUM | 11}, \
2241 {"$12", RTYPE_NUM | 12}, \
2242 {"$13", RTYPE_NUM | 13}, \
2243 {"$14", RTYPE_NUM | 14}, \
2244 {"$15", RTYPE_NUM | 15}, \
2245 {"$16", RTYPE_NUM | 16}, \
2246 {"$17", RTYPE_NUM | 17}, \
2247 {"$18", RTYPE_NUM | 18}, \
2248 {"$19", RTYPE_NUM | 19}, \
2249 {"$20", RTYPE_NUM | 20}, \
2250 {"$21", RTYPE_NUM | 21}, \
2251 {"$22", RTYPE_NUM | 22}, \
2252 {"$23", RTYPE_NUM | 23}, \
2253 {"$24", RTYPE_NUM | 24}, \
2254 {"$25", RTYPE_NUM | 25}, \
2255 {"$26", RTYPE_NUM | 26}, \
2256 {"$27", RTYPE_NUM | 27}, \
2257 {"$28", RTYPE_NUM | 28}, \
2258 {"$29", RTYPE_NUM | 29}, \
2259 {"$30", RTYPE_NUM | 30}, \
2260 {"$31", RTYPE_NUM | 31}
2262 #define FPU_REGISTER_NAMES \
2263 {"$f0", RTYPE_FPU | 0}, \
2264 {"$f1", RTYPE_FPU | 1}, \
2265 {"$f2", RTYPE_FPU | 2}, \
2266 {"$f3", RTYPE_FPU | 3}, \
2267 {"$f4", RTYPE_FPU | 4}, \
2268 {"$f5", RTYPE_FPU | 5}, \
2269 {"$f6", RTYPE_FPU | 6}, \
2270 {"$f7", RTYPE_FPU | 7}, \
2271 {"$f8", RTYPE_FPU | 8}, \
2272 {"$f9", RTYPE_FPU | 9}, \
2273 {"$f10", RTYPE_FPU | 10}, \
2274 {"$f11", RTYPE_FPU | 11}, \
2275 {"$f12", RTYPE_FPU | 12}, \
2276 {"$f13", RTYPE_FPU | 13}, \
2277 {"$f14", RTYPE_FPU | 14}, \
2278 {"$f15", RTYPE_FPU | 15}, \
2279 {"$f16", RTYPE_FPU | 16}, \
2280 {"$f17", RTYPE_FPU | 17}, \
2281 {"$f18", RTYPE_FPU | 18}, \
2282 {"$f19", RTYPE_FPU | 19}, \
2283 {"$f20", RTYPE_FPU | 20}, \
2284 {"$f21", RTYPE_FPU | 21}, \
2285 {"$f22", RTYPE_FPU | 22}, \
2286 {"$f23", RTYPE_FPU | 23}, \
2287 {"$f24", RTYPE_FPU | 24}, \
2288 {"$f25", RTYPE_FPU | 25}, \
2289 {"$f26", RTYPE_FPU | 26}, \
2290 {"$f27", RTYPE_FPU | 27}, \
2291 {"$f28", RTYPE_FPU | 28}, \
2292 {"$f29", RTYPE_FPU | 29}, \
2293 {"$f30", RTYPE_FPU | 30}, \
2294 {"$f31", RTYPE_FPU | 31}
2296 #define FPU_CONDITION_CODE_NAMES \
2297 {"$fcc0", RTYPE_FCC | 0}, \
2298 {"$fcc1", RTYPE_FCC | 1}, \
2299 {"$fcc2", RTYPE_FCC | 2}, \
2300 {"$fcc3", RTYPE_FCC | 3}, \
2301 {"$fcc4", RTYPE_FCC | 4}, \
2302 {"$fcc5", RTYPE_FCC | 5}, \
2303 {"$fcc6", RTYPE_FCC | 6}, \
2304 {"$fcc7", RTYPE_FCC | 7}
2306 #define COPROC_CONDITION_CODE_NAMES \
2307 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2308 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2309 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2310 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2311 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2312 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2313 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2314 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2316 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2317 {"$a4", RTYPE_GP | 8}, \
2318 {"$a5", RTYPE_GP | 9}, \
2319 {"$a6", RTYPE_GP | 10}, \
2320 {"$a7", RTYPE_GP | 11}, \
2321 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2322 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2323 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2324 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2325 {"$t0", RTYPE_GP | 12}, \
2326 {"$t1", RTYPE_GP | 13}, \
2327 {"$t2", RTYPE_GP | 14}, \
2328 {"$t3", RTYPE_GP | 15}
2330 #define O32_SYMBOLIC_REGISTER_NAMES \
2331 {"$t0", RTYPE_GP | 8}, \
2332 {"$t1", RTYPE_GP | 9}, \
2333 {"$t2", RTYPE_GP | 10}, \
2334 {"$t3", RTYPE_GP | 11}, \
2335 {"$t4", RTYPE_GP | 12}, \
2336 {"$t5", RTYPE_GP | 13}, \
2337 {"$t6", RTYPE_GP | 14}, \
2338 {"$t7", RTYPE_GP | 15}, \
2339 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2340 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2341 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2342 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2344 /* Remaining symbolic register names */
2345 #define SYMBOLIC_REGISTER_NAMES \
2346 {"$zero", RTYPE_GP | 0}, \
2347 {"$at", RTYPE_GP | 1}, \
2348 {"$AT", RTYPE_GP | 1}, \
2349 {"$v0", RTYPE_GP | 2}, \
2350 {"$v1", RTYPE_GP | 3}, \
2351 {"$a0", RTYPE_GP | 4}, \
2352 {"$a1", RTYPE_GP | 5}, \
2353 {"$a2", RTYPE_GP | 6}, \
2354 {"$a3", RTYPE_GP | 7}, \
2355 {"$s0", RTYPE_GP | 16}, \
2356 {"$s1", RTYPE_GP | 17}, \
2357 {"$s2", RTYPE_GP | 18}, \
2358 {"$s3", RTYPE_GP | 19}, \
2359 {"$s4", RTYPE_GP | 20}, \
2360 {"$s5", RTYPE_GP | 21}, \
2361 {"$s6", RTYPE_GP | 22}, \
2362 {"$s7", RTYPE_GP | 23}, \
2363 {"$t8", RTYPE_GP | 24}, \
2364 {"$t9", RTYPE_GP | 25}, \
2365 {"$k0", RTYPE_GP | 26}, \
2366 {"$kt0", RTYPE_GP | 26}, \
2367 {"$k1", RTYPE_GP | 27}, \
2368 {"$kt1", RTYPE_GP | 27}, \
2369 {"$gp", RTYPE_GP | 28}, \
2370 {"$sp", RTYPE_GP | 29}, \
2371 {"$s8", RTYPE_GP | 30}, \
2372 {"$fp", RTYPE_GP | 30}, \
2373 {"$ra", RTYPE_GP | 31}
2375 #define MIPS16_SPECIAL_REGISTER_NAMES \
2376 {"$pc", RTYPE_PC | 0}
2378 #define MDMX_VECTOR_REGISTER_NAMES \
2379 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2380 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2381 {"$v2", RTYPE_VEC | 2}, \
2382 {"$v3", RTYPE_VEC | 3}, \
2383 {"$v4", RTYPE_VEC | 4}, \
2384 {"$v5", RTYPE_VEC | 5}, \
2385 {"$v6", RTYPE_VEC | 6}, \
2386 {"$v7", RTYPE_VEC | 7}, \
2387 {"$v8", RTYPE_VEC | 8}, \
2388 {"$v9", RTYPE_VEC | 9}, \
2389 {"$v10", RTYPE_VEC | 10}, \
2390 {"$v11", RTYPE_VEC | 11}, \
2391 {"$v12", RTYPE_VEC | 12}, \
2392 {"$v13", RTYPE_VEC | 13}, \
2393 {"$v14", RTYPE_VEC | 14}, \
2394 {"$v15", RTYPE_VEC | 15}, \
2395 {"$v16", RTYPE_VEC | 16}, \
2396 {"$v17", RTYPE_VEC | 17}, \
2397 {"$v18", RTYPE_VEC | 18}, \
2398 {"$v19", RTYPE_VEC | 19}, \
2399 {"$v20", RTYPE_VEC | 20}, \
2400 {"$v21", RTYPE_VEC | 21}, \
2401 {"$v22", RTYPE_VEC | 22}, \
2402 {"$v23", RTYPE_VEC | 23}, \
2403 {"$v24", RTYPE_VEC | 24}, \
2404 {"$v25", RTYPE_VEC | 25}, \
2405 {"$v26", RTYPE_VEC | 26}, \
2406 {"$v27", RTYPE_VEC | 27}, \
2407 {"$v28", RTYPE_VEC | 28}, \
2408 {"$v29", RTYPE_VEC | 29}, \
2409 {"$v30", RTYPE_VEC | 30}, \
2410 {"$v31", RTYPE_VEC | 31}
2412 #define R5900_I_NAMES \
2413 {"$I", RTYPE_R5900_I | 0}
2415 #define R5900_Q_NAMES \
2416 {"$Q", RTYPE_R5900_Q | 0}
2418 #define R5900_R_NAMES \
2419 {"$R", RTYPE_R5900_R | 0}
2421 #define R5900_ACC_NAMES \
2422 {"$ACC", RTYPE_R5900_ACC | 0 }
2424 #define MIPS_DSP_ACCUMULATOR_NAMES \
2425 {"$ac0", RTYPE_ACC | 0}, \
2426 {"$ac1", RTYPE_ACC | 1}, \
2427 {"$ac2", RTYPE_ACC | 2}, \
2428 {"$ac3", RTYPE_ACC | 3}
2430 static const struct regname reg_names[] = {
2431 GENERIC_REGISTER_NUMBERS,
2433 FPU_CONDITION_CODE_NAMES,
2434 COPROC_CONDITION_CODE_NAMES,
2436 /* The $txx registers depends on the abi,
2437 these will be added later into the symbol table from
2438 one of the tables below once mips_abi is set after
2439 parsing of arguments from the command line. */
2440 SYMBOLIC_REGISTER_NAMES,
2442 MIPS16_SPECIAL_REGISTER_NAMES,
2443 MDMX_VECTOR_REGISTER_NAMES,
2448 MIPS_DSP_ACCUMULATOR_NAMES,
2452 static const struct regname reg_names_o32[] = {
2453 O32_SYMBOLIC_REGISTER_NAMES,
2457 static const struct regname reg_names_n32n64[] = {
2458 N32N64_SYMBOLIC_REGISTER_NAMES,
2462 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2463 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2464 of these register symbols, return the associated vector register,
2465 otherwise return SYMVAL itself. */
2468 mips_prefer_vec_regno (unsigned int symval)
2470 if ((symval & -2) == (RTYPE_GP | 2))
2471 return RTYPE_VEC | (symval & 1);
2475 /* Return true if string [S, E) is a valid register name, storing its
2476 symbol value in *SYMVAL_PTR if so. */
2479 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2484 /* Terminate name. */
2488 /* Look up the name. */
2489 symbol = symbol_find (s);
2492 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2495 *symval_ptr = S_GET_VALUE (symbol);
2499 /* Return true if the string at *SPTR is a valid register name. Allow it
2500 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2503 When returning true, move *SPTR past the register, store the
2504 register's symbol value in *SYMVAL_PTR and the channel mask in
2505 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2506 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2507 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2510 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2511 unsigned int *channels_ptr)
2515 unsigned int channels, symval, bit;
2517 /* Find end of name. */
2519 if (is_name_beginner (*e))
2521 while (is_part_of_name (*e))
2525 if (!mips_parse_register_1 (s, e, &symval))
2530 /* Eat characters from the end of the string that are valid
2531 channel suffixes. The preceding register must be $ACC or
2532 end with a digit, so there is no ambiguity. */
2535 for (q = "wzyx"; *q; q++, bit <<= 1)
2536 if (m > s && m[-1] == *q)
2543 || !mips_parse_register_1 (s, m, &symval)
2544 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2549 *symval_ptr = symval;
2551 *channels_ptr = channels;
2555 /* Check if SPTR points at a valid register specifier according to TYPES.
2556 If so, then return 1, advance S to consume the specifier and store
2557 the register's number in REGNOP, otherwise return 0. */
2560 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2564 if (mips_parse_register (s, ®no, NULL))
2566 if (types & RTYPE_VEC)
2567 regno = mips_prefer_vec_regno (regno);
2576 as_warn (_("Unrecognized register name `%s'"), *s);
2581 return regno <= RNUM_MASK;
2584 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2585 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2588 mips_parse_vu0_channels (char *s, unsigned int *channels)
2593 for (i = 0; i < 4; i++)
2594 if (*s == "xyzw"[i])
2596 *channels |= 1 << (3 - i);
2602 /* Token types for parsed operand lists. */
2603 enum mips_operand_token_type {
2604 /* A plain register, e.g. $f2. */
2607 /* A 4-bit XYZW channel mask. */
2610 /* An element of a vector, e.g. $v0[1]. */
2613 /* A continuous range of registers, e.g. $s0-$s4. */
2616 /* A (possibly relocated) expression. */
2619 /* A floating-point value. */
2622 /* A single character. This can be '(', ')' or ',', but '(' only appears
2626 /* A doubled character, either "--" or "++". */
2629 /* The end of the operand list. */
2633 /* A parsed operand token. */
2634 struct mips_operand_token
2636 /* The type of token. */
2637 enum mips_operand_token_type type;
2640 /* The register symbol value for an OT_REG. */
2643 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2644 unsigned int channels;
2646 /* The register symbol value and index for an OT_REG_ELEMENT. */
2652 /* The two register symbol values involved in an OT_REG_RANGE. */
2654 unsigned int regno1;
2655 unsigned int regno2;
2658 /* The value of an OT_INTEGER. The value is represented as an
2659 expression and the relocation operators that were applied to
2660 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2661 relocation operators were used. */
2664 bfd_reloc_code_real_type relocs[3];
2667 /* The binary data for an OT_FLOAT constant, and the number of bytes
2670 unsigned char data[8];
2674 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2679 /* An obstack used to construct lists of mips_operand_tokens. */
2680 static struct obstack mips_operand_tokens;
2682 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2685 mips_add_token (struct mips_operand_token *token,
2686 enum mips_operand_token_type type)
2689 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2692 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2693 and OT_REG tokens for them if so, and return a pointer to the first
2694 unconsumed character. Return null otherwise. */
2697 mips_parse_base_start (char *s)
2699 struct mips_operand_token token;
2700 unsigned int regno, channels;
2701 bfd_boolean decrement_p;
2707 SKIP_SPACE_TABS (s);
2709 /* Only match "--" as part of a base expression. In other contexts "--X"
2710 is a double negative. */
2711 decrement_p = (s[0] == '-' && s[1] == '-');
2715 SKIP_SPACE_TABS (s);
2718 /* Allow a channel specifier because that leads to better error messages
2719 than treating something like "$vf0x++" as an expression. */
2720 if (!mips_parse_register (&s, ®no, &channels))
2724 mips_add_token (&token, OT_CHAR);
2729 mips_add_token (&token, OT_DOUBLE_CHAR);
2732 token.u.regno = regno;
2733 mips_add_token (&token, OT_REG);
2737 token.u.channels = channels;
2738 mips_add_token (&token, OT_CHANNELS);
2741 /* For consistency, only match "++" as part of base expressions too. */
2742 SKIP_SPACE_TABS (s);
2743 if (s[0] == '+' && s[1] == '+')
2747 mips_add_token (&token, OT_DOUBLE_CHAR);
2753 /* Parse one or more tokens from S. Return a pointer to the first
2754 unconsumed character on success. Return null if an error was found
2755 and store the error text in insn_error. FLOAT_FORMAT is as for
2756 mips_parse_arguments. */
2759 mips_parse_argument_token (char *s, char float_format)
2761 char *end, *save_in, *err;
2762 unsigned int regno1, regno2, channels;
2763 struct mips_operand_token token;
2765 /* First look for "($reg", since we want to treat that as an
2766 OT_CHAR and OT_REG rather than an expression. */
2767 end = mips_parse_base_start (s);
2771 /* Handle other characters that end up as OT_CHARs. */
2772 if (*s == ')' || *s == ',')
2775 mips_add_token (&token, OT_CHAR);
2780 /* Handle tokens that start with a register. */
2781 if (mips_parse_register (&s, ®no1, &channels))
2785 /* A register and a VU0 channel suffix. */
2786 token.u.regno = regno1;
2787 mips_add_token (&token, OT_REG);
2789 token.u.channels = channels;
2790 mips_add_token (&token, OT_CHANNELS);
2794 SKIP_SPACE_TABS (s);
2797 /* A register range. */
2799 SKIP_SPACE_TABS (s);
2800 if (!mips_parse_register (&s, ®no2, NULL))
2802 insn_error = _("Invalid register range");
2806 token.u.reg_range.regno1 = regno1;
2807 token.u.reg_range.regno2 = regno2;
2808 mips_add_token (&token, OT_REG_RANGE);
2813 /* A vector element. */
2814 expressionS element;
2817 SKIP_SPACE_TABS (s);
2818 my_getExpression (&element, s);
2819 if (element.X_op != O_constant)
2821 insn_error = _("Vector element must be constant");
2825 SKIP_SPACE_TABS (s);
2828 insn_error = _("Missing `]'");
2833 token.u.reg_element.regno = regno1;
2834 token.u.reg_element.index = element.X_add_number;
2835 mips_add_token (&token, OT_REG_ELEMENT);
2839 /* Looks like just a plain register. */
2840 token.u.regno = regno1;
2841 mips_add_token (&token, OT_REG);
2847 /* First try to treat expressions as floats. */
2848 save_in = input_line_pointer;
2849 input_line_pointer = s;
2850 err = md_atof (float_format, (char *) token.u.flt.data,
2851 &token.u.flt.length);
2852 end = input_line_pointer;
2853 input_line_pointer = save_in;
2861 mips_add_token (&token, OT_FLOAT);
2866 /* Treat everything else as an integer expression. */
2867 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
2868 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
2869 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
2870 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
2872 mips_add_token (&token, OT_INTEGER);
2876 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2877 if expressions should be treated as 32-bit floating-point constants,
2878 'd' if they should be treated as 64-bit floating-point constants,
2879 or 0 if they should be treated as integer expressions (the usual case).
2881 Return a list of tokens on success, otherwise return 0. The caller
2882 must obstack_free the list after use. */
2884 static struct mips_operand_token *
2885 mips_parse_arguments (char *s, char float_format)
2887 struct mips_operand_token token;
2889 SKIP_SPACE_TABS (s);
2892 s = mips_parse_argument_token (s, float_format);
2895 obstack_free (&mips_operand_tokens,
2896 obstack_finish (&mips_operand_tokens));
2899 SKIP_SPACE_TABS (s);
2901 mips_add_token (&token, OT_END);
2902 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
2905 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2906 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2909 is_opcode_valid (const struct mips_opcode *mo)
2911 int isa = mips_opts.isa;
2912 int ase = mips_opts.ase;
2916 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2917 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2918 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2919 ase |= mips_ases[i].flags64;
2921 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2924 /* Check whether the instruction or macro requires single-precision or
2925 double-precision floating-point support. Note that this information is
2926 stored differently in the opcode table for insns and macros. */
2927 if (mo->pinfo == INSN_MACRO)
2929 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2930 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2934 fp_s = mo->pinfo & FP_S;
2935 fp_d = mo->pinfo & FP_D;
2938 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2941 if (fp_s && mips_opts.soft_float)
2947 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2948 selected ISA and architecture. */
2951 is_opcode_valid_16 (const struct mips_opcode *mo)
2953 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2956 /* Return TRUE if the size of the microMIPS opcode MO matches one
2957 explicitly requested. Always TRUE in the standard MIPS mode. */
2960 is_size_valid (const struct mips_opcode *mo)
2962 if (!mips_opts.micromips)
2965 if (mips_opts.insn32)
2967 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2969 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2972 if (!forced_insn_length)
2974 if (mo->pinfo == INSN_MACRO)
2976 return forced_insn_length == micromips_insn_length (mo);
2979 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2980 of the preceding instruction. Always TRUE in the standard MIPS mode.
2982 We don't accept macros in 16-bit delay slots to avoid a case where
2983 a macro expansion fails because it relies on a preceding 32-bit real
2984 instruction to have matched and does not handle the operands correctly.
2985 The only macros that may expand to 16-bit instructions are JAL that
2986 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2987 and BGT (that likewise cannot be placed in a delay slot) that decay to
2988 a NOP. In all these cases the macros precede any corresponding real
2989 instruction definitions in the opcode table, so they will match in the
2990 second pass where the size of the delay slot is ignored and therefore
2991 produce correct code. */
2994 is_delay_slot_valid (const struct mips_opcode *mo)
2996 if (!mips_opts.micromips)
2999 if (mo->pinfo == INSN_MACRO)
3000 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3001 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3002 && micromips_insn_length (mo) != 4)
3004 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3005 && micromips_insn_length (mo) != 2)
3011 /* For consistency checking, verify that all bits of OPCODE are specified
3012 either by the match/mask part of the instruction definition, or by the
3013 operand list. Also build up a list of operands in OPERANDS.
3015 INSN_BITS says which bits of the instruction are significant.
3016 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3017 provides the mips_operand description of each operand. DECODE_OPERAND
3018 is null for MIPS16 instructions. */
3021 validate_mips_insn (const struct mips_opcode *opcode,
3022 unsigned long insn_bits,
3023 const struct mips_operand *(*decode_operand) (const char *),
3024 struct mips_operand_array *operands)
3027 unsigned long used_bits, doubled, undefined, opno, mask;
3028 const struct mips_operand *operand;
3030 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3031 if ((mask & opcode->match) != opcode->match)
3033 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3034 opcode->name, opcode->args);
3039 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3040 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3041 for (s = opcode->args; *s; ++s)
3054 if (!decode_operand)
3055 operand = decode_mips16_operand (*s, FALSE);
3057 operand = decode_operand (s);
3058 if (!operand && opcode->pinfo != INSN_MACRO)
3060 as_bad (_("internal: unknown operand type: %s %s"),
3061 opcode->name, opcode->args);
3064 gas_assert (opno < MAX_OPERANDS);
3065 operands->operand[opno] = operand;
3066 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3068 used_bits = mips_insert_operand (operand, used_bits, -1);
3069 if (operand->type == OP_MDMX_IMM_REG)
3070 /* Bit 5 is the format selector (OB vs QH). The opcode table
3071 has separate entries for each format. */
3072 used_bits &= ~(1 << (operand->lsb + 5));
3073 if (operand->type == OP_ENTRY_EXIT_LIST)
3074 used_bits &= ~(mask & 0x700);
3076 /* Skip prefix characters. */
3077 if (decode_operand && (*s == '+' || *s == 'm'))
3082 doubled = used_bits & mask & insn_bits;
3085 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3086 " %s %s"), doubled, opcode->name, opcode->args);
3090 undefined = ~used_bits & insn_bits;
3091 if (opcode->pinfo != INSN_MACRO && undefined)
3093 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3094 undefined, opcode->name, opcode->args);
3097 used_bits &= ~insn_bits;
3100 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3101 used_bits, opcode->name, opcode->args);
3107 /* The MIPS16 version of validate_mips_insn. */
3110 validate_mips16_insn (const struct mips_opcode *opcode,
3111 struct mips_operand_array *operands)
3113 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3115 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3116 instruction. Use TMP to describe the full instruction. */
3117 struct mips_opcode tmp;
3122 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3124 return validate_mips_insn (opcode, 0xffff, 0, operands);
3127 /* The microMIPS version of validate_mips_insn. */
3130 validate_micromips_insn (const struct mips_opcode *opc,
3131 struct mips_operand_array *operands)
3133 unsigned long insn_bits;
3134 unsigned long major;
3135 unsigned int length;
3137 if (opc->pinfo == INSN_MACRO)
3138 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3141 length = micromips_insn_length (opc);
3142 if (length != 2 && length != 4)
3144 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3145 "%s %s"), length, opc->name, opc->args);
3148 major = opc->match >> (10 + 8 * (length - 2));
3149 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3150 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3152 as_bad (_("Internal error: bad microMIPS opcode "
3153 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3157 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3158 insn_bits = 1 << 4 * length;
3159 insn_bits <<= 4 * length;
3161 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3165 /* This function is called once, at assembler startup time. It should set up
3166 all the tables, etc. that the MD part of the assembler will need. */
3171 const char *retval = NULL;
3175 if (mips_pic != NO_PIC)
3177 if (g_switch_seen && g_switch_value != 0)
3178 as_bad (_("-G may not be used in position-independent code"));
3182 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3183 as_warn (_("Could not set architecture and machine"));
3185 op_hash = hash_new ();
3187 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3188 for (i = 0; i < NUMOPCODES;)
3190 const char *name = mips_opcodes[i].name;
3192 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3195 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3196 mips_opcodes[i].name, retval);
3197 /* Probably a memory allocation problem? Give up now. */
3198 as_fatal (_("Broken assembler. No assembly attempted."));
3202 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3203 decode_mips_operand, &mips_operands[i]))
3205 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3207 create_insn (&nop_insn, mips_opcodes + i);
3208 if (mips_fix_loongson2f_nop)
3209 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3210 nop_insn.fixed_p = 1;
3214 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3217 mips16_op_hash = hash_new ();
3218 mips16_operands = XCNEWVEC (struct mips_operand_array,
3219 bfd_mips16_num_opcodes);
3222 while (i < bfd_mips16_num_opcodes)
3224 const char *name = mips16_opcodes[i].name;
3226 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3228 as_fatal (_("internal: can't hash `%s': %s"),
3229 mips16_opcodes[i].name, retval);
3232 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3234 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3236 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3237 mips16_nop_insn.fixed_p = 1;
3241 while (i < bfd_mips16_num_opcodes
3242 && strcmp (mips16_opcodes[i].name, name) == 0);
3245 micromips_op_hash = hash_new ();
3246 micromips_operands = XCNEWVEC (struct mips_operand_array,
3247 bfd_micromips_num_opcodes);
3250 while (i < bfd_micromips_num_opcodes)
3252 const char *name = micromips_opcodes[i].name;
3254 retval = hash_insert (micromips_op_hash, name,
3255 (void *) µmips_opcodes[i]);
3257 as_fatal (_("internal: can't hash `%s': %s"),
3258 micromips_opcodes[i].name, retval);
3261 struct mips_cl_insn *micromips_nop_insn;
3263 if (!validate_micromips_insn (µmips_opcodes[i],
3264 µmips_operands[i]))
3267 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3269 if (micromips_insn_length (micromips_opcodes + i) == 2)
3270 micromips_nop_insn = µmips_nop16_insn;
3271 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3272 micromips_nop_insn = µmips_nop32_insn;
3276 if (micromips_nop_insn->insn_mo == NULL
3277 && strcmp (name, "nop") == 0)
3279 create_insn (micromips_nop_insn, micromips_opcodes + i);
3280 micromips_nop_insn->fixed_p = 1;
3284 while (++i < bfd_micromips_num_opcodes
3285 && strcmp (micromips_opcodes[i].name, name) == 0);
3289 as_fatal (_("Broken assembler. No assembly attempted."));
3291 /* We add all the general register names to the symbol table. This
3292 helps us detect invalid uses of them. */
3293 for (i = 0; reg_names[i].name; i++)
3294 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3295 reg_names[i].num, /* & RNUM_MASK, */
3296 &zero_address_frag));
3298 for (i = 0; reg_names_n32n64[i].name; i++)
3299 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3300 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3301 &zero_address_frag));
3303 for (i = 0; reg_names_o32[i].name; i++)
3304 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3305 reg_names_o32[i].num, /* & RNUM_MASK, */
3306 &zero_address_frag));
3308 for (i = 0; i < 32; i++)
3312 /* R5900 VU0 floating-point register. */
3313 regname[sizeof (rename) - 1] = 0;
3314 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3315 symbol_table_insert (symbol_new (regname, reg_section,
3316 RTYPE_VF | i, &zero_address_frag));
3318 /* R5900 VU0 integer register. */
3319 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3320 symbol_table_insert (symbol_new (regname, reg_section,
3321 RTYPE_VI | i, &zero_address_frag));
3325 obstack_init (&mips_operand_tokens);
3327 mips_no_prev_insn ();
3330 mips_cprmask[0] = 0;
3331 mips_cprmask[1] = 0;
3332 mips_cprmask[2] = 0;
3333 mips_cprmask[3] = 0;
3335 /* set the default alignment for the text section (2**2) */
3336 record_alignment (text_section, 2);
3338 bfd_set_gp_size (stdoutput, g_switch_value);
3340 /* On a native system other than VxWorks, sections must be aligned
3341 to 16 byte boundaries. When configured for an embedded ELF
3342 target, we don't bother. */
3343 if (strncmp (TARGET_OS, "elf", 3) != 0
3344 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3346 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3347 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3348 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3351 /* Create a .reginfo section for register masks and a .mdebug
3352 section for debugging information. */
3360 subseg = now_subseg;
3362 /* The ABI says this section should be loaded so that the
3363 running program can access it. However, we don't load it
3364 if we are configured for an embedded target */
3365 flags = SEC_READONLY | SEC_DATA;
3366 if (strncmp (TARGET_OS, "elf", 3) != 0)
3367 flags |= SEC_ALLOC | SEC_LOAD;
3369 if (mips_abi != N64_ABI)
3371 sec = subseg_new (".reginfo", (subsegT) 0);
3373 bfd_set_section_flags (stdoutput, sec, flags);
3374 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3376 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3380 /* The 64-bit ABI uses a .MIPS.options section rather than
3381 .reginfo section. */
3382 sec = subseg_new (".MIPS.options", (subsegT) 0);
3383 bfd_set_section_flags (stdoutput, sec, flags);
3384 bfd_set_section_alignment (stdoutput, sec, 3);
3386 /* Set up the option header. */
3388 Elf_Internal_Options opthdr;
3391 opthdr.kind = ODK_REGINFO;
3392 opthdr.size = (sizeof (Elf_External_Options)
3393 + sizeof (Elf64_External_RegInfo));
3396 f = frag_more (sizeof (Elf_External_Options));
3397 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3398 (Elf_External_Options *) f);
3400 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3404 if (ECOFF_DEBUGGING)
3406 sec = subseg_new (".mdebug", (subsegT) 0);
3407 (void) bfd_set_section_flags (stdoutput, sec,
3408 SEC_HAS_CONTENTS | SEC_READONLY);
3409 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3411 else if (mips_flag_pdr)
3413 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3414 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3415 SEC_READONLY | SEC_RELOC
3417 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3420 subseg_set (seg, subseg);
3423 if (! ECOFF_DEBUGGING)
3426 if (mips_fix_vr4120)
3427 init_vr4120_conflicts ();
3433 mips_emit_delays ();
3434 if (! ECOFF_DEBUGGING)
3439 md_assemble (char *str)
3441 struct mips_cl_insn insn;
3442 bfd_reloc_code_real_type unused_reloc[3]
3443 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3445 imm_expr.X_op = O_absent;
3446 imm2_expr.X_op = O_absent;
3447 offset_expr.X_op = O_absent;
3448 offset_reloc[0] = BFD_RELOC_UNUSED;
3449 offset_reloc[1] = BFD_RELOC_UNUSED;
3450 offset_reloc[2] = BFD_RELOC_UNUSED;
3452 mips_mark_labels ();
3453 mips_assembling_insn = TRUE;
3455 if (mips_opts.mips16)
3456 mips16_ip (str, &insn);
3459 mips_ip (str, &insn);
3460 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3461 str, insn.insn_opcode));
3465 as_bad ("%s `%s'", insn_error, str);
3466 else if (insn.insn_mo->pinfo == INSN_MACRO)
3469 if (mips_opts.mips16)
3470 mips16_macro (&insn);
3477 if (offset_expr.X_op != O_absent)
3478 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3480 append_insn (&insn, NULL, unused_reloc, FALSE);
3483 mips_assembling_insn = FALSE;
3486 /* Convenience functions for abstracting away the differences between
3487 MIPS16 and non-MIPS16 relocations. */
3489 static inline bfd_boolean
3490 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3494 case BFD_RELOC_MIPS16_JMP:
3495 case BFD_RELOC_MIPS16_GPREL:
3496 case BFD_RELOC_MIPS16_GOT16:
3497 case BFD_RELOC_MIPS16_CALL16:
3498 case BFD_RELOC_MIPS16_HI16_S:
3499 case BFD_RELOC_MIPS16_HI16:
3500 case BFD_RELOC_MIPS16_LO16:
3508 static inline bfd_boolean
3509 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3513 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3514 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3515 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3516 case BFD_RELOC_MICROMIPS_GPREL16:
3517 case BFD_RELOC_MICROMIPS_JMP:
3518 case BFD_RELOC_MICROMIPS_HI16:
3519 case BFD_RELOC_MICROMIPS_HI16_S:
3520 case BFD_RELOC_MICROMIPS_LO16:
3521 case BFD_RELOC_MICROMIPS_LITERAL:
3522 case BFD_RELOC_MICROMIPS_GOT16:
3523 case BFD_RELOC_MICROMIPS_CALL16:
3524 case BFD_RELOC_MICROMIPS_GOT_HI16:
3525 case BFD_RELOC_MICROMIPS_GOT_LO16:
3526 case BFD_RELOC_MICROMIPS_CALL_HI16:
3527 case BFD_RELOC_MICROMIPS_CALL_LO16:
3528 case BFD_RELOC_MICROMIPS_SUB:
3529 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3530 case BFD_RELOC_MICROMIPS_GOT_OFST:
3531 case BFD_RELOC_MICROMIPS_GOT_DISP:
3532 case BFD_RELOC_MICROMIPS_HIGHEST:
3533 case BFD_RELOC_MICROMIPS_HIGHER:
3534 case BFD_RELOC_MICROMIPS_SCN_DISP:
3535 case BFD_RELOC_MICROMIPS_JALR:
3543 static inline bfd_boolean
3544 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3546 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3549 static inline bfd_boolean
3550 got16_reloc_p (bfd_reloc_code_real_type reloc)
3552 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3553 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3556 static inline bfd_boolean
3557 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3559 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3560 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3563 static inline bfd_boolean
3564 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3566 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3567 || reloc == BFD_RELOC_MICROMIPS_LO16);
3570 static inline bfd_boolean
3571 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3573 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3576 static inline bfd_boolean
3577 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3579 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3580 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3583 /* Return true if RELOC is a PC-relative relocation that does not have
3584 full address range. */
3586 static inline bfd_boolean
3587 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3591 case BFD_RELOC_16_PCREL_S2:
3592 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3593 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3594 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3597 case BFD_RELOC_32_PCREL:
3598 return HAVE_64BIT_ADDRESSES;
3605 /* Return true if the given relocation might need a matching %lo().
3606 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3607 need a matching %lo() when applied to local symbols. */
3609 static inline bfd_boolean
3610 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3612 return (HAVE_IN_PLACE_ADDENDS
3613 && (hi16_reloc_p (reloc)
3614 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3615 all GOT16 relocations evaluate to "G". */
3616 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3619 /* Return the type of %lo() reloc needed by RELOC, given that
3620 reloc_needs_lo_p. */
3622 static inline bfd_reloc_code_real_type
3623 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3625 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3626 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3630 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3633 static inline bfd_boolean
3634 fixup_has_matching_lo_p (fixS *fixp)
3636 return (fixp->fx_next != NULL
3637 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3638 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3639 && fixp->fx_offset == fixp->fx_next->fx_offset);
3642 /* Move all labels in LABELS to the current insertion point. TEXT_P
3643 says whether the labels refer to text or data. */
3646 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3648 struct insn_label_list *l;
3651 for (l = labels; l != NULL; l = l->next)
3653 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3654 symbol_set_frag (l->label, frag_now);
3655 val = (valueT) frag_now_fix ();
3656 /* MIPS16/microMIPS text labels are stored as odd. */
3657 if (text_p && HAVE_CODE_COMPRESSION)
3659 S_SET_VALUE (l->label, val);
3663 /* Move all labels in insn_labels to the current insertion point
3664 and treat them as text labels. */
3667 mips_move_text_labels (void)
3669 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3673 s_is_linkonce (symbolS *sym, segT from_seg)
3675 bfd_boolean linkonce = FALSE;
3676 segT symseg = S_GET_SEGMENT (sym);
3678 if (symseg != from_seg && !S_IS_LOCAL (sym))
3680 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3682 /* The GNU toolchain uses an extension for ELF: a section
3683 beginning with the magic string .gnu.linkonce is a
3684 linkonce section. */
3685 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3686 sizeof ".gnu.linkonce" - 1) == 0)
3692 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3693 linker to handle them specially, such as generating jalx instructions
3694 when needed. We also make them odd for the duration of the assembly,
3695 in order to generate the right sort of code. We will make them even
3696 in the adjust_symtab routine, while leaving them marked. This is
3697 convenient for the debugger and the disassembler. The linker knows
3698 to make them odd again. */
3701 mips_compressed_mark_label (symbolS *label)
3703 gas_assert (HAVE_CODE_COMPRESSION);
3705 if (mips_opts.mips16)
3706 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3708 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3709 if ((S_GET_VALUE (label) & 1) == 0
3710 /* Don't adjust the address if the label is global or weak, or
3711 in a link-once section, since we'll be emitting symbol reloc
3712 references to it which will be patched up by the linker, and
3713 the final value of the symbol may or may not be MIPS16/microMIPS. */
3714 && !S_IS_WEAK (label)
3715 && !S_IS_EXTERNAL (label)
3716 && !s_is_linkonce (label, now_seg))
3717 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3720 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3723 mips_compressed_mark_labels (void)
3725 struct insn_label_list *l;
3727 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3728 mips_compressed_mark_label (l->label);
3731 /* End the current frag. Make it a variant frag and record the
3735 relax_close_frag (void)
3737 mips_macro_warning.first_frag = frag_now;
3738 frag_var (rs_machine_dependent, 0, 0,
3739 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3740 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3742 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3743 mips_relax.first_fixup = 0;
3746 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3747 See the comment above RELAX_ENCODE for more details. */
3750 relax_start (symbolS *symbol)
3752 gas_assert (mips_relax.sequence == 0);
3753 mips_relax.sequence = 1;
3754 mips_relax.symbol = symbol;
3757 /* Start generating the second version of a relaxable sequence.
3758 See the comment above RELAX_ENCODE for more details. */
3763 gas_assert (mips_relax.sequence == 1);
3764 mips_relax.sequence = 2;
3767 /* End the current relaxable sequence. */
3772 gas_assert (mips_relax.sequence == 2);
3773 relax_close_frag ();
3774 mips_relax.sequence = 0;
3777 /* Return true if IP is a delayed branch or jump. */
3779 static inline bfd_boolean
3780 delayed_branch_p (const struct mips_cl_insn *ip)
3782 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3783 | INSN_COND_BRANCH_DELAY
3784 | INSN_COND_BRANCH_LIKELY)) != 0;
3787 /* Return true if IP is a compact branch or jump. */
3789 static inline bfd_boolean
3790 compact_branch_p (const struct mips_cl_insn *ip)
3792 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3793 | INSN2_COND_BRANCH)) != 0;
3796 /* Return true if IP is an unconditional branch or jump. */
3798 static inline bfd_boolean
3799 uncond_branch_p (const struct mips_cl_insn *ip)
3801 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3802 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3805 /* Return true if IP is a branch-likely instruction. */
3807 static inline bfd_boolean
3808 branch_likely_p (const struct mips_cl_insn *ip)
3810 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3813 /* Return the type of nop that should be used to fill the delay slot
3814 of delayed branch IP. */
3816 static struct mips_cl_insn *
3817 get_delay_slot_nop (const struct mips_cl_insn *ip)
3819 if (mips_opts.micromips
3820 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3821 return µmips_nop32_insn;
3825 /* Return a mask that has bit N set if OPCODE reads the register(s)
3829 insn_read_mask (const struct mips_opcode *opcode)
3831 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3834 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3838 insn_write_mask (const struct mips_opcode *opcode)
3840 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3843 /* Return a mask of the registers specified by operand OPERAND of INSN.
3844 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3848 operand_reg_mask (const struct mips_cl_insn *insn,
3849 const struct mips_operand *operand,
3850 unsigned int type_mask)
3852 unsigned int uval, vsel;
3854 switch (operand->type)
3861 case OP_ADDIUSP_INT:
3862 case OP_ENTRY_EXIT_LIST:
3863 case OP_REPEAT_DEST_REG:
3864 case OP_REPEAT_PREV_REG:
3867 case OP_VU0_MATCH_SUFFIX:
3871 case OP_OPTIONAL_REG:
3873 const struct mips_reg_operand *reg_op;
3875 reg_op = (const struct mips_reg_operand *) operand;
3876 if (!(type_mask & (1 << reg_op->reg_type)))
3878 uval = insn_extract_operand (insn, operand);
3879 return 1 << mips_decode_reg_operand (reg_op, uval);
3884 const struct mips_reg_pair_operand *pair_op;
3886 pair_op = (const struct mips_reg_pair_operand *) operand;
3887 if (!(type_mask & (1 << pair_op->reg_type)))
3889 uval = insn_extract_operand (insn, operand);
3890 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
3893 case OP_CLO_CLZ_DEST:
3894 if (!(type_mask & (1 << OP_REG_GP)))
3896 uval = insn_extract_operand (insn, operand);
3897 return (1 << (uval & 31)) | (1 << (uval >> 5));
3899 case OP_LWM_SWM_LIST:
3902 case OP_SAVE_RESTORE_LIST:
3905 case OP_MDMX_IMM_REG:
3906 if (!(type_mask & (1 << OP_REG_VEC)))
3908 uval = insn_extract_operand (insn, operand);
3910 if ((vsel & 0x18) == 0x18)
3912 return 1 << (uval & 31);
3917 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3918 where bit N of OPNO_MASK is set if operand N should be included.
3919 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3923 insn_reg_mask (const struct mips_cl_insn *insn,
3924 unsigned int type_mask, unsigned int opno_mask)
3926 unsigned int opno, reg_mask;
3930 while (opno_mask != 0)
3933 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
3940 /* Return the mask of core registers that IP reads. */
3943 gpr_read_mask (const struct mips_cl_insn *ip)
3945 unsigned long pinfo, pinfo2;
3948 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
3949 pinfo = ip->insn_mo->pinfo;
3950 pinfo2 = ip->insn_mo->pinfo2;
3951 if (pinfo & INSN_UDI)
3953 /* UDI instructions have traditionally been assumed to read RS
3955 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3956 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3958 if (pinfo & INSN_READ_GPR_24)
3960 if (pinfo2 & INSN2_READ_GPR_16)
3962 if (pinfo2 & INSN2_READ_SP)
3964 if (pinfo2 & INSN2_READ_GPR_31)
3966 /* Don't include register 0. */
3970 /* Return the mask of core registers that IP writes. */
3973 gpr_write_mask (const struct mips_cl_insn *ip)
3975 unsigned long pinfo, pinfo2;
3978 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
3979 pinfo = ip->insn_mo->pinfo;
3980 pinfo2 = ip->insn_mo->pinfo2;
3981 if (pinfo & INSN_WRITE_GPR_24)
3983 if (pinfo & INSN_WRITE_GPR_31)
3985 if (pinfo & INSN_UDI)
3986 /* UDI instructions have traditionally been assumed to write to RD. */
3987 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3988 if (pinfo2 & INSN2_WRITE_SP)
3990 /* Don't include register 0. */
3994 /* Return the mask of floating-point registers that IP reads. */
3997 fpr_read_mask (const struct mips_cl_insn *ip)
3999 unsigned long pinfo;
4002 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4003 insn_read_mask (ip->insn_mo));
4004 pinfo = ip->insn_mo->pinfo;
4005 /* Conservatively treat all operands to an FP_D instruction are doubles.
4006 (This is overly pessimistic for things like cvt.d.s.) */
4007 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4012 /* Return the mask of floating-point registers that IP writes. */
4015 fpr_write_mask (const struct mips_cl_insn *ip)
4017 unsigned long pinfo;
4020 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4021 insn_write_mask (ip->insn_mo));
4022 pinfo = ip->insn_mo->pinfo;
4023 /* Conservatively treat all operands to an FP_D instruction are doubles.
4024 (This is overly pessimistic for things like cvt.s.d.) */
4025 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4030 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4031 Check whether that is allowed. */
4034 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4036 const char *s = insn->name;
4038 if (insn->pinfo == INSN_MACRO)
4039 /* Let a macro pass, we'll catch it later when it is expanded. */
4042 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4044 /* Allow odd registers for single-precision ops. */
4045 switch (insn->pinfo & (FP_S | FP_D))
4056 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4057 s = strchr (insn->name, '.');
4058 if (s != NULL && opnum == 2)
4059 s = strchr (s + 1, '.');
4060 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4063 /* Single-precision coprocessor loads and moves are OK too. */
4064 if ((insn->pinfo & FP_S)
4065 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4066 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4072 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4073 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4074 this operand is normally printed in hex or decimal. */
4077 report_bad_range (struct mips_cl_insn *insn, int argnum,
4078 offsetT val, int min_val, int max_val,
4079 bfd_boolean print_hex)
4081 if (print_hex && val >= 0)
4082 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4084 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4086 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4088 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4090 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4092 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4095 /* Report an invalid combination of position and size operands for a bitfield
4096 operation. POS and SIZE are the values that were given. */
4099 report_bad_field (offsetT pos, offsetT size)
4101 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4102 (unsigned long) pos, (unsigned long) size);
4105 /* Information about an instruction argument that we're trying to match. */
4106 struct mips_arg_info
4108 /* The instruction so far. */
4109 struct mips_cl_insn *insn;
4111 /* The first unconsumed operand token. */
4112 struct mips_operand_token *token;
4114 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4117 /* The 1-based argument number, for error reporting. This does not
4118 count elided optional registers, etc.. */
4121 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4122 unsigned int last_regno;
4124 /* If the first operand was an OP_REG, this is the register that it
4125 specified, otherwise it is ILLEGAL_REG. */
4126 unsigned int dest_regno;
4128 /* The value of the last OP_INT operand. Only used for OP_MSB,
4129 where it gives the lsb position. */
4130 unsigned int last_op_int;
4132 /* If true, match routines should silently reject invalid arguments.
4133 If false, match routines can accept invalid arguments as long as
4134 they report an appropriate error. They still have the option of
4135 silently rejecting arguments, in which case a generic "Invalid operands"
4136 style of error will be used instead. */
4137 bfd_boolean soft_match;
4139 /* If true, the OP_INT match routine should treat plain symbolic operands
4140 as if a relocation operator like %lo(...) had been used. This is only
4141 ever true if the operand can be relocated. */
4142 bfd_boolean allow_nonconst;
4144 /* When true, the OP_INT match routine should allow unsigned N-bit
4145 arguments to be used where a signed N-bit operand is expected. */
4146 bfd_boolean lax_max;
4148 /* True if a reference to the current AT register was seen. */
4149 bfd_boolean seen_at;
4152 /* Try to match an OT_CHAR token for character CH. Consume the token
4153 and return true on success, otherwise return false. */
4156 match_char (struct mips_arg_info *arg, char ch)
4158 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4168 /* Try to get an expression from the next tokens in ARG. Consume the
4169 tokens and return true on success, storing the expression value in
4170 VALUE and relocation types in R. */
4173 match_expression (struct mips_arg_info *arg, expressionS *value,
4174 bfd_reloc_code_real_type *r)
4176 if (arg->token->type == OT_INTEGER)
4178 *value = arg->token->u.integer.value;
4179 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4184 /* Error-reporting is more consistent if we treat registers as O_register
4185 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4186 then handled in the same way. */
4187 if (arg->token->type == OT_REG)
4189 value->X_add_number = arg->token->u.regno;
4192 else if (arg->token[0].type == OT_CHAR
4193 && arg->token[0].u.ch == '('
4194 && arg->token[1].type == OT_REG
4195 && arg->token[2].type == OT_CHAR
4196 && arg->token[2].u.ch == ')')
4198 value->X_add_number = arg->token[1].u.regno;
4204 value->X_op = O_register;
4205 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4209 /* Try to get a constant expression from the next tokens in ARG. Consume
4210 the tokens and return return true on success, storing the constant value
4211 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4215 match_const_int (struct mips_arg_info *arg, offsetT *value, offsetT fallback)
4218 bfd_reloc_code_real_type r[3];
4220 if (!match_expression (arg, &ex, r))
4223 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4224 *value = ex.X_add_number;
4227 if (arg->soft_match)
4229 as_bad (_("Operand %d of `%s' must be constant"),
4230 arg->argnum, arg->insn->insn_mo->name);
4236 /* Return the RTYPE_* flags for a register operand of type TYPE that
4237 appears in instruction OPCODE. */
4240 convert_reg_type (const struct mips_opcode *opcode,
4241 enum mips_reg_operand_type type)
4246 return RTYPE_NUM | RTYPE_GP;
4249 /* Allow vector register names for MDMX if the instruction is a 64-bit
4250 FPR load, store or move (including moves to and from GPRs). */
4251 if ((mips_opts.ase & ASE_MDMX)
4252 && (opcode->pinfo & FP_D)
4253 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4254 | INSN_COPROC_MEMORY_DELAY
4255 | INSN_LOAD_COPROC_DELAY
4256 | INSN_LOAD_MEMORY_DELAY
4257 | INSN_STORE_MEMORY)))
4258 return RTYPE_FPU | RTYPE_VEC;
4262 if (opcode->pinfo & (FP_D | FP_S))
4263 return RTYPE_CCC | RTYPE_FCC;
4267 if (opcode->membership & INSN_5400)
4269 return RTYPE_FPU | RTYPE_VEC;
4275 if (opcode->name[strlen (opcode->name) - 1] == '0')
4276 return RTYPE_NUM | RTYPE_CP0;
4283 return RTYPE_NUM | RTYPE_VI;
4286 return RTYPE_NUM | RTYPE_VF;
4288 case OP_REG_R5900_I:
4289 return RTYPE_R5900_I;
4291 case OP_REG_R5900_Q:
4292 return RTYPE_R5900_Q;
4294 case OP_REG_R5900_R:
4295 return RTYPE_R5900_R;
4297 case OP_REG_R5900_ACC:
4298 return RTYPE_R5900_ACC;
4303 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4306 check_regno (struct mips_arg_info *arg,
4307 enum mips_reg_operand_type type, unsigned int regno)
4309 if (AT && type == OP_REG_GP && regno == AT)
4310 arg->seen_at = TRUE;
4312 if (type == OP_REG_FP
4315 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4316 as_warn (_("Float register should be even, was %d"), regno);
4318 if (type == OP_REG_CCC)
4323 name = arg->insn->insn_mo->name;
4324 length = strlen (name);
4325 if ((regno & 1) != 0
4326 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4327 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4328 as_warn (_("Condition code register should be even for %s, was %d"),
4331 if ((regno & 3) != 0
4332 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4333 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4338 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4339 a register of type TYPE. Return true on success, storing the register
4340 number in *REGNO and warning about any dubious uses. */
4343 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4344 unsigned int symval, unsigned int *regno)
4346 if (type == OP_REG_VEC)
4347 symval = mips_prefer_vec_regno (symval);
4348 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4351 *regno = symval & RNUM_MASK;
4352 check_regno (arg, type, *regno);
4356 /* Try to interpret the next token in ARG as a register of type TYPE.
4357 Consume the token and return true on success, storing the register
4358 number in *REGNO. Return false on failure. */
4361 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4362 unsigned int *regno)
4364 if (arg->token->type == OT_REG
4365 && match_regno (arg, type, arg->token->u.regno, regno))
4373 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4374 Consume the token and return true on success, storing the register numbers
4375 in *REGNO1 and *REGNO2. Return false on failure. */
4378 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4379 unsigned int *regno1, unsigned int *regno2)
4381 if (match_reg (arg, type, regno1))
4386 if (arg->token->type == OT_REG_RANGE
4387 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4388 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4389 && *regno1 <= *regno2)
4397 /* OP_INT matcher. */
4400 match_int_operand (struct mips_arg_info *arg,
4401 const struct mips_operand *operand_base)
4403 const struct mips_int_operand *operand;
4405 int min_val, max_val, factor;
4407 bfd_boolean print_hex;
4409 operand = (const struct mips_int_operand *) operand_base;
4410 factor = 1 << operand->shift;
4411 min_val = mips_int_operand_min (operand);
4412 max_val = mips_int_operand_max (operand);
4414 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4416 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4417 /* Assume we have an elided offset. The later match will fail
4418 if this turns out to be wrong. */
4420 else if (operand_base->lsb == 0
4421 && operand_base->size == 16
4422 && operand->shift == 0
4423 && operand->bias == 0
4424 && (operand->max_val == 32767 || operand->max_val == 65535))
4426 /* The operand can be relocated. */
4427 if (!match_expression (arg, &offset_expr, offset_reloc))
4430 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4431 /* Relocation operators were used. Accept the arguent and
4432 leave the relocation value in offset_expr and offset_relocs
4433 for the caller to process. */
4436 if (offset_expr.X_op != O_constant)
4438 /* If non-constant operands are allowed then leave them for
4439 the caller to process, otherwise fail the match. */
4440 if (!arg->allow_nonconst)
4442 offset_reloc[0] = BFD_RELOC_LO16;
4446 /* Clear the global state; we're going to install the operand
4448 sval = offset_expr.X_add_number;
4449 offset_expr.X_op = O_absent;
4453 if (!match_const_int (arg, &sval, min_val))
4457 arg->last_op_int = sval;
4459 /* Check the range. If there's a problem, record the lowest acceptable
4460 value in arg->last_op_int in order to prevent an unhelpful error
4463 Bit counts have traditionally been printed in hex by the disassembler
4464 but printed as decimal in error messages. Only resort to hex if
4465 the operand is bigger than 6 bits. */
4466 print_hex = operand->print_hex && operand_base->size > 6;
4467 if (sval < min_val || sval > max_val)
4469 if (arg->soft_match)
4471 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
4473 arg->last_op_int = min_val;
4475 else if (sval % factor)
4477 if (arg->soft_match)
4479 as_bad (print_hex && sval >= 0
4480 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4481 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4482 arg->argnum, arg->insn->insn_mo->name, factor,
4483 (unsigned long) sval);
4484 arg->last_op_int = min_val;
4487 uval = (unsigned int) sval >> operand->shift;
4488 uval -= operand->bias;
4490 /* Handle -mfix-cn63xxp1. */
4492 && mips_fix_cn63xxp1
4493 && !mips_opts.micromips
4494 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4509 /* The rest must be changed to 28. */
4514 insn_insert_operand (arg->insn, operand_base, uval);
4518 /* OP_MAPPED_INT matcher. */
4521 match_mapped_int_operand (struct mips_arg_info *arg,
4522 const struct mips_operand *operand_base)
4524 const struct mips_mapped_int_operand *operand;
4525 unsigned int uval, num_vals;
4528 operand = (const struct mips_mapped_int_operand *) operand_base;
4529 if (!match_const_int (arg, &sval, operand->int_map[0]))
4532 num_vals = 1 << operand_base->size;
4533 for (uval = 0; uval < num_vals; uval++)
4534 if (operand->int_map[uval] == sval)
4536 if (uval == num_vals)
4539 insn_insert_operand (arg->insn, operand_base, uval);
4543 /* OP_MSB matcher. */
4546 match_msb_operand (struct mips_arg_info *arg,
4547 const struct mips_operand *operand_base)
4549 const struct mips_msb_operand *operand;
4550 int min_val, max_val, max_high;
4551 offsetT size, sval, high;
4553 operand = (const struct mips_msb_operand *) operand_base;
4554 min_val = operand->bias;
4555 max_val = min_val + (1 << operand_base->size) - 1;
4556 max_high = operand->opsize;
4558 if (!match_const_int (arg, &size, 1))
4561 high = size + arg->last_op_int;
4562 sval = operand->add_lsb ? high : size;
4564 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4566 if (arg->soft_match)
4568 report_bad_field (arg->last_op_int, size);
4571 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4575 /* OP_REG matcher. */
4578 match_reg_operand (struct mips_arg_info *arg,
4579 const struct mips_operand *operand_base)
4581 const struct mips_reg_operand *operand;
4582 unsigned int regno, uval, num_vals;
4584 operand = (const struct mips_reg_operand *) operand_base;
4585 if (!match_reg (arg, operand->reg_type, ®no))
4588 if (operand->reg_map)
4590 num_vals = 1 << operand->root.size;
4591 for (uval = 0; uval < num_vals; uval++)
4592 if (operand->reg_map[uval] == regno)
4594 if (num_vals == uval)
4600 arg->last_regno = regno;
4601 if (arg->opnum == 1)
4602 arg->dest_regno = regno;
4603 insn_insert_operand (arg->insn, operand_base, uval);
4607 /* OP_REG_PAIR matcher. */
4610 match_reg_pair_operand (struct mips_arg_info *arg,
4611 const struct mips_operand *operand_base)
4613 const struct mips_reg_pair_operand *operand;
4614 unsigned int regno1, regno2, uval, num_vals;
4616 operand = (const struct mips_reg_pair_operand *) operand_base;
4617 if (!match_reg (arg, operand->reg_type, ®no1)
4618 || !match_char (arg, ',')
4619 || !match_reg (arg, operand->reg_type, ®no2))
4622 num_vals = 1 << operand_base->size;
4623 for (uval = 0; uval < num_vals; uval++)
4624 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4626 if (uval == num_vals)
4629 insn_insert_operand (arg->insn, operand_base, uval);
4633 /* OP_PCREL matcher. The caller chooses the relocation type. */
4636 match_pcrel_operand (struct mips_arg_info *arg)
4638 bfd_reloc_code_real_type r[3];
4640 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4643 /* OP_PERF_REG matcher. */
4646 match_perf_reg_operand (struct mips_arg_info *arg,
4647 const struct mips_operand *operand)
4651 if (!match_const_int (arg, &sval, 0))
4656 || (mips_opts.arch == CPU_R5900
4657 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4658 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4660 if (arg->soft_match)
4662 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4665 insn_insert_operand (arg->insn, operand, sval);
4669 /* OP_ADDIUSP matcher. */
4672 match_addiusp_operand (struct mips_arg_info *arg,
4673 const struct mips_operand *operand)
4678 if (!match_const_int (arg, &sval, -256))
4685 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4688 uval = (unsigned int) sval;
4689 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4690 insn_insert_operand (arg->insn, operand, uval);
4694 /* OP_CLO_CLZ_DEST matcher. */
4697 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4698 const struct mips_operand *operand)
4702 if (!match_reg (arg, OP_REG_GP, ®no))
4705 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4709 /* OP_LWM_SWM_LIST matcher. */
4712 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4713 const struct mips_operand *operand)
4715 unsigned int reglist, sregs, ra, regno1, regno2;
4716 struct mips_arg_info reset;
4719 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4723 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4728 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4731 while (match_char (arg, ',')
4732 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4735 if (operand->size == 2)
4737 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4743 and any permutations of these. */
4744 if ((reglist & 0xfff1ffff) != 0x80010000)
4747 sregs = (reglist >> 17) & 7;
4752 /* The list must include at least one of ra and s0-sN,
4753 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4754 which are $23 and $30 respectively.) E.g.:
4762 and any permutations of these. */
4763 if ((reglist & 0x3f00ffff) != 0)
4766 ra = (reglist >> 27) & 0x10;
4767 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4770 if ((sregs & -sregs) != sregs)
4773 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4777 /* OP_ENTRY_EXIT_LIST matcher. */
4780 match_entry_exit_operand (struct mips_arg_info *arg,
4781 const struct mips_operand *operand)
4784 bfd_boolean is_exit;
4786 /* The format is the same for both ENTRY and EXIT, but the constraints
4788 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4789 mask = (is_exit ? 7 << 3 : 0);
4792 unsigned int regno1, regno2;
4793 bfd_boolean is_freg;
4795 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4797 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4802 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4805 mask |= (5 + regno2) << 3;
4807 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4808 mask |= (regno2 - 3) << 3;
4809 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4810 mask |= (regno2 - 15) << 1;
4811 else if (regno1 == RA && regno2 == RA)
4816 while (match_char (arg, ','));
4818 insn_insert_operand (arg->insn, operand, mask);
4822 /* OP_SAVE_RESTORE_LIST matcher. */
4825 match_save_restore_list_operand (struct mips_arg_info *arg)
4827 unsigned int opcode, args, statics, sregs;
4828 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4833 opcode = arg->insn->insn_opcode;
4835 num_frame_sizes = 0;
4841 unsigned int regno1, regno2;
4843 if (arg->token->type == OT_INTEGER)
4845 /* Handle the frame size. */
4846 if (!match_const_int (arg, &frame_size, 0))
4848 num_frame_sizes += 1;
4852 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4855 while (regno1 <= regno2)
4857 if (regno1 >= 4 && regno1 <= 7)
4859 if (num_frame_sizes == 0)
4861 args |= 1 << (regno1 - 4);
4863 /* statics $a0-$a3 */
4864 statics |= 1 << (regno1 - 4);
4866 else if (regno1 >= 16 && regno1 <= 23)
4868 sregs |= 1 << (regno1 - 16);
4869 else if (regno1 == 30)
4872 else if (regno1 == 31)
4873 /* Add $ra to insn. */
4883 while (match_char (arg, ','));
4885 /* Encode args/statics combination. */
4888 else if (args == 0xf)
4889 /* All $a0-$a3 are args. */
4890 opcode |= MIPS16_ALL_ARGS << 16;
4891 else if (statics == 0xf)
4892 /* All $a0-$a3 are statics. */
4893 opcode |= MIPS16_ALL_STATICS << 16;
4896 /* Count arg registers. */
4906 /* Count static registers. */
4908 while (statics & 0x8)
4910 statics = (statics << 1) & 0xf;
4916 /* Encode args/statics. */
4917 opcode |= ((num_args << 2) | num_statics) << 16;
4920 /* Encode $s0/$s1. */
4921 if (sregs & (1 << 0)) /* $s0 */
4923 if (sregs & (1 << 1)) /* $s1 */
4927 /* Encode $s2-$s8. */
4936 opcode |= num_sregs << 24;
4938 /* Encode frame size. */
4939 if (num_frame_sizes == 0)
4940 error = _("Missing frame size");
4941 else if (num_frame_sizes > 1)
4942 error = _("Frame size specified twice");
4943 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4944 error = _("Invalid frame size");
4945 else if (frame_size != 128 || (opcode >> 16) != 0)
4948 opcode |= (((frame_size & 0xf0) << 16)
4949 | (frame_size & 0x0f));
4954 if (arg->soft_match)
4956 as_bad ("%s", error);
4959 /* Finally build the instruction. */
4960 if ((opcode >> 16) != 0 || frame_size == 0)
4961 opcode |= MIPS16_EXTEND;
4962 arg->insn->insn_opcode = opcode;
4966 /* OP_MDMX_IMM_REG matcher. */
4969 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
4970 const struct mips_operand *operand)
4972 unsigned int regno, uval;
4974 const struct mips_opcode *opcode;
4976 /* The mips_opcode records whether this is an octobyte or quadhalf
4977 instruction. Start out with that bit in place. */
4978 opcode = arg->insn->insn_mo;
4979 uval = mips_extract_operand (operand, opcode->match);
4980 is_qh = (uval != 0);
4982 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
4984 if ((opcode->membership & INSN_5400)
4985 && strcmp (opcode->name, "rzu.ob") == 0)
4987 if (arg->soft_match)
4989 as_bad (_("Operand %d of `%s' must be an immediate"),
4990 arg->argnum, opcode->name);
4993 /* Check whether this is a vector register or a broadcast of
4994 a single element. */
4995 if (arg->token->type == OT_REG_ELEMENT)
4997 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
5000 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
5002 if (arg->soft_match)
5004 as_bad (_("Invalid element selector"));
5007 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
5011 /* A full vector. */
5012 if ((opcode->membership & INSN_5400)
5013 && (strcmp (opcode->name, "sll.ob") == 0
5014 || strcmp (opcode->name, "srl.ob") == 0))
5016 if (arg->soft_match)
5018 as_bad (_("Operand %d of `%s' must be scalar"),
5019 arg->argnum, opcode->name);
5022 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5025 uval |= MDMX_FMTSEL_VEC_QH << 5;
5027 uval |= MDMX_FMTSEL_VEC_OB << 5;
5036 if (!match_const_int (arg, &sval, 0))
5038 if (sval < 0 || sval > 31)
5040 if (arg->soft_match)
5042 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
5044 uval |= (sval & 31);
5046 uval |= MDMX_FMTSEL_IMM_QH << 5;
5048 uval |= MDMX_FMTSEL_IMM_OB << 5;
5050 insn_insert_operand (arg->insn, operand, uval);
5054 /* OP_PC matcher. */
5057 match_pc_operand (struct mips_arg_info *arg)
5059 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5067 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5068 register that we need to match. */
5071 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5075 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5078 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5079 the length of the value in bytes (4 for float, 8 for double) and
5080 USING_GPRS says whether the destination is a GPR rather than an FPR.
5082 Return the constant in IMM and OFFSET as follows:
5084 - If the constant should be loaded via memory, set IMM to O_absent and
5085 OFFSET to the memory address.
5087 - Otherwise, if the constant should be loaded into two 32-bit registers,
5088 set IMM to the O_constant to load into the high register and OFFSET
5089 to the corresponding value for the low register.
5091 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5093 These constants only appear as the last operand in an instruction,
5094 and every instruction that accepts them in any variant accepts them
5095 in all variants. This means we don't have to worry about backing out
5096 any changes if the instruction does not match. We just match
5097 unconditionally and report an error if the constant is invalid. */
5100 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5101 expressionS *offset, int length, bfd_boolean using_gprs)
5106 const char *newname;
5107 unsigned char *data;
5109 /* Where the constant is placed is based on how the MIPS assembler
5112 length == 4 && using_gprs -- immediate value only
5113 length == 8 && using_gprs -- .rdata or immediate value
5114 length == 4 && !using_gprs -- .lit4 or immediate value
5115 length == 8 && !using_gprs -- .lit8 or immediate value
5117 The .lit4 and .lit8 sections are only used if permitted by the
5119 if (arg->token->type != OT_FLOAT)
5122 gas_assert (arg->token->u.flt.length == length);
5123 data = arg->token->u.flt.data;
5126 /* Handle 32-bit constants for which an immediate value is best. */
5129 || g_switch_value < 4
5130 || (data[0] == 0 && data[1] == 0)
5131 || (data[2] == 0 && data[3] == 0)))
5133 imm->X_op = O_constant;
5134 if (!target_big_endian)
5135 imm->X_add_number = bfd_getl32 (data);
5137 imm->X_add_number = bfd_getb32 (data);
5138 offset->X_op = O_absent;
5142 /* Handle 64-bit constants for which an immediate value is best. */
5144 && !mips_disable_float_construction
5145 /* Constants can only be constructed in GPRs and copied
5146 to FPRs if the GPRs are at least as wide as the FPRs.
5147 Force the constant into memory if we are using 64-bit FPRs
5148 but the GPRs are only 32 bits wide. */
5149 /* ??? No longer true with the addition of MTHC1, but this
5150 is legacy code... */
5151 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5152 && ((data[0] == 0 && data[1] == 0)
5153 || (data[2] == 0 && data[3] == 0))
5154 && ((data[4] == 0 && data[5] == 0)
5155 || (data[6] == 0 && data[7] == 0)))
5157 /* The value is simple enough to load with a couple of instructions.
5158 If using 32-bit registers, set IMM to the high order 32 bits and
5159 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5161 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5163 imm->X_op = O_constant;
5164 offset->X_op = O_constant;
5165 if (!target_big_endian)
5167 imm->X_add_number = bfd_getl32 (data + 4);
5168 offset->X_add_number = bfd_getl32 (data);
5172 imm->X_add_number = bfd_getb32 (data);
5173 offset->X_add_number = bfd_getb32 (data + 4);
5175 if (offset->X_add_number == 0)
5176 offset->X_op = O_absent;
5180 imm->X_op = O_constant;
5181 if (!target_big_endian)
5182 imm->X_add_number = bfd_getl64 (data);
5184 imm->X_add_number = bfd_getb64 (data);
5185 offset->X_op = O_absent;
5190 /* Switch to the right section. */
5192 subseg = now_subseg;
5195 gas_assert (!using_gprs && g_switch_value >= 4);
5200 if (using_gprs || g_switch_value < 8)
5201 newname = RDATA_SECTION_NAME;
5206 new_seg = subseg_new (newname, (subsegT) 0);
5207 bfd_set_section_flags (stdoutput, new_seg,
5208 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5209 frag_align (length == 4 ? 2 : 3, 0, 0);
5210 if (strncmp (TARGET_OS, "elf", 3) != 0)
5211 record_alignment (new_seg, 4);
5213 record_alignment (new_seg, length == 4 ? 2 : 3);
5215 as_bad (_("Can't use floating point insn in this section"));
5217 /* Set the argument to the current address in the section. */
5218 imm->X_op = O_absent;
5219 offset->X_op = O_symbol;
5220 offset->X_add_symbol = symbol_temp_new_now ();
5221 offset->X_add_number = 0;
5223 /* Put the floating point number into the section. */
5224 p = frag_more (length);
5225 memcpy (p, data, length);
5227 /* Switch back to the original section. */
5228 subseg_set (seg, subseg);
5232 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5236 match_vu0_suffix_operand (struct mips_arg_info *arg,
5237 const struct mips_operand *operand,
5238 bfd_boolean match_p)
5242 /* The operand can be an XYZW mask or a single 2-bit channel index
5243 (with X being 0). */
5244 gas_assert (operand->size == 2 || operand->size == 4);
5246 /* The suffix can be omitted when it is already part of the opcode. */
5247 if (arg->token->type != OT_CHANNELS)
5250 uval = arg->token->u.channels;
5251 if (operand->size == 2)
5253 /* Check that a single bit is set and convert it into a 2-bit index. */
5254 if ((uval & -uval) != uval)
5256 uval = 4 - ffs (uval);
5259 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5264 insn_insert_operand (arg->insn, operand, uval);
5268 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5269 of the argument text if the match is successful, otherwise return null. */
5272 match_operand (struct mips_arg_info *arg,
5273 const struct mips_operand *operand)
5275 switch (operand->type)
5278 return match_int_operand (arg, operand);
5281 return match_mapped_int_operand (arg, operand);
5284 return match_msb_operand (arg, operand);
5287 case OP_OPTIONAL_REG:
5288 return match_reg_operand (arg, operand);
5291 return match_reg_pair_operand (arg, operand);
5294 return match_pcrel_operand (arg);
5297 return match_perf_reg_operand (arg, operand);
5299 case OP_ADDIUSP_INT:
5300 return match_addiusp_operand (arg, operand);
5302 case OP_CLO_CLZ_DEST:
5303 return match_clo_clz_dest_operand (arg, operand);
5305 case OP_LWM_SWM_LIST:
5306 return match_lwm_swm_list_operand (arg, operand);
5308 case OP_ENTRY_EXIT_LIST:
5309 return match_entry_exit_operand (arg, operand);
5311 case OP_SAVE_RESTORE_LIST:
5312 return match_save_restore_list_operand (arg);
5314 case OP_MDMX_IMM_REG:
5315 return match_mdmx_imm_reg_operand (arg, operand);
5317 case OP_REPEAT_DEST_REG:
5318 return match_tied_reg_operand (arg, arg->dest_regno);
5320 case OP_REPEAT_PREV_REG:
5321 return match_tied_reg_operand (arg, arg->last_regno);
5324 return match_pc_operand (arg);
5327 return match_vu0_suffix_operand (arg, operand, FALSE);
5329 case OP_VU0_MATCH_SUFFIX:
5330 return match_vu0_suffix_operand (arg, operand, TRUE);
5335 /* ARG is the state after successfully matching an instruction.
5336 Issue any queued-up warnings. */
5339 check_completed_insn (struct mips_arg_info *arg)
5344 as_warn (_("Used $at without \".set noat\""));
5346 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5350 /* Return true if modifying general-purpose register REG needs a delay. */
5353 reg_needs_delay (unsigned int reg)
5355 unsigned long prev_pinfo;
5357 prev_pinfo = history[0].insn_mo->pinfo;
5358 if (!mips_opts.noreorder
5359 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5360 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5361 && (gpr_write_mask (&history[0]) & (1 << reg)))
5367 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5368 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5369 by VR4120 errata. */
5372 classify_vr4120_insn (const char *name)
5374 if (strncmp (name, "macc", 4) == 0)
5375 return FIX_VR4120_MACC;
5376 if (strncmp (name, "dmacc", 5) == 0)
5377 return FIX_VR4120_DMACC;
5378 if (strncmp (name, "mult", 4) == 0)
5379 return FIX_VR4120_MULT;
5380 if (strncmp (name, "dmult", 5) == 0)
5381 return FIX_VR4120_DMULT;
5382 if (strstr (name, "div"))
5383 return FIX_VR4120_DIV;
5384 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5385 return FIX_VR4120_MTHILO;
5386 return NUM_FIX_VR4120_CLASSES;
5389 #define INSN_ERET 0x42000018
5390 #define INSN_DERET 0x4200001f
5392 /* Return the number of instructions that must separate INSN1 and INSN2,
5393 where INSN1 is the earlier instruction. Return the worst-case value
5394 for any INSN2 if INSN2 is null. */
5397 insns_between (const struct mips_cl_insn *insn1,
5398 const struct mips_cl_insn *insn2)
5400 unsigned long pinfo1, pinfo2;
5403 /* If INFO2 is null, pessimistically assume that all flags are set for
5404 the second instruction. */
5405 pinfo1 = insn1->insn_mo->pinfo;
5406 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5408 /* For most targets, write-after-read dependencies on the HI and LO
5409 registers must be separated by at least two instructions. */
5410 if (!hilo_interlocks)
5412 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5414 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5418 /* If we're working around r7000 errata, there must be two instructions
5419 between an mfhi or mflo and any instruction that uses the result. */
5420 if (mips_7000_hilo_fix
5421 && !mips_opts.micromips
5422 && MF_HILO_INSN (pinfo1)
5423 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5426 /* If we're working around 24K errata, one instruction is required
5427 if an ERET or DERET is followed by a branch instruction. */
5428 if (mips_fix_24k && !mips_opts.micromips)
5430 if (insn1->insn_opcode == INSN_ERET
5431 || insn1->insn_opcode == INSN_DERET)
5434 || insn2->insn_opcode == INSN_ERET
5435 || insn2->insn_opcode == INSN_DERET
5436 || delayed_branch_p (insn2))
5441 /* If working around VR4120 errata, check for combinations that need
5442 a single intervening instruction. */
5443 if (mips_fix_vr4120 && !mips_opts.micromips)
5445 unsigned int class1, class2;
5447 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5448 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5452 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5453 if (vr4120_conflicts[class1] & (1 << class2))
5458 if (!HAVE_CODE_COMPRESSION)
5460 /* Check for GPR or coprocessor load delays. All such delays
5461 are on the RT register. */
5462 /* Itbl support may require additional care here. */
5463 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5464 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5466 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5470 /* Check for generic coprocessor hazards.
5472 This case is not handled very well. There is no special
5473 knowledge of CP0 handling, and the coprocessors other than
5474 the floating point unit are not distinguished at all. */
5475 /* Itbl support may require additional care here. FIXME!
5476 Need to modify this to include knowledge about
5477 user specified delays! */
5478 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5479 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5481 /* Handle cases where INSN1 writes to a known general coprocessor
5482 register. There must be a one instruction delay before INSN2
5483 if INSN2 reads that register, otherwise no delay is needed. */
5484 mask = fpr_write_mask (insn1);
5487 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5492 /* Read-after-write dependencies on the control registers
5493 require a two-instruction gap. */
5494 if ((pinfo1 & INSN_WRITE_COND_CODE)
5495 && (pinfo2 & INSN_READ_COND_CODE))
5498 /* We don't know exactly what INSN1 does. If INSN2 is
5499 also a coprocessor instruction, assume there must be
5500 a one instruction gap. */
5501 if (pinfo2 & INSN_COP)
5506 /* Check for read-after-write dependencies on the coprocessor
5507 control registers in cases where INSN1 does not need a general
5508 coprocessor delay. This means that INSN1 is a floating point
5509 comparison instruction. */
5510 /* Itbl support may require additional care here. */
5511 else if (!cop_interlocks
5512 && (pinfo1 & INSN_WRITE_COND_CODE)
5513 && (pinfo2 & INSN_READ_COND_CODE))
5520 /* Return the number of nops that would be needed to work around the
5521 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5522 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5523 that are contained within the first IGNORE instructions of HIST. */
5526 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5527 const struct mips_cl_insn *insn)
5532 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5533 are not affected by the errata. */
5535 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5536 || strcmp (insn->insn_mo->name, "mtlo") == 0
5537 || strcmp (insn->insn_mo->name, "mthi") == 0))
5540 /* Search for the first MFLO or MFHI. */
5541 for (i = 0; i < MAX_VR4130_NOPS; i++)
5542 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5544 /* Extract the destination register. */
5545 mask = gpr_write_mask (&hist[i]);
5547 /* No nops are needed if INSN reads that register. */
5548 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5551 /* ...or if any of the intervening instructions do. */
5552 for (j = 0; j < i; j++)
5553 if (gpr_read_mask (&hist[j]) & mask)
5557 return MAX_VR4130_NOPS - i;
5562 #define BASE_REG_EQ(INSN1, INSN2) \
5563 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5564 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5566 /* Return the minimum alignment for this store instruction. */
5569 fix_24k_align_to (const struct mips_opcode *mo)
5571 if (strcmp (mo->name, "sh") == 0)
5574 if (strcmp (mo->name, "swc1") == 0
5575 || strcmp (mo->name, "swc2") == 0
5576 || strcmp (mo->name, "sw") == 0
5577 || strcmp (mo->name, "sc") == 0
5578 || strcmp (mo->name, "s.s") == 0)
5581 if (strcmp (mo->name, "sdc1") == 0
5582 || strcmp (mo->name, "sdc2") == 0
5583 || strcmp (mo->name, "s.d") == 0)
5590 struct fix_24k_store_info
5592 /* Immediate offset, if any, for this store instruction. */
5594 /* Alignment required by this store instruction. */
5596 /* True for register offsets. */
5597 int register_offset;
5600 /* Comparison function used by qsort. */
5603 fix_24k_sort (const void *a, const void *b)
5605 const struct fix_24k_store_info *pos1 = a;
5606 const struct fix_24k_store_info *pos2 = b;
5608 return (pos1->off - pos2->off);
5611 /* INSN is a store instruction. Try to record the store information
5612 in STINFO. Return false if the information isn't known. */
5615 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5616 const struct mips_cl_insn *insn)
5618 /* The instruction must have a known offset. */
5619 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5622 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5623 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5627 /* Return the number of nops that would be needed to work around the 24k
5628 "lost data on stores during refill" errata if instruction INSN
5629 immediately followed the 2 instructions described by HIST.
5630 Ignore hazards that are contained within the first IGNORE
5631 instructions of HIST.
5633 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5634 for the data cache refills and store data. The following describes
5635 the scenario where the store data could be lost.
5637 * A data cache miss, due to either a load or a store, causing fill
5638 data to be supplied by the memory subsystem
5639 * The first three doublewords of fill data are returned and written
5641 * A sequence of four stores occurs in consecutive cycles around the
5642 final doubleword of the fill:
5646 * Zero, One or more instructions
5649 The four stores A-D must be to different doublewords of the line that
5650 is being filled. The fourth instruction in the sequence above permits
5651 the fill of the final doubleword to be transferred from the FSB into
5652 the cache. In the sequence above, the stores may be either integer
5653 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5654 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5655 different doublewords on the line. If the floating point unit is
5656 running in 1:2 mode, it is not possible to create the sequence above
5657 using only floating point store instructions.
5659 In this case, the cache line being filled is incorrectly marked
5660 invalid, thereby losing the data from any store to the line that
5661 occurs between the original miss and the completion of the five
5662 cycle sequence shown above.
5664 The workarounds are:
5666 * Run the data cache in write-through mode.
5667 * Insert a non-store instruction between
5668 Store A and Store B or Store B and Store C. */
5671 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5672 const struct mips_cl_insn *insn)
5674 struct fix_24k_store_info pos[3];
5675 int align, i, base_offset;
5680 /* If the previous instruction wasn't a store, there's nothing to
5682 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5685 /* If the instructions after the previous one are unknown, we have
5686 to assume the worst. */
5690 /* Check whether we are dealing with three consecutive stores. */
5691 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5692 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5695 /* If we don't know the relationship between the store addresses,
5696 assume the worst. */
5697 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5698 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5701 if (!fix_24k_record_store_info (&pos[0], insn)
5702 || !fix_24k_record_store_info (&pos[1], &hist[0])
5703 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5706 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5708 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5709 X bytes and such that the base register + X is known to be aligned
5712 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5716 align = pos[0].align_to;
5717 base_offset = pos[0].off;
5718 for (i = 1; i < 3; i++)
5719 if (align < pos[i].align_to)
5721 align = pos[i].align_to;
5722 base_offset = pos[i].off;
5724 for (i = 0; i < 3; i++)
5725 pos[i].off -= base_offset;
5728 pos[0].off &= ~align + 1;
5729 pos[1].off &= ~align + 1;
5730 pos[2].off &= ~align + 1;
5732 /* If any two stores write to the same chunk, they also write to the
5733 same doubleword. The offsets are still sorted at this point. */
5734 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5737 /* A range of at least 9 bytes is needed for the stores to be in
5738 non-overlapping doublewords. */
5739 if (pos[2].off - pos[0].off <= 8)
5742 if (pos[2].off - pos[1].off >= 24
5743 || pos[1].off - pos[0].off >= 24
5744 || pos[2].off - pos[0].off >= 32)
5750 /* Return the number of nops that would be needed if instruction INSN
5751 immediately followed the MAX_NOPS instructions given by HIST,
5752 where HIST[0] is the most recent instruction. Ignore hazards
5753 between INSN and the first IGNORE instructions in HIST.
5755 If INSN is null, return the worse-case number of nops for any
5759 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5760 const struct mips_cl_insn *insn)
5762 int i, nops, tmp_nops;
5765 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5767 tmp_nops = insns_between (hist + i, insn) - i;
5768 if (tmp_nops > nops)
5772 if (mips_fix_vr4130 && !mips_opts.micromips)
5774 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5775 if (tmp_nops > nops)
5779 if (mips_fix_24k && !mips_opts.micromips)
5781 tmp_nops = nops_for_24k (ignore, hist, insn);
5782 if (tmp_nops > nops)
5789 /* The variable arguments provide NUM_INSNS extra instructions that
5790 might be added to HIST. Return the largest number of nops that
5791 would be needed after the extended sequence, ignoring hazards
5792 in the first IGNORE instructions. */
5795 nops_for_sequence (int num_insns, int ignore,
5796 const struct mips_cl_insn *hist, ...)
5799 struct mips_cl_insn buffer[MAX_NOPS];
5800 struct mips_cl_insn *cursor;
5803 va_start (args, hist);
5804 cursor = buffer + num_insns;
5805 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5806 while (cursor > buffer)
5807 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5809 nops = nops_for_insn (ignore, buffer, NULL);
5814 /* Like nops_for_insn, but if INSN is a branch, take into account the
5815 worst-case delay for the branch target. */
5818 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5819 const struct mips_cl_insn *insn)
5823 nops = nops_for_insn (ignore, hist, insn);
5824 if (delayed_branch_p (insn))
5826 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5827 hist, insn, get_delay_slot_nop (insn));
5828 if (tmp_nops > nops)
5831 else if (compact_branch_p (insn))
5833 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5834 if (tmp_nops > nops)
5840 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5843 fix_loongson2f_nop (struct mips_cl_insn * ip)
5845 gas_assert (!HAVE_CODE_COMPRESSION);
5846 if (strcmp (ip->insn_mo->name, "nop") == 0)
5847 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5850 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5851 jr target pc &= 'hffff_ffff_cfff_ffff. */
5854 fix_loongson2f_jump (struct mips_cl_insn * ip)
5856 gas_assert (!HAVE_CODE_COMPRESSION);
5857 if (strcmp (ip->insn_mo->name, "j") == 0
5858 || strcmp (ip->insn_mo->name, "jr") == 0
5859 || strcmp (ip->insn_mo->name, "jalr") == 0)
5867 sreg = EXTRACT_OPERAND (0, RS, *ip);
5868 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5871 ep.X_op = O_constant;
5872 ep.X_add_number = 0xcfff0000;
5873 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5874 ep.X_add_number = 0xffff;
5875 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5876 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5881 fix_loongson2f (struct mips_cl_insn * ip)
5883 if (mips_fix_loongson2f_nop)
5884 fix_loongson2f_nop (ip);
5886 if (mips_fix_loongson2f_jump)
5887 fix_loongson2f_jump (ip);
5890 /* IP is a branch that has a delay slot, and we need to fill it
5891 automatically. Return true if we can do that by swapping IP
5892 with the previous instruction.
5893 ADDRESS_EXPR is an operand of the instruction to be used with
5897 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5898 bfd_reloc_code_real_type *reloc_type)
5900 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
5901 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5903 /* -O2 and above is required for this optimization. */
5904 if (mips_optimize < 2)
5907 /* If we have seen .set volatile or .set nomove, don't optimize. */
5908 if (mips_opts.nomove)
5911 /* We can't swap if the previous instruction's position is fixed. */
5912 if (history[0].fixed_p)
5915 /* If the previous previous insn was in a .set noreorder, we can't
5916 swap. Actually, the MIPS assembler will swap in this situation.
5917 However, gcc configured -with-gnu-as will generate code like
5925 in which we can not swap the bne and INSN. If gcc is not configured
5926 -with-gnu-as, it does not output the .set pseudo-ops. */
5927 if (history[1].noreorder_p)
5930 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5931 This means that the previous instruction was a 4-byte one anyhow. */
5932 if (mips_opts.mips16 && history[0].fixp[0])
5935 /* If the branch is itself the target of a branch, we can not swap.
5936 We cheat on this; all we check for is whether there is a label on
5937 this instruction. If there are any branches to anything other than
5938 a label, users must use .set noreorder. */
5939 if (seg_info (now_seg)->label_list)
5942 /* If the previous instruction is in a variant frag other than this
5943 branch's one, we cannot do the swap. This does not apply to
5944 MIPS16 code, which uses variant frags for different purposes. */
5945 if (!mips_opts.mips16
5947 && history[0].frag->fr_type == rs_machine_dependent)
5950 /* We do not swap with instructions that cannot architecturally
5951 be placed in a branch delay slot, such as SYNC or ERET. We
5952 also refrain from swapping with a trap instruction, since it
5953 complicates trap handlers to have the trap instruction be in
5955 prev_pinfo = history[0].insn_mo->pinfo;
5956 if (prev_pinfo & INSN_NO_DELAY_SLOT)
5959 /* Check for conflicts between the branch and the instructions
5960 before the candidate delay slot. */
5961 if (nops_for_insn (0, history + 1, ip) > 0)
5964 /* Check for conflicts between the swapped sequence and the
5965 target of the branch. */
5966 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5969 /* If the branch reads a register that the previous
5970 instruction sets, we can not swap. */
5971 gpr_read = gpr_read_mask (ip);
5972 prev_gpr_write = gpr_write_mask (&history[0]);
5973 if (gpr_read & prev_gpr_write)
5976 /* If the branch writes a register that the previous
5977 instruction sets, we can not swap. */
5978 gpr_write = gpr_write_mask (ip);
5979 if (gpr_write & prev_gpr_write)
5982 /* If the branch writes a register that the previous
5983 instruction reads, we can not swap. */
5984 prev_gpr_read = gpr_read_mask (&history[0]);
5985 if (gpr_write & prev_gpr_read)
5988 /* If one instruction sets a condition code and the
5989 other one uses a condition code, we can not swap. */
5990 pinfo = ip->insn_mo->pinfo;
5991 if ((pinfo & INSN_READ_COND_CODE)
5992 && (prev_pinfo & INSN_WRITE_COND_CODE))
5994 if ((pinfo & INSN_WRITE_COND_CODE)
5995 && (prev_pinfo & INSN_READ_COND_CODE))
5998 /* If the previous instruction uses the PC, we can not swap. */
5999 prev_pinfo2 = history[0].insn_mo->pinfo2;
6000 if (prev_pinfo2 & INSN2_READ_PC)
6003 /* If the previous instruction has an incorrect size for a fixed
6004 branch delay slot in microMIPS mode, we cannot swap. */
6005 pinfo2 = ip->insn_mo->pinfo2;
6006 if (mips_opts.micromips
6007 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6008 && insn_length (history) != 2)
6010 if (mips_opts.micromips
6011 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6012 && insn_length (history) != 4)
6015 /* On R5900 short loops need to be fixed by inserting a nop in
6016 the branch delay slots.
6017 A short loop can be terminated too early. */
6018 if (mips_opts.arch == CPU_R5900
6019 /* Check if instruction has a parameter, ignore "j $31". */
6020 && (address_expr != NULL)
6021 /* Parameter must be 16 bit. */
6022 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6023 /* Branch to same segment. */
6024 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6025 /* Branch to same code fragment. */
6026 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6027 /* Can only calculate branch offset if value is known. */
6028 && symbol_constant_p(address_expr->X_add_symbol)
6029 /* Check if branch is really conditional. */
6030 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6031 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6032 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6035 /* Check if loop is shorter than 6 instructions including
6036 branch and delay slot. */
6037 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6044 /* When the loop includes branches or jumps,
6045 it is not a short loop. */
6046 for (i = 0; i < (distance / 4); i++)
6048 if ((history[i].cleared_p)
6049 || delayed_branch_p(&history[i]))
6057 /* Insert nop after branch to fix short loop. */
6066 /* Decide how we should add IP to the instruction stream.
6067 ADDRESS_EXPR is an operand of the instruction to be used with
6070 static enum append_method
6071 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6072 bfd_reloc_code_real_type *reloc_type)
6074 /* The relaxed version of a macro sequence must be inherently
6076 if (mips_relax.sequence == 2)
6079 /* We must not dabble with instructions in a ".set norerorder" block. */
6080 if (mips_opts.noreorder)
6083 /* Otherwise, it's our responsibility to fill branch delay slots. */
6084 if (delayed_branch_p (ip))
6086 if (!branch_likely_p (ip)
6087 && can_swap_branch_p (ip, address_expr, reloc_type))
6090 if (mips_opts.mips16
6091 && ISA_SUPPORTS_MIPS16E
6092 && gpr_read_mask (ip) != 0)
6093 return APPEND_ADD_COMPACT;
6095 return APPEND_ADD_WITH_NOP;
6101 /* IP is a MIPS16 instruction whose opcode we have just changed.
6102 Point IP->insn_mo to the new opcode's definition. */
6105 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6107 const struct mips_opcode *mo, *end;
6109 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6110 for (mo = ip->insn_mo; mo < end; mo++)
6111 if ((ip->insn_opcode & mo->mask) == mo->match)
6119 /* For microMIPS macros, we need to generate a local number label
6120 as the target of branches. */
6121 #define MICROMIPS_LABEL_CHAR '\037'
6122 static unsigned long micromips_target_label;
6123 static char micromips_target_name[32];
6126 micromips_label_name (void)
6128 char *p = micromips_target_name;
6129 char symbol_name_temporary[24];
6137 l = micromips_target_label;
6138 #ifdef LOCAL_LABEL_PREFIX
6139 *p++ = LOCAL_LABEL_PREFIX;
6142 *p++ = MICROMIPS_LABEL_CHAR;
6145 symbol_name_temporary[i++] = l % 10 + '0';
6150 *p++ = symbol_name_temporary[--i];
6153 return micromips_target_name;
6157 micromips_label_expr (expressionS *label_expr)
6159 label_expr->X_op = O_symbol;
6160 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6161 label_expr->X_add_number = 0;
6165 micromips_label_inc (void)
6167 micromips_target_label++;
6168 *micromips_target_name = '\0';
6172 micromips_add_label (void)
6176 s = colon (micromips_label_name ());
6177 micromips_label_inc ();
6178 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6181 /* If assembling microMIPS code, then return the microMIPS reloc
6182 corresponding to the requested one if any. Otherwise return
6183 the reloc unchanged. */
6185 static bfd_reloc_code_real_type
6186 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6188 static const bfd_reloc_code_real_type relocs[][2] =
6190 /* Keep sorted incrementally by the left-hand key. */
6191 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6192 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6193 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6194 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6195 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6196 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6197 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6198 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6199 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6200 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6201 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6202 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6203 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6204 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6205 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6206 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6207 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6208 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6209 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6210 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6211 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6212 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6213 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6214 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6215 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6216 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6217 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6219 bfd_reloc_code_real_type r;
6222 if (!mips_opts.micromips)
6224 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6230 return relocs[i][1];
6235 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6236 Return true on success, storing the resolved value in RESULT. */
6239 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6244 case BFD_RELOC_MIPS_HIGHEST:
6245 case BFD_RELOC_MICROMIPS_HIGHEST:
6246 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6249 case BFD_RELOC_MIPS_HIGHER:
6250 case BFD_RELOC_MICROMIPS_HIGHER:
6251 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6254 case BFD_RELOC_HI16_S:
6255 case BFD_RELOC_MICROMIPS_HI16_S:
6256 case BFD_RELOC_MIPS16_HI16_S:
6257 *result = ((operand + 0x8000) >> 16) & 0xffff;
6260 case BFD_RELOC_HI16:
6261 case BFD_RELOC_MICROMIPS_HI16:
6262 case BFD_RELOC_MIPS16_HI16:
6263 *result = (operand >> 16) & 0xffff;
6266 case BFD_RELOC_LO16:
6267 case BFD_RELOC_MICROMIPS_LO16:
6268 case BFD_RELOC_MIPS16_LO16:
6269 *result = operand & 0xffff;
6272 case BFD_RELOC_UNUSED:
6281 /* Output an instruction. IP is the instruction information.
6282 ADDRESS_EXPR is an operand of the instruction to be used with
6283 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6284 a macro expansion. */
6287 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6288 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6290 unsigned long prev_pinfo2, pinfo;
6291 bfd_boolean relaxed_branch = FALSE;
6292 enum append_method method;
6293 bfd_boolean relax32;
6296 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6297 fix_loongson2f (ip);
6299 file_ase_mips16 |= mips_opts.mips16;
6300 file_ase_micromips |= mips_opts.micromips;
6302 prev_pinfo2 = history[0].insn_mo->pinfo2;
6303 pinfo = ip->insn_mo->pinfo;
6305 if (mips_opts.micromips
6307 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6308 && micromips_insn_length (ip->insn_mo) != 2)
6309 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6310 && micromips_insn_length (ip->insn_mo) != 4)))
6311 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6312 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6314 if (address_expr == NULL)
6316 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6317 && reloc_type[1] == BFD_RELOC_UNUSED
6318 && reloc_type[2] == BFD_RELOC_UNUSED
6319 && address_expr->X_op == O_constant)
6321 switch (*reloc_type)
6323 case BFD_RELOC_MIPS_JMP:
6327 shift = mips_opts.micromips ? 1 : 2;
6328 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6329 as_bad (_("jump to misaligned address (0x%lx)"),
6330 (unsigned long) address_expr->X_add_number);
6331 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6337 case BFD_RELOC_MIPS16_JMP:
6338 if ((address_expr->X_add_number & 3) != 0)
6339 as_bad (_("jump to misaligned address (0x%lx)"),
6340 (unsigned long) address_expr->X_add_number);
6342 (((address_expr->X_add_number & 0x7c0000) << 3)
6343 | ((address_expr->X_add_number & 0xf800000) >> 7)
6344 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6348 case BFD_RELOC_16_PCREL_S2:
6352 shift = mips_opts.micromips ? 1 : 2;
6353 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6354 as_bad (_("branch to misaligned address (0x%lx)"),
6355 (unsigned long) address_expr->X_add_number);
6356 if (!mips_relax_branch)
6358 if ((address_expr->X_add_number + (1 << (shift + 15)))
6359 & ~((1 << (shift + 16)) - 1))
6360 as_bad (_("branch address range overflow (0x%lx)"),
6361 (unsigned long) address_expr->X_add_number);
6362 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6372 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6375 ip->insn_opcode |= value & 0xffff;
6383 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6385 /* There are a lot of optimizations we could do that we don't.
6386 In particular, we do not, in general, reorder instructions.
6387 If you use gcc with optimization, it will reorder
6388 instructions and generally do much more optimization then we
6389 do here; repeating all that work in the assembler would only
6390 benefit hand written assembly code, and does not seem worth
6392 int nops = (mips_optimize == 0
6393 ? nops_for_insn (0, history, NULL)
6394 : nops_for_insn_or_target (0, history, ip));
6398 unsigned long old_frag_offset;
6401 old_frag = frag_now;
6402 old_frag_offset = frag_now_fix ();
6404 for (i = 0; i < nops; i++)
6405 add_fixed_insn (NOP_INSN);
6406 insert_into_history (0, nops, NOP_INSN);
6410 listing_prev_line ();
6411 /* We may be at the start of a variant frag. In case we
6412 are, make sure there is enough space for the frag
6413 after the frags created by listing_prev_line. The
6414 argument to frag_grow here must be at least as large
6415 as the argument to all other calls to frag_grow in
6416 this file. We don't have to worry about being in the
6417 middle of a variant frag, because the variants insert
6418 all needed nop instructions themselves. */
6422 mips_move_text_labels ();
6424 #ifndef NO_ECOFF_DEBUGGING
6425 if (ECOFF_DEBUGGING)
6426 ecoff_fix_loc (old_frag, old_frag_offset);
6430 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6434 /* Work out how many nops in prev_nop_frag are needed by IP,
6435 ignoring hazards generated by the first prev_nop_frag_since
6437 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6438 gas_assert (nops <= prev_nop_frag_holds);
6440 /* Enforce NOPS as a minimum. */
6441 if (nops > prev_nop_frag_required)
6442 prev_nop_frag_required = nops;
6444 if (prev_nop_frag_holds == prev_nop_frag_required)
6446 /* Settle for the current number of nops. Update the history
6447 accordingly (for the benefit of any future .set reorder code). */
6448 prev_nop_frag = NULL;
6449 insert_into_history (prev_nop_frag_since,
6450 prev_nop_frag_holds, NOP_INSN);
6454 /* Allow this instruction to replace one of the nops that was
6455 tentatively added to prev_nop_frag. */
6456 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6457 prev_nop_frag_holds--;
6458 prev_nop_frag_since++;
6462 method = get_append_method (ip, address_expr, reloc_type);
6463 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6465 dwarf2_emit_insn (0);
6466 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6467 so "move" the instruction address accordingly.
6469 Also, it doesn't seem appropriate for the assembler to reorder .loc
6470 entries. If this instruction is a branch that we are going to swap
6471 with the previous instruction, the two instructions should be
6472 treated as a unit, and the debug information for both instructions
6473 should refer to the start of the branch sequence. Using the
6474 current position is certainly wrong when swapping a 32-bit branch
6475 and a 16-bit delay slot, since the current position would then be
6476 in the middle of a branch. */
6477 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6479 relax32 = (mips_relax_branch
6480 /* Don't try branch relaxation within .set nomacro, or within
6481 .set noat if we use $at for PIC computations. If it turns
6482 out that the branch was out-of-range, we'll get an error. */
6483 && !mips_opts.warn_about_macros
6484 && (mips_opts.at || mips_pic == NO_PIC)
6485 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6486 as they have no complementing branches. */
6487 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6489 if (!HAVE_CODE_COMPRESSION
6492 && *reloc_type == BFD_RELOC_16_PCREL_S2
6493 && delayed_branch_p (ip))
6495 relaxed_branch = TRUE;
6496 add_relaxed_insn (ip, (relaxed_branch_length
6498 uncond_branch_p (ip) ? -1
6499 : branch_likely_p (ip) ? 1
6503 uncond_branch_p (ip),
6504 branch_likely_p (ip),
6505 pinfo & INSN_WRITE_GPR_31,
6507 address_expr->X_add_symbol,
6508 address_expr->X_add_number);
6509 *reloc_type = BFD_RELOC_UNUSED;
6511 else if (mips_opts.micromips
6513 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6514 || *reloc_type > BFD_RELOC_UNUSED)
6515 && (delayed_branch_p (ip) || compact_branch_p (ip))
6516 /* Don't try branch relaxation when users specify
6517 16-bit/32-bit instructions. */
6518 && !forced_insn_length)
6520 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6521 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6522 int uncond = uncond_branch_p (ip) ? -1 : 0;
6523 int compact = compact_branch_p (ip);
6524 int al = pinfo & INSN_WRITE_GPR_31;
6527 gas_assert (address_expr != NULL);
6528 gas_assert (!mips_relax.sequence);
6530 relaxed_branch = TRUE;
6531 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6532 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6533 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6535 address_expr->X_add_symbol,
6536 address_expr->X_add_number);
6537 *reloc_type = BFD_RELOC_UNUSED;
6539 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6541 /* We need to set up a variant frag. */
6542 gas_assert (address_expr != NULL);
6543 add_relaxed_insn (ip, 4, 0,
6545 (*reloc_type - BFD_RELOC_UNUSED,
6546 forced_insn_length == 2, forced_insn_length == 4,
6547 delayed_branch_p (&history[0]),
6548 history[0].mips16_absolute_jump_p),
6549 make_expr_symbol (address_expr), 0);
6551 else if (mips_opts.mips16 && insn_length (ip) == 2)
6553 if (!delayed_branch_p (ip))
6554 /* Make sure there is enough room to swap this instruction with
6555 a following jump instruction. */
6557 add_fixed_insn (ip);
6561 if (mips_opts.mips16
6562 && mips_opts.noreorder
6563 && delayed_branch_p (&history[0]))
6564 as_warn (_("extended instruction in delay slot"));
6566 if (mips_relax.sequence)
6568 /* If we've reached the end of this frag, turn it into a variant
6569 frag and record the information for the instructions we've
6571 if (frag_room () < 4)
6572 relax_close_frag ();
6573 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6576 if (mips_relax.sequence != 2)
6578 if (mips_macro_warning.first_insn_sizes[0] == 0)
6579 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6580 mips_macro_warning.sizes[0] += insn_length (ip);
6581 mips_macro_warning.insns[0]++;
6583 if (mips_relax.sequence != 1)
6585 if (mips_macro_warning.first_insn_sizes[1] == 0)
6586 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6587 mips_macro_warning.sizes[1] += insn_length (ip);
6588 mips_macro_warning.insns[1]++;
6591 if (mips_opts.mips16)
6594 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6596 add_fixed_insn (ip);
6599 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6601 bfd_reloc_code_real_type final_type[3];
6602 reloc_howto_type *howto0;
6603 reloc_howto_type *howto;
6606 /* Perform any necessary conversion to microMIPS relocations
6607 and find out how many relocations there actually are. */
6608 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6609 final_type[i] = micromips_map_reloc (reloc_type[i]);
6611 /* In a compound relocation, it is the final (outermost)
6612 operator that determines the relocated field. */
6613 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6618 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6619 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6620 bfd_get_reloc_size (howto),
6622 howto0 && howto0->pc_relative,
6625 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6626 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6627 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6629 /* These relocations can have an addend that won't fit in
6630 4 octets for 64bit assembly. */
6632 && ! howto->partial_inplace
6633 && (reloc_type[0] == BFD_RELOC_16
6634 || reloc_type[0] == BFD_RELOC_32
6635 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6636 || reloc_type[0] == BFD_RELOC_GPREL16
6637 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6638 || reloc_type[0] == BFD_RELOC_GPREL32
6639 || reloc_type[0] == BFD_RELOC_64
6640 || reloc_type[0] == BFD_RELOC_CTOR
6641 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6642 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6643 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6644 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6645 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6646 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6647 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6648 || hi16_reloc_p (reloc_type[0])
6649 || lo16_reloc_p (reloc_type[0])))
6650 ip->fixp[0]->fx_no_overflow = 1;
6652 /* These relocations can have an addend that won't fit in 2 octets. */
6653 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6654 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6655 ip->fixp[0]->fx_no_overflow = 1;
6657 if (mips_relax.sequence)
6659 if (mips_relax.first_fixup == 0)
6660 mips_relax.first_fixup = ip->fixp[0];
6662 else if (reloc_needs_lo_p (*reloc_type))
6664 struct mips_hi_fixup *hi_fixup;
6666 /* Reuse the last entry if it already has a matching %lo. */
6667 hi_fixup = mips_hi_fixup_list;
6669 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6671 hi_fixup = ((struct mips_hi_fixup *)
6672 xmalloc (sizeof (struct mips_hi_fixup)));
6673 hi_fixup->next = mips_hi_fixup_list;
6674 mips_hi_fixup_list = hi_fixup;
6676 hi_fixup->fixp = ip->fixp[0];
6677 hi_fixup->seg = now_seg;
6680 /* Add fixups for the second and third relocations, if given.
6681 Note that the ABI allows the second relocation to be
6682 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6683 moment we only use RSS_UNDEF, but we could add support
6684 for the others if it ever becomes necessary. */
6685 for (i = 1; i < 3; i++)
6686 if (reloc_type[i] != BFD_RELOC_UNUSED)
6688 ip->fixp[i] = fix_new (ip->frag, ip->where,
6689 ip->fixp[0]->fx_size, NULL, 0,
6690 FALSE, final_type[i]);
6692 /* Use fx_tcbit to mark compound relocs. */
6693 ip->fixp[0]->fx_tcbit = 1;
6694 ip->fixp[i]->fx_tcbit = 1;
6699 /* Update the register mask information. */
6700 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6701 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6706 insert_into_history (0, 1, ip);
6709 case APPEND_ADD_WITH_NOP:
6711 struct mips_cl_insn *nop;
6713 insert_into_history (0, 1, ip);
6714 nop = get_delay_slot_nop (ip);
6715 add_fixed_insn (nop);
6716 insert_into_history (0, 1, nop);
6717 if (mips_relax.sequence)
6718 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6722 case APPEND_ADD_COMPACT:
6723 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6724 gas_assert (mips_opts.mips16);
6725 ip->insn_opcode |= 0x0080;
6726 find_altered_mips16_opcode (ip);
6728 insert_into_history (0, 1, ip);
6733 struct mips_cl_insn delay = history[0];
6734 if (mips_opts.mips16)
6736 know (delay.frag == ip->frag);
6737 move_insn (ip, delay.frag, delay.where);
6738 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6740 else if (relaxed_branch || delay.frag != ip->frag)
6742 /* Add the delay slot instruction to the end of the
6743 current frag and shrink the fixed part of the
6744 original frag. If the branch occupies the tail of
6745 the latter, move it backwards to cover the gap. */
6746 delay.frag->fr_fix -= branch_disp;
6747 if (delay.frag == ip->frag)
6748 move_insn (ip, ip->frag, ip->where - branch_disp);
6749 add_fixed_insn (&delay);
6753 move_insn (&delay, ip->frag,
6754 ip->where - branch_disp + insn_length (ip));
6755 move_insn (ip, history[0].frag, history[0].where);
6759 insert_into_history (0, 1, &delay);
6764 /* If we have just completed an unconditional branch, clear the history. */
6765 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6766 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6770 mips_no_prev_insn ();
6772 for (i = 0; i < ARRAY_SIZE (history); i++)
6773 history[i].cleared_p = 1;
6776 /* We need to emit a label at the end of branch-likely macros. */
6777 if (emit_branch_likely_macro)
6779 emit_branch_likely_macro = FALSE;
6780 micromips_add_label ();
6783 /* We just output an insn, so the next one doesn't have a label. */
6784 mips_clear_insn_labels ();
6787 /* Forget that there was any previous instruction or label.
6788 When BRANCH is true, the branch history is also flushed. */
6791 mips_no_prev_insn (void)
6793 prev_nop_frag = NULL;
6794 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6795 mips_clear_insn_labels ();
6798 /* This function must be called before we emit something other than
6799 instructions. It is like mips_no_prev_insn except that it inserts
6800 any NOPS that might be needed by previous instructions. */
6803 mips_emit_delays (void)
6805 if (! mips_opts.noreorder)
6807 int nops = nops_for_insn (0, history, NULL);
6811 add_fixed_insn (NOP_INSN);
6812 mips_move_text_labels ();
6815 mips_no_prev_insn ();
6818 /* Start a (possibly nested) noreorder block. */
6821 start_noreorder (void)
6823 if (mips_opts.noreorder == 0)
6828 /* None of the instructions before the .set noreorder can be moved. */
6829 for (i = 0; i < ARRAY_SIZE (history); i++)
6830 history[i].fixed_p = 1;
6832 /* Insert any nops that might be needed between the .set noreorder
6833 block and the previous instructions. We will later remove any
6834 nops that turn out not to be needed. */
6835 nops = nops_for_insn (0, history, NULL);
6838 if (mips_optimize != 0)
6840 /* Record the frag which holds the nop instructions, so
6841 that we can remove them if we don't need them. */
6842 frag_grow (nops * NOP_INSN_SIZE);
6843 prev_nop_frag = frag_now;
6844 prev_nop_frag_holds = nops;
6845 prev_nop_frag_required = 0;
6846 prev_nop_frag_since = 0;
6849 for (; nops > 0; --nops)
6850 add_fixed_insn (NOP_INSN);
6852 /* Move on to a new frag, so that it is safe to simply
6853 decrease the size of prev_nop_frag. */
6854 frag_wane (frag_now);
6856 mips_move_text_labels ();
6858 mips_mark_labels ();
6859 mips_clear_insn_labels ();
6861 mips_opts.noreorder++;
6862 mips_any_noreorder = 1;
6865 /* End a nested noreorder block. */
6868 end_noreorder (void)
6870 mips_opts.noreorder--;
6871 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6873 /* Commit to inserting prev_nop_frag_required nops and go back to
6874 handling nop insertion the .set reorder way. */
6875 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
6877 insert_into_history (prev_nop_frag_since,
6878 prev_nop_frag_required, NOP_INSN);
6879 prev_nop_frag = NULL;
6883 /* Sign-extend 32-bit mode constants that have bit 31 set and all
6884 higher bits unset. */
6887 normalize_constant_expr (expressionS *ex)
6889 if (ex->X_op == O_constant
6890 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
6891 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
6895 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
6896 all higher bits unset. */
6899 normalize_address_expr (expressionS *ex)
6901 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
6902 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
6903 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
6904 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
6908 /* Try to match TOKENS against OPCODE, storing the result in INSN.
6909 Return true if the match was successful.
6911 OPCODE_EXTRA is a value that should be ORed into the opcode
6912 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
6913 there are more alternatives after OPCODE and SOFT_MATCH is
6914 as for mips_arg_info. */
6917 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
6918 struct mips_operand_token *tokens, unsigned int opcode_extra,
6919 bfd_boolean more_alts, bfd_boolean soft_match)
6922 struct mips_arg_info arg;
6923 const struct mips_operand *operand;
6926 imm_expr.X_op = O_absent;
6927 imm2_expr.X_op = O_absent;
6928 offset_expr.X_op = O_absent;
6929 offset_reloc[0] = BFD_RELOC_UNUSED;
6930 offset_reloc[1] = BFD_RELOC_UNUSED;
6931 offset_reloc[2] = BFD_RELOC_UNUSED;
6933 create_insn (insn, opcode);
6934 insn->insn_opcode |= opcode_extra;
6936 memset (&arg, 0, sizeof (arg));
6940 arg.last_regno = ILLEGAL_REG;
6941 arg.dest_regno = ILLEGAL_REG;
6942 arg.soft_match = soft_match;
6943 for (args = opcode->args;; ++args)
6945 if (arg.token->type == OT_END)
6947 /* Handle unary instructions in which only one operand is given.
6948 The source is then the same as the destination. */
6949 if (arg.opnum == 1 && *args == ',')
6951 operand = (mips_opts.micromips
6952 ? decode_micromips_operand (args + 1)
6953 : decode_mips_operand (args + 1));
6954 if (operand && mips_optional_operand_p (operand))
6962 /* Treat elided base registers as $0. */
6963 if (strcmp (args, "(b)") == 0)
6971 /* The register suffix is optional. */
6976 /* Fail the match if there were too few operands. */
6980 /* Successful match. */
6981 if (arg.dest_regno == arg.last_regno
6982 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
6985 as_bad (_("Source and destination must be different"));
6986 else if (arg.last_regno == 31)
6987 as_bad (_("A destination register must be supplied"));
6989 check_completed_insn (&arg);
6993 /* Fail the match if the line has too many operands. */
6997 /* Handle characters that need to match exactly. */
6998 if (*args == '(' || *args == ')' || *args == ',')
7000 if (match_char (&arg, *args))
7007 if (arg.token->type == OT_DOUBLE_CHAR
7008 && arg.token->u.ch == *args)
7016 /* Handle special macro operands. Work out the properties of
7019 arg.lax_max = FALSE;
7038 /* If these integer forms come last, there is no other
7039 form of the instruction that could match. Prefer to
7040 give detailed error messages where possible. */
7042 arg.soft_match = FALSE;
7046 /* "+I" is like "I", except that imm2_expr is used. */
7047 if (match_const_int (&arg, &imm2_expr.X_add_number, 0))
7048 imm2_expr.X_op = O_constant;
7050 insn_error = _("absolute expression required");
7051 if (HAVE_32BIT_GPRS)
7052 normalize_constant_expr (&imm2_expr);
7057 *offset_reloc = BFD_RELOC_MIPS_JMP;
7087 /* If these integer forms come last, there is no other
7088 form of the instruction that could match. Prefer to
7089 give detailed error messages where possible. */
7091 arg.soft_match = FALSE;
7095 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
7096 imm_expr.X_op = O_constant;
7098 insn_error = _("absolute expression required");
7099 if (HAVE_32BIT_GPRS)
7100 normalize_constant_expr (&imm_expr);
7104 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7106 /* Assume that the offset has been elided and that what
7107 we saw was a base register. The match will fail later
7108 if that assumption turns out to be wrong. */
7109 offset_expr.X_op = O_constant;
7110 offset_expr.X_add_number = 0;
7112 else if (match_expression (&arg, &offset_expr, offset_reloc))
7113 normalize_address_expr (&offset_expr);
7115 insn_error = _("absolute expression required");
7119 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7121 insn_error = _("floating-point expression required");
7125 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7127 insn_error = _("floating-point expression required");
7131 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7133 insn_error = _("floating-point expression required");
7137 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7139 insn_error = _("floating-point expression required");
7142 /* ??? This is the traditional behavior, but is flaky if
7143 there are alternative versions of the same instruction
7144 for different subarchitectures. The next alternative
7145 might not be suitable. */
7147 /* For compatibility with older assemblers, we accept
7148 0x8000-0xffff as signed 16-bit numbers when only
7149 signed numbers are allowed. */
7150 arg.lax_max = !more_alts;
7152 /* Only accept non-constant operands if this is the
7153 final alternative. Later alternatives might include
7154 a macro implementation. */
7155 arg.allow_nonconst = !more_alts;
7159 /* There are no macro implementations for out-of-range values. */
7160 arg.allow_nonconst = TRUE;
7164 /* There should always be a macro implementation. */
7165 arg.allow_nonconst = FALSE;
7169 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7173 *offset_reloc = BFD_RELOC_MIPS_JMP;
7177 gas_assert (mips_opts.micromips);
7183 if (!forced_insn_length)
7184 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7186 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7188 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7194 operand = (mips_opts.micromips
7195 ? decode_micromips_operand (args)
7196 : decode_mips_operand (args));
7200 /* Skip prefixes. */
7201 if (*args == '+' || *args == 'm')
7204 if (mips_optional_operand_p (operand)
7206 && (arg.token[0].type != OT_REG
7207 || arg.token[1].type == OT_END))
7209 /* Assume that the register has been elided and is the
7210 same as the first operand. */
7215 if (!match_operand (&arg, operand))
7220 /* Like match_insn, but for MIPS16. */
7223 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7224 struct mips_operand_token *tokens, bfd_boolean soft_match)
7227 const struct mips_operand *operand;
7228 const struct mips_operand *ext_operand;
7229 struct mips_arg_info arg;
7232 create_insn (insn, opcode);
7233 imm_expr.X_op = O_absent;
7234 imm2_expr.X_op = O_absent;
7235 offset_expr.X_op = O_absent;
7236 offset_reloc[0] = BFD_RELOC_UNUSED;
7237 offset_reloc[1] = BFD_RELOC_UNUSED;
7238 offset_reloc[2] = BFD_RELOC_UNUSED;
7241 memset (&arg, 0, sizeof (arg));
7245 arg.last_regno = ILLEGAL_REG;
7246 arg.dest_regno = ILLEGAL_REG;
7247 arg.soft_match = soft_match;
7249 for (args = opcode->args;; ++args)
7253 if (arg.token->type == OT_END)
7257 /* Handle unary instructions in which only one operand is given.
7258 The source is then the same as the destination. */
7259 if (arg.opnum == 1 && *args == ',')
7261 operand = decode_mips16_operand (args[1], FALSE);
7262 if (operand && mips_optional_operand_p (operand))
7270 /* Fail the match if there were too few operands. */
7274 /* Successful match. Stuff the immediate value in now, if
7276 if (opcode->pinfo == INSN_MACRO)
7278 gas_assert (relax_char == 0 || relax_char == 'p');
7279 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7282 && offset_expr.X_op == O_constant
7283 && calculate_reloc (*offset_reloc,
7284 offset_expr.X_add_number,
7287 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7288 forced_insn_length, &insn->insn_opcode);
7289 offset_expr.X_op = O_absent;
7290 *offset_reloc = BFD_RELOC_UNUSED;
7292 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7294 if (forced_insn_length == 2)
7295 as_bad (_("invalid unextended operand value"));
7296 forced_insn_length = 4;
7297 insn->insn_opcode |= MIPS16_EXTEND;
7299 else if (relax_char)
7300 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7302 check_completed_insn (&arg);
7306 /* Fail the match if the line has too many operands. */
7310 /* Handle characters that need to match exactly. */
7311 if (*args == '(' || *args == ')' || *args == ',')
7313 if (match_char (&arg, *args))
7331 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
7332 imm_expr.X_op = O_constant;
7334 insn_error = _("absolute expression required");
7335 if (HAVE_32BIT_GPRS)
7336 normalize_constant_expr (&imm_expr);
7341 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7342 insn->insn_opcode <<= 16;
7346 operand = decode_mips16_operand (c, FALSE);
7350 /* '6' is a special case. It is used for BREAK and SDBBP,
7351 whose operands are only meaningful to the software that decodes
7352 them. This means that there is no architectural reason why
7353 they cannot be prefixed by EXTEND, but in practice,
7354 exception handlers will only look at the instruction
7355 itself. We therefore allow '6' to be extended when
7356 disassembling but not when assembling. */
7357 if (operand->type != OP_PCREL && c != '6')
7359 ext_operand = decode_mips16_operand (c, TRUE);
7360 if (operand != ext_operand)
7362 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7364 offset_expr.X_op = O_constant;
7365 offset_expr.X_add_number = 0;
7370 /* We need the OT_INTEGER check because some MIPS16
7371 immediate variants are listed before the register ones. */
7372 if (arg.token->type != OT_INTEGER
7373 || !match_expression (&arg, &offset_expr, offset_reloc))
7376 /* '8' is used for SLTI(U) and has traditionally not
7377 been allowed to take relocation operators. */
7378 if (offset_reloc[0] != BFD_RELOC_UNUSED
7379 && (ext_operand->size != 16 || c == '8'))
7387 if (mips_optional_operand_p (operand)
7389 && (arg.token[0].type != OT_REG
7390 || arg.token[1].type == OT_END))
7392 /* Assume that the register has been elided and is the
7393 same as the first operand. */
7398 if (!match_operand (&arg, operand))
7403 /* Set up global variables for the start of a new macro. */
7408 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
7409 memset (&mips_macro_warning.first_insn_sizes, 0,
7410 sizeof (mips_macro_warning.first_insn_sizes));
7411 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
7412 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
7413 && delayed_branch_p (&history[0]));
7414 switch (history[0].insn_mo->pinfo2
7415 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7417 case INSN2_BRANCH_DELAY_32BIT:
7418 mips_macro_warning.delay_slot_length = 4;
7420 case INSN2_BRANCH_DELAY_16BIT:
7421 mips_macro_warning.delay_slot_length = 2;
7424 mips_macro_warning.delay_slot_length = 0;
7427 mips_macro_warning.first_frag = NULL;
7430 /* Given that a macro is longer than one instruction or of the wrong size,
7431 return the appropriate warning for it. Return null if no warning is
7432 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7433 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7434 and RELAX_NOMACRO. */
7437 macro_warning (relax_substateT subtype)
7439 if (subtype & RELAX_DELAY_SLOT)
7440 return _("Macro instruction expanded into multiple instructions"
7441 " in a branch delay slot");
7442 else if (subtype & RELAX_NOMACRO)
7443 return _("Macro instruction expanded into multiple instructions");
7444 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7445 | RELAX_DELAY_SLOT_SIZE_SECOND))
7446 return ((subtype & RELAX_DELAY_SLOT_16BIT)
7447 ? _("Macro instruction expanded into a wrong size instruction"
7448 " in a 16-bit branch delay slot")
7449 : _("Macro instruction expanded into a wrong size instruction"
7450 " in a 32-bit branch delay slot"));
7455 /* Finish up a macro. Emit warnings as appropriate. */
7460 /* Relaxation warning flags. */
7461 relax_substateT subtype = 0;
7463 /* Check delay slot size requirements. */
7464 if (mips_macro_warning.delay_slot_length == 2)
7465 subtype |= RELAX_DELAY_SLOT_16BIT;
7466 if (mips_macro_warning.delay_slot_length != 0)
7468 if (mips_macro_warning.delay_slot_length
7469 != mips_macro_warning.first_insn_sizes[0])
7470 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7471 if (mips_macro_warning.delay_slot_length
7472 != mips_macro_warning.first_insn_sizes[1])
7473 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7476 /* Check instruction count requirements. */
7477 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7479 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
7480 subtype |= RELAX_SECOND_LONGER;
7481 if (mips_opts.warn_about_macros)
7482 subtype |= RELAX_NOMACRO;
7483 if (mips_macro_warning.delay_slot_p)
7484 subtype |= RELAX_DELAY_SLOT;
7487 /* If both alternatives fail to fill a delay slot correctly,
7488 emit the warning now. */
7489 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7490 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7495 s = subtype & (RELAX_DELAY_SLOT_16BIT
7496 | RELAX_DELAY_SLOT_SIZE_FIRST
7497 | RELAX_DELAY_SLOT_SIZE_SECOND);
7498 msg = macro_warning (s);
7500 as_warn ("%s", msg);
7504 /* If both implementations are longer than 1 instruction, then emit the
7506 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7511 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7512 msg = macro_warning (s);
7514 as_warn ("%s", msg);
7518 /* If any flags still set, then one implementation might need a warning
7519 and the other either will need one of a different kind or none at all.
7520 Pass any remaining flags over to relaxation. */
7521 if (mips_macro_warning.first_frag != NULL)
7522 mips_macro_warning.first_frag->fr_subtype |= subtype;
7525 /* Instruction operand formats used in macros that vary between
7526 standard MIPS and microMIPS code. */
7528 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
7529 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7530 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7531 static const char * const lui_fmt[2] = { "t,u", "s,u" };
7532 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
7533 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
7534 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7535 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7537 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7538 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7539 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7540 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7541 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7542 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7543 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7544 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7546 /* Read a macro's relocation codes from *ARGS and store them in *R.
7547 The first argument in *ARGS will be either the code for a single
7548 relocation or -1 followed by the three codes that make up a
7549 composite relocation. */
7552 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7556 next = va_arg (*args, int);
7558 r[0] = (bfd_reloc_code_real_type) next;
7561 for (i = 0; i < 3; i++)
7562 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7563 /* This function is only used for 16-bit relocation fields.
7564 To make the macro code simpler, treat an unrelocated value
7565 in the same way as BFD_RELOC_LO16. */
7566 if (r[0] == BFD_RELOC_UNUSED)
7567 r[0] = BFD_RELOC_LO16;
7571 /* Build an instruction created by a macro expansion. This is passed
7572 a pointer to the count of instructions created so far, an
7573 expression, the name of the instruction to build, an operand format
7574 string, and corresponding arguments. */
7577 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
7579 const struct mips_opcode *mo = NULL;
7580 bfd_reloc_code_real_type r[3];
7581 const struct mips_opcode *amo;
7582 const struct mips_operand *operand;
7583 struct hash_control *hash;
7584 struct mips_cl_insn insn;
7588 va_start (args, fmt);
7590 if (mips_opts.mips16)
7592 mips16_macro_build (ep, name, fmt, &args);
7597 r[0] = BFD_RELOC_UNUSED;
7598 r[1] = BFD_RELOC_UNUSED;
7599 r[2] = BFD_RELOC_UNUSED;
7600 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7601 amo = (struct mips_opcode *) hash_find (hash, name);
7603 gas_assert (strcmp (name, amo->name) == 0);
7607 /* Search until we get a match for NAME. It is assumed here that
7608 macros will never generate MDMX, MIPS-3D, or MT instructions.
7609 We try to match an instruction that fulfils the branch delay
7610 slot instruction length requirement (if any) of the previous
7611 instruction. While doing this we record the first instruction
7612 seen that matches all the other conditions and use it anyway
7613 if the requirement cannot be met; we will issue an appropriate
7614 warning later on. */
7615 if (strcmp (fmt, amo->args) == 0
7616 && amo->pinfo != INSN_MACRO
7617 && is_opcode_valid (amo)
7618 && is_size_valid (amo))
7620 if (is_delay_slot_valid (amo))
7630 gas_assert (amo->name);
7632 while (strcmp (name, amo->name) == 0);
7635 create_insn (&insn, mo);
7648 macro_read_relocs (&args, r);
7649 gas_assert (*r == BFD_RELOC_GPREL16
7650 || *r == BFD_RELOC_MIPS_HIGHER
7651 || *r == BFD_RELOC_HI16_S
7652 || *r == BFD_RELOC_LO16
7653 || *r == BFD_RELOC_MIPS_GOT_OFST);
7657 macro_read_relocs (&args, r);
7661 macro_read_relocs (&args, r);
7662 gas_assert (ep != NULL
7663 && (ep->X_op == O_constant
7664 || (ep->X_op == O_symbol
7665 && (*r == BFD_RELOC_MIPS_HIGHEST
7666 || *r == BFD_RELOC_HI16_S
7667 || *r == BFD_RELOC_HI16
7668 || *r == BFD_RELOC_GPREL16
7669 || *r == BFD_RELOC_MIPS_GOT_HI16
7670 || *r == BFD_RELOC_MIPS_CALL_HI16))));
7674 gas_assert (ep != NULL);
7677 * This allows macro() to pass an immediate expression for
7678 * creating short branches without creating a symbol.
7680 * We don't allow branch relaxation for these branches, as
7681 * they should only appear in ".set nomacro" anyway.
7683 if (ep->X_op == O_constant)
7685 /* For microMIPS we always use relocations for branches.
7686 So we should not resolve immediate values. */
7687 gas_assert (!mips_opts.micromips);
7689 if ((ep->X_add_number & 3) != 0)
7690 as_bad (_("branch to misaligned address (0x%lx)"),
7691 (unsigned long) ep->X_add_number);
7692 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7693 as_bad (_("branch address range overflow (0x%lx)"),
7694 (unsigned long) ep->X_add_number);
7695 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7699 *r = BFD_RELOC_16_PCREL_S2;
7703 gas_assert (ep != NULL);
7704 *r = BFD_RELOC_MIPS_JMP;
7708 operand = (mips_opts.micromips
7709 ? decode_micromips_operand (fmt)
7710 : decode_mips_operand (fmt));
7714 uval = va_arg (args, int);
7715 if (operand->type == OP_CLO_CLZ_DEST)
7716 uval |= (uval << 5);
7717 insn_insert_operand (&insn, operand, uval);
7719 if (*fmt == '+' || *fmt == 'm')
7725 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7727 append_insn (&insn, ep, r, TRUE);
7731 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
7734 struct mips_opcode *mo;
7735 struct mips_cl_insn insn;
7736 const struct mips_operand *operand;
7737 bfd_reloc_code_real_type r[3]
7738 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
7740 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
7742 gas_assert (strcmp (name, mo->name) == 0);
7744 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7747 gas_assert (mo->name);
7748 gas_assert (strcmp (name, mo->name) == 0);
7751 create_insn (&insn, mo);
7789 gas_assert (ep != NULL);
7791 if (ep->X_op != O_constant)
7792 *r = (int) BFD_RELOC_UNUSED + c;
7793 else if (calculate_reloc (*r, ep->X_add_number, &value))
7795 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
7797 *r = BFD_RELOC_UNUSED;
7803 operand = decode_mips16_operand (c, FALSE);
7807 insn_insert_operand (&insn, operand, va_arg (*args, int));
7812 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7814 append_insn (&insn, ep, r, TRUE);
7818 * Generate a "jalr" instruction with a relocation hint to the called
7819 * function. This occurs in NewABI PIC code.
7822 macro_build_jalr (expressionS *ep, int cprestore)
7824 static const bfd_reloc_code_real_type jalr_relocs[2]
7825 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7826 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7830 if (MIPS_JALR_HINT_P (ep))
7835 if (mips_opts.micromips)
7837 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7838 ? "jalr" : "jalrs");
7839 if (MIPS_JALR_HINT_P (ep)
7841 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7842 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7844 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7847 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7848 if (MIPS_JALR_HINT_P (ep))
7849 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7853 * Generate a "lui" instruction.
7856 macro_build_lui (expressionS *ep, int regnum)
7858 gas_assert (! mips_opts.mips16);
7860 if (ep->X_op != O_constant)
7862 gas_assert (ep->X_op == O_symbol);
7863 /* _gp_disp is a special case, used from s_cpload.
7864 __gnu_local_gp is used if mips_no_shared. */
7865 gas_assert (mips_pic == NO_PIC
7867 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7868 || (! mips_in_shared
7869 && strcmp (S_GET_NAME (ep->X_add_symbol),
7870 "__gnu_local_gp") == 0));
7873 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7876 /* Generate a sequence of instructions to do a load or store from a constant
7877 offset off of a base register (breg) into/from a target register (treg),
7878 using AT if necessary. */
7880 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7881 int treg, int breg, int dbl)
7883 gas_assert (ep->X_op == O_constant);
7885 /* Sign-extending 32-bit constants makes their handling easier. */
7887 normalize_constant_expr (ep);
7889 /* Right now, this routine can only handle signed 32-bit constants. */
7890 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7891 as_warn (_("operand overflow"));
7893 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7895 /* Signed 16-bit offset will fit in the op. Easy! */
7896 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7900 /* 32-bit offset, need multiple instructions and AT, like:
7901 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7902 addu $tempreg,$tempreg,$breg
7903 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7904 to handle the complete offset. */
7905 macro_build_lui (ep, AT);
7906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7907 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7910 as_bad (_("Macro used $at after \".set noat\""));
7915 * Generates code to set the $at register to true (one)
7916 * if reg is less than the immediate expression.
7919 set_at (int reg, int unsignedp)
7921 if (imm_expr.X_op == O_constant
7922 && imm_expr.X_add_number >= -0x8000
7923 && imm_expr.X_add_number < 0x8000)
7924 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
7925 AT, reg, BFD_RELOC_LO16);
7928 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7929 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
7933 /* Count the leading zeroes by performing a binary chop. This is a
7934 bulky bit of source, but performance is a LOT better for the
7935 majority of values than a simple loop to count the bits:
7936 for (lcnt = 0; (lcnt < 32); lcnt++)
7937 if ((v) & (1 << (31 - lcnt)))
7939 However it is not code size friendly, and the gain will drop a bit
7940 on certain cached systems.
7942 #define COUNT_TOP_ZEROES(v) \
7943 (((v) & ~0xffff) == 0 \
7944 ? ((v) & ~0xff) == 0 \
7945 ? ((v) & ~0xf) == 0 \
7946 ? ((v) & ~0x3) == 0 \
7947 ? ((v) & ~0x1) == 0 \
7952 : ((v) & ~0x7) == 0 \
7955 : ((v) & ~0x3f) == 0 \
7956 ? ((v) & ~0x1f) == 0 \
7959 : ((v) & ~0x7f) == 0 \
7962 : ((v) & ~0xfff) == 0 \
7963 ? ((v) & ~0x3ff) == 0 \
7964 ? ((v) & ~0x1ff) == 0 \
7967 : ((v) & ~0x7ff) == 0 \
7970 : ((v) & ~0x3fff) == 0 \
7971 ? ((v) & ~0x1fff) == 0 \
7974 : ((v) & ~0x7fff) == 0 \
7977 : ((v) & ~0xffffff) == 0 \
7978 ? ((v) & ~0xfffff) == 0 \
7979 ? ((v) & ~0x3ffff) == 0 \
7980 ? ((v) & ~0x1ffff) == 0 \
7983 : ((v) & ~0x7ffff) == 0 \
7986 : ((v) & ~0x3fffff) == 0 \
7987 ? ((v) & ~0x1fffff) == 0 \
7990 : ((v) & ~0x7fffff) == 0 \
7993 : ((v) & ~0xfffffff) == 0 \
7994 ? ((v) & ~0x3ffffff) == 0 \
7995 ? ((v) & ~0x1ffffff) == 0 \
7998 : ((v) & ~0x7ffffff) == 0 \
8001 : ((v) & ~0x3fffffff) == 0 \
8002 ? ((v) & ~0x1fffffff) == 0 \
8005 : ((v) & ~0x7fffffff) == 0 \
8010 * This routine generates the least number of instructions necessary to load
8011 * an absolute expression value into a register.
8014 load_register (int reg, expressionS *ep, int dbl)
8017 expressionS hi32, lo32;
8019 if (ep->X_op != O_big)
8021 gas_assert (ep->X_op == O_constant);
8023 /* Sign-extending 32-bit constants makes their handling easier. */
8025 normalize_constant_expr (ep);
8027 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8029 /* We can handle 16 bit signed values with an addiu to
8030 $zero. No need to ever use daddiu here, since $zero and
8031 the result are always correct in 32 bit mode. */
8032 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8035 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8037 /* We can handle 16 bit unsigned values with an ori to
8039 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8042 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8044 /* 32 bit values require an lui. */
8045 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8046 if ((ep->X_add_number & 0xffff) != 0)
8047 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8052 /* The value is larger than 32 bits. */
8054 if (!dbl || HAVE_32BIT_GPRS)
8058 sprintf_vma (value, ep->X_add_number);
8059 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8060 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8064 if (ep->X_op != O_big)
8067 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8068 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8069 hi32.X_add_number &= 0xffffffff;
8071 lo32.X_add_number &= 0xffffffff;
8075 gas_assert (ep->X_add_number > 2);
8076 if (ep->X_add_number == 3)
8077 generic_bignum[3] = 0;
8078 else if (ep->X_add_number > 4)
8079 as_bad (_("Number larger than 64 bits"));
8080 lo32.X_op = O_constant;
8081 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8082 hi32.X_op = O_constant;
8083 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8086 if (hi32.X_add_number == 0)
8091 unsigned long hi, lo;
8093 if (hi32.X_add_number == (offsetT) 0xffffffff)
8095 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8097 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8100 if (lo32.X_add_number & 0x80000000)
8102 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8103 if (lo32.X_add_number & 0xffff)
8104 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8109 /* Check for 16bit shifted constant. We know that hi32 is
8110 non-zero, so start the mask on the first bit of the hi32
8115 unsigned long himask, lomask;
8119 himask = 0xffff >> (32 - shift);
8120 lomask = (0xffff << shift) & 0xffffffff;
8124 himask = 0xffff << (shift - 32);
8127 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8128 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8132 tmp.X_op = O_constant;
8134 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8135 | (lo32.X_add_number >> shift));
8137 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8138 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8139 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8140 reg, reg, (shift >= 32) ? shift - 32 : shift);
8145 while (shift <= (64 - 16));
8147 /* Find the bit number of the lowest one bit, and store the
8148 shifted value in hi/lo. */
8149 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8150 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8154 while ((lo & 1) == 0)
8159 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8165 while ((hi & 1) == 0)
8174 /* Optimize if the shifted value is a (power of 2) - 1. */
8175 if ((hi == 0 && ((lo + 1) & lo) == 0)
8176 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
8178 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
8183 /* This instruction will set the register to be all
8185 tmp.X_op = O_constant;
8186 tmp.X_add_number = (offsetT) -1;
8187 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8191 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8192 reg, reg, (bit >= 32) ? bit - 32 : bit);
8194 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
8195 reg, reg, (shift >= 32) ? shift - 32 : shift);
8200 /* Sign extend hi32 before calling load_register, because we can
8201 generally get better code when we load a sign extended value. */
8202 if ((hi32.X_add_number & 0x80000000) != 0)
8203 hi32.X_add_number |= ~(offsetT) 0xffffffff;
8204 load_register (reg, &hi32, 0);
8207 if ((lo32.X_add_number & 0xffff0000) == 0)
8211 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
8219 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
8221 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8222 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
8228 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
8232 mid16.X_add_number >>= 16;
8233 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8234 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8237 if ((lo32.X_add_number & 0xffff) != 0)
8238 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8242 load_delay_nop (void)
8244 if (!gpr_interlocks)
8245 macro_build (NULL, "nop", "");
8248 /* Load an address into a register. */
8251 load_address (int reg, expressionS *ep, int *used_at)
8253 if (ep->X_op != O_constant
8254 && ep->X_op != O_symbol)
8256 as_bad (_("expression too complex"));
8257 ep->X_op = O_constant;
8260 if (ep->X_op == O_constant)
8262 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
8266 if (mips_pic == NO_PIC)
8268 /* If this is a reference to a GP relative symbol, we want
8269 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8271 lui $reg,<sym> (BFD_RELOC_HI16_S)
8272 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8273 If we have an addend, we always use the latter form.
8275 With 64bit address space and a usable $at we want
8276 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8277 lui $at,<sym> (BFD_RELOC_HI16_S)
8278 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8279 daddiu $at,<sym> (BFD_RELOC_LO16)
8283 If $at is already in use, we use a path which is suboptimal
8284 on superscalar processors.
8285 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8286 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8288 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8290 daddiu $reg,<sym> (BFD_RELOC_LO16)
8292 For GP relative symbols in 64bit address space we can use
8293 the same sequence as in 32bit address space. */
8294 if (HAVE_64BIT_SYMBOLS)
8296 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8297 && !nopic_need_relax (ep->X_add_symbol, 1))
8299 relax_start (ep->X_add_symbol);
8300 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8301 mips_gp_register, BFD_RELOC_GPREL16);
8305 if (*used_at == 0 && mips_opts.at)
8307 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8308 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
8309 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8310 BFD_RELOC_MIPS_HIGHER);
8311 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
8312 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
8313 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
8318 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8319 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8320 BFD_RELOC_MIPS_HIGHER);
8321 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8322 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
8323 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8324 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
8327 if (mips_relax.sequence)
8332 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8333 && !nopic_need_relax (ep->X_add_symbol, 1))
8335 relax_start (ep->X_add_symbol);
8336 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8337 mips_gp_register, BFD_RELOC_GPREL16);
8340 macro_build_lui (ep, reg);
8341 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8342 reg, reg, BFD_RELOC_LO16);
8343 if (mips_relax.sequence)
8347 else if (!mips_big_got)
8351 /* If this is a reference to an external symbol, we want
8352 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8354 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8356 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8357 If there is a constant, it must be added in after.
8359 If we have NewABI, we want
8360 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8361 unless we're referencing a global symbol with a non-zero
8362 offset, in which case cst must be added separately. */
8365 if (ep->X_add_number)
8367 ex.X_add_number = ep->X_add_number;
8368 ep->X_add_number = 0;
8369 relax_start (ep->X_add_symbol);
8370 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8371 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8372 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8373 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8374 ex.X_op = O_constant;
8375 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8376 reg, reg, BFD_RELOC_LO16);
8377 ep->X_add_number = ex.X_add_number;
8380 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8381 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8382 if (mips_relax.sequence)
8387 ex.X_add_number = ep->X_add_number;
8388 ep->X_add_number = 0;
8389 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8390 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8392 relax_start (ep->X_add_symbol);
8394 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8398 if (ex.X_add_number != 0)
8400 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8401 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8402 ex.X_op = O_constant;
8403 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8404 reg, reg, BFD_RELOC_LO16);
8408 else if (mips_big_got)
8412 /* This is the large GOT case. If this is a reference to an
8413 external symbol, we want
8414 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8416 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8418 Otherwise, for a reference to a local symbol in old ABI, we want
8419 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8421 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8422 If there is a constant, it must be added in after.
8424 In the NewABI, for local symbols, with or without offsets, we want:
8425 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8426 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8430 ex.X_add_number = ep->X_add_number;
8431 ep->X_add_number = 0;
8432 relax_start (ep->X_add_symbol);
8433 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8435 reg, reg, mips_gp_register);
8436 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8437 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8438 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8439 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8440 else if (ex.X_add_number)
8442 ex.X_op = O_constant;
8443 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8447 ep->X_add_number = ex.X_add_number;
8449 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8450 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8451 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8452 BFD_RELOC_MIPS_GOT_OFST);
8457 ex.X_add_number = ep->X_add_number;
8458 ep->X_add_number = 0;
8459 relax_start (ep->X_add_symbol);
8460 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8461 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8462 reg, reg, mips_gp_register);
8463 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8464 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8466 if (reg_needs_delay (mips_gp_register))
8468 /* We need a nop before loading from $gp. This special
8469 check is required because the lui which starts the main
8470 instruction stream does not refer to $gp, and so will not
8471 insert the nop which may be required. */
8472 macro_build (NULL, "nop", "");
8474 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8475 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8477 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8481 if (ex.X_add_number != 0)
8483 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8484 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8485 ex.X_op = O_constant;
8486 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8494 if (!mips_opts.at && *used_at == 1)
8495 as_bad (_("Macro used $at after \".set noat\""));
8498 /* Move the contents of register SOURCE into register DEST. */
8501 move_register (int dest, int source)
8503 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8504 instruction specifically requires a 32-bit one. */
8505 if (mips_opts.micromips
8506 && !mips_opts.insn32
8507 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8508 macro_build (NULL, "move", "mp,mj", dest, source);
8510 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8514 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8515 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8516 The two alternatives are:
8518 Global symbol Local sybmol
8519 ------------- ------------
8520 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8522 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8524 load_got_offset emits the first instruction and add_got_offset
8525 emits the second for a 16-bit offset or add_got_offset_hilo emits
8526 a sequence to add a 32-bit offset using a scratch register. */
8529 load_got_offset (int dest, expressionS *local)
8534 global.X_add_number = 0;
8536 relax_start (local->X_add_symbol);
8537 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8538 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8540 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8541 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8546 add_got_offset (int dest, expressionS *local)
8550 global.X_op = O_constant;
8551 global.X_op_symbol = NULL;
8552 global.X_add_symbol = NULL;
8553 global.X_add_number = local->X_add_number;
8555 relax_start (local->X_add_symbol);
8556 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
8557 dest, dest, BFD_RELOC_LO16);
8559 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
8564 add_got_offset_hilo (int dest, expressionS *local, int tmp)
8567 int hold_mips_optimize;
8569 global.X_op = O_constant;
8570 global.X_op_symbol = NULL;
8571 global.X_add_symbol = NULL;
8572 global.X_add_number = local->X_add_number;
8574 relax_start (local->X_add_symbol);
8575 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8577 /* Set mips_optimize around the lui instruction to avoid
8578 inserting an unnecessary nop after the lw. */
8579 hold_mips_optimize = mips_optimize;
8581 macro_build_lui (&global, tmp);
8582 mips_optimize = hold_mips_optimize;
8583 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8586 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8589 /* Emit a sequence of instructions to emulate a branch likely operation.
8590 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8591 is its complementing branch with the original condition negated.
8592 CALL is set if the original branch specified the link operation.
8593 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8595 Code like this is produced in the noreorder mode:
8600 delay slot (executed only if branch taken)
8608 delay slot (executed only if branch taken)
8611 In the reorder mode the delay slot would be filled with a nop anyway,
8612 so code produced is simply:
8617 This function is used when producing code for the microMIPS ASE that
8618 does not implement branch likely instructions in hardware. */
8621 macro_build_branch_likely (const char *br, const char *brneg,
8622 int call, expressionS *ep, const char *fmt,
8623 unsigned int sreg, unsigned int treg)
8625 int noreorder = mips_opts.noreorder;
8628 gas_assert (mips_opts.micromips);
8632 micromips_label_expr (&expr1);
8633 macro_build (&expr1, brneg, fmt, sreg, treg);
8634 macro_build (NULL, "nop", "");
8635 macro_build (ep, call ? "bal" : "b", "p");
8637 /* Set to true so that append_insn adds a label. */
8638 emit_branch_likely_macro = TRUE;
8642 macro_build (ep, br, fmt, sreg, treg);
8643 macro_build (NULL, "nop", "");
8648 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8649 the condition code tested. EP specifies the branch target. */
8652 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8679 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8682 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8683 the register tested. EP specifies the branch target. */
8686 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8688 const char *brneg = NULL;
8698 br = mips_opts.micromips ? "bgez" : "bgezl";
8702 gas_assert (mips_opts.micromips);
8703 br = mips_opts.insn32 ? "bgezal" : "bgezals";
8711 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8718 br = mips_opts.micromips ? "blez" : "blezl";
8725 br = mips_opts.micromips ? "bltz" : "bltzl";
8729 gas_assert (mips_opts.micromips);
8730 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8737 if (mips_opts.micromips && brneg)
8738 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8740 macro_build (ep, br, "s,p", sreg);
8743 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8744 TREG as the registers tested. EP specifies the branch target. */
8747 macro_build_branch_rsrt (int type, expressionS *ep,
8748 unsigned int sreg, unsigned int treg)
8750 const char *brneg = NULL;
8762 br = mips_opts.micromips ? "beq" : "beql";
8771 br = mips_opts.micromips ? "bne" : "bnel";
8777 if (mips_opts.micromips && brneg)
8778 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8780 macro_build (ep, br, "s,t,p", sreg, treg);
8783 /* Return the high part that should be loaded in order to make the low
8784 part of VALUE accessible using an offset of OFFBITS bits. */
8787 offset_high_part (offsetT value, unsigned int offbits)
8794 bias = 1 << (offbits - 1);
8795 low_mask = bias * 2 - 1;
8796 return (value + bias) & ~low_mask;
8799 /* Return true if the value stored in offset_expr and offset_reloc
8800 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8801 amount that the caller wants to add without inducing overflow
8802 and ALIGN is the known alignment of the value in bytes. */
8805 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8809 /* Accept any relocation operator if overflow isn't a concern. */
8810 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8813 /* These relocations are guaranteed not to overflow in correct links. */
8814 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8815 || gprel16_reloc_p (*offset_reloc))
8818 if (offset_expr.X_op == O_constant
8819 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8820 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8827 * This routine implements the seemingly endless macro or synthesized
8828 * instructions and addressing modes in the mips assembly language. Many
8829 * of these macros are simple and are similar to each other. These could
8830 * probably be handled by some kind of table or grammar approach instead of
8831 * this verbose method. Others are not simple macros but are more like
8832 * optimizing code generation.
8833 * One interesting optimization is when several store macros appear
8834 * consecutively that would load AT with the upper half of the same address.
8835 * The ensuing load upper instructions are ommited. This implies some kind
8836 * of global optimization. We currently only optimize within a single macro.
8837 * For many of the load and store macros if the address is specified as a
8838 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8839 * first load register 'at' with zero and use it as the base register. The
8840 * mips assembler simply uses register $zero. Just one tiny optimization
8844 macro (struct mips_cl_insn *ip, char *str)
8846 const struct mips_operand_array *operands;
8847 unsigned int breg, i;
8848 unsigned int tempreg;
8851 expressionS label_expr;
8866 bfd_boolean large_offset;
8868 int hold_mips_optimize;
8870 unsigned int op[MAX_OPERANDS];
8872 gas_assert (! mips_opts.mips16);
8874 operands = insn_operands (ip);
8875 for (i = 0; i < MAX_OPERANDS; i++)
8876 if (operands->operand[i])
8877 op[i] = insn_extract_operand (ip, operands->operand[i]);
8881 mask = ip->insn_mo->mask;
8883 label_expr.X_op = O_constant;
8884 label_expr.X_op_symbol = NULL;
8885 label_expr.X_add_symbol = NULL;
8886 label_expr.X_add_number = 0;
8888 expr1.X_op = O_constant;
8889 expr1.X_op_symbol = NULL;
8890 expr1.X_add_symbol = NULL;
8891 expr1.X_add_number = 1;
8907 if (mips_opts.micromips)
8908 micromips_label_expr (&label_expr);
8910 label_expr.X_add_number = 8;
8911 macro_build (&label_expr, "bgez", "s,p", op[1]);
8913 macro_build (NULL, "nop", "");
8915 move_register (op[0], op[1]);
8916 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
8917 if (mips_opts.micromips)
8918 micromips_add_label ();
8935 if (!mips_opts.micromips)
8937 if (imm_expr.X_op == O_constant
8938 && imm_expr.X_add_number >= -0x200
8939 && imm_expr.X_add_number < 0x200)
8941 macro_build (NULL, s, "t,r,.", op[0], op[1], imm_expr.X_add_number);
8950 if (imm_expr.X_op == O_constant
8951 && imm_expr.X_add_number >= -0x8000
8952 && imm_expr.X_add_number < 0x8000)
8954 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8959 load_register (AT, &imm_expr, dbl);
8960 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
8979 if (imm_expr.X_op == O_constant
8980 && imm_expr.X_add_number >= 0
8981 && imm_expr.X_add_number < 0x10000)
8983 if (mask != M_NOR_I)
8984 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
8987 macro_build (&imm_expr, "ori", "t,r,i",
8988 op[0], op[1], BFD_RELOC_LO16);
8989 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
8995 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8996 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9000 switch (imm_expr.X_add_number)
9003 macro_build (NULL, "nop", "");
9006 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9010 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9011 (int) imm_expr.X_add_number);
9014 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9015 (unsigned long) imm_expr.X_add_number);
9024 gas_assert (mips_opts.micromips);
9025 macro_build_branch_ccl (mask, &offset_expr,
9026 EXTRACT_OPERAND (1, BCC, *ip));
9033 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9039 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
9044 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9051 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9052 else if (op[0] == 0)
9053 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9057 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9058 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9059 &offset_expr, AT, ZERO);
9069 macro_build_branch_rs (mask, &offset_expr, op[0]);
9075 /* Check for > max integer. */
9076 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9079 /* Result is always false. */
9081 macro_build (NULL, "nop", "");
9083 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9086 if (imm_expr.X_op != O_constant)
9087 as_bad (_("Unsupported large constant"));
9088 ++imm_expr.X_add_number;
9092 if (mask == M_BGEL_I)
9094 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9096 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9097 &offset_expr, op[0]);
9100 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9102 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9103 &offset_expr, op[0]);
9106 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
9109 /* result is always true */
9110 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
9111 macro_build (&offset_expr, "b", "p");
9116 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9117 &offset_expr, AT, ZERO);
9125 else if (op[0] == 0)
9126 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9127 &offset_expr, ZERO, op[1]);
9131 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9132 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9133 &offset_expr, AT, ZERO);
9142 && imm_expr.X_op == O_constant
9143 && imm_expr.X_add_number == -1))
9145 if (imm_expr.X_op != O_constant)
9146 as_bad (_("Unsupported large constant"));
9147 ++imm_expr.X_add_number;
9151 if (mask == M_BGEUL_I)
9153 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9155 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9156 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9157 &offset_expr, op[0], ZERO);
9162 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9163 &offset_expr, AT, ZERO);
9171 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9172 else if (op[0] == 0)
9173 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9177 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9178 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9179 &offset_expr, AT, ZERO);
9187 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9188 &offset_expr, op[0], ZERO);
9189 else if (op[0] == 0)
9194 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9195 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9196 &offset_expr, AT, ZERO);
9204 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9205 else if (op[0] == 0)
9206 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
9210 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9211 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9212 &offset_expr, AT, ZERO);
9219 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9221 if (imm_expr.X_op != O_constant)
9222 as_bad (_("Unsupported large constant"));
9223 ++imm_expr.X_add_number;
9227 if (mask == M_BLTL_I)
9229 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9230 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9231 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9232 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9237 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9238 &offset_expr, AT, ZERO);
9246 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9247 &offset_expr, op[0], ZERO);
9248 else if (op[0] == 0)
9253 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9254 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9255 &offset_expr, AT, ZERO);
9264 && imm_expr.X_op == O_constant
9265 && imm_expr.X_add_number == -1))
9267 if (imm_expr.X_op != O_constant)
9268 as_bad (_("Unsupported large constant"));
9269 ++imm_expr.X_add_number;
9273 if (mask == M_BLTUL_I)
9275 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9277 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9278 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9279 &offset_expr, op[0], ZERO);
9284 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9285 &offset_expr, AT, ZERO);
9293 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9294 else if (op[0] == 0)
9295 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
9299 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9300 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9301 &offset_expr, AT, ZERO);
9310 else if (op[0] == 0)
9311 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9312 &offset_expr, ZERO, op[1]);
9316 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9317 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9318 &offset_expr, AT, ZERO);
9324 /* Use unsigned arithmetic. */
9328 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9330 as_bad (_("Unsupported large constant"));
9335 pos = imm_expr.X_add_number;
9336 size = imm2_expr.X_add_number;
9341 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9344 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9346 report_bad_field (pos, size);
9350 if (size <= 32 && pos < 32)
9355 else if (size <= 32)
9365 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9372 /* Use unsigned arithmetic. */
9376 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9378 as_bad (_("Unsupported large constant"));
9383 pos = imm_expr.X_add_number;
9384 size = imm2_expr.X_add_number;
9389 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9392 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9394 report_bad_field (pos, size);
9398 if (pos < 32 && (pos + size - 1) < 32)
9413 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9414 (int) (pos + size - 1));
9430 as_warn (_("Divide by zero."));
9432 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9434 macro_build (NULL, "break", BRK_FMT, 7);
9441 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9442 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9446 if (mips_opts.micromips)
9447 micromips_label_expr (&label_expr);
9449 label_expr.X_add_number = 8;
9450 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9451 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9452 macro_build (NULL, "break", BRK_FMT, 7);
9453 if (mips_opts.micromips)
9454 micromips_add_label ();
9456 expr1.X_add_number = -1;
9458 load_register (AT, &expr1, dbl);
9459 if (mips_opts.micromips)
9460 micromips_label_expr (&label_expr);
9462 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
9463 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
9466 expr1.X_add_number = 1;
9467 load_register (AT, &expr1, dbl);
9468 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
9472 expr1.X_add_number = 0x80000000;
9473 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
9477 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
9478 /* We want to close the noreorder block as soon as possible, so
9479 that later insns are available for delay slot filling. */
9484 if (mips_opts.micromips)
9485 micromips_label_expr (&label_expr);
9487 label_expr.X_add_number = 8;
9488 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
9489 macro_build (NULL, "nop", "");
9491 /* We want to close the noreorder block as soon as possible, so
9492 that later insns are available for delay slot filling. */
9495 macro_build (NULL, "break", BRK_FMT, 6);
9497 if (mips_opts.micromips)
9498 micromips_add_label ();
9499 macro_build (NULL, s, MFHL_FMT, op[0]);
9538 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9540 as_warn (_("Divide by zero."));
9542 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9544 macro_build (NULL, "break", BRK_FMT, 7);
9547 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9549 if (strcmp (s2, "mflo") == 0)
9550 move_register (op[0], op[1]);
9552 move_register (op[0], ZERO);
9555 if (imm_expr.X_op == O_constant
9556 && imm_expr.X_add_number == -1
9557 && s[strlen (s) - 1] != 'u')
9559 if (strcmp (s2, "mflo") == 0)
9560 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
9562 move_register (op[0], ZERO);
9567 load_register (AT, &imm_expr, dbl);
9568 macro_build (NULL, s, "z,s,t", op[1], AT);
9569 macro_build (NULL, s2, MFHL_FMT, op[0]);
9591 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9592 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9593 /* We want to close the noreorder block as soon as possible, so
9594 that later insns are available for delay slot filling. */
9599 if (mips_opts.micromips)
9600 micromips_label_expr (&label_expr);
9602 label_expr.X_add_number = 8;
9603 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9604 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9606 /* We want to close the noreorder block as soon as possible, so
9607 that later insns are available for delay slot filling. */
9609 macro_build (NULL, "break", BRK_FMT, 7);
9610 if (mips_opts.micromips)
9611 micromips_add_label ();
9613 macro_build (NULL, s2, MFHL_FMT, op[0]);
9625 /* Load the address of a symbol into a register. If breg is not
9626 zero, we then add a base register to it. */
9629 if (dbl && HAVE_32BIT_GPRS)
9630 as_warn (_("dla used to load 32-bit register"));
9632 if (!dbl && HAVE_64BIT_OBJECTS)
9633 as_warn (_("la used to load 64-bit address"));
9635 if (small_offset_p (0, align, 16))
9637 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
9638 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9642 if (mips_opts.at && (op[0] == breg))
9650 if (offset_expr.X_op != O_symbol
9651 && offset_expr.X_op != O_constant)
9653 as_bad (_("Expression too complex"));
9654 offset_expr.X_op = O_constant;
9657 if (offset_expr.X_op == O_constant)
9658 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
9659 else if (mips_pic == NO_PIC)
9661 /* If this is a reference to a GP relative symbol, we want
9662 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9664 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9665 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9666 If we have a constant, we need two instructions anyhow,
9667 so we may as well always use the latter form.
9669 With 64bit address space and a usable $at we want
9670 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9671 lui $at,<sym> (BFD_RELOC_HI16_S)
9672 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9673 daddiu $at,<sym> (BFD_RELOC_LO16)
9675 daddu $tempreg,$tempreg,$at
9677 If $at is already in use, we use a path which is suboptimal
9678 on superscalar processors.
9679 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9680 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9682 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9684 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9686 For GP relative symbols in 64bit address space we can use
9687 the same sequence as in 32bit address space. */
9688 if (HAVE_64BIT_SYMBOLS)
9690 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9691 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9693 relax_start (offset_expr.X_add_symbol);
9694 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9695 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9699 if (used_at == 0 && mips_opts.at)
9701 macro_build (&offset_expr, "lui", LUI_FMT,
9702 tempreg, BFD_RELOC_MIPS_HIGHEST);
9703 macro_build (&offset_expr, "lui", LUI_FMT,
9704 AT, BFD_RELOC_HI16_S);
9705 macro_build (&offset_expr, "daddiu", "t,r,j",
9706 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9707 macro_build (&offset_expr, "daddiu", "t,r,j",
9708 AT, AT, BFD_RELOC_LO16);
9709 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9710 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9715 macro_build (&offset_expr, "lui", LUI_FMT,
9716 tempreg, BFD_RELOC_MIPS_HIGHEST);
9717 macro_build (&offset_expr, "daddiu", "t,r,j",
9718 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9719 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9720 macro_build (&offset_expr, "daddiu", "t,r,j",
9721 tempreg, tempreg, BFD_RELOC_HI16_S);
9722 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9723 macro_build (&offset_expr, "daddiu", "t,r,j",
9724 tempreg, tempreg, BFD_RELOC_LO16);
9727 if (mips_relax.sequence)
9732 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9733 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9735 relax_start (offset_expr.X_add_symbol);
9736 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9737 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9740 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9741 as_bad (_("Offset too large"));
9742 macro_build_lui (&offset_expr, tempreg);
9743 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9744 tempreg, tempreg, BFD_RELOC_LO16);
9745 if (mips_relax.sequence)
9749 else if (!mips_big_got && !HAVE_NEWABI)
9751 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9753 /* If this is a reference to an external symbol, and there
9754 is no constant, we want
9755 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9756 or for lca or if tempreg is PIC_CALL_REG
9757 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9758 For a local symbol, we want
9759 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9761 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9763 If we have a small constant, and this is a reference to
9764 an external symbol, we want
9765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9767 addiu $tempreg,$tempreg,<constant>
9768 For a local symbol, we want the same instruction
9769 sequence, but we output a BFD_RELOC_LO16 reloc on the
9772 If we have a large constant, and this is a reference to
9773 an external symbol, we want
9774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9775 lui $at,<hiconstant>
9776 addiu $at,$at,<loconstant>
9777 addu $tempreg,$tempreg,$at
9778 For a local symbol, we want the same instruction
9779 sequence, but we output a BFD_RELOC_LO16 reloc on the
9783 if (offset_expr.X_add_number == 0)
9785 if (mips_pic == SVR4_PIC
9787 && (call || tempreg == PIC_CALL_REG))
9788 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9790 relax_start (offset_expr.X_add_symbol);
9791 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9792 lw_reloc_type, mips_gp_register);
9795 /* We're going to put in an addu instruction using
9796 tempreg, so we may as well insert the nop right
9801 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9802 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9804 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9805 tempreg, tempreg, BFD_RELOC_LO16);
9807 /* FIXME: If breg == 0, and the next instruction uses
9808 $tempreg, then if this variant case is used an extra
9809 nop will be generated. */
9811 else if (offset_expr.X_add_number >= -0x8000
9812 && offset_expr.X_add_number < 0x8000)
9814 load_got_offset (tempreg, &offset_expr);
9816 add_got_offset (tempreg, &offset_expr);
9820 expr1.X_add_number = offset_expr.X_add_number;
9821 offset_expr.X_add_number =
9822 SEXT_16BIT (offset_expr.X_add_number);
9823 load_got_offset (tempreg, &offset_expr);
9824 offset_expr.X_add_number = expr1.X_add_number;
9825 /* If we are going to add in a base register, and the
9826 target register and the base register are the same,
9827 then we are using AT as a temporary register. Since
9828 we want to load the constant into AT, we add our
9829 current AT (from the global offset table) and the
9830 register into the register now, and pretend we were
9831 not using a base register. */
9835 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9840 add_got_offset_hilo (tempreg, &offset_expr, AT);
9844 else if (!mips_big_got && HAVE_NEWABI)
9846 int add_breg_early = 0;
9848 /* If this is a reference to an external, and there is no
9849 constant, or local symbol (*), with or without a
9851 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9852 or for lca or if tempreg is PIC_CALL_REG
9853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9855 If we have a small constant, and this is a reference to
9856 an external symbol, we want
9857 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9858 addiu $tempreg,$tempreg,<constant>
9860 If we have a large constant, and this is a reference to
9861 an external symbol, we want
9862 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9863 lui $at,<hiconstant>
9864 addiu $at,$at,<loconstant>
9865 addu $tempreg,$tempreg,$at
9867 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9868 local symbols, even though it introduces an additional
9871 if (offset_expr.X_add_number)
9873 expr1.X_add_number = offset_expr.X_add_number;
9874 offset_expr.X_add_number = 0;
9876 relax_start (offset_expr.X_add_symbol);
9877 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9878 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9880 if (expr1.X_add_number >= -0x8000
9881 && expr1.X_add_number < 0x8000)
9883 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9884 tempreg, tempreg, BFD_RELOC_LO16);
9886 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9890 /* If we are going to add in a base register, and the
9891 target register and the base register are the same,
9892 then we are using AT as a temporary register. Since
9893 we want to load the constant into AT, we add our
9894 current AT (from the global offset table) and the
9895 register into the register now, and pretend we were
9896 not using a base register. */
9901 gas_assert (tempreg == AT);
9902 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9908 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9915 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9918 offset_expr.X_add_number = expr1.X_add_number;
9920 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9921 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9924 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9925 op[0], tempreg, breg);
9931 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
9933 relax_start (offset_expr.X_add_symbol);
9934 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9935 BFD_RELOC_MIPS_CALL16, mips_gp_register);
9937 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9938 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9943 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9944 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9947 else if (mips_big_got && !HAVE_NEWABI)
9950 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9951 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9952 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9954 /* This is the large GOT case. If this is a reference to an
9955 external symbol, and there is no constant, we want
9956 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9957 addu $tempreg,$tempreg,$gp
9958 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9959 or for lca or if tempreg is PIC_CALL_REG
9960 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9961 addu $tempreg,$tempreg,$gp
9962 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9963 For a local symbol, we want
9964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9966 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9968 If we have a small constant, and this is a reference to
9969 an external symbol, we want
9970 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9971 addu $tempreg,$tempreg,$gp
9972 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9974 addiu $tempreg,$tempreg,<constant>
9975 For a local symbol, we want
9976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9978 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9980 If we have a large constant, and this is a reference to
9981 an external symbol, we want
9982 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9983 addu $tempreg,$tempreg,$gp
9984 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9985 lui $at,<hiconstant>
9986 addiu $at,$at,<loconstant>
9987 addu $tempreg,$tempreg,$at
9988 For a local symbol, we want
9989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9990 lui $at,<hiconstant>
9991 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9992 addu $tempreg,$tempreg,$at
9995 expr1.X_add_number = offset_expr.X_add_number;
9996 offset_expr.X_add_number = 0;
9997 relax_start (offset_expr.X_add_symbol);
9998 gpdelay = reg_needs_delay (mips_gp_register);
9999 if (expr1.X_add_number == 0 && breg == 0
10000 && (call || tempreg == PIC_CALL_REG))
10002 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10003 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10005 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10007 tempreg, tempreg, mips_gp_register);
10008 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10009 tempreg, lw_reloc_type, tempreg);
10010 if (expr1.X_add_number == 0)
10014 /* We're going to put in an addu instruction using
10015 tempreg, so we may as well insert the nop right
10020 else if (expr1.X_add_number >= -0x8000
10021 && expr1.X_add_number < 0x8000)
10024 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10025 tempreg, tempreg, BFD_RELOC_LO16);
10031 /* If we are going to add in a base register, and the
10032 target register and the base register are the same,
10033 then we are using AT as a temporary register. Since
10034 we want to load the constant into AT, we add our
10035 current AT (from the global offset table) and the
10036 register into the register now, and pretend we were
10037 not using a base register. */
10042 gas_assert (tempreg == AT);
10044 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10049 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10054 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10059 /* This is needed because this instruction uses $gp, but
10060 the first instruction on the main stream does not. */
10061 macro_build (NULL, "nop", "");
10064 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10065 local_reloc_type, mips_gp_register);
10066 if (expr1.X_add_number >= -0x8000
10067 && expr1.X_add_number < 0x8000)
10070 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10071 tempreg, tempreg, BFD_RELOC_LO16);
10072 /* FIXME: If add_number is 0, and there was no base
10073 register, the external symbol case ended with a load,
10074 so if the symbol turns out to not be external, and
10075 the next instruction uses tempreg, an unnecessary nop
10076 will be inserted. */
10082 /* We must add in the base register now, as in the
10083 external symbol case. */
10084 gas_assert (tempreg == AT);
10086 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10089 /* We set breg to 0 because we have arranged to add
10090 it in in both cases. */
10094 macro_build_lui (&expr1, AT);
10095 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10096 AT, AT, BFD_RELOC_LO16);
10097 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10098 tempreg, tempreg, AT);
10103 else if (mips_big_got && HAVE_NEWABI)
10105 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10106 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10107 int add_breg_early = 0;
10109 /* This is the large GOT case. If this is a reference to an
10110 external symbol, and there is no constant, we want
10111 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10112 add $tempreg,$tempreg,$gp
10113 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10114 or for lca or if tempreg is PIC_CALL_REG
10115 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10116 add $tempreg,$tempreg,$gp
10117 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10119 If we have a small constant, and this is a reference to
10120 an external symbol, we want
10121 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10122 add $tempreg,$tempreg,$gp
10123 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10124 addi $tempreg,$tempreg,<constant>
10126 If we have a large constant, and this is a reference to
10127 an external symbol, we want
10128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10129 addu $tempreg,$tempreg,$gp
10130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10131 lui $at,<hiconstant>
10132 addi $at,$at,<loconstant>
10133 add $tempreg,$tempreg,$at
10135 If we have NewABI, and we know it's a local symbol, we want
10136 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10137 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10138 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10140 relax_start (offset_expr.X_add_symbol);
10142 expr1.X_add_number = offset_expr.X_add_number;
10143 offset_expr.X_add_number = 0;
10145 if (expr1.X_add_number == 0 && breg == 0
10146 && (call || tempreg == PIC_CALL_REG))
10148 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10149 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10151 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10153 tempreg, tempreg, mips_gp_register);
10154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10155 tempreg, lw_reloc_type, tempreg);
10157 if (expr1.X_add_number == 0)
10159 else if (expr1.X_add_number >= -0x8000
10160 && expr1.X_add_number < 0x8000)
10162 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10163 tempreg, tempreg, BFD_RELOC_LO16);
10165 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10169 /* If we are going to add in a base register, and the
10170 target register and the base register are the same,
10171 then we are using AT as a temporary register. Since
10172 we want to load the constant into AT, we add our
10173 current AT (from the global offset table) and the
10174 register into the register now, and pretend we were
10175 not using a base register. */
10180 gas_assert (tempreg == AT);
10181 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10184 add_breg_early = 1;
10187 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10188 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10193 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10196 offset_expr.X_add_number = expr1.X_add_number;
10197 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10198 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10199 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10200 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10201 if (add_breg_early)
10203 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10204 op[0], tempreg, breg);
10214 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10218 gas_assert (!mips_opts.micromips);
10219 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10223 gas_assert (!mips_opts.micromips);
10224 macro_build (NULL, "c2", "C", 0x02);
10228 gas_assert (!mips_opts.micromips);
10229 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10233 gas_assert (!mips_opts.micromips);
10234 macro_build (NULL, "c2", "C", 3);
10238 gas_assert (!mips_opts.micromips);
10239 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10243 /* The j instruction may not be used in PIC code, since it
10244 requires an absolute address. We convert it to a b
10246 if (mips_pic == NO_PIC)
10247 macro_build (&offset_expr, "j", "a");
10249 macro_build (&offset_expr, "b", "p");
10252 /* The jal instructions must be handled as macros because when
10253 generating PIC code they expand to multi-instruction
10254 sequences. Normally they are simple instructions. */
10258 /* Fall through. */
10260 gas_assert (mips_opts.micromips);
10261 if (mips_opts.insn32)
10263 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10271 /* Fall through. */
10274 if (mips_pic == NO_PIC)
10276 s = jals ? "jalrs" : "jalr";
10277 if (mips_opts.micromips
10278 && !mips_opts.insn32
10280 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10281 macro_build (NULL, s, "mj", op[1]);
10283 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10287 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10288 && mips_cprestore_offset >= 0);
10290 if (op[1] != PIC_CALL_REG)
10291 as_warn (_("MIPS PIC call to register other than $25"));
10293 s = ((mips_opts.micromips
10294 && !mips_opts.insn32
10295 && (!mips_opts.noreorder || cprestore))
10296 ? "jalrs" : "jalr");
10297 if (mips_opts.micromips
10298 && !mips_opts.insn32
10300 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10301 macro_build (NULL, s, "mj", op[1]);
10303 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10304 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
10306 if (mips_cprestore_offset < 0)
10307 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10310 if (!mips_frame_reg_valid)
10312 as_warn (_("No .frame pseudo-op used in PIC code"));
10313 /* Quiet this warning. */
10314 mips_frame_reg_valid = 1;
10316 if (!mips_cprestore_valid)
10318 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10319 /* Quiet this warning. */
10320 mips_cprestore_valid = 1;
10322 if (mips_opts.noreorder)
10323 macro_build (NULL, "nop", "");
10324 expr1.X_add_number = mips_cprestore_offset;
10325 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10328 HAVE_64BIT_ADDRESSES);
10336 gas_assert (mips_opts.micromips);
10337 if (mips_opts.insn32)
10339 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10343 /* Fall through. */
10345 if (mips_pic == NO_PIC)
10346 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
10347 else if (mips_pic == SVR4_PIC)
10349 /* If this is a reference to an external symbol, and we are
10350 using a small GOT, we want
10351 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10355 lw $gp,cprestore($sp)
10356 The cprestore value is set using the .cprestore
10357 pseudo-op. If we are using a big GOT, we want
10358 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10360 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10364 lw $gp,cprestore($sp)
10365 If the symbol is not external, we want
10366 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10368 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10371 lw $gp,cprestore($sp)
10373 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10374 sequences above, minus nops, unless the symbol is local,
10375 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10381 relax_start (offset_expr.X_add_symbol);
10382 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10383 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10386 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10387 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
10393 relax_start (offset_expr.X_add_symbol);
10394 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10395 BFD_RELOC_MIPS_CALL_HI16);
10396 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10397 PIC_CALL_REG, mips_gp_register);
10398 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10399 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10402 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10403 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10405 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10406 PIC_CALL_REG, PIC_CALL_REG,
10407 BFD_RELOC_MIPS_GOT_OFST);
10411 macro_build_jalr (&offset_expr, 0);
10415 relax_start (offset_expr.X_add_symbol);
10418 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10419 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10428 gpdelay = reg_needs_delay (mips_gp_register);
10429 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10430 BFD_RELOC_MIPS_CALL_HI16);
10431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10432 PIC_CALL_REG, mips_gp_register);
10433 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10434 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10439 macro_build (NULL, "nop", "");
10441 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10442 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
10445 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10446 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
10448 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
10450 if (mips_cprestore_offset < 0)
10451 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10454 if (!mips_frame_reg_valid)
10456 as_warn (_("No .frame pseudo-op used in PIC code"));
10457 /* Quiet this warning. */
10458 mips_frame_reg_valid = 1;
10460 if (!mips_cprestore_valid)
10462 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10463 /* Quiet this warning. */
10464 mips_cprestore_valid = 1;
10466 if (mips_opts.noreorder)
10467 macro_build (NULL, "nop", "");
10468 expr1.X_add_number = mips_cprestore_offset;
10469 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10472 HAVE_64BIT_ADDRESSES);
10476 else if (mips_pic == VXWORKS_PIC)
10477 as_bad (_("Non-PIC jump used in PIC library"));
10584 gas_assert (!mips_opts.micromips);
10587 /* Itbl support may require additional care here. */
10593 /* Itbl support may require additional care here. */
10599 offbits = (mips_opts.micromips ? 12 : 16);
10600 /* Itbl support may require additional care here. */
10604 gas_assert (!mips_opts.micromips);
10607 /* Itbl support may require additional care here. */
10613 offbits = (mips_opts.micromips ? 12 : 16);
10618 offbits = (mips_opts.micromips ? 12 : 16);
10623 /* Itbl support may require additional care here. */
10629 offbits = (mips_opts.micromips ? 12 : 16);
10630 /* Itbl support may require additional care here. */
10636 /* Itbl support may require additional care here. */
10642 /* Itbl support may require additional care here. */
10648 offbits = (mips_opts.micromips ? 12 : 16);
10653 offbits = (mips_opts.micromips ? 12 : 16);
10658 offbits = (mips_opts.micromips ? 12 : 16);
10663 offbits = (mips_opts.micromips ? 12 : 16);
10668 offbits = (mips_opts.micromips ? 12 : 16);
10671 gas_assert (mips_opts.micromips);
10678 gas_assert (mips_opts.micromips);
10685 gas_assert (mips_opts.micromips);
10691 gas_assert (mips_opts.micromips);
10698 /* We don't want to use $0 as tempreg. */
10699 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
10702 tempreg = op[0] + lp;
10718 gas_assert (!mips_opts.micromips);
10721 /* Itbl support may require additional care here. */
10727 /* Itbl support may require additional care here. */
10733 offbits = (mips_opts.micromips ? 12 : 16);
10734 /* Itbl support may require additional care here. */
10738 gas_assert (!mips_opts.micromips);
10741 /* Itbl support may require additional care here. */
10747 offbits = (mips_opts.micromips ? 12 : 16);
10752 offbits = (mips_opts.micromips ? 12 : 16);
10757 offbits = (mips_opts.micromips ? 12 : 16);
10762 offbits = (mips_opts.micromips ? 12 : 16);
10766 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10767 offbits = (mips_opts.micromips ? 12 : 16);
10776 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10777 offbits = (mips_opts.micromips ? 12 : 16);
10788 /* Itbl support may require additional care here. */
10793 offbits = (mips_opts.micromips ? 12 : 16);
10794 /* Itbl support may require additional care here. */
10800 /* Itbl support may require additional care here. */
10804 gas_assert (!mips_opts.micromips);
10807 /* Itbl support may require additional care here. */
10813 offbits = (mips_opts.micromips ? 12 : 16);
10818 offbits = (mips_opts.micromips ? 12 : 16);
10821 gas_assert (mips_opts.micromips);
10827 gas_assert (mips_opts.micromips);
10833 gas_assert (mips_opts.micromips);
10839 gas_assert (mips_opts.micromips);
10848 if (small_offset_p (0, align, 16))
10850 /* The first case exists for M_LD_AB and M_SD_AB, which are
10851 macros for o32 but which should act like normal instructions
10854 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
10855 offset_reloc[1], offset_reloc[2], breg);
10856 else if (small_offset_p (0, align, offbits))
10859 macro_build (NULL, s, fmt, op[0], breg);
10861 macro_build (NULL, s, fmt, op[0],
10862 (int) offset_expr.X_add_number, breg);
10868 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10869 tempreg, breg, -1, offset_reloc[0],
10870 offset_reloc[1], offset_reloc[2]);
10872 macro_build (NULL, s, fmt, op[0], tempreg);
10874 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10882 if (offset_expr.X_op != O_constant
10883 && offset_expr.X_op != O_symbol)
10885 as_bad (_("Expression too complex"));
10886 offset_expr.X_op = O_constant;
10889 if (HAVE_32BIT_ADDRESSES
10890 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10894 sprintf_vma (value, offset_expr.X_add_number);
10895 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10898 /* A constant expression in PIC code can be handled just as it
10899 is in non PIC code. */
10900 if (offset_expr.X_op == O_constant)
10902 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10903 offbits == 0 ? 16 : offbits);
10904 offset_expr.X_add_number -= expr1.X_add_number;
10906 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10908 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10909 tempreg, tempreg, breg);
10912 if (offset_expr.X_add_number != 0)
10913 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10914 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10915 macro_build (NULL, s, fmt, op[0], tempreg);
10917 else if (offbits == 16)
10918 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10920 macro_build (NULL, s, fmt, op[0],
10921 (int) offset_expr.X_add_number, tempreg);
10923 else if (offbits != 16)
10925 /* The offset field is too narrow to be used for a low-part
10926 relocation, so load the whole address into the auxillary
10928 load_address (tempreg, &offset_expr, &used_at);
10930 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10931 tempreg, tempreg, breg);
10933 macro_build (NULL, s, fmt, op[0], tempreg);
10935 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10937 else if (mips_pic == NO_PIC)
10939 /* If this is a reference to a GP relative symbol, and there
10940 is no base register, we want
10941 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10942 Otherwise, if there is no base register, we want
10943 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10944 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10945 If we have a constant, we need two instructions anyhow,
10946 so we always use the latter form.
10948 If we have a base register, and this is a reference to a
10949 GP relative symbol, we want
10950 addu $tempreg,$breg,$gp
10951 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
10953 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10954 addu $tempreg,$tempreg,$breg
10955 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10956 With a constant we always use the latter case.
10958 With 64bit address space and no base register and $at usable,
10960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10961 lui $at,<sym> (BFD_RELOC_HI16_S)
10962 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10965 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10966 If we have a base register, we want
10967 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10968 lui $at,<sym> (BFD_RELOC_HI16_S)
10969 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10973 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10975 Without $at we can't generate the optimal path for superscalar
10976 processors here since this would require two temporary registers.
10977 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10978 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10980 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10982 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10983 If we have a base register, we want
10984 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10985 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10987 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10989 daddu $tempreg,$tempreg,$breg
10990 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10992 For GP relative symbols in 64bit address space we can use
10993 the same sequence as in 32bit address space. */
10994 if (HAVE_64BIT_SYMBOLS)
10996 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10997 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10999 relax_start (offset_expr.X_add_symbol);
11002 macro_build (&offset_expr, s, fmt, op[0],
11003 BFD_RELOC_GPREL16, mips_gp_register);
11007 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11008 tempreg, breg, mips_gp_register);
11009 macro_build (&offset_expr, s, fmt, op[0],
11010 BFD_RELOC_GPREL16, tempreg);
11015 if (used_at == 0 && mips_opts.at)
11017 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11018 BFD_RELOC_MIPS_HIGHEST);
11019 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11021 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11022 tempreg, BFD_RELOC_MIPS_HIGHER);
11024 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11025 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11026 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11027 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11033 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11034 BFD_RELOC_MIPS_HIGHEST);
11035 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11036 tempreg, BFD_RELOC_MIPS_HIGHER);
11037 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11038 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11039 tempreg, BFD_RELOC_HI16_S);
11040 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11042 macro_build (NULL, "daddu", "d,v,t",
11043 tempreg, tempreg, breg);
11044 macro_build (&offset_expr, s, fmt, op[0],
11045 BFD_RELOC_LO16, tempreg);
11048 if (mips_relax.sequence)
11055 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11056 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11058 relax_start (offset_expr.X_add_symbol);
11059 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11063 macro_build_lui (&offset_expr, tempreg);
11064 macro_build (&offset_expr, s, fmt, op[0],
11065 BFD_RELOC_LO16, tempreg);
11066 if (mips_relax.sequence)
11071 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11072 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11074 relax_start (offset_expr.X_add_symbol);
11075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11076 tempreg, breg, mips_gp_register);
11077 macro_build (&offset_expr, s, fmt, op[0],
11078 BFD_RELOC_GPREL16, tempreg);
11081 macro_build_lui (&offset_expr, tempreg);
11082 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11083 tempreg, tempreg, breg);
11084 macro_build (&offset_expr, s, fmt, op[0],
11085 BFD_RELOC_LO16, tempreg);
11086 if (mips_relax.sequence)
11090 else if (!mips_big_got)
11092 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11094 /* If this is a reference to an external symbol, we want
11095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11097 <op> op[0],0($tempreg)
11099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11101 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11102 <op> op[0],0($tempreg)
11104 For NewABI, we want
11105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11106 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11108 If there is a base register, we add it to $tempreg before
11109 the <op>. If there is a constant, we stick it in the
11110 <op> instruction. We don't handle constants larger than
11111 16 bits, because we have no way to load the upper 16 bits
11112 (actually, we could handle them for the subset of cases
11113 in which we are not using $at). */
11114 gas_assert (offset_expr.X_op == O_symbol);
11117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11118 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11121 tempreg, tempreg, breg);
11122 macro_build (&offset_expr, s, fmt, op[0],
11123 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11126 expr1.X_add_number = offset_expr.X_add_number;
11127 offset_expr.X_add_number = 0;
11128 if (expr1.X_add_number < -0x8000
11129 || expr1.X_add_number >= 0x8000)
11130 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11131 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11132 lw_reloc_type, mips_gp_register);
11134 relax_start (offset_expr.X_add_symbol);
11136 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11137 tempreg, BFD_RELOC_LO16);
11140 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11141 tempreg, tempreg, breg);
11142 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11144 else if (mips_big_got && !HAVE_NEWABI)
11148 /* If this is a reference to an external symbol, we want
11149 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11150 addu $tempreg,$tempreg,$gp
11151 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11152 <op> op[0],0($tempreg)
11154 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11156 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11157 <op> op[0],0($tempreg)
11158 If there is a base register, we add it to $tempreg before
11159 the <op>. If there is a constant, we stick it in the
11160 <op> instruction. We don't handle constants larger than
11161 16 bits, because we have no way to load the upper 16 bits
11162 (actually, we could handle them for the subset of cases
11163 in which we are not using $at). */
11164 gas_assert (offset_expr.X_op == O_symbol);
11165 expr1.X_add_number = offset_expr.X_add_number;
11166 offset_expr.X_add_number = 0;
11167 if (expr1.X_add_number < -0x8000
11168 || expr1.X_add_number >= 0x8000)
11169 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11170 gpdelay = reg_needs_delay (mips_gp_register);
11171 relax_start (offset_expr.X_add_symbol);
11172 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11173 BFD_RELOC_MIPS_GOT_HI16);
11174 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11176 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11177 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11180 macro_build (NULL, "nop", "");
11181 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11182 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11184 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11185 tempreg, BFD_RELOC_LO16);
11189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11190 tempreg, tempreg, breg);
11191 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11193 else if (mips_big_got && HAVE_NEWABI)
11195 /* If this is a reference to an external symbol, we want
11196 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11197 add $tempreg,$tempreg,$gp
11198 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11199 <op> op[0],<ofst>($tempreg)
11200 Otherwise, for local symbols, we want:
11201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11202 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11203 gas_assert (offset_expr.X_op == O_symbol);
11204 expr1.X_add_number = offset_expr.X_add_number;
11205 offset_expr.X_add_number = 0;
11206 if (expr1.X_add_number < -0x8000
11207 || expr1.X_add_number >= 0x8000)
11208 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11209 relax_start (offset_expr.X_add_symbol);
11210 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11211 BFD_RELOC_MIPS_GOT_HI16);
11212 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11214 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11215 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11217 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11218 tempreg, tempreg, breg);
11219 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11222 offset_expr.X_add_number = expr1.X_add_number;
11223 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11224 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11227 tempreg, tempreg, breg);
11228 macro_build (&offset_expr, s, fmt, op[0],
11229 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11238 gas_assert (mips_opts.micromips);
11239 gas_assert (mips_opts.insn32);
11240 start_noreorder ();
11241 macro_build (NULL, "jr", "s", RA);
11242 expr1.X_add_number = op[0] << 2;
11243 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11248 gas_assert (mips_opts.micromips);
11249 gas_assert (mips_opts.insn32);
11250 macro_build (NULL, "jr", "s", op[0]);
11251 if (mips_opts.noreorder)
11252 macro_build (NULL, "nop", "");
11257 load_register (op[0], &imm_expr, 0);
11261 load_register (op[0], &imm_expr, 1);
11265 if (imm_expr.X_op == O_constant)
11268 load_register (AT, &imm_expr, 0);
11269 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11274 gas_assert (offset_expr.X_op == O_symbol
11275 && strcmp (segment_name (S_GET_SEGMENT
11276 (offset_expr.X_add_symbol)),
11278 && offset_expr.X_add_number == 0);
11279 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
11280 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
11285 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11286 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11287 order 32 bits of the value and the low order 32 bits are either
11288 zero or in OFFSET_EXPR. */
11289 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11291 if (HAVE_64BIT_GPRS)
11292 load_register (op[0], &imm_expr, 1);
11297 if (target_big_endian)
11309 load_register (hreg, &imm_expr, 0);
11312 if (offset_expr.X_op == O_absent)
11313 move_register (lreg, 0);
11316 gas_assert (offset_expr.X_op == O_constant);
11317 load_register (lreg, &offset_expr, 0);
11324 /* We know that sym is in the .rdata section. First we get the
11325 upper 16 bits of the address. */
11326 if (mips_pic == NO_PIC)
11328 macro_build_lui (&offset_expr, AT);
11333 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11334 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11338 /* Now we load the register(s). */
11339 if (HAVE_64BIT_GPRS)
11342 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11343 BFD_RELOC_LO16, AT);
11348 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11349 BFD_RELOC_LO16, AT);
11352 /* FIXME: How in the world do we deal with the possible
11354 offset_expr.X_add_number += 4;
11355 macro_build (&offset_expr, "lw", "t,o(b)",
11356 op[0] + 1, BFD_RELOC_LO16, AT);
11362 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11363 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11364 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11365 the value and the low order 32 bits are either zero or in
11367 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11370 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
11371 if (HAVE_64BIT_FPRS)
11373 gas_assert (HAVE_64BIT_GPRS);
11374 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
11378 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
11379 if (offset_expr.X_op == O_absent)
11380 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
11383 gas_assert (offset_expr.X_op == O_constant);
11384 load_register (AT, &offset_expr, 0);
11385 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11391 gas_assert (offset_expr.X_op == O_symbol
11392 && offset_expr.X_add_number == 0);
11393 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11394 if (strcmp (s, ".lit8") == 0)
11396 op[2] = mips_gp_register;
11397 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11398 offset_reloc[1] = BFD_RELOC_UNUSED;
11399 offset_reloc[2] = BFD_RELOC_UNUSED;
11403 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
11405 if (mips_pic != NO_PIC)
11406 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11407 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11410 /* FIXME: This won't work for a 64 bit address. */
11411 macro_build_lui (&offset_expr, AT);
11415 offset_reloc[0] = BFD_RELOC_LO16;
11416 offset_reloc[1] = BFD_RELOC_UNUSED;
11417 offset_reloc[2] = BFD_RELOC_UNUSED;
11424 * The MIPS assembler seems to check for X_add_number not
11425 * being double aligned and generating:
11426 * lui at,%hi(foo+1)
11428 * addiu at,at,%lo(foo+1)
11431 * But, the resulting address is the same after relocation so why
11432 * generate the extra instruction?
11434 /* Itbl support may require additional care here. */
11437 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11446 gas_assert (!mips_opts.micromips);
11447 /* Itbl support may require additional care here. */
11450 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11470 if (HAVE_64BIT_GPRS)
11480 if (HAVE_64BIT_GPRS)
11488 /* Even on a big endian machine $fn comes before $fn+1. We have
11489 to adjust when loading from memory. We set coproc if we must
11490 load $fn+1 first. */
11491 /* Itbl support may require additional care here. */
11492 if (!target_big_endian)
11496 if (small_offset_p (0, align, 16))
11499 if (!small_offset_p (4, align, 16))
11501 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11502 -1, offset_reloc[0], offset_reloc[1],
11504 expr1.X_add_number = 0;
11508 offset_reloc[0] = BFD_RELOC_LO16;
11509 offset_reloc[1] = BFD_RELOC_UNUSED;
11510 offset_reloc[2] = BFD_RELOC_UNUSED;
11512 if (strcmp (s, "lw") == 0 && op[0] == breg)
11514 ep->X_add_number += 4;
11515 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
11516 offset_reloc[1], offset_reloc[2], breg);
11517 ep->X_add_number -= 4;
11518 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
11519 offset_reloc[1], offset_reloc[2], breg);
11523 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
11524 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11526 ep->X_add_number += 4;
11527 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
11528 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11534 if (offset_expr.X_op != O_symbol
11535 && offset_expr.X_op != O_constant)
11537 as_bad (_("Expression too complex"));
11538 offset_expr.X_op = O_constant;
11541 if (HAVE_32BIT_ADDRESSES
11542 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11546 sprintf_vma (value, offset_expr.X_add_number);
11547 as_bad (_("Number (0x%s) larger than 32 bits"), value);
11550 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
11552 /* If this is a reference to a GP relative symbol, we want
11553 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11554 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11555 If we have a base register, we use this
11557 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11558 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11559 If this is not a GP relative symbol, we want
11560 lui $at,<sym> (BFD_RELOC_HI16_S)
11561 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11562 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11563 If there is a base register, we add it to $at after the
11564 lui instruction. If there is a constant, we always use
11566 if (offset_expr.X_op == O_symbol
11567 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11568 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11570 relax_start (offset_expr.X_add_symbol);
11573 tempreg = mips_gp_register;
11577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11578 AT, breg, mips_gp_register);
11583 /* Itbl support may require additional care here. */
11584 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11585 BFD_RELOC_GPREL16, tempreg);
11586 offset_expr.X_add_number += 4;
11588 /* Set mips_optimize to 2 to avoid inserting an
11590 hold_mips_optimize = mips_optimize;
11592 /* Itbl support may require additional care here. */
11593 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11594 BFD_RELOC_GPREL16, tempreg);
11595 mips_optimize = hold_mips_optimize;
11599 offset_expr.X_add_number -= 4;
11602 if (offset_high_part (offset_expr.X_add_number, 16)
11603 != offset_high_part (offset_expr.X_add_number + 4, 16))
11605 load_address (AT, &offset_expr, &used_at);
11606 offset_expr.X_op = O_constant;
11607 offset_expr.X_add_number = 0;
11610 macro_build_lui (&offset_expr, AT);
11612 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11613 /* Itbl support may require additional care here. */
11614 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11615 BFD_RELOC_LO16, AT);
11616 /* FIXME: How do we handle overflow here? */
11617 offset_expr.X_add_number += 4;
11618 /* Itbl support may require additional care here. */
11619 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11620 BFD_RELOC_LO16, AT);
11621 if (mips_relax.sequence)
11624 else if (!mips_big_got)
11626 /* If this is a reference to an external symbol, we want
11627 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11630 <op> op[0]+1,4($at)
11632 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11634 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11635 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11636 If there is a base register we add it to $at before the
11637 lwc1 instructions. If there is a constant we include it
11638 in the lwc1 instructions. */
11640 expr1.X_add_number = offset_expr.X_add_number;
11641 if (expr1.X_add_number < -0x8000
11642 || expr1.X_add_number >= 0x8000 - 4)
11643 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11644 load_got_offset (AT, &offset_expr);
11647 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11649 /* Set mips_optimize to 2 to avoid inserting an undesired
11651 hold_mips_optimize = mips_optimize;
11654 /* Itbl support may require additional care here. */
11655 relax_start (offset_expr.X_add_symbol);
11656 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11657 BFD_RELOC_LO16, AT);
11658 expr1.X_add_number += 4;
11659 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11660 BFD_RELOC_LO16, AT);
11662 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11663 BFD_RELOC_LO16, AT);
11664 offset_expr.X_add_number += 4;
11665 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11666 BFD_RELOC_LO16, AT);
11669 mips_optimize = hold_mips_optimize;
11671 else if (mips_big_got)
11675 /* If this is a reference to an external symbol, we want
11676 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11678 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11681 <op> op[0]+1,4($at)
11683 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11685 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11686 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11687 If there is a base register we add it to $at before the
11688 lwc1 instructions. If there is a constant we include it
11689 in the lwc1 instructions. */
11691 expr1.X_add_number = offset_expr.X_add_number;
11692 offset_expr.X_add_number = 0;
11693 if (expr1.X_add_number < -0x8000
11694 || expr1.X_add_number >= 0x8000 - 4)
11695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11696 gpdelay = reg_needs_delay (mips_gp_register);
11697 relax_start (offset_expr.X_add_symbol);
11698 macro_build (&offset_expr, "lui", LUI_FMT,
11699 AT, BFD_RELOC_MIPS_GOT_HI16);
11700 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11701 AT, AT, mips_gp_register);
11702 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11703 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
11706 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11707 /* Itbl support may require additional care here. */
11708 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11709 BFD_RELOC_LO16, AT);
11710 expr1.X_add_number += 4;
11712 /* Set mips_optimize to 2 to avoid inserting an undesired
11714 hold_mips_optimize = mips_optimize;
11716 /* Itbl support may require additional care here. */
11717 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11718 BFD_RELOC_LO16, AT);
11719 mips_optimize = hold_mips_optimize;
11720 expr1.X_add_number -= 4;
11723 offset_expr.X_add_number = expr1.X_add_number;
11725 macro_build (NULL, "nop", "");
11726 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11727 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11731 /* Itbl support may require additional care here. */
11732 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11733 BFD_RELOC_LO16, AT);
11734 offset_expr.X_add_number += 4;
11736 /* Set mips_optimize to 2 to avoid inserting an undesired
11738 hold_mips_optimize = mips_optimize;
11740 /* Itbl support may require additional care here. */
11741 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11742 BFD_RELOC_LO16, AT);
11743 mips_optimize = hold_mips_optimize;
11762 /* New code added to support COPZ instructions.
11763 This code builds table entries out of the macros in mip_opcodes.
11764 R4000 uses interlocks to handle coproc delays.
11765 Other chips (like the R3000) require nops to be inserted for delays.
11767 FIXME: Currently, we require that the user handle delays.
11768 In order to fill delay slots for non-interlocked chips,
11769 we must have a way to specify delays based on the coprocessor.
11770 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11771 What are the side-effects of the cop instruction?
11772 What cache support might we have and what are its effects?
11773 Both coprocessor & memory require delays. how long???
11774 What registers are read/set/modified?
11776 If an itbl is provided to interpret cop instructions,
11777 this knowledge can be encoded in the itbl spec. */
11791 gas_assert (!mips_opts.micromips);
11792 /* For now we just do C (same as Cz). The parameter will be
11793 stored in insn_opcode by mips_ip. */
11794 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11798 move_register (op[0], op[1]);
11802 gas_assert (mips_opts.micromips);
11803 gas_assert (mips_opts.insn32);
11804 move_register (micromips_to_32_reg_h_map1[op[0]],
11805 micromips_to_32_reg_m_map[op[1]]);
11806 move_register (micromips_to_32_reg_h_map2[op[0]],
11807 micromips_to_32_reg_n_map[op[2]]);
11813 if (mips_opts.arch == CPU_R5900)
11814 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11818 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11819 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11826 /* The MIPS assembler some times generates shifts and adds. I'm
11827 not trying to be that fancy. GCC should do this for us
11830 load_register (AT, &imm_expr, dbl);
11831 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11832 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11845 start_noreorder ();
11848 load_register (AT, &imm_expr, dbl);
11849 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11850 op[1], imm ? AT : op[2]);
11851 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11852 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
11853 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11855 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
11858 if (mips_opts.micromips)
11859 micromips_label_expr (&label_expr);
11861 label_expr.X_add_number = 8;
11862 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
11863 macro_build (NULL, "nop", "");
11864 macro_build (NULL, "break", BRK_FMT, 6);
11865 if (mips_opts.micromips)
11866 micromips_add_label ();
11869 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11882 start_noreorder ();
11885 load_register (AT, &imm_expr, dbl);
11886 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11887 op[1], imm ? AT : op[2]);
11888 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11889 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11891 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11894 if (mips_opts.micromips)
11895 micromips_label_expr (&label_expr);
11897 label_expr.X_add_number = 8;
11898 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11899 macro_build (NULL, "nop", "");
11900 macro_build (NULL, "break", BRK_FMT, 6);
11901 if (mips_opts.micromips)
11902 micromips_add_label ();
11908 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11910 if (op[0] == op[1])
11917 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
11918 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
11922 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
11923 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
11924 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
11925 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11929 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11931 if (op[0] == op[1])
11938 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
11939 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
11943 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
11944 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
11945 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
11946 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11955 if (imm_expr.X_op != O_constant)
11956 as_bad (_("Improper rotate count"));
11957 rot = imm_expr.X_add_number & 0x3f;
11958 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11960 rot = (64 - rot) & 0x3f;
11962 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
11964 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
11969 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
11972 l = (rot < 0x20) ? "dsll" : "dsll32";
11973 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
11976 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
11977 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
11978 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11986 if (imm_expr.X_op != O_constant)
11987 as_bad (_("Improper rotate count"));
11988 rot = imm_expr.X_add_number & 0x1f;
11989 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11991 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
11992 (32 - rot) & 0x1f);
11997 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12001 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12002 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12003 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12008 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12010 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12014 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12015 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12016 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12017 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12021 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12023 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12027 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12028 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12029 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12030 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12039 if (imm_expr.X_op != O_constant)
12040 as_bad (_("Improper rotate count"));
12041 rot = imm_expr.X_add_number & 0x3f;
12042 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12045 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12047 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12052 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12055 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12056 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12059 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12060 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12061 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12069 if (imm_expr.X_op != O_constant)
12070 as_bad (_("Improper rotate count"));
12071 rot = imm_expr.X_add_number & 0x1f;
12072 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12074 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12079 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12083 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12084 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12085 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12091 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12092 else if (op[2] == 0)
12093 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12096 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12097 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12102 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12104 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12109 as_warn (_("Instruction %s: result is always false"),
12110 ip->insn_mo->name);
12111 move_register (op[0], 0);
12114 if (CPU_HAS_SEQ (mips_opts.arch)
12115 && -512 <= imm_expr.X_add_number
12116 && imm_expr.X_add_number < 512)
12118 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12119 (int) imm_expr.X_add_number);
12122 if (imm_expr.X_op == O_constant
12123 && imm_expr.X_add_number >= 0
12124 && imm_expr.X_add_number < 0x10000)
12125 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12126 else if (imm_expr.X_op == O_constant
12127 && imm_expr.X_add_number > -0x8000
12128 && imm_expr.X_add_number < 0)
12130 imm_expr.X_add_number = -imm_expr.X_add_number;
12131 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12132 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12134 else if (CPU_HAS_SEQ (mips_opts.arch))
12137 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12138 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12143 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12144 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12147 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12150 case M_SGE: /* X >= Y <==> not (X < Y) */
12156 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12157 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12160 case M_SGE_I: /* X >= I <==> not (X < I) */
12162 if (imm_expr.X_op == O_constant
12163 && imm_expr.X_add_number >= -0x8000
12164 && imm_expr.X_add_number < 0x8000)
12165 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12166 op[0], op[1], BFD_RELOC_LO16);
12169 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12170 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12174 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12177 case M_SGT: /* X > Y <==> Y < X */
12183 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12186 case M_SGT_I: /* X > I <==> I < X */
12193 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12194 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12197 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12203 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12204 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12207 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12214 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12215 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12216 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12220 if (imm_expr.X_op == O_constant
12221 && imm_expr.X_add_number >= -0x8000
12222 && imm_expr.X_add_number < 0x8000)
12224 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12229 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12230 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12234 if (imm_expr.X_op == O_constant
12235 && imm_expr.X_add_number >= -0x8000
12236 && imm_expr.X_add_number < 0x8000)
12238 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12243 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12244 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12249 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12250 else if (op[2] == 0)
12251 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12254 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12255 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12260 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12262 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12267 as_warn (_("Instruction %s: result is always true"),
12268 ip->insn_mo->name);
12269 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
12270 op[0], 0, BFD_RELOC_LO16);
12273 if (CPU_HAS_SEQ (mips_opts.arch)
12274 && -512 <= imm_expr.X_add_number
12275 && imm_expr.X_add_number < 512)
12277 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
12278 (int) imm_expr.X_add_number);
12281 if (imm_expr.X_op == O_constant
12282 && imm_expr.X_add_number >= 0
12283 && imm_expr.X_add_number < 0x10000)
12285 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12288 else if (imm_expr.X_op == O_constant
12289 && imm_expr.X_add_number > -0x8000
12290 && imm_expr.X_add_number < 0)
12292 imm_expr.X_add_number = -imm_expr.X_add_number;
12293 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12294 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12296 else if (CPU_HAS_SEQ (mips_opts.arch))
12299 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12300 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
12305 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12306 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12309 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12324 if (!mips_opts.micromips)
12326 if (imm_expr.X_op == O_constant
12327 && imm_expr.X_add_number > -0x200
12328 && imm_expr.X_add_number <= 0x200)
12330 macro_build (NULL, s, "t,r,.", op[0], op[1], -imm_expr.X_add_number);
12339 if (imm_expr.X_op == O_constant
12340 && imm_expr.X_add_number > -0x8000
12341 && imm_expr.X_add_number <= 0x8000)
12343 imm_expr.X_add_number = -imm_expr.X_add_number;
12344 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12349 load_register (AT, &imm_expr, dbl);
12350 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
12372 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12373 macro_build (NULL, s, "s,t", op[0], AT);
12378 gas_assert (!mips_opts.micromips);
12379 gas_assert (mips_opts.isa == ISA_MIPS1);
12383 * Is the double cfc1 instruction a bug in the mips assembler;
12384 * or is there a reason for it?
12386 start_noreorder ();
12387 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12388 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12389 macro_build (NULL, "nop", "");
12390 expr1.X_add_number = 3;
12391 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
12392 expr1.X_add_number = 2;
12393 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12394 macro_build (NULL, "ctc1", "t,G", AT, RA);
12395 macro_build (NULL, "nop", "");
12396 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
12398 macro_build (NULL, "ctc1", "t,G", op[2], RA);
12399 macro_build (NULL, "nop", "");
12416 offbits = (mips_opts.micromips ? 12 : 16);
12422 offbits = (mips_opts.micromips ? 12 : 16);
12434 offbits = (mips_opts.micromips ? 12 : 16);
12441 offbits = (mips_opts.micromips ? 12 : 16);
12447 large_offset = !small_offset_p (off, align, offbits);
12449 expr1.X_add_number = 0;
12454 if (small_offset_p (0, align, 16))
12455 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12456 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12459 load_address (tempreg, ep, &used_at);
12461 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12462 tempreg, tempreg, breg);
12464 offset_reloc[0] = BFD_RELOC_LO16;
12465 offset_reloc[1] = BFD_RELOC_UNUSED;
12466 offset_reloc[2] = BFD_RELOC_UNUSED;
12471 else if (!ust && op[0] == breg)
12482 if (!target_big_endian)
12483 ep->X_add_number += off;
12485 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
12487 macro_build (ep, s, "t,o(b)", tempreg, -1,
12488 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12490 if (!target_big_endian)
12491 ep->X_add_number -= off;
12493 ep->X_add_number += off;
12495 macro_build (NULL, s2, "t,~(b)",
12496 tempreg, (int) ep->X_add_number, breg);
12498 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12499 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12501 /* If necessary, move the result in tempreg to the final destination. */
12502 if (!ust && op[0] != tempreg)
12504 /* Protect second load's delay slot. */
12506 move_register (op[0], tempreg);
12512 if (target_big_endian == ust)
12513 ep->X_add_number += off;
12514 tempreg = ust || large_offset ? op[0] : AT;
12515 macro_build (ep, s, "t,o(b)", tempreg, -1,
12516 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12518 /* For halfword transfers we need a temporary register to shuffle
12519 bytes. Unfortunately for M_USH_A we have none available before
12520 the next store as AT holds the base address. We deal with this
12521 case by clobbering TREG and then restoring it as with ULH. */
12522 tempreg = ust == large_offset ? op[0] : AT;
12524 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
12526 if (target_big_endian == ust)
12527 ep->X_add_number -= off;
12529 ep->X_add_number += off;
12530 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12531 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12533 /* For M_USH_A re-retrieve the LSB. */
12534 if (ust && large_offset)
12536 if (target_big_endian)
12537 ep->X_add_number += off;
12539 ep->X_add_number -= off;
12540 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12541 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
12543 /* For ULH and M_USH_A OR the LSB in. */
12544 if (!ust || large_offset)
12546 tempreg = !large_offset ? AT : op[0];
12547 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
12548 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12553 /* FIXME: Check if this is one of the itbl macros, since they
12554 are added dynamically. */
12555 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
12558 if (!mips_opts.at && used_at)
12559 as_bad (_("Macro used $at after \".set noat\""));
12562 /* Implement macros in mips16 mode. */
12565 mips16_macro (struct mips_cl_insn *ip)
12567 const struct mips_operand_array *operands;
12572 const char *s, *s2, *s3;
12573 unsigned int op[MAX_OPERANDS];
12576 mask = ip->insn_mo->mask;
12578 operands = insn_operands (ip);
12579 for (i = 0; i < MAX_OPERANDS; i++)
12580 if (operands->operand[i])
12581 op[i] = insn_extract_operand (ip, operands->operand[i]);
12585 expr1.X_op = O_constant;
12586 expr1.X_op_symbol = NULL;
12587 expr1.X_add_symbol = NULL;
12588 expr1.X_add_number = 1;
12607 start_noreorder ();
12608 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
12609 expr1.X_add_number = 2;
12610 macro_build (&expr1, "bnez", "x,p", op[2]);
12611 macro_build (NULL, "break", "6", 7);
12613 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12614 since that causes an overflow. We should do that as well,
12615 but I don't see how to do the comparisons without a temporary
12618 macro_build (NULL, s, "x", op[0]);
12637 start_noreorder ();
12638 macro_build (NULL, s, "0,x,y", op[1], op[2]);
12639 expr1.X_add_number = 2;
12640 macro_build (&expr1, "bnez", "x,p", op[2]);
12641 macro_build (NULL, "break", "6", 7);
12643 macro_build (NULL, s2, "x", op[0]);
12649 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12650 macro_build (NULL, "mflo", "x", op[0]);
12658 if (imm_expr.X_op != O_constant)
12659 as_bad (_("Unsupported large constant"));
12660 imm_expr.X_add_number = -imm_expr.X_add_number;
12661 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
12665 if (imm_expr.X_op != O_constant)
12666 as_bad (_("Unsupported large constant"));
12667 imm_expr.X_add_number = -imm_expr.X_add_number;
12668 macro_build (&imm_expr, "addiu", "x,k", op[0]);
12672 if (imm_expr.X_op != O_constant)
12673 as_bad (_("Unsupported large constant"));
12674 imm_expr.X_add_number = -imm_expr.X_add_number;
12675 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
12697 goto do_reverse_branch;
12701 goto do_reverse_branch;
12713 goto do_reverse_branch;
12724 macro_build (NULL, s, "x,y", op[0], op[1]);
12725 macro_build (&offset_expr, s2, "p");
12752 goto do_addone_branch_i;
12757 goto do_addone_branch_i;
12772 goto do_addone_branch_i;
12778 do_addone_branch_i:
12779 if (imm_expr.X_op != O_constant)
12780 as_bad (_("Unsupported large constant"));
12781 ++imm_expr.X_add_number;
12784 macro_build (&imm_expr, s, s3, op[0]);
12785 macro_build (&offset_expr, s2, "p");
12789 expr1.X_add_number = 0;
12790 macro_build (&expr1, "slti", "x,8", op[1]);
12791 if (op[0] != op[1])
12792 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
12793 expr1.X_add_number = 2;
12794 macro_build (&expr1, "bteqz", "p");
12795 macro_build (NULL, "neg", "x,w", op[0], op[0]);
12800 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12801 opcode bits in *OPCODE_EXTRA. */
12803 static struct mips_opcode *
12804 mips_lookup_insn (struct hash_control *hash, const char *start,
12805 ssize_t length, unsigned int *opcode_extra)
12807 char *name, *dot, *p;
12808 unsigned int mask, suffix;
12810 struct mips_opcode *insn;
12812 /* Make a copy of the instruction so that we can fiddle with it. */
12813 name = alloca (length + 1);
12814 memcpy (name, start, length);
12815 name[length] = '\0';
12817 /* Look up the instruction as-is. */
12818 insn = (struct mips_opcode *) hash_find (hash, name);
12822 dot = strchr (name, '.');
12825 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12826 p = mips_parse_vu0_channels (dot + 1, &mask);
12827 if (*p == 0 && mask != 0)
12830 insn = (struct mips_opcode *) hash_find (hash, name);
12832 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12834 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12840 if (mips_opts.micromips)
12842 /* See if there's an instruction size override suffix,
12843 either `16' or `32', at the end of the mnemonic proper,
12844 that defines the operation, i.e. before the first `.'
12845 character if any. Strip it and retry. */
12846 opend = dot != NULL ? dot - name : length;
12847 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12849 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12855 memcpy (name + opend - 2, name + opend, length - opend + 1);
12856 insn = (struct mips_opcode *) hash_find (hash, name);
12859 forced_insn_length = suffix;
12868 /* Assemble an instruction into its binary format. If the instruction
12869 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12870 associated with "I", "+I" and "A" operands respectively. Otherwise
12871 store the value of the relocatable field (if any) in offset_expr.
12872 In both cases set offset_reloc to the relocation operators applied
12876 mips_ip (char *str, struct mips_cl_insn *ip)
12878 bfd_boolean wrong_delay_slot_insns = FALSE;
12879 bfd_boolean need_delay_slot_ok = TRUE;
12880 struct mips_opcode *firstinsn = NULL;
12881 const struct mips_opcode *past;
12882 struct hash_control *hash;
12883 struct mips_opcode *first, *insn;
12886 struct mips_operand_token *tokens;
12887 unsigned int opcode_extra;
12891 if (mips_opts.micromips)
12893 hash = micromips_op_hash;
12894 past = µmips_opcodes[bfd_micromips_num_opcodes];
12899 past = &mips_opcodes[NUMOPCODES];
12901 forced_insn_length = 0;
12905 /* We first try to match an instruction up to a space or to the end. */
12906 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12909 first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
12912 insn_error = _("Unrecognized opcode");
12915 /* When no opcode suffix is specified, assume ".xyzw". */
12916 if ((insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
12917 opcode_extra = 0xf << mips_vu0_channel_mask.lsb;
12919 if (strcmp (insn->name, "li.s") == 0)
12921 else if (strcmp (insn->name, "li.d") == 0)
12925 tokens = mips_parse_arguments (str + end, format);
12929 /* For microMIPS instructions placed in a fixed-length branch delay slot
12930 we make up to two passes over the relevant fragment of the opcode
12931 table. First we try instructions that meet the delay slot's length
12932 requirement. If none matched, then we retry with the remaining ones
12933 and if one matches, then we use it and then issue an appropriate
12934 warning later on. */
12937 bfd_boolean delay_slot_ok;
12938 bfd_boolean size_ok;
12940 bfd_boolean more_alts;
12942 gas_assert (strcmp (insn->name, first->name) == 0);
12944 ok = is_opcode_valid (insn);
12945 size_ok = is_size_valid (insn);
12946 delay_slot_ok = is_delay_slot_valid (insn);
12947 if (!delay_slot_ok && !wrong_delay_slot_insns)
12950 wrong_delay_slot_insns = TRUE;
12952 more_alts = (insn + 1 < past
12953 && strcmp (insn[0].name, insn[1].name) == 0);
12954 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
12956 static char buf[256];
12963 if (wrong_delay_slot_insns && need_delay_slot_ok)
12965 gas_assert (firstinsn);
12966 need_delay_slot_ok = FALSE;
12972 obstack_free (&mips_operand_tokens, tokens);
12977 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
12978 mips_cpu_info_from_arch (mips_opts.arch)->name,
12979 mips_cpu_info_from_isa (mips_opts.isa)->name);
12980 else if (mips_opts.insn32)
12981 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
12983 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
12984 8 * forced_insn_length);
12990 if (match_insn (ip, insn, tokens, opcode_extra, more_alts,
12991 more_alts || (wrong_delay_slot_insns
12992 && need_delay_slot_ok)))
12994 obstack_free (&mips_operand_tokens, tokens);
12998 /* Args don't match. */
12999 insn_error = _("Illegal operands");
13005 if (wrong_delay_slot_insns && need_delay_slot_ok)
13007 gas_assert (firstinsn);
13008 need_delay_slot_ok = FALSE;
13013 obstack_free (&mips_operand_tokens, tokens);
13018 /* As for mips_ip, but used when assembling MIPS16 code.
13019 Also set forced_insn_length to the resulting instruction size in
13020 bytes if the user explicitly requested a small or extended instruction. */
13023 mips16_ip (char *str, struct mips_cl_insn *ip)
13026 struct mips_opcode *insn;
13027 struct mips_operand_token *tokens;
13031 forced_insn_length = 0;
13033 for (s = str; ISLOWER (*s); ++s)
13045 if (s[1] == 't' && s[2] == ' ')
13048 forced_insn_length = 2;
13052 else if (s[1] == 'e' && s[2] == ' ')
13055 forced_insn_length = 4;
13059 /* Fall through. */
13061 insn_error = _("unknown opcode");
13065 if (mips_opts.noautoextend && !forced_insn_length)
13066 forced_insn_length = 2;
13068 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13070 insn_error = _("unrecognized opcode");
13074 tokens = mips_parse_arguments (s, 0);
13081 bfd_boolean more_alts;
13083 gas_assert (strcmp (insn->name, str) == 0);
13085 ok = is_opcode_valid_16 (insn);
13086 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13087 && strcmp (insn[0].name, insn[1].name) == 0);
13099 static char buf[100];
13101 _("Opcode not supported on this processor: %s (%s)"),
13102 mips_cpu_info_from_arch (mips_opts.arch)->name,
13103 mips_cpu_info_from_isa (mips_opts.isa)->name);
13106 obstack_free (&mips_operand_tokens, tokens);
13111 if (match_mips16_insn (ip, insn, tokens, more_alts))
13113 obstack_free (&mips_operand_tokens, tokens);
13117 /* Args don't match. */
13124 insn_error = _("illegal operands");
13126 obstack_free (&mips_operand_tokens, tokens);
13131 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13132 NBITS is the number of significant bits in VAL. */
13134 static unsigned long
13135 mips16_immed_extend (offsetT val, unsigned int nbits)
13140 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13143 else if (nbits == 15)
13145 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13150 extval = ((val & 0x1f) << 6) | (val & 0x20);
13153 return (extval << 16) | val;
13156 /* Like decode_mips16_operand, but require the operand to be defined and
13157 require it to be an integer. */
13159 static const struct mips_int_operand *
13160 mips16_immed_operand (int type, bfd_boolean extended_p)
13162 const struct mips_operand *operand;
13164 operand = decode_mips16_operand (type, extended_p);
13165 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13167 return (const struct mips_int_operand *) operand;
13170 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13173 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13174 bfd_reloc_code_real_type reloc, offsetT sval)
13176 int min_val, max_val;
13178 min_val = mips_int_operand_min (operand);
13179 max_val = mips_int_operand_max (operand);
13180 if (reloc != BFD_RELOC_UNUSED)
13183 sval = SEXT_16BIT (sval);
13188 return (sval >= min_val
13190 && (sval & ((1 << operand->shift) - 1)) == 0);
13193 /* Install immediate value VAL into MIPS16 instruction *INSN,
13194 extending it if necessary. The instruction in *INSN may
13195 already be extended.
13197 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13198 if none. In the former case, VAL is a 16-bit number with no
13199 defined signedness.
13201 TYPE is the type of the immediate field. USER_INSN_LENGTH
13202 is the length that the user requested, or 0 if none. */
13205 mips16_immed (char *file, unsigned int line, int type,
13206 bfd_reloc_code_real_type reloc, offsetT val,
13207 unsigned int user_insn_length, unsigned long *insn)
13209 const struct mips_int_operand *operand;
13210 unsigned int uval, length;
13212 operand = mips16_immed_operand (type, FALSE);
13213 if (!mips16_immed_in_range_p (operand, reloc, val))
13215 /* We need an extended instruction. */
13216 if (user_insn_length == 2)
13217 as_bad_where (file, line, _("invalid unextended operand value"));
13219 *insn |= MIPS16_EXTEND;
13221 else if (user_insn_length == 4)
13223 /* The operand doesn't force an unextended instruction to be extended.
13224 Warn if the user wanted an extended instruction anyway. */
13225 *insn |= MIPS16_EXTEND;
13226 as_warn_where (file, line,
13227 _("extended operand requested but not required"));
13230 length = mips16_opcode_length (*insn);
13233 operand = mips16_immed_operand (type, TRUE);
13234 if (!mips16_immed_in_range_p (operand, reloc, val))
13235 as_bad_where (file, line,
13236 _("operand value out of range for instruction"));
13238 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13240 *insn = mips_insert_operand (&operand->root, *insn, uval);
13242 *insn |= mips16_immed_extend (uval, operand->root.size);
13245 struct percent_op_match
13248 bfd_reloc_code_real_type reloc;
13251 static const struct percent_op_match mips_percent_op[] =
13253 {"%lo", BFD_RELOC_LO16},
13254 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13255 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13256 {"%call16", BFD_RELOC_MIPS_CALL16},
13257 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13258 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13259 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13260 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13261 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13262 {"%got", BFD_RELOC_MIPS_GOT16},
13263 {"%gp_rel", BFD_RELOC_GPREL16},
13264 {"%half", BFD_RELOC_16},
13265 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13266 {"%higher", BFD_RELOC_MIPS_HIGHER},
13267 {"%neg", BFD_RELOC_MIPS_SUB},
13268 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13269 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13270 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13271 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13272 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13273 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13274 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13275 {"%hi", BFD_RELOC_HI16_S}
13278 static const struct percent_op_match mips16_percent_op[] =
13280 {"%lo", BFD_RELOC_MIPS16_LO16},
13281 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13282 {"%got", BFD_RELOC_MIPS16_GOT16},
13283 {"%call16", BFD_RELOC_MIPS16_CALL16},
13284 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13285 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13286 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13287 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13288 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13289 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13290 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13291 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13295 /* Return true if *STR points to a relocation operator. When returning true,
13296 move *STR over the operator and store its relocation code in *RELOC.
13297 Leave both *STR and *RELOC alone when returning false. */
13300 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13302 const struct percent_op_match *percent_op;
13305 if (mips_opts.mips16)
13307 percent_op = mips16_percent_op;
13308 limit = ARRAY_SIZE (mips16_percent_op);
13312 percent_op = mips_percent_op;
13313 limit = ARRAY_SIZE (mips_percent_op);
13316 for (i = 0; i < limit; i++)
13317 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13319 int len = strlen (percent_op[i].str);
13321 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13324 *str += strlen (percent_op[i].str);
13325 *reloc = percent_op[i].reloc;
13327 /* Check whether the output BFD supports this relocation.
13328 If not, issue an error and fall back on something safe. */
13329 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13331 as_bad (_("relocation %s isn't supported by the current ABI"),
13332 percent_op[i].str);
13333 *reloc = BFD_RELOC_UNUSED;
13341 /* Parse string STR as a 16-bit relocatable operand. Store the
13342 expression in *EP and the relocations in the array starting
13343 at RELOC. Return the number of relocation operators used.
13345 On exit, EXPR_END points to the first character after the expression. */
13348 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13351 bfd_reloc_code_real_type reversed_reloc[3];
13352 size_t reloc_index, i;
13353 int crux_depth, str_depth;
13356 /* Search for the start of the main expression, recoding relocations
13357 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13358 of the main expression and with CRUX_DEPTH containing the number
13359 of open brackets at that point. */
13366 crux_depth = str_depth;
13368 /* Skip over whitespace and brackets, keeping count of the number
13370 while (*str == ' ' || *str == '\t' || *str == '(')
13375 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13376 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13378 my_getExpression (ep, crux);
13381 /* Match every open bracket. */
13382 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13386 if (crux_depth > 0)
13387 as_bad (_("unclosed '('"));
13391 if (reloc_index != 0)
13393 prev_reloc_op_frag = frag_now;
13394 for (i = 0; i < reloc_index; i++)
13395 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13398 return reloc_index;
13402 my_getExpression (expressionS *ep, char *str)
13406 save_in = input_line_pointer;
13407 input_line_pointer = str;
13409 expr_end = input_line_pointer;
13410 input_line_pointer = save_in;
13414 md_atof (int type, char *litP, int *sizeP)
13416 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13420 md_number_to_chars (char *buf, valueT val, int n)
13422 if (target_big_endian)
13423 number_to_chars_bigendian (buf, val, n);
13425 number_to_chars_littleendian (buf, val, n);
13428 static int support_64bit_objects(void)
13430 const char **list, **l;
13433 list = bfd_target_list ();
13434 for (l = list; *l != NULL; l++)
13435 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13436 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13438 yes = (*l != NULL);
13443 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13444 NEW_VALUE. Warn if another value was already specified. Note:
13445 we have to defer parsing the -march and -mtune arguments in order
13446 to handle 'from-abi' correctly, since the ABI might be specified
13447 in a later argument. */
13450 mips_set_option_string (const char **string_ptr, const char *new_value)
13452 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13453 as_warn (_("A different %s was already specified, is now %s"),
13454 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13457 *string_ptr = new_value;
13461 md_parse_option (int c, char *arg)
13465 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13466 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13468 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13469 c == mips_ases[i].option_on);
13475 case OPTION_CONSTRUCT_FLOATS:
13476 mips_disable_float_construction = 0;
13479 case OPTION_NO_CONSTRUCT_FLOATS:
13480 mips_disable_float_construction = 1;
13492 target_big_endian = 1;
13496 target_big_endian = 0;
13502 else if (arg[0] == '0')
13504 else if (arg[0] == '1')
13514 mips_debug = atoi (arg);
13518 file_mips_isa = ISA_MIPS1;
13522 file_mips_isa = ISA_MIPS2;
13526 file_mips_isa = ISA_MIPS3;
13530 file_mips_isa = ISA_MIPS4;
13534 file_mips_isa = ISA_MIPS5;
13537 case OPTION_MIPS32:
13538 file_mips_isa = ISA_MIPS32;
13541 case OPTION_MIPS32R2:
13542 file_mips_isa = ISA_MIPS32R2;
13545 case OPTION_MIPS64R2:
13546 file_mips_isa = ISA_MIPS64R2;
13549 case OPTION_MIPS64:
13550 file_mips_isa = ISA_MIPS64;
13554 mips_set_option_string (&mips_tune_string, arg);
13558 mips_set_option_string (&mips_arch_string, arg);
13562 mips_set_option_string (&mips_arch_string, "4650");
13563 mips_set_option_string (&mips_tune_string, "4650");
13566 case OPTION_NO_M4650:
13570 mips_set_option_string (&mips_arch_string, "4010");
13571 mips_set_option_string (&mips_tune_string, "4010");
13574 case OPTION_NO_M4010:
13578 mips_set_option_string (&mips_arch_string, "4100");
13579 mips_set_option_string (&mips_tune_string, "4100");
13582 case OPTION_NO_M4100:
13586 mips_set_option_string (&mips_arch_string, "3900");
13587 mips_set_option_string (&mips_tune_string, "3900");
13590 case OPTION_NO_M3900:
13593 case OPTION_MICROMIPS:
13594 if (mips_opts.mips16 == 1)
13596 as_bad (_("-mmicromips cannot be used with -mips16"));
13599 mips_opts.micromips = 1;
13600 mips_no_prev_insn ();
13603 case OPTION_NO_MICROMIPS:
13604 mips_opts.micromips = 0;
13605 mips_no_prev_insn ();
13608 case OPTION_MIPS16:
13609 if (mips_opts.micromips == 1)
13611 as_bad (_("-mips16 cannot be used with -micromips"));
13614 mips_opts.mips16 = 1;
13615 mips_no_prev_insn ();
13618 case OPTION_NO_MIPS16:
13619 mips_opts.mips16 = 0;
13620 mips_no_prev_insn ();
13623 case OPTION_FIX_24K:
13627 case OPTION_NO_FIX_24K:
13631 case OPTION_FIX_LOONGSON2F_JUMP:
13632 mips_fix_loongson2f_jump = TRUE;
13635 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13636 mips_fix_loongson2f_jump = FALSE;
13639 case OPTION_FIX_LOONGSON2F_NOP:
13640 mips_fix_loongson2f_nop = TRUE;
13643 case OPTION_NO_FIX_LOONGSON2F_NOP:
13644 mips_fix_loongson2f_nop = FALSE;
13647 case OPTION_FIX_VR4120:
13648 mips_fix_vr4120 = 1;
13651 case OPTION_NO_FIX_VR4120:
13652 mips_fix_vr4120 = 0;
13655 case OPTION_FIX_VR4130:
13656 mips_fix_vr4130 = 1;
13659 case OPTION_NO_FIX_VR4130:
13660 mips_fix_vr4130 = 0;
13663 case OPTION_FIX_CN63XXP1:
13664 mips_fix_cn63xxp1 = TRUE;
13667 case OPTION_NO_FIX_CN63XXP1:
13668 mips_fix_cn63xxp1 = FALSE;
13671 case OPTION_RELAX_BRANCH:
13672 mips_relax_branch = 1;
13675 case OPTION_NO_RELAX_BRANCH:
13676 mips_relax_branch = 0;
13679 case OPTION_INSN32:
13680 mips_opts.insn32 = TRUE;
13683 case OPTION_NO_INSN32:
13684 mips_opts.insn32 = FALSE;
13687 case OPTION_MSHARED:
13688 mips_in_shared = TRUE;
13691 case OPTION_MNO_SHARED:
13692 mips_in_shared = FALSE;
13695 case OPTION_MSYM32:
13696 mips_opts.sym32 = TRUE;
13699 case OPTION_MNO_SYM32:
13700 mips_opts.sym32 = FALSE;
13703 /* When generating ELF code, we permit -KPIC and -call_shared to
13704 select SVR4_PIC, and -non_shared to select no PIC. This is
13705 intended to be compatible with Irix 5. */
13706 case OPTION_CALL_SHARED:
13707 mips_pic = SVR4_PIC;
13708 mips_abicalls = TRUE;
13711 case OPTION_CALL_NONPIC:
13713 mips_abicalls = TRUE;
13716 case OPTION_NON_SHARED:
13718 mips_abicalls = FALSE;
13721 /* The -xgot option tells the assembler to use 32 bit offsets
13722 when accessing the got in SVR4_PIC mode. It is for Irix
13729 g_switch_value = atoi (arg);
13733 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13736 mips_abi = O32_ABI;
13740 mips_abi = N32_ABI;
13744 mips_abi = N64_ABI;
13745 if (!support_64bit_objects())
13746 as_fatal (_("No compiled in support for 64 bit object file format"));
13750 file_mips_gp32 = 1;
13754 file_mips_gp32 = 0;
13758 file_mips_fp32 = 1;
13762 file_mips_fp32 = 0;
13765 case OPTION_SINGLE_FLOAT:
13766 file_mips_single_float = 1;
13769 case OPTION_DOUBLE_FLOAT:
13770 file_mips_single_float = 0;
13773 case OPTION_SOFT_FLOAT:
13774 file_mips_soft_float = 1;
13777 case OPTION_HARD_FLOAT:
13778 file_mips_soft_float = 0;
13782 if (strcmp (arg, "32") == 0)
13783 mips_abi = O32_ABI;
13784 else if (strcmp (arg, "o64") == 0)
13785 mips_abi = O64_ABI;
13786 else if (strcmp (arg, "n32") == 0)
13787 mips_abi = N32_ABI;
13788 else if (strcmp (arg, "64") == 0)
13790 mips_abi = N64_ABI;
13791 if (! support_64bit_objects())
13792 as_fatal (_("No compiled in support for 64 bit object file "
13795 else if (strcmp (arg, "eabi") == 0)
13796 mips_abi = EABI_ABI;
13799 as_fatal (_("invalid abi -mabi=%s"), arg);
13804 case OPTION_M7000_HILO_FIX:
13805 mips_7000_hilo_fix = TRUE;
13808 case OPTION_MNO_7000_HILO_FIX:
13809 mips_7000_hilo_fix = FALSE;
13812 case OPTION_MDEBUG:
13813 mips_flag_mdebug = TRUE;
13816 case OPTION_NO_MDEBUG:
13817 mips_flag_mdebug = FALSE;
13821 mips_flag_pdr = TRUE;
13824 case OPTION_NO_PDR:
13825 mips_flag_pdr = FALSE;
13828 case OPTION_MVXWORKS_PIC:
13829 mips_pic = VXWORKS_PIC;
13833 if (strcmp (arg, "2008") == 0)
13834 mips_flag_nan2008 = TRUE;
13835 else if (strcmp (arg, "legacy") == 0)
13836 mips_flag_nan2008 = FALSE;
13839 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13848 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13853 /* Set up globals to generate code for the ISA or processor
13854 described by INFO. */
13857 mips_set_architecture (const struct mips_cpu_info *info)
13861 file_mips_arch = info->cpu;
13862 mips_opts.arch = info->cpu;
13863 mips_opts.isa = info->isa;
13868 /* Likewise for tuning. */
13871 mips_set_tune (const struct mips_cpu_info *info)
13874 mips_tune = info->cpu;
13879 mips_after_parse_args (void)
13881 const struct mips_cpu_info *arch_info = 0;
13882 const struct mips_cpu_info *tune_info = 0;
13884 /* GP relative stuff not working for PE */
13885 if (strncmp (TARGET_OS, "pe", 2) == 0)
13887 if (g_switch_seen && g_switch_value != 0)
13888 as_bad (_("-G not supported in this configuration."));
13889 g_switch_value = 0;
13892 if (mips_abi == NO_ABI)
13893 mips_abi = MIPS_DEFAULT_ABI;
13895 /* The following code determines the architecture and register size.
13896 Similar code was added to GCC 3.3 (see override_options() in
13897 config/mips/mips.c). The GAS and GCC code should be kept in sync
13898 as much as possible. */
13900 if (mips_arch_string != 0)
13901 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13903 if (file_mips_isa != ISA_UNKNOWN)
13905 /* Handle -mipsN. At this point, file_mips_isa contains the
13906 ISA level specified by -mipsN, while arch_info->isa contains
13907 the -march selection (if any). */
13908 if (arch_info != 0)
13910 /* -march takes precedence over -mipsN, since it is more descriptive.
13911 There's no harm in specifying both as long as the ISA levels
13913 if (file_mips_isa != arch_info->isa)
13914 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13915 mips_cpu_info_from_isa (file_mips_isa)->name,
13916 mips_cpu_info_from_isa (arch_info->isa)->name);
13919 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13922 if (arch_info == 0)
13924 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13925 gas_assert (arch_info);
13928 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13929 as_bad (_("-march=%s is not compatible with the selected ABI"),
13932 mips_set_architecture (arch_info);
13934 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13935 if (mips_tune_string != 0)
13936 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13938 if (tune_info == 0)
13939 mips_set_tune (arch_info);
13941 mips_set_tune (tune_info);
13943 if (file_mips_gp32 >= 0)
13945 /* The user specified the size of the integer registers. Make sure
13946 it agrees with the ABI and ISA. */
13947 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13948 as_bad (_("-mgp64 used with a 32-bit processor"));
13949 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13950 as_bad (_("-mgp32 used with a 64-bit ABI"));
13951 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13952 as_bad (_("-mgp64 used with a 32-bit ABI"));
13956 /* Infer the integer register size from the ABI and processor.
13957 Restrict ourselves to 32-bit registers if that's all the
13958 processor has, or if the ABI cannot handle 64-bit registers. */
13959 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13960 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13963 switch (file_mips_fp32)
13967 /* No user specified float register size.
13968 ??? GAS treats single-float processors as though they had 64-bit
13969 float registers (although it complains when double-precision
13970 instructions are used). As things stand, saying they have 32-bit
13971 registers would lead to spurious "register must be even" messages.
13972 So here we assume float registers are never smaller than the
13974 if (file_mips_gp32 == 0)
13975 /* 64-bit integer registers implies 64-bit float registers. */
13976 file_mips_fp32 = 0;
13977 else if ((mips_opts.ase & FP64_ASES)
13978 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13979 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13980 file_mips_fp32 = 0;
13982 /* 32-bit float registers. */
13983 file_mips_fp32 = 1;
13986 /* The user specified the size of the float registers. Check if it
13987 agrees with the ABI and ISA. */
13989 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13990 as_bad (_("-mfp64 used with a 32-bit fpu"));
13991 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13992 && !ISA_HAS_MXHC1 (mips_opts.isa))
13993 as_warn (_("-mfp64 used with a 32-bit ABI"));
13996 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13997 as_warn (_("-mfp32 used with a 64-bit ABI"));
14001 /* End of GCC-shared inference code. */
14003 /* This flag is set when we have a 64-bit capable CPU but use only
14004 32-bit wide registers. Note that EABI does not use it. */
14005 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14006 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14007 || mips_abi == O32_ABI))
14008 mips_32bitmode = 1;
14010 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14011 as_bad (_("trap exception not supported at ISA 1"));
14013 /* If the selected architecture includes support for ASEs, enable
14014 generation of code for them. */
14015 if (mips_opts.mips16 == -1)
14016 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
14017 if (mips_opts.micromips == -1)
14018 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
14020 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14021 ASEs from being selected implicitly. */
14022 if (file_mips_fp32 == 1)
14023 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
14025 /* If the user didn't explicitly select or deselect a particular ASE,
14026 use the default setting for the CPU. */
14027 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
14029 file_mips_isa = mips_opts.isa;
14030 file_ase = mips_opts.ase;
14031 mips_opts.gp32 = file_mips_gp32;
14032 mips_opts.fp32 = file_mips_fp32;
14033 mips_opts.soft_float = file_mips_soft_float;
14034 mips_opts.single_float = file_mips_single_float;
14036 mips_check_isa_supports_ases ();
14038 if (mips_flag_mdebug < 0)
14039 mips_flag_mdebug = 0;
14043 mips_init_after_args (void)
14045 /* initialize opcodes */
14046 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14047 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14051 md_pcrel_from (fixS *fixP)
14053 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14054 switch (fixP->fx_r_type)
14056 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14057 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14058 /* Return the address of the delay slot. */
14061 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14062 case BFD_RELOC_MICROMIPS_JMP:
14063 case BFD_RELOC_16_PCREL_S2:
14064 case BFD_RELOC_MIPS_JMP:
14065 /* Return the address of the delay slot. */
14068 case BFD_RELOC_32_PCREL:
14072 /* We have no relocation type for PC relative MIPS16 instructions. */
14073 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14074 as_bad_where (fixP->fx_file, fixP->fx_line,
14075 _("PC relative MIPS16 instruction references a different section"));
14080 /* This is called before the symbol table is processed. In order to
14081 work with gcc when using mips-tfile, we must keep all local labels.
14082 However, in other cases, we want to discard them. If we were
14083 called with -g, but we didn't see any debugging information, it may
14084 mean that gcc is smuggling debugging information through to
14085 mips-tfile, in which case we must generate all local labels. */
14088 mips_frob_file_before_adjust (void)
14090 #ifndef NO_ECOFF_DEBUGGING
14091 if (ECOFF_DEBUGGING
14093 && ! ecoff_debugging_seen)
14094 flag_keep_locals = 1;
14098 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14099 the corresponding LO16 reloc. This is called before md_apply_fix and
14100 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14101 relocation operators.
14103 For our purposes, a %lo() expression matches a %got() or %hi()
14106 (a) it refers to the same symbol; and
14107 (b) the offset applied in the %lo() expression is no lower than
14108 the offset applied in the %got() or %hi().
14110 (b) allows us to cope with code like:
14113 lh $4,%lo(foo+2)($4)
14115 ...which is legal on RELA targets, and has a well-defined behaviour
14116 if the user knows that adding 2 to "foo" will not induce a carry to
14119 When several %lo()s match a particular %got() or %hi(), we use the
14120 following rules to distinguish them:
14122 (1) %lo()s with smaller offsets are a better match than %lo()s with
14125 (2) %lo()s with no matching %got() or %hi() are better than those
14126 that already have a matching %got() or %hi().
14128 (3) later %lo()s are better than earlier %lo()s.
14130 These rules are applied in order.
14132 (1) means, among other things, that %lo()s with identical offsets are
14133 chosen if they exist.
14135 (2) means that we won't associate several high-part relocations with
14136 the same low-part relocation unless there's no alternative. Having
14137 several high parts for the same low part is a GNU extension; this rule
14138 allows careful users to avoid it.
14140 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14141 with the last high-part relocation being at the front of the list.
14142 It therefore makes sense to choose the last matching low-part
14143 relocation, all other things being equal. It's also easier
14144 to code that way. */
14147 mips_frob_file (void)
14149 struct mips_hi_fixup *l;
14150 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14152 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14154 segment_info_type *seginfo;
14155 bfd_boolean matched_lo_p;
14156 fixS **hi_pos, **lo_pos, **pos;
14158 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14160 /* If a GOT16 relocation turns out to be against a global symbol,
14161 there isn't supposed to be a matching LO. Ignore %gots against
14162 constants; we'll report an error for those later. */
14163 if (got16_reloc_p (l->fixp->fx_r_type)
14164 && !(l->fixp->fx_addsy
14165 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14168 /* Check quickly whether the next fixup happens to be a matching %lo. */
14169 if (fixup_has_matching_lo_p (l->fixp))
14172 seginfo = seg_info (l->seg);
14174 /* Set HI_POS to the position of this relocation in the chain.
14175 Set LO_POS to the position of the chosen low-part relocation.
14176 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14177 relocation that matches an immediately-preceding high-part
14181 matched_lo_p = FALSE;
14182 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14184 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14186 if (*pos == l->fixp)
14189 if ((*pos)->fx_r_type == looking_for_rtype
14190 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14191 && (*pos)->fx_offset >= l->fixp->fx_offset
14193 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14195 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14198 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14199 && fixup_has_matching_lo_p (*pos));
14202 /* If we found a match, remove the high-part relocation from its
14203 current position and insert it before the low-part relocation.
14204 Make the offsets match so that fixup_has_matching_lo_p()
14207 We don't warn about unmatched high-part relocations since some
14208 versions of gcc have been known to emit dead "lui ...%hi(...)"
14210 if (lo_pos != NULL)
14212 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14213 if (l->fixp->fx_next != *lo_pos)
14215 *hi_pos = l->fixp->fx_next;
14216 l->fixp->fx_next = *lo_pos;
14224 mips_force_relocation (fixS *fixp)
14226 if (generic_force_reloc (fixp))
14229 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14230 so that the linker relaxation can update targets. */
14231 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14232 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14233 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14239 /* Read the instruction associated with RELOC from BUF. */
14241 static unsigned int
14242 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14244 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14245 return read_compressed_insn (buf, 4);
14247 return read_insn (buf);
14250 /* Write instruction INSN to BUF, given that it has been relocated
14254 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14255 unsigned long insn)
14257 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14258 write_compressed_insn (buf, insn, 4);
14260 write_insn (buf, insn);
14263 /* Apply a fixup to the object file. */
14266 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14269 unsigned long insn;
14270 reloc_howto_type *howto;
14272 /* We ignore generic BFD relocations we don't know about. */
14273 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14277 gas_assert (fixP->fx_size == 2
14278 || fixP->fx_size == 4
14279 || fixP->fx_r_type == BFD_RELOC_16
14280 || fixP->fx_r_type == BFD_RELOC_64
14281 || fixP->fx_r_type == BFD_RELOC_CTOR
14282 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14283 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14284 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14285 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14286 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
14288 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14290 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14291 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14292 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14293 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14294 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
14296 /* Don't treat parts of a composite relocation as done. There are two
14299 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14300 should nevertheless be emitted if the first part is.
14302 (2) In normal usage, composite relocations are never assembly-time
14303 constants. The easiest way of dealing with the pathological
14304 exceptions is to generate a relocation against STN_UNDEF and
14305 leave everything up to the linker. */
14306 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14309 switch (fixP->fx_r_type)
14311 case BFD_RELOC_MIPS_TLS_GD:
14312 case BFD_RELOC_MIPS_TLS_LDM:
14313 case BFD_RELOC_MIPS_TLS_DTPREL32:
14314 case BFD_RELOC_MIPS_TLS_DTPREL64:
14315 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14316 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14317 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14318 case BFD_RELOC_MIPS_TLS_TPREL32:
14319 case BFD_RELOC_MIPS_TLS_TPREL64:
14320 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14321 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14322 case BFD_RELOC_MICROMIPS_TLS_GD:
14323 case BFD_RELOC_MICROMIPS_TLS_LDM:
14324 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14325 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14326 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14327 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14328 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14329 case BFD_RELOC_MIPS16_TLS_GD:
14330 case BFD_RELOC_MIPS16_TLS_LDM:
14331 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14332 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14333 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14334 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14335 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14336 if (!fixP->fx_addsy)
14338 as_bad_where (fixP->fx_file, fixP->fx_line,
14339 _("TLS relocation against a constant"));
14342 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14345 case BFD_RELOC_MIPS_JMP:
14346 case BFD_RELOC_MIPS_SHIFT5:
14347 case BFD_RELOC_MIPS_SHIFT6:
14348 case BFD_RELOC_MIPS_GOT_DISP:
14349 case BFD_RELOC_MIPS_GOT_PAGE:
14350 case BFD_RELOC_MIPS_GOT_OFST:
14351 case BFD_RELOC_MIPS_SUB:
14352 case BFD_RELOC_MIPS_INSERT_A:
14353 case BFD_RELOC_MIPS_INSERT_B:
14354 case BFD_RELOC_MIPS_DELETE:
14355 case BFD_RELOC_MIPS_HIGHEST:
14356 case BFD_RELOC_MIPS_HIGHER:
14357 case BFD_RELOC_MIPS_SCN_DISP:
14358 case BFD_RELOC_MIPS_REL16:
14359 case BFD_RELOC_MIPS_RELGOT:
14360 case BFD_RELOC_MIPS_JALR:
14361 case BFD_RELOC_HI16:
14362 case BFD_RELOC_HI16_S:
14363 case BFD_RELOC_LO16:
14364 case BFD_RELOC_GPREL16:
14365 case BFD_RELOC_MIPS_LITERAL:
14366 case BFD_RELOC_MIPS_CALL16:
14367 case BFD_RELOC_MIPS_GOT16:
14368 case BFD_RELOC_GPREL32:
14369 case BFD_RELOC_MIPS_GOT_HI16:
14370 case BFD_RELOC_MIPS_GOT_LO16:
14371 case BFD_RELOC_MIPS_CALL_HI16:
14372 case BFD_RELOC_MIPS_CALL_LO16:
14373 case BFD_RELOC_MIPS16_GPREL:
14374 case BFD_RELOC_MIPS16_GOT16:
14375 case BFD_RELOC_MIPS16_CALL16:
14376 case BFD_RELOC_MIPS16_HI16:
14377 case BFD_RELOC_MIPS16_HI16_S:
14378 case BFD_RELOC_MIPS16_LO16:
14379 case BFD_RELOC_MIPS16_JMP:
14380 case BFD_RELOC_MICROMIPS_JMP:
14381 case BFD_RELOC_MICROMIPS_GOT_DISP:
14382 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14383 case BFD_RELOC_MICROMIPS_GOT_OFST:
14384 case BFD_RELOC_MICROMIPS_SUB:
14385 case BFD_RELOC_MICROMIPS_HIGHEST:
14386 case BFD_RELOC_MICROMIPS_HIGHER:
14387 case BFD_RELOC_MICROMIPS_SCN_DISP:
14388 case BFD_RELOC_MICROMIPS_JALR:
14389 case BFD_RELOC_MICROMIPS_HI16:
14390 case BFD_RELOC_MICROMIPS_HI16_S:
14391 case BFD_RELOC_MICROMIPS_LO16:
14392 case BFD_RELOC_MICROMIPS_GPREL16:
14393 case BFD_RELOC_MICROMIPS_LITERAL:
14394 case BFD_RELOC_MICROMIPS_CALL16:
14395 case BFD_RELOC_MICROMIPS_GOT16:
14396 case BFD_RELOC_MICROMIPS_GOT_HI16:
14397 case BFD_RELOC_MICROMIPS_GOT_LO16:
14398 case BFD_RELOC_MICROMIPS_CALL_HI16:
14399 case BFD_RELOC_MICROMIPS_CALL_LO16:
14400 case BFD_RELOC_MIPS_EH:
14405 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14407 insn = read_reloc_insn (buf, fixP->fx_r_type);
14408 if (mips16_reloc_p (fixP->fx_r_type))
14409 insn |= mips16_immed_extend (value, 16);
14411 insn |= (value & 0xffff);
14412 write_reloc_insn (buf, fixP->fx_r_type, insn);
14415 as_bad_where (fixP->fx_file, fixP->fx_line,
14416 _("Unsupported constant in relocation"));
14421 /* This is handled like BFD_RELOC_32, but we output a sign
14422 extended value if we are only 32 bits. */
14425 if (8 <= sizeof (valueT))
14426 md_number_to_chars (buf, *valP, 8);
14431 if ((*valP & 0x80000000) != 0)
14435 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14436 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14441 case BFD_RELOC_RVA:
14443 case BFD_RELOC_32_PCREL:
14445 /* If we are deleting this reloc entry, we must fill in the
14446 value now. This can happen if we have a .word which is not
14447 resolved when it appears but is later defined. */
14449 md_number_to_chars (buf, *valP, fixP->fx_size);
14452 case BFD_RELOC_16_PCREL_S2:
14453 if ((*valP & 0x3) != 0)
14454 as_bad_where (fixP->fx_file, fixP->fx_line,
14455 _("Branch to misaligned address (%lx)"), (long) *valP);
14457 /* We need to save the bits in the instruction since fixup_segment()
14458 might be deleting the relocation entry (i.e., a branch within
14459 the current segment). */
14460 if (! fixP->fx_done)
14463 /* Update old instruction data. */
14464 insn = read_insn (buf);
14466 if (*valP + 0x20000 <= 0x3ffff)
14468 insn |= (*valP >> 2) & 0xffff;
14469 write_insn (buf, insn);
14471 else if (mips_pic == NO_PIC
14473 && fixP->fx_frag->fr_address >= text_section->vma
14474 && (fixP->fx_frag->fr_address
14475 < text_section->vma + bfd_get_section_size (text_section))
14476 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14477 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14478 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14480 /* The branch offset is too large. If this is an
14481 unconditional branch, and we are not generating PIC code,
14482 we can convert it to an absolute jump instruction. */
14483 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14484 insn = 0x0c000000; /* jal */
14486 insn = 0x08000000; /* j */
14487 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14489 fixP->fx_addsy = section_symbol (text_section);
14490 *valP += md_pcrel_from (fixP);
14491 write_insn (buf, insn);
14495 /* If we got here, we have branch-relaxation disabled,
14496 and there's nothing we can do to fix this instruction
14497 without turning it into a longer sequence. */
14498 as_bad_where (fixP->fx_file, fixP->fx_line,
14499 _("Branch out of range"));
14503 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14504 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14505 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14506 /* We adjust the offset back to even. */
14507 if ((*valP & 0x1) != 0)
14510 if (! fixP->fx_done)
14513 /* Should never visit here, because we keep the relocation. */
14517 case BFD_RELOC_VTABLE_INHERIT:
14520 && !S_IS_DEFINED (fixP->fx_addsy)
14521 && !S_IS_WEAK (fixP->fx_addsy))
14522 S_SET_WEAK (fixP->fx_addsy);
14525 case BFD_RELOC_VTABLE_ENTRY:
14533 /* Remember value for tc_gen_reloc. */
14534 fixP->fx_addnumber = *valP;
14544 name = input_line_pointer;
14545 c = get_symbol_end ();
14546 p = (symbolS *) symbol_find_or_make (name);
14547 *input_line_pointer = c;
14551 /* Align the current frag to a given power of two. If a particular
14552 fill byte should be used, FILL points to an integer that contains
14553 that byte, otherwise FILL is null.
14555 This function used to have the comment:
14557 The MIPS assembler also automatically adjusts any preceding label.
14559 The implementation therefore applied the adjustment to a maximum of
14560 one label. However, other label adjustments are applied to batches
14561 of labels, and adjusting just one caused problems when new labels
14562 were added for the sake of debugging or unwind information.
14563 We therefore adjust all preceding labels (given as LABELS) instead. */
14566 mips_align (int to, int *fill, struct insn_label_list *labels)
14568 mips_emit_delays ();
14569 mips_record_compressed_mode ();
14570 if (fill == NULL && subseg_text_p (now_seg))
14571 frag_align_code (to, 0);
14573 frag_align (to, fill ? *fill : 0, 0);
14574 record_alignment (now_seg, to);
14575 mips_move_labels (labels, FALSE);
14578 /* Align to a given power of two. .align 0 turns off the automatic
14579 alignment used by the data creating pseudo-ops. */
14582 s_align (int x ATTRIBUTE_UNUSED)
14584 int temp, fill_value, *fill_ptr;
14585 long max_alignment = 28;
14587 /* o Note that the assembler pulls down any immediately preceding label
14588 to the aligned address.
14589 o It's not documented but auto alignment is reinstated by
14590 a .align pseudo instruction.
14591 o Note also that after auto alignment is turned off the mips assembler
14592 issues an error on attempt to assemble an improperly aligned data item.
14595 temp = get_absolute_expression ();
14596 if (temp > max_alignment)
14597 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14600 as_warn (_("Alignment negative: 0 assumed."));
14603 if (*input_line_pointer == ',')
14605 ++input_line_pointer;
14606 fill_value = get_absolute_expression ();
14607 fill_ptr = &fill_value;
14613 segment_info_type *si = seg_info (now_seg);
14614 struct insn_label_list *l = si->label_list;
14615 /* Auto alignment should be switched on by next section change. */
14617 mips_align (temp, fill_ptr, l);
14624 demand_empty_rest_of_line ();
14628 s_change_sec (int sec)
14632 /* The ELF backend needs to know that we are changing sections, so
14633 that .previous works correctly. We could do something like check
14634 for an obj_section_change_hook macro, but that might be confusing
14635 as it would not be appropriate to use it in the section changing
14636 functions in read.c, since obj-elf.c intercepts those. FIXME:
14637 This should be cleaner, somehow. */
14638 obj_elf_section_change_hook ();
14640 mips_emit_delays ();
14651 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14652 demand_empty_rest_of_line ();
14656 seg = subseg_new (RDATA_SECTION_NAME,
14657 (subsegT) get_absolute_expression ());
14658 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14659 | SEC_READONLY | SEC_RELOC
14661 if (strncmp (TARGET_OS, "elf", 3) != 0)
14662 record_alignment (seg, 4);
14663 demand_empty_rest_of_line ();
14667 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14668 bfd_set_section_flags (stdoutput, seg,
14669 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14670 if (strncmp (TARGET_OS, "elf", 3) != 0)
14671 record_alignment (seg, 4);
14672 demand_empty_rest_of_line ();
14676 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14677 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14678 if (strncmp (TARGET_OS, "elf", 3) != 0)
14679 record_alignment (seg, 4);
14680 demand_empty_rest_of_line ();
14688 s_change_section (int ignore ATTRIBUTE_UNUSED)
14690 char *section_name;
14695 int section_entry_size;
14696 int section_alignment;
14698 section_name = input_line_pointer;
14699 c = get_symbol_end ();
14701 next_c = *(input_line_pointer + 1);
14703 /* Do we have .section Name<,"flags">? */
14704 if (c != ',' || (c == ',' && next_c == '"'))
14706 /* just after name is now '\0'. */
14707 *input_line_pointer = c;
14708 input_line_pointer = section_name;
14709 obj_elf_section (ignore);
14712 input_line_pointer++;
14714 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14716 section_type = get_absolute_expression ();
14719 if (*input_line_pointer++ == ',')
14720 section_flag = get_absolute_expression ();
14723 if (*input_line_pointer++ == ',')
14724 section_entry_size = get_absolute_expression ();
14726 section_entry_size = 0;
14727 if (*input_line_pointer++ == ',')
14728 section_alignment = get_absolute_expression ();
14730 section_alignment = 0;
14731 /* FIXME: really ignore? */
14732 (void) section_alignment;
14734 section_name = xstrdup (section_name);
14736 /* When using the generic form of .section (as implemented by obj-elf.c),
14737 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14738 traditionally had to fall back on the more common @progbits instead.
14740 There's nothing really harmful in this, since bfd will correct
14741 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14742 means that, for backwards compatibility, the special_section entries
14743 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14745 Even so, we shouldn't force users of the MIPS .section syntax to
14746 incorrectly label the sections as SHT_PROGBITS. The best compromise
14747 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14748 generic type-checking code. */
14749 if (section_type == SHT_MIPS_DWARF)
14750 section_type = SHT_PROGBITS;
14752 obj_elf_change_section (section_name, section_type, section_flag,
14753 section_entry_size, 0, 0, 0);
14755 if (now_seg->name != section_name)
14756 free (section_name);
14760 mips_enable_auto_align (void)
14766 s_cons (int log_size)
14768 segment_info_type *si = seg_info (now_seg);
14769 struct insn_label_list *l = si->label_list;
14771 mips_emit_delays ();
14772 if (log_size > 0 && auto_align)
14773 mips_align (log_size, 0, l);
14774 cons (1 << log_size);
14775 mips_clear_insn_labels ();
14779 s_float_cons (int type)
14781 segment_info_type *si = seg_info (now_seg);
14782 struct insn_label_list *l = si->label_list;
14784 mips_emit_delays ();
14789 mips_align (3, 0, l);
14791 mips_align (2, 0, l);
14795 mips_clear_insn_labels ();
14798 /* Handle .globl. We need to override it because on Irix 5 you are
14801 where foo is an undefined symbol, to mean that foo should be
14802 considered to be the address of a function. */
14805 s_mips_globl (int x ATTRIBUTE_UNUSED)
14814 name = input_line_pointer;
14815 c = get_symbol_end ();
14816 symbolP = symbol_find_or_make (name);
14817 S_SET_EXTERNAL (symbolP);
14819 *input_line_pointer = c;
14820 SKIP_WHITESPACE ();
14822 /* On Irix 5, every global symbol that is not explicitly labelled as
14823 being a function is apparently labelled as being an object. */
14826 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14827 && (*input_line_pointer != ','))
14832 secname = input_line_pointer;
14833 c = get_symbol_end ();
14834 sec = bfd_get_section_by_name (stdoutput, secname);
14836 as_bad (_("%s: no such section"), secname);
14837 *input_line_pointer = c;
14839 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14840 flag = BSF_FUNCTION;
14843 symbol_get_bfdsym (symbolP)->flags |= flag;
14845 c = *input_line_pointer;
14848 input_line_pointer++;
14849 SKIP_WHITESPACE ();
14850 if (is_end_of_line[(unsigned char) *input_line_pointer])
14856 demand_empty_rest_of_line ();
14860 s_option (int x ATTRIBUTE_UNUSED)
14865 opt = input_line_pointer;
14866 c = get_symbol_end ();
14870 /* FIXME: What does this mean? */
14872 else if (strncmp (opt, "pic", 3) == 0)
14876 i = atoi (opt + 3);
14881 mips_pic = SVR4_PIC;
14882 mips_abicalls = TRUE;
14885 as_bad (_(".option pic%d not supported"), i);
14887 if (mips_pic == SVR4_PIC)
14889 if (g_switch_seen && g_switch_value != 0)
14890 as_warn (_("-G may not be used with SVR4 PIC code"));
14891 g_switch_value = 0;
14892 bfd_set_gp_size (stdoutput, 0);
14896 as_warn (_("Unrecognized option \"%s\""), opt);
14898 *input_line_pointer = c;
14899 demand_empty_rest_of_line ();
14902 /* This structure is used to hold a stack of .set values. */
14904 struct mips_option_stack
14906 struct mips_option_stack *next;
14907 struct mips_set_options options;
14910 static struct mips_option_stack *mips_opts_stack;
14912 /* Handle the .set pseudo-op. */
14915 s_mipsset (int x ATTRIBUTE_UNUSED)
14917 char *name = input_line_pointer, ch;
14918 const struct mips_ase *ase;
14920 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14921 ++input_line_pointer;
14922 ch = *input_line_pointer;
14923 *input_line_pointer = '\0';
14925 if (strcmp (name, "reorder") == 0)
14927 if (mips_opts.noreorder)
14930 else if (strcmp (name, "noreorder") == 0)
14932 if (!mips_opts.noreorder)
14933 start_noreorder ();
14935 else if (strncmp (name, "at=", 3) == 0)
14937 char *s = name + 3;
14939 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14940 as_bad (_("Unrecognized register name `%s'"), s);
14942 else if (strcmp (name, "at") == 0)
14944 mips_opts.at = ATREG;
14946 else if (strcmp (name, "noat") == 0)
14948 mips_opts.at = ZERO;
14950 else if (strcmp (name, "macro") == 0)
14952 mips_opts.warn_about_macros = 0;
14954 else if (strcmp (name, "nomacro") == 0)
14956 if (mips_opts.noreorder == 0)
14957 as_bad (_("`noreorder' must be set before `nomacro'"));
14958 mips_opts.warn_about_macros = 1;
14960 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14962 mips_opts.nomove = 0;
14964 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14966 mips_opts.nomove = 1;
14968 else if (strcmp (name, "bopt") == 0)
14970 mips_opts.nobopt = 0;
14972 else if (strcmp (name, "nobopt") == 0)
14974 mips_opts.nobopt = 1;
14976 else if (strcmp (name, "gp=default") == 0)
14977 mips_opts.gp32 = file_mips_gp32;
14978 else if (strcmp (name, "gp=32") == 0)
14979 mips_opts.gp32 = 1;
14980 else if (strcmp (name, "gp=64") == 0)
14982 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14983 as_warn (_("%s isa does not support 64-bit registers"),
14984 mips_cpu_info_from_isa (mips_opts.isa)->name);
14985 mips_opts.gp32 = 0;
14987 else if (strcmp (name, "fp=default") == 0)
14988 mips_opts.fp32 = file_mips_fp32;
14989 else if (strcmp (name, "fp=32") == 0)
14990 mips_opts.fp32 = 1;
14991 else if (strcmp (name, "fp=64") == 0)
14993 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14994 as_warn (_("%s isa does not support 64-bit floating point registers"),
14995 mips_cpu_info_from_isa (mips_opts.isa)->name);
14996 mips_opts.fp32 = 0;
14998 else if (strcmp (name, "softfloat") == 0)
14999 mips_opts.soft_float = 1;
15000 else if (strcmp (name, "hardfloat") == 0)
15001 mips_opts.soft_float = 0;
15002 else if (strcmp (name, "singlefloat") == 0)
15003 mips_opts.single_float = 1;
15004 else if (strcmp (name, "doublefloat") == 0)
15005 mips_opts.single_float = 0;
15006 else if (strcmp (name, "mips16") == 0
15007 || strcmp (name, "MIPS-16") == 0)
15009 if (mips_opts.micromips == 1)
15010 as_fatal (_("`mips16' cannot be used with `micromips'"));
15011 mips_opts.mips16 = 1;
15013 else if (strcmp (name, "nomips16") == 0
15014 || strcmp (name, "noMIPS-16") == 0)
15015 mips_opts.mips16 = 0;
15016 else if (strcmp (name, "micromips") == 0)
15018 if (mips_opts.mips16 == 1)
15019 as_fatal (_("`micromips' cannot be used with `mips16'"));
15020 mips_opts.micromips = 1;
15022 else if (strcmp (name, "nomicromips") == 0)
15023 mips_opts.micromips = 0;
15024 else if (name[0] == 'n'
15026 && (ase = mips_lookup_ase (name + 2)))
15027 mips_set_ase (ase, FALSE);
15028 else if ((ase = mips_lookup_ase (name)))
15029 mips_set_ase (ase, TRUE);
15030 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15034 /* Permit the user to change the ISA and architecture on the fly.
15035 Needless to say, misuse can cause serious problems. */
15036 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15039 mips_opts.isa = file_mips_isa;
15040 mips_opts.arch = file_mips_arch;
15042 else if (strncmp (name, "arch=", 5) == 0)
15044 const struct mips_cpu_info *p;
15046 p = mips_parse_cpu("internal use", name + 5);
15048 as_bad (_("unknown architecture %s"), name + 5);
15051 mips_opts.arch = p->cpu;
15052 mips_opts.isa = p->isa;
15055 else if (strncmp (name, "mips", 4) == 0)
15057 const struct mips_cpu_info *p;
15059 p = mips_parse_cpu("internal use", name);
15061 as_bad (_("unknown ISA level %s"), name + 4);
15064 mips_opts.arch = p->cpu;
15065 mips_opts.isa = p->isa;
15069 as_bad (_("unknown ISA or architecture %s"), name);
15071 switch (mips_opts.isa)
15079 mips_opts.gp32 = 1;
15080 mips_opts.fp32 = 1;
15087 mips_opts.gp32 = 0;
15088 if (mips_opts.arch == CPU_R5900)
15090 mips_opts.fp32 = 1;
15094 mips_opts.fp32 = 0;
15098 as_bad (_("unknown ISA level %s"), name + 4);
15103 mips_opts.gp32 = file_mips_gp32;
15104 mips_opts.fp32 = file_mips_fp32;
15107 else if (strcmp (name, "autoextend") == 0)
15108 mips_opts.noautoextend = 0;
15109 else if (strcmp (name, "noautoextend") == 0)
15110 mips_opts.noautoextend = 1;
15111 else if (strcmp (name, "insn32") == 0)
15112 mips_opts.insn32 = TRUE;
15113 else if (strcmp (name, "noinsn32") == 0)
15114 mips_opts.insn32 = FALSE;
15115 else if (strcmp (name, "push") == 0)
15117 struct mips_option_stack *s;
15119 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15120 s->next = mips_opts_stack;
15121 s->options = mips_opts;
15122 mips_opts_stack = s;
15124 else if (strcmp (name, "pop") == 0)
15126 struct mips_option_stack *s;
15128 s = mips_opts_stack;
15130 as_bad (_(".set pop with no .set push"));
15133 /* If we're changing the reorder mode we need to handle
15134 delay slots correctly. */
15135 if (s->options.noreorder && ! mips_opts.noreorder)
15136 start_noreorder ();
15137 else if (! s->options.noreorder && mips_opts.noreorder)
15140 mips_opts = s->options;
15141 mips_opts_stack = s->next;
15145 else if (strcmp (name, "sym32") == 0)
15146 mips_opts.sym32 = TRUE;
15147 else if (strcmp (name, "nosym32") == 0)
15148 mips_opts.sym32 = FALSE;
15149 else if (strchr (name, ','))
15151 /* Generic ".set" directive; use the generic handler. */
15152 *input_line_pointer = ch;
15153 input_line_pointer = name;
15159 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
15161 mips_check_isa_supports_ases ();
15162 *input_line_pointer = ch;
15163 demand_empty_rest_of_line ();
15166 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15167 .option pic2. It means to generate SVR4 PIC calls. */
15170 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15172 mips_pic = SVR4_PIC;
15173 mips_abicalls = TRUE;
15175 if (g_switch_seen && g_switch_value != 0)
15176 as_warn (_("-G may not be used with SVR4 PIC code"));
15177 g_switch_value = 0;
15179 bfd_set_gp_size (stdoutput, 0);
15180 demand_empty_rest_of_line ();
15183 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15184 PIC code. It sets the $gp register for the function based on the
15185 function address, which is in the register named in the argument.
15186 This uses a relocation against _gp_disp, which is handled specially
15187 by the linker. The result is:
15188 lui $gp,%hi(_gp_disp)
15189 addiu $gp,$gp,%lo(_gp_disp)
15190 addu $gp,$gp,.cpload argument
15191 The .cpload argument is normally $25 == $t9.
15193 The -mno-shared option changes this to:
15194 lui $gp,%hi(__gnu_local_gp)
15195 addiu $gp,$gp,%lo(__gnu_local_gp)
15196 and the argument is ignored. This saves an instruction, but the
15197 resulting code is not position independent; it uses an absolute
15198 address for __gnu_local_gp. Thus code assembled with -mno-shared
15199 can go into an ordinary executable, but not into a shared library. */
15202 s_cpload (int ignore ATTRIBUTE_UNUSED)
15208 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15209 .cpload is ignored. */
15210 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15216 if (mips_opts.mips16)
15218 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15219 ignore_rest_of_line ();
15223 /* .cpload should be in a .set noreorder section. */
15224 if (mips_opts.noreorder == 0)
15225 as_warn (_(".cpload not in noreorder section"));
15227 reg = tc_get_register (0);
15229 /* If we need to produce a 64-bit address, we are better off using
15230 the default instruction sequence. */
15231 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15233 ex.X_op = O_symbol;
15234 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15236 ex.X_op_symbol = NULL;
15237 ex.X_add_number = 0;
15239 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15240 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15242 mips_mark_labels ();
15243 mips_assembling_insn = TRUE;
15246 macro_build_lui (&ex, mips_gp_register);
15247 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15248 mips_gp_register, BFD_RELOC_LO16);
15250 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15251 mips_gp_register, reg);
15254 mips_assembling_insn = FALSE;
15255 demand_empty_rest_of_line ();
15258 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15259 .cpsetup $reg1, offset|$reg2, label
15261 If offset is given, this results in:
15262 sd $gp, offset($sp)
15263 lui $gp, %hi(%neg(%gp_rel(label)))
15264 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15265 daddu $gp, $gp, $reg1
15267 If $reg2 is given, this results in:
15268 daddu $reg2, $gp, $0
15269 lui $gp, %hi(%neg(%gp_rel(label)))
15270 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15271 daddu $gp, $gp, $reg1
15272 $reg1 is normally $25 == $t9.
15274 The -mno-shared option replaces the last three instructions with
15276 addiu $gp,$gp,%lo(_gp) */
15279 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15281 expressionS ex_off;
15282 expressionS ex_sym;
15285 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15286 We also need NewABI support. */
15287 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15293 if (mips_opts.mips16)
15295 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15296 ignore_rest_of_line ();
15300 reg1 = tc_get_register (0);
15301 SKIP_WHITESPACE ();
15302 if (*input_line_pointer != ',')
15304 as_bad (_("missing argument separator ',' for .cpsetup"));
15308 ++input_line_pointer;
15309 SKIP_WHITESPACE ();
15310 if (*input_line_pointer == '$')
15312 mips_cpreturn_register = tc_get_register (0);
15313 mips_cpreturn_offset = -1;
15317 mips_cpreturn_offset = get_absolute_expression ();
15318 mips_cpreturn_register = -1;
15320 SKIP_WHITESPACE ();
15321 if (*input_line_pointer != ',')
15323 as_bad (_("missing argument separator ',' for .cpsetup"));
15327 ++input_line_pointer;
15328 SKIP_WHITESPACE ();
15329 expression (&ex_sym);
15331 mips_mark_labels ();
15332 mips_assembling_insn = TRUE;
15335 if (mips_cpreturn_register == -1)
15337 ex_off.X_op = O_constant;
15338 ex_off.X_add_symbol = NULL;
15339 ex_off.X_op_symbol = NULL;
15340 ex_off.X_add_number = mips_cpreturn_offset;
15342 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15343 BFD_RELOC_LO16, SP);
15346 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15347 mips_gp_register, 0);
15349 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15351 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15352 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15355 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15356 mips_gp_register, -1, BFD_RELOC_GPREL16,
15357 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15359 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15360 mips_gp_register, reg1);
15366 ex.X_op = O_symbol;
15367 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15368 ex.X_op_symbol = NULL;
15369 ex.X_add_number = 0;
15371 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15372 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15374 macro_build_lui (&ex, mips_gp_register);
15375 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15376 mips_gp_register, BFD_RELOC_LO16);
15381 mips_assembling_insn = FALSE;
15382 demand_empty_rest_of_line ();
15386 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15388 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15389 .cplocal is ignored. */
15390 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15396 if (mips_opts.mips16)
15398 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15399 ignore_rest_of_line ();
15403 mips_gp_register = tc_get_register (0);
15404 demand_empty_rest_of_line ();
15407 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15408 offset from $sp. The offset is remembered, and after making a PIC
15409 call $gp is restored from that location. */
15412 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15416 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15417 .cprestore is ignored. */
15418 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15424 if (mips_opts.mips16)
15426 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15427 ignore_rest_of_line ();
15431 mips_cprestore_offset = get_absolute_expression ();
15432 mips_cprestore_valid = 1;
15434 ex.X_op = O_constant;
15435 ex.X_add_symbol = NULL;
15436 ex.X_op_symbol = NULL;
15437 ex.X_add_number = mips_cprestore_offset;
15439 mips_mark_labels ();
15440 mips_assembling_insn = TRUE;
15443 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15444 SP, HAVE_64BIT_ADDRESSES);
15447 mips_assembling_insn = FALSE;
15448 demand_empty_rest_of_line ();
15451 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15452 was given in the preceding .cpsetup, it results in:
15453 ld $gp, offset($sp)
15455 If a register $reg2 was given there, it results in:
15456 daddu $gp, $reg2, $0 */
15459 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15463 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15464 We also need NewABI support. */
15465 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15471 if (mips_opts.mips16)
15473 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15474 ignore_rest_of_line ();
15478 mips_mark_labels ();
15479 mips_assembling_insn = TRUE;
15482 if (mips_cpreturn_register == -1)
15484 ex.X_op = O_constant;
15485 ex.X_add_symbol = NULL;
15486 ex.X_op_symbol = NULL;
15487 ex.X_add_number = mips_cpreturn_offset;
15489 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15492 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15493 mips_cpreturn_register, 0);
15496 mips_assembling_insn = FALSE;
15497 demand_empty_rest_of_line ();
15500 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15501 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15502 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15503 debug information or MIPS16 TLS. */
15506 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15507 bfd_reloc_code_real_type rtype)
15514 if (ex.X_op != O_symbol)
15516 as_bad (_("Unsupported use of %s"), dirstr);
15517 ignore_rest_of_line ();
15520 p = frag_more (bytes);
15521 md_number_to_chars (p, 0, bytes);
15522 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15523 demand_empty_rest_of_line ();
15524 mips_clear_insn_labels ();
15527 /* Handle .dtprelword. */
15530 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15532 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15535 /* Handle .dtpreldword. */
15538 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15540 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15543 /* Handle .tprelword. */
15546 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15548 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15551 /* Handle .tpreldword. */
15554 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15556 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15559 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15560 code. It sets the offset to use in gp_rel relocations. */
15563 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15565 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15566 We also need NewABI support. */
15567 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15573 mips_gprel_offset = get_absolute_expression ();
15575 demand_empty_rest_of_line ();
15578 /* Handle the .gpword pseudo-op. This is used when generating PIC
15579 code. It generates a 32 bit GP relative reloc. */
15582 s_gpword (int ignore ATTRIBUTE_UNUSED)
15584 segment_info_type *si;
15585 struct insn_label_list *l;
15589 /* When not generating PIC code, this is treated as .word. */
15590 if (mips_pic != SVR4_PIC)
15596 si = seg_info (now_seg);
15597 l = si->label_list;
15598 mips_emit_delays ();
15600 mips_align (2, 0, l);
15603 mips_clear_insn_labels ();
15605 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15607 as_bad (_("Unsupported use of .gpword"));
15608 ignore_rest_of_line ();
15612 md_number_to_chars (p, 0, 4);
15613 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15614 BFD_RELOC_GPREL32);
15616 demand_empty_rest_of_line ();
15620 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15622 segment_info_type *si;
15623 struct insn_label_list *l;
15627 /* When not generating PIC code, this is treated as .dword. */
15628 if (mips_pic != SVR4_PIC)
15634 si = seg_info (now_seg);
15635 l = si->label_list;
15636 mips_emit_delays ();
15638 mips_align (3, 0, l);
15641 mips_clear_insn_labels ();
15643 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15645 as_bad (_("Unsupported use of .gpdword"));
15646 ignore_rest_of_line ();
15650 md_number_to_chars (p, 0, 8);
15651 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15652 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15654 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15655 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15656 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15658 demand_empty_rest_of_line ();
15661 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15662 tables. It generates a R_MIPS_EH reloc. */
15665 s_ehword (int ignore ATTRIBUTE_UNUSED)
15670 mips_emit_delays ();
15673 mips_clear_insn_labels ();
15675 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15677 as_bad (_("Unsupported use of .ehword"));
15678 ignore_rest_of_line ();
15682 md_number_to_chars (p, 0, 4);
15683 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15684 BFD_RELOC_MIPS_EH);
15686 demand_empty_rest_of_line ();
15689 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15690 tables in SVR4 PIC code. */
15693 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15697 /* This is ignored when not generating SVR4 PIC code. */
15698 if (mips_pic != SVR4_PIC)
15704 mips_mark_labels ();
15705 mips_assembling_insn = TRUE;
15707 /* Add $gp to the register named as an argument. */
15709 reg = tc_get_register (0);
15710 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15713 mips_assembling_insn = FALSE;
15714 demand_empty_rest_of_line ();
15717 /* Handle the .insn pseudo-op. This marks instruction labels in
15718 mips16/micromips mode. This permits the linker to handle them specially,
15719 such as generating jalx instructions when needed. We also make
15720 them odd for the duration of the assembly, in order to generate the
15721 right sort of code. We will make them even in the adjust_symtab
15722 routine, while leaving them marked. This is convenient for the
15723 debugger and the disassembler. The linker knows to make them odd
15727 s_insn (int ignore ATTRIBUTE_UNUSED)
15729 mips_mark_labels ();
15731 demand_empty_rest_of_line ();
15734 /* Handle the .nan pseudo-op. */
15737 s_nan (int ignore ATTRIBUTE_UNUSED)
15739 static const char str_legacy[] = "legacy";
15740 static const char str_2008[] = "2008";
15743 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15745 if (i == sizeof (str_2008) - 1
15746 && memcmp (input_line_pointer, str_2008, i) == 0)
15747 mips_flag_nan2008 = TRUE;
15748 else if (i == sizeof (str_legacy) - 1
15749 && memcmp (input_line_pointer, str_legacy, i) == 0)
15750 mips_flag_nan2008 = FALSE;
15752 as_bad (_("Bad .nan directive"));
15754 input_line_pointer += i;
15755 demand_empty_rest_of_line ();
15758 /* Handle a .stab[snd] directive. Ideally these directives would be
15759 implemented in a transparent way, so that removing them would not
15760 have any effect on the generated instructions. However, s_stab
15761 internally changes the section, so in practice we need to decide
15762 now whether the preceding label marks compressed code. We do not
15763 support changing the compression mode of a label after a .stab*
15764 directive, such as in:
15770 so the current mode wins. */
15773 s_mips_stab (int type)
15775 mips_mark_labels ();
15779 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15782 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15789 name = input_line_pointer;
15790 c = get_symbol_end ();
15791 symbolP = symbol_find_or_make (name);
15792 S_SET_WEAK (symbolP);
15793 *input_line_pointer = c;
15795 SKIP_WHITESPACE ();
15797 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15799 if (S_IS_DEFINED (symbolP))
15801 as_bad (_("ignoring attempt to redefine symbol %s"),
15802 S_GET_NAME (symbolP));
15803 ignore_rest_of_line ();
15807 if (*input_line_pointer == ',')
15809 ++input_line_pointer;
15810 SKIP_WHITESPACE ();
15814 if (exp.X_op != O_symbol)
15816 as_bad (_("bad .weakext directive"));
15817 ignore_rest_of_line ();
15820 symbol_set_value_expression (symbolP, &exp);
15823 demand_empty_rest_of_line ();
15826 /* Parse a register string into a number. Called from the ECOFF code
15827 to parse .frame. The argument is non-zero if this is the frame
15828 register, so that we can record it in mips_frame_reg. */
15831 tc_get_register (int frame)
15835 SKIP_WHITESPACE ();
15836 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15840 mips_frame_reg = reg != 0 ? reg : SP;
15841 mips_frame_reg_valid = 1;
15842 mips_cprestore_valid = 0;
15848 md_section_align (asection *seg, valueT addr)
15850 int align = bfd_get_section_alignment (stdoutput, seg);
15852 /* We don't need to align ELF sections to the full alignment.
15853 However, Irix 5 may prefer that we align them at least to a 16
15854 byte boundary. We don't bother to align the sections if we
15855 are targeted for an embedded system. */
15856 if (strncmp (TARGET_OS, "elf", 3) == 0)
15861 return ((addr + (1 << align) - 1) & (-1 << align));
15864 /* Utility routine, called from above as well. If called while the
15865 input file is still being read, it's only an approximation. (For
15866 example, a symbol may later become defined which appeared to be
15867 undefined earlier.) */
15870 nopic_need_relax (symbolS *sym, int before_relaxing)
15875 if (g_switch_value > 0)
15877 const char *symname;
15880 /* Find out whether this symbol can be referenced off the $gp
15881 register. It can be if it is smaller than the -G size or if
15882 it is in the .sdata or .sbss section. Certain symbols can
15883 not be referenced off the $gp, although it appears as though
15885 symname = S_GET_NAME (sym);
15886 if (symname != (const char *) NULL
15887 && (strcmp (symname, "eprol") == 0
15888 || strcmp (symname, "etext") == 0
15889 || strcmp (symname, "_gp") == 0
15890 || strcmp (symname, "edata") == 0
15891 || strcmp (symname, "_fbss") == 0
15892 || strcmp (symname, "_fdata") == 0
15893 || strcmp (symname, "_ftext") == 0
15894 || strcmp (symname, "end") == 0
15895 || strcmp (symname, "_gp_disp") == 0))
15897 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15899 #ifndef NO_ECOFF_DEBUGGING
15900 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15901 && (symbol_get_obj (sym)->ecoff_extern_size
15902 <= g_switch_value))
15904 /* We must defer this decision until after the whole
15905 file has been read, since there might be a .extern
15906 after the first use of this symbol. */
15907 || (before_relaxing
15908 #ifndef NO_ECOFF_DEBUGGING
15909 && symbol_get_obj (sym)->ecoff_extern_size == 0
15911 && S_GET_VALUE (sym) == 0)
15912 || (S_GET_VALUE (sym) != 0
15913 && S_GET_VALUE (sym) <= g_switch_value)))
15917 const char *segname;
15919 segname = segment_name (S_GET_SEGMENT (sym));
15920 gas_assert (strcmp (segname, ".lit8") != 0
15921 && strcmp (segname, ".lit4") != 0);
15922 change = (strcmp (segname, ".sdata") != 0
15923 && strcmp (segname, ".sbss") != 0
15924 && strncmp (segname, ".sdata.", 7) != 0
15925 && strncmp (segname, ".sbss.", 6) != 0
15926 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15927 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15932 /* We are not optimizing for the $gp register. */
15937 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15940 pic_need_relax (symbolS *sym, asection *segtype)
15944 /* Handle the case of a symbol equated to another symbol. */
15945 while (symbol_equated_reloc_p (sym))
15949 /* It's possible to get a loop here in a badly written program. */
15950 n = symbol_get_value_expression (sym)->X_add_symbol;
15956 if (symbol_section_p (sym))
15959 symsec = S_GET_SEGMENT (sym);
15961 /* This must duplicate the test in adjust_reloc_syms. */
15962 return (!bfd_is_und_section (symsec)
15963 && !bfd_is_abs_section (symsec)
15964 && !bfd_is_com_section (symsec)
15965 && !s_is_linkonce (sym, segtype)
15966 /* A global or weak symbol is treated as external. */
15967 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15971 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15972 extended opcode. SEC is the section the frag is in. */
15975 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15978 const struct mips_int_operand *operand;
15983 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15985 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15988 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15989 operand = mips16_immed_operand (type, FALSE);
15991 sym_frag = symbol_get_frag (fragp->fr_symbol);
15992 val = S_GET_VALUE (fragp->fr_symbol);
15993 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15995 if (operand->root.type == OP_PCREL)
15997 const struct mips_pcrel_operand *pcrel_op;
16001 /* We won't have the section when we are called from
16002 mips_relax_frag. However, we will always have been called
16003 from md_estimate_size_before_relax first. If this is a
16004 branch to a different section, we mark it as such. If SEC is
16005 NULL, and the frag is not marked, then it must be a branch to
16006 the same section. */
16007 pcrel_op = (const struct mips_pcrel_operand *) operand;
16010 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16015 /* Must have been called from md_estimate_size_before_relax. */
16018 fragp->fr_subtype =
16019 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16021 /* FIXME: We should support this, and let the linker
16022 catch branches and loads that are out of range. */
16023 as_bad_where (fragp->fr_file, fragp->fr_line,
16024 _("unsupported PC relative reference to different section"));
16028 if (fragp != sym_frag && sym_frag->fr_address == 0)
16029 /* Assume non-extended on the first relaxation pass.
16030 The address we have calculated will be bogus if this is
16031 a forward branch to another frag, as the forward frag
16032 will have fr_address == 0. */
16036 /* In this case, we know for sure that the symbol fragment is in
16037 the same section. If the relax_marker of the symbol fragment
16038 differs from the relax_marker of this fragment, we have not
16039 yet adjusted the symbol fragment fr_address. We want to add
16040 in STRETCH in order to get a better estimate of the address.
16041 This particularly matters because of the shift bits. */
16043 && sym_frag->relax_marker != fragp->relax_marker)
16047 /* Adjust stretch for any alignment frag. Note that if have
16048 been expanding the earlier code, the symbol may be
16049 defined in what appears to be an earlier frag. FIXME:
16050 This doesn't handle the fr_subtype field, which specifies
16051 a maximum number of bytes to skip when doing an
16053 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16055 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16058 stretch = - ((- stretch)
16059 & ~ ((1 << (int) f->fr_offset) - 1));
16061 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16070 addr = fragp->fr_address + fragp->fr_fix;
16072 /* The base address rules are complicated. The base address of
16073 a branch is the following instruction. The base address of a
16074 PC relative load or add is the instruction itself, but if it
16075 is in a delay slot (in which case it can not be extended) use
16076 the address of the instruction whose delay slot it is in. */
16077 if (pcrel_op->include_isa_bit)
16081 /* If we are currently assuming that this frag should be
16082 extended, then, the current address is two bytes
16084 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16087 /* Ignore the low bit in the target, since it will be set
16088 for a text label. */
16091 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16093 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16096 val -= addr & -(1 << pcrel_op->align_log2);
16098 /* If any of the shifted bits are set, we must use an extended
16099 opcode. If the address depends on the size of this
16100 instruction, this can lead to a loop, so we arrange to always
16101 use an extended opcode. We only check this when we are in
16102 the main relaxation loop, when SEC is NULL. */
16103 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16105 fragp->fr_subtype =
16106 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16110 /* If we are about to mark a frag as extended because the value
16111 is precisely the next value above maxtiny, then there is a
16112 chance of an infinite loop as in the following code:
16117 In this case when the la is extended, foo is 0x3fc bytes
16118 away, so the la can be shrunk, but then foo is 0x400 away, so
16119 the la must be extended. To avoid this loop, we mark the
16120 frag as extended if it was small, and is about to become
16121 extended with the next value above maxtiny. */
16122 maxtiny = mips_int_operand_max (operand);
16123 if (val == maxtiny + (1 << operand->shift)
16124 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16127 fragp->fr_subtype =
16128 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16132 else if (symsec != absolute_section && sec != NULL)
16133 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16135 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16138 /* Compute the length of a branch sequence, and adjust the
16139 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16140 worst-case length is computed, with UPDATE being used to indicate
16141 whether an unconditional (-1), branch-likely (+1) or regular (0)
16142 branch is to be computed. */
16144 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16146 bfd_boolean toofar;
16150 && S_IS_DEFINED (fragp->fr_symbol)
16151 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16156 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16158 addr = fragp->fr_address + fragp->fr_fix + 4;
16162 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16165 /* If the symbol is not defined or it's in a different segment,
16166 assume the user knows what's going on and emit a short
16172 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16174 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16175 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16176 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16177 RELAX_BRANCH_LINK (fragp->fr_subtype),
16183 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16186 if (mips_pic != NO_PIC)
16188 /* Additional space for PIC loading of target address. */
16190 if (mips_opts.isa == ISA_MIPS1)
16191 /* Additional space for $at-stabilizing nop. */
16195 /* If branch is conditional. */
16196 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16203 /* Compute the length of a branch sequence, and adjust the
16204 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16205 worst-case length is computed, with UPDATE being used to indicate
16206 whether an unconditional (-1), or regular (0) branch is to be
16210 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16212 bfd_boolean toofar;
16216 && S_IS_DEFINED (fragp->fr_symbol)
16217 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16222 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16223 /* Ignore the low bit in the target, since it will be set
16224 for a text label. */
16225 if ((val & 1) != 0)
16228 addr = fragp->fr_address + fragp->fr_fix + 4;
16232 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16235 /* If the symbol is not defined or it's in a different segment,
16236 assume the user knows what's going on and emit a short
16242 if (fragp && update
16243 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16244 fragp->fr_subtype = (toofar
16245 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16246 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16251 bfd_boolean compact_known = fragp != NULL;
16252 bfd_boolean compact = FALSE;
16253 bfd_boolean uncond;
16256 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16258 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16260 uncond = update < 0;
16262 /* If label is out of range, we turn branch <br>:
16264 <br> label # 4 bytes
16270 nop # 2 bytes if compact && !PIC
16273 if (mips_pic == NO_PIC && (!compact_known || compact))
16276 /* If assembling PIC code, we further turn:
16282 lw/ld at, %got(label)(gp) # 4 bytes
16283 d/addiu at, %lo(label) # 4 bytes
16286 if (mips_pic != NO_PIC)
16289 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16291 <brneg> 0f # 4 bytes
16292 nop # 2 bytes if !compact
16295 length += (compact_known && compact) ? 4 : 6;
16301 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16302 bit accordingly. */
16305 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16307 bfd_boolean toofar;
16310 && S_IS_DEFINED (fragp->fr_symbol)
16311 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16317 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16318 /* Ignore the low bit in the target, since it will be set
16319 for a text label. */
16320 if ((val & 1) != 0)
16323 /* Assume this is a 2-byte branch. */
16324 addr = fragp->fr_address + fragp->fr_fix + 2;
16326 /* We try to avoid the infinite loop by not adding 2 more bytes for
16331 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16333 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16334 else if (type == 'E')
16335 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16340 /* If the symbol is not defined or it's in a different segment,
16341 we emit a normal 32-bit branch. */
16344 if (fragp && update
16345 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16347 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16348 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16356 /* Estimate the size of a frag before relaxing. Unless this is the
16357 mips16, we are not really relaxing here, and the final size is
16358 encoded in the subtype information. For the mips16, we have to
16359 decide whether we are using an extended opcode or not. */
16362 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16366 if (RELAX_BRANCH_P (fragp->fr_subtype))
16369 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16371 return fragp->fr_var;
16374 if (RELAX_MIPS16_P (fragp->fr_subtype))
16375 /* We don't want to modify the EXTENDED bit here; it might get us
16376 into infinite loops. We change it only in mips_relax_frag(). */
16377 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16379 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16383 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16384 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16385 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16386 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16387 fragp->fr_var = length;
16392 if (mips_pic == NO_PIC)
16393 change = nopic_need_relax (fragp->fr_symbol, 0);
16394 else if (mips_pic == SVR4_PIC)
16395 change = pic_need_relax (fragp->fr_symbol, segtype);
16396 else if (mips_pic == VXWORKS_PIC)
16397 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16404 fragp->fr_subtype |= RELAX_USE_SECOND;
16405 return -RELAX_FIRST (fragp->fr_subtype);
16408 return -RELAX_SECOND (fragp->fr_subtype);
16411 /* This is called to see whether a reloc against a defined symbol
16412 should be converted into a reloc against a section. */
16415 mips_fix_adjustable (fixS *fixp)
16417 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16418 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16421 if (fixp->fx_addsy == NULL)
16424 /* If symbol SYM is in a mergeable section, relocations of the form
16425 SYM + 0 can usually be made section-relative. The mergeable data
16426 is then identified by the section offset rather than by the symbol.
16428 However, if we're generating REL LO16 relocations, the offset is split
16429 between the LO16 and parterning high part relocation. The linker will
16430 need to recalculate the complete offset in order to correctly identify
16433 The linker has traditionally not looked for the parterning high part
16434 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16435 placed anywhere. Rather than break backwards compatibility by changing
16436 this, it seems better not to force the issue, and instead keep the
16437 original symbol. This will work with either linker behavior. */
16438 if ((lo16_reloc_p (fixp->fx_r_type)
16439 || reloc_needs_lo_p (fixp->fx_r_type))
16440 && HAVE_IN_PLACE_ADDENDS
16441 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16444 /* There is no place to store an in-place offset for JALR relocations.
16445 Likewise an in-range offset of limited PC-relative relocations may
16446 overflow the in-place relocatable field if recalculated against the
16447 start address of the symbol's containing section. */
16448 if (HAVE_IN_PLACE_ADDENDS
16449 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16450 || jalr_reloc_p (fixp->fx_r_type)))
16453 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16454 to a floating-point stub. The same is true for non-R_MIPS16_26
16455 relocations against MIPS16 functions; in this case, the stub becomes
16456 the function's canonical address.
16458 Floating-point stubs are stored in unique .mips16.call.* or
16459 .mips16.fn.* sections. If a stub T for function F is in section S,
16460 the first relocation in section S must be against F; this is how the
16461 linker determines the target function. All relocations that might
16462 resolve to T must also be against F. We therefore have the following
16463 restrictions, which are given in an intentionally-redundant way:
16465 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16468 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16469 if that stub might be used.
16471 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16474 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16475 that stub might be used.
16477 There is a further restriction:
16479 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16480 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16481 targets with in-place addends; the relocation field cannot
16482 encode the low bit.
16484 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16485 against a MIPS16 symbol. We deal with (5) by by not reducing any
16486 such relocations on REL targets.
16488 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16489 relocation against some symbol R, no relocation against R may be
16490 reduced. (Note that this deals with (2) as well as (1) because
16491 relocations against global symbols will never be reduced on ELF
16492 targets.) This approach is a little simpler than trying to detect
16493 stub sections, and gives the "all or nothing" per-symbol consistency
16494 that we have for MIPS16 symbols. */
16495 if (fixp->fx_subsy == NULL
16496 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16497 || *symbol_get_tc (fixp->fx_addsy)
16498 || (HAVE_IN_PLACE_ADDENDS
16499 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16500 && jmp_reloc_p (fixp->fx_r_type))))
16506 /* Translate internal representation of relocation info to BFD target
16510 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16512 static arelent *retval[4];
16514 bfd_reloc_code_real_type code;
16516 memset (retval, 0, sizeof(retval));
16517 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16518 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16519 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16520 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16522 if (fixp->fx_pcrel)
16524 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16525 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16526 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16527 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16528 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16530 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16531 Relocations want only the symbol offset. */
16532 reloc->addend = fixp->fx_addnumber + reloc->address;
16535 reloc->addend = fixp->fx_addnumber;
16537 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16538 entry to be used in the relocation's section offset. */
16539 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16541 reloc->address = reloc->addend;
16545 code = fixp->fx_r_type;
16547 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16548 if (reloc->howto == NULL)
16550 as_bad_where (fixp->fx_file, fixp->fx_line,
16551 _("Can not represent %s relocation in this object file format"),
16552 bfd_get_reloc_code_name (code));
16559 /* Relax a machine dependent frag. This returns the amount by which
16560 the current size of the frag should change. */
16563 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16565 if (RELAX_BRANCH_P (fragp->fr_subtype))
16567 offsetT old_var = fragp->fr_var;
16569 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16571 return fragp->fr_var - old_var;
16574 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16576 offsetT old_var = fragp->fr_var;
16577 offsetT new_var = 4;
16579 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16580 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16581 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16582 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16583 fragp->fr_var = new_var;
16585 return new_var - old_var;
16588 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16591 if (mips16_extended_frag (fragp, NULL, stretch))
16593 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16595 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16600 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16602 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16609 /* Convert a machine dependent frag. */
16612 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16614 if (RELAX_BRANCH_P (fragp->fr_subtype))
16617 unsigned long insn;
16621 buf = fragp->fr_literal + fragp->fr_fix;
16622 insn = read_insn (buf);
16624 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16626 /* We generate a fixup instead of applying it right now
16627 because, if there are linker relaxations, we're going to
16628 need the relocations. */
16629 exp.X_op = O_symbol;
16630 exp.X_add_symbol = fragp->fr_symbol;
16631 exp.X_add_number = fragp->fr_offset;
16633 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16634 BFD_RELOC_16_PCREL_S2);
16635 fixp->fx_file = fragp->fr_file;
16636 fixp->fx_line = fragp->fr_line;
16638 buf = write_insn (buf, insn);
16644 as_warn_where (fragp->fr_file, fragp->fr_line,
16645 _("Relaxed out-of-range branch into a jump"));
16647 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16650 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16652 /* Reverse the branch. */
16653 switch ((insn >> 28) & 0xf)
16656 /* bc[0-3][tf]l? instructions can have the condition
16657 reversed by tweaking a single TF bit, and their
16658 opcodes all have 0x4???????. */
16659 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16660 insn ^= 0x00010000;
16664 /* bltz 0x04000000 bgez 0x04010000
16665 bltzal 0x04100000 bgezal 0x04110000 */
16666 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16667 insn ^= 0x00010000;
16671 /* beq 0x10000000 bne 0x14000000
16672 blez 0x18000000 bgtz 0x1c000000 */
16673 insn ^= 0x04000000;
16681 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16683 /* Clear the and-link bit. */
16684 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16686 /* bltzal 0x04100000 bgezal 0x04110000
16687 bltzall 0x04120000 bgezall 0x04130000 */
16688 insn &= ~0x00100000;
16691 /* Branch over the branch (if the branch was likely) or the
16692 full jump (not likely case). Compute the offset from the
16693 current instruction to branch to. */
16694 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16698 /* How many bytes in instructions we've already emitted? */
16699 i = buf - fragp->fr_literal - fragp->fr_fix;
16700 /* How many bytes in instructions from here to the end? */
16701 i = fragp->fr_var - i;
16703 /* Convert to instruction count. */
16705 /* Branch counts from the next instruction. */
16708 /* Branch over the jump. */
16709 buf = write_insn (buf, insn);
16712 buf = write_insn (buf, 0);
16714 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16716 /* beql $0, $0, 2f */
16718 /* Compute the PC offset from the current instruction to
16719 the end of the variable frag. */
16720 /* How many bytes in instructions we've already emitted? */
16721 i = buf - fragp->fr_literal - fragp->fr_fix;
16722 /* How many bytes in instructions from here to the end? */
16723 i = fragp->fr_var - i;
16724 /* Convert to instruction count. */
16726 /* Don't decrement i, because we want to branch over the
16730 buf = write_insn (buf, insn);
16731 buf = write_insn (buf, 0);
16735 if (mips_pic == NO_PIC)
16738 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16739 ? 0x0c000000 : 0x08000000);
16740 exp.X_op = O_symbol;
16741 exp.X_add_symbol = fragp->fr_symbol;
16742 exp.X_add_number = fragp->fr_offset;
16744 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16745 FALSE, BFD_RELOC_MIPS_JMP);
16746 fixp->fx_file = fragp->fr_file;
16747 fixp->fx_line = fragp->fr_line;
16749 buf = write_insn (buf, insn);
16753 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16755 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16756 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16757 insn |= at << OP_SH_RT;
16758 exp.X_op = O_symbol;
16759 exp.X_add_symbol = fragp->fr_symbol;
16760 exp.X_add_number = fragp->fr_offset;
16762 if (fragp->fr_offset)
16764 exp.X_add_symbol = make_expr_symbol (&exp);
16765 exp.X_add_number = 0;
16768 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16769 FALSE, BFD_RELOC_MIPS_GOT16);
16770 fixp->fx_file = fragp->fr_file;
16771 fixp->fx_line = fragp->fr_line;
16773 buf = write_insn (buf, insn);
16775 if (mips_opts.isa == ISA_MIPS1)
16777 buf = write_insn (buf, 0);
16779 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16780 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16781 insn |= at << OP_SH_RS | at << OP_SH_RT;
16783 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16784 FALSE, BFD_RELOC_LO16);
16785 fixp->fx_file = fragp->fr_file;
16786 fixp->fx_line = fragp->fr_line;
16788 buf = write_insn (buf, insn);
16791 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16795 insn |= at << OP_SH_RS;
16797 buf = write_insn (buf, insn);
16801 fragp->fr_fix += fragp->fr_var;
16802 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16806 /* Relax microMIPS branches. */
16807 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16809 char *buf = fragp->fr_literal + fragp->fr_fix;
16810 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16811 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16812 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16813 bfd_boolean short_ds;
16814 unsigned long insn;
16818 exp.X_op = O_symbol;
16819 exp.X_add_symbol = fragp->fr_symbol;
16820 exp.X_add_number = fragp->fr_offset;
16822 fragp->fr_fix += fragp->fr_var;
16824 /* Handle 16-bit branches that fit or are forced to fit. */
16825 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16827 /* We generate a fixup instead of applying it right now,
16828 because if there is linker relaxation, we're going to
16829 need the relocations. */
16831 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16832 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16833 else if (type == 'E')
16834 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16835 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16839 fixp->fx_file = fragp->fr_file;
16840 fixp->fx_line = fragp->fr_line;
16842 /* These relocations can have an addend that won't fit in
16844 fixp->fx_no_overflow = 1;
16849 /* Handle 32-bit branches that fit or are forced to fit. */
16850 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16851 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16853 /* We generate a fixup instead of applying it right now,
16854 because if there is linker relaxation, we're going to
16855 need the relocations. */
16856 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16857 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16858 fixp->fx_file = fragp->fr_file;
16859 fixp->fx_line = fragp->fr_line;
16865 /* Relax 16-bit branches to 32-bit branches. */
16868 insn = read_compressed_insn (buf, 2);
16870 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16871 insn = 0x94000000; /* beq */
16872 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16874 unsigned long regno;
16876 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16877 regno = micromips_to_32_reg_d_map [regno];
16878 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16879 insn |= regno << MICROMIPSOP_SH_RS;
16884 /* Nothing else to do, just write it out. */
16885 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16886 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16888 buf = write_compressed_insn (buf, insn, 4);
16889 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16894 insn = read_compressed_insn (buf, 4);
16896 /* Relax 32-bit branches to a sequence of instructions. */
16897 as_warn_where (fragp->fr_file, fragp->fr_line,
16898 _("Relaxed out-of-range branch into a jump"));
16900 /* Set the short-delay-slot bit. */
16901 short_ds = al && (insn & 0x02000000) != 0;
16903 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16907 /* Reverse the branch. */
16908 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16909 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16910 insn ^= 0x20000000;
16911 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16912 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16913 || (insn & 0xffe00000) == 0x40800000 /* blez */
16914 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16915 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16916 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16917 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16918 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16919 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16920 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16921 insn ^= 0x00400000;
16922 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16923 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16924 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16925 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16926 insn ^= 0x00200000;
16932 /* Clear the and-link and short-delay-slot bits. */
16933 gas_assert ((insn & 0xfda00000) == 0x40200000);
16935 /* bltzal 0x40200000 bgezal 0x40600000 */
16936 /* bltzals 0x42200000 bgezals 0x42600000 */
16937 insn &= ~0x02200000;
16940 /* Make a label at the end for use with the branch. */
16941 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16942 micromips_label_inc ();
16943 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16946 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16947 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16948 fixp->fx_file = fragp->fr_file;
16949 fixp->fx_line = fragp->fr_line;
16951 /* Branch over the jump. */
16952 buf = write_compressed_insn (buf, insn, 4);
16955 buf = write_compressed_insn (buf, 0x0c00, 2);
16958 if (mips_pic == NO_PIC)
16960 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16962 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16963 insn = al ? jal : 0xd4000000;
16965 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16966 BFD_RELOC_MICROMIPS_JMP);
16967 fixp->fx_file = fragp->fr_file;
16968 fixp->fx_line = fragp->fr_line;
16970 buf = write_compressed_insn (buf, insn, 4);
16973 buf = write_compressed_insn (buf, 0x0c00, 2);
16977 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16978 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16979 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16981 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16982 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16983 insn |= at << MICROMIPSOP_SH_RT;
16985 if (exp.X_add_number)
16987 exp.X_add_symbol = make_expr_symbol (&exp);
16988 exp.X_add_number = 0;
16991 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16992 BFD_RELOC_MICROMIPS_GOT16);
16993 fixp->fx_file = fragp->fr_file;
16994 fixp->fx_line = fragp->fr_line;
16996 buf = write_compressed_insn (buf, insn, 4);
16998 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16999 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17000 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17002 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17003 BFD_RELOC_MICROMIPS_LO16);
17004 fixp->fx_file = fragp->fr_file;
17005 fixp->fx_line = fragp->fr_line;
17007 buf = write_compressed_insn (buf, insn, 4);
17009 /* jr/jrc/jalr/jalrs $at */
17010 insn = al ? jalr : jr;
17011 insn |= at << MICROMIPSOP_SH_MJ;
17013 buf = write_compressed_insn (buf, insn, 2);
17016 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17020 if (RELAX_MIPS16_P (fragp->fr_subtype))
17023 const struct mips_int_operand *operand;
17026 unsigned int user_length, length;
17027 unsigned long insn;
17030 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17031 operand = mips16_immed_operand (type, FALSE);
17033 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17034 val = resolve_symbol_value (fragp->fr_symbol);
17035 if (operand->root.type == OP_PCREL)
17037 const struct mips_pcrel_operand *pcrel_op;
17040 pcrel_op = (const struct mips_pcrel_operand *) operand;
17041 addr = fragp->fr_address + fragp->fr_fix;
17043 /* The rules for the base address of a PC relative reloc are
17044 complicated; see mips16_extended_frag. */
17045 if (pcrel_op->include_isa_bit)
17050 /* Ignore the low bit in the target, since it will be
17051 set for a text label. */
17054 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17056 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17059 addr &= -(1 << pcrel_op->align_log2);
17062 /* Make sure the section winds up with the alignment we have
17064 if (operand->shift > 0)
17065 record_alignment (asec, operand->shift);
17069 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17070 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17071 as_warn_where (fragp->fr_file, fragp->fr_line,
17072 _("extended instruction in delay slot"));
17074 buf = fragp->fr_literal + fragp->fr_fix;
17076 insn = read_compressed_insn (buf, 2);
17078 insn |= MIPS16_EXTEND;
17080 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17082 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17087 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17088 BFD_RELOC_UNUSED, val, user_length, &insn);
17090 length = (ext ? 4 : 2);
17091 gas_assert (mips16_opcode_length (insn) == length);
17092 write_compressed_insn (buf, insn, length);
17093 fragp->fr_fix += length;
17097 relax_substateT subtype = fragp->fr_subtype;
17098 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17099 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17103 first = RELAX_FIRST (subtype);
17104 second = RELAX_SECOND (subtype);
17105 fixp = (fixS *) fragp->fr_opcode;
17107 /* If the delay slot chosen does not match the size of the instruction,
17108 then emit a warning. */
17109 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17110 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17115 s = subtype & (RELAX_DELAY_SLOT_16BIT
17116 | RELAX_DELAY_SLOT_SIZE_FIRST
17117 | RELAX_DELAY_SLOT_SIZE_SECOND);
17118 msg = macro_warning (s);
17120 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17124 /* Possibly emit a warning if we've chosen the longer option. */
17125 if (use_second == second_longer)
17131 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17132 msg = macro_warning (s);
17134 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17138 /* Go through all the fixups for the first sequence. Disable them
17139 (by marking them as done) if we're going to use the second
17140 sequence instead. */
17142 && fixp->fx_frag == fragp
17143 && fixp->fx_where < fragp->fr_fix - second)
17145 if (subtype & RELAX_USE_SECOND)
17147 fixp = fixp->fx_next;
17150 /* Go through the fixups for the second sequence. Disable them if
17151 we're going to use the first sequence, otherwise adjust their
17152 addresses to account for the relaxation. */
17153 while (fixp && fixp->fx_frag == fragp)
17155 if (subtype & RELAX_USE_SECOND)
17156 fixp->fx_where -= first;
17159 fixp = fixp->fx_next;
17162 /* Now modify the frag contents. */
17163 if (subtype & RELAX_USE_SECOND)
17167 start = fragp->fr_literal + fragp->fr_fix - first - second;
17168 memmove (start, start + first, second);
17169 fragp->fr_fix -= first;
17172 fragp->fr_fix -= second;
17176 /* This function is called after the relocs have been generated.
17177 We've been storing mips16 text labels as odd. Here we convert them
17178 back to even for the convenience of the debugger. */
17181 mips_frob_file_after_relocs (void)
17184 unsigned int count, i;
17186 syms = bfd_get_outsymbols (stdoutput);
17187 count = bfd_get_symcount (stdoutput);
17188 for (i = 0; i < count; i++, syms++)
17189 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17190 && ((*syms)->value & 1) != 0)
17192 (*syms)->value &= ~1;
17193 /* If the symbol has an odd size, it was probably computed
17194 incorrectly, so adjust that as well. */
17195 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17196 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17200 /* This function is called whenever a label is defined, including fake
17201 labels instantiated off the dot special symbol. It is used when
17202 handling branch delays; if a branch has a label, we assume we cannot
17203 move it. This also bumps the value of the symbol by 1 in compressed
17207 mips_record_label (symbolS *sym)
17209 segment_info_type *si = seg_info (now_seg);
17210 struct insn_label_list *l;
17212 if (free_insn_labels == NULL)
17213 l = (struct insn_label_list *) xmalloc (sizeof *l);
17216 l = free_insn_labels;
17217 free_insn_labels = l->next;
17221 l->next = si->label_list;
17222 si->label_list = l;
17225 /* This function is called as tc_frob_label() whenever a label is defined
17226 and adds a DWARF-2 record we only want for true labels. */
17229 mips_define_label (symbolS *sym)
17231 mips_record_label (sym);
17232 dwarf2_emit_label (sym);
17235 /* This function is called by tc_new_dot_label whenever a new dot symbol
17239 mips_add_dot_label (symbolS *sym)
17241 mips_record_label (sym);
17242 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17243 mips_compressed_mark_label (sym);
17246 /* Some special processing for a MIPS ELF file. */
17249 mips_elf_final_processing (void)
17251 /* Write out the register information. */
17252 if (mips_abi != N64_ABI)
17256 s.ri_gprmask = mips_gprmask;
17257 s.ri_cprmask[0] = mips_cprmask[0];
17258 s.ri_cprmask[1] = mips_cprmask[1];
17259 s.ri_cprmask[2] = mips_cprmask[2];
17260 s.ri_cprmask[3] = mips_cprmask[3];
17261 /* The gp_value field is set by the MIPS ELF backend. */
17263 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17264 ((Elf32_External_RegInfo *)
17265 mips_regmask_frag));
17269 Elf64_Internal_RegInfo s;
17271 s.ri_gprmask = mips_gprmask;
17273 s.ri_cprmask[0] = mips_cprmask[0];
17274 s.ri_cprmask[1] = mips_cprmask[1];
17275 s.ri_cprmask[2] = mips_cprmask[2];
17276 s.ri_cprmask[3] = mips_cprmask[3];
17277 /* The gp_value field is set by the MIPS ELF backend. */
17279 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17280 ((Elf64_External_RegInfo *)
17281 mips_regmask_frag));
17284 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17285 sort of BFD interface for this. */
17286 if (mips_any_noreorder)
17287 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17288 if (mips_pic != NO_PIC)
17290 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
17291 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17294 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17296 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17297 defined at present; this might need to change in future. */
17298 if (file_ase_mips16)
17299 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17300 if (file_ase_micromips)
17301 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17302 if (file_ase & ASE_MDMX)
17303 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17305 /* Set the MIPS ELF ABI flags. */
17306 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17307 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17308 else if (mips_abi == O64_ABI)
17309 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17310 else if (mips_abi == EABI_ABI)
17312 if (!file_mips_gp32)
17313 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17315 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17317 else if (mips_abi == N32_ABI)
17318 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17320 /* Nothing to do for N64_ABI. */
17322 if (mips_32bitmode)
17323 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17325 if (mips_flag_nan2008)
17326 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17328 #if 0 /* XXX FIXME */
17329 /* 32 bit code with 64 bit FP registers. */
17330 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17331 elf_elfheader (stdoutput)->e_flags |= ???;
17335 typedef struct proc {
17337 symbolS *func_end_sym;
17338 unsigned long reg_mask;
17339 unsigned long reg_offset;
17340 unsigned long fpreg_mask;
17341 unsigned long fpreg_offset;
17342 unsigned long frame_offset;
17343 unsigned long frame_reg;
17344 unsigned long pc_reg;
17347 static procS cur_proc;
17348 static procS *cur_proc_ptr;
17349 static int numprocs;
17351 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17352 as "2", and a normal nop as "0". */
17354 #define NOP_OPCODE_MIPS 0
17355 #define NOP_OPCODE_MIPS16 1
17356 #define NOP_OPCODE_MICROMIPS 2
17359 mips_nop_opcode (void)
17361 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17362 return NOP_OPCODE_MICROMIPS;
17363 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17364 return NOP_OPCODE_MIPS16;
17366 return NOP_OPCODE_MIPS;
17369 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17370 32-bit microMIPS NOPs here (if applicable). */
17373 mips_handle_align (fragS *fragp)
17377 int bytes, size, excess;
17380 if (fragp->fr_type != rs_align_code)
17383 p = fragp->fr_literal + fragp->fr_fix;
17385 switch (nop_opcode)
17387 case NOP_OPCODE_MICROMIPS:
17388 opcode = micromips_nop32_insn.insn_opcode;
17391 case NOP_OPCODE_MIPS16:
17392 opcode = mips16_nop_insn.insn_opcode;
17395 case NOP_OPCODE_MIPS:
17397 opcode = nop_insn.insn_opcode;
17402 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17403 excess = bytes % size;
17405 /* Handle the leading part if we're not inserting a whole number of
17406 instructions, and make it the end of the fixed part of the frag.
17407 Try to fit in a short microMIPS NOP if applicable and possible,
17408 and use zeroes otherwise. */
17409 gas_assert (excess < 4);
17410 fragp->fr_fix += excess;
17415 /* Fall through. */
17417 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17419 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17423 /* Fall through. */
17426 /* Fall through. */
17431 md_number_to_chars (p, opcode, size);
17432 fragp->fr_var = size;
17436 md_obj_begin (void)
17443 /* Check for premature end, nesting errors, etc. */
17445 as_warn (_("missing .end at end of assembly"));
17454 if (*input_line_pointer == '-')
17456 ++input_line_pointer;
17459 if (!ISDIGIT (*input_line_pointer))
17460 as_bad (_("expected simple number"));
17461 if (input_line_pointer[0] == '0')
17463 if (input_line_pointer[1] == 'x')
17465 input_line_pointer += 2;
17466 while (ISXDIGIT (*input_line_pointer))
17469 val |= hex_value (*input_line_pointer++);
17471 return negative ? -val : val;
17475 ++input_line_pointer;
17476 while (ISDIGIT (*input_line_pointer))
17479 val |= *input_line_pointer++ - '0';
17481 return negative ? -val : val;
17484 if (!ISDIGIT (*input_line_pointer))
17486 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17487 *input_line_pointer, *input_line_pointer);
17488 as_warn (_("invalid number"));
17491 while (ISDIGIT (*input_line_pointer))
17494 val += *input_line_pointer++ - '0';
17496 return negative ? -val : val;
17499 /* The .file directive; just like the usual .file directive, but there
17500 is an initial number which is the ECOFF file index. In the non-ECOFF
17501 case .file implies DWARF-2. */
17504 s_mips_file (int x ATTRIBUTE_UNUSED)
17506 static int first_file_directive = 0;
17508 if (ECOFF_DEBUGGING)
17517 filename = dwarf2_directive_file (0);
17519 /* Versions of GCC up to 3.1 start files with a ".file"
17520 directive even for stabs output. Make sure that this
17521 ".file" is handled. Note that you need a version of GCC
17522 after 3.1 in order to support DWARF-2 on MIPS. */
17523 if (filename != NULL && ! first_file_directive)
17525 (void) new_logical_line (filename, -1);
17526 s_app_file_string (filename, 0);
17528 first_file_directive = 1;
17532 /* The .loc directive, implying DWARF-2. */
17535 s_mips_loc (int x ATTRIBUTE_UNUSED)
17537 if (!ECOFF_DEBUGGING)
17538 dwarf2_directive_loc (0);
17541 /* The .end directive. */
17544 s_mips_end (int x ATTRIBUTE_UNUSED)
17548 /* Following functions need their own .frame and .cprestore directives. */
17549 mips_frame_reg_valid = 0;
17550 mips_cprestore_valid = 0;
17552 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17555 demand_empty_rest_of_line ();
17560 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17561 as_warn (_(".end not in text section"));
17565 as_warn (_(".end directive without a preceding .ent directive."));
17566 demand_empty_rest_of_line ();
17572 gas_assert (S_GET_NAME (p));
17573 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17574 as_warn (_(".end symbol does not match .ent symbol."));
17576 if (debug_type == DEBUG_STABS)
17577 stabs_generate_asm_endfunc (S_GET_NAME (p),
17581 as_warn (_(".end directive missing or unknown symbol"));
17583 /* Create an expression to calculate the size of the function. */
17584 if (p && cur_proc_ptr)
17586 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17587 expressionS *exp = xmalloc (sizeof (expressionS));
17590 exp->X_op = O_subtract;
17591 exp->X_add_symbol = symbol_temp_new_now ();
17592 exp->X_op_symbol = p;
17593 exp->X_add_number = 0;
17595 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17598 /* Generate a .pdr section. */
17599 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17601 segT saved_seg = now_seg;
17602 subsegT saved_subseg = now_subseg;
17606 #ifdef md_flush_pending_output
17607 md_flush_pending_output ();
17610 gas_assert (pdr_seg);
17611 subseg_set (pdr_seg, 0);
17613 /* Write the symbol. */
17614 exp.X_op = O_symbol;
17615 exp.X_add_symbol = p;
17616 exp.X_add_number = 0;
17617 emit_expr (&exp, 4);
17619 fragp = frag_more (7 * 4);
17621 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17622 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17623 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17624 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17625 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17626 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17627 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17629 subseg_set (saved_seg, saved_subseg);
17632 cur_proc_ptr = NULL;
17635 /* The .aent and .ent directives. */
17638 s_mips_ent (int aent)
17642 symbolP = get_symbol ();
17643 if (*input_line_pointer == ',')
17644 ++input_line_pointer;
17645 SKIP_WHITESPACE ();
17646 if (ISDIGIT (*input_line_pointer)
17647 || *input_line_pointer == '-')
17650 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17651 as_warn (_(".ent or .aent not in text section."));
17653 if (!aent && cur_proc_ptr)
17654 as_warn (_("missing .end"));
17658 /* This function needs its own .frame and .cprestore directives. */
17659 mips_frame_reg_valid = 0;
17660 mips_cprestore_valid = 0;
17662 cur_proc_ptr = &cur_proc;
17663 memset (cur_proc_ptr, '\0', sizeof (procS));
17665 cur_proc_ptr->func_sym = symbolP;
17669 if (debug_type == DEBUG_STABS)
17670 stabs_generate_asm_func (S_GET_NAME (symbolP),
17671 S_GET_NAME (symbolP));
17674 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17676 demand_empty_rest_of_line ();
17679 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17680 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17681 s_mips_frame is used so that we can set the PDR information correctly.
17682 We can't use the ecoff routines because they make reference to the ecoff
17683 symbol table (in the mdebug section). */
17686 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17688 if (ECOFF_DEBUGGING)
17694 if (cur_proc_ptr == (procS *) NULL)
17696 as_warn (_(".frame outside of .ent"));
17697 demand_empty_rest_of_line ();
17701 cur_proc_ptr->frame_reg = tc_get_register (1);
17703 SKIP_WHITESPACE ();
17704 if (*input_line_pointer++ != ','
17705 || get_absolute_expression_and_terminator (&val) != ',')
17707 as_warn (_("Bad .frame directive"));
17708 --input_line_pointer;
17709 demand_empty_rest_of_line ();
17713 cur_proc_ptr->frame_offset = val;
17714 cur_proc_ptr->pc_reg = tc_get_register (0);
17716 demand_empty_rest_of_line ();
17720 /* The .fmask and .mask directives. If the mdebug section is present
17721 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17722 embedded targets, s_mips_mask is used so that we can set the PDR
17723 information correctly. We can't use the ecoff routines because they
17724 make reference to the ecoff symbol table (in the mdebug section). */
17727 s_mips_mask (int reg_type)
17729 if (ECOFF_DEBUGGING)
17730 s_ignore (reg_type);
17735 if (cur_proc_ptr == (procS *) NULL)
17737 as_warn (_(".mask/.fmask outside of .ent"));
17738 demand_empty_rest_of_line ();
17742 if (get_absolute_expression_and_terminator (&mask) != ',')
17744 as_warn (_("Bad .mask/.fmask directive"));
17745 --input_line_pointer;
17746 demand_empty_rest_of_line ();
17750 off = get_absolute_expression ();
17752 if (reg_type == 'F')
17754 cur_proc_ptr->fpreg_mask = mask;
17755 cur_proc_ptr->fpreg_offset = off;
17759 cur_proc_ptr->reg_mask = mask;
17760 cur_proc_ptr->reg_offset = off;
17763 demand_empty_rest_of_line ();
17767 /* A table describing all the processors gas knows about. Names are
17768 matched in the order listed.
17770 To ease comparison, please keep this table in the same order as
17771 gcc's mips_cpu_info_table[]. */
17772 static const struct mips_cpu_info mips_cpu_info_table[] =
17774 /* Entries for generic ISAs */
17775 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17776 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17777 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17778 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17779 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17780 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17781 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17782 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17783 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17786 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17787 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17788 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17791 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17794 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17795 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17796 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17797 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17798 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17799 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17800 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17801 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17802 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17803 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17804 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17805 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17806 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17807 /* ST Microelectronics Loongson 2E and 2F cores */
17808 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17809 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17812 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17813 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17814 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17815 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17816 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17817 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17818 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17819 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17820 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17821 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17822 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17823 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17824 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17825 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17826 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17829 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17830 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17831 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17832 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17834 /* MIPS 32 Release 2 */
17835 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17836 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17837 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17838 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17839 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17840 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17841 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17842 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17843 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17844 ISA_MIPS32R2, CPU_MIPS32R2 },
17845 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17846 ISA_MIPS32R2, CPU_MIPS32R2 },
17847 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17848 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17849 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17850 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17851 /* Deprecated forms of the above. */
17852 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17853 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17854 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17855 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17856 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17857 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17858 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17859 /* Deprecated forms of the above. */
17860 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17861 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17862 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17863 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17864 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17865 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17866 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17867 /* Deprecated forms of the above. */
17868 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17869 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17870 /* 34Kn is a 34kc without DSP. */
17871 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17872 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17873 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17874 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17875 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17876 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17877 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17878 /* Deprecated forms of the above. */
17879 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17880 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17881 /* 1004K cores are multiprocessor versions of the 34K. */
17882 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17883 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17884 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17885 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17888 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17889 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17890 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17891 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17893 /* Broadcom SB-1 CPU core */
17894 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17895 /* Broadcom SB-1A CPU core */
17896 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17898 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17900 /* MIPS 64 Release 2 */
17902 /* Cavium Networks Octeon CPU core */
17903 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17904 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17905 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17908 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17911 XLP is mostly like XLR, with the prominent exception that it is
17912 MIPS64R2 rather than MIPS64. */
17913 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17916 { NULL, 0, 0, 0, 0 }
17920 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17921 with a final "000" replaced by "k". Ignore case.
17923 Note: this function is shared between GCC and GAS. */
17926 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17928 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17929 given++, canonical++;
17931 return ((*given == 0 && *canonical == 0)
17932 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17936 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17937 CPU name. We've traditionally allowed a lot of variation here.
17939 Note: this function is shared between GCC and GAS. */
17942 mips_matching_cpu_name_p (const char *canonical, const char *given)
17944 /* First see if the name matches exactly, or with a final "000"
17945 turned into "k". */
17946 if (mips_strict_matching_cpu_name_p (canonical, given))
17949 /* If not, try comparing based on numerical designation alone.
17950 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17951 if (TOLOWER (*given) == 'r')
17953 if (!ISDIGIT (*given))
17956 /* Skip over some well-known prefixes in the canonical name,
17957 hoping to find a number there too. */
17958 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17960 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17962 else if (TOLOWER (canonical[0]) == 'r')
17965 return mips_strict_matching_cpu_name_p (canonical, given);
17969 /* Parse an option that takes the name of a processor as its argument.
17970 OPTION is the name of the option and CPU_STRING is the argument.
17971 Return the corresponding processor enumeration if the CPU_STRING is
17972 recognized, otherwise report an error and return null.
17974 A similar function exists in GCC. */
17976 static const struct mips_cpu_info *
17977 mips_parse_cpu (const char *option, const char *cpu_string)
17979 const struct mips_cpu_info *p;
17981 /* 'from-abi' selects the most compatible architecture for the given
17982 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17983 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17984 version. Look first at the -mgp options, if given, otherwise base
17985 the choice on MIPS_DEFAULT_64BIT.
17987 Treat NO_ABI like the EABIs. One reason to do this is that the
17988 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17989 architecture. This code picks MIPS I for 'mips' and MIPS III for
17990 'mips64', just as we did in the days before 'from-abi'. */
17991 if (strcasecmp (cpu_string, "from-abi") == 0)
17993 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17994 return mips_cpu_info_from_isa (ISA_MIPS1);
17996 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17997 return mips_cpu_info_from_isa (ISA_MIPS3);
17999 if (file_mips_gp32 >= 0)
18000 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
18002 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18007 /* 'default' has traditionally been a no-op. Probably not very useful. */
18008 if (strcasecmp (cpu_string, "default") == 0)
18011 for (p = mips_cpu_info_table; p->name != 0; p++)
18012 if (mips_matching_cpu_name_p (p->name, cpu_string))
18015 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
18019 /* Return the canonical processor information for ISA (a member of the
18020 ISA_MIPS* enumeration). */
18022 static const struct mips_cpu_info *
18023 mips_cpu_info_from_isa (int isa)
18027 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18028 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18029 && isa == mips_cpu_info_table[i].isa)
18030 return (&mips_cpu_info_table[i]);
18035 static const struct mips_cpu_info *
18036 mips_cpu_info_from_arch (int arch)
18040 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18041 if (arch == mips_cpu_info_table[i].cpu)
18042 return (&mips_cpu_info_table[i]);
18048 show (FILE *stream, const char *string, int *col_p, int *first_p)
18052 fprintf (stream, "%24s", "");
18057 fprintf (stream, ", ");
18061 if (*col_p + strlen (string) > 72)
18063 fprintf (stream, "\n%24s", "");
18067 fprintf (stream, "%s", string);
18068 *col_p += strlen (string);
18074 md_show_usage (FILE *stream)
18079 fprintf (stream, _("\
18081 -EB generate big endian output\n\
18082 -EL generate little endian output\n\
18083 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18084 -G NUM allow referencing objects up to NUM bytes\n\
18085 implicitly with the gp register [default 8]\n"));
18086 fprintf (stream, _("\
18087 -mips1 generate MIPS ISA I instructions\n\
18088 -mips2 generate MIPS ISA II instructions\n\
18089 -mips3 generate MIPS ISA III instructions\n\
18090 -mips4 generate MIPS ISA IV instructions\n\
18091 -mips5 generate MIPS ISA V instructions\n\
18092 -mips32 generate MIPS32 ISA instructions\n\
18093 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18094 -mips64 generate MIPS64 ISA instructions\n\
18095 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18096 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18100 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18101 show (stream, mips_cpu_info_table[i].name, &column, &first);
18102 show (stream, "from-abi", &column, &first);
18103 fputc ('\n', stream);
18105 fprintf (stream, _("\
18106 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18107 -no-mCPU don't generate code specific to CPU.\n\
18108 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18112 show (stream, "3900", &column, &first);
18113 show (stream, "4010", &column, &first);
18114 show (stream, "4100", &column, &first);
18115 show (stream, "4650", &column, &first);
18116 fputc ('\n', stream);
18118 fprintf (stream, _("\
18119 -mips16 generate mips16 instructions\n\
18120 -no-mips16 do not generate mips16 instructions\n"));
18121 fprintf (stream, _("\
18122 -mmicromips generate microMIPS instructions\n\
18123 -mno-micromips do not generate microMIPS instructions\n"));
18124 fprintf (stream, _("\
18125 -msmartmips generate smartmips instructions\n\
18126 -mno-smartmips do not generate smartmips instructions\n"));
18127 fprintf (stream, _("\
18128 -mdsp generate DSP instructions\n\
18129 -mno-dsp do not generate DSP instructions\n"));
18130 fprintf (stream, _("\
18131 -mdspr2 generate DSP R2 instructions\n\
18132 -mno-dspr2 do not generate DSP R2 instructions\n"));
18133 fprintf (stream, _("\
18134 -mmt generate MT instructions\n\
18135 -mno-mt do not generate MT instructions\n"));
18136 fprintf (stream, _("\
18137 -mmcu generate MCU instructions\n\
18138 -mno-mcu do not generate MCU instructions\n"));
18139 fprintf (stream, _("\
18140 -mvirt generate Virtualization instructions\n\
18141 -mno-virt do not generate Virtualization instructions\n"));
18142 fprintf (stream, _("\
18143 -minsn32 only generate 32-bit microMIPS instructions\n\
18144 -mno-insn32 generate all microMIPS instructions\n"));
18145 fprintf (stream, _("\
18146 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18147 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18148 -mfix-vr4120 work around certain VR4120 errata\n\
18149 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18150 -mfix-24k insert a nop after ERET and DERET instructions\n\
18151 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18152 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18153 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18154 -msym32 assume all symbols have 32-bit values\n\
18155 -O0 remove unneeded NOPs, do not swap branches\n\
18156 -O remove unneeded NOPs and swap branches\n\
18157 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18158 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18159 fprintf (stream, _("\
18160 -mhard-float allow floating-point instructions\n\
18161 -msoft-float do not allow floating-point instructions\n\
18162 -msingle-float only allow 32-bit floating-point operations\n\
18163 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18164 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18165 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18166 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18170 show (stream, "legacy", &column, &first);
18171 show (stream, "2008", &column, &first);
18173 fputc ('\n', stream);
18175 fprintf (stream, _("\
18176 -KPIC, -call_shared generate SVR4 position independent code\n\
18177 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18178 -mvxworks-pic generate VxWorks position independent code\n\
18179 -non_shared do not generate code that can operate with DSOs\n\
18180 -xgot assume a 32 bit GOT\n\
18181 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18182 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18183 position dependent (non shared) code\n\
18184 -mabi=ABI create ABI conformant object file for:\n"));
18188 show (stream, "32", &column, &first);
18189 show (stream, "o64", &column, &first);
18190 show (stream, "n32", &column, &first);
18191 show (stream, "64", &column, &first);
18192 show (stream, "eabi", &column, &first);
18194 fputc ('\n', stream);
18196 fprintf (stream, _("\
18197 -32 create o32 ABI object file (default)\n\
18198 -n32 create n32 ABI object file\n\
18199 -64 create 64 ABI object file\n"));
18204 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
18206 if (HAVE_64BIT_SYMBOLS)
18207 return dwarf2_format_64bit_irix;
18209 return dwarf2_format_32bit;
18214 mips_dwarf2_addr_size (void)
18216 if (HAVE_64BIT_OBJECTS)
18222 /* Standard calling conventions leave the CFA at SP on entry. */
18224 mips_cfi_frame_initial_instructions (void)
18226 cfi_add_CFA_def_cfa_register (SP);
18230 tc_mips_regname_to_dw2regnum (char *regname)
18232 unsigned int regnum = -1;
18235 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))