1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* Decide whether to do GP reference optimizations based on the object
59 /* These variables are filled in with the masks of registers used.
60 The object format code reads them and puts them in the appropriate
62 unsigned long mips_gprmask;
63 unsigned long mips_cprmask[4];
65 /* MIPS ISA (Instruction Set Architecture) level. */
66 static int mips_isa = -1;
68 static int mips_warn_about_macros;
69 static int mips_noreorder;
70 static int mips_nomove;
72 static int mips_nobopt;
75 /* The size of the small data section. */
76 static int g_switch_value = 8;
82 /* handle of the OPCODE hash table */
83 static struct hash_control *op_hash = NULL;
85 /* This array holds the chars that always start a comment. If the
86 pre-processor is disabled, these aren't very useful */
87 const char comment_chars[] = "#";
89 /* This array holds the chars that only start a comment at the beginning of
90 a line. If the line seems to have the form '# 123 filename'
91 .line and .file directives will appear in the pre-processed output */
92 /* Note that input_file.c hand checks for '#' at the beginning of the
93 first line of the input file. This is because the compiler outputs
94 #NO_APP at the beginning of its output. */
95 /* Also note that C style comments are always supported. */
96 const char line_comment_chars[] = "#";
98 /* This array holds machine specific line separator characters. */
99 const char line_separator_chars[] = "";
101 /* Chars that can be used to separate mant from exp in floating point nums */
102 const char EXP_CHARS[] = "eE";
104 /* Chars that mean this number is a floating point constant */
107 const char FLT_CHARS[] = "rRsSfFdDxXpP";
109 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
110 changed in read.c . Ideally it shouldn't have to know about it at all,
111 but nothing is ideal around here.
114 static char *insn_error;
116 static int byte_order = BYTE_ORDER;
118 static int auto_align = 1;
120 /* Symbol labelling the current insn. */
121 static symbolS *insn_label;
123 /* To output NOP instructions correctly, we need to keep information
124 about the previous two instructions. */
126 /* Whether we are optimizing. The default value of 2 means to remove
127 unneeded NOPs and swap branch instructions when possible. A value
128 of 1 means to not swap branches. A value of 0 means to always
130 static int mips_optimize = 2;
132 /* The previous instruction. */
133 static struct mips_cl_insn prev_insn;
135 /* The instruction before prev_insn. */
136 static struct mips_cl_insn prev_prev_insn;
138 /* If we don't want information for prev_insn or prev_prev_insn, we
139 point the insn_mo field at this dummy integer. */
140 static const struct mips_opcode dummy_opcode = { 0 };
142 /* Non-zero if prev_insn is valid. */
143 static int prev_insn_valid;
145 /* The frag for the previous instruction. */
146 static struct frag *prev_insn_frag;
148 /* The offset into prev_insn_frag for the previous instruction. */
149 static long prev_insn_where;
151 /* The reloc for the previous instruction, if any. */
152 static fixS *prev_insn_fixp;
154 /* Non-zero if the previous instruction was in a delay slot. */
155 static int prev_insn_is_delay_slot;
157 /* Non-zero if the previous instruction was in a .set noreorder. */
158 static int prev_insn_unreordered;
160 /* Non-zero if the previous previous instruction was in a .set
162 static int prev_prev_insn_unreordered;
164 /* Prototypes for static functions. */
167 #define internalError() \
168 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
170 #define internalError() as_fatal ("MIPS internal Error");
173 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
174 unsigned int reg, int fpr));
175 static void append_insn PARAMS ((struct mips_cl_insn * ip,
177 bfd_reloc_code_real_type r));
178 static void mips_no_prev_insn PARAMS ((void));
179 static void mips_emit_delays PARAMS ((void));
180 static int gp_reference PARAMS ((expressionS * ep));
181 static void macro_build PARAMS ((int *counter, expressionS * ep,
182 const char *name, const char *fmt,
184 static void macro_build_lui PARAMS ((int *counter, expressionS * ep,
186 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
187 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
189 static void load_register PARAMS ((int *counter,
190 int reg, expressionS * ep));
191 static void macro PARAMS ((struct mips_cl_insn * ip));
192 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
193 static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
194 static void my_getExpression PARAMS ((expressionS * ep, char *str));
195 static symbolS *get_symbol PARAMS ((void));
196 static void mips_align PARAMS ((int to, int fill));
197 static void s_align PARAMS ((int));
198 static void s_stringer PARAMS ((int));
199 static void s_change_sec PARAMS ((int));
200 static void s_cons PARAMS ((int));
201 static void s_err PARAMS ((int));
202 static void s_extern PARAMS ((int));
203 static void s_float_cons PARAMS ((int));
204 static void s_option PARAMS ((int));
205 static void s_mipsset PARAMS ((int));
206 static void s_mips_space PARAMS ((int));
208 static void md_obj_begin PARAMS ((void));
209 static void md_obj_end PARAMS ((void));
210 static long get_number PARAMS ((void));
211 static void s_ent PARAMS ((int));
212 static void s_mipsend PARAMS ((int));
213 static void s_file PARAMS ((int));
215 static void s_frame PARAMS ((int));
216 static void s_loc PARAMS ((int));
217 static void s_mask PARAMS ((char));
223 The following pseudo-ops from the Kane and Heinrich MIPS book
224 should be defined here, but are currently unsupported: .alias,
225 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
227 The following pseudo-ops from the Kane and Heinrich MIPS book are
228 specific to the type of debugging information being generated, and
229 should be defined by the object format: .aent, .begin, .bend,
230 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
233 The following pseudo-ops from the Kane and Heinrich MIPS book are
234 not MIPS CPU specific, but are also not specific to the object file
235 format. This file is probably the best place to define them, but
236 they are not currently supported: .asm0, .endr, .lab, .repeat,
237 .struct, .weakext. */
239 const pseudo_typeS md_pseudo_table[] =
241 /* MIPS specific pseudo-ops. */
242 {"option", s_option, 0},
243 {"set", s_mipsset, 0},
244 {"rdata", s_change_sec, 'r',},
245 {"sdata", s_change_sec, 's',},
247 /* Relatively generic pseudo-ops that happen to be used on MIPS
249 {"asciiz", s_stringer, 1},
250 {"bss", s_change_sec, 'b'},
254 /* These pseudo-ops are defined in read.c, but must be overridden
255 here for one reason or another. */
256 {"align", s_align, 0},
257 {"ascii", s_stringer, 0},
258 {"asciz", s_stringer, 1},
260 {"data", s_change_sec, 'd'},
261 {"double", s_float_cons, 'd'},
262 {"extern", s_extern, 0},
263 {"float", s_float_cons, 'f'},
264 {"space", s_mips_space, 0},
265 {"text", s_change_sec, 't'},
269 /* These pseudo-ops should be defined by the object file format.
270 However, ECOFF is the only format which currently defines them,
271 so we have versions here for a.out. */
273 {"end", s_mipsend, 0},
276 {"fmask", s_ignore, 'F'},
277 {"frame", s_ignore, 0},
278 {"loc", s_ignore, 0},
279 {"mask", s_ignore, 'R'},
280 {"verstamp", s_ignore, 0},
287 const relax_typeS md_relax_table[] =
293 static char *expr_end;
295 static expressionS imm_expr;
296 static expressionS offset_expr;
297 static bfd_reloc_code_real_type imm_reloc;
298 static bfd_reloc_code_real_type offset_reloc;
300 /* FIXME: This should be handled in a different way. */
301 extern int target_big_endian;
304 * This function is called once, at assembler startup time. It should
305 * set up all the tables, etc. that the MD part of the assembler will need.
311 register const char *retval = NULL;
312 register unsigned int i = 0;
316 if (strcmp (TARGET_CPU, "mips") == 0)
318 else if (strcmp (TARGET_CPU, "r6000") == 0
319 || strcmp (TARGET_CPU, "mips2") == 0)
321 else if (strcmp (TARGET_CPU, "mips64") == 0
322 || strcmp (TARGET_CPU, "r4000") == 0
323 || strcmp (TARGET_CPU, "mips3") == 0)
332 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000);
335 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000);
338 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000);
342 as_warn ("Could not set architecture and machine");
344 if ((op_hash = hash_new ()) == NULL)
346 as_fatal ("Virtual memory exhausted");
348 for (i = 0; i < NUMOPCODES;)
350 const char *name = mips_opcodes[i].name;
352 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
355 fprintf (stderr, "internal error: can't hash `%s': %s\n",
356 mips_opcodes[i].name, retval);
357 as_fatal ("Broken assembler. No assembly attempted.");
361 if (mips_opcodes[i].pinfo != INSN_MACRO
362 && ((mips_opcodes[i].match & mips_opcodes[i].mask)
363 != mips_opcodes[i].match))
365 fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n",
366 mips_opcodes[i].name, mips_opcodes[i].args);
367 as_fatal ("Broken assembler. No assembly attempted.");
371 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
374 mips_no_prev_insn ();
382 /* set the default alignment for the text section (2**2) */
383 record_alignment (text_section, 2);
385 /* FIXME: This should be handled in a different way. */
386 target_big_endian = byte_order == BIG_ENDIAN;
389 bfd_set_gp_size (stdoutput, g_switch_value);
409 struct mips_cl_insn insn;
411 imm_expr.X_op = O_absent;
412 offset_expr.X_op = O_absent;
414 mips_ip (str, &insn);
417 as_bad ("%s `%s'", insn_error, str);
420 if (insn.insn_mo->pinfo == INSN_MACRO)
426 if (imm_expr.X_op != O_absent)
427 append_insn (&insn, &imm_expr, imm_reloc);
428 else if (offset_expr.X_op != O_absent)
429 append_insn (&insn, &offset_expr, offset_reloc);
431 append_insn (&insn, NULL, BFD_RELOC_UNUSED);
435 /* See whether instruction IP reads register REG. If FPR is non-zero,
436 REG is a floating point register. */
439 insn_uses_reg (ip, reg, fpr)
440 struct mips_cl_insn *ip;
444 /* Don't report on general register 0, since it never changes. */
445 if (! fpr && reg == 0)
450 /* If we are called with either $f0 or $f1, we must check $f0.
451 This is not optimal, because it will introduce an unnecessary
452 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
453 need to distinguish reading both $f0 and $f1 or just one of
454 them. Note that we don't have to check the other way,
455 because there is no instruction that sets both $f0 and $f1
456 and requires a delay. */
457 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
458 && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS)
459 == (reg &~ (unsigned) 1)))
461 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
462 && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT)
463 == (reg &~ (unsigned) 1)))
468 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
469 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
471 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
472 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
479 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
480 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
484 * Output an instruction.
487 append_insn (ip, address_expr, reloc_type)
488 struct mips_cl_insn *ip;
489 expressionS *address_expr;
490 bfd_reloc_code_real_type reloc_type;
492 register unsigned long prev_pinfo, pinfo;
497 prev_pinfo = prev_insn.insn_mo->pinfo;
498 pinfo = ip->insn_mo->pinfo;
500 if (! mips_noreorder)
502 /* If the previous insn required any delay slots, see if we need
503 to insert a NOP or two. There are eight kinds of possible
504 hazards, of which an instruction can have at most one type.
505 (1) a load from memory delay
506 (2) a load from a coprocessor delay
507 (3) an unconditional branch delay
508 (4) a conditional branch delay
509 (5) a move to coprocessor register delay
510 (6) a load coprocessor register from memory delay
511 (7) a coprocessor condition code delay
512 (8) a HI/LO special register delay
514 There are a lot of optimizations we could do that we don't.
515 In particular, we do not, in general, reorder instructions.
516 If you use gcc with optimization, it will reorder
517 instructions and generally do much more optimization then we
518 do here; repeating all that work in the assembler would only
519 benefit hand written assembly code, and does not seem worth
522 /* This is how a NOP is emitted. */
523 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
525 /* The previous insn might require a delay slot, depending upon
526 the contents of the current insn. */
527 if ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
529 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))
531 /* A load from a coprocessor or from memory. All load
532 delays delay the use of general register rt for one
533 instruction on the r3000. The r6000 and r4000 use
535 know (prev_pinfo & INSN_WRITE_GPR_T);
536 if (mips_optimize == 0
537 || insn_uses_reg (ip,
538 ((prev_insn.insn_opcode >> OP_SH_RT)
543 else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY)
545 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))
547 /* A generic coprocessor delay. The previous instruction
548 modified a coprocessor general or control register. If
549 it modified a control register, we need to avoid any
550 coprocessor instruction (this is probably not always
551 required, but it sometimes is). If it modified a general
552 register, we avoid using that register.
554 On the r6000 and r4000 loading a coprocessor register
555 from memory is interlocked, and does not require a delay.
557 This case is not handled very well. There is no special
558 knowledge of CP0 handling, and the coprocessors other
559 than the floating point unit are not distinguished at
561 if (prev_pinfo & INSN_WRITE_FPR_T)
563 if (mips_optimize == 0
564 || insn_uses_reg (ip,
565 ((prev_insn.insn_opcode >> OP_SH_FT)
570 else if (prev_pinfo & INSN_WRITE_FPR_S)
572 if (mips_optimize == 0
573 || insn_uses_reg (ip,
574 ((prev_insn.insn_opcode >> OP_SH_FS)
581 /* We don't know exactly what the previous instruction
582 does. If the current instruction uses a coprocessor
583 register, we must insert a NOP. If previous
584 instruction may set the condition codes, and the
585 current instruction uses them, we must insert two
587 if (mips_optimize == 0
588 || ((prev_pinfo & INSN_WRITE_COND_CODE)
589 && (pinfo & INSN_READ_COND_CODE)))
591 else if (pinfo & INSN_COP)
595 else if (prev_pinfo & INSN_WRITE_COND_CODE)
597 /* The previous instruction sets the coprocessor condition
598 codes, but does not require a general coprocessor delay
599 (this means it is a floating point comparison
600 instruction). If this instruction uses the condition
601 codes, we need to insert a single NOP. */
602 if (mips_optimize == 0
603 || (pinfo & INSN_READ_COND_CODE))
606 else if (prev_pinfo & INSN_READ_LO)
608 /* The previous instruction reads the LO register; if the
609 current instruction writes to the LO register, we must
611 if (mips_optimize == 0
612 || (pinfo & INSN_WRITE_LO))
615 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
617 /* The previous instruction reads the HI register; if the
618 current instruction writes to the HI register, we must
620 if (mips_optimize == 0
621 || (pinfo & INSN_WRITE_HI))
625 /* There are two cases which require two intervening
626 instructions: 1) setting the condition codes using a move to
627 coprocessor instruction which requires a general coprocessor
628 delay and then reading the condition codes 2) reading the HI
629 or LO register and then writing to it. If we are not already
630 emitting a NOP instruction, we must check for these cases
631 compared to the instruction previous to the previous
634 && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
635 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
636 && (pinfo & INSN_READ_COND_CODE))
637 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
638 && (pinfo & INSN_WRITE_LO))
639 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
640 && (pinfo & INSN_WRITE_HI))))
643 /* Now emit the right number of NOP instructions. */
649 if (insn_label != NULL)
651 assert (S_GET_SEGMENT (insn_label) == now_seg);
652 insn_label->sy_frag = frag_now;
653 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
660 /* This is testing the address of the frag, not the alignment of
661 the instruction in the current section. */
669 if (address_expr != NULL)
671 if (address_expr->X_op == O_constant)
676 ip->insn_opcode |= address_expr->X_add_number;
680 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
683 case BFD_RELOC_MIPS_JMP:
684 case BFD_RELOC_16_PCREL_S2:
693 assert (reloc_type != BFD_RELOC_UNUSED);
695 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
697 reloc_type == BFD_RELOC_16_PCREL_S2,
702 md_number_to_chars (f, ip->insn_opcode, 4);
704 /* Update the register mask information. */
705 if (pinfo & INSN_WRITE_GPR_D)
706 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
707 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
708 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
709 if (pinfo & INSN_READ_GPR_S)
710 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
711 if (pinfo & INSN_WRITE_GPR_31)
712 mips_gprmask |= 1 << 31;
713 if (pinfo & INSN_WRITE_FPR_D)
714 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
715 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
716 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
717 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
718 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
719 if (pinfo & INSN_COP)
721 /* We don't keep enough information to sort these cases out. */
723 /* Never set the bit for $0, which is always zero. */
724 mips_gprmask &=~ 1 << 0;
726 if (! mips_noreorder)
728 /* Filling the branch delay slot is more complex. We try to
729 switch the branch with the previous instruction, which we can
730 do if the previous instruction does not set up a condition
731 that the branch tests and if the branch is not itself the
732 target of any branch. */
733 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
734 || (pinfo & INSN_COND_BRANCH_DELAY))
736 if (mips_optimize < 2
737 /* If we have seen .set nobopt, don't optimize. */
739 /* If we have seen .set volatile or .set nomove, don't
742 /* If we had to emit any NOP instructions, then we
743 already know we can not swap. */
745 /* If we don't even know the previous insn, we can not
748 /* If the previous insn is already in a branch delay
749 slot, then we can not swap. */
750 || prev_insn_is_delay_slot
751 /* If the previous previous insn was in a .set
752 noreorder, we can't swap. Actually, the MIPS
753 assembler will swap in this situation. However, gcc
754 configured -with-gnu-as will generate code like
760 in which we can not swap the bne and INSN. If gcc is
761 not configured -with-gnu-as, it does not output the
762 .set pseudo-ops. We don't have to check
763 prev_insn_unreordered, because prev_insn_valid will
764 be 0 in that case. We don't want to use
765 prev_prev_insn_valid, because we do want to be able
766 to swap at the start of a function. */
767 || prev_prev_insn_unreordered
768 /* If the branch is itself the target of a branch, we
769 can not swap. We cheat on this; all we check for is
770 whether there is a label on this instruction. If
771 there are any branches to anything other than a
772 label, users must use .set noreorder. */
773 || insn_label != NULL
774 /* If the branch reads the condition codes, we don't
775 even try to swap, because in the sequence
780 we can not swap, and I don't feel like handling that
782 || (pinfo & INSN_READ_COND_CODE)
783 /* We can not swap with an instruction that requires a
784 delay slot, becase the target of the branch might
785 interfere with that instruction. */
787 & (INSN_LOAD_COPROC_DELAY
788 | INSN_COPROC_MOVE_DELAY
789 | INSN_WRITE_COND_CODE
794 & (INSN_LOAD_MEMORY_DELAY
795 | INSN_COPROC_MEMORY_DELAY)))
796 /* We can not swap with a branch instruction. */
798 & (INSN_UNCOND_BRANCH_DELAY
799 | INSN_COND_BRANCH_DELAY
800 | INSN_COND_BRANCH_LIKELY))
801 /* We do not swap with a trap instruction, since it
802 complicates trap handlers to have the trap
803 instruction be in a delay slot. */
804 || (prev_pinfo & INSN_TRAP)
805 /* If the branch reads a register that the previous
806 instruction sets, we can not swap. */
807 || ((prev_pinfo & INSN_WRITE_GPR_T)
808 && insn_uses_reg (ip,
809 ((prev_insn.insn_opcode >> OP_SH_RT)
812 || ((prev_pinfo & INSN_WRITE_GPR_D)
813 && insn_uses_reg (ip,
814 ((prev_insn.insn_opcode >> OP_SH_RD)
817 /* If the branch writes a register that the previous
818 instruction sets, we can not swap (we know that
819 branches write only to RD or to $31). */
820 || ((prev_pinfo & INSN_WRITE_GPR_T)
821 && (((pinfo & INSN_WRITE_GPR_D)
822 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
823 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
824 || ((pinfo & INSN_WRITE_GPR_31)
825 && (((prev_insn.insn_opcode >> OP_SH_RT)
828 || ((prev_pinfo & INSN_WRITE_GPR_D)
829 && (((pinfo & INSN_WRITE_GPR_D)
830 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
831 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
832 || ((pinfo & INSN_WRITE_GPR_31)
833 && (((prev_insn.insn_opcode >> OP_SH_RD)
836 /* If the branch writes a register that the previous
837 instruction reads, we can not swap (we know that
838 branches only write to RD or to $31). */
839 || ((pinfo & INSN_WRITE_GPR_D)
840 && insn_uses_reg (&prev_insn,
841 ((ip->insn_opcode >> OP_SH_RD)
844 || ((pinfo & INSN_WRITE_GPR_31)
845 && insn_uses_reg (&prev_insn, 31, 0))
846 /* If the previous previous instruction has a load
847 delay, and sets a register that the branch reads, we
849 || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
851 && (prev_prev_insn.insn_mo->pinfo
852 & INSN_LOAD_MEMORY_DELAY)))
853 && insn_uses_reg (ip,
854 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
858 /* We could do even better for unconditional branches to
859 portions of this object file; we could pick up the
860 instruction at the destination, put it in the delay
861 slot, and bump the destination address. */
863 /* Update the previous insn information. */
864 prev_prev_insn = *ip;
865 prev_insn.insn_mo = &dummy_opcode;
872 /* It looks like we can actually do the swap. */
873 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
874 memcpy (temp, prev_f, 4);
875 memcpy (prev_f, f, 4);
879 prev_insn_fixp->fx_frag = frag_now;
880 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
884 fixp->fx_frag = prev_insn_frag;
885 fixp->fx_where = prev_insn_where;
887 /* Update the previous insn information; leave prev_insn
889 prev_prev_insn = *ip;
891 prev_insn_is_delay_slot = 1;
893 /* If that was an unconditional branch, forget the previous
895 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
897 prev_prev_insn.insn_mo = &dummy_opcode;
898 prev_insn.insn_mo = &dummy_opcode;
901 else if (pinfo & INSN_COND_BRANCH_LIKELY)
903 /* We don't yet optimize a branch likely. What we should do
904 is look at the target, copy the instruction found there
905 into the delay slot, and increment the branch to jump to
906 the next instruction. */
908 /* Update the previous insn information. */
909 prev_prev_insn = *ip;
910 prev_insn.insn_mo = &dummy_opcode;
914 /* Update the previous insn information. */
916 prev_prev_insn.insn_mo = &dummy_opcode;
918 prev_prev_insn = prev_insn;
921 /* Any time we see a branch, we always fill the delay slot
922 immediately; since this insn is not a branch, we know it
923 is not in a delay slot. */
924 prev_insn_is_delay_slot = 0;
927 prev_prev_insn_unreordered = prev_insn_unreordered;
928 prev_insn_unreordered = 0;
929 prev_insn_frag = frag_now;
930 prev_insn_where = f - frag_now->fr_literal;
931 prev_insn_fixp = fixp;
935 /* We just output an insn, so the next one doesn't have a label. */
939 /* This function forgets that there was any previous instruction or
945 prev_insn.insn_mo = &dummy_opcode;
946 prev_prev_insn.insn_mo = &dummy_opcode;
948 prev_insn_is_delay_slot = 0;
949 prev_insn_unreordered = 0;
950 prev_prev_insn_unreordered = 0;
954 /* This function must be called whenever we turn on noreorder or emit
955 something other than instructions. It inserts any NOPS which might
956 be needed by the previous instruction, and clears the information
957 kept for the previous instructions. */
962 if (! mips_noreorder)
967 if ((prev_insn.insn_mo->pinfo
968 & (INSN_LOAD_COPROC_DELAY
969 | INSN_COPROC_MOVE_DELAY
970 | INSN_WRITE_COND_CODE
974 && (prev_insn.insn_mo->pinfo
975 & (INSN_LOAD_MEMORY_DELAY
976 | INSN_COPROC_MEMORY_DELAY))))
979 if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
980 || (prev_insn.insn_mo->pinfo & INSN_READ_HI)
981 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))
984 else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
985 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
986 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))
991 if (insn_label != NULL)
993 assert (S_GET_SEGMENT (insn_label) == now_seg);
994 insn_label->sy_frag = frag_now;
995 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
998 mips_no_prev_insn ();
1002 /* Return 1 if an expression can be accessed via the GP register. */
1010 const char *symname;
1011 const char *segname;
1013 sym = ep->X_add_symbol;
1014 if (sym == (symbolS *) NULL
1015 || ep->X_op_symbol != (symbolS *) NULL)
1018 /* Certain symbols can not be referenced off the GP, although it
1019 appears as though they can. */
1020 symname = S_GET_NAME (sym);
1021 if (symname != (const char *) NULL
1022 && (strcmp (symname, "eprol") == 0
1023 || strcmp (symname, "etext") == 0
1024 || strcmp (symname, "_gp") == 0
1025 || strcmp (symname, "edata") == 0
1026 || strcmp (symname, "_fbss") == 0
1027 || strcmp (symname, "_fdata") == 0
1028 || strcmp (symname, "_ftext") == 0
1029 || strcmp (symname, "end") == 0))
1031 if (! S_IS_DEFINED (sym)
1032 && S_GET_VALUE (sym) != 0
1033 && S_GET_VALUE (sym) <= g_switch_value)
1035 segname = segment_name (S_GET_SEGMENT (ep->X_add_symbol));
1036 return (strcmp (segname, ".sdata") == 0
1037 || strcmp (segname, ".sbss") == 0
1038 || strcmp (segname, ".lit8") == 0
1039 || strcmp (segname, ".lit4") == 0);
1040 #else /* ! defined (GPOPT) */
1041 /* We are not optimizing for the GP register. */
1043 #endif /* ! defined (GPOPT) */
1046 /* Build an instruction created by a macro expansion. This is passed
1047 a pointer to the count of instructions created so far, an
1048 expression, the name of the instruction to build, an operand format
1049 string, and corresponding arguments. */
1053 macro_build (int *counter,
1058 #else /* ! defined (NO_STDARG) */
1060 macro_build (counter, ep, name, fmt, va_alist)
1066 #endif /* ! defined (NO_STDARG) */
1068 struct mips_cl_insn insn;
1069 bfd_reloc_code_real_type r;
1073 va_start (args, fmt);
1079 * If the macro is about to expand into a second instruction,
1080 * print a warning if needed. We need to pass ip as a parameter
1081 * to generate a better warning message here...
1083 if (mips_warn_about_macros && *counter == 1)
1084 as_warn ("Macro instruction expanded into multiple instructions");
1086 *counter += 1; /* bump instruction counter */
1088 r = BFD_RELOC_UNUSED;
1089 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1090 assert (insn.insn_mo);
1091 assert (strcmp (name, insn.insn_mo->name) == 0);
1093 while (strcmp (fmt, insn.insn_mo->args) != 0)
1096 assert (insn.insn_mo->name);
1097 assert (strcmp (name, insn.insn_mo->name) == 0);
1099 assert (insn.insn_mo->pinfo != INSN_MACRO);
1100 insn.insn_opcode = insn.insn_mo->match;
1116 insn.insn_opcode |= va_arg (args, int) << 16;
1122 insn.insn_opcode |= va_arg (args, int) << 16;
1127 insn.insn_opcode |= va_arg (args, int) << 11;
1132 insn.insn_opcode |= va_arg (args, int) << 11;
1139 insn.insn_opcode |= va_arg (args, int) << 6;
1143 insn.insn_opcode |= va_arg (args, int) << 6;
1147 insn.insn_opcode |= va_arg (args, int) << 6;
1154 insn.insn_opcode |= va_arg (args, int) << 21;
1164 assert (ep != NULL && ep->X_op == O_constant);
1165 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
1170 assert (ep != NULL);
1172 * This allows macro() to pass an immediate expression for
1173 * creating short branches without creating a symbol.
1174 * Note that the expression still might come from the assembly
1175 * input, in which case the value is not checked for range nor
1176 * is a relocation entry generated (yuck).
1178 if (ep->X_op == O_constant)
1180 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
1184 r = BFD_RELOC_16_PCREL_S2;
1193 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1195 /* Use GP relative addressing if possible. */
1196 if (r == BFD_RELOC_LO16
1197 && gp_reference (ep))
1198 r = BFD_RELOC_MIPS_GPREL;
1200 append_insn (&insn, ep, r);
1204 * Generate a "lui" instruction.
1207 macro_build_lui (counter, ep, regnum)
1212 expressionS high_expr;
1213 struct mips_cl_insn insn;
1214 bfd_reloc_code_real_type r;
1215 CONST char *name = "lui";
1216 CONST char *fmt = "t,u";
1220 if (high_expr.X_op == O_constant)
1222 /* we can compute the instruction now without a relocation entry */
1223 if (high_expr.X_add_number & 0x8000)
1224 high_expr.X_add_number += 0x10000;
1225 high_expr.X_add_number =
1226 ((unsigned long) high_expr.X_add_number >> 16) & 0xffff;
1227 r = BFD_RELOC_UNUSED;
1230 r = BFD_RELOC_HI16_S;
1233 * If the macro is about to expand into a second instruction,
1234 * print a warning if needed. We need to pass ip as a parameter
1235 * to generate a better warning message here...
1237 if (mips_warn_about_macros && *counter == 1)
1238 as_warn ("Macro instruction expanded into multiple instructions");
1240 *counter += 1; /* bump instruction counter */
1242 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1243 assert (insn.insn_mo);
1244 assert (strcmp (name, insn.insn_mo->name) == 0);
1245 assert (strcmp (fmt, insn.insn_mo->args) == 0);
1247 insn.insn_opcode = insn.insn_mo->match | (regnum << 16);
1248 if (r == BFD_RELOC_UNUSED)
1250 insn.insn_opcode |= high_expr.X_add_number;
1251 append_insn (&insn, NULL, r);
1254 append_insn (&insn, &high_expr, r);
1258 * Generates code to set the $at register to true (one)
1259 * if reg is less than the immediate expression.
1262 set_at (counter, reg, unsignedp)
1267 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1268 macro_build (counter, &imm_expr,
1269 unsignedp ? "sltiu" : "slti",
1273 load_register (counter, AT, &imm_expr);
1274 macro_build (counter, NULL,
1275 unsignedp ? "sltu" : "slt",
1276 "d,v,t", AT, reg, AT);
1280 /* Warn if an expression is not a constant. */
1283 check_absolute_expr (ip, ex)
1284 struct mips_cl_insn *ip;
1287 if (ex->X_op != O_constant)
1288 as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name);
1292 * This routine generates the least number of instructions neccessary to load
1293 * an absolute expression value into a register.
1296 load_register (counter, reg, ep)
1301 assert (ep->X_op == O_constant);
1302 if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000)
1303 macro_build (counter, ep,
1304 mips_isa < 3 ? "addiu" : "daddiu",
1306 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
1307 macro_build (counter, ep, "ori", "t,r,i", reg, 0);
1308 else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
1309 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
1310 == ~ (offsetT) 0x7fffffff))
1312 macro_build (counter, ep, "lui", "t,u", reg);
1313 if ((ep->X_add_number & 0xffff) != 0)
1314 macro_build (counter, ep, "ori", "t,r,i", reg, reg);
1316 else if (mips_isa < 3)
1318 as_bad ("Number larger than 32 bits");
1319 macro_build (counter, ep, "addiu", "t,r,j", reg, 0);
1324 expressionS hi32, lo32;
1328 hi32.X_add_number >>= shift;
1329 hi32.X_add_number &= 0xffffffff;
1330 if ((hi32.X_add_number & 0x80000000) != 0)
1331 hi32.X_add_number |= ~ (offsetT) 0xffffffff;
1332 load_register (counter, reg, &hi32);
1334 lo32.X_add_number &= 0xffffffff;
1335 if ((lo32.X_add_number & 0xffff0000) == 0)
1336 macro_build (counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
1341 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1343 mid16.X_add_number >>= 16;
1344 macro_build (counter, &mid16, "ori", "t,r,i", reg, reg);
1345 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1347 if ((lo32.X_add_number & 0xffff) != 0)
1348 macro_build (counter, &lo32, "ori", "t,r,i", reg, reg);
1354 * This routine implements the seemingly endless macro or synthesized
1355 * instructions and addressing modes in the mips assembly language. Many
1356 * of these macros are simple and are similar to each other. These could
1357 * probably be handled by some kind of table or grammer aproach instead of
1358 * this verbose method. Others are not simple macros but are more like
1359 * optimizing code generation.
1360 * One interesting optimization is when several store macros appear
1361 * consecutivly that would load AT with the upper half of the same address.
1362 * The ensuing load upper instructions are ommited. This implies some kind
1363 * of global optimization. We currently only optimize within a single macro.
1364 * For many of the load and store macros if the address is specified as a
1365 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1366 * first load register 'at' with zero and use it as the base register. The
1367 * mips assembler simply uses register $zero. Just one tiny optimization
1372 struct mips_cl_insn *ip;
1374 register int treg, sreg, dreg, breg;
1388 treg = (ip->insn_opcode >> 16) & 0x1f;
1389 dreg = (ip->insn_opcode >> 11) & 0x1f;
1390 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
1391 mask = ip->insn_mo->mask;
1393 expr1.X_op = O_constant;
1394 expr1.X_op_symbol = NULL;
1395 expr1.X_add_symbol = NULL;
1396 expr1.X_add_number = 1;
1408 mips_emit_delays ();
1411 expr1.X_add_number = 8;
1412 macro_build (&icnt, &expr1, "bgez", "s,p", sreg);
1414 macro_build (&icnt, NULL, "nop", "", 0);
1416 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg, 0);
1417 macro_build (&icnt, NULL,
1418 dbl ? "dsub" : "sub",
1419 "d,v,t", dreg, 0, sreg);
1442 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1444 macro_build (&icnt, &imm_expr, s, "t,r,j", treg, sreg);
1447 load_register (&icnt, AT, &imm_expr);
1448 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
1467 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
1469 if (mask != M_NOR_I)
1470 macro_build (&icnt, &imm_expr, s, "t,r,i", treg, sreg);
1473 macro_build (&icnt, &imm_expr, "ori", "t,r,i", treg, sreg);
1474 macro_build (&icnt, &imm_expr, "nor", "d,v,t", treg, treg, 0);
1479 load_register (&icnt, AT, &imm_expr);
1480 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
1497 if (imm_expr.X_add_number == 0)
1499 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, 0);
1502 load_register (&icnt, AT, &imm_expr);
1503 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, AT);
1511 macro_build (&icnt, &offset_expr,
1512 likely ? "bgezl" : "bgez",
1518 macro_build (&icnt, &offset_expr,
1519 likely ? "blezl" : "blez",
1523 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
1524 macro_build (&icnt, &offset_expr,
1525 likely ? "beql" : "beq",
1532 /* check for > max integer */
1533 maxnum = 0x7fffffff;
1541 if (imm_expr.X_add_number >= maxnum)
1544 /* result is always false */
1547 as_warn ("Branch %s is always false (nop)", ip->insn_mo->name);
1548 macro_build (&icnt, NULL, "nop", "", 0);
1552 as_warn ("Branch likely %s is always false", ip->insn_mo->name);
1553 macro_build (&icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
1557 imm_expr.X_add_number++;
1561 if (mask == M_BGEL_I)
1563 if (imm_expr.X_add_number == 0)
1565 macro_build (&icnt, &offset_expr,
1566 likely ? "bgezl" : "bgez",
1570 if (imm_expr.X_add_number == 1)
1572 macro_build (&icnt, &offset_expr,
1573 likely ? "bgtzl" : "bgtz",
1577 maxnum = 0x7fffffff;
1585 maxnum = - maxnum - 1;
1586 if (imm_expr.X_add_number <= maxnum)
1589 /* result is always true */
1590 as_warn ("Branch %s is always true", ip->insn_mo->name);
1591 macro_build (&icnt, &offset_expr, "b", "p");
1594 set_at (&icnt, sreg, 0);
1595 macro_build (&icnt, &offset_expr,
1596 likely ? "beql" : "beq",
1607 macro_build (&icnt, &offset_expr,
1608 likely ? "beql" : "beq",
1612 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
1613 macro_build (&icnt, &offset_expr,
1614 likely ? "beql" : "beq",
1621 if (sreg == 0 || imm_expr.X_add_number == -1)
1623 imm_expr.X_add_number++;
1627 if (mask == M_BGEUL_I)
1629 if (imm_expr.X_add_number == 0)
1631 if (imm_expr.X_add_number == 1)
1633 macro_build (&icnt, &offset_expr,
1634 likely ? "bnel" : "bne",
1638 set_at (&icnt, sreg, 1);
1639 macro_build (&icnt, &offset_expr,
1640 likely ? "beql" : "beq",
1649 macro_build (&icnt, &offset_expr,
1650 likely ? "bgtzl" : "bgtz",
1656 macro_build (&icnt, &offset_expr,
1657 likely ? "bltzl" : "bltz",
1661 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
1662 macro_build (&icnt, &offset_expr,
1663 likely ? "bnel" : "bne",
1672 macro_build (&icnt, &offset_expr,
1673 likely ? "bnel" : "bne",
1679 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
1680 macro_build (&icnt, &offset_expr,
1681 likely ? "bnel" : "bne",
1690 macro_build (&icnt, &offset_expr,
1691 likely ? "blezl" : "blez",
1697 macro_build (&icnt, &offset_expr,
1698 likely ? "bgezl" : "bgez",
1702 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
1703 macro_build (&icnt, &offset_expr,
1704 likely ? "beql" : "beq",
1711 maxnum = 0x7fffffff;
1719 if (imm_expr.X_add_number >= maxnum)
1721 imm_expr.X_add_number++;
1725 if (mask == M_BLTL_I)
1727 if (imm_expr.X_add_number == 0)
1729 macro_build (&icnt, &offset_expr,
1730 likely ? "bltzl" : "bltz",
1734 if (imm_expr.X_add_number == 1)
1736 macro_build (&icnt, &offset_expr,
1737 likely ? "blezl" : "blez",
1741 set_at (&icnt, sreg, 0);
1742 macro_build (&icnt, &offset_expr,
1743 likely ? "bnel" : "bne",
1752 macro_build (&icnt, &offset_expr,
1753 likely ? "beql" : "beq",
1759 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
1760 macro_build (&icnt, &offset_expr,
1761 likely ? "beql" : "beq",
1768 if (sreg == 0 || imm_expr.X_add_number == -1)
1770 imm_expr.X_add_number++;
1774 if (mask == M_BLTUL_I)
1776 if (imm_expr.X_add_number == 0)
1778 if (imm_expr.X_add_number == 1)
1780 macro_build (&icnt, &offset_expr,
1781 likely ? "beql" : "beq",
1785 set_at (&icnt, sreg, 1);
1786 macro_build (&icnt, &offset_expr,
1787 likely ? "bnel" : "bne",
1796 macro_build (&icnt, &offset_expr,
1797 likely ? "bltzl" : "bltz",
1803 macro_build (&icnt, &offset_expr,
1804 likely ? "bgtzl" : "bgtz",
1808 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
1809 macro_build (&icnt, &offset_expr,
1810 likely ? "bnel" : "bne",
1821 macro_build (&icnt, &offset_expr,
1822 likely ? "bnel" : "bne",
1826 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
1827 macro_build (&icnt, &offset_expr,
1828 likely ? "bnel" : "bne",
1844 as_warn ("Divide by zero.");
1845 macro_build (&icnt, NULL, "break", "c", 7);
1849 mips_emit_delays ();
1851 macro_build (&icnt, NULL,
1852 dbl ? "ddiv" : "div",
1853 "z,s,t", sreg, treg);
1854 expr1.X_add_number = 8;
1855 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
1856 macro_build (&icnt, NULL, "nop", "", 0);
1857 macro_build (&icnt, NULL, "break", "c", 7);
1858 expr1.X_add_number = -1;
1859 macro_build (&icnt, &expr1,
1860 dbl ? "daddiu" : "addiu",
1862 expr1.X_add_number = dbl ? 20 : 16;
1863 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, AT);
1866 expr1.X_add_number = 1;
1867 macro_build (&icnt, &expr1, "daddiu", "t,r,j", AT, 0);
1868 macro_build (&icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
1872 expr1.X_add_number = 0x80000000;
1873 macro_build (&icnt, &expr1, "lui", "t,u", AT);
1875 expr1.X_add_number = 8;
1876 macro_build (&icnt, &expr1, "bne", "s,t,p", sreg, AT);
1877 macro_build (&icnt, NULL, "nop", "", 0);
1878 macro_build (&icnt, NULL, "break", "c", 6);
1880 macro_build (&icnt, NULL, s, "d", dreg);
1919 if (imm_expr.X_add_number == 0)
1921 as_warn ("Divide by zero.");
1922 macro_build (&icnt, NULL, "break", "c", 7);
1925 if (imm_expr.X_add_number == 1)
1927 if (strcmp (s2, "mflo") == 0)
1928 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg);
1930 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
1933 if (imm_expr.X_add_number == -1
1934 && s[strlen (s) - 1] != 'u')
1936 if (strcmp (s2, "mflo") == 0)
1939 macro_build (&icnt, NULL, "dneg", "d,w", dreg, sreg);
1941 macro_build (&icnt, NULL, "neg", "d,w", dreg, sreg);
1944 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
1948 load_register (&icnt, AT, &imm_expr);
1949 macro_build (&icnt, NULL, s, "z,s,t", sreg, AT);
1950 macro_build (&icnt, NULL, s2, "d", dreg);
1969 mips_emit_delays ();
1971 macro_build (&icnt, NULL, s, "z,s,t", sreg, treg);
1972 expr1.X_add_number = 8;
1973 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
1974 macro_build (&icnt, NULL, "nop", "", 0);
1975 macro_build (&icnt, NULL, "break", "c", 7);
1977 macro_build (&icnt, NULL, s2, "d", dreg);
1981 if (offset_expr.X_op == O_constant)
1983 load_register (&icnt, treg, &offset_expr);
1986 if (gp_reference (&offset_expr))
1987 macro_build (&icnt, &offset_expr,
1988 mips_isa < 3 ? "addiu" : "daddiu",
1992 /* FIXME: This won't work for a 64 bit address. */
1993 macro_build_lui (&icnt, &offset_expr, treg);
1994 macro_build (&icnt, &offset_expr,
1995 mips_isa < 3 ? "addiu" : "daddiu",
1996 "t,r,j", treg, treg);
2001 tempreg = (breg == treg) ? AT : treg;
2002 if (offset_expr.X_op == O_constant)
2003 load_register (&icnt, tempreg, &offset_expr);
2004 else if (gp_reference (&offset_expr))
2005 macro_build (&icnt, &offset_expr,
2006 mips_isa < 3 ? "addiu" : "daddiu",
2007 "t,r,j", tempreg, GP);
2010 /* FIXME: This won't work for a 64 bit address. */
2011 macro_build_lui (&icnt, &offset_expr, tempreg);
2012 macro_build (&icnt, &offset_expr,
2013 mips_isa < 3 ? "addiu" : "daddiu",
2014 "t,r,j", tempreg, tempreg);
2017 macro_build (&icnt, NULL, "addu", "d,v,t", treg, tempreg, breg);
2087 if (breg == treg || coproc)
2156 if (mask == M_LWC1_AB
2157 || mask == M_SWC1_AB
2159 || mask == M_LDC1_AB
2160 || mask == M_SDC1_AB)
2166 if (gp_reference (&offset_expr))
2170 macro_build (&icnt, &offset_expr, s, fmt, treg, GP);
2173 macro_build (&icnt, (expressionS *) NULL,
2174 mips_isa < 3 ? "addu" : "daddu",
2175 "d,v,t", tempreg, breg, GP);
2179 /* FIXME: This won't work for a 64 bit address. */
2180 macro_build_lui (&icnt, &offset_expr, tempreg);
2182 macro_build (&icnt, NULL,
2183 mips_isa < 3 ? "addu" : "daddu",
2184 "d,v,t", tempreg, tempreg, breg);
2186 macro_build (&icnt, &offset_expr, s, fmt, treg, tempreg);
2193 load_register (&icnt, treg, &imm_expr);
2198 lw $v0,%lo(foo)($at)
2199 lw $v1,%lo(foo+4)($at)
2204 /* FIXME: This won't work for a 64 bit address. */
2205 macro_build_lui (&icnt, &offset_expr, AT);
2207 macro_build (&icnt, &offset_expr, "ld", "t,o(b)", treg, AT);
2210 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg, AT);
2211 offset_expr.X_add_number += 4;
2212 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg + 1, AT);
2217 /* Load a floating point number from the .lit8 section. */
2220 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, GP);
2226 /* Even on a big endian machine $fn comes before $fn+1. We have
2227 to adjust when loading from memory. */
2228 assert (mips_isa < 2);
2229 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2230 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2232 offset_expr.X_add_number += 4;
2233 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2234 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2240 * The MIPS assembler seems to check for X_add_number not
2241 * being double aligned and generating:
2244 * addiu at,at,%lo(foo+1)
2247 * But, the resulting address is the same after relocation so why
2248 * generate the extra instruction?
2250 if (gp_reference (&offset_expr))
2256 macro_build (&icnt, &offset_expr,
2257 mips_isa < 3 ? "addu" : "daddu",
2258 "d,v,t", AT, breg, GP);
2264 /* FIXME: This won't work for a 64 bit address. */
2265 macro_build_lui (&icnt, &offset_expr, AT);
2267 macro_build (&icnt, NULL,
2268 mips_isa < 3 ? "addu" : "daddu",
2269 "d,v,t", AT, AT, breg);
2273 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, tempreg);
2276 /* Even on a big endian machine $fn comes before $fn+1. We
2277 have to adjust when loading from memory. */
2278 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2279 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2281 offset_expr.X_add_number += 4;
2282 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2283 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2296 assert (mips_isa < 3);
2297 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
2298 offset_expr.X_add_number += 4;
2299 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, breg);
2322 if (gp_reference (&offset_expr))
2330 macro_build (&icnt, (expressionS *) NULL,
2331 mips_isa < 3 ? "addu" : "daddu",
2332 "d,v,t", tempreg, breg, GP);
2336 /* FIXME: This won't work for a 64 bit address. */
2337 macro_build_lui (&icnt, &offset_expr, tempreg);
2339 macro_build (&icnt, NULL,
2340 mips_isa < 3 ? "addu" : "daddu",
2341 "d,v,t", tempreg, tempreg, breg);
2344 macro_build (&icnt, &offset_expr, s2, "t,o(b)", treg, tempreg);
2347 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, tempreg);
2348 offset_expr.X_add_number += 4;
2349 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, tempreg);
2358 macro_build (&icnt, NULL,
2359 dbl ? "dmultu" : "multu",
2361 macro_build (&icnt, NULL, "mflo", "d", dreg);
2367 /* The MIPS assembler some times generates shifts and adds. I'm
2368 not trying to be that fancy. GCC should do this for us
2370 load_register (&icnt, AT, &imm_expr);
2371 macro_build (&icnt, NULL,
2372 dbl ? "dmult" : "mult",
2374 macro_build (&icnt, NULL, "mflo", "d", dreg);
2380 mips_emit_delays ();
2382 macro_build (&icnt, NULL,
2383 dbl ? "dmult" : "mult",
2385 macro_build (&icnt, NULL, "mflo", "d", dreg);
2386 macro_build (&icnt, NULL,
2387 dbl ? "dsra32" : "sra",
2388 "d,w,<", dreg, dreg, 31);
2389 macro_build (&icnt, NULL, "mfhi", "d", AT);
2390 expr1.X_add_number = 8;
2391 macro_build (&icnt, &expr1, "beq", "s,t,p", dreg, AT);
2392 macro_build (&icnt, NULL, "nop", "", 0);
2393 macro_build (&icnt, NULL, "break", "c", 6);
2395 macro_build (&icnt, NULL, "mflo", "d", dreg);
2401 mips_emit_delays ();
2403 macro_build (&icnt, NULL,
2404 dbl ? "dmultu" : "multu",
2406 macro_build (&icnt, NULL, "mfhi", "d", AT);
2407 macro_build (&icnt, NULL, "mflo", "d", dreg);
2408 expr1.X_add_number = 8;
2409 macro_build (&icnt, &expr1, "beq", "s,t,p", AT, 0);
2410 macro_build (&icnt, NULL, "nop", "", 0);
2411 macro_build (&icnt, NULL, "break", "c", 6);
2416 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2417 macro_build (&icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
2418 macro_build (&icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
2419 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2423 macro_build (&icnt, NULL, "sll", "d,w,<", AT, sreg,
2424 imm_expr.X_add_number & 0x1f);
2425 macro_build (&icnt, NULL, "srl", "d,w,<", dreg, sreg,
2426 (0 - imm_expr.X_add_number) & 0x1f);
2427 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2431 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2432 macro_build (&icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
2433 macro_build (&icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
2434 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2438 macro_build (&icnt, NULL, "srl", "d,w,<", AT, sreg,
2439 imm_expr.X_add_number & 0x1f);
2440 macro_build (&icnt, NULL, "sll", "d,w,<", dreg, sreg,
2441 (0 - imm_expr.X_add_number) & 0x1f);
2442 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2446 assert (mips_isa < 2);
2447 /* Even on a big endian machine $fn comes before $fn+1. We have
2448 to adjust when storing to memory. */
2449 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2450 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2452 offset_expr.X_add_number += 4;
2453 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2454 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2459 if (gp_reference (&offset_expr))
2465 macro_build (&icnt, (expressionS *) NULL,
2466 mips_isa < 3 ? "addu" : "daddu",
2467 "d,v,t", AT, breg, GP);
2473 /* FIXME: This won't work for a 64 bit address. */
2474 macro_build_lui (&icnt, &offset_expr, AT);
2476 macro_build (&icnt, NULL,
2477 mips_isa < 3 ? "addu" : "daddu",
2478 "d,v,t", AT, AT, breg);
2482 macro_build (&icnt, &offset_expr, "sdc1", "T,o(b)", treg, tempreg);
2485 /* Even on a big endian machine $fn comes before $fn+1. We
2486 have to adjust when storing to memory. */
2487 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2488 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2490 offset_expr.X_add_number += 4;
2491 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2492 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2501 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, treg);
2503 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2506 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2507 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
2512 if (imm_expr.X_add_number == 0)
2514 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2519 as_warn ("Instruction %s: result is always false",
2521 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
2524 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
2526 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2529 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2531 imm_expr.X_add_number = -imm_expr.X_add_number;
2532 macro_build (&icnt, &imm_expr,
2533 mips_isa < 3 ? "addiu" : "daddiu",
2534 "t,r,j", dreg, sreg);
2539 load_register (&icnt, AT, &imm_expr);
2540 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2543 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
2548 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
2554 macro_build (&icnt, NULL, s, "d,v,t", dreg, sreg, treg);
2555 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2558 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
2560 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
2562 macro_build (&icnt, &expr1,
2563 mask == M_SGE_I ? "slti" : "sltiu",
2564 "t,r,j", dreg, sreg);
2569 load_register (&icnt, AT, &imm_expr);
2570 macro_build (&icnt, NULL,
2571 mask == M_SGE_I ? "slt" : "sltu",
2572 "d,v,t", dreg, sreg, AT);
2575 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2580 case M_SGT: /* sreg > treg <==> treg < sreg */
2586 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
2589 case M_SGT_I: /* sreg > I <==> I < sreg */
2595 load_register (&icnt, AT, &imm_expr);
2596 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
2599 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2605 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
2606 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2609 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2615 load_register (&icnt, AT, &imm_expr);
2616 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
2617 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2621 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
2623 macro_build (&icnt, &imm_expr, "slti", "t,r,j", dreg, sreg);
2626 load_register (&icnt, AT, &imm_expr);
2627 macro_build (&icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
2631 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
2633 macro_build (&icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg);
2636 load_register (&icnt, AT, &imm_expr);
2637 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
2642 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, treg);
2644 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2647 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2648 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
2653 if (imm_expr.X_add_number == 0)
2655 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2660 as_warn ("Instruction %s: result is always true",
2662 macro_build (&icnt, &expr1,
2663 mips_isa < 3 ? "addiu" : "daddiu",
2667 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
2669 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2672 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2674 imm_expr.X_add_number = -imm_expr.X_add_number;
2675 macro_build (&icnt, &imm_expr,
2676 mips_isa < 3 ? "addiu" : "daddiu",
2677 "t,r,j", dreg, sreg);
2682 load_register (&icnt, AT, &imm_expr);
2683 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2686 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
2694 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
2696 imm_expr.X_add_number = -imm_expr.X_add_number;
2697 macro_build (&icnt, &imm_expr,
2698 dbl ? "daddi" : "addi",
2699 "t,r,j", dreg, sreg);
2702 load_register (&icnt, AT, &imm_expr);
2703 macro_build (&icnt, NULL,
2704 dbl ? "dsub" : "sub",
2705 "d,v,t", dreg, sreg, AT);
2711 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
2713 imm_expr.X_add_number = -imm_expr.X_add_number;
2714 macro_build (&icnt, &imm_expr,
2715 dbl ? "daddiu" : "addiu",
2716 "t,r,j", dreg, sreg);
2719 load_register (&icnt, AT, &imm_expr);
2720 macro_build (&icnt, NULL,
2721 dbl ? "dsubu" : "subu",
2722 "d,v,t", dreg, sreg, AT);
2743 load_register (&icnt, AT, &imm_expr);
2744 macro_build (&icnt, NULL, s, "s,t", sreg, AT);
2749 assert (mips_isa < 2);
2750 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
2751 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
2754 * Is the double cfc1 instruction a bug in the mips assembler;
2755 * or is there a reason for it?
2757 mips_emit_delays ();
2759 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
2760 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
2761 macro_build (&icnt, NULL, "nop", "");
2762 expr1.X_add_number = 3;
2763 macro_build (&icnt, &expr1, "ori", "t,r,i", AT, treg);
2764 expr1.X_add_number = 2;
2765 macro_build (&icnt, &expr1, "xori", "t,r,i", AT, AT);
2766 macro_build (&icnt, NULL, "ctc1", "t,G", AT, 31);
2767 macro_build (&icnt, NULL, "nop", "");
2768 macro_build (&icnt, NULL,
2769 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
2770 macro_build (&icnt, NULL, "ctc1", "t,G", treg, 31);
2771 macro_build (&icnt, NULL, "nop", "");
2781 /* avoid load delay */
2782 offset_expr.X_add_number += 1;
2783 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
2784 offset_expr.X_add_number -= 1;
2785 macro_build (&icnt, &offset_expr, "lbu", "t,o(b)", AT, breg);
2786 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2787 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2791 /* does this work on a big endian machine? */
2792 offset_expr.X_add_number += 3;
2793 macro_build (&icnt, &offset_expr, "lwl", "t,o(b)", treg, breg);
2794 offset_expr.X_add_number -= 3;
2795 macro_build (&icnt, &offset_expr, "lwr", "t,o(b)", treg, breg);
2801 if (offset_expr.X_op == O_constant)
2802 load_register (&icnt, AT, &offset_expr);
2803 else if (gp_reference (&offset_expr))
2804 macro_build (&icnt, &offset_expr,
2805 mips_isa < 3 ? "addiu" : "daddiu",
2809 /* FIXME: This won't work for a 64 bit address. */
2810 macro_build_lui (&icnt, &offset_expr, AT);
2811 macro_build (&icnt, &offset_expr,
2812 mips_isa < 3 ? "addiu" : "daddiu",
2815 if (mask == M_ULW_A)
2817 expr1.X_add_number = 3;
2818 macro_build (&icnt, &expr1, "lwl", "t,o(b)", treg, AT);
2819 imm_expr.X_add_number = 0;
2820 macro_build (&icnt, &expr1, "lwr", "t,o(b)", treg, AT);
2824 macro_build (&icnt, &expr1,
2825 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, AT);
2826 imm_expr.X_add_number = 0;
2827 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2828 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2829 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2834 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", treg, breg);
2835 macro_build (&icnt, NULL, "srl", "d,w,<", AT, treg, 8);
2836 offset_expr.X_add_number += 1;
2837 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", AT, breg);
2841 offset_expr.X_add_number += 3;
2842 macro_build (&icnt, &offset_expr, "swl", "t,o(b)", treg, breg);
2843 offset_expr.X_add_number -= 3;
2844 macro_build (&icnt, &offset_expr, "swr", "t,o(b)", treg, breg);
2849 if (offset_expr.X_op == O_constant)
2850 load_register (&icnt, AT, &offset_expr);
2851 else if (gp_reference (&offset_expr))
2852 macro_build (&icnt, &offset_expr,
2853 mips_isa < 3 ? "addiu" : "daddiu",
2857 /* FIXME: This won't work for a 64 bit address. */
2858 macro_build_lui (&icnt, &offset_expr, AT);
2859 macro_build (&icnt, &offset_expr,
2860 mips_isa < 3 ? "addiu" : "daddiu",
2863 if (mask == M_USW_A)
2865 expr1.X_add_number = 3;
2866 macro_build (&icnt, &expr1, "swl", "t,o(b)", treg, AT);
2867 expr1.X_add_number = 0;
2868 macro_build (&icnt, &expr1, "swr", "t,o(b)", treg, AT);
2872 expr1.X_add_number = 0;
2873 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2874 macro_build (&icnt, NULL, "srl", "d,w,<", treg, treg, 8);
2875 expr1.X_add_number = 1;
2876 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2877 expr1.X_add_number = 0;
2878 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2879 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2880 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2885 as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
2889 as_warn ("Macro used $at after \".set noat\"");
2894 This routine assembles an instruction into its binary format. As a side
2895 effect it sets one of the global variables imm_reloc or offset_reloc to the
2896 type of relocation to do if one of the operands is an address expression.
2901 struct mips_cl_insn *ip;
2906 struct mips_opcode *insn;
2909 unsigned int lastregno = 0;
2914 for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s)
2926 as_warn ("Unknown opcode: `%s'", str);
2929 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
2931 as_warn ("`%s' not in hash table.", str);
2932 insn_error = "ERROR: Unrecognized opcode";
2940 assert (strcmp (insn->name, str) == 0);
2942 if (insn->pinfo == INSN_MACRO)
2943 insn_isa = insn->match;
2944 else if (insn->pinfo & INSN_ISA2)
2946 else if (insn->pinfo & INSN_ISA3)
2951 if (insn_isa > mips_isa)
2953 if (insn + 1 < &mips_opcodes[NUMOPCODES]
2954 && strcmp (insn->name, insn[1].name) == 0)
2959 insn_error = "ERROR: instruction not supported on this processor";
2964 ip->insn_opcode = insn->match;
2965 for (args = insn->args;; ++args)
2971 case '\0': /* end of args */
2984 ip->insn_opcode |= lastregno << 21;
2989 ip->insn_opcode |= lastregno << 16;
2993 ip->insn_opcode |= lastregno << 11;
2999 /* handle optional base register.
3000 Either the base register is omitted or
3001 we must have a left paren. */
3002 /* this is dependent on the next operand specifier
3003 is a 'b' for base register */
3004 assert (args[1] == 'b');
3008 case ')': /* these must match exactly */
3013 case '<': /* must be at least one digit */
3015 * According to the manual, if the shift amount is greater
3016 * than 31 or less than 0 the the shift amount should be
3017 * mod 32. In reality the mips assembler issues an error.
3018 * We issue a warning and do the mod.
3020 my_getExpression (&imm_expr, s);
3021 check_absolute_expr (ip, &imm_expr);
3022 if ((unsigned long) imm_expr.X_add_number > 31)
3024 as_warn ("Improper shift amount (%ld)",
3025 (long) imm_expr.X_add_number);
3026 imm_expr.X_add_number = imm_expr.X_add_number % 32;
3028 ip->insn_opcode |= imm_expr.X_add_number << 6;
3029 imm_expr.X_op = O_absent;
3033 case 'c': /* break code */
3034 my_getExpression (&imm_expr, s);
3035 check_absolute_expr (ip, &imm_expr);
3036 if ((unsigned) imm_expr.X_add_number > 1023)
3037 as_warn ("Illegal break code (%ld)",
3038 (long) imm_expr.X_add_number);
3039 ip->insn_opcode |= imm_expr.X_add_number << 16;
3040 imm_expr.X_op = O_absent;
3044 case 'B': /* syscall code */
3045 my_getExpression (&imm_expr, s);
3046 check_absolute_expr (ip, &imm_expr);
3047 if ((unsigned) imm_expr.X_add_number > 0xfffff)
3048 as_warn ("Illegal syscall code (%ld)",
3049 (long) imm_expr.X_add_number);
3050 ip->insn_opcode |= imm_expr.X_add_number << 6;
3051 imm_expr.X_op = O_absent;
3055 case 'C': /* Coprocessor code */
3056 my_getExpression (&imm_expr, s);
3057 check_absolute_expr (ip, &imm_expr);
3058 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
3060 as_warn ("Coproccesor code > 25 bits (%ld)",
3061 (long) imm_expr.X_add_number);
3062 imm_expr.X_add_number &= ((1<<25) - 1);
3064 ip->insn_opcode |= imm_expr.X_add_number;
3065 imm_expr.X_op = O_absent;
3069 case 'b': /* base register */
3070 case 'd': /* destination register */
3071 case 's': /* source register */
3072 case 't': /* target register */
3073 case 'r': /* both target and source */
3074 case 'v': /* both dest and source */
3075 case 'w': /* both dest and target */
3076 case 'E': /* coprocessor target register */
3077 case 'G': /* coprocessor destination register */
3078 case 'x': /* ignore register name */
3079 case 'z': /* must be zero register */
3093 while (isdigit (*s));
3095 as_bad ("Invalid register number (%d)", regno);
3097 else if (*args != 'E' && *args != 'G')
3099 if (s[1] == 'f' && s[2] == 'p')
3104 else if (s[1] == 's' && s[2] == 'p')
3109 else if (s[1] == 'g' && s[2] == 'p')
3114 else if (s[1] == 'a' && s[2] == 't')
3121 if (regno == AT && ! mips_noat)
3122 as_warn ("Used $at without \".set noat\"");
3129 if (c == 'r' || c == 'v' || c == 'w')
3136 /* 'z' only matches $0. */
3137 if (c == 'z' && regno != 0)
3145 ip->insn_opcode |= regno << 21;
3149 ip->insn_opcode |= regno << 11;
3154 ip->insn_opcode |= regno << 16;
3157 /* This case exists because on the r3000 trunc
3158 expands into a macro which requires a gp
3159 register. On the r6000 or r4000 it is
3160 assembled into a single instruction which
3161 ignores the register. Thus the insn version
3162 is MIPS_ISA2 and uses 'x', and the macro
3163 version is MIPS_ISA1 and uses 't'. */
3166 /* This case is for the div instruction, which
3167 acts differently if the destination argument
3168 is $0. This only matches $0, and is checked
3169 outside the switch. */
3180 ip->insn_opcode |= lastregno << 21;
3183 ip->insn_opcode |= lastregno << 16;
3188 case 'D': /* floating point destination register */
3189 case 'S': /* floating point source register */
3190 case 'T': /* floating point target register */
3194 if (s[0] == '$' && s[1] == 'f' && isdigit (s[2]))
3204 while (isdigit (*s));
3207 as_bad ("Invalid float register number (%d)", regno);
3210 !(strcmp (str, "mtc1") == 0 ||
3211 strcmp (str, "mfc1") == 0 ||
3212 strcmp (str, "lwc1") == 0 ||
3213 strcmp (str, "swc1") == 0))
3214 as_warn ("Float register should be even, was %d",
3222 if (c == 'V' || c == 'W')
3232 ip->insn_opcode |= regno << 6;
3236 ip->insn_opcode |= regno << 11;
3240 ip->insn_opcode |= regno << 16;
3248 ip->insn_opcode |= lastregno << 11;
3251 ip->insn_opcode |= lastregno << 16;
3257 my_getExpression (&imm_expr, s);
3258 check_absolute_expr (ip, &imm_expr);
3263 my_getExpression (&offset_expr, s);
3264 imm_reloc = BFD_RELOC_32;
3276 unsigned char temp[8];
3278 unsigned int length;
3283 /* These only appear as the last operand in an
3284 instruction, and every instruction that accepts
3285 them in any variant accepts them in all variants.
3286 This means we don't have to worry about backing out
3287 any changes if the instruction does not match.
3289 The difference between them is the size of the
3290 floating point constant and where it goes. For 'F'
3291 and 'L' the constant is 64 bits; for 'f' and 'l' it
3292 is 32 bits. Where the constant is placed is based
3293 on how the MIPS assembler does things:
3296 f -- immediate value
3300 f64 = *args == 'F' || *args == 'L';
3302 save_in = input_line_pointer;
3303 input_line_pointer = s;
3304 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
3306 s = input_line_pointer;
3307 input_line_pointer = save_in;
3308 if (err != NULL && *err != '\0')
3310 as_bad ("Bad floating point constant: %s", err);
3311 memset (temp, '\0', sizeof temp);
3312 length = f64 ? 8 : 4;
3315 assert (length == (f64 ? 8 : 4));
3319 imm_expr.X_op = O_constant;
3320 if (byte_order == LITTLE_ENDIAN)
3321 imm_expr.X_add_number =
3322 (((((((int) temp[3] << 8)
3327 imm_expr.X_add_number =
3328 (((((((int) temp[0] << 8)
3335 /* Switch to the right section. */
3337 subseg = now_subseg;
3341 subseg_new (".rdata", (subsegT) 0);
3344 subseg_new (".lit8", (subsegT) 0);
3347 subseg_new (".lit4", (subsegT) 0);
3351 as_bad ("Can't use floating point insn in this section");
3353 /* Set the argument to the current address in the
3355 offset_expr.X_op = O_symbol;
3356 offset_expr.X_add_symbol =
3357 symbol_new ("L0\001", now_seg,
3358 (valueT) frag_now_fix (), frag_now);
3359 offset_expr.X_add_number = 0;
3361 /* Put the floating point number into the section. */
3362 p = frag_more ((int) length);
3363 memcpy (p, temp, length);
3365 /* Switch back to the original section. */
3366 subseg_set (seg, subseg);
3371 case 'i': /* 16 bit unsigned immediate */
3372 case 'j': /* 16 bit signed immediate */
3373 imm_reloc = BFD_RELOC_LO16;
3374 c = my_getSmallExpression (&imm_expr, s);
3379 if (imm_expr.X_op == O_constant)
3380 imm_expr.X_add_number =
3381 (imm_expr.X_add_number >> 16) & 0xffff;
3383 imm_reloc = BFD_RELOC_HI16_S;
3385 imm_reloc = BFD_RELOC_HI16;
3389 check_absolute_expr (ip, &imm_expr);
3392 if (imm_expr.X_add_number < 0
3393 || imm_expr.X_add_number >= 0x10000)
3395 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3396 !strcmp (insn->name, insn[1].name))
3398 as_bad ("16 bit expression not in range 0..65535");
3403 if (imm_expr.X_add_number < -0x8000 ||
3404 imm_expr.X_add_number >= 0x8000)
3406 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3407 !strcmp (insn->name, insn[1].name))
3409 as_bad ("16 bit expression not in range -32768..32767");
3415 case 'o': /* 16 bit offset */
3416 c = my_getSmallExpression (&offset_expr, s);
3418 * If this value won't fit into a 16 bit offset, then
3419 * go find a macro that will generate the 32 bit offset
3422 if (offset_expr.X_op != O_constant
3423 || offset_expr.X_add_number >= 0x8000
3424 || offset_expr.X_add_number < -0x8000)
3427 offset_reloc = BFD_RELOC_LO16;
3428 if (c == 'h' || c == 'H')
3430 assert (offset_expr.X_op == O_constant);
3431 offset_expr.X_add_number =
3432 (offset_expr.X_add_number >> 16) & 0xffff;
3437 case 'p': /* pc relative offset */
3438 offset_reloc = BFD_RELOC_16_PCREL_S2;
3439 my_getExpression (&offset_expr, s);
3443 case 'u': /* upper 16 bits */
3444 c = my_getSmallExpression (&imm_expr, s);
3445 if (imm_expr.X_op != O_constant
3446 || imm_expr.X_add_number < 0
3447 || imm_expr.X_add_number >= 0x10000)
3448 as_bad ("lui expression not in range 0..65535");
3449 imm_reloc = BFD_RELOC_LO16;
3454 if (imm_expr.X_op == O_constant)
3455 imm_expr.X_add_number =
3456 (imm_expr.X_add_number >> 16) & 0xffff;
3458 imm_reloc = BFD_RELOC_HI16_S;
3460 imm_reloc = BFD_RELOC_HI16;
3466 case 'a': /* 26 bit address */
3467 my_getExpression (&offset_expr, s);
3469 offset_reloc = BFD_RELOC_MIPS_JMP;
3473 fprintf (stderr, "bad char = '%c'\n", *args);
3478 /* Args don't match. */
3479 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3480 !strcmp (insn->name, insn[1].name))
3486 insn_error = "ERROR: Illegal operands";
3495 my_getSmallExpression (ep, str)
3506 ((str[1] == 'h' && str[2] == 'i')
3507 || (str[1] == 'H' && str[2] == 'I')
3508 || (str[1] == 'l' && str[2] == 'o'))
3520 * A small expression may be followed by a base register.
3521 * Scan to the end of this operand, and then back over a possible
3522 * base register. Then scan the small expression up to that
3523 * point. (Based on code in sparc.c...)
3525 for (sp = str; *sp && *sp != ','; sp++)
3527 if (sp - 4 >= str && sp[-1] == RP)
3529 if (isdigit (sp[-2]))
3531 for (sp -= 3; sp >= str && isdigit (*sp); sp--)
3533 if (*sp == '$' && sp > str && sp[-1] == LP)
3539 else if (sp - 5 >= str
3542 && ((sp[-3] == 'f' && sp[-2] == 'p')
3543 || (sp[-3] == 's' && sp[-2] == 'p')
3544 || (sp[-3] == 'g' && sp[-2] == 'p')
3545 || (sp[-3] == 'a' && sp[-2] == 't')))
3551 /* no expression means zero offset */
3554 /* %xx(reg) is an error */
3555 ep->X_op = O_absent;
3560 ep->X_op = O_absent;
3563 ep->X_add_symbol = NULL;
3564 ep->X_op_symbol = NULL;
3565 ep->X_add_number = 0;
3570 my_getExpression (ep, str);
3577 my_getExpression (ep, str);
3578 return c; /* => %hi or %lo encountered */
3582 my_getExpression (ep, str)
3588 save_in = input_line_pointer;
3589 input_line_pointer = str;
3591 expr_end = input_line_pointer;
3592 input_line_pointer = save_in;
3595 /* Turn a string in input_line_pointer into a floating point constant
3596 of type type, and store the appropriate bytes in *litP. The number
3597 of LITTLENUMS emitted is stored in *sizeP . An error message is
3598 returned, or NULL on OK. */
3601 md_atof (type, litP, sizeP)
3607 LITTLENUM_TYPE words[4];
3623 return "bad call to md_atof";
3626 t = atof_ieee (input_line_pointer, type, words);
3628 input_line_pointer = t;
3632 if (byte_order == LITTLE_ENDIAN)
3634 for (i = prec - 1; i >= 0; i--)
3636 md_number_to_chars (litP, (valueT) words[i], 2);
3642 for (i = 0; i < prec; i++)
3644 md_number_to_chars (litP, (valueT) words[i], 2);
3653 md_number_to_chars (buf, val, n)
3701 md_number_to_chars (buf, hi, 4);
3726 md_parse_option (argP, cntP, vecP)
3731 /* Accept -nocpp but ignore it. */
3732 if (strcmp (*argP, "nocpp") == 0)
3738 if (strcmp (*argP, "EL") == 0
3739 || strcmp (*argP, "EB") == 0)
3741 /* FIXME: This breaks -L -EL. */
3749 if ((*argP)[1] == '0')
3758 if ((*argP)[1] == '\0' || (*argP)[1] == '2')
3763 if (strncmp (*argP, "mips", 4) == 0)
3765 mips_isa = atol (*argP + 4);
3768 else if (mips_isa < 1 || mips_isa > 3)
3770 as_bad ("-mips%d not supported", mips_isa);
3777 if (strncmp (*argP, "mcpu=", 5) == 0)
3781 /* Identify the processor type */
3783 if (strcmp (p, "default") == 0
3784 || strcmp (p, "DEFAULT") == 0)
3788 if (*p == 'r' || *p == 'R')
3795 if (strcmp (p, "2000") == 0
3796 || strcmp (p, "2k") == 0
3797 || strcmp (p, "2K") == 0)
3802 if (strcmp (p, "3000") == 0
3803 || strcmp (p, "3k") == 0
3804 || strcmp (p, "3K") == 0)
3809 if (strcmp (p, "4000") == 0
3810 || strcmp (p, "4k") == 0
3811 || strcmp (p, "4K") == 0)
3816 if (strcmp (p, "6000") == 0
3817 || strcmp (p, "6k") == 0
3818 || strcmp (p, "6K") == 0)
3825 as_bad ("bad value (%s) for -mcpu= switch", *argP + 5);
3838 if ((*argP)[1] != '\0')
3839 g_switch_value = atoi (*argP + 1);
3842 **vecP = (char *) NULL;
3845 g_switch_value = atoi (**vecP);
3848 as_warn ("Number expected after -G");
3854 return 1; /* pretend you parsed the character */
3858 md_pcrel_from (fixP)
3861 /* return the address of the delay slot */
3862 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3865 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3866 reloc for a cons. We could use the definition there, except that
3867 we want to handle 64 bit relocs specially. */
3870 cons_fix_new_mips (frag, where, nbytes, exp)
3873 unsigned int nbytes;
3876 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3878 FIXME: There is no way to select anything but 32 bit mode right
3882 if (byte_order == BIG_ENDIAN)
3887 if (nbytes != 2 && nbytes != 4)
3888 as_bad ("Unsupported reloc size %d", nbytes);
3890 fix_new_exp (frag_now, where, (int) nbytes, exp, 0,
3891 nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32);
3895 md_apply_fix (fixP, valueP)
3902 assert (fixP->fx_size == 4);
3905 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
3907 switch (fixP->fx_r_type)
3910 case BFD_RELOC_MIPS_JMP:
3911 case BFD_RELOC_HI16:
3912 case BFD_RELOC_HI16_S:
3913 case BFD_RELOC_LO16:
3914 case BFD_RELOC_MIPS_GPREL:
3915 /* Nothing needed to do. The value comes from the reloc entry */
3918 case BFD_RELOC_16_PCREL_S2:
3920 * We need to save the bits in the instruction since fixup_segment()
3921 * might be deleting the relocation entry (i.e., a branch within
3922 * the current segment).
3925 as_warn ("Branch to odd address (%lx)", value);
3927 if ((value & ~0xFFFF) && (value & ~0xFFFF) != (-1 & ~0xFFFF))
3928 as_bad ("Relocation overflow");
3930 /* update old instruction data */
3931 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
3935 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
3939 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
3946 insn |= value & 0xFFFF;
3947 md_number_to_chars ((char *) buf, (valueT) insn, 4);
3961 const struct mips_opcode *p;
3962 int treg, sreg, dreg, shamt;
3967 for (i = 0; i < NUMOPCODES; ++i)
3969 p = &mips_opcodes[i];
3970 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
3972 printf ("%08lx %s\t", oc, p->name);
3973 treg = (oc >> 16) & 0x1f;
3974 sreg = (oc >> 21) & 0x1f;
3975 dreg = (oc >> 11) & 0x1f;
3976 shamt = (oc >> 6) & 0x1f;
3978 for (args = p->args;; ++args)
3989 printf ("%c", *args);
3993 assert (treg == sreg);
3994 printf ("$%d,$%d", treg, sreg);
3999 printf ("$%d", dreg);
4004 printf ("$%d", treg);
4009 printf ("$%d", sreg);
4013 printf ("0x%08lx", oc & 0x1ffffff);
4024 printf ("$%d", shamt);
4035 printf ("%08lx UNDEFINED\n", oc);
4046 name = input_line_pointer;
4047 c = get_symbol_end ();
4048 p = (symbolS *) symbol_find_or_make (name);
4049 *input_line_pointer = c;
4053 /* Align the current frag to a given power of two. The MIPS assembler
4054 also automatically adjusts any preceding label. */
4057 mips_align (to, fill)
4061 mips_emit_delays ();
4062 frag_align (to, fill);
4063 record_alignment (now_seg, to);
4064 if (insn_label != NULL)
4066 assert (S_GET_SEGMENT (insn_label) == now_seg);
4067 insn_label->sy_frag = frag_now;
4068 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
4073 /* Align to a given power of two. .align 0 turns off the automatic
4074 alignment used by the data creating pseudo-ops. */
4081 register long temp_fill;
4082 long max_alignment = 15;
4086 o Note that the assembler pulls down any immediately preceeding label
4087 to the aligned address.
4088 o It's not documented but auto alignment is reinstated by
4089 a .align pseudo instruction.
4090 o Note also that after auto alignment is turned off the mips assembler
4091 issues an error on attempt to assemble an improperly aligned data item.
4096 temp = get_absolute_expression ();
4097 if (temp > max_alignment)
4098 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
4101 as_warn ("Alignment negative: 0 assumed.");
4104 if (*input_line_pointer == ',')
4106 input_line_pointer++;
4107 temp_fill = get_absolute_expression ();
4114 mips_align (temp, (int) temp_fill);
4121 demand_empty_rest_of_line ();
4124 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4125 that there was a previous instruction. */
4128 s_stringer (append_zero)
4131 mips_emit_delays ();
4133 stringer (append_zero);
4144 mips_emit_delays ();
4154 subseg_set (bss_section, (subsegT) get_absolute_expression ());
4155 demand_empty_rest_of_line ();
4160 subseg_new (".rdata", (subsegT) get_absolute_expression ());
4161 demand_empty_rest_of_line ();
4163 #else /* ! defined (OBJ_ECOFF) */
4165 seg = subseg_new (".rodata", (subsegT) get_absolute_expression ());
4166 bfd_set_section_flags (stdoutput, seg,
4172 demand_empty_rest_of_line ();
4174 #else /* ! defined (OBJ_ELF) */
4177 #endif /* ! defined (OBJ_ELF) */
4178 #endif /* ! defined (OBJ_ECOFF) */
4182 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
4184 bfd_set_section_flags (stdoutput, seg,
4185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
4187 demand_empty_rest_of_line ();
4189 #else /* ! defined (GPOPT) */
4190 as_bad ("Global pointers not supported; recompile -G 0");
4191 demand_empty_rest_of_line ();
4193 #endif /* ! defined (GPOPT) */
4203 mips_emit_delays ();
4204 if (log_size > 0 && auto_align)
4205 mips_align (log_size, 0);
4207 cons (1 << log_size);
4214 as_fatal ("Encountered `.err', aborting assembly");
4224 symbolP = get_symbol ();
4225 if (*input_line_pointer == ',')
4226 input_line_pointer++;
4227 size = get_absolute_expression ();
4228 S_SET_VALUE (symbolP, size);
4229 S_SET_EXTERNAL (symbolP);
4232 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4233 so we use an additional ECOFF specific field. */
4234 symbolP->ecoff_undefined = 1;
4242 mips_emit_delays ();
4259 if (strcmp (input_line_pointer, "O1") != 0
4260 && strcmp (input_line_pointer, "O2") != 0)
4261 as_warn ("Unrecognized option");
4262 demand_empty_rest_of_line ();
4269 char *name = input_line_pointer, ch;
4271 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4272 input_line_pointer++;
4273 ch = *input_line_pointer;
4274 *input_line_pointer = '\0';
4276 if (strcmp (name, "reorder") == 0)
4280 prev_insn_unreordered = 1;
4281 prev_prev_insn_unreordered = 1;
4285 else if (strcmp (name, "noreorder") == 0)
4287 mips_emit_delays ();
4290 else if (strcmp (name, "at") == 0)
4294 else if (strcmp (name, "noat") == 0)
4298 else if (strcmp (name, "macro") == 0)
4300 mips_warn_about_macros = 0;
4302 else if (strcmp (name, "nomacro") == 0)
4304 if (mips_noreorder == 0)
4305 as_bad ("`noreorder' must be set before `nomacro'");
4306 mips_warn_about_macros = 1;
4308 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
4312 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
4316 else if (strcmp (name, "bopt") == 0)
4320 else if (strcmp (name, "nobopt") == 0)
4326 as_warn ("Tried to set unrecognized symbol: %s\n", name);
4328 *input_line_pointer = ch;
4329 demand_empty_rest_of_line ();
4332 /* The same as the usual .space directive, except that we have to
4333 forget about any previous instruction. */
4336 s_mips_space (param)
4339 mips_emit_delays ();
4350 if (*input_line_pointer++ != '$')
4352 as_warn ("expected `$'");
4355 if (isdigit ((unsigned char) *input_line_pointer))
4357 reg = get_absolute_expression ();
4358 if (reg < 0 || reg >= 32)
4360 as_warn ("Bad register number");
4366 if (strncmp (input_line_pointer, "fp", 2) == 0)
4368 else if (strncmp (input_line_pointer, "sp", 2) == 0)
4370 else if (strncmp (input_line_pointer, "gp", 2) == 0)
4372 else if (strncmp (input_line_pointer, "at", 2) == 0)
4376 as_warn ("Unrecognized register name");
4379 input_line_pointer += 2;
4385 * Translate internal representation of relocation info to BFD target format.
4388 tc_gen_reloc (section, fixp)
4394 reloc = (arelent *) xmalloc (sizeof (arelent));
4395 assert (reloc != 0);
4397 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
4398 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4399 if (fixp->fx_pcrel == 0)
4400 reloc->addend = fixp->fx_addnumber;
4405 reloc->addend = -reloc->address;
4407 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
4408 assert (reloc->howto != 0);
4413 /* should never be called */
4415 md_section_align (seg, addr)
4419 int align = bfd_get_section_alignment (stdoutput, seg);
4421 return ((addr + (1 << align) - 1) & (-1 << align));
4425 md_estimate_size_before_relax (fragP, segtype)
4429 as_fatal ("md_estimate_size_before_relax");
4431 } /* md_estimate_size_before_relax() */
4433 /* This function is called whenever a label is defined. It is used
4434 when handling branch delays; if a branch has a label, we assume we
4438 mips_define_label (sym)
4446 /* These functions should really be defined by the object file format,
4447 since they are related to debugging information. However, this
4448 code has to work for the a.out format, which does not define them,
4449 so we provide simple versions here. These don't actually generate
4450 any debugging information, but they do simple checking and someday
4451 somebody may make them useful. */
4455 struct loc *loc_next;
4456 unsigned long loc_fileno;
4457 unsigned long loc_lineno;
4458 unsigned long loc_offset;
4459 unsigned short loc_delta;
4460 unsigned short loc_count;
4469 struct proc *proc_next;
4470 struct symbol *proc_isym;
4471 struct symbol *proc_end;
4472 unsigned long proc_reg_mask;
4473 unsigned long proc_reg_offset;
4474 unsigned long proc_fpreg_mask;
4475 unsigned long proc_fpreg_offset;
4476 unsigned long proc_frameoffset;
4477 unsigned long proc_framereg;
4478 unsigned long proc_pcreg;
4480 struct file *proc_file;
4487 struct file *file_next;
4488 unsigned long file_fileno;
4489 struct symbol *file_symbol;
4490 struct symbol *file_end;
4491 struct proc *file_proc;
4496 static struct obstack proc_frags;
4497 static procS *proc_lastP;
4498 static procS *proc_rootP;
4499 static int numprocs;
4504 obstack_begin (&proc_frags, 0x2000);
4510 /* check for premature end, nesting errors, etc */
4511 if (proc_lastP && proc_lastP->proc_end == NULL)
4512 as_warn ("missing `.end' at end of assembly");
4515 extern char hex_value[];
4523 if (*input_line_pointer == '-')
4525 ++input_line_pointer;
4528 if (!isdigit (*input_line_pointer))
4529 as_bad ("Expected simple number.");
4530 if (input_line_pointer[0] == '0')
4532 if (input_line_pointer[1] == 'x')
4534 input_line_pointer += 2;
4535 while (isxdigit (*input_line_pointer))
4538 val |= hex_value[(int) *input_line_pointer++];
4540 return negative ? -val : val;
4544 ++input_line_pointer;
4545 while (isdigit (*input_line_pointer))
4548 val |= *input_line_pointer++ - '0';
4550 return negative ? -val : val;
4553 if (!isdigit (*input_line_pointer))
4555 printf (" *input_line_pointer == '%c' 0x%02x\n",
4556 *input_line_pointer, *input_line_pointer);
4557 as_warn ("Invalid number");
4560 while (isdigit (*input_line_pointer))
4563 val += *input_line_pointer++ - '0';
4565 return negative ? -val : val;
4568 /* The .file directive; just like the usual .file directive, but there
4569 is an initial number which is the ECOFF file index. */
4577 line = get_number ();
4582 /* The .end directive. */
4590 if (!is_end_of_line[(unsigned char) *input_line_pointer])
4593 demand_empty_rest_of_line ();
4597 if (now_seg != text_section)
4598 as_warn (".end not in text section");
4601 as_warn (".end and no .ent seen yet.");
4607 assert (S_GET_NAME (p));
4608 if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym)))
4609 as_warn (".end symbol does not match .ent symbol.");
4612 proc_lastP->proc_end = (symbolS *) 1;
4615 /* The .aent and .ent directives. */
4625 symbolP = get_symbol ();
4626 if (*input_line_pointer == ',')
4627 input_line_pointer++;
4628 if (isdigit (*input_line_pointer) || *input_line_pointer == '-')
4629 number = get_number ();
4630 if (now_seg != text_section)
4631 as_warn (".ent or .aent not in text section.");
4633 if (!aent && proc_lastP && proc_lastP->proc_end == NULL)
4634 as_warn ("missing `.end'");
4638 procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP));
4639 procP->proc_isym = symbolP;
4640 procP->proc_reg_mask = 0;
4641 procP->proc_reg_offset = 0;
4642 procP->proc_fpreg_mask = 0;
4643 procP->proc_fpreg_offset = 0;
4644 procP->proc_frameoffset = 0;
4645 procP->proc_framereg = 0;
4646 procP->proc_pcreg = 0;
4647 procP->proc_end = NULL;
4648 procP->proc_next = NULL;
4650 proc_lastP->proc_next = procP;
4656 demand_empty_rest_of_line ();
4659 /* The .frame directive. */
4672 frame_reg = tc_get_register ();
4673 if (*input_line_pointer == ',')
4674 input_line_pointer++;
4675 frame_off = get_absolute_expression ();
4676 if (*input_line_pointer == ',')
4677 input_line_pointer++;
4678 pcreg = tc_get_register ();
4681 assert (proc_rootP);
4682 proc_rootP->proc_framereg = frame_reg;
4683 proc_rootP->proc_frameoffset = frame_off;
4684 proc_rootP->proc_pcreg = pcreg;
4685 /* bob macho .frame */
4687 /* We don't have to write out a frame stab for unoptimized code. */
4688 if (!(frame_reg == 30 && frame_off == 0))
4691 as_warn ("No .ent for .frame to use.");
4692 (void) sprintf (str, "R%d;%d", frame_reg, frame_off);
4693 symP = symbol_new (str, N_VFP, 0, frag_now);
4694 S_SET_TYPE (symP, N_RMASK);
4695 S_SET_OTHER (symP, 0);
4696 S_SET_DESC (symP, 0);
4697 symP->sy_forward = proc_lastP->proc_isym;
4698 /* bob perhaps I should have used pseudo set */
4700 demand_empty_rest_of_line ();
4704 /* The .fmask and .mask directives. */
4711 char str[100], *strP;
4717 mask = get_number ();
4718 if (*input_line_pointer == ',')
4719 input_line_pointer++;
4720 off = get_absolute_expression ();
4722 /* bob only for coff */
4723 assert (proc_rootP);
4724 if (reg_type == 'F')
4726 proc_rootP->proc_fpreg_mask = mask;
4727 proc_rootP->proc_fpreg_offset = off;
4731 proc_rootP->proc_reg_mask = mask;
4732 proc_rootP->proc_reg_offset = off;
4735 /* bob macho .mask + .fmask */
4737 /* We don't have to write out a mask stab if no saved regs. */
4741 as_warn ("No .ent for .mask to use.");
4743 for (i = 0; i < 32; i++)
4747 sprintf (strP, "%c%d,", reg_type, i);
4748 strP += strlen (strP);
4752 sprintf (strP, ";%d,", off);
4753 symP = symbol_new (str, N_RMASK, 0, frag_now);
4754 S_SET_TYPE (symP, N_RMASK);
4755 S_SET_OTHER (symP, 0);
4756 S_SET_DESC (symP, 0);
4757 symP->sy_forward = proc_lastP->proc_isym;
4758 /* bob perhaps I should have used pseudo set */
4763 /* The .loc directive. */
4774 assert (now_seg == text_section);
4776 lineno = get_number ();
4777 addroff = obstack_next_free (&frags) - frag_now->fr_literal;
4779 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
4780 S_SET_TYPE (symbolP, N_SLINE);
4781 S_SET_OTHER (symbolP, 0);
4782 S_SET_DESC (symbolP, lineno);
4783 symbolP->sy_segment = now_seg;
4787 #endif /* ! defined (OBJ_ECOFF) */