1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_symbol
53 #undef obj_sec_sym_ok_for_reloc
56 /* Fix any of them that we actually care about. */
58 #define OUTPUT_FLAVOR mips_output_flavor()
65 #ifndef ECOFF_DEBUGGING
66 #define ECOFF_DEBUGGING 0
71 static char *mips_regmask_frag;
74 #define PIC_CALL_REG 25
82 extern int target_big_endian;
84 /* The default target format to use. */
88 switch (OUTPUT_FLAVOR)
90 case bfd_target_aout_flavour:
91 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
92 case bfd_target_ecoff_flavour:
93 return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips";
94 case bfd_target_elf_flavour:
95 return target_big_endian ? "elf32-bigmips" : "elf32-littlemips";
101 /* The name of the readonly data section. */
102 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
104 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
106 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
110 /* These variables are filled in with the masks of registers used.
111 The object format code reads them and puts them in the appropriate
113 unsigned long mips_gprmask;
114 unsigned long mips_cprmask[4];
116 /* MIPS ISA (Instruction Set Architecture) level (may be changed
117 temporarily using .set mipsN). */
118 static int mips_isa = -1;
120 /* MIPS ISA we are using for this output file. */
121 static int file_mips_isa;
123 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
124 static int mips_cpu = -1;
126 /* Whether the 4650 instructions (mad/madu) are permitted. */
127 static int mips_4650 = -1;
129 /* MIPS PIC level. */
133 /* Do not generate PIC code. */
136 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
137 not sure what it is supposed to do. */
140 /* Generate PIC code as in the SVR4 MIPS ABI. */
143 /* Generate PIC code without using a global offset table: the data
144 segment has a maximum size of 64K, all data references are off
145 the $gp register, and all text references are PC relative. This
146 is used on some embedded systems. */
150 static enum mips_pic_level mips_pic;
152 /* 1 if trap instructions should used for overflow rather than break
154 static int mips_trap;
156 static int mips_warn_about_macros;
157 static int mips_noreorder;
158 static int mips_any_noreorder;
159 static int mips_nomove;
160 static int mips_noat;
161 static int mips_nobopt;
163 /* The size of the small data section. */
164 static int g_switch_value = 8;
165 /* Whether the -G option was used. */
166 static int g_switch_seen = 0;
171 /* If we can determine in advance that GP optimization won't be
172 possible, we can skip the relaxation stuff that tries to produce
173 GP-relative references. This makes delay slot optimization work
176 This function can only provide a guess, but it seems to work for
177 gcc output. If it guesses wrong, the only loss should be in
178 efficiency; it shouldn't introduce any bugs.
180 I don't know if a fix is needed for the SVR4_PIC mode. I've only
181 fixed it for the non-PIC mode. KR 95/04/07 */
182 static int nopic_need_relax PARAMS ((symbolS *));
184 /* handle of the OPCODE hash table */
185 static struct hash_control *op_hash = NULL;
187 /* This array holds the chars that always start a comment. If the
188 pre-processor is disabled, these aren't very useful */
189 const char comment_chars[] = "#";
191 /* This array holds the chars that only start a comment at the beginning of
192 a line. If the line seems to have the form '# 123 filename'
193 .line and .file directives will appear in the pre-processed output */
194 /* Note that input_file.c hand checks for '#' at the beginning of the
195 first line of the input file. This is because the compiler outputs
196 #NO_APP at the beginning of its output. */
197 /* Also note that C style comments are always supported. */
198 const char line_comment_chars[] = "#";
200 /* This array holds machine specific line separator characters. */
201 const char line_separator_chars[] = "";
203 /* Chars that can be used to separate mant from exp in floating point nums */
204 const char EXP_CHARS[] = "eE";
206 /* Chars that mean this number is a floating point constant */
209 const char FLT_CHARS[] = "rRsSfFdDxXpP";
211 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
212 changed in read.c . Ideally it shouldn't have to know about it at all,
213 but nothing is ideal around here.
216 static char *insn_error;
218 static int byte_order;
220 static int auto_align = 1;
222 /* Symbol labelling the current insn. */
223 static symbolS *insn_label;
225 /* When outputting SVR4 PIC code, the assembler needs to know the
226 offset in the stack frame from which to restore the $gp register.
227 This is set by the .cprestore pseudo-op, and saved in this
229 static offsetT mips_cprestore_offset = -1;
231 /* This is the register which holds the stack frame, as set by the
232 .frame pseudo-op. This is needed to implement .cprestore. */
233 static int mips_frame_reg = SP;
235 /* To output NOP instructions correctly, we need to keep information
236 about the previous two instructions. */
238 /* Whether we are optimizing. The default value of 2 means to remove
239 unneeded NOPs and swap branch instructions when possible. A value
240 of 1 means to not swap branches. A value of 0 means to always
242 static int mips_optimize = 2;
244 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
245 equivalent to seeing no -g option at all. */
246 static int mips_debug = 0;
248 /* The previous instruction. */
249 static struct mips_cl_insn prev_insn;
251 /* The instruction before prev_insn. */
252 static struct mips_cl_insn prev_prev_insn;
254 /* If we don't want information for prev_insn or prev_prev_insn, we
255 point the insn_mo field at this dummy integer. */
256 static const struct mips_opcode dummy_opcode = { 0 };
258 /* Non-zero if prev_insn is valid. */
259 static int prev_insn_valid;
261 /* The frag for the previous instruction. */
262 static struct frag *prev_insn_frag;
264 /* The offset into prev_insn_frag for the previous instruction. */
265 static long prev_insn_where;
267 /* The reloc for the previous instruction, if any. */
268 static fixS *prev_insn_fixp;
270 /* Non-zero if the previous instruction was in a delay slot. */
271 static int prev_insn_is_delay_slot;
273 /* Non-zero if the previous instruction was in a .set noreorder. */
274 static int prev_insn_unreordered;
276 /* Non-zero if the previous previous instruction was in a .set
278 static int prev_prev_insn_unreordered;
280 /* Since the MIPS does not have multiple forms of PC relative
281 instructions, we do not have to do relaxing as is done on other
282 platforms. However, we do have to handle GP relative addressing
283 correctly, which turns out to be a similar problem.
285 Every macro that refers to a symbol can occur in (at least) two
286 forms, one with GP relative addressing and one without. For
287 example, loading a global variable into a register generally uses
288 a macro instruction like this:
290 If i can be addressed off the GP register (this is true if it is in
291 the .sbss or .sdata section, or if it is known to be smaller than
292 the -G argument) this will generate the following instruction:
294 This instruction will use a GPREL reloc. If i can not be addressed
295 off the GP register, the following instruction sequence will be used:
298 In this case the first instruction will have a HI16 reloc, and the
299 second reloc will have a LO16 reloc. Both relocs will be against
302 The issue here is that we may not know whether i is GP addressable
303 until after we see the instruction that uses it. Therefore, we
304 want to be able to choose the final instruction sequence only at
305 the end of the assembly. This is similar to the way other
306 platforms choose the size of a PC relative instruction only at the
309 When generating position independent code we do not use GP
310 addressing in quite the same way, but the issue still arises as
311 external symbols and local symbols must be handled differently.
313 We handle these issues by actually generating both possible
314 instruction sequences. The longer one is put in a frag_var with
315 type rs_machine_dependent. We encode what to do with the frag in
316 the subtype field. We encode (1) the number of existing bytes to
317 replace, (2) the number of new bytes to use, (3) the offset from
318 the start of the existing bytes to the first reloc we must generate
319 (that is, the offset is applied from the start of the existing
320 bytes after they are replaced by the new bytes, if any), (4) the
321 offset from the start of the existing bytes to the second reloc,
322 (5) whether a third reloc is needed (the third reloc is always four
323 bytes after the second reloc), and (6) whether to warn if this
324 variant is used (this is sometimes needed if .set nomacro or .set
325 noat is in effect). All these numbers are reasonably small.
327 Generating two instruction sequences must be handled carefully to
328 ensure that delay slots are handled correctly. Fortunately, there
329 are a limited number of cases. When the second instruction
330 sequence is generated, append_insn is directed to maintain the
331 existing delay slot information, so it continues to apply to any
332 code after the second instruction sequence. This means that the
333 second instruction sequence must not impose any requirements not
334 required by the first instruction sequence.
336 These variant frags are then handled in functions called by the
337 machine independent code. md_estimate_size_before_relax returns
338 the final size of the frag. md_convert_frag sets up the final form
339 of the frag. tc_gen_reloc adjust the first reloc and adds a second
341 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
345 | (((reloc1) + 64) << 9) \
346 | (((reloc2) + 64) << 2) \
347 | ((reloc3) ? (1 << 1) : 0) \
349 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
350 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
351 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
352 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
353 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
354 #define RELAX_WARN(i) ((i) & 1)
356 /* Prototypes for static functions. */
359 #define internalError() \
360 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
362 #define internalError() as_fatal ("MIPS internal Error");
365 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
366 unsigned int reg, int fpr));
367 static void append_insn PARAMS ((char *place,
368 struct mips_cl_insn * ip,
370 bfd_reloc_code_real_type r));
371 static void mips_no_prev_insn PARAMS ((void));
372 static void mips_emit_delays PARAMS ((void));
373 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
374 const char *name, const char *fmt,
376 static void macro_build_lui PARAMS ((char *place, int *counter,
377 expressionS * ep, int regnum));
378 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
379 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
381 static void load_register PARAMS ((int *, int, expressionS *, int));
382 static void load_address PARAMS ((int *counter, int reg, expressionS *ep));
383 static void macro PARAMS ((struct mips_cl_insn * ip));
384 #ifdef LOSING_COMPILER
385 static void macro2 PARAMS ((struct mips_cl_insn * ip));
387 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
388 static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
389 static void my_getExpression PARAMS ((expressionS * ep, char *str));
390 static symbolS *get_symbol PARAMS ((void));
391 static void mips_align PARAMS ((int to, int fill, symbolS *label));
392 static void s_align PARAMS ((int));
393 static void s_change_sec PARAMS ((int));
394 static void s_cons PARAMS ((int));
395 static void s_err PARAMS ((int));
396 static void s_extern PARAMS ((int));
397 static void s_float_cons PARAMS ((int));
398 static void s_mips_globl PARAMS ((int));
399 static void s_option PARAMS ((int));
400 static void s_mipsset PARAMS ((int));
401 static void s_abicalls PARAMS ((int));
402 static void s_cpload PARAMS ((int));
403 static void s_cprestore PARAMS ((int));
404 static void s_gpword PARAMS ((int));
405 static void s_cpadd PARAMS ((int));
406 static void md_obj_begin PARAMS ((void));
407 static void md_obj_end PARAMS ((void));
408 static long get_number PARAMS ((void));
409 static void s_ent PARAMS ((int));
410 static void s_mipsend PARAMS ((int));
411 static void s_file PARAMS ((int));
415 The following pseudo-ops from the Kane and Heinrich MIPS book
416 should be defined here, but are currently unsupported: .alias,
417 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
419 The following pseudo-ops from the Kane and Heinrich MIPS book are
420 specific to the type of debugging information being generated, and
421 should be defined by the object format: .aent, .begin, .bend,
422 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
425 The following pseudo-ops from the Kane and Heinrich MIPS book are
426 not MIPS CPU specific, but are also not specific to the object file
427 format. This file is probably the best place to define them, but
428 they are not currently supported: .asm0, .endr, .lab, .repeat,
429 .struct, .weakext. */
431 static const pseudo_typeS mips_pseudo_table[] =
433 /* MIPS specific pseudo-ops. */
434 {"option", s_option, 0},
435 {"set", s_mipsset, 0},
436 {"rdata", s_change_sec, 'r'},
437 {"sdata", s_change_sec, 's'},
438 {"livereg", s_ignore, 0},
439 {"abicalls", s_abicalls, 0},
440 {"cpload", s_cpload, 0},
441 {"cprestore", s_cprestore, 0},
442 {"gpword", s_gpword, 0},
443 {"cpadd", s_cpadd, 0},
445 /* Relatively generic pseudo-ops that happen to be used on MIPS
447 {"asciiz", stringer, 1},
448 {"bss", s_change_sec, 'b'},
451 {"dword", s_cons, 3},
453 /* These pseudo-ops are defined in read.c, but must be overridden
454 here for one reason or another. */
455 {"align", s_align, 0},
457 {"data", s_change_sec, 'd'},
458 {"double", s_float_cons, 'd'},
459 {"extern", s_extern, 0},
460 {"float", s_float_cons, 'f'},
461 {"globl", s_mips_globl, 0},
462 {"global", s_mips_globl, 0},
463 {"hword", s_cons, 1},
468 {"short", s_cons, 1},
469 {"single", s_float_cons, 'f'},
470 {"text", s_change_sec, 't'},
475 static const pseudo_typeS mips_nonecoff_pseudo_table[] = {
476 /* These pseudo-ops should be defined by the object file format.
477 However, a.out doesn't support them, so we have versions here. */
479 {"bgnb", s_ignore, 0},
480 {"end", s_mipsend, 0},
481 {"endb", s_ignore, 0},
484 {"fmask", s_ignore, 'F'},
485 {"frame", s_ignore, 0},
486 {"loc", s_ignore, 0},
487 {"mask", s_ignore, 'R'},
488 {"verstamp", s_ignore, 0},
492 static const pseudo_typeS mips_elf_pseudo_table[] = {
493 /* Redirect additional ELF data allocation pseudo-ops. */
494 {"2byte", s_cons, 2},
495 {"4byte", s_cons, 4},
496 {"8byte", s_cons, 8},
501 extern void pop_insert PARAMS ((const pseudo_typeS *));
506 pop_insert (mips_pseudo_table);
507 if (! ECOFF_DEBUGGING)
508 pop_insert (mips_nonecoff_pseudo_table);
509 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
510 pop_insert (mips_elf_pseudo_table);
513 static char *expr_end;
515 static expressionS imm_expr;
516 static expressionS offset_expr;
517 static bfd_reloc_code_real_type imm_reloc;
518 static bfd_reloc_code_real_type offset_reloc;
521 * This function is called once, at assembler startup time. It should
522 * set up all the tables, etc. that the MD part of the assembler will need.
528 register const char *retval = NULL;
529 register unsigned int i = 0;
537 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
539 a = xmalloc (sizeof TARGET_CPU);
540 strcpy (a, TARGET_CPU);
541 a[(sizeof TARGET_CPU) - 3] = '\0';
545 if (strcmp (cpu, "mips") == 0)
551 else if (strcmp (cpu, "r6000") == 0
552 || strcmp (cpu, "mips2") == 0)
558 else if (strcmp (cpu, "mips64") == 0
559 || strcmp (cpu, "r4000") == 0
560 || strcmp (cpu, "mips3") == 0)
566 else if (strcmp (cpu, "r4400") == 0)
572 else if (strcmp (cpu, "mips64orion") == 0
573 || strcmp (cpu, "r4600") == 0)
579 else if (strcmp (cpu, "r4650") == 0)
587 else if (strcmp (cpu, "r8000") == 0
588 || strcmp (cpu, "mips4") == 0)
594 else if (strcmp (cpu, "r10000") == 0)
614 if (mips_isa < 2 && mips_trap)
615 as_bad ("trap exception not supported at ISA 1");
620 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000);
623 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000);
626 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000);
629 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000);
633 as_warn ("Could not set architecture and machine");
635 file_mips_isa = mips_isa;
637 op_hash = hash_new ();
639 for (i = 0; i < NUMOPCODES;)
641 const char *name = mips_opcodes[i].name;
643 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
646 fprintf (stderr, "internal error: can't hash `%s': %s\n",
647 mips_opcodes[i].name, retval);
648 as_fatal ("Broken assembler. No assembly attempted.");
652 if (mips_opcodes[i].pinfo != INSN_MACRO
653 && ((mips_opcodes[i].match & mips_opcodes[i].mask)
654 != mips_opcodes[i].match))
656 fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n",
657 mips_opcodes[i].name, mips_opcodes[i].args);
658 as_fatal ("Broken assembler. No assembly attempted.");
662 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
665 mips_no_prev_insn ();
673 /* set the default alignment for the text section (2**2) */
674 record_alignment (text_section, 2);
676 if (USE_GLOBAL_POINTER_OPT)
677 bfd_set_gp_size (stdoutput, g_switch_value);
679 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
681 /* Sections must be aligned to 16 byte boundaries. */
682 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
683 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
684 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
686 /* Create a .reginfo section for register masks and a .mdebug
687 section for debugging information. */
695 sec = subseg_new (".reginfo", (subsegT) 0);
697 /* The ABI says this section should be loaded so that the
698 running program can access it. */
699 (void) bfd_set_section_flags (stdoutput, sec,
700 (SEC_ALLOC | SEC_LOAD
701 | SEC_READONLY | SEC_DATA));
702 (void) bfd_set_section_alignment (stdoutput, sec, 2);
705 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
710 sec = subseg_new (".mdebug", (subsegT) 0);
711 (void) bfd_set_section_flags (stdoutput, sec,
712 SEC_HAS_CONTENTS | SEC_READONLY);
713 (void) bfd_set_section_alignment (stdoutput, sec, 2);
716 subseg_set (seg, subseg);
720 if (! ECOFF_DEBUGGING)
727 if (! ECOFF_DEBUGGING)
735 struct mips_cl_insn insn;
737 imm_expr.X_op = O_absent;
738 offset_expr.X_op = O_absent;
740 mips_ip (str, &insn);
743 as_bad ("%s `%s'", insn_error, str);
746 if (insn.insn_mo->pinfo == INSN_MACRO)
752 if (imm_expr.X_op != O_absent)
753 append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc);
754 else if (offset_expr.X_op != O_absent)
755 append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc);
757 append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED);
761 /* See whether instruction IP reads register REG. If FPR is non-zero,
762 REG is a floating point register. */
765 insn_uses_reg (ip, reg, fpr)
766 struct mips_cl_insn *ip;
770 /* Don't report on general register 0, since it never changes. */
771 if (! fpr && reg == 0)
776 /* If we are called with either $f0 or $f1, we must check $f0.
777 This is not optimal, because it will introduce an unnecessary
778 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
779 need to distinguish reading both $f0 and $f1 or just one of
780 them. Note that we don't have to check the other way,
781 because there is no instruction that sets both $f0 and $f1
782 and requires a delay. */
783 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
784 && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS)
785 == (reg &~ (unsigned) 1)))
787 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
788 && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT)
789 == (reg &~ (unsigned) 1)))
794 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
795 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
797 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
798 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
805 /* Output an instruction. PLACE is where to put the instruction; if
806 it is NULL, this uses frag_more to get room. IP is the instruction
807 information. ADDRESS_EXPR is an operand of the instruction to be
808 used with RELOC_TYPE. */
811 append_insn (place, ip, address_expr, reloc_type)
813 struct mips_cl_insn *ip;
814 expressionS *address_expr;
815 bfd_reloc_code_real_type reloc_type;
817 register unsigned long prev_pinfo, pinfo;
822 prev_pinfo = prev_insn.insn_mo->pinfo;
823 pinfo = ip->insn_mo->pinfo;
825 if (place == NULL && ! mips_noreorder)
827 /* If the previous insn required any delay slots, see if we need
828 to insert a NOP or two. There are eight kinds of possible
829 hazards, of which an instruction can have at most one type.
830 (1) a load from memory delay
831 (2) a load from a coprocessor delay
832 (3) an unconditional branch delay
833 (4) a conditional branch delay
834 (5) a move to coprocessor register delay
835 (6) a load coprocessor register from memory delay
836 (7) a coprocessor condition code delay
837 (8) a HI/LO special register delay
839 There are a lot of optimizations we could do that we don't.
840 In particular, we do not, in general, reorder instructions.
841 If you use gcc with optimization, it will reorder
842 instructions and generally do much more optimization then we
843 do here; repeating all that work in the assembler would only
844 benefit hand written assembly code, and does not seem worth
847 /* This is how a NOP is emitted. */
848 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
850 /* The previous insn might require a delay slot, depending upon
851 the contents of the current insn. */
853 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
855 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
857 /* A load from a coprocessor or from memory. All load
858 delays delay the use of general register rt for one
859 instruction on the r3000. The r6000 and r4000 use
861 know (prev_pinfo & INSN_WRITE_GPR_T);
862 if (mips_optimize == 0
863 || insn_uses_reg (ip,
864 ((prev_insn.insn_opcode >> OP_SH_RT)
869 else if (mips_isa < 4
870 && ((prev_pinfo & INSN_COPROC_MOVE_DELAY)
872 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
874 /* A generic coprocessor delay. The previous instruction
875 modified a coprocessor general or control register. If
876 it modified a control register, we need to avoid any
877 coprocessor instruction (this is probably not always
878 required, but it sometimes is). If it modified a general
879 register, we avoid using that register.
881 On the r6000 and r4000 loading a coprocessor register
882 from memory is interlocked, and does not require a delay.
884 This case is not handled very well. There is no special
885 knowledge of CP0 handling, and the coprocessors other
886 than the floating point unit are not distinguished at
888 if (prev_pinfo & INSN_WRITE_FPR_T)
890 if (mips_optimize == 0
891 || insn_uses_reg (ip,
892 ((prev_insn.insn_opcode >> OP_SH_FT)
897 else if (prev_pinfo & INSN_WRITE_FPR_S)
899 if (mips_optimize == 0
900 || insn_uses_reg (ip,
901 ((prev_insn.insn_opcode >> OP_SH_FS)
908 /* We don't know exactly what the previous instruction
909 does. If the current instruction uses a coprocessor
910 register, we must insert a NOP. If previous
911 instruction may set the condition codes, and the
912 current instruction uses them, we must insert two
914 if (mips_optimize == 0
915 || ((prev_pinfo & INSN_WRITE_COND_CODE)
916 && (pinfo & INSN_READ_COND_CODE)))
918 else if (pinfo & INSN_COP)
922 else if (mips_isa < 4
923 && (prev_pinfo & INSN_WRITE_COND_CODE))
925 /* The previous instruction sets the coprocessor condition
926 codes, but does not require a general coprocessor delay
927 (this means it is a floating point comparison
928 instruction). If this instruction uses the condition
929 codes, we need to insert a single NOP. */
930 if (mips_optimize == 0
931 || (pinfo & INSN_READ_COND_CODE))
934 else if (prev_pinfo & INSN_READ_LO)
936 /* The previous instruction reads the LO register; if the
937 current instruction writes to the LO register, we must
938 insert two NOPS. The R4650 has interlocks. */
940 && (mips_optimize == 0
941 || (pinfo & INSN_WRITE_LO)))
944 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
946 /* The previous instruction reads the HI register; if the
947 current instruction writes to the HI register, we must
948 insert a NOP. The R4650 has interlocks. */
950 && (mips_optimize == 0
951 || (pinfo & INSN_WRITE_HI)))
955 /* There are two cases which require two intervening
956 instructions: 1) setting the condition codes using a move to
957 coprocessor instruction which requires a general coprocessor
958 delay and then reading the condition codes 2) reading the HI
959 or LO register and then writing to it (except on the R4650,
960 which has interlocks). If we are not already emitting a NOP
961 instruction, we must check for these cases compared to the
962 instruction previous to the previous instruction. */
965 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
966 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
967 && (pinfo & INSN_READ_COND_CODE))
968 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
969 && (pinfo & INSN_WRITE_LO)
971 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
972 && (pinfo & INSN_WRITE_HI)
976 /* If we are being given a nop instruction, don't bother with
977 one of the nops we would otherwise output. This will only
978 happen when a nop instruction is used with mips_optimize set
980 if (nops > 0 && ip->insn_opcode == 0)
983 /* Now emit the right number of NOP instructions. */
988 for (i = 0; i < nops; i++)
992 listing_prev_line ();
993 /* We may be at the start of a variant frag. In case we
994 are, make sure there is enough space for the frag
995 after the frags created by listing_prev_line. The
996 argument to frag_grow here must be at least as large
997 as the argument to all other calls to frag_grow in
998 this file. We don't have to worry about being in the
999 middle of a variant frag, because the variants insert
1000 all needed nop instructions themselves. */
1003 if (insn_label != NULL)
1005 assert (S_GET_SEGMENT (insn_label) == now_seg);
1006 insn_label->sy_frag = frag_now;
1007 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
1017 if (address_expr != NULL)
1019 if (address_expr->X_op == O_constant)
1024 ip->insn_opcode |= address_expr->X_add_number;
1027 case BFD_RELOC_LO16:
1028 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1031 case BFD_RELOC_MIPS_JMP:
1032 case BFD_RELOC_16_PCREL_S2:
1041 assert (reloc_type != BFD_RELOC_UNUSED);
1043 /* Don't generate a reloc if we are writing into a variant
1046 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1048 reloc_type == BFD_RELOC_16_PCREL_S2,
1053 md_number_to_chars (f, ip->insn_opcode, 4);
1055 /* Update the register mask information. */
1056 if (pinfo & INSN_WRITE_GPR_D)
1057 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
1058 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
1059 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
1060 if (pinfo & INSN_READ_GPR_S)
1061 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
1062 if (pinfo & INSN_WRITE_GPR_31)
1063 mips_gprmask |= 1 << 31;
1064 if (pinfo & INSN_WRITE_FPR_D)
1065 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
1066 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
1067 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
1068 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
1069 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
1070 if ((pinfo & INSN_READ_FPR_R) != 0)
1071 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
1072 if (pinfo & INSN_COP)
1074 /* We don't keep enough information to sort these cases out. */
1076 /* Never set the bit for $0, which is always zero. */
1077 mips_gprmask &=~ 1 << 0;
1079 if (place == NULL && ! mips_noreorder)
1081 /* Filling the branch delay slot is more complex. We try to
1082 switch the branch with the previous instruction, which we can
1083 do if the previous instruction does not set up a condition
1084 that the branch tests and if the branch is not itself the
1085 target of any branch. */
1086 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
1087 || (pinfo & INSN_COND_BRANCH_DELAY))
1089 if (mips_optimize < 2
1090 /* If we have seen .set volatile or .set nomove, don't
1093 /* If we had to emit any NOP instructions, then we
1094 already know we can not swap. */
1096 /* If we don't even know the previous insn, we can not
1098 || ! prev_insn_valid
1099 /* If the previous insn is already in a branch delay
1100 slot, then we can not swap. */
1101 || prev_insn_is_delay_slot
1102 /* If the previous previous insn was in a .set
1103 noreorder, we can't swap. Actually, the MIPS
1104 assembler will swap in this situation. However, gcc
1105 configured -with-gnu-as will generate code like
1111 in which we can not swap the bne and INSN. If gcc is
1112 not configured -with-gnu-as, it does not output the
1113 .set pseudo-ops. We don't have to check
1114 prev_insn_unreordered, because prev_insn_valid will
1115 be 0 in that case. We don't want to use
1116 prev_prev_insn_valid, because we do want to be able
1117 to swap at the start of a function. */
1118 || prev_prev_insn_unreordered
1119 /* If the branch is itself the target of a branch, we
1120 can not swap. We cheat on this; all we check for is
1121 whether there is a label on this instruction. If
1122 there are any branches to anything other than a
1123 label, users must use .set noreorder. */
1124 || insn_label != NULL
1125 /* If the previous instruction is in a variant frag, we
1126 can not do the swap. */
1127 || prev_insn_frag->fr_type == rs_machine_dependent
1128 /* If the branch reads the condition codes, we don't
1129 even try to swap, because in the sequence
1134 we can not swap, and I don't feel like handling that
1137 && (pinfo & INSN_READ_COND_CODE))
1138 /* We can not swap with an instruction that requires a
1139 delay slot, becase the target of the branch might
1140 interfere with that instruction. */
1143 & (INSN_LOAD_COPROC_DELAY
1144 | INSN_COPROC_MOVE_DELAY
1145 | INSN_WRITE_COND_CODE)))
1152 & (INSN_LOAD_MEMORY_DELAY
1153 | INSN_COPROC_MEMORY_DELAY)))
1154 /* We can not swap with a branch instruction. */
1156 & (INSN_UNCOND_BRANCH_DELAY
1157 | INSN_COND_BRANCH_DELAY
1158 | INSN_COND_BRANCH_LIKELY))
1159 /* We do not swap with a trap instruction, since it
1160 complicates trap handlers to have the trap
1161 instruction be in a delay slot. */
1162 || (prev_pinfo & INSN_TRAP)
1163 /* If the branch reads a register that the previous
1164 instruction sets, we can not swap. */
1165 || ((prev_pinfo & INSN_WRITE_GPR_T)
1166 && insn_uses_reg (ip,
1167 ((prev_insn.insn_opcode >> OP_SH_RT)
1170 || ((prev_pinfo & INSN_WRITE_GPR_D)
1171 && insn_uses_reg (ip,
1172 ((prev_insn.insn_opcode >> OP_SH_RD)
1175 /* If the branch writes a register that the previous
1176 instruction sets, we can not swap (we know that
1177 branches write only to RD or to $31). */
1178 || ((prev_pinfo & INSN_WRITE_GPR_T)
1179 && (((pinfo & INSN_WRITE_GPR_D)
1180 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
1181 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1182 || ((pinfo & INSN_WRITE_GPR_31)
1183 && (((prev_insn.insn_opcode >> OP_SH_RT)
1186 || ((prev_pinfo & INSN_WRITE_GPR_D)
1187 && (((pinfo & INSN_WRITE_GPR_D)
1188 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
1189 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1190 || ((pinfo & INSN_WRITE_GPR_31)
1191 && (((prev_insn.insn_opcode >> OP_SH_RD)
1194 /* If the branch writes a register that the previous
1195 instruction reads, we can not swap (we know that
1196 branches only write to RD or to $31). */
1197 || ((pinfo & INSN_WRITE_GPR_D)
1198 && insn_uses_reg (&prev_insn,
1199 ((ip->insn_opcode >> OP_SH_RD)
1202 || ((pinfo & INSN_WRITE_GPR_31)
1203 && insn_uses_reg (&prev_insn, 31, 0))
1204 /* If we are generating embedded PIC code, the branch
1205 might be expanded into a sequence which uses $at, so
1206 we can't swap with an instruction which reads it. */
1207 || (mips_pic == EMBEDDED_PIC
1208 && insn_uses_reg (&prev_insn, AT, 0))
1209 /* If the previous previous instruction has a load
1210 delay, and sets a register that the branch reads, we
1213 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
1215 && (prev_prev_insn.insn_mo->pinfo
1216 & INSN_LOAD_MEMORY_DELAY)))
1217 && insn_uses_reg (ip,
1218 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
1222 /* We could do even better for unconditional branches to
1223 portions of this object file; we could pick up the
1224 instruction at the destination, put it in the delay
1225 slot, and bump the destination address. */
1227 /* Update the previous insn information. */
1228 prev_prev_insn = *ip;
1229 prev_insn.insn_mo = &dummy_opcode;
1236 /* It looks like we can actually do the swap. */
1237 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
1238 memcpy (temp, prev_f, 4);
1239 memcpy (prev_f, f, 4);
1240 memcpy (f, temp, 4);
1243 prev_insn_fixp->fx_frag = frag_now;
1244 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
1248 fixp->fx_frag = prev_insn_frag;
1249 fixp->fx_where = prev_insn_where;
1251 /* Update the previous insn information; leave prev_insn
1253 prev_prev_insn = *ip;
1255 prev_insn_is_delay_slot = 1;
1257 /* If that was an unconditional branch, forget the previous
1258 insn information. */
1259 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
1261 prev_prev_insn.insn_mo = &dummy_opcode;
1262 prev_insn.insn_mo = &dummy_opcode;
1265 else if (pinfo & INSN_COND_BRANCH_LIKELY)
1267 /* We don't yet optimize a branch likely. What we should do
1268 is look at the target, copy the instruction found there
1269 into the delay slot, and increment the branch to jump to
1270 the next instruction. */
1272 /* Update the previous insn information. */
1273 prev_prev_insn = *ip;
1274 prev_insn.insn_mo = &dummy_opcode;
1278 /* Update the previous insn information. */
1280 prev_prev_insn.insn_mo = &dummy_opcode;
1282 prev_prev_insn = prev_insn;
1285 /* Any time we see a branch, we always fill the delay slot
1286 immediately; since this insn is not a branch, we know it
1287 is not in a delay slot. */
1288 prev_insn_is_delay_slot = 0;
1291 prev_prev_insn_unreordered = prev_insn_unreordered;
1292 prev_insn_unreordered = 0;
1293 prev_insn_frag = frag_now;
1294 prev_insn_where = f - frag_now->fr_literal;
1295 prev_insn_fixp = fixp;
1296 prev_insn_valid = 1;
1299 /* We just output an insn, so the next one doesn't have a label. */
1303 /* This function forgets that there was any previous instruction or
1307 mips_no_prev_insn ()
1309 prev_insn.insn_mo = &dummy_opcode;
1310 prev_prev_insn.insn_mo = &dummy_opcode;
1311 prev_insn_valid = 0;
1312 prev_insn_is_delay_slot = 0;
1313 prev_insn_unreordered = 0;
1314 prev_prev_insn_unreordered = 0;
1318 /* This function must be called whenever we turn on noreorder or emit
1319 something other than instructions. It inserts any NOPS which might
1320 be needed by the previous instruction, and clears the information
1321 kept for the previous instructions. */
1326 if (! mips_noreorder)
1332 && (prev_insn.insn_mo->pinfo
1333 & (INSN_LOAD_COPROC_DELAY
1334 | INSN_COPROC_MOVE_DELAY
1335 | INSN_WRITE_COND_CODE)))
1337 && (prev_insn.insn_mo->pinfo
1341 && (prev_insn.insn_mo->pinfo
1342 & (INSN_LOAD_MEMORY_DELAY
1343 | INSN_COPROC_MEMORY_DELAY))))
1347 && (prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
1349 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
1350 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
1353 else if ((mips_isa < 4
1354 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
1356 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1357 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
1362 if (insn_label != NULL)
1364 assert (S_GET_SEGMENT (insn_label) == now_seg);
1365 insn_label->sy_frag = frag_now;
1366 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
1371 mips_no_prev_insn ();
1374 /* Build an instruction created by a macro expansion. This is passed
1375 a pointer to the count of instructions created so far, an
1376 expression, the name of the instruction to build, an operand format
1377 string, and corresponding arguments. */
1381 macro_build (char *place,
1389 macro_build (place, counter, ep, name, fmt, va_alist)
1398 struct mips_cl_insn insn;
1399 bfd_reloc_code_real_type r;
1403 va_start (args, fmt);
1409 * If the macro is about to expand into a second instruction,
1410 * print a warning if needed. We need to pass ip as a parameter
1411 * to generate a better warning message here...
1413 if (mips_warn_about_macros && place == NULL && *counter == 1)
1414 as_warn ("Macro instruction expanded into multiple instructions");
1417 *counter += 1; /* bump instruction counter */
1419 r = BFD_RELOC_UNUSED;
1420 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1421 assert (insn.insn_mo);
1422 assert (strcmp (name, insn.insn_mo->name) == 0);
1424 while (strcmp (fmt, insn.insn_mo->args) != 0
1425 || insn.insn_mo->pinfo == INSN_MACRO)
1428 assert (insn.insn_mo->name);
1429 assert (strcmp (name, insn.insn_mo->name) == 0);
1431 insn.insn_opcode = insn.insn_mo->match;
1447 insn.insn_opcode |= va_arg (args, int) << 16;
1453 insn.insn_opcode |= va_arg (args, int) << 16;
1458 insn.insn_opcode |= va_arg (args, int) << 11;
1463 insn.insn_opcode |= va_arg (args, int) << 11;
1470 insn.insn_opcode |= va_arg (args, int) << 6;
1474 insn.insn_opcode |= va_arg (args, int) << 6;
1478 insn.insn_opcode |= va_arg (args, int) << 6;
1485 insn.insn_opcode |= va_arg (args, int) << 21;
1491 r = (bfd_reloc_code_real_type) va_arg (args, int);
1492 assert (r == BFD_RELOC_MIPS_GPREL
1493 || r == BFD_RELOC_MIPS_LITERAL
1494 || r == BFD_RELOC_LO16
1495 || r == BFD_RELOC_MIPS_GOT16
1496 || r == BFD_RELOC_MIPS_CALL16
1497 || (ep->X_op == O_subtract
1498 && now_seg == text_section
1499 && r == BFD_RELOC_PCREL_LO16));
1503 r = (bfd_reloc_code_real_type) va_arg (args, int);
1505 && (ep->X_op == O_constant
1506 || (ep->X_op == O_symbol
1507 && (r == BFD_RELOC_HI16_S
1508 || r == BFD_RELOC_HI16))
1509 || (ep->X_op == O_subtract
1510 && now_seg == text_section
1511 && r == BFD_RELOC_PCREL_HI16_S)));
1512 if (ep->X_op == O_constant)
1514 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
1516 r = BFD_RELOC_UNUSED;
1521 assert (ep != NULL);
1523 * This allows macro() to pass an immediate expression for
1524 * creating short branches without creating a symbol.
1525 * Note that the expression still might come from the assembly
1526 * input, in which case the value is not checked for range nor
1527 * is a relocation entry generated (yuck).
1529 if (ep->X_op == O_constant)
1531 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
1535 r = BFD_RELOC_16_PCREL_S2;
1539 assert (ep != NULL);
1540 r = BFD_RELOC_MIPS_JMP;
1549 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1551 append_insn (place, &insn, ep, r);
1555 * Generate a "lui" instruction.
1558 macro_build_lui (place, counter, ep, regnum)
1564 expressionS high_expr;
1565 struct mips_cl_insn insn;
1566 bfd_reloc_code_real_type r;
1567 CONST char *name = "lui";
1568 CONST char *fmt = "t,u";
1574 high_expr.X_op = O_constant;
1575 high_expr.X_add_number = 0;
1578 if (high_expr.X_op == O_constant)
1580 /* we can compute the instruction now without a relocation entry */
1581 if (high_expr.X_add_number & 0x8000)
1582 high_expr.X_add_number += 0x10000;
1583 high_expr.X_add_number =
1584 ((unsigned long) high_expr.X_add_number >> 16) & 0xffff;
1585 r = BFD_RELOC_UNUSED;
1589 assert (ep->X_op == O_symbol);
1590 /* _gp_disp is a special case, used from s_cpload. */
1591 assert (mips_pic == NO_PIC
1592 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
1593 r = BFD_RELOC_HI16_S;
1597 * If the macro is about to expand into a second instruction,
1598 * print a warning if needed. We need to pass ip as a parameter
1599 * to generate a better warning message here...
1601 if (mips_warn_about_macros && place == NULL && *counter == 1)
1602 as_warn ("Macro instruction expanded into multiple instructions");
1605 *counter += 1; /* bump instruction counter */
1607 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1608 assert (insn.insn_mo);
1609 assert (strcmp (name, insn.insn_mo->name) == 0);
1610 assert (strcmp (fmt, insn.insn_mo->args) == 0);
1612 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
1613 if (r == BFD_RELOC_UNUSED)
1615 insn.insn_opcode |= high_expr.X_add_number;
1616 append_insn (place, &insn, NULL, r);
1619 append_insn (place, &insn, &high_expr, r);
1623 * Generates code to set the $at register to true (one)
1624 * if reg is less than the immediate expression.
1627 set_at (counter, reg, unsignedp)
1632 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1633 macro_build ((char *) NULL, counter, &imm_expr,
1634 unsignedp ? "sltiu" : "slti",
1635 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
1638 load_register (counter, AT, &imm_expr, 0);
1639 macro_build ((char *) NULL, counter, NULL,
1640 unsignedp ? "sltu" : "slt",
1641 "d,v,t", AT, reg, AT);
1645 /* Warn if an expression is not a constant. */
1648 check_absolute_expr (ip, ex)
1649 struct mips_cl_insn *ip;
1652 if (ex->X_op != O_constant)
1653 as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name);
1657 * This routine generates the least number of instructions neccessary to load
1658 * an absolute expression value into a register.
1661 load_register (counter, reg, ep, dbl)
1668 expressionS hi32, lo32, tmp;
1670 if (ep->X_op != O_big)
1672 assert (ep->X_op == O_constant);
1673 if (ep->X_add_number < 0x8000
1674 && (ep->X_add_number >= 0
1675 || (ep->X_add_number >= -0x8000
1678 || sizeof (ep->X_add_number) > 4))))
1680 /* We can handle 16 bit signed values with an addiu to
1681 $zero. No need to ever use daddiu here, since $zero and
1682 the result are always correct in 32 bit mode. */
1683 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
1684 (int) BFD_RELOC_LO16);
1687 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
1689 /* We can handle 16 bit unsigned values with an ori to
1691 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
1692 (int) BFD_RELOC_LO16);
1695 else if (((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
1696 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
1697 == ~ (offsetT) 0x7fffffff))
1700 || sizeof (ep->X_add_number) > 4
1701 || (ep->X_add_number & 0x80000000) == 0))
1703 /* 32 bit values require an lui. */
1704 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
1705 (int) BFD_RELOC_HI16);
1706 if ((ep->X_add_number & 0xffff) != 0)
1707 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
1708 (int) BFD_RELOC_LO16);
1713 /* 32 bit value with high bit set being loaded into a 64 bit
1714 register. We can't use lui, because that would
1715 incorrectly set the 32 high bits. */
1716 generic_bignum[3] = 0;
1717 generic_bignum[2] = 0;
1718 generic_bignum[1] = (ep->X_add_number >> 16) & 0xffff;
1719 generic_bignum[0] = ep->X_add_number & 0xffff;
1721 tmp.X_add_number = 4;
1726 /* The value is larger than 32 bits. */
1730 as_bad ("Number larger than 32 bits");
1731 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
1732 (int) BFD_RELOC_LO16);
1736 if (ep->X_op != O_big)
1740 hi32.X_add_number >>= shift;
1741 hi32.X_add_number &= 0xffffffff;
1742 if ((hi32.X_add_number & 0x80000000) != 0)
1743 hi32.X_add_number |= ~ (offsetT) 0xffffffff;
1745 lo32.X_add_number &= 0xffffffff;
1749 assert (ep->X_add_number > 2);
1750 if (ep->X_add_number == 3)
1751 generic_bignum[3] = 0;
1752 else if (ep->X_add_number > 4)
1753 as_bad ("Number larger than 64 bits");
1754 lo32.X_op = O_constant;
1755 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
1756 hi32.X_op = O_constant;
1757 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
1760 if (hi32.X_add_number == 0)
1764 load_register (counter, reg, &hi32, 0);
1767 if ((lo32.X_add_number & 0xffff0000) == 0)
1771 macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg,
1782 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
1787 mid16.X_add_number >>= 16;
1788 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
1789 freg, (int) BFD_RELOC_LO16);
1790 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
1794 if ((lo32.X_add_number & 0xffff) != 0)
1795 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
1796 (int) BFD_RELOC_LO16);
1799 /* Load an address into a register. */
1802 load_address (counter, reg, ep)
1809 if (ep->X_op != O_constant
1810 && ep->X_op != O_symbol)
1812 as_bad ("expression too complex");
1813 ep->X_op = O_constant;
1816 if (ep->X_op == O_constant)
1818 load_register (counter, reg, ep, 0);
1822 if (mips_pic == NO_PIC)
1824 /* If this is a reference to a GP relative symbol, we want
1825 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1827 lui $reg,<sym> (BFD_RELOC_HI16_S)
1828 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1829 If we have an addend, we always use the latter form. */
1830 if (ep->X_add_number != 0 || nopic_need_relax (ep->X_add_symbol))
1835 macro_build ((char *) NULL, counter, ep,
1836 mips_isa < 3 ? "addiu" : "daddiu",
1837 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
1838 p = frag_var (rs_machine_dependent, 8, 0,
1839 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros),
1840 ep->X_add_symbol, (long) 0, (char *) NULL);
1842 macro_build_lui (p, counter, ep, reg);
1845 macro_build (p, counter, ep,
1846 mips_isa < 3 ? "addiu" : "daddiu",
1847 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
1849 else if (mips_pic == SVR4_PIC)
1853 /* If this is a reference to an external symbol, we want
1854 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1856 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1858 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1859 If there is a constant, it must be added in after. */
1860 ex.X_add_number = ep->X_add_number;
1861 ep->X_add_number = 0;
1863 macro_build ((char *) NULL, counter, ep,
1864 mips_isa < 3 ? "lw" : "ld",
1865 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
1866 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
1867 p = frag_var (rs_machine_dependent, 4, 0,
1868 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros),
1869 ep->X_add_symbol, (long) 0, (char *) NULL);
1870 macro_build (p, counter, ep,
1871 mips_isa < 3 ? "addiu" : "daddiu",
1872 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
1873 if (ex.X_add_number != 0)
1875 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
1876 as_bad ("PIC code offset overflow (max 16 signed bits)");
1877 ex.X_op = O_constant;
1878 macro_build (p, counter, &ex,
1879 mips_isa < 3 ? "addiu" : "daddiu",
1880 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
1883 else if (mips_pic == EMBEDDED_PIC)
1886 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1888 macro_build ((char *) NULL, counter, ep,
1889 mips_isa < 3 ? "addiu" : "daddiu",
1890 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
1898 * This routine implements the seemingly endless macro or synthesized
1899 * instructions and addressing modes in the mips assembly language. Many
1900 * of these macros are simple and are similar to each other. These could
1901 * probably be handled by some kind of table or grammer aproach instead of
1902 * this verbose method. Others are not simple macros but are more like
1903 * optimizing code generation.
1904 * One interesting optimization is when several store macros appear
1905 * consecutivly that would load AT with the upper half of the same address.
1906 * The ensuing load upper instructions are ommited. This implies some kind
1907 * of global optimization. We currently only optimize within a single macro.
1908 * For many of the load and store macros if the address is specified as a
1909 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1910 * first load register 'at' with zero and use it as the base register. The
1911 * mips assembler simply uses register $zero. Just one tiny optimization
1916 struct mips_cl_insn *ip;
1918 register int treg, sreg, dreg, breg;
1933 bfd_reloc_code_real_type r;
1935 int hold_mips_optimize;
1937 treg = (ip->insn_opcode >> 16) & 0x1f;
1938 dreg = (ip->insn_opcode >> 11) & 0x1f;
1939 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
1940 mask = ip->insn_mo->mask;
1942 expr1.X_op = O_constant;
1943 expr1.X_op_symbol = NULL;
1944 expr1.X_add_symbol = NULL;
1945 expr1.X_add_number = 1;
1957 mips_emit_delays ();
1959 mips_any_noreorder = 1;
1961 expr1.X_add_number = 8;
1962 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
1964 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
1966 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0);
1967 macro_build ((char *) NULL, &icnt, NULL,
1968 dbl ? "dsub" : "sub",
1969 "d,v,t", dreg, 0, sreg);
1992 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1994 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
1995 (int) BFD_RELOC_LO16);
1998 load_register (&icnt, AT, &imm_expr, dbl);
1999 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
2018 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
2020 if (mask != M_NOR_I)
2021 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
2022 sreg, (int) BFD_RELOC_LO16);
2025 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
2026 treg, sreg, (int) BFD_RELOC_LO16);
2027 macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t",
2033 load_register (&icnt, AT, &imm_expr, 0);
2034 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
2051 if (imm_expr.X_add_number == 0)
2053 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
2057 load_register (&icnt, AT, &imm_expr, 0);
2058 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
2066 macro_build ((char *) NULL, &icnt, &offset_expr,
2067 likely ? "bgezl" : "bgez",
2073 macro_build ((char *) NULL, &icnt, &offset_expr,
2074 likely ? "blezl" : "blez",
2078 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
2079 macro_build ((char *) NULL, &icnt, &offset_expr,
2080 likely ? "beql" : "beq",
2087 /* check for > max integer */
2088 maxnum = 0x7fffffff;
2096 if (imm_expr.X_add_number >= maxnum
2097 && (mips_isa < 3 || sizeof (maxnum) > 4))
2100 /* result is always false */
2103 as_warn ("Branch %s is always false (nop)", ip->insn_mo->name);
2104 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2108 as_warn ("Branch likely %s is always false", ip->insn_mo->name);
2109 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
2114 imm_expr.X_add_number++;
2118 if (mask == M_BGEL_I)
2120 if (imm_expr.X_add_number == 0)
2122 macro_build ((char *) NULL, &icnt, &offset_expr,
2123 likely ? "bgezl" : "bgez",
2127 if (imm_expr.X_add_number == 1)
2129 macro_build ((char *) NULL, &icnt, &offset_expr,
2130 likely ? "bgtzl" : "bgtz",
2134 maxnum = 0x7fffffff;
2142 maxnum = - maxnum - 1;
2143 if (imm_expr.X_add_number <= maxnum
2144 && (mips_isa < 3 || sizeof (maxnum) > 4))
2147 /* result is always true */
2148 as_warn ("Branch %s is always true", ip->insn_mo->name);
2149 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
2152 set_at (&icnt, sreg, 0);
2153 macro_build ((char *) NULL, &icnt, &offset_expr,
2154 likely ? "beql" : "beq",
2165 macro_build ((char *) NULL, &icnt, &offset_expr,
2166 likely ? "beql" : "beq",
2170 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
2172 macro_build ((char *) NULL, &icnt, &offset_expr,
2173 likely ? "beql" : "beq",
2180 if (sreg == 0 || imm_expr.X_add_number == -1)
2182 imm_expr.X_add_number++;
2186 if (mask == M_BGEUL_I)
2188 if (imm_expr.X_add_number == 0)
2190 if (imm_expr.X_add_number == 1)
2192 macro_build ((char *) NULL, &icnt, &offset_expr,
2193 likely ? "bnel" : "bne",
2197 set_at (&icnt, sreg, 1);
2198 macro_build ((char *) NULL, &icnt, &offset_expr,
2199 likely ? "beql" : "beq",
2208 macro_build ((char *) NULL, &icnt, &offset_expr,
2209 likely ? "bgtzl" : "bgtz",
2215 macro_build ((char *) NULL, &icnt, &offset_expr,
2216 likely ? "bltzl" : "bltz",
2220 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
2221 macro_build ((char *) NULL, &icnt, &offset_expr,
2222 likely ? "bnel" : "bne",
2231 macro_build ((char *) NULL, &icnt, &offset_expr,
2232 likely ? "bnel" : "bne",
2238 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
2240 macro_build ((char *) NULL, &icnt, &offset_expr,
2241 likely ? "bnel" : "bne",
2250 macro_build ((char *) NULL, &icnt, &offset_expr,
2251 likely ? "blezl" : "blez",
2257 macro_build ((char *) NULL, &icnt, &offset_expr,
2258 likely ? "bgezl" : "bgez",
2262 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
2263 macro_build ((char *) NULL, &icnt, &offset_expr,
2264 likely ? "beql" : "beq",
2271 maxnum = 0x7fffffff;
2279 if (imm_expr.X_add_number >= maxnum
2280 && (mips_isa < 3 || sizeof (maxnum) > 4))
2282 imm_expr.X_add_number++;
2286 if (mask == M_BLTL_I)
2288 if (imm_expr.X_add_number == 0)
2290 macro_build ((char *) NULL, &icnt, &offset_expr,
2291 likely ? "bltzl" : "bltz",
2295 if (imm_expr.X_add_number == 1)
2297 macro_build ((char *) NULL, &icnt, &offset_expr,
2298 likely ? "blezl" : "blez",
2302 set_at (&icnt, sreg, 0);
2303 macro_build ((char *) NULL, &icnt, &offset_expr,
2304 likely ? "bnel" : "bne",
2313 macro_build ((char *) NULL, &icnt, &offset_expr,
2314 likely ? "beql" : "beq",
2320 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
2322 macro_build ((char *) NULL, &icnt, &offset_expr,
2323 likely ? "beql" : "beq",
2330 if (sreg == 0 || imm_expr.X_add_number == -1)
2332 imm_expr.X_add_number++;
2336 if (mask == M_BLTUL_I)
2338 if (imm_expr.X_add_number == 0)
2340 if (imm_expr.X_add_number == 1)
2342 macro_build ((char *) NULL, &icnt, &offset_expr,
2343 likely ? "beql" : "beq",
2347 set_at (&icnt, sreg, 1);
2348 macro_build ((char *) NULL, &icnt, &offset_expr,
2349 likely ? "bnel" : "bne",
2358 macro_build ((char *) NULL, &icnt, &offset_expr,
2359 likely ? "bltzl" : "bltz",
2365 macro_build ((char *) NULL, &icnt, &offset_expr,
2366 likely ? "bgtzl" : "bgtz",
2370 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
2371 macro_build ((char *) NULL, &icnt, &offset_expr,
2372 likely ? "bnel" : "bne",
2383 macro_build ((char *) NULL, &icnt, &offset_expr,
2384 likely ? "bnel" : "bne",
2388 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
2390 macro_build ((char *) NULL, &icnt, &offset_expr,
2391 likely ? "bnel" : "bne",
2407 as_warn ("Divide by zero.");
2409 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
2411 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2415 mips_emit_delays ();
2417 mips_any_noreorder = 1;
2418 macro_build ((char *) NULL, &icnt, NULL,
2419 dbl ? "ddiv" : "div",
2420 "z,s,t", sreg, treg);
2422 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
2425 expr1.X_add_number = 8;
2426 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
2427 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2428 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2430 expr1.X_add_number = -1;
2431 macro_build ((char *) NULL, &icnt, &expr1,
2432 dbl ? "daddiu" : "addiu",
2433 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
2434 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
2435 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
2438 expr1.X_add_number = 1;
2439 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
2440 (int) BFD_RELOC_LO16);
2441 macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT,
2446 expr1.X_add_number = 0x80000000;
2447 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
2448 (int) BFD_RELOC_HI16);
2451 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT);
2454 expr1.X_add_number = 8;
2455 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
2456 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2457 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
2460 macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg);
2499 if (imm_expr.X_add_number == 0)
2501 as_warn ("Divide by zero.");
2503 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
2505 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2508 if (imm_expr.X_add_number == 1)
2510 if (strcmp (s2, "mflo") == 0)
2511 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg,
2514 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
2517 if (imm_expr.X_add_number == -1
2518 && s[strlen (s) - 1] != 'u')
2520 if (strcmp (s2, "mflo") == 0)
2523 macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg,
2526 macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg,
2530 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
2534 load_register (&icnt, AT, &imm_expr, dbl);
2535 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
2536 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
2555 mips_emit_delays ();
2557 mips_any_noreorder = 1;
2558 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
2560 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
2563 expr1.X_add_number = 8;
2564 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
2565 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
2566 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
2569 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
2575 /* Load the address of a symbol into a register. If breg is not
2576 zero, we then add a base register to it. */
2578 /* When generating embedded PIC code, we permit expressions of
2581 where bar is an address in the .text section. These are used
2582 when getting the addresses of functions. We don't permit
2583 X_add_number to be non-zero, because if the symbol is
2584 external the relaxing code needs to know that any addend is
2585 purely the offset to X_op_symbol. */
2586 if (mips_pic == EMBEDDED_PIC
2587 && offset_expr.X_op == O_subtract
2588 && now_seg == text_section
2589 && (offset_expr.X_op_symbol->sy_value.X_op == O_constant
2590 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section
2591 : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol
2592 && (S_GET_SEGMENT (offset_expr.X_op_symbol
2593 ->sy_value.X_add_symbol)
2596 && offset_expr.X_add_number == 0)
2598 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
2599 treg, (int) BFD_RELOC_PCREL_HI16_S);
2600 macro_build ((char *) NULL, &icnt, &offset_expr,
2601 mips_isa < 3 ? "addiu" : "daddiu",
2602 "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
2606 if (offset_expr.X_op != O_symbol
2607 && offset_expr.X_op != O_constant)
2609 as_bad ("expression too complex");
2610 offset_expr.X_op = O_constant;
2624 if (offset_expr.X_op == O_constant)
2625 load_register (&icnt, tempreg, &offset_expr, dbl);
2626 else if (mips_pic == NO_PIC)
2628 /* If this is a reference to an GP relative symbol, we want
2629 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2631 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2632 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2633 If we have a constant, we need two instructions anyhow,
2634 so we may as well always use the latter form. */
2635 if (offset_expr.X_add_number != 0
2636 || nopic_need_relax (offset_expr.X_add_symbol))
2641 macro_build ((char *) NULL, &icnt, &offset_expr,
2642 mips_isa < 3 ? "addiu" : "daddiu",
2643 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
2644 p = frag_var (rs_machine_dependent, 8, 0,
2645 RELAX_ENCODE (4, 8, 0, 4, 0,
2646 mips_warn_about_macros),
2647 offset_expr.X_add_symbol, (long) 0,
2650 macro_build_lui (p, &icnt, &offset_expr, tempreg);
2653 macro_build (p, &icnt, &offset_expr,
2654 mips_isa < 3 ? "addiu" : "daddiu",
2655 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
2657 else if (mips_pic == SVR4_PIC)
2659 /* If this is a reference to an external symbol, and there
2660 is no constant, we want
2661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2662 For a local symbol, we want
2663 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2665 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2667 If we have a small constant, and this is a reference to
2668 an external symbol, we want
2669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2671 addiu $tempreg,$tempreg,<constant>
2672 For a local symbol, we want the same instruction
2673 sequence, but we output a BFD_RELOC_LO16 reloc on the
2676 If we have a large constant, and this is a reference to
2677 an external symbol, we want
2678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2679 lui $at,<hiconstant>
2680 addiu $at,$at,<loconstant>
2681 addu $tempreg,$tempreg,$at
2682 For a local symbol, we want the same instruction
2683 sequence, but we output a BFD_RELOC_LO16 reloc on the
2684 addiu instruction. */
2685 expr1.X_add_number = offset_expr.X_add_number;
2686 offset_expr.X_add_number = 0;
2688 macro_build ((char *) NULL, &icnt, &offset_expr,
2690 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
2691 if (expr1.X_add_number == 0)
2699 /* We're going to put in an addu instruction using
2700 tempreg, so we may as well insert the nop right
2702 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2706 p = frag_var (rs_machine_dependent, 8 - off, 0,
2707 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
2709 ? mips_warn_about_macros
2711 offset_expr.X_add_symbol, (long) 0,
2715 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
2718 macro_build (p, &icnt, &expr1,
2719 mips_isa < 3 ? "addiu" : "daddiu",
2720 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
2721 /* FIXME: If breg == 0, and the next instruction uses
2722 $tempreg, then if this variant case is used an extra
2723 nop will be generated. */
2725 else if (expr1.X_add_number >= -0x8000
2726 && expr1.X_add_number < 0x8000)
2728 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2730 macro_build ((char *) NULL, &icnt, &expr1,
2731 mips_isa < 3 ? "addiu" : "daddiu",
2732 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
2733 (void) frag_var (rs_machine_dependent, 0, 0,
2734 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2735 offset_expr.X_add_symbol, (long) 0,
2742 /* If we are going to add in a base register, and the
2743 target register and the base register are the same,
2744 then we are using AT as a temporary register. Since
2745 we want to load the constant into AT, we add our
2746 current AT (from the global offset table) and the
2747 register into the register now, and pretend we were
2748 not using a base register. */
2753 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2755 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2756 mips_isa < 3 ? "addu" : "daddu",
2757 "d,v,t", treg, AT, breg);
2763 /* Set mips_optimize around the lui instruction to avoid
2764 inserting an unnecessary nop after the lw. */
2765 hold_mips_optimize = mips_optimize;
2767 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
2768 mips_optimize = hold_mips_optimize;
2770 macro_build ((char *) NULL, &icnt, &expr1,
2771 mips_isa < 3 ? "addiu" : "daddiu",
2772 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
2773 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2774 mips_isa < 3 ? "addu" : "daddu",
2775 "d,v,t", tempreg, tempreg, AT);
2776 (void) frag_var (rs_machine_dependent, 0, 0,
2777 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
2778 offset_expr.X_add_symbol, (long) 0,
2783 else if (mips_pic == EMBEDDED_PIC)
2786 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2788 macro_build ((char *) NULL, &icnt, &offset_expr,
2789 mips_isa < 3 ? "addiu" : "daddiu",
2790 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
2796 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2797 mips_isa < 3 ? "addu" : "daddu",
2798 "d,v,t", treg, tempreg, breg);
2806 /* The j instruction may not be used in PIC code, since it
2807 requires an absolute address. We convert it to a b
2809 if (mips_pic == NO_PIC)
2810 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
2812 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
2815 /* The jal instructions must be handled as macros because when
2816 generating PIC code they expand to multi-instruction
2817 sequences. Normally they are simple instructions. */
2822 if (mips_pic == NO_PIC
2823 || mips_pic == EMBEDDED_PIC)
2824 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
2826 else if (mips_pic == SVR4_PIC)
2828 if (sreg != PIC_CALL_REG)
2829 as_warn ("MIPS PIC call to register other than $25");
2831 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
2833 if (mips_cprestore_offset < 0)
2834 as_warn ("No .cprestore pseudo-op used in PIC code");
2837 expr1.X_add_number = mips_cprestore_offset;
2838 macro_build ((char *) NULL, &icnt, &expr1,
2839 mips_isa < 3 ? "lw" : "ld",
2840 "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
2849 if (mips_pic == NO_PIC)
2850 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
2851 else if (mips_pic == SVR4_PIC)
2853 /* If this is a reference to an external symbol, we want
2854 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2858 lw $gp,cprestore($sp)
2859 The cprestore value is set using the .cprestore
2860 pseudo-op. If the symbol is not external, we want
2861 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2863 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2866 lw $gp,cprestore($sp)
2869 macro_build ((char *) NULL, &icnt, &offset_expr,
2870 mips_isa < 3 ? "lw" : "ld",
2871 "t,o(b)", PIC_CALL_REG,
2872 (int) BFD_RELOC_MIPS_CALL16, GP);
2873 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
2874 p = frag_var (rs_machine_dependent, 4, 0,
2875 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2876 offset_expr.X_add_symbol, (long) 0, (char *) NULL);
2877 macro_build (p, &icnt, &offset_expr,
2878 mips_isa < 3 ? "addiu" : "daddiu",
2879 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
2880 (int) BFD_RELOC_LO16);
2881 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2882 "jalr", "s", PIC_CALL_REG);
2883 if (mips_cprestore_offset < 0)
2884 as_warn ("No .cprestore pseudo-op used in PIC code");
2888 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
2890 expr1.X_add_number = mips_cprestore_offset;
2891 macro_build ((char *) NULL, &icnt, &expr1,
2892 mips_isa < 3 ? "lw" : "ld",
2893 "t,o(b)", GP, (int) BFD_RELOC_LO16,
2897 else if (mips_pic == EMBEDDED_PIC)
2899 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
2900 /* The linker may expand the call to a longer sequence which
2901 uses $at, so we must break rather than return. */
2977 if (breg == treg || coproc || lr)
3046 if (mask == M_LWC1_AB
3047 || mask == M_SWC1_AB
3048 || mask == M_LDC1_AB
3049 || mask == M_SDC1_AB
3058 if (offset_expr.X_op != O_constant
3059 && offset_expr.X_op != O_symbol)
3061 as_bad ("expression too complex");
3062 offset_expr.X_op = O_constant;
3065 /* A constant expression in PIC code can be handled just as it
3066 is in non PIC code. */
3067 if (mips_pic == NO_PIC
3068 || offset_expr.X_op == O_constant)
3070 /* If this is a reference to a GP relative symbol, and there
3071 is no base register, we want
3072 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3073 Otherwise, if there is no base register, we want
3074 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3075 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3076 If we have a constant, we need two instructions anyhow,
3077 so we always use the latter form.
3079 If we have a base register, and this is a reference to a
3080 GP relative symbol, we want
3081 addu $tempreg,$breg,$gp
3082 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3084 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3085 addu $tempreg,$tempreg,$breg
3086 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3087 With a constant we always use the latter case. */
3090 if (offset_expr.X_add_number != 0
3091 || nopic_need_relax (offset_expr.X_add_symbol))
3096 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3097 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
3098 p = frag_var (rs_machine_dependent, 8, 0,
3099 RELAX_ENCODE (4, 8, 0, 4, 0,
3100 (mips_warn_about_macros
3101 || (used_at && mips_noat))),
3102 offset_expr.X_add_symbol, (long) 0,
3106 macro_build_lui (p, &icnt, &offset_expr, tempreg);
3109 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
3110 (int) BFD_RELOC_LO16, tempreg);
3114 if (offset_expr.X_add_number != 0
3115 || nopic_need_relax (offset_expr.X_add_symbol))
3120 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3121 mips_isa < 3 ? "addu" : "daddu",
3122 "d,v,t", tempreg, breg, GP);
3123 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3124 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
3125 p = frag_var (rs_machine_dependent, 12, 0,
3126 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3127 offset_expr.X_add_symbol, (long) 0,
3130 macro_build_lui (p, &icnt, &offset_expr, tempreg);
3133 macro_build (p, &icnt, (expressionS *) NULL,
3134 mips_isa < 3 ? "addu" : "daddu",
3135 "d,v,t", tempreg, tempreg, breg);
3138 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
3139 (int) BFD_RELOC_LO16, tempreg);
3142 else if (mips_pic == SVR4_PIC)
3144 /* If this is a reference to an external symbol, we want
3145 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3147 <op> $treg,0($tempreg)
3149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3151 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3152 <op> $treg,0($tempreg)
3153 If there is a base register, we add it to $tempreg before
3154 the <op>. If there is a constant, we stick it in the
3155 <op> instruction. We don't handle constants larger than
3156 16 bits, because we have no way to load the upper 16 bits
3157 (actually, we could handle them for the subset of cases
3158 in which we are not using $at). */
3159 assert (offset_expr.X_op == O_symbol);
3160 expr1.X_add_number = offset_expr.X_add_number;
3161 offset_expr.X_add_number = 0;
3162 if (expr1.X_add_number < -0x8000
3163 || expr1.X_add_number >= 0x8000)
3164 as_bad ("PIC code offset overflow (max 16 signed bits)");
3166 macro_build ((char *) NULL, &icnt, &offset_expr,
3167 mips_isa < 3 ? "lw" : "ld",
3168 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
3169 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
3170 p = frag_var (rs_machine_dependent, 4, 0,
3171 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3172 offset_expr.X_add_symbol, (long) 0,
3174 macro_build (p, &icnt, &offset_expr,
3175 mips_isa < 3 ? "addiu" : "daddiu",
3176 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
3178 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3179 mips_isa < 3 ? "addu" : "daddu",
3180 "d,v,t", tempreg, tempreg, breg);
3181 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
3182 (int) BFD_RELOC_LO16, tempreg);
3184 else if (mips_pic == EMBEDDED_PIC)
3186 /* If there is no base register, we want
3187 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3188 If there is a base register, we want
3189 addu $tempreg,$breg,$gp
3190 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3192 assert (offset_expr.X_op == O_symbol);
3195 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3196 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
3201 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3202 mips_isa < 3 ? "addu" : "daddu",
3203 "d,v,t", tempreg, breg, GP);
3204 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3205 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
3218 load_register (&icnt, treg, &imm_expr, 0);
3222 load_register (&icnt, treg, &imm_expr, 1);
3226 if (imm_expr.X_op == O_constant)
3228 load_register (&icnt, AT, &imm_expr, 0);
3229 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3230 "mtc1", "t,G", AT, treg);
3235 assert (offset_expr.X_op == O_symbol
3236 && strcmp (segment_name (S_GET_SEGMENT
3237 (offset_expr.X_add_symbol)),
3239 && offset_expr.X_add_number == 0);
3240 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
3241 treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
3246 /* We know that sym is in the .rdata section. First we get the
3247 upper 16 bits of the address. */
3248 if (mips_pic == NO_PIC)
3250 /* FIXME: This won't work for a 64 bit address. */
3251 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
3253 else if (mips_pic == SVR4_PIC)
3255 macro_build ((char *) NULL, &icnt, &offset_expr,
3256 mips_isa < 3 ? "lw" : "ld",
3257 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
3259 else if (mips_pic == EMBEDDED_PIC)
3261 /* For embedded PIC we pick up the entire address off $gp in
3262 a single instruction. */
3263 macro_build ((char *) NULL, &icnt, &offset_expr,
3264 mips_isa < 3 ? "addiu" : "daddiu",
3265 "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
3266 offset_expr.X_op = O_constant;
3267 offset_expr.X_add_number = 0;
3272 /* Now we load the register(s). */
3274 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
3275 treg, (int) BFD_RELOC_LO16, AT);
3278 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
3279 treg, (int) BFD_RELOC_LO16, AT);
3282 /* FIXME: How in the world do we deal with the possible
3284 offset_expr.X_add_number += 4;
3285 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
3286 treg + 1, (int) BFD_RELOC_LO16, AT);
3290 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3291 does not become a variant frag. */
3292 frag_wane (frag_now);
3298 assert (offset_expr.X_op == O_symbol
3299 && offset_expr.X_add_number == 0);
3300 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
3301 if (strcmp (s, ".lit8") == 0)
3305 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
3306 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
3310 r = BFD_RELOC_MIPS_LITERAL;
3315 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
3316 if (mips_pic == SVR4_PIC)
3317 macro_build ((char *) NULL, &icnt, &offset_expr,
3318 mips_isa < 3 ? "lw" : "ld",
3319 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
3322 /* FIXME: This won't work for a 64 bit address. */
3323 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
3328 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
3329 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
3331 /* To avoid confusion in tc_gen_reloc, we must ensure
3332 that this does not become a variant frag. */
3333 frag_wane (frag_now);
3344 /* Even on a big endian machine $fn comes before $fn+1. We have
3345 to adjust when loading from memory. */
3348 assert (mips_isa < 2);
3349 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
3350 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
3352 /* FIXME: A possible overflow which I don't know how to deal
3354 offset_expr.X_add_number += 4;
3355 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
3356 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
3359 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3360 does not become a variant frag. */
3361 frag_wane (frag_now);
3370 * The MIPS assembler seems to check for X_add_number not
3371 * being double aligned and generating:
3374 * addiu at,at,%lo(foo+1)
3377 * But, the resulting address is the same after relocation so why
3378 * generate the extra instruction?
3425 if (offset_expr.X_op != O_symbol
3426 && offset_expr.X_op != O_constant)
3428 as_bad ("expression too complex");
3429 offset_expr.X_op = O_constant;
3432 /* Even on a big endian machine $fn comes before $fn+1. We have
3433 to adjust when loading from memory. We set coproc if we must
3434 load $fn+1 first. */
3435 if (byte_order == LITTLE_ENDIAN)
3438 if (mips_pic == NO_PIC
3439 || offset_expr.X_op == O_constant)
3441 /* If this is a reference to a GP relative symbol, we want
3442 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3443 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3444 If we have a base register, we use this
3446 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3447 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3448 If this is not a GP relative symbol, we want
3449 lui $at,<sym> (BFD_RELOC_HI16_S)
3450 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3451 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3452 If there is a base register, we add it to $at after the
3453 lui instruction. If there is a constant, we always use
3455 if (offset_expr.X_add_number != 0
3456 || nopic_need_relax (offset_expr.X_add_symbol))
3475 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3476 mips_isa < 3 ? "addu" : "daddu",
3477 "d,v,t", AT, breg, GP);
3483 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3484 coproc ? treg + 1 : treg,
3485 (int) BFD_RELOC_MIPS_GPREL, tempreg);
3486 offset_expr.X_add_number += 4;
3488 /* Set mips_optimize to 2 to avoid inserting an
3490 hold_mips_optimize = mips_optimize;
3492 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3493 coproc ? treg : treg + 1,
3494 (int) BFD_RELOC_MIPS_GPREL, tempreg);
3495 mips_optimize = hold_mips_optimize;
3497 p = frag_var (rs_machine_dependent, 12 + off, 0,
3498 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
3499 used_at && mips_noat),
3500 offset_expr.X_add_symbol, (long) 0,
3503 /* We just generated two relocs. When tc_gen_reloc
3504 handles this case, it will skip the first reloc and
3505 handle the second. The second reloc already has an
3506 extra addend of 4, which we added above. We must
3507 subtract it out, and then subtract another 4 to make
3508 the first reloc come out right. The second reloc
3509 will come out right because we are going to add 4 to
3510 offset_expr when we build its instruction below. */
3511 offset_expr.X_add_number -= 8;
3512 offset_expr.X_op = O_constant;
3514 macro_build_lui (p, &icnt, &offset_expr, AT);
3519 macro_build (p, &icnt, (expressionS *) NULL,
3520 mips_isa < 3 ? "addu" : "daddu",
3521 "d,v,t", AT, breg, AT);
3525 macro_build (p, &icnt, &offset_expr, s, fmt,
3526 coproc ? treg + 1 : treg,
3527 (int) BFD_RELOC_LO16, AT);
3530 /* FIXME: How do we handle overflow here? */
3531 offset_expr.X_add_number += 4;
3532 macro_build (p, &icnt, &offset_expr, s, fmt,
3533 coproc ? treg : treg + 1,
3534 (int) BFD_RELOC_LO16, AT);
3536 else if (mips_pic == SVR4_PIC)
3540 /* If this is a reference to an external symbol, we want
3541 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3546 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3548 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3549 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3550 If there is a base register we add it to $at before the
3551 lwc1 instructions. If there is a constant we include it
3552 in the lwc1 instructions. */
3554 expr1.X_add_number = offset_expr.X_add_number;
3555 offset_expr.X_add_number = 0;
3556 if (expr1.X_add_number < -0x8000
3557 || expr1.X_add_number >= 0x8000 - 4)
3558 as_bad ("PIC code offset overflow (max 16 signed bits)");
3563 frag_grow (24 + off);
3564 macro_build ((char *) NULL, &icnt, &offset_expr,
3565 mips_isa < 3 ? "lw" : "ld",
3566 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
3567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
3569 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3570 mips_isa < 3 ? "addu" : "daddu",
3571 "d,v,t", AT, breg, AT);
3572 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
3573 coproc ? treg + 1 : treg,
3574 (int) BFD_RELOC_LO16, AT);
3575 expr1.X_add_number += 4;
3577 /* Set mips_optimize to 2 to avoid inserting an undesired
3579 hold_mips_optimize = mips_optimize;
3581 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
3582 coproc ? treg : treg + 1,
3583 (int) BFD_RELOC_LO16, AT);
3584 mips_optimize = hold_mips_optimize;
3586 (void) frag_var (rs_machine_dependent, 0, 0,
3587 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
3588 offset_expr.X_add_symbol, (long) 0,
3591 else if (mips_pic == EMBEDDED_PIC)
3593 /* If there is no base register, we use
3594 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3595 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3596 If we have a base register, we use
3598 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3599 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3608 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3609 mips_isa < 3 ? "addu" : "daddu",
3610 "d,v,t", AT, breg, GP);
3615 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3616 coproc ? treg + 1 : treg,
3617 (int) BFD_RELOC_MIPS_GPREL, tempreg);
3618 offset_expr.X_add_number += 4;
3619 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
3620 coproc ? treg : treg + 1,
3621 (int) BFD_RELOC_MIPS_GPREL, tempreg);
3637 assert (mips_isa < 3);
3638 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
3639 (int) BFD_RELOC_LO16, breg);
3640 offset_expr.X_add_number += 4;
3641 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
3642 (int) BFD_RELOC_LO16, breg);
3644 #ifdef LOSING_COMPILER
3650 as_warn ("Macro used $at after \".set noat\"");
3655 struct mips_cl_insn *ip;
3657 register int treg, sreg, dreg, breg;
3672 bfd_reloc_code_real_type r;
3675 treg = (ip->insn_opcode >> 16) & 0x1f;
3676 dreg = (ip->insn_opcode >> 11) & 0x1f;
3677 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3678 mask = ip->insn_mo->mask;
3680 expr1.X_op = O_constant;
3681 expr1.X_op_symbol = NULL;
3682 expr1.X_add_symbol = NULL;
3683 expr1.X_add_number = 1;
3687 #endif /* LOSING_COMPILER */
3692 macro_build ((char *) NULL, &icnt, NULL,
3693 dbl ? "dmultu" : "multu",
3695 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
3701 /* The MIPS assembler some times generates shifts and adds. I'm
3702 not trying to be that fancy. GCC should do this for us
3704 load_register (&icnt, AT, &imm_expr, dbl);
3705 macro_build ((char *) NULL, &icnt, NULL,
3706 dbl ? "dmult" : "mult",
3708 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
3714 mips_emit_delays ();
3716 mips_any_noreorder = 1;
3717 macro_build ((char *) NULL, &icnt, NULL,
3718 dbl ? "dmult" : "mult",
3720 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
3721 macro_build ((char *) NULL, &icnt, NULL,
3722 dbl ? "dsra32" : "sra",
3723 "d,w,<", dreg, dreg, 31);
3724 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
3726 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT);
3729 expr1.X_add_number = 8;
3730 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
3731 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
3732 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
3735 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
3741 mips_emit_delays ();
3743 mips_any_noreorder = 1;
3744 macro_build ((char *) NULL, &icnt, NULL,
3745 dbl ? "dmultu" : "multu",
3747 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
3748 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
3750 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0);
3753 expr1.X_add_number = 8;
3754 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
3755 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
3756 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
3762 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
3763 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
3764 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg,
3766 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
3770 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg,
3771 imm_expr.X_add_number & 0x1f);
3772 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
3773 (0 - imm_expr.X_add_number) & 0x1f);
3774 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
3778 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
3779 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
3780 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg,
3782 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
3786 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg,
3787 imm_expr.X_add_number & 0x1f);
3788 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
3789 (0 - imm_expr.X_add_number) & 0x1f);
3790 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
3794 assert (mips_isa < 2);
3795 /* Even on a big endian machine $fn comes before $fn+1. We have
3796 to adjust when storing to memory. */
3797 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
3798 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
3799 (int) BFD_RELOC_LO16, breg);
3800 offset_expr.X_add_number += 4;
3801 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
3802 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
3803 (int) BFD_RELOC_LO16, breg);
3808 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
3809 treg, (int) BFD_RELOC_LO16);
3811 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
3812 sreg, (int) BFD_RELOC_LO16);
3815 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
3817 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
3818 dreg, (int) BFD_RELOC_LO16);
3823 if (imm_expr.X_add_number == 0)
3825 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
3826 sreg, (int) BFD_RELOC_LO16);
3831 as_warn ("Instruction %s: result is always false",
3833 macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0);
3836 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
3838 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
3839 sreg, (int) BFD_RELOC_LO16);
3842 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
3844 imm_expr.X_add_number = -imm_expr.X_add_number;
3845 macro_build ((char *) NULL, &icnt, &imm_expr,
3846 mips_isa < 3 ? "addiu" : "daddiu",
3847 "t,r,j", dreg, sreg,
3848 (int) BFD_RELOC_LO16);
3853 load_register (&icnt, AT, &imm_expr, 0);
3854 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
3858 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
3859 (int) BFD_RELOC_LO16);
3864 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
3870 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
3871 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
3872 (int) BFD_RELOC_LO16);
3875 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
3877 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
3879 macro_build ((char *) NULL, &icnt, &expr1,
3880 mask == M_SGE_I ? "slti" : "sltiu",
3881 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
3886 load_register (&icnt, AT, &imm_expr, 0);
3887 macro_build ((char *) NULL, &icnt, NULL,
3888 mask == M_SGE_I ? "slt" : "sltu",
3889 "d,v,t", dreg, sreg, AT);
3892 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
3893 (int) BFD_RELOC_LO16);
3898 case M_SGT: /* sreg > treg <==> treg < sreg */
3904 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
3907 case M_SGT_I: /* sreg > I <==> I < sreg */
3913 load_register (&icnt, AT, &imm_expr, 0);
3914 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
3917 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3923 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
3924 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
3925 (int) BFD_RELOC_LO16);
3928 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3934 load_register (&icnt, AT, &imm_expr, 0);
3935 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
3936 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
3937 (int) BFD_RELOC_LO16);
3941 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
3943 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
3944 dreg, sreg, (int) BFD_RELOC_LO16);
3947 load_register (&icnt, AT, &imm_expr, 0);
3948 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
3952 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
3954 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
3955 dreg, sreg, (int) BFD_RELOC_LO16);
3958 load_register (&icnt, AT, &imm_expr, 0);
3959 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg,
3965 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
3968 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
3972 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
3974 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
3980 if (imm_expr.X_add_number == 0)
3982 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
3988 as_warn ("Instruction %s: result is always true",
3990 macro_build ((char *) NULL, &icnt, &expr1,
3991 mips_isa < 3 ? "addiu" : "daddiu",
3992 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
3995 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
3997 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
3998 dreg, sreg, (int) BFD_RELOC_LO16);
4001 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
4003 imm_expr.X_add_number = -imm_expr.X_add_number;
4004 macro_build ((char *) NULL, &icnt, &imm_expr,
4005 mips_isa < 3 ? "addiu" : "daddiu",
4006 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
4011 load_register (&icnt, AT, &imm_expr, 0);
4012 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
4016 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
4024 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
4026 imm_expr.X_add_number = -imm_expr.X_add_number;
4027 macro_build ((char *) NULL, &icnt, &imm_expr,
4028 dbl ? "daddi" : "addi",
4029 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
4032 load_register (&icnt, AT, &imm_expr, dbl);
4033 macro_build ((char *) NULL, &icnt, NULL,
4034 dbl ? "dsub" : "sub",
4035 "d,v,t", dreg, sreg, AT);
4041 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
4043 imm_expr.X_add_number = -imm_expr.X_add_number;
4044 macro_build ((char *) NULL, &icnt, &imm_expr,
4045 dbl ? "daddiu" : "addiu",
4046 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
4049 load_register (&icnt, AT, &imm_expr, dbl);
4050 macro_build ((char *) NULL, &icnt, NULL,
4051 dbl ? "dsubu" : "subu",
4052 "d,v,t", dreg, sreg, AT);
4073 load_register (&icnt, AT, &imm_expr, 0);
4074 macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT);
4079 assert (mips_isa < 2);
4080 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
4081 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
4084 * Is the double cfc1 instruction a bug in the mips assembler;
4085 * or is there a reason for it?
4087 mips_emit_delays ();
4089 mips_any_noreorder = 1;
4090 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
4091 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
4092 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
4093 expr1.X_add_number = 3;
4094 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
4095 (int) BFD_RELOC_LO16);
4096 expr1.X_add_number = 2;
4097 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
4098 (int) BFD_RELOC_LO16);
4099 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31);
4100 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
4101 macro_build ((char *) NULL, &icnt, NULL,
4102 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
4103 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31);
4104 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
4114 if (offset_expr.X_add_number >= 0x7fff)
4115 as_bad ("operand overflow");
4116 /* avoid load delay */
4117 if (byte_order == LITTLE_ENDIAN)
4118 offset_expr.X_add_number += 1;
4119 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
4120 (int) BFD_RELOC_LO16, breg);
4121 if (byte_order == LITTLE_ENDIAN)
4122 offset_expr.X_add_number -= 1;
4124 offset_expr.X_add_number += 1;
4125 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
4126 (int) BFD_RELOC_LO16, breg);
4127 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
4128 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
4141 if (offset_expr.X_add_number >= 0x8000 - off)
4142 as_bad ("operand overflow");
4143 if (byte_order == LITTLE_ENDIAN)
4144 offset_expr.X_add_number += off;
4145 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
4146 (int) BFD_RELOC_LO16, breg);
4147 if (byte_order == LITTLE_ENDIAN)
4148 offset_expr.X_add_number -= off;
4150 offset_expr.X_add_number += off;
4151 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
4152 (int) BFD_RELOC_LO16, breg);
4165 load_address (&icnt, AT, &offset_expr);
4166 if (byte_order == LITTLE_ENDIAN)
4167 expr1.X_add_number = off;
4169 expr1.X_add_number = 0;
4170 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
4171 (int) BFD_RELOC_LO16, AT);
4172 if (byte_order == LITTLE_ENDIAN)
4173 expr1.X_add_number = 0;
4175 expr1.X_add_number = off;
4176 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
4177 (int) BFD_RELOC_LO16, AT);
4182 load_address (&icnt, AT, &offset_expr);
4183 if (byte_order == BIG_ENDIAN)
4184 expr1.X_add_number = 0;
4185 macro_build ((char *) NULL, &icnt, &expr1,
4186 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
4187 (int) BFD_RELOC_LO16, AT);
4188 if (byte_order == BIG_ENDIAN)
4189 expr1.X_add_number = 1;
4191 expr1.X_add_number = 0;
4192 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
4193 (int) BFD_RELOC_LO16, AT);
4194 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
4196 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
4201 if (offset_expr.X_add_number >= 0x7fff)
4202 as_bad ("operand overflow");
4203 if (byte_order == BIG_ENDIAN)
4204 offset_expr.X_add_number += 1;
4205 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
4206 (int) BFD_RELOC_LO16, breg);
4207 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
4208 if (byte_order == BIG_ENDIAN)
4209 offset_expr.X_add_number -= 1;
4211 offset_expr.X_add_number += 1;
4212 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
4213 (int) BFD_RELOC_LO16, breg);
4226 if (offset_expr.X_add_number >= 0x8000 - off)
4227 as_bad ("operand overflow");
4228 if (byte_order == LITTLE_ENDIAN)
4229 offset_expr.X_add_number += off;
4230 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
4231 (int) BFD_RELOC_LO16, breg);
4232 if (byte_order == LITTLE_ENDIAN)
4233 offset_expr.X_add_number -= off;
4235 offset_expr.X_add_number += off;
4236 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
4237 (int) BFD_RELOC_LO16, breg);
4250 load_address (&icnt, AT, &offset_expr);
4251 if (byte_order == LITTLE_ENDIAN)
4252 expr1.X_add_number = off;
4254 expr1.X_add_number = 0;
4255 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
4256 (int) BFD_RELOC_LO16, AT);
4257 if (byte_order == LITTLE_ENDIAN)
4258 expr1.X_add_number = 0;
4260 expr1.X_add_number = off;
4261 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
4262 (int) BFD_RELOC_LO16, AT);
4266 load_address (&icnt, AT, &offset_expr);
4267 if (byte_order == LITTLE_ENDIAN)
4268 expr1.X_add_number = 0;
4269 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
4270 (int) BFD_RELOC_LO16, AT);
4271 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg,
4273 if (byte_order == LITTLE_ENDIAN)
4274 expr1.X_add_number = 1;
4276 expr1.X_add_number = 0;
4277 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
4278 (int) BFD_RELOC_LO16, AT);
4279 if (byte_order == LITTLE_ENDIAN)
4280 expr1.X_add_number = 0;
4282 expr1.X_add_number = 1;
4283 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
4284 (int) BFD_RELOC_LO16, AT);
4285 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
4287 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
4292 as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
4296 as_warn ("Macro used $at after \".set noat\"");
4301 This routine assembles an instruction into its binary format. As a side
4302 effect it sets one of the global variables imm_reloc or offset_reloc to the
4303 type of relocation to do if one of the operands is an address expression.
4308 struct mips_cl_insn *ip;
4313 struct mips_opcode *insn;
4316 unsigned int lastregno = 0;
4321 for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s)
4333 as_fatal ("Unknown opcode: `%s'", str);
4335 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
4337 as_warn ("`%s' not in hash table.", str);
4338 insn_error = "ERROR: Unrecognized opcode";
4346 assert (strcmp (insn->name, str) == 0);
4348 if (insn->pinfo == INSN_MACRO)
4349 insn_isa = insn->match;
4350 else if ((insn->pinfo & INSN_ISA) == INSN_ISA2)
4352 else if ((insn->pinfo & INSN_ISA) == INSN_ISA3)
4354 else if ((insn->pinfo & INSN_ISA) == INSN_ISA4)
4359 if (insn_isa > mips_isa
4360 || ((insn->pinfo & INSN_ISA) == INSN_4650
4363 if (insn + 1 < &mips_opcodes[NUMOPCODES]
4364 && strcmp (insn->name, insn[1].name) == 0)
4369 as_warn ("Instruction not supported on this processor");
4373 ip->insn_opcode = insn->match;
4374 for (args = insn->args;; ++args)
4380 case '\0': /* end of args */
4393 ip->insn_opcode |= lastregno << 21;
4398 ip->insn_opcode |= lastregno << 16;
4402 ip->insn_opcode |= lastregno << 11;
4408 /* handle optional base register.
4409 Either the base register is omitted or
4410 we must have a left paren. */
4411 /* this is dependent on the next operand specifier
4412 is a 'b' for base register */
4413 assert (args[1] == 'b');
4417 case ')': /* these must match exactly */
4422 case '<': /* must be at least one digit */
4424 * According to the manual, if the shift amount is greater
4425 * than 31 or less than 0 the the shift amount should be
4426 * mod 32. In reality the mips assembler issues an error.
4427 * We issue a warning and mask out all but the low 5 bits.
4429 my_getExpression (&imm_expr, s);
4430 check_absolute_expr (ip, &imm_expr);
4431 if ((unsigned long) imm_expr.X_add_number > 31)
4433 as_warn ("Improper shift amount (%ld)",
4434 (long) imm_expr.X_add_number);
4435 imm_expr.X_add_number = imm_expr.X_add_number & 0x1f;
4437 ip->insn_opcode |= imm_expr.X_add_number << 6;
4438 imm_expr.X_op = O_absent;
4442 case '>': /* shift amount minus 32 */
4443 my_getExpression (&imm_expr, s);
4444 check_absolute_expr (ip, &imm_expr);
4445 if ((unsigned long) imm_expr.X_add_number < 32
4446 || (unsigned long) imm_expr.X_add_number > 63)
4448 ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6;
4449 imm_expr.X_op = O_absent;
4453 case 'k': /* cache code */
4454 case 'h': /* prefx code */
4455 my_getExpression (&imm_expr, s);
4456 check_absolute_expr (ip, &imm_expr);
4457 if ((unsigned long) imm_expr.X_add_number > 31)
4459 as_warn ("Invalid value for `%s' (%lu)",
4461 (unsigned long) imm_expr.X_add_number);
4462 imm_expr.X_add_number &= 0x1f;
4465 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
4467 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
4468 imm_expr.X_op = O_absent;
4472 case 'c': /* break code */
4473 my_getExpression (&imm_expr, s);
4474 check_absolute_expr (ip, &imm_expr);
4475 if ((unsigned) imm_expr.X_add_number > 1023)
4476 as_warn ("Illegal break code (%ld)",
4477 (long) imm_expr.X_add_number);
4478 ip->insn_opcode |= imm_expr.X_add_number << 16;
4479 imm_expr.X_op = O_absent;
4483 case 'B': /* syscall code */
4484 my_getExpression (&imm_expr, s);
4485 check_absolute_expr (ip, &imm_expr);
4486 if ((unsigned) imm_expr.X_add_number > 0xfffff)
4487 as_warn ("Illegal syscall code (%ld)",
4488 (long) imm_expr.X_add_number);
4489 ip->insn_opcode |= imm_expr.X_add_number << 6;
4490 imm_expr.X_op = O_absent;
4494 case 'C': /* Coprocessor code */
4495 my_getExpression (&imm_expr, s);
4496 check_absolute_expr (ip, &imm_expr);
4497 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
4499 as_warn ("Coproccesor code > 25 bits (%ld)",
4500 (long) imm_expr.X_add_number);
4501 imm_expr.X_add_number &= ((1<<25) - 1);
4503 ip->insn_opcode |= imm_expr.X_add_number;
4504 imm_expr.X_op = O_absent;
4508 case 'b': /* base register */
4509 case 'd': /* destination register */
4510 case 's': /* source register */
4511 case 't': /* target register */
4512 case 'r': /* both target and source */
4513 case 'v': /* both dest and source */
4514 case 'w': /* both dest and target */
4515 case 'E': /* coprocessor target register */
4516 case 'G': /* coprocessor destination register */
4517 case 'x': /* ignore register name */
4518 case 'z': /* must be zero register */
4532 while (isdigit (*s));
4534 as_bad ("Invalid register number (%d)", regno);
4536 else if (*args == 'E' || *args == 'G')
4540 if (s[1] == 'f' && s[2] == 'p')
4545 else if (s[1] == 's' && s[2] == 'p')
4550 else if (s[1] == 'g' && s[2] == 'p')
4555 else if (s[1] == 'a' && s[2] == 't')
4560 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
4565 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
4573 if (regno == AT && ! mips_noat)
4574 as_warn ("Used $at without \".set noat\"");
4580 if (c == 'r' || c == 'v' || c == 'w')
4587 /* 'z' only matches $0. */
4588 if (c == 'z' && regno != 0)
4596 ip->insn_opcode |= regno << 21;
4600 ip->insn_opcode |= regno << 11;
4605 ip->insn_opcode |= regno << 16;
4608 /* This case exists because on the r3000 trunc
4609 expands into a macro which requires a gp
4610 register. On the r6000 or r4000 it is
4611 assembled into a single instruction which
4612 ignores the register. Thus the insn version
4613 is MIPS_ISA2 and uses 'x', and the macro
4614 version is MIPS_ISA1 and uses 't'. */
4617 /* This case is for the div instruction, which
4618 acts differently if the destination argument
4619 is $0. This only matches $0, and is checked
4620 outside the switch. */
4631 ip->insn_opcode |= lastregno << 21;
4634 ip->insn_opcode |= lastregno << 16;
4639 case 'D': /* floating point destination register */
4640 case 'S': /* floating point source register */
4641 case 'T': /* floating point target register */
4642 case 'R': /* floating point source register */
4646 if (s[0] == '$' && s[1] == 'f' && isdigit (s[2]))
4656 while (isdigit (*s));
4659 as_bad ("Invalid float register number (%d)", regno);
4661 if ((regno & 1) != 0
4663 && ! (strcmp (str, "mtc1") == 0 ||
4664 strcmp (str, "mfc1") == 0 ||
4665 strcmp (str, "lwc1") == 0 ||
4666 strcmp (str, "swc1") == 0))
4667 as_warn ("Float register should be even, was %d",
4675 if (c == 'V' || c == 'W')
4685 ip->insn_opcode |= regno << 6;
4689 ip->insn_opcode |= regno << 11;
4693 ip->insn_opcode |= regno << 16;
4696 ip->insn_opcode |= regno << 21;
4705 ip->insn_opcode |= lastregno << 11;
4708 ip->insn_opcode |= lastregno << 16;
4714 my_getExpression (&imm_expr, s);
4715 if (imm_expr.X_op != O_big)
4716 check_absolute_expr (ip, &imm_expr);
4721 my_getExpression (&offset_expr, s);
4722 imm_reloc = BFD_RELOC_32;
4734 unsigned char temp[8];
4736 unsigned int length;
4741 /* These only appear as the last operand in an
4742 instruction, and every instruction that accepts
4743 them in any variant accepts them in all variants.
4744 This means we don't have to worry about backing out
4745 any changes if the instruction does not match.
4747 The difference between them is the size of the
4748 floating point constant and where it goes. For 'F'
4749 and 'L' the constant is 64 bits; for 'f' and 'l' it
4750 is 32 bits. Where the constant is placed is based
4751 on how the MIPS assembler does things:
4754 f -- immediate value
4757 The .lit4 and .lit8 sections are only used if
4758 permitted by the -G argument.
4760 When generating embedded PIC code, we use the
4761 .lit8 section but not the .lit4 section (we can do
4762 .lit4 inline easily; we need to put .lit8
4763 somewhere in the data segment, and using .lit8
4764 permits the linker to eventually combine identical
4767 f64 = *args == 'F' || *args == 'L';
4769 save_in = input_line_pointer;
4770 input_line_pointer = s;
4771 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
4773 s = input_line_pointer;
4774 input_line_pointer = save_in;
4775 if (err != NULL && *err != '\0')
4777 as_bad ("Bad floating point constant: %s", err);
4778 memset (temp, '\0', sizeof temp);
4779 length = f64 ? 8 : 4;
4782 assert (length == (f64 ? 8 : 4));
4786 && (! USE_GLOBAL_POINTER_OPT
4787 || mips_pic == EMBEDDED_PIC
4788 || g_switch_value < 4)
4791 imm_expr.X_op = O_constant;
4792 if (byte_order == LITTLE_ENDIAN)
4793 imm_expr.X_add_number =
4794 (((((((int) temp[3] << 8)
4799 imm_expr.X_add_number =
4800 (((((((int) temp[0] << 8)
4807 const char *newname;
4810 /* Switch to the right section. */
4812 subseg = now_subseg;
4815 default: /* unused default case avoids warnings. */
4817 newname = RDATA_SECTION_NAME;
4818 if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
4822 newname = RDATA_SECTION_NAME;
4825 assert (!USE_GLOBAL_POINTER_OPT
4826 || g_switch_value >= 4);
4830 new_seg = subseg_new (newname, (subsegT) 0);
4831 frag_align (*args == 'l' ? 2 : 3, 0);
4832 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4833 record_alignment (new_seg, 4);
4835 record_alignment (new_seg, *args == 'l' ? 2 : 3);
4837 as_bad ("Can't use floating point insn in this section");
4839 /* Set the argument to the current address in the
4841 offset_expr.X_op = O_symbol;
4842 offset_expr.X_add_symbol =
4843 symbol_new ("L0\001", now_seg,
4844 (valueT) frag_now_fix (), frag_now);
4845 offset_expr.X_add_number = 0;
4847 /* Put the floating point number into the section. */
4848 p = frag_more ((int) length);
4849 memcpy (p, temp, length);
4851 /* Switch back to the original section. */
4852 subseg_set (seg, subseg);
4857 case 'i': /* 16 bit unsigned immediate */
4858 case 'j': /* 16 bit signed immediate */
4859 imm_reloc = BFD_RELOC_LO16;
4860 c = my_getSmallExpression (&imm_expr, s);
4865 if (imm_expr.X_op == O_constant)
4866 imm_expr.X_add_number =
4867 (imm_expr.X_add_number >> 16) & 0xffff;
4869 imm_reloc = BFD_RELOC_HI16_S;
4871 imm_reloc = BFD_RELOC_HI16;
4874 else if (imm_expr.X_op != O_big)
4875 check_absolute_expr (ip, &imm_expr);
4878 if (imm_expr.X_op == O_big
4879 || imm_expr.X_add_number < 0
4880 || imm_expr.X_add_number >= 0x10000)
4882 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
4883 !strcmp (insn->name, insn[1].name))
4885 as_bad ("16 bit expression not in range 0..65535");
4893 /* The upper bound should be 0x8000, but
4894 unfortunately the MIPS assembler accepts numbers
4895 from 0x8000 to 0xffff and sign extends them, and
4896 we want to be compatible. We only permit this
4897 extended range for an instruction which does not
4898 provide any further alternates, since those
4899 alternates may handle other cases. People should
4900 use the numbers they mean, rather than relying on
4901 a mysterious sign extension. */
4902 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
4903 strcmp (insn->name, insn[1].name) == 0);
4908 if (imm_expr.X_op == O_big
4909 || imm_expr.X_add_number < -0x8000
4910 || imm_expr.X_add_number >= max
4912 && imm_expr.X_add_number < 0
4914 && imm_expr.X_unsigned
4915 && sizeof (imm_expr.X_add_number) <= 4))
4919 as_bad ("16 bit expression not in range -32768..32767");
4925 case 'o': /* 16 bit offset */
4926 c = my_getSmallExpression (&offset_expr, s);
4928 /* If this value won't fit into a 16 bit offset, then go
4929 find a macro that will generate the 32 bit offset
4930 code pattern. As a special hack, we accept the
4931 difference of two local symbols as a constant. This
4932 is required to suppose embedded PIC switches, which
4933 use an instruction which looks like
4934 lw $4,$L12-$LS12($4)
4935 The problem with handling this in a more general
4936 fashion is that the macro function doesn't expect to
4937 see anything which can be handled in a single
4938 constant instruction. */
4940 && (offset_expr.X_op != O_constant
4941 || offset_expr.X_add_number >= 0x8000
4942 || offset_expr.X_add_number < -0x8000)
4943 && (mips_pic != EMBEDDED_PIC
4944 || offset_expr.X_op != O_subtract
4945 || now_seg != text_section
4946 || (S_GET_SEGMENT (offset_expr.X_op_symbol)
4950 offset_reloc = BFD_RELOC_LO16;
4951 if (c == 'h' || c == 'H')
4953 assert (offset_expr.X_op == O_constant);
4954 offset_expr.X_add_number =
4955 (offset_expr.X_add_number >> 16) & 0xffff;
4960 case 'p': /* pc relative offset */
4961 offset_reloc = BFD_RELOC_16_PCREL_S2;
4962 my_getExpression (&offset_expr, s);
4966 case 'u': /* upper 16 bits */
4967 c = my_getSmallExpression (&imm_expr, s);
4968 if (imm_expr.X_op == O_constant
4969 && (imm_expr.X_add_number < 0
4970 || imm_expr.X_add_number >= 0x10000))
4971 as_bad ("lui expression not in range 0..65535");
4972 imm_reloc = BFD_RELOC_LO16;
4977 if (imm_expr.X_op == O_constant)
4978 imm_expr.X_add_number =
4979 (imm_expr.X_add_number >> 16) & 0xffff;
4981 imm_reloc = BFD_RELOC_HI16_S;
4983 imm_reloc = BFD_RELOC_HI16;
4989 case 'a': /* 26 bit address */
4990 my_getExpression (&offset_expr, s);
4992 offset_reloc = BFD_RELOC_MIPS_JMP;
4995 case 'N': /* 3 bit branch condition code */
4996 case 'M': /* 3 bit compare condition code */
4997 my_getExpression (&imm_expr, s);
4998 check_absolute_expr (ip, &imm_expr);
4999 if ((unsigned long) imm_expr.X_add_number > 7)
5001 as_warn ("Condition code > 7 (%ld)",
5002 (long) imm_expr.X_add_number);
5003 imm_expr.X_add_number &= 7;
5006 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_BCC;
5008 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CCC;
5009 imm_expr.X_op = O_absent;
5014 fprintf (stderr, "bad char = '%c'\n", *args);
5019 /* Args don't match. */
5020 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
5021 !strcmp (insn->name, insn[1].name))
5027 insn_error = "ERROR: Illegal operands";
5036 my_getSmallExpression (ep, str)
5047 ((str[1] == 'h' && str[2] == 'i')
5048 || (str[1] == 'H' && str[2] == 'I')
5049 || (str[1] == 'l' && str[2] == 'o'))
5061 * A small expression may be followed by a base register.
5062 * Scan to the end of this operand, and then back over a possible
5063 * base register. Then scan the small expression up to that
5064 * point. (Based on code in sparc.c...)
5066 for (sp = str; *sp && *sp != ','; sp++)
5068 if (sp - 4 >= str && sp[-1] == RP)
5070 if (isdigit (sp[-2]))
5072 for (sp -= 3; sp >= str && isdigit (*sp); sp--)
5074 if (*sp == '$' && sp > str && sp[-1] == LP)
5080 else if (sp - 5 >= str
5083 && ((sp[-3] == 'f' && sp[-2] == 'p')
5084 || (sp[-3] == 's' && sp[-2] == 'p')
5085 || (sp[-3] == 'g' && sp[-2] == 'p')
5086 || (sp[-3] == 'a' && sp[-2] == 't')))
5092 /* no expression means zero offset */
5095 /* %xx(reg) is an error */
5096 ep->X_op = O_absent;
5101 ep->X_op = O_constant;
5104 ep->X_add_symbol = NULL;
5105 ep->X_op_symbol = NULL;
5106 ep->X_add_number = 0;
5111 my_getExpression (ep, str);
5118 my_getExpression (ep, str);
5119 return c; /* => %hi or %lo encountered */
5123 my_getExpression (ep, str)
5129 save_in = input_line_pointer;
5130 input_line_pointer = str;
5132 expr_end = input_line_pointer;
5133 input_line_pointer = save_in;
5136 /* Turn a string in input_line_pointer into a floating point constant
5137 of type type, and store the appropriate bytes in *litP. The number
5138 of LITTLENUMS emitted is stored in *sizeP . An error message is
5139 returned, or NULL on OK. */
5142 md_atof (type, litP, sizeP)
5148 LITTLENUM_TYPE words[4];
5164 return "bad call to md_atof";
5167 t = atof_ieee (input_line_pointer, type, words);
5169 input_line_pointer = t;
5173 if (byte_order == LITTLE_ENDIAN)
5175 for (i = prec - 1; i >= 0; i--)
5177 md_number_to_chars (litP, (valueT) words[i], 2);
5183 for (i = 0; i < prec; i++)
5185 md_number_to_chars (litP, (valueT) words[i], 2);
5194 md_number_to_chars (buf, val, n)
5202 number_to_chars_littleendian (buf, val, n);
5206 number_to_chars_bigendian (buf, val, n);
5214 CONST char *md_shortopts = "O::g::G:";
5216 struct option md_longopts[] = {
5217 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5218 {"mips0", no_argument, NULL, OPTION_MIPS1},
5219 {"mips1", no_argument, NULL, OPTION_MIPS1},
5220 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5221 {"mips2", no_argument, NULL, OPTION_MIPS2},
5222 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5223 {"mips3", no_argument, NULL, OPTION_MIPS3},
5224 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5225 {"mips4", no_argument, NULL, OPTION_MIPS4},
5226 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5227 {"mcpu", required_argument, NULL, OPTION_MCPU},
5228 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5229 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
5230 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5231 {"trap", no_argument, NULL, OPTION_TRAP},
5232 {"no-break", no_argument, NULL, OPTION_TRAP},
5233 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5234 {"break", no_argument, NULL, OPTION_BREAK},
5235 {"no-trap", no_argument, NULL, OPTION_BREAK},
5236 #define OPTION_EB (OPTION_MD_BASE + 11)
5237 {"EB", no_argument, NULL, OPTION_EB},
5238 #define OPTION_EL (OPTION_MD_BASE + 12)
5239 {"EL", no_argument, NULL, OPTION_EL},
5240 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5241 {"m4650", no_argument, NULL, OPTION_M4650},
5242 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5243 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
5245 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5246 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5248 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
5249 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
5250 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
5253 {NULL, no_argument, NULL, 0}
5255 size_t md_longopts_size = sizeof(md_longopts);
5258 md_parse_option (c, arg)
5273 target_big_endian = 1;
5277 target_big_endian = 0;
5281 if (arg && arg[1] == '0')
5291 mips_debug = atoi (arg);
5292 /* When the MIPS assembler sees -g or -g2, it does not do
5293 optimizations which limit full symbolic debugging. We take
5294 that to be equivalent to -O0. */
5295 if (mips_debug == 2)
5327 /* Identify the processor type */
5329 if (strcmp (p, "default") == 0
5330 || strcmp (p, "DEFAULT") == 0)
5334 if (*p == 'r' || *p == 'R')
5341 if (strcmp (p, "10000") == 0
5342 || strcmp (p, "10k") == 0
5343 || strcmp (p, "10K") == 0)
5348 if (strcmp (p, "2000") == 0
5349 || strcmp (p, "2k") == 0
5350 || strcmp (p, "2K") == 0)
5355 if (strcmp (p, "3000") == 0
5356 || strcmp (p, "3k") == 0
5357 || strcmp (p, "3K") == 0)
5362 if (strcmp (p, "4000") == 0
5363 || strcmp (p, "4k") == 0
5364 || strcmp (p, "4K") == 0)
5366 else if (strcmp (p, "4400") == 0)
5368 else if (strcmp (p, "4600") == 0)
5370 else if (strcmp (p, "4650") == 0)
5379 if (strcmp (p, "6000") == 0
5380 || strcmp (p, "6k") == 0
5381 || strcmp (p, "6K") == 0)
5386 if (strcmp (p, "8000") == 0
5387 || strcmp (p, "8k") == 0
5388 || strcmp (p, "8K") == 0)
5393 if (strcmp (p, "orion") == 0)
5400 as_bad ("invalid architecture -mcpu=%s", arg);
5411 case OPTION_NO_M4650:
5415 case OPTION_MEMBEDDED_PIC:
5416 mips_pic = EMBEDDED_PIC;
5417 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
5419 as_bad ("-G may not be used with embedded PIC code");
5422 g_switch_value = 0x7fffffff;
5425 /* When generating ELF code, we permit -KPIC and -call_shared to
5426 select SVR4_PIC, and -non_shared to select no PIC. This is
5427 intended to be compatible with Irix 5. */
5428 case OPTION_CALL_SHARED:
5429 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
5431 as_bad ("-call_shared is supported only for ELF format");
5434 mips_pic = SVR4_PIC;
5435 if (g_switch_seen && g_switch_value != 0)
5437 as_bad ("-G may not be used with SVR4 PIC code");
5443 case OPTION_NON_SHARED:
5444 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
5446 as_bad ("-non_shared is supported only for ELF format");
5453 if (! USE_GLOBAL_POINTER_OPT)
5455 as_bad ("-G is not supported for this configuration");
5458 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
5460 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5464 g_switch_value = atoi (arg);
5476 md_show_usage (stream)
5481 -membedded-pic generate embedded position independent code\n\
5482 -EB generate big endian output\n\
5483 -EL generate little endian output\n\
5484 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5485 -G NUM allow referencing objects up to NUM bytes\n\
5486 implicitly with the gp register [default 8]\n");
5488 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5489 -mips2, -mcpu=r6000 generate code for r6000\n\
5490 -mips3, -mcpu=r4000 generate code for r4000\n\
5491 -mips4, -mcpu=r8000 generate code for r8000\n\
5492 -m4650 permit -m4650 instructions\n\
5493 -no-m4650 do not permit -m4650 instructions\n\
5494 -O0 remove unneeded NOPs, do not swap branches\n\
5495 -O remove unneeded NOPs and swap branches\n\
5496 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5497 --break, --no-trap break exception on div by 0 and mult overflow\n");
5500 -KPIC, -call_shared generate SVR4 position independent code\n\
5501 -non_shared do not generate position independent code\n");
5506 mips_init_after_args ()
5508 if (target_big_endian)
5509 byte_order = BIG_ENDIAN;
5511 byte_order = LITTLE_ENDIAN;
5515 md_pcrel_from (fixP)
5518 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
5519 && fixP->fx_addsy != (symbolS *) NULL
5520 && ! S_IS_DEFINED (fixP->fx_addsy))
5522 /* This makes a branch to an undefined symbol be a branch to the
5523 current location. */
5527 /* return the address of the delay slot */
5528 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5531 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5532 reloc for a cons. We could use the definition there, except that
5533 we want to handle 64 bit relocs specially. */
5536 cons_fix_new_mips (frag, where, nbytes, exp)
5539 unsigned int nbytes;
5542 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5544 FIXME: There is no way to select anything but 32 bit mode right
5548 if (byte_order == BIG_ENDIAN)
5553 if (nbytes != 2 && nbytes != 4)
5554 as_bad ("Unsupported reloc size %d", nbytes);
5556 fix_new_exp (frag_now, where, (int) nbytes, exp, 0,
5557 nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32);
5560 /* When generating embedded PIC code we need to use a special
5561 relocation to represent the difference of two symbols in the .text
5562 section (switch tables use a difference of this sort). See
5563 include/coff/mips.h for details. This macro checks whether this
5564 fixup requires the special reloc. */
5565 #define SWITCH_TABLE(fixp) \
5566 ((fixp)->fx_r_type == BFD_RELOC_32 \
5567 && (fixp)->fx_addsy != NULL \
5568 && (fixp)->fx_subsy != NULL \
5569 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5570 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5572 /* When generating embedded PIC code we must keep all PC relative
5573 relocations, in case the linker has to relax a call. We also need
5574 to keep relocations for switch table entries. */
5578 mips_force_relocation (fixp)
5581 return (mips_pic == EMBEDDED_PIC
5583 || SWITCH_TABLE (fixp)
5584 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
5585 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
5588 /* Apply a fixup to the object file. */
5591 md_apply_fix (fixP, valueP)
5598 assert (fixP->fx_size == 4 || fixP->fx_r_type == BFD_RELOC_16);
5601 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
5603 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
5606 switch (fixP->fx_r_type)
5608 case BFD_RELOC_MIPS_JMP:
5609 case BFD_RELOC_HI16:
5610 case BFD_RELOC_HI16_S:
5611 case BFD_RELOC_MIPS_GPREL:
5612 case BFD_RELOC_MIPS_LITERAL:
5613 case BFD_RELOC_MIPS_CALL16:
5614 case BFD_RELOC_MIPS_GOT16:
5615 case BFD_RELOC_MIPS_GPREL32:
5617 as_bad_where (fixP->fx_file, fixP->fx_line,
5618 "Invalid PC relative reloc");
5619 /* Nothing needed to do. The value comes from the reloc entry */
5622 case BFD_RELOC_PCREL_HI16_S:
5623 /* The addend for this is tricky if it is internal, so we just
5624 do everything here rather than in bfd_perform_relocation. */
5625 if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
5627 /* For an external symbol adjust by the address to make it
5628 pcrel_offset. We use the address of the RELLO reloc
5629 which follows this one. */
5630 value += (fixP->fx_next->fx_frag->fr_address
5631 + fixP->fx_next->fx_where);
5636 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
5637 if (byte_order == BIG_ENDIAN)
5639 md_number_to_chars (buf, value, 2);
5642 case BFD_RELOC_PCREL_LO16:
5643 /* The addend for this is tricky if it is internal, so we just
5644 do everything here rather than in bfd_perform_relocation. */
5645 if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
5646 value += fixP->fx_frag->fr_address + fixP->fx_where;
5647 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
5648 if (byte_order == BIG_ENDIAN)
5650 md_number_to_chars (buf, value, 2);
5654 /* If we are deleting this reloc entry, we must fill in the
5655 value now. This can happen if we have a .word which is not
5656 resolved when it appears but is later defined. We also need
5657 to fill in the value if this is an embedded PIC switch table
5660 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
5661 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
5666 /* If we are deleting this reloc entry, we must fill in the
5668 assert (fixP->fx_size == 2);
5670 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
5674 case BFD_RELOC_LO16:
5675 /* When handling an embedded PIC switch statement, we can wind
5676 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5679 if (value < -0x8000 || value > 0x7fff)
5680 as_bad_where (fixP->fx_file, fixP->fx_line,
5681 "relocation overflow");
5682 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
5683 if (byte_order == BIG_ENDIAN)
5685 md_number_to_chars (buf, value, 2);
5689 case BFD_RELOC_16_PCREL_S2:
5691 * We need to save the bits in the instruction since fixup_segment()
5692 * might be deleting the relocation entry (i.e., a branch within
5693 * the current segment).
5696 as_warn_where (fixP->fx_file, fixP->fx_line,
5697 "Branch to odd address (%lx)", value);
5700 /* update old instruction data */
5701 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
5705 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
5709 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
5717 if (value >= -0x8000 && value < 0x8000)
5718 insn |= value & 0xffff;
5721 /* The branch offset is too large. If this is an
5722 unconditional branch, and we are not generating PIC code,
5723 we can convert it to an absolute jump instruction. */
5724 if (mips_pic == NO_PIC
5726 && fixP->fx_frag->fr_address >= text_section->vma
5727 && (fixP->fx_frag->fr_address
5728 < text_section->vma + text_section->_raw_size)
5729 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5730 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
5731 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5733 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
5734 insn = 0x0c000000; /* jal */
5736 insn = 0x08000000; /* j */
5737 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
5739 fixP->fx_addsy = section_symbol (text_section);
5740 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
5744 /* FIXME. It would be possible in principle to handle
5745 conditional branches which overflow. They could be
5746 transformed into a branch around a jump. This would
5747 require setting up variant frags for each different
5748 branch type. The native MIPS assembler attempts to
5749 handle these cases, but it appears to do it
5751 as_bad_where (fixP->fx_file, fixP->fx_line,
5752 "Relocation overflow");
5756 md_number_to_chars ((char *) buf, (valueT) insn, 4);
5771 const struct mips_opcode *p;
5772 int treg, sreg, dreg, shamt;
5777 for (i = 0; i < NUMOPCODES; ++i)
5779 p = &mips_opcodes[i];
5780 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
5782 printf ("%08lx %s\t", oc, p->name);
5783 treg = (oc >> 16) & 0x1f;
5784 sreg = (oc >> 21) & 0x1f;
5785 dreg = (oc >> 11) & 0x1f;
5786 shamt = (oc >> 6) & 0x1f;
5788 for (args = p->args;; ++args)
5799 printf ("%c", *args);
5803 assert (treg == sreg);
5804 printf ("$%d,$%d", treg, sreg);
5809 printf ("$%d", dreg);
5814 printf ("$%d", treg);
5818 printf ("0x%x", treg);
5823 printf ("$%d", sreg);
5827 printf ("0x%08lx", oc & 0x1ffffff);
5839 printf ("$%d", shamt);
5850 printf ("%08lx UNDEFINED\n", oc);
5861 name = input_line_pointer;
5862 c = get_symbol_end ();
5863 p = (symbolS *) symbol_find_or_make (name);
5864 *input_line_pointer = c;
5868 /* Align the current frag to a given power of two. The MIPS assembler
5869 also automatically adjusts any preceding label. */
5872 mips_align (to, fill, label)
5877 mips_emit_delays ();
5878 frag_align (to, fill);
5879 record_alignment (now_seg, to);
5882 assert (S_GET_SEGMENT (label) == now_seg);
5883 label->sy_frag = frag_now;
5884 S_SET_VALUE (label, (valueT) frag_now_fix ());
5888 /* Align to a given power of two. .align 0 turns off the automatic
5889 alignment used by the data creating pseudo-ops. */
5896 register long temp_fill;
5897 long max_alignment = 15;
5901 o Note that the assembler pulls down any immediately preceeding label
5902 to the aligned address.
5903 o It's not documented but auto alignment is reinstated by
5904 a .align pseudo instruction.
5905 o Note also that after auto alignment is turned off the mips assembler
5906 issues an error on attempt to assemble an improperly aligned data item.
5911 temp = get_absolute_expression ();
5912 if (temp > max_alignment)
5913 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
5916 as_warn ("Alignment negative: 0 assumed.");
5919 if (*input_line_pointer == ',')
5921 input_line_pointer++;
5922 temp_fill = get_absolute_expression ();
5929 mips_align (temp, (int) temp_fill, insn_label);
5936 demand_empty_rest_of_line ();
5940 mips_flush_pending_output ()
5942 mips_emit_delays ();
5952 /* When generating embedded PIC code, we only use the .text, .lit8,
5953 .sdata and .sbss sections. We change the .data and .rdata
5954 pseudo-ops to use .sdata. */
5955 if (mips_pic == EMBEDDED_PIC
5956 && (sec == 'd' || sec == 'r'))
5959 mips_emit_delays ();
5969 subseg_set (bss_section, (subsegT) get_absolute_expression ());
5970 demand_empty_rest_of_line ();
5974 if (USE_GLOBAL_POINTER_OPT)
5976 seg = subseg_new (RDATA_SECTION_NAME,
5977 (subsegT) get_absolute_expression ());
5978 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
5980 bfd_set_section_flags (stdoutput, seg,
5986 bfd_set_section_alignment (stdoutput, seg, 4);
5988 demand_empty_rest_of_line ();
5992 as_bad ("No read only data section in this object file format");
5993 demand_empty_rest_of_line ();
5999 if (USE_GLOBAL_POINTER_OPT)
6001 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
6002 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6004 bfd_set_section_flags (stdoutput, seg,
6005 SEC_ALLOC | SEC_LOAD | SEC_RELOC
6007 bfd_set_section_alignment (stdoutput, seg, 4);
6009 demand_empty_rest_of_line ();
6014 as_bad ("Global pointers not supported; recompile -G 0");
6015 demand_empty_rest_of_line ();
6024 mips_enable_auto_align ()
6036 mips_emit_delays ();
6037 if (log_size > 0 && auto_align)
6038 mips_align (log_size, 0, label);
6040 cons (1 << log_size);
6047 as_fatal ("Encountered `.err', aborting assembly");
6057 symbolP = get_symbol ();
6058 if (*input_line_pointer == ',')
6059 input_line_pointer++;
6060 size = get_absolute_expression ();
6061 S_SET_EXTERNAL (symbolP);
6063 if (ECOFF_DEBUGGING)
6064 symbolP->ecoff_extern_size = size;
6075 mips_emit_delays ();
6079 mips_align (3, 0, label);
6081 mips_align (2, 0, label);
6088 /* Handle .globl. We need to override it because on Irix 5 you are
6091 where foo is an undefined symbol, to mean that foo should be
6092 considered to be the address of a function. */
6102 name = input_line_pointer;
6103 c = get_symbol_end ();
6104 symbolP = symbol_find_or_make (name);
6105 *input_line_pointer = c;
6107 if (! is_end_of_line[(unsigned char) *input_line_pointer])
6112 secname = input_line_pointer;
6113 c = get_symbol_end ();
6114 sec = bfd_get_section_by_name (stdoutput, secname);
6116 as_bad ("%s: no such section", secname);
6117 *input_line_pointer = c;
6119 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
6120 symbolP->bsym->flags |= BSF_FUNCTION;
6123 S_SET_EXTERNAL (symbolP);
6124 demand_empty_rest_of_line ();
6134 opt = input_line_pointer;
6135 c = get_symbol_end ();
6139 /* FIXME: What does this mean? */
6141 else if (strncmp (opt, "pic", 3) == 0)
6149 mips_pic = SVR4_PIC;
6151 as_bad (".option pic%d not supported", i);
6153 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
6155 if (g_switch_seen && g_switch_value != 0)
6156 as_warn ("-G may not be used with SVR4 PIC code");
6158 bfd_set_gp_size (stdoutput, 0);
6162 as_warn ("Unrecognized option \"%s\"", opt);
6164 *input_line_pointer = c;
6165 demand_empty_rest_of_line ();
6172 char *name = input_line_pointer, ch;
6174 while (!is_end_of_line[(unsigned char) *input_line_pointer])
6175 input_line_pointer++;
6176 ch = *input_line_pointer;
6177 *input_line_pointer = '\0';
6179 if (strcmp (name, "reorder") == 0)
6183 prev_insn_unreordered = 1;
6184 prev_prev_insn_unreordered = 1;
6188 else if (strcmp (name, "noreorder") == 0)
6190 mips_emit_delays ();
6192 mips_any_noreorder = 1;
6194 else if (strcmp (name, "at") == 0)
6198 else if (strcmp (name, "noat") == 0)
6202 else if (strcmp (name, "macro") == 0)
6204 mips_warn_about_macros = 0;
6206 else if (strcmp (name, "nomacro") == 0)
6208 if (mips_noreorder == 0)
6209 as_bad ("`noreorder' must be set before `nomacro'");
6210 mips_warn_about_macros = 1;
6212 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
6216 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
6220 else if (strcmp (name, "bopt") == 0)
6224 else if (strcmp (name, "nobopt") == 0)
6228 else if (strncmp (name, "mips", 4) == 0)
6232 /* Permit the user to change the ISA on the fly. Needless to
6233 say, misuse can cause serious problems. */
6234 isa = atoi (name + 4);
6236 mips_isa = file_mips_isa;
6237 else if (isa < 1 || isa > 4)
6238 as_bad ("unknown ISA level");
6244 as_warn ("Tried to set unrecognized symbol: %s\n", name);
6246 *input_line_pointer = ch;
6247 demand_empty_rest_of_line ();
6250 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6251 .option pic2. It means to generate SVR4 PIC calls. */
6257 mips_pic = SVR4_PIC;
6258 if (USE_GLOBAL_POINTER_OPT)
6260 if (g_switch_seen && g_switch_value != 0)
6261 as_warn ("-G may not be used with SVR4 PIC code");
6264 bfd_set_gp_size (stdoutput, 0);
6265 demand_empty_rest_of_line ();
6268 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6269 PIC code. It sets the $gp register for the function based on the
6270 function address, which is in the register named in the argument.
6271 This uses a relocation against _gp_disp, which is handled specially
6272 by the linker. The result is:
6273 lui $gp,%hi(_gp_disp)
6274 addiu $gp,$gp,%lo(_gp_disp)
6275 addu $gp,$gp,.cpload argument
6276 The .cpload argument is normally $25 == $t9. */
6285 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6286 if (mips_pic != SVR4_PIC)
6292 /* .cpload should be a in .set noreorder section. */
6293 if (mips_noreorder == 0)
6294 as_warn (".cpload not in noreorder section");
6297 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
6298 ex.X_op_symbol = NULL;
6299 ex.X_add_number = 0;
6301 macro_build_lui ((char *) NULL, &icnt, &ex, GP);
6302 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP,
6303 (int) BFD_RELOC_LO16);
6305 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
6306 GP, GP, tc_get_register (0));
6308 demand_empty_rest_of_line ();
6311 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6312 offset from $sp. The offset is remembered, and after making a PIC
6313 call $gp is restored from that location. */
6316 s_cprestore (ignore)
6322 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6323 if (mips_pic != SVR4_PIC)
6329 mips_cprestore_offset = get_absolute_expression ();
6331 ex.X_op = O_constant;
6332 ex.X_add_symbol = NULL;
6333 ex.X_op_symbol = NULL;
6334 ex.X_add_number = mips_cprestore_offset;
6336 macro_build ((char *) NULL, &icnt, &ex,
6337 mips_isa < 3 ? "sw" : "sd",
6338 "t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
6340 demand_empty_rest_of_line ();
6343 /* Handle the .gpword pseudo-op. This is used when generating PIC
6344 code. It generates a 32 bit GP relative reloc. */
6354 /* When not generating PIC code, this is treated as .word. */
6355 if (mips_pic != SVR4_PIC)
6362 mips_emit_delays ();
6364 mips_align (2, 0, label);
6369 if (ex.X_op != O_symbol || ex.X_add_number != 0)
6371 as_bad ("Unsupported use of .gpword");
6372 ignore_rest_of_line ();
6376 md_number_to_chars (p, (valueT) 0, 4);
6377 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0,
6378 BFD_RELOC_MIPS_GPREL32);
6380 demand_empty_rest_of_line ();
6383 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6384 tables in SVR4 PIC code. */
6393 /* This is ignored when not generating SVR4 PIC code. */
6394 if (mips_pic != SVR4_PIC)
6400 /* Add $gp to the register named as an argument. */
6401 reg = tc_get_register (0);
6402 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6403 mips_isa < 3 ? "addu" : "daddu",
6404 "d,v,t", reg, reg, GP);
6406 demand_empty_rest_of_line ();
6409 /* Parse a register string into a number. Called from the ECOFF code
6410 to parse .frame. The argument is non-zero if this is the frame
6411 register, so that we can record it in mips_frame_reg. */
6414 tc_get_register (frame)
6420 if (*input_line_pointer++ != '$')
6422 as_warn ("expected `$'");
6425 else if (isdigit ((unsigned char) *input_line_pointer))
6427 reg = get_absolute_expression ();
6428 if (reg < 0 || reg >= 32)
6430 as_warn ("Bad register number");
6436 if (strncmp (input_line_pointer, "fp", 2) == 0)
6438 else if (strncmp (input_line_pointer, "sp", 2) == 0)
6440 else if (strncmp (input_line_pointer, "gp", 2) == 0)
6442 else if (strncmp (input_line_pointer, "at", 2) == 0)
6446 as_warn ("Unrecognized register name");
6449 input_line_pointer += 2;
6452 mips_frame_reg = reg != 0 ? reg : SP;
6457 md_section_align (seg, addr)
6461 int align = bfd_get_section_alignment (stdoutput, seg);
6463 return ((addr + (1 << align) - 1) & (-1 << align));
6466 /* Utility routine, called from above as well. If called while the
6467 input file is still being read, it's only an approximation. (For
6468 example, a symbol may later become defined which appeared to be
6469 undefined earlier.) */
6472 nopic_need_relax (sym)
6478 if (USE_GLOBAL_POINTER_OPT)
6480 const char *symname;
6483 /* Find out whether this symbol can be referenced off the GP
6484 register. It can be if it is smaller than the -G size or if
6485 it is in the .sdata or .sbss section. Certain symbols can
6486 not be referenced off the GP, although it appears as though
6488 symname = S_GET_NAME (sym);
6489 if (symname != (const char *) NULL
6490 && (strcmp (symname, "eprol") == 0
6491 || strcmp (symname, "etext") == 0
6492 || strcmp (symname, "_gp") == 0
6493 || strcmp (symname, "edata") == 0
6494 || strcmp (symname, "_fbss") == 0
6495 || strcmp (symname, "_fdata") == 0
6496 || strcmp (symname, "_ftext") == 0
6497 || strcmp (symname, "end") == 0
6498 || strcmp (symname, "_gp_disp") == 0))
6500 else if (! S_IS_DEFINED (sym)
6501 && ((sym->ecoff_extern_size != 0
6502 && sym->ecoff_extern_size <= g_switch_value)
6503 || (S_GET_VALUE (sym) != 0
6504 && S_GET_VALUE (sym) <= g_switch_value)))
6508 const char *segname;
6510 segname = segment_name (S_GET_SEGMENT (sym));
6511 assert (strcmp (segname, ".lit8") != 0
6512 && strcmp (segname, ".lit4") != 0);
6513 change = (strcmp (segname, ".sdata") != 0
6514 && strcmp (segname, ".sbss") != 0);
6519 /* We are not optimizing for the GP register. */
6523 /* Estimate the size of a frag before relaxing. We are not really
6524 relaxing here, and the final size is encoded in the subtype
6529 md_estimate_size_before_relax (fragp, segtype)
6535 if (mips_pic == NO_PIC)
6537 change = nopic_need_relax (fragp->fr_symbol);
6539 else if (mips_pic == SVR4_PIC)
6541 asection *symsec = fragp->fr_symbol->bsym->section;
6543 /* This must duplicate the test in adjust_reloc_syms. */
6544 change = (symsec != &bfd_und_section
6545 && symsec != &bfd_abs_section
6546 && ! bfd_is_com_section (symsec));
6553 /* Record the offset to the first reloc in the fr_opcode field.
6554 This lets md_convert_frag and tc_gen_reloc know that the code
6555 must be expanded. */
6556 fragp->fr_opcode = (fragp->fr_literal
6558 - RELAX_OLD (fragp->fr_subtype)
6559 + RELAX_RELOC1 (fragp->fr_subtype));
6560 /* FIXME: This really needs as_warn_where. */
6561 if (RELAX_WARN (fragp->fr_subtype))
6562 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6568 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
6571 /* Translate internal representation of relocation info to BFD target
6575 tc_gen_reloc (section, fixp)
6579 static arelent *retval[4];
6582 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
6585 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
6586 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6588 if (mips_pic == EMBEDDED_PIC
6589 && SWITCH_TABLE (fixp))
6591 /* For a switch table entry we use a special reloc. The addend
6592 is actually the difference between the reloc address and the
6594 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
6595 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
6596 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6597 fixp->fx_r_type = BFD_RELOC_GPREL32;
6599 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
6601 /* We use a special addend for an internal RELLO reloc. */
6602 if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM)
6603 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
6605 reloc->addend = fixp->fx_addnumber + reloc->address;
6607 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
6609 assert (fixp->fx_next != NULL
6610 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
6611 /* We use a special addend for an internal RELHI reloc. The
6612 reloc is relative to the RELLO; adjust the addend
6614 if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM)
6615 reloc->addend = (fixp->fx_next->fx_frag->fr_address
6616 + fixp->fx_next->fx_where
6617 - S_GET_VALUE (fixp->fx_subsy));
6619 reloc->addend = (fixp->fx_addnumber
6620 + fixp->fx_next->fx_frag->fr_address
6621 + fixp->fx_next->fx_where);
6623 else if (fixp->fx_pcrel == 0)
6624 reloc->addend = fixp->fx_addnumber;
6627 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
6628 /* A gruesome hack which is a result of the gruesome gas reloc
6630 reloc->addend = reloc->address;
6632 reloc->addend = -reloc->address;
6635 /* If this is a variant frag, we may need to adjust the existing
6636 reloc and generate a new one. */
6637 if (fixp->fx_frag->fr_opcode != NULL
6638 && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
6639 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
6640 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16))
6644 /* If this is not the last reloc in this frag, then we have two
6645 GPREL relocs, both of which are being replaced. Let the
6646 second one handle all of them. */
6647 if (fixp->fx_next != NULL
6648 && fixp->fx_frag == fixp->fx_next->fx_frag)
6650 assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
6651 && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL);
6656 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
6657 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6658 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
6660 reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym;
6661 reloc2->address = (reloc->address
6662 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
6663 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
6664 reloc2->addend = fixp->fx_addnumber;
6665 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
6666 assert (reloc2->howto != NULL);
6668 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
6672 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
6675 reloc3->address += 4;
6678 if (mips_pic == NO_PIC)
6680 assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL);
6681 fixp->fx_r_type = BFD_RELOC_HI16_S;
6683 else if (mips_pic == SVR4_PIC)
6685 if (fixp->fx_r_type != BFD_RELOC_MIPS_GOT16)
6687 assert (fixp->fx_r_type == BFD_RELOC_MIPS_CALL16);
6688 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
6695 /* To support a PC relative reloc when generating embedded PIC code
6696 for ECOFF, we use a Cygnus extension. We check for that here to
6697 make sure that we don't let such a reloc escape normally. */
6698 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour
6699 && fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
6700 && mips_pic != EMBEDDED_PIC)
6701 reloc->howto = NULL;
6703 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6705 if (reloc->howto == NULL)
6707 as_bad_where (fixp->fx_file, fixp->fx_line,
6708 "Can not represent relocation in this object file format");
6715 /* Convert a machine dependent frag. */
6718 md_convert_frag (abfd, asec, fragp)
6726 if (fragp->fr_opcode == NULL)
6729 old = RELAX_OLD (fragp->fr_subtype);
6730 new = RELAX_NEW (fragp->fr_subtype);
6731 fixptr = fragp->fr_literal + fragp->fr_fix;
6734 memcpy (fixptr - old, fixptr, new);
6736 fragp->fr_fix += new - old;
6739 /* This function is called whenever a label is defined. It is used
6740 when handling branch delays; if a branch has a label, we assume we
6744 mips_define_label (sym)
6750 /* Decide whether a label is local. This is called by LOCAL_LABEL.
6751 In order to work with gcc when using mips-tfile, we must keep all
6752 local labels. However, in other cases, we want to discard them,
6753 since they are useless. */
6756 mips_local_label (name)
6761 && ! ecoff_debugging_seen)
6763 /* We were called with -g, but we didn't see any debugging
6764 information. That may mean that gcc is smuggling debugging
6765 information through to mips-tfile, in which case we must
6766 generate all local labels. */
6770 /* Here it's OK to discard local labels. */
6776 /* gcc for the SGI generates a bunch of local labels named LM%d. I
6777 don't know why they don't start with '$'. We must check specially
6779 if (name[0] == 'L' && name[1] == 'M')
6786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6788 /* Some special processing for a MIPS ELF file. */
6791 mips_elf_final_processing ()
6795 /* Write out the .reginfo section. */
6796 s.ri_gprmask = mips_gprmask;
6797 s.ri_cprmask[0] = mips_cprmask[0];
6798 s.ri_cprmask[1] = mips_cprmask[1];
6799 s.ri_cprmask[2] = mips_cprmask[2];
6800 s.ri_cprmask[3] = mips_cprmask[3];
6801 /* The gp_value field is set by the MIPS ELF backend. */
6803 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
6804 ((Elf32_External_RegInfo *)
6805 mips_regmask_frag));
6807 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6808 sort of BFD interface for this. */
6809 if (mips_any_noreorder)
6810 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
6811 if (mips_pic != NO_PIC)
6812 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
6815 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
6817 /* These functions should really be defined by the object file format,
6818 since they are related to debugging information. However, this
6819 code has to work for the a.out format, which does not define them,
6820 so we provide simple versions here. These don't actually generate
6821 any debugging information, but they do simple checking and someday
6822 somebody may make them useful. */
6826 struct loc *loc_next;
6827 unsigned long loc_fileno;
6828 unsigned long loc_lineno;
6829 unsigned long loc_offset;
6830 unsigned short loc_delta;
6831 unsigned short loc_count;
6840 struct proc *proc_next;
6841 struct symbol *proc_isym;
6842 struct symbol *proc_end;
6843 unsigned long proc_reg_mask;
6844 unsigned long proc_reg_offset;
6845 unsigned long proc_fpreg_mask;
6846 unsigned long proc_fpreg_offset;
6847 unsigned long proc_frameoffset;
6848 unsigned long proc_framereg;
6849 unsigned long proc_pcreg;
6851 struct file *proc_file;
6858 struct file *file_next;
6859 unsigned long file_fileno;
6860 struct symbol *file_symbol;
6861 struct symbol *file_end;
6862 struct proc *file_proc;
6867 static struct obstack proc_frags;
6868 static procS *proc_lastP;
6869 static procS *proc_rootP;
6870 static int numprocs;
6875 obstack_begin (&proc_frags, 0x2000);
6881 /* check for premature end, nesting errors, etc */
6882 if (proc_lastP && proc_lastP->proc_end == NULL)
6883 as_warn ("missing `.end' at end of assembly");
6892 if (*input_line_pointer == '-')
6894 ++input_line_pointer;
6897 if (!isdigit (*input_line_pointer))
6898 as_bad ("Expected simple number.");
6899 if (input_line_pointer[0] == '0')
6901 if (input_line_pointer[1] == 'x')
6903 input_line_pointer += 2;
6904 while (isxdigit (*input_line_pointer))
6907 val |= hex_value (*input_line_pointer++);
6909 return negative ? -val : val;
6913 ++input_line_pointer;
6914 while (isdigit (*input_line_pointer))
6917 val |= *input_line_pointer++ - '0';
6919 return negative ? -val : val;
6922 if (!isdigit (*input_line_pointer))
6924 printf (" *input_line_pointer == '%c' 0x%02x\n",
6925 *input_line_pointer, *input_line_pointer);
6926 as_warn ("Invalid number");
6929 while (isdigit (*input_line_pointer))
6932 val += *input_line_pointer++ - '0';
6934 return negative ? -val : val;
6937 /* The .file directive; just like the usual .file directive, but there
6938 is an initial number which is the ECOFF file index. */
6946 line = get_number ();
6951 /* The .end directive. */
6959 if (!is_end_of_line[(unsigned char) *input_line_pointer])
6962 demand_empty_rest_of_line ();
6966 if (now_seg != text_section)
6967 as_warn (".end not in text section");
6970 as_warn (".end and no .ent seen yet.");
6976 assert (S_GET_NAME (p));
6977 if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym)))
6978 as_warn (".end symbol does not match .ent symbol.");
6981 proc_lastP->proc_end = (symbolS *) 1;
6984 /* The .aent and .ent directives. */
6994 symbolP = get_symbol ();
6995 if (*input_line_pointer == ',')
6996 input_line_pointer++;
6998 if (isdigit (*input_line_pointer) || *input_line_pointer == '-')
6999 number = get_number ();
7000 if (now_seg != text_section)
7001 as_warn (".ent or .aent not in text section.");
7003 if (!aent && proc_lastP && proc_lastP->proc_end == NULL)
7004 as_warn ("missing `.end'");
7008 procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP));
7009 procP->proc_isym = symbolP;
7010 procP->proc_reg_mask = 0;
7011 procP->proc_reg_offset = 0;
7012 procP->proc_fpreg_mask = 0;
7013 procP->proc_fpreg_offset = 0;
7014 procP->proc_frameoffset = 0;
7015 procP->proc_framereg = 0;
7016 procP->proc_pcreg = 0;
7017 procP->proc_end = NULL;
7018 procP->proc_next = NULL;
7020 proc_lastP->proc_next = procP;
7026 demand_empty_rest_of_line ();
7029 /* The .frame directive. */
7042 frame_reg = tc_get_register (1);
7043 if (*input_line_pointer == ',')
7044 input_line_pointer++;
7045 frame_off = get_absolute_expression ();
7046 if (*input_line_pointer == ',')
7047 input_line_pointer++;
7048 pcreg = tc_get_register (0);
7051 assert (proc_rootP);
7052 proc_rootP->proc_framereg = frame_reg;
7053 proc_rootP->proc_frameoffset = frame_off;
7054 proc_rootP->proc_pcreg = pcreg;
7055 /* bob macho .frame */
7057 /* We don't have to write out a frame stab for unoptimized code. */
7058 if (!(frame_reg == FP && frame_off == 0))
7061 as_warn ("No .ent for .frame to use.");
7062 (void) sprintf (str, "R%d;%d", frame_reg, frame_off);
7063 symP = symbol_new (str, N_VFP, 0, frag_now);
7064 S_SET_TYPE (symP, N_RMASK);
7065 S_SET_OTHER (symP, 0);
7066 S_SET_DESC (symP, 0);
7067 symP->sy_forward = proc_lastP->proc_isym;
7068 /* bob perhaps I should have used pseudo set */
7070 demand_empty_rest_of_line ();
7074 /* The .fmask and .mask directives. */
7081 char str[100], *strP;
7087 mask = get_number ();
7088 if (*input_line_pointer == ',')
7089 input_line_pointer++;
7090 off = get_absolute_expression ();
7092 /* bob only for coff */
7093 assert (proc_rootP);
7094 if (reg_type == 'F')
7096 proc_rootP->proc_fpreg_mask = mask;
7097 proc_rootP->proc_fpreg_offset = off;
7101 proc_rootP->proc_reg_mask = mask;
7102 proc_rootP->proc_reg_offset = off;
7105 /* bob macho .mask + .fmask */
7107 /* We don't have to write out a mask stab if no saved regs. */
7111 as_warn ("No .ent for .mask to use.");
7113 for (i = 0; i < 32; i++)
7117 sprintf (strP, "%c%d,", reg_type, i);
7118 strP += strlen (strP);
7122 sprintf (strP, ";%d,", off);
7123 symP = symbol_new (str, N_RMASK, 0, frag_now);
7124 S_SET_TYPE (symP, N_RMASK);
7125 S_SET_OTHER (symP, 0);
7126 S_SET_DESC (symP, 0);
7127 symP->sy_forward = proc_lastP->proc_isym;
7128 /* bob perhaps I should have used pseudo set */
7133 /* The .loc directive. */
7144 assert (now_seg == text_section);
7146 lineno = get_number ();
7147 addroff = frag_now_fix ();
7149 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
7150 S_SET_TYPE (symbolP, N_SLINE);
7151 S_SET_OTHER (symbolP, 0);
7152 S_SET_DESC (symbolP, lineno);
7153 symbolP->sy_segment = now_seg;