1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32 = -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32 = -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float = 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float = 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008 = FALSE;
278 static struct mips_set_options mips_opts =
280 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
284 /* soft_float */ FALSE, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch = CPU_UNKNOWN;
328 static const char *mips_arch_string;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune = CPU_UNKNOWN;
333 static const char *mips_tune_string;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode = 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got = 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap = 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value = 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen = 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS *, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control *op_hash = NULL;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control *mips16_op_hash = NULL;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control *micromips_op_hash = NULL;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error;
632 static int auto_align = 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset = -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset = -1;
644 static int mips_cpreturn_register = -1;
645 static int mips_gp_register = GP;
646 static int mips_gprel_offset = 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid = 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg = SP;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid = 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize = 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug = 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history[1 + MAX_NOPS];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn;
691 static struct mips_cl_insn mips16_nop_insn;
692 static struct mips_cl_insn micromips_nop16_insn;
693 static struct mips_cl_insn micromips_nop32_insn;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS *prev_nop_frag;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup *next;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup *mips_hi_fixup_list;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS *prev_reloc_op_frag;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map[] =
760 X, X, 2, 3, 4, 5, 6, 7,
761 X, X, X, X, X, X, X, X,
762 0, 1, X, X, X, X, X, X,
763 X, X, X, X, X, X, X, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map[] =
788 0, X, 2, 3, X, X, X, X,
789 X, X, X, X, X, X, X, X,
790 4, 1, 5, 6, 7, X, X, X,
791 X, X, X, X, X, X, X, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map[] =
797 0, X, 2, 3, 4, 5, 6, 7,
798 X, X, X, X, X, X, X, X,
799 X, 1, X, X, X, X, X, X,
800 X, X, X, X, X, X, X, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro = FALSE;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1272 static void append_insn
1273 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1274 bfd_boolean expansionp);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS *, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS *, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS *, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn *ip, char *str);
1283 static void mips16_macro (struct mips_cl_insn * ip);
1284 static void mips_ip (char *str, struct mips_cl_insn * ip);
1285 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS *, bfd_reloc_code_real_type *, char *);
1291 static void my_getExpression (expressionS *, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean pic_need_relax (symbolS *, asection *);
1328 static int relaxed_branch_length (fragS *, asection *, int);
1329 static int validate_mips_insn (const struct mips_opcode *);
1330 static int validate_micromips_insn (const struct mips_opcode *);
1331 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1332 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1334 /* Table and functions used to map between CPU/ISA names, and
1335 ISA levels, and CPU numbers. */
1337 struct mips_cpu_info
1339 const char *name; /* CPU or ISA name. */
1340 int flags; /* MIPS_CPU_* flags. */
1341 int ase; /* Set of ASEs implemented by the CPU. */
1342 int isa; /* ISA level. */
1343 int cpu; /* CPU number (default CPU if ISA). */
1346 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1348 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1349 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1350 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1352 /* Command-line options. */
1353 const char *md_shortopts = "O::g::G:";
1357 OPTION_MARCH = OPTION_MD_BASE,
1381 OPTION_NO_SMARTMIPS,
1387 OPTION_NO_MICROMIPS,
1390 OPTION_COMPAT_ARCH_BASE,
1399 OPTION_M7000_HILO_FIX,
1400 OPTION_MNO_7000_HILO_FIX,
1403 OPTION_FIX_LOONGSON2F_JUMP,
1404 OPTION_NO_FIX_LOONGSON2F_JUMP,
1405 OPTION_FIX_LOONGSON2F_NOP,
1406 OPTION_NO_FIX_LOONGSON2F_NOP,
1408 OPTION_NO_FIX_VR4120,
1410 OPTION_NO_FIX_VR4130,
1411 OPTION_FIX_CN63XXP1,
1412 OPTION_NO_FIX_CN63XXP1,
1419 OPTION_CONSTRUCT_FLOATS,
1420 OPTION_NO_CONSTRUCT_FLOATS,
1423 OPTION_RELAX_BRANCH,
1424 OPTION_NO_RELAX_BRANCH,
1433 OPTION_SINGLE_FLOAT,
1434 OPTION_DOUBLE_FLOAT,
1447 OPTION_MVXWORKS_PIC,
1452 struct option md_longopts[] =
1454 /* Options which specify architecture. */
1455 {"march", required_argument, NULL, OPTION_MARCH},
1456 {"mtune", required_argument, NULL, OPTION_MTUNE},
1457 {"mips0", no_argument, NULL, OPTION_MIPS1},
1458 {"mips1", no_argument, NULL, OPTION_MIPS1},
1459 {"mips2", no_argument, NULL, OPTION_MIPS2},
1460 {"mips3", no_argument, NULL, OPTION_MIPS3},
1461 {"mips4", no_argument, NULL, OPTION_MIPS4},
1462 {"mips5", no_argument, NULL, OPTION_MIPS5},
1463 {"mips32", no_argument, NULL, OPTION_MIPS32},
1464 {"mips64", no_argument, NULL, OPTION_MIPS64},
1465 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1466 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1468 /* Options which specify Application Specific Extensions (ASEs). */
1469 {"mips16", no_argument, NULL, OPTION_MIPS16},
1470 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1471 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1472 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1473 {"mdmx", no_argument, NULL, OPTION_MDMX},
1474 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1475 {"mdsp", no_argument, NULL, OPTION_DSP},
1476 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1477 {"mmt", no_argument, NULL, OPTION_MT},
1478 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1479 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1480 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1481 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1482 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1483 {"meva", no_argument, NULL, OPTION_EVA},
1484 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1485 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1486 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1487 {"mmcu", no_argument, NULL, OPTION_MCU},
1488 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1489 {"mvirt", no_argument, NULL, OPTION_VIRT},
1490 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1492 /* Old-style architecture options. Don't add more of these. */
1493 {"m4650", no_argument, NULL, OPTION_M4650},
1494 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1495 {"m4010", no_argument, NULL, OPTION_M4010},
1496 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1497 {"m4100", no_argument, NULL, OPTION_M4100},
1498 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1499 {"m3900", no_argument, NULL, OPTION_M3900},
1500 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1502 /* Options which enable bug fixes. */
1503 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1504 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1505 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1506 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1507 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1508 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1509 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1510 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1511 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1512 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1513 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1514 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1515 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1516 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1517 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1519 /* Miscellaneous options. */
1520 {"trap", no_argument, NULL, OPTION_TRAP},
1521 {"no-break", no_argument, NULL, OPTION_TRAP},
1522 {"break", no_argument, NULL, OPTION_BREAK},
1523 {"no-trap", no_argument, NULL, OPTION_BREAK},
1524 {"EB", no_argument, NULL, OPTION_EB},
1525 {"EL", no_argument, NULL, OPTION_EL},
1526 {"mfp32", no_argument, NULL, OPTION_FP32},
1527 {"mgp32", no_argument, NULL, OPTION_GP32},
1528 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1529 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1530 {"mfp64", no_argument, NULL, OPTION_FP64},
1531 {"mgp64", no_argument, NULL, OPTION_GP64},
1532 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1533 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1534 {"minsn32", no_argument, NULL, OPTION_INSN32},
1535 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1536 {"mshared", no_argument, NULL, OPTION_MSHARED},
1537 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1538 {"msym32", no_argument, NULL, OPTION_MSYM32},
1539 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1540 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1541 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1542 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1543 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1545 /* Strictly speaking this next option is ELF specific,
1546 but we allow it for other ports as well in order to
1547 make testing easier. */
1548 {"32", no_argument, NULL, OPTION_32},
1550 /* ELF-specific options. */
1551 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1552 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1553 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1554 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1555 {"xgot", no_argument, NULL, OPTION_XGOT},
1556 {"mabi", required_argument, NULL, OPTION_MABI},
1557 {"n32", no_argument, NULL, OPTION_N32},
1558 {"64", no_argument, NULL, OPTION_64},
1559 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1560 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1561 {"mpdr", no_argument, NULL, OPTION_PDR},
1562 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1563 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1564 {"mnan", required_argument, NULL, OPTION_NAN},
1566 {NULL, no_argument, NULL, 0}
1568 size_t md_longopts_size = sizeof (md_longopts);
1570 /* Information about either an Application Specific Extension or an
1571 optional architecture feature that, for simplicity, we treat in the
1572 same way as an ASE. */
1575 /* The name of the ASE, used in both the command-line and .set options. */
1578 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1579 and 64-bit architectures, the flags here refer to the subset that
1580 is available on both. */
1583 /* The ASE_* flag used for instructions that are available on 64-bit
1584 architectures but that are not included in FLAGS. */
1585 unsigned int flags64;
1587 /* The command-line options that turn the ASE on and off. */
1591 /* The minimum required architecture revisions for MIPS32, MIPS64,
1592 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1595 int micromips32_rev;
1596 int micromips64_rev;
1599 /* A table of all supported ASEs. */
1600 static const struct mips_ase mips_ases[] = {
1601 { "dsp", ASE_DSP, ASE_DSP64,
1602 OPTION_DSP, OPTION_NO_DSP,
1605 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1606 OPTION_DSPR2, OPTION_NO_DSPR2,
1609 { "eva", ASE_EVA, 0,
1610 OPTION_EVA, OPTION_NO_EVA,
1613 { "mcu", ASE_MCU, 0,
1614 OPTION_MCU, OPTION_NO_MCU,
1617 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1618 { "mdmx", ASE_MDMX, 0,
1619 OPTION_MDMX, OPTION_NO_MDMX,
1622 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1623 { "mips3d", ASE_MIPS3D, 0,
1624 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1628 OPTION_MT, OPTION_NO_MT,
1631 { "smartmips", ASE_SMARTMIPS, 0,
1632 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1635 { "virt", ASE_VIRT, ASE_VIRT64,
1636 OPTION_VIRT, OPTION_NO_VIRT,
1640 /* The set of ASEs that require -mfp64. */
1641 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1643 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1644 static const unsigned int mips_ase_groups[] = {
1650 The following pseudo-ops from the Kane and Heinrich MIPS book
1651 should be defined here, but are currently unsupported: .alias,
1652 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 specific to the type of debugging information being generated, and
1656 should be defined by the object format: .aent, .begin, .bend,
1657 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1660 The following pseudo-ops from the Kane and Heinrich MIPS book are
1661 not MIPS CPU specific, but are also not specific to the object file
1662 format. This file is probably the best place to define them, but
1663 they are not currently supported: .asm0, .endr, .lab, .struct. */
1665 static const pseudo_typeS mips_pseudo_table[] =
1667 /* MIPS specific pseudo-ops. */
1668 {"option", s_option, 0},
1669 {"set", s_mipsset, 0},
1670 {"rdata", s_change_sec, 'r'},
1671 {"sdata", s_change_sec, 's'},
1672 {"livereg", s_ignore, 0},
1673 {"abicalls", s_abicalls, 0},
1674 {"cpload", s_cpload, 0},
1675 {"cpsetup", s_cpsetup, 0},
1676 {"cplocal", s_cplocal, 0},
1677 {"cprestore", s_cprestore, 0},
1678 {"cpreturn", s_cpreturn, 0},
1679 {"dtprelword", s_dtprelword, 0},
1680 {"dtpreldword", s_dtpreldword, 0},
1681 {"tprelword", s_tprelword, 0},
1682 {"tpreldword", s_tpreldword, 0},
1683 {"gpvalue", s_gpvalue, 0},
1684 {"gpword", s_gpword, 0},
1685 {"gpdword", s_gpdword, 0},
1686 {"ehword", s_ehword, 0},
1687 {"cpadd", s_cpadd, 0},
1688 {"insn", s_insn, 0},
1691 /* Relatively generic pseudo-ops that happen to be used on MIPS
1693 {"asciiz", stringer, 8 + 1},
1694 {"bss", s_change_sec, 'b'},
1696 {"half", s_cons, 1},
1697 {"dword", s_cons, 3},
1698 {"weakext", s_mips_weakext, 0},
1699 {"origin", s_org, 0},
1700 {"repeat", s_rept, 0},
1702 /* For MIPS this is non-standard, but we define it for consistency. */
1703 {"sbss", s_change_sec, 'B'},
1705 /* These pseudo-ops are defined in read.c, but must be overridden
1706 here for one reason or another. */
1707 {"align", s_align, 0},
1708 {"byte", s_cons, 0},
1709 {"data", s_change_sec, 'd'},
1710 {"double", s_float_cons, 'd'},
1711 {"float", s_float_cons, 'f'},
1712 {"globl", s_mips_globl, 0},
1713 {"global", s_mips_globl, 0},
1714 {"hword", s_cons, 1},
1716 {"long", s_cons, 2},
1717 {"octa", s_cons, 4},
1718 {"quad", s_cons, 3},
1719 {"section", s_change_section, 0},
1720 {"short", s_cons, 1},
1721 {"single", s_float_cons, 'f'},
1722 {"stabd", s_mips_stab, 'd'},
1723 {"stabn", s_mips_stab, 'n'},
1724 {"stabs", s_mips_stab, 's'},
1725 {"text", s_change_sec, 't'},
1726 {"word", s_cons, 2},
1728 { "extern", ecoff_directive_extern, 0},
1733 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1735 /* These pseudo-ops should be defined by the object file format.
1736 However, a.out doesn't support them, so we have versions here. */
1737 {"aent", s_mips_ent, 1},
1738 {"bgnb", s_ignore, 0},
1739 {"end", s_mips_end, 0},
1740 {"endb", s_ignore, 0},
1741 {"ent", s_mips_ent, 0},
1742 {"file", s_mips_file, 0},
1743 {"fmask", s_mips_mask, 'F'},
1744 {"frame", s_mips_frame, 0},
1745 {"loc", s_mips_loc, 0},
1746 {"mask", s_mips_mask, 'R'},
1747 {"verstamp", s_ignore, 0},
1751 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1752 purpose of the `.dc.a' internal pseudo-op. */
1755 mips_address_bytes (void)
1757 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1760 extern void pop_insert (const pseudo_typeS *);
1763 mips_pop_insert (void)
1765 pop_insert (mips_pseudo_table);
1766 if (! ECOFF_DEBUGGING)
1767 pop_insert (mips_nonecoff_pseudo_table);
1770 /* Symbols labelling the current insn. */
1772 struct insn_label_list
1774 struct insn_label_list *next;
1778 static struct insn_label_list *free_insn_labels;
1779 #define label_list tc_segment_info_data.labels
1781 static void mips_clear_insn_labels (void);
1782 static void mips_mark_labels (void);
1783 static void mips_compressed_mark_labels (void);
1786 mips_clear_insn_labels (void)
1788 register struct insn_label_list **pl;
1789 segment_info_type *si;
1793 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1796 si = seg_info (now_seg);
1797 *pl = si->label_list;
1798 si->label_list = NULL;
1802 /* Mark instruction labels in MIPS16/microMIPS mode. */
1805 mips_mark_labels (void)
1807 if (HAVE_CODE_COMPRESSION)
1808 mips_compressed_mark_labels ();
1811 static char *expr_end;
1813 /* Expressions which appear in macro instructions. These are set by
1814 mips_ip and read by macro. */
1816 static expressionS imm_expr;
1817 static expressionS imm2_expr;
1819 /* The relocatable field in an instruction and the relocs associated
1820 with it. These variables are used for instructions like LUI and
1821 JAL as well as true offsets. They are also used for address
1822 operands in macros. */
1824 static expressionS offset_expr;
1825 static bfd_reloc_code_real_type offset_reloc[3]
1826 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1828 /* This is set to the resulting size of the instruction to be produced
1829 by mips16_ip if an explicit extension is used or by mips_ip if an
1830 explicit size is supplied. */
1832 static unsigned int forced_insn_length;
1834 /* True if we are assembling an instruction. All dot symbols defined during
1835 this time should be treated as code labels. */
1837 static bfd_boolean mips_assembling_insn;
1839 /* The pdr segment for per procedure frame/regmask info. Not used for
1842 static segT pdr_seg;
1844 /* The default target format to use. */
1846 #if defined (TE_FreeBSD)
1847 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1848 #elif defined (TE_TMIPS)
1849 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1851 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1855 mips_target_format (void)
1857 switch (OUTPUT_FLAVOR)
1859 case bfd_target_elf_flavour:
1861 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1862 return (target_big_endian
1863 ? "elf32-bigmips-vxworks"
1864 : "elf32-littlemips-vxworks");
1866 return (target_big_endian
1867 ? (HAVE_64BIT_OBJECTS
1868 ? ELF_TARGET ("elf64-", "big")
1870 ? ELF_TARGET ("elf32-n", "big")
1871 : ELF_TARGET ("elf32-", "big")))
1872 : (HAVE_64BIT_OBJECTS
1873 ? ELF_TARGET ("elf64-", "little")
1875 ? ELF_TARGET ("elf32-n", "little")
1876 : ELF_TARGET ("elf32-", "little"))));
1883 /* Return the ISA revision that is currently in use, or 0 if we are
1884 generating code for MIPS V or below. */
1889 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1892 /* microMIPS implies revision 2 or above. */
1893 if (mips_opts.micromips)
1896 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1902 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1905 mips_ase_mask (unsigned int flags)
1909 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1910 if (flags & mips_ase_groups[i])
1911 flags |= mips_ase_groups[i];
1915 /* Check whether the current ISA supports ASE. Issue a warning if
1919 mips_check_isa_supports_ase (const struct mips_ase *ase)
1923 static unsigned int warned_isa;
1924 static unsigned int warned_fp32;
1926 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1927 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1929 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1930 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1931 && (warned_isa & ase->flags) != ase->flags)
1933 warned_isa |= ase->flags;
1934 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1935 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1937 as_warn (_("The %d-bit %s architecture does not support the"
1938 " `%s' extension"), size, base, ase->name);
1940 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1941 ase->name, base, size, min_rev);
1943 if ((ase->flags & FP64_ASES)
1945 && (warned_fp32 & ase->flags) != ase->flags)
1947 warned_fp32 |= ase->flags;
1948 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1952 /* Check all enabled ASEs to see whether they are supported by the
1953 chosen architecture. */
1956 mips_check_isa_supports_ases (void)
1958 unsigned int i, mask;
1960 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1962 mask = mips_ase_mask (mips_ases[i].flags);
1963 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1964 mips_check_isa_supports_ase (&mips_ases[i]);
1968 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1969 that were affected. */
1972 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1976 mask = mips_ase_mask (ase->flags);
1977 mips_opts.ase &= ~mask;
1979 mips_opts.ase |= ase->flags;
1983 /* Return the ASE called NAME, or null if none. */
1985 static const struct mips_ase *
1986 mips_lookup_ase (const char *name)
1990 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1991 if (strcmp (name, mips_ases[i].name) == 0)
1992 return &mips_ases[i];
1996 /* Return the length of a microMIPS instruction in bytes. If bits of
1997 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1998 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1999 major opcode) will require further modifications to the opcode
2002 static inline unsigned int
2003 micromips_insn_length (const struct mips_opcode *mo)
2005 return (mo->mask >> 16) == 0 ? 2 : 4;
2008 /* Return the length of MIPS16 instruction OPCODE. */
2010 static inline unsigned int
2011 mips16_opcode_length (unsigned long opcode)
2013 return (opcode >> 16) == 0 ? 2 : 4;
2016 /* Return the length of instruction INSN. */
2018 static inline unsigned int
2019 insn_length (const struct mips_cl_insn *insn)
2021 if (mips_opts.micromips)
2022 return micromips_insn_length (insn->insn_mo);
2023 else if (mips_opts.mips16)
2024 return mips16_opcode_length (insn->insn_opcode);
2029 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2032 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2037 insn->insn_opcode = mo->match;
2040 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2041 insn->fixp[i] = NULL;
2042 insn->fixed_p = (mips_opts.noreorder > 0);
2043 insn->noreorder_p = (mips_opts.noreorder > 0);
2044 insn->mips16_absolute_jump_p = 0;
2045 insn->complete_p = 0;
2046 insn->cleared_p = 0;
2049 /* Record the current MIPS16/microMIPS mode in now_seg. */
2052 mips_record_compressed_mode (void)
2054 segment_info_type *si;
2056 si = seg_info (now_seg);
2057 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2058 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2059 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2060 si->tc_segment_info_data.micromips = mips_opts.micromips;
2063 /* Read a standard MIPS instruction from BUF. */
2065 static unsigned long
2066 read_insn (char *buf)
2068 if (target_big_endian)
2069 return bfd_getb32 ((bfd_byte *) buf);
2071 return bfd_getl32 ((bfd_byte *) buf);
2074 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2078 write_insn (char *buf, unsigned int insn)
2080 md_number_to_chars (buf, insn, 4);
2084 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2085 has length LENGTH. */
2087 static unsigned long
2088 read_compressed_insn (char *buf, unsigned int length)
2094 for (i = 0; i < length; i += 2)
2097 if (target_big_endian)
2098 insn |= bfd_getb16 ((char *) buf);
2100 insn |= bfd_getl16 ((char *) buf);
2106 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2107 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2110 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2114 for (i = 0; i < length; i += 2)
2115 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2116 return buf + length;
2119 /* Install INSN at the location specified by its "frag" and "where" fields. */
2122 install_insn (const struct mips_cl_insn *insn)
2124 char *f = insn->frag->fr_literal + insn->where;
2125 if (HAVE_CODE_COMPRESSION)
2126 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2128 write_insn (f, insn->insn_opcode);
2129 mips_record_compressed_mode ();
2132 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2133 and install the opcode in the new location. */
2136 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2141 insn->where = where;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 if (insn->fixp[i] != NULL)
2145 insn->fixp[i]->fx_frag = frag;
2146 insn->fixp[i]->fx_where = where;
2148 install_insn (insn);
2151 /* Add INSN to the end of the output. */
2154 add_fixed_insn (struct mips_cl_insn *insn)
2156 char *f = frag_more (insn_length (insn));
2157 move_insn (insn, frag_now, f - frag_now->fr_literal);
2160 /* Start a variant frag and move INSN to the start of the variant part,
2161 marking it as fixed. The other arguments are as for frag_var. */
2164 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2165 relax_substateT subtype, symbolS *symbol, offsetT offset)
2167 frag_grow (max_chars);
2168 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2170 frag_var (rs_machine_dependent, max_chars, var,
2171 subtype, symbol, offset, NULL);
2174 /* Insert N copies of INSN into the history buffer, starting at
2175 position FIRST. Neither FIRST nor N need to be clipped. */
2178 insert_into_history (unsigned int first, unsigned int n,
2179 const struct mips_cl_insn *insn)
2181 if (mips_relax.sequence != 2)
2185 for (i = ARRAY_SIZE (history); i-- > first;)
2187 history[i] = history[i - n];
2193 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2194 the idea is to make it obvious at a glance that each errata is
2198 init_vr4120_conflicts (void)
2200 #define CONFLICT(FIRST, SECOND) \
2201 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2203 /* Errata 21 - [D]DIV[U] after [D]MACC */
2204 CONFLICT (MACC, DIV);
2205 CONFLICT (DMACC, DIV);
2207 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2208 CONFLICT (DMULT, DMULT);
2209 CONFLICT (DMULT, DMACC);
2210 CONFLICT (DMACC, DMULT);
2211 CONFLICT (DMACC, DMACC);
2213 /* Errata 24 - MT{LO,HI} after [D]MACC */
2214 CONFLICT (MACC, MTHILO);
2215 CONFLICT (DMACC, MTHILO);
2217 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2218 instruction is executed immediately after a MACC or DMACC
2219 instruction, the result of [either instruction] is incorrect." */
2220 CONFLICT (MACC, MULT);
2221 CONFLICT (MACC, DMULT);
2222 CONFLICT (DMACC, MULT);
2223 CONFLICT (DMACC, DMULT);
2225 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2226 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2227 DDIV or DDIVU instruction, the result of the MACC or
2228 DMACC instruction is incorrect.". */
2229 CONFLICT (DMULT, MACC);
2230 CONFLICT (DMULT, DMACC);
2231 CONFLICT (DIV, MACC);
2232 CONFLICT (DIV, DMACC);
2242 #define RTYPE_MASK 0x1ff00
2243 #define RTYPE_NUM 0x00100
2244 #define RTYPE_FPU 0x00200
2245 #define RTYPE_FCC 0x00400
2246 #define RTYPE_VEC 0x00800
2247 #define RTYPE_GP 0x01000
2248 #define RTYPE_CP0 0x02000
2249 #define RTYPE_PC 0x04000
2250 #define RTYPE_ACC 0x08000
2251 #define RTYPE_CCC 0x10000
2252 #define RNUM_MASK 0x000ff
2253 #define RWARN 0x80000
2255 #define GENERIC_REGISTER_NUMBERS \
2256 {"$0", RTYPE_NUM | 0}, \
2257 {"$1", RTYPE_NUM | 1}, \
2258 {"$2", RTYPE_NUM | 2}, \
2259 {"$3", RTYPE_NUM | 3}, \
2260 {"$4", RTYPE_NUM | 4}, \
2261 {"$5", RTYPE_NUM | 5}, \
2262 {"$6", RTYPE_NUM | 6}, \
2263 {"$7", RTYPE_NUM | 7}, \
2264 {"$8", RTYPE_NUM | 8}, \
2265 {"$9", RTYPE_NUM | 9}, \
2266 {"$10", RTYPE_NUM | 10}, \
2267 {"$11", RTYPE_NUM | 11}, \
2268 {"$12", RTYPE_NUM | 12}, \
2269 {"$13", RTYPE_NUM | 13}, \
2270 {"$14", RTYPE_NUM | 14}, \
2271 {"$15", RTYPE_NUM | 15}, \
2272 {"$16", RTYPE_NUM | 16}, \
2273 {"$17", RTYPE_NUM | 17}, \
2274 {"$18", RTYPE_NUM | 18}, \
2275 {"$19", RTYPE_NUM | 19}, \
2276 {"$20", RTYPE_NUM | 20}, \
2277 {"$21", RTYPE_NUM | 21}, \
2278 {"$22", RTYPE_NUM | 22}, \
2279 {"$23", RTYPE_NUM | 23}, \
2280 {"$24", RTYPE_NUM | 24}, \
2281 {"$25", RTYPE_NUM | 25}, \
2282 {"$26", RTYPE_NUM | 26}, \
2283 {"$27", RTYPE_NUM | 27}, \
2284 {"$28", RTYPE_NUM | 28}, \
2285 {"$29", RTYPE_NUM | 29}, \
2286 {"$30", RTYPE_NUM | 30}, \
2287 {"$31", RTYPE_NUM | 31}
2289 #define FPU_REGISTER_NAMES \
2290 {"$f0", RTYPE_FPU | 0}, \
2291 {"$f1", RTYPE_FPU | 1}, \
2292 {"$f2", RTYPE_FPU | 2}, \
2293 {"$f3", RTYPE_FPU | 3}, \
2294 {"$f4", RTYPE_FPU | 4}, \
2295 {"$f5", RTYPE_FPU | 5}, \
2296 {"$f6", RTYPE_FPU | 6}, \
2297 {"$f7", RTYPE_FPU | 7}, \
2298 {"$f8", RTYPE_FPU | 8}, \
2299 {"$f9", RTYPE_FPU | 9}, \
2300 {"$f10", RTYPE_FPU | 10}, \
2301 {"$f11", RTYPE_FPU | 11}, \
2302 {"$f12", RTYPE_FPU | 12}, \
2303 {"$f13", RTYPE_FPU | 13}, \
2304 {"$f14", RTYPE_FPU | 14}, \
2305 {"$f15", RTYPE_FPU | 15}, \
2306 {"$f16", RTYPE_FPU | 16}, \
2307 {"$f17", RTYPE_FPU | 17}, \
2308 {"$f18", RTYPE_FPU | 18}, \
2309 {"$f19", RTYPE_FPU | 19}, \
2310 {"$f20", RTYPE_FPU | 20}, \
2311 {"$f21", RTYPE_FPU | 21}, \
2312 {"$f22", RTYPE_FPU | 22}, \
2313 {"$f23", RTYPE_FPU | 23}, \
2314 {"$f24", RTYPE_FPU | 24}, \
2315 {"$f25", RTYPE_FPU | 25}, \
2316 {"$f26", RTYPE_FPU | 26}, \
2317 {"$f27", RTYPE_FPU | 27}, \
2318 {"$f28", RTYPE_FPU | 28}, \
2319 {"$f29", RTYPE_FPU | 29}, \
2320 {"$f30", RTYPE_FPU | 30}, \
2321 {"$f31", RTYPE_FPU | 31}
2323 #define FPU_CONDITION_CODE_NAMES \
2324 {"$fcc0", RTYPE_FCC | 0}, \
2325 {"$fcc1", RTYPE_FCC | 1}, \
2326 {"$fcc2", RTYPE_FCC | 2}, \
2327 {"$fcc3", RTYPE_FCC | 3}, \
2328 {"$fcc4", RTYPE_FCC | 4}, \
2329 {"$fcc5", RTYPE_FCC | 5}, \
2330 {"$fcc6", RTYPE_FCC | 6}, \
2331 {"$fcc7", RTYPE_FCC | 7}
2333 #define COPROC_CONDITION_CODE_NAMES \
2334 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2335 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2336 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2337 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2338 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2339 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2340 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2341 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2343 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2344 {"$a4", RTYPE_GP | 8}, \
2345 {"$a5", RTYPE_GP | 9}, \
2346 {"$a6", RTYPE_GP | 10}, \
2347 {"$a7", RTYPE_GP | 11}, \
2348 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2349 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2350 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2351 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2352 {"$t0", RTYPE_GP | 12}, \
2353 {"$t1", RTYPE_GP | 13}, \
2354 {"$t2", RTYPE_GP | 14}, \
2355 {"$t3", RTYPE_GP | 15}
2357 #define O32_SYMBOLIC_REGISTER_NAMES \
2358 {"$t0", RTYPE_GP | 8}, \
2359 {"$t1", RTYPE_GP | 9}, \
2360 {"$t2", RTYPE_GP | 10}, \
2361 {"$t3", RTYPE_GP | 11}, \
2362 {"$t4", RTYPE_GP | 12}, \
2363 {"$t5", RTYPE_GP | 13}, \
2364 {"$t6", RTYPE_GP | 14}, \
2365 {"$t7", RTYPE_GP | 15}, \
2366 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2367 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2368 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2369 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2371 /* Remaining symbolic register names */
2372 #define SYMBOLIC_REGISTER_NAMES \
2373 {"$zero", RTYPE_GP | 0}, \
2374 {"$at", RTYPE_GP | 1}, \
2375 {"$AT", RTYPE_GP | 1}, \
2376 {"$v0", RTYPE_GP | 2}, \
2377 {"$v1", RTYPE_GP | 3}, \
2378 {"$a0", RTYPE_GP | 4}, \
2379 {"$a1", RTYPE_GP | 5}, \
2380 {"$a2", RTYPE_GP | 6}, \
2381 {"$a3", RTYPE_GP | 7}, \
2382 {"$s0", RTYPE_GP | 16}, \
2383 {"$s1", RTYPE_GP | 17}, \
2384 {"$s2", RTYPE_GP | 18}, \
2385 {"$s3", RTYPE_GP | 19}, \
2386 {"$s4", RTYPE_GP | 20}, \
2387 {"$s5", RTYPE_GP | 21}, \
2388 {"$s6", RTYPE_GP | 22}, \
2389 {"$s7", RTYPE_GP | 23}, \
2390 {"$t8", RTYPE_GP | 24}, \
2391 {"$t9", RTYPE_GP | 25}, \
2392 {"$k0", RTYPE_GP | 26}, \
2393 {"$kt0", RTYPE_GP | 26}, \
2394 {"$k1", RTYPE_GP | 27}, \
2395 {"$kt1", RTYPE_GP | 27}, \
2396 {"$gp", RTYPE_GP | 28}, \
2397 {"$sp", RTYPE_GP | 29}, \
2398 {"$s8", RTYPE_GP | 30}, \
2399 {"$fp", RTYPE_GP | 30}, \
2400 {"$ra", RTYPE_GP | 31}
2402 #define MIPS16_SPECIAL_REGISTER_NAMES \
2403 {"$pc", RTYPE_PC | 0}
2405 #define MDMX_VECTOR_REGISTER_NAMES \
2406 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2407 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2408 {"$v2", RTYPE_VEC | 2}, \
2409 {"$v3", RTYPE_VEC | 3}, \
2410 {"$v4", RTYPE_VEC | 4}, \
2411 {"$v5", RTYPE_VEC | 5}, \
2412 {"$v6", RTYPE_VEC | 6}, \
2413 {"$v7", RTYPE_VEC | 7}, \
2414 {"$v8", RTYPE_VEC | 8}, \
2415 {"$v9", RTYPE_VEC | 9}, \
2416 {"$v10", RTYPE_VEC | 10}, \
2417 {"$v11", RTYPE_VEC | 11}, \
2418 {"$v12", RTYPE_VEC | 12}, \
2419 {"$v13", RTYPE_VEC | 13}, \
2420 {"$v14", RTYPE_VEC | 14}, \
2421 {"$v15", RTYPE_VEC | 15}, \
2422 {"$v16", RTYPE_VEC | 16}, \
2423 {"$v17", RTYPE_VEC | 17}, \
2424 {"$v18", RTYPE_VEC | 18}, \
2425 {"$v19", RTYPE_VEC | 19}, \
2426 {"$v20", RTYPE_VEC | 20}, \
2427 {"$v21", RTYPE_VEC | 21}, \
2428 {"$v22", RTYPE_VEC | 22}, \
2429 {"$v23", RTYPE_VEC | 23}, \
2430 {"$v24", RTYPE_VEC | 24}, \
2431 {"$v25", RTYPE_VEC | 25}, \
2432 {"$v26", RTYPE_VEC | 26}, \
2433 {"$v27", RTYPE_VEC | 27}, \
2434 {"$v28", RTYPE_VEC | 28}, \
2435 {"$v29", RTYPE_VEC | 29}, \
2436 {"$v30", RTYPE_VEC | 30}, \
2437 {"$v31", RTYPE_VEC | 31}
2439 #define MIPS_DSP_ACCUMULATOR_NAMES \
2440 {"$ac0", RTYPE_ACC | 0}, \
2441 {"$ac1", RTYPE_ACC | 1}, \
2442 {"$ac2", RTYPE_ACC | 2}, \
2443 {"$ac3", RTYPE_ACC | 3}
2445 static const struct regname reg_names[] = {
2446 GENERIC_REGISTER_NUMBERS,
2448 FPU_CONDITION_CODE_NAMES,
2449 COPROC_CONDITION_CODE_NAMES,
2451 /* The $txx registers depends on the abi,
2452 these will be added later into the symbol table from
2453 one of the tables below once mips_abi is set after
2454 parsing of arguments from the command line. */
2455 SYMBOLIC_REGISTER_NAMES,
2457 MIPS16_SPECIAL_REGISTER_NAMES,
2458 MDMX_VECTOR_REGISTER_NAMES,
2459 MIPS_DSP_ACCUMULATOR_NAMES,
2463 static const struct regname reg_names_o32[] = {
2464 O32_SYMBOLIC_REGISTER_NAMES,
2468 static const struct regname reg_names_n32n64[] = {
2469 N32N64_SYMBOLIC_REGISTER_NAMES,
2473 /* Check if S points at a valid register specifier according to TYPES.
2474 If so, then return 1, advance S to consume the specifier and store
2475 the register's number in REGNOP, otherwise return 0. */
2478 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2485 /* Find end of name. */
2487 if (is_name_beginner (*e))
2489 while (is_part_of_name (*e))
2492 /* Terminate name. */
2496 /* Look for a register symbol. */
2497 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2499 int r = S_GET_VALUE (symbolP);
2501 reg = r & RNUM_MASK;
2502 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2503 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2504 reg = (r & RNUM_MASK) - 2;
2506 /* Else see if this is a register defined in an itbl entry. */
2507 else if ((types & RTYPE_GP) && itbl_have_entries)
2514 if (itbl_get_reg_val (n, &r))
2515 reg = r & RNUM_MASK;
2518 /* Advance to next token if a register was recognised. */
2521 else if (types & RWARN)
2522 as_warn (_("Unrecognized register name `%s'"), *s);
2530 /* Check if S points at a valid register list according to TYPES.
2531 If so, then return 1, advance S to consume the list and store
2532 the registers present on the list as a bitmask of ones in REGLISTP,
2533 otherwise return 0. A valid list comprises a comma-separated
2534 enumeration of valid single registers and/or dash-separated
2535 contiguous register ranges as determined by their numbers.
2537 As a special exception if one of s0-s7 registers is specified as
2538 the range's lower delimiter and s8 (fp) is its upper one, then no
2539 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2540 are selected; they have to be listed separately if needed. */
2543 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2545 unsigned int reglist = 0;
2546 unsigned int lastregno;
2547 bfd_boolean ok = TRUE;
2548 unsigned int regmask;
2549 char *s_endlist = *s;
2553 while (reg_lookup (s, types, ®no))
2559 ok = reg_lookup (s, types, &lastregno);
2560 if (ok && lastregno < regno)
2566 if (lastregno == FP && regno >= S0 && regno <= S7)
2571 regmask = 1 << lastregno;
2572 regmask = (regmask << 1) - 1;
2573 regmask ^= (1 << regno) - 1;
2587 *reglistp = reglist;
2588 return ok && reglist != 0;
2592 mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
2593 const unsigned int *map1, const unsigned int *map2,
2598 for (i = 0; i < count; i++)
2599 if (map1[i] == regno1 && map2[i] == regno2)
2604 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2605 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2608 is_opcode_valid (const struct mips_opcode *mo)
2610 int isa = mips_opts.isa;
2611 int ase = mips_opts.ase;
2615 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2616 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2617 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2618 ase |= mips_ases[i].flags64;
2620 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2623 /* Check whether the instruction or macro requires single-precision or
2624 double-precision floating-point support. Note that this information is
2625 stored differently in the opcode table for insns and macros. */
2626 if (mo->pinfo == INSN_MACRO)
2628 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2629 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2633 fp_s = mo->pinfo & FP_S;
2634 fp_d = mo->pinfo & FP_D;
2637 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2640 if (fp_s && mips_opts.soft_float)
2646 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2647 selected ISA and architecture. */
2650 is_opcode_valid_16 (const struct mips_opcode *mo)
2652 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2655 /* Return TRUE if the size of the microMIPS opcode MO matches one
2656 explicitly requested. Always TRUE in the standard MIPS mode. */
2659 is_size_valid (const struct mips_opcode *mo)
2661 if (!mips_opts.micromips)
2664 if (mips_opts.insn32)
2666 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2668 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2671 if (!forced_insn_length)
2673 if (mo->pinfo == INSN_MACRO)
2675 return forced_insn_length == micromips_insn_length (mo);
2678 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2679 of the preceding instruction. Always TRUE in the standard MIPS mode.
2681 We don't accept macros in 16-bit delay slots to avoid a case where
2682 a macro expansion fails because it relies on a preceding 32-bit real
2683 instruction to have matched and does not handle the operands correctly.
2684 The only macros that may expand to 16-bit instructions are JAL that
2685 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2686 and BGT (that likewise cannot be placed in a delay slot) that decay to
2687 a NOP. In all these cases the macros precede any corresponding real
2688 instruction definitions in the opcode table, so they will match in the
2689 second pass where the size of the delay slot is ignored and therefore
2690 produce correct code. */
2693 is_delay_slot_valid (const struct mips_opcode *mo)
2695 if (!mips_opts.micromips)
2698 if (mo->pinfo == INSN_MACRO)
2699 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2700 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2701 && micromips_insn_length (mo) != 4)
2703 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2704 && micromips_insn_length (mo) != 2)
2710 /* This function is called once, at assembler startup time. It should set up
2711 all the tables, etc. that the MD part of the assembler will need. */
2716 const char *retval = NULL;
2720 if (mips_pic != NO_PIC)
2722 if (g_switch_seen && g_switch_value != 0)
2723 as_bad (_("-G may not be used in position-independent code"));
2727 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2728 as_warn (_("Could not set architecture and machine"));
2730 op_hash = hash_new ();
2732 for (i = 0; i < NUMOPCODES;)
2734 const char *name = mips_opcodes[i].name;
2736 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2739 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2740 mips_opcodes[i].name, retval);
2741 /* Probably a memory allocation problem? Give up now. */
2742 as_fatal (_("Broken assembler. No assembly attempted."));
2746 if (mips_opcodes[i].pinfo != INSN_MACRO)
2748 if (!validate_mips_insn (&mips_opcodes[i]))
2750 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2752 create_insn (&nop_insn, mips_opcodes + i);
2753 if (mips_fix_loongson2f_nop)
2754 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2755 nop_insn.fixed_p = 1;
2760 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2763 mips16_op_hash = hash_new ();
2766 while (i < bfd_mips16_num_opcodes)
2768 const char *name = mips16_opcodes[i].name;
2770 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2772 as_fatal (_("internal: can't hash `%s': %s"),
2773 mips16_opcodes[i].name, retval);
2776 if (mips16_opcodes[i].pinfo != INSN_MACRO
2777 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2778 != mips16_opcodes[i].match))
2780 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2781 mips16_opcodes[i].name, mips16_opcodes[i].args);
2784 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2786 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2787 mips16_nop_insn.fixed_p = 1;
2791 while (i < bfd_mips16_num_opcodes
2792 && strcmp (mips16_opcodes[i].name, name) == 0);
2795 micromips_op_hash = hash_new ();
2798 while (i < bfd_micromips_num_opcodes)
2800 const char *name = micromips_opcodes[i].name;
2802 retval = hash_insert (micromips_op_hash, name,
2803 (void *) µmips_opcodes[i]);
2805 as_fatal (_("internal: can't hash `%s': %s"),
2806 micromips_opcodes[i].name, retval);
2808 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2810 struct mips_cl_insn *micromips_nop_insn;
2812 if (!validate_micromips_insn (µmips_opcodes[i]))
2815 if (micromips_insn_length (micromips_opcodes + i) == 2)
2816 micromips_nop_insn = µmips_nop16_insn;
2817 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2818 micromips_nop_insn = µmips_nop32_insn;
2822 if (micromips_nop_insn->insn_mo == NULL
2823 && strcmp (name, "nop") == 0)
2825 create_insn (micromips_nop_insn, micromips_opcodes + i);
2826 micromips_nop_insn->fixed_p = 1;
2829 while (++i < bfd_micromips_num_opcodes
2830 && strcmp (micromips_opcodes[i].name, name) == 0);
2834 as_fatal (_("Broken assembler. No assembly attempted."));
2836 /* We add all the general register names to the symbol table. This
2837 helps us detect invalid uses of them. */
2838 for (i = 0; reg_names[i].name; i++)
2839 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2840 reg_names[i].num, /* & RNUM_MASK, */
2841 &zero_address_frag));
2843 for (i = 0; reg_names_n32n64[i].name; i++)
2844 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2845 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2846 &zero_address_frag));
2848 for (i = 0; reg_names_o32[i].name; i++)
2849 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2850 reg_names_o32[i].num, /* & RNUM_MASK, */
2851 &zero_address_frag));
2853 mips_no_prev_insn ();
2856 mips_cprmask[0] = 0;
2857 mips_cprmask[1] = 0;
2858 mips_cprmask[2] = 0;
2859 mips_cprmask[3] = 0;
2861 /* set the default alignment for the text section (2**2) */
2862 record_alignment (text_section, 2);
2864 bfd_set_gp_size (stdoutput, g_switch_value);
2866 /* On a native system other than VxWorks, sections must be aligned
2867 to 16 byte boundaries. When configured for an embedded ELF
2868 target, we don't bother. */
2869 if (strncmp (TARGET_OS, "elf", 3) != 0
2870 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2872 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2873 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2874 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2877 /* Create a .reginfo section for register masks and a .mdebug
2878 section for debugging information. */
2886 subseg = now_subseg;
2888 /* The ABI says this section should be loaded so that the
2889 running program can access it. However, we don't load it
2890 if we are configured for an embedded target */
2891 flags = SEC_READONLY | SEC_DATA;
2892 if (strncmp (TARGET_OS, "elf", 3) != 0)
2893 flags |= SEC_ALLOC | SEC_LOAD;
2895 if (mips_abi != N64_ABI)
2897 sec = subseg_new (".reginfo", (subsegT) 0);
2899 bfd_set_section_flags (stdoutput, sec, flags);
2900 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2902 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2906 /* The 64-bit ABI uses a .MIPS.options section rather than
2907 .reginfo section. */
2908 sec = subseg_new (".MIPS.options", (subsegT) 0);
2909 bfd_set_section_flags (stdoutput, sec, flags);
2910 bfd_set_section_alignment (stdoutput, sec, 3);
2912 /* Set up the option header. */
2914 Elf_Internal_Options opthdr;
2917 opthdr.kind = ODK_REGINFO;
2918 opthdr.size = (sizeof (Elf_External_Options)
2919 + sizeof (Elf64_External_RegInfo));
2922 f = frag_more (sizeof (Elf_External_Options));
2923 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2924 (Elf_External_Options *) f);
2926 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2930 if (ECOFF_DEBUGGING)
2932 sec = subseg_new (".mdebug", (subsegT) 0);
2933 (void) bfd_set_section_flags (stdoutput, sec,
2934 SEC_HAS_CONTENTS | SEC_READONLY);
2935 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2937 else if (mips_flag_pdr)
2939 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2940 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2941 SEC_READONLY | SEC_RELOC
2943 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2946 subseg_set (seg, subseg);
2949 if (! ECOFF_DEBUGGING)
2952 if (mips_fix_vr4120)
2953 init_vr4120_conflicts ();
2959 mips_emit_delays ();
2960 if (! ECOFF_DEBUGGING)
2965 md_assemble (char *str)
2967 struct mips_cl_insn insn;
2968 bfd_reloc_code_real_type unused_reloc[3]
2969 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2971 imm_expr.X_op = O_absent;
2972 imm2_expr.X_op = O_absent;
2973 offset_expr.X_op = O_absent;
2974 offset_reloc[0] = BFD_RELOC_UNUSED;
2975 offset_reloc[1] = BFD_RELOC_UNUSED;
2976 offset_reloc[2] = BFD_RELOC_UNUSED;
2978 mips_mark_labels ();
2979 mips_assembling_insn = TRUE;
2981 if (mips_opts.mips16)
2982 mips16_ip (str, &insn);
2985 mips_ip (str, &insn);
2986 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2987 str, insn.insn_opcode));
2991 as_bad ("%s `%s'", insn_error, str);
2992 else if (insn.insn_mo->pinfo == INSN_MACRO)
2995 if (mips_opts.mips16)
2996 mips16_macro (&insn);
3003 if (offset_expr.X_op != O_absent)
3004 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3006 append_insn (&insn, NULL, unused_reloc, FALSE);
3009 mips_assembling_insn = FALSE;
3012 /* Convenience functions for abstracting away the differences between
3013 MIPS16 and non-MIPS16 relocations. */
3015 static inline bfd_boolean
3016 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3020 case BFD_RELOC_MIPS16_JMP:
3021 case BFD_RELOC_MIPS16_GPREL:
3022 case BFD_RELOC_MIPS16_GOT16:
3023 case BFD_RELOC_MIPS16_CALL16:
3024 case BFD_RELOC_MIPS16_HI16_S:
3025 case BFD_RELOC_MIPS16_HI16:
3026 case BFD_RELOC_MIPS16_LO16:
3034 static inline bfd_boolean
3035 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3039 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3040 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3041 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3042 case BFD_RELOC_MICROMIPS_GPREL16:
3043 case BFD_RELOC_MICROMIPS_JMP:
3044 case BFD_RELOC_MICROMIPS_HI16:
3045 case BFD_RELOC_MICROMIPS_HI16_S:
3046 case BFD_RELOC_MICROMIPS_LO16:
3047 case BFD_RELOC_MICROMIPS_LITERAL:
3048 case BFD_RELOC_MICROMIPS_GOT16:
3049 case BFD_RELOC_MICROMIPS_CALL16:
3050 case BFD_RELOC_MICROMIPS_GOT_HI16:
3051 case BFD_RELOC_MICROMIPS_GOT_LO16:
3052 case BFD_RELOC_MICROMIPS_CALL_HI16:
3053 case BFD_RELOC_MICROMIPS_CALL_LO16:
3054 case BFD_RELOC_MICROMIPS_SUB:
3055 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3056 case BFD_RELOC_MICROMIPS_GOT_OFST:
3057 case BFD_RELOC_MICROMIPS_GOT_DISP:
3058 case BFD_RELOC_MICROMIPS_HIGHEST:
3059 case BFD_RELOC_MICROMIPS_HIGHER:
3060 case BFD_RELOC_MICROMIPS_SCN_DISP:
3061 case BFD_RELOC_MICROMIPS_JALR:
3069 static inline bfd_boolean
3070 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3072 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3075 static inline bfd_boolean
3076 got16_reloc_p (bfd_reloc_code_real_type reloc)
3078 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3079 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3082 static inline bfd_boolean
3083 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3085 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3086 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3089 static inline bfd_boolean
3090 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3092 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3093 || reloc == BFD_RELOC_MICROMIPS_LO16);
3096 static inline bfd_boolean
3097 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3099 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3102 static inline bfd_boolean
3103 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3105 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3106 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3109 /* Return true if RELOC is a PC-relative relocation that does not have
3110 full address range. */
3112 static inline bfd_boolean
3113 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3117 case BFD_RELOC_16_PCREL_S2:
3118 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3119 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3120 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3123 case BFD_RELOC_32_PCREL:
3124 return HAVE_64BIT_ADDRESSES;
3131 /* Return true if the given relocation might need a matching %lo().
3132 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3133 need a matching %lo() when applied to local symbols. */
3135 static inline bfd_boolean
3136 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3138 return (HAVE_IN_PLACE_ADDENDS
3139 && (hi16_reloc_p (reloc)
3140 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3141 all GOT16 relocations evaluate to "G". */
3142 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3145 /* Return the type of %lo() reloc needed by RELOC, given that
3146 reloc_needs_lo_p. */
3148 static inline bfd_reloc_code_real_type
3149 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3151 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3152 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3156 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3159 static inline bfd_boolean
3160 fixup_has_matching_lo_p (fixS *fixp)
3162 return (fixp->fx_next != NULL
3163 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3164 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3165 && fixp->fx_offset == fixp->fx_next->fx_offset);
3168 /* This function returns true if modifying a register requires a
3172 reg_needs_delay (unsigned int reg)
3174 unsigned long prev_pinfo;
3176 prev_pinfo = history[0].insn_mo->pinfo;
3177 if (! mips_opts.noreorder
3178 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3179 && ! gpr_interlocks)
3180 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3181 && ! cop_interlocks)))
3183 /* A load from a coprocessor or from memory. All load delays
3184 delay the use of general register rt for one instruction. */
3185 /* Itbl support may require additional care here. */
3186 know (prev_pinfo & INSN_WRITE_GPR_T);
3187 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3194 /* Move all labels in LABELS to the current insertion point. TEXT_P
3195 says whether the labels refer to text or data. */
3198 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3200 struct insn_label_list *l;
3203 for (l = labels; l != NULL; l = l->next)
3205 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3206 symbol_set_frag (l->label, frag_now);
3207 val = (valueT) frag_now_fix ();
3208 /* MIPS16/microMIPS text labels are stored as odd. */
3209 if (text_p && HAVE_CODE_COMPRESSION)
3211 S_SET_VALUE (l->label, val);
3215 /* Move all labels in insn_labels to the current insertion point
3216 and treat them as text labels. */
3219 mips_move_text_labels (void)
3221 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3225 s_is_linkonce (symbolS *sym, segT from_seg)
3227 bfd_boolean linkonce = FALSE;
3228 segT symseg = S_GET_SEGMENT (sym);
3230 if (symseg != from_seg && !S_IS_LOCAL (sym))
3232 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3234 /* The GNU toolchain uses an extension for ELF: a section
3235 beginning with the magic string .gnu.linkonce is a
3236 linkonce section. */
3237 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3238 sizeof ".gnu.linkonce" - 1) == 0)
3244 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3245 linker to handle them specially, such as generating jalx instructions
3246 when needed. We also make them odd for the duration of the assembly,
3247 in order to generate the right sort of code. We will make them even
3248 in the adjust_symtab routine, while leaving them marked. This is
3249 convenient for the debugger and the disassembler. The linker knows
3250 to make them odd again. */
3253 mips_compressed_mark_label (symbolS *label)
3255 gas_assert (HAVE_CODE_COMPRESSION);
3257 if (mips_opts.mips16)
3258 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3260 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3261 if ((S_GET_VALUE (label) & 1) == 0
3262 /* Don't adjust the address if the label is global or weak, or
3263 in a link-once section, since we'll be emitting symbol reloc
3264 references to it which will be patched up by the linker, and
3265 the final value of the symbol may or may not be MIPS16/microMIPS. */
3266 && !S_IS_WEAK (label)
3267 && !S_IS_EXTERNAL (label)
3268 && !s_is_linkonce (label, now_seg))
3269 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3272 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3275 mips_compressed_mark_labels (void)
3277 struct insn_label_list *l;
3279 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3280 mips_compressed_mark_label (l->label);
3283 /* End the current frag. Make it a variant frag and record the
3287 relax_close_frag (void)
3289 mips_macro_warning.first_frag = frag_now;
3290 frag_var (rs_machine_dependent, 0, 0,
3291 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3292 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3294 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3295 mips_relax.first_fixup = 0;
3298 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3299 See the comment above RELAX_ENCODE for more details. */
3302 relax_start (symbolS *symbol)
3304 gas_assert (mips_relax.sequence == 0);
3305 mips_relax.sequence = 1;
3306 mips_relax.symbol = symbol;
3309 /* Start generating the second version of a relaxable sequence.
3310 See the comment above RELAX_ENCODE for more details. */
3315 gas_assert (mips_relax.sequence == 1);
3316 mips_relax.sequence = 2;
3319 /* End the current relaxable sequence. */
3324 gas_assert (mips_relax.sequence == 2);
3325 relax_close_frag ();
3326 mips_relax.sequence = 0;
3329 /* Return true if IP is a delayed branch or jump. */
3331 static inline bfd_boolean
3332 delayed_branch_p (const struct mips_cl_insn *ip)
3334 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3335 | INSN_COND_BRANCH_DELAY
3336 | INSN_COND_BRANCH_LIKELY)) != 0;
3339 /* Return true if IP is a compact branch or jump. */
3341 static inline bfd_boolean
3342 compact_branch_p (const struct mips_cl_insn *ip)
3344 if (mips_opts.mips16)
3345 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3346 | MIPS16_INSN_COND_BRANCH)) != 0;
3348 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3349 | INSN2_COND_BRANCH)) != 0;
3352 /* Return true if IP is an unconditional branch or jump. */
3354 static inline bfd_boolean
3355 uncond_branch_p (const struct mips_cl_insn *ip)
3357 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3358 || (mips_opts.mips16
3359 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3360 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3363 /* Return true if IP is a branch-likely instruction. */
3365 static inline bfd_boolean
3366 branch_likely_p (const struct mips_cl_insn *ip)
3368 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3371 /* Return the type of nop that should be used to fill the delay slot
3372 of delayed branch IP. */
3374 static struct mips_cl_insn *
3375 get_delay_slot_nop (const struct mips_cl_insn *ip)
3377 if (mips_opts.micromips
3378 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3379 return µmips_nop32_insn;
3383 /* Return the mask of core registers that IP reads or writes. */
3386 gpr_mod_mask (const struct mips_cl_insn *ip)
3388 unsigned long pinfo2;
3392 pinfo2 = ip->insn_mo->pinfo2;
3393 if (mips_opts.micromips)
3395 if (pinfo2 & INSN2_MOD_GPR_MD)
3396 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3397 if (pinfo2 & INSN2_MOD_GPR_MF)
3398 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3399 if (pinfo2 & INSN2_MOD_SP)
3405 /* Return the mask of core registers that IP reads. */
3408 gpr_read_mask (const struct mips_cl_insn *ip)
3410 unsigned long pinfo, pinfo2;
3413 mask = gpr_mod_mask (ip);
3414 pinfo = ip->insn_mo->pinfo;
3415 pinfo2 = ip->insn_mo->pinfo2;
3416 if (mips_opts.mips16)
3418 if (pinfo & MIPS16_INSN_READ_X)
3419 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3420 if (pinfo & MIPS16_INSN_READ_Y)
3421 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3422 if (pinfo & MIPS16_INSN_READ_T)
3424 if (pinfo & MIPS16_INSN_READ_SP)
3426 if (pinfo & MIPS16_INSN_READ_31)
3428 if (pinfo & MIPS16_INSN_READ_Z)
3429 mask |= 1 << (mips16_to_32_reg_map
3430 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3431 if (pinfo & MIPS16_INSN_READ_GPR_X)
3432 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3436 if (pinfo2 & INSN2_READ_GPR_D)
3437 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3438 if (pinfo & INSN_READ_GPR_T)
3439 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3440 if (pinfo & INSN_READ_GPR_S)
3441 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3442 if (pinfo2 & INSN2_READ_GP)
3444 if (pinfo2 & INSN2_READ_GPR_31)
3446 if (pinfo2 & INSN2_READ_GPR_Z)
3447 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3449 if (mips_opts.micromips)
3451 if (pinfo2 & INSN2_READ_GPR_MC)
3452 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3453 if (pinfo2 & INSN2_READ_GPR_ME)
3454 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3455 if (pinfo2 & INSN2_READ_GPR_MG)
3456 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3457 if (pinfo2 & INSN2_READ_GPR_MJ)
3458 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3459 if (pinfo2 & INSN2_READ_GPR_MMN)
3461 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3462 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3464 if (pinfo2 & INSN2_READ_GPR_MP)
3465 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3466 if (pinfo2 & INSN2_READ_GPR_MQ)
3467 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3469 /* Don't include register 0. */
3473 /* Return the mask of core registers that IP writes. */
3476 gpr_write_mask (const struct mips_cl_insn *ip)
3478 unsigned long pinfo, pinfo2;
3481 mask = gpr_mod_mask (ip);
3482 pinfo = ip->insn_mo->pinfo;
3483 pinfo2 = ip->insn_mo->pinfo2;
3484 if (mips_opts.mips16)
3486 if (pinfo & MIPS16_INSN_WRITE_X)
3487 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3488 if (pinfo & MIPS16_INSN_WRITE_Y)
3489 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3490 if (pinfo & MIPS16_INSN_WRITE_Z)
3491 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3492 if (pinfo & MIPS16_INSN_WRITE_T)
3494 if (pinfo & MIPS16_INSN_WRITE_SP)
3496 if (pinfo & MIPS16_INSN_WRITE_31)
3498 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3499 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3503 if (pinfo & INSN_WRITE_GPR_D)
3504 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3505 if (pinfo & INSN_WRITE_GPR_T)
3506 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3507 if (pinfo & INSN_WRITE_GPR_S)
3508 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3509 if (pinfo & INSN_WRITE_GPR_31)
3511 if (pinfo2 & INSN2_WRITE_GPR_Z)
3512 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3514 if (mips_opts.micromips)
3516 if (pinfo2 & INSN2_WRITE_GPR_MB)
3517 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3518 if (pinfo2 & INSN2_WRITE_GPR_MH)
3520 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3521 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3523 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3524 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3525 if (pinfo2 & INSN2_WRITE_GPR_MP)
3526 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3528 /* Don't include register 0. */
3532 /* Return the mask of floating-point registers that IP reads. */
3535 fpr_read_mask (const struct mips_cl_insn *ip)
3537 unsigned long pinfo, pinfo2;
3541 pinfo = ip->insn_mo->pinfo;
3542 pinfo2 = ip->insn_mo->pinfo2;
3543 if (!mips_opts.mips16)
3545 if (pinfo2 & INSN2_READ_FPR_D)
3546 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3547 if (pinfo & INSN_READ_FPR_S)
3548 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3549 if (pinfo & INSN_READ_FPR_T)
3550 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3551 if (pinfo & INSN_READ_FPR_R)
3552 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3553 if (pinfo2 & INSN2_READ_FPR_Z)
3554 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3556 /* Conservatively treat all operands to an FP_D instruction are doubles.
3557 (This is overly pessimistic for things like cvt.d.s.) */
3558 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3563 /* Return the mask of floating-point registers that IP writes. */
3566 fpr_write_mask (const struct mips_cl_insn *ip)
3568 unsigned long pinfo, pinfo2;
3572 pinfo = ip->insn_mo->pinfo;
3573 pinfo2 = ip->insn_mo->pinfo2;
3574 if (!mips_opts.mips16)
3576 if (pinfo & INSN_WRITE_FPR_D)
3577 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3578 if (pinfo & INSN_WRITE_FPR_S)
3579 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3580 if (pinfo & INSN_WRITE_FPR_T)
3581 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3582 if (pinfo2 & INSN2_WRITE_FPR_Z)
3583 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3585 /* Conservatively treat all operands to an FP_D instruction are doubles.
3586 (This is overly pessimistic for things like cvt.s.d.) */
3587 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3592 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3593 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3594 by VR4120 errata. */
3597 classify_vr4120_insn (const char *name)
3599 if (strncmp (name, "macc", 4) == 0)
3600 return FIX_VR4120_MACC;
3601 if (strncmp (name, "dmacc", 5) == 0)
3602 return FIX_VR4120_DMACC;
3603 if (strncmp (name, "mult", 4) == 0)
3604 return FIX_VR4120_MULT;
3605 if (strncmp (name, "dmult", 5) == 0)
3606 return FIX_VR4120_DMULT;
3607 if (strstr (name, "div"))
3608 return FIX_VR4120_DIV;
3609 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3610 return FIX_VR4120_MTHILO;
3611 return NUM_FIX_VR4120_CLASSES;
3614 #define INSN_ERET 0x42000018
3615 #define INSN_DERET 0x4200001f
3617 /* Return the number of instructions that must separate INSN1 and INSN2,
3618 where INSN1 is the earlier instruction. Return the worst-case value
3619 for any INSN2 if INSN2 is null. */
3622 insns_between (const struct mips_cl_insn *insn1,
3623 const struct mips_cl_insn *insn2)
3625 unsigned long pinfo1, pinfo2;
3628 /* This function needs to know which pinfo flags are set for INSN2
3629 and which registers INSN2 uses. The former is stored in PINFO2 and
3630 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3631 will have every flag set and INSN2_USES_GPR will always return true. */
3632 pinfo1 = insn1->insn_mo->pinfo;
3633 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3635 #define INSN2_USES_GPR(REG) \
3636 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3638 /* For most targets, write-after-read dependencies on the HI and LO
3639 registers must be separated by at least two instructions. */
3640 if (!hilo_interlocks)
3642 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3644 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3648 /* If we're working around r7000 errata, there must be two instructions
3649 between an mfhi or mflo and any instruction that uses the result. */
3650 if (mips_7000_hilo_fix
3651 && !mips_opts.micromips
3652 && MF_HILO_INSN (pinfo1)
3653 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3656 /* If we're working around 24K errata, one instruction is required
3657 if an ERET or DERET is followed by a branch instruction. */
3658 if (mips_fix_24k && !mips_opts.micromips)
3660 if (insn1->insn_opcode == INSN_ERET
3661 || insn1->insn_opcode == INSN_DERET)
3664 || insn2->insn_opcode == INSN_ERET
3665 || insn2->insn_opcode == INSN_DERET
3666 || delayed_branch_p (insn2))
3671 /* If working around VR4120 errata, check for combinations that need
3672 a single intervening instruction. */
3673 if (mips_fix_vr4120 && !mips_opts.micromips)
3675 unsigned int class1, class2;
3677 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3678 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3682 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3683 if (vr4120_conflicts[class1] & (1 << class2))
3688 if (!HAVE_CODE_COMPRESSION)
3690 /* Check for GPR or coprocessor load delays. All such delays
3691 are on the RT register. */
3692 /* Itbl support may require additional care here. */
3693 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3694 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3696 know (pinfo1 & INSN_WRITE_GPR_T);
3697 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3701 /* Check for generic coprocessor hazards.
3703 This case is not handled very well. There is no special
3704 knowledge of CP0 handling, and the coprocessors other than
3705 the floating point unit are not distinguished at all. */
3706 /* Itbl support may require additional care here. FIXME!
3707 Need to modify this to include knowledge about
3708 user specified delays! */
3709 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3710 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3712 /* Handle cases where INSN1 writes to a known general coprocessor
3713 register. There must be a one instruction delay before INSN2
3714 if INSN2 reads that register, otherwise no delay is needed. */
3715 mask = fpr_write_mask (insn1);
3718 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3723 /* Read-after-write dependencies on the control registers
3724 require a two-instruction gap. */
3725 if ((pinfo1 & INSN_WRITE_COND_CODE)
3726 && (pinfo2 & INSN_READ_COND_CODE))
3729 /* We don't know exactly what INSN1 does. If INSN2 is
3730 also a coprocessor instruction, assume there must be
3731 a one instruction gap. */
3732 if (pinfo2 & INSN_COP)
3737 /* Check for read-after-write dependencies on the coprocessor
3738 control registers in cases where INSN1 does not need a general
3739 coprocessor delay. This means that INSN1 is a floating point
3740 comparison instruction. */
3741 /* Itbl support may require additional care here. */
3742 else if (!cop_interlocks
3743 && (pinfo1 & INSN_WRITE_COND_CODE)
3744 && (pinfo2 & INSN_READ_COND_CODE))
3748 #undef INSN2_USES_GPR
3753 /* Return the number of nops that would be needed to work around the
3754 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3755 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3756 that are contained within the first IGNORE instructions of HIST. */
3759 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3760 const struct mips_cl_insn *insn)
3765 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3766 are not affected by the errata. */
3768 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3769 || strcmp (insn->insn_mo->name, "mtlo") == 0
3770 || strcmp (insn->insn_mo->name, "mthi") == 0))
3773 /* Search for the first MFLO or MFHI. */
3774 for (i = 0; i < MAX_VR4130_NOPS; i++)
3775 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3777 /* Extract the destination register. */
3778 mask = gpr_write_mask (&hist[i]);
3780 /* No nops are needed if INSN reads that register. */
3781 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3784 /* ...or if any of the intervening instructions do. */
3785 for (j = 0; j < i; j++)
3786 if (gpr_read_mask (&hist[j]) & mask)
3790 return MAX_VR4130_NOPS - i;
3795 #define BASE_REG_EQ(INSN1, INSN2) \
3796 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3797 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3799 /* Return the minimum alignment for this store instruction. */
3802 fix_24k_align_to (const struct mips_opcode *mo)
3804 if (strcmp (mo->name, "sh") == 0)
3807 if (strcmp (mo->name, "swc1") == 0
3808 || strcmp (mo->name, "swc2") == 0
3809 || strcmp (mo->name, "sw") == 0
3810 || strcmp (mo->name, "sc") == 0
3811 || strcmp (mo->name, "s.s") == 0)
3814 if (strcmp (mo->name, "sdc1") == 0
3815 || strcmp (mo->name, "sdc2") == 0
3816 || strcmp (mo->name, "s.d") == 0)
3823 struct fix_24k_store_info
3825 /* Immediate offset, if any, for this store instruction. */
3827 /* Alignment required by this store instruction. */
3829 /* True for register offsets. */
3830 int register_offset;
3833 /* Comparison function used by qsort. */
3836 fix_24k_sort (const void *a, const void *b)
3838 const struct fix_24k_store_info *pos1 = a;
3839 const struct fix_24k_store_info *pos2 = b;
3841 return (pos1->off - pos2->off);
3844 /* INSN is a store instruction. Try to record the store information
3845 in STINFO. Return false if the information isn't known. */
3848 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3849 const struct mips_cl_insn *insn)
3851 /* The instruction must have a known offset. */
3852 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3855 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3856 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3860 /* Return the number of nops that would be needed to work around the 24k
3861 "lost data on stores during refill" errata if instruction INSN
3862 immediately followed the 2 instructions described by HIST.
3863 Ignore hazards that are contained within the first IGNORE
3864 instructions of HIST.
3866 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3867 for the data cache refills and store data. The following describes
3868 the scenario where the store data could be lost.
3870 * A data cache miss, due to either a load or a store, causing fill
3871 data to be supplied by the memory subsystem
3872 * The first three doublewords of fill data are returned and written
3874 * A sequence of four stores occurs in consecutive cycles around the
3875 final doubleword of the fill:
3879 * Zero, One or more instructions
3882 The four stores A-D must be to different doublewords of the line that
3883 is being filled. The fourth instruction in the sequence above permits
3884 the fill of the final doubleword to be transferred from the FSB into
3885 the cache. In the sequence above, the stores may be either integer
3886 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3887 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3888 different doublewords on the line. If the floating point unit is
3889 running in 1:2 mode, it is not possible to create the sequence above
3890 using only floating point store instructions.
3892 In this case, the cache line being filled is incorrectly marked
3893 invalid, thereby losing the data from any store to the line that
3894 occurs between the original miss and the completion of the five
3895 cycle sequence shown above.
3897 The workarounds are:
3899 * Run the data cache in write-through mode.
3900 * Insert a non-store instruction between
3901 Store A and Store B or Store B and Store C. */
3904 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3905 const struct mips_cl_insn *insn)
3907 struct fix_24k_store_info pos[3];
3908 int align, i, base_offset;
3913 /* If the previous instruction wasn't a store, there's nothing to
3915 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3918 /* If the instructions after the previous one are unknown, we have
3919 to assume the worst. */
3923 /* Check whether we are dealing with three consecutive stores. */
3924 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3925 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3928 /* If we don't know the relationship between the store addresses,
3929 assume the worst. */
3930 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3931 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3934 if (!fix_24k_record_store_info (&pos[0], insn)
3935 || !fix_24k_record_store_info (&pos[1], &hist[0])
3936 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3939 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3941 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3942 X bytes and such that the base register + X is known to be aligned
3945 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3949 align = pos[0].align_to;
3950 base_offset = pos[0].off;
3951 for (i = 1; i < 3; i++)
3952 if (align < pos[i].align_to)
3954 align = pos[i].align_to;
3955 base_offset = pos[i].off;
3957 for (i = 0; i < 3; i++)
3958 pos[i].off -= base_offset;
3961 pos[0].off &= ~align + 1;
3962 pos[1].off &= ~align + 1;
3963 pos[2].off &= ~align + 1;
3965 /* If any two stores write to the same chunk, they also write to the
3966 same doubleword. The offsets are still sorted at this point. */
3967 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3970 /* A range of at least 9 bytes is needed for the stores to be in
3971 non-overlapping doublewords. */
3972 if (pos[2].off - pos[0].off <= 8)
3975 if (pos[2].off - pos[1].off >= 24
3976 || pos[1].off - pos[0].off >= 24
3977 || pos[2].off - pos[0].off >= 32)
3983 /* Return the number of nops that would be needed if instruction INSN
3984 immediately followed the MAX_NOPS instructions given by HIST,
3985 where HIST[0] is the most recent instruction. Ignore hazards
3986 between INSN and the first IGNORE instructions in HIST.
3988 If INSN is null, return the worse-case number of nops for any
3992 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3993 const struct mips_cl_insn *insn)
3995 int i, nops, tmp_nops;
3998 for (i = ignore; i < MAX_DELAY_NOPS; i++)
4000 tmp_nops = insns_between (hist + i, insn) - i;
4001 if (tmp_nops > nops)
4005 if (mips_fix_vr4130 && !mips_opts.micromips)
4007 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
4008 if (tmp_nops > nops)
4012 if (mips_fix_24k && !mips_opts.micromips)
4014 tmp_nops = nops_for_24k (ignore, hist, insn);
4015 if (tmp_nops > nops)
4022 /* The variable arguments provide NUM_INSNS extra instructions that
4023 might be added to HIST. Return the largest number of nops that
4024 would be needed after the extended sequence, ignoring hazards
4025 in the first IGNORE instructions. */
4028 nops_for_sequence (int num_insns, int ignore,
4029 const struct mips_cl_insn *hist, ...)
4032 struct mips_cl_insn buffer[MAX_NOPS];
4033 struct mips_cl_insn *cursor;
4036 va_start (args, hist);
4037 cursor = buffer + num_insns;
4038 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4039 while (cursor > buffer)
4040 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4042 nops = nops_for_insn (ignore, buffer, NULL);
4047 /* Like nops_for_insn, but if INSN is a branch, take into account the
4048 worst-case delay for the branch target. */
4051 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4052 const struct mips_cl_insn *insn)
4056 nops = nops_for_insn (ignore, hist, insn);
4057 if (delayed_branch_p (insn))
4059 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4060 hist, insn, get_delay_slot_nop (insn));
4061 if (tmp_nops > nops)
4064 else if (compact_branch_p (insn))
4066 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4067 if (tmp_nops > nops)
4073 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4076 fix_loongson2f_nop (struct mips_cl_insn * ip)
4078 gas_assert (!HAVE_CODE_COMPRESSION);
4079 if (strcmp (ip->insn_mo->name, "nop") == 0)
4080 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4083 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4084 jr target pc &= 'hffff_ffff_cfff_ffff. */
4087 fix_loongson2f_jump (struct mips_cl_insn * ip)
4089 gas_assert (!HAVE_CODE_COMPRESSION);
4090 if (strcmp (ip->insn_mo->name, "j") == 0
4091 || strcmp (ip->insn_mo->name, "jr") == 0
4092 || strcmp (ip->insn_mo->name, "jalr") == 0)
4100 sreg = EXTRACT_OPERAND (0, RS, *ip);
4101 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4104 ep.X_op = O_constant;
4105 ep.X_add_number = 0xcfff0000;
4106 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4107 ep.X_add_number = 0xffff;
4108 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4109 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4114 fix_loongson2f (struct mips_cl_insn * ip)
4116 if (mips_fix_loongson2f_nop)
4117 fix_loongson2f_nop (ip);
4119 if (mips_fix_loongson2f_jump)
4120 fix_loongson2f_jump (ip);
4123 /* IP is a branch that has a delay slot, and we need to fill it
4124 automatically. Return true if we can do that by swapping IP
4125 with the previous instruction.
4126 ADDRESS_EXPR is an operand of the instruction to be used with
4130 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4131 bfd_reloc_code_real_type *reloc_type)
4133 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4134 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4136 /* -O2 and above is required for this optimization. */
4137 if (mips_optimize < 2)
4140 /* If we have seen .set volatile or .set nomove, don't optimize. */
4141 if (mips_opts.nomove)
4144 /* We can't swap if the previous instruction's position is fixed. */
4145 if (history[0].fixed_p)
4148 /* If the previous previous insn was in a .set noreorder, we can't
4149 swap. Actually, the MIPS assembler will swap in this situation.
4150 However, gcc configured -with-gnu-as will generate code like
4158 in which we can not swap the bne and INSN. If gcc is not configured
4159 -with-gnu-as, it does not output the .set pseudo-ops. */
4160 if (history[1].noreorder_p)
4163 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4164 This means that the previous instruction was a 4-byte one anyhow. */
4165 if (mips_opts.mips16 && history[0].fixp[0])
4168 /* If the branch is itself the target of a branch, we can not swap.
4169 We cheat on this; all we check for is whether there is a label on
4170 this instruction. If there are any branches to anything other than
4171 a label, users must use .set noreorder. */
4172 if (seg_info (now_seg)->label_list)
4175 /* If the previous instruction is in a variant frag other than this
4176 branch's one, we cannot do the swap. This does not apply to
4177 MIPS16 code, which uses variant frags for different purposes. */
4178 if (!mips_opts.mips16
4180 && history[0].frag->fr_type == rs_machine_dependent)
4183 /* We do not swap with instructions that cannot architecturally
4184 be placed in a branch delay slot, such as SYNC or ERET. We
4185 also refrain from swapping with a trap instruction, since it
4186 complicates trap handlers to have the trap instruction be in
4188 prev_pinfo = history[0].insn_mo->pinfo;
4189 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4192 /* Check for conflicts between the branch and the instructions
4193 before the candidate delay slot. */
4194 if (nops_for_insn (0, history + 1, ip) > 0)
4197 /* Check for conflicts between the swapped sequence and the
4198 target of the branch. */
4199 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4202 /* If the branch reads a register that the previous
4203 instruction sets, we can not swap. */
4204 gpr_read = gpr_read_mask (ip);
4205 prev_gpr_write = gpr_write_mask (&history[0]);
4206 if (gpr_read & prev_gpr_write)
4209 /* If the branch writes a register that the previous
4210 instruction sets, we can not swap. */
4211 gpr_write = gpr_write_mask (ip);
4212 if (gpr_write & prev_gpr_write)
4215 /* If the branch writes a register that the previous
4216 instruction reads, we can not swap. */
4217 prev_gpr_read = gpr_read_mask (&history[0]);
4218 if (gpr_write & prev_gpr_read)
4221 /* If one instruction sets a condition code and the
4222 other one uses a condition code, we can not swap. */
4223 pinfo = ip->insn_mo->pinfo;
4224 if ((pinfo & INSN_READ_COND_CODE)
4225 && (prev_pinfo & INSN_WRITE_COND_CODE))
4227 if ((pinfo & INSN_WRITE_COND_CODE)
4228 && (prev_pinfo & INSN_READ_COND_CODE))
4231 /* If the previous instruction uses the PC, we can not swap. */
4232 prev_pinfo2 = history[0].insn_mo->pinfo2;
4233 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4235 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4238 /* If the previous instruction has an incorrect size for a fixed
4239 branch delay slot in microMIPS mode, we cannot swap. */
4240 pinfo2 = ip->insn_mo->pinfo2;
4241 if (mips_opts.micromips
4242 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4243 && insn_length (history) != 2)
4245 if (mips_opts.micromips
4246 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4247 && insn_length (history) != 4)
4250 /* On R5900 short loops need to be fixed by inserting a nop in
4251 the branch delay slots.
4252 A short loop can be terminated too early. */
4253 if (mips_opts.arch == CPU_R5900
4254 /* Check if instruction has a parameter, ignore "j $31". */
4255 && (address_expr != NULL)
4256 /* Parameter must be 16 bit. */
4257 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4258 /* Branch to same segment. */
4259 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4260 /* Branch to same code fragment. */
4261 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4262 /* Can only calculate branch offset if value is known. */
4263 && symbol_constant_p(address_expr->X_add_symbol)
4264 /* Check if branch is really conditional. */
4265 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4266 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4267 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4270 /* Check if loop is shorter than 6 instructions including
4271 branch and delay slot. */
4272 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4279 /* When the loop includes branches or jumps,
4280 it is not a short loop. */
4281 for (i = 0; i < (distance / 4); i++)
4283 if ((history[i].cleared_p)
4284 || delayed_branch_p(&history[i]))
4292 /* Insert nop after branch to fix short loop. */
4301 /* Decide how we should add IP to the instruction stream.
4302 ADDRESS_EXPR is an operand of the instruction to be used with
4305 static enum append_method
4306 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4307 bfd_reloc_code_real_type *reloc_type)
4309 unsigned long pinfo;
4311 /* The relaxed version of a macro sequence must be inherently
4313 if (mips_relax.sequence == 2)
4316 /* We must not dabble with instructions in a ".set norerorder" block. */
4317 if (mips_opts.noreorder)
4320 /* Otherwise, it's our responsibility to fill branch delay slots. */
4321 if (delayed_branch_p (ip))
4323 if (!branch_likely_p (ip)
4324 && can_swap_branch_p (ip, address_expr, reloc_type))
4327 pinfo = ip->insn_mo->pinfo;
4328 if (mips_opts.mips16
4329 && ISA_SUPPORTS_MIPS16E
4330 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4331 return APPEND_ADD_COMPACT;
4333 return APPEND_ADD_WITH_NOP;
4339 /* IP is a MIPS16 instruction whose opcode we have just changed.
4340 Point IP->insn_mo to the new opcode's definition. */
4343 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4345 const struct mips_opcode *mo, *end;
4347 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4348 for (mo = ip->insn_mo; mo < end; mo++)
4349 if ((ip->insn_opcode & mo->mask) == mo->match)
4357 /* For microMIPS macros, we need to generate a local number label
4358 as the target of branches. */
4359 #define MICROMIPS_LABEL_CHAR '\037'
4360 static unsigned long micromips_target_label;
4361 static char micromips_target_name[32];
4364 micromips_label_name (void)
4366 char *p = micromips_target_name;
4367 char symbol_name_temporary[24];
4375 l = micromips_target_label;
4376 #ifdef LOCAL_LABEL_PREFIX
4377 *p++ = LOCAL_LABEL_PREFIX;
4380 *p++ = MICROMIPS_LABEL_CHAR;
4383 symbol_name_temporary[i++] = l % 10 + '0';
4388 *p++ = symbol_name_temporary[--i];
4391 return micromips_target_name;
4395 micromips_label_expr (expressionS *label_expr)
4397 label_expr->X_op = O_symbol;
4398 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4399 label_expr->X_add_number = 0;
4403 micromips_label_inc (void)
4405 micromips_target_label++;
4406 *micromips_target_name = '\0';
4410 micromips_add_label (void)
4414 s = colon (micromips_label_name ());
4415 micromips_label_inc ();
4416 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4419 /* If assembling microMIPS code, then return the microMIPS reloc
4420 corresponding to the requested one if any. Otherwise return
4421 the reloc unchanged. */
4423 static bfd_reloc_code_real_type
4424 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4426 static const bfd_reloc_code_real_type relocs[][2] =
4428 /* Keep sorted incrementally by the left-hand key. */
4429 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4430 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4431 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4432 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4433 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4434 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4435 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4436 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4437 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4438 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4439 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4440 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4441 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4442 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4443 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4444 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4445 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4446 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4447 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4448 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4449 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4450 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4451 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4452 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4453 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4454 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4455 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4457 bfd_reloc_code_real_type r;
4460 if (!mips_opts.micromips)
4462 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4468 return relocs[i][1];
4473 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4474 Return true on success, storing the resolved value in RESULT. */
4477 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4482 case BFD_RELOC_MIPS_HIGHEST:
4483 case BFD_RELOC_MICROMIPS_HIGHEST:
4484 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4487 case BFD_RELOC_MIPS_HIGHER:
4488 case BFD_RELOC_MICROMIPS_HIGHER:
4489 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4492 case BFD_RELOC_HI16_S:
4493 case BFD_RELOC_MICROMIPS_HI16_S:
4494 case BFD_RELOC_MIPS16_HI16_S:
4495 *result = ((operand + 0x8000) >> 16) & 0xffff;
4498 case BFD_RELOC_HI16:
4499 case BFD_RELOC_MICROMIPS_HI16:
4500 case BFD_RELOC_MIPS16_HI16:
4501 *result = (operand >> 16) & 0xffff;
4504 case BFD_RELOC_LO16:
4505 case BFD_RELOC_MICROMIPS_LO16:
4506 case BFD_RELOC_MIPS16_LO16:
4507 *result = operand & 0xffff;
4510 case BFD_RELOC_UNUSED:
4519 /* Output an instruction. IP is the instruction information.
4520 ADDRESS_EXPR is an operand of the instruction to be used with
4521 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4522 a macro expansion. */
4525 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4526 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4528 unsigned long prev_pinfo2, pinfo;
4529 bfd_boolean relaxed_branch = FALSE;
4530 enum append_method method;
4531 bfd_boolean relax32;
4534 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4535 fix_loongson2f (ip);
4537 file_ase_mips16 |= mips_opts.mips16;
4538 file_ase_micromips |= mips_opts.micromips;
4540 prev_pinfo2 = history[0].insn_mo->pinfo2;
4541 pinfo = ip->insn_mo->pinfo;
4543 if (mips_opts.micromips
4545 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4546 && micromips_insn_length (ip->insn_mo) != 2)
4547 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4548 && micromips_insn_length (ip->insn_mo) != 4)))
4549 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4550 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4552 if (address_expr == NULL)
4554 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4555 && reloc_type[1] == BFD_RELOC_UNUSED
4556 && reloc_type[2] == BFD_RELOC_UNUSED
4557 && address_expr->X_op == O_constant)
4559 switch (*reloc_type)
4561 case BFD_RELOC_MIPS_JMP:
4565 shift = mips_opts.micromips ? 1 : 2;
4566 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4567 as_bad (_("jump to misaligned address (0x%lx)"),
4568 (unsigned long) address_expr->X_add_number);
4569 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4575 case BFD_RELOC_MIPS16_JMP:
4576 if ((address_expr->X_add_number & 3) != 0)
4577 as_bad (_("jump to misaligned address (0x%lx)"),
4578 (unsigned long) address_expr->X_add_number);
4580 (((address_expr->X_add_number & 0x7c0000) << 3)
4581 | ((address_expr->X_add_number & 0xf800000) >> 7)
4582 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4586 case BFD_RELOC_16_PCREL_S2:
4590 shift = mips_opts.micromips ? 1 : 2;
4591 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4592 as_bad (_("branch to misaligned address (0x%lx)"),
4593 (unsigned long) address_expr->X_add_number);
4594 if (!mips_relax_branch)
4596 if ((address_expr->X_add_number + (1 << (shift + 15)))
4597 & ~((1 << (shift + 16)) - 1))
4598 as_bad (_("branch address range overflow (0x%lx)"),
4599 (unsigned long) address_expr->X_add_number);
4600 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4610 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4613 ip->insn_opcode |= value & 0xffff;
4621 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4623 /* There are a lot of optimizations we could do that we don't.
4624 In particular, we do not, in general, reorder instructions.
4625 If you use gcc with optimization, it will reorder
4626 instructions and generally do much more optimization then we
4627 do here; repeating all that work in the assembler would only
4628 benefit hand written assembly code, and does not seem worth
4630 int nops = (mips_optimize == 0
4631 ? nops_for_insn (0, history, NULL)
4632 : nops_for_insn_or_target (0, history, ip));
4636 unsigned long old_frag_offset;
4639 old_frag = frag_now;
4640 old_frag_offset = frag_now_fix ();
4642 for (i = 0; i < nops; i++)
4643 add_fixed_insn (NOP_INSN);
4644 insert_into_history (0, nops, NOP_INSN);
4648 listing_prev_line ();
4649 /* We may be at the start of a variant frag. In case we
4650 are, make sure there is enough space for the frag
4651 after the frags created by listing_prev_line. The
4652 argument to frag_grow here must be at least as large
4653 as the argument to all other calls to frag_grow in
4654 this file. We don't have to worry about being in the
4655 middle of a variant frag, because the variants insert
4656 all needed nop instructions themselves. */
4660 mips_move_text_labels ();
4662 #ifndef NO_ECOFF_DEBUGGING
4663 if (ECOFF_DEBUGGING)
4664 ecoff_fix_loc (old_frag, old_frag_offset);
4668 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4672 /* Work out how many nops in prev_nop_frag are needed by IP,
4673 ignoring hazards generated by the first prev_nop_frag_since
4675 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4676 gas_assert (nops <= prev_nop_frag_holds);
4678 /* Enforce NOPS as a minimum. */
4679 if (nops > prev_nop_frag_required)
4680 prev_nop_frag_required = nops;
4682 if (prev_nop_frag_holds == prev_nop_frag_required)
4684 /* Settle for the current number of nops. Update the history
4685 accordingly (for the benefit of any future .set reorder code). */
4686 prev_nop_frag = NULL;
4687 insert_into_history (prev_nop_frag_since,
4688 prev_nop_frag_holds, NOP_INSN);
4692 /* Allow this instruction to replace one of the nops that was
4693 tentatively added to prev_nop_frag. */
4694 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4695 prev_nop_frag_holds--;
4696 prev_nop_frag_since++;
4700 method = get_append_method (ip, address_expr, reloc_type);
4701 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4703 dwarf2_emit_insn (0);
4704 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4705 so "move" the instruction address accordingly.
4707 Also, it doesn't seem appropriate for the assembler to reorder .loc
4708 entries. If this instruction is a branch that we are going to swap
4709 with the previous instruction, the two instructions should be
4710 treated as a unit, and the debug information for both instructions
4711 should refer to the start of the branch sequence. Using the
4712 current position is certainly wrong when swapping a 32-bit branch
4713 and a 16-bit delay slot, since the current position would then be
4714 in the middle of a branch. */
4715 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4717 relax32 = (mips_relax_branch
4718 /* Don't try branch relaxation within .set nomacro, or within
4719 .set noat if we use $at for PIC computations. If it turns
4720 out that the branch was out-of-range, we'll get an error. */
4721 && !mips_opts.warn_about_macros
4722 && (mips_opts.at || mips_pic == NO_PIC)
4723 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4724 as they have no complementing branches. */
4725 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4727 if (!HAVE_CODE_COMPRESSION
4730 && *reloc_type == BFD_RELOC_16_PCREL_S2
4731 && delayed_branch_p (ip))
4733 relaxed_branch = TRUE;
4734 add_relaxed_insn (ip, (relaxed_branch_length
4736 uncond_branch_p (ip) ? -1
4737 : branch_likely_p (ip) ? 1
4741 uncond_branch_p (ip),
4742 branch_likely_p (ip),
4743 pinfo & INSN_WRITE_GPR_31,
4745 address_expr->X_add_symbol,
4746 address_expr->X_add_number);
4747 *reloc_type = BFD_RELOC_UNUSED;
4749 else if (mips_opts.micromips
4751 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4752 || *reloc_type > BFD_RELOC_UNUSED)
4753 && (delayed_branch_p (ip) || compact_branch_p (ip))
4754 /* Don't try branch relaxation when users specify
4755 16-bit/32-bit instructions. */
4756 && !forced_insn_length)
4758 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4759 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4760 int uncond = uncond_branch_p (ip) ? -1 : 0;
4761 int compact = compact_branch_p (ip);
4762 int al = pinfo & INSN_WRITE_GPR_31;
4765 gas_assert (address_expr != NULL);
4766 gas_assert (!mips_relax.sequence);
4768 relaxed_branch = TRUE;
4769 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4770 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4771 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4773 address_expr->X_add_symbol,
4774 address_expr->X_add_number);
4775 *reloc_type = BFD_RELOC_UNUSED;
4777 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4779 /* We need to set up a variant frag. */
4780 gas_assert (address_expr != NULL);
4781 add_relaxed_insn (ip, 4, 0,
4783 (*reloc_type - BFD_RELOC_UNUSED,
4784 forced_insn_length == 2, forced_insn_length == 4,
4785 delayed_branch_p (&history[0]),
4786 history[0].mips16_absolute_jump_p),
4787 make_expr_symbol (address_expr), 0);
4789 else if (mips_opts.mips16 && insn_length (ip) == 2)
4791 if (!delayed_branch_p (ip))
4792 /* Make sure there is enough room to swap this instruction with
4793 a following jump instruction. */
4795 add_fixed_insn (ip);
4799 if (mips_opts.mips16
4800 && mips_opts.noreorder
4801 && delayed_branch_p (&history[0]))
4802 as_warn (_("extended instruction in delay slot"));
4804 if (mips_relax.sequence)
4806 /* If we've reached the end of this frag, turn it into a variant
4807 frag and record the information for the instructions we've
4809 if (frag_room () < 4)
4810 relax_close_frag ();
4811 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4814 if (mips_relax.sequence != 2)
4816 if (mips_macro_warning.first_insn_sizes[0] == 0)
4817 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4818 mips_macro_warning.sizes[0] += insn_length (ip);
4819 mips_macro_warning.insns[0]++;
4821 if (mips_relax.sequence != 1)
4823 if (mips_macro_warning.first_insn_sizes[1] == 0)
4824 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4825 mips_macro_warning.sizes[1] += insn_length (ip);
4826 mips_macro_warning.insns[1]++;
4829 if (mips_opts.mips16)
4832 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4834 add_fixed_insn (ip);
4837 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4839 bfd_reloc_code_real_type final_type[3];
4840 reloc_howto_type *howto0;
4841 reloc_howto_type *howto;
4844 /* Perform any necessary conversion to microMIPS relocations
4845 and find out how many relocations there actually are. */
4846 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4847 final_type[i] = micromips_map_reloc (reloc_type[i]);
4849 /* In a compound relocation, it is the final (outermost)
4850 operator that determines the relocated field. */
4851 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4856 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4857 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4858 bfd_get_reloc_size (howto),
4860 howto0 && howto0->pc_relative,
4863 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4864 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4865 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4867 /* These relocations can have an addend that won't fit in
4868 4 octets for 64bit assembly. */
4870 && ! howto->partial_inplace
4871 && (reloc_type[0] == BFD_RELOC_16
4872 || reloc_type[0] == BFD_RELOC_32
4873 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4874 || reloc_type[0] == BFD_RELOC_GPREL16
4875 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4876 || reloc_type[0] == BFD_RELOC_GPREL32
4877 || reloc_type[0] == BFD_RELOC_64
4878 || reloc_type[0] == BFD_RELOC_CTOR
4879 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4880 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4881 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4882 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4883 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4884 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4885 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4886 || hi16_reloc_p (reloc_type[0])
4887 || lo16_reloc_p (reloc_type[0])))
4888 ip->fixp[0]->fx_no_overflow = 1;
4890 /* These relocations can have an addend that won't fit in 2 octets. */
4891 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4892 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4893 ip->fixp[0]->fx_no_overflow = 1;
4895 if (mips_relax.sequence)
4897 if (mips_relax.first_fixup == 0)
4898 mips_relax.first_fixup = ip->fixp[0];
4900 else if (reloc_needs_lo_p (*reloc_type))
4902 struct mips_hi_fixup *hi_fixup;
4904 /* Reuse the last entry if it already has a matching %lo. */
4905 hi_fixup = mips_hi_fixup_list;
4907 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4909 hi_fixup = ((struct mips_hi_fixup *)
4910 xmalloc (sizeof (struct mips_hi_fixup)));
4911 hi_fixup->next = mips_hi_fixup_list;
4912 mips_hi_fixup_list = hi_fixup;
4914 hi_fixup->fixp = ip->fixp[0];
4915 hi_fixup->seg = now_seg;
4918 /* Add fixups for the second and third relocations, if given.
4919 Note that the ABI allows the second relocation to be
4920 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4921 moment we only use RSS_UNDEF, but we could add support
4922 for the others if it ever becomes necessary. */
4923 for (i = 1; i < 3; i++)
4924 if (reloc_type[i] != BFD_RELOC_UNUSED)
4926 ip->fixp[i] = fix_new (ip->frag, ip->where,
4927 ip->fixp[0]->fx_size, NULL, 0,
4928 FALSE, final_type[i]);
4930 /* Use fx_tcbit to mark compound relocs. */
4931 ip->fixp[0]->fx_tcbit = 1;
4932 ip->fixp[i]->fx_tcbit = 1;
4937 /* Update the register mask information. */
4938 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4939 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4944 insert_into_history (0, 1, ip);
4947 case APPEND_ADD_WITH_NOP:
4949 struct mips_cl_insn *nop;
4951 insert_into_history (0, 1, ip);
4952 nop = get_delay_slot_nop (ip);
4953 add_fixed_insn (nop);
4954 insert_into_history (0, 1, nop);
4955 if (mips_relax.sequence)
4956 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4960 case APPEND_ADD_COMPACT:
4961 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4962 gas_assert (mips_opts.mips16);
4963 ip->insn_opcode |= 0x0080;
4964 find_altered_mips16_opcode (ip);
4966 insert_into_history (0, 1, ip);
4971 struct mips_cl_insn delay = history[0];
4972 if (mips_opts.mips16)
4974 know (delay.frag == ip->frag);
4975 move_insn (ip, delay.frag, delay.where);
4976 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4978 else if (relaxed_branch || delay.frag != ip->frag)
4980 /* Add the delay slot instruction to the end of the
4981 current frag and shrink the fixed part of the
4982 original frag. If the branch occupies the tail of
4983 the latter, move it backwards to cover the gap. */
4984 delay.frag->fr_fix -= branch_disp;
4985 if (delay.frag == ip->frag)
4986 move_insn (ip, ip->frag, ip->where - branch_disp);
4987 add_fixed_insn (&delay);
4991 move_insn (&delay, ip->frag,
4992 ip->where - branch_disp + insn_length (ip));
4993 move_insn (ip, history[0].frag, history[0].where);
4997 insert_into_history (0, 1, &delay);
5002 /* If we have just completed an unconditional branch, clear the history. */
5003 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
5004 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
5008 mips_no_prev_insn ();
5010 for (i = 0; i < ARRAY_SIZE (history); i++)
5011 history[i].cleared_p = 1;
5014 /* We need to emit a label at the end of branch-likely macros. */
5015 if (emit_branch_likely_macro)
5017 emit_branch_likely_macro = FALSE;
5018 micromips_add_label ();
5021 /* We just output an insn, so the next one doesn't have a label. */
5022 mips_clear_insn_labels ();
5025 /* Forget that there was any previous instruction or label.
5026 When BRANCH is true, the branch history is also flushed. */
5029 mips_no_prev_insn (void)
5031 prev_nop_frag = NULL;
5032 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
5033 mips_clear_insn_labels ();
5036 /* This function must be called before we emit something other than
5037 instructions. It is like mips_no_prev_insn except that it inserts
5038 any NOPS that might be needed by previous instructions. */
5041 mips_emit_delays (void)
5043 if (! mips_opts.noreorder)
5045 int nops = nops_for_insn (0, history, NULL);
5049 add_fixed_insn (NOP_INSN);
5050 mips_move_text_labels ();
5053 mips_no_prev_insn ();
5056 /* Start a (possibly nested) noreorder block. */
5059 start_noreorder (void)
5061 if (mips_opts.noreorder == 0)
5066 /* None of the instructions before the .set noreorder can be moved. */
5067 for (i = 0; i < ARRAY_SIZE (history); i++)
5068 history[i].fixed_p = 1;
5070 /* Insert any nops that might be needed between the .set noreorder
5071 block and the previous instructions. We will later remove any
5072 nops that turn out not to be needed. */
5073 nops = nops_for_insn (0, history, NULL);
5076 if (mips_optimize != 0)
5078 /* Record the frag which holds the nop instructions, so
5079 that we can remove them if we don't need them. */
5080 frag_grow (nops * NOP_INSN_SIZE);
5081 prev_nop_frag = frag_now;
5082 prev_nop_frag_holds = nops;
5083 prev_nop_frag_required = 0;
5084 prev_nop_frag_since = 0;
5087 for (; nops > 0; --nops)
5088 add_fixed_insn (NOP_INSN);
5090 /* Move on to a new frag, so that it is safe to simply
5091 decrease the size of prev_nop_frag. */
5092 frag_wane (frag_now);
5094 mips_move_text_labels ();
5096 mips_mark_labels ();
5097 mips_clear_insn_labels ();
5099 mips_opts.noreorder++;
5100 mips_any_noreorder = 1;
5103 /* End a nested noreorder block. */
5106 end_noreorder (void)
5108 mips_opts.noreorder--;
5109 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5111 /* Commit to inserting prev_nop_frag_required nops and go back to
5112 handling nop insertion the .set reorder way. */
5113 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5115 insert_into_history (prev_nop_frag_since,
5116 prev_nop_frag_required, NOP_INSN);
5117 prev_nop_frag = NULL;
5121 /* Set up global variables for the start of a new macro. */
5126 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5127 memset (&mips_macro_warning.first_insn_sizes, 0,
5128 sizeof (mips_macro_warning.first_insn_sizes));
5129 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5130 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5131 && delayed_branch_p (&history[0]));
5132 switch (history[0].insn_mo->pinfo2
5133 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5135 case INSN2_BRANCH_DELAY_32BIT:
5136 mips_macro_warning.delay_slot_length = 4;
5138 case INSN2_BRANCH_DELAY_16BIT:
5139 mips_macro_warning.delay_slot_length = 2;
5142 mips_macro_warning.delay_slot_length = 0;
5145 mips_macro_warning.first_frag = NULL;
5148 /* Given that a macro is longer than one instruction or of the wrong size,
5149 return the appropriate warning for it. Return null if no warning is
5150 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5151 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5152 and RELAX_NOMACRO. */
5155 macro_warning (relax_substateT subtype)
5157 if (subtype & RELAX_DELAY_SLOT)
5158 return _("Macro instruction expanded into multiple instructions"
5159 " in a branch delay slot");
5160 else if (subtype & RELAX_NOMACRO)
5161 return _("Macro instruction expanded into multiple instructions");
5162 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5163 | RELAX_DELAY_SLOT_SIZE_SECOND))
5164 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5165 ? _("Macro instruction expanded into a wrong size instruction"
5166 " in a 16-bit branch delay slot")
5167 : _("Macro instruction expanded into a wrong size instruction"
5168 " in a 32-bit branch delay slot"));
5173 /* Finish up a macro. Emit warnings as appropriate. */
5178 /* Relaxation warning flags. */
5179 relax_substateT subtype = 0;
5181 /* Check delay slot size requirements. */
5182 if (mips_macro_warning.delay_slot_length == 2)
5183 subtype |= RELAX_DELAY_SLOT_16BIT;
5184 if (mips_macro_warning.delay_slot_length != 0)
5186 if (mips_macro_warning.delay_slot_length
5187 != mips_macro_warning.first_insn_sizes[0])
5188 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5189 if (mips_macro_warning.delay_slot_length
5190 != mips_macro_warning.first_insn_sizes[1])
5191 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5194 /* Check instruction count requirements. */
5195 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5197 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5198 subtype |= RELAX_SECOND_LONGER;
5199 if (mips_opts.warn_about_macros)
5200 subtype |= RELAX_NOMACRO;
5201 if (mips_macro_warning.delay_slot_p)
5202 subtype |= RELAX_DELAY_SLOT;
5205 /* If both alternatives fail to fill a delay slot correctly,
5206 emit the warning now. */
5207 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5208 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5213 s = subtype & (RELAX_DELAY_SLOT_16BIT
5214 | RELAX_DELAY_SLOT_SIZE_FIRST
5215 | RELAX_DELAY_SLOT_SIZE_SECOND);
5216 msg = macro_warning (s);
5218 as_warn ("%s", msg);
5222 /* If both implementations are longer than 1 instruction, then emit the
5224 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5229 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5230 msg = macro_warning (s);
5232 as_warn ("%s", msg);
5236 /* If any flags still set, then one implementation might need a warning
5237 and the other either will need one of a different kind or none at all.
5238 Pass any remaining flags over to relaxation. */
5239 if (mips_macro_warning.first_frag != NULL)
5240 mips_macro_warning.first_frag->fr_subtype |= subtype;
5243 /* Instruction operand formats used in macros that vary between
5244 standard MIPS and microMIPS code. */
5246 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
5247 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5248 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5249 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5250 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5251 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
5252 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5253 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5255 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5256 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5257 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5258 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5259 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5260 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5261 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5262 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5264 /* Read a macro's relocation codes from *ARGS and store them in *R.
5265 The first argument in *ARGS will be either the code for a single
5266 relocation or -1 followed by the three codes that make up a
5267 composite relocation. */
5270 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5274 next = va_arg (*args, int);
5276 r[0] = (bfd_reloc_code_real_type) next;
5279 for (i = 0; i < 3; i++)
5280 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5281 /* This function is only used for 16-bit relocation fields.
5282 To make the macro code simpler, treat an unrelocated value
5283 in the same way as BFD_RELOC_LO16. */
5284 if (r[0] == BFD_RELOC_UNUSED)
5285 r[0] = BFD_RELOC_LO16;
5289 /* Build an instruction created by a macro expansion. This is passed
5290 a pointer to the count of instructions created so far, an
5291 expression, the name of the instruction to build, an operand format
5292 string, and corresponding arguments. */
5295 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5297 const struct mips_opcode *mo = NULL;
5298 bfd_reloc_code_real_type r[3];
5299 const struct mips_opcode *amo;
5300 struct hash_control *hash;
5301 struct mips_cl_insn insn;
5304 va_start (args, fmt);
5306 if (mips_opts.mips16)
5308 mips16_macro_build (ep, name, fmt, &args);
5313 r[0] = BFD_RELOC_UNUSED;
5314 r[1] = BFD_RELOC_UNUSED;
5315 r[2] = BFD_RELOC_UNUSED;
5316 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5317 amo = (struct mips_opcode *) hash_find (hash, name);
5319 gas_assert (strcmp (name, amo->name) == 0);
5323 /* Search until we get a match for NAME. It is assumed here that
5324 macros will never generate MDMX, MIPS-3D, or MT instructions.
5325 We try to match an instruction that fulfils the branch delay
5326 slot instruction length requirement (if any) of the previous
5327 instruction. While doing this we record the first instruction
5328 seen that matches all the other conditions and use it anyway
5329 if the requirement cannot be met; we will issue an appropriate
5330 warning later on. */
5331 if (strcmp (fmt, amo->args) == 0
5332 && amo->pinfo != INSN_MACRO
5333 && is_opcode_valid (amo)
5334 && is_size_valid (amo))
5336 if (is_delay_slot_valid (amo))
5346 gas_assert (amo->name);
5348 while (strcmp (name, amo->name) == 0);
5351 create_insn (&insn, mo);
5369 INSERT_OPERAND (mips_opts.micromips,
5370 EXTLSB, insn, va_arg (args, int));
5375 /* Note that in the macro case, these arguments are already
5376 in MSB form. (When handling the instruction in the
5377 non-macro case, these arguments are sizes from which
5378 MSB values must be calculated.) */
5379 INSERT_OPERAND (mips_opts.micromips,
5380 INSMSB, insn, va_arg (args, int));
5384 gas_assert (!mips_opts.micromips);
5385 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5391 /* Note that in the macro case, these arguments are already
5392 in MSBD form. (When handling the instruction in the
5393 non-macro case, these arguments are sizes from which
5394 MSBD values must be calculated.) */
5395 INSERT_OPERAND (mips_opts.micromips,
5396 EXTMSBD, insn, va_arg (args, int));
5400 gas_assert (!mips_opts.micromips);
5401 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5405 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5414 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5418 gas_assert (mips_opts.micromips);
5422 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5426 INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int));
5430 gas_assert (!mips_opts.micromips);
5432 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5436 if (mips_opts.micromips)
5437 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5439 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5443 gas_assert (!mips_opts.micromips);
5445 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5449 gas_assert (!mips_opts.micromips);
5451 int tmp = va_arg (args, int);
5453 INSERT_OPERAND (0, RT, insn, tmp);
5454 INSERT_OPERAND (0, RD, insn, tmp);
5460 gas_assert (!mips_opts.micromips);
5461 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5468 INSERT_OPERAND (mips_opts.micromips,
5469 SHAMT, insn, va_arg (args, int));
5473 gas_assert (!mips_opts.micromips);
5474 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5478 gas_assert (!mips_opts.micromips);
5479 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5483 gas_assert (!mips_opts.micromips);
5484 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5488 gas_assert (!mips_opts.micromips);
5489 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5496 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5501 macro_read_relocs (&args, r);
5502 gas_assert (*r == BFD_RELOC_GPREL16
5503 || *r == BFD_RELOC_MIPS_HIGHER
5504 || *r == BFD_RELOC_HI16_S
5505 || *r == BFD_RELOC_LO16
5506 || *r == BFD_RELOC_MIPS_GOT_OFST);
5510 macro_read_relocs (&args, r);
5514 macro_read_relocs (&args, r);
5515 gas_assert (ep != NULL
5516 && (ep->X_op == O_constant
5517 || (ep->X_op == O_symbol
5518 && (*r == BFD_RELOC_MIPS_HIGHEST
5519 || *r == BFD_RELOC_HI16_S
5520 || *r == BFD_RELOC_HI16
5521 || *r == BFD_RELOC_GPREL16
5522 || *r == BFD_RELOC_MIPS_GOT_HI16
5523 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5527 gas_assert (ep != NULL);
5530 * This allows macro() to pass an immediate expression for
5531 * creating short branches without creating a symbol.
5533 * We don't allow branch relaxation for these branches, as
5534 * they should only appear in ".set nomacro" anyway.
5536 if (ep->X_op == O_constant)
5538 /* For microMIPS we always use relocations for branches.
5539 So we should not resolve immediate values. */
5540 gas_assert (!mips_opts.micromips);
5542 if ((ep->X_add_number & 3) != 0)
5543 as_bad (_("branch to misaligned address (0x%lx)"),
5544 (unsigned long) ep->X_add_number);
5545 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5546 as_bad (_("branch address range overflow (0x%lx)"),
5547 (unsigned long) ep->X_add_number);
5548 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5552 *r = BFD_RELOC_16_PCREL_S2;
5556 gas_assert (ep != NULL);
5557 *r = BFD_RELOC_MIPS_JMP;
5561 gas_assert (!mips_opts.micromips);
5562 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5566 INSERT_OPERAND (mips_opts.micromips,
5567 CACHE, insn, va_arg (args, unsigned long));
5571 gas_assert (mips_opts.micromips);
5572 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5576 gas_assert (mips_opts.micromips);
5577 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5581 INSERT_OPERAND (mips_opts.micromips,
5582 3BITPOS, insn, va_arg (args, unsigned int));
5586 INSERT_OPERAND (mips_opts.micromips,
5587 OFFSET12, insn, va_arg (args, unsigned long));
5591 gas_assert (mips_opts.micromips);
5592 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5595 case 'm': /* Opcode extension character. */
5596 gas_assert (mips_opts.micromips);
5600 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5604 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5608 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5622 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5624 append_insn (&insn, ep, r, TRUE);
5628 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5631 struct mips_opcode *mo;
5632 struct mips_cl_insn insn;
5633 bfd_reloc_code_real_type r[3]
5634 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5636 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5638 gas_assert (strcmp (name, mo->name) == 0);
5640 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5643 gas_assert (mo->name);
5644 gas_assert (strcmp (name, mo->name) == 0);
5647 create_insn (&insn, mo);
5665 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5670 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5674 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5678 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5688 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5695 regno = va_arg (*args, int);
5696 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5697 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5720 gas_assert (ep != NULL);
5722 if (ep->X_op != O_constant)
5723 *r = (int) BFD_RELOC_UNUSED + c;
5724 else if (calculate_reloc (*r, ep->X_add_number, &value))
5726 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5728 *r = BFD_RELOC_UNUSED;
5734 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5741 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5743 append_insn (&insn, ep, r, TRUE);
5747 * Sign-extend 32-bit mode constants that have bit 31 set and all
5748 * higher bits unset.
5751 normalize_constant_expr (expressionS *ex)
5753 if (ex->X_op == O_constant
5754 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5755 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5760 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5761 * all higher bits unset.
5764 normalize_address_expr (expressionS *ex)
5766 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5767 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5768 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5769 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5774 * Generate a "jalr" instruction with a relocation hint to the called
5775 * function. This occurs in NewABI PIC code.
5778 macro_build_jalr (expressionS *ep, int cprestore)
5780 static const bfd_reloc_code_real_type jalr_relocs[2]
5781 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5782 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5786 if (MIPS_JALR_HINT_P (ep))
5791 if (mips_opts.micromips)
5793 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
5794 ? "jalr" : "jalrs");
5795 if (MIPS_JALR_HINT_P (ep)
5797 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5798 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5800 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5803 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5804 if (MIPS_JALR_HINT_P (ep))
5805 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5809 * Generate a "lui" instruction.
5812 macro_build_lui (expressionS *ep, int regnum)
5814 gas_assert (! mips_opts.mips16);
5816 if (ep->X_op != O_constant)
5818 gas_assert (ep->X_op == O_symbol);
5819 /* _gp_disp is a special case, used from s_cpload.
5820 __gnu_local_gp is used if mips_no_shared. */
5821 gas_assert (mips_pic == NO_PIC
5823 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5824 || (! mips_in_shared
5825 && strcmp (S_GET_NAME (ep->X_add_symbol),
5826 "__gnu_local_gp") == 0));
5829 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5832 /* Generate a sequence of instructions to do a load or store from a constant
5833 offset off of a base register (breg) into/from a target register (treg),
5834 using AT if necessary. */
5836 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5837 int treg, int breg, int dbl)
5839 gas_assert (ep->X_op == O_constant);
5841 /* Sign-extending 32-bit constants makes their handling easier. */
5843 normalize_constant_expr (ep);
5845 /* Right now, this routine can only handle signed 32-bit constants. */
5846 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5847 as_warn (_("operand overflow"));
5849 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5851 /* Signed 16-bit offset will fit in the op. Easy! */
5852 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5856 /* 32-bit offset, need multiple instructions and AT, like:
5857 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5858 addu $tempreg,$tempreg,$breg
5859 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5860 to handle the complete offset. */
5861 macro_build_lui (ep, AT);
5862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5863 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5866 as_bad (_("Macro used $at after \".set noat\""));
5871 * Generates code to set the $at register to true (one)
5872 * if reg is less than the immediate expression.
5875 set_at (int reg, int unsignedp)
5877 if (imm_expr.X_op == O_constant
5878 && imm_expr.X_add_number >= -0x8000
5879 && imm_expr.X_add_number < 0x8000)
5880 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5881 AT, reg, BFD_RELOC_LO16);
5884 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5885 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5889 /* Warn if an expression is not a constant. */
5892 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5894 if (ex->X_op == O_big)
5895 as_bad (_("unsupported large constant"));
5896 else if (ex->X_op != O_constant)
5897 as_bad (_("Instruction %s requires absolute expression"),
5900 if (HAVE_32BIT_GPRS)
5901 normalize_constant_expr (ex);
5904 /* Count the leading zeroes by performing a binary chop. This is a
5905 bulky bit of source, but performance is a LOT better for the
5906 majority of values than a simple loop to count the bits:
5907 for (lcnt = 0; (lcnt < 32); lcnt++)
5908 if ((v) & (1 << (31 - lcnt)))
5910 However it is not code size friendly, and the gain will drop a bit
5911 on certain cached systems.
5913 #define COUNT_TOP_ZEROES(v) \
5914 (((v) & ~0xffff) == 0 \
5915 ? ((v) & ~0xff) == 0 \
5916 ? ((v) & ~0xf) == 0 \
5917 ? ((v) & ~0x3) == 0 \
5918 ? ((v) & ~0x1) == 0 \
5923 : ((v) & ~0x7) == 0 \
5926 : ((v) & ~0x3f) == 0 \
5927 ? ((v) & ~0x1f) == 0 \
5930 : ((v) & ~0x7f) == 0 \
5933 : ((v) & ~0xfff) == 0 \
5934 ? ((v) & ~0x3ff) == 0 \
5935 ? ((v) & ~0x1ff) == 0 \
5938 : ((v) & ~0x7ff) == 0 \
5941 : ((v) & ~0x3fff) == 0 \
5942 ? ((v) & ~0x1fff) == 0 \
5945 : ((v) & ~0x7fff) == 0 \
5948 : ((v) & ~0xffffff) == 0 \
5949 ? ((v) & ~0xfffff) == 0 \
5950 ? ((v) & ~0x3ffff) == 0 \
5951 ? ((v) & ~0x1ffff) == 0 \
5954 : ((v) & ~0x7ffff) == 0 \
5957 : ((v) & ~0x3fffff) == 0 \
5958 ? ((v) & ~0x1fffff) == 0 \
5961 : ((v) & ~0x7fffff) == 0 \
5964 : ((v) & ~0xfffffff) == 0 \
5965 ? ((v) & ~0x3ffffff) == 0 \
5966 ? ((v) & ~0x1ffffff) == 0 \
5969 : ((v) & ~0x7ffffff) == 0 \
5972 : ((v) & ~0x3fffffff) == 0 \
5973 ? ((v) & ~0x1fffffff) == 0 \
5976 : ((v) & ~0x7fffffff) == 0 \
5981 * This routine generates the least number of instructions necessary to load
5982 * an absolute expression value into a register.
5985 load_register (int reg, expressionS *ep, int dbl)
5988 expressionS hi32, lo32;
5990 if (ep->X_op != O_big)
5992 gas_assert (ep->X_op == O_constant);
5994 /* Sign-extending 32-bit constants makes their handling easier. */
5996 normalize_constant_expr (ep);
5998 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
6000 /* We can handle 16 bit signed values with an addiu to
6001 $zero. No need to ever use daddiu here, since $zero and
6002 the result are always correct in 32 bit mode. */
6003 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6006 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
6008 /* We can handle 16 bit unsigned values with an ori to
6010 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6013 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
6015 /* 32 bit values require an lui. */
6016 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6017 if ((ep->X_add_number & 0xffff) != 0)
6018 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6023 /* The value is larger than 32 bits. */
6025 if (!dbl || HAVE_32BIT_GPRS)
6029 sprintf_vma (value, ep->X_add_number);
6030 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6031 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6035 if (ep->X_op != O_big)
6038 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6039 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6040 hi32.X_add_number &= 0xffffffff;
6042 lo32.X_add_number &= 0xffffffff;
6046 gas_assert (ep->X_add_number > 2);
6047 if (ep->X_add_number == 3)
6048 generic_bignum[3] = 0;
6049 else if (ep->X_add_number > 4)
6050 as_bad (_("Number larger than 64 bits"));
6051 lo32.X_op = O_constant;
6052 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6053 hi32.X_op = O_constant;
6054 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6057 if (hi32.X_add_number == 0)
6062 unsigned long hi, lo;
6064 if (hi32.X_add_number == (offsetT) 0xffffffff)
6066 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6068 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6071 if (lo32.X_add_number & 0x80000000)
6073 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6074 if (lo32.X_add_number & 0xffff)
6075 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6080 /* Check for 16bit shifted constant. We know that hi32 is
6081 non-zero, so start the mask on the first bit of the hi32
6086 unsigned long himask, lomask;
6090 himask = 0xffff >> (32 - shift);
6091 lomask = (0xffff << shift) & 0xffffffff;
6095 himask = 0xffff << (shift - 32);
6098 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6099 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6103 tmp.X_op = O_constant;
6105 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6106 | (lo32.X_add_number >> shift));
6108 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6109 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6110 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6111 reg, reg, (shift >= 32) ? shift - 32 : shift);
6116 while (shift <= (64 - 16));
6118 /* Find the bit number of the lowest one bit, and store the
6119 shifted value in hi/lo. */
6120 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6121 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6125 while ((lo & 1) == 0)
6130 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6136 while ((hi & 1) == 0)
6145 /* Optimize if the shifted value is a (power of 2) - 1. */
6146 if ((hi == 0 && ((lo + 1) & lo) == 0)
6147 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6149 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6154 /* This instruction will set the register to be all
6156 tmp.X_op = O_constant;
6157 tmp.X_add_number = (offsetT) -1;
6158 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6162 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6163 reg, reg, (bit >= 32) ? bit - 32 : bit);
6165 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6166 reg, reg, (shift >= 32) ? shift - 32 : shift);
6171 /* Sign extend hi32 before calling load_register, because we can
6172 generally get better code when we load a sign extended value. */
6173 if ((hi32.X_add_number & 0x80000000) != 0)
6174 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6175 load_register (reg, &hi32, 0);
6178 if ((lo32.X_add_number & 0xffff0000) == 0)
6182 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6190 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6192 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6193 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6199 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6203 mid16.X_add_number >>= 16;
6204 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6205 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6208 if ((lo32.X_add_number & 0xffff) != 0)
6209 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6213 load_delay_nop (void)
6215 if (!gpr_interlocks)
6216 macro_build (NULL, "nop", "");
6219 /* Load an address into a register. */
6222 load_address (int reg, expressionS *ep, int *used_at)
6224 if (ep->X_op != O_constant
6225 && ep->X_op != O_symbol)
6227 as_bad (_("expression too complex"));
6228 ep->X_op = O_constant;
6231 if (ep->X_op == O_constant)
6233 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6237 if (mips_pic == NO_PIC)
6239 /* If this is a reference to a GP relative symbol, we want
6240 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6242 lui $reg,<sym> (BFD_RELOC_HI16_S)
6243 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6244 If we have an addend, we always use the latter form.
6246 With 64bit address space and a usable $at we want
6247 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6248 lui $at,<sym> (BFD_RELOC_HI16_S)
6249 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6250 daddiu $at,<sym> (BFD_RELOC_LO16)
6254 If $at is already in use, we use a path which is suboptimal
6255 on superscalar processors.
6256 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6257 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6259 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6261 daddiu $reg,<sym> (BFD_RELOC_LO16)
6263 For GP relative symbols in 64bit address space we can use
6264 the same sequence as in 32bit address space. */
6265 if (HAVE_64BIT_SYMBOLS)
6267 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6268 && !nopic_need_relax (ep->X_add_symbol, 1))
6270 relax_start (ep->X_add_symbol);
6271 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6272 mips_gp_register, BFD_RELOC_GPREL16);
6276 if (*used_at == 0 && mips_opts.at)
6278 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6279 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6280 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6281 BFD_RELOC_MIPS_HIGHER);
6282 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6283 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6284 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6289 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6290 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6291 BFD_RELOC_MIPS_HIGHER);
6292 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6293 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6294 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6295 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6298 if (mips_relax.sequence)
6303 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6304 && !nopic_need_relax (ep->X_add_symbol, 1))
6306 relax_start (ep->X_add_symbol);
6307 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6308 mips_gp_register, BFD_RELOC_GPREL16);
6311 macro_build_lui (ep, reg);
6312 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6313 reg, reg, BFD_RELOC_LO16);
6314 if (mips_relax.sequence)
6318 else if (!mips_big_got)
6322 /* If this is a reference to an external symbol, we want
6323 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6325 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6327 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6328 If there is a constant, it must be added in after.
6330 If we have NewABI, we want
6331 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6332 unless we're referencing a global symbol with a non-zero
6333 offset, in which case cst must be added separately. */
6336 if (ep->X_add_number)
6338 ex.X_add_number = ep->X_add_number;
6339 ep->X_add_number = 0;
6340 relax_start (ep->X_add_symbol);
6341 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6342 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6343 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6344 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6345 ex.X_op = O_constant;
6346 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6347 reg, reg, BFD_RELOC_LO16);
6348 ep->X_add_number = ex.X_add_number;
6351 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6352 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6353 if (mips_relax.sequence)
6358 ex.X_add_number = ep->X_add_number;
6359 ep->X_add_number = 0;
6360 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6361 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6363 relax_start (ep->X_add_symbol);
6365 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6369 if (ex.X_add_number != 0)
6371 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6372 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6373 ex.X_op = O_constant;
6374 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6375 reg, reg, BFD_RELOC_LO16);
6379 else if (mips_big_got)
6383 /* This is the large GOT case. If this is a reference to an
6384 external symbol, we want
6385 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6387 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6389 Otherwise, for a reference to a local symbol in old ABI, we want
6390 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6392 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6393 If there is a constant, it must be added in after.
6395 In the NewABI, for local symbols, with or without offsets, we want:
6396 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6397 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6401 ex.X_add_number = ep->X_add_number;
6402 ep->X_add_number = 0;
6403 relax_start (ep->X_add_symbol);
6404 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6405 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6406 reg, reg, mips_gp_register);
6407 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6408 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6409 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6410 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6411 else if (ex.X_add_number)
6413 ex.X_op = O_constant;
6414 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6418 ep->X_add_number = ex.X_add_number;
6420 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6421 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6422 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6423 BFD_RELOC_MIPS_GOT_OFST);
6428 ex.X_add_number = ep->X_add_number;
6429 ep->X_add_number = 0;
6430 relax_start (ep->X_add_symbol);
6431 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6432 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6433 reg, reg, mips_gp_register);
6434 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6435 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6437 if (reg_needs_delay (mips_gp_register))
6439 /* We need a nop before loading from $gp. This special
6440 check is required because the lui which starts the main
6441 instruction stream does not refer to $gp, and so will not
6442 insert the nop which may be required. */
6443 macro_build (NULL, "nop", "");
6445 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6446 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6448 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6452 if (ex.X_add_number != 0)
6454 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6455 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6456 ex.X_op = O_constant;
6457 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6465 if (!mips_opts.at && *used_at == 1)
6466 as_bad (_("Macro used $at after \".set noat\""));
6469 /* Move the contents of register SOURCE into register DEST. */
6472 move_register (int dest, int source)
6474 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6475 instruction specifically requires a 32-bit one. */
6476 if (mips_opts.micromips
6477 && !mips_opts.insn32
6478 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6479 macro_build (NULL, "move", "mp,mj", dest, source);
6481 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6485 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6486 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6487 The two alternatives are:
6489 Global symbol Local sybmol
6490 ------------- ------------
6491 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6493 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6495 load_got_offset emits the first instruction and add_got_offset
6496 emits the second for a 16-bit offset or add_got_offset_hilo emits
6497 a sequence to add a 32-bit offset using a scratch register. */
6500 load_got_offset (int dest, expressionS *local)
6505 global.X_add_number = 0;
6507 relax_start (local->X_add_symbol);
6508 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6509 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6511 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6512 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6517 add_got_offset (int dest, expressionS *local)
6521 global.X_op = O_constant;
6522 global.X_op_symbol = NULL;
6523 global.X_add_symbol = NULL;
6524 global.X_add_number = local->X_add_number;
6526 relax_start (local->X_add_symbol);
6527 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6528 dest, dest, BFD_RELOC_LO16);
6530 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6535 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6538 int hold_mips_optimize;
6540 global.X_op = O_constant;
6541 global.X_op_symbol = NULL;
6542 global.X_add_symbol = NULL;
6543 global.X_add_number = local->X_add_number;
6545 relax_start (local->X_add_symbol);
6546 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6548 /* Set mips_optimize around the lui instruction to avoid
6549 inserting an unnecessary nop after the lw. */
6550 hold_mips_optimize = mips_optimize;
6552 macro_build_lui (&global, tmp);
6553 mips_optimize = hold_mips_optimize;
6554 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6557 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6560 /* Emit a sequence of instructions to emulate a branch likely operation.
6561 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6562 is its complementing branch with the original condition negated.
6563 CALL is set if the original branch specified the link operation.
6564 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6566 Code like this is produced in the noreorder mode:
6571 delay slot (executed only if branch taken)
6579 delay slot (executed only if branch taken)
6582 In the reorder mode the delay slot would be filled with a nop anyway,
6583 so code produced is simply:
6588 This function is used when producing code for the microMIPS ASE that
6589 does not implement branch likely instructions in hardware. */
6592 macro_build_branch_likely (const char *br, const char *brneg,
6593 int call, expressionS *ep, const char *fmt,
6594 unsigned int sreg, unsigned int treg)
6596 int noreorder = mips_opts.noreorder;
6599 gas_assert (mips_opts.micromips);
6603 micromips_label_expr (&expr1);
6604 macro_build (&expr1, brneg, fmt, sreg, treg);
6605 macro_build (NULL, "nop", "");
6606 macro_build (ep, call ? "bal" : "b", "p");
6608 /* Set to true so that append_insn adds a label. */
6609 emit_branch_likely_macro = TRUE;
6613 macro_build (ep, br, fmt, sreg, treg);
6614 macro_build (NULL, "nop", "");
6619 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6620 the condition code tested. EP specifies the branch target. */
6623 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6650 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6653 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6654 the register tested. EP specifies the branch target. */
6657 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6659 const char *brneg = NULL;
6669 br = mips_opts.micromips ? "bgez" : "bgezl";
6673 gas_assert (mips_opts.micromips);
6674 br = mips_opts.insn32 ? "bgezal" : "bgezals";
6682 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6689 br = mips_opts.micromips ? "blez" : "blezl";
6696 br = mips_opts.micromips ? "bltz" : "bltzl";
6700 gas_assert (mips_opts.micromips);
6701 br = mips_opts.insn32 ? "bltzal" : "bltzals";
6708 if (mips_opts.micromips && brneg)
6709 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6711 macro_build (ep, br, "s,p", sreg);
6714 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6715 TREG as the registers tested. EP specifies the branch target. */
6718 macro_build_branch_rsrt (int type, expressionS *ep,
6719 unsigned int sreg, unsigned int treg)
6721 const char *brneg = NULL;
6733 br = mips_opts.micromips ? "beq" : "beql";
6742 br = mips_opts.micromips ? "bne" : "bnel";
6748 if (mips_opts.micromips && brneg)
6749 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6751 macro_build (ep, br, "s,t,p", sreg, treg);
6754 /* Return the high part that should be loaded in order to make the low
6755 part of VALUE accessible using an offset of OFFBITS bits. */
6758 offset_high_part (offsetT value, unsigned int offbits)
6765 bias = 1 << (offbits - 1);
6766 low_mask = bias * 2 - 1;
6767 return (value + bias) & ~low_mask;
6770 /* Return true if the value stored in offset_expr and offset_reloc
6771 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6772 amount that the caller wants to add without inducing overflow
6773 and ALIGN is the known alignment of the value in bytes. */
6776 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
6780 /* Accept any relocation operator if overflow isn't a concern. */
6781 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
6784 /* These relocations are guaranteed not to overflow in correct links. */
6785 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
6786 || gprel16_reloc_p (*offset_reloc))
6789 if (offset_expr.X_op == O_constant
6790 && offset_high_part (offset_expr.X_add_number, offbits) == 0
6791 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
6798 * This routine implements the seemingly endless macro or synthesized
6799 * instructions and addressing modes in the mips assembly language. Many
6800 * of these macros are simple and are similar to each other. These could
6801 * probably be handled by some kind of table or grammar approach instead of
6802 * this verbose method. Others are not simple macros but are more like
6803 * optimizing code generation.
6804 * One interesting optimization is when several store macros appear
6805 * consecutively that would load AT with the upper half of the same address.
6806 * The ensuing load upper instructions are ommited. This implies some kind
6807 * of global optimization. We currently only optimize within a single macro.
6808 * For many of the load and store macros if the address is specified as a
6809 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6810 * first load register 'at' with zero and use it as the base register. The
6811 * mips assembler simply uses register $zero. Just one tiny optimization
6815 macro (struct mips_cl_insn *ip, char *str)
6817 unsigned int treg, sreg, dreg, breg;
6818 unsigned int tempreg;
6821 expressionS label_expr;
6836 bfd_boolean large_offset;
6838 int hold_mips_optimize;
6841 gas_assert (! mips_opts.mips16);
6843 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6844 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6845 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6846 mask = ip->insn_mo->mask;
6848 label_expr.X_op = O_constant;
6849 label_expr.X_op_symbol = NULL;
6850 label_expr.X_add_symbol = NULL;
6851 label_expr.X_add_number = 0;
6853 expr1.X_op = O_constant;
6854 expr1.X_op_symbol = NULL;
6855 expr1.X_add_symbol = NULL;
6856 expr1.X_add_number = 1;
6872 if (mips_opts.micromips)
6873 micromips_label_expr (&label_expr);
6875 label_expr.X_add_number = 8;
6876 macro_build (&label_expr, "bgez", "s,p", sreg);
6878 macro_build (NULL, "nop", "");
6880 move_register (dreg, sreg);
6881 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6882 if (mips_opts.micromips)
6883 micromips_add_label ();
6900 if (!mips_opts.micromips)
6902 if (imm_expr.X_op == O_constant
6903 && imm_expr.X_add_number >= -0x200
6904 && imm_expr.X_add_number < 0x200)
6906 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6915 if (imm_expr.X_op == O_constant
6916 && imm_expr.X_add_number >= -0x8000
6917 && imm_expr.X_add_number < 0x8000)
6919 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6924 load_register (AT, &imm_expr, dbl);
6925 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6944 if (imm_expr.X_op == O_constant
6945 && imm_expr.X_add_number >= 0
6946 && imm_expr.X_add_number < 0x10000)
6948 if (mask != M_NOR_I)
6949 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6952 macro_build (&imm_expr, "ori", "t,r,i",
6953 treg, sreg, BFD_RELOC_LO16);
6954 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6960 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6961 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6965 switch (imm_expr.X_add_number)
6968 macro_build (NULL, "nop", "");
6971 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6975 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6976 (int) imm_expr.X_add_number);
6979 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6980 (unsigned long) imm_expr.X_add_number);
6989 gas_assert (mips_opts.micromips);
6990 macro_build_branch_ccl (mask, &offset_expr,
6991 EXTRACT_OPERAND (1, BCC, *ip));
6998 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7004 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
7009 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
7016 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
7018 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
7022 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7023 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7024 &offset_expr, AT, ZERO);
7034 macro_build_branch_rs (mask, &offset_expr, sreg);
7040 /* Check for > max integer. */
7041 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7044 /* Result is always false. */
7046 macro_build (NULL, "nop", "");
7048 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
7051 if (imm_expr.X_op != O_constant)
7052 as_bad (_("Unsupported large constant"));
7053 ++imm_expr.X_add_number;
7057 if (mask == M_BGEL_I)
7059 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7061 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
7062 &offset_expr, sreg);
7065 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7067 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
7068 &offset_expr, sreg);
7071 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
7074 /* result is always true */
7075 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
7076 macro_build (&offset_expr, "b", "p");
7081 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7082 &offset_expr, AT, ZERO);
7091 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7092 &offset_expr, ZERO, treg);
7096 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7097 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7098 &offset_expr, AT, ZERO);
7107 && imm_expr.X_op == O_constant
7108 && imm_expr.X_add_number == -1))
7110 if (imm_expr.X_op != O_constant)
7111 as_bad (_("Unsupported large constant"));
7112 ++imm_expr.X_add_number;
7116 if (mask == M_BGEUL_I)
7118 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7120 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7121 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7122 &offset_expr, sreg, ZERO);
7127 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7128 &offset_expr, AT, ZERO);
7136 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7138 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7142 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7143 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7144 &offset_expr, AT, ZERO);
7152 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7153 &offset_expr, sreg, ZERO);
7159 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7160 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7161 &offset_expr, AT, ZERO);
7169 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7171 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7175 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7176 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7177 &offset_expr, AT, ZERO);
7184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7186 if (imm_expr.X_op != O_constant)
7187 as_bad (_("Unsupported large constant"));
7188 ++imm_expr.X_add_number;
7192 if (mask == M_BLTL_I)
7194 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7195 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7196 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7197 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7202 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7203 &offset_expr, AT, ZERO);
7211 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7212 &offset_expr, sreg, ZERO);
7218 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7219 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7220 &offset_expr, AT, ZERO);
7229 && imm_expr.X_op == O_constant
7230 && imm_expr.X_add_number == -1))
7232 if (imm_expr.X_op != O_constant)
7233 as_bad (_("Unsupported large constant"));
7234 ++imm_expr.X_add_number;
7238 if (mask == M_BLTUL_I)
7240 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7242 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7243 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7244 &offset_expr, sreg, ZERO);
7249 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7250 &offset_expr, AT, ZERO);
7258 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7260 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7264 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7265 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7266 &offset_expr, AT, ZERO);
7276 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7277 &offset_expr, ZERO, treg);
7281 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7282 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7283 &offset_expr, AT, ZERO);
7289 /* Use unsigned arithmetic. */
7293 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7295 as_bad (_("Unsupported large constant"));
7300 pos = imm_expr.X_add_number;
7301 size = imm2_expr.X_add_number;
7306 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7309 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7311 as_bad (_("Improper extract size (%lu, position %lu)"),
7312 (unsigned long) size, (unsigned long) pos);
7316 if (size <= 32 && pos < 32)
7321 else if (size <= 32)
7331 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7338 /* Use unsigned arithmetic. */
7342 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7344 as_bad (_("Unsupported large constant"));
7349 pos = imm_expr.X_add_number;
7350 size = imm2_expr.X_add_number;
7355 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7358 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7360 as_bad (_("Improper insert size (%lu, position %lu)"),
7361 (unsigned long) size, (unsigned long) pos);
7365 if (pos < 32 && (pos + size - 1) < 32)
7380 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7381 (int) (pos + size - 1));
7397 as_warn (_("Divide by zero."));
7399 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7401 macro_build (NULL, "break", BRK_FMT, 7);
7408 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7409 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7413 if (mips_opts.micromips)
7414 micromips_label_expr (&label_expr);
7416 label_expr.X_add_number = 8;
7417 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7418 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7419 macro_build (NULL, "break", BRK_FMT, 7);
7420 if (mips_opts.micromips)
7421 micromips_add_label ();
7423 expr1.X_add_number = -1;
7425 load_register (AT, &expr1, dbl);
7426 if (mips_opts.micromips)
7427 micromips_label_expr (&label_expr);
7429 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7430 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7433 expr1.X_add_number = 1;
7434 load_register (AT, &expr1, dbl);
7435 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7439 expr1.X_add_number = 0x80000000;
7440 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7444 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7445 /* We want to close the noreorder block as soon as possible, so
7446 that later insns are available for delay slot filling. */
7451 if (mips_opts.micromips)
7452 micromips_label_expr (&label_expr);
7454 label_expr.X_add_number = 8;
7455 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7456 macro_build (NULL, "nop", "");
7458 /* We want to close the noreorder block as soon as possible, so
7459 that later insns are available for delay slot filling. */
7462 macro_build (NULL, "break", BRK_FMT, 6);
7464 if (mips_opts.micromips)
7465 micromips_add_label ();
7466 macro_build (NULL, s, MFHL_FMT, dreg);
7505 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7507 as_warn (_("Divide by zero."));
7509 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7511 macro_build (NULL, "break", BRK_FMT, 7);
7514 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7516 if (strcmp (s2, "mflo") == 0)
7517 move_register (dreg, sreg);
7519 move_register (dreg, ZERO);
7522 if (imm_expr.X_op == O_constant
7523 && imm_expr.X_add_number == -1
7524 && s[strlen (s) - 1] != 'u')
7526 if (strcmp (s2, "mflo") == 0)
7528 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7531 move_register (dreg, ZERO);
7536 load_register (AT, &imm_expr, dbl);
7537 macro_build (NULL, s, "z,s,t", sreg, AT);
7538 macro_build (NULL, s2, MFHL_FMT, dreg);
7560 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7561 macro_build (NULL, s, "z,s,t", sreg, treg);
7562 /* We want to close the noreorder block as soon as possible, so
7563 that later insns are available for delay slot filling. */
7568 if (mips_opts.micromips)
7569 micromips_label_expr (&label_expr);
7571 label_expr.X_add_number = 8;
7572 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7573 macro_build (NULL, s, "z,s,t", sreg, treg);
7575 /* We want to close the noreorder block as soon as possible, so
7576 that later insns are available for delay slot filling. */
7578 macro_build (NULL, "break", BRK_FMT, 7);
7579 if (mips_opts.micromips)
7580 micromips_add_label ();
7582 macro_build (NULL, s2, MFHL_FMT, dreg);
7594 /* Load the address of a symbol into a register. If breg is not
7595 zero, we then add a base register to it. */
7597 if (dbl && HAVE_32BIT_GPRS)
7598 as_warn (_("dla used to load 32-bit register"));
7600 if (!dbl && HAVE_64BIT_OBJECTS)
7601 as_warn (_("la used to load 64-bit address"));
7603 if (small_offset_p (0, align, 16))
7605 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
7606 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
7610 if (mips_opts.at && (treg == breg))
7620 if (offset_expr.X_op != O_symbol
7621 && offset_expr.X_op != O_constant)
7623 as_bad (_("Expression too complex"));
7624 offset_expr.X_op = O_constant;
7627 if (offset_expr.X_op == O_constant)
7628 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7629 else if (mips_pic == NO_PIC)
7631 /* If this is a reference to a GP relative symbol, we want
7632 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7634 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7635 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7636 If we have a constant, we need two instructions anyhow,
7637 so we may as well always use the latter form.
7639 With 64bit address space and a usable $at we want
7640 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7641 lui $at,<sym> (BFD_RELOC_HI16_S)
7642 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7643 daddiu $at,<sym> (BFD_RELOC_LO16)
7645 daddu $tempreg,$tempreg,$at
7647 If $at is already in use, we use a path which is suboptimal
7648 on superscalar processors.
7649 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7650 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7652 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7654 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7656 For GP relative symbols in 64bit address space we can use
7657 the same sequence as in 32bit address space. */
7658 if (HAVE_64BIT_SYMBOLS)
7660 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7661 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7663 relax_start (offset_expr.X_add_symbol);
7664 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7665 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7669 if (used_at == 0 && mips_opts.at)
7671 macro_build (&offset_expr, "lui", LUI_FMT,
7672 tempreg, BFD_RELOC_MIPS_HIGHEST);
7673 macro_build (&offset_expr, "lui", LUI_FMT,
7674 AT, BFD_RELOC_HI16_S);
7675 macro_build (&offset_expr, "daddiu", "t,r,j",
7676 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7677 macro_build (&offset_expr, "daddiu", "t,r,j",
7678 AT, AT, BFD_RELOC_LO16);
7679 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7680 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7685 macro_build (&offset_expr, "lui", LUI_FMT,
7686 tempreg, BFD_RELOC_MIPS_HIGHEST);
7687 macro_build (&offset_expr, "daddiu", "t,r,j",
7688 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7689 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7690 macro_build (&offset_expr, "daddiu", "t,r,j",
7691 tempreg, tempreg, BFD_RELOC_HI16_S);
7692 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7693 macro_build (&offset_expr, "daddiu", "t,r,j",
7694 tempreg, tempreg, BFD_RELOC_LO16);
7697 if (mips_relax.sequence)
7702 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7703 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7705 relax_start (offset_expr.X_add_symbol);
7706 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7707 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7710 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7711 as_bad (_("Offset too large"));
7712 macro_build_lui (&offset_expr, tempreg);
7713 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7714 tempreg, tempreg, BFD_RELOC_LO16);
7715 if (mips_relax.sequence)
7719 else if (!mips_big_got && !HAVE_NEWABI)
7721 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7723 /* If this is a reference to an external symbol, and there
7724 is no constant, we want
7725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7726 or for lca or if tempreg is PIC_CALL_REG
7727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7728 For a local symbol, we want
7729 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7731 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7733 If we have a small constant, and this is a reference to
7734 an external symbol, we want
7735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7737 addiu $tempreg,$tempreg,<constant>
7738 For a local symbol, we want the same instruction
7739 sequence, but we output a BFD_RELOC_LO16 reloc on the
7742 If we have a large constant, and this is a reference to
7743 an external symbol, we want
7744 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7745 lui $at,<hiconstant>
7746 addiu $at,$at,<loconstant>
7747 addu $tempreg,$tempreg,$at
7748 For a local symbol, we want the same instruction
7749 sequence, but we output a BFD_RELOC_LO16 reloc on the
7753 if (offset_expr.X_add_number == 0)
7755 if (mips_pic == SVR4_PIC
7757 && (call || tempreg == PIC_CALL_REG))
7758 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7760 relax_start (offset_expr.X_add_symbol);
7761 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7762 lw_reloc_type, mips_gp_register);
7765 /* We're going to put in an addu instruction using
7766 tempreg, so we may as well insert the nop right
7771 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7772 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7774 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7775 tempreg, tempreg, BFD_RELOC_LO16);
7777 /* FIXME: If breg == 0, and the next instruction uses
7778 $tempreg, then if this variant case is used an extra
7779 nop will be generated. */
7781 else if (offset_expr.X_add_number >= -0x8000
7782 && offset_expr.X_add_number < 0x8000)
7784 load_got_offset (tempreg, &offset_expr);
7786 add_got_offset (tempreg, &offset_expr);
7790 expr1.X_add_number = offset_expr.X_add_number;
7791 offset_expr.X_add_number =
7792 SEXT_16BIT (offset_expr.X_add_number);
7793 load_got_offset (tempreg, &offset_expr);
7794 offset_expr.X_add_number = expr1.X_add_number;
7795 /* If we are going to add in a base register, and the
7796 target register and the base register are the same,
7797 then we are using AT as a temporary register. Since
7798 we want to load the constant into AT, we add our
7799 current AT (from the global offset table) and the
7800 register into the register now, and pretend we were
7801 not using a base register. */
7805 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7810 add_got_offset_hilo (tempreg, &offset_expr, AT);
7814 else if (!mips_big_got && HAVE_NEWABI)
7816 int add_breg_early = 0;
7818 /* If this is a reference to an external, and there is no
7819 constant, or local symbol (*), with or without a
7821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7822 or for lca or if tempreg is PIC_CALL_REG
7823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7825 If we have a small constant, and this is a reference to
7826 an external symbol, we want
7827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7828 addiu $tempreg,$tempreg,<constant>
7830 If we have a large constant, and this is a reference to
7831 an external symbol, we want
7832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7833 lui $at,<hiconstant>
7834 addiu $at,$at,<loconstant>
7835 addu $tempreg,$tempreg,$at
7837 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7838 local symbols, even though it introduces an additional
7841 if (offset_expr.X_add_number)
7843 expr1.X_add_number = offset_expr.X_add_number;
7844 offset_expr.X_add_number = 0;
7846 relax_start (offset_expr.X_add_symbol);
7847 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7848 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7850 if (expr1.X_add_number >= -0x8000
7851 && expr1.X_add_number < 0x8000)
7853 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7854 tempreg, tempreg, BFD_RELOC_LO16);
7856 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7858 /* If we are going to add in a base register, and the
7859 target register and the base register are the same,
7860 then we are using AT as a temporary register. Since
7861 we want to load the constant into AT, we add our
7862 current AT (from the global offset table) and the
7863 register into the register now, and pretend we were
7864 not using a base register. */
7869 gas_assert (tempreg == AT);
7870 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7876 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7877 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7883 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7886 offset_expr.X_add_number = expr1.X_add_number;
7888 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7889 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7892 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7893 treg, tempreg, breg);
7899 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7901 relax_start (offset_expr.X_add_symbol);
7902 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7903 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7905 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7906 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7911 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7912 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7915 else if (mips_big_got && !HAVE_NEWABI)
7918 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7919 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7920 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7922 /* This is the large GOT case. If this is a reference to an
7923 external symbol, and there is no constant, we want
7924 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7925 addu $tempreg,$tempreg,$gp
7926 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7927 or for lca or if tempreg is PIC_CALL_REG
7928 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7929 addu $tempreg,$tempreg,$gp
7930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7931 For a local symbol, we want
7932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7936 If we have a small constant, and this is a reference to
7937 an external symbol, we want
7938 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7939 addu $tempreg,$tempreg,$gp
7940 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7942 addiu $tempreg,$tempreg,<constant>
7943 For a local symbol, we want
7944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7946 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7948 If we have a large constant, and this is a reference to
7949 an external symbol, we want
7950 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7951 addu $tempreg,$tempreg,$gp
7952 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7953 lui $at,<hiconstant>
7954 addiu $at,$at,<loconstant>
7955 addu $tempreg,$tempreg,$at
7956 For a local symbol, we want
7957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7958 lui $at,<hiconstant>
7959 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7960 addu $tempreg,$tempreg,$at
7963 expr1.X_add_number = offset_expr.X_add_number;
7964 offset_expr.X_add_number = 0;
7965 relax_start (offset_expr.X_add_symbol);
7966 gpdelay = reg_needs_delay (mips_gp_register);
7967 if (expr1.X_add_number == 0 && breg == 0
7968 && (call || tempreg == PIC_CALL_REG))
7970 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7971 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7973 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7975 tempreg, tempreg, mips_gp_register);
7976 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7977 tempreg, lw_reloc_type, tempreg);
7978 if (expr1.X_add_number == 0)
7982 /* We're going to put in an addu instruction using
7983 tempreg, so we may as well insert the nop right
7988 else if (expr1.X_add_number >= -0x8000
7989 && expr1.X_add_number < 0x8000)
7992 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7993 tempreg, tempreg, BFD_RELOC_LO16);
7997 /* If we are going to add in a base register, and the
7998 target register and the base register are the same,
7999 then we are using AT as a temporary register. Since
8000 we want to load the constant into AT, we add our
8001 current AT (from the global offset table) and the
8002 register into the register now, and pretend we were
8003 not using a base register. */
8008 gas_assert (tempreg == AT);
8010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8015 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8020 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
8025 /* This is needed because this instruction uses $gp, but
8026 the first instruction on the main stream does not. */
8027 macro_build (NULL, "nop", "");
8030 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8031 local_reloc_type, mips_gp_register);
8032 if (expr1.X_add_number >= -0x8000
8033 && expr1.X_add_number < 0x8000)
8036 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8037 tempreg, tempreg, BFD_RELOC_LO16);
8038 /* FIXME: If add_number is 0, and there was no base
8039 register, the external symbol case ended with a load,
8040 so if the symbol turns out to not be external, and
8041 the next instruction uses tempreg, an unnecessary nop
8042 will be inserted. */
8048 /* We must add in the base register now, as in the
8049 external symbol case. */
8050 gas_assert (tempreg == AT);
8052 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8055 /* We set breg to 0 because we have arranged to add
8056 it in in both cases. */
8060 macro_build_lui (&expr1, AT);
8061 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8062 AT, AT, BFD_RELOC_LO16);
8063 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8064 tempreg, tempreg, AT);
8069 else if (mips_big_got && HAVE_NEWABI)
8071 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8072 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8073 int add_breg_early = 0;
8075 /* This is the large GOT case. If this is a reference to an
8076 external symbol, and there is no constant, we want
8077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8078 add $tempreg,$tempreg,$gp
8079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8080 or for lca or if tempreg is PIC_CALL_REG
8081 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8082 add $tempreg,$tempreg,$gp
8083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8085 If we have a small constant, and this is a reference to
8086 an external symbol, we want
8087 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8088 add $tempreg,$tempreg,$gp
8089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8090 addi $tempreg,$tempreg,<constant>
8092 If we have a large constant, and this is a reference to
8093 an external symbol, we want
8094 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8095 addu $tempreg,$tempreg,$gp
8096 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8097 lui $at,<hiconstant>
8098 addi $at,$at,<loconstant>
8099 add $tempreg,$tempreg,$at
8101 If we have NewABI, and we know it's a local symbol, we want
8102 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8103 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8104 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8106 relax_start (offset_expr.X_add_symbol);
8108 expr1.X_add_number = offset_expr.X_add_number;
8109 offset_expr.X_add_number = 0;
8111 if (expr1.X_add_number == 0 && breg == 0
8112 && (call || tempreg == PIC_CALL_REG))
8114 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8115 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8117 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8119 tempreg, tempreg, mips_gp_register);
8120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8121 tempreg, lw_reloc_type, tempreg);
8123 if (expr1.X_add_number == 0)
8125 else if (expr1.X_add_number >= -0x8000
8126 && expr1.X_add_number < 0x8000)
8128 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8129 tempreg, tempreg, BFD_RELOC_LO16);
8131 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8133 /* If we are going to add in a base register, and the
8134 target register and the base register are the same,
8135 then we are using AT as a temporary register. Since
8136 we want to load the constant into AT, we add our
8137 current AT (from the global offset table) and the
8138 register into the register now, and pretend we were
8139 not using a base register. */
8144 gas_assert (tempreg == AT);
8145 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8151 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8157 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8160 offset_expr.X_add_number = expr1.X_add_number;
8161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8162 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8163 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8164 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8167 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8168 treg, tempreg, breg);
8178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8182 gas_assert (!mips_opts.micromips);
8184 unsigned long temp = (treg << 16) | (0x01);
8185 macro_build (NULL, "c2", "C", temp);
8190 gas_assert (!mips_opts.micromips);
8192 unsigned long temp = (0x02);
8193 macro_build (NULL, "c2", "C", temp);
8198 gas_assert (!mips_opts.micromips);
8200 unsigned long temp = (treg << 16) | (0x02);
8201 macro_build (NULL, "c2", "C", temp);
8206 gas_assert (!mips_opts.micromips);
8207 macro_build (NULL, "c2", "C", 3);
8211 gas_assert (!mips_opts.micromips);
8213 unsigned long temp = (treg << 16) | 0x03;
8214 macro_build (NULL, "c2", "C", temp);
8219 /* The j instruction may not be used in PIC code, since it
8220 requires an absolute address. We convert it to a b
8222 if (mips_pic == NO_PIC)
8223 macro_build (&offset_expr, "j", "a");
8225 macro_build (&offset_expr, "b", "p");
8228 /* The jal instructions must be handled as macros because when
8229 generating PIC code they expand to multi-instruction
8230 sequences. Normally they are simple instructions. */
8235 gas_assert (mips_opts.micromips);
8236 if (mips_opts.insn32)
8238 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8248 if (mips_pic == NO_PIC)
8250 s = jals ? "jalrs" : "jalr";
8251 if (mips_opts.micromips
8252 && !mips_opts.insn32
8254 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8255 macro_build (NULL, s, "mj", sreg);
8257 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8261 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8262 && mips_cprestore_offset >= 0);
8264 if (sreg != PIC_CALL_REG)
8265 as_warn (_("MIPS PIC call to register other than $25"));
8267 s = ((mips_opts.micromips
8268 && !mips_opts.insn32
8269 && (!mips_opts.noreorder || cprestore))
8270 ? "jalrs" : "jalr");
8271 if (mips_opts.micromips
8272 && !mips_opts.insn32
8274 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8275 macro_build (NULL, s, "mj", sreg);
8277 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8278 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8280 if (mips_cprestore_offset < 0)
8281 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8284 if (!mips_frame_reg_valid)
8286 as_warn (_("No .frame pseudo-op used in PIC code"));
8287 /* Quiet this warning. */
8288 mips_frame_reg_valid = 1;
8290 if (!mips_cprestore_valid)
8292 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8293 /* Quiet this warning. */
8294 mips_cprestore_valid = 1;
8296 if (mips_opts.noreorder)
8297 macro_build (NULL, "nop", "");
8298 expr1.X_add_number = mips_cprestore_offset;
8299 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8302 HAVE_64BIT_ADDRESSES);
8310 gas_assert (mips_opts.micromips);
8311 if (mips_opts.insn32)
8313 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8319 if (mips_pic == NO_PIC)
8320 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8321 else if (mips_pic == SVR4_PIC)
8323 /* If this is a reference to an external symbol, and we are
8324 using a small GOT, we want
8325 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8329 lw $gp,cprestore($sp)
8330 The cprestore value is set using the .cprestore
8331 pseudo-op. If we are using a big GOT, we want
8332 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8334 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8338 lw $gp,cprestore($sp)
8339 If the symbol is not external, we want
8340 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8342 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8345 lw $gp,cprestore($sp)
8347 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8348 sequences above, minus nops, unless the symbol is local,
8349 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8355 relax_start (offset_expr.X_add_symbol);
8356 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8357 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8360 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8361 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8367 relax_start (offset_expr.X_add_symbol);
8368 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8369 BFD_RELOC_MIPS_CALL_HI16);
8370 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8371 PIC_CALL_REG, mips_gp_register);
8372 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8373 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8376 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8377 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8379 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8380 PIC_CALL_REG, PIC_CALL_REG,
8381 BFD_RELOC_MIPS_GOT_OFST);
8385 macro_build_jalr (&offset_expr, 0);
8389 relax_start (offset_expr.X_add_symbol);
8392 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8393 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8402 gpdelay = reg_needs_delay (mips_gp_register);
8403 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8404 BFD_RELOC_MIPS_CALL_HI16);
8405 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8406 PIC_CALL_REG, mips_gp_register);
8407 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8408 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8413 macro_build (NULL, "nop", "");
8415 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8416 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8419 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8420 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8422 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8424 if (mips_cprestore_offset < 0)
8425 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8428 if (!mips_frame_reg_valid)
8430 as_warn (_("No .frame pseudo-op used in PIC code"));
8431 /* Quiet this warning. */
8432 mips_frame_reg_valid = 1;
8434 if (!mips_cprestore_valid)
8436 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8437 /* Quiet this warning. */
8438 mips_cprestore_valid = 1;
8440 if (mips_opts.noreorder)
8441 macro_build (NULL, "nop", "");
8442 expr1.X_add_number = mips_cprestore_offset;
8443 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8446 HAVE_64BIT_ADDRESSES);
8450 else if (mips_pic == VXWORKS_PIC)
8451 as_bad (_("Non-PIC jump used in PIC library"));
8529 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8535 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8560 gas_assert (!mips_opts.micromips);
8563 /* Itbl support may require additional care here. */
8569 /* Itbl support may require additional care here. */
8575 offbits = (mips_opts.micromips ? 12 : 16);
8576 /* Itbl support may require additional care here. */
8580 gas_assert (!mips_opts.micromips);
8583 /* Itbl support may require additional care here. */
8589 offbits = (mips_opts.micromips ? 12 : 16);
8594 offbits = (mips_opts.micromips ? 12 : 16);
8599 /* Itbl support may require additional care here. */
8605 offbits = (mips_opts.micromips ? 12 : 16);
8606 /* Itbl support may require additional care here. */
8612 /* Itbl support may require additional care here. */
8618 /* Itbl support may require additional care here. */
8624 offbits = (mips_opts.micromips ? 12 : 16);
8629 offbits = (mips_opts.micromips ? 12 : 16);
8634 offbits = (mips_opts.micromips ? 12 : 16);
8639 offbits = (mips_opts.micromips ? 12 : 16);
8644 offbits = (mips_opts.micromips ? 12 : 16);
8647 gas_assert (mips_opts.micromips);
8654 gas_assert (mips_opts.micromips);
8661 gas_assert (mips_opts.micromips);
8667 gas_assert (mips_opts.micromips);
8674 /* We don't want to use $0 as tempreg. */
8675 if (breg == treg + lp || treg + lp == ZERO)
8678 tempreg = treg + lp;
8694 gas_assert (!mips_opts.micromips);
8697 /* Itbl support may require additional care here. */
8703 /* Itbl support may require additional care here. */
8709 offbits = (mips_opts.micromips ? 12 : 16);
8710 /* Itbl support may require additional care here. */
8714 gas_assert (!mips_opts.micromips);
8717 /* Itbl support may require additional care here. */
8723 offbits = (mips_opts.micromips ? 12 : 16);
8728 offbits = (mips_opts.micromips ? 12 : 16);
8733 offbits = (mips_opts.micromips ? 12 : 16);
8738 offbits = (mips_opts.micromips ? 12 : 16);
8742 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8743 offbits = (mips_opts.micromips ? 12 : 16);
8752 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8753 offbits = (mips_opts.micromips ? 12 : 16);
8764 /* Itbl support may require additional care here. */
8769 offbits = (mips_opts.micromips ? 12 : 16);
8770 /* Itbl support may require additional care here. */
8776 /* Itbl support may require additional care here. */
8780 gas_assert (!mips_opts.micromips);
8783 /* Itbl support may require additional care here. */
8789 offbits = (mips_opts.micromips ? 12 : 16);
8794 offbits = (mips_opts.micromips ? 12 : 16);
8797 gas_assert (mips_opts.micromips);
8803 gas_assert (mips_opts.micromips);
8809 gas_assert (mips_opts.micromips);
8815 gas_assert (mips_opts.micromips);
8823 if (small_offset_p (0, align, 16))
8825 /* The first case exists for M_LD_AB and M_SD_AB, which are
8826 macros for o32 but which should act like normal instructions
8829 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
8830 offset_reloc[1], offset_reloc[2], breg);
8831 else if (small_offset_p (0, align, offbits))
8834 macro_build (NULL, s, fmt, treg, breg);
8836 macro_build (NULL, s, fmt, treg,
8837 (unsigned long) offset_expr.X_add_number, breg);
8843 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8844 tempreg, breg, -1, offset_reloc[0],
8845 offset_reloc[1], offset_reloc[2]);
8847 macro_build (NULL, s, fmt, treg, tempreg);
8849 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8857 if (offset_expr.X_op != O_constant
8858 && offset_expr.X_op != O_symbol)
8860 as_bad (_("Expression too complex"));
8861 offset_expr.X_op = O_constant;
8864 if (HAVE_32BIT_ADDRESSES
8865 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8869 sprintf_vma (value, offset_expr.X_add_number);
8870 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8873 /* A constant expression in PIC code can be handled just as it
8874 is in non PIC code. */
8875 if (offset_expr.X_op == O_constant)
8877 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
8878 offbits == 0 ? 16 : offbits);
8879 offset_expr.X_add_number -= expr1.X_add_number;
8881 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8883 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8884 tempreg, tempreg, breg);
8887 if (offset_expr.X_add_number != 0)
8888 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8889 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
8890 macro_build (NULL, s, fmt, treg, tempreg);
8892 else if (offbits == 16)
8893 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8895 macro_build (NULL, s, fmt, treg,
8896 (unsigned long) offset_expr.X_add_number, tempreg);
8898 else if (offbits != 16)
8900 /* The offset field is too narrow to be used for a low-part
8901 relocation, so load the whole address into the auxillary
8903 load_address (tempreg, &offset_expr, &used_at);
8905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8906 tempreg, tempreg, breg);
8908 macro_build (NULL, s, fmt, treg, tempreg);
8910 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8912 else if (mips_pic == NO_PIC)
8914 /* If this is a reference to a GP relative symbol, and there
8915 is no base register, we want
8916 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8917 Otherwise, if there is no base register, we want
8918 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8919 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8920 If we have a constant, we need two instructions anyhow,
8921 so we always use the latter form.
8923 If we have a base register, and this is a reference to a
8924 GP relative symbol, we want
8925 addu $tempreg,$breg,$gp
8926 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8928 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8929 addu $tempreg,$tempreg,$breg
8930 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8931 With a constant we always use the latter case.
8933 With 64bit address space and no base register and $at usable,
8935 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8936 lui $at,<sym> (BFD_RELOC_HI16_S)
8937 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8940 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8941 If we have a base register, we want
8942 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8943 lui $at,<sym> (BFD_RELOC_HI16_S)
8944 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8948 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8950 Without $at we can't generate the optimal path for superscalar
8951 processors here since this would require two temporary registers.
8952 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8955 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8957 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8958 If we have a base register, we want
8959 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8960 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8962 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8964 daddu $tempreg,$tempreg,$breg
8965 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8967 For GP relative symbols in 64bit address space we can use
8968 the same sequence as in 32bit address space. */
8969 if (HAVE_64BIT_SYMBOLS)
8971 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8972 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8974 relax_start (offset_expr.X_add_symbol);
8977 macro_build (&offset_expr, s, fmt, treg,
8978 BFD_RELOC_GPREL16, mips_gp_register);
8982 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8983 tempreg, breg, mips_gp_register);
8984 macro_build (&offset_expr, s, fmt, treg,
8985 BFD_RELOC_GPREL16, tempreg);
8990 if (used_at == 0 && mips_opts.at)
8992 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8993 BFD_RELOC_MIPS_HIGHEST);
8994 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8996 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8997 tempreg, BFD_RELOC_MIPS_HIGHER);
8999 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
9000 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9001 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9002 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
9008 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9009 BFD_RELOC_MIPS_HIGHEST);
9010 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9011 tempreg, BFD_RELOC_MIPS_HIGHER);
9012 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9013 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9014 tempreg, BFD_RELOC_HI16_S);
9015 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9017 macro_build (NULL, "daddu", "d,v,t",
9018 tempreg, tempreg, breg);
9019 macro_build (&offset_expr, s, fmt, treg,
9020 BFD_RELOC_LO16, tempreg);
9023 if (mips_relax.sequence)
9030 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9031 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9033 relax_start (offset_expr.X_add_symbol);
9034 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9038 macro_build_lui (&offset_expr, tempreg);
9039 macro_build (&offset_expr, s, fmt, treg,
9040 BFD_RELOC_LO16, tempreg);
9041 if (mips_relax.sequence)
9046 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9047 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9049 relax_start (offset_expr.X_add_symbol);
9050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9051 tempreg, breg, mips_gp_register);
9052 macro_build (&offset_expr, s, fmt, treg,
9053 BFD_RELOC_GPREL16, tempreg);
9056 macro_build_lui (&offset_expr, tempreg);
9057 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9058 tempreg, tempreg, breg);
9059 macro_build (&offset_expr, s, fmt, treg,
9060 BFD_RELOC_LO16, tempreg);
9061 if (mips_relax.sequence)
9065 else if (!mips_big_got)
9067 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9069 /* If this is a reference to an external symbol, we want
9070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9072 <op> $treg,0($tempreg)
9074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9076 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9077 <op> $treg,0($tempreg)
9080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9081 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9083 If there is a base register, we add it to $tempreg before
9084 the <op>. If there is a constant, we stick it in the
9085 <op> instruction. We don't handle constants larger than
9086 16 bits, because we have no way to load the upper 16 bits
9087 (actually, we could handle them for the subset of cases
9088 in which we are not using $at). */
9089 gas_assert (offset_expr.X_op == O_symbol);
9092 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9093 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9095 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9096 tempreg, tempreg, breg);
9097 macro_build (&offset_expr, s, fmt, treg,
9098 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9101 expr1.X_add_number = offset_expr.X_add_number;
9102 offset_expr.X_add_number = 0;
9103 if (expr1.X_add_number < -0x8000
9104 || expr1.X_add_number >= 0x8000)
9105 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9107 lw_reloc_type, mips_gp_register);
9109 relax_start (offset_expr.X_add_symbol);
9111 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9112 tempreg, BFD_RELOC_LO16);
9115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9116 tempreg, tempreg, breg);
9117 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9119 else if (mips_big_got && !HAVE_NEWABI)
9123 /* If this is a reference to an external symbol, we want
9124 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9125 addu $tempreg,$tempreg,$gp
9126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9127 <op> $treg,0($tempreg)
9129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9131 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9132 <op> $treg,0($tempreg)
9133 If there is a base register, we add it to $tempreg before
9134 the <op>. If there is a constant, we stick it in the
9135 <op> instruction. We don't handle constants larger than
9136 16 bits, because we have no way to load the upper 16 bits
9137 (actually, we could handle them for the subset of cases
9138 in which we are not using $at). */
9139 gas_assert (offset_expr.X_op == O_symbol);
9140 expr1.X_add_number = offset_expr.X_add_number;
9141 offset_expr.X_add_number = 0;
9142 if (expr1.X_add_number < -0x8000
9143 || expr1.X_add_number >= 0x8000)
9144 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9145 gpdelay = reg_needs_delay (mips_gp_register);
9146 relax_start (offset_expr.X_add_symbol);
9147 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9148 BFD_RELOC_MIPS_GOT_HI16);
9149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9151 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9152 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9155 macro_build (NULL, "nop", "");
9156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9157 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9159 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9160 tempreg, BFD_RELOC_LO16);
9164 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9165 tempreg, tempreg, breg);
9166 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9168 else if (mips_big_got && HAVE_NEWABI)
9170 /* If this is a reference to an external symbol, we want
9171 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9172 add $tempreg,$tempreg,$gp
9173 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9174 <op> $treg,<ofst>($tempreg)
9175 Otherwise, for local symbols, we want:
9176 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9177 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9178 gas_assert (offset_expr.X_op == O_symbol);
9179 expr1.X_add_number = offset_expr.X_add_number;
9180 offset_expr.X_add_number = 0;
9181 if (expr1.X_add_number < -0x8000
9182 || expr1.X_add_number >= 0x8000)
9183 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9184 relax_start (offset_expr.X_add_symbol);
9185 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9186 BFD_RELOC_MIPS_GOT_HI16);
9187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9189 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9190 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9192 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9193 tempreg, tempreg, breg);
9194 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9197 offset_expr.X_add_number = expr1.X_add_number;
9198 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9199 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9202 tempreg, tempreg, breg);
9203 macro_build (&offset_expr, s, fmt, treg,
9204 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9213 gas_assert (mips_opts.micromips);
9214 gas_assert (mips_opts.insn32);
9216 macro_build (NULL, "jr", "s", RA);
9217 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
9218 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
9223 gas_assert (mips_opts.micromips);
9224 gas_assert (mips_opts.insn32);
9225 macro_build (NULL, "jr", "s", sreg);
9226 if (mips_opts.noreorder)
9227 macro_build (NULL, "nop", "");
9232 load_register (treg, &imm_expr, 0);
9236 load_register (treg, &imm_expr, 1);
9240 if (imm_expr.X_op == O_constant)
9243 load_register (AT, &imm_expr, 0);
9244 macro_build (NULL, "mtc1", "t,G", AT, treg);
9249 gas_assert (offset_expr.X_op == O_symbol
9250 && strcmp (segment_name (S_GET_SEGMENT
9251 (offset_expr.X_add_symbol)),
9253 && offset_expr.X_add_number == 0);
9254 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9255 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9260 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9261 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9262 order 32 bits of the value and the low order 32 bits are either
9263 zero or in OFFSET_EXPR. */
9264 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9266 if (HAVE_64BIT_GPRS)
9267 load_register (treg, &imm_expr, 1);
9272 if (target_big_endian)
9284 load_register (hreg, &imm_expr, 0);
9287 if (offset_expr.X_op == O_absent)
9288 move_register (lreg, 0);
9291 gas_assert (offset_expr.X_op == O_constant);
9292 load_register (lreg, &offset_expr, 0);
9299 /* We know that sym is in the .rdata section. First we get the
9300 upper 16 bits of the address. */
9301 if (mips_pic == NO_PIC)
9303 macro_build_lui (&offset_expr, AT);
9308 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9309 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9313 /* Now we load the register(s). */
9314 if (HAVE_64BIT_GPRS)
9317 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9322 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9325 /* FIXME: How in the world do we deal with the possible
9327 offset_expr.X_add_number += 4;
9328 macro_build (&offset_expr, "lw", "t,o(b)",
9329 treg + 1, BFD_RELOC_LO16, AT);
9335 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9336 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9337 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9338 the value and the low order 32 bits are either zero or in
9340 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9343 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9344 if (HAVE_64BIT_FPRS)
9346 gas_assert (HAVE_64BIT_GPRS);
9347 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9351 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9352 if (offset_expr.X_op == O_absent)
9353 macro_build (NULL, "mtc1", "t,G", 0, treg);
9356 gas_assert (offset_expr.X_op == O_constant);
9357 load_register (AT, &offset_expr, 0);
9358 macro_build (NULL, "mtc1", "t,G", AT, treg);
9364 gas_assert (offset_expr.X_op == O_symbol
9365 && offset_expr.X_add_number == 0);
9366 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9367 if (strcmp (s, ".lit8") == 0)
9369 breg = mips_gp_register;
9370 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
9371 offset_reloc[1] = BFD_RELOC_UNUSED;
9372 offset_reloc[2] = BFD_RELOC_UNUSED;
9376 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9378 if (mips_pic != NO_PIC)
9379 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9380 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9383 /* FIXME: This won't work for a 64 bit address. */
9384 macro_build_lui (&offset_expr, AT);
9388 offset_reloc[0] = BFD_RELOC_LO16;
9389 offset_reloc[1] = BFD_RELOC_UNUSED;
9390 offset_reloc[2] = BFD_RELOC_UNUSED;
9397 * The MIPS assembler seems to check for X_add_number not
9398 * being double aligned and generating:
9401 * addiu at,at,%lo(foo+1)
9404 * But, the resulting address is the same after relocation so why
9405 * generate the extra instruction?
9407 /* Itbl support may require additional care here. */
9410 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9419 gas_assert (!mips_opts.micromips);
9420 /* Itbl support may require additional care here. */
9423 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9443 if (HAVE_64BIT_GPRS)
9453 if (HAVE_64BIT_GPRS)
9461 /* Even on a big endian machine $fn comes before $fn+1. We have
9462 to adjust when loading from memory. We set coproc if we must
9463 load $fn+1 first. */
9464 /* Itbl support may require additional care here. */
9465 if (!target_big_endian)
9468 if (small_offset_p (0, align, 16))
9471 if (!small_offset_p (4, align, 16))
9473 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
9474 -1, offset_reloc[0], offset_reloc[1],
9476 expr1.X_add_number = 0;
9480 offset_reloc[0] = BFD_RELOC_LO16;
9481 offset_reloc[1] = BFD_RELOC_UNUSED;
9482 offset_reloc[2] = BFD_RELOC_UNUSED;
9484 if (strcmp (s, "lw") == 0 && treg == breg)
9486 ep->X_add_number += 4;
9487 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
9488 offset_reloc[1], offset_reloc[2], breg);
9489 ep->X_add_number -= 4;
9490 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
9491 offset_reloc[1], offset_reloc[2], breg);
9495 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
9496 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9498 ep->X_add_number += 4;
9499 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
9500 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9506 if (offset_expr.X_op != O_symbol
9507 && offset_expr.X_op != O_constant)
9509 as_bad (_("Expression too complex"));
9510 offset_expr.X_op = O_constant;
9513 if (HAVE_32BIT_ADDRESSES
9514 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9518 sprintf_vma (value, offset_expr.X_add_number);
9519 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9522 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9524 /* If this is a reference to a GP relative symbol, we want
9525 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9526 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9527 If we have a base register, we use this
9529 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9530 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9531 If this is not a GP relative symbol, we want
9532 lui $at,<sym> (BFD_RELOC_HI16_S)
9533 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9534 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9535 If there is a base register, we add it to $at after the
9536 lui instruction. If there is a constant, we always use
9538 if (offset_expr.X_op == O_symbol
9539 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9540 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9542 relax_start (offset_expr.X_add_symbol);
9545 tempreg = mips_gp_register;
9549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9550 AT, breg, mips_gp_register);
9555 /* Itbl support may require additional care here. */
9556 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9557 BFD_RELOC_GPREL16, tempreg);
9558 offset_expr.X_add_number += 4;
9560 /* Set mips_optimize to 2 to avoid inserting an
9562 hold_mips_optimize = mips_optimize;
9564 /* Itbl support may require additional care here. */
9565 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9566 BFD_RELOC_GPREL16, tempreg);
9567 mips_optimize = hold_mips_optimize;
9571 offset_expr.X_add_number -= 4;
9574 if (offset_high_part (offset_expr.X_add_number, 16)
9575 != offset_high_part (offset_expr.X_add_number + 4, 16))
9577 load_address (AT, &offset_expr, &used_at);
9578 offset_expr.X_op = O_constant;
9579 offset_expr.X_add_number = 0;
9582 macro_build_lui (&offset_expr, AT);
9584 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9585 /* Itbl support may require additional care here. */
9586 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9587 BFD_RELOC_LO16, AT);
9588 /* FIXME: How do we handle overflow here? */
9589 offset_expr.X_add_number += 4;
9590 /* Itbl support may require additional care here. */
9591 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9592 BFD_RELOC_LO16, AT);
9593 if (mips_relax.sequence)
9596 else if (!mips_big_got)
9598 /* If this is a reference to an external symbol, we want
9599 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9604 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9606 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9607 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9608 If there is a base register we add it to $at before the
9609 lwc1 instructions. If there is a constant we include it
9610 in the lwc1 instructions. */
9612 expr1.X_add_number = offset_expr.X_add_number;
9613 if (expr1.X_add_number < -0x8000
9614 || expr1.X_add_number >= 0x8000 - 4)
9615 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9616 load_got_offset (AT, &offset_expr);
9619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9621 /* Set mips_optimize to 2 to avoid inserting an undesired
9623 hold_mips_optimize = mips_optimize;
9626 /* Itbl support may require additional care here. */
9627 relax_start (offset_expr.X_add_symbol);
9628 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9629 BFD_RELOC_LO16, AT);
9630 expr1.X_add_number += 4;
9631 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9632 BFD_RELOC_LO16, AT);
9634 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9635 BFD_RELOC_LO16, AT);
9636 offset_expr.X_add_number += 4;
9637 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9638 BFD_RELOC_LO16, AT);
9641 mips_optimize = hold_mips_optimize;
9643 else if (mips_big_got)
9647 /* If this is a reference to an external symbol, we want
9648 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9650 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9655 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9657 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9658 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9659 If there is a base register we add it to $at before the
9660 lwc1 instructions. If there is a constant we include it
9661 in the lwc1 instructions. */
9663 expr1.X_add_number = offset_expr.X_add_number;
9664 offset_expr.X_add_number = 0;
9665 if (expr1.X_add_number < -0x8000
9666 || expr1.X_add_number >= 0x8000 - 4)
9667 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9668 gpdelay = reg_needs_delay (mips_gp_register);
9669 relax_start (offset_expr.X_add_symbol);
9670 macro_build (&offset_expr, "lui", LUI_FMT,
9671 AT, BFD_RELOC_MIPS_GOT_HI16);
9672 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9673 AT, AT, mips_gp_register);
9674 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9675 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9678 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9679 /* Itbl support may require additional care here. */
9680 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9681 BFD_RELOC_LO16, AT);
9682 expr1.X_add_number += 4;
9684 /* Set mips_optimize to 2 to avoid inserting an undesired
9686 hold_mips_optimize = mips_optimize;
9688 /* Itbl support may require additional care here. */
9689 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9690 BFD_RELOC_LO16, AT);
9691 mips_optimize = hold_mips_optimize;
9692 expr1.X_add_number -= 4;
9695 offset_expr.X_add_number = expr1.X_add_number;
9697 macro_build (NULL, "nop", "");
9698 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9699 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9702 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9703 /* Itbl support may require additional care here. */
9704 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9705 BFD_RELOC_LO16, AT);
9706 offset_expr.X_add_number += 4;
9708 /* Set mips_optimize to 2 to avoid inserting an undesired
9710 hold_mips_optimize = mips_optimize;
9712 /* Itbl support may require additional care here. */
9713 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9714 BFD_RELOC_LO16, AT);
9715 mips_optimize = hold_mips_optimize;
9734 /* New code added to support COPZ instructions.
9735 This code builds table entries out of the macros in mip_opcodes.
9736 R4000 uses interlocks to handle coproc delays.
9737 Other chips (like the R3000) require nops to be inserted for delays.
9739 FIXME: Currently, we require that the user handle delays.
9740 In order to fill delay slots for non-interlocked chips,
9741 we must have a way to specify delays based on the coprocessor.
9742 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9743 What are the side-effects of the cop instruction?
9744 What cache support might we have and what are its effects?
9745 Both coprocessor & memory require delays. how long???
9746 What registers are read/set/modified?
9748 If an itbl is provided to interpret cop instructions,
9749 this knowledge can be encoded in the itbl spec. */
9763 gas_assert (!mips_opts.micromips);
9764 /* For now we just do C (same as Cz). The parameter will be
9765 stored in insn_opcode by mips_ip. */
9766 macro_build (NULL, s, "C", ip->insn_opcode);
9770 move_register (dreg, sreg);
9774 gas_assert (mips_opts.micromips);
9775 gas_assert (mips_opts.insn32);
9776 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
9777 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
9778 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
9779 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
9780 move_register (dreg, sreg);
9781 move_register (breg, treg);
9787 if (mips_opts.arch == CPU_R5900)
9789 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9793 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9794 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9801 /* The MIPS assembler some times generates shifts and adds. I'm
9802 not trying to be that fancy. GCC should do this for us
9805 load_register (AT, &imm_expr, dbl);
9806 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9807 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9823 load_register (AT, &imm_expr, dbl);
9824 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9825 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9826 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9827 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9829 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9832 if (mips_opts.micromips)
9833 micromips_label_expr (&label_expr);
9835 label_expr.X_add_number = 8;
9836 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9837 macro_build (NULL, "nop", "");
9838 macro_build (NULL, "break", BRK_FMT, 6);
9839 if (mips_opts.micromips)
9840 micromips_add_label ();
9843 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9859 load_register (AT, &imm_expr, dbl);
9860 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9861 sreg, imm ? AT : treg);
9862 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9863 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9865 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9868 if (mips_opts.micromips)
9869 micromips_label_expr (&label_expr);
9871 label_expr.X_add_number = 8;
9872 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9873 macro_build (NULL, "nop", "");
9874 macro_build (NULL, "break", BRK_FMT, 6);
9875 if (mips_opts.micromips)
9876 micromips_add_label ();
9882 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9893 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9894 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9898 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9899 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9900 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9901 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9905 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9916 macro_build (NULL, "negu", "d,w", tempreg, treg);
9917 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9921 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9922 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9923 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9924 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9933 if (imm_expr.X_op != O_constant)
9934 as_bad (_("Improper rotate count"));
9935 rot = imm_expr.X_add_number & 0x3f;
9936 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9938 rot = (64 - rot) & 0x3f;
9940 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9942 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9947 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9950 l = (rot < 0x20) ? "dsll" : "dsll32";
9951 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9954 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9955 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9956 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9964 if (imm_expr.X_op != O_constant)
9965 as_bad (_("Improper rotate count"));
9966 rot = imm_expr.X_add_number & 0x1f;
9967 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9969 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9974 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9978 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9979 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9980 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9985 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9987 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9991 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9992 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9993 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9994 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9998 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10000 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
10004 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
10005 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
10006 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
10007 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10016 if (imm_expr.X_op != O_constant)
10017 as_bad (_("Improper rotate count"));
10018 rot = imm_expr.X_add_number & 0x3f;
10019 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10022 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10024 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10029 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10032 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10033 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10036 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10037 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10038 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10046 if (imm_expr.X_op != O_constant)
10047 as_bad (_("Improper rotate count"));
10048 rot = imm_expr.X_add_number & 0x1f;
10049 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10051 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10056 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10060 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10061 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10062 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10068 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10069 else if (treg == 0)
10070 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10073 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10074 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10079 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10081 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10086 as_warn (_("Instruction %s: result is always false"),
10087 ip->insn_mo->name);
10088 move_register (dreg, 0);
10091 if (CPU_HAS_SEQ (mips_opts.arch)
10092 && -512 <= imm_expr.X_add_number
10093 && imm_expr.X_add_number < 512)
10095 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10096 (int) imm_expr.X_add_number);
10099 if (imm_expr.X_op == O_constant
10100 && imm_expr.X_add_number >= 0
10101 && imm_expr.X_add_number < 0x10000)
10103 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10105 else if (imm_expr.X_op == O_constant
10106 && imm_expr.X_add_number > -0x8000
10107 && imm_expr.X_add_number < 0)
10109 imm_expr.X_add_number = -imm_expr.X_add_number;
10110 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10111 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10113 else if (CPU_HAS_SEQ (mips_opts.arch))
10116 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10117 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10122 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10123 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10126 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10129 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10135 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10136 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10139 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10141 if (imm_expr.X_op == O_constant
10142 && imm_expr.X_add_number >= -0x8000
10143 && imm_expr.X_add_number < 0x8000)
10145 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10146 dreg, sreg, BFD_RELOC_LO16);
10150 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10151 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10155 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10158 case M_SGT: /* sreg > treg <==> treg < sreg */
10164 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10167 case M_SGT_I: /* sreg > I <==> I < sreg */
10174 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10175 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10178 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10184 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10185 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10188 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10195 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10196 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10197 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10201 if (imm_expr.X_op == O_constant
10202 && imm_expr.X_add_number >= -0x8000
10203 && imm_expr.X_add_number < 0x8000)
10205 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10209 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10210 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10214 if (imm_expr.X_op == O_constant
10215 && imm_expr.X_add_number >= -0x8000
10216 && imm_expr.X_add_number < 0x8000)
10218 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10223 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10224 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10229 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10230 else if (treg == 0)
10231 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10234 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10235 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10240 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10242 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10247 as_warn (_("Instruction %s: result is always true"),
10248 ip->insn_mo->name);
10249 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10250 dreg, 0, BFD_RELOC_LO16);
10253 if (CPU_HAS_SEQ (mips_opts.arch)
10254 && -512 <= imm_expr.X_add_number
10255 && imm_expr.X_add_number < 512)
10257 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10258 (int) imm_expr.X_add_number);
10261 if (imm_expr.X_op == O_constant
10262 && imm_expr.X_add_number >= 0
10263 && imm_expr.X_add_number < 0x10000)
10265 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10267 else if (imm_expr.X_op == O_constant
10268 && imm_expr.X_add_number > -0x8000
10269 && imm_expr.X_add_number < 0)
10271 imm_expr.X_add_number = -imm_expr.X_add_number;
10272 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10273 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10275 else if (CPU_HAS_SEQ (mips_opts.arch))
10278 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10279 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10284 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10285 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10288 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10303 if (!mips_opts.micromips)
10305 if (imm_expr.X_op == O_constant
10306 && imm_expr.X_add_number > -0x200
10307 && imm_expr.X_add_number <= 0x200)
10309 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10318 if (imm_expr.X_op == O_constant
10319 && imm_expr.X_add_number > -0x8000
10320 && imm_expr.X_add_number <= 0x8000)
10322 imm_expr.X_add_number = -imm_expr.X_add_number;
10323 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10328 load_register (AT, &imm_expr, dbl);
10329 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10351 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10352 macro_build (NULL, s, "s,t", sreg, AT);
10357 gas_assert (!mips_opts.micromips);
10358 gas_assert (mips_opts.isa == ISA_MIPS1);
10360 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10361 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10364 * Is the double cfc1 instruction a bug in the mips assembler;
10365 * or is there a reason for it?
10367 start_noreorder ();
10368 macro_build (NULL, "cfc1", "t,G", treg, RA);
10369 macro_build (NULL, "cfc1", "t,G", treg, RA);
10370 macro_build (NULL, "nop", "");
10371 expr1.X_add_number = 3;
10372 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10373 expr1.X_add_number = 2;
10374 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10375 macro_build (NULL, "ctc1", "t,G", AT, RA);
10376 macro_build (NULL, "nop", "");
10377 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10379 macro_build (NULL, "ctc1", "t,G", treg, RA);
10380 macro_build (NULL, "nop", "");
10397 offbits = (mips_opts.micromips ? 12 : 16);
10403 offbits = (mips_opts.micromips ? 12 : 16);
10415 offbits = (mips_opts.micromips ? 12 : 16);
10422 offbits = (mips_opts.micromips ? 12 : 16);
10427 large_offset = !small_offset_p (off, align, offbits);
10429 expr1.X_add_number = 0;
10434 if (small_offset_p (0, align, 16))
10435 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
10436 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10439 load_address (tempreg, ep, &used_at);
10441 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10442 tempreg, tempreg, breg);
10444 offset_reloc[0] = BFD_RELOC_LO16;
10445 offset_reloc[1] = BFD_RELOC_UNUSED;
10446 offset_reloc[2] = BFD_RELOC_UNUSED;
10451 else if (!ust && treg == breg)
10462 if (!target_big_endian)
10463 ep->X_add_number += off;
10465 macro_build (NULL, s, "t,~(b)",
10466 tempreg, (unsigned long) ep->X_add_number, breg);
10468 macro_build (ep, s, "t,o(b)", tempreg, -1,
10469 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10471 if (!target_big_endian)
10472 ep->X_add_number -= off;
10474 ep->X_add_number += off;
10476 macro_build (NULL, s2, "t,~(b)",
10477 tempreg, (unsigned long) ep->X_add_number, breg);
10479 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10480 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10482 /* If necessary, move the result in tempreg to the final destination. */
10483 if (!ust && treg != tempreg)
10485 /* Protect second load's delay slot. */
10487 move_register (treg, tempreg);
10493 if (target_big_endian == ust)
10494 ep->X_add_number += off;
10495 tempreg = ust || large_offset ? treg : AT;
10496 macro_build (ep, s, "t,o(b)", tempreg, -1,
10497 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10499 /* For halfword transfers we need a temporary register to shuffle
10500 bytes. Unfortunately for M_USH_A we have none available before
10501 the next store as AT holds the base address. We deal with this
10502 case by clobbering TREG and then restoring it as with ULH. */
10503 tempreg = ust == large_offset ? treg : AT;
10505 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10507 if (target_big_endian == ust)
10508 ep->X_add_number -= off;
10510 ep->X_add_number += off;
10511 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10512 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10514 /* For M_USH_A re-retrieve the LSB. */
10515 if (ust && large_offset)
10517 if (target_big_endian)
10518 ep->X_add_number += off;
10520 ep->X_add_number -= off;
10521 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
10522 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
10524 /* For ULH and M_USH_A OR the LSB in. */
10525 if (!ust || large_offset)
10527 tempreg = !large_offset ? AT : treg;
10528 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10529 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10534 /* FIXME: Check if this is one of the itbl macros, since they
10535 are added dynamically. */
10536 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10539 if (!mips_opts.at && used_at)
10540 as_bad (_("Macro used $at after \".set noat\""));
10543 /* Implement macros in mips16 mode. */
10546 mips16_macro (struct mips_cl_insn *ip)
10549 int xreg, yreg, zreg, tmp;
10552 const char *s, *s2, *s3;
10554 mask = ip->insn_mo->mask;
10556 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10557 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10558 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10560 expr1.X_op = O_constant;
10561 expr1.X_op_symbol = NULL;
10562 expr1.X_add_symbol = NULL;
10563 expr1.X_add_number = 1;
10582 start_noreorder ();
10583 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10584 expr1.X_add_number = 2;
10585 macro_build (&expr1, "bnez", "x,p", yreg);
10586 macro_build (NULL, "break", "6", 7);
10588 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10589 since that causes an overflow. We should do that as well,
10590 but I don't see how to do the comparisons without a temporary
10593 macro_build (NULL, s, "x", zreg);
10612 start_noreorder ();
10613 macro_build (NULL, s, "0,x,y", xreg, yreg);
10614 expr1.X_add_number = 2;
10615 macro_build (&expr1, "bnez", "x,p", yreg);
10616 macro_build (NULL, "break", "6", 7);
10618 macro_build (NULL, s2, "x", zreg);
10624 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10625 macro_build (NULL, "mflo", "x", zreg);
10633 if (imm_expr.X_op != O_constant)
10634 as_bad (_("Unsupported large constant"));
10635 imm_expr.X_add_number = -imm_expr.X_add_number;
10636 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10640 if (imm_expr.X_op != O_constant)
10641 as_bad (_("Unsupported large constant"));
10642 imm_expr.X_add_number = -imm_expr.X_add_number;
10643 macro_build (&imm_expr, "addiu", "x,k", xreg);
10647 if (imm_expr.X_op != O_constant)
10648 as_bad (_("Unsupported large constant"));
10649 imm_expr.X_add_number = -imm_expr.X_add_number;
10650 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10672 goto do_reverse_branch;
10676 goto do_reverse_branch;
10688 goto do_reverse_branch;
10699 macro_build (NULL, s, "x,y", xreg, yreg);
10700 macro_build (&offset_expr, s2, "p");
10727 goto do_addone_branch_i;
10732 goto do_addone_branch_i;
10747 goto do_addone_branch_i;
10753 do_addone_branch_i:
10754 if (imm_expr.X_op != O_constant)
10755 as_bad (_("Unsupported large constant"));
10756 ++imm_expr.X_add_number;
10759 macro_build (&imm_expr, s, s3, xreg);
10760 macro_build (&offset_expr, s2, "p");
10764 expr1.X_add_number = 0;
10765 macro_build (&expr1, "slti", "x,8", yreg);
10767 move_register (xreg, yreg);
10768 expr1.X_add_number = 2;
10769 macro_build (&expr1, "bteqz", "p");
10770 macro_build (NULL, "neg", "x,w", xreg, xreg);
10774 /* For consistency checking, verify that all bits are specified either
10775 by the match/mask part of the instruction definition, or by the
10778 validate_mips_insn (const struct mips_opcode *opc)
10780 const char *p = opc->args;
10782 unsigned long used_bits = opc->mask;
10784 if ((used_bits & opc->match) != opc->match)
10786 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10787 opc->name, opc->args);
10790 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10800 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10801 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10802 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10803 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10804 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10805 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10806 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10807 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10808 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10809 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10810 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10812 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10813 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10814 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10815 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10816 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10817 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10818 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10819 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10820 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10821 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10822 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10823 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10824 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10825 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10826 case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10827 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10830 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10831 c, opc->name, opc->args);
10835 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10836 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10838 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10839 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10840 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10841 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10843 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10844 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10846 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10847 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10849 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10850 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10851 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10852 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10853 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10854 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10855 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10856 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10857 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10858 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10859 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10860 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10861 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10862 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10863 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10864 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10865 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10867 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10868 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10869 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10870 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10872 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10873 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10874 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10875 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10876 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10877 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10878 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10879 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10880 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10883 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10884 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10885 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10886 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10887 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10888 case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
10889 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10890 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10891 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10892 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10893 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10894 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10895 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10896 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10897 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10898 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10899 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10900 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10901 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10902 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10903 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10904 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10905 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10906 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10907 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10909 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10910 c, opc->name, opc->args);
10914 if (used_bits != 0xffffffff)
10916 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10917 ~used_bits & 0xffffffff, opc->name, opc->args);
10923 /* For consistency checking, verify that the length implied matches the
10924 major opcode and that all bits are specified either by the match/mask
10925 part of the instruction definition, or by the operand list. */
10928 validate_micromips_insn (const struct mips_opcode *opc)
10930 unsigned long match = opc->match;
10931 unsigned long mask = opc->mask;
10932 const char *p = opc->args;
10933 unsigned long insn_bits;
10934 unsigned long used_bits;
10935 unsigned long major;
10936 unsigned int length;
10940 if ((mask & match) != match)
10942 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10943 opc->name, opc->args);
10946 length = micromips_insn_length (opc);
10947 if (length != 2 && length != 4)
10949 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10950 "%s %s"), length, opc->name, opc->args);
10953 major = match >> (10 + 8 * (length - 2));
10954 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10955 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10957 as_bad (_("Internal error: bad microMIPS opcode "
10958 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10962 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10963 insn_bits = 1 << 4 * length;
10964 insn_bits <<= 4 * length;
10967 #define USE_BITS(field) \
10968 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10979 case 'A': USE_BITS (EXTLSB); break;
10980 case 'B': USE_BITS (INSMSB); break;
10981 case 'C': USE_BITS (EXTMSBD); break;
10982 case 'E': USE_BITS (EXTLSB); break;
10983 case 'F': USE_BITS (INSMSB); break;
10984 case 'G': USE_BITS (EXTMSBD); break;
10985 case 'H': USE_BITS (EXTMSBD); break;
10986 case 'i': USE_BITS (TARGET); break;
10987 case 'j': USE_BITS (EVAOFFSET); break;
10989 as_bad (_("Internal error: bad mips opcode "
10990 "(unknown extension operand type `%c%c'): %s %s"),
10991 e, c, opc->name, opc->args);
10999 case 'A': USE_BITS (IMMA); break;
11000 case 'B': USE_BITS (IMMB); break;
11001 case 'C': USE_BITS (IMMC); break;
11002 case 'D': USE_BITS (IMMD); break;
11003 case 'E': USE_BITS (IMME); break;
11004 case 'F': USE_BITS (IMMF); break;
11005 case 'G': USE_BITS (IMMG); break;
11006 case 'H': USE_BITS (IMMH); break;
11007 case 'I': USE_BITS (IMMI); break;
11008 case 'J': USE_BITS (IMMJ); break;
11009 case 'L': USE_BITS (IMML); break;
11010 case 'M': USE_BITS (IMMM); break;
11011 case 'N': USE_BITS (IMMN); break;
11012 case 'O': USE_BITS (IMMO); break;
11013 case 'P': USE_BITS (IMMP); break;
11014 case 'Q': USE_BITS (IMMQ); break;
11015 case 'U': USE_BITS (IMMU); break;
11016 case 'W': USE_BITS (IMMW); break;
11017 case 'X': USE_BITS (IMMX); break;
11018 case 'Y': USE_BITS (IMMY); break;
11021 case 'b': USE_BITS (MB); break;
11022 case 'c': USE_BITS (MC); break;
11023 case 'd': USE_BITS (MD); break;
11024 case 'e': USE_BITS (ME); break;
11025 case 'f': USE_BITS (MF); break;
11026 case 'g': USE_BITS (MG); break;
11027 case 'h': USE_BITS (MH); break;
11028 case 'j': USE_BITS (MJ); break;
11029 case 'l': USE_BITS (ML); break;
11030 case 'm': USE_BITS (MM); break;
11031 case 'n': USE_BITS (MN); break;
11032 case 'p': USE_BITS (MP); break;
11033 case 'q': USE_BITS (MQ); break;
11041 as_bad (_("Internal error: bad mips opcode "
11042 "(unknown extension operand type `%c%c'): %s %s"),
11043 e, c, opc->name, opc->args);
11047 case '.': USE_BITS (OFFSET10); break;
11048 case '1': USE_BITS (STYPE); break;
11049 case '2': USE_BITS (BP); break;
11050 case '3': USE_BITS (SA3); break;
11051 case '4': USE_BITS (SA4); break;
11052 case '5': USE_BITS (IMM8); break;
11053 case '6': USE_BITS (RS); break;
11054 case '7': USE_BITS (DSPACC); break;
11055 case '8': USE_BITS (WRDSP); break;
11056 case '0': USE_BITS (DSPSFT); break;
11057 case '<': USE_BITS (SHAMT); break;
11058 case '>': USE_BITS (SHAMT); break;
11059 case '@': USE_BITS (IMM10); break;
11060 case 'B': USE_BITS (CODE10); break;
11061 case 'C': USE_BITS (COPZ); break;
11062 case 'D': USE_BITS (FD); break;
11063 case 'E': USE_BITS (RT); break;
11064 case 'G': USE_BITS (RS); break;
11065 case 'H': USE_BITS (SEL); break;
11066 case 'K': USE_BITS (RS); break;
11067 case 'M': USE_BITS (CCC); break;
11068 case 'N': USE_BITS (BCC); break;
11069 case 'R': USE_BITS (FR); break;
11070 case 'S': USE_BITS (FS); break;
11071 case 'T': USE_BITS (FT); break;
11072 case 'V': USE_BITS (FS); break;
11073 case '\\': USE_BITS (3BITPOS); break;
11074 case '^': USE_BITS (RD); break;
11075 case 'a': USE_BITS (TARGET); break;
11076 case 'b': USE_BITS (RS); break;
11077 case 'c': USE_BITS (CODE); break;
11078 case 'd': USE_BITS (RD); break;
11079 case 'h': USE_BITS (PREFX); break;
11080 case 'i': USE_BITS (IMMEDIATE); break;
11081 case 'j': USE_BITS (DELTA); break;
11082 case 'k': USE_BITS (CACHE); break;
11083 case 'n': USE_BITS (RT); break;
11084 case 'o': USE_BITS (DELTA); break;
11085 case 'p': USE_BITS (DELTA); break;
11086 case 'q': USE_BITS (CODE2); break;
11087 case 'r': USE_BITS (RS); break;
11088 case 's': USE_BITS (RS); break;
11089 case 't': USE_BITS (RT); break;
11090 case 'u': USE_BITS (IMMEDIATE); break;
11091 case 'v': USE_BITS (RS); break;
11092 case 'w': USE_BITS (RT); break;
11093 case 'y': USE_BITS (RS3); break;
11095 case '|': USE_BITS (TRAP); break;
11096 case '~': USE_BITS (OFFSET12); break;
11098 as_bad (_("Internal error: bad microMIPS opcode "
11099 "(unknown operand type `%c'): %s %s"),
11100 c, opc->name, opc->args);
11104 if (used_bits != insn_bits)
11106 if (~used_bits & insn_bits)
11107 as_bad (_("Internal error: bad microMIPS opcode "
11108 "(bits 0x%lx undefined): %s %s"),
11109 ~used_bits & insn_bits, opc->name, opc->args);
11110 if (used_bits & ~insn_bits)
11111 as_bad (_("Internal error: bad microMIPS opcode "
11112 "(bits 0x%lx defined): %s %s"),
11113 used_bits & ~insn_bits, opc->name, opc->args);
11119 /* UDI immediates. */
11120 struct mips_immed {
11122 unsigned int shift;
11123 unsigned long mask;
11127 static const struct mips_immed mips_immed[] = {
11128 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11129 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11130 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11131 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11135 /* Check whether an odd floating-point register is allowed. */
11137 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11139 const char *s = insn->name;
11141 if (insn->pinfo == INSN_MACRO)
11142 /* Let a macro pass, we'll catch it later when it is expanded. */
11145 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11147 /* Allow odd registers for single-precision ops. */
11148 switch (insn->pinfo & (FP_S | FP_D))
11152 return 1; /* both single precision - ok */
11154 return 0; /* both double precision - fail */
11159 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11160 s = strchr (insn->name, '.');
11162 s = s != NULL ? strchr (s + 1, '.') : NULL;
11163 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11166 /* Single-precision coprocessor loads and moves are OK too. */
11167 if ((insn->pinfo & FP_S)
11168 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11169 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11175 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11176 taking bits from BIT up. */
11178 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11180 return (ep->X_op == O_constant
11181 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11182 && ep->X_add_number >= min << bit
11183 && ep->X_add_number < max << bit);
11186 /* Assemble an instruction into its binary format. If the instruction
11187 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11188 associated with "I", "+I" and "A" operands respectively. Otherwise
11189 store the value of the relocatable field (if any) in offset_expr.
11190 In both cases set offset_reloc to the relocation operators applied
11194 mips_ip (char *str, struct mips_cl_insn *ip)
11196 bfd_boolean wrong_delay_slot_insns = FALSE;
11197 bfd_boolean need_delay_slot_ok = TRUE;
11198 struct mips_opcode *firstinsn = NULL;
11199 const struct mips_opcode *past;
11200 struct hash_control *hash;
11204 struct mips_opcode *insn;
11206 unsigned int regno, regno2;
11207 unsigned int lastregno;
11208 unsigned int destregno = 0;
11209 unsigned int lastpos = 0;
11210 unsigned int limlo, limhi;
11213 offsetT min_range, max_range;
11217 unsigned int rtype;
11223 if (mips_opts.micromips)
11225 hash = micromips_op_hash;
11226 past = µmips_opcodes[bfd_micromips_num_opcodes];
11231 past = &mips_opcodes[NUMOPCODES];
11233 forced_insn_length = 0;
11236 /* We first try to match an instruction up to a space or to the end. */
11237 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11240 /* Make a copy of the instruction so that we can fiddle with it. */
11241 name = alloca (end + 1);
11242 memcpy (name, str, end);
11247 insn = (struct mips_opcode *) hash_find (hash, name);
11249 if (insn != NULL || !mips_opts.micromips)
11251 if (forced_insn_length)
11254 /* See if there's an instruction size override suffix,
11255 either `16' or `32', at the end of the mnemonic proper,
11256 that defines the operation, i.e. before the first `.'
11257 character if any. Strip it and retry. */
11258 dot = strchr (name, '.');
11259 opend = dot != NULL ? dot - name : end;
11262 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11263 forced_insn_length = 2;
11264 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11265 forced_insn_length = 4;
11268 memcpy (name + opend - 2, name + opend, end - opend + 1);
11272 insn_error = _("Unrecognized opcode");
11276 /* For microMIPS instructions placed in a fixed-length branch delay slot
11277 we make up to two passes over the relevant fragment of the opcode
11278 table. First we try instructions that meet the delay slot's length
11279 requirement. If none matched, then we retry with the remaining ones
11280 and if one matches, then we use it and then issue an appropriate
11281 warning later on. */
11282 argsStart = s = str + end;
11285 bfd_boolean delay_slot_ok;
11286 bfd_boolean size_ok;
11289 gas_assert (strcmp (insn->name, name) == 0);
11291 ok = is_opcode_valid (insn);
11292 size_ok = is_size_valid (insn);
11293 delay_slot_ok = is_delay_slot_valid (insn);
11294 if (!delay_slot_ok && !wrong_delay_slot_insns)
11297 wrong_delay_slot_insns = TRUE;
11299 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11301 static char buf[256];
11303 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11308 if (wrong_delay_slot_insns && need_delay_slot_ok)
11310 gas_assert (firstinsn);
11311 need_delay_slot_ok = FALSE;
11321 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11322 mips_cpu_info_from_arch (mips_opts.arch)->name,
11323 mips_cpu_info_from_isa (mips_opts.isa)->name);
11324 else if (mips_opts.insn32)
11325 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11327 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11328 8 * forced_insn_length);
11334 imm_expr.X_op = O_absent;
11335 imm2_expr.X_op = O_absent;
11336 offset_expr.X_op = O_absent;
11337 offset_reloc[0] = BFD_RELOC_UNUSED;
11338 offset_reloc[1] = BFD_RELOC_UNUSED;
11339 offset_reloc[2] = BFD_RELOC_UNUSED;
11341 create_insn (ip, insn);
11344 lastregno = 0xffffffff;
11345 for (args = insn->args;; ++args)
11349 s += strspn (s, " \t");
11353 case '\0': /* end of args */
11359 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11360 code) or 14 (for microMIPS code). */
11361 my_getExpression (&imm_expr, s);
11362 check_absolute_expr (ip, &imm_expr);
11363 if ((unsigned long) imm_expr.X_add_number != 1
11364 && (unsigned long) imm_expr.X_add_number != 3)
11366 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11367 (unsigned long) imm_expr.X_add_number);
11369 INSERT_OPERAND (mips_opts.micromips,
11370 BP, *ip, imm_expr.X_add_number);
11371 imm_expr.X_op = O_absent;
11376 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11377 code) or 13 (for microMIPS code). */
11379 unsigned long mask = (mips_opts.micromips
11380 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11382 my_getExpression (&imm_expr, s);
11383 check_absolute_expr (ip, &imm_expr);
11384 if ((unsigned long) imm_expr.X_add_number > mask)
11385 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11386 mask, (unsigned long) imm_expr.X_add_number);
11387 INSERT_OPERAND (mips_opts.micromips,
11388 SA3, *ip, imm_expr.X_add_number);
11389 imm_expr.X_op = O_absent;
11395 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11396 code) or 12 (for microMIPS code). */
11398 unsigned long mask = (mips_opts.micromips
11399 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11401 my_getExpression (&imm_expr, s);
11402 check_absolute_expr (ip, &imm_expr);
11403 if ((unsigned long) imm_expr.X_add_number > mask)
11404 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11405 mask, (unsigned long) imm_expr.X_add_number);
11406 INSERT_OPERAND (mips_opts.micromips,
11407 SA4, *ip, imm_expr.X_add_number);
11408 imm_expr.X_op = O_absent;
11414 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11415 code) or 13 (for microMIPS code). */
11417 unsigned long mask = (mips_opts.micromips
11418 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11420 my_getExpression (&imm_expr, s);
11421 check_absolute_expr (ip, &imm_expr);
11422 if ((unsigned long) imm_expr.X_add_number > mask)
11423 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11424 mask, (unsigned long) imm_expr.X_add_number);
11425 INSERT_OPERAND (mips_opts.micromips,
11426 IMM8, *ip, imm_expr.X_add_number);
11427 imm_expr.X_op = O_absent;
11433 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11434 code) or 16 (for microMIPS code). */
11436 unsigned long mask = (mips_opts.micromips
11437 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11439 my_getExpression (&imm_expr, s);
11440 check_absolute_expr (ip, &imm_expr);
11441 if ((unsigned long) imm_expr.X_add_number > mask)
11442 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11443 mask, (unsigned long) imm_expr.X_add_number);
11444 INSERT_OPERAND (mips_opts.micromips,
11445 RS, *ip, imm_expr.X_add_number);
11446 imm_expr.X_op = O_absent;
11452 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11453 or 14 (for microMIPS code). */
11454 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11455 && s[3] >= '0' && s[3] <= '3')
11457 regno = s[3] - '0';
11459 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11463 as_bad (_("Invalid dsp acc register"));
11467 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11468 code) or 14 (for microMIPS code). */
11470 unsigned long mask = (mips_opts.micromips
11471 ? MICROMIPSOP_MASK_WRDSP
11474 my_getExpression (&imm_expr, s);
11475 check_absolute_expr (ip, &imm_expr);
11476 if ((unsigned long) imm_expr.X_add_number > mask)
11477 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11478 mask, (unsigned long) imm_expr.X_add_number);
11479 INSERT_OPERAND (mips_opts.micromips,
11480 WRDSP, *ip, imm_expr.X_add_number);
11481 imm_expr.X_op = O_absent;
11486 case '9': /* Four DSP accumulators in bits 21,22. */
11487 gas_assert (!mips_opts.micromips);
11488 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11489 && s[3] >= '0' && s[3] <= '3')
11491 regno = s[3] - '0';
11493 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11497 as_bad (_("Invalid dsp acc register"));
11501 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11502 code) or 16 (for microMIPS code). */
11504 long mask = (mips_opts.micromips
11505 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11507 my_getExpression (&imm_expr, s);
11508 check_absolute_expr (ip, &imm_expr);
11509 min_range = -((mask + 1) >> 1);
11510 max_range = ((mask + 1) >> 1) - 1;
11511 if (imm_expr.X_add_number < min_range
11512 || imm_expr.X_add_number > max_range)
11513 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11514 (long) min_range, (long) max_range,
11515 (long) imm_expr.X_add_number);
11516 INSERT_OPERAND (mips_opts.micromips,
11517 DSPSFT, *ip, imm_expr.X_add_number);
11518 imm_expr.X_op = O_absent;
11523 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11524 gas_assert (!mips_opts.micromips);
11525 my_getExpression (&imm_expr, s);
11526 check_absolute_expr (ip, &imm_expr);
11527 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11529 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11531 (unsigned long) imm_expr.X_add_number);
11533 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11534 imm_expr.X_op = O_absent;
11538 case ':': /* DSP 7-bit signed immediate in bit 19. */
11539 gas_assert (!mips_opts.micromips);
11540 my_getExpression (&imm_expr, s);
11541 check_absolute_expr (ip, &imm_expr);
11542 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11543 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11544 if (imm_expr.X_add_number < min_range ||
11545 imm_expr.X_add_number > max_range)
11547 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11548 (long) min_range, (long) max_range,
11549 (long) imm_expr.X_add_number);
11551 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11552 imm_expr.X_op = O_absent;
11556 case '@': /* DSP 10-bit signed immediate in bit 16. */
11558 long mask = (mips_opts.micromips
11559 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11561 my_getExpression (&imm_expr, s);
11562 check_absolute_expr (ip, &imm_expr);
11563 min_range = -((mask + 1) >> 1);
11564 max_range = ((mask + 1) >> 1) - 1;
11565 if (imm_expr.X_add_number < min_range
11566 || imm_expr.X_add_number > max_range)
11567 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11568 (long) min_range, (long) max_range,
11569 (long) imm_expr.X_add_number);
11570 INSERT_OPERAND (mips_opts.micromips,
11571 IMM10, *ip, imm_expr.X_add_number);
11572 imm_expr.X_op = O_absent;
11577 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11578 gas_assert (mips_opts.micromips);
11579 my_getExpression (&imm_expr, s);
11580 check_absolute_expr (ip, &imm_expr);
11581 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11582 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11583 MICROMIPSOP_MASK_RD,
11584 (unsigned long) imm_expr.X_add_number);
11585 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11586 imm_expr.X_op = O_absent;
11590 case '!': /* MT usermode flag bit. */
11591 gas_assert (!mips_opts.micromips);
11592 my_getExpression (&imm_expr, s);
11593 check_absolute_expr (ip, &imm_expr);
11594 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11595 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11596 (unsigned long) imm_expr.X_add_number);
11597 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11598 imm_expr.X_op = O_absent;
11602 case '$': /* MT load high flag bit. */
11603 gas_assert (!mips_opts.micromips);
11604 my_getExpression (&imm_expr, s);
11605 check_absolute_expr (ip, &imm_expr);
11606 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11607 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11608 (unsigned long) imm_expr.X_add_number);
11609 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11610 imm_expr.X_op = O_absent;
11614 case '*': /* Four DSP accumulators in bits 18,19. */
11615 gas_assert (!mips_opts.micromips);
11616 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11617 s[3] >= '0' && s[3] <= '3')
11619 regno = s[3] - '0';
11621 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11625 as_bad (_("Invalid dsp/smartmips acc register"));
11628 case '&': /* Four DSP accumulators in bits 13,14. */
11629 gas_assert (!mips_opts.micromips);
11630 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11631 s[3] >= '0' && s[3] <= '3')
11633 regno = s[3] - '0';
11635 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11639 as_bad (_("Invalid dsp/smartmips acc register"));
11642 case '\\': /* 3-bit bit position. */
11644 unsigned long mask = (mips_opts.micromips
11645 ? MICROMIPSOP_MASK_3BITPOS
11646 : OP_MASK_3BITPOS);
11648 my_getExpression (&imm_expr, s);
11649 check_absolute_expr (ip, &imm_expr);
11650 if ((unsigned long) imm_expr.X_add_number > mask)
11651 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11653 mask, (unsigned long) imm_expr.X_add_number);
11654 INSERT_OPERAND (mips_opts.micromips,
11655 3BITPOS, *ip, imm_expr.X_add_number);
11656 imm_expr.X_op = O_absent;
11670 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11674 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11678 gas_assert (!mips_opts.micromips);
11679 INSERT_OPERAND (0, FT, *ip, lastregno);
11683 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11689 /* Handle optional base register.
11690 Either the base register is omitted or
11691 we must have a left paren. */
11692 /* This is dependent on the next operand specifier
11693 is a base register specification. */
11694 gas_assert (args[1] == 'b'
11695 || (mips_opts.micromips
11697 && (args[2] == 'l' || args[2] == 'n'
11698 || args[2] == 's' || args[2] == 'a')));
11699 if (*s == '\0' && args[1] == 'b')
11701 /* Fall through. */
11703 case ')': /* These must match exactly. */
11708 case '+': /* Opcode extension character. */
11711 case '1': /* UDI immediates. */
11715 gas_assert (!mips_opts.micromips);
11717 const struct mips_immed *imm = mips_immed;
11719 while (imm->type && imm->type != *args)
11723 my_getExpression (&imm_expr, s);
11724 check_absolute_expr (ip, &imm_expr);
11725 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11727 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11728 imm->desc ? imm->desc : ip->insn_mo->name,
11729 (unsigned long) imm_expr.X_add_number,
11730 (unsigned long) imm_expr.X_add_number);
11731 imm_expr.X_add_number &= imm->mask;
11733 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11735 imm_expr.X_op = O_absent;
11740 case 'J': /* 10-bit hypcall code. */
11741 gas_assert (!mips_opts.micromips);
11743 unsigned long mask = OP_MASK_CODE10;
11745 my_getExpression (&imm_expr, s);
11746 check_absolute_expr (ip, &imm_expr);
11747 if ((unsigned long) imm_expr.X_add_number > mask)
11748 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11750 mask, (unsigned long) imm_expr.X_add_number);
11751 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11752 imm_expr.X_op = O_absent;
11757 case 'A': /* ins/ext position, becomes LSB. */
11766 my_getExpression (&imm_expr, s);
11767 check_absolute_expr (ip, &imm_expr);
11768 if ((unsigned long) imm_expr.X_add_number < limlo
11769 || (unsigned long) imm_expr.X_add_number > limhi)
11771 as_bad (_("Improper position (%lu)"),
11772 (unsigned long) imm_expr.X_add_number);
11773 imm_expr.X_add_number = limlo;
11775 lastpos = imm_expr.X_add_number;
11776 INSERT_OPERAND (mips_opts.micromips,
11777 EXTLSB, *ip, imm_expr.X_add_number);
11778 imm_expr.X_op = O_absent;
11782 case 'B': /* ins size, becomes MSB. */
11791 my_getExpression (&imm_expr, s);
11792 check_absolute_expr (ip, &imm_expr);
11793 /* Check for negative input so that small negative numbers
11794 will not succeed incorrectly. The checks against
11795 (pos+size) transitively check "size" itself,
11796 assuming that "pos" is reasonable. */
11797 if ((long) imm_expr.X_add_number < 0
11798 || ((unsigned long) imm_expr.X_add_number
11800 || ((unsigned long) imm_expr.X_add_number
11801 + lastpos) > limhi)
11803 as_bad (_("Improper insert size (%lu, position %lu)"),
11804 (unsigned long) imm_expr.X_add_number,
11805 (unsigned long) lastpos);
11806 imm_expr.X_add_number = limlo - lastpos;
11808 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11809 lastpos + imm_expr.X_add_number - 1);
11810 imm_expr.X_op = O_absent;
11814 case 'C': /* ext size, becomes MSBD. */
11830 my_getExpression (&imm_expr, s);
11831 check_absolute_expr (ip, &imm_expr);
11832 /* The checks against (pos+size) don't transitively check
11833 "size" itself, assuming that "pos" is reasonable.
11834 We also need to check the lower bound of "size". */
11835 if ((long) imm_expr.X_add_number < sizelo
11836 || ((unsigned long) imm_expr.X_add_number
11838 || ((unsigned long) imm_expr.X_add_number
11839 + lastpos) > limhi)
11841 as_bad (_("Improper extract size (%lu, position %lu)"),
11842 (unsigned long) imm_expr.X_add_number,
11843 (unsigned long) lastpos);
11844 imm_expr.X_add_number = limlo - lastpos;
11846 INSERT_OPERAND (mips_opts.micromips,
11847 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11848 imm_expr.X_op = O_absent;
11853 /* "+I" is like "I", except that imm2_expr is used. */
11854 my_getExpression (&imm2_expr, s);
11855 if (imm2_expr.X_op != O_big
11856 && imm2_expr.X_op != O_constant)
11857 insn_error = _("absolute expression required");
11858 if (HAVE_32BIT_GPRS)
11859 normalize_constant_expr (&imm2_expr);
11863 case 't': /* Coprocessor register number. */
11864 gas_assert (!mips_opts.micromips);
11865 if (s[0] == '$' && ISDIGIT (s[1]))
11875 while (ISDIGIT (*s));
11877 as_bad (_("Invalid register number (%d)"), regno);
11880 INSERT_OPERAND (0, RT, *ip, regno);
11885 as_bad (_("Invalid coprocessor 0 register number"));
11889 /* bbit[01] and bbit[01]32 bit index. Give error if index
11890 is not in the valid range. */
11891 gas_assert (!mips_opts.micromips);
11892 my_getExpression (&imm_expr, s);
11893 check_absolute_expr (ip, &imm_expr);
11894 if ((unsigned) imm_expr.X_add_number > 31)
11896 as_bad (_("Improper bit index (%lu)"),
11897 (unsigned long) imm_expr.X_add_number);
11898 imm_expr.X_add_number = 0;
11900 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11901 imm_expr.X_op = O_absent;
11906 /* bbit[01] bit index when bbit is used but we generate
11907 bbit[01]32 because the index is over 32. Move to the
11908 next candidate if index is not in the valid range. */
11909 gas_assert (!mips_opts.micromips);
11910 my_getExpression (&imm_expr, s);
11911 check_absolute_expr (ip, &imm_expr);
11912 if ((unsigned) imm_expr.X_add_number < 32
11913 || (unsigned) imm_expr.X_add_number > 63)
11915 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11916 imm_expr.X_op = O_absent;
11921 /* cins, cins32, exts and exts32 position field. Give error
11922 if it's not in the valid range. */
11923 gas_assert (!mips_opts.micromips);
11924 my_getExpression (&imm_expr, s);
11925 check_absolute_expr (ip, &imm_expr);
11926 if ((unsigned) imm_expr.X_add_number > 31)
11928 as_bad (_("Improper position (%lu)"),
11929 (unsigned long) imm_expr.X_add_number);
11930 imm_expr.X_add_number = 0;
11932 lastpos = imm_expr.X_add_number;
11933 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11934 imm_expr.X_op = O_absent;
11939 /* cins, cins32, exts and exts32 position field. Move to
11940 the next candidate if it's not in the valid range. */
11941 gas_assert (!mips_opts.micromips);
11942 my_getExpression (&imm_expr, s);
11943 check_absolute_expr (ip, &imm_expr);
11944 if ((unsigned) imm_expr.X_add_number < 32
11945 || (unsigned) imm_expr.X_add_number > 63)
11947 lastpos = imm_expr.X_add_number;
11948 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11949 imm_expr.X_op = O_absent;
11954 /* cins32 and exts32 length-minus-one field. */
11955 gas_assert (!mips_opts.micromips);
11956 my_getExpression (&imm_expr, s);
11957 check_absolute_expr (ip, &imm_expr);
11958 if ((unsigned long) imm_expr.X_add_number > 31
11959 || (unsigned long) imm_expr.X_add_number + lastpos > 31)
11961 as_bad (_("Improper size (%lu)"),
11962 (unsigned long) imm_expr.X_add_number);
11963 imm_expr.X_add_number = 0;
11965 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11966 imm_expr.X_op = O_absent;
11971 /* cins/exts length-minus-one field. */
11972 gas_assert (!mips_opts.micromips);
11973 my_getExpression (&imm_expr, s);
11974 check_absolute_expr (ip, &imm_expr);
11975 if ((unsigned long) imm_expr.X_add_number > 31
11976 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11978 as_bad (_("Improper size (%lu)"),
11979 (unsigned long) imm_expr.X_add_number);
11980 imm_expr.X_add_number = 0;
11982 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11983 imm_expr.X_op = O_absent;
11988 /* seqi/snei immediate field. */
11989 gas_assert (!mips_opts.micromips);
11990 my_getExpression (&imm_expr, s);
11991 check_absolute_expr (ip, &imm_expr);
11992 if ((long) imm_expr.X_add_number < -512
11993 || (long) imm_expr.X_add_number >= 512)
11995 as_bad (_("Improper immediate (%ld)"),
11996 (long) imm_expr.X_add_number);
11997 imm_expr.X_add_number = 0;
11999 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
12000 imm_expr.X_op = O_absent;
12004 case 'a': /* 8-bit signed offset in bit 6 */
12005 gas_assert (!mips_opts.micromips);
12006 my_getExpression (&imm_expr, s);
12007 check_absolute_expr (ip, &imm_expr);
12008 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
12009 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
12010 if (imm_expr.X_add_number < min_range
12011 || imm_expr.X_add_number > max_range)
12013 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12014 (long) min_range, (long) max_range,
12015 (long) imm_expr.X_add_number);
12017 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
12018 imm_expr.X_op = O_absent;
12022 case 'b': /* 8-bit signed offset in bit 3 */
12023 gas_assert (!mips_opts.micromips);
12024 my_getExpression (&imm_expr, s);
12025 check_absolute_expr (ip, &imm_expr);
12026 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12027 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12028 if (imm_expr.X_add_number < min_range
12029 || imm_expr.X_add_number > max_range)
12031 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12032 (long) min_range, (long) max_range,
12033 (long) imm_expr.X_add_number);
12035 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12036 imm_expr.X_op = O_absent;
12040 case 'c': /* 9-bit signed offset in bit 6 */
12041 gas_assert (!mips_opts.micromips);
12042 my_getExpression (&imm_expr, s);
12043 check_absolute_expr (ip, &imm_expr);
12044 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12045 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12046 /* We check the offset range before adjusted. */
12049 if (imm_expr.X_add_number < min_range
12050 || imm_expr.X_add_number > max_range)
12052 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12053 (long) min_range, (long) max_range,
12054 (long) imm_expr.X_add_number);
12056 if (imm_expr.X_add_number & 0xf)
12058 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12059 (long) imm_expr.X_add_number);
12061 /* Right shift 4 bits to adjust the offset operand. */
12062 INSERT_OPERAND (0, OFFSET_C, *ip,
12063 imm_expr.X_add_number >> 4);
12064 imm_expr.X_op = O_absent;
12069 gas_assert (!mips_opts.micromips);
12070 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12072 if (regno == AT && mips_opts.at)
12074 if (mips_opts.at == ATREG)
12075 as_warn (_("used $at without \".set noat\""));
12077 as_warn (_("used $%u with \".set at=$%u\""),
12078 regno, mips_opts.at);
12080 INSERT_OPERAND (0, RZ, *ip, regno);
12084 gas_assert (!mips_opts.micromips);
12085 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12087 INSERT_OPERAND (0, FZ, *ip, regno);
12097 bfd_reloc_code_real_type r[3];
12099 /* Check whether there is only a single bracketed expression
12100 left. If so, it must be the base register and the
12101 constant must be zero. */
12102 if (*s == '(' && strchr (s + 1, '(') == 0)
12105 /* If this value won't fit into the offset, then go find
12106 a macro that will generate a 16- or 32-bit offset code
12108 i = my_getSmallExpression (&imm_expr, r, s);
12109 if ((i == 0 && (imm_expr.X_op != O_constant
12110 || imm_expr.X_add_number >= 1 << shift
12111 || imm_expr.X_add_number < -1 << shift))
12114 imm_expr.X_op = O_absent;
12117 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12118 imm_expr.X_add_number);
12119 imm_expr.X_op = O_absent;
12125 as_bad (_("Internal error: bad %s opcode "
12126 "(unknown extension operand type `+%c'): %s %s"),
12127 mips_opts.micromips ? "microMIPS" : "MIPS",
12128 *args, insn->name, insn->args);
12129 /* Further processing is fruitless. */
12134 case '.': /* 10-bit offset. */
12135 gas_assert (mips_opts.micromips);
12136 case '~': /* 12-bit offset. */
12138 int shift = *args == '.' ? 9 : 11;
12140 bfd_reloc_code_real_type r[3];
12142 /* Check whether there is only a single bracketed expression
12143 left. If so, it must be the base register and the
12144 constant must be zero. */
12145 if (*s == '(' && strchr (s + 1, '(') == 0)
12148 /* If this value won't fit into the offset, then go find
12149 a macro that will generate a 16- or 32-bit offset code
12151 i = my_getSmallExpression (&imm_expr, r, s);
12152 if ((i == 0 && (imm_expr.X_op != O_constant
12153 || imm_expr.X_add_number >= 1 << shift
12154 || imm_expr.X_add_number < -1 << shift))
12157 imm_expr.X_op = O_absent;
12161 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12163 INSERT_OPERAND (mips_opts.micromips,
12164 OFFSET12, *ip, imm_expr.X_add_number);
12165 imm_expr.X_op = O_absent;
12170 case '<': /* must be at least one digit */
12172 * According to the manual, if the shift amount is greater
12173 * than 31 or less than 0, then the shift amount should be
12174 * mod 32. In reality the mips assembler issues an error.
12175 * We issue a warning and mask out all but the low 5 bits.
12177 my_getExpression (&imm_expr, s);
12178 check_absolute_expr (ip, &imm_expr);
12179 if ((unsigned long) imm_expr.X_add_number > 31)
12180 as_warn (_("Improper shift amount (%lu)"),
12181 (unsigned long) imm_expr.X_add_number);
12182 INSERT_OPERAND (mips_opts.micromips,
12183 SHAMT, *ip, imm_expr.X_add_number);
12184 imm_expr.X_op = O_absent;
12188 case '>': /* shift amount minus 32 */
12189 my_getExpression (&imm_expr, s);
12190 check_absolute_expr (ip, &imm_expr);
12191 if ((unsigned long) imm_expr.X_add_number < 32
12192 || (unsigned long) imm_expr.X_add_number > 63)
12194 INSERT_OPERAND (mips_opts.micromips,
12195 SHAMT, *ip, imm_expr.X_add_number - 32);
12196 imm_expr.X_op = O_absent;
12200 case 'k': /* CACHE code. */
12201 case 'h': /* PREFX code. */
12202 case '1': /* SYNC type. */
12203 my_getExpression (&imm_expr, s);
12204 check_absolute_expr (ip, &imm_expr);
12205 if ((unsigned long) imm_expr.X_add_number > 31)
12206 as_warn (_("Invalid value for `%s' (%lu)"),
12208 (unsigned long) imm_expr.X_add_number);
12212 if (mips_fix_cn63xxp1
12213 && !mips_opts.micromips
12214 && strcmp ("pref", insn->name) == 0)
12215 switch (imm_expr.X_add_number)
12224 case 31: /* These are ok. */
12227 default: /* The rest must be changed to 28. */
12228 imm_expr.X_add_number = 28;
12231 INSERT_OPERAND (mips_opts.micromips,
12232 CACHE, *ip, imm_expr.X_add_number);
12235 INSERT_OPERAND (mips_opts.micromips,
12236 PREFX, *ip, imm_expr.X_add_number);
12239 INSERT_OPERAND (mips_opts.micromips,
12240 STYPE, *ip, imm_expr.X_add_number);
12243 imm_expr.X_op = O_absent;
12247 case 'c': /* BREAK code. */
12249 unsigned long mask = (mips_opts.micromips
12250 ? MICROMIPSOP_MASK_CODE
12253 my_getExpression (&imm_expr, s);
12254 check_absolute_expr (ip, &imm_expr);
12255 if ((unsigned long) imm_expr.X_add_number > mask)
12256 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12258 mask, (unsigned long) imm_expr.X_add_number);
12259 INSERT_OPERAND (mips_opts.micromips,
12260 CODE, *ip, imm_expr.X_add_number);
12261 imm_expr.X_op = O_absent;
12266 case 'q': /* Lower BREAK code. */
12268 unsigned long mask = (mips_opts.micromips
12269 ? MICROMIPSOP_MASK_CODE2
12272 my_getExpression (&imm_expr, s);
12273 check_absolute_expr (ip, &imm_expr);
12274 if ((unsigned long) imm_expr.X_add_number > mask)
12275 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12277 mask, (unsigned long) imm_expr.X_add_number);
12278 INSERT_OPERAND (mips_opts.micromips,
12279 CODE2, *ip, imm_expr.X_add_number);
12280 imm_expr.X_op = O_absent;
12285 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12287 unsigned long mask = (mips_opts.micromips
12288 ? MICROMIPSOP_MASK_CODE10
12291 my_getExpression (&imm_expr, s);
12292 check_absolute_expr (ip, &imm_expr);
12293 if ((unsigned long) imm_expr.X_add_number > mask)
12294 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12296 mask, (unsigned long) imm_expr.X_add_number);
12297 if (mips_opts.micromips)
12298 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12300 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12301 imm_expr.X_op = O_absent;
12306 case 'C': /* 25- or 23-bit coprocessor code. */
12308 unsigned long mask = (mips_opts.micromips
12309 ? MICROMIPSOP_MASK_COPZ
12312 my_getExpression (&imm_expr, s);
12313 check_absolute_expr (ip, &imm_expr);
12314 if ((unsigned long) imm_expr.X_add_number > mask)
12315 as_warn (_("Coproccesor code > %u bits (%lu)"),
12316 mips_opts.micromips ? 23U : 25U,
12317 (unsigned long) imm_expr.X_add_number);
12318 INSERT_OPERAND (mips_opts.micromips,
12319 COPZ, *ip, imm_expr.X_add_number);
12320 imm_expr.X_op = O_absent;
12325 case 'J': /* 19-bit WAIT code. */
12326 gas_assert (!mips_opts.micromips);
12327 my_getExpression (&imm_expr, s);
12328 check_absolute_expr (ip, &imm_expr);
12329 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12331 as_warn (_("Illegal 19-bit code (%lu)"),
12332 (unsigned long) imm_expr.X_add_number);
12333 imm_expr.X_add_number &= OP_MASK_CODE19;
12335 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12336 imm_expr.X_op = O_absent;
12340 case 'P': /* Performance register. */
12341 gas_assert (!mips_opts.micromips);
12342 my_getExpression (&imm_expr, s);
12343 check_absolute_expr (ip, &imm_expr);
12344 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12345 as_warn (_("Invalid performance register (%lu)"),
12346 (unsigned long) imm_expr.X_add_number);
12347 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12348 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12349 as_warn (_("Invalid performance register (%lu)"),
12350 (unsigned long) imm_expr.X_add_number);
12351 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12352 imm_expr.X_op = O_absent;
12356 case 'G': /* Coprocessor destination register. */
12358 unsigned long opcode = ip->insn_opcode;
12359 unsigned long mask;
12360 unsigned int types;
12363 if (mips_opts.micromips)
12365 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12366 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12367 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12371 case 0x000000fc: /* mfc0 */
12372 case 0x000002fc: /* mtc0 */
12373 case 0x580000fc: /* dmfc0 */
12374 case 0x580002fc: /* dmtc0 */
12384 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12385 cop0 = opcode == OP_OP_COP0;
12387 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12388 ok = reg_lookup (&s, types, ®no);
12389 if (mips_opts.micromips)
12390 INSERT_OPERAND (1, RS, *ip, regno);
12392 INSERT_OPERAND (0, RD, *ip, regno);
12401 case 'y': /* ALNV.PS source register. */
12402 gas_assert (mips_opts.micromips);
12404 case 'x': /* Ignore register name. */
12405 case 'U': /* Destination register (CLO/CLZ). */
12406 case 'g': /* Coprocessor destination register. */
12407 gas_assert (!mips_opts.micromips);
12408 case 'b': /* Base register. */
12409 case 'd': /* Destination register. */
12410 case 's': /* Source register. */
12411 case 't': /* Target register. */
12412 case 'r': /* Both target and source. */
12413 case 'v': /* Both dest and source. */
12414 case 'w': /* Both dest and target. */
12415 case 'E': /* Coprocessor target register. */
12416 case 'K': /* RDHWR destination register. */
12417 case 'z': /* Must be zero register. */
12420 if (*args == 'E' || *args == 'K')
12421 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12424 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12425 if (regno == AT && mips_opts.at)
12427 if (mips_opts.at == ATREG)
12428 as_warn (_("Used $at without \".set noat\""));
12430 as_warn (_("Used $%u with \".set at=$%u\""),
12431 regno, mips_opts.at);
12441 if (c == 'r' || c == 'v' || c == 'w')
12448 /* 'z' only matches $0. */
12449 if (c == 'z' && regno != 0)
12452 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12454 if (regno == lastregno)
12457 = _("Source and destination must be different");
12460 if (regno == 31 && lastregno == 0xffffffff)
12463 = _("A destination register must be supplied");
12467 /* Now that we have assembled one operand, we use the args
12468 string to figure out where it goes in the instruction. */
12475 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12479 if (mips_opts.micromips)
12480 INSERT_OPERAND (1, RS, *ip, regno);
12482 INSERT_OPERAND (0, RD, *ip, regno);
12487 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12491 gas_assert (!mips_opts.micromips);
12492 INSERT_OPERAND (0, RD, *ip, regno);
12493 INSERT_OPERAND (0, RT, *ip, regno);
12499 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12503 gas_assert (mips_opts.micromips);
12504 INSERT_OPERAND (1, RS3, *ip, regno);
12508 /* This case exists because on the r3000 trunc
12509 expands into a macro which requires a gp
12510 register. On the r6000 or r4000 it is
12511 assembled into a single instruction which
12512 ignores the register. Thus the insn version
12513 is MIPS_ISA2 and uses 'x', and the macro
12514 version is MIPS_ISA1 and uses 't'. */
12518 /* This case is for the div instruction, which
12519 acts differently if the destination argument
12520 is $0. This only matches $0, and is checked
12521 outside the switch. */
12531 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12535 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12540 case 'O': /* MDMX alignment immediate constant. */
12541 gas_assert (!mips_opts.micromips);
12542 my_getExpression (&imm_expr, s);
12543 check_absolute_expr (ip, &imm_expr);
12544 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12545 as_warn (_("Improper align amount (%ld), using low bits"),
12546 (long) imm_expr.X_add_number);
12547 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12548 imm_expr.X_op = O_absent;
12552 case 'Q': /* MDMX vector, element sel, or const. */
12555 /* MDMX Immediate. */
12556 gas_assert (!mips_opts.micromips);
12557 my_getExpression (&imm_expr, s);
12558 check_absolute_expr (ip, &imm_expr);
12559 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12560 as_warn (_("Invalid MDMX Immediate (%ld)"),
12561 (long) imm_expr.X_add_number);
12562 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12563 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12564 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12566 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12567 imm_expr.X_op = O_absent;
12571 /* Not MDMX Immediate. Fall through. */
12572 case 'X': /* MDMX destination register. */
12573 case 'Y': /* MDMX source register. */
12574 case 'Z': /* MDMX target register. */
12575 is_mdmx = !(insn->membership & INSN_5400);
12577 gas_assert (!mips_opts.micromips);
12578 case 'D': /* Floating point destination register. */
12579 case 'S': /* Floating point source register. */
12580 case 'T': /* Floating point target register. */
12581 case 'R': /* Floating point source register. */
12585 || ((mips_opts.ase & ASE_MDMX)
12586 && (ip->insn_mo->pinfo & FP_D)
12587 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12588 | INSN_COPROC_MEMORY_DELAY
12589 | INSN_LOAD_COPROC_DELAY
12590 | INSN_LOAD_MEMORY_DELAY
12591 | INSN_STORE_MEMORY))))
12592 rtype |= RTYPE_VEC;
12594 if (reg_lookup (&s, rtype, ®no))
12596 if ((regno & 1) != 0
12598 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12599 as_warn (_("Float register should be even, was %d"),
12607 if (c == 'V' || c == 'W')
12618 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12624 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12628 /* This is like 'Z', but also needs to fix the MDMX
12629 vector/scalar select bits. Note that the
12630 scalar immediate case is handled above. */
12631 if ((ip->insn_mo->membership & INSN_5400)
12632 && strcmp (insn->name, "rzu.ob") == 0)
12633 as_bad (_("Operand %d of `%s' must be an immediate"),
12634 argnum, ip->insn_mo->name);
12638 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12639 int max_el = (is_qh ? 3 : 7);
12641 my_getExpression(&imm_expr, s);
12642 check_absolute_expr (ip, &imm_expr);
12644 if (imm_expr.X_add_number > max_el)
12645 as_bad (_("Bad element selector %ld"),
12646 (long) imm_expr.X_add_number);
12647 imm_expr.X_add_number &= max_el;
12648 ip->insn_opcode |= (imm_expr.X_add_number
12651 imm_expr.X_op = O_absent;
12653 as_warn (_("Expecting ']' found '%s'"), s);
12659 if ((ip->insn_mo->membership & INSN_5400)
12660 && (strcmp (insn->name, "sll.ob") == 0
12661 || strcmp (insn->name, "srl.ob") == 0))
12662 as_bad (_("Operand %d of `%s' must be scalar"),
12663 argnum, ip->insn_mo->name);
12665 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12666 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12669 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12672 /* Fall through. */
12676 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12680 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12690 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12694 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12700 my_getExpression (&imm_expr, s);
12701 if (imm_expr.X_op != O_big
12702 && imm_expr.X_op != O_constant)
12703 insn_error = _("absolute expression required");
12704 if (HAVE_32BIT_GPRS)
12705 normalize_constant_expr (&imm_expr);
12710 my_getSmallExpression (&offset_expr, offset_reloc, s);
12711 if (offset_expr.X_op == O_register)
12713 /* Assume that the offset has been elided and that what
12714 we saw was a base register. The match will fail later
12715 if that assumption turns out to be wrong. */
12716 offset_expr.X_op = O_constant;
12717 offset_expr.X_add_number = 0;
12721 normalize_address_expr (&offset_expr);
12735 unsigned char temp[8];
12737 unsigned int length;
12742 /* These only appear as the last operand in an
12743 instruction, and every instruction that accepts
12744 them in any variant accepts them in all variants.
12745 This means we don't have to worry about backing out
12746 any changes if the instruction does not match.
12748 The difference between them is the size of the
12749 floating point constant and where it goes. For 'F'
12750 and 'L' the constant is 64 bits; for 'f' and 'l' it
12751 is 32 bits. Where the constant is placed is based
12752 on how the MIPS assembler does things:
12755 f -- immediate value
12758 The .lit4 and .lit8 sections are only used if
12759 permitted by the -G argument.
12761 The code below needs to know whether the target register
12762 is 32 or 64 bits wide. It relies on the fact 'f' and
12763 'F' are used with GPR-based instructions and 'l' and
12764 'L' are used with FPR-based instructions. */
12766 f64 = *args == 'F' || *args == 'L';
12767 using_gprs = *args == 'F' || *args == 'f';
12769 save_in = input_line_pointer;
12770 input_line_pointer = s;
12771 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12773 s = input_line_pointer;
12774 input_line_pointer = save_in;
12775 if (err != NULL && *err != '\0')
12777 as_bad (_("Bad floating point constant: %s"), err);
12778 memset (temp, '\0', sizeof temp);
12779 length = f64 ? 8 : 4;
12782 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12786 && (g_switch_value < 4
12787 || (temp[0] == 0 && temp[1] == 0)
12788 || (temp[2] == 0 && temp[3] == 0))))
12790 imm_expr.X_op = O_constant;
12791 if (!target_big_endian)
12792 imm_expr.X_add_number = bfd_getl32 (temp);
12794 imm_expr.X_add_number = bfd_getb32 (temp);
12796 else if (length > 4
12797 && !mips_disable_float_construction
12798 /* Constants can only be constructed in GPRs and
12799 copied to FPRs if the GPRs are at least as wide
12800 as the FPRs. Force the constant into memory if
12801 we are using 64-bit FPRs but the GPRs are only
12804 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12805 && ((temp[0] == 0 && temp[1] == 0)
12806 || (temp[2] == 0 && temp[3] == 0))
12807 && ((temp[4] == 0 && temp[5] == 0)
12808 || (temp[6] == 0 && temp[7] == 0)))
12810 /* The value is simple enough to load with a couple of
12811 instructions. If using 32-bit registers, set
12812 imm_expr to the high order 32 bits and offset_expr to
12813 the low order 32 bits. Otherwise, set imm_expr to
12814 the entire 64 bit constant. */
12815 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12817 imm_expr.X_op = O_constant;
12818 offset_expr.X_op = O_constant;
12819 if (!target_big_endian)
12821 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12822 offset_expr.X_add_number = bfd_getl32 (temp);
12826 imm_expr.X_add_number = bfd_getb32 (temp);
12827 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12829 if (offset_expr.X_add_number == 0)
12830 offset_expr.X_op = O_absent;
12834 imm_expr.X_op = O_constant;
12835 if (!target_big_endian)
12836 imm_expr.X_add_number = bfd_getl64 (temp);
12838 imm_expr.X_add_number = bfd_getb64 (temp);
12843 const char *newname;
12846 /* Switch to the right section. */
12848 subseg = now_subseg;
12851 default: /* unused default case avoids warnings. */
12853 newname = RDATA_SECTION_NAME;
12854 if (g_switch_value >= 8)
12858 newname = RDATA_SECTION_NAME;
12861 gas_assert (g_switch_value >= 4);
12865 new_seg = subseg_new (newname, (subsegT) 0);
12866 bfd_set_section_flags (stdoutput, new_seg,
12871 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12872 if (strncmp (TARGET_OS, "elf", 3) != 0)
12873 record_alignment (new_seg, 4);
12875 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12876 if (seg == now_seg)
12877 as_bad (_("Can't use floating point insn in this section"));
12879 /* Set the argument to the current address in the
12881 offset_expr.X_op = O_symbol;
12882 offset_expr.X_add_symbol = symbol_temp_new_now ();
12883 offset_expr.X_add_number = 0;
12885 /* Put the floating point number into the section. */
12886 p = frag_more ((int) length);
12887 memcpy (p, temp, length);
12889 /* Switch back to the original section. */
12890 subseg_set (seg, subseg);
12895 case 'i': /* 16-bit unsigned immediate. */
12896 case 'j': /* 16-bit signed immediate. */
12897 *offset_reloc = BFD_RELOC_LO16;
12898 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0)
12901 offsetT minval, maxval;
12903 more = (insn + 1 < past
12904 && strcmp (insn->name, insn[1].name) == 0);
12906 /* For compatibility with older assemblers, we accept
12907 0x8000-0xffff as signed 16-bit numbers when only
12908 signed numbers are allowed. */
12910 minval = 0, maxval = 0xffff;
12912 minval = -0x8000, maxval = 0x7fff;
12914 minval = -0x8000, maxval = 0xffff;
12916 if (offset_expr.X_op != O_constant
12917 || offset_expr.X_add_number < minval
12918 || offset_expr.X_add_number > maxval)
12922 if (offset_expr.X_op == O_constant
12923 || offset_expr.X_op == O_big)
12924 as_bad (_("Expression out of range"));
12930 case 'o': /* 16-bit offset. */
12931 offset_reloc[0] = BFD_RELOC_LO16;
12932 offset_reloc[1] = BFD_RELOC_UNUSED;
12933 offset_reloc[2] = BFD_RELOC_UNUSED;
12935 /* Check whether there is only a single bracketed expression
12936 left. If so, it must be the base register and the
12937 constant must be zero. */
12938 if (*s == '(' && strchr (s + 1, '(') == 0)
12940 offset_expr.X_op = O_constant;
12941 offset_expr.X_add_number = 0;
12945 /* If this value won't fit into a 16 bit offset, then go
12946 find a macro that will generate the 32 bit offset
12948 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12949 && (offset_expr.X_op != O_constant
12950 || offset_expr.X_add_number >= 0x8000
12951 || offset_expr.X_add_number < -0x8000))
12957 case 'p': /* PC-relative offset. */
12958 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12959 my_getExpression (&offset_expr, s);
12963 case 'u': /* Upper 16 bits. */
12964 *offset_reloc = BFD_RELOC_LO16;
12965 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12966 && offset_expr.X_op == O_constant
12967 && (offset_expr.X_add_number < 0
12968 || offset_expr.X_add_number >= 0x10000))
12969 as_bad (_("lui expression (%lu) not in range 0..65535"),
12970 (unsigned long) offset_expr.X_add_number);
12974 case 'a': /* 26-bit address. */
12976 *offset_reloc = BFD_RELOC_MIPS_JMP;
12977 my_getExpression (&offset_expr, s);
12981 case 'N': /* 3-bit branch condition code. */
12982 case 'M': /* 3-bit compare condition code. */
12984 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12985 rtype |= RTYPE_FCC;
12986 if (!reg_lookup (&s, rtype, ®no))
12988 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12989 || strcmp (str + strlen (str) - 5, "any2f") == 0
12990 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12991 && (regno & 1) != 0)
12992 as_warn (_("Condition code register should be even for %s, "
12995 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12996 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12997 && (regno & 3) != 0)
12998 as_warn (_("Condition code register should be 0 or 4 for %s, "
13002 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
13004 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
13008 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
13019 while (ISDIGIT (*s));
13022 c = 8; /* Invalid sel value. */
13025 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13026 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13030 gas_assert (!mips_opts.micromips);
13031 /* Must be at least one digit. */
13032 my_getExpression (&imm_expr, s);
13033 check_absolute_expr (ip, &imm_expr);
13035 if ((unsigned long) imm_expr.X_add_number
13036 > (unsigned long) OP_MASK_VECBYTE)
13038 as_bad (_("bad byte vector index (%ld)"),
13039 (long) imm_expr.X_add_number);
13040 imm_expr.X_add_number = 0;
13043 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13044 imm_expr.X_op = O_absent;
13049 gas_assert (!mips_opts.micromips);
13050 my_getExpression (&imm_expr, s);
13051 check_absolute_expr (ip, &imm_expr);
13053 if ((unsigned long) imm_expr.X_add_number
13054 > (unsigned long) OP_MASK_VECALIGN)
13056 as_bad (_("bad byte vector index (%ld)"),
13057 (long) imm_expr.X_add_number);
13058 imm_expr.X_add_number = 0;
13061 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13062 imm_expr.X_op = O_absent;
13066 case 'm': /* Opcode extension character. */
13067 gas_assert (mips_opts.micromips);
13072 if (strncmp (s, "$pc", 3) == 0)
13099 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13100 if (regno == AT && mips_opts.at)
13102 if (mips_opts.at == ATREG)
13103 as_warn (_("Used $at without \".set noat\""));
13105 as_warn (_("Used $%u with \".set at=$%u\""),
13106 regno, mips_opts.at);
13112 gas_assert (args[1] == ',');
13118 gas_assert (args[1] == ',');
13120 continue; /* Nothing to do. */
13126 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13128 if (regno == lastregno)
13131 = _("Source and destination must be different");
13134 if (regno == 31 && lastregno == 0xffffffff)
13137 = _("A destination register must be supplied");
13148 gas_assert (args[1] == ',');
13155 gas_assert (args[1] == ',');
13158 continue; /* Nothing to do. */
13162 /* Make sure regno is the same as lastregno. */
13163 if (c == 't' && regno != lastregno)
13166 /* Make sure regno is the same as destregno. */
13167 if (c == 'x' && regno != destregno)
13170 /* We need to save regno, before regno maps to the
13171 microMIPS register encoding. */
13181 regno = ILLEGAL_REG;
13185 regno = mips32_to_micromips_reg_b_map[regno];
13189 regno = mips32_to_micromips_reg_c_map[regno];
13193 regno = mips32_to_micromips_reg_d_map[regno];
13197 regno = mips32_to_micromips_reg_e_map[regno];
13201 regno = mips32_to_micromips_reg_f_map[regno];
13205 regno = mips32_to_micromips_reg_g_map[regno];
13209 s += strspn (s, " \t");
13212 regno = ILLEGAL_REG;
13216 s += strspn (s, " \t");
13217 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
13220 regno = ILLEGAL_REG;
13223 if (regno2 == AT && mips_opts.at)
13225 if (mips_opts.at == ATREG)
13226 as_warn (_("Used $at without \".set noat\""));
13228 as_warn (_("Used $%u with \".set at=$%u\""),
13229 regno2, mips_opts.at);
13231 regno = (mips_lookup_reg_pair
13233 micromips_to_32_reg_h_map1,
13234 micromips_to_32_reg_h_map2, 8));
13238 regno = mips32_to_micromips_reg_l_map[regno];
13242 regno = mips32_to_micromips_reg_m_map[regno];
13246 regno = mips32_to_micromips_reg_n_map[regno];
13250 regno = mips32_to_micromips_reg_q_map[regno];
13255 regno = ILLEGAL_REG;
13260 regno = ILLEGAL_REG;
13265 regno = ILLEGAL_REG;
13268 case 'j': /* Do nothing. */
13278 if (regno == ILLEGAL_REG)
13284 INSERT_OPERAND (1, MB, *ip, regno);
13288 INSERT_OPERAND (1, MC, *ip, regno);
13292 INSERT_OPERAND (1, MD, *ip, regno);
13296 INSERT_OPERAND (1, ME, *ip, regno);
13300 INSERT_OPERAND (1, MF, *ip, regno);
13304 INSERT_OPERAND (1, MG, *ip, regno);
13308 INSERT_OPERAND (1, MH, *ip, regno);
13312 INSERT_OPERAND (1, MJ, *ip, regno);
13316 INSERT_OPERAND (1, ML, *ip, regno);
13320 INSERT_OPERAND (1, MM, *ip, regno);
13324 INSERT_OPERAND (1, MN, *ip, regno);
13328 INSERT_OPERAND (1, MP, *ip, regno);
13332 INSERT_OPERAND (1, MQ, *ip, regno);
13335 case 'a': /* Do nothing. */
13336 case 's': /* Do nothing. */
13337 case 't': /* Do nothing. */
13338 case 'x': /* Do nothing. */
13339 case 'y': /* Do nothing. */
13340 case 'z': /* Do nothing. */
13350 bfd_reloc_code_real_type r[3];
13354 /* Check whether there is only a single bracketed
13355 expression left. If so, it must be the base register
13356 and the constant must be zero. */
13357 if (*s == '(' && strchr (s + 1, '(') == 0)
13359 INSERT_OPERAND (1, IMMA, *ip, 0);
13363 if (my_getSmallExpression (&ep, r, s) > 0
13364 || !expr_const_in_range (&ep, -64, 64, 2))
13367 imm = ep.X_add_number >> 2;
13368 INSERT_OPERAND (1, IMMA, *ip, imm);
13375 bfd_reloc_code_real_type r[3];
13379 if (my_getSmallExpression (&ep, r, s) > 0
13380 || ep.X_op != O_constant)
13383 for (imm = 0; imm < 8; imm++)
13384 if (micromips_imm_b_map[imm] == ep.X_add_number)
13389 INSERT_OPERAND (1, IMMB, *ip, imm);
13396 bfd_reloc_code_real_type r[3];
13400 if (my_getSmallExpression (&ep, r, s) > 0
13401 || ep.X_op != O_constant)
13404 for (imm = 0; imm < 16; imm++)
13405 if (micromips_imm_c_map[imm] == ep.X_add_number)
13410 INSERT_OPERAND (1, IMMC, *ip, imm);
13415 case 'D': /* pc relative offset */
13416 case 'E': /* pc relative offset */
13417 my_getExpression (&offset_expr, s);
13418 if (offset_expr.X_op == O_register)
13421 if (!forced_insn_length)
13422 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13424 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13426 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13432 bfd_reloc_code_real_type r[3];
13436 if (my_getSmallExpression (&ep, r, s) > 0
13437 || !expr_const_in_range (&ep, 0, 16, 0))
13440 imm = ep.X_add_number;
13441 INSERT_OPERAND (1, IMMF, *ip, imm);
13448 bfd_reloc_code_real_type r[3];
13452 /* Check whether there is only a single bracketed
13453 expression left. If so, it must be the base register
13454 and the constant must be zero. */
13455 if (*s == '(' && strchr (s + 1, '(') == 0)
13457 INSERT_OPERAND (1, IMMG, *ip, 0);
13461 if (my_getSmallExpression (&ep, r, s) > 0
13462 || !expr_const_in_range (&ep, -1, 15, 0))
13465 imm = ep.X_add_number & 15;
13466 INSERT_OPERAND (1, IMMG, *ip, imm);
13473 bfd_reloc_code_real_type r[3];
13477 /* Check whether there is only a single bracketed
13478 expression left. If so, it must be the base register
13479 and the constant must be zero. */
13480 if (*s == '(' && strchr (s + 1, '(') == 0)
13482 INSERT_OPERAND (1, IMMH, *ip, 0);
13486 if (my_getSmallExpression (&ep, r, s) > 0
13487 || !expr_const_in_range (&ep, 0, 16, 1))
13490 imm = ep.X_add_number >> 1;
13491 INSERT_OPERAND (1, IMMH, *ip, imm);
13498 bfd_reloc_code_real_type r[3];
13502 if (my_getSmallExpression (&ep, r, s) > 0
13503 || !expr_const_in_range (&ep, -1, 127, 0))
13506 imm = ep.X_add_number & 127;
13507 INSERT_OPERAND (1, IMMI, *ip, imm);
13514 bfd_reloc_code_real_type r[3];
13518 /* Check whether there is only a single bracketed
13519 expression left. If so, it must be the base register
13520 and the constant must be zero. */
13521 if (*s == '(' && strchr (s + 1, '(') == 0)
13523 INSERT_OPERAND (1, IMMJ, *ip, 0);
13527 if (my_getSmallExpression (&ep, r, s) > 0
13528 || !expr_const_in_range (&ep, 0, 16, 2))
13531 imm = ep.X_add_number >> 2;
13532 INSERT_OPERAND (1, IMMJ, *ip, imm);
13539 bfd_reloc_code_real_type r[3];
13543 /* Check whether there is only a single bracketed
13544 expression left. If so, it must be the base register
13545 and the constant must be zero. */
13546 if (*s == '(' && strchr (s + 1, '(') == 0)
13548 INSERT_OPERAND (1, IMML, *ip, 0);
13552 if (my_getSmallExpression (&ep, r, s) > 0
13553 || !expr_const_in_range (&ep, 0, 16, 0))
13556 imm = ep.X_add_number;
13557 INSERT_OPERAND (1, IMML, *ip, imm);
13564 bfd_reloc_code_real_type r[3];
13568 if (my_getSmallExpression (&ep, r, s) > 0
13569 || !expr_const_in_range (&ep, 1, 9, 0))
13572 imm = ep.X_add_number & 7;
13573 INSERT_OPERAND (1, IMMM, *ip, imm);
13578 case 'N': /* Register list for lwm and swm. */
13580 /* A comma-separated list of registers and/or
13581 dash-separated contiguous ranges including
13582 both ra and a set of one or more registers
13583 starting at s0 up to s3 which have to be
13590 and any permutations of these. */
13591 unsigned int reglist;
13594 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13597 if ((reglist & 0xfff1ffff) != 0x80010000)
13600 reglist = (reglist >> 17) & 7;
13602 if ((reglist & -reglist) != reglist)
13605 imm = ffs (reglist) - 1;
13606 INSERT_OPERAND (1, IMMN, *ip, imm);
13610 case 'O': /* sdbbp 4-bit code. */
13612 bfd_reloc_code_real_type r[3];
13616 if (my_getSmallExpression (&ep, r, s) > 0
13617 || !expr_const_in_range (&ep, 0, 16, 0))
13620 imm = ep.X_add_number;
13621 INSERT_OPERAND (1, IMMO, *ip, imm);
13628 bfd_reloc_code_real_type r[3];
13632 if (my_getSmallExpression (&ep, r, s) > 0
13633 || !expr_const_in_range (&ep, 0, 32, 2))
13636 imm = ep.X_add_number >> 2;
13637 INSERT_OPERAND (1, IMMP, *ip, imm);
13644 bfd_reloc_code_real_type r[3];
13648 if (my_getSmallExpression (&ep, r, s) > 0
13649 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13652 imm = ep.X_add_number >> 2;
13653 INSERT_OPERAND (1, IMMQ, *ip, imm);
13660 bfd_reloc_code_real_type r[3];
13664 /* Check whether there is only a single bracketed
13665 expression left. If so, it must be the base register
13666 and the constant must be zero. */
13667 if (*s == '(' && strchr (s + 1, '(') == 0)
13669 INSERT_OPERAND (1, IMMU, *ip, 0);
13673 if (my_getSmallExpression (&ep, r, s) > 0
13674 || !expr_const_in_range (&ep, 0, 32, 2))
13677 imm = ep.X_add_number >> 2;
13678 INSERT_OPERAND (1, IMMU, *ip, imm);
13685 bfd_reloc_code_real_type r[3];
13689 if (my_getSmallExpression (&ep, r, s) > 0
13690 || !expr_const_in_range (&ep, 0, 64, 2))
13693 imm = ep.X_add_number >> 2;
13694 INSERT_OPERAND (1, IMMW, *ip, imm);
13701 bfd_reloc_code_real_type r[3];
13705 if (my_getSmallExpression (&ep, r, s) > 0
13706 || !expr_const_in_range (&ep, -8, 8, 0))
13709 imm = ep.X_add_number;
13710 INSERT_OPERAND (1, IMMX, *ip, imm);
13717 bfd_reloc_code_real_type r[3];
13721 if (my_getSmallExpression (&ep, r, s) > 0
13722 || expr_const_in_range (&ep, -2, 2, 2)
13723 || !expr_const_in_range (&ep, -258, 258, 2))
13726 imm = ep.X_add_number >> 2;
13727 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13728 INSERT_OPERAND (1, IMMY, *ip, imm);
13735 bfd_reloc_code_real_type r[3];
13738 if (my_getSmallExpression (&ep, r, s) > 0
13739 || !expr_const_in_range (&ep, 0, 1, 0))
13746 as_bad (_("Internal error: bad microMIPS opcode "
13747 "(unknown extension operand type `m%c'): %s %s"),
13748 *args, insn->name, insn->args);
13749 /* Further processing is fruitless. */
13754 case 'n': /* Register list for 32-bit lwm and swm. */
13755 gas_assert (mips_opts.micromips);
13757 /* A comma-separated list of registers and/or
13758 dash-separated contiguous ranges including
13759 at least one of ra and a set of one or more
13760 registers starting at s0 up to s7 and then
13761 s8 which have to be consecutive, e.g.:
13769 and any permutations of these. */
13770 unsigned int reglist;
13774 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13777 if ((reglist & 0x3f00ffff) != 0)
13780 ra = (reglist >> 27) & 0x10;
13781 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13783 if ((reglist & -reglist) != reglist)
13786 imm = (ffs (reglist) - 1) | ra;
13787 INSERT_OPERAND (1, RT, *ip, imm);
13788 imm_expr.X_op = O_absent;
13792 case '|': /* 4-bit trap code. */
13793 gas_assert (mips_opts.micromips);
13794 my_getExpression (&imm_expr, s);
13795 check_absolute_expr (ip, &imm_expr);
13796 if ((unsigned long) imm_expr.X_add_number
13797 > MICROMIPSOP_MASK_TRAP)
13798 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13799 (unsigned long) imm_expr.X_add_number,
13800 ip->insn_mo->name);
13801 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13802 imm_expr.X_op = O_absent;
13807 as_bad (_("Bad char = '%c'\n"), *args);
13812 /* Args don't match. */
13814 insn_error = _("Illegal operands");
13815 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13820 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13822 gas_assert (firstinsn);
13823 need_delay_slot_ok = FALSE;
13832 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13834 /* As for mips_ip, but used when assembling MIPS16 code.
13835 Also set forced_insn_length to the resulting instruction size in
13836 bytes if the user explicitly requested a small or extended instruction. */
13839 mips16_ip (char *str, struct mips_cl_insn *ip)
13843 struct mips_opcode *insn;
13845 unsigned int regno;
13846 unsigned int lastregno = 0;
13852 forced_insn_length = 0;
13854 for (s = str; ISLOWER (*s); ++s)
13866 if (s[1] == 't' && s[2] == ' ')
13869 forced_insn_length = 2;
13873 else if (s[1] == 'e' && s[2] == ' ')
13876 forced_insn_length = 4;
13880 /* Fall through. */
13882 insn_error = _("unknown opcode");
13886 if (mips_opts.noautoextend && !forced_insn_length)
13887 forced_insn_length = 2;
13889 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13891 insn_error = _("unrecognized opcode");
13901 gas_assert (strcmp (insn->name, str) == 0);
13903 ok = is_opcode_valid_16 (insn);
13906 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13907 && strcmp (insn->name, insn[1].name) == 0)
13916 static char buf[100];
13918 _("Opcode not supported on this processor: %s (%s)"),
13919 mips_cpu_info_from_arch (mips_opts.arch)->name,
13920 mips_cpu_info_from_isa (mips_opts.isa)->name);
13927 create_insn (ip, insn);
13928 imm_expr.X_op = O_absent;
13929 imm2_expr.X_op = O_absent;
13930 offset_expr.X_op = O_absent;
13931 offset_reloc[0] = BFD_RELOC_UNUSED;
13932 offset_reloc[1] = BFD_RELOC_UNUSED;
13933 offset_reloc[2] = BFD_RELOC_UNUSED;
13935 for (args = insn->args; 1; ++args)
13942 /* In this switch statement we call break if we did not find
13943 a match, continue if we did find a match, or return if we
13954 /* Stuff the immediate value in now, if we can. */
13955 if (insn->pinfo == INSN_MACRO)
13957 gas_assert (relax_char == 0);
13958 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
13960 else if (relax_char
13961 && offset_expr.X_op == O_constant
13962 && calculate_reloc (*offset_reloc,
13963 offset_expr.X_add_number,
13966 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
13967 forced_insn_length, &ip->insn_opcode);
13968 offset_expr.X_op = O_absent;
13969 *offset_reloc = BFD_RELOC_UNUSED;
13971 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
13973 if (forced_insn_length == 2)
13974 as_bad (_("invalid unextended operand value"));
13975 forced_insn_length = 4;
13976 ip->insn_opcode |= MIPS16_EXTEND;
13978 else if (relax_char)
13979 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
13992 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13995 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14011 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14013 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14017 /* Fall through. */
14028 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14030 if (c == 'v' || c == 'w')
14033 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14035 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14046 if (c == 'v' || c == 'w')
14048 regno = mips16_to_32_reg_map[lastregno];
14062 regno = mips32_to_16_reg_map[regno];
14067 regno = ILLEGAL_REG;
14072 regno = ILLEGAL_REG;
14077 regno = ILLEGAL_REG;
14082 if (regno == AT && mips_opts.at)
14084 if (mips_opts.at == ATREG)
14085 as_warn (_("used $at without \".set noat\""));
14087 as_warn (_("used $%u with \".set at=$%u\""),
14088 regno, mips_opts.at);
14096 if (regno == ILLEGAL_REG)
14103 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14107 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14110 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14113 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14119 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14122 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14123 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14133 if (strncmp (s, "$pc", 3) == 0)
14150 i = my_getSmallExpression (&offset_expr, offset_reloc, s);
14157 *offset_reloc = BFD_RELOC_UNUSED;
14158 /* Fall through. */
14165 my_getExpression (&offset_expr, s);
14166 if (offset_expr.X_op == O_register)
14168 /* What we thought was an expression turned out to
14171 if (s[0] == '(' && args[1] == '(')
14173 /* It looks like the expression was omitted
14174 before a register indirection, which means
14175 that the expression is implicitly zero. We
14176 still set up offset_expr, so that we handle
14177 explicit extensions correctly. */
14178 offset_expr.X_op = O_constant;
14179 offset_expr.X_add_number = 0;
14187 /* We need to relax this instruction. */
14197 /* We use offset_reloc rather than imm_reloc for the PC
14198 relative operands. This lets macros with both
14199 immediate and address operands work correctly. */
14200 my_getExpression (&offset_expr, s);
14202 if (offset_expr.X_op == O_register)
14205 /* We need to relax this instruction. */
14210 case '6': /* break code */
14211 my_getExpression (&imm_expr, s);
14212 check_absolute_expr (ip, &imm_expr);
14213 if ((unsigned long) imm_expr.X_add_number > 63)
14214 as_warn (_("Invalid value for `%s' (%lu)"),
14216 (unsigned long) imm_expr.X_add_number);
14217 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14218 imm_expr.X_op = O_absent;
14223 my_getExpression (&imm_expr, s);
14224 if (imm_expr.X_op != O_big
14225 && imm_expr.X_op != O_constant)
14226 insn_error = _("absolute expression required");
14227 if (HAVE_32BIT_GPRS)
14228 normalize_constant_expr (&imm_expr);
14232 case 'a': /* 26 bit address */
14234 my_getExpression (&offset_expr, s);
14236 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14237 ip->insn_opcode <<= 16;
14240 case 'l': /* register list for entry macro */
14241 case 'L': /* register list for exit macro */
14251 unsigned int freg, reg1, reg2;
14253 while (*s == ' ' || *s == ',')
14255 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14257 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14261 as_bad (_("can't parse register list"));
14271 if (!reg_lookup (&s, freg ? RTYPE_FPU
14272 : (RTYPE_GP | RTYPE_NUM), ®2))
14274 as_bad (_("invalid register list"));
14278 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14280 mask &= ~ (7 << 3);
14283 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14285 mask &= ~ (7 << 3);
14288 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14289 mask |= (reg2 - 3) << 3;
14290 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14291 mask |= (reg2 - 15) << 1;
14292 else if (reg1 == RA && reg2 == RA)
14296 as_bad (_("invalid register list"));
14300 /* The mask is filled in in the opcode table for the
14301 benefit of the disassembler. We remove it before
14302 applying the actual mask. */
14303 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14304 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14308 case 'm': /* Register list for save insn. */
14309 case 'M': /* Register list for restore insn. */
14311 int opcode = ip->insn_opcode;
14312 int framesz = 0, seen_framesz = 0;
14313 int nargs = 0, statics = 0, sregs = 0;
14317 unsigned int reg1, reg2;
14319 SKIP_SPACE_TABS (s);
14322 SKIP_SPACE_TABS (s);
14324 my_getExpression (&imm_expr, s);
14325 if (imm_expr.X_op == O_constant)
14327 /* Handle the frame size. */
14330 as_bad (_("more than one frame size in list"));
14334 framesz = imm_expr.X_add_number;
14335 imm_expr.X_op = O_absent;
14340 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14342 as_bad (_("can't parse register list"));
14354 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14357 as_bad (_("can't parse register list"));
14362 while (reg1 <= reg2)
14364 if (reg1 >= 4 && reg1 <= 7)
14368 nargs |= 1 << (reg1 - 4);
14370 /* statics $a0-$a3 */
14371 statics |= 1 << (reg1 - 4);
14373 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14376 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14378 else if (reg1 == 31)
14380 /* Add $ra to insn. */
14385 as_bad (_("unexpected register in list"));
14393 /* Encode args/statics combination. */
14394 if (nargs & statics)
14395 as_bad (_("arg/static registers overlap"));
14396 else if (nargs == 0xf)
14397 /* All $a0-$a3 are args. */
14398 opcode |= MIPS16_ALL_ARGS << 16;
14399 else if (statics == 0xf)
14400 /* All $a0-$a3 are statics. */
14401 opcode |= MIPS16_ALL_STATICS << 16;
14404 int narg = 0, nstat = 0;
14406 /* Count arg registers. */
14407 while (nargs & 0x1)
14413 as_bad (_("invalid arg register list"));
14415 /* Count static registers. */
14416 while (statics & 0x8)
14418 statics = (statics << 1) & 0xf;
14422 as_bad (_("invalid static register list"));
14424 /* Encode args/statics. */
14425 opcode |= ((narg << 2) | nstat) << 16;
14428 /* Encode $s0/$s1. */
14429 if (sregs & (1 << 0)) /* $s0 */
14431 if (sregs & (1 << 1)) /* $s1 */
14437 /* Count regs $s2-$s8. */
14445 as_bad (_("invalid static register list"));
14446 /* Encode $s2-$s8. */
14447 opcode |= nsreg << 24;
14450 /* Encode frame size. */
14452 as_bad (_("missing frame size"));
14453 else if ((framesz & 7) != 0 || framesz < 0
14454 || framesz > 0xff * 8)
14455 as_bad (_("invalid frame size"));
14456 else if (framesz != 128 || (opcode >> 16) != 0)
14459 opcode |= (((framesz & 0xf0) << 16)
14460 | (framesz & 0x0f));
14463 /* Finally build the instruction. */
14464 if ((opcode >> 16) != 0 || framesz == 0)
14465 opcode |= MIPS16_EXTEND;
14466 ip->insn_opcode = opcode;
14470 case 'e': /* extend code */
14471 my_getExpression (&imm_expr, s);
14472 check_absolute_expr (ip, &imm_expr);
14473 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14475 as_warn (_("Invalid value for `%s' (%lu)"),
14477 (unsigned long) imm_expr.X_add_number);
14478 imm_expr.X_add_number &= 0x7ff;
14480 ip->insn_opcode |= imm_expr.X_add_number;
14481 imm_expr.X_op = O_absent;
14491 /* Args don't match. */
14492 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14493 strcmp (insn->name, insn[1].name) == 0)
14500 insn_error = _("illegal operands");
14506 /* This structure holds information we know about a mips16 immediate
14509 struct mips16_immed_operand
14511 /* The type code used in the argument string in the opcode table. */
14513 /* The number of bits in the short form of the opcode. */
14515 /* The number of bits in the extended form of the opcode. */
14517 /* The amount by which the short form is shifted when it is used;
14518 for example, the sw instruction has a shift count of 2. */
14520 /* The amount by which the short form is shifted when it is stored
14521 into the instruction code. */
14523 /* Non-zero if the short form is unsigned. */
14525 /* Non-zero if the extended form is unsigned. */
14527 /* Non-zero if the value is PC relative. */
14531 /* The mips16 immediate operand types. */
14533 static const struct mips16_immed_operand mips16_immed_operands[] =
14535 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14536 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14537 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14538 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14539 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14540 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14541 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14542 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14543 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14544 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14545 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14546 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14547 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14548 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14549 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14550 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14551 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14552 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14553 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14554 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14555 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14558 #define MIPS16_NUM_IMMED \
14559 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14561 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14562 NBITS is the number of significant bits in VAL. */
14564 static unsigned long
14565 mips16_immed_extend (offsetT val, unsigned int nbits)
14570 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14573 else if (nbits == 15)
14575 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14580 extval = ((val & 0x1f) << 6) | (val & 0x20);
14583 return (extval << 16) | val;
14586 /* Install immediate value VAL into MIPS16 instruction *INSN,
14587 extending it if necessary. The instruction in *INSN may
14588 already be extended.
14590 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14591 if none. In the former case, VAL is a 16-bit number with no
14592 defined signedness.
14594 TYPE is the type of the immediate field. USER_INSN_LENGTH
14595 is the length that the user requested, or 0 if none. */
14598 mips16_immed (char *file, unsigned int line, int type,
14599 bfd_reloc_code_real_type reloc, offsetT val,
14600 unsigned int user_insn_length, unsigned long *insn)
14602 const struct mips16_immed_operand *op;
14603 int mintiny, maxtiny;
14605 op = mips16_immed_operands;
14606 while (op->type != type)
14609 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14614 if (type == '<' || type == '>' || type == '[' || type == ']')
14617 maxtiny = 1 << op->nbits;
14622 maxtiny = (1 << op->nbits) - 1;
14624 if (reloc != BFD_RELOC_UNUSED)
14629 mintiny = - (1 << (op->nbits - 1));
14630 maxtiny = (1 << (op->nbits - 1)) - 1;
14631 if (reloc != BFD_RELOC_UNUSED)
14632 val = SEXT_16BIT (val);
14635 /* Branch offsets have an implicit 0 in the lowest bit. */
14636 if (type == 'p' || type == 'q')
14639 if ((val & ((1 << op->shift) - 1)) != 0
14640 || val < (mintiny << op->shift)
14641 || val > (maxtiny << op->shift))
14643 /* We need an extended instruction. */
14644 if (user_insn_length == 2)
14645 as_bad_where (file, line, _("invalid unextended operand value"));
14647 *insn |= MIPS16_EXTEND;
14649 else if (user_insn_length == 4)
14651 /* The operand doesn't force an unextended instruction to be extended.
14652 Warn if the user wanted an extended instruction anyway. */
14653 *insn |= MIPS16_EXTEND;
14654 as_warn_where (file, line,
14655 _("extended operand requested but not required"));
14658 if (mips16_opcode_length (*insn) == 2)
14662 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14663 insnval <<= op->op_shift;
14668 long minext, maxext;
14670 if (reloc == BFD_RELOC_UNUSED)
14675 maxext = (1 << op->extbits) - 1;
14679 minext = - (1 << (op->extbits - 1));
14680 maxext = (1 << (op->extbits - 1)) - 1;
14682 if (val < minext || val > maxext)
14683 as_bad_where (file, line,
14684 _("operand value out of range for instruction"));
14687 *insn |= mips16_immed_extend (val, op->extbits);
14691 struct percent_op_match
14694 bfd_reloc_code_real_type reloc;
14697 static const struct percent_op_match mips_percent_op[] =
14699 {"%lo", BFD_RELOC_LO16},
14700 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14701 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14702 {"%call16", BFD_RELOC_MIPS_CALL16},
14703 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14704 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14705 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14706 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14707 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14708 {"%got", BFD_RELOC_MIPS_GOT16},
14709 {"%gp_rel", BFD_RELOC_GPREL16},
14710 {"%half", BFD_RELOC_16},
14711 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14712 {"%higher", BFD_RELOC_MIPS_HIGHER},
14713 {"%neg", BFD_RELOC_MIPS_SUB},
14714 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14715 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14716 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14717 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14718 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14719 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14720 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14721 {"%hi", BFD_RELOC_HI16_S}
14724 static const struct percent_op_match mips16_percent_op[] =
14726 {"%lo", BFD_RELOC_MIPS16_LO16},
14727 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14728 {"%got", BFD_RELOC_MIPS16_GOT16},
14729 {"%call16", BFD_RELOC_MIPS16_CALL16},
14730 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14731 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14732 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14733 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14734 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14735 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14736 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14737 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14741 /* Return true if *STR points to a relocation operator. When returning true,
14742 move *STR over the operator and store its relocation code in *RELOC.
14743 Leave both *STR and *RELOC alone when returning false. */
14746 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14748 const struct percent_op_match *percent_op;
14751 if (mips_opts.mips16)
14753 percent_op = mips16_percent_op;
14754 limit = ARRAY_SIZE (mips16_percent_op);
14758 percent_op = mips_percent_op;
14759 limit = ARRAY_SIZE (mips_percent_op);
14762 for (i = 0; i < limit; i++)
14763 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14765 int len = strlen (percent_op[i].str);
14767 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14770 *str += strlen (percent_op[i].str);
14771 *reloc = percent_op[i].reloc;
14773 /* Check whether the output BFD supports this relocation.
14774 If not, issue an error and fall back on something safe. */
14775 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14777 as_bad (_("relocation %s isn't supported by the current ABI"),
14778 percent_op[i].str);
14779 *reloc = BFD_RELOC_UNUSED;
14787 /* Parse string STR as a 16-bit relocatable operand. Store the
14788 expression in *EP and the relocations in the array starting
14789 at RELOC. Return the number of relocation operators used.
14791 On exit, EXPR_END points to the first character after the expression. */
14794 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14797 bfd_reloc_code_real_type reversed_reloc[3];
14798 size_t reloc_index, i;
14799 int crux_depth, str_depth;
14802 /* Search for the start of the main expression, recoding relocations
14803 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14804 of the main expression and with CRUX_DEPTH containing the number
14805 of open brackets at that point. */
14812 crux_depth = str_depth;
14814 /* Skip over whitespace and brackets, keeping count of the number
14816 while (*str == ' ' || *str == '\t' || *str == '(')
14821 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14822 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14824 my_getExpression (ep, crux);
14827 /* Match every open bracket. */
14828 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14832 if (crux_depth > 0)
14833 as_bad (_("unclosed '('"));
14837 if (reloc_index != 0)
14839 prev_reloc_op_frag = frag_now;
14840 for (i = 0; i < reloc_index; i++)
14841 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14844 return reloc_index;
14848 my_getExpression (expressionS *ep, char *str)
14852 save_in = input_line_pointer;
14853 input_line_pointer = str;
14855 expr_end = input_line_pointer;
14856 input_line_pointer = save_in;
14860 md_atof (int type, char *litP, int *sizeP)
14862 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14866 md_number_to_chars (char *buf, valueT val, int n)
14868 if (target_big_endian)
14869 number_to_chars_bigendian (buf, val, n);
14871 number_to_chars_littleendian (buf, val, n);
14874 static int support_64bit_objects(void)
14876 const char **list, **l;
14879 list = bfd_target_list ();
14880 for (l = list; *l != NULL; l++)
14881 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14882 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14884 yes = (*l != NULL);
14889 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14890 NEW_VALUE. Warn if another value was already specified. Note:
14891 we have to defer parsing the -march and -mtune arguments in order
14892 to handle 'from-abi' correctly, since the ABI might be specified
14893 in a later argument. */
14896 mips_set_option_string (const char **string_ptr, const char *new_value)
14898 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14899 as_warn (_("A different %s was already specified, is now %s"),
14900 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14903 *string_ptr = new_value;
14907 md_parse_option (int c, char *arg)
14911 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14912 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14914 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14915 c == mips_ases[i].option_on);
14921 case OPTION_CONSTRUCT_FLOATS:
14922 mips_disable_float_construction = 0;
14925 case OPTION_NO_CONSTRUCT_FLOATS:
14926 mips_disable_float_construction = 1;
14938 target_big_endian = 1;
14942 target_big_endian = 0;
14948 else if (arg[0] == '0')
14950 else if (arg[0] == '1')
14960 mips_debug = atoi (arg);
14964 file_mips_isa = ISA_MIPS1;
14968 file_mips_isa = ISA_MIPS2;
14972 file_mips_isa = ISA_MIPS3;
14976 file_mips_isa = ISA_MIPS4;
14980 file_mips_isa = ISA_MIPS5;
14983 case OPTION_MIPS32:
14984 file_mips_isa = ISA_MIPS32;
14987 case OPTION_MIPS32R2:
14988 file_mips_isa = ISA_MIPS32R2;
14991 case OPTION_MIPS64R2:
14992 file_mips_isa = ISA_MIPS64R2;
14995 case OPTION_MIPS64:
14996 file_mips_isa = ISA_MIPS64;
15000 mips_set_option_string (&mips_tune_string, arg);
15004 mips_set_option_string (&mips_arch_string, arg);
15008 mips_set_option_string (&mips_arch_string, "4650");
15009 mips_set_option_string (&mips_tune_string, "4650");
15012 case OPTION_NO_M4650:
15016 mips_set_option_string (&mips_arch_string, "4010");
15017 mips_set_option_string (&mips_tune_string, "4010");
15020 case OPTION_NO_M4010:
15024 mips_set_option_string (&mips_arch_string, "4100");
15025 mips_set_option_string (&mips_tune_string, "4100");
15028 case OPTION_NO_M4100:
15032 mips_set_option_string (&mips_arch_string, "3900");
15033 mips_set_option_string (&mips_tune_string, "3900");
15036 case OPTION_NO_M3900:
15039 case OPTION_MICROMIPS:
15040 if (mips_opts.mips16 == 1)
15042 as_bad (_("-mmicromips cannot be used with -mips16"));
15045 mips_opts.micromips = 1;
15046 mips_no_prev_insn ();
15049 case OPTION_NO_MICROMIPS:
15050 mips_opts.micromips = 0;
15051 mips_no_prev_insn ();
15054 case OPTION_MIPS16:
15055 if (mips_opts.micromips == 1)
15057 as_bad (_("-mips16 cannot be used with -micromips"));
15060 mips_opts.mips16 = 1;
15061 mips_no_prev_insn ();
15064 case OPTION_NO_MIPS16:
15065 mips_opts.mips16 = 0;
15066 mips_no_prev_insn ();
15069 case OPTION_FIX_24K:
15073 case OPTION_NO_FIX_24K:
15077 case OPTION_FIX_LOONGSON2F_JUMP:
15078 mips_fix_loongson2f_jump = TRUE;
15081 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15082 mips_fix_loongson2f_jump = FALSE;
15085 case OPTION_FIX_LOONGSON2F_NOP:
15086 mips_fix_loongson2f_nop = TRUE;
15089 case OPTION_NO_FIX_LOONGSON2F_NOP:
15090 mips_fix_loongson2f_nop = FALSE;
15093 case OPTION_FIX_VR4120:
15094 mips_fix_vr4120 = 1;
15097 case OPTION_NO_FIX_VR4120:
15098 mips_fix_vr4120 = 0;
15101 case OPTION_FIX_VR4130:
15102 mips_fix_vr4130 = 1;
15105 case OPTION_NO_FIX_VR4130:
15106 mips_fix_vr4130 = 0;
15109 case OPTION_FIX_CN63XXP1:
15110 mips_fix_cn63xxp1 = TRUE;
15113 case OPTION_NO_FIX_CN63XXP1:
15114 mips_fix_cn63xxp1 = FALSE;
15117 case OPTION_RELAX_BRANCH:
15118 mips_relax_branch = 1;
15121 case OPTION_NO_RELAX_BRANCH:
15122 mips_relax_branch = 0;
15125 case OPTION_INSN32:
15126 mips_opts.insn32 = TRUE;
15129 case OPTION_NO_INSN32:
15130 mips_opts.insn32 = FALSE;
15133 case OPTION_MSHARED:
15134 mips_in_shared = TRUE;
15137 case OPTION_MNO_SHARED:
15138 mips_in_shared = FALSE;
15141 case OPTION_MSYM32:
15142 mips_opts.sym32 = TRUE;
15145 case OPTION_MNO_SYM32:
15146 mips_opts.sym32 = FALSE;
15149 /* When generating ELF code, we permit -KPIC and -call_shared to
15150 select SVR4_PIC, and -non_shared to select no PIC. This is
15151 intended to be compatible with Irix 5. */
15152 case OPTION_CALL_SHARED:
15153 mips_pic = SVR4_PIC;
15154 mips_abicalls = TRUE;
15157 case OPTION_CALL_NONPIC:
15159 mips_abicalls = TRUE;
15162 case OPTION_NON_SHARED:
15164 mips_abicalls = FALSE;
15167 /* The -xgot option tells the assembler to use 32 bit offsets
15168 when accessing the got in SVR4_PIC mode. It is for Irix
15175 g_switch_value = atoi (arg);
15179 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15182 mips_abi = O32_ABI;
15186 mips_abi = N32_ABI;
15190 mips_abi = N64_ABI;
15191 if (!support_64bit_objects())
15192 as_fatal (_("No compiled in support for 64 bit object file format"));
15196 file_mips_gp32 = 1;
15200 file_mips_gp32 = 0;
15204 file_mips_fp32 = 1;
15208 file_mips_fp32 = 0;
15211 case OPTION_SINGLE_FLOAT:
15212 file_mips_single_float = 1;
15215 case OPTION_DOUBLE_FLOAT:
15216 file_mips_single_float = 0;
15219 case OPTION_SOFT_FLOAT:
15220 file_mips_soft_float = 1;
15223 case OPTION_HARD_FLOAT:
15224 file_mips_soft_float = 0;
15228 if (strcmp (arg, "32") == 0)
15229 mips_abi = O32_ABI;
15230 else if (strcmp (arg, "o64") == 0)
15231 mips_abi = O64_ABI;
15232 else if (strcmp (arg, "n32") == 0)
15233 mips_abi = N32_ABI;
15234 else if (strcmp (arg, "64") == 0)
15236 mips_abi = N64_ABI;
15237 if (! support_64bit_objects())
15238 as_fatal (_("No compiled in support for 64 bit object file "
15241 else if (strcmp (arg, "eabi") == 0)
15242 mips_abi = EABI_ABI;
15245 as_fatal (_("invalid abi -mabi=%s"), arg);
15250 case OPTION_M7000_HILO_FIX:
15251 mips_7000_hilo_fix = TRUE;
15254 case OPTION_MNO_7000_HILO_FIX:
15255 mips_7000_hilo_fix = FALSE;
15258 case OPTION_MDEBUG:
15259 mips_flag_mdebug = TRUE;
15262 case OPTION_NO_MDEBUG:
15263 mips_flag_mdebug = FALSE;
15267 mips_flag_pdr = TRUE;
15270 case OPTION_NO_PDR:
15271 mips_flag_pdr = FALSE;
15274 case OPTION_MVXWORKS_PIC:
15275 mips_pic = VXWORKS_PIC;
15279 if (strcmp (arg, "2008") == 0)
15280 mips_flag_nan2008 = TRUE;
15281 else if (strcmp (arg, "legacy") == 0)
15282 mips_flag_nan2008 = FALSE;
15285 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
15294 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15299 /* Set up globals to generate code for the ISA or processor
15300 described by INFO. */
15303 mips_set_architecture (const struct mips_cpu_info *info)
15307 file_mips_arch = info->cpu;
15308 mips_opts.arch = info->cpu;
15309 mips_opts.isa = info->isa;
15314 /* Likewise for tuning. */
15317 mips_set_tune (const struct mips_cpu_info *info)
15320 mips_tune = info->cpu;
15325 mips_after_parse_args (void)
15327 const struct mips_cpu_info *arch_info = 0;
15328 const struct mips_cpu_info *tune_info = 0;
15330 /* GP relative stuff not working for PE */
15331 if (strncmp (TARGET_OS, "pe", 2) == 0)
15333 if (g_switch_seen && g_switch_value != 0)
15334 as_bad (_("-G not supported in this configuration."));
15335 g_switch_value = 0;
15338 if (mips_abi == NO_ABI)
15339 mips_abi = MIPS_DEFAULT_ABI;
15341 /* The following code determines the architecture and register size.
15342 Similar code was added to GCC 3.3 (see override_options() in
15343 config/mips/mips.c). The GAS and GCC code should be kept in sync
15344 as much as possible. */
15346 if (mips_arch_string != 0)
15347 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15349 if (file_mips_isa != ISA_UNKNOWN)
15351 /* Handle -mipsN. At this point, file_mips_isa contains the
15352 ISA level specified by -mipsN, while arch_info->isa contains
15353 the -march selection (if any). */
15354 if (arch_info != 0)
15356 /* -march takes precedence over -mipsN, since it is more descriptive.
15357 There's no harm in specifying both as long as the ISA levels
15359 if (file_mips_isa != arch_info->isa)
15360 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15361 mips_cpu_info_from_isa (file_mips_isa)->name,
15362 mips_cpu_info_from_isa (arch_info->isa)->name);
15365 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15368 if (arch_info == 0)
15370 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15371 gas_assert (arch_info);
15374 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15375 as_bad (_("-march=%s is not compatible with the selected ABI"),
15378 mips_set_architecture (arch_info);
15380 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15381 if (mips_tune_string != 0)
15382 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15384 if (tune_info == 0)
15385 mips_set_tune (arch_info);
15387 mips_set_tune (tune_info);
15389 if (file_mips_gp32 >= 0)
15391 /* The user specified the size of the integer registers. Make sure
15392 it agrees with the ABI and ISA. */
15393 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15394 as_bad (_("-mgp64 used with a 32-bit processor"));
15395 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15396 as_bad (_("-mgp32 used with a 64-bit ABI"));
15397 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15398 as_bad (_("-mgp64 used with a 32-bit ABI"));
15402 /* Infer the integer register size from the ABI and processor.
15403 Restrict ourselves to 32-bit registers if that's all the
15404 processor has, or if the ABI cannot handle 64-bit registers. */
15405 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15406 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15409 switch (file_mips_fp32)
15413 /* No user specified float register size.
15414 ??? GAS treats single-float processors as though they had 64-bit
15415 float registers (although it complains when double-precision
15416 instructions are used). As things stand, saying they have 32-bit
15417 registers would lead to spurious "register must be even" messages.
15418 So here we assume float registers are never smaller than the
15420 if (file_mips_gp32 == 0)
15421 /* 64-bit integer registers implies 64-bit float registers. */
15422 file_mips_fp32 = 0;
15423 else if ((mips_opts.ase & FP64_ASES)
15424 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15425 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15426 file_mips_fp32 = 0;
15428 /* 32-bit float registers. */
15429 file_mips_fp32 = 1;
15432 /* The user specified the size of the float registers. Check if it
15433 agrees with the ABI and ISA. */
15435 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15436 as_bad (_("-mfp64 used with a 32-bit fpu"));
15437 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15438 && !ISA_HAS_MXHC1 (mips_opts.isa))
15439 as_warn (_("-mfp64 used with a 32-bit ABI"));
15442 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15443 as_warn (_("-mfp32 used with a 64-bit ABI"));
15447 /* End of GCC-shared inference code. */
15449 /* This flag is set when we have a 64-bit capable CPU but use only
15450 32-bit wide registers. Note that EABI does not use it. */
15451 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15452 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15453 || mips_abi == O32_ABI))
15454 mips_32bitmode = 1;
15456 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15457 as_bad (_("trap exception not supported at ISA 1"));
15459 /* If the selected architecture includes support for ASEs, enable
15460 generation of code for them. */
15461 if (mips_opts.mips16 == -1)
15462 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15463 if (mips_opts.micromips == -1)
15464 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15466 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15467 ASEs from being selected implicitly. */
15468 if (file_mips_fp32 == 1)
15469 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15471 /* If the user didn't explicitly select or deselect a particular ASE,
15472 use the default setting for the CPU. */
15473 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15475 file_mips_isa = mips_opts.isa;
15476 file_ase = mips_opts.ase;
15477 mips_opts.gp32 = file_mips_gp32;
15478 mips_opts.fp32 = file_mips_fp32;
15479 mips_opts.soft_float = file_mips_soft_float;
15480 mips_opts.single_float = file_mips_single_float;
15482 mips_check_isa_supports_ases ();
15484 if (mips_flag_mdebug < 0)
15485 mips_flag_mdebug = 0;
15489 mips_init_after_args (void)
15491 /* initialize opcodes */
15492 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15493 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15497 md_pcrel_from (fixS *fixP)
15499 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15500 switch (fixP->fx_r_type)
15502 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15503 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15504 /* Return the address of the delay slot. */
15507 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15508 case BFD_RELOC_MICROMIPS_JMP:
15509 case BFD_RELOC_16_PCREL_S2:
15510 case BFD_RELOC_MIPS_JMP:
15511 /* Return the address of the delay slot. */
15514 case BFD_RELOC_32_PCREL:
15518 /* We have no relocation type for PC relative MIPS16 instructions. */
15519 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15520 as_bad_where (fixP->fx_file, fixP->fx_line,
15521 _("PC relative MIPS16 instruction references a different section"));
15526 /* This is called before the symbol table is processed. In order to
15527 work with gcc when using mips-tfile, we must keep all local labels.
15528 However, in other cases, we want to discard them. If we were
15529 called with -g, but we didn't see any debugging information, it may
15530 mean that gcc is smuggling debugging information through to
15531 mips-tfile, in which case we must generate all local labels. */
15534 mips_frob_file_before_adjust (void)
15536 #ifndef NO_ECOFF_DEBUGGING
15537 if (ECOFF_DEBUGGING
15539 && ! ecoff_debugging_seen)
15540 flag_keep_locals = 1;
15544 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15545 the corresponding LO16 reloc. This is called before md_apply_fix and
15546 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15547 relocation operators.
15549 For our purposes, a %lo() expression matches a %got() or %hi()
15552 (a) it refers to the same symbol; and
15553 (b) the offset applied in the %lo() expression is no lower than
15554 the offset applied in the %got() or %hi().
15556 (b) allows us to cope with code like:
15559 lh $4,%lo(foo+2)($4)
15561 ...which is legal on RELA targets, and has a well-defined behaviour
15562 if the user knows that adding 2 to "foo" will not induce a carry to
15565 When several %lo()s match a particular %got() or %hi(), we use the
15566 following rules to distinguish them:
15568 (1) %lo()s with smaller offsets are a better match than %lo()s with
15571 (2) %lo()s with no matching %got() or %hi() are better than those
15572 that already have a matching %got() or %hi().
15574 (3) later %lo()s are better than earlier %lo()s.
15576 These rules are applied in order.
15578 (1) means, among other things, that %lo()s with identical offsets are
15579 chosen if they exist.
15581 (2) means that we won't associate several high-part relocations with
15582 the same low-part relocation unless there's no alternative. Having
15583 several high parts for the same low part is a GNU extension; this rule
15584 allows careful users to avoid it.
15586 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15587 with the last high-part relocation being at the front of the list.
15588 It therefore makes sense to choose the last matching low-part
15589 relocation, all other things being equal. It's also easier
15590 to code that way. */
15593 mips_frob_file (void)
15595 struct mips_hi_fixup *l;
15596 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15598 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15600 segment_info_type *seginfo;
15601 bfd_boolean matched_lo_p;
15602 fixS **hi_pos, **lo_pos, **pos;
15604 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15606 /* If a GOT16 relocation turns out to be against a global symbol,
15607 there isn't supposed to be a matching LO. Ignore %gots against
15608 constants; we'll report an error for those later. */
15609 if (got16_reloc_p (l->fixp->fx_r_type)
15610 && !(l->fixp->fx_addsy
15611 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15614 /* Check quickly whether the next fixup happens to be a matching %lo. */
15615 if (fixup_has_matching_lo_p (l->fixp))
15618 seginfo = seg_info (l->seg);
15620 /* Set HI_POS to the position of this relocation in the chain.
15621 Set LO_POS to the position of the chosen low-part relocation.
15622 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15623 relocation that matches an immediately-preceding high-part
15627 matched_lo_p = FALSE;
15628 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15630 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15632 if (*pos == l->fixp)
15635 if ((*pos)->fx_r_type == looking_for_rtype
15636 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15637 && (*pos)->fx_offset >= l->fixp->fx_offset
15639 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15641 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15644 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15645 && fixup_has_matching_lo_p (*pos));
15648 /* If we found a match, remove the high-part relocation from its
15649 current position and insert it before the low-part relocation.
15650 Make the offsets match so that fixup_has_matching_lo_p()
15653 We don't warn about unmatched high-part relocations since some
15654 versions of gcc have been known to emit dead "lui ...%hi(...)"
15656 if (lo_pos != NULL)
15658 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15659 if (l->fixp->fx_next != *lo_pos)
15661 *hi_pos = l->fixp->fx_next;
15662 l->fixp->fx_next = *lo_pos;
15670 mips_force_relocation (fixS *fixp)
15672 if (generic_force_reloc (fixp))
15675 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15676 so that the linker relaxation can update targets. */
15677 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15678 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15679 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15685 /* Read the instruction associated with RELOC from BUF. */
15687 static unsigned int
15688 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15690 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15691 return read_compressed_insn (buf, 4);
15693 return read_insn (buf);
15696 /* Write instruction INSN to BUF, given that it has been relocated
15700 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15701 unsigned long insn)
15703 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15704 write_compressed_insn (buf, insn, 4);
15706 write_insn (buf, insn);
15709 /* Apply a fixup to the object file. */
15712 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15715 unsigned long insn;
15716 reloc_howto_type *howto;
15718 /* We ignore generic BFD relocations we don't know about. */
15719 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15723 gas_assert (fixP->fx_size == 2
15724 || fixP->fx_size == 4
15725 || fixP->fx_r_type == BFD_RELOC_16
15726 || fixP->fx_r_type == BFD_RELOC_64
15727 || fixP->fx_r_type == BFD_RELOC_CTOR
15728 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15729 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15730 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15731 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15732 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15734 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15736 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15737 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15738 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15739 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15740 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15742 /* Don't treat parts of a composite relocation as done. There are two
15745 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15746 should nevertheless be emitted if the first part is.
15748 (2) In normal usage, composite relocations are never assembly-time
15749 constants. The easiest way of dealing with the pathological
15750 exceptions is to generate a relocation against STN_UNDEF and
15751 leave everything up to the linker. */
15752 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15755 switch (fixP->fx_r_type)
15757 case BFD_RELOC_MIPS_TLS_GD:
15758 case BFD_RELOC_MIPS_TLS_LDM:
15759 case BFD_RELOC_MIPS_TLS_DTPREL32:
15760 case BFD_RELOC_MIPS_TLS_DTPREL64:
15761 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15762 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15763 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15764 case BFD_RELOC_MIPS_TLS_TPREL32:
15765 case BFD_RELOC_MIPS_TLS_TPREL64:
15766 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15767 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15768 case BFD_RELOC_MICROMIPS_TLS_GD:
15769 case BFD_RELOC_MICROMIPS_TLS_LDM:
15770 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15771 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15772 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15773 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15774 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15775 case BFD_RELOC_MIPS16_TLS_GD:
15776 case BFD_RELOC_MIPS16_TLS_LDM:
15777 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15778 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15779 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15780 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15781 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15782 if (!fixP->fx_addsy)
15784 as_bad_where (fixP->fx_file, fixP->fx_line,
15785 _("TLS relocation against a constant"));
15788 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15791 case BFD_RELOC_MIPS_JMP:
15792 case BFD_RELOC_MIPS_SHIFT5:
15793 case BFD_RELOC_MIPS_SHIFT6:
15794 case BFD_RELOC_MIPS_GOT_DISP:
15795 case BFD_RELOC_MIPS_GOT_PAGE:
15796 case BFD_RELOC_MIPS_GOT_OFST:
15797 case BFD_RELOC_MIPS_SUB:
15798 case BFD_RELOC_MIPS_INSERT_A:
15799 case BFD_RELOC_MIPS_INSERT_B:
15800 case BFD_RELOC_MIPS_DELETE:
15801 case BFD_RELOC_MIPS_HIGHEST:
15802 case BFD_RELOC_MIPS_HIGHER:
15803 case BFD_RELOC_MIPS_SCN_DISP:
15804 case BFD_RELOC_MIPS_REL16:
15805 case BFD_RELOC_MIPS_RELGOT:
15806 case BFD_RELOC_MIPS_JALR:
15807 case BFD_RELOC_HI16:
15808 case BFD_RELOC_HI16_S:
15809 case BFD_RELOC_LO16:
15810 case BFD_RELOC_GPREL16:
15811 case BFD_RELOC_MIPS_LITERAL:
15812 case BFD_RELOC_MIPS_CALL16:
15813 case BFD_RELOC_MIPS_GOT16:
15814 case BFD_RELOC_GPREL32:
15815 case BFD_RELOC_MIPS_GOT_HI16:
15816 case BFD_RELOC_MIPS_GOT_LO16:
15817 case BFD_RELOC_MIPS_CALL_HI16:
15818 case BFD_RELOC_MIPS_CALL_LO16:
15819 case BFD_RELOC_MIPS16_GPREL:
15820 case BFD_RELOC_MIPS16_GOT16:
15821 case BFD_RELOC_MIPS16_CALL16:
15822 case BFD_RELOC_MIPS16_HI16:
15823 case BFD_RELOC_MIPS16_HI16_S:
15824 case BFD_RELOC_MIPS16_LO16:
15825 case BFD_RELOC_MIPS16_JMP:
15826 case BFD_RELOC_MICROMIPS_JMP:
15827 case BFD_RELOC_MICROMIPS_GOT_DISP:
15828 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15829 case BFD_RELOC_MICROMIPS_GOT_OFST:
15830 case BFD_RELOC_MICROMIPS_SUB:
15831 case BFD_RELOC_MICROMIPS_HIGHEST:
15832 case BFD_RELOC_MICROMIPS_HIGHER:
15833 case BFD_RELOC_MICROMIPS_SCN_DISP:
15834 case BFD_RELOC_MICROMIPS_JALR:
15835 case BFD_RELOC_MICROMIPS_HI16:
15836 case BFD_RELOC_MICROMIPS_HI16_S:
15837 case BFD_RELOC_MICROMIPS_LO16:
15838 case BFD_RELOC_MICROMIPS_GPREL16:
15839 case BFD_RELOC_MICROMIPS_LITERAL:
15840 case BFD_RELOC_MICROMIPS_CALL16:
15841 case BFD_RELOC_MICROMIPS_GOT16:
15842 case BFD_RELOC_MICROMIPS_GOT_HI16:
15843 case BFD_RELOC_MICROMIPS_GOT_LO16:
15844 case BFD_RELOC_MICROMIPS_CALL_HI16:
15845 case BFD_RELOC_MICROMIPS_CALL_LO16:
15846 case BFD_RELOC_MIPS_EH:
15851 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15853 insn = read_reloc_insn (buf, fixP->fx_r_type);
15854 if (mips16_reloc_p (fixP->fx_r_type))
15855 insn |= mips16_immed_extend (value, 16);
15857 insn |= (value & 0xffff);
15858 write_reloc_insn (buf, fixP->fx_r_type, insn);
15861 as_bad_where (fixP->fx_file, fixP->fx_line,
15862 _("Unsupported constant in relocation"));
15867 /* This is handled like BFD_RELOC_32, but we output a sign
15868 extended value if we are only 32 bits. */
15871 if (8 <= sizeof (valueT))
15872 md_number_to_chars (buf, *valP, 8);
15877 if ((*valP & 0x80000000) != 0)
15881 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15882 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15887 case BFD_RELOC_RVA:
15889 case BFD_RELOC_32_PCREL:
15891 /* If we are deleting this reloc entry, we must fill in the
15892 value now. This can happen if we have a .word which is not
15893 resolved when it appears but is later defined. */
15895 md_number_to_chars (buf, *valP, fixP->fx_size);
15898 case BFD_RELOC_16_PCREL_S2:
15899 if ((*valP & 0x3) != 0)
15900 as_bad_where (fixP->fx_file, fixP->fx_line,
15901 _("Branch to misaligned address (%lx)"), (long) *valP);
15903 /* We need to save the bits in the instruction since fixup_segment()
15904 might be deleting the relocation entry (i.e., a branch within
15905 the current segment). */
15906 if (! fixP->fx_done)
15909 /* Update old instruction data. */
15910 insn = read_insn (buf);
15912 if (*valP + 0x20000 <= 0x3ffff)
15914 insn |= (*valP >> 2) & 0xffff;
15915 write_insn (buf, insn);
15917 else if (mips_pic == NO_PIC
15919 && fixP->fx_frag->fr_address >= text_section->vma
15920 && (fixP->fx_frag->fr_address
15921 < text_section->vma + bfd_get_section_size (text_section))
15922 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15923 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15924 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15926 /* The branch offset is too large. If this is an
15927 unconditional branch, and we are not generating PIC code,
15928 we can convert it to an absolute jump instruction. */
15929 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15930 insn = 0x0c000000; /* jal */
15932 insn = 0x08000000; /* j */
15933 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15935 fixP->fx_addsy = section_symbol (text_section);
15936 *valP += md_pcrel_from (fixP);
15937 write_insn (buf, insn);
15941 /* If we got here, we have branch-relaxation disabled,
15942 and there's nothing we can do to fix this instruction
15943 without turning it into a longer sequence. */
15944 as_bad_where (fixP->fx_file, fixP->fx_line,
15945 _("Branch out of range"));
15949 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15950 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15951 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15952 /* We adjust the offset back to even. */
15953 if ((*valP & 0x1) != 0)
15956 if (! fixP->fx_done)
15959 /* Should never visit here, because we keep the relocation. */
15963 case BFD_RELOC_VTABLE_INHERIT:
15966 && !S_IS_DEFINED (fixP->fx_addsy)
15967 && !S_IS_WEAK (fixP->fx_addsy))
15968 S_SET_WEAK (fixP->fx_addsy);
15971 case BFD_RELOC_VTABLE_ENTRY:
15979 /* Remember value for tc_gen_reloc. */
15980 fixP->fx_addnumber = *valP;
15990 name = input_line_pointer;
15991 c = get_symbol_end ();
15992 p = (symbolS *) symbol_find_or_make (name);
15993 *input_line_pointer = c;
15997 /* Align the current frag to a given power of two. If a particular
15998 fill byte should be used, FILL points to an integer that contains
15999 that byte, otherwise FILL is null.
16001 This function used to have the comment:
16003 The MIPS assembler also automatically adjusts any preceding label.
16005 The implementation therefore applied the adjustment to a maximum of
16006 one label. However, other label adjustments are applied to batches
16007 of labels, and adjusting just one caused problems when new labels
16008 were added for the sake of debugging or unwind information.
16009 We therefore adjust all preceding labels (given as LABELS) instead. */
16012 mips_align (int to, int *fill, struct insn_label_list *labels)
16014 mips_emit_delays ();
16015 mips_record_compressed_mode ();
16016 if (fill == NULL && subseg_text_p (now_seg))
16017 frag_align_code (to, 0);
16019 frag_align (to, fill ? *fill : 0, 0);
16020 record_alignment (now_seg, to);
16021 mips_move_labels (labels, FALSE);
16024 /* Align to a given power of two. .align 0 turns off the automatic
16025 alignment used by the data creating pseudo-ops. */
16028 s_align (int x ATTRIBUTE_UNUSED)
16030 int temp, fill_value, *fill_ptr;
16031 long max_alignment = 28;
16033 /* o Note that the assembler pulls down any immediately preceding label
16034 to the aligned address.
16035 o It's not documented but auto alignment is reinstated by
16036 a .align pseudo instruction.
16037 o Note also that after auto alignment is turned off the mips assembler
16038 issues an error on attempt to assemble an improperly aligned data item.
16041 temp = get_absolute_expression ();
16042 if (temp > max_alignment)
16043 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16046 as_warn (_("Alignment negative: 0 assumed."));
16049 if (*input_line_pointer == ',')
16051 ++input_line_pointer;
16052 fill_value = get_absolute_expression ();
16053 fill_ptr = &fill_value;
16059 segment_info_type *si = seg_info (now_seg);
16060 struct insn_label_list *l = si->label_list;
16061 /* Auto alignment should be switched on by next section change. */
16063 mips_align (temp, fill_ptr, l);
16070 demand_empty_rest_of_line ();
16074 s_change_sec (int sec)
16078 /* The ELF backend needs to know that we are changing sections, so
16079 that .previous works correctly. We could do something like check
16080 for an obj_section_change_hook macro, but that might be confusing
16081 as it would not be appropriate to use it in the section changing
16082 functions in read.c, since obj-elf.c intercepts those. FIXME:
16083 This should be cleaner, somehow. */
16084 obj_elf_section_change_hook ();
16086 mips_emit_delays ();
16097 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16098 demand_empty_rest_of_line ();
16102 seg = subseg_new (RDATA_SECTION_NAME,
16103 (subsegT) get_absolute_expression ());
16104 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16105 | SEC_READONLY | SEC_RELOC
16107 if (strncmp (TARGET_OS, "elf", 3) != 0)
16108 record_alignment (seg, 4);
16109 demand_empty_rest_of_line ();
16113 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16114 bfd_set_section_flags (stdoutput, seg,
16115 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16116 if (strncmp (TARGET_OS, "elf", 3) != 0)
16117 record_alignment (seg, 4);
16118 demand_empty_rest_of_line ();
16122 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16123 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16124 if (strncmp (TARGET_OS, "elf", 3) != 0)
16125 record_alignment (seg, 4);
16126 demand_empty_rest_of_line ();
16134 s_change_section (int ignore ATTRIBUTE_UNUSED)
16136 char *section_name;
16141 int section_entry_size;
16142 int section_alignment;
16144 section_name = input_line_pointer;
16145 c = get_symbol_end ();
16147 next_c = *(input_line_pointer + 1);
16149 /* Do we have .section Name<,"flags">? */
16150 if (c != ',' || (c == ',' && next_c == '"'))
16152 /* just after name is now '\0'. */
16153 *input_line_pointer = c;
16154 input_line_pointer = section_name;
16155 obj_elf_section (ignore);
16158 input_line_pointer++;
16160 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16162 section_type = get_absolute_expression ();
16165 if (*input_line_pointer++ == ',')
16166 section_flag = get_absolute_expression ();
16169 if (*input_line_pointer++ == ',')
16170 section_entry_size = get_absolute_expression ();
16172 section_entry_size = 0;
16173 if (*input_line_pointer++ == ',')
16174 section_alignment = get_absolute_expression ();
16176 section_alignment = 0;
16177 /* FIXME: really ignore? */
16178 (void) section_alignment;
16180 section_name = xstrdup (section_name);
16182 /* When using the generic form of .section (as implemented by obj-elf.c),
16183 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16184 traditionally had to fall back on the more common @progbits instead.
16186 There's nothing really harmful in this, since bfd will correct
16187 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16188 means that, for backwards compatibility, the special_section entries
16189 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16191 Even so, we shouldn't force users of the MIPS .section syntax to
16192 incorrectly label the sections as SHT_PROGBITS. The best compromise
16193 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16194 generic type-checking code. */
16195 if (section_type == SHT_MIPS_DWARF)
16196 section_type = SHT_PROGBITS;
16198 obj_elf_change_section (section_name, section_type, section_flag,
16199 section_entry_size, 0, 0, 0);
16201 if (now_seg->name != section_name)
16202 free (section_name);
16206 mips_enable_auto_align (void)
16212 s_cons (int log_size)
16214 segment_info_type *si = seg_info (now_seg);
16215 struct insn_label_list *l = si->label_list;
16217 mips_emit_delays ();
16218 if (log_size > 0 && auto_align)
16219 mips_align (log_size, 0, l);
16220 cons (1 << log_size);
16221 mips_clear_insn_labels ();
16225 s_float_cons (int type)
16227 segment_info_type *si = seg_info (now_seg);
16228 struct insn_label_list *l = si->label_list;
16230 mips_emit_delays ();
16235 mips_align (3, 0, l);
16237 mips_align (2, 0, l);
16241 mips_clear_insn_labels ();
16244 /* Handle .globl. We need to override it because on Irix 5 you are
16247 where foo is an undefined symbol, to mean that foo should be
16248 considered to be the address of a function. */
16251 s_mips_globl (int x ATTRIBUTE_UNUSED)
16260 name = input_line_pointer;
16261 c = get_symbol_end ();
16262 symbolP = symbol_find_or_make (name);
16263 S_SET_EXTERNAL (symbolP);
16265 *input_line_pointer = c;
16266 SKIP_WHITESPACE ();
16268 /* On Irix 5, every global symbol that is not explicitly labelled as
16269 being a function is apparently labelled as being an object. */
16272 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16273 && (*input_line_pointer != ','))
16278 secname = input_line_pointer;
16279 c = get_symbol_end ();
16280 sec = bfd_get_section_by_name (stdoutput, secname);
16282 as_bad (_("%s: no such section"), secname);
16283 *input_line_pointer = c;
16285 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16286 flag = BSF_FUNCTION;
16289 symbol_get_bfdsym (symbolP)->flags |= flag;
16291 c = *input_line_pointer;
16294 input_line_pointer++;
16295 SKIP_WHITESPACE ();
16296 if (is_end_of_line[(unsigned char) *input_line_pointer])
16302 demand_empty_rest_of_line ();
16306 s_option (int x ATTRIBUTE_UNUSED)
16311 opt = input_line_pointer;
16312 c = get_symbol_end ();
16316 /* FIXME: What does this mean? */
16318 else if (strncmp (opt, "pic", 3) == 0)
16322 i = atoi (opt + 3);
16327 mips_pic = SVR4_PIC;
16328 mips_abicalls = TRUE;
16331 as_bad (_(".option pic%d not supported"), i);
16333 if (mips_pic == SVR4_PIC)
16335 if (g_switch_seen && g_switch_value != 0)
16336 as_warn (_("-G may not be used with SVR4 PIC code"));
16337 g_switch_value = 0;
16338 bfd_set_gp_size (stdoutput, 0);
16342 as_warn (_("Unrecognized option \"%s\""), opt);
16344 *input_line_pointer = c;
16345 demand_empty_rest_of_line ();
16348 /* This structure is used to hold a stack of .set values. */
16350 struct mips_option_stack
16352 struct mips_option_stack *next;
16353 struct mips_set_options options;
16356 static struct mips_option_stack *mips_opts_stack;
16358 /* Handle the .set pseudo-op. */
16361 s_mipsset (int x ATTRIBUTE_UNUSED)
16363 char *name = input_line_pointer, ch;
16364 const struct mips_ase *ase;
16366 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16367 ++input_line_pointer;
16368 ch = *input_line_pointer;
16369 *input_line_pointer = '\0';
16371 if (strcmp (name, "reorder") == 0)
16373 if (mips_opts.noreorder)
16376 else if (strcmp (name, "noreorder") == 0)
16378 if (!mips_opts.noreorder)
16379 start_noreorder ();
16381 else if (strncmp (name, "at=", 3) == 0)
16383 char *s = name + 3;
16385 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16386 as_bad (_("Unrecognized register name `%s'"), s);
16388 else if (strcmp (name, "at") == 0)
16390 mips_opts.at = ATREG;
16392 else if (strcmp (name, "noat") == 0)
16394 mips_opts.at = ZERO;
16396 else if (strcmp (name, "macro") == 0)
16398 mips_opts.warn_about_macros = 0;
16400 else if (strcmp (name, "nomacro") == 0)
16402 if (mips_opts.noreorder == 0)
16403 as_bad (_("`noreorder' must be set before `nomacro'"));
16404 mips_opts.warn_about_macros = 1;
16406 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16408 mips_opts.nomove = 0;
16410 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16412 mips_opts.nomove = 1;
16414 else if (strcmp (name, "bopt") == 0)
16416 mips_opts.nobopt = 0;
16418 else if (strcmp (name, "nobopt") == 0)
16420 mips_opts.nobopt = 1;
16422 else if (strcmp (name, "gp=default") == 0)
16423 mips_opts.gp32 = file_mips_gp32;
16424 else if (strcmp (name, "gp=32") == 0)
16425 mips_opts.gp32 = 1;
16426 else if (strcmp (name, "gp=64") == 0)
16428 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16429 as_warn (_("%s isa does not support 64-bit registers"),
16430 mips_cpu_info_from_isa (mips_opts.isa)->name);
16431 mips_opts.gp32 = 0;
16433 else if (strcmp (name, "fp=default") == 0)
16434 mips_opts.fp32 = file_mips_fp32;
16435 else if (strcmp (name, "fp=32") == 0)
16436 mips_opts.fp32 = 1;
16437 else if (strcmp (name, "fp=64") == 0)
16439 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16440 as_warn (_("%s isa does not support 64-bit floating point registers"),
16441 mips_cpu_info_from_isa (mips_opts.isa)->name);
16442 mips_opts.fp32 = 0;
16444 else if (strcmp (name, "softfloat") == 0)
16445 mips_opts.soft_float = 1;
16446 else if (strcmp (name, "hardfloat") == 0)
16447 mips_opts.soft_float = 0;
16448 else if (strcmp (name, "singlefloat") == 0)
16449 mips_opts.single_float = 1;
16450 else if (strcmp (name, "doublefloat") == 0)
16451 mips_opts.single_float = 0;
16452 else if (strcmp (name, "mips16") == 0
16453 || strcmp (name, "MIPS-16") == 0)
16455 if (mips_opts.micromips == 1)
16456 as_fatal (_("`mips16' cannot be used with `micromips'"));
16457 mips_opts.mips16 = 1;
16459 else if (strcmp (name, "nomips16") == 0
16460 || strcmp (name, "noMIPS-16") == 0)
16461 mips_opts.mips16 = 0;
16462 else if (strcmp (name, "micromips") == 0)
16464 if (mips_opts.mips16 == 1)
16465 as_fatal (_("`micromips' cannot be used with `mips16'"));
16466 mips_opts.micromips = 1;
16468 else if (strcmp (name, "nomicromips") == 0)
16469 mips_opts.micromips = 0;
16470 else if (name[0] == 'n'
16472 && (ase = mips_lookup_ase (name + 2)))
16473 mips_set_ase (ase, FALSE);
16474 else if ((ase = mips_lookup_ase (name)))
16475 mips_set_ase (ase, TRUE);
16476 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16480 /* Permit the user to change the ISA and architecture on the fly.
16481 Needless to say, misuse can cause serious problems. */
16482 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16485 mips_opts.isa = file_mips_isa;
16486 mips_opts.arch = file_mips_arch;
16488 else if (strncmp (name, "arch=", 5) == 0)
16490 const struct mips_cpu_info *p;
16492 p = mips_parse_cpu("internal use", name + 5);
16494 as_bad (_("unknown architecture %s"), name + 5);
16497 mips_opts.arch = p->cpu;
16498 mips_opts.isa = p->isa;
16501 else if (strncmp (name, "mips", 4) == 0)
16503 const struct mips_cpu_info *p;
16505 p = mips_parse_cpu("internal use", name);
16507 as_bad (_("unknown ISA level %s"), name + 4);
16510 mips_opts.arch = p->cpu;
16511 mips_opts.isa = p->isa;
16515 as_bad (_("unknown ISA or architecture %s"), name);
16517 switch (mips_opts.isa)
16525 mips_opts.gp32 = 1;
16526 mips_opts.fp32 = 1;
16533 mips_opts.gp32 = 0;
16534 if (mips_opts.arch == CPU_R5900)
16536 mips_opts.fp32 = 1;
16540 mips_opts.fp32 = 0;
16544 as_bad (_("unknown ISA level %s"), name + 4);
16549 mips_opts.gp32 = file_mips_gp32;
16550 mips_opts.fp32 = file_mips_fp32;
16553 else if (strcmp (name, "autoextend") == 0)
16554 mips_opts.noautoextend = 0;
16555 else if (strcmp (name, "noautoextend") == 0)
16556 mips_opts.noautoextend = 1;
16557 else if (strcmp (name, "insn32") == 0)
16558 mips_opts.insn32 = TRUE;
16559 else if (strcmp (name, "noinsn32") == 0)
16560 mips_opts.insn32 = FALSE;
16561 else if (strcmp (name, "push") == 0)
16563 struct mips_option_stack *s;
16565 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16566 s->next = mips_opts_stack;
16567 s->options = mips_opts;
16568 mips_opts_stack = s;
16570 else if (strcmp (name, "pop") == 0)
16572 struct mips_option_stack *s;
16574 s = mips_opts_stack;
16576 as_bad (_(".set pop with no .set push"));
16579 /* If we're changing the reorder mode we need to handle
16580 delay slots correctly. */
16581 if (s->options.noreorder && ! mips_opts.noreorder)
16582 start_noreorder ();
16583 else if (! s->options.noreorder && mips_opts.noreorder)
16586 mips_opts = s->options;
16587 mips_opts_stack = s->next;
16591 else if (strcmp (name, "sym32") == 0)
16592 mips_opts.sym32 = TRUE;
16593 else if (strcmp (name, "nosym32") == 0)
16594 mips_opts.sym32 = FALSE;
16595 else if (strchr (name, ','))
16597 /* Generic ".set" directive; use the generic handler. */
16598 *input_line_pointer = ch;
16599 input_line_pointer = name;
16605 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16607 mips_check_isa_supports_ases ();
16608 *input_line_pointer = ch;
16609 demand_empty_rest_of_line ();
16612 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16613 .option pic2. It means to generate SVR4 PIC calls. */
16616 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16618 mips_pic = SVR4_PIC;
16619 mips_abicalls = TRUE;
16621 if (g_switch_seen && g_switch_value != 0)
16622 as_warn (_("-G may not be used with SVR4 PIC code"));
16623 g_switch_value = 0;
16625 bfd_set_gp_size (stdoutput, 0);
16626 demand_empty_rest_of_line ();
16629 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16630 PIC code. It sets the $gp register for the function based on the
16631 function address, which is in the register named in the argument.
16632 This uses a relocation against _gp_disp, which is handled specially
16633 by the linker. The result is:
16634 lui $gp,%hi(_gp_disp)
16635 addiu $gp,$gp,%lo(_gp_disp)
16636 addu $gp,$gp,.cpload argument
16637 The .cpload argument is normally $25 == $t9.
16639 The -mno-shared option changes this to:
16640 lui $gp,%hi(__gnu_local_gp)
16641 addiu $gp,$gp,%lo(__gnu_local_gp)
16642 and the argument is ignored. This saves an instruction, but the
16643 resulting code is not position independent; it uses an absolute
16644 address for __gnu_local_gp. Thus code assembled with -mno-shared
16645 can go into an ordinary executable, but not into a shared library. */
16648 s_cpload (int ignore ATTRIBUTE_UNUSED)
16654 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16655 .cpload is ignored. */
16656 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16662 if (mips_opts.mips16)
16664 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16665 ignore_rest_of_line ();
16669 /* .cpload should be in a .set noreorder section. */
16670 if (mips_opts.noreorder == 0)
16671 as_warn (_(".cpload not in noreorder section"));
16673 reg = tc_get_register (0);
16675 /* If we need to produce a 64-bit address, we are better off using
16676 the default instruction sequence. */
16677 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16679 ex.X_op = O_symbol;
16680 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16682 ex.X_op_symbol = NULL;
16683 ex.X_add_number = 0;
16685 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16686 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16688 mips_mark_labels ();
16689 mips_assembling_insn = TRUE;
16692 macro_build_lui (&ex, mips_gp_register);
16693 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16694 mips_gp_register, BFD_RELOC_LO16);
16696 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16697 mips_gp_register, reg);
16700 mips_assembling_insn = FALSE;
16701 demand_empty_rest_of_line ();
16704 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16705 .cpsetup $reg1, offset|$reg2, label
16707 If offset is given, this results in:
16708 sd $gp, offset($sp)
16709 lui $gp, %hi(%neg(%gp_rel(label)))
16710 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16711 daddu $gp, $gp, $reg1
16713 If $reg2 is given, this results in:
16714 daddu $reg2, $gp, $0
16715 lui $gp, %hi(%neg(%gp_rel(label)))
16716 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16717 daddu $gp, $gp, $reg1
16718 $reg1 is normally $25 == $t9.
16720 The -mno-shared option replaces the last three instructions with
16722 addiu $gp,$gp,%lo(_gp) */
16725 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16727 expressionS ex_off;
16728 expressionS ex_sym;
16731 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16732 We also need NewABI support. */
16733 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16739 if (mips_opts.mips16)
16741 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16742 ignore_rest_of_line ();
16746 reg1 = tc_get_register (0);
16747 SKIP_WHITESPACE ();
16748 if (*input_line_pointer != ',')
16750 as_bad (_("missing argument separator ',' for .cpsetup"));
16754 ++input_line_pointer;
16755 SKIP_WHITESPACE ();
16756 if (*input_line_pointer == '$')
16758 mips_cpreturn_register = tc_get_register (0);
16759 mips_cpreturn_offset = -1;
16763 mips_cpreturn_offset = get_absolute_expression ();
16764 mips_cpreturn_register = -1;
16766 SKIP_WHITESPACE ();
16767 if (*input_line_pointer != ',')
16769 as_bad (_("missing argument separator ',' for .cpsetup"));
16773 ++input_line_pointer;
16774 SKIP_WHITESPACE ();
16775 expression (&ex_sym);
16777 mips_mark_labels ();
16778 mips_assembling_insn = TRUE;
16781 if (mips_cpreturn_register == -1)
16783 ex_off.X_op = O_constant;
16784 ex_off.X_add_symbol = NULL;
16785 ex_off.X_op_symbol = NULL;
16786 ex_off.X_add_number = mips_cpreturn_offset;
16788 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16789 BFD_RELOC_LO16, SP);
16792 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16793 mips_gp_register, 0);
16795 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16797 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16798 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16801 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16802 mips_gp_register, -1, BFD_RELOC_GPREL16,
16803 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16805 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16806 mips_gp_register, reg1);
16812 ex.X_op = O_symbol;
16813 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16814 ex.X_op_symbol = NULL;
16815 ex.X_add_number = 0;
16817 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16818 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16820 macro_build_lui (&ex, mips_gp_register);
16821 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16822 mips_gp_register, BFD_RELOC_LO16);
16827 mips_assembling_insn = FALSE;
16828 demand_empty_rest_of_line ();
16832 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16834 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16835 .cplocal is ignored. */
16836 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16842 if (mips_opts.mips16)
16844 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16845 ignore_rest_of_line ();
16849 mips_gp_register = tc_get_register (0);
16850 demand_empty_rest_of_line ();
16853 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16854 offset from $sp. The offset is remembered, and after making a PIC
16855 call $gp is restored from that location. */
16858 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16862 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16863 .cprestore is ignored. */
16864 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16870 if (mips_opts.mips16)
16872 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16873 ignore_rest_of_line ();
16877 mips_cprestore_offset = get_absolute_expression ();
16878 mips_cprestore_valid = 1;
16880 ex.X_op = O_constant;
16881 ex.X_add_symbol = NULL;
16882 ex.X_op_symbol = NULL;
16883 ex.X_add_number = mips_cprestore_offset;
16885 mips_mark_labels ();
16886 mips_assembling_insn = TRUE;
16889 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16890 SP, HAVE_64BIT_ADDRESSES);
16893 mips_assembling_insn = FALSE;
16894 demand_empty_rest_of_line ();
16897 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16898 was given in the preceding .cpsetup, it results in:
16899 ld $gp, offset($sp)
16901 If a register $reg2 was given there, it results in:
16902 daddu $gp, $reg2, $0 */
16905 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16909 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16910 We also need NewABI support. */
16911 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16917 if (mips_opts.mips16)
16919 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16920 ignore_rest_of_line ();
16924 mips_mark_labels ();
16925 mips_assembling_insn = TRUE;
16928 if (mips_cpreturn_register == -1)
16930 ex.X_op = O_constant;
16931 ex.X_add_symbol = NULL;
16932 ex.X_op_symbol = NULL;
16933 ex.X_add_number = mips_cpreturn_offset;
16935 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16938 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16939 mips_cpreturn_register, 0);
16942 mips_assembling_insn = FALSE;
16943 demand_empty_rest_of_line ();
16946 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16947 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16948 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16949 debug information or MIPS16 TLS. */
16952 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16953 bfd_reloc_code_real_type rtype)
16960 if (ex.X_op != O_symbol)
16962 as_bad (_("Unsupported use of %s"), dirstr);
16963 ignore_rest_of_line ();
16966 p = frag_more (bytes);
16967 md_number_to_chars (p, 0, bytes);
16968 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16969 demand_empty_rest_of_line ();
16970 mips_clear_insn_labels ();
16973 /* Handle .dtprelword. */
16976 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16978 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16981 /* Handle .dtpreldword. */
16984 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16986 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16989 /* Handle .tprelword. */
16992 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16994 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16997 /* Handle .tpreldword. */
17000 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17002 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17005 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17006 code. It sets the offset to use in gp_rel relocations. */
17009 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17011 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17012 We also need NewABI support. */
17013 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17019 mips_gprel_offset = get_absolute_expression ();
17021 demand_empty_rest_of_line ();
17024 /* Handle the .gpword pseudo-op. This is used when generating PIC
17025 code. It generates a 32 bit GP relative reloc. */
17028 s_gpword (int ignore ATTRIBUTE_UNUSED)
17030 segment_info_type *si;
17031 struct insn_label_list *l;
17035 /* When not generating PIC code, this is treated as .word. */
17036 if (mips_pic != SVR4_PIC)
17042 si = seg_info (now_seg);
17043 l = si->label_list;
17044 mips_emit_delays ();
17046 mips_align (2, 0, l);
17049 mips_clear_insn_labels ();
17051 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17053 as_bad (_("Unsupported use of .gpword"));
17054 ignore_rest_of_line ();
17058 md_number_to_chars (p, 0, 4);
17059 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17060 BFD_RELOC_GPREL32);
17062 demand_empty_rest_of_line ();
17066 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17068 segment_info_type *si;
17069 struct insn_label_list *l;
17073 /* When not generating PIC code, this is treated as .dword. */
17074 if (mips_pic != SVR4_PIC)
17080 si = seg_info (now_seg);
17081 l = si->label_list;
17082 mips_emit_delays ();
17084 mips_align (3, 0, l);
17087 mips_clear_insn_labels ();
17089 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17091 as_bad (_("Unsupported use of .gpdword"));
17092 ignore_rest_of_line ();
17096 md_number_to_chars (p, 0, 8);
17097 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17098 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17100 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17101 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17102 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17104 demand_empty_rest_of_line ();
17107 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17108 tables. It generates a R_MIPS_EH reloc. */
17111 s_ehword (int ignore ATTRIBUTE_UNUSED)
17116 mips_emit_delays ();
17119 mips_clear_insn_labels ();
17121 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17123 as_bad (_("Unsupported use of .ehword"));
17124 ignore_rest_of_line ();
17128 md_number_to_chars (p, 0, 4);
17129 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17130 BFD_RELOC_MIPS_EH);
17132 demand_empty_rest_of_line ();
17135 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17136 tables in SVR4 PIC code. */
17139 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17143 /* This is ignored when not generating SVR4 PIC code. */
17144 if (mips_pic != SVR4_PIC)
17150 mips_mark_labels ();
17151 mips_assembling_insn = TRUE;
17153 /* Add $gp to the register named as an argument. */
17155 reg = tc_get_register (0);
17156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17159 mips_assembling_insn = FALSE;
17160 demand_empty_rest_of_line ();
17163 /* Handle the .insn pseudo-op. This marks instruction labels in
17164 mips16/micromips mode. This permits the linker to handle them specially,
17165 such as generating jalx instructions when needed. We also make
17166 them odd for the duration of the assembly, in order to generate the
17167 right sort of code. We will make them even in the adjust_symtab
17168 routine, while leaving them marked. This is convenient for the
17169 debugger and the disassembler. The linker knows to make them odd
17173 s_insn (int ignore ATTRIBUTE_UNUSED)
17175 mips_mark_labels ();
17177 demand_empty_rest_of_line ();
17180 /* Handle the .nan pseudo-op. */
17183 s_nan (int ignore ATTRIBUTE_UNUSED)
17185 static const char str_legacy[] = "legacy";
17186 static const char str_2008[] = "2008";
17189 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17191 if (i == sizeof (str_2008) - 1
17192 && memcmp (input_line_pointer, str_2008, i) == 0)
17193 mips_flag_nan2008 = TRUE;
17194 else if (i == sizeof (str_legacy) - 1
17195 && memcmp (input_line_pointer, str_legacy, i) == 0)
17196 mips_flag_nan2008 = FALSE;
17198 as_bad (_("Bad .nan directive"));
17200 input_line_pointer += i;
17201 demand_empty_rest_of_line ();
17204 /* Handle a .stab[snd] directive. Ideally these directives would be
17205 implemented in a transparent way, so that removing them would not
17206 have any effect on the generated instructions. However, s_stab
17207 internally changes the section, so in practice we need to decide
17208 now whether the preceding label marks compressed code. We do not
17209 support changing the compression mode of a label after a .stab*
17210 directive, such as in:
17216 so the current mode wins. */
17219 s_mips_stab (int type)
17221 mips_mark_labels ();
17225 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17228 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17235 name = input_line_pointer;
17236 c = get_symbol_end ();
17237 symbolP = symbol_find_or_make (name);
17238 S_SET_WEAK (symbolP);
17239 *input_line_pointer = c;
17241 SKIP_WHITESPACE ();
17243 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17245 if (S_IS_DEFINED (symbolP))
17247 as_bad (_("ignoring attempt to redefine symbol %s"),
17248 S_GET_NAME (symbolP));
17249 ignore_rest_of_line ();
17253 if (*input_line_pointer == ',')
17255 ++input_line_pointer;
17256 SKIP_WHITESPACE ();
17260 if (exp.X_op != O_symbol)
17262 as_bad (_("bad .weakext directive"));
17263 ignore_rest_of_line ();
17266 symbol_set_value_expression (symbolP, &exp);
17269 demand_empty_rest_of_line ();
17272 /* Parse a register string into a number. Called from the ECOFF code
17273 to parse .frame. The argument is non-zero if this is the frame
17274 register, so that we can record it in mips_frame_reg. */
17277 tc_get_register (int frame)
17281 SKIP_WHITESPACE ();
17282 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17286 mips_frame_reg = reg != 0 ? reg : SP;
17287 mips_frame_reg_valid = 1;
17288 mips_cprestore_valid = 0;
17294 md_section_align (asection *seg, valueT addr)
17296 int align = bfd_get_section_alignment (stdoutput, seg);
17298 /* We don't need to align ELF sections to the full alignment.
17299 However, Irix 5 may prefer that we align them at least to a 16
17300 byte boundary. We don't bother to align the sections if we
17301 are targeted for an embedded system. */
17302 if (strncmp (TARGET_OS, "elf", 3) == 0)
17307 return ((addr + (1 << align) - 1) & (-1 << align));
17310 /* Utility routine, called from above as well. If called while the
17311 input file is still being read, it's only an approximation. (For
17312 example, a symbol may later become defined which appeared to be
17313 undefined earlier.) */
17316 nopic_need_relax (symbolS *sym, int before_relaxing)
17321 if (g_switch_value > 0)
17323 const char *symname;
17326 /* Find out whether this symbol can be referenced off the $gp
17327 register. It can be if it is smaller than the -G size or if
17328 it is in the .sdata or .sbss section. Certain symbols can
17329 not be referenced off the $gp, although it appears as though
17331 symname = S_GET_NAME (sym);
17332 if (symname != (const char *) NULL
17333 && (strcmp (symname, "eprol") == 0
17334 || strcmp (symname, "etext") == 0
17335 || strcmp (symname, "_gp") == 0
17336 || strcmp (symname, "edata") == 0
17337 || strcmp (symname, "_fbss") == 0
17338 || strcmp (symname, "_fdata") == 0
17339 || strcmp (symname, "_ftext") == 0
17340 || strcmp (symname, "end") == 0
17341 || strcmp (symname, "_gp_disp") == 0))
17343 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17345 #ifndef NO_ECOFF_DEBUGGING
17346 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17347 && (symbol_get_obj (sym)->ecoff_extern_size
17348 <= g_switch_value))
17350 /* We must defer this decision until after the whole
17351 file has been read, since there might be a .extern
17352 after the first use of this symbol. */
17353 || (before_relaxing
17354 #ifndef NO_ECOFF_DEBUGGING
17355 && symbol_get_obj (sym)->ecoff_extern_size == 0
17357 && S_GET_VALUE (sym) == 0)
17358 || (S_GET_VALUE (sym) != 0
17359 && S_GET_VALUE (sym) <= g_switch_value)))
17363 const char *segname;
17365 segname = segment_name (S_GET_SEGMENT (sym));
17366 gas_assert (strcmp (segname, ".lit8") != 0
17367 && strcmp (segname, ".lit4") != 0);
17368 change = (strcmp (segname, ".sdata") != 0
17369 && strcmp (segname, ".sbss") != 0
17370 && strncmp (segname, ".sdata.", 7) != 0
17371 && strncmp (segname, ".sbss.", 6) != 0
17372 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17373 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17378 /* We are not optimizing for the $gp register. */
17383 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17386 pic_need_relax (symbolS *sym, asection *segtype)
17390 /* Handle the case of a symbol equated to another symbol. */
17391 while (symbol_equated_reloc_p (sym))
17395 /* It's possible to get a loop here in a badly written program. */
17396 n = symbol_get_value_expression (sym)->X_add_symbol;
17402 if (symbol_section_p (sym))
17405 symsec = S_GET_SEGMENT (sym);
17407 /* This must duplicate the test in adjust_reloc_syms. */
17408 return (!bfd_is_und_section (symsec)
17409 && !bfd_is_abs_section (symsec)
17410 && !bfd_is_com_section (symsec)
17411 && !s_is_linkonce (sym, segtype)
17412 /* A global or weak symbol is treated as external. */
17413 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17417 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17418 extended opcode. SEC is the section the frag is in. */
17421 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17424 const struct mips16_immed_operand *op;
17426 int mintiny, maxtiny;
17430 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17432 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17435 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17436 op = mips16_immed_operands;
17437 while (op->type != type)
17440 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17445 if (type == '<' || type == '>' || type == '[' || type == ']')
17448 maxtiny = 1 << op->nbits;
17453 maxtiny = (1 << op->nbits) - 1;
17458 mintiny = - (1 << (op->nbits - 1));
17459 maxtiny = (1 << (op->nbits - 1)) - 1;
17462 sym_frag = symbol_get_frag (fragp->fr_symbol);
17463 val = S_GET_VALUE (fragp->fr_symbol);
17464 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17470 /* We won't have the section when we are called from
17471 mips_relax_frag. However, we will always have been called
17472 from md_estimate_size_before_relax first. If this is a
17473 branch to a different section, we mark it as such. If SEC is
17474 NULL, and the frag is not marked, then it must be a branch to
17475 the same section. */
17478 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17483 /* Must have been called from md_estimate_size_before_relax. */
17486 fragp->fr_subtype =
17487 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17489 /* FIXME: We should support this, and let the linker
17490 catch branches and loads that are out of range. */
17491 as_bad_where (fragp->fr_file, fragp->fr_line,
17492 _("unsupported PC relative reference to different section"));
17496 if (fragp != sym_frag && sym_frag->fr_address == 0)
17497 /* Assume non-extended on the first relaxation pass.
17498 The address we have calculated will be bogus if this is
17499 a forward branch to another frag, as the forward frag
17500 will have fr_address == 0. */
17504 /* In this case, we know for sure that the symbol fragment is in
17505 the same section. If the relax_marker of the symbol fragment
17506 differs from the relax_marker of this fragment, we have not
17507 yet adjusted the symbol fragment fr_address. We want to add
17508 in STRETCH in order to get a better estimate of the address.
17509 This particularly matters because of the shift bits. */
17511 && sym_frag->relax_marker != fragp->relax_marker)
17515 /* Adjust stretch for any alignment frag. Note that if have
17516 been expanding the earlier code, the symbol may be
17517 defined in what appears to be an earlier frag. FIXME:
17518 This doesn't handle the fr_subtype field, which specifies
17519 a maximum number of bytes to skip when doing an
17521 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17523 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17526 stretch = - ((- stretch)
17527 & ~ ((1 << (int) f->fr_offset) - 1));
17529 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17538 addr = fragp->fr_address + fragp->fr_fix;
17540 /* The base address rules are complicated. The base address of
17541 a branch is the following instruction. The base address of a
17542 PC relative load or add is the instruction itself, but if it
17543 is in a delay slot (in which case it can not be extended) use
17544 the address of the instruction whose delay slot it is in. */
17545 if (type == 'p' || type == 'q')
17549 /* If we are currently assuming that this frag should be
17550 extended, then, the current address is two bytes
17552 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17555 /* Ignore the low bit in the target, since it will be set
17556 for a text label. */
17557 if ((val & 1) != 0)
17560 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17562 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17565 val -= addr & ~ ((1 << op->shift) - 1);
17567 /* Branch offsets have an implicit 0 in the lowest bit. */
17568 if (type == 'p' || type == 'q')
17571 /* If any of the shifted bits are set, we must use an extended
17572 opcode. If the address depends on the size of this
17573 instruction, this can lead to a loop, so we arrange to always
17574 use an extended opcode. We only check this when we are in
17575 the main relaxation loop, when SEC is NULL. */
17576 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17578 fragp->fr_subtype =
17579 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17583 /* If we are about to mark a frag as extended because the value
17584 is precisely maxtiny + 1, then there is a chance of an
17585 infinite loop as in the following code:
17590 In this case when the la is extended, foo is 0x3fc bytes
17591 away, so the la can be shrunk, but then foo is 0x400 away, so
17592 the la must be extended. To avoid this loop, we mark the
17593 frag as extended if it was small, and is about to become
17594 extended with a value of maxtiny + 1. */
17595 if (val == ((maxtiny + 1) << op->shift)
17596 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17599 fragp->fr_subtype =
17600 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17604 else if (symsec != absolute_section && sec != NULL)
17605 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17607 if ((val & ((1 << op->shift) - 1)) != 0
17608 || val < (mintiny << op->shift)
17609 || val > (maxtiny << op->shift))
17615 /* Compute the length of a branch sequence, and adjust the
17616 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17617 worst-case length is computed, with UPDATE being used to indicate
17618 whether an unconditional (-1), branch-likely (+1) or regular (0)
17619 branch is to be computed. */
17621 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17623 bfd_boolean toofar;
17627 && S_IS_DEFINED (fragp->fr_symbol)
17628 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17633 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17635 addr = fragp->fr_address + fragp->fr_fix + 4;
17639 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17642 /* If the symbol is not defined or it's in a different segment,
17643 assume the user knows what's going on and emit a short
17649 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17651 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17652 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17653 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17654 RELAX_BRANCH_LINK (fragp->fr_subtype),
17660 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17663 if (mips_pic != NO_PIC)
17665 /* Additional space for PIC loading of target address. */
17667 if (mips_opts.isa == ISA_MIPS1)
17668 /* Additional space for $at-stabilizing nop. */
17672 /* If branch is conditional. */
17673 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17680 /* Compute the length of a branch sequence, and adjust the
17681 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17682 worst-case length is computed, with UPDATE being used to indicate
17683 whether an unconditional (-1), or regular (0) branch is to be
17687 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17689 bfd_boolean toofar;
17693 && S_IS_DEFINED (fragp->fr_symbol)
17694 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17699 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17700 /* Ignore the low bit in the target, since it will be set
17701 for a text label. */
17702 if ((val & 1) != 0)
17705 addr = fragp->fr_address + fragp->fr_fix + 4;
17709 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17712 /* If the symbol is not defined or it's in a different segment,
17713 assume the user knows what's going on and emit a short
17719 if (fragp && update
17720 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17721 fragp->fr_subtype = (toofar
17722 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17723 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17728 bfd_boolean compact_known = fragp != NULL;
17729 bfd_boolean compact = FALSE;
17730 bfd_boolean uncond;
17733 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17735 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17737 uncond = update < 0;
17739 /* If label is out of range, we turn branch <br>:
17741 <br> label # 4 bytes
17747 nop # 2 bytes if compact && !PIC
17750 if (mips_pic == NO_PIC && (!compact_known || compact))
17753 /* If assembling PIC code, we further turn:
17759 lw/ld at, %got(label)(gp) # 4 bytes
17760 d/addiu at, %lo(label) # 4 bytes
17763 if (mips_pic != NO_PIC)
17766 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17768 <brneg> 0f # 4 bytes
17769 nop # 2 bytes if !compact
17772 length += (compact_known && compact) ? 4 : 6;
17778 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17779 bit accordingly. */
17782 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17784 bfd_boolean toofar;
17787 && S_IS_DEFINED (fragp->fr_symbol)
17788 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17794 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17795 /* Ignore the low bit in the target, since it will be set
17796 for a text label. */
17797 if ((val & 1) != 0)
17800 /* Assume this is a 2-byte branch. */
17801 addr = fragp->fr_address + fragp->fr_fix + 2;
17803 /* We try to avoid the infinite loop by not adding 2 more bytes for
17808 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17810 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17811 else if (type == 'E')
17812 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17817 /* If the symbol is not defined or it's in a different segment,
17818 we emit a normal 32-bit branch. */
17821 if (fragp && update
17822 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17824 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17825 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17833 /* Estimate the size of a frag before relaxing. Unless this is the
17834 mips16, we are not really relaxing here, and the final size is
17835 encoded in the subtype information. For the mips16, we have to
17836 decide whether we are using an extended opcode or not. */
17839 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17843 if (RELAX_BRANCH_P (fragp->fr_subtype))
17846 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17848 return fragp->fr_var;
17851 if (RELAX_MIPS16_P (fragp->fr_subtype))
17852 /* We don't want to modify the EXTENDED bit here; it might get us
17853 into infinite loops. We change it only in mips_relax_frag(). */
17854 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17856 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17860 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17861 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17862 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17863 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17864 fragp->fr_var = length;
17869 if (mips_pic == NO_PIC)
17870 change = nopic_need_relax (fragp->fr_symbol, 0);
17871 else if (mips_pic == SVR4_PIC)
17872 change = pic_need_relax (fragp->fr_symbol, segtype);
17873 else if (mips_pic == VXWORKS_PIC)
17874 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17881 fragp->fr_subtype |= RELAX_USE_SECOND;
17882 return -RELAX_FIRST (fragp->fr_subtype);
17885 return -RELAX_SECOND (fragp->fr_subtype);
17888 /* This is called to see whether a reloc against a defined symbol
17889 should be converted into a reloc against a section. */
17892 mips_fix_adjustable (fixS *fixp)
17894 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17895 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17898 if (fixp->fx_addsy == NULL)
17901 /* If symbol SYM is in a mergeable section, relocations of the form
17902 SYM + 0 can usually be made section-relative. The mergeable data
17903 is then identified by the section offset rather than by the symbol.
17905 However, if we're generating REL LO16 relocations, the offset is split
17906 between the LO16 and parterning high part relocation. The linker will
17907 need to recalculate the complete offset in order to correctly identify
17910 The linker has traditionally not looked for the parterning high part
17911 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17912 placed anywhere. Rather than break backwards compatibility by changing
17913 this, it seems better not to force the issue, and instead keep the
17914 original symbol. This will work with either linker behavior. */
17915 if ((lo16_reloc_p (fixp->fx_r_type)
17916 || reloc_needs_lo_p (fixp->fx_r_type))
17917 && HAVE_IN_PLACE_ADDENDS
17918 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17921 /* There is no place to store an in-place offset for JALR relocations.
17922 Likewise an in-range offset of limited PC-relative relocations may
17923 overflow the in-place relocatable field if recalculated against the
17924 start address of the symbol's containing section. */
17925 if (HAVE_IN_PLACE_ADDENDS
17926 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17927 || jalr_reloc_p (fixp->fx_r_type)))
17930 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17931 to a floating-point stub. The same is true for non-R_MIPS16_26
17932 relocations against MIPS16 functions; in this case, the stub becomes
17933 the function's canonical address.
17935 Floating-point stubs are stored in unique .mips16.call.* or
17936 .mips16.fn.* sections. If a stub T for function F is in section S,
17937 the first relocation in section S must be against F; this is how the
17938 linker determines the target function. All relocations that might
17939 resolve to T must also be against F. We therefore have the following
17940 restrictions, which are given in an intentionally-redundant way:
17942 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17945 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17946 if that stub might be used.
17948 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17951 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17952 that stub might be used.
17954 There is a further restriction:
17956 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17957 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17958 targets with in-place addends; the relocation field cannot
17959 encode the low bit.
17961 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17962 against a MIPS16 symbol. We deal with (5) by by not reducing any
17963 such relocations on REL targets.
17965 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17966 relocation against some symbol R, no relocation against R may be
17967 reduced. (Note that this deals with (2) as well as (1) because
17968 relocations against global symbols will never be reduced on ELF
17969 targets.) This approach is a little simpler than trying to detect
17970 stub sections, and gives the "all or nothing" per-symbol consistency
17971 that we have for MIPS16 symbols. */
17972 if (fixp->fx_subsy == NULL
17973 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17974 || *symbol_get_tc (fixp->fx_addsy)
17975 || (HAVE_IN_PLACE_ADDENDS
17976 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17977 && jmp_reloc_p (fixp->fx_r_type))))
17983 /* Translate internal representation of relocation info to BFD target
17987 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17989 static arelent *retval[4];
17991 bfd_reloc_code_real_type code;
17993 memset (retval, 0, sizeof(retval));
17994 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17995 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17996 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17997 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17999 if (fixp->fx_pcrel)
18001 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18002 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18003 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18004 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18005 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18007 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18008 Relocations want only the symbol offset. */
18009 reloc->addend = fixp->fx_addnumber + reloc->address;
18012 reloc->addend = fixp->fx_addnumber;
18014 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18015 entry to be used in the relocation's section offset. */
18016 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18018 reloc->address = reloc->addend;
18022 code = fixp->fx_r_type;
18024 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18025 if (reloc->howto == NULL)
18027 as_bad_where (fixp->fx_file, fixp->fx_line,
18028 _("Can not represent %s relocation in this object file format"),
18029 bfd_get_reloc_code_name (code));
18036 /* Relax a machine dependent frag. This returns the amount by which
18037 the current size of the frag should change. */
18040 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18042 if (RELAX_BRANCH_P (fragp->fr_subtype))
18044 offsetT old_var = fragp->fr_var;
18046 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18048 return fragp->fr_var - old_var;
18051 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18053 offsetT old_var = fragp->fr_var;
18054 offsetT new_var = 4;
18056 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18057 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18058 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18059 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18060 fragp->fr_var = new_var;
18062 return new_var - old_var;
18065 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18068 if (mips16_extended_frag (fragp, NULL, stretch))
18070 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18072 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18077 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18079 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18086 /* Convert a machine dependent frag. */
18089 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18091 if (RELAX_BRANCH_P (fragp->fr_subtype))
18094 unsigned long insn;
18098 buf = fragp->fr_literal + fragp->fr_fix;
18099 insn = read_insn (buf);
18101 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18103 /* We generate a fixup instead of applying it right now
18104 because, if there are linker relaxations, we're going to
18105 need the relocations. */
18106 exp.X_op = O_symbol;
18107 exp.X_add_symbol = fragp->fr_symbol;
18108 exp.X_add_number = fragp->fr_offset;
18110 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18111 BFD_RELOC_16_PCREL_S2);
18112 fixp->fx_file = fragp->fr_file;
18113 fixp->fx_line = fragp->fr_line;
18115 buf = write_insn (buf, insn);
18121 as_warn_where (fragp->fr_file, fragp->fr_line,
18122 _("Relaxed out-of-range branch into a jump"));
18124 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18127 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18129 /* Reverse the branch. */
18130 switch ((insn >> 28) & 0xf)
18133 /* bc[0-3][tf]l? instructions can have the condition
18134 reversed by tweaking a single TF bit, and their
18135 opcodes all have 0x4???????. */
18136 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18137 insn ^= 0x00010000;
18141 /* bltz 0x04000000 bgez 0x04010000
18142 bltzal 0x04100000 bgezal 0x04110000 */
18143 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18144 insn ^= 0x00010000;
18148 /* beq 0x10000000 bne 0x14000000
18149 blez 0x18000000 bgtz 0x1c000000 */
18150 insn ^= 0x04000000;
18158 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18160 /* Clear the and-link bit. */
18161 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18163 /* bltzal 0x04100000 bgezal 0x04110000
18164 bltzall 0x04120000 bgezall 0x04130000 */
18165 insn &= ~0x00100000;
18168 /* Branch over the branch (if the branch was likely) or the
18169 full jump (not likely case). Compute the offset from the
18170 current instruction to branch to. */
18171 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18175 /* How many bytes in instructions we've already emitted? */
18176 i = buf - fragp->fr_literal - fragp->fr_fix;
18177 /* How many bytes in instructions from here to the end? */
18178 i = fragp->fr_var - i;
18180 /* Convert to instruction count. */
18182 /* Branch counts from the next instruction. */
18185 /* Branch over the jump. */
18186 buf = write_insn (buf, insn);
18189 buf = write_insn (buf, 0);
18191 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18193 /* beql $0, $0, 2f */
18195 /* Compute the PC offset from the current instruction to
18196 the end of the variable frag. */
18197 /* How many bytes in instructions we've already emitted? */
18198 i = buf - fragp->fr_literal - fragp->fr_fix;
18199 /* How many bytes in instructions from here to the end? */
18200 i = fragp->fr_var - i;
18201 /* Convert to instruction count. */
18203 /* Don't decrement i, because we want to branch over the
18207 buf = write_insn (buf, insn);
18208 buf = write_insn (buf, 0);
18212 if (mips_pic == NO_PIC)
18215 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18216 ? 0x0c000000 : 0x08000000);
18217 exp.X_op = O_symbol;
18218 exp.X_add_symbol = fragp->fr_symbol;
18219 exp.X_add_number = fragp->fr_offset;
18221 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18222 FALSE, BFD_RELOC_MIPS_JMP);
18223 fixp->fx_file = fragp->fr_file;
18224 fixp->fx_line = fragp->fr_line;
18226 buf = write_insn (buf, insn);
18230 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18232 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18233 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18234 insn |= at << OP_SH_RT;
18235 exp.X_op = O_symbol;
18236 exp.X_add_symbol = fragp->fr_symbol;
18237 exp.X_add_number = fragp->fr_offset;
18239 if (fragp->fr_offset)
18241 exp.X_add_symbol = make_expr_symbol (&exp);
18242 exp.X_add_number = 0;
18245 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18246 FALSE, BFD_RELOC_MIPS_GOT16);
18247 fixp->fx_file = fragp->fr_file;
18248 fixp->fx_line = fragp->fr_line;
18250 buf = write_insn (buf, insn);
18252 if (mips_opts.isa == ISA_MIPS1)
18254 buf = write_insn (buf, 0);
18256 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18257 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18258 insn |= at << OP_SH_RS | at << OP_SH_RT;
18260 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18261 FALSE, BFD_RELOC_LO16);
18262 fixp->fx_file = fragp->fr_file;
18263 fixp->fx_line = fragp->fr_line;
18265 buf = write_insn (buf, insn);
18268 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18272 insn |= at << OP_SH_RS;
18274 buf = write_insn (buf, insn);
18278 fragp->fr_fix += fragp->fr_var;
18279 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18283 /* Relax microMIPS branches. */
18284 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18286 char *buf = fragp->fr_literal + fragp->fr_fix;
18287 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18288 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18289 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18290 bfd_boolean short_ds;
18291 unsigned long insn;
18295 exp.X_op = O_symbol;
18296 exp.X_add_symbol = fragp->fr_symbol;
18297 exp.X_add_number = fragp->fr_offset;
18299 fragp->fr_fix += fragp->fr_var;
18301 /* Handle 16-bit branches that fit or are forced to fit. */
18302 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18304 /* We generate a fixup instead of applying it right now,
18305 because if there is linker relaxation, we're going to
18306 need the relocations. */
18308 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18309 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18310 else if (type == 'E')
18311 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18312 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18316 fixp->fx_file = fragp->fr_file;
18317 fixp->fx_line = fragp->fr_line;
18319 /* These relocations can have an addend that won't fit in
18321 fixp->fx_no_overflow = 1;
18326 /* Handle 32-bit branches that fit or are forced to fit. */
18327 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18328 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18330 /* We generate a fixup instead of applying it right now,
18331 because if there is linker relaxation, we're going to
18332 need the relocations. */
18333 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18334 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18335 fixp->fx_file = fragp->fr_file;
18336 fixp->fx_line = fragp->fr_line;
18342 /* Relax 16-bit branches to 32-bit branches. */
18345 insn = read_compressed_insn (buf, 2);
18347 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18348 insn = 0x94000000; /* beq */
18349 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18351 unsigned long regno;
18353 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18354 regno = micromips_to_32_reg_d_map [regno];
18355 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18356 insn |= regno << MICROMIPSOP_SH_RS;
18361 /* Nothing else to do, just write it out. */
18362 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18363 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18365 buf = write_compressed_insn (buf, insn, 4);
18366 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18371 insn = read_compressed_insn (buf, 4);
18373 /* Relax 32-bit branches to a sequence of instructions. */
18374 as_warn_where (fragp->fr_file, fragp->fr_line,
18375 _("Relaxed out-of-range branch into a jump"));
18377 /* Set the short-delay-slot bit. */
18378 short_ds = al && (insn & 0x02000000) != 0;
18380 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18384 /* Reverse the branch. */
18385 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18386 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18387 insn ^= 0x20000000;
18388 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18389 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18390 || (insn & 0xffe00000) == 0x40800000 /* blez */
18391 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18392 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18393 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18394 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18395 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18396 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18397 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18398 insn ^= 0x00400000;
18399 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18400 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18401 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18402 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18403 insn ^= 0x00200000;
18409 /* Clear the and-link and short-delay-slot bits. */
18410 gas_assert ((insn & 0xfda00000) == 0x40200000);
18412 /* bltzal 0x40200000 bgezal 0x40600000 */
18413 /* bltzals 0x42200000 bgezals 0x42600000 */
18414 insn &= ~0x02200000;
18417 /* Make a label at the end for use with the branch. */
18418 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18419 micromips_label_inc ();
18420 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18423 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18424 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18425 fixp->fx_file = fragp->fr_file;
18426 fixp->fx_line = fragp->fr_line;
18428 /* Branch over the jump. */
18429 buf = write_compressed_insn (buf, insn, 4);
18432 buf = write_compressed_insn (buf, 0x0c00, 2);
18435 if (mips_pic == NO_PIC)
18437 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18439 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18440 insn = al ? jal : 0xd4000000;
18442 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18443 BFD_RELOC_MICROMIPS_JMP);
18444 fixp->fx_file = fragp->fr_file;
18445 fixp->fx_line = fragp->fr_line;
18447 buf = write_compressed_insn (buf, insn, 4);
18450 buf = write_compressed_insn (buf, 0x0c00, 2);
18454 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18455 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18456 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18458 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18459 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18460 insn |= at << MICROMIPSOP_SH_RT;
18462 if (exp.X_add_number)
18464 exp.X_add_symbol = make_expr_symbol (&exp);
18465 exp.X_add_number = 0;
18468 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18469 BFD_RELOC_MICROMIPS_GOT16);
18470 fixp->fx_file = fragp->fr_file;
18471 fixp->fx_line = fragp->fr_line;
18473 buf = write_compressed_insn (buf, insn, 4);
18475 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18476 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18477 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18479 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18480 BFD_RELOC_MICROMIPS_LO16);
18481 fixp->fx_file = fragp->fr_file;
18482 fixp->fx_line = fragp->fr_line;
18484 buf = write_compressed_insn (buf, insn, 4);
18486 /* jr/jrc/jalr/jalrs $at */
18487 insn = al ? jalr : jr;
18488 insn |= at << MICROMIPSOP_SH_MJ;
18490 buf = write_compressed_insn (buf, insn, 2);
18493 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18497 if (RELAX_MIPS16_P (fragp->fr_subtype))
18500 const struct mips16_immed_operand *op;
18503 unsigned int user_length, length;
18504 unsigned long insn;
18507 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18508 op = mips16_immed_operands;
18509 while (op->type != type)
18512 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18513 val = resolve_symbol_value (fragp->fr_symbol);
18518 addr = fragp->fr_address + fragp->fr_fix;
18520 /* The rules for the base address of a PC relative reloc are
18521 complicated; see mips16_extended_frag. */
18522 if (type == 'p' || type == 'q')
18527 /* Ignore the low bit in the target, since it will be
18528 set for a text label. */
18529 if ((val & 1) != 0)
18532 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18534 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18537 addr &= ~ (addressT) ((1 << op->shift) - 1);
18540 /* Make sure the section winds up with the alignment we have
18543 record_alignment (asec, op->shift);
18547 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18548 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18549 as_warn_where (fragp->fr_file, fragp->fr_line,
18550 _("extended instruction in delay slot"));
18552 buf = fragp->fr_literal + fragp->fr_fix;
18554 insn = read_compressed_insn (buf, 2);
18556 insn |= MIPS16_EXTEND;
18558 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18560 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18565 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18566 BFD_RELOC_UNUSED, val, user_length, &insn);
18568 length = (ext ? 4 : 2);
18569 gas_assert (mips16_opcode_length (insn) == length);
18570 write_compressed_insn (buf, insn, length);
18571 fragp->fr_fix += length;
18575 relax_substateT subtype = fragp->fr_subtype;
18576 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18577 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18581 first = RELAX_FIRST (subtype);
18582 second = RELAX_SECOND (subtype);
18583 fixp = (fixS *) fragp->fr_opcode;
18585 /* If the delay slot chosen does not match the size of the instruction,
18586 then emit a warning. */
18587 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18588 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18593 s = subtype & (RELAX_DELAY_SLOT_16BIT
18594 | RELAX_DELAY_SLOT_SIZE_FIRST
18595 | RELAX_DELAY_SLOT_SIZE_SECOND);
18596 msg = macro_warning (s);
18598 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18602 /* Possibly emit a warning if we've chosen the longer option. */
18603 if (use_second == second_longer)
18609 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18610 msg = macro_warning (s);
18612 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18616 /* Go through all the fixups for the first sequence. Disable them
18617 (by marking them as done) if we're going to use the second
18618 sequence instead. */
18620 && fixp->fx_frag == fragp
18621 && fixp->fx_where < fragp->fr_fix - second)
18623 if (subtype & RELAX_USE_SECOND)
18625 fixp = fixp->fx_next;
18628 /* Go through the fixups for the second sequence. Disable them if
18629 we're going to use the first sequence, otherwise adjust their
18630 addresses to account for the relaxation. */
18631 while (fixp && fixp->fx_frag == fragp)
18633 if (subtype & RELAX_USE_SECOND)
18634 fixp->fx_where -= first;
18637 fixp = fixp->fx_next;
18640 /* Now modify the frag contents. */
18641 if (subtype & RELAX_USE_SECOND)
18645 start = fragp->fr_literal + fragp->fr_fix - first - second;
18646 memmove (start, start + first, second);
18647 fragp->fr_fix -= first;
18650 fragp->fr_fix -= second;
18654 /* This function is called after the relocs have been generated.
18655 We've been storing mips16 text labels as odd. Here we convert them
18656 back to even for the convenience of the debugger. */
18659 mips_frob_file_after_relocs (void)
18662 unsigned int count, i;
18664 syms = bfd_get_outsymbols (stdoutput);
18665 count = bfd_get_symcount (stdoutput);
18666 for (i = 0; i < count; i++, syms++)
18667 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18668 && ((*syms)->value & 1) != 0)
18670 (*syms)->value &= ~1;
18671 /* If the symbol has an odd size, it was probably computed
18672 incorrectly, so adjust that as well. */
18673 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18674 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18678 /* This function is called whenever a label is defined, including fake
18679 labels instantiated off the dot special symbol. It is used when
18680 handling branch delays; if a branch has a label, we assume we cannot
18681 move it. This also bumps the value of the symbol by 1 in compressed
18685 mips_record_label (symbolS *sym)
18687 segment_info_type *si = seg_info (now_seg);
18688 struct insn_label_list *l;
18690 if (free_insn_labels == NULL)
18691 l = (struct insn_label_list *) xmalloc (sizeof *l);
18694 l = free_insn_labels;
18695 free_insn_labels = l->next;
18699 l->next = si->label_list;
18700 si->label_list = l;
18703 /* This function is called as tc_frob_label() whenever a label is defined
18704 and adds a DWARF-2 record we only want for true labels. */
18707 mips_define_label (symbolS *sym)
18709 mips_record_label (sym);
18710 dwarf2_emit_label (sym);
18713 /* This function is called by tc_new_dot_label whenever a new dot symbol
18717 mips_add_dot_label (symbolS *sym)
18719 mips_record_label (sym);
18720 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18721 mips_compressed_mark_label (sym);
18724 /* Some special processing for a MIPS ELF file. */
18727 mips_elf_final_processing (void)
18729 /* Write out the register information. */
18730 if (mips_abi != N64_ABI)
18734 s.ri_gprmask = mips_gprmask;
18735 s.ri_cprmask[0] = mips_cprmask[0];
18736 s.ri_cprmask[1] = mips_cprmask[1];
18737 s.ri_cprmask[2] = mips_cprmask[2];
18738 s.ri_cprmask[3] = mips_cprmask[3];
18739 /* The gp_value field is set by the MIPS ELF backend. */
18741 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18742 ((Elf32_External_RegInfo *)
18743 mips_regmask_frag));
18747 Elf64_Internal_RegInfo s;
18749 s.ri_gprmask = mips_gprmask;
18751 s.ri_cprmask[0] = mips_cprmask[0];
18752 s.ri_cprmask[1] = mips_cprmask[1];
18753 s.ri_cprmask[2] = mips_cprmask[2];
18754 s.ri_cprmask[3] = mips_cprmask[3];
18755 /* The gp_value field is set by the MIPS ELF backend. */
18757 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18758 ((Elf64_External_RegInfo *)
18759 mips_regmask_frag));
18762 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18763 sort of BFD interface for this. */
18764 if (mips_any_noreorder)
18765 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18766 if (mips_pic != NO_PIC)
18768 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18769 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18772 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18774 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18775 defined at present; this might need to change in future. */
18776 if (file_ase_mips16)
18777 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18778 if (file_ase_micromips)
18779 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18780 if (file_ase & ASE_MDMX)
18781 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18783 /* Set the MIPS ELF ABI flags. */
18784 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18785 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18786 else if (mips_abi == O64_ABI)
18787 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18788 else if (mips_abi == EABI_ABI)
18790 if (!file_mips_gp32)
18791 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18793 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18795 else if (mips_abi == N32_ABI)
18796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18798 /* Nothing to do for N64_ABI. */
18800 if (mips_32bitmode)
18801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18803 if (mips_flag_nan2008)
18804 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18806 #if 0 /* XXX FIXME */
18807 /* 32 bit code with 64 bit FP registers. */
18808 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18809 elf_elfheader (stdoutput)->e_flags |= ???;
18813 typedef struct proc {
18815 symbolS *func_end_sym;
18816 unsigned long reg_mask;
18817 unsigned long reg_offset;
18818 unsigned long fpreg_mask;
18819 unsigned long fpreg_offset;
18820 unsigned long frame_offset;
18821 unsigned long frame_reg;
18822 unsigned long pc_reg;
18825 static procS cur_proc;
18826 static procS *cur_proc_ptr;
18827 static int numprocs;
18829 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18830 as "2", and a normal nop as "0". */
18832 #define NOP_OPCODE_MIPS 0
18833 #define NOP_OPCODE_MIPS16 1
18834 #define NOP_OPCODE_MICROMIPS 2
18837 mips_nop_opcode (void)
18839 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18840 return NOP_OPCODE_MICROMIPS;
18841 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18842 return NOP_OPCODE_MIPS16;
18844 return NOP_OPCODE_MIPS;
18847 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18848 32-bit microMIPS NOPs here (if applicable). */
18851 mips_handle_align (fragS *fragp)
18855 int bytes, size, excess;
18858 if (fragp->fr_type != rs_align_code)
18861 p = fragp->fr_literal + fragp->fr_fix;
18863 switch (nop_opcode)
18865 case NOP_OPCODE_MICROMIPS:
18866 opcode = micromips_nop32_insn.insn_opcode;
18869 case NOP_OPCODE_MIPS16:
18870 opcode = mips16_nop_insn.insn_opcode;
18873 case NOP_OPCODE_MIPS:
18875 opcode = nop_insn.insn_opcode;
18880 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18881 excess = bytes % size;
18883 /* Handle the leading part if we're not inserting a whole number of
18884 instructions, and make it the end of the fixed part of the frag.
18885 Try to fit in a short microMIPS NOP if applicable and possible,
18886 and use zeroes otherwise. */
18887 gas_assert (excess < 4);
18888 fragp->fr_fix += excess;
18893 /* Fall through. */
18895 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18897 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18901 /* Fall through. */
18904 /* Fall through. */
18909 md_number_to_chars (p, opcode, size);
18910 fragp->fr_var = size;
18914 md_obj_begin (void)
18921 /* Check for premature end, nesting errors, etc. */
18923 as_warn (_("missing .end at end of assembly"));
18932 if (*input_line_pointer == '-')
18934 ++input_line_pointer;
18937 if (!ISDIGIT (*input_line_pointer))
18938 as_bad (_("expected simple number"));
18939 if (input_line_pointer[0] == '0')
18941 if (input_line_pointer[1] == 'x')
18943 input_line_pointer += 2;
18944 while (ISXDIGIT (*input_line_pointer))
18947 val |= hex_value (*input_line_pointer++);
18949 return negative ? -val : val;
18953 ++input_line_pointer;
18954 while (ISDIGIT (*input_line_pointer))
18957 val |= *input_line_pointer++ - '0';
18959 return negative ? -val : val;
18962 if (!ISDIGIT (*input_line_pointer))
18964 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18965 *input_line_pointer, *input_line_pointer);
18966 as_warn (_("invalid number"));
18969 while (ISDIGIT (*input_line_pointer))
18972 val += *input_line_pointer++ - '0';
18974 return negative ? -val : val;
18977 /* The .file directive; just like the usual .file directive, but there
18978 is an initial number which is the ECOFF file index. In the non-ECOFF
18979 case .file implies DWARF-2. */
18982 s_mips_file (int x ATTRIBUTE_UNUSED)
18984 static int first_file_directive = 0;
18986 if (ECOFF_DEBUGGING)
18995 filename = dwarf2_directive_file (0);
18997 /* Versions of GCC up to 3.1 start files with a ".file"
18998 directive even for stabs output. Make sure that this
18999 ".file" is handled. Note that you need a version of GCC
19000 after 3.1 in order to support DWARF-2 on MIPS. */
19001 if (filename != NULL && ! first_file_directive)
19003 (void) new_logical_line (filename, -1);
19004 s_app_file_string (filename, 0);
19006 first_file_directive = 1;
19010 /* The .loc directive, implying DWARF-2. */
19013 s_mips_loc (int x ATTRIBUTE_UNUSED)
19015 if (!ECOFF_DEBUGGING)
19016 dwarf2_directive_loc (0);
19019 /* The .end directive. */
19022 s_mips_end (int x ATTRIBUTE_UNUSED)
19026 /* Following functions need their own .frame and .cprestore directives. */
19027 mips_frame_reg_valid = 0;
19028 mips_cprestore_valid = 0;
19030 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19033 demand_empty_rest_of_line ();
19038 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19039 as_warn (_(".end not in text section"));
19043 as_warn (_(".end directive without a preceding .ent directive."));
19044 demand_empty_rest_of_line ();
19050 gas_assert (S_GET_NAME (p));
19051 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19052 as_warn (_(".end symbol does not match .ent symbol."));
19054 if (debug_type == DEBUG_STABS)
19055 stabs_generate_asm_endfunc (S_GET_NAME (p),
19059 as_warn (_(".end directive missing or unknown symbol"));
19061 /* Create an expression to calculate the size of the function. */
19062 if (p && cur_proc_ptr)
19064 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19065 expressionS *exp = xmalloc (sizeof (expressionS));
19068 exp->X_op = O_subtract;
19069 exp->X_add_symbol = symbol_temp_new_now ();
19070 exp->X_op_symbol = p;
19071 exp->X_add_number = 0;
19073 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19076 /* Generate a .pdr section. */
19077 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19079 segT saved_seg = now_seg;
19080 subsegT saved_subseg = now_subseg;
19084 #ifdef md_flush_pending_output
19085 md_flush_pending_output ();
19088 gas_assert (pdr_seg);
19089 subseg_set (pdr_seg, 0);
19091 /* Write the symbol. */
19092 exp.X_op = O_symbol;
19093 exp.X_add_symbol = p;
19094 exp.X_add_number = 0;
19095 emit_expr (&exp, 4);
19097 fragp = frag_more (7 * 4);
19099 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19100 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19101 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19102 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19103 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19104 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19105 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19107 subseg_set (saved_seg, saved_subseg);
19110 cur_proc_ptr = NULL;
19113 /* The .aent and .ent directives. */
19116 s_mips_ent (int aent)
19120 symbolP = get_symbol ();
19121 if (*input_line_pointer == ',')
19122 ++input_line_pointer;
19123 SKIP_WHITESPACE ();
19124 if (ISDIGIT (*input_line_pointer)
19125 || *input_line_pointer == '-')
19128 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19129 as_warn (_(".ent or .aent not in text section."));
19131 if (!aent && cur_proc_ptr)
19132 as_warn (_("missing .end"));
19136 /* This function needs its own .frame and .cprestore directives. */
19137 mips_frame_reg_valid = 0;
19138 mips_cprestore_valid = 0;
19140 cur_proc_ptr = &cur_proc;
19141 memset (cur_proc_ptr, '\0', sizeof (procS));
19143 cur_proc_ptr->func_sym = symbolP;
19147 if (debug_type == DEBUG_STABS)
19148 stabs_generate_asm_func (S_GET_NAME (symbolP),
19149 S_GET_NAME (symbolP));
19152 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19154 demand_empty_rest_of_line ();
19157 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19158 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19159 s_mips_frame is used so that we can set the PDR information correctly.
19160 We can't use the ecoff routines because they make reference to the ecoff
19161 symbol table (in the mdebug section). */
19164 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19166 if (ECOFF_DEBUGGING)
19172 if (cur_proc_ptr == (procS *) NULL)
19174 as_warn (_(".frame outside of .ent"));
19175 demand_empty_rest_of_line ();
19179 cur_proc_ptr->frame_reg = tc_get_register (1);
19181 SKIP_WHITESPACE ();
19182 if (*input_line_pointer++ != ','
19183 || get_absolute_expression_and_terminator (&val) != ',')
19185 as_warn (_("Bad .frame directive"));
19186 --input_line_pointer;
19187 demand_empty_rest_of_line ();
19191 cur_proc_ptr->frame_offset = val;
19192 cur_proc_ptr->pc_reg = tc_get_register (0);
19194 demand_empty_rest_of_line ();
19198 /* The .fmask and .mask directives. If the mdebug section is present
19199 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19200 embedded targets, s_mips_mask is used so that we can set the PDR
19201 information correctly. We can't use the ecoff routines because they
19202 make reference to the ecoff symbol table (in the mdebug section). */
19205 s_mips_mask (int reg_type)
19207 if (ECOFF_DEBUGGING)
19208 s_ignore (reg_type);
19213 if (cur_proc_ptr == (procS *) NULL)
19215 as_warn (_(".mask/.fmask outside of .ent"));
19216 demand_empty_rest_of_line ();
19220 if (get_absolute_expression_and_terminator (&mask) != ',')
19222 as_warn (_("Bad .mask/.fmask directive"));
19223 --input_line_pointer;
19224 demand_empty_rest_of_line ();
19228 off = get_absolute_expression ();
19230 if (reg_type == 'F')
19232 cur_proc_ptr->fpreg_mask = mask;
19233 cur_proc_ptr->fpreg_offset = off;
19237 cur_proc_ptr->reg_mask = mask;
19238 cur_proc_ptr->reg_offset = off;
19241 demand_empty_rest_of_line ();
19245 /* A table describing all the processors gas knows about. Names are
19246 matched in the order listed.
19248 To ease comparison, please keep this table in the same order as
19249 gcc's mips_cpu_info_table[]. */
19250 static const struct mips_cpu_info mips_cpu_info_table[] =
19252 /* Entries for generic ISAs */
19253 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19254 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19255 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19256 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19257 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19258 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19259 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19260 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19261 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19264 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19265 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19266 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19269 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19272 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19273 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19274 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19275 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19276 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19277 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19278 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19279 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19280 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19281 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19282 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19283 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19284 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19285 /* ST Microelectronics Loongson 2E and 2F cores */
19286 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19287 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19290 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19291 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19292 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19293 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19294 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19295 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19296 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19297 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19298 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19299 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19300 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19301 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19302 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19303 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19304 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19307 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19308 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19309 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19310 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19312 /* MIPS 32 Release 2 */
19313 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19315 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19316 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19317 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19318 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19319 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19320 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19322 ISA_MIPS32R2, CPU_MIPS32R2 },
19323 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19324 ISA_MIPS32R2, CPU_MIPS32R2 },
19325 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19326 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19327 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19328 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19329 /* Deprecated forms of the above. */
19330 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19331 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19332 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19333 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19334 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19335 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19336 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19337 /* Deprecated forms of the above. */
19338 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19339 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19340 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19341 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19342 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19343 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19344 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19345 /* Deprecated forms of the above. */
19346 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19347 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19348 /* 34Kn is a 34kc without DSP. */
19349 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19350 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19351 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19352 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19353 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19354 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19355 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19356 /* Deprecated forms of the above. */
19357 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19358 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19359 /* 1004K cores are multiprocessor versions of the 34K. */
19360 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19361 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19362 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19363 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19366 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19367 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19368 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19369 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19371 /* Broadcom SB-1 CPU core */
19372 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19373 /* Broadcom SB-1A CPU core */
19374 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19376 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19378 /* MIPS 64 Release 2 */
19380 /* Cavium Networks Octeon CPU core */
19381 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19382 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19383 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19386 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19389 XLP is mostly like XLR, with the prominent exception that it is
19390 MIPS64R2 rather than MIPS64. */
19391 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19394 { NULL, 0, 0, 0, 0 }
19398 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19399 with a final "000" replaced by "k". Ignore case.
19401 Note: this function is shared between GCC and GAS. */
19404 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19406 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19407 given++, canonical++;
19409 return ((*given == 0 && *canonical == 0)
19410 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19414 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19415 CPU name. We've traditionally allowed a lot of variation here.
19417 Note: this function is shared between GCC and GAS. */
19420 mips_matching_cpu_name_p (const char *canonical, const char *given)
19422 /* First see if the name matches exactly, or with a final "000"
19423 turned into "k". */
19424 if (mips_strict_matching_cpu_name_p (canonical, given))
19427 /* If not, try comparing based on numerical designation alone.
19428 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19429 if (TOLOWER (*given) == 'r')
19431 if (!ISDIGIT (*given))
19434 /* Skip over some well-known prefixes in the canonical name,
19435 hoping to find a number there too. */
19436 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19438 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19440 else if (TOLOWER (canonical[0]) == 'r')
19443 return mips_strict_matching_cpu_name_p (canonical, given);
19447 /* Parse an option that takes the name of a processor as its argument.
19448 OPTION is the name of the option and CPU_STRING is the argument.
19449 Return the corresponding processor enumeration if the CPU_STRING is
19450 recognized, otherwise report an error and return null.
19452 A similar function exists in GCC. */
19454 static const struct mips_cpu_info *
19455 mips_parse_cpu (const char *option, const char *cpu_string)
19457 const struct mips_cpu_info *p;
19459 /* 'from-abi' selects the most compatible architecture for the given
19460 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19461 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19462 version. Look first at the -mgp options, if given, otherwise base
19463 the choice on MIPS_DEFAULT_64BIT.
19465 Treat NO_ABI like the EABIs. One reason to do this is that the
19466 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19467 architecture. This code picks MIPS I for 'mips' and MIPS III for
19468 'mips64', just as we did in the days before 'from-abi'. */
19469 if (strcasecmp (cpu_string, "from-abi") == 0)
19471 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19472 return mips_cpu_info_from_isa (ISA_MIPS1);
19474 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19475 return mips_cpu_info_from_isa (ISA_MIPS3);
19477 if (file_mips_gp32 >= 0)
19478 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19480 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19485 /* 'default' has traditionally been a no-op. Probably not very useful. */
19486 if (strcasecmp (cpu_string, "default") == 0)
19489 for (p = mips_cpu_info_table; p->name != 0; p++)
19490 if (mips_matching_cpu_name_p (p->name, cpu_string))
19493 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19497 /* Return the canonical processor information for ISA (a member of the
19498 ISA_MIPS* enumeration). */
19500 static const struct mips_cpu_info *
19501 mips_cpu_info_from_isa (int isa)
19505 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19506 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19507 && isa == mips_cpu_info_table[i].isa)
19508 return (&mips_cpu_info_table[i]);
19513 static const struct mips_cpu_info *
19514 mips_cpu_info_from_arch (int arch)
19518 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19519 if (arch == mips_cpu_info_table[i].cpu)
19520 return (&mips_cpu_info_table[i]);
19526 show (FILE *stream, const char *string, int *col_p, int *first_p)
19530 fprintf (stream, "%24s", "");
19535 fprintf (stream, ", ");
19539 if (*col_p + strlen (string) > 72)
19541 fprintf (stream, "\n%24s", "");
19545 fprintf (stream, "%s", string);
19546 *col_p += strlen (string);
19552 md_show_usage (FILE *stream)
19557 fprintf (stream, _("\
19559 -EB generate big endian output\n\
19560 -EL generate little endian output\n\
19561 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19562 -G NUM allow referencing objects up to NUM bytes\n\
19563 implicitly with the gp register [default 8]\n"));
19564 fprintf (stream, _("\
19565 -mips1 generate MIPS ISA I instructions\n\
19566 -mips2 generate MIPS ISA II instructions\n\
19567 -mips3 generate MIPS ISA III instructions\n\
19568 -mips4 generate MIPS ISA IV instructions\n\
19569 -mips5 generate MIPS ISA V instructions\n\
19570 -mips32 generate MIPS32 ISA instructions\n\
19571 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19572 -mips64 generate MIPS64 ISA instructions\n\
19573 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19574 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19578 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19579 show (stream, mips_cpu_info_table[i].name, &column, &first);
19580 show (stream, "from-abi", &column, &first);
19581 fputc ('\n', stream);
19583 fprintf (stream, _("\
19584 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19585 -no-mCPU don't generate code specific to CPU.\n\
19586 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19590 show (stream, "3900", &column, &first);
19591 show (stream, "4010", &column, &first);
19592 show (stream, "4100", &column, &first);
19593 show (stream, "4650", &column, &first);
19594 fputc ('\n', stream);
19596 fprintf (stream, _("\
19597 -mips16 generate mips16 instructions\n\
19598 -no-mips16 do not generate mips16 instructions\n"));
19599 fprintf (stream, _("\
19600 -mmicromips generate microMIPS instructions\n\
19601 -mno-micromips do not generate microMIPS instructions\n"));
19602 fprintf (stream, _("\
19603 -msmartmips generate smartmips instructions\n\
19604 -mno-smartmips do not generate smartmips instructions\n"));
19605 fprintf (stream, _("\
19606 -mdsp generate DSP instructions\n\
19607 -mno-dsp do not generate DSP instructions\n"));
19608 fprintf (stream, _("\
19609 -mdspr2 generate DSP R2 instructions\n\
19610 -mno-dspr2 do not generate DSP R2 instructions\n"));
19611 fprintf (stream, _("\
19612 -mmt generate MT instructions\n\
19613 -mno-mt do not generate MT instructions\n"));
19614 fprintf (stream, _("\
19615 -mmcu generate MCU instructions\n\
19616 -mno-mcu do not generate MCU instructions\n"));
19617 fprintf (stream, _("\
19618 -mvirt generate Virtualization instructions\n\
19619 -mno-virt do not generate Virtualization instructions\n"));
19620 fprintf (stream, _("\
19621 -minsn32 only generate 32-bit microMIPS instructions\n\
19622 -mno-insn32 generate all microMIPS instructions\n"));
19623 fprintf (stream, _("\
19624 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19625 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19626 -mfix-vr4120 work around certain VR4120 errata\n\
19627 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19628 -mfix-24k insert a nop after ERET and DERET instructions\n\
19629 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19630 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19631 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19632 -msym32 assume all symbols have 32-bit values\n\
19633 -O0 remove unneeded NOPs, do not swap branches\n\
19634 -O remove unneeded NOPs and swap branches\n\
19635 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19636 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19637 fprintf (stream, _("\
19638 -mhard-float allow floating-point instructions\n\
19639 -msoft-float do not allow floating-point instructions\n\
19640 -msingle-float only allow 32-bit floating-point operations\n\
19641 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19642 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19643 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19644 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19648 show (stream, "legacy", &column, &first);
19649 show (stream, "2008", &column, &first);
19651 fputc ('\n', stream);
19653 fprintf (stream, _("\
19654 -KPIC, -call_shared generate SVR4 position independent code\n\
19655 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19656 -mvxworks-pic generate VxWorks position independent code\n\
19657 -non_shared do not generate code that can operate with DSOs\n\
19658 -xgot assume a 32 bit GOT\n\
19659 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19660 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19661 position dependent (non shared) code\n\
19662 -mabi=ABI create ABI conformant object file for:\n"));
19666 show (stream, "32", &column, &first);
19667 show (stream, "o64", &column, &first);
19668 show (stream, "n32", &column, &first);
19669 show (stream, "64", &column, &first);
19670 show (stream, "eabi", &column, &first);
19672 fputc ('\n', stream);
19674 fprintf (stream, _("\
19675 -32 create o32 ABI object file (default)\n\
19676 -n32 create n32 ABI object file\n\
19677 -64 create 64 ABI object file\n"));
19682 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19684 if (HAVE_64BIT_SYMBOLS)
19685 return dwarf2_format_64bit_irix;
19687 return dwarf2_format_32bit;
19692 mips_dwarf2_addr_size (void)
19694 if (HAVE_64BIT_OBJECTS)
19700 /* Standard calling conventions leave the CFA at SP on entry. */
19702 mips_cfi_frame_initial_instructions (void)
19704 cfi_add_CFA_def_cfa_register (SP);
19708 tc_mips_regname_to_dw2regnum (char *regname)
19710 unsigned int regnum = -1;
19713 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))