1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi = NO_ABI;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls = FALSE;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32 = -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32 = -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts =
202 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask;
209 unsigned long mips_cprmask[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa = ISA_UNKNOWN;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch = CPU_UNKNOWN;
228 static const char *mips_arch_string;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune = CPU_UNKNOWN;
233 static const char *mips_tune_string;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode = 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* True if relocations are stored in-place. */
283 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
285 /* We can only have 64bit addresses if the object file format supports it. */
286 #define HAVE_32BIT_ADDRESSES \
288 || (bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS)) \
291 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
293 /* Addresses are loaded in different ways, depending on the address size
294 in use. The n32 ABI Documentation also mandates the use of additions
295 with overflow checking, but existing implementations don't follow it. */
296 #define ADDRESS_ADD_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
299 #define ADDRESS_ADDI_INSN \
300 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
302 #define ADDRESS_LOAD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
305 #define ADDRESS_STORE_INSN \
306 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
308 /* Return true if the given CPU supports the MIPS16 ASE. */
309 #define CPU_HAS_MIPS16(cpu) \
310 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
311 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
313 /* Return true if the given CPU supports the MIPS3D ASE. */
314 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
317 /* Return true if the given CPU supports the MDMX ASE. */
318 #define CPU_HAS_MDMX(cpu) (FALSE \
321 /* True if CPU has a dror instruction. */
322 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
324 /* True if CPU has a ror instruction. */
325 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
327 /* True if mflo and mfhi can be immediately followed by instructions
328 which write to the HI and LO registers.
330 According to MIPS specifications, MIPS ISAs I, II, and III need
331 (at least) two instructions between the reads of HI/LO and
332 instructions which write them, and later ISAs do not. Contradicting
333 the MIPS specifications, some MIPS IV processor user manuals (e.g.
334 the UM for the NEC Vr5000) document needing the instructions between
335 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
336 MIPS64 and later ISAs to have the interlocks, plus any specific
337 earlier-ISA CPUs for which CPU documentation declares that the
338 instructions are really interlocked. */
339 #define hilo_interlocks \
340 (mips_opts.isa == ISA_MIPS32 \
341 || mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_R10000 \
346 || mips_opts.arch == CPU_R12000 \
347 || mips_opts.arch == CPU_RM7000 \
348 || mips_opts.arch == CPU_VR5500 \
351 /* Whether the processor uses hardware interlocks to protect reads
352 from the GPRs after they are loaded from memory, and thus does not
353 require nops to be inserted. This applies to instructions marked
354 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
356 #define gpr_interlocks \
357 (mips_opts.isa != ISA_MIPS1 \
358 || mips_opts.arch == CPU_R3900)
360 /* Whether the processor uses hardware interlocks to avoid delays
361 required by coprocessor instructions, and thus does not require
362 nops to be inserted. This applies to instructions marked
363 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
364 between instructions marked INSN_WRITE_COND_CODE and ones marked
365 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
366 levels I, II, and III. */
367 /* Itbl support may require additional care here. */
368 #define cop_interlocks \
369 ((mips_opts.isa != ISA_MIPS1 \
370 && mips_opts.isa != ISA_MIPS2 \
371 && mips_opts.isa != ISA_MIPS3) \
372 || mips_opts.arch == CPU_R4300 \
375 /* Whether the processor uses hardware interlocks to protect reads
376 from coprocessor registers after they are loaded from memory, and
377 thus does not require nops to be inserted. This applies to
378 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
379 requires at MIPS ISA level I. */
380 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
382 /* Is this a mfhi or mflo instruction? */
383 #define MF_HILO_INSN(PINFO) \
384 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
386 /* MIPS PIC level. */
388 enum mips_pic_level mips_pic;
390 /* 1 if we should generate 32 bit offsets from the $gp register in
391 SVR4_PIC mode. Currently has no meaning in other modes. */
392 static int mips_big_got = 0;
394 /* 1 if trap instructions should used for overflow rather than break
396 static int mips_trap = 0;
398 /* 1 if double width floating point constants should not be constructed
399 by assembling two single width halves into two single width floating
400 point registers which just happen to alias the double width destination
401 register. On some architectures this aliasing can be disabled by a bit
402 in the status register, and the setting of this bit cannot be determined
403 automatically at assemble time. */
404 static int mips_disable_float_construction;
406 /* Non-zero if any .set noreorder directives were used. */
408 static int mips_any_noreorder;
410 /* Non-zero if nops should be inserted when the register referenced in
411 an mfhi/mflo instruction is read in the next two instructions. */
412 static int mips_7000_hilo_fix;
414 /* The size of the small data section. */
415 static unsigned int g_switch_value = 8;
416 /* Whether the -G option was used. */
417 static int g_switch_seen = 0;
422 /* If we can determine in advance that GP optimization won't be
423 possible, we can skip the relaxation stuff that tries to produce
424 GP-relative references. This makes delay slot optimization work
427 This function can only provide a guess, but it seems to work for
428 gcc output. It needs to guess right for gcc, otherwise gcc
429 will put what it thinks is a GP-relative instruction in a branch
432 I don't know if a fix is needed for the SVR4_PIC mode. I've only
433 fixed it for the non-PIC mode. KR 95/04/07 */
434 static int nopic_need_relax (symbolS *, int);
436 /* handle of the OPCODE hash table */
437 static struct hash_control *op_hash = NULL;
439 /* The opcode hash table we use for the mips16. */
440 static struct hash_control *mips16_op_hash = NULL;
442 /* This array holds the chars that always start a comment. If the
443 pre-processor is disabled, these aren't very useful */
444 const char comment_chars[] = "#";
446 /* This array holds the chars that only start a comment at the beginning of
447 a line. If the line seems to have the form '# 123 filename'
448 .line and .file directives will appear in the pre-processed output */
449 /* Note that input_file.c hand checks for '#' at the beginning of the
450 first line of the input file. This is because the compiler outputs
451 #NO_APP at the beginning of its output. */
452 /* Also note that C style comments are always supported. */
453 const char line_comment_chars[] = "#";
455 /* This array holds machine specific line separator characters. */
456 const char line_separator_chars[] = ";";
458 /* Chars that can be used to separate mant from exp in floating point nums */
459 const char EXP_CHARS[] = "eE";
461 /* Chars that mean this number is a floating point constant */
464 const char FLT_CHARS[] = "rRsSfFdDxXpP";
466 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
467 changed in read.c . Ideally it shouldn't have to know about it at all,
468 but nothing is ideal around here.
471 static char *insn_error;
473 static int auto_align = 1;
475 /* When outputting SVR4 PIC code, the assembler needs to know the
476 offset in the stack frame from which to restore the $gp register.
477 This is set by the .cprestore pseudo-op, and saved in this
479 static offsetT mips_cprestore_offset = -1;
481 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
482 more optimizations, it can use a register value instead of a memory-saved
483 offset and even an other register than $gp as global pointer. */
484 static offsetT mips_cpreturn_offset = -1;
485 static int mips_cpreturn_register = -1;
486 static int mips_gp_register = GP;
487 static int mips_gprel_offset = 0;
489 /* Whether mips_cprestore_offset has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_cprestore_valid = 0;
493 /* This is the register which holds the stack frame, as set by the
494 .frame pseudo-op. This is needed to implement .cprestore. */
495 static int mips_frame_reg = SP;
497 /* Whether mips_frame_reg has been set in the current function
498 (or whether it has already been warned about, if not). */
499 static int mips_frame_reg_valid = 0;
501 /* To output NOP instructions correctly, we need to keep information
502 about the previous two instructions. */
504 /* Whether we are optimizing. The default value of 2 means to remove
505 unneeded NOPs and swap branch instructions when possible. A value
506 of 1 means to not swap branches. A value of 0 means to always
508 static int mips_optimize = 2;
510 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
511 equivalent to seeing no -g option at all. */
512 static int mips_debug = 0;
514 /* The previous instruction. */
515 static struct mips_cl_insn prev_insn;
517 /* The instruction before prev_insn. */
518 static struct mips_cl_insn prev_prev_insn;
520 /* If we don't want information for prev_insn or prev_prev_insn, we
521 point the insn_mo field at this dummy integer. */
522 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
524 /* Non-zero if prev_insn is valid. */
525 static int prev_insn_valid;
527 /* The frag for the previous instruction. */
528 static struct frag *prev_insn_frag;
530 /* The offset into prev_insn_frag for the previous instruction. */
531 static long prev_insn_where;
533 /* The reloc type for the previous instruction, if any. */
534 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
536 /* The reloc for the previous instruction, if any. */
537 static fixS *prev_insn_fixp[3];
539 /* Non-zero if the previous instruction was in a delay slot. */
540 static int prev_insn_is_delay_slot;
542 /* Non-zero if the previous instruction was in a .set noreorder. */
543 static int prev_insn_unreordered;
545 /* Non-zero if the previous instruction uses an extend opcode (if
547 static int prev_insn_extended;
549 /* Non-zero if the previous previous instruction was in a .set
551 static int prev_prev_insn_unreordered;
553 /* If this is set, it points to a frag holding nop instructions which
554 were inserted before the start of a noreorder section. If those
555 nops turn out to be unnecessary, the size of the frag can be
557 static fragS *prev_nop_frag;
559 /* The number of nop instructions we created in prev_nop_frag. */
560 static int prev_nop_frag_holds;
562 /* The number of nop instructions that we know we need in
564 static int prev_nop_frag_required;
566 /* The number of instructions we've seen since prev_nop_frag. */
567 static int prev_nop_frag_since;
569 /* For ECOFF and ELF, relocations against symbols are done in two
570 parts, with a HI relocation and a LO relocation. Each relocation
571 has only 16 bits of space to store an addend. This means that in
572 order for the linker to handle carries correctly, it must be able
573 to locate both the HI and the LO relocation. This means that the
574 relocations must appear in order in the relocation table.
576 In order to implement this, we keep track of each unmatched HI
577 relocation. We then sort them so that they immediately precede the
578 corresponding LO relocation. */
583 struct mips_hi_fixup *next;
586 /* The section this fixup is in. */
590 /* The list of unmatched HI relocs. */
592 static struct mips_hi_fixup *mips_hi_fixup_list;
594 /* The frag containing the last explicit relocation operator.
595 Null if explicit relocations have not been used. */
597 static fragS *prev_reloc_op_frag;
599 /* Map normal MIPS register numbers to mips16 register numbers. */
601 #define X ILLEGAL_REG
602 static const int mips32_to_16_reg_map[] =
604 X, X, 2, 3, 4, 5, 6, 7,
605 X, X, X, X, X, X, X, X,
606 0, 1, X, X, X, X, X, X,
607 X, X, X, X, X, X, X, X
611 /* Map mips16 register numbers to normal MIPS register numbers. */
613 static const unsigned int mips16_to_32_reg_map[] =
615 16, 17, 2, 3, 4, 5, 6, 7
618 static int mips_fix_vr4120;
620 /* We don't relax branches by default, since this causes us to expand
621 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
622 fail to compute the offset before expanding the macro to the most
623 efficient expansion. */
625 static int mips_relax_branch;
627 /* The expansion of many macros depends on the type of symbol that
628 they refer to. For example, when generating position-dependent code,
629 a macro that refers to a symbol may have two different expansions,
630 one which uses GP-relative addresses and one which uses absolute
631 addresses. When generating SVR4-style PIC, a macro may have
632 different expansions for local and global symbols.
634 We handle these situations by generating both sequences and putting
635 them in variant frags. In position-dependent code, the first sequence
636 will be the GP-relative one and the second sequence will be the
637 absolute one. In SVR4 PIC, the first sequence will be for global
638 symbols and the second will be for local symbols.
640 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
641 SECOND are the lengths of the two sequences in bytes. These fields
642 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
643 the subtype has the following flags:
646 Set if it has been decided that we should use the second
647 sequence instead of the first.
650 Set in the first variant frag if the macro's second implementation
651 is longer than its first. This refers to the macro as a whole,
652 not an individual relaxation.
655 Set in the first variant frag if the macro appeared in a .set nomacro
656 block and if one alternative requires a warning but the other does not.
659 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
662 The frag's "opcode" points to the first fixup for relaxable code.
664 Relaxable macros are generated using a sequence such as:
666 relax_start (SYMBOL);
667 ... generate first expansion ...
669 ... generate second expansion ...
672 The code and fixups for the unwanted alternative are discarded
673 by md_convert_frag. */
674 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
676 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
677 #define RELAX_SECOND(X) ((X) & 0xff)
678 #define RELAX_USE_SECOND 0x10000
679 #define RELAX_SECOND_LONGER 0x20000
680 #define RELAX_NOMACRO 0x40000
681 #define RELAX_DELAY_SLOT 0x80000
683 /* Branch without likely bit. If label is out of range, we turn:
685 beq reg1, reg2, label
695 with the following opcode replacements:
702 bltzal <-> bgezal (with jal label instead of j label)
704 Even though keeping the delay slot instruction in the delay slot of
705 the branch would be more efficient, it would be very tricky to do
706 correctly, because we'd have to introduce a variable frag *after*
707 the delay slot instruction, and expand that instead. Let's do it
708 the easy way for now, even if the branch-not-taken case now costs
709 one additional instruction. Out-of-range branches are not supposed
710 to be common, anyway.
712 Branch likely. If label is out of range, we turn:
714 beql reg1, reg2, label
715 delay slot (annulled if branch not taken)
724 delay slot (executed only if branch taken)
727 It would be possible to generate a shorter sequence by losing the
728 likely bit, generating something like:
733 delay slot (executed only if branch taken)
745 bltzall -> bgezal (with jal label instead of j label)
746 bgezall -> bltzal (ditto)
749 but it's not clear that it would actually improve performance. */
750 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
753 | ((toofar) ? 1 : 0) \
755 | ((likely) ? 4 : 0) \
756 | ((uncond) ? 8 : 0)))
757 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
758 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
759 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
760 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
761 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
763 /* For mips16 code, we use an entirely different form of relaxation.
764 mips16 supports two versions of most instructions which take
765 immediate values: a small one which takes some small value, and a
766 larger one which takes a 16 bit value. Since branches also follow
767 this pattern, relaxing these values is required.
769 We can assemble both mips16 and normal MIPS code in a single
770 object. Therefore, we need to support this type of relaxation at
771 the same time that we support the relaxation described above. We
772 use the high bit of the subtype field to distinguish these cases.
774 The information we store for this type of relaxation is the
775 argument code found in the opcode file for this relocation, whether
776 the user explicitly requested a small or extended form, and whether
777 the relocation is in a jump or jal delay slot. That tells us the
778 size of the value, and how it should be stored. We also store
779 whether the fragment is considered to be extended or not. We also
780 store whether this is known to be a branch to a different section,
781 whether we have tried to relax this frag yet, and whether we have
782 ever extended a PC relative fragment because of a shift count. */
783 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
786 | ((small) ? 0x100 : 0) \
787 | ((ext) ? 0x200 : 0) \
788 | ((dslot) ? 0x400 : 0) \
789 | ((jal_dslot) ? 0x800 : 0))
790 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
791 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
792 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
793 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
794 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
795 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
796 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
797 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
798 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
799 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
800 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
801 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
803 /* Is the given value a sign-extended 32-bit value? */
804 #define IS_SEXT_32BIT_NUM(x) \
805 (((x) &~ (offsetT) 0x7fffffff) == 0 \
806 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
808 /* Is the given value a sign-extended 16-bit value? */
809 #define IS_SEXT_16BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fff) == 0 \
811 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
814 /* Global variables used when generating relaxable macros. See the
815 comment above RELAX_ENCODE for more details about how relaxation
818 /* 0 if we're not emitting a relaxable macro.
819 1 if we're emitting the first of the two relaxation alternatives.
820 2 if we're emitting the second alternative. */
823 /* The first relaxable fixup in the current frag. (In other words,
824 the first fixup that refers to relaxable code.) */
827 /* sizes[0] says how many bytes of the first alternative are stored in
828 the current frag. Likewise sizes[1] for the second alternative. */
829 unsigned int sizes[2];
831 /* The symbol on which the choice of sequence depends. */
835 /* Global variables used to decide whether a macro needs a warning. */
837 /* True if the macro is in a branch delay slot. */
838 bfd_boolean delay_slot_p;
840 /* For relaxable macros, sizes[0] is the length of the first alternative
841 in bytes and sizes[1] is the length of the second alternative.
842 For non-relaxable macros, both elements give the length of the
844 unsigned int sizes[2];
846 /* The first variant frag for this macro. */
848 } mips_macro_warning;
850 /* Prototypes for static functions. */
852 #define internalError() \
853 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
855 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
857 static void append_insn
858 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
859 static void mips_no_prev_insn (int);
860 static void mips16_macro_build
861 (expressionS *, const char *, const char *, va_list);
862 static void load_register (int, expressionS *, int);
863 static void macro_start (void);
864 static void macro_end (void);
865 static void macro (struct mips_cl_insn * ip);
866 static void mips16_macro (struct mips_cl_insn * ip);
867 #ifdef LOSING_COMPILER
868 static void macro2 (struct mips_cl_insn * ip);
870 static void mips_ip (char *str, struct mips_cl_insn * ip);
871 static void mips16_ip (char *str, struct mips_cl_insn * ip);
872 static void mips16_immed
873 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
874 unsigned long *, bfd_boolean *, unsigned short *);
875 static size_t my_getSmallExpression
876 (expressionS *, bfd_reloc_code_real_type *, char *);
877 static void my_getExpression (expressionS *, char *);
878 static void s_align (int);
879 static void s_change_sec (int);
880 static void s_change_section (int);
881 static void s_cons (int);
882 static void s_float_cons (int);
883 static void s_mips_globl (int);
884 static void s_option (int);
885 static void s_mipsset (int);
886 static void s_abicalls (int);
887 static void s_cpload (int);
888 static void s_cpsetup (int);
889 static void s_cplocal (int);
890 static void s_cprestore (int);
891 static void s_cpreturn (int);
892 static void s_gpvalue (int);
893 static void s_gpword (int);
894 static void s_gpdword (int);
895 static void s_cpadd (int);
896 static void s_insn (int);
897 static void md_obj_begin (void);
898 static void md_obj_end (void);
899 static void s_mips_ent (int);
900 static void s_mips_end (int);
901 static void s_mips_frame (int);
902 static void s_mips_mask (int reg_type);
903 static void s_mips_stab (int);
904 static void s_mips_weakext (int);
905 static void s_mips_file (int);
906 static void s_mips_loc (int);
907 static bfd_boolean pic_need_relax (symbolS *, asection *);
908 static int relaxed_branch_length (fragS *, asection *, int);
909 static int validate_mips_insn (const struct mips_opcode *);
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name; /* CPU or ISA name. */
917 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
918 int isa; /* ISA level. */
919 int cpu; /* CPU number (default CPU if ISA). */
922 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
923 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
924 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
928 The following pseudo-ops from the Kane and Heinrich MIPS book
929 should be defined here, but are currently unsupported: .alias,
930 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
932 The following pseudo-ops from the Kane and Heinrich MIPS book are
933 specific to the type of debugging information being generated, and
934 should be defined by the object format: .aent, .begin, .bend,
935 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
938 The following pseudo-ops from the Kane and Heinrich MIPS book are
939 not MIPS CPU specific, but are also not specific to the object file
940 format. This file is probably the best place to define them, but
941 they are not currently supported: .asm0, .endr, .lab, .repeat,
944 static const pseudo_typeS mips_pseudo_table[] =
946 /* MIPS specific pseudo-ops. */
947 {"option", s_option, 0},
948 {"set", s_mipsset, 0},
949 {"rdata", s_change_sec, 'r'},
950 {"sdata", s_change_sec, 's'},
951 {"livereg", s_ignore, 0},
952 {"abicalls", s_abicalls, 0},
953 {"cpload", s_cpload, 0},
954 {"cpsetup", s_cpsetup, 0},
955 {"cplocal", s_cplocal, 0},
956 {"cprestore", s_cprestore, 0},
957 {"cpreturn", s_cpreturn, 0},
958 {"gpvalue", s_gpvalue, 0},
959 {"gpword", s_gpword, 0},
960 {"gpdword", s_gpdword, 0},
961 {"cpadd", s_cpadd, 0},
964 /* Relatively generic pseudo-ops that happen to be used on MIPS
966 {"asciiz", stringer, 1},
967 {"bss", s_change_sec, 'b'},
970 {"dword", s_cons, 3},
971 {"weakext", s_mips_weakext, 0},
973 /* These pseudo-ops are defined in read.c, but must be overridden
974 here for one reason or another. */
975 {"align", s_align, 0},
977 {"data", s_change_sec, 'd'},
978 {"double", s_float_cons, 'd'},
979 {"float", s_float_cons, 'f'},
980 {"globl", s_mips_globl, 0},
981 {"global", s_mips_globl, 0},
982 {"hword", s_cons, 1},
987 {"section", s_change_section, 0},
988 {"short", s_cons, 1},
989 {"single", s_float_cons, 'f'},
990 {"stabn", s_mips_stab, 'n'},
991 {"text", s_change_sec, 't'},
994 { "extern", ecoff_directive_extern, 0},
999 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1001 /* These pseudo-ops should be defined by the object file format.
1002 However, a.out doesn't support them, so we have versions here. */
1003 {"aent", s_mips_ent, 1},
1004 {"bgnb", s_ignore, 0},
1005 {"end", s_mips_end, 0},
1006 {"endb", s_ignore, 0},
1007 {"ent", s_mips_ent, 0},
1008 {"file", s_mips_file, 0},
1009 {"fmask", s_mips_mask, 'F'},
1010 {"frame", s_mips_frame, 0},
1011 {"loc", s_mips_loc, 0},
1012 {"mask", s_mips_mask, 'R'},
1013 {"verstamp", s_ignore, 0},
1017 extern void pop_insert (const pseudo_typeS *);
1020 mips_pop_insert (void)
1022 pop_insert (mips_pseudo_table);
1023 if (! ECOFF_DEBUGGING)
1024 pop_insert (mips_nonecoff_pseudo_table);
1027 /* Symbols labelling the current insn. */
1029 struct insn_label_list
1031 struct insn_label_list *next;
1035 static struct insn_label_list *insn_labels;
1036 static struct insn_label_list *free_insn_labels;
1038 static void mips_clear_insn_labels (void);
1041 mips_clear_insn_labels (void)
1043 register struct insn_label_list **pl;
1045 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1051 static char *expr_end;
1053 /* Expressions which appear in instructions. These are set by
1056 static expressionS imm_expr;
1057 static expressionS imm2_expr;
1058 static expressionS offset_expr;
1060 /* Relocs associated with imm_expr and offset_expr. */
1062 static bfd_reloc_code_real_type imm_reloc[3]
1063 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1064 static bfd_reloc_code_real_type offset_reloc[3]
1065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1067 /* These are set by mips16_ip if an explicit extension is used. */
1069 static bfd_boolean mips16_small, mips16_ext;
1072 /* The pdr segment for per procedure frame/regmask info. Not used for
1075 static segT pdr_seg;
1078 /* The default target format to use. */
1081 mips_target_format (void)
1083 switch (OUTPUT_FLAVOR)
1085 case bfd_target_ecoff_flavour:
1086 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1087 case bfd_target_coff_flavour:
1089 case bfd_target_elf_flavour:
1091 /* This is traditional mips. */
1092 return (target_big_endian
1093 ? (HAVE_64BIT_OBJECTS
1094 ? "elf64-tradbigmips"
1096 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1097 : (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradlittlemips"
1100 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1106 ? "elf32-nbigmips" : "elf32-bigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-littlemips"
1110 ? "elf32-nlittlemips" : "elf32-littlemips")));
1118 /* This function is called once, at assembler startup time. It should
1119 set up all the tables, etc. that the MD part of the assembler will need. */
1124 register const char *retval = NULL;
1128 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1129 as_warn (_("Could not set architecture and machine"));
1131 op_hash = hash_new ();
1133 for (i = 0; i < NUMOPCODES;)
1135 const char *name = mips_opcodes[i].name;
1137 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1140 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1141 mips_opcodes[i].name, retval);
1142 /* Probably a memory allocation problem? Give up now. */
1143 as_fatal (_("Broken assembler. No assembly attempted."));
1147 if (mips_opcodes[i].pinfo != INSN_MACRO)
1149 if (!validate_mips_insn (&mips_opcodes[i]))
1154 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1157 mips16_op_hash = hash_new ();
1160 while (i < bfd_mips16_num_opcodes)
1162 const char *name = mips16_opcodes[i].name;
1164 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1166 as_fatal (_("internal: can't hash `%s': %s"),
1167 mips16_opcodes[i].name, retval);
1170 if (mips16_opcodes[i].pinfo != INSN_MACRO
1171 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1172 != mips16_opcodes[i].match))
1174 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1175 mips16_opcodes[i].name, mips16_opcodes[i].args);
1180 while (i < bfd_mips16_num_opcodes
1181 && strcmp (mips16_opcodes[i].name, name) == 0);
1185 as_fatal (_("Broken assembler. No assembly attempted."));
1187 /* We add all the general register names to the symbol table. This
1188 helps us detect invalid uses of them. */
1189 for (i = 0; i < 32; i++)
1193 sprintf (buf, "$%d", i);
1194 symbol_table_insert (symbol_new (buf, reg_section, i,
1195 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1208 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1214 &zero_address_frag));
1216 /* If we don't add these register names to the symbol table, they
1217 may end up being added as regular symbols by operand(), and then
1218 make it to the object file as undefined in case they're not
1219 regarded as local symbols. They're local in o32, since `$' is a
1220 local symbol prefix, but not in n32 or n64. */
1221 for (i = 0; i < 8; i++)
1225 sprintf (buf, "$fcc%i", i);
1226 symbol_table_insert (symbol_new (buf, reg_section, -1,
1227 &zero_address_frag));
1230 mips_no_prev_insn (FALSE);
1233 mips_cprmask[0] = 0;
1234 mips_cprmask[1] = 0;
1235 mips_cprmask[2] = 0;
1236 mips_cprmask[3] = 0;
1238 /* set the default alignment for the text section (2**2) */
1239 record_alignment (text_section, 2);
1241 bfd_set_gp_size (stdoutput, g_switch_value);
1243 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1245 /* On a native system, sections must be aligned to 16 byte
1246 boundaries. When configured for an embedded ELF target, we
1248 if (strcmp (TARGET_OS, "elf") != 0)
1250 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1251 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1252 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1255 /* Create a .reginfo section for register masks and a .mdebug
1256 section for debugging information. */
1264 subseg = now_subseg;
1266 /* The ABI says this section should be loaded so that the
1267 running program can access it. However, we don't load it
1268 if we are configured for an embedded target */
1269 flags = SEC_READONLY | SEC_DATA;
1270 if (strcmp (TARGET_OS, "elf") != 0)
1271 flags |= SEC_ALLOC | SEC_LOAD;
1273 if (mips_abi != N64_ABI)
1275 sec = subseg_new (".reginfo", (subsegT) 0);
1277 bfd_set_section_flags (stdoutput, sec, flags);
1278 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1281 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1286 /* The 64-bit ABI uses a .MIPS.options section rather than
1287 .reginfo section. */
1288 sec = subseg_new (".MIPS.options", (subsegT) 0);
1289 bfd_set_section_flags (stdoutput, sec, flags);
1290 bfd_set_section_alignment (stdoutput, sec, 3);
1293 /* Set up the option header. */
1295 Elf_Internal_Options opthdr;
1298 opthdr.kind = ODK_REGINFO;
1299 opthdr.size = (sizeof (Elf_External_Options)
1300 + sizeof (Elf64_External_RegInfo));
1303 f = frag_more (sizeof (Elf_External_Options));
1304 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1305 (Elf_External_Options *) f);
1307 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1312 if (ECOFF_DEBUGGING)
1314 sec = subseg_new (".mdebug", (subsegT) 0);
1315 (void) bfd_set_section_flags (stdoutput, sec,
1316 SEC_HAS_CONTENTS | SEC_READONLY);
1317 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1320 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1322 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1323 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1324 SEC_READONLY | SEC_RELOC
1326 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1330 subseg_set (seg, subseg);
1334 if (! ECOFF_DEBUGGING)
1341 if (! ECOFF_DEBUGGING)
1346 md_assemble (char *str)
1348 struct mips_cl_insn insn;
1349 bfd_reloc_code_real_type unused_reloc[3]
1350 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1352 imm_expr.X_op = O_absent;
1353 imm2_expr.X_op = O_absent;
1354 offset_expr.X_op = O_absent;
1355 imm_reloc[0] = BFD_RELOC_UNUSED;
1356 imm_reloc[1] = BFD_RELOC_UNUSED;
1357 imm_reloc[2] = BFD_RELOC_UNUSED;
1358 offset_reloc[0] = BFD_RELOC_UNUSED;
1359 offset_reloc[1] = BFD_RELOC_UNUSED;
1360 offset_reloc[2] = BFD_RELOC_UNUSED;
1362 if (mips_opts.mips16)
1363 mips16_ip (str, &insn);
1366 mips_ip (str, &insn);
1367 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1368 str, insn.insn_opcode));
1373 as_bad ("%s `%s'", insn_error, str);
1377 if (insn.insn_mo->pinfo == INSN_MACRO)
1380 if (mips_opts.mips16)
1381 mips16_macro (&insn);
1388 if (imm_expr.X_op != O_absent)
1389 append_insn (&insn, &imm_expr, imm_reloc);
1390 else if (offset_expr.X_op != O_absent)
1391 append_insn (&insn, &offset_expr, offset_reloc);
1393 append_insn (&insn, NULL, unused_reloc);
1397 /* Return true if the given relocation might need a matching %lo().
1398 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1399 applied to local symbols. */
1401 static inline bfd_boolean
1402 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1404 return (HAVE_IN_PLACE_ADDENDS
1405 && (reloc == BFD_RELOC_HI16_S
1406 || reloc == BFD_RELOC_MIPS_GOT16));
1409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1412 static inline bfd_boolean
1413 fixup_has_matching_lo_p (fixS *fixp)
1415 return (fixp->fx_next != NULL
1416 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1417 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1418 && fixp->fx_offset == fixp->fx_next->fx_offset);
1421 /* See whether instruction IP reads register REG. CLASS is the type
1425 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1426 enum mips_regclass class)
1428 if (class == MIPS16_REG)
1430 assert (mips_opts.mips16);
1431 reg = mips16_to_32_reg_map[reg];
1432 class = MIPS_GR_REG;
1435 /* Don't report on general register ZERO, since it never changes. */
1436 if (class == MIPS_GR_REG && reg == ZERO)
1439 if (class == MIPS_FP_REG)
1441 assert (! mips_opts.mips16);
1442 /* If we are called with either $f0 or $f1, we must check $f0.
1443 This is not optimal, because it will introduce an unnecessary
1444 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1445 need to distinguish reading both $f0 and $f1 or just one of
1446 them. Note that we don't have to check the other way,
1447 because there is no instruction that sets both $f0 and $f1
1448 and requires a delay. */
1449 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1450 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1451 == (reg &~ (unsigned) 1)))
1453 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1454 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1455 == (reg &~ (unsigned) 1)))
1458 else if (! mips_opts.mips16)
1460 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1461 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1463 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1464 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1469 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1470 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1471 & MIPS16OP_MASK_RX)]
1474 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1475 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1476 & MIPS16OP_MASK_RY)]
1479 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1480 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1481 & MIPS16OP_MASK_MOVE32Z)]
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1488 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1490 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1491 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1492 & MIPS16OP_MASK_REGR32) == reg)
1499 /* This function returns true if modifying a register requires a
1503 reg_needs_delay (unsigned int reg)
1505 unsigned long prev_pinfo;
1507 prev_pinfo = prev_insn.insn_mo->pinfo;
1508 if (! mips_opts.noreorder
1509 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1510 && ! gpr_interlocks)
1511 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1512 && ! cop_interlocks)))
1514 /* A load from a coprocessor or from memory. All load delays
1515 delay the use of general register rt for one instruction. */
1516 /* Itbl support may require additional care here. */
1517 know (prev_pinfo & INSN_WRITE_GPR_T);
1518 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1525 /* Mark instruction labels in mips16 mode. This permits the linker to
1526 handle them specially, such as generating jalx instructions when
1527 needed. We also make them odd for the duration of the assembly, in
1528 order to generate the right sort of code. We will make them even
1529 in the adjust_symtab routine, while leaving them marked. This is
1530 convenient for the debugger and the disassembler. The linker knows
1531 to make them odd again. */
1534 mips16_mark_labels (void)
1536 if (mips_opts.mips16)
1538 struct insn_label_list *l;
1541 for (l = insn_labels; l != NULL; l = l->next)
1544 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1545 S_SET_OTHER (l->label, STO_MIPS16);
1547 val = S_GET_VALUE (l->label);
1549 S_SET_VALUE (l->label, val + 1);
1554 /* End the current frag. Make it a variant frag and record the
1558 relax_close_frag (void)
1560 mips_macro_warning.first_frag = frag_now;
1561 frag_var (rs_machine_dependent, 0, 0,
1562 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1563 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1565 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1566 mips_relax.first_fixup = 0;
1569 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1570 See the comment above RELAX_ENCODE for more details. */
1573 relax_start (symbolS *symbol)
1575 assert (mips_relax.sequence == 0);
1576 mips_relax.sequence = 1;
1577 mips_relax.symbol = symbol;
1580 /* Start generating the second version of a relaxable sequence.
1581 See the comment above RELAX_ENCODE for more details. */
1586 assert (mips_relax.sequence == 1);
1587 mips_relax.sequence = 2;
1590 /* End the current relaxable sequence. */
1595 assert (mips_relax.sequence == 2);
1596 relax_close_frag ();
1597 mips_relax.sequence = 0;
1600 /* Output an instruction. IP is the instruction information.
1601 ADDRESS_EXPR is an operand of the instruction to be used with
1605 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1606 bfd_reloc_code_real_type *reloc_type)
1608 register unsigned long prev_pinfo, pinfo;
1612 relax_stateT prev_insn_frag_type = 0;
1613 bfd_boolean relaxed_branch = FALSE;
1614 bfd_boolean force_new_frag = FALSE;
1616 /* Mark instruction labels in mips16 mode. */
1617 mips16_mark_labels ();
1619 prev_pinfo = prev_insn.insn_mo->pinfo;
1620 pinfo = ip->insn_mo->pinfo;
1622 if (mips_relax.sequence != 2
1623 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1627 /* If the previous insn required any delay slots, see if we need
1628 to insert a NOP or two. There are eight kinds of possible
1629 hazards, of which an instruction can have at most one type.
1630 (1) a load from memory delay
1631 (2) a load from a coprocessor delay
1632 (3) an unconditional branch delay
1633 (4) a conditional branch delay
1634 (5) a move to coprocessor register delay
1635 (6) a load coprocessor register from memory delay
1636 (7) a coprocessor condition code delay
1637 (8) a HI/LO special register delay
1639 There are a lot of optimizations we could do that we don't.
1640 In particular, we do not, in general, reorder instructions.
1641 If you use gcc with optimization, it will reorder
1642 instructions and generally do much more optimization then we
1643 do here; repeating all that work in the assembler would only
1644 benefit hand written assembly code, and does not seem worth
1647 /* This is how a NOP is emitted. */
1648 #define emit_nop() \
1650 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1651 : md_number_to_chars (frag_more (4), 0, 4))
1653 /* The previous insn might require a delay slot, depending upon
1654 the contents of the current insn. */
1655 if (! mips_opts.mips16
1656 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1657 && ! gpr_interlocks)
1658 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1659 && ! cop_interlocks)))
1661 /* A load from a coprocessor or from memory. All load
1662 delays delay the use of general register rt for one
1664 /* Itbl support may require additional care here. */
1665 know (prev_pinfo & INSN_WRITE_GPR_T);
1666 if (mips_optimize == 0
1667 || insn_uses_reg (ip,
1668 ((prev_insn.insn_opcode >> OP_SH_RT)
1673 else if (! mips_opts.mips16
1674 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1675 && ! cop_interlocks)
1676 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1677 && ! cop_mem_interlocks)))
1679 /* A generic coprocessor delay. The previous instruction
1680 modified a coprocessor general or control register. If
1681 it modified a control register, we need to avoid any
1682 coprocessor instruction (this is probably not always
1683 required, but it sometimes is). If it modified a general
1684 register, we avoid using that register.
1686 This case is not handled very well. There is no special
1687 knowledge of CP0 handling, and the coprocessors other
1688 than the floating point unit are not distinguished at
1690 /* Itbl support may require additional care here. FIXME!
1691 Need to modify this to include knowledge about
1692 user specified delays! */
1693 if (prev_pinfo & INSN_WRITE_FPR_T)
1695 if (mips_optimize == 0
1696 || insn_uses_reg (ip,
1697 ((prev_insn.insn_opcode >> OP_SH_FT)
1702 else if (prev_pinfo & INSN_WRITE_FPR_S)
1704 if (mips_optimize == 0
1705 || insn_uses_reg (ip,
1706 ((prev_insn.insn_opcode >> OP_SH_FS)
1713 /* We don't know exactly what the previous instruction
1714 does. If the current instruction uses a coprocessor
1715 register, we must insert a NOP. If previous
1716 instruction may set the condition codes, and the
1717 current instruction uses them, we must insert two
1719 /* Itbl support may require additional care here. */
1720 if (mips_optimize == 0
1721 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1722 && (pinfo & INSN_READ_COND_CODE)))
1724 else if (pinfo & INSN_COP)
1728 else if (! mips_opts.mips16
1729 && (prev_pinfo & INSN_WRITE_COND_CODE)
1730 && ! cop_interlocks)
1732 /* The previous instruction sets the coprocessor condition
1733 codes, but does not require a general coprocessor delay
1734 (this means it is a floating point comparison
1735 instruction). If this instruction uses the condition
1736 codes, we need to insert a single NOP. */
1737 /* Itbl support may require additional care here. */
1738 if (mips_optimize == 0
1739 || (pinfo & INSN_READ_COND_CODE))
1743 /* If we're fixing up mfhi/mflo for the r7000 and the
1744 previous insn was an mfhi/mflo and the current insn
1745 reads the register that the mfhi/mflo wrote to, then
1748 else if (mips_7000_hilo_fix
1749 && MF_HILO_INSN (prev_pinfo)
1750 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1757 /* If we're fixing up mfhi/mflo for the r7000 and the
1758 2nd previous insn was an mfhi/mflo and the current insn
1759 reads the register that the mfhi/mflo wrote to, then
1762 else if (mips_7000_hilo_fix
1763 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1764 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1772 else if (prev_pinfo & INSN_READ_LO)
1774 /* The previous instruction reads the LO register; if the
1775 current instruction writes to the LO register, we must
1776 insert two NOPS. Some newer processors have interlocks.
1777 Also the tx39's multiply instructions can be executed
1778 immediately after a read from HI/LO (without the delay),
1779 though the tx39's divide insns still do require the
1781 if (! (hilo_interlocks
1782 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1783 && (mips_optimize == 0
1784 || (pinfo & INSN_WRITE_LO)))
1786 /* Most mips16 branch insns don't have a delay slot.
1787 If a read from LO is immediately followed by a branch
1788 to a write to LO we have a read followed by a write
1789 less than 2 insns away. We assume the target of
1790 a branch might be a write to LO, and insert a nop
1791 between a read and an immediately following branch. */
1792 else if (mips_opts.mips16
1793 && (mips_optimize == 0
1794 || (pinfo & MIPS16_INSN_BRANCH)))
1797 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1799 /* The previous instruction reads the HI register; if the
1800 current instruction writes to the HI register, we must
1801 insert a NOP. Some newer processors have interlocks.
1802 Also the note tx39's multiply above. */
1803 if (! (hilo_interlocks
1804 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1805 && (mips_optimize == 0
1806 || (pinfo & INSN_WRITE_HI)))
1808 /* Most mips16 branch insns don't have a delay slot.
1809 If a read from HI is immediately followed by a branch
1810 to a write to HI we have a read followed by a write
1811 less than 2 insns away. We assume the target of
1812 a branch might be a write to HI, and insert a nop
1813 between a read and an immediately following branch. */
1814 else if (mips_opts.mips16
1815 && (mips_optimize == 0
1816 || (pinfo & MIPS16_INSN_BRANCH)))
1820 /* If the previous instruction was in a noreorder section, then
1821 we don't want to insert the nop after all. */
1822 /* Itbl support may require additional care here. */
1823 if (prev_insn_unreordered)
1826 /* There are two cases which require two intervening
1827 instructions: 1) setting the condition codes using a move to
1828 coprocessor instruction which requires a general coprocessor
1829 delay and then reading the condition codes 2) reading the HI
1830 or LO register and then writing to it (except on processors
1831 which have interlocks). If we are not already emitting a NOP
1832 instruction, we must check for these cases compared to the
1833 instruction previous to the previous instruction. */
1834 if ((! mips_opts.mips16
1835 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1836 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1837 && (pinfo & INSN_READ_COND_CODE)
1838 && ! cop_interlocks)
1839 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1840 && (pinfo & INSN_WRITE_LO)
1841 && ! (hilo_interlocks
1842 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1843 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1844 && (pinfo & INSN_WRITE_HI)
1845 && ! (hilo_interlocks
1846 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1851 if (prev_prev_insn_unreordered)
1854 if (prev_prev_nop && nops == 0)
1857 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1859 /* We're out of bits in pinfo, so we must resort to string
1860 ops here. Shortcuts are selected based on opcodes being
1861 limited to the VR4120 instruction set. */
1863 const char *pn = prev_insn.insn_mo->name;
1864 const char *tn = ip->insn_mo->name;
1865 if (strncmp (pn, "macc", 4) == 0
1866 || strncmp (pn, "dmacc", 5) == 0)
1868 /* Errata 21 - [D]DIV[U] after [D]MACC */
1869 if (strstr (tn, "div"))
1872 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1873 instruction is executed immediately after a MACC or
1874 DMACC instruction, the result of [either instruction]
1876 if (strncmp (tn, "mult", 4) == 0
1877 || strncmp (tn, "dmult", 5) == 0)
1880 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1881 Applies on top of VR4181A MD(1) errata. */
1882 if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn, "mtlo") == 0
1887 || strcmp (tn, "mthi") == 0)
1890 else if (strncmp (pn, "dmult", 5) == 0
1891 && (strncmp (tn, "dmult", 5) == 0
1892 || strncmp (tn, "dmacc", 5) == 0))
1894 /* Here is the rest of errata 23. */
1897 else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
1898 && (strncmp (tn, "macc", 4) == 0
1899 || strncmp (tn, "dmacc", 5) == 0))
1901 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1902 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1903 DDIV or DDIVU instruction, the result of the MACC or
1904 DMACC instruction is incorrect.". This partly overlaps
1905 the workaround for errata 23. */
1908 if (nops < min_nops)
1912 /* If we are being given a nop instruction, don't bother with
1913 one of the nops we would otherwise output. This will only
1914 happen when a nop instruction is used with mips_optimize set
1917 && ! mips_opts.noreorder
1918 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1921 /* Now emit the right number of NOP instructions. */
1922 if (nops > 0 && ! mips_opts.noreorder)
1925 unsigned long old_frag_offset;
1927 struct insn_label_list *l;
1929 old_frag = frag_now;
1930 old_frag_offset = frag_now_fix ();
1932 for (i = 0; i < nops; i++)
1937 listing_prev_line ();
1938 /* We may be at the start of a variant frag. In case we
1939 are, make sure there is enough space for the frag
1940 after the frags created by listing_prev_line. The
1941 argument to frag_grow here must be at least as large
1942 as the argument to all other calls to frag_grow in
1943 this file. We don't have to worry about being in the
1944 middle of a variant frag, because the variants insert
1945 all needed nop instructions themselves. */
1949 for (l = insn_labels; l != NULL; l = l->next)
1953 assert (S_GET_SEGMENT (l->label) == now_seg);
1954 symbol_set_frag (l->label, frag_now);
1955 val = (valueT) frag_now_fix ();
1956 /* mips16 text labels are stored as odd. */
1957 if (mips_opts.mips16)
1959 S_SET_VALUE (l->label, val);
1962 #ifndef NO_ECOFF_DEBUGGING
1963 if (ECOFF_DEBUGGING)
1964 ecoff_fix_loc (old_frag, old_frag_offset);
1967 else if (prev_nop_frag != NULL)
1969 /* We have a frag holding nops we may be able to remove. If
1970 we don't need any nops, we can decrease the size of
1971 prev_nop_frag by the size of one instruction. If we do
1972 need some nops, we count them in prev_nops_required. */
1973 if (prev_nop_frag_since == 0)
1977 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1978 --prev_nop_frag_holds;
1981 prev_nop_frag_required += nops;
1985 if (prev_prev_nop == 0)
1987 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1988 --prev_nop_frag_holds;
1991 ++prev_nop_frag_required;
1994 if (prev_nop_frag_holds <= prev_nop_frag_required)
1995 prev_nop_frag = NULL;
1997 ++prev_nop_frag_since;
1999 /* Sanity check: by the time we reach the second instruction
2000 after prev_nop_frag, we should have used up all the nops
2001 one way or another. */
2002 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2006 /* Record the frag type before frag_var. */
2008 prev_insn_frag_type = prev_insn_frag->fr_type;
2011 && *reloc_type == BFD_RELOC_16_PCREL_S2
2012 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2013 || pinfo & INSN_COND_BRANCH_LIKELY)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts.warn_about_macros
2019 && !(mips_opts.noat && mips_pic != NO_PIC)
2020 && !mips_opts.mips16)
2022 relaxed_branch = TRUE;
2023 f = frag_var (rs_machine_dependent,
2024 relaxed_branch_length
2026 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2027 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2029 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2030 pinfo & INSN_COND_BRANCH_LIKELY,
2031 pinfo & INSN_WRITE_GPR_31,
2033 address_expr->X_add_symbol,
2034 address_expr->X_add_number,
2036 *reloc_type = BFD_RELOC_UNUSED;
2038 else if (*reloc_type > BFD_RELOC_UNUSED)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts.mips16 && address_expr != NULL);
2042 f = frag_var (rs_machine_dependent, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2044 mips16_small, mips16_ext,
2046 & INSN_UNCOND_BRANCH_DELAY),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP)),
2049 make_expr_symbol (address_expr), 0, NULL);
2051 else if (mips_opts.mips16
2053 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2055 /* Make sure there is enough room to swap this instruction with
2056 a following jump instruction. */
2062 if (mips_opts.mips16
2063 && mips_opts.noreorder
2064 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2065 as_warn (_("extended instruction in delay slot"));
2067 if (mips_relax.sequence)
2069 /* If we've reached the end of this frag, turn it into a variant
2070 frag and record the information for the instructions we've
2072 if (frag_room () < 4)
2073 relax_close_frag ();
2074 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2077 if (mips_relax.sequence != 2)
2078 mips_macro_warning.sizes[0] += 4;
2079 if (mips_relax.sequence != 1)
2080 mips_macro_warning.sizes[1] += 4;
2085 fixp[0] = fixp[1] = fixp[2] = NULL;
2086 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2088 if (address_expr->X_op == O_constant)
2092 switch (*reloc_type)
2095 ip->insn_opcode |= address_expr->X_add_number;
2098 case BFD_RELOC_MIPS_HIGHEST:
2099 tmp = (address_expr->X_add_number
2100 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2102 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2105 case BFD_RELOC_MIPS_HIGHER:
2106 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2107 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2110 case BFD_RELOC_HI16_S:
2111 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2115 case BFD_RELOC_HI16:
2116 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2119 case BFD_RELOC_UNUSED:
2120 case BFD_RELOC_LO16:
2121 case BFD_RELOC_MIPS_GOT_DISP:
2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2125 case BFD_RELOC_MIPS_JMP:
2126 if ((address_expr->X_add_number & 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr->X_add_number);
2129 if (address_expr->X_add_number & ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr->X_add_number);
2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP:
2136 if ((address_expr->X_add_number & 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr->X_add_number);
2139 if (address_expr->X_add_number & ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr->X_add_number);
2143 (((address_expr->X_add_number & 0x7c0000) << 3)
2144 | ((address_expr->X_add_number & 0xf800000) >> 7)
2145 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2:
2155 else if (*reloc_type < BFD_RELOC_UNUSED)
2158 reloc_howto_type *howto;
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i = 1; i < 3; i++)
2164 if (reloc_type[i] == BFD_RELOC_UNUSED)
2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2169 bfd_get_reloc_size(howto),
2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2177 && ! howto->partial_inplace
2178 && (reloc_type[0] == BFD_RELOC_16
2179 || reloc_type[0] == BFD_RELOC_32
2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2181 || reloc_type[0] == BFD_RELOC_HI16_S
2182 || reloc_type[0] == BFD_RELOC_LO16
2183 || reloc_type[0] == BFD_RELOC_GPREL16
2184 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2185 || reloc_type[0] == BFD_RELOC_GPREL32
2186 || reloc_type[0] == BFD_RELOC_64
2187 || reloc_type[0] == BFD_RELOC_CTOR
2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2194 fixp[0]->fx_no_overflow = 1;
2196 if (mips_relax.sequence)
2198 if (mips_relax.first_fixup == 0)
2199 mips_relax.first_fixup = fixp[0];
2201 else if (reloc_needs_lo_p (*reloc_type))
2203 struct mips_hi_fixup *hi_fixup;
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup = mips_hi_fixup_list;
2208 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2210 hi_fixup = ((struct mips_hi_fixup *)
2211 xmalloc (sizeof (struct mips_hi_fixup)));
2212 hi_fixup->next = mips_hi_fixup_list;
2213 mips_hi_fixup_list = hi_fixup;
2215 hi_fixup->fixp = fixp[0];
2216 hi_fixup->seg = now_seg;
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i = 1; i < 3; i++)
2225 if (reloc_type[i] != BFD_RELOC_UNUSED)
2227 fixp[i] = fix_new (frag_now, fixp[0]->fx_where,
2228 fixp[0]->fx_size, NULL, 0,
2229 FALSE, reloc_type[i]);
2231 /* Use fx_tcbit to mark compound relocs. */
2232 fixp[0]->fx_tcbit = 1;
2233 fixp[i]->fx_tcbit = 1;
2238 if (! mips_opts.mips16)
2240 md_number_to_chars (f, ip->insn_opcode, 4);
2242 dwarf2_emit_insn (4);
2245 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2247 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2248 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2250 /* The value passed to dwarf2_emit_insn is the distance between
2251 the end of the current instruction and the address that should
2252 be recorded in the debug tables. Since we want to use ISA-encoded
2253 addresses in MIPS16 debug info, the value is one byte less than
2254 the real instruction length. */
2255 dwarf2_emit_insn (3);
2262 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2265 md_number_to_chars (f, ip->insn_opcode, 2);
2267 dwarf2_emit_insn (ip->use_extend ? 3 : 1);
2271 /* Update the register mask information. */
2272 if (! mips_opts.mips16)
2274 if (pinfo & INSN_WRITE_GPR_D)
2275 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2276 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2277 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2278 if (pinfo & INSN_READ_GPR_S)
2279 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2280 if (pinfo & INSN_WRITE_GPR_31)
2281 mips_gprmask |= 1 << RA;
2282 if (pinfo & INSN_WRITE_FPR_D)
2283 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2284 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2285 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2286 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2287 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2288 if ((pinfo & INSN_READ_FPR_R) != 0)
2289 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2290 if (pinfo & INSN_COP)
2292 /* We don't keep enough information to sort these cases out.
2293 The itbl support does keep this information however, although
2294 we currently don't support itbl fprmats as part of the cop
2295 instruction. May want to add this support in the future. */
2297 /* Never set the bit for $0, which is always zero. */
2298 mips_gprmask &= ~1 << 0;
2302 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2303 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2304 & MIPS16OP_MASK_RX);
2305 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2306 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2307 & MIPS16OP_MASK_RY);
2308 if (pinfo & MIPS16_INSN_WRITE_Z)
2309 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2310 & MIPS16OP_MASK_RZ);
2311 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2312 mips_gprmask |= 1 << TREG;
2313 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2314 mips_gprmask |= 1 << SP;
2315 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2316 mips_gprmask |= 1 << RA;
2317 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2318 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2319 if (pinfo & MIPS16_INSN_READ_Z)
2320 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2321 & MIPS16OP_MASK_MOVE32Z);
2322 if (pinfo & MIPS16_INSN_READ_GPR_X)
2323 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2324 & MIPS16OP_MASK_REGR32);
2327 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2329 /* Filling the branch delay slot is more complex. We try to
2330 switch the branch with the previous instruction, which we can
2331 do if the previous instruction does not set up a condition
2332 that the branch tests and if the branch is not itself the
2333 target of any branch. */
2334 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2335 || (pinfo & INSN_COND_BRANCH_DELAY))
2337 if (mips_optimize < 2
2338 /* If we have seen .set volatile or .set nomove, don't
2340 || mips_opts.nomove != 0
2341 /* If we had to emit any NOP instructions, then we
2342 already know we can not swap. */
2344 /* If we don't even know the previous insn, we can not
2346 || ! prev_insn_valid
2347 /* If the previous insn is already in a branch delay
2348 slot, then we can not swap. */
2349 || prev_insn_is_delay_slot
2350 /* If the previous previous insn was in a .set
2351 noreorder, we can't swap. Actually, the MIPS
2352 assembler will swap in this situation. However, gcc
2353 configured -with-gnu-as will generate code like
2359 in which we can not swap the bne and INSN. If gcc is
2360 not configured -with-gnu-as, it does not output the
2361 .set pseudo-ops. We don't have to check
2362 prev_insn_unreordered, because prev_insn_valid will
2363 be 0 in that case. We don't want to use
2364 prev_prev_insn_valid, because we do want to be able
2365 to swap at the start of a function. */
2366 || prev_prev_insn_unreordered
2367 /* If the branch is itself the target of a branch, we
2368 can not swap. We cheat on this; all we check for is
2369 whether there is a label on this instruction. If
2370 there are any branches to anything other than a
2371 label, users must use .set noreorder. */
2372 || insn_labels != NULL
2373 /* If the previous instruction is in a variant frag
2374 other than this branch's one, we cannot do the swap.
2375 This does not apply to the mips16, which uses variant
2376 frags for different purposes. */
2377 || (! mips_opts.mips16
2378 && prev_insn_frag_type == rs_machine_dependent)
2379 /* If the branch reads the condition codes, we don't
2380 even try to swap, because in the sequence
2385 we can not swap, and I don't feel like handling that
2387 || (! mips_opts.mips16
2388 && (pinfo & INSN_READ_COND_CODE)
2389 && ! cop_interlocks)
2390 /* We can not swap with an instruction that requires a
2391 delay slot, because the target of the branch might
2392 interfere with that instruction. */
2393 || (! mips_opts.mips16
2395 /* Itbl support may require additional care here. */
2396 & (INSN_LOAD_COPROC_DELAY
2397 | INSN_COPROC_MOVE_DELAY
2398 | INSN_WRITE_COND_CODE))
2399 && ! cop_interlocks)
2400 || (! (hilo_interlocks
2401 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2405 || (! mips_opts.mips16
2406 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2407 && ! gpr_interlocks)
2408 || (! mips_opts.mips16
2409 /* Itbl support may require additional care here. */
2410 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2411 && ! cop_mem_interlocks)
2412 /* We can not swap with a branch instruction. */
2414 & (INSN_UNCOND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_DELAY
2416 | INSN_COND_BRANCH_LIKELY))
2417 /* We do not swap with a trap instruction, since it
2418 complicates trap handlers to have the trap
2419 instruction be in a delay slot. */
2420 || (prev_pinfo & INSN_TRAP)
2421 /* If the branch reads a register that the previous
2422 instruction sets, we can not swap. */
2423 || (! mips_opts.mips16
2424 && (prev_pinfo & INSN_WRITE_GPR_T)
2425 && insn_uses_reg (ip,
2426 ((prev_insn.insn_opcode >> OP_SH_RT)
2429 || (! mips_opts.mips16
2430 && (prev_pinfo & INSN_WRITE_GPR_D)
2431 && insn_uses_reg (ip,
2432 ((prev_insn.insn_opcode >> OP_SH_RD)
2435 || (mips_opts.mips16
2436 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2437 && insn_uses_reg (ip,
2438 ((prev_insn.insn_opcode
2440 & MIPS16OP_MASK_RX),
2442 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2443 && insn_uses_reg (ip,
2444 ((prev_insn.insn_opcode
2446 & MIPS16OP_MASK_RY),
2448 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2449 && insn_uses_reg (ip,
2450 ((prev_insn.insn_opcode
2452 & MIPS16OP_MASK_RZ),
2454 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2455 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2456 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2457 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2458 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2459 && insn_uses_reg (ip,
2460 MIPS16OP_EXTRACT_REG32R (prev_insn.
2463 /* If the branch writes a register that the previous
2464 instruction sets, we can not swap (we know that
2465 branches write only to RD or to $31). */
2466 || (! mips_opts.mips16
2467 && (prev_pinfo & INSN_WRITE_GPR_T)
2468 && (((pinfo & INSN_WRITE_GPR_D)
2469 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2470 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2471 || ((pinfo & INSN_WRITE_GPR_31)
2472 && (((prev_insn.insn_opcode >> OP_SH_RT)
2475 || (! mips_opts.mips16
2476 && (prev_pinfo & INSN_WRITE_GPR_D)
2477 && (((pinfo & INSN_WRITE_GPR_D)
2478 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2479 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2480 || ((pinfo & INSN_WRITE_GPR_31)
2481 && (((prev_insn.insn_opcode >> OP_SH_RD)
2484 || (mips_opts.mips16
2485 && (pinfo & MIPS16_INSN_WRITE_31)
2486 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2487 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2488 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2490 /* If the branch writes a register that the previous
2491 instruction reads, we can not swap (we know that
2492 branches only write to RD or to $31). */
2493 || (! mips_opts.mips16
2494 && (pinfo & INSN_WRITE_GPR_D)
2495 && insn_uses_reg (&prev_insn,
2496 ((ip->insn_opcode >> OP_SH_RD)
2499 || (! mips_opts.mips16
2500 && (pinfo & INSN_WRITE_GPR_31)
2501 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2502 || (mips_opts.mips16
2503 && (pinfo & MIPS16_INSN_WRITE_31)
2504 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2511 && ! cop_interlocks)
2512 || ((prev_prev_insn.insn_mo->pinfo
2513 & INSN_LOAD_MEMORY_DELAY)
2514 && ! gpr_interlocks))
2515 && insn_uses_reg (ip,
2516 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo & INSN_READ_COND_CODE)
2522 && (prev_pinfo & INSN_WRITE_COND_CODE))
2523 || ((pinfo & INSN_WRITE_COND_CODE)
2524 && (prev_pinfo & INSN_READ_COND_CODE))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts.mips16
2528 && (prev_pinfo & MIPS16_INSN_READ_PC))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts.mips16 && prev_insn_extended)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts.mips16 && prev_insn_fixp[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo & INSN_SYNC))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 if (mips_relax.sequence)
2546 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2547 /* Update the previous insn information. */
2548 prev_prev_insn = *ip;
2549 prev_insn.insn_mo = &dummy_opcode;
2553 /* It looks like we can actually do the swap. */
2554 if (! mips_opts.mips16)
2559 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2560 if (!relaxed_branch)
2562 /* If this is not a relaxed branch, then just
2563 swap the instructions. */
2564 memcpy (temp, prev_f, 4);
2565 memcpy (prev_f, f, 4);
2566 memcpy (f, temp, 4);
2570 /* If this is a relaxed branch, then we move the
2571 instruction to be placed in the delay slot to
2572 the current frag, shrinking the fixed part of
2573 the originating frag. If the branch occupies
2574 the tail of the latter, we move it backwards,
2575 into the space freed by the moved instruction. */
2577 memcpy (f, prev_f, 4);
2578 prev_insn_frag->fr_fix -= 4;
2579 if (prev_insn_frag->fr_type == rs_machine_dependent)
2580 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2583 if (prev_insn_fixp[0])
2585 prev_insn_fixp[0]->fx_frag = frag_now;
2586 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2588 if (prev_insn_fixp[1])
2590 prev_insn_fixp[1]->fx_frag = frag_now;
2591 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2593 if (prev_insn_fixp[2])
2595 prev_insn_fixp[2]->fx_frag = frag_now;
2596 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2598 if (prev_insn_fixp[0] && HAVE_NEWABI
2599 && prev_insn_frag != frag_now
2600 && (prev_insn_fixp[0]->fx_r_type
2601 == BFD_RELOC_MIPS_GOT_DISP
2602 || (prev_insn_fixp[0]->fx_r_type
2603 == BFD_RELOC_MIPS_CALL16)))
2605 /* To avoid confusion in tc_gen_reloc, we must
2606 ensure that this does not become a variant
2608 force_new_frag = TRUE;
2611 if (!relaxed_branch)
2615 fixp[0]->fx_frag = prev_insn_frag;
2616 fixp[0]->fx_where = prev_insn_where;
2620 fixp[1]->fx_frag = prev_insn_frag;
2621 fixp[1]->fx_where = prev_insn_where;
2625 fixp[2]->fx_frag = prev_insn_frag;
2626 fixp[2]->fx_where = prev_insn_where;
2629 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2632 fixp[0]->fx_where -= 4;
2634 fixp[1]->fx_where -= 4;
2636 fixp[2]->fx_where -= 4;
2644 assert (prev_insn_fixp[0] == NULL);
2645 assert (prev_insn_fixp[1] == NULL);
2646 assert (prev_insn_fixp[2] == NULL);
2647 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2648 memcpy (temp, prev_f, 2);
2649 memcpy (prev_f, f, 2);
2650 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2652 assert (*reloc_type == BFD_RELOC_UNUSED);
2653 memcpy (f, temp, 2);
2657 memcpy (f, f + 2, 2);
2658 memcpy (f + 2, temp, 2);
2662 fixp[0]->fx_frag = prev_insn_frag;
2663 fixp[0]->fx_where = prev_insn_where;
2667 fixp[1]->fx_frag = prev_insn_frag;
2668 fixp[1]->fx_where = prev_insn_where;
2672 fixp[2]->fx_frag = prev_insn_frag;
2673 fixp[2]->fx_where = prev_insn_where;
2677 /* Update the previous insn information; leave prev_insn
2679 prev_prev_insn = *ip;
2681 prev_insn_is_delay_slot = 1;
2683 /* If that was an unconditional branch, forget the previous
2684 insn information. */
2685 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2687 prev_prev_insn.insn_mo = &dummy_opcode;
2688 prev_insn.insn_mo = &dummy_opcode;
2691 prev_insn_fixp[0] = NULL;
2692 prev_insn_fixp[1] = NULL;
2693 prev_insn_fixp[2] = NULL;
2694 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2695 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2696 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2697 prev_insn_extended = 0;
2699 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2701 /* We don't yet optimize a branch likely. What we should do
2702 is look at the target, copy the instruction found there
2703 into the delay slot, and increment the branch to jump to
2704 the next instruction. */
2706 /* Update the previous insn information. */
2707 prev_prev_insn = *ip;
2708 prev_insn.insn_mo = &dummy_opcode;
2709 prev_insn_fixp[0] = NULL;
2710 prev_insn_fixp[1] = NULL;
2711 prev_insn_fixp[2] = NULL;
2712 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2713 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2714 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2715 prev_insn_extended = 0;
2716 prev_insn_is_delay_slot = 1;
2720 /* Update the previous insn information. */
2722 prev_prev_insn.insn_mo = &dummy_opcode;
2724 prev_prev_insn = prev_insn;
2727 /* Any time we see a branch, we always fill the delay slot
2728 immediately; since this insn is not a branch, we know it
2729 is not in a delay slot. */
2730 prev_insn_is_delay_slot = 0;
2732 prev_insn_fixp[0] = fixp[0];
2733 prev_insn_fixp[1] = fixp[1];
2734 prev_insn_fixp[2] = fixp[2];
2735 prev_insn_reloc_type[0] = reloc_type[0];
2736 prev_insn_reloc_type[1] = reloc_type[1];
2737 prev_insn_reloc_type[2] = reloc_type[2];
2738 if (mips_opts.mips16)
2739 prev_insn_extended = (ip->use_extend
2740 || *reloc_type > BFD_RELOC_UNUSED);
2743 prev_prev_insn_unreordered = prev_insn_unreordered;
2744 prev_insn_unreordered = 0;
2745 prev_insn_frag = frag_now;
2746 prev_insn_where = f - frag_now->fr_literal;
2747 prev_insn_valid = 1;
2749 else if (mips_relax.sequence != 2)
2751 /* We need to record a bit of information even when we are not
2752 reordering, in order to determine the base address for mips16
2753 PC relative relocs. */
2754 prev_prev_insn = prev_insn;
2756 prev_insn_reloc_type[0] = reloc_type[0];
2757 prev_insn_reloc_type[1] = reloc_type[1];
2758 prev_insn_reloc_type[2] = reloc_type[2];
2759 prev_prev_insn_unreordered = prev_insn_unreordered;
2760 prev_insn_unreordered = 1;
2763 /* We just output an insn, so the next one doesn't have a label. */
2764 mips_clear_insn_labels ();
2767 /* This function forgets that there was any previous instruction or
2768 label. If PRESERVE is non-zero, it remembers enough information to
2769 know whether nops are needed before a noreorder section. */
2772 mips_no_prev_insn (int preserve)
2776 prev_insn.insn_mo = &dummy_opcode;
2777 prev_prev_insn.insn_mo = &dummy_opcode;
2778 prev_nop_frag = NULL;
2779 prev_nop_frag_holds = 0;
2780 prev_nop_frag_required = 0;
2781 prev_nop_frag_since = 0;
2783 prev_insn_valid = 0;
2784 prev_insn_is_delay_slot = 0;
2785 prev_insn_unreordered = 0;
2786 prev_insn_extended = 0;
2787 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2788 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2789 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2790 prev_prev_insn_unreordered = 0;
2791 mips_clear_insn_labels ();
2794 /* This function must be called whenever we turn on noreorder or emit
2795 something other than instructions. It inserts any NOPS which might
2796 be needed by the previous instruction, and clears the information
2797 kept for the previous instructions. The INSNS parameter is true if
2798 instructions are to follow. */
2801 mips_emit_delays (bfd_boolean insns)
2803 if (! mips_opts.noreorder)
2808 if ((! mips_opts.mips16
2809 && ((prev_insn.insn_mo->pinfo
2810 & (INSN_LOAD_COPROC_DELAY
2811 | INSN_COPROC_MOVE_DELAY
2812 | INSN_WRITE_COND_CODE))
2813 && ! cop_interlocks))
2814 || (! hilo_interlocks
2815 && (prev_insn.insn_mo->pinfo
2818 || (! mips_opts.mips16
2819 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2820 && ! gpr_interlocks)
2821 || (! mips_opts.mips16
2822 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2823 && ! cop_mem_interlocks))
2825 /* Itbl support may require additional care here. */
2827 if ((! mips_opts.mips16
2828 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2829 && ! cop_interlocks))
2830 || (! hilo_interlocks
2831 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2832 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2835 if (prev_insn_unreordered)
2838 else if ((! mips_opts.mips16
2839 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2840 && ! cop_interlocks))
2841 || (! hilo_interlocks
2842 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2843 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2845 /* Itbl support may require additional care here. */
2846 if (! prev_prev_insn_unreordered)
2850 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2853 const char *pn = prev_insn.insn_mo->name;
2854 if (strncmp (pn, "macc", 4) == 0
2855 || strncmp (pn, "dmacc", 5) == 0
2856 || strncmp (pn, "dmult", 5) == 0
2857 || strstr (pn, "div"))
2859 if (nops < min_nops)
2865 struct insn_label_list *l;
2869 /* Record the frag which holds the nop instructions, so
2870 that we can remove them if we don't need them. */
2871 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2872 prev_nop_frag = frag_now;
2873 prev_nop_frag_holds = nops;
2874 prev_nop_frag_required = 0;
2875 prev_nop_frag_since = 0;
2878 for (; nops > 0; --nops)
2883 /* Move on to a new frag, so that it is safe to simply
2884 decrease the size of prev_nop_frag. */
2885 frag_wane (frag_now);
2889 for (l = insn_labels; l != NULL; l = l->next)
2893 assert (S_GET_SEGMENT (l->label) == now_seg);
2894 symbol_set_frag (l->label, frag_now);
2895 val = (valueT) frag_now_fix ();
2896 /* mips16 text labels are stored as odd. */
2897 if (mips_opts.mips16)
2899 S_SET_VALUE (l->label, val);
2904 /* Mark instruction labels in mips16 mode. */
2906 mips16_mark_labels ();
2908 mips_no_prev_insn (insns);
2911 /* Set up global variables for the start of a new macro. */
2916 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2917 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2918 && (prev_insn.insn_mo->pinfo
2919 & (INSN_UNCOND_BRANCH_DELAY
2920 | INSN_COND_BRANCH_DELAY
2921 | INSN_COND_BRANCH_LIKELY)) != 0);
2924 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2925 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2926 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2929 macro_warning (relax_substateT subtype)
2931 if (subtype & RELAX_DELAY_SLOT)
2932 return _("Macro instruction expanded into multiple instructions"
2933 " in a branch delay slot");
2934 else if (subtype & RELAX_NOMACRO)
2935 return _("Macro instruction expanded into multiple instructions");
2940 /* Finish up a macro. Emit warnings as appropriate. */
2945 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2947 relax_substateT subtype;
2949 /* Set up the relaxation warning flags. */
2951 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2952 subtype |= RELAX_SECOND_LONGER;
2953 if (mips_opts.warn_about_macros)
2954 subtype |= RELAX_NOMACRO;
2955 if (mips_macro_warning.delay_slot_p)
2956 subtype |= RELAX_DELAY_SLOT;
2958 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2960 /* Either the macro has a single implementation or both
2961 implementations are longer than 4 bytes. Emit the
2963 const char *msg = macro_warning (subtype);
2969 /* One implementation might need a warning but the other
2970 definitely doesn't. */
2971 mips_macro_warning.first_frag->fr_subtype |= subtype;
2976 /* Read a macro's relocation codes from *ARGS and store them in *R.
2977 The first argument in *ARGS will be either the code for a single
2978 relocation or -1 followed by the three codes that make up a
2979 composite relocation. */
2982 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
2986 next = va_arg (*args, int);
2988 r[0] = (bfd_reloc_code_real_type) next;
2990 for (i = 0; i < 3; i++)
2991 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
2994 /* Build an instruction created by a macro expansion. This is passed
2995 a pointer to the count of instructions created so far, an
2996 expression, the name of the instruction to build, an operand format
2997 string, and corresponding arguments. */
3000 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3002 struct mips_cl_insn insn;
3003 bfd_reloc_code_real_type r[3];
3006 va_start (args, fmt);
3008 if (mips_opts.mips16)
3010 mips16_macro_build (ep, name, fmt, args);
3015 r[0] = BFD_RELOC_UNUSED;
3016 r[1] = BFD_RELOC_UNUSED;
3017 r[2] = BFD_RELOC_UNUSED;
3018 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3019 assert (insn.insn_mo);
3020 assert (strcmp (name, insn.insn_mo->name) == 0);
3022 /* Search until we get a match for NAME. */
3025 /* It is assumed here that macros will never generate
3026 MDMX or MIPS-3D instructions. */
3027 if (strcmp (fmt, insn.insn_mo->args) == 0
3028 && insn.insn_mo->pinfo != INSN_MACRO
3029 && OPCODE_IS_MEMBER (insn.insn_mo,
3031 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3033 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3037 assert (insn.insn_mo->name);
3038 assert (strcmp (name, insn.insn_mo->name) == 0);
3041 insn.insn_opcode = insn.insn_mo->match;
3059 insn.insn_opcode |= (va_arg (args, int)
3060 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3065 /* Note that in the macro case, these arguments are already
3066 in MSB form. (When handling the instruction in the
3067 non-macro case, these arguments are sizes from which
3068 MSB values must be calculated.) */
3069 insn.insn_opcode |= (va_arg (args, int)
3070 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3076 /* Note that in the macro case, these arguments are already
3077 in MSBD form. (When handling the instruction in the
3078 non-macro case, these arguments are sizes from which
3079 MSBD values must be calculated.) */
3080 insn.insn_opcode |= (va_arg (args, int)
3081 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3092 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3096 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3101 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3107 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3112 int tmp = va_arg (args, int);
3114 insn.insn_opcode |= tmp << OP_SH_RT;
3115 insn.insn_opcode |= tmp << OP_SH_RD;
3121 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3128 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3132 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3136 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3140 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3144 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3151 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3157 macro_read_relocs (&args, r);
3158 assert (*r == BFD_RELOC_GPREL16
3159 || *r == BFD_RELOC_MIPS_LITERAL
3160 || *r == BFD_RELOC_MIPS_HIGHER
3161 || *r == BFD_RELOC_HI16_S
3162 || *r == BFD_RELOC_LO16
3163 || *r == BFD_RELOC_MIPS_GOT16
3164 || *r == BFD_RELOC_MIPS_CALL16
3165 || *r == BFD_RELOC_MIPS_GOT_DISP
3166 || *r == BFD_RELOC_MIPS_GOT_PAGE
3167 || *r == BFD_RELOC_MIPS_GOT_OFST
3168 || *r == BFD_RELOC_MIPS_GOT_LO16
3169 || *r == BFD_RELOC_MIPS_CALL_LO16);
3173 macro_read_relocs (&args, r);
3175 && (ep->X_op == O_constant
3176 || (ep->X_op == O_symbol
3177 && (*r == BFD_RELOC_MIPS_HIGHEST
3178 || *r == BFD_RELOC_HI16_S
3179 || *r == BFD_RELOC_HI16
3180 || *r == BFD_RELOC_GPREL16
3181 || *r == BFD_RELOC_MIPS_GOT_HI16
3182 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3186 assert (ep != NULL);
3188 * This allows macro() to pass an immediate expression for
3189 * creating short branches without creating a symbol.
3190 * Note that the expression still might come from the assembly
3191 * input, in which case the value is not checked for range nor
3192 * is a relocation entry generated (yuck).
3194 if (ep->X_op == O_constant)
3196 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3200 *r = BFD_RELOC_16_PCREL_S2;
3204 assert (ep != NULL);
3205 *r = BFD_RELOC_MIPS_JMP;
3209 insn.insn_opcode |= va_arg (args, unsigned long);
3218 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3220 append_insn (&insn, ep, r);
3224 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3227 struct mips_cl_insn insn;
3228 bfd_reloc_code_real_type r[3]
3229 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3231 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3232 assert (insn.insn_mo);
3233 assert (strcmp (name, insn.insn_mo->name) == 0);
3235 while (strcmp (fmt, insn.insn_mo->args) != 0
3236 || insn.insn_mo->pinfo == INSN_MACRO)
3239 assert (insn.insn_mo->name);
3240 assert (strcmp (name, insn.insn_mo->name) == 0);
3243 insn.insn_opcode = insn.insn_mo->match;
3244 insn.use_extend = FALSE;
3263 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3268 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3272 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3276 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3286 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3293 regno = va_arg (args, int);
3294 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3295 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3316 assert (ep != NULL);
3318 if (ep->X_op != O_constant)
3319 *r = (int) BFD_RELOC_UNUSED + c;
3322 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3323 FALSE, &insn.insn_opcode, &insn.use_extend,
3326 *r = BFD_RELOC_UNUSED;
3332 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3339 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3341 append_insn (&insn, ep, r);
3345 * Generate a "jalr" instruction with a relocation hint to the called
3346 * function. This occurs in NewABI PIC code.
3349 macro_build_jalr (expressionS *ep)
3358 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3360 fix_new_exp (frag_now, f - frag_now->fr_literal,
3361 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3365 * Generate a "lui" instruction.
3368 macro_build_lui (expressionS *ep, int regnum)
3370 expressionS high_expr;
3371 struct mips_cl_insn insn;
3372 bfd_reloc_code_real_type r[3]
3373 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3374 const char *name = "lui";
3375 const char *fmt = "t,u";
3377 assert (! mips_opts.mips16);
3381 if (high_expr.X_op == O_constant)
3383 /* we can compute the instruction now without a relocation entry */
3384 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3386 *r = BFD_RELOC_UNUSED;
3390 assert (ep->X_op == O_symbol);
3391 /* _gp_disp is a special case, used from s_cpload. */
3392 assert (mips_pic == NO_PIC
3394 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3395 *r = BFD_RELOC_HI16_S;
3398 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3399 assert (insn.insn_mo);
3400 assert (strcmp (name, insn.insn_mo->name) == 0);
3401 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3403 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3404 if (*r == BFD_RELOC_UNUSED)
3406 insn.insn_opcode |= high_expr.X_add_number;
3407 append_insn (&insn, NULL, r);
3410 append_insn (&insn, &high_expr, r);
3413 /* Generate a sequence of instructions to do a load or store from a constant
3414 offset off of a base register (breg) into/from a target register (treg),
3415 using AT if necessary. */
3417 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3418 int treg, int breg, int dbl)
3420 assert (ep->X_op == O_constant);
3422 /* Sign-extending 32-bit constants makes their handling easier. */
3423 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3424 == ~((bfd_vma) 0x7fffffff)))
3426 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3427 as_bad (_("constant too large"));
3429 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3433 /* Right now, this routine can only handle signed 32-bit constants. */
3434 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3435 as_warn (_("operand overflow"));
3437 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3439 /* Signed 16-bit offset will fit in the op. Easy! */
3440 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3444 /* 32-bit offset, need multiple instructions and AT, like:
3445 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3446 addu $tempreg,$tempreg,$breg
3447 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3448 to handle the complete offset. */
3449 macro_build_lui (ep, AT);
3450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3451 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3454 as_warn (_("Macro used $at after \".set noat\""));
3459 * Generates code to set the $at register to true (one)
3460 * if reg is less than the immediate expression.
3463 set_at (int reg, int unsignedp)
3465 if (imm_expr.X_op == O_constant
3466 && imm_expr.X_add_number >= -0x8000
3467 && imm_expr.X_add_number < 0x8000)
3468 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3469 AT, reg, BFD_RELOC_LO16);
3472 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3473 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3478 normalize_constant_expr (expressionS *ex)
3480 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3481 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3485 /* Warn if an expression is not a constant. */
3488 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3490 if (ex->X_op == O_big)
3491 as_bad (_("unsupported large constant"));
3492 else if (ex->X_op != O_constant)
3493 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3495 normalize_constant_expr (ex);
3498 /* Count the leading zeroes by performing a binary chop. This is a
3499 bulky bit of source, but performance is a LOT better for the
3500 majority of values than a simple loop to count the bits:
3501 for (lcnt = 0; (lcnt < 32); lcnt++)
3502 if ((v) & (1 << (31 - lcnt)))
3504 However it is not code size friendly, and the gain will drop a bit
3505 on certain cached systems.
3507 #define COUNT_TOP_ZEROES(v) \
3508 (((v) & ~0xffff) == 0 \
3509 ? ((v) & ~0xff) == 0 \
3510 ? ((v) & ~0xf) == 0 \
3511 ? ((v) & ~0x3) == 0 \
3512 ? ((v) & ~0x1) == 0 \
3517 : ((v) & ~0x7) == 0 \
3520 : ((v) & ~0x3f) == 0 \
3521 ? ((v) & ~0x1f) == 0 \
3524 : ((v) & ~0x7f) == 0 \
3527 : ((v) & ~0xfff) == 0 \
3528 ? ((v) & ~0x3ff) == 0 \
3529 ? ((v) & ~0x1ff) == 0 \
3532 : ((v) & ~0x7ff) == 0 \
3535 : ((v) & ~0x3fff) == 0 \
3536 ? ((v) & ~0x1fff) == 0 \
3539 : ((v) & ~0x7fff) == 0 \
3542 : ((v) & ~0xffffff) == 0 \
3543 ? ((v) & ~0xfffff) == 0 \
3544 ? ((v) & ~0x3ffff) == 0 \
3545 ? ((v) & ~0x1ffff) == 0 \
3548 : ((v) & ~0x7ffff) == 0 \
3551 : ((v) & ~0x3fffff) == 0 \
3552 ? ((v) & ~0x1fffff) == 0 \
3555 : ((v) & ~0x7fffff) == 0 \
3558 : ((v) & ~0xfffffff) == 0 \
3559 ? ((v) & ~0x3ffffff) == 0 \
3560 ? ((v) & ~0x1ffffff) == 0 \
3563 : ((v) & ~0x7ffffff) == 0 \
3566 : ((v) & ~0x3fffffff) == 0 \
3567 ? ((v) & ~0x1fffffff) == 0 \
3570 : ((v) & ~0x7fffffff) == 0 \
3575 * This routine generates the least number of instructions necessary to load
3576 * an absolute expression value into a register.
3579 load_register (int reg, expressionS *ep, int dbl)
3582 expressionS hi32, lo32;
3584 if (ep->X_op != O_big)
3586 assert (ep->X_op == O_constant);
3588 /* Sign-extending 32-bit constants makes their handling easier. */
3589 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3590 == ~((bfd_vma) 0x7fffffff)))
3592 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3593 as_bad (_("constant too large"));
3595 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3599 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3601 /* We can handle 16 bit signed values with an addiu to
3602 $zero. No need to ever use daddiu here, since $zero and
3603 the result are always correct in 32 bit mode. */
3604 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3607 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3609 /* We can handle 16 bit unsigned values with an ori to
3611 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3614 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3616 /* 32 bit values require an lui. */
3617 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3618 if ((ep->X_add_number & 0xffff) != 0)
3619 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3624 /* The value is larger than 32 bits. */
3626 if (HAVE_32BIT_GPRS)
3628 as_bad (_("Number (0x%lx) larger than 32 bits"),
3629 (unsigned long) ep->X_add_number);
3630 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3634 if (ep->X_op != O_big)
3637 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3638 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3639 hi32.X_add_number &= 0xffffffff;
3641 lo32.X_add_number &= 0xffffffff;
3645 assert (ep->X_add_number > 2);
3646 if (ep->X_add_number == 3)
3647 generic_bignum[3] = 0;
3648 else if (ep->X_add_number > 4)
3649 as_bad (_("Number larger than 64 bits"));
3650 lo32.X_op = O_constant;
3651 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3652 hi32.X_op = O_constant;
3653 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3656 if (hi32.X_add_number == 0)
3661 unsigned long hi, lo;
3663 if (hi32.X_add_number == (offsetT) 0xffffffff)
3665 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3667 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3670 if (lo32.X_add_number & 0x80000000)
3672 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3673 if (lo32.X_add_number & 0xffff)
3674 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3679 /* Check for 16bit shifted constant. We know that hi32 is
3680 non-zero, so start the mask on the first bit of the hi32
3685 unsigned long himask, lomask;
3689 himask = 0xffff >> (32 - shift);
3690 lomask = (0xffff << shift) & 0xffffffff;
3694 himask = 0xffff << (shift - 32);
3697 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3698 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3702 tmp.X_op = O_constant;
3704 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3705 | (lo32.X_add_number >> shift));
3707 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3708 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3709 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3710 reg, reg, (shift >= 32) ? shift - 32 : shift);
3715 while (shift <= (64 - 16));
3717 /* Find the bit number of the lowest one bit, and store the
3718 shifted value in hi/lo. */
3719 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3720 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3724 while ((lo & 1) == 0)
3729 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3735 while ((hi & 1) == 0)
3744 /* Optimize if the shifted value is a (power of 2) - 1. */
3745 if ((hi == 0 && ((lo + 1) & lo) == 0)
3746 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3748 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3753 /* This instruction will set the register to be all
3755 tmp.X_op = O_constant;
3756 tmp.X_add_number = (offsetT) -1;
3757 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3761 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3762 reg, reg, (bit >= 32) ? bit - 32 : bit);
3764 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3765 reg, reg, (shift >= 32) ? shift - 32 : shift);
3770 /* Sign extend hi32 before calling load_register, because we can
3771 generally get better code when we load a sign extended value. */
3772 if ((hi32.X_add_number & 0x80000000) != 0)
3773 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3774 load_register (reg, &hi32, 0);
3777 if ((lo32.X_add_number & 0xffff0000) == 0)
3781 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3789 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3791 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3792 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3798 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3802 mid16.X_add_number >>= 16;
3803 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3804 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3807 if ((lo32.X_add_number & 0xffff) != 0)
3808 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3812 load_delay_nop (void)
3814 if (!gpr_interlocks)
3815 macro_build (NULL, "nop", "");
3818 /* Load an address into a register. */
3821 load_address (int reg, expressionS *ep, int *used_at)
3823 if (ep->X_op != O_constant
3824 && ep->X_op != O_symbol)
3826 as_bad (_("expression too complex"));
3827 ep->X_op = O_constant;
3830 if (ep->X_op == O_constant)
3832 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3836 if (mips_pic == NO_PIC)
3838 /* If this is a reference to a GP relative symbol, we want
3839 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3841 lui $reg,<sym> (BFD_RELOC_HI16_S)
3842 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3843 If we have an addend, we always use the latter form.
3845 With 64bit address space and a usable $at we want
3846 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3847 lui $at,<sym> (BFD_RELOC_HI16_S)
3848 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3849 daddiu $at,<sym> (BFD_RELOC_LO16)
3853 If $at is already in use, we use a path which is suboptimal
3854 on superscalar processors.
3855 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3856 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3858 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3860 daddiu $reg,<sym> (BFD_RELOC_LO16)
3862 if (HAVE_64BIT_ADDRESSES)
3864 /* ??? We don't provide a GP-relative alternative for these macros.
3865 It used not to be possible with the original relaxation code,
3866 but it could be done now. */
3868 if (*used_at == 0 && ! mips_opts.noat)
3870 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3871 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3872 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3873 BFD_RELOC_MIPS_HIGHER);
3874 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3875 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3876 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3881 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3882 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3883 BFD_RELOC_MIPS_HIGHER);
3884 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3885 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3886 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3887 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3892 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3893 && ! nopic_need_relax (ep->X_add_symbol, 1))
3895 relax_start (ep->X_add_symbol);
3896 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3897 mips_gp_register, BFD_RELOC_GPREL16);
3900 macro_build_lui (ep, reg);
3901 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3902 reg, reg, BFD_RELOC_LO16);
3903 if (mips_relax.sequence)
3907 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3911 /* If this is a reference to an external symbol, we want
3912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3914 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3916 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3917 If there is a constant, it must be added in after.
3919 If we have NewABI, we want
3920 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3921 unless we're referencing a global symbol with a non-zero
3922 offset, in which case cst must be added separately. */
3925 if (ep->X_add_number)
3927 ex.X_add_number = ep->X_add_number;
3928 ep->X_add_number = 0;
3929 relax_start (ep->X_add_symbol);
3930 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3931 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3932 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3933 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3934 ex.X_op = O_constant;
3935 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3936 reg, reg, BFD_RELOC_LO16);
3937 ep->X_add_number = ex.X_add_number;
3940 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3941 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3942 if (mips_relax.sequence)
3947 ex.X_add_number = ep->X_add_number;
3948 ep->X_add_number = 0;
3949 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3950 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3952 relax_start (ep->X_add_symbol);
3954 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3958 if (ex.X_add_number != 0)
3960 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3961 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3962 ex.X_op = O_constant;
3963 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3964 reg, reg, BFD_RELOC_LO16);
3968 else if (mips_pic == SVR4_PIC)
3972 /* This is the large GOT case. If this is a reference to an
3973 external symbol, we want
3974 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3976 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3978 Otherwise, for a reference to a local symbol in old ABI, we want
3979 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3981 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3982 If there is a constant, it must be added in after.
3984 In the NewABI, for local symbols, with or without offsets, we want:
3985 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3986 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3990 ex.X_add_number = ep->X_add_number;
3991 ep->X_add_number = 0;
3992 relax_start (ep->X_add_symbol);
3993 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3994 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3995 reg, reg, mips_gp_register);
3996 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3997 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3998 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3999 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4000 else if (ex.X_add_number)
4002 ex.X_op = O_constant;
4003 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4007 ep->X_add_number = ex.X_add_number;
4009 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4010 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4011 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4012 BFD_RELOC_MIPS_GOT_OFST);
4017 ex.X_add_number = ep->X_add_number;
4018 ep->X_add_number = 0;
4019 relax_start (ep->X_add_symbol);
4020 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4022 reg, reg, mips_gp_register);
4023 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4024 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4026 if (reg_needs_delay (mips_gp_register))
4028 /* We need a nop before loading from $gp. This special
4029 check is required because the lui which starts the main
4030 instruction stream does not refer to $gp, and so will not
4031 insert the nop which may be required. */
4032 macro_build (NULL, "nop", "");
4034 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4035 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4037 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4041 if (ex.X_add_number != 0)
4043 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4044 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4045 ex.X_op = O_constant;
4046 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4055 /* Move the contents of register SOURCE into register DEST. */
4058 move_register (int dest, int source)
4060 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4064 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4065 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4066 The two alternatives are:
4068 Global symbol Local sybmol
4069 ------------- ------------
4070 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4072 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4074 load_got_offset emits the first instruction and add_got_offset
4075 emits the second for a 16-bit offset or add_got_offset_hilo emits
4076 a sequence to add a 32-bit offset using a scratch register. */
4079 load_got_offset (int dest, expressionS *local)
4084 global.X_add_number = 0;
4086 relax_start (local->X_add_symbol);
4087 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4088 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4090 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4091 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4096 add_got_offset (int dest, expressionS *local)
4100 global.X_op = O_constant;
4101 global.X_op_symbol = NULL;
4102 global.X_add_symbol = NULL;
4103 global.X_add_number = local->X_add_number;
4105 relax_start (local->X_add_symbol);
4106 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4107 dest, dest, BFD_RELOC_LO16);
4109 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4114 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4117 int hold_mips_optimize;
4119 global.X_op = O_constant;
4120 global.X_op_symbol = NULL;
4121 global.X_add_symbol = NULL;
4122 global.X_add_number = local->X_add_number;
4124 relax_start (local->X_add_symbol);
4125 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4127 /* Set mips_optimize around the lui instruction to avoid
4128 inserting an unnecessary nop after the lw. */
4129 hold_mips_optimize = mips_optimize;
4131 macro_build_lui (&global, tmp);
4132 mips_optimize = hold_mips_optimize;
4133 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4136 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4141 * This routine implements the seemingly endless macro or synthesized
4142 * instructions and addressing modes in the mips assembly language. Many
4143 * of these macros are simple and are similar to each other. These could
4144 * probably be handled by some kind of table or grammar approach instead of
4145 * this verbose method. Others are not simple macros but are more like
4146 * optimizing code generation.
4147 * One interesting optimization is when several store macros appear
4148 * consecutively that would load AT with the upper half of the same address.
4149 * The ensuing load upper instructions are ommited. This implies some kind
4150 * of global optimization. We currently only optimize within a single macro.
4151 * For many of the load and store macros if the address is specified as a
4152 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4153 * first load register 'at' with zero and use it as the base register. The
4154 * mips assembler simply uses register $zero. Just one tiny optimization
4158 macro (struct mips_cl_insn *ip)
4160 register int treg, sreg, dreg, breg;
4176 bfd_reloc_code_real_type r;
4177 int hold_mips_optimize;
4179 assert (! mips_opts.mips16);
4181 treg = (ip->insn_opcode >> 16) & 0x1f;
4182 dreg = (ip->insn_opcode >> 11) & 0x1f;
4183 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4184 mask = ip->insn_mo->mask;
4186 expr1.X_op = O_constant;
4187 expr1.X_op_symbol = NULL;
4188 expr1.X_add_symbol = NULL;
4189 expr1.X_add_number = 1;
4201 mips_emit_delays (TRUE);
4202 ++mips_opts.noreorder;
4203 mips_any_noreorder = 1;
4205 expr1.X_add_number = 8;
4206 macro_build (&expr1, "bgez", "s,p", sreg);
4208 macro_build (NULL, "nop", "", 0);
4210 move_register (dreg, sreg);
4211 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4213 --mips_opts.noreorder;
4234 if (imm_expr.X_op == O_constant
4235 && imm_expr.X_add_number >= -0x8000
4236 && imm_expr.X_add_number < 0x8000)
4238 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4241 load_register (AT, &imm_expr, dbl);
4242 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4261 if (imm_expr.X_op == O_constant
4262 && imm_expr.X_add_number >= 0
4263 && imm_expr.X_add_number < 0x10000)
4265 if (mask != M_NOR_I)
4266 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4269 macro_build (&imm_expr, "ori", "t,r,i",
4270 treg, sreg, BFD_RELOC_LO16);
4271 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4276 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4277 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4294 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4296 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4299 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4300 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4308 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4313 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4316 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4317 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4323 /* check for > max integer */
4324 maxnum = 0x7fffffff;
4325 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4332 if (imm_expr.X_op == O_constant
4333 && imm_expr.X_add_number >= maxnum
4334 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4337 /* result is always false */
4339 macro_build (NULL, "nop", "", 0);
4341 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4344 if (imm_expr.X_op != O_constant)
4345 as_bad (_("Unsupported large constant"));
4346 ++imm_expr.X_add_number;
4350 if (mask == M_BGEL_I)
4352 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4354 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4359 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4362 maxnum = 0x7fffffff;
4363 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4370 maxnum = - maxnum - 1;
4371 if (imm_expr.X_op == O_constant
4372 && imm_expr.X_add_number <= maxnum
4373 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4376 /* result is always true */
4377 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4378 macro_build (&offset_expr, "b", "p");
4382 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4392 macro_build (&offset_expr, likely ? "beql" : "beq",
4396 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4397 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4405 && imm_expr.X_op == O_constant
4406 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4408 if (imm_expr.X_op != O_constant)
4409 as_bad (_("Unsupported large constant"));
4410 ++imm_expr.X_add_number;
4414 if (mask == M_BGEUL_I)
4416 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4418 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4420 macro_build (&offset_expr, likely ? "bnel" : "bne",
4425 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4433 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4438 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4441 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4442 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4450 macro_build (&offset_expr, likely ? "bnel" : "bne",
4456 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4457 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4465 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4470 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4473 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4474 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4480 maxnum = 0x7fffffff;
4481 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4488 if (imm_expr.X_op == O_constant
4489 && imm_expr.X_add_number >= maxnum
4490 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4492 if (imm_expr.X_op != O_constant)
4493 as_bad (_("Unsupported large constant"));
4494 ++imm_expr.X_add_number;
4498 if (mask == M_BLTL_I)
4500 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4502 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4505 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4507 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4511 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4519 macro_build (&offset_expr, likely ? "beql" : "beq",
4525 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4526 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4534 && imm_expr.X_op == O_constant
4535 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4537 if (imm_expr.X_op != O_constant)
4538 as_bad (_("Unsupported large constant"));
4539 ++imm_expr.X_add_number;
4543 if (mask == M_BLTUL_I)
4545 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4547 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4549 macro_build (&offset_expr, likely ? "beql" : "beq",
4554 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4562 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4567 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4570 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4571 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4581 macro_build (&offset_expr, likely ? "bnel" : "bne",
4585 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4586 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4594 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4596 as_bad (_("Unsupported large constant"));
4601 pos = (unsigned long) imm_expr.X_add_number;
4602 size = (unsigned long) imm2_expr.X_add_number;
4607 as_bad (_("Improper position (%lu)"), pos);
4610 if (size == 0 || size > 64
4611 || (pos + size - 1) > 63)
4613 as_bad (_("Improper extract size (%lu, position %lu)"),
4618 if (size <= 32 && pos < 32)
4623 else if (size <= 32)
4633 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4642 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4644 as_bad (_("Unsupported large constant"));
4649 pos = (unsigned long) imm_expr.X_add_number;
4650 size = (unsigned long) imm2_expr.X_add_number;
4655 as_bad (_("Improper position (%lu)"), pos);
4658 if (size == 0 || size > 64
4659 || (pos + size - 1) > 63)
4661 as_bad (_("Improper insert size (%lu, position %lu)"),
4666 if (pos < 32 && (pos + size - 1) < 32)
4681 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4698 as_warn (_("Divide by zero."));
4700 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4702 macro_build (NULL, "break", "c", 7);
4706 mips_emit_delays (TRUE);
4707 ++mips_opts.noreorder;
4708 mips_any_noreorder = 1;
4711 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4712 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4716 expr1.X_add_number = 8;
4717 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4718 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4719 macro_build (NULL, "break", "c", 7);
4721 expr1.X_add_number = -1;
4722 load_register (AT, &expr1, dbl);
4723 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4724 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4727 expr1.X_add_number = 1;
4728 load_register (AT, &expr1, dbl);
4729 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4733 expr1.X_add_number = 0x80000000;
4734 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4738 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4739 /* We want to close the noreorder block as soon as possible, so
4740 that later insns are available for delay slot filling. */
4741 --mips_opts.noreorder;
4745 expr1.X_add_number = 8;
4746 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4747 macro_build (NULL, "nop", "", 0);
4749 /* We want to close the noreorder block as soon as possible, so
4750 that later insns are available for delay slot filling. */
4751 --mips_opts.noreorder;
4753 macro_build (NULL, "break", "c", 6);
4755 macro_build (NULL, s, "d", dreg);
4794 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4796 as_warn (_("Divide by zero."));
4798 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4800 macro_build (NULL, "break", "c", 7);
4803 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4805 if (strcmp (s2, "mflo") == 0)
4806 move_register (dreg, sreg);
4808 move_register (dreg, 0);
4811 if (imm_expr.X_op == O_constant
4812 && imm_expr.X_add_number == -1
4813 && s[strlen (s) - 1] != 'u')
4815 if (strcmp (s2, "mflo") == 0)
4817 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4820 move_register (dreg, 0);
4824 load_register (AT, &imm_expr, dbl);
4825 macro_build (NULL, s, "z,s,t", sreg, AT);
4826 macro_build (NULL, s2, "d", dreg);
4845 mips_emit_delays (TRUE);
4846 ++mips_opts.noreorder;
4847 mips_any_noreorder = 1;
4850 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4851 macro_build (NULL, s, "z,s,t", sreg, treg);
4852 /* We want to close the noreorder block as soon as possible, so
4853 that later insns are available for delay slot filling. */
4854 --mips_opts.noreorder;
4858 expr1.X_add_number = 8;
4859 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4860 macro_build (NULL, s, "z,s,t", sreg, treg);
4862 /* We want to close the noreorder block as soon as possible, so
4863 that later insns are available for delay slot filling. */
4864 --mips_opts.noreorder;
4865 macro_build (NULL, "break", "c", 7);
4867 macro_build (NULL, s2, "d", dreg);
4879 /* Load the address of a symbol into a register. If breg is not
4880 zero, we then add a base register to it. */
4882 if (dbl && HAVE_32BIT_GPRS)
4883 as_warn (_("dla used to load 32-bit register"));
4885 if (! dbl && HAVE_64BIT_OBJECTS)
4886 as_warn (_("la used to load 64-bit address"));
4888 if (offset_expr.X_op == O_constant
4889 && offset_expr.X_add_number >= -0x8000
4890 && offset_expr.X_add_number < 0x8000)
4892 macro_build (&offset_expr,
4893 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4894 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4909 if (offset_expr.X_op != O_symbol
4910 && offset_expr.X_op != O_constant)
4912 as_bad (_("expression too complex"));
4913 offset_expr.X_op = O_constant;
4916 if (offset_expr.X_op == O_constant)
4917 load_register (tempreg, &offset_expr,
4919 ? (dbl || HAVE_64BIT_ADDRESSES)
4920 : HAVE_64BIT_ADDRESSES));
4921 else if (mips_pic == NO_PIC)
4923 /* If this is a reference to a GP relative symbol, we want
4924 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4926 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4927 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4928 If we have a constant, we need two instructions anyhow,
4929 so we may as well always use the latter form.
4931 With 64bit address space and a usable $at we want
4932 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4933 lui $at,<sym> (BFD_RELOC_HI16_S)
4934 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4935 daddiu $at,<sym> (BFD_RELOC_LO16)
4937 daddu $tempreg,$tempreg,$at
4939 If $at is already in use, we use a path which is suboptimal
4940 on superscalar processors.
4941 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4942 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4944 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4946 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4948 if (HAVE_64BIT_ADDRESSES)
4950 /* ??? We don't provide a GP-relative alternative for
4951 these macros. It used not to be possible with the
4952 original relaxation code, but it could be done now. */
4954 if (used_at == 0 && ! mips_opts.noat)
4956 macro_build (&offset_expr, "lui", "t,u",
4957 tempreg, BFD_RELOC_MIPS_HIGHEST);
4958 macro_build (&offset_expr, "lui", "t,u",
4959 AT, BFD_RELOC_HI16_S);
4960 macro_build (&offset_expr, "daddiu", "t,r,j",
4961 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4962 macro_build (&offset_expr, "daddiu", "t,r,j",
4963 AT, AT, BFD_RELOC_LO16);
4964 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4965 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4970 macro_build (&offset_expr, "lui", "t,u",
4971 tempreg, BFD_RELOC_MIPS_HIGHEST);
4972 macro_build (&offset_expr, "daddiu", "t,r,j",
4973 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4974 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4975 macro_build (&offset_expr, "daddiu", "t,r,j",
4976 tempreg, tempreg, BFD_RELOC_HI16_S);
4977 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4978 macro_build (&offset_expr, "daddiu", "t,r,j",
4979 tempreg, tempreg, BFD_RELOC_LO16);
4984 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4985 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4987 relax_start (offset_expr.X_add_symbol);
4988 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4989 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4992 macro_build_lui (&offset_expr, tempreg);
4993 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4994 tempreg, tempreg, BFD_RELOC_LO16);
4995 if (mips_relax.sequence)
4999 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5001 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5003 /* If this is a reference to an external symbol, and there
5004 is no constant, we want
5005 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5006 or for lca or if tempreg is PIC_CALL_REG
5007 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5008 For a local symbol, we want
5009 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5011 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5013 If we have a small constant, and this is a reference to
5014 an external symbol, we want
5015 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5017 addiu $tempreg,$tempreg,<constant>
5018 For a local symbol, we want the same instruction
5019 sequence, but we output a BFD_RELOC_LO16 reloc on the
5022 If we have a large constant, and this is a reference to
5023 an external symbol, we want
5024 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5025 lui $at,<hiconstant>
5026 addiu $at,$at,<loconstant>
5027 addu $tempreg,$tempreg,$at
5028 For a local symbol, we want the same instruction
5029 sequence, but we output a BFD_RELOC_LO16 reloc on the
5033 if (offset_expr.X_add_number == 0)
5035 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5036 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5038 relax_start (offset_expr.X_add_symbol);
5039 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5040 lw_reloc_type, mips_gp_register);
5043 /* We're going to put in an addu instruction using
5044 tempreg, so we may as well insert the nop right
5049 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5050 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5052 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5053 tempreg, tempreg, BFD_RELOC_LO16);
5055 /* FIXME: If breg == 0, and the next instruction uses
5056 $tempreg, then if this variant case is used an extra
5057 nop will be generated. */
5059 else if (offset_expr.X_add_number >= -0x8000
5060 && offset_expr.X_add_number < 0x8000)
5062 load_got_offset (tempreg, &offset_expr);
5064 add_got_offset (tempreg, &offset_expr);
5068 expr1.X_add_number = offset_expr.X_add_number;
5069 offset_expr.X_add_number =
5070 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5071 load_got_offset (tempreg, &offset_expr);
5072 offset_expr.X_add_number = expr1.X_add_number;
5073 /* If we are going to add in a base register, and the
5074 target register and the base register are the same,
5075 then we are using AT as a temporary register. Since
5076 we want to load the constant into AT, we add our
5077 current AT (from the global offset table) and the
5078 register into the register now, and pretend we were
5079 not using a base register. */
5083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5088 add_got_offset_hilo (tempreg, &offset_expr, AT);
5092 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5094 int add_breg_early = 0;
5096 /* If this is a reference to an external, and there is no
5097 constant, or local symbol (*), with or without a
5099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5100 or for lca or if tempreg is PIC_CALL_REG
5101 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5103 If we have a small constant, and this is a reference to
5104 an external symbol, we want
5105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5106 addiu $tempreg,$tempreg,<constant>
5108 If we have a large constant, and this is a reference to
5109 an external symbol, we want
5110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5111 lui $at,<hiconstant>
5112 addiu $at,$at,<loconstant>
5113 addu $tempreg,$tempreg,$at
5115 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5116 local symbols, even though it introduces an additional
5119 if (offset_expr.X_add_number)
5121 expr1.X_add_number = offset_expr.X_add_number;
5122 offset_expr.X_add_number = 0;
5124 relax_start (offset_expr.X_add_symbol);
5125 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5126 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5128 if (expr1.X_add_number >= -0x8000
5129 && expr1.X_add_number < 0x8000)
5131 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5132 tempreg, tempreg, BFD_RELOC_LO16);
5134 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5138 /* If we are going to add in a base register, and the
5139 target register and the base register are the same,
5140 then we are using AT as a temporary register. Since
5141 we want to load the constant into AT, we add our
5142 current AT (from the global offset table) and the
5143 register into the register now, and pretend we were
5144 not using a base register. */
5149 assert (tempreg == AT);
5150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5156 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5163 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5166 offset_expr.X_add_number = expr1.X_add_number;
5168 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5169 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5172 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5173 treg, tempreg, breg);
5179 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5181 relax_start (offset_expr.X_add_symbol);
5182 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5183 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5185 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5186 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5191 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5192 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5195 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5198 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5199 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5200 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5202 /* This is the large GOT case. If this is a reference to an
5203 external symbol, and there is no constant, we want
5204 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5205 addu $tempreg,$tempreg,$gp
5206 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5207 or for lca or if tempreg is PIC_CALL_REG
5208 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5209 addu $tempreg,$tempreg,$gp
5210 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5211 For a local symbol, we want
5212 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5214 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5216 If we have a small constant, and this is a reference to
5217 an external symbol, we want
5218 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5219 addu $tempreg,$tempreg,$gp
5220 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5222 addiu $tempreg,$tempreg,<constant>
5223 For a local symbol, we want
5224 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5226 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5228 If we have a large constant, and this is a reference to
5229 an external symbol, we want
5230 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5231 addu $tempreg,$tempreg,$gp
5232 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5233 lui $at,<hiconstant>
5234 addiu $at,$at,<loconstant>
5235 addu $tempreg,$tempreg,$at
5236 For a local symbol, we want
5237 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5238 lui $at,<hiconstant>
5239 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5240 addu $tempreg,$tempreg,$at
5243 expr1.X_add_number = offset_expr.X_add_number;
5244 offset_expr.X_add_number = 0;
5245 relax_start (offset_expr.X_add_symbol);
5246 gpdelay = reg_needs_delay (mips_gp_register);
5247 if (expr1.X_add_number == 0 && breg == 0
5248 && (call || tempreg == PIC_CALL_REG))
5250 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5251 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5253 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5254 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5255 tempreg, tempreg, mips_gp_register);
5256 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5257 tempreg, lw_reloc_type, tempreg);
5258 if (expr1.X_add_number == 0)
5262 /* We're going to put in an addu instruction using
5263 tempreg, so we may as well insert the nop right
5268 else if (expr1.X_add_number >= -0x8000
5269 && expr1.X_add_number < 0x8000)
5272 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5273 tempreg, tempreg, BFD_RELOC_LO16);
5279 /* If we are going to add in a base register, and the
5280 target register and the base register are the same,
5281 then we are using AT as a temporary register. Since
5282 we want to load the constant into AT, we add our
5283 current AT (from the global offset table) and the
5284 register into the register now, and pretend we were
5285 not using a base register. */
5290 assert (tempreg == AT);
5292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5297 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5298 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5302 offset_expr.X_add_number =
5303 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5308 /* This is needed because this instruction uses $gp, but
5309 the first instruction on the main stream does not. */
5310 macro_build (NULL, "nop", "");
5313 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5314 local_reloc_type, mips_gp_register);
5315 if (expr1.X_add_number >= -0x8000
5316 && expr1.X_add_number < 0x8000)
5319 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5320 tempreg, tempreg, BFD_RELOC_LO16);
5321 /* FIXME: If add_number is 0, and there was no base
5322 register, the external symbol case ended with a load,
5323 so if the symbol turns out to not be external, and
5324 the next instruction uses tempreg, an unnecessary nop
5325 will be inserted. */
5331 /* We must add in the base register now, as in the
5332 external symbol case. */
5333 assert (tempreg == AT);
5335 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5338 /* We set breg to 0 because we have arranged to add
5339 it in in both cases. */
5343 macro_build_lui (&expr1, AT);
5344 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5345 AT, AT, BFD_RELOC_LO16);
5346 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5347 tempreg, tempreg, AT);
5351 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5353 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5354 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5355 int add_breg_early = 0;
5357 /* This is the large GOT case. If this is a reference to an
5358 external symbol, and there is no constant, we want
5359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5360 add $tempreg,$tempreg,$gp
5361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5362 or for lca or if tempreg is PIC_CALL_REG
5363 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5364 add $tempreg,$tempreg,$gp
5365 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5367 If we have a small constant, and this is a reference to
5368 an external symbol, we want
5369 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5370 add $tempreg,$tempreg,$gp
5371 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5372 addi $tempreg,$tempreg,<constant>
5374 If we have a large constant, and this is a reference to
5375 an external symbol, we want
5376 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5377 addu $tempreg,$tempreg,$gp
5378 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5379 lui $at,<hiconstant>
5380 addi $at,$at,<loconstant>
5381 add $tempreg,$tempreg,$at
5383 If we have NewABI, and we know it's a local symbol, we want
5384 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5385 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5386 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5388 relax_start (offset_expr.X_add_symbol);
5390 expr1.X_add_number = offset_expr.X_add_number;
5391 offset_expr.X_add_number = 0;
5393 if (expr1.X_add_number == 0 && breg == 0
5394 && (call || tempreg == PIC_CALL_REG))
5396 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5397 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5399 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5401 tempreg, tempreg, mips_gp_register);
5402 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5403 tempreg, lw_reloc_type, tempreg);
5405 if (expr1.X_add_number == 0)
5407 else if (expr1.X_add_number >= -0x8000
5408 && expr1.X_add_number < 0x8000)
5410 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5411 tempreg, tempreg, BFD_RELOC_LO16);
5413 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5417 /* If we are going to add in a base register, and the
5418 target register and the base register are the same,
5419 then we are using AT as a temporary register. Since
5420 we want to load the constant into AT, we add our
5421 current AT (from the global offset table) and the
5422 register into the register now, and pretend we were
5423 not using a base register. */
5428 assert (tempreg == AT);
5429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5435 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5441 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5444 offset_expr.X_add_number = expr1.X_add_number;
5445 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5446 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5447 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5448 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5451 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5452 treg, tempreg, breg);
5465 if (mips_pic == NO_PIC)
5466 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5468 s = ADDRESS_ADD_INSN;
5470 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5479 /* The j instruction may not be used in PIC code, since it
5480 requires an absolute address. We convert it to a b
5482 if (mips_pic == NO_PIC)
5483 macro_build (&offset_expr, "j", "a");
5485 macro_build (&offset_expr, "b", "p");
5488 /* The jal instructions must be handled as macros because when
5489 generating PIC code they expand to multi-instruction
5490 sequences. Normally they are simple instructions. */
5495 if (mips_pic == NO_PIC)
5496 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5497 else if (mips_pic == SVR4_PIC)
5499 if (sreg != PIC_CALL_REG)
5500 as_warn (_("MIPS PIC call to register other than $25"));
5502 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5505 if (mips_cprestore_offset < 0)
5506 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5509 if (! mips_frame_reg_valid)
5511 as_warn (_("No .frame pseudo-op used in PIC code"));
5512 /* Quiet this warning. */
5513 mips_frame_reg_valid = 1;
5515 if (! mips_cprestore_valid)
5517 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5518 /* Quiet this warning. */
5519 mips_cprestore_valid = 1;
5521 expr1.X_add_number = mips_cprestore_offset;
5522 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5525 HAVE_64BIT_ADDRESSES);
5535 if (mips_pic == NO_PIC)
5536 macro_build (&offset_expr, "jal", "a");
5537 else if (mips_pic == SVR4_PIC)
5539 /* If this is a reference to an external symbol, and we are
5540 using a small GOT, we want
5541 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5545 lw $gp,cprestore($sp)
5546 The cprestore value is set using the .cprestore
5547 pseudo-op. If we are using a big GOT, we want
5548 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5550 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5554 lw $gp,cprestore($sp)
5555 If the symbol is not external, we want
5556 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5558 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5561 lw $gp,cprestore($sp)
5563 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5564 sequences above, minus nops, unless the symbol is local,
5565 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5571 relax_start (offset_expr.X_add_symbol);
5572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5573 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5576 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5577 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5583 relax_start (offset_expr.X_add_symbol);
5584 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5585 BFD_RELOC_MIPS_CALL_HI16);
5586 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5587 PIC_CALL_REG, mips_gp_register);
5588 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5589 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5592 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5593 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5595 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5596 PIC_CALL_REG, PIC_CALL_REG,
5597 BFD_RELOC_MIPS_GOT_OFST);
5601 macro_build_jalr (&offset_expr);
5605 relax_start (offset_expr.X_add_symbol);
5608 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5609 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5618 gpdelay = reg_needs_delay (mips_gp_register);
5619 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5620 BFD_RELOC_MIPS_CALL_HI16);
5621 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5622 PIC_CALL_REG, mips_gp_register);
5623 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5624 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5629 macro_build (NULL, "nop", "");
5631 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5632 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5635 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5636 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5638 macro_build_jalr (&offset_expr);
5640 if (mips_cprestore_offset < 0)
5641 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5644 if (! mips_frame_reg_valid)
5646 as_warn (_("No .frame pseudo-op used in PIC code"));
5647 /* Quiet this warning. */
5648 mips_frame_reg_valid = 1;
5650 if (! mips_cprestore_valid)
5652 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5653 /* Quiet this warning. */
5654 mips_cprestore_valid = 1;
5656 if (mips_opts.noreorder)
5657 macro_build (NULL, "nop", "");
5658 expr1.X_add_number = mips_cprestore_offset;
5659 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5662 HAVE_64BIT_ADDRESSES);
5688 /* Itbl support may require additional care here. */
5693 /* Itbl support may require additional care here. */
5698 /* Itbl support may require additional care here. */
5703 /* Itbl support may require additional care here. */
5715 if (mips_opts.arch == CPU_R4650)
5717 as_bad (_("opcode not supported on this processor"));
5721 /* Itbl support may require additional care here. */
5726 /* Itbl support may require additional care here. */
5731 /* Itbl support may require additional care here. */
5751 if (breg == treg || coproc || lr)
5773 /* Itbl support may require additional care here. */
5778 /* Itbl support may require additional care here. */
5783 /* Itbl support may require additional care here. */
5788 /* Itbl support may require additional care here. */
5804 if (mips_opts.arch == CPU_R4650)
5806 as_bad (_("opcode not supported on this processor"));
5811 /* Itbl support may require additional care here. */
5815 /* Itbl support may require additional care here. */
5820 /* Itbl support may require additional care here. */
5832 /* Itbl support may require additional care here. */
5833 if (mask == M_LWC1_AB
5834 || mask == M_SWC1_AB
5835 || mask == M_LDC1_AB
5836 || mask == M_SDC1_AB
5845 /* Sign-extending 32-bit constants makes their handling easier.
5846 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5848 if ((! HAVE_64BIT_ADDRESSES
5849 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5850 && (offset_expr.X_op == O_constant)
5851 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5852 == ~((bfd_vma) 0x7fffffff)))
5854 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5855 as_bad (_("constant too large"));
5857 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5858 ^ 0x80000000) - 0x80000000);
5861 if (offset_expr.X_op != O_constant
5862 && offset_expr.X_op != O_symbol)
5864 as_bad (_("expression too complex"));
5865 offset_expr.X_op = O_constant;
5868 /* A constant expression in PIC code can be handled just as it
5869 is in non PIC code. */
5870 if (mips_pic == NO_PIC
5871 || offset_expr.X_op == O_constant)
5873 /* If this is a reference to a GP relative symbol, and there
5874 is no base register, we want
5875 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5876 Otherwise, if there is no base register, we want
5877 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5878 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5879 If we have a constant, we need two instructions anyhow,
5880 so we always use the latter form.
5882 If we have a base register, and this is a reference to a
5883 GP relative symbol, we want
5884 addu $tempreg,$breg,$gp
5885 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5887 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5888 addu $tempreg,$tempreg,$breg
5889 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5890 With a constant we always use the latter case.
5892 With 64bit address space and no base register and $at usable,
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5895 lui $at,<sym> (BFD_RELOC_HI16_S)
5896 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5899 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5900 If we have a base register, we want
5901 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5902 lui $at,<sym> (BFD_RELOC_HI16_S)
5903 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5907 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5909 Without $at we can't generate the optimal path for superscalar
5910 processors here since this would require two temporary registers.
5911 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5912 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5914 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5916 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5917 If we have a base register, we want
5918 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5919 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5921 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5923 daddu $tempreg,$tempreg,$breg
5924 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5926 If we have 64-bit addresses, as an optimization, for
5927 addresses which are 32-bit constants (e.g. kseg0/kseg1
5928 addresses) we fall back to the 32-bit address generation
5929 mechanism since it is more efficient. Note that due to
5930 the signed offset used by memory operations, the 32-bit
5931 range is shifted down by 32768 here. This code should
5932 probably attempt to generate 64-bit constants more
5933 efficiently in general.
5935 As an extension for architectures with 64-bit registers,
5936 we don't truncate 64-bit addresses given as literal
5937 constants down to 32 bits, to support existing practice
5938 in the mips64 Linux (the kernel), that compiles source
5939 files with -mabi=64, assembling them as o32 or n32 (with
5940 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5941 the whole kernel is loaded into a memory region that is
5942 addressable with sign-extended 32-bit addresses, it is
5943 wasteful to compute the upper 32 bits of every
5944 non-literal address, that takes more space and time.
5945 Some day this should probably be implemented as an
5946 assembler option, such that the kernel doesn't have to
5947 use such ugly hacks, even though it will still have to
5948 end up converting the binary to ELF32 for a number of
5949 platforms whose boot loaders don't support ELF64
5951 if ((HAVE_64BIT_ADDRESSES
5952 && ! (offset_expr.X_op == O_constant
5953 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5955 && offset_expr.X_op == O_constant
5956 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5958 /* ??? We don't provide a GP-relative alternative for
5959 these macros. It used not to be possible with the
5960 original relaxation code, but it could be done now. */
5962 if (used_at == 0 && ! mips_opts.noat)
5964 macro_build (&offset_expr, "lui", "t,u", tempreg,
5965 BFD_RELOC_MIPS_HIGHEST);
5966 macro_build (&offset_expr, "lui", "t,u", AT,
5968 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5969 tempreg, BFD_RELOC_MIPS_HIGHER);
5971 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
5972 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5973 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5974 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
5980 macro_build (&offset_expr, "lui", "t,u", tempreg,
5981 BFD_RELOC_MIPS_HIGHEST);
5982 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5983 tempreg, BFD_RELOC_MIPS_HIGHER);
5984 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5985 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5986 tempreg, BFD_RELOC_HI16_S);
5987 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5989 macro_build (NULL, "daddu", "d,v,t",
5990 tempreg, tempreg, breg);
5991 macro_build (&offset_expr, s, fmt, treg,
5992 BFD_RELOC_LO16, tempreg);
5998 if (offset_expr.X_op == O_constant
5999 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6000 as_bad (_("load/store address overflow (max 32 bits)"));
6004 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6005 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6007 relax_start (offset_expr.X_add_symbol);
6008 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6013 macro_build_lui (&offset_expr, tempreg);
6014 macro_build (&offset_expr, s, fmt, treg,
6015 BFD_RELOC_LO16, tempreg);
6016 if (mips_relax.sequence)
6021 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6022 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6024 relax_start (offset_expr.X_add_symbol);
6025 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6026 tempreg, breg, mips_gp_register);
6027 macro_build (&offset_expr, s, fmt, treg,
6028 BFD_RELOC_GPREL16, tempreg);
6031 macro_build_lui (&offset_expr, tempreg);
6032 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6033 tempreg, tempreg, breg);
6034 macro_build (&offset_expr, s, fmt, treg,
6035 BFD_RELOC_LO16, tempreg);
6036 if (mips_relax.sequence)
6040 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6042 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6044 /* If this is a reference to an external symbol, we want
6045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6047 <op> $treg,0($tempreg)
6049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6051 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6052 <op> $treg,0($tempreg)
6055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6056 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6058 If there is a base register, we add it to $tempreg before
6059 the <op>. If there is a constant, we stick it in the
6060 <op> instruction. We don't handle constants larger than
6061 16 bits, because we have no way to load the upper 16 bits
6062 (actually, we could handle them for the subset of cases
6063 in which we are not using $at). */
6064 assert (offset_expr.X_op == O_symbol);
6067 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6068 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6070 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6071 tempreg, tempreg, breg);
6072 macro_build (&offset_expr, s, fmt, treg,
6073 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6080 expr1.X_add_number = offset_expr.X_add_number;
6081 offset_expr.X_add_number = 0;
6082 if (expr1.X_add_number < -0x8000
6083 || expr1.X_add_number >= 0x8000)
6084 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6085 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6086 lw_reloc_type, mips_gp_register);
6088 relax_start (offset_expr.X_add_symbol);
6090 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6091 tempreg, BFD_RELOC_LO16);
6094 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6095 tempreg, tempreg, breg);
6096 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6098 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6102 /* If this is a reference to an external symbol, we want
6103 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6104 addu $tempreg,$tempreg,$gp
6105 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6106 <op> $treg,0($tempreg)
6108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6110 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6111 <op> $treg,0($tempreg)
6112 If there is a base register, we add it to $tempreg before
6113 the <op>. If there is a constant, we stick it in the
6114 <op> instruction. We don't handle constants larger than
6115 16 bits, because we have no way to load the upper 16 bits
6116 (actually, we could handle them for the subset of cases
6117 in which we are not using $at). */
6118 assert (offset_expr.X_op == O_symbol);
6119 expr1.X_add_number = offset_expr.X_add_number;
6120 offset_expr.X_add_number = 0;
6121 if (expr1.X_add_number < -0x8000
6122 || expr1.X_add_number >= 0x8000)
6123 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6124 gpdelay = reg_needs_delay (mips_gp_register);
6125 relax_start (offset_expr.X_add_symbol);
6126 macro_build (&offset_expr, "lui", "t,u", tempreg,
6127 BFD_RELOC_MIPS_GOT_HI16);
6128 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6130 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6131 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6134 macro_build (NULL, "nop", "");
6135 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6136 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6138 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6139 tempreg, BFD_RELOC_LO16);
6143 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6144 tempreg, tempreg, breg);
6145 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6147 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6149 /* If this is a reference to an external symbol, we want
6150 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6151 add $tempreg,$tempreg,$gp
6152 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6153 <op> $treg,<ofst>($tempreg)
6154 Otherwise, for local symbols, we want:
6155 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6156 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6157 assert (offset_expr.X_op == O_symbol);
6158 expr1.X_add_number = offset_expr.X_add_number;
6159 offset_expr.X_add_number = 0;
6160 if (expr1.X_add_number < -0x8000
6161 || expr1.X_add_number >= 0x8000)
6162 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6163 relax_start (offset_expr.X_add_symbol);
6164 macro_build (&offset_expr, "lui", "t,u", tempreg,
6165 BFD_RELOC_MIPS_GOT_HI16);
6166 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6168 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6169 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6171 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6172 tempreg, tempreg, breg);
6173 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6176 offset_expr.X_add_number = expr1.X_add_number;
6177 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6178 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6180 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6181 tempreg, tempreg, breg);
6182 macro_build (&offset_expr, s, fmt, treg,
6183 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6196 load_register (treg, &imm_expr, 0);
6200 load_register (treg, &imm_expr, 1);
6204 if (imm_expr.X_op == O_constant)
6206 load_register (AT, &imm_expr, 0);
6207 macro_build (NULL, "mtc1", "t,G", AT, treg);
6212 assert (offset_expr.X_op == O_symbol
6213 && strcmp (segment_name (S_GET_SEGMENT
6214 (offset_expr.X_add_symbol)),
6216 && offset_expr.X_add_number == 0);
6217 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6218 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6223 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6224 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6225 order 32 bits of the value and the low order 32 bits are either
6226 zero or in OFFSET_EXPR. */
6227 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6229 if (HAVE_64BIT_GPRS)
6230 load_register (treg, &imm_expr, 1);
6235 if (target_big_endian)
6247 load_register (hreg, &imm_expr, 0);
6250 if (offset_expr.X_op == O_absent)
6251 move_register (lreg, 0);
6254 assert (offset_expr.X_op == O_constant);
6255 load_register (lreg, &offset_expr, 0);
6262 /* We know that sym is in the .rdata section. First we get the
6263 upper 16 bits of the address. */
6264 if (mips_pic == NO_PIC)
6266 macro_build_lui (&offset_expr, AT);
6268 else if (mips_pic == SVR4_PIC)
6270 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6271 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6276 /* Now we load the register(s). */
6277 if (HAVE_64BIT_GPRS)
6278 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6281 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6284 /* FIXME: How in the world do we deal with the possible
6286 offset_expr.X_add_number += 4;
6287 macro_build (&offset_expr, "lw", "t,o(b)",
6288 treg + 1, BFD_RELOC_LO16, AT);
6294 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6295 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6296 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6297 the value and the low order 32 bits are either zero or in
6299 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6301 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6302 if (HAVE_64BIT_FPRS)
6304 assert (HAVE_64BIT_GPRS);
6305 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6309 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6310 if (offset_expr.X_op == O_absent)
6311 macro_build (NULL, "mtc1", "t,G", 0, treg);
6314 assert (offset_expr.X_op == O_constant);
6315 load_register (AT, &offset_expr, 0);
6316 macro_build (NULL, "mtc1", "t,G", AT, treg);
6322 assert (offset_expr.X_op == O_symbol
6323 && offset_expr.X_add_number == 0);
6324 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6325 if (strcmp (s, ".lit8") == 0)
6327 if (mips_opts.isa != ISA_MIPS1)
6329 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6330 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6333 breg = mips_gp_register;
6334 r = BFD_RELOC_MIPS_LITERAL;
6339 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6340 if (mips_pic == SVR4_PIC)
6341 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6342 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6345 /* FIXME: This won't work for a 64 bit address. */
6346 macro_build_lui (&offset_expr, AT);
6349 if (mips_opts.isa != ISA_MIPS1)
6351 macro_build (&offset_expr, "ldc1", "T,o(b)",
6352 treg, BFD_RELOC_LO16, AT);
6361 if (mips_opts.arch == CPU_R4650)
6363 as_bad (_("opcode not supported on this processor"));
6366 /* Even on a big endian machine $fn comes before $fn+1. We have
6367 to adjust when loading from memory. */
6370 assert (mips_opts.isa == ISA_MIPS1);
6371 macro_build (&offset_expr, "lwc1", "T,o(b)",
6372 target_big_endian ? treg + 1 : treg, r, breg);
6373 /* FIXME: A possible overflow which I don't know how to deal
6375 offset_expr.X_add_number += 4;
6376 macro_build (&offset_expr, "lwc1", "T,o(b)",
6377 target_big_endian ? treg : treg + 1, r, breg);
6385 * The MIPS assembler seems to check for X_add_number not
6386 * being double aligned and generating:
6389 * addiu at,at,%lo(foo+1)
6392 * But, the resulting address is the same after relocation so why
6393 * generate the extra instruction?
6395 if (mips_opts.arch == CPU_R4650)
6397 as_bad (_("opcode not supported on this processor"));
6400 /* Itbl support may require additional care here. */
6402 if (mips_opts.isa != ISA_MIPS1)
6413 if (mips_opts.arch == CPU_R4650)
6415 as_bad (_("opcode not supported on this processor"));
6419 if (mips_opts.isa != ISA_MIPS1)
6427 /* Itbl support may require additional care here. */
6432 if (HAVE_64BIT_GPRS)
6443 if (HAVE_64BIT_GPRS)
6453 if (offset_expr.X_op != O_symbol
6454 && offset_expr.X_op != O_constant)
6456 as_bad (_("expression too complex"));
6457 offset_expr.X_op = O_constant;
6460 /* Even on a big endian machine $fn comes before $fn+1. We have
6461 to adjust when loading from memory. We set coproc if we must
6462 load $fn+1 first. */
6463 /* Itbl support may require additional care here. */
6464 if (! target_big_endian)
6467 if (mips_pic == NO_PIC
6468 || offset_expr.X_op == O_constant)
6470 /* If this is a reference to a GP relative symbol, we want
6471 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6472 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6473 If we have a base register, we use this
6475 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6476 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6477 If this is not a GP relative symbol, we want
6478 lui $at,<sym> (BFD_RELOC_HI16_S)
6479 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6480 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6481 If there is a base register, we add it to $at after the
6482 lui instruction. If there is a constant, we always use
6484 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6485 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6489 relax_start (offset_expr.X_add_symbol);
6492 tempreg = mips_gp_register;
6497 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6498 AT, breg, mips_gp_register);
6503 /* Itbl support may require additional care here. */
6504 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6505 BFD_RELOC_GPREL16, tempreg);
6506 offset_expr.X_add_number += 4;
6508 /* Set mips_optimize to 2 to avoid inserting an
6510 hold_mips_optimize = mips_optimize;
6512 /* Itbl support may require additional care here. */
6513 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6514 BFD_RELOC_GPREL16, tempreg);
6515 mips_optimize = hold_mips_optimize;
6519 /* We just generated two relocs. When tc_gen_reloc
6520 handles this case, it will skip the first reloc and
6521 handle the second. The second reloc already has an
6522 extra addend of 4, which we added above. We must
6523 subtract it out, and then subtract another 4 to make
6524 the first reloc come out right. The second reloc
6525 will come out right because we are going to add 4 to
6526 offset_expr when we build its instruction below.
6528 If we have a symbol, then we don't want to include
6529 the offset, because it will wind up being included
6530 when we generate the reloc. */
6532 if (offset_expr.X_op == O_constant)
6533 offset_expr.X_add_number -= 8;
6536 offset_expr.X_add_number = -4;
6537 offset_expr.X_op = O_constant;
6540 macro_build_lui (&offset_expr, AT);
6542 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6543 /* Itbl support may require additional care here. */
6544 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6545 BFD_RELOC_LO16, AT);
6546 /* FIXME: How do we handle overflow here? */
6547 offset_expr.X_add_number += 4;
6548 /* Itbl support may require additional care here. */
6549 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6550 BFD_RELOC_LO16, AT);
6551 if (mips_relax.sequence)
6554 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6556 /* If this is a reference to an external symbol, we want
6557 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6562 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6564 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6565 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6566 If there is a base register we add it to $at before the
6567 lwc1 instructions. If there is a constant we include it
6568 in the lwc1 instructions. */
6570 expr1.X_add_number = offset_expr.X_add_number;
6571 if (expr1.X_add_number < -0x8000
6572 || expr1.X_add_number >= 0x8000 - 4)
6573 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6574 load_got_offset (AT, &offset_expr);
6577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6579 /* Set mips_optimize to 2 to avoid inserting an undesired
6581 hold_mips_optimize = mips_optimize;
6584 /* Itbl support may require additional care here. */
6585 relax_start (offset_expr.X_add_symbol);
6586 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6587 BFD_RELOC_LO16, AT);
6588 expr1.X_add_number += 4;
6589 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6590 BFD_RELOC_LO16, AT);
6592 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6593 BFD_RELOC_LO16, AT);
6594 offset_expr.X_add_number += 4;
6595 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6596 BFD_RELOC_LO16, AT);
6599 mips_optimize = hold_mips_optimize;
6601 else if (mips_pic == SVR4_PIC)
6605 /* If this is a reference to an external symbol, we want
6606 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6608 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6613 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6615 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6616 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6617 If there is a base register we add it to $at before the
6618 lwc1 instructions. If there is a constant we include it
6619 in the lwc1 instructions. */
6621 expr1.X_add_number = offset_expr.X_add_number;
6622 offset_expr.X_add_number = 0;
6623 if (expr1.X_add_number < -0x8000
6624 || expr1.X_add_number >= 0x8000 - 4)
6625 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6626 gpdelay = reg_needs_delay (mips_gp_register);
6627 relax_start (offset_expr.X_add_symbol);
6628 macro_build (&offset_expr, "lui", "t,u",
6629 AT, BFD_RELOC_MIPS_GOT_HI16);
6630 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6631 AT, AT, mips_gp_register);
6632 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6633 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6636 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6637 /* Itbl support may require additional care here. */
6638 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6639 BFD_RELOC_LO16, AT);
6640 expr1.X_add_number += 4;
6642 /* Set mips_optimize to 2 to avoid inserting an undesired
6644 hold_mips_optimize = mips_optimize;
6646 /* Itbl support may require additional care here. */
6647 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6648 BFD_RELOC_LO16, AT);
6649 mips_optimize = hold_mips_optimize;
6650 expr1.X_add_number -= 4;
6653 offset_expr.X_add_number = expr1.X_add_number;
6655 macro_build (NULL, "nop", "");
6656 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6657 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6660 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6661 /* Itbl support may require additional care here. */
6662 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6663 BFD_RELOC_LO16, AT);
6664 offset_expr.X_add_number += 4;
6666 /* Set mips_optimize to 2 to avoid inserting an undesired
6668 hold_mips_optimize = mips_optimize;
6670 /* Itbl support may require additional care here. */
6671 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6672 BFD_RELOC_LO16, AT);
6673 mips_optimize = hold_mips_optimize;
6690 assert (HAVE_32BIT_ADDRESSES);
6691 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6692 offset_expr.X_add_number += 4;
6693 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6696 /* New code added to support COPZ instructions.
6697 This code builds table entries out of the macros in mip_opcodes.
6698 R4000 uses interlocks to handle coproc delays.
6699 Other chips (like the R3000) require nops to be inserted for delays.
6701 FIXME: Currently, we require that the user handle delays.
6702 In order to fill delay slots for non-interlocked chips,
6703 we must have a way to specify delays based on the coprocessor.
6704 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6705 What are the side-effects of the cop instruction?
6706 What cache support might we have and what are its effects?
6707 Both coprocessor & memory require delays. how long???
6708 What registers are read/set/modified?
6710 If an itbl is provided to interpret cop instructions,
6711 this knowledge can be encoded in the itbl spec. */
6725 /* For now we just do C (same as Cz). The parameter will be
6726 stored in insn_opcode by mips_ip. */
6727 macro_build (NULL, s, "C", ip->insn_opcode);
6731 move_register (dreg, sreg);
6734 #ifdef LOSING_COMPILER
6736 /* Try and see if this is a new itbl instruction.
6737 This code builds table entries out of the macros in mip_opcodes.
6738 FIXME: For now we just assemble the expression and pass it's
6739 value along as a 32-bit immediate.
6740 We may want to have the assembler assemble this value,
6741 so that we gain the assembler's knowledge of delay slots,
6743 Would it be more efficient to use mask (id) here? */
6744 if (itbl_have_entries
6745 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6747 s = ip->insn_mo->name;
6749 coproc = ITBL_DECODE_PNUM (immed_expr);;
6750 macro_build (&immed_expr, s, "C");
6757 as_warn (_("Macro used $at after \".set noat\""));
6761 macro2 (struct mips_cl_insn *ip)
6763 register int treg, sreg, dreg, breg;
6778 bfd_reloc_code_real_type r;
6780 treg = (ip->insn_opcode >> 16) & 0x1f;
6781 dreg = (ip->insn_opcode >> 11) & 0x1f;
6782 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6783 mask = ip->insn_mo->mask;
6785 expr1.X_op = O_constant;
6786 expr1.X_op_symbol = NULL;
6787 expr1.X_add_symbol = NULL;
6788 expr1.X_add_number = 1;
6792 #endif /* LOSING_COMPILER */
6797 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6798 macro_build (NULL, "mflo", "d", dreg);
6804 /* The MIPS assembler some times generates shifts and adds. I'm
6805 not trying to be that fancy. GCC should do this for us
6807 load_register (AT, &imm_expr, dbl);
6808 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6809 macro_build (NULL, "mflo", "d", dreg);
6822 mips_emit_delays (TRUE);
6823 ++mips_opts.noreorder;
6824 mips_any_noreorder = 1;
6826 load_register (AT, &imm_expr, dbl);
6827 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6828 macro_build (NULL, "mflo", "d", dreg);
6829 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6830 macro_build (NULL, "mfhi", "d", AT);
6832 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6835 expr1.X_add_number = 8;
6836 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6837 macro_build (NULL, "nop", "", 0);
6838 macro_build (NULL, "break", "c", 6);
6840 --mips_opts.noreorder;
6841 macro_build (NULL, "mflo", "d", dreg);
6854 mips_emit_delays (TRUE);
6855 ++mips_opts.noreorder;
6856 mips_any_noreorder = 1;
6858 load_register (AT, &imm_expr, dbl);
6859 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6860 sreg, imm ? AT : treg);
6861 macro_build (NULL, "mfhi", "d", AT);
6862 macro_build (NULL, "mflo", "d", dreg);
6864 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6867 expr1.X_add_number = 8;
6868 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6869 macro_build (NULL, "nop", "", 0);
6870 macro_build (NULL, "break", "c", 6);
6872 --mips_opts.noreorder;
6876 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6888 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6889 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6894 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6895 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6896 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6897 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6901 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6913 macro_build (NULL, "negu", "d,w", tempreg, treg);
6914 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6919 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6920 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6921 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6922 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6930 if (imm_expr.X_op != O_constant)
6931 as_bad (_("Improper rotate count"));
6932 rot = imm_expr.X_add_number & 0x3f;
6933 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6935 rot = (64 - rot) & 0x3f;
6937 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6939 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6944 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
6947 l = (rot < 0x20) ? "dsll" : "dsll32";
6948 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6950 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
6951 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6952 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6960 if (imm_expr.X_op != O_constant)
6961 as_bad (_("Improper rotate count"));
6962 rot = imm_expr.X_add_number & 0x1f;
6963 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6965 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6970 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
6973 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
6974 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6975 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6980 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6982 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
6985 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6986 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
6987 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
6988 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6992 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6994 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
6997 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6998 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
6999 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7000 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7008 if (imm_expr.X_op != O_constant)
7009 as_bad (_("Improper rotate count"));
7010 rot = imm_expr.X_add_number & 0x3f;
7011 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7014 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7016 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7021 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7024 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7025 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7027 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7028 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7029 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7037 if (imm_expr.X_op != O_constant)
7038 as_bad (_("Improper rotate count"));
7039 rot = imm_expr.X_add_number & 0x1f;
7040 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7042 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7047 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7050 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7051 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7052 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7057 if (mips_opts.arch == CPU_R4650)
7059 as_bad (_("opcode not supported on this processor"));
7062 assert (mips_opts.isa == ISA_MIPS1);
7063 /* Even on a big endian machine $fn comes before $fn+1. We have
7064 to adjust when storing to memory. */
7065 macro_build (&offset_expr, "swc1", "T,o(b)",
7066 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7067 offset_expr.X_add_number += 4;
7068 macro_build (&offset_expr, "swc1", "T,o(b)",
7069 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7074 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7076 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7079 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7080 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7085 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7087 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7092 as_warn (_("Instruction %s: result is always false"),
7094 move_register (dreg, 0);
7097 if (imm_expr.X_op == O_constant
7098 && imm_expr.X_add_number >= 0
7099 && imm_expr.X_add_number < 0x10000)
7101 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7104 else if (imm_expr.X_op == O_constant
7105 && imm_expr.X_add_number > -0x8000
7106 && imm_expr.X_add_number < 0)
7108 imm_expr.X_add_number = -imm_expr.X_add_number;
7109 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7110 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7115 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7116 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7119 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7124 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7130 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7131 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7134 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7136 if (imm_expr.X_op == O_constant
7137 && imm_expr.X_add_number >= -0x8000
7138 && imm_expr.X_add_number < 0x8000)
7140 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7141 dreg, sreg, BFD_RELOC_LO16);
7146 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7147 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7151 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7156 case M_SGT: /* sreg > treg <==> treg < sreg */
7162 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7165 case M_SGT_I: /* sreg > I <==> I < sreg */
7171 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7172 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7175 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7181 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7182 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7185 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7191 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7192 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7193 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7197 if (imm_expr.X_op == O_constant
7198 && imm_expr.X_add_number >= -0x8000
7199 && imm_expr.X_add_number < 0x8000)
7201 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7204 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7205 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7209 if (imm_expr.X_op == O_constant
7210 && imm_expr.X_add_number >= -0x8000
7211 && imm_expr.X_add_number < 0x8000)
7213 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7217 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7218 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7223 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7225 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7228 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7229 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7234 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7236 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7241 as_warn (_("Instruction %s: result is always true"),
7243 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7244 dreg, 0, BFD_RELOC_LO16);
7247 if (imm_expr.X_op == O_constant
7248 && imm_expr.X_add_number >= 0
7249 && imm_expr.X_add_number < 0x10000)
7251 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7254 else if (imm_expr.X_op == O_constant
7255 && imm_expr.X_add_number > -0x8000
7256 && imm_expr.X_add_number < 0)
7258 imm_expr.X_add_number = -imm_expr.X_add_number;
7259 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7260 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7265 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7266 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7269 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7277 if (imm_expr.X_op == O_constant
7278 && imm_expr.X_add_number > -0x8000
7279 && imm_expr.X_add_number <= 0x8000)
7281 imm_expr.X_add_number = -imm_expr.X_add_number;
7282 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7283 dreg, sreg, BFD_RELOC_LO16);
7286 load_register (AT, &imm_expr, dbl);
7287 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7293 if (imm_expr.X_op == O_constant
7294 && imm_expr.X_add_number > -0x8000
7295 && imm_expr.X_add_number <= 0x8000)
7297 imm_expr.X_add_number = -imm_expr.X_add_number;
7298 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7299 dreg, sreg, BFD_RELOC_LO16);
7302 load_register (AT, &imm_expr, dbl);
7303 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7324 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7325 macro_build (NULL, s, "s,t", sreg, AT);
7330 assert (mips_opts.isa == ISA_MIPS1);
7331 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7332 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7335 * Is the double cfc1 instruction a bug in the mips assembler;
7336 * or is there a reason for it?
7338 mips_emit_delays (TRUE);
7339 ++mips_opts.noreorder;
7340 mips_any_noreorder = 1;
7341 macro_build (NULL, "cfc1", "t,G", treg, RA);
7342 macro_build (NULL, "cfc1", "t,G", treg, RA);
7343 macro_build (NULL, "nop", "");
7344 expr1.X_add_number = 3;
7345 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7346 expr1.X_add_number = 2;
7347 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7348 macro_build (NULL, "ctc1", "t,G", AT, RA);
7349 macro_build (NULL, "nop", "");
7350 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7352 macro_build (NULL, "ctc1", "t,G", treg, RA);
7353 macro_build (NULL, "nop", "");
7354 --mips_opts.noreorder;
7363 if (offset_expr.X_add_number >= 0x7fff)
7364 as_bad (_("operand overflow"));
7365 if (! target_big_endian)
7366 ++offset_expr.X_add_number;
7367 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7368 if (! target_big_endian)
7369 --offset_expr.X_add_number;
7371 ++offset_expr.X_add_number;
7372 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7373 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7374 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7387 if (offset_expr.X_add_number >= 0x8000 - off)
7388 as_bad (_("operand overflow"));
7393 if (! target_big_endian)
7394 offset_expr.X_add_number += off;
7395 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7396 if (! target_big_endian)
7397 offset_expr.X_add_number -= off;
7399 offset_expr.X_add_number += off;
7400 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7402 /* If necessary, move the result in tempreg the final destination. */
7403 if (treg == tempreg)
7405 /* Protect second load's delay slot. */
7407 move_register (treg, tempreg);
7421 load_address (AT, &offset_expr, &used_at);
7423 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7424 if (! target_big_endian)
7425 expr1.X_add_number = off;
7427 expr1.X_add_number = 0;
7428 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7429 if (! target_big_endian)
7430 expr1.X_add_number = 0;
7432 expr1.X_add_number = off;
7433 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7439 load_address (AT, &offset_expr, &used_at);
7441 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7442 if (target_big_endian)
7443 expr1.X_add_number = 0;
7444 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7445 treg, BFD_RELOC_LO16, AT);
7446 if (target_big_endian)
7447 expr1.X_add_number = 1;
7449 expr1.X_add_number = 0;
7450 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7451 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7452 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7456 if (offset_expr.X_add_number >= 0x7fff)
7457 as_bad (_("operand overflow"));
7458 if (target_big_endian)
7459 ++offset_expr.X_add_number;
7460 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7461 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7462 if (target_big_endian)
7463 --offset_expr.X_add_number;
7465 ++offset_expr.X_add_number;
7466 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7479 if (offset_expr.X_add_number >= 0x8000 - off)
7480 as_bad (_("operand overflow"));
7481 if (! target_big_endian)
7482 offset_expr.X_add_number += off;
7483 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7484 if (! target_big_endian)
7485 offset_expr.X_add_number -= off;
7487 offset_expr.X_add_number += off;
7488 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7502 load_address (AT, &offset_expr, &used_at);
7504 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7505 if (! target_big_endian)
7506 expr1.X_add_number = off;
7508 expr1.X_add_number = 0;
7509 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7510 if (! target_big_endian)
7511 expr1.X_add_number = 0;
7513 expr1.X_add_number = off;
7514 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7519 load_address (AT, &offset_expr, &used_at);
7521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7522 if (! target_big_endian)
7523 expr1.X_add_number = 0;
7524 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7525 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7526 if (! target_big_endian)
7527 expr1.X_add_number = 1;
7529 expr1.X_add_number = 0;
7530 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7531 if (! target_big_endian)
7532 expr1.X_add_number = 0;
7534 expr1.X_add_number = 1;
7535 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7536 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7537 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7541 /* FIXME: Check if this is one of the itbl macros, since they
7542 are added dynamically. */
7543 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7547 as_warn (_("Macro used $at after \".set noat\""));
7550 /* Implement macros in mips16 mode. */
7553 mips16_macro (struct mips_cl_insn *ip)
7556 int xreg, yreg, zreg, tmp;
7559 const char *s, *s2, *s3;
7561 mask = ip->insn_mo->mask;
7563 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7564 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7565 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7567 expr1.X_op = O_constant;
7568 expr1.X_op_symbol = NULL;
7569 expr1.X_add_symbol = NULL;
7570 expr1.X_add_number = 1;
7589 mips_emit_delays (TRUE);
7590 ++mips_opts.noreorder;
7591 mips_any_noreorder = 1;
7592 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7593 expr1.X_add_number = 2;
7594 macro_build (&expr1, "bnez", "x,p", yreg);
7595 macro_build (NULL, "break", "6", 7);
7597 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7598 since that causes an overflow. We should do that as well,
7599 but I don't see how to do the comparisons without a temporary
7601 --mips_opts.noreorder;
7602 macro_build (NULL, s, "x", zreg);
7621 mips_emit_delays (TRUE);
7622 ++mips_opts.noreorder;
7623 mips_any_noreorder = 1;
7624 macro_build (NULL, s, "0,x,y", xreg, yreg);
7625 expr1.X_add_number = 2;
7626 macro_build (&expr1, "bnez", "x,p", yreg);
7627 macro_build (NULL, "break", "6", 7);
7628 --mips_opts.noreorder;
7629 macro_build (NULL, s2, "x", zreg);
7635 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7636 macro_build (NULL, "mflo", "x", zreg);
7644 if (imm_expr.X_op != O_constant)
7645 as_bad (_("Unsupported large constant"));
7646 imm_expr.X_add_number = -imm_expr.X_add_number;
7647 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7651 if (imm_expr.X_op != O_constant)
7652 as_bad (_("Unsupported large constant"));
7653 imm_expr.X_add_number = -imm_expr.X_add_number;
7654 macro_build (&imm_expr, "addiu", "x,k", xreg);
7658 if (imm_expr.X_op != O_constant)
7659 as_bad (_("Unsupported large constant"));
7660 imm_expr.X_add_number = -imm_expr.X_add_number;
7661 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7683 goto do_reverse_branch;
7687 goto do_reverse_branch;
7699 goto do_reverse_branch;
7710 macro_build (NULL, s, "x,y", xreg, yreg);
7711 macro_build (&offset_expr, s2, "p");
7738 goto do_addone_branch_i;
7743 goto do_addone_branch_i;
7758 goto do_addone_branch_i;
7765 if (imm_expr.X_op != O_constant)
7766 as_bad (_("Unsupported large constant"));
7767 ++imm_expr.X_add_number;
7770 macro_build (&imm_expr, s, s3, xreg);
7771 macro_build (&offset_expr, s2, "p");
7775 expr1.X_add_number = 0;
7776 macro_build (&expr1, "slti", "x,8", yreg);
7778 move_register (xreg, yreg);
7779 expr1.X_add_number = 2;
7780 macro_build (&expr1, "bteqz", "p");
7781 macro_build (NULL, "neg", "x,w", xreg, xreg);
7785 /* For consistency checking, verify that all bits are specified either
7786 by the match/mask part of the instruction definition, or by the
7789 validate_mips_insn (const struct mips_opcode *opc)
7791 const char *p = opc->args;
7793 unsigned long used_bits = opc->mask;
7795 if ((used_bits & opc->match) != opc->match)
7797 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7798 opc->name, opc->args);
7801 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7811 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7812 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7813 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7814 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7815 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7816 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7817 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7818 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7819 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7822 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7823 c, opc->name, opc->args);
7827 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7828 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7830 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7831 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7832 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7833 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7835 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7836 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7838 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7839 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7841 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7842 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7843 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7844 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7845 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7846 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7847 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7848 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7849 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7850 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7851 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7852 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7853 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7854 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7855 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7856 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7857 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7859 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7860 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7861 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7862 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7864 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7865 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7866 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7867 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7868 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7869 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7870 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7871 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7872 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7875 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7876 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7877 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7878 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7879 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7883 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7884 c, opc->name, opc->args);
7888 if (used_bits != 0xffffffff)
7890 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7891 ~used_bits & 0xffffffff, opc->name, opc->args);
7897 /* This routine assembles an instruction into its binary format. As a
7898 side effect, it sets one of the global variables imm_reloc or
7899 offset_reloc to the type of relocation to do if one of the operands
7900 is an address expression. */
7903 mips_ip (char *str, struct mips_cl_insn *ip)
7908 struct mips_opcode *insn;
7911 unsigned int lastregno = 0;
7912 unsigned int lastpos = 0;
7913 unsigned int limlo, limhi;
7919 /* If the instruction contains a '.', we first try to match an instruction
7920 including the '.'. Then we try again without the '.'. */
7922 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7925 /* If we stopped on whitespace, then replace the whitespace with null for
7926 the call to hash_find. Save the character we replaced just in case we
7927 have to re-parse the instruction. */
7934 insn = (struct mips_opcode *) hash_find (op_hash, str);
7936 /* If we didn't find the instruction in the opcode table, try again, but
7937 this time with just the instruction up to, but not including the
7941 /* Restore the character we overwrite above (if any). */
7945 /* Scan up to the first '.' or whitespace. */
7947 *s != '\0' && *s != '.' && !ISSPACE (*s);
7951 /* If we did not find a '.', then we can quit now. */
7954 insn_error = "unrecognized opcode";
7958 /* Lookup the instruction in the hash table. */
7960 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7962 insn_error = "unrecognized opcode";
7972 assert (strcmp (insn->name, str) == 0);
7974 if (OPCODE_IS_MEMBER (insn,
7976 | (file_ase_mips16 ? INSN_MIPS16 : 0)
7977 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7978 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7984 if (insn->pinfo != INSN_MACRO)
7986 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7992 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7993 && strcmp (insn->name, insn[1].name) == 0)
8002 static char buf[100];
8004 _("opcode not supported on this processor: %s (%s)"),
8005 mips_cpu_info_from_arch (mips_opts.arch)->name,
8006 mips_cpu_info_from_isa (mips_opts.isa)->name);
8016 ip->insn_opcode = insn->match;
8018 for (args = insn->args;; ++args)
8022 s += strspn (s, " \t");
8026 case '\0': /* end of args */
8039 ip->insn_opcode |= lastregno << OP_SH_RS;
8043 ip->insn_opcode |= lastregno << OP_SH_RT;
8047 ip->insn_opcode |= lastregno << OP_SH_FT;
8051 ip->insn_opcode |= lastregno << OP_SH_FS;
8057 /* Handle optional base register.
8058 Either the base register is omitted or
8059 we must have a left paren. */
8060 /* This is dependent on the next operand specifier
8061 is a base register specification. */
8062 assert (args[1] == 'b' || args[1] == '5'
8063 || args[1] == '-' || args[1] == '4');
8067 case ')': /* these must match exactly */
8074 case '+': /* Opcode extension character. */
8077 case 'A': /* ins/ext position, becomes LSB. */
8086 my_getExpression (&imm_expr, s);
8087 check_absolute_expr (ip, &imm_expr);
8088 if ((unsigned long) imm_expr.X_add_number < limlo
8089 || (unsigned long) imm_expr.X_add_number > limhi)
8091 as_bad (_("Improper position (%lu)"),
8092 (unsigned long) imm_expr.X_add_number);
8093 imm_expr.X_add_number = limlo;
8095 lastpos = imm_expr.X_add_number;
8096 ip->insn_opcode |= (imm_expr.X_add_number
8097 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8098 imm_expr.X_op = O_absent;
8102 case 'B': /* ins size, becomes MSB. */
8111 my_getExpression (&imm_expr, s);
8112 check_absolute_expr (ip, &imm_expr);
8113 /* Check for negative input so that small negative numbers
8114 will not succeed incorrectly. The checks against
8115 (pos+size) transitively check "size" itself,
8116 assuming that "pos" is reasonable. */
8117 if ((long) imm_expr.X_add_number < 0
8118 || ((unsigned long) imm_expr.X_add_number
8120 || ((unsigned long) imm_expr.X_add_number
8123 as_bad (_("Improper insert size (%lu, position %lu)"),
8124 (unsigned long) imm_expr.X_add_number,
8125 (unsigned long) lastpos);
8126 imm_expr.X_add_number = limlo - lastpos;
8128 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8129 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8130 imm_expr.X_op = O_absent;
8134 case 'C': /* ext size, becomes MSBD. */
8147 my_getExpression (&imm_expr, s);
8148 check_absolute_expr (ip, &imm_expr);
8149 /* Check for negative input so that small negative numbers
8150 will not succeed incorrectly. The checks against
8151 (pos+size) transitively check "size" itself,
8152 assuming that "pos" is reasonable. */
8153 if ((long) imm_expr.X_add_number < 0
8154 || ((unsigned long) imm_expr.X_add_number
8156 || ((unsigned long) imm_expr.X_add_number
8159 as_bad (_("Improper extract size (%lu, position %lu)"),
8160 (unsigned long) imm_expr.X_add_number,
8161 (unsigned long) lastpos);
8162 imm_expr.X_add_number = limlo - lastpos;
8164 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8165 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8166 imm_expr.X_op = O_absent;
8171 /* +D is for disassembly only; never match. */
8175 /* "+I" is like "I", except that imm2_expr is used. */
8176 my_getExpression (&imm2_expr, s);
8177 if (imm2_expr.X_op != O_big
8178 && imm2_expr.X_op != O_constant)
8179 insn_error = _("absolute expression required");
8180 normalize_constant_expr (&imm2_expr);
8185 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8186 *args, insn->name, insn->args);
8187 /* Further processing is fruitless. */
8192 case '<': /* must be at least one digit */
8194 * According to the manual, if the shift amount is greater
8195 * than 31 or less than 0, then the shift amount should be
8196 * mod 32. In reality the mips assembler issues an error.
8197 * We issue a warning and mask out all but the low 5 bits.
8199 my_getExpression (&imm_expr, s);
8200 check_absolute_expr (ip, &imm_expr);
8201 if ((unsigned long) imm_expr.X_add_number > 31)
8203 as_warn (_("Improper shift amount (%lu)"),
8204 (unsigned long) imm_expr.X_add_number);
8205 imm_expr.X_add_number &= OP_MASK_SHAMT;
8207 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8208 imm_expr.X_op = O_absent;
8212 case '>': /* shift amount minus 32 */
8213 my_getExpression (&imm_expr, s);
8214 check_absolute_expr (ip, &imm_expr);
8215 if ((unsigned long) imm_expr.X_add_number < 32
8216 || (unsigned long) imm_expr.X_add_number > 63)
8218 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8219 imm_expr.X_op = O_absent;
8223 case 'k': /* cache code */
8224 case 'h': /* prefx code */
8225 my_getExpression (&imm_expr, s);
8226 check_absolute_expr (ip, &imm_expr);
8227 if ((unsigned long) imm_expr.X_add_number > 31)
8229 as_warn (_("Invalid value for `%s' (%lu)"),
8231 (unsigned long) imm_expr.X_add_number);
8232 imm_expr.X_add_number &= 0x1f;
8235 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8237 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8238 imm_expr.X_op = O_absent;
8242 case 'c': /* break code */
8243 my_getExpression (&imm_expr, s);
8244 check_absolute_expr (ip, &imm_expr);
8245 if ((unsigned long) imm_expr.X_add_number > 1023)
8247 as_warn (_("Illegal break code (%lu)"),
8248 (unsigned long) imm_expr.X_add_number);
8249 imm_expr.X_add_number &= OP_MASK_CODE;
8251 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8252 imm_expr.X_op = O_absent;
8256 case 'q': /* lower break code */
8257 my_getExpression (&imm_expr, s);
8258 check_absolute_expr (ip, &imm_expr);
8259 if ((unsigned long) imm_expr.X_add_number > 1023)
8261 as_warn (_("Illegal lower break code (%lu)"),
8262 (unsigned long) imm_expr.X_add_number);
8263 imm_expr.X_add_number &= OP_MASK_CODE2;
8265 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8266 imm_expr.X_op = O_absent;
8270 case 'B': /* 20-bit syscall/break code. */
8271 my_getExpression (&imm_expr, s);
8272 check_absolute_expr (ip, &imm_expr);
8273 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8274 as_warn (_("Illegal 20-bit code (%lu)"),
8275 (unsigned long) imm_expr.X_add_number);
8276 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8277 imm_expr.X_op = O_absent;
8281 case 'C': /* Coprocessor code */
8282 my_getExpression (&imm_expr, s);
8283 check_absolute_expr (ip, &imm_expr);
8284 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8286 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8287 (unsigned long) imm_expr.X_add_number);
8288 imm_expr.X_add_number &= ((1 << 25) - 1);
8290 ip->insn_opcode |= imm_expr.X_add_number;
8291 imm_expr.X_op = O_absent;
8295 case 'J': /* 19-bit wait code. */
8296 my_getExpression (&imm_expr, s);
8297 check_absolute_expr (ip, &imm_expr);
8298 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8299 as_warn (_("Illegal 19-bit code (%lu)"),
8300 (unsigned long) imm_expr.X_add_number);
8301 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8302 imm_expr.X_op = O_absent;
8306 case 'P': /* Performance register */
8307 my_getExpression (&imm_expr, s);
8308 check_absolute_expr (ip, &imm_expr);
8309 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8311 as_warn (_("Invalid performance register (%lu)"),
8312 (unsigned long) imm_expr.X_add_number);
8313 imm_expr.X_add_number &= OP_MASK_PERFREG;
8315 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8316 imm_expr.X_op = O_absent;
8320 case 'b': /* base register */
8321 case 'd': /* destination register */
8322 case 's': /* source register */
8323 case 't': /* target register */
8324 case 'r': /* both target and source */
8325 case 'v': /* both dest and source */
8326 case 'w': /* both dest and target */
8327 case 'E': /* coprocessor target register */
8328 case 'G': /* coprocessor destination register */
8329 case 'K': /* 'rdhwr' destination register */
8330 case 'x': /* ignore register name */
8331 case 'z': /* must be zero register */
8332 case 'U': /* destination register (clo/clz). */
8347 while (ISDIGIT (*s));
8349 as_bad (_("Invalid register number (%d)"), regno);
8351 else if (*args == 'E' || *args == 'G' || *args == 'K')
8355 if (s[1] == 'r' && s[2] == 'a')
8360 else if (s[1] == 'f' && s[2] == 'p')
8365 else if (s[1] == 's' && s[2] == 'p')
8370 else if (s[1] == 'g' && s[2] == 'p')
8375 else if (s[1] == 'a' && s[2] == 't')
8380 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8385 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8390 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8395 else if (itbl_have_entries)
8400 p = s + 1; /* advance past '$' */
8401 n = itbl_get_field (&p); /* n is name */
8403 /* See if this is a register defined in an
8405 if (itbl_get_reg_val (n, &r))
8407 /* Get_field advances to the start of
8408 the next field, so we need to back
8409 rack to the end of the last field. */
8413 s = strchr (s, '\0');
8427 as_warn (_("Used $at without \".set noat\""));
8433 if (c == 'r' || c == 'v' || c == 'w')
8440 /* 'z' only matches $0. */
8441 if (c == 'z' && regno != 0)
8444 /* Now that we have assembled one operand, we use the args string
8445 * to figure out where it goes in the instruction. */
8452 ip->insn_opcode |= regno << OP_SH_RS;
8457 ip->insn_opcode |= regno << OP_SH_RD;
8460 ip->insn_opcode |= regno << OP_SH_RD;
8461 ip->insn_opcode |= regno << OP_SH_RT;
8466 ip->insn_opcode |= regno << OP_SH_RT;
8469 /* This case exists because on the r3000 trunc
8470 expands into a macro which requires a gp
8471 register. On the r6000 or r4000 it is
8472 assembled into a single instruction which
8473 ignores the register. Thus the insn version
8474 is MIPS_ISA2 and uses 'x', and the macro
8475 version is MIPS_ISA1 and uses 't'. */
8478 /* This case is for the div instruction, which
8479 acts differently if the destination argument
8480 is $0. This only matches $0, and is checked
8481 outside the switch. */
8484 /* Itbl operand; not yet implemented. FIXME ?? */
8486 /* What about all other operands like 'i', which
8487 can be specified in the opcode table? */
8497 ip->insn_opcode |= lastregno << OP_SH_RS;
8500 ip->insn_opcode |= lastregno << OP_SH_RT;
8505 case 'O': /* MDMX alignment immediate constant. */
8506 my_getExpression (&imm_expr, s);
8507 check_absolute_expr (ip, &imm_expr);
8508 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8510 as_warn ("Improper align amount (%ld), using low bits",
8511 (long) imm_expr.X_add_number);
8512 imm_expr.X_add_number &= OP_MASK_ALN;
8514 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8515 imm_expr.X_op = O_absent;
8519 case 'Q': /* MDMX vector, element sel, or const. */
8522 /* MDMX Immediate. */
8523 my_getExpression (&imm_expr, s);
8524 check_absolute_expr (ip, &imm_expr);
8525 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8527 as_warn (_("Invalid MDMX Immediate (%ld)"),
8528 (long) imm_expr.X_add_number);
8529 imm_expr.X_add_number &= OP_MASK_FT;
8531 imm_expr.X_add_number &= OP_MASK_FT;
8532 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8533 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8535 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8536 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8537 imm_expr.X_op = O_absent;
8541 /* Not MDMX Immediate. Fall through. */
8542 case 'X': /* MDMX destination register. */
8543 case 'Y': /* MDMX source register. */
8544 case 'Z': /* MDMX target register. */
8546 case 'D': /* floating point destination register */
8547 case 'S': /* floating point source register */
8548 case 'T': /* floating point target register */
8549 case 'R': /* floating point source register */
8553 /* Accept $fN for FP and MDMX register numbers, and in
8554 addition accept $vN for MDMX register numbers. */
8555 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8556 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8567 while (ISDIGIT (*s));
8570 as_bad (_("Invalid float register number (%d)"), regno);
8572 if ((regno & 1) != 0
8574 && ! (strcmp (str, "mtc1") == 0
8575 || strcmp (str, "mfc1") == 0
8576 || strcmp (str, "lwc1") == 0
8577 || strcmp (str, "swc1") == 0
8578 || strcmp (str, "l.s") == 0
8579 || strcmp (str, "s.s") == 0))
8580 as_warn (_("Float register should be even, was %d"),
8588 if (c == 'V' || c == 'W')
8599 ip->insn_opcode |= regno << OP_SH_FD;
8604 ip->insn_opcode |= regno << OP_SH_FS;
8607 /* This is like 'Z', but also needs to fix the MDMX
8608 vector/scalar select bits. Note that the
8609 scalar immediate case is handled above. */
8612 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8613 int max_el = (is_qh ? 3 : 7);
8615 my_getExpression(&imm_expr, s);
8616 check_absolute_expr (ip, &imm_expr);
8618 if (imm_expr.X_add_number > max_el)
8619 as_bad(_("Bad element selector %ld"),
8620 (long) imm_expr.X_add_number);
8621 imm_expr.X_add_number &= max_el;
8622 ip->insn_opcode |= (imm_expr.X_add_number
8625 imm_expr.X_op = O_absent;
8627 as_warn(_("Expecting ']' found '%s'"), s);
8633 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8634 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8637 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8644 ip->insn_opcode |= regno << OP_SH_FT;
8647 ip->insn_opcode |= regno << OP_SH_FR;
8657 ip->insn_opcode |= lastregno << OP_SH_FS;
8660 ip->insn_opcode |= lastregno << OP_SH_FT;
8666 my_getExpression (&imm_expr, s);
8667 if (imm_expr.X_op != O_big
8668 && imm_expr.X_op != O_constant)
8669 insn_error = _("absolute expression required");
8670 normalize_constant_expr (&imm_expr);
8675 my_getExpression (&offset_expr, s);
8676 *imm_reloc = BFD_RELOC_32;
8689 unsigned char temp[8];
8691 unsigned int length;
8696 /* These only appear as the last operand in an
8697 instruction, and every instruction that accepts
8698 them in any variant accepts them in all variants.
8699 This means we don't have to worry about backing out
8700 any changes if the instruction does not match.
8702 The difference between them is the size of the
8703 floating point constant and where it goes. For 'F'
8704 and 'L' the constant is 64 bits; for 'f' and 'l' it
8705 is 32 bits. Where the constant is placed is based
8706 on how the MIPS assembler does things:
8709 f -- immediate value
8712 The .lit4 and .lit8 sections are only used if
8713 permitted by the -G argument.
8715 The code below needs to know whether the target register
8716 is 32 or 64 bits wide. It relies on the fact 'f' and
8717 'F' are used with GPR-based instructions and 'l' and
8718 'L' are used with FPR-based instructions. */
8720 f64 = *args == 'F' || *args == 'L';
8721 using_gprs = *args == 'F' || *args == 'f';
8723 save_in = input_line_pointer;
8724 input_line_pointer = s;
8725 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8727 s = input_line_pointer;
8728 input_line_pointer = save_in;
8729 if (err != NULL && *err != '\0')
8731 as_bad (_("Bad floating point constant: %s"), err);
8732 memset (temp, '\0', sizeof temp);
8733 length = f64 ? 8 : 4;
8736 assert (length == (unsigned) (f64 ? 8 : 4));
8740 && (g_switch_value < 4
8741 || (temp[0] == 0 && temp[1] == 0)
8742 || (temp[2] == 0 && temp[3] == 0))))
8744 imm_expr.X_op = O_constant;
8745 if (! target_big_endian)
8746 imm_expr.X_add_number = bfd_getl32 (temp);
8748 imm_expr.X_add_number = bfd_getb32 (temp);
8751 && ! mips_disable_float_construction
8752 /* Constants can only be constructed in GPRs and
8753 copied to FPRs if the GPRs are at least as wide
8754 as the FPRs. Force the constant into memory if
8755 we are using 64-bit FPRs but the GPRs are only
8758 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8759 && ((temp[0] == 0 && temp[1] == 0)
8760 || (temp[2] == 0 && temp[3] == 0))
8761 && ((temp[4] == 0 && temp[5] == 0)
8762 || (temp[6] == 0 && temp[7] == 0)))
8764 /* The value is simple enough to load with a couple of
8765 instructions. If using 32-bit registers, set
8766 imm_expr to the high order 32 bits and offset_expr to
8767 the low order 32 bits. Otherwise, set imm_expr to
8768 the entire 64 bit constant. */
8769 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8771 imm_expr.X_op = O_constant;
8772 offset_expr.X_op = O_constant;
8773 if (! target_big_endian)
8775 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8776 offset_expr.X_add_number = bfd_getl32 (temp);
8780 imm_expr.X_add_number = bfd_getb32 (temp);
8781 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8783 if (offset_expr.X_add_number == 0)
8784 offset_expr.X_op = O_absent;
8786 else if (sizeof (imm_expr.X_add_number) > 4)
8788 imm_expr.X_op = O_constant;
8789 if (! target_big_endian)
8790 imm_expr.X_add_number = bfd_getl64 (temp);
8792 imm_expr.X_add_number = bfd_getb64 (temp);
8796 imm_expr.X_op = O_big;
8797 imm_expr.X_add_number = 4;
8798 if (! target_big_endian)
8800 generic_bignum[0] = bfd_getl16 (temp);
8801 generic_bignum[1] = bfd_getl16 (temp + 2);
8802 generic_bignum[2] = bfd_getl16 (temp + 4);
8803 generic_bignum[3] = bfd_getl16 (temp + 6);
8807 generic_bignum[0] = bfd_getb16 (temp + 6);
8808 generic_bignum[1] = bfd_getb16 (temp + 4);
8809 generic_bignum[2] = bfd_getb16 (temp + 2);
8810 generic_bignum[3] = bfd_getb16 (temp);
8816 const char *newname;
8819 /* Switch to the right section. */
8821 subseg = now_subseg;
8824 default: /* unused default case avoids warnings. */
8826 newname = RDATA_SECTION_NAME;
8827 if (g_switch_value >= 8)
8831 newname = RDATA_SECTION_NAME;
8834 assert (g_switch_value >= 4);
8838 new_seg = subseg_new (newname, (subsegT) 0);
8839 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8840 bfd_set_section_flags (stdoutput, new_seg,
8845 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8846 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8847 && strcmp (TARGET_OS, "elf") != 0)
8848 record_alignment (new_seg, 4);
8850 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8852 as_bad (_("Can't use floating point insn in this section"));
8854 /* Set the argument to the current address in the
8856 offset_expr.X_op = O_symbol;
8857 offset_expr.X_add_symbol =
8858 symbol_new ("L0\001", now_seg,
8859 (valueT) frag_now_fix (), frag_now);
8860 offset_expr.X_add_number = 0;
8862 /* Put the floating point number into the section. */
8863 p = frag_more ((int) length);
8864 memcpy (p, temp, length);
8866 /* Switch back to the original section. */
8867 subseg_set (seg, subseg);
8872 case 'i': /* 16 bit unsigned immediate */
8873 case 'j': /* 16 bit signed immediate */
8874 *imm_reloc = BFD_RELOC_LO16;
8875 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
8878 offsetT minval, maxval;
8880 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
8881 && strcmp (insn->name, insn[1].name) == 0);
8883 /* If the expression was written as an unsigned number,
8884 only treat it as signed if there are no more
8888 && sizeof (imm_expr.X_add_number) <= 4
8889 && imm_expr.X_op == O_constant
8890 && imm_expr.X_add_number < 0
8891 && imm_expr.X_unsigned
8895 /* For compatibility with older assemblers, we accept
8896 0x8000-0xffff as signed 16-bit numbers when only
8897 signed numbers are allowed. */
8899 minval = 0, maxval = 0xffff;
8901 minval = -0x8000, maxval = 0x7fff;
8903 minval = -0x8000, maxval = 0xffff;
8905 if (imm_expr.X_op != O_constant
8906 || imm_expr.X_add_number < minval
8907 || imm_expr.X_add_number > maxval)
8911 if (imm_expr.X_op == O_constant
8912 || imm_expr.X_op == O_big)
8913 as_bad (_("expression out of range"));
8919 case 'o': /* 16 bit offset */
8920 /* Check whether there is only a single bracketed expression
8921 left. If so, it must be the base register and the
8922 constant must be zero. */
8923 if (*s == '(' && strchr (s + 1, '(') == 0)
8925 offset_expr.X_op = O_constant;
8926 offset_expr.X_add_number = 0;
8930 /* If this value won't fit into a 16 bit offset, then go
8931 find a macro that will generate the 32 bit offset
8933 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
8934 && (offset_expr.X_op != O_constant
8935 || offset_expr.X_add_number >= 0x8000
8936 || offset_expr.X_add_number < -0x8000))
8942 case 'p': /* pc relative offset */
8943 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8944 my_getExpression (&offset_expr, s);
8948 case 'u': /* upper 16 bits */
8949 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
8950 && imm_expr.X_op == O_constant
8951 && (imm_expr.X_add_number < 0
8952 || imm_expr.X_add_number >= 0x10000))
8953 as_bad (_("lui expression not in range 0..65535"));
8957 case 'a': /* 26 bit address */
8958 my_getExpression (&offset_expr, s);
8960 *offset_reloc = BFD_RELOC_MIPS_JMP;
8963 case 'N': /* 3 bit branch condition code */
8964 case 'M': /* 3 bit compare condition code */
8965 if (strncmp (s, "$fcc", 4) != 0)
8975 while (ISDIGIT (*s));
8977 as_bad (_("Invalid condition code register $fcc%d"), regno);
8978 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
8979 || strcmp(str + strlen(str) - 5, "any2f") == 0
8980 || strcmp(str + strlen(str) - 5, "any2t") == 0)
8981 && (regno & 1) != 0)
8982 as_warn(_("Condition code register should be even for %s, was %d"),
8984 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
8985 || strcmp(str + strlen(str) - 5, "any4t") == 0)
8986 && (regno & 3) != 0)
8987 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8990 ip->insn_opcode |= regno << OP_SH_BCC;
8992 ip->insn_opcode |= regno << OP_SH_CCC;
8996 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9007 while (ISDIGIT (*s));
9010 c = 8; /* Invalid sel value. */
9013 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9014 ip->insn_opcode |= c;
9018 /* Must be at least one digit. */
9019 my_getExpression (&imm_expr, s);
9020 check_absolute_expr (ip, &imm_expr);
9022 if ((unsigned long) imm_expr.X_add_number
9023 > (unsigned long) OP_MASK_VECBYTE)
9025 as_bad (_("bad byte vector index (%ld)"),
9026 (long) imm_expr.X_add_number);
9027 imm_expr.X_add_number = 0;
9030 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9031 imm_expr.X_op = O_absent;
9036 my_getExpression (&imm_expr, s);
9037 check_absolute_expr (ip, &imm_expr);
9039 if ((unsigned long) imm_expr.X_add_number
9040 > (unsigned long) OP_MASK_VECALIGN)
9042 as_bad (_("bad byte vector index (%ld)"),
9043 (long) imm_expr.X_add_number);
9044 imm_expr.X_add_number = 0;
9047 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9048 imm_expr.X_op = O_absent;
9053 as_bad (_("bad char = '%c'\n"), *args);
9058 /* Args don't match. */
9059 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9060 !strcmp (insn->name, insn[1].name))
9064 insn_error = _("illegal operands");
9069 insn_error = _("illegal operands");
9074 /* This routine assembles an instruction into its binary format when
9075 assembling for the mips16. As a side effect, it sets one of the
9076 global variables imm_reloc or offset_reloc to the type of
9077 relocation to do if one of the operands is an address expression.
9078 It also sets mips16_small and mips16_ext if the user explicitly
9079 requested a small or extended instruction. */
9082 mips16_ip (char *str, struct mips_cl_insn *ip)
9086 struct mips_opcode *insn;
9089 unsigned int lastregno = 0;
9094 mips16_small = FALSE;
9097 for (s = str; ISLOWER (*s); ++s)
9109 if (s[1] == 't' && s[2] == ' ')
9112 mips16_small = TRUE;
9116 else if (s[1] == 'e' && s[2] == ' ')
9125 insn_error = _("unknown opcode");
9129 if (mips_opts.noautoextend && ! mips16_ext)
9130 mips16_small = TRUE;
9132 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9134 insn_error = _("unrecognized opcode");
9141 assert (strcmp (insn->name, str) == 0);
9144 ip->insn_opcode = insn->match;
9145 ip->use_extend = FALSE;
9146 imm_expr.X_op = O_absent;
9147 imm_reloc[0] = BFD_RELOC_UNUSED;
9148 imm_reloc[1] = BFD_RELOC_UNUSED;
9149 imm_reloc[2] = BFD_RELOC_UNUSED;
9150 imm2_expr.X_op = O_absent;
9151 offset_expr.X_op = O_absent;
9152 offset_reloc[0] = BFD_RELOC_UNUSED;
9153 offset_reloc[1] = BFD_RELOC_UNUSED;
9154 offset_reloc[2] = BFD_RELOC_UNUSED;
9155 for (args = insn->args; 1; ++args)
9162 /* In this switch statement we call break if we did not find
9163 a match, continue if we did find a match, or return if we
9172 /* Stuff the immediate value in now, if we can. */
9173 if (imm_expr.X_op == O_constant
9174 && *imm_reloc > BFD_RELOC_UNUSED
9175 && insn->pinfo != INSN_MACRO)
9177 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9178 imm_expr.X_add_number, TRUE, mips16_small,
9179 mips16_ext, &ip->insn_opcode,
9180 &ip->use_extend, &ip->extend);
9181 imm_expr.X_op = O_absent;
9182 *imm_reloc = BFD_RELOC_UNUSED;
9196 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9199 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9215 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9217 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9244 while (ISDIGIT (*s));
9247 as_bad (_("invalid register number (%d)"), regno);
9253 if (s[1] == 'r' && s[2] == 'a')
9258 else if (s[1] == 'f' && s[2] == 'p')
9263 else if (s[1] == 's' && s[2] == 'p')
9268 else if (s[1] == 'g' && s[2] == 'p')
9273 else if (s[1] == 'a' && s[2] == 't')
9278 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9283 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9288 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9301 if (c == 'v' || c == 'w')
9303 regno = mips16_to_32_reg_map[lastregno];
9317 regno = mips32_to_16_reg_map[regno];
9322 regno = ILLEGAL_REG;
9327 regno = ILLEGAL_REG;
9332 regno = ILLEGAL_REG;
9337 if (regno == AT && ! mips_opts.noat)
9338 as_warn (_("used $at without \".set noat\""));
9345 if (regno == ILLEGAL_REG)
9352 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9356 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9359 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9362 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9368 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9371 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9372 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9382 if (strncmp (s, "$pc", 3) == 0)
9406 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9408 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9409 and generate the appropriate reloc. If the text
9410 inside %gprel is not a symbol name with an
9411 optional offset, then we generate a normal reloc
9412 and will probably fail later. */
9413 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9414 if (imm_expr.X_op == O_symbol)
9417 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9419 ip->use_extend = TRUE;
9426 /* Just pick up a normal expression. */
9427 my_getExpression (&imm_expr, s);
9430 if (imm_expr.X_op == O_register)
9432 /* What we thought was an expression turned out to
9435 if (s[0] == '(' && args[1] == '(')
9437 /* It looks like the expression was omitted
9438 before a register indirection, which means
9439 that the expression is implicitly zero. We
9440 still set up imm_expr, so that we handle
9441 explicit extensions correctly. */
9442 imm_expr.X_op = O_constant;
9443 imm_expr.X_add_number = 0;
9444 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9451 /* We need to relax this instruction. */
9452 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9461 /* We use offset_reloc rather than imm_reloc for the PC
9462 relative operands. This lets macros with both
9463 immediate and address operands work correctly. */
9464 my_getExpression (&offset_expr, s);
9466 if (offset_expr.X_op == O_register)
9469 /* We need to relax this instruction. */
9470 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9474 case '6': /* break code */
9475 my_getExpression (&imm_expr, s);
9476 check_absolute_expr (ip, &imm_expr);
9477 if ((unsigned long) imm_expr.X_add_number > 63)
9479 as_warn (_("Invalid value for `%s' (%lu)"),
9481 (unsigned long) imm_expr.X_add_number);
9482 imm_expr.X_add_number &= 0x3f;
9484 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9485 imm_expr.X_op = O_absent;
9489 case 'a': /* 26 bit address */
9490 my_getExpression (&offset_expr, s);
9492 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9493 ip->insn_opcode <<= 16;
9496 case 'l': /* register list for entry macro */
9497 case 'L': /* register list for exit macro */
9507 int freg, reg1, reg2;
9509 while (*s == ' ' || *s == ',')
9513 as_bad (_("can't parse register list"));
9525 while (ISDIGIT (*s))
9547 as_bad (_("invalid register list"));
9552 while (ISDIGIT (*s))
9559 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9564 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9569 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9570 mask |= (reg2 - 3) << 3;
9571 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9572 mask |= (reg2 - 15) << 1;
9573 else if (reg1 == RA && reg2 == RA)
9577 as_bad (_("invalid register list"));
9581 /* The mask is filled in in the opcode table for the
9582 benefit of the disassembler. We remove it before
9583 applying the actual mask. */
9584 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9585 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9589 case 'e': /* extend code */
9590 my_getExpression (&imm_expr, s);
9591 check_absolute_expr (ip, &imm_expr);
9592 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9594 as_warn (_("Invalid value for `%s' (%lu)"),
9596 (unsigned long) imm_expr.X_add_number);
9597 imm_expr.X_add_number &= 0x7ff;
9599 ip->insn_opcode |= imm_expr.X_add_number;
9600 imm_expr.X_op = O_absent;
9610 /* Args don't match. */
9611 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9612 strcmp (insn->name, insn[1].name) == 0)
9619 insn_error = _("illegal operands");
9625 /* This structure holds information we know about a mips16 immediate
9628 struct mips16_immed_operand
9630 /* The type code used in the argument string in the opcode table. */
9632 /* The number of bits in the short form of the opcode. */
9634 /* The number of bits in the extended form of the opcode. */
9636 /* The amount by which the short form is shifted when it is used;
9637 for example, the sw instruction has a shift count of 2. */
9639 /* The amount by which the short form is shifted when it is stored
9640 into the instruction code. */
9642 /* Non-zero if the short form is unsigned. */
9644 /* Non-zero if the extended form is unsigned. */
9646 /* Non-zero if the value is PC relative. */
9650 /* The mips16 immediate operand types. */
9652 static const struct mips16_immed_operand mips16_immed_operands[] =
9654 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9655 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9656 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9657 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9658 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9659 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9660 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9661 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9662 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9663 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9664 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9665 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9666 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9667 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9668 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9669 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9670 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9671 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9672 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9673 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9674 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9677 #define MIPS16_NUM_IMMED \
9678 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9680 /* Handle a mips16 instruction with an immediate value. This or's the
9681 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9682 whether an extended value is needed; if one is needed, it sets
9683 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9684 If SMALL is true, an unextended opcode was explicitly requested.
9685 If EXT is true, an extended opcode was explicitly requested. If
9686 WARN is true, warn if EXT does not match reality. */
9689 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9690 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9691 unsigned long *insn, bfd_boolean *use_extend,
9692 unsigned short *extend)
9694 register const struct mips16_immed_operand *op;
9695 int mintiny, maxtiny;
9696 bfd_boolean needext;
9698 op = mips16_immed_operands;
9699 while (op->type != type)
9702 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9707 if (type == '<' || type == '>' || type == '[' || type == ']')
9710 maxtiny = 1 << op->nbits;
9715 maxtiny = (1 << op->nbits) - 1;
9720 mintiny = - (1 << (op->nbits - 1));
9721 maxtiny = (1 << (op->nbits - 1)) - 1;
9724 /* Branch offsets have an implicit 0 in the lowest bit. */
9725 if (type == 'p' || type == 'q')
9728 if ((val & ((1 << op->shift) - 1)) != 0
9729 || val < (mintiny << op->shift)
9730 || val > (maxtiny << op->shift))
9735 if (warn && ext && ! needext)
9736 as_warn_where (file, line,
9737 _("extended operand requested but not required"));
9738 if (small && needext)
9739 as_bad_where (file, line, _("invalid unextended operand value"));
9741 if (small || (! ext && ! needext))
9745 *use_extend = FALSE;
9746 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9747 insnval <<= op->op_shift;
9752 long minext, maxext;
9758 maxext = (1 << op->extbits) - 1;
9762 minext = - (1 << (op->extbits - 1));
9763 maxext = (1 << (op->extbits - 1)) - 1;
9765 if (val < minext || val > maxext)
9766 as_bad_where (file, line,
9767 _("operand value out of range for instruction"));
9770 if (op->extbits == 16)
9772 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9775 else if (op->extbits == 15)
9777 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9782 extval = ((val & 0x1f) << 6) | (val & 0x20);
9786 *extend = (unsigned short) extval;
9791 static const struct percent_op_match
9794 bfd_reloc_code_real_type reloc;
9797 {"%lo", BFD_RELOC_LO16},
9799 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9800 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9801 {"%call16", BFD_RELOC_MIPS_CALL16},
9802 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9803 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9804 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9805 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9806 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9807 {"%got", BFD_RELOC_MIPS_GOT16},
9808 {"%gp_rel", BFD_RELOC_GPREL16},
9809 {"%half", BFD_RELOC_16},
9810 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9811 {"%higher", BFD_RELOC_MIPS_HIGHER},
9812 {"%neg", BFD_RELOC_MIPS_SUB},
9814 {"%hi", BFD_RELOC_HI16_S}
9818 /* Return true if *STR points to a relocation operator. When returning true,
9819 move *STR over the operator and store its relocation code in *RELOC.
9820 Leave both *STR and *RELOC alone when returning false. */
9823 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9827 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9828 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9830 *str += strlen (percent_op[i].str);
9831 *reloc = percent_op[i].reloc;
9833 /* Check whether the output BFD supports this relocation.
9834 If not, issue an error and fall back on something safe. */
9835 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9837 as_bad ("relocation %s isn't supported by the current ABI",
9839 *reloc = BFD_RELOC_UNUSED;
9847 /* Parse string STR as a 16-bit relocatable operand. Store the
9848 expression in *EP and the relocations in the array starting
9849 at RELOC. Return the number of relocation operators used.
9851 On exit, EXPR_END points to the first character after the expression. */
9854 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
9857 bfd_reloc_code_real_type reversed_reloc[3];
9858 size_t reloc_index, i;
9859 int crux_depth, str_depth;
9862 /* Search for the start of the main expression, recoding relocations
9863 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9864 of the main expression and with CRUX_DEPTH containing the number
9865 of open brackets at that point. */
9872 crux_depth = str_depth;
9874 /* Skip over whitespace and brackets, keeping count of the number
9876 while (*str == ' ' || *str == '\t' || *str == '(')
9881 && reloc_index < (HAVE_NEWABI ? 3 : 1)
9882 && parse_relocation (&str, &reversed_reloc[reloc_index]));
9884 my_getExpression (ep, crux);
9887 /* Match every open bracket. */
9888 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
9893 as_bad ("unclosed '('");
9897 if (reloc_index != 0)
9899 prev_reloc_op_frag = frag_now;
9900 for (i = 0; i < reloc_index; i++)
9901 reloc[i] = reversed_reloc[reloc_index - 1 - i];
9908 my_getExpression (expressionS *ep, char *str)
9913 save_in = input_line_pointer;
9914 input_line_pointer = str;
9916 expr_end = input_line_pointer;
9917 input_line_pointer = save_in;
9919 /* If we are in mips16 mode, and this is an expression based on `.',
9920 then we bump the value of the symbol by 1 since that is how other
9921 text symbols are handled. We don't bother to handle complex
9922 expressions, just `.' plus or minus a constant. */
9923 if (mips_opts.mips16
9924 && ep->X_op == O_symbol
9925 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9926 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9927 && symbol_get_frag (ep->X_add_symbol) == frag_now
9928 && symbol_constant_p (ep->X_add_symbol)
9929 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9930 S_SET_VALUE (ep->X_add_symbol, val + 1);
9933 /* Turn a string in input_line_pointer into a floating point constant
9934 of type TYPE, and store the appropriate bytes in *LITP. The number
9935 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9936 returned, or NULL on OK. */
9939 md_atof (int type, char *litP, int *sizeP)
9942 LITTLENUM_TYPE words[4];
9958 return _("bad call to md_atof");
9961 t = atof_ieee (input_line_pointer, type, words);
9963 input_line_pointer = t;
9967 if (! target_big_endian)
9969 for (i = prec - 1; i >= 0; i--)
9971 md_number_to_chars (litP, words[i], 2);
9977 for (i = 0; i < prec; i++)
9979 md_number_to_chars (litP, words[i], 2);
9988 md_number_to_chars (char *buf, valueT val, int n)
9990 if (target_big_endian)
9991 number_to_chars_bigendian (buf, val, n);
9993 number_to_chars_littleendian (buf, val, n);
9997 static int support_64bit_objects(void)
9999 const char **list, **l;
10002 list = bfd_target_list ();
10003 for (l = list; *l != NULL; l++)
10005 /* This is traditional mips */
10006 if (strcmp (*l, "elf64-tradbigmips") == 0
10007 || strcmp (*l, "elf64-tradlittlemips") == 0)
10009 if (strcmp (*l, "elf64-bigmips") == 0
10010 || strcmp (*l, "elf64-littlemips") == 0)
10013 yes = (*l != NULL);
10017 #endif /* OBJ_ELF */
10019 const char *md_shortopts = "O::g::G:";
10021 struct option md_longopts[] =
10023 /* Options which specify architecture. */
10024 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10025 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10026 {"march", required_argument, NULL, OPTION_MARCH},
10027 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10028 {"mtune", required_argument, NULL, OPTION_MTUNE},
10029 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10030 {"mips0", no_argument, NULL, OPTION_MIPS1},
10031 {"mips1", no_argument, NULL, OPTION_MIPS1},
10032 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10033 {"mips2", no_argument, NULL, OPTION_MIPS2},
10034 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10035 {"mips3", no_argument, NULL, OPTION_MIPS3},
10036 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10037 {"mips4", no_argument, NULL, OPTION_MIPS4},
10038 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10039 {"mips5", no_argument, NULL, OPTION_MIPS5},
10040 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10041 {"mips32", no_argument, NULL, OPTION_MIPS32},
10042 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10043 {"mips64", no_argument, NULL, OPTION_MIPS64},
10044 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10045 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10046 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10047 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10049 /* Options which specify Application Specific Extensions (ASEs). */
10050 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10051 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10052 {"mips16", no_argument, NULL, OPTION_MIPS16},
10053 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10054 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10055 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10056 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10057 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10058 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10059 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10060 {"mdmx", no_argument, NULL, OPTION_MDMX},
10061 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10062 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10064 /* Old-style architecture options. Don't add more of these. */
10065 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10066 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10067 {"m4650", no_argument, NULL, OPTION_M4650},
10068 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10069 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10070 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10071 {"m4010", no_argument, NULL, OPTION_M4010},
10072 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10073 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10074 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10075 {"m4100", no_argument, NULL, OPTION_M4100},
10076 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10077 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10078 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10079 {"m3900", no_argument, NULL, OPTION_M3900},
10080 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10081 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10083 /* Options which enable bug fixes. */
10084 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10085 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10086 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10087 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10088 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10089 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10090 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10091 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10092 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10093 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10095 /* Miscellaneous options. */
10096 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10097 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10098 {"trap", no_argument, NULL, OPTION_TRAP},
10099 {"no-break", no_argument, NULL, OPTION_TRAP},
10100 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10101 {"break", no_argument, NULL, OPTION_BREAK},
10102 {"no-trap", no_argument, NULL, OPTION_BREAK},
10103 #define OPTION_EB (OPTION_MISC_BASE + 2)
10104 {"EB", no_argument, NULL, OPTION_EB},
10105 #define OPTION_EL (OPTION_MISC_BASE + 3)
10106 {"EL", no_argument, NULL, OPTION_EL},
10107 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10108 {"mfp32", no_argument, NULL, OPTION_FP32},
10109 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10110 {"mgp32", no_argument, NULL, OPTION_GP32},
10111 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10112 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10113 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10114 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10115 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10116 {"mfp64", no_argument, NULL, OPTION_FP64},
10117 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10118 {"mgp64", no_argument, NULL, OPTION_GP64},
10119 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10120 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10121 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10122 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10124 /* ELF-specific options. */
10126 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10127 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10128 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10129 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10130 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10131 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10132 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10133 {"xgot", no_argument, NULL, OPTION_XGOT},
10134 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10135 {"mabi", required_argument, NULL, OPTION_MABI},
10136 #define OPTION_32 (OPTION_ELF_BASE + 4)
10137 {"32", no_argument, NULL, OPTION_32},
10138 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10139 {"n32", no_argument, NULL, OPTION_N32},
10140 #define OPTION_64 (OPTION_ELF_BASE + 6)
10141 {"64", no_argument, NULL, OPTION_64},
10142 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10143 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10144 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10145 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10146 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10147 {"mpdr", no_argument, NULL, OPTION_PDR},
10148 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10149 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10150 #endif /* OBJ_ELF */
10152 {NULL, no_argument, NULL, 0}
10154 size_t md_longopts_size = sizeof (md_longopts);
10156 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10157 NEW_VALUE. Warn if another value was already specified. Note:
10158 we have to defer parsing the -march and -mtune arguments in order
10159 to handle 'from-abi' correctly, since the ABI might be specified
10160 in a later argument. */
10163 mips_set_option_string (const char **string_ptr, const char *new_value)
10165 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10166 as_warn (_("A different %s was already specified, is now %s"),
10167 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10170 *string_ptr = new_value;
10174 md_parse_option (int c, char *arg)
10178 case OPTION_CONSTRUCT_FLOATS:
10179 mips_disable_float_construction = 0;
10182 case OPTION_NO_CONSTRUCT_FLOATS:
10183 mips_disable_float_construction = 1;
10195 target_big_endian = 1;
10199 target_big_endian = 0;
10203 if (arg && arg[1] == '0')
10213 mips_debug = atoi (arg);
10214 /* When the MIPS assembler sees -g or -g2, it does not do
10215 optimizations which limit full symbolic debugging. We take
10216 that to be equivalent to -O0. */
10217 if (mips_debug == 2)
10222 file_mips_isa = ISA_MIPS1;
10226 file_mips_isa = ISA_MIPS2;
10230 file_mips_isa = ISA_MIPS3;
10234 file_mips_isa = ISA_MIPS4;
10238 file_mips_isa = ISA_MIPS5;
10241 case OPTION_MIPS32:
10242 file_mips_isa = ISA_MIPS32;
10245 case OPTION_MIPS32R2:
10246 file_mips_isa = ISA_MIPS32R2;
10249 case OPTION_MIPS64R2:
10250 file_mips_isa = ISA_MIPS64R2;
10253 case OPTION_MIPS64:
10254 file_mips_isa = ISA_MIPS64;
10258 mips_set_option_string (&mips_tune_string, arg);
10262 mips_set_option_string (&mips_arch_string, arg);
10266 mips_set_option_string (&mips_arch_string, "4650");
10267 mips_set_option_string (&mips_tune_string, "4650");
10270 case OPTION_NO_M4650:
10274 mips_set_option_string (&mips_arch_string, "4010");
10275 mips_set_option_string (&mips_tune_string, "4010");
10278 case OPTION_NO_M4010:
10282 mips_set_option_string (&mips_arch_string, "4100");
10283 mips_set_option_string (&mips_tune_string, "4100");
10286 case OPTION_NO_M4100:
10290 mips_set_option_string (&mips_arch_string, "3900");
10291 mips_set_option_string (&mips_tune_string, "3900");
10294 case OPTION_NO_M3900:
10298 mips_opts.ase_mdmx = 1;
10301 case OPTION_NO_MDMX:
10302 mips_opts.ase_mdmx = 0;
10305 case OPTION_MIPS16:
10306 mips_opts.mips16 = 1;
10307 mips_no_prev_insn (FALSE);
10310 case OPTION_NO_MIPS16:
10311 mips_opts.mips16 = 0;
10312 mips_no_prev_insn (FALSE);
10315 case OPTION_MIPS3D:
10316 mips_opts.ase_mips3d = 1;
10319 case OPTION_NO_MIPS3D:
10320 mips_opts.ase_mips3d = 0;
10323 case OPTION_FIX_VR4120:
10324 mips_fix_vr4120 = 1;
10327 case OPTION_NO_FIX_VR4120:
10328 mips_fix_vr4120 = 0;
10331 case OPTION_RELAX_BRANCH:
10332 mips_relax_branch = 1;
10335 case OPTION_NO_RELAX_BRANCH:
10336 mips_relax_branch = 0;
10340 /* When generating ELF code, we permit -KPIC and -call_shared to
10341 select SVR4_PIC, and -non_shared to select no PIC. This is
10342 intended to be compatible with Irix 5. */
10343 case OPTION_CALL_SHARED:
10344 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10346 as_bad (_("-call_shared is supported only for ELF format"));
10349 mips_pic = SVR4_PIC;
10350 mips_abicalls = TRUE;
10351 if (g_switch_seen && g_switch_value != 0)
10353 as_bad (_("-G may not be used with SVR4 PIC code"));
10356 g_switch_value = 0;
10359 case OPTION_NON_SHARED:
10360 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10362 as_bad (_("-non_shared is supported only for ELF format"));
10366 mips_abicalls = FALSE;
10369 /* The -xgot option tells the assembler to use 32 offsets when
10370 accessing the got in SVR4_PIC mode. It is for Irix
10375 #endif /* OBJ_ELF */
10378 if (mips_pic == SVR4_PIC)
10380 as_bad (_("-G may not be used with SVR4 PIC code"));
10384 g_switch_value = atoi (arg);
10389 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10392 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10394 as_bad (_("-32 is supported for ELF format only"));
10397 mips_abi = O32_ABI;
10401 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10403 as_bad (_("-n32 is supported for ELF format only"));
10406 mips_abi = N32_ABI;
10410 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10412 as_bad (_("-64 is supported for ELF format only"));
10415 mips_abi = N64_ABI;
10416 if (! support_64bit_objects())
10417 as_fatal (_("No compiled in support for 64 bit object file format"));
10419 #endif /* OBJ_ELF */
10422 file_mips_gp32 = 1;
10426 file_mips_gp32 = 0;
10430 file_mips_fp32 = 1;
10434 file_mips_fp32 = 0;
10439 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10441 as_bad (_("-mabi is supported for ELF format only"));
10444 if (strcmp (arg, "32") == 0)
10445 mips_abi = O32_ABI;
10446 else if (strcmp (arg, "o64") == 0)
10447 mips_abi = O64_ABI;
10448 else if (strcmp (arg, "n32") == 0)
10449 mips_abi = N32_ABI;
10450 else if (strcmp (arg, "64") == 0)
10452 mips_abi = N64_ABI;
10453 if (! support_64bit_objects())
10454 as_fatal (_("No compiled in support for 64 bit object file "
10457 else if (strcmp (arg, "eabi") == 0)
10458 mips_abi = EABI_ABI;
10461 as_fatal (_("invalid abi -mabi=%s"), arg);
10465 #endif /* OBJ_ELF */
10467 case OPTION_M7000_HILO_FIX:
10468 mips_7000_hilo_fix = TRUE;
10471 case OPTION_MNO_7000_HILO_FIX:
10472 mips_7000_hilo_fix = FALSE;
10476 case OPTION_MDEBUG:
10477 mips_flag_mdebug = TRUE;
10480 case OPTION_NO_MDEBUG:
10481 mips_flag_mdebug = FALSE;
10485 mips_flag_pdr = TRUE;
10488 case OPTION_NO_PDR:
10489 mips_flag_pdr = FALSE;
10491 #endif /* OBJ_ELF */
10500 /* Set up globals to generate code for the ISA or processor
10501 described by INFO. */
10504 mips_set_architecture (const struct mips_cpu_info *info)
10508 file_mips_arch = info->cpu;
10509 mips_opts.arch = info->cpu;
10510 mips_opts.isa = info->isa;
10515 /* Likewise for tuning. */
10518 mips_set_tune (const struct mips_cpu_info *info)
10521 mips_tune = info->cpu;
10526 mips_after_parse_args (void)
10528 const struct mips_cpu_info *arch_info = 0;
10529 const struct mips_cpu_info *tune_info = 0;
10531 /* GP relative stuff not working for PE */
10532 if (strncmp (TARGET_OS, "pe", 2) == 0
10533 && g_switch_value != 0)
10536 as_bad (_("-G not supported in this configuration."));
10537 g_switch_value = 0;
10540 if (mips_abi == NO_ABI)
10541 mips_abi = MIPS_DEFAULT_ABI;
10543 /* The following code determines the architecture and register size.
10544 Similar code was added to GCC 3.3 (see override_options() in
10545 config/mips/mips.c). The GAS and GCC code should be kept in sync
10546 as much as possible. */
10548 if (mips_arch_string != 0)
10549 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10551 if (file_mips_isa != ISA_UNKNOWN)
10553 /* Handle -mipsN. At this point, file_mips_isa contains the
10554 ISA level specified by -mipsN, while arch_info->isa contains
10555 the -march selection (if any). */
10556 if (arch_info != 0)
10558 /* -march takes precedence over -mipsN, since it is more descriptive.
10559 There's no harm in specifying both as long as the ISA levels
10561 if (file_mips_isa != arch_info->isa)
10562 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10563 mips_cpu_info_from_isa (file_mips_isa)->name,
10564 mips_cpu_info_from_isa (arch_info->isa)->name);
10567 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10570 if (arch_info == 0)
10571 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10573 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10574 as_bad ("-march=%s is not compatible with the selected ABI",
10577 mips_set_architecture (arch_info);
10579 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10580 if (mips_tune_string != 0)
10581 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10583 if (tune_info == 0)
10584 mips_set_tune (arch_info);
10586 mips_set_tune (tune_info);
10588 if (file_mips_gp32 >= 0)
10590 /* The user specified the size of the integer registers. Make sure
10591 it agrees with the ABI and ISA. */
10592 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10593 as_bad (_("-mgp64 used with a 32-bit processor"));
10594 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10595 as_bad (_("-mgp32 used with a 64-bit ABI"));
10596 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10597 as_bad (_("-mgp64 used with a 32-bit ABI"));
10601 /* Infer the integer register size from the ABI and processor.
10602 Restrict ourselves to 32-bit registers if that's all the
10603 processor has, or if the ABI cannot handle 64-bit registers. */
10604 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10605 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10608 /* ??? GAS treats single-float processors as though they had 64-bit
10609 float registers (although it complains when double-precision
10610 instructions are used). As things stand, saying they have 32-bit
10611 registers would lead to spurious "register must be even" messages.
10612 So here we assume float registers are always the same size as
10613 integer ones, unless the user says otherwise. */
10614 if (file_mips_fp32 < 0)
10615 file_mips_fp32 = file_mips_gp32;
10617 /* End of GCC-shared inference code. */
10619 /* This flag is set when we have a 64-bit capable CPU but use only
10620 32-bit wide registers. Note that EABI does not use it. */
10621 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10622 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10623 || mips_abi == O32_ABI))
10624 mips_32bitmode = 1;
10626 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10627 as_bad (_("trap exception not supported at ISA 1"));
10629 /* If the selected architecture includes support for ASEs, enable
10630 generation of code for them. */
10631 if (mips_opts.mips16 == -1)
10632 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10633 if (mips_opts.ase_mips3d == -1)
10634 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10635 if (mips_opts.ase_mdmx == -1)
10636 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10638 file_mips_isa = mips_opts.isa;
10639 file_ase_mips16 = mips_opts.mips16;
10640 file_ase_mips3d = mips_opts.ase_mips3d;
10641 file_ase_mdmx = mips_opts.ase_mdmx;
10642 mips_opts.gp32 = file_mips_gp32;
10643 mips_opts.fp32 = file_mips_fp32;
10645 if (mips_flag_mdebug < 0)
10647 #ifdef OBJ_MAYBE_ECOFF
10648 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10649 mips_flag_mdebug = 1;
10651 #endif /* OBJ_MAYBE_ECOFF */
10652 mips_flag_mdebug = 0;
10657 mips_init_after_args (void)
10659 /* initialize opcodes */
10660 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10661 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10665 md_pcrel_from (fixS *fixP)
10667 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10668 switch (fixP->fx_r_type)
10670 case BFD_RELOC_16_PCREL_S2:
10671 case BFD_RELOC_MIPS_JMP:
10672 /* Return the address of the delay slot. */
10679 /* This is called before the symbol table is processed. In order to
10680 work with gcc when using mips-tfile, we must keep all local labels.
10681 However, in other cases, we want to discard them. If we were
10682 called with -g, but we didn't see any debugging information, it may
10683 mean that gcc is smuggling debugging information through to
10684 mips-tfile, in which case we must generate all local labels. */
10687 mips_frob_file_before_adjust (void)
10689 #ifndef NO_ECOFF_DEBUGGING
10690 if (ECOFF_DEBUGGING
10692 && ! ecoff_debugging_seen)
10693 flag_keep_locals = 1;
10697 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10698 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10699 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10700 relocation operators.
10702 For our purposes, a %lo() expression matches a %got() or %hi()
10705 (a) it refers to the same symbol; and
10706 (b) the offset applied in the %lo() expression is no lower than
10707 the offset applied in the %got() or %hi().
10709 (b) allows us to cope with code like:
10712 lh $4,%lo(foo+2)($4)
10714 ...which is legal on RELA targets, and has a well-defined behaviour
10715 if the user knows that adding 2 to "foo" will not induce a carry to
10718 When several %lo()s match a particular %got() or %hi(), we use the
10719 following rules to distinguish them:
10721 (1) %lo()s with smaller offsets are a better match than %lo()s with
10724 (2) %lo()s with no matching %got() or %hi() are better than those
10725 that already have a matching %got() or %hi().
10727 (3) later %lo()s are better than earlier %lo()s.
10729 These rules are applied in order.
10731 (1) means, among other things, that %lo()s with identical offsets are
10732 chosen if they exist.
10734 (2) means that we won't associate several high-part relocations with
10735 the same low-part relocation unless there's no alternative. Having
10736 several high parts for the same low part is a GNU extension; this rule
10737 allows careful users to avoid it.
10739 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10740 with the last high-part relocation being at the front of the list.
10741 It therefore makes sense to choose the last matching low-part
10742 relocation, all other things being equal. It's also easier
10743 to code that way. */
10746 mips_frob_file (void)
10748 struct mips_hi_fixup *l;
10750 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10752 segment_info_type *seginfo;
10753 bfd_boolean matched_lo_p;
10754 fixS **hi_pos, **lo_pos, **pos;
10756 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10758 /* If a GOT16 relocation turns out to be against a global symbol,
10759 there isn't supposed to be a matching LO. */
10760 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10761 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10764 /* Check quickly whether the next fixup happens to be a matching %lo. */
10765 if (fixup_has_matching_lo_p (l->fixp))
10768 seginfo = seg_info (l->seg);
10770 /* Set HI_POS to the position of this relocation in the chain.
10771 Set LO_POS to the position of the chosen low-part relocation.
10772 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10773 relocation that matches an immediately-preceding high-part
10777 matched_lo_p = FALSE;
10778 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10780 if (*pos == l->fixp)
10783 if ((*pos)->fx_r_type == BFD_RELOC_LO16
10784 && (*pos)->fx_addsy == l->fixp->fx_addsy
10785 && (*pos)->fx_offset >= l->fixp->fx_offset
10787 || (*pos)->fx_offset < (*lo_pos)->fx_offset
10789 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
10792 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
10793 && fixup_has_matching_lo_p (*pos));
10796 /* If we found a match, remove the high-part relocation from its
10797 current position and insert it before the low-part relocation.
10798 Make the offsets match so that fixup_has_matching_lo_p()
10801 We don't warn about unmatched high-part relocations since some
10802 versions of gcc have been known to emit dead "lui ...%hi(...)"
10804 if (lo_pos != NULL)
10806 l->fixp->fx_offset = (*lo_pos)->fx_offset;
10807 if (l->fixp->fx_next != *lo_pos)
10809 *hi_pos = l->fixp->fx_next;
10810 l->fixp->fx_next = *lo_pos;
10817 /* We may have combined relocations without symbols in the N32/N64 ABI.
10818 We have to prevent gas from dropping them. */
10821 mips_force_relocation (fixS *fixp)
10823 if (generic_force_reloc (fixp))
10827 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10828 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10829 || fixp->fx_r_type == BFD_RELOC_HI16_S
10830 || fixp->fx_r_type == BFD_RELOC_LO16))
10836 /* This hook is called before a fix is simplified. We don't really
10837 decide whether to skip a fix here. Rather, we turn global symbols
10838 used as branch targets into local symbols, such that they undergo
10839 simplification. We can only do this if the symbol is defined and
10840 it is in the same section as the branch. If this doesn't hold, we
10841 emit a better error message than just saying the relocation is not
10842 valid for the selected object format.
10844 FIXP is the fix-up we're going to try to simplify, SEG is the
10845 segment in which the fix up occurs. The return value should be
10846 non-zero to indicate the fix-up is valid for further
10847 simplifications. */
10850 mips_validate_fix (struct fix *fixP, asection *seg)
10852 /* There's a lot of discussion on whether it should be possible to
10853 use R_MIPS_PC16 to represent branch relocations. The outcome
10854 seems to be that it can, but gas/bfd are very broken in creating
10855 RELA relocations for this, so for now we only accept branches to
10856 symbols in the same section. Anything else is of dubious value,
10857 since there's no guarantee that at link time the symbol would be
10858 in range. Even for branches to local symbols this is arguably
10859 wrong, since it we assume the symbol is not going to be
10860 overridden, which should be possible per ELF library semantics,
10861 but then, there isn't a dynamic relocation that could be used to
10862 this effect, and the target would likely be out of range as well.
10864 Unfortunately, it seems that there is too much code out there
10865 that relies on branches to symbols that are global to be resolved
10866 as if they were local, like the IRIX tools do, so we do it as
10867 well, but with a warning so that people are reminded to fix their
10868 code. If we ever get back to using R_MIPS_PC16 for branch
10869 targets, this entire block should go away (and probably the
10870 whole function). */
10872 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
10873 && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
10874 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
10875 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
10878 if (! S_IS_DEFINED (fixP->fx_addsy))
10880 as_bad_where (fixP->fx_file, fixP->fx_line,
10881 _("Cannot branch to undefined symbol."));
10882 /* Avoid any further errors about this fixup. */
10885 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
10887 as_bad_where (fixP->fx_file, fixP->fx_line,
10888 _("Cannot branch to symbol in another section."));
10891 else if (S_IS_EXTERNAL (fixP->fx_addsy))
10893 symbolS *sym = fixP->fx_addsy;
10895 if (mips_pic == SVR4_PIC)
10896 as_warn_where (fixP->fx_file, fixP->fx_line,
10897 _("Pretending global symbol used as branch target is local."));
10899 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
10900 S_GET_SEGMENT (sym),
10902 symbol_get_frag (sym));
10903 copy_symbol_attributes (fixP->fx_addsy, sym);
10904 S_CLEAR_EXTERNAL (fixP->fx_addsy);
10905 assert (symbol_resolved_p (sym));
10906 symbol_mark_resolved (fixP->fx_addsy);
10913 /* Apply a fixup to the object file. */
10916 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10920 reloc_howto_type *howto;
10922 /* We ignore generic BFD relocations we don't know about. */
10923 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10927 assert (fixP->fx_size == 4
10928 || fixP->fx_r_type == BFD_RELOC_16
10929 || fixP->fx_r_type == BFD_RELOC_64
10930 || fixP->fx_r_type == BFD_RELOC_CTOR
10931 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10932 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10933 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10935 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
10937 assert (! fixP->fx_pcrel);
10939 /* Don't treat parts of a composite relocation as done. There are two
10942 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10943 should nevertheless be emitted if the first part is.
10945 (2) In normal usage, composite relocations are never assembly-time
10946 constants. The easiest way of dealing with the pathological
10947 exceptions is to generate a relocation against STN_UNDEF and
10948 leave everything up to the linker. */
10949 if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0)
10952 switch (fixP->fx_r_type)
10954 case BFD_RELOC_MIPS_JMP:
10955 case BFD_RELOC_MIPS_SHIFT5:
10956 case BFD_RELOC_MIPS_SHIFT6:
10957 case BFD_RELOC_MIPS_GOT_DISP:
10958 case BFD_RELOC_MIPS_GOT_PAGE:
10959 case BFD_RELOC_MIPS_GOT_OFST:
10960 case BFD_RELOC_MIPS_SUB:
10961 case BFD_RELOC_MIPS_INSERT_A:
10962 case BFD_RELOC_MIPS_INSERT_B:
10963 case BFD_RELOC_MIPS_DELETE:
10964 case BFD_RELOC_MIPS_HIGHEST:
10965 case BFD_RELOC_MIPS_HIGHER:
10966 case BFD_RELOC_MIPS_SCN_DISP:
10967 case BFD_RELOC_MIPS_REL16:
10968 case BFD_RELOC_MIPS_RELGOT:
10969 case BFD_RELOC_MIPS_JALR:
10970 case BFD_RELOC_HI16:
10971 case BFD_RELOC_HI16_S:
10972 case BFD_RELOC_GPREL16:
10973 case BFD_RELOC_MIPS_LITERAL:
10974 case BFD_RELOC_MIPS_CALL16:
10975 case BFD_RELOC_MIPS_GOT16:
10976 case BFD_RELOC_GPREL32:
10977 case BFD_RELOC_MIPS_GOT_HI16:
10978 case BFD_RELOC_MIPS_GOT_LO16:
10979 case BFD_RELOC_MIPS_CALL_HI16:
10980 case BFD_RELOC_MIPS_CALL_LO16:
10981 case BFD_RELOC_MIPS16_GPREL:
10982 assert (! fixP->fx_pcrel);
10983 /* Nothing needed to do. The value comes from the reloc entry */
10986 case BFD_RELOC_MIPS16_JMP:
10987 /* We currently always generate a reloc against a symbol, which
10988 means that we don't want an addend even if the symbol is
10994 /* This is handled like BFD_RELOC_32, but we output a sign
10995 extended value if we are only 32 bits. */
10998 if (8 <= sizeof (valueT))
10999 md_number_to_chars (buf, *valP, 8);
11004 if ((*valP & 0x80000000) != 0)
11008 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11010 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11016 case BFD_RELOC_RVA:
11018 /* If we are deleting this reloc entry, we must fill in the
11019 value now. This can happen if we have a .word which is not
11020 resolved when it appears but is later defined. */
11022 md_number_to_chars (buf, *valP, 4);
11026 /* If we are deleting this reloc entry, we must fill in the
11029 md_number_to_chars (buf, *valP, 2);
11032 case BFD_RELOC_LO16:
11033 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11034 may be safe to remove, but if so it's not obvious. */
11035 /* When handling an embedded PIC switch statement, we can wind
11036 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11039 if (*valP + 0x8000 > 0xffff)
11040 as_bad_where (fixP->fx_file, fixP->fx_line,
11041 _("relocation overflow"));
11042 if (target_big_endian)
11044 md_number_to_chars (buf, *valP, 2);
11048 case BFD_RELOC_16_PCREL_S2:
11049 if ((*valP & 0x3) != 0)
11050 as_bad_where (fixP->fx_file, fixP->fx_line,
11051 _("Branch to odd address (%lx)"), (long) *valP);
11054 * We need to save the bits in the instruction since fixup_segment()
11055 * might be deleting the relocation entry (i.e., a branch within
11056 * the current segment).
11058 if (! fixP->fx_done)
11061 /* update old instruction data */
11062 if (target_big_endian)
11063 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11065 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11067 if (*valP + 0x20000 <= 0x3ffff)
11069 insn |= (*valP >> 2) & 0xffff;
11070 md_number_to_chars (buf, insn, 4);
11072 else if (mips_pic == NO_PIC
11074 && fixP->fx_frag->fr_address >= text_section->vma
11075 && (fixP->fx_frag->fr_address
11076 < text_section->vma + bfd_get_section_size (text_section))
11077 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11078 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11079 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11081 /* The branch offset is too large. If this is an
11082 unconditional branch, and we are not generating PIC code,
11083 we can convert it to an absolute jump instruction. */
11084 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11085 insn = 0x0c000000; /* jal */
11087 insn = 0x08000000; /* j */
11088 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11090 fixP->fx_addsy = section_symbol (text_section);
11091 *valP += md_pcrel_from (fixP);
11092 md_number_to_chars (buf, insn, 4);
11096 /* If we got here, we have branch-relaxation disabled,
11097 and there's nothing we can do to fix this instruction
11098 without turning it into a longer sequence. */
11099 as_bad_where (fixP->fx_file, fixP->fx_line,
11100 _("Branch out of range"));
11104 case BFD_RELOC_VTABLE_INHERIT:
11107 && !S_IS_DEFINED (fixP->fx_addsy)
11108 && !S_IS_WEAK (fixP->fx_addsy))
11109 S_SET_WEAK (fixP->fx_addsy);
11112 case BFD_RELOC_VTABLE_ENTRY:
11120 /* Remember value for tc_gen_reloc. */
11121 fixP->fx_addnumber = *valP;
11126 printInsn (unsigned long oc)
11128 const struct mips_opcode *p;
11129 int treg, sreg, dreg, shamt;
11134 for (i = 0; i < NUMOPCODES; ++i)
11136 p = &mips_opcodes[i];
11137 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11139 printf ("%08lx %s\t", oc, p->name);
11140 treg = (oc >> 16) & 0x1f;
11141 sreg = (oc >> 21) & 0x1f;
11142 dreg = (oc >> 11) & 0x1f;
11143 shamt = (oc >> 6) & 0x1f;
11145 for (args = p->args;; ++args)
11156 printf ("%c", *args);
11160 assert (treg == sreg);
11161 printf ("$%d,$%d", treg, sreg);
11166 printf ("$%d", dreg);
11171 printf ("$%d", treg);
11175 printf ("0x%x", treg);
11180 printf ("$%d", sreg);
11184 printf ("0x%08lx", oc & 0x1ffffff);
11191 printf ("%d", imm);
11196 printf ("$%d", shamt);
11207 printf (_("%08lx UNDEFINED\n"), oc);
11218 name = input_line_pointer;
11219 c = get_symbol_end ();
11220 p = (symbolS *) symbol_find_or_make (name);
11221 *input_line_pointer = c;
11225 /* Align the current frag to a given power of two. The MIPS assembler
11226 also automatically adjusts any preceding label. */
11229 mips_align (int to, int fill, symbolS *label)
11231 mips_emit_delays (FALSE);
11232 frag_align (to, fill, 0);
11233 record_alignment (now_seg, to);
11236 assert (S_GET_SEGMENT (label) == now_seg);
11237 symbol_set_frag (label, frag_now);
11238 S_SET_VALUE (label, (valueT) frag_now_fix ());
11242 /* Align to a given power of two. .align 0 turns off the automatic
11243 alignment used by the data creating pseudo-ops. */
11246 s_align (int x ATTRIBUTE_UNUSED)
11249 register long temp_fill;
11250 long max_alignment = 15;
11254 o Note that the assembler pulls down any immediately preceding label
11255 to the aligned address.
11256 o It's not documented but auto alignment is reinstated by
11257 a .align pseudo instruction.
11258 o Note also that after auto alignment is turned off the mips assembler
11259 issues an error on attempt to assemble an improperly aligned data item.
11264 temp = get_absolute_expression ();
11265 if (temp > max_alignment)
11266 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11269 as_warn (_("Alignment negative: 0 assumed."));
11272 if (*input_line_pointer == ',')
11274 ++input_line_pointer;
11275 temp_fill = get_absolute_expression ();
11282 mips_align (temp, (int) temp_fill,
11283 insn_labels != NULL ? insn_labels->label : NULL);
11290 demand_empty_rest_of_line ();
11294 mips_flush_pending_output (void)
11296 mips_emit_delays (FALSE);
11297 mips_clear_insn_labels ();
11301 s_change_sec (int sec)
11306 /* The ELF backend needs to know that we are changing sections, so
11307 that .previous works correctly. We could do something like check
11308 for an obj_section_change_hook macro, but that might be confusing
11309 as it would not be appropriate to use it in the section changing
11310 functions in read.c, since obj-elf.c intercepts those. FIXME:
11311 This should be cleaner, somehow. */
11312 obj_elf_section_change_hook ();
11315 mips_emit_delays (FALSE);
11325 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11326 demand_empty_rest_of_line ();
11330 seg = subseg_new (RDATA_SECTION_NAME,
11331 (subsegT) get_absolute_expression ());
11332 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11334 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11335 | SEC_READONLY | SEC_RELOC
11337 if (strcmp (TARGET_OS, "elf") != 0)
11338 record_alignment (seg, 4);
11340 demand_empty_rest_of_line ();
11344 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11345 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11347 bfd_set_section_flags (stdoutput, seg,
11348 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11349 if (strcmp (TARGET_OS, "elf") != 0)
11350 record_alignment (seg, 4);
11352 demand_empty_rest_of_line ();
11360 s_change_section (int ignore ATTRIBUTE_UNUSED)
11363 char *section_name;
11368 int section_entry_size;
11369 int section_alignment;
11371 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11374 section_name = input_line_pointer;
11375 c = get_symbol_end ();
11377 next_c = *(input_line_pointer + 1);
11379 /* Do we have .section Name<,"flags">? */
11380 if (c != ',' || (c == ',' && next_c == '"'))
11382 /* just after name is now '\0'. */
11383 *input_line_pointer = c;
11384 input_line_pointer = section_name;
11385 obj_elf_section (ignore);
11388 input_line_pointer++;
11390 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11392 section_type = get_absolute_expression ();
11395 if (*input_line_pointer++ == ',')
11396 section_flag = get_absolute_expression ();
11399 if (*input_line_pointer++ == ',')
11400 section_entry_size = get_absolute_expression ();
11402 section_entry_size = 0;
11403 if (*input_line_pointer++ == ',')
11404 section_alignment = get_absolute_expression ();
11406 section_alignment = 0;
11408 section_name = xstrdup (section_name);
11410 /* When using the generic form of .section (as implemented by obj-elf.c),
11411 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11412 traditionally had to fall back on the more common @progbits instead.
11414 There's nothing really harmful in this, since bfd will correct
11415 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11416 means that, for backwards compatibiltiy, the special_section entries
11417 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11419 Even so, we shouldn't force users of the MIPS .section syntax to
11420 incorrectly label the sections as SHT_PROGBITS. The best compromise
11421 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11422 generic type-checking code. */
11423 if (section_type == SHT_MIPS_DWARF)
11424 section_type = SHT_PROGBITS;
11426 obj_elf_change_section (section_name, section_type, section_flag,
11427 section_entry_size, 0, 0, 0);
11429 if (now_seg->name != section_name)
11430 free (section_name);
11431 #endif /* OBJ_ELF */
11435 mips_enable_auto_align (void)
11441 s_cons (int log_size)
11445 label = insn_labels != NULL ? insn_labels->label : NULL;
11446 mips_emit_delays (FALSE);
11447 if (log_size > 0 && auto_align)
11448 mips_align (log_size, 0, label);
11449 mips_clear_insn_labels ();
11450 cons (1 << log_size);
11454 s_float_cons (int type)
11458 label = insn_labels != NULL ? insn_labels->label : NULL;
11460 mips_emit_delays (FALSE);
11465 mips_align (3, 0, label);
11467 mips_align (2, 0, label);
11470 mips_clear_insn_labels ();
11475 /* Handle .globl. We need to override it because on Irix 5 you are
11478 where foo is an undefined symbol, to mean that foo should be
11479 considered to be the address of a function. */
11482 s_mips_globl (int x ATTRIBUTE_UNUSED)
11489 name = input_line_pointer;
11490 c = get_symbol_end ();
11491 symbolP = symbol_find_or_make (name);
11492 *input_line_pointer = c;
11493 SKIP_WHITESPACE ();
11495 /* On Irix 5, every global symbol that is not explicitly labelled as
11496 being a function is apparently labelled as being an object. */
11499 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11504 secname = input_line_pointer;
11505 c = get_symbol_end ();
11506 sec = bfd_get_section_by_name (stdoutput, secname);
11508 as_bad (_("%s: no such section"), secname);
11509 *input_line_pointer = c;
11511 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11512 flag = BSF_FUNCTION;
11515 symbol_get_bfdsym (symbolP)->flags |= flag;
11517 S_SET_EXTERNAL (symbolP);
11518 demand_empty_rest_of_line ();
11522 s_option (int x ATTRIBUTE_UNUSED)
11527 opt = input_line_pointer;
11528 c = get_symbol_end ();
11532 /* FIXME: What does this mean? */
11534 else if (strncmp (opt, "pic", 3) == 0)
11538 i = atoi (opt + 3);
11543 mips_pic = SVR4_PIC;
11544 mips_abicalls = TRUE;
11547 as_bad (_(".option pic%d not supported"), i);
11549 if (mips_pic == SVR4_PIC)
11551 if (g_switch_seen && g_switch_value != 0)
11552 as_warn (_("-G may not be used with SVR4 PIC code"));
11553 g_switch_value = 0;
11554 bfd_set_gp_size (stdoutput, 0);
11558 as_warn (_("Unrecognized option \"%s\""), opt);
11560 *input_line_pointer = c;
11561 demand_empty_rest_of_line ();
11564 /* This structure is used to hold a stack of .set values. */
11566 struct mips_option_stack
11568 struct mips_option_stack *next;
11569 struct mips_set_options options;
11572 static struct mips_option_stack *mips_opts_stack;
11574 /* Handle the .set pseudo-op. */
11577 s_mipsset (int x ATTRIBUTE_UNUSED)
11579 char *name = input_line_pointer, ch;
11581 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11582 ++input_line_pointer;
11583 ch = *input_line_pointer;
11584 *input_line_pointer = '\0';
11586 if (strcmp (name, "reorder") == 0)
11588 if (mips_opts.noreorder && prev_nop_frag != NULL)
11590 /* If we still have pending nops, we can discard them. The
11591 usual nop handling will insert any that are still
11593 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11594 * (mips_opts.mips16 ? 2 : 4));
11595 prev_nop_frag = NULL;
11597 mips_opts.noreorder = 0;
11599 else if (strcmp (name, "noreorder") == 0)
11601 mips_emit_delays (TRUE);
11602 mips_opts.noreorder = 1;
11603 mips_any_noreorder = 1;
11605 else if (strcmp (name, "at") == 0)
11607 mips_opts.noat = 0;
11609 else if (strcmp (name, "noat") == 0)
11611 mips_opts.noat = 1;
11613 else if (strcmp (name, "macro") == 0)
11615 mips_opts.warn_about_macros = 0;
11617 else if (strcmp (name, "nomacro") == 0)
11619 if (mips_opts.noreorder == 0)
11620 as_bad (_("`noreorder' must be set before `nomacro'"));
11621 mips_opts.warn_about_macros = 1;
11623 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11625 mips_opts.nomove = 0;
11627 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11629 mips_opts.nomove = 1;
11631 else if (strcmp (name, "bopt") == 0)
11633 mips_opts.nobopt = 0;
11635 else if (strcmp (name, "nobopt") == 0)
11637 mips_opts.nobopt = 1;
11639 else if (strcmp (name, "mips16") == 0
11640 || strcmp (name, "MIPS-16") == 0)
11641 mips_opts.mips16 = 1;
11642 else if (strcmp (name, "nomips16") == 0
11643 || strcmp (name, "noMIPS-16") == 0)
11644 mips_opts.mips16 = 0;
11645 else if (strcmp (name, "mips3d") == 0)
11646 mips_opts.ase_mips3d = 1;
11647 else if (strcmp (name, "nomips3d") == 0)
11648 mips_opts.ase_mips3d = 0;
11649 else if (strcmp (name, "mdmx") == 0)
11650 mips_opts.ase_mdmx = 1;
11651 else if (strcmp (name, "nomdmx") == 0)
11652 mips_opts.ase_mdmx = 0;
11653 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11657 /* Permit the user to change the ISA and architecture on the fly.
11658 Needless to say, misuse can cause serious problems. */
11659 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11662 mips_opts.isa = file_mips_isa;
11663 mips_opts.arch = file_mips_arch;
11665 else if (strncmp (name, "arch=", 5) == 0)
11667 const struct mips_cpu_info *p;
11669 p = mips_parse_cpu("internal use", name + 5);
11671 as_bad (_("unknown architecture %s"), name + 5);
11674 mips_opts.arch = p->cpu;
11675 mips_opts.isa = p->isa;
11678 else if (strncmp (name, "mips", 4) == 0)
11680 const struct mips_cpu_info *p;
11682 p = mips_parse_cpu("internal use", name);
11684 as_bad (_("unknown ISA level %s"), name + 4);
11687 mips_opts.arch = p->cpu;
11688 mips_opts.isa = p->isa;
11692 as_bad (_("unknown ISA or architecture %s"), name);
11694 switch (mips_opts.isa)
11702 mips_opts.gp32 = 1;
11703 mips_opts.fp32 = 1;
11710 mips_opts.gp32 = 0;
11711 mips_opts.fp32 = 0;
11714 as_bad (_("unknown ISA level %s"), name + 4);
11719 mips_opts.gp32 = file_mips_gp32;
11720 mips_opts.fp32 = file_mips_fp32;
11723 else if (strcmp (name, "autoextend") == 0)
11724 mips_opts.noautoextend = 0;
11725 else if (strcmp (name, "noautoextend") == 0)
11726 mips_opts.noautoextend = 1;
11727 else if (strcmp (name, "push") == 0)
11729 struct mips_option_stack *s;
11731 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11732 s->next = mips_opts_stack;
11733 s->options = mips_opts;
11734 mips_opts_stack = s;
11736 else if (strcmp (name, "pop") == 0)
11738 struct mips_option_stack *s;
11740 s = mips_opts_stack;
11742 as_bad (_(".set pop with no .set push"));
11745 /* If we're changing the reorder mode we need to handle
11746 delay slots correctly. */
11747 if (s->options.noreorder && ! mips_opts.noreorder)
11748 mips_emit_delays (TRUE);
11749 else if (! s->options.noreorder && mips_opts.noreorder)
11751 if (prev_nop_frag != NULL)
11753 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11754 * (mips_opts.mips16 ? 2 : 4));
11755 prev_nop_frag = NULL;
11759 mips_opts = s->options;
11760 mips_opts_stack = s->next;
11766 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11768 *input_line_pointer = ch;
11769 demand_empty_rest_of_line ();
11772 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11773 .option pic2. It means to generate SVR4 PIC calls. */
11776 s_abicalls (int ignore ATTRIBUTE_UNUSED)
11778 mips_pic = SVR4_PIC;
11779 mips_abicalls = TRUE;
11781 if (g_switch_seen && g_switch_value != 0)
11782 as_warn (_("-G may not be used with SVR4 PIC code"));
11783 g_switch_value = 0;
11785 bfd_set_gp_size (stdoutput, 0);
11786 demand_empty_rest_of_line ();
11789 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11790 PIC code. It sets the $gp register for the function based on the
11791 function address, which is in the register named in the argument.
11792 This uses a relocation against _gp_disp, which is handled specially
11793 by the linker. The result is:
11794 lui $gp,%hi(_gp_disp)
11795 addiu $gp,$gp,%lo(_gp_disp)
11796 addu $gp,$gp,.cpload argument
11797 The .cpload argument is normally $25 == $t9. */
11800 s_cpload (int ignore ATTRIBUTE_UNUSED)
11804 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11805 .cpload is ignored. */
11806 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11812 /* .cpload should be in a .set noreorder section. */
11813 if (mips_opts.noreorder == 0)
11814 as_warn (_(".cpload not in noreorder section"));
11816 ex.X_op = O_symbol;
11817 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11818 ex.X_op_symbol = NULL;
11819 ex.X_add_number = 0;
11821 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11822 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11825 macro_build_lui (&ex, mips_gp_register);
11826 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11827 mips_gp_register, BFD_RELOC_LO16);
11828 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
11829 mips_gp_register, tc_get_register (0));
11832 demand_empty_rest_of_line ();
11835 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11836 .cpsetup $reg1, offset|$reg2, label
11838 If offset is given, this results in:
11839 sd $gp, offset($sp)
11840 lui $gp, %hi(%neg(%gp_rel(label)))
11841 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11842 daddu $gp, $gp, $reg1
11844 If $reg2 is given, this results in:
11845 daddu $reg2, $gp, $0
11846 lui $gp, %hi(%neg(%gp_rel(label)))
11847 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11848 daddu $gp, $gp, $reg1
11849 $reg1 is normally $25 == $t9. */
11851 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
11853 expressionS ex_off;
11854 expressionS ex_sym;
11857 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11858 We also need NewABI support. */
11859 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11865 reg1 = tc_get_register (0);
11866 SKIP_WHITESPACE ();
11867 if (*input_line_pointer != ',')
11869 as_bad (_("missing argument separator ',' for .cpsetup"));
11873 ++input_line_pointer;
11874 SKIP_WHITESPACE ();
11875 if (*input_line_pointer == '$')
11877 mips_cpreturn_register = tc_get_register (0);
11878 mips_cpreturn_offset = -1;
11882 mips_cpreturn_offset = get_absolute_expression ();
11883 mips_cpreturn_register = -1;
11885 SKIP_WHITESPACE ();
11886 if (*input_line_pointer != ',')
11888 as_bad (_("missing argument separator ',' for .cpsetup"));
11892 ++input_line_pointer;
11893 SKIP_WHITESPACE ();
11894 expression (&ex_sym);
11897 if (mips_cpreturn_register == -1)
11899 ex_off.X_op = O_constant;
11900 ex_off.X_add_symbol = NULL;
11901 ex_off.X_op_symbol = NULL;
11902 ex_off.X_add_number = mips_cpreturn_offset;
11904 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
11905 BFD_RELOC_LO16, SP);
11908 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
11909 mips_gp_register, 0);
11911 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
11912 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, BFD_RELOC_HI16_S);
11914 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
11915 mips_gp_register, -1, BFD_RELOC_GPREL16,
11916 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
11918 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
11919 mips_gp_register, reg1);
11922 demand_empty_rest_of_line ();
11926 s_cplocal (int ignore ATTRIBUTE_UNUSED)
11928 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11929 .cplocal is ignored. */
11930 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11936 mips_gp_register = tc_get_register (0);
11937 demand_empty_rest_of_line ();
11940 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11941 offset from $sp. The offset is remembered, and after making a PIC
11942 call $gp is restored from that location. */
11945 s_cprestore (int ignore ATTRIBUTE_UNUSED)
11949 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11950 .cprestore is ignored. */
11951 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11957 mips_cprestore_offset = get_absolute_expression ();
11958 mips_cprestore_valid = 1;
11960 ex.X_op = O_constant;
11961 ex.X_add_symbol = NULL;
11962 ex.X_op_symbol = NULL;
11963 ex.X_add_number = mips_cprestore_offset;
11966 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
11967 SP, HAVE_64BIT_ADDRESSES);
11970 demand_empty_rest_of_line ();
11973 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11974 was given in the preceding .cpsetup, it results in:
11975 ld $gp, offset($sp)
11977 If a register $reg2 was given there, it results in:
11978 daddu $gp, $reg2, $0
11981 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
11985 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11986 We also need NewABI support. */
11987 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11994 if (mips_cpreturn_register == -1)
11996 ex.X_op = O_constant;
11997 ex.X_add_symbol = NULL;
11998 ex.X_op_symbol = NULL;
11999 ex.X_add_number = mips_cpreturn_offset;
12001 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12004 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12005 mips_cpreturn_register, 0);
12008 demand_empty_rest_of_line ();
12011 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12012 code. It sets the offset to use in gp_rel relocations. */
12015 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12017 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12018 We also need NewABI support. */
12019 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12025 mips_gprel_offset = get_absolute_expression ();
12027 demand_empty_rest_of_line ();
12030 /* Handle the .gpword pseudo-op. This is used when generating PIC
12031 code. It generates a 32 bit GP relative reloc. */
12034 s_gpword (int ignore ATTRIBUTE_UNUSED)
12040 /* When not generating PIC code, this is treated as .word. */
12041 if (mips_pic != SVR4_PIC)
12047 label = insn_labels != NULL ? insn_labels->label : NULL;
12048 mips_emit_delays (TRUE);
12050 mips_align (2, 0, label);
12051 mips_clear_insn_labels ();
12055 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12057 as_bad (_("Unsupported use of .gpword"));
12058 ignore_rest_of_line ();
12062 md_number_to_chars (p, 0, 4);
12063 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12064 BFD_RELOC_GPREL32);
12066 demand_empty_rest_of_line ();
12070 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12076 /* When not generating PIC code, this is treated as .dword. */
12077 if (mips_pic != SVR4_PIC)
12083 label = insn_labels != NULL ? insn_labels->label : NULL;
12084 mips_emit_delays (TRUE);
12086 mips_align (3, 0, label);
12087 mips_clear_insn_labels ();
12091 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12093 as_bad (_("Unsupported use of .gpdword"));
12094 ignore_rest_of_line ();
12098 md_number_to_chars (p, 0, 8);
12099 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12100 BFD_RELOC_GPREL32)->fx_tcbit = 1;
12102 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12103 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
12104 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
12106 demand_empty_rest_of_line ();
12109 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12110 tables in SVR4 PIC code. */
12113 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12117 /* This is ignored when not generating SVR4 PIC code. */
12118 if (mips_pic != SVR4_PIC)
12124 /* Add $gp to the register named as an argument. */
12126 reg = tc_get_register (0);
12127 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12130 demand_empty_rest_of_line ();
12133 /* Handle the .insn pseudo-op. This marks instruction labels in
12134 mips16 mode. This permits the linker to handle them specially,
12135 such as generating jalx instructions when needed. We also make
12136 them odd for the duration of the assembly, in order to generate the
12137 right sort of code. We will make them even in the adjust_symtab
12138 routine, while leaving them marked. This is convenient for the
12139 debugger and the disassembler. The linker knows to make them odd
12143 s_insn (int ignore ATTRIBUTE_UNUSED)
12145 mips16_mark_labels ();
12147 demand_empty_rest_of_line ();
12150 /* Handle a .stabn directive. We need these in order to mark a label
12151 as being a mips16 text label correctly. Sometimes the compiler
12152 will emit a label, followed by a .stabn, and then switch sections.
12153 If the label and .stabn are in mips16 mode, then the label is
12154 really a mips16 text label. */
12157 s_mips_stab (int type)
12160 mips16_mark_labels ();
12165 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12169 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12176 name = input_line_pointer;
12177 c = get_symbol_end ();
12178 symbolP = symbol_find_or_make (name);
12179 S_SET_WEAK (symbolP);
12180 *input_line_pointer = c;
12182 SKIP_WHITESPACE ();
12184 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12186 if (S_IS_DEFINED (symbolP))
12188 as_bad ("ignoring attempt to redefine symbol %s",
12189 S_GET_NAME (symbolP));
12190 ignore_rest_of_line ();
12194 if (*input_line_pointer == ',')
12196 ++input_line_pointer;
12197 SKIP_WHITESPACE ();
12201 if (exp.X_op != O_symbol)
12203 as_bad ("bad .weakext directive");
12204 ignore_rest_of_line ();
12207 symbol_set_value_expression (symbolP, &exp);
12210 demand_empty_rest_of_line ();
12213 /* Parse a register string into a number. Called from the ECOFF code
12214 to parse .frame. The argument is non-zero if this is the frame
12215 register, so that we can record it in mips_frame_reg. */
12218 tc_get_register (int frame)
12222 SKIP_WHITESPACE ();
12223 if (*input_line_pointer++ != '$')
12225 as_warn (_("expected `$'"));
12228 else if (ISDIGIT (*input_line_pointer))
12230 reg = get_absolute_expression ();
12231 if (reg < 0 || reg >= 32)
12233 as_warn (_("Bad register number"));
12239 if (strncmp (input_line_pointer, "ra", 2) == 0)
12242 input_line_pointer += 2;
12244 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12247 input_line_pointer += 2;
12249 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12252 input_line_pointer += 2;
12254 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12257 input_line_pointer += 2;
12259 else if (strncmp (input_line_pointer, "at", 2) == 0)
12262 input_line_pointer += 2;
12264 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12267 input_line_pointer += 3;
12269 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12272 input_line_pointer += 3;
12274 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12277 input_line_pointer += 4;
12281 as_warn (_("Unrecognized register name"));
12283 while (ISALNUM(*input_line_pointer))
12284 input_line_pointer++;
12289 mips_frame_reg = reg != 0 ? reg : SP;
12290 mips_frame_reg_valid = 1;
12291 mips_cprestore_valid = 0;
12297 md_section_align (asection *seg, valueT addr)
12299 int align = bfd_get_section_alignment (stdoutput, seg);
12302 /* We don't need to align ELF sections to the full alignment.
12303 However, Irix 5 may prefer that we align them at least to a 16
12304 byte boundary. We don't bother to align the sections if we are
12305 targeted for an embedded system. */
12306 if (strcmp (TARGET_OS, "elf") == 0)
12312 return ((addr + (1 << align) - 1) & (-1 << align));
12315 /* Utility routine, called from above as well. If called while the
12316 input file is still being read, it's only an approximation. (For
12317 example, a symbol may later become defined which appeared to be
12318 undefined earlier.) */
12321 nopic_need_relax (symbolS *sym, int before_relaxing)
12326 if (g_switch_value > 0)
12328 const char *symname;
12331 /* Find out whether this symbol can be referenced off the $gp
12332 register. It can be if it is smaller than the -G size or if
12333 it is in the .sdata or .sbss section. Certain symbols can
12334 not be referenced off the $gp, although it appears as though
12336 symname = S_GET_NAME (sym);
12337 if (symname != (const char *) NULL
12338 && (strcmp (symname, "eprol") == 0
12339 || strcmp (symname, "etext") == 0
12340 || strcmp (symname, "_gp") == 0
12341 || strcmp (symname, "edata") == 0
12342 || strcmp (symname, "_fbss") == 0
12343 || strcmp (symname, "_fdata") == 0
12344 || strcmp (symname, "_ftext") == 0
12345 || strcmp (symname, "end") == 0
12346 || strcmp (symname, "_gp_disp") == 0))
12348 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12350 #ifndef NO_ECOFF_DEBUGGING
12351 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12352 && (symbol_get_obj (sym)->ecoff_extern_size
12353 <= g_switch_value))
12355 /* We must defer this decision until after the whole
12356 file has been read, since there might be a .extern
12357 after the first use of this symbol. */
12358 || (before_relaxing
12359 #ifndef NO_ECOFF_DEBUGGING
12360 && symbol_get_obj (sym)->ecoff_extern_size == 0
12362 && S_GET_VALUE (sym) == 0)
12363 || (S_GET_VALUE (sym) != 0
12364 && S_GET_VALUE (sym) <= g_switch_value)))
12368 const char *segname;
12370 segname = segment_name (S_GET_SEGMENT (sym));
12371 assert (strcmp (segname, ".lit8") != 0
12372 && strcmp (segname, ".lit4") != 0);
12373 change = (strcmp (segname, ".sdata") != 0
12374 && strcmp (segname, ".sbss") != 0
12375 && strncmp (segname, ".sdata.", 7) != 0
12376 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12381 /* We are not optimizing for the $gp register. */
12386 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12389 pic_need_relax (symbolS *sym, asection *segtype)
12392 bfd_boolean linkonce;
12394 /* Handle the case of a symbol equated to another symbol. */
12395 while (symbol_equated_reloc_p (sym))
12399 /* It's possible to get a loop here in a badly written
12401 n = symbol_get_value_expression (sym)->X_add_symbol;
12407 symsec = S_GET_SEGMENT (sym);
12409 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12411 if (symsec != segtype && ! S_IS_LOCAL (sym))
12413 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12417 /* The GNU toolchain uses an extension for ELF: a section
12418 beginning with the magic string .gnu.linkonce is a linkonce
12420 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12421 sizeof ".gnu.linkonce" - 1) == 0)
12425 /* This must duplicate the test in adjust_reloc_syms. */
12426 return (symsec != &bfd_und_section
12427 && symsec != &bfd_abs_section
12428 && ! bfd_is_com_section (symsec)
12431 /* A global or weak symbol is treated as external. */
12432 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12433 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12439 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12440 extended opcode. SEC is the section the frag is in. */
12443 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12446 register const struct mips16_immed_operand *op;
12448 int mintiny, maxtiny;
12452 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12454 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12457 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12458 op = mips16_immed_operands;
12459 while (op->type != type)
12462 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12467 if (type == '<' || type == '>' || type == '[' || type == ']')
12470 maxtiny = 1 << op->nbits;
12475 maxtiny = (1 << op->nbits) - 1;
12480 mintiny = - (1 << (op->nbits - 1));
12481 maxtiny = (1 << (op->nbits - 1)) - 1;
12484 sym_frag = symbol_get_frag (fragp->fr_symbol);
12485 val = S_GET_VALUE (fragp->fr_symbol);
12486 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12492 /* We won't have the section when we are called from
12493 mips_relax_frag. However, we will always have been called
12494 from md_estimate_size_before_relax first. If this is a
12495 branch to a different section, we mark it as such. If SEC is
12496 NULL, and the frag is not marked, then it must be a branch to
12497 the same section. */
12500 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12505 /* Must have been called from md_estimate_size_before_relax. */
12508 fragp->fr_subtype =
12509 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12511 /* FIXME: We should support this, and let the linker
12512 catch branches and loads that are out of range. */
12513 as_bad_where (fragp->fr_file, fragp->fr_line,
12514 _("unsupported PC relative reference to different section"));
12518 if (fragp != sym_frag && sym_frag->fr_address == 0)
12519 /* Assume non-extended on the first relaxation pass.
12520 The address we have calculated will be bogus if this is
12521 a forward branch to another frag, as the forward frag
12522 will have fr_address == 0. */
12526 /* In this case, we know for sure that the symbol fragment is in
12527 the same section. If the relax_marker of the symbol fragment
12528 differs from the relax_marker of this fragment, we have not
12529 yet adjusted the symbol fragment fr_address. We want to add
12530 in STRETCH in order to get a better estimate of the address.
12531 This particularly matters because of the shift bits. */
12533 && sym_frag->relax_marker != fragp->relax_marker)
12537 /* Adjust stretch for any alignment frag. Note that if have
12538 been expanding the earlier code, the symbol may be
12539 defined in what appears to be an earlier frag. FIXME:
12540 This doesn't handle the fr_subtype field, which specifies
12541 a maximum number of bytes to skip when doing an
12543 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12545 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12548 stretch = - ((- stretch)
12549 & ~ ((1 << (int) f->fr_offset) - 1));
12551 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12560 addr = fragp->fr_address + fragp->fr_fix;
12562 /* The base address rules are complicated. The base address of
12563 a branch is the following instruction. The base address of a
12564 PC relative load or add is the instruction itself, but if it
12565 is in a delay slot (in which case it can not be extended) use
12566 the address of the instruction whose delay slot it is in. */
12567 if (type == 'p' || type == 'q')
12571 /* If we are currently assuming that this frag should be
12572 extended, then, the current address is two bytes
12574 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12577 /* Ignore the low bit in the target, since it will be set
12578 for a text label. */
12579 if ((val & 1) != 0)
12582 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12584 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12587 val -= addr & ~ ((1 << op->shift) - 1);
12589 /* Branch offsets have an implicit 0 in the lowest bit. */
12590 if (type == 'p' || type == 'q')
12593 /* If any of the shifted bits are set, we must use an extended
12594 opcode. If the address depends on the size of this
12595 instruction, this can lead to a loop, so we arrange to always
12596 use an extended opcode. We only check this when we are in
12597 the main relaxation loop, when SEC is NULL. */
12598 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12600 fragp->fr_subtype =
12601 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12605 /* If we are about to mark a frag as extended because the value
12606 is precisely maxtiny + 1, then there is a chance of an
12607 infinite loop as in the following code:
12612 In this case when the la is extended, foo is 0x3fc bytes
12613 away, so the la can be shrunk, but then foo is 0x400 away, so
12614 the la must be extended. To avoid this loop, we mark the
12615 frag as extended if it was small, and is about to become
12616 extended with a value of maxtiny + 1. */
12617 if (val == ((maxtiny + 1) << op->shift)
12618 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12621 fragp->fr_subtype =
12622 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12626 else if (symsec != absolute_section && sec != NULL)
12627 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12629 if ((val & ((1 << op->shift) - 1)) != 0
12630 || val < (mintiny << op->shift)
12631 || val > (maxtiny << op->shift))
12637 /* Compute the length of a branch sequence, and adjust the
12638 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12639 worst-case length is computed, with UPDATE being used to indicate
12640 whether an unconditional (-1), branch-likely (+1) or regular (0)
12641 branch is to be computed. */
12643 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12645 bfd_boolean toofar;
12649 && S_IS_DEFINED (fragp->fr_symbol)
12650 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12655 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12657 addr = fragp->fr_address + fragp->fr_fix + 4;
12661 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12664 /* If the symbol is not defined or it's in a different segment,
12665 assume the user knows what's going on and emit a short
12671 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12673 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12674 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12675 RELAX_BRANCH_LINK (fragp->fr_subtype),
12681 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12684 if (mips_pic != NO_PIC)
12686 /* Additional space for PIC loading of target address. */
12688 if (mips_opts.isa == ISA_MIPS1)
12689 /* Additional space for $at-stabilizing nop. */
12693 /* If branch is conditional. */
12694 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12701 /* Estimate the size of a frag before relaxing. Unless this is the
12702 mips16, we are not really relaxing here, and the final size is
12703 encoded in the subtype information. For the mips16, we have to
12704 decide whether we are using an extended opcode or not. */
12707 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12711 if (RELAX_BRANCH_P (fragp->fr_subtype))
12714 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12716 return fragp->fr_var;
12719 if (RELAX_MIPS16_P (fragp->fr_subtype))
12720 /* We don't want to modify the EXTENDED bit here; it might get us
12721 into infinite loops. We change it only in mips_relax_frag(). */
12722 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12724 if (mips_pic == NO_PIC)
12725 change = nopic_need_relax (fragp->fr_symbol, 0);
12726 else if (mips_pic == SVR4_PIC)
12727 change = pic_need_relax (fragp->fr_symbol, segtype);
12733 fragp->fr_subtype |= RELAX_USE_SECOND;
12734 return -RELAX_FIRST (fragp->fr_subtype);
12737 return -RELAX_SECOND (fragp->fr_subtype);
12740 /* This is called to see whether a reloc against a defined symbol
12741 should be converted into a reloc against a section. */
12744 mips_fix_adjustable (fixS *fixp)
12746 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12747 about the format of the offset in the .o file. */
12748 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12751 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12752 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12755 if (fixp->fx_addsy == NULL)
12758 /* If symbol SYM is in a mergeable section, relocations of the form
12759 SYM + 0 can usually be made section-relative. The mergeable data
12760 is then identified by the section offset rather than by the symbol.
12762 However, if we're generating REL LO16 relocations, the offset is split
12763 between the LO16 and parterning high part relocation. The linker will
12764 need to recalculate the complete offset in order to correctly identify
12767 The linker has traditionally not looked for the parterning high part
12768 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12769 placed anywhere. Rather than break backwards compatibility by changing
12770 this, it seems better not to force the issue, and instead keep the
12771 original symbol. This will work with either linker behavior. */
12772 if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
12773 && HAVE_IN_PLACE_ADDENDS
12774 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
12778 /* Don't adjust relocations against mips16 symbols, so that the linker
12779 can find them if it needs to set up a stub. */
12780 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12781 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12782 && fixp->fx_subsy == NULL)
12789 /* Translate internal representation of relocation info to BFD target
12793 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12795 static arelent *retval[4];
12797 bfd_reloc_code_real_type code;
12799 memset (retval, 0, sizeof(retval));
12800 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
12801 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12802 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12803 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12805 assert (! fixp->fx_pcrel);
12806 reloc->addend = fixp->fx_addnumber;
12808 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12809 entry to be used in the relocation's section offset. */
12810 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12812 reloc->address = reloc->addend;
12816 code = fixp->fx_r_type;
12818 /* To support a PC relative reloc, we used a Cygnus extension.
12819 We check for that here to make sure that we don't let such a
12820 reloc escape normally. (FIXME: This was formerly used by
12821 embedded-PIC support, but is now used by branch handling in
12822 general. That probably should be fixed.) */
12823 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12824 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12825 && code == BFD_RELOC_16_PCREL_S2)
12826 reloc->howto = NULL;
12828 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12830 if (reloc->howto == NULL)
12832 as_bad_where (fixp->fx_file, fixp->fx_line,
12833 _("Can not represent %s relocation in this object file format"),
12834 bfd_get_reloc_code_name (code));
12841 /* Relax a machine dependent frag. This returns the amount by which
12842 the current size of the frag should change. */
12845 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
12847 if (RELAX_BRANCH_P (fragp->fr_subtype))
12849 offsetT old_var = fragp->fr_var;
12851 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
12853 return fragp->fr_var - old_var;
12856 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12859 if (mips16_extended_frag (fragp, NULL, stretch))
12861 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12863 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12868 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12870 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12877 /* Convert a machine dependent frag. */
12880 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
12882 if (RELAX_BRANCH_P (fragp->fr_subtype))
12885 unsigned long insn;
12889 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
12891 if (target_big_endian)
12892 insn = bfd_getb32 (buf);
12894 insn = bfd_getl32 (buf);
12896 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12898 /* We generate a fixup instead of applying it right now
12899 because, if there are linker relaxations, we're going to
12900 need the relocations. */
12901 exp.X_op = O_symbol;
12902 exp.X_add_symbol = fragp->fr_symbol;
12903 exp.X_add_number = fragp->fr_offset;
12905 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
12907 BFD_RELOC_16_PCREL_S2);
12908 fixp->fx_file = fragp->fr_file;
12909 fixp->fx_line = fragp->fr_line;
12911 md_number_to_chars (buf, insn, 4);
12918 as_warn_where (fragp->fr_file, fragp->fr_line,
12919 _("relaxed out-of-range branch into a jump"));
12921 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
12924 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12926 /* Reverse the branch. */
12927 switch ((insn >> 28) & 0xf)
12930 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12931 have the condition reversed by tweaking a single
12932 bit, and their opcodes all have 0x4???????. */
12933 assert ((insn & 0xf1000000) == 0x41000000);
12934 insn ^= 0x00010000;
12938 /* bltz 0x04000000 bgez 0x04010000
12939 bltzal 0x04100000 bgezal 0x04110000 */
12940 assert ((insn & 0xfc0e0000) == 0x04000000);
12941 insn ^= 0x00010000;
12945 /* beq 0x10000000 bne 0x14000000
12946 blez 0x18000000 bgtz 0x1c000000 */
12947 insn ^= 0x04000000;
12955 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
12957 /* Clear the and-link bit. */
12958 assert ((insn & 0xfc1c0000) == 0x04100000);
12960 /* bltzal 0x04100000 bgezal 0x04110000
12961 bltzall 0x04120000 bgezall 0x04130000 */
12962 insn &= ~0x00100000;
12965 /* Branch over the branch (if the branch was likely) or the
12966 full jump (not likely case). Compute the offset from the
12967 current instruction to branch to. */
12968 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12972 /* How many bytes in instructions we've already emitted? */
12973 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12974 /* How many bytes in instructions from here to the end? */
12975 i = fragp->fr_var - i;
12977 /* Convert to instruction count. */
12979 /* Branch counts from the next instruction. */
12982 /* Branch over the jump. */
12983 md_number_to_chars (buf, insn, 4);
12987 md_number_to_chars (buf, 0, 4);
12990 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12992 /* beql $0, $0, 2f */
12994 /* Compute the PC offset from the current instruction to
12995 the end of the variable frag. */
12996 /* How many bytes in instructions we've already emitted? */
12997 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12998 /* How many bytes in instructions from here to the end? */
12999 i = fragp->fr_var - i;
13000 /* Convert to instruction count. */
13002 /* Don't decrement i, because we want to branch over the
13006 md_number_to_chars (buf, insn, 4);
13009 md_number_to_chars (buf, 0, 4);
13014 if (mips_pic == NO_PIC)
13017 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13018 ? 0x0c000000 : 0x08000000);
13019 exp.X_op = O_symbol;
13020 exp.X_add_symbol = fragp->fr_symbol;
13021 exp.X_add_number = fragp->fr_offset;
13023 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13024 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13025 fixp->fx_file = fragp->fr_file;
13026 fixp->fx_line = fragp->fr_line;
13028 md_number_to_chars (buf, insn, 4);
13033 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13034 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13035 exp.X_op = O_symbol;
13036 exp.X_add_symbol = fragp->fr_symbol;
13037 exp.X_add_number = fragp->fr_offset;
13039 if (fragp->fr_offset)
13041 exp.X_add_symbol = make_expr_symbol (&exp);
13042 exp.X_add_number = 0;
13045 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13046 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13047 fixp->fx_file = fragp->fr_file;
13048 fixp->fx_line = fragp->fr_line;
13050 md_number_to_chars (buf, insn, 4);
13053 if (mips_opts.isa == ISA_MIPS1)
13056 md_number_to_chars (buf, 0, 4);
13060 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13061 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13063 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13064 4, &exp, 0, BFD_RELOC_LO16);
13065 fixp->fx_file = fragp->fr_file;
13066 fixp->fx_line = fragp->fr_line;
13068 md_number_to_chars (buf, insn, 4);
13072 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13077 md_number_to_chars (buf, insn, 4);
13082 assert (buf == (bfd_byte *)fragp->fr_literal
13083 + fragp->fr_fix + fragp->fr_var);
13085 fragp->fr_fix += fragp->fr_var;
13090 if (RELAX_MIPS16_P (fragp->fr_subtype))
13093 register const struct mips16_immed_operand *op;
13094 bfd_boolean small, ext;
13097 unsigned long insn;
13098 bfd_boolean use_extend;
13099 unsigned short extend;
13101 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13102 op = mips16_immed_operands;
13103 while (op->type != type)
13106 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13117 resolve_symbol_value (fragp->fr_symbol);
13118 val = S_GET_VALUE (fragp->fr_symbol);
13123 addr = fragp->fr_address + fragp->fr_fix;
13125 /* The rules for the base address of a PC relative reloc are
13126 complicated; see mips16_extended_frag. */
13127 if (type == 'p' || type == 'q')
13132 /* Ignore the low bit in the target, since it will be
13133 set for a text label. */
13134 if ((val & 1) != 0)
13137 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13139 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13142 addr &= ~ (addressT) ((1 << op->shift) - 1);
13145 /* Make sure the section winds up with the alignment we have
13148 record_alignment (asec, op->shift);
13152 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13153 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13154 as_warn_where (fragp->fr_file, fragp->fr_line,
13155 _("extended instruction in delay slot"));
13157 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13159 if (target_big_endian)
13160 insn = bfd_getb16 (buf);
13162 insn = bfd_getl16 (buf);
13164 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13165 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13166 small, ext, &insn, &use_extend, &extend);
13170 md_number_to_chars (buf, 0xf000 | extend, 2);
13171 fragp->fr_fix += 2;
13175 md_number_to_chars (buf, insn, 2);
13176 fragp->fr_fix += 2;
13184 first = RELAX_FIRST (fragp->fr_subtype);
13185 second = RELAX_SECOND (fragp->fr_subtype);
13186 fixp = (fixS *) fragp->fr_opcode;
13188 /* Possibly emit a warning if we've chosen the longer option. */
13189 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13190 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13192 const char *msg = macro_warning (fragp->fr_subtype);
13194 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13197 /* Go through all the fixups for the first sequence. Disable them
13198 (by marking them as done) if we're going to use the second
13199 sequence instead. */
13201 && fixp->fx_frag == fragp
13202 && fixp->fx_where < fragp->fr_fix - second)
13204 if (fragp->fr_subtype & RELAX_USE_SECOND)
13206 fixp = fixp->fx_next;
13209 /* Go through the fixups for the second sequence. Disable them if
13210 we're going to use the first sequence, otherwise adjust their
13211 addresses to account for the relaxation. */
13212 while (fixp && fixp->fx_frag == fragp)
13214 if (fragp->fr_subtype & RELAX_USE_SECOND)
13215 fixp->fx_where -= first;
13218 fixp = fixp->fx_next;
13221 /* Now modify the frag contents. */
13222 if (fragp->fr_subtype & RELAX_USE_SECOND)
13226 start = fragp->fr_literal + fragp->fr_fix - first - second;
13227 memmove (start, start + first, second);
13228 fragp->fr_fix -= first;
13231 fragp->fr_fix -= second;
13237 /* This function is called after the relocs have been generated.
13238 We've been storing mips16 text labels as odd. Here we convert them
13239 back to even for the convenience of the debugger. */
13242 mips_frob_file_after_relocs (void)
13245 unsigned int count, i;
13247 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13250 syms = bfd_get_outsymbols (stdoutput);
13251 count = bfd_get_symcount (stdoutput);
13252 for (i = 0; i < count; i++, syms++)
13254 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13255 && ((*syms)->value & 1) != 0)
13257 (*syms)->value &= ~1;
13258 /* If the symbol has an odd size, it was probably computed
13259 incorrectly, so adjust that as well. */
13260 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13261 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13268 /* This function is called whenever a label is defined. It is used
13269 when handling branch delays; if a branch has a label, we assume we
13270 can not move it. */
13273 mips_define_label (symbolS *sym)
13275 struct insn_label_list *l;
13277 if (free_insn_labels == NULL)
13278 l = (struct insn_label_list *) xmalloc (sizeof *l);
13281 l = free_insn_labels;
13282 free_insn_labels = l->next;
13286 l->next = insn_labels;
13290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13292 /* Some special processing for a MIPS ELF file. */
13295 mips_elf_final_processing (void)
13297 /* Write out the register information. */
13298 if (mips_abi != N64_ABI)
13302 s.ri_gprmask = mips_gprmask;
13303 s.ri_cprmask[0] = mips_cprmask[0];
13304 s.ri_cprmask[1] = mips_cprmask[1];
13305 s.ri_cprmask[2] = mips_cprmask[2];
13306 s.ri_cprmask[3] = mips_cprmask[3];
13307 /* The gp_value field is set by the MIPS ELF backend. */
13309 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13310 ((Elf32_External_RegInfo *)
13311 mips_regmask_frag));
13315 Elf64_Internal_RegInfo s;
13317 s.ri_gprmask = mips_gprmask;
13319 s.ri_cprmask[0] = mips_cprmask[0];
13320 s.ri_cprmask[1] = mips_cprmask[1];
13321 s.ri_cprmask[2] = mips_cprmask[2];
13322 s.ri_cprmask[3] = mips_cprmask[3];
13323 /* The gp_value field is set by the MIPS ELF backend. */
13325 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13326 ((Elf64_External_RegInfo *)
13327 mips_regmask_frag));
13330 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13331 sort of BFD interface for this. */
13332 if (mips_any_noreorder)
13333 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13334 if (mips_pic != NO_PIC)
13336 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13337 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13340 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13342 /* Set MIPS ELF flags for ASEs. */
13343 if (file_ase_mips16)
13344 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13345 #if 0 /* XXX FIXME */
13346 if (file_ase_mips3d)
13347 elf_elfheader (stdoutput)->e_flags |= ???;
13350 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13352 /* Set the MIPS ELF ABI flags. */
13353 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13354 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13355 else if (mips_abi == O64_ABI)
13356 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13357 else if (mips_abi == EABI_ABI)
13359 if (!file_mips_gp32)
13360 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13362 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13364 else if (mips_abi == N32_ABI)
13365 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13367 /* Nothing to do for N64_ABI. */
13369 if (mips_32bitmode)
13370 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13373 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13375 typedef struct proc {
13377 unsigned long reg_mask;
13378 unsigned long reg_offset;
13379 unsigned long fpreg_mask;
13380 unsigned long fpreg_offset;
13381 unsigned long frame_offset;
13382 unsigned long frame_reg;
13383 unsigned long pc_reg;
13386 static procS cur_proc;
13387 static procS *cur_proc_ptr;
13388 static int numprocs;
13390 /* Fill in an rs_align_code fragment. */
13393 mips_handle_align (fragS *fragp)
13395 if (fragp->fr_type != rs_align_code)
13398 if (mips_opts.mips16)
13400 static const unsigned char be_nop[] = { 0x65, 0x00 };
13401 static const unsigned char le_nop[] = { 0x00, 0x65 };
13406 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13407 p = fragp->fr_literal + fragp->fr_fix;
13415 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13419 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13423 md_obj_begin (void)
13430 /* check for premature end, nesting errors, etc */
13432 as_warn (_("missing .end at end of assembly"));
13441 if (*input_line_pointer == '-')
13443 ++input_line_pointer;
13446 if (!ISDIGIT (*input_line_pointer))
13447 as_bad (_("expected simple number"));
13448 if (input_line_pointer[0] == '0')
13450 if (input_line_pointer[1] == 'x')
13452 input_line_pointer += 2;
13453 while (ISXDIGIT (*input_line_pointer))
13456 val |= hex_value (*input_line_pointer++);
13458 return negative ? -val : val;
13462 ++input_line_pointer;
13463 while (ISDIGIT (*input_line_pointer))
13466 val |= *input_line_pointer++ - '0';
13468 return negative ? -val : val;
13471 if (!ISDIGIT (*input_line_pointer))
13473 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13474 *input_line_pointer, *input_line_pointer);
13475 as_warn (_("invalid number"));
13478 while (ISDIGIT (*input_line_pointer))
13481 val += *input_line_pointer++ - '0';
13483 return negative ? -val : val;
13486 /* The .file directive; just like the usual .file directive, but there
13487 is an initial number which is the ECOFF file index. In the non-ECOFF
13488 case .file implies DWARF-2. */
13491 s_mips_file (int x ATTRIBUTE_UNUSED)
13493 static int first_file_directive = 0;
13495 if (ECOFF_DEBUGGING)
13504 filename = dwarf2_directive_file (0);
13506 /* Versions of GCC up to 3.1 start files with a ".file"
13507 directive even for stabs output. Make sure that this
13508 ".file" is handled. Note that you need a version of GCC
13509 after 3.1 in order to support DWARF-2 on MIPS. */
13510 if (filename != NULL && ! first_file_directive)
13512 (void) new_logical_line (filename, -1);
13513 s_app_file_string (filename, 0);
13515 first_file_directive = 1;
13519 /* The .loc directive, implying DWARF-2. */
13522 s_mips_loc (int x ATTRIBUTE_UNUSED)
13524 if (!ECOFF_DEBUGGING)
13525 dwarf2_directive_loc (0);
13528 /* The .end directive. */
13531 s_mips_end (int x ATTRIBUTE_UNUSED)
13535 /* Following functions need their own .frame and .cprestore directives. */
13536 mips_frame_reg_valid = 0;
13537 mips_cprestore_valid = 0;
13539 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13542 demand_empty_rest_of_line ();
13547 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13548 as_warn (_(".end not in text section"));
13552 as_warn (_(".end directive without a preceding .ent directive."));
13553 demand_empty_rest_of_line ();
13559 assert (S_GET_NAME (p));
13560 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13561 as_warn (_(".end symbol does not match .ent symbol."));
13563 if (debug_type == DEBUG_STABS)
13564 stabs_generate_asm_endfunc (S_GET_NAME (p),
13568 as_warn (_(".end directive missing or unknown symbol"));
13571 /* Generate a .pdr section. */
13572 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13575 segT saved_seg = now_seg;
13576 subsegT saved_subseg = now_subseg;
13581 dot = frag_now_fix ();
13583 #ifdef md_flush_pending_output
13584 md_flush_pending_output ();
13588 subseg_set (pdr_seg, 0);
13590 /* Write the symbol. */
13591 exp.X_op = O_symbol;
13592 exp.X_add_symbol = p;
13593 exp.X_add_number = 0;
13594 emit_expr (&exp, 4);
13596 fragp = frag_more (7 * 4);
13598 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13599 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13600 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13601 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13602 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13603 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13604 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13606 subseg_set (saved_seg, saved_subseg);
13608 #endif /* OBJ_ELF */
13610 cur_proc_ptr = NULL;
13613 /* The .aent and .ent directives. */
13616 s_mips_ent (int aent)
13620 symbolP = get_symbol ();
13621 if (*input_line_pointer == ',')
13622 ++input_line_pointer;
13623 SKIP_WHITESPACE ();
13624 if (ISDIGIT (*input_line_pointer)
13625 || *input_line_pointer == '-')
13628 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13629 as_warn (_(".ent or .aent not in text section."));
13631 if (!aent && cur_proc_ptr)
13632 as_warn (_("missing .end"));
13636 /* This function needs its own .frame and .cprestore directives. */
13637 mips_frame_reg_valid = 0;
13638 mips_cprestore_valid = 0;
13640 cur_proc_ptr = &cur_proc;
13641 memset (cur_proc_ptr, '\0', sizeof (procS));
13643 cur_proc_ptr->isym = symbolP;
13645 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13649 if (debug_type == DEBUG_STABS)
13650 stabs_generate_asm_func (S_GET_NAME (symbolP),
13651 S_GET_NAME (symbolP));
13654 demand_empty_rest_of_line ();
13657 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13658 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13659 s_mips_frame is used so that we can set the PDR information correctly.
13660 We can't use the ecoff routines because they make reference to the ecoff
13661 symbol table (in the mdebug section). */
13664 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13667 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13671 if (cur_proc_ptr == (procS *) NULL)
13673 as_warn (_(".frame outside of .ent"));
13674 demand_empty_rest_of_line ();
13678 cur_proc_ptr->frame_reg = tc_get_register (1);
13680 SKIP_WHITESPACE ();
13681 if (*input_line_pointer++ != ','
13682 || get_absolute_expression_and_terminator (&val) != ',')
13684 as_warn (_("Bad .frame directive"));
13685 --input_line_pointer;
13686 demand_empty_rest_of_line ();
13690 cur_proc_ptr->frame_offset = val;
13691 cur_proc_ptr->pc_reg = tc_get_register (0);
13693 demand_empty_rest_of_line ();
13696 #endif /* OBJ_ELF */
13700 /* The .fmask and .mask directives. If the mdebug section is present
13701 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13702 embedded targets, s_mips_mask is used so that we can set the PDR
13703 information correctly. We can't use the ecoff routines because they
13704 make reference to the ecoff symbol table (in the mdebug section). */
13707 s_mips_mask (int reg_type)
13710 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13714 if (cur_proc_ptr == (procS *) NULL)
13716 as_warn (_(".mask/.fmask outside of .ent"));
13717 demand_empty_rest_of_line ();
13721 if (get_absolute_expression_and_terminator (&mask) != ',')
13723 as_warn (_("Bad .mask/.fmask directive"));
13724 --input_line_pointer;
13725 demand_empty_rest_of_line ();
13729 off = get_absolute_expression ();
13731 if (reg_type == 'F')
13733 cur_proc_ptr->fpreg_mask = mask;
13734 cur_proc_ptr->fpreg_offset = off;
13738 cur_proc_ptr->reg_mask = mask;
13739 cur_proc_ptr->reg_offset = off;
13742 demand_empty_rest_of_line ();
13745 #endif /* OBJ_ELF */
13746 s_ignore (reg_type);
13749 /* The .loc directive. */
13759 assert (now_seg == text_section);
13761 lineno = get_number ();
13762 addroff = frag_now_fix ();
13764 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13765 S_SET_TYPE (symbolP, N_SLINE);
13766 S_SET_OTHER (symbolP, 0);
13767 S_SET_DESC (symbolP, lineno);
13768 symbolP->sy_segment = now_seg;
13772 /* A table describing all the processors gas knows about. Names are
13773 matched in the order listed.
13775 To ease comparison, please keep this table in the same order as
13776 gcc's mips_cpu_info_table[]. */
13777 static const struct mips_cpu_info mips_cpu_info_table[] =
13779 /* Entries for generic ISAs */
13780 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13781 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13782 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13783 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13784 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13785 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13786 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
13787 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13788 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
13791 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13792 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13793 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13796 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13799 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13800 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13801 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13802 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13803 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
13804 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
13805 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
13806 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13807 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13808 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13809 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13810 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13813 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13814 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13815 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13816 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13817 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
13818 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
13819 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13820 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13821 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13822 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13823 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13824 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
13825 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
13828 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
13829 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13830 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13833 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13834 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13836 /* Broadcom SB-1 CPU core */
13837 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13844 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13845 with a final "000" replaced by "k". Ignore case.
13847 Note: this function is shared between GCC and GAS. */
13850 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13852 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13853 given++, canonical++;
13855 return ((*given == 0 && *canonical == 0)
13856 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13860 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13861 CPU name. We've traditionally allowed a lot of variation here.
13863 Note: this function is shared between GCC and GAS. */
13866 mips_matching_cpu_name_p (const char *canonical, const char *given)
13868 /* First see if the name matches exactly, or with a final "000"
13869 turned into "k". */
13870 if (mips_strict_matching_cpu_name_p (canonical, given))
13873 /* If not, try comparing based on numerical designation alone.
13874 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13875 if (TOLOWER (*given) == 'r')
13877 if (!ISDIGIT (*given))
13880 /* Skip over some well-known prefixes in the canonical name,
13881 hoping to find a number there too. */
13882 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13884 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13886 else if (TOLOWER (canonical[0]) == 'r')
13889 return mips_strict_matching_cpu_name_p (canonical, given);
13893 /* Parse an option that takes the name of a processor as its argument.
13894 OPTION is the name of the option and CPU_STRING is the argument.
13895 Return the corresponding processor enumeration if the CPU_STRING is
13896 recognized, otherwise report an error and return null.
13898 A similar function exists in GCC. */
13900 static const struct mips_cpu_info *
13901 mips_parse_cpu (const char *option, const char *cpu_string)
13903 const struct mips_cpu_info *p;
13905 /* 'from-abi' selects the most compatible architecture for the given
13906 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13907 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13908 version. Look first at the -mgp options, if given, otherwise base
13909 the choice on MIPS_DEFAULT_64BIT.
13911 Treat NO_ABI like the EABIs. One reason to do this is that the
13912 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13913 architecture. This code picks MIPS I for 'mips' and MIPS III for
13914 'mips64', just as we did in the days before 'from-abi'. */
13915 if (strcasecmp (cpu_string, "from-abi") == 0)
13917 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13918 return mips_cpu_info_from_isa (ISA_MIPS1);
13920 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13921 return mips_cpu_info_from_isa (ISA_MIPS3);
13923 if (file_mips_gp32 >= 0)
13924 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13926 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13931 /* 'default' has traditionally been a no-op. Probably not very useful. */
13932 if (strcasecmp (cpu_string, "default") == 0)
13935 for (p = mips_cpu_info_table; p->name != 0; p++)
13936 if (mips_matching_cpu_name_p (p->name, cpu_string))
13939 as_bad ("Bad value (%s) for %s", cpu_string, option);
13943 /* Return the canonical processor information for ISA (a member of the
13944 ISA_MIPS* enumeration). */
13946 static const struct mips_cpu_info *
13947 mips_cpu_info_from_isa (int isa)
13951 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13952 if (mips_cpu_info_table[i].is_isa
13953 && isa == mips_cpu_info_table[i].isa)
13954 return (&mips_cpu_info_table[i]);
13959 static const struct mips_cpu_info *
13960 mips_cpu_info_from_arch (int arch)
13964 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13965 if (arch == mips_cpu_info_table[i].cpu)
13966 return (&mips_cpu_info_table[i]);
13972 show (FILE *stream, const char *string, int *col_p, int *first_p)
13976 fprintf (stream, "%24s", "");
13981 fprintf (stream, ", ");
13985 if (*col_p + strlen (string) > 72)
13987 fprintf (stream, "\n%24s", "");
13991 fprintf (stream, "%s", string);
13992 *col_p += strlen (string);
13998 md_show_usage (FILE *stream)
14003 fprintf (stream, _("\
14005 -EB generate big endian output\n\
14006 -EL generate little endian output\n\
14007 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14008 -G NUM allow referencing objects up to NUM bytes\n\
14009 implicitly with the gp register [default 8]\n"));
14010 fprintf (stream, _("\
14011 -mips1 generate MIPS ISA I instructions\n\
14012 -mips2 generate MIPS ISA II instructions\n\
14013 -mips3 generate MIPS ISA III instructions\n\
14014 -mips4 generate MIPS ISA IV instructions\n\
14015 -mips5 generate MIPS ISA V instructions\n\
14016 -mips32 generate MIPS32 ISA instructions\n\
14017 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14018 -mips64 generate MIPS64 ISA instructions\n\
14019 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14020 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14024 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14025 show (stream, mips_cpu_info_table[i].name, &column, &first);
14026 show (stream, "from-abi", &column, &first);
14027 fputc ('\n', stream);
14029 fprintf (stream, _("\
14030 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14031 -no-mCPU don't generate code specific to CPU.\n\
14032 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14036 show (stream, "3900", &column, &first);
14037 show (stream, "4010", &column, &first);
14038 show (stream, "4100", &column, &first);
14039 show (stream, "4650", &column, &first);
14040 fputc ('\n', stream);
14042 fprintf (stream, _("\
14043 -mips16 generate mips16 instructions\n\
14044 -no-mips16 do not generate mips16 instructions\n"));
14045 fprintf (stream, _("\
14046 -mfix-vr4120 work around certain VR4120 errata\n\
14047 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14048 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14049 -O0 remove unneeded NOPs, do not swap branches\n\
14050 -O remove unneeded NOPs and swap branches\n\
14051 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14052 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14053 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14055 fprintf (stream, _("\
14056 -KPIC, -call_shared generate SVR4 position independent code\n\
14057 -non_shared do not generate position independent code\n\
14058 -xgot assume a 32 bit GOT\n\
14059 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14060 -mabi=ABI create ABI conformant object file for:\n"));
14064 show (stream, "32", &column, &first);
14065 show (stream, "o64", &column, &first);
14066 show (stream, "n32", &column, &first);
14067 show (stream, "64", &column, &first);
14068 show (stream, "eabi", &column, &first);
14070 fputc ('\n', stream);
14072 fprintf (stream, _("\
14073 -32 create o32 ABI object file (default)\n\
14074 -n32 create n32 ABI object file\n\
14075 -64 create 64 ABI object file\n"));
14080 mips_dwarf2_format (void)
14082 if (mips_abi == N64_ABI)
14085 return dwarf2_format_64bit_irix;
14087 return dwarf2_format_64bit;
14091 return dwarf2_format_32bit;
14095 mips_dwarf2_addr_size (void)
14097 if (mips_abi == N64_ABI)