1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro = FALSE;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1295 static void append_insn
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS *, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS *, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS *, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn *ip, char *str);
1306 static void mips16_macro (struct mips_cl_insn * ip);
1307 static void mips_ip (char *str, struct mips_cl_insn * ip);
1308 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314 static void my_getExpression (expressionS *, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean pic_need_relax (symbolS *, asection *);
1350 static int relaxed_branch_length (fragS *, asection *, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name; /* CPU or ISA name. */
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts = "O::g::G:";
1378 OPTION_MARCH = OPTION_MD_BASE,
1410 OPTION_NO_SMARTMIPS,
1420 OPTION_NO_MICROMIPS,
1423 OPTION_COMPAT_ARCH_BASE,
1432 OPTION_M7000_HILO_FIX,
1433 OPTION_MNO_7000_HILO_FIX,
1437 OPTION_NO_FIX_RM7000,
1438 OPTION_FIX_LOONGSON2F_JUMP,
1439 OPTION_NO_FIX_LOONGSON2F_JUMP,
1440 OPTION_FIX_LOONGSON2F_NOP,
1441 OPTION_NO_FIX_LOONGSON2F_NOP,
1443 OPTION_NO_FIX_VR4120,
1445 OPTION_NO_FIX_VR4130,
1446 OPTION_FIX_CN63XXP1,
1447 OPTION_NO_FIX_CN63XXP1,
1454 OPTION_CONSTRUCT_FLOATS,
1455 OPTION_NO_CONSTRUCT_FLOATS,
1459 OPTION_RELAX_BRANCH,
1460 OPTION_NO_RELAX_BRANCH,
1469 OPTION_SINGLE_FLOAT,
1470 OPTION_DOUBLE_FLOAT,
1483 OPTION_MVXWORKS_PIC,
1486 OPTION_NO_ODD_SPREG,
1490 struct option md_longopts[] =
1492 /* Options which specify architecture. */
1493 {"march", required_argument, NULL, OPTION_MARCH},
1494 {"mtune", required_argument, NULL, OPTION_MTUNE},
1495 {"mips0", no_argument, NULL, OPTION_MIPS1},
1496 {"mips1", no_argument, NULL, OPTION_MIPS1},
1497 {"mips2", no_argument, NULL, OPTION_MIPS2},
1498 {"mips3", no_argument, NULL, OPTION_MIPS3},
1499 {"mips4", no_argument, NULL, OPTION_MIPS4},
1500 {"mips5", no_argument, NULL, OPTION_MIPS5},
1501 {"mips32", no_argument, NULL, OPTION_MIPS32},
1502 {"mips64", no_argument, NULL, OPTION_MIPS64},
1503 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1504 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1505 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1506 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1507 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1508 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1509 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1510 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1512 /* Options which specify Application Specific Extensions (ASEs). */
1513 {"mips16", no_argument, NULL, OPTION_MIPS16},
1514 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1515 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1516 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1517 {"mdmx", no_argument, NULL, OPTION_MDMX},
1518 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1519 {"mdsp", no_argument, NULL, OPTION_DSP},
1520 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1521 {"mmt", no_argument, NULL, OPTION_MT},
1522 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1523 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1524 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1525 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1526 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1527 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1528 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1529 {"meva", no_argument, NULL, OPTION_EVA},
1530 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1531 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1532 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1533 {"mmcu", no_argument, NULL, OPTION_MCU},
1534 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1535 {"mvirt", no_argument, NULL, OPTION_VIRT},
1536 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1537 {"mmsa", no_argument, NULL, OPTION_MSA},
1538 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1539 {"mxpa", no_argument, NULL, OPTION_XPA},
1540 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1542 /* Old-style architecture options. Don't add more of these. */
1543 {"m4650", no_argument, NULL, OPTION_M4650},
1544 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1545 {"m4010", no_argument, NULL, OPTION_M4010},
1546 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1547 {"m4100", no_argument, NULL, OPTION_M4100},
1548 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1549 {"m3900", no_argument, NULL, OPTION_M3900},
1550 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1552 /* Options which enable bug fixes. */
1553 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1554 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1555 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1556 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1557 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1558 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1559 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1560 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1561 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1562 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1563 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1564 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1565 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1566 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1567 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1568 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1569 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1571 /* Miscellaneous options. */
1572 {"trap", no_argument, NULL, OPTION_TRAP},
1573 {"no-break", no_argument, NULL, OPTION_TRAP},
1574 {"break", no_argument, NULL, OPTION_BREAK},
1575 {"no-trap", no_argument, NULL, OPTION_BREAK},
1576 {"EB", no_argument, NULL, OPTION_EB},
1577 {"EL", no_argument, NULL, OPTION_EL},
1578 {"mfp32", no_argument, NULL, OPTION_FP32},
1579 {"mgp32", no_argument, NULL, OPTION_GP32},
1580 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1581 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1582 {"mfp64", no_argument, NULL, OPTION_FP64},
1583 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1584 {"mgp64", no_argument, NULL, OPTION_GP64},
1585 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1586 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1587 {"minsn32", no_argument, NULL, OPTION_INSN32},
1588 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1589 {"mshared", no_argument, NULL, OPTION_MSHARED},
1590 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1591 {"msym32", no_argument, NULL, OPTION_MSYM32},
1592 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1593 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1594 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1595 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1596 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1597 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1598 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1600 /* Strictly speaking this next option is ELF specific,
1601 but we allow it for other ports as well in order to
1602 make testing easier. */
1603 {"32", no_argument, NULL, OPTION_32},
1605 /* ELF-specific options. */
1606 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1607 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1608 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1609 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1610 {"xgot", no_argument, NULL, OPTION_XGOT},
1611 {"mabi", required_argument, NULL, OPTION_MABI},
1612 {"n32", no_argument, NULL, OPTION_N32},
1613 {"64", no_argument, NULL, OPTION_64},
1614 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1615 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1616 {"mpdr", no_argument, NULL, OPTION_PDR},
1617 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1618 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1619 {"mnan", required_argument, NULL, OPTION_NAN},
1621 {NULL, no_argument, NULL, 0}
1623 size_t md_longopts_size = sizeof (md_longopts);
1625 /* Information about either an Application Specific Extension or an
1626 optional architecture feature that, for simplicity, we treat in the
1627 same way as an ASE. */
1630 /* The name of the ASE, used in both the command-line and .set options. */
1633 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1634 and 64-bit architectures, the flags here refer to the subset that
1635 is available on both. */
1638 /* The ASE_* flag used for instructions that are available on 64-bit
1639 architectures but that are not included in FLAGS. */
1640 unsigned int flags64;
1642 /* The command-line options that turn the ASE on and off. */
1646 /* The minimum required architecture revisions for MIPS32, MIPS64,
1647 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1650 int micromips32_rev;
1651 int micromips64_rev;
1653 /* The architecture where the ASE was removed or -1 if the extension has not
1658 /* A table of all supported ASEs. */
1659 static const struct mips_ase mips_ases[] = {
1660 { "dsp", ASE_DSP, ASE_DSP64,
1661 OPTION_DSP, OPTION_NO_DSP,
1665 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1666 OPTION_DSPR2, OPTION_NO_DSPR2,
1670 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1671 OPTION_DSPR3, OPTION_NO_DSPR3,
1675 { "eva", ASE_EVA, 0,
1676 OPTION_EVA, OPTION_NO_EVA,
1680 { "mcu", ASE_MCU, 0,
1681 OPTION_MCU, OPTION_NO_MCU,
1685 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1686 { "mdmx", ASE_MDMX, 0,
1687 OPTION_MDMX, OPTION_NO_MDMX,
1691 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1692 { "mips3d", ASE_MIPS3D, 0,
1693 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1698 OPTION_MT, OPTION_NO_MT,
1702 { "smartmips", ASE_SMARTMIPS, 0,
1703 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1707 { "virt", ASE_VIRT, ASE_VIRT64,
1708 OPTION_VIRT, OPTION_NO_VIRT,
1712 { "msa", ASE_MSA, ASE_MSA64,
1713 OPTION_MSA, OPTION_NO_MSA,
1717 { "xpa", ASE_XPA, 0,
1718 OPTION_XPA, OPTION_NO_XPA,
1723 /* The set of ASEs that require -mfp64. */
1724 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1726 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1727 static const unsigned int mips_ase_groups[] = {
1728 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1733 The following pseudo-ops from the Kane and Heinrich MIPS book
1734 should be defined here, but are currently unsupported: .alias,
1735 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1737 The following pseudo-ops from the Kane and Heinrich MIPS book are
1738 specific to the type of debugging information being generated, and
1739 should be defined by the object format: .aent, .begin, .bend,
1740 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1743 The following pseudo-ops from the Kane and Heinrich MIPS book are
1744 not MIPS CPU specific, but are also not specific to the object file
1745 format. This file is probably the best place to define them, but
1746 they are not currently supported: .asm0, .endr, .lab, .struct. */
1748 static const pseudo_typeS mips_pseudo_table[] =
1750 /* MIPS specific pseudo-ops. */
1751 {"option", s_option, 0},
1752 {"set", s_mipsset, 0},
1753 {"rdata", s_change_sec, 'r'},
1754 {"sdata", s_change_sec, 's'},
1755 {"livereg", s_ignore, 0},
1756 {"abicalls", s_abicalls, 0},
1757 {"cpload", s_cpload, 0},
1758 {"cpsetup", s_cpsetup, 0},
1759 {"cplocal", s_cplocal, 0},
1760 {"cprestore", s_cprestore, 0},
1761 {"cpreturn", s_cpreturn, 0},
1762 {"dtprelword", s_dtprelword, 0},
1763 {"dtpreldword", s_dtpreldword, 0},
1764 {"tprelword", s_tprelword, 0},
1765 {"tpreldword", s_tpreldword, 0},
1766 {"gpvalue", s_gpvalue, 0},
1767 {"gpword", s_gpword, 0},
1768 {"gpdword", s_gpdword, 0},
1769 {"ehword", s_ehword, 0},
1770 {"cpadd", s_cpadd, 0},
1771 {"insn", s_insn, 0},
1773 {"module", s_module, 0},
1775 /* Relatively generic pseudo-ops that happen to be used on MIPS
1777 {"asciiz", stringer, 8 + 1},
1778 {"bss", s_change_sec, 'b'},
1780 {"half", s_cons, 1},
1781 {"dword", s_cons, 3},
1782 {"weakext", s_mips_weakext, 0},
1783 {"origin", s_org, 0},
1784 {"repeat", s_rept, 0},
1786 /* For MIPS this is non-standard, but we define it for consistency. */
1787 {"sbss", s_change_sec, 'B'},
1789 /* These pseudo-ops are defined in read.c, but must be overridden
1790 here for one reason or another. */
1791 {"align", s_align, 0},
1792 {"byte", s_cons, 0},
1793 {"data", s_change_sec, 'd'},
1794 {"double", s_float_cons, 'd'},
1795 {"float", s_float_cons, 'f'},
1796 {"globl", s_mips_globl, 0},
1797 {"global", s_mips_globl, 0},
1798 {"hword", s_cons, 1},
1800 {"long", s_cons, 2},
1801 {"octa", s_cons, 4},
1802 {"quad", s_cons, 3},
1803 {"section", s_change_section, 0},
1804 {"short", s_cons, 1},
1805 {"single", s_float_cons, 'f'},
1806 {"stabd", s_mips_stab, 'd'},
1807 {"stabn", s_mips_stab, 'n'},
1808 {"stabs", s_mips_stab, 's'},
1809 {"text", s_change_sec, 't'},
1810 {"word", s_cons, 2},
1812 { "extern", ecoff_directive_extern, 0},
1817 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1819 /* These pseudo-ops should be defined by the object file format.
1820 However, a.out doesn't support them, so we have versions here. */
1821 {"aent", s_mips_ent, 1},
1822 {"bgnb", s_ignore, 0},
1823 {"end", s_mips_end, 0},
1824 {"endb", s_ignore, 0},
1825 {"ent", s_mips_ent, 0},
1826 {"file", s_mips_file, 0},
1827 {"fmask", s_mips_mask, 'F'},
1828 {"frame", s_mips_frame, 0},
1829 {"loc", s_mips_loc, 0},
1830 {"mask", s_mips_mask, 'R'},
1831 {"verstamp", s_ignore, 0},
1835 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1836 purpose of the `.dc.a' internal pseudo-op. */
1839 mips_address_bytes (void)
1841 file_mips_check_options ();
1842 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1845 extern void pop_insert (const pseudo_typeS *);
1848 mips_pop_insert (void)
1850 pop_insert (mips_pseudo_table);
1851 if (! ECOFF_DEBUGGING)
1852 pop_insert (mips_nonecoff_pseudo_table);
1855 /* Symbols labelling the current insn. */
1857 struct insn_label_list
1859 struct insn_label_list *next;
1863 static struct insn_label_list *free_insn_labels;
1864 #define label_list tc_segment_info_data.labels
1866 static void mips_clear_insn_labels (void);
1867 static void mips_mark_labels (void);
1868 static void mips_compressed_mark_labels (void);
1871 mips_clear_insn_labels (void)
1873 struct insn_label_list **pl;
1874 segment_info_type *si;
1878 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1881 si = seg_info (now_seg);
1882 *pl = si->label_list;
1883 si->label_list = NULL;
1887 /* Mark instruction labels in MIPS16/microMIPS mode. */
1890 mips_mark_labels (void)
1892 if (HAVE_CODE_COMPRESSION)
1893 mips_compressed_mark_labels ();
1896 static char *expr_end;
1898 /* An expression in a macro instruction. This is set by mips_ip and
1899 mips16_ip and when populated is always an O_constant. */
1901 static expressionS imm_expr;
1903 /* The relocatable field in an instruction and the relocs associated
1904 with it. These variables are used for instructions like LUI and
1905 JAL as well as true offsets. They are also used for address
1906 operands in macros. */
1908 static expressionS offset_expr;
1909 static bfd_reloc_code_real_type offset_reloc[3]
1910 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1912 /* This is set to the resulting size of the instruction to be produced
1913 by mips16_ip if an explicit extension is used or by mips_ip if an
1914 explicit size is supplied. */
1916 static unsigned int forced_insn_length;
1918 /* True if we are assembling an instruction. All dot symbols defined during
1919 this time should be treated as code labels. */
1921 static bfd_boolean mips_assembling_insn;
1923 /* The pdr segment for per procedure frame/regmask info. Not used for
1926 static segT pdr_seg;
1928 /* The default target format to use. */
1930 #if defined (TE_FreeBSD)
1931 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1932 #elif defined (TE_TMIPS)
1933 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1935 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1939 mips_target_format (void)
1941 switch (OUTPUT_FLAVOR)
1943 case bfd_target_elf_flavour:
1945 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1946 return (target_big_endian
1947 ? "elf32-bigmips-vxworks"
1948 : "elf32-littlemips-vxworks");
1950 return (target_big_endian
1951 ? (HAVE_64BIT_OBJECTS
1952 ? ELF_TARGET ("elf64-", "big")
1954 ? ELF_TARGET ("elf32-n", "big")
1955 : ELF_TARGET ("elf32-", "big")))
1956 : (HAVE_64BIT_OBJECTS
1957 ? ELF_TARGET ("elf64-", "little")
1959 ? ELF_TARGET ("elf32-n", "little")
1960 : ELF_TARGET ("elf32-", "little"))));
1967 /* Return the ISA revision that is currently in use, or 0 if we are
1968 generating code for MIPS V or below. */
1973 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1976 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1979 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1982 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1985 /* microMIPS implies revision 2 or above. */
1986 if (mips_opts.micromips)
1989 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1995 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1998 mips_ase_mask (unsigned int flags)
2002 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2003 if (flags & mips_ase_groups[i])
2004 flags |= mips_ase_groups[i];
2008 /* Check whether the current ISA supports ASE. Issue a warning if
2012 mips_check_isa_supports_ase (const struct mips_ase *ase)
2016 static unsigned int warned_isa;
2017 static unsigned int warned_fp32;
2019 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2020 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2022 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2023 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2024 && (warned_isa & ase->flags) != ase->flags)
2026 warned_isa |= ase->flags;
2027 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2028 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2030 as_warn (_("the %d-bit %s architecture does not support the"
2031 " `%s' extension"), size, base, ase->name);
2033 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2034 ase->name, base, size, min_rev);
2036 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2037 && (warned_isa & ase->flags) != ase->flags)
2039 warned_isa |= ase->flags;
2040 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2041 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2042 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2043 ase->name, base, size, ase->rem_rev);
2046 if ((ase->flags & FP64_ASES)
2047 && mips_opts.fp != 64
2048 && (warned_fp32 & ase->flags) != ase->flags)
2050 warned_fp32 |= ase->flags;
2051 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2055 /* Check all enabled ASEs to see whether they are supported by the
2056 chosen architecture. */
2059 mips_check_isa_supports_ases (void)
2061 unsigned int i, mask;
2063 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2065 mask = mips_ase_mask (mips_ases[i].flags);
2066 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2067 mips_check_isa_supports_ase (&mips_ases[i]);
2071 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2072 that were affected. */
2075 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2076 bfd_boolean enabled_p)
2080 mask = mips_ase_mask (ase->flags);
2083 opts->ase |= ase->flags;
2087 /* Return the ASE called NAME, or null if none. */
2089 static const struct mips_ase *
2090 mips_lookup_ase (const char *name)
2094 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2095 if (strcmp (name, mips_ases[i].name) == 0)
2096 return &mips_ases[i];
2100 /* Return the length of a microMIPS instruction in bytes. If bits of
2101 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2102 otherwise it is a 32-bit instruction. */
2104 static inline unsigned int
2105 micromips_insn_length (const struct mips_opcode *mo)
2107 return (mo->mask >> 16) == 0 ? 2 : 4;
2110 /* Return the length of MIPS16 instruction OPCODE. */
2112 static inline unsigned int
2113 mips16_opcode_length (unsigned long opcode)
2115 return (opcode >> 16) == 0 ? 2 : 4;
2118 /* Return the length of instruction INSN. */
2120 static inline unsigned int
2121 insn_length (const struct mips_cl_insn *insn)
2123 if (mips_opts.micromips)
2124 return micromips_insn_length (insn->insn_mo);
2125 else if (mips_opts.mips16)
2126 return mips16_opcode_length (insn->insn_opcode);
2131 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2134 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2139 insn->insn_opcode = mo->match;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 insn->fixp[i] = NULL;
2144 insn->fixed_p = (mips_opts.noreorder > 0);
2145 insn->noreorder_p = (mips_opts.noreorder > 0);
2146 insn->mips16_absolute_jump_p = 0;
2147 insn->complete_p = 0;
2148 insn->cleared_p = 0;
2151 /* Get a list of all the operands in INSN. */
2153 static const struct mips_operand_array *
2154 insn_operands (const struct mips_cl_insn *insn)
2156 if (insn->insn_mo >= &mips_opcodes[0]
2157 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2158 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2160 if (insn->insn_mo >= &mips16_opcodes[0]
2161 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2162 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2164 if (insn->insn_mo >= µmips_opcodes[0]
2165 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2166 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2171 /* Get a description of operand OPNO of INSN. */
2173 static const struct mips_operand *
2174 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2176 const struct mips_operand_array *operands;
2178 operands = insn_operands (insn);
2179 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2181 return operands->operand[opno];
2184 /* Install UVAL as the value of OPERAND in INSN. */
2187 insn_insert_operand (struct mips_cl_insn *insn,
2188 const struct mips_operand *operand, unsigned int uval)
2190 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2193 /* Extract the value of OPERAND from INSN. */
2195 static inline unsigned
2196 insn_extract_operand (const struct mips_cl_insn *insn,
2197 const struct mips_operand *operand)
2199 return mips_extract_operand (operand, insn->insn_opcode);
2202 /* Record the current MIPS16/microMIPS mode in now_seg. */
2205 mips_record_compressed_mode (void)
2207 segment_info_type *si;
2209 si = seg_info (now_seg);
2210 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2211 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2212 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2213 si->tc_segment_info_data.micromips = mips_opts.micromips;
2216 /* Read a standard MIPS instruction from BUF. */
2218 static unsigned long
2219 read_insn (char *buf)
2221 if (target_big_endian)
2222 return bfd_getb32 ((bfd_byte *) buf);
2224 return bfd_getl32 ((bfd_byte *) buf);
2227 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2231 write_insn (char *buf, unsigned int insn)
2233 md_number_to_chars (buf, insn, 4);
2237 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2238 has length LENGTH. */
2240 static unsigned long
2241 read_compressed_insn (char *buf, unsigned int length)
2247 for (i = 0; i < length; i += 2)
2250 if (target_big_endian)
2251 insn |= bfd_getb16 ((char *) buf);
2253 insn |= bfd_getl16 ((char *) buf);
2259 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2260 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2263 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2267 for (i = 0; i < length; i += 2)
2268 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2269 return buf + length;
2272 /* Install INSN at the location specified by its "frag" and "where" fields. */
2275 install_insn (const struct mips_cl_insn *insn)
2277 char *f = insn->frag->fr_literal + insn->where;
2278 if (HAVE_CODE_COMPRESSION)
2279 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2281 write_insn (f, insn->insn_opcode);
2282 mips_record_compressed_mode ();
2285 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2286 and install the opcode in the new location. */
2289 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2294 insn->where = where;
2295 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2296 if (insn->fixp[i] != NULL)
2298 insn->fixp[i]->fx_frag = frag;
2299 insn->fixp[i]->fx_where = where;
2301 install_insn (insn);
2304 /* Add INSN to the end of the output. */
2307 add_fixed_insn (struct mips_cl_insn *insn)
2309 char *f = frag_more (insn_length (insn));
2310 move_insn (insn, frag_now, f - frag_now->fr_literal);
2313 /* Start a variant frag and move INSN to the start of the variant part,
2314 marking it as fixed. The other arguments are as for frag_var. */
2317 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2318 relax_substateT subtype, symbolS *symbol, offsetT offset)
2320 frag_grow (max_chars);
2321 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2323 frag_var (rs_machine_dependent, max_chars, var,
2324 subtype, symbol, offset, NULL);
2327 /* Insert N copies of INSN into the history buffer, starting at
2328 position FIRST. Neither FIRST nor N need to be clipped. */
2331 insert_into_history (unsigned int first, unsigned int n,
2332 const struct mips_cl_insn *insn)
2334 if (mips_relax.sequence != 2)
2338 for (i = ARRAY_SIZE (history); i-- > first;)
2340 history[i] = history[i - n];
2346 /* Clear the error in insn_error. */
2349 clear_insn_error (void)
2351 memset (&insn_error, 0, sizeof (insn_error));
2354 /* Possibly record error message MSG for the current instruction.
2355 If the error is about a particular argument, ARGNUM is the 1-based
2356 number of that argument, otherwise it is 0. FORMAT is the format
2357 of MSG. Return true if MSG was used, false if the current message
2361 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2366 /* Give priority to errors against specific arguments, and to
2367 the first whole-instruction message. */
2373 /* Keep insn_error if it is against a later argument. */
2374 if (argnum < insn_error.min_argnum)
2377 /* If both errors are against the same argument but are different,
2378 give up on reporting a specific error for this argument.
2379 See the comment about mips_insn_error for details. */
2380 if (argnum == insn_error.min_argnum
2382 && strcmp (insn_error.msg, msg) != 0)
2385 insn_error.min_argnum += 1;
2389 insn_error.min_argnum = argnum;
2390 insn_error.format = format;
2391 insn_error.msg = msg;
2395 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error (int argnum, const char *msg)
2401 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2404 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2405 as for set_insn_error_format. */
2408 set_insn_error_i (int argnum, const char *msg, int i)
2410 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2414 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2415 are as for set_insn_error_format. */
2418 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2420 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2422 insn_error.u.ss[0] = s1;
2423 insn_error.u.ss[1] = s2;
2427 /* Report the error in insn_error, which is against assembly code STR. */
2430 report_insn_error (const char *str)
2432 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2434 switch (insn_error.format)
2441 as_bad (msg, insn_error.u.i, str);
2445 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2449 free ((char *) msg);
2452 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2453 the idea is to make it obvious at a glance that each errata is
2457 init_vr4120_conflicts (void)
2459 #define CONFLICT(FIRST, SECOND) \
2460 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2462 /* Errata 21 - [D]DIV[U] after [D]MACC */
2463 CONFLICT (MACC, DIV);
2464 CONFLICT (DMACC, DIV);
2466 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2467 CONFLICT (DMULT, DMULT);
2468 CONFLICT (DMULT, DMACC);
2469 CONFLICT (DMACC, DMULT);
2470 CONFLICT (DMACC, DMACC);
2472 /* Errata 24 - MT{LO,HI} after [D]MACC */
2473 CONFLICT (MACC, MTHILO);
2474 CONFLICT (DMACC, MTHILO);
2476 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2477 instruction is executed immediately after a MACC or DMACC
2478 instruction, the result of [either instruction] is incorrect." */
2479 CONFLICT (MACC, MULT);
2480 CONFLICT (MACC, DMULT);
2481 CONFLICT (DMACC, MULT);
2482 CONFLICT (DMACC, DMULT);
2484 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2485 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2486 DDIV or DDIVU instruction, the result of the MACC or
2487 DMACC instruction is incorrect.". */
2488 CONFLICT (DMULT, MACC);
2489 CONFLICT (DMULT, DMACC);
2490 CONFLICT (DIV, MACC);
2491 CONFLICT (DIV, DMACC);
2501 #define RNUM_MASK 0x00000ff
2502 #define RTYPE_MASK 0x0ffff00
2503 #define RTYPE_NUM 0x0000100
2504 #define RTYPE_FPU 0x0000200
2505 #define RTYPE_FCC 0x0000400
2506 #define RTYPE_VEC 0x0000800
2507 #define RTYPE_GP 0x0001000
2508 #define RTYPE_CP0 0x0002000
2509 #define RTYPE_PC 0x0004000
2510 #define RTYPE_ACC 0x0008000
2511 #define RTYPE_CCC 0x0010000
2512 #define RTYPE_VI 0x0020000
2513 #define RTYPE_VF 0x0040000
2514 #define RTYPE_R5900_I 0x0080000
2515 #define RTYPE_R5900_Q 0x0100000
2516 #define RTYPE_R5900_R 0x0200000
2517 #define RTYPE_R5900_ACC 0x0400000
2518 #define RTYPE_MSA 0x0800000
2519 #define RWARN 0x8000000
2521 #define GENERIC_REGISTER_NUMBERS \
2522 {"$0", RTYPE_NUM | 0}, \
2523 {"$1", RTYPE_NUM | 1}, \
2524 {"$2", RTYPE_NUM | 2}, \
2525 {"$3", RTYPE_NUM | 3}, \
2526 {"$4", RTYPE_NUM | 4}, \
2527 {"$5", RTYPE_NUM | 5}, \
2528 {"$6", RTYPE_NUM | 6}, \
2529 {"$7", RTYPE_NUM | 7}, \
2530 {"$8", RTYPE_NUM | 8}, \
2531 {"$9", RTYPE_NUM | 9}, \
2532 {"$10", RTYPE_NUM | 10}, \
2533 {"$11", RTYPE_NUM | 11}, \
2534 {"$12", RTYPE_NUM | 12}, \
2535 {"$13", RTYPE_NUM | 13}, \
2536 {"$14", RTYPE_NUM | 14}, \
2537 {"$15", RTYPE_NUM | 15}, \
2538 {"$16", RTYPE_NUM | 16}, \
2539 {"$17", RTYPE_NUM | 17}, \
2540 {"$18", RTYPE_NUM | 18}, \
2541 {"$19", RTYPE_NUM | 19}, \
2542 {"$20", RTYPE_NUM | 20}, \
2543 {"$21", RTYPE_NUM | 21}, \
2544 {"$22", RTYPE_NUM | 22}, \
2545 {"$23", RTYPE_NUM | 23}, \
2546 {"$24", RTYPE_NUM | 24}, \
2547 {"$25", RTYPE_NUM | 25}, \
2548 {"$26", RTYPE_NUM | 26}, \
2549 {"$27", RTYPE_NUM | 27}, \
2550 {"$28", RTYPE_NUM | 28}, \
2551 {"$29", RTYPE_NUM | 29}, \
2552 {"$30", RTYPE_NUM | 30}, \
2553 {"$31", RTYPE_NUM | 31}
2555 #define FPU_REGISTER_NAMES \
2556 {"$f0", RTYPE_FPU | 0}, \
2557 {"$f1", RTYPE_FPU | 1}, \
2558 {"$f2", RTYPE_FPU | 2}, \
2559 {"$f3", RTYPE_FPU | 3}, \
2560 {"$f4", RTYPE_FPU | 4}, \
2561 {"$f5", RTYPE_FPU | 5}, \
2562 {"$f6", RTYPE_FPU | 6}, \
2563 {"$f7", RTYPE_FPU | 7}, \
2564 {"$f8", RTYPE_FPU | 8}, \
2565 {"$f9", RTYPE_FPU | 9}, \
2566 {"$f10", RTYPE_FPU | 10}, \
2567 {"$f11", RTYPE_FPU | 11}, \
2568 {"$f12", RTYPE_FPU | 12}, \
2569 {"$f13", RTYPE_FPU | 13}, \
2570 {"$f14", RTYPE_FPU | 14}, \
2571 {"$f15", RTYPE_FPU | 15}, \
2572 {"$f16", RTYPE_FPU | 16}, \
2573 {"$f17", RTYPE_FPU | 17}, \
2574 {"$f18", RTYPE_FPU | 18}, \
2575 {"$f19", RTYPE_FPU | 19}, \
2576 {"$f20", RTYPE_FPU | 20}, \
2577 {"$f21", RTYPE_FPU | 21}, \
2578 {"$f22", RTYPE_FPU | 22}, \
2579 {"$f23", RTYPE_FPU | 23}, \
2580 {"$f24", RTYPE_FPU | 24}, \
2581 {"$f25", RTYPE_FPU | 25}, \
2582 {"$f26", RTYPE_FPU | 26}, \
2583 {"$f27", RTYPE_FPU | 27}, \
2584 {"$f28", RTYPE_FPU | 28}, \
2585 {"$f29", RTYPE_FPU | 29}, \
2586 {"$f30", RTYPE_FPU | 30}, \
2587 {"$f31", RTYPE_FPU | 31}
2589 #define FPU_CONDITION_CODE_NAMES \
2590 {"$fcc0", RTYPE_FCC | 0}, \
2591 {"$fcc1", RTYPE_FCC | 1}, \
2592 {"$fcc2", RTYPE_FCC | 2}, \
2593 {"$fcc3", RTYPE_FCC | 3}, \
2594 {"$fcc4", RTYPE_FCC | 4}, \
2595 {"$fcc5", RTYPE_FCC | 5}, \
2596 {"$fcc6", RTYPE_FCC | 6}, \
2597 {"$fcc7", RTYPE_FCC | 7}
2599 #define COPROC_CONDITION_CODE_NAMES \
2600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2610 {"$a4", RTYPE_GP | 8}, \
2611 {"$a5", RTYPE_GP | 9}, \
2612 {"$a6", RTYPE_GP | 10}, \
2613 {"$a7", RTYPE_GP | 11}, \
2614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2618 {"$t0", RTYPE_GP | 12}, \
2619 {"$t1", RTYPE_GP | 13}, \
2620 {"$t2", RTYPE_GP | 14}, \
2621 {"$t3", RTYPE_GP | 15}
2623 #define O32_SYMBOLIC_REGISTER_NAMES \
2624 {"$t0", RTYPE_GP | 8}, \
2625 {"$t1", RTYPE_GP | 9}, \
2626 {"$t2", RTYPE_GP | 10}, \
2627 {"$t3", RTYPE_GP | 11}, \
2628 {"$t4", RTYPE_GP | 12}, \
2629 {"$t5", RTYPE_GP | 13}, \
2630 {"$t6", RTYPE_GP | 14}, \
2631 {"$t7", RTYPE_GP | 15}, \
2632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2637 /* Remaining symbolic register names */
2638 #define SYMBOLIC_REGISTER_NAMES \
2639 {"$zero", RTYPE_GP | 0}, \
2640 {"$at", RTYPE_GP | 1}, \
2641 {"$AT", RTYPE_GP | 1}, \
2642 {"$v0", RTYPE_GP | 2}, \
2643 {"$v1", RTYPE_GP | 3}, \
2644 {"$a0", RTYPE_GP | 4}, \
2645 {"$a1", RTYPE_GP | 5}, \
2646 {"$a2", RTYPE_GP | 6}, \
2647 {"$a3", RTYPE_GP | 7}, \
2648 {"$s0", RTYPE_GP | 16}, \
2649 {"$s1", RTYPE_GP | 17}, \
2650 {"$s2", RTYPE_GP | 18}, \
2651 {"$s3", RTYPE_GP | 19}, \
2652 {"$s4", RTYPE_GP | 20}, \
2653 {"$s5", RTYPE_GP | 21}, \
2654 {"$s6", RTYPE_GP | 22}, \
2655 {"$s7", RTYPE_GP | 23}, \
2656 {"$t8", RTYPE_GP | 24}, \
2657 {"$t9", RTYPE_GP | 25}, \
2658 {"$k0", RTYPE_GP | 26}, \
2659 {"$kt0", RTYPE_GP | 26}, \
2660 {"$k1", RTYPE_GP | 27}, \
2661 {"$kt1", RTYPE_GP | 27}, \
2662 {"$gp", RTYPE_GP | 28}, \
2663 {"$sp", RTYPE_GP | 29}, \
2664 {"$s8", RTYPE_GP | 30}, \
2665 {"$fp", RTYPE_GP | 30}, \
2666 {"$ra", RTYPE_GP | 31}
2668 #define MIPS16_SPECIAL_REGISTER_NAMES \
2669 {"$pc", RTYPE_PC | 0}
2671 #define MDMX_VECTOR_REGISTER_NAMES \
2672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2674 {"$v2", RTYPE_VEC | 2}, \
2675 {"$v3", RTYPE_VEC | 3}, \
2676 {"$v4", RTYPE_VEC | 4}, \
2677 {"$v5", RTYPE_VEC | 5}, \
2678 {"$v6", RTYPE_VEC | 6}, \
2679 {"$v7", RTYPE_VEC | 7}, \
2680 {"$v8", RTYPE_VEC | 8}, \
2681 {"$v9", RTYPE_VEC | 9}, \
2682 {"$v10", RTYPE_VEC | 10}, \
2683 {"$v11", RTYPE_VEC | 11}, \
2684 {"$v12", RTYPE_VEC | 12}, \
2685 {"$v13", RTYPE_VEC | 13}, \
2686 {"$v14", RTYPE_VEC | 14}, \
2687 {"$v15", RTYPE_VEC | 15}, \
2688 {"$v16", RTYPE_VEC | 16}, \
2689 {"$v17", RTYPE_VEC | 17}, \
2690 {"$v18", RTYPE_VEC | 18}, \
2691 {"$v19", RTYPE_VEC | 19}, \
2692 {"$v20", RTYPE_VEC | 20}, \
2693 {"$v21", RTYPE_VEC | 21}, \
2694 {"$v22", RTYPE_VEC | 22}, \
2695 {"$v23", RTYPE_VEC | 23}, \
2696 {"$v24", RTYPE_VEC | 24}, \
2697 {"$v25", RTYPE_VEC | 25}, \
2698 {"$v26", RTYPE_VEC | 26}, \
2699 {"$v27", RTYPE_VEC | 27}, \
2700 {"$v28", RTYPE_VEC | 28}, \
2701 {"$v29", RTYPE_VEC | 29}, \
2702 {"$v30", RTYPE_VEC | 30}, \
2703 {"$v31", RTYPE_VEC | 31}
2705 #define R5900_I_NAMES \
2706 {"$I", RTYPE_R5900_I | 0}
2708 #define R5900_Q_NAMES \
2709 {"$Q", RTYPE_R5900_Q | 0}
2711 #define R5900_R_NAMES \
2712 {"$R", RTYPE_R5900_R | 0}
2714 #define R5900_ACC_NAMES \
2715 {"$ACC", RTYPE_R5900_ACC | 0 }
2717 #define MIPS_DSP_ACCUMULATOR_NAMES \
2718 {"$ac0", RTYPE_ACC | 0}, \
2719 {"$ac1", RTYPE_ACC | 1}, \
2720 {"$ac2", RTYPE_ACC | 2}, \
2721 {"$ac3", RTYPE_ACC | 3}
2723 static const struct regname reg_names[] = {
2724 GENERIC_REGISTER_NUMBERS,
2726 FPU_CONDITION_CODE_NAMES,
2727 COPROC_CONDITION_CODE_NAMES,
2729 /* The $txx registers depends on the abi,
2730 these will be added later into the symbol table from
2731 one of the tables below once mips_abi is set after
2732 parsing of arguments from the command line. */
2733 SYMBOLIC_REGISTER_NAMES,
2735 MIPS16_SPECIAL_REGISTER_NAMES,
2736 MDMX_VECTOR_REGISTER_NAMES,
2741 MIPS_DSP_ACCUMULATOR_NAMES,
2745 static const struct regname reg_names_o32[] = {
2746 O32_SYMBOLIC_REGISTER_NAMES,
2750 static const struct regname reg_names_n32n64[] = {
2751 N32N64_SYMBOLIC_REGISTER_NAMES,
2755 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2756 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2757 of these register symbols, return the associated vector register,
2758 otherwise return SYMVAL itself. */
2761 mips_prefer_vec_regno (unsigned int symval)
2763 if ((symval & -2) == (RTYPE_GP | 2))
2764 return RTYPE_VEC | (symval & 1);
2768 /* Return true if string [S, E) is a valid register name, storing its
2769 symbol value in *SYMVAL_PTR if so. */
2772 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2777 /* Terminate name. */
2781 /* Look up the name. */
2782 symbol = symbol_find (s);
2785 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2788 *symval_ptr = S_GET_VALUE (symbol);
2792 /* Return true if the string at *SPTR is a valid register name. Allow it
2793 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2796 When returning true, move *SPTR past the register, store the
2797 register's symbol value in *SYMVAL_PTR and the channel mask in
2798 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2799 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2800 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2803 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2804 unsigned int *channels_ptr)
2808 unsigned int channels, symval, bit;
2810 /* Find end of name. */
2812 if (is_name_beginner (*e))
2814 while (is_part_of_name (*e))
2818 if (!mips_parse_register_1 (s, e, &symval))
2823 /* Eat characters from the end of the string that are valid
2824 channel suffixes. The preceding register must be $ACC or
2825 end with a digit, so there is no ambiguity. */
2828 for (q = "wzyx"; *q; q++, bit <<= 1)
2829 if (m > s && m[-1] == *q)
2836 || !mips_parse_register_1 (s, m, &symval)
2837 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2842 *symval_ptr = symval;
2844 *channels_ptr = channels;
2848 /* Check if SPTR points at a valid register specifier according to TYPES.
2849 If so, then return 1, advance S to consume the specifier and store
2850 the register's number in REGNOP, otherwise return 0. */
2853 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2857 if (mips_parse_register (s, ®no, NULL))
2859 if (types & RTYPE_VEC)
2860 regno = mips_prefer_vec_regno (regno);
2869 as_warn (_("unrecognized register name `%s'"), *s);
2874 return regno <= RNUM_MASK;
2877 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2878 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2881 mips_parse_vu0_channels (char *s, unsigned int *channels)
2886 for (i = 0; i < 4; i++)
2887 if (*s == "xyzw"[i])
2889 *channels |= 1 << (3 - i);
2895 /* Token types for parsed operand lists. */
2896 enum mips_operand_token_type {
2897 /* A plain register, e.g. $f2. */
2900 /* A 4-bit XYZW channel mask. */
2903 /* A constant vector index, e.g. [1]. */
2906 /* A register vector index, e.g. [$2]. */
2909 /* A continuous range of registers, e.g. $s0-$s4. */
2912 /* A (possibly relocated) expression. */
2915 /* A floating-point value. */
2918 /* A single character. This can be '(', ')' or ',', but '(' only appears
2922 /* A doubled character, either "--" or "++". */
2925 /* The end of the operand list. */
2929 /* A parsed operand token. */
2930 struct mips_operand_token
2932 /* The type of token. */
2933 enum mips_operand_token_type type;
2936 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2939 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2940 unsigned int channels;
2942 /* The integer value of an OT_INTEGER_INDEX. */
2945 /* The two register symbol values involved in an OT_REG_RANGE. */
2947 unsigned int regno1;
2948 unsigned int regno2;
2951 /* The value of an OT_INTEGER. The value is represented as an
2952 expression and the relocation operators that were applied to
2953 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2954 relocation operators were used. */
2957 bfd_reloc_code_real_type relocs[3];
2960 /* The binary data for an OT_FLOAT constant, and the number of bytes
2963 unsigned char data[8];
2967 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2972 /* An obstack used to construct lists of mips_operand_tokens. */
2973 static struct obstack mips_operand_tokens;
2975 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2978 mips_add_token (struct mips_operand_token *token,
2979 enum mips_operand_token_type type)
2982 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2985 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2986 and OT_REG tokens for them if so, and return a pointer to the first
2987 unconsumed character. Return null otherwise. */
2990 mips_parse_base_start (char *s)
2992 struct mips_operand_token token;
2993 unsigned int regno, channels;
2994 bfd_boolean decrement_p;
3000 SKIP_SPACE_TABS (s);
3002 /* Only match "--" as part of a base expression. In other contexts "--X"
3003 is a double negative. */
3004 decrement_p = (s[0] == '-' && s[1] == '-');
3008 SKIP_SPACE_TABS (s);
3011 /* Allow a channel specifier because that leads to better error messages
3012 than treating something like "$vf0x++" as an expression. */
3013 if (!mips_parse_register (&s, ®no, &channels))
3017 mips_add_token (&token, OT_CHAR);
3022 mips_add_token (&token, OT_DOUBLE_CHAR);
3025 token.u.regno = regno;
3026 mips_add_token (&token, OT_REG);
3030 token.u.channels = channels;
3031 mips_add_token (&token, OT_CHANNELS);
3034 /* For consistency, only match "++" as part of base expressions too. */
3035 SKIP_SPACE_TABS (s);
3036 if (s[0] == '+' && s[1] == '+')
3040 mips_add_token (&token, OT_DOUBLE_CHAR);
3046 /* Parse one or more tokens from S. Return a pointer to the first
3047 unconsumed character on success. Return null if an error was found
3048 and store the error text in insn_error. FLOAT_FORMAT is as for
3049 mips_parse_arguments. */
3052 mips_parse_argument_token (char *s, char float_format)
3054 char *end, *save_in;
3056 unsigned int regno1, regno2, channels;
3057 struct mips_operand_token token;
3059 /* First look for "($reg", since we want to treat that as an
3060 OT_CHAR and OT_REG rather than an expression. */
3061 end = mips_parse_base_start (s);
3065 /* Handle other characters that end up as OT_CHARs. */
3066 if (*s == ')' || *s == ',')
3069 mips_add_token (&token, OT_CHAR);
3074 /* Handle tokens that start with a register. */
3075 if (mips_parse_register (&s, ®no1, &channels))
3079 /* A register and a VU0 channel suffix. */
3080 token.u.regno = regno1;
3081 mips_add_token (&token, OT_REG);
3083 token.u.channels = channels;
3084 mips_add_token (&token, OT_CHANNELS);
3088 SKIP_SPACE_TABS (s);
3091 /* A register range. */
3093 SKIP_SPACE_TABS (s);
3094 if (!mips_parse_register (&s, ®no2, NULL))
3096 set_insn_error (0, _("invalid register range"));
3100 token.u.reg_range.regno1 = regno1;
3101 token.u.reg_range.regno2 = regno2;
3102 mips_add_token (&token, OT_REG_RANGE);
3106 /* Add the register itself. */
3107 token.u.regno = regno1;
3108 mips_add_token (&token, OT_REG);
3110 /* Check for a vector index. */
3114 SKIP_SPACE_TABS (s);
3115 if (mips_parse_register (&s, &token.u.regno, NULL))
3116 mips_add_token (&token, OT_REG_INDEX);
3119 expressionS element;
3121 my_getExpression (&element, s);
3122 if (element.X_op != O_constant)
3124 set_insn_error (0, _("vector element must be constant"));
3128 token.u.index = element.X_add_number;
3129 mips_add_token (&token, OT_INTEGER_INDEX);
3131 SKIP_SPACE_TABS (s);
3134 set_insn_error (0, _("missing `]'"));
3144 /* First try to treat expressions as floats. */
3145 save_in = input_line_pointer;
3146 input_line_pointer = s;
3147 err = md_atof (float_format, (char *) token.u.flt.data,
3148 &token.u.flt.length);
3149 end = input_line_pointer;
3150 input_line_pointer = save_in;
3153 set_insn_error (0, err);
3158 mips_add_token (&token, OT_FLOAT);
3163 /* Treat everything else as an integer expression. */
3164 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3165 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3166 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3167 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3169 mips_add_token (&token, OT_INTEGER);
3173 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3174 if expressions should be treated as 32-bit floating-point constants,
3175 'd' if they should be treated as 64-bit floating-point constants,
3176 or 0 if they should be treated as integer expressions (the usual case).
3178 Return a list of tokens on success, otherwise return 0. The caller
3179 must obstack_free the list after use. */
3181 static struct mips_operand_token *
3182 mips_parse_arguments (char *s, char float_format)
3184 struct mips_operand_token token;
3186 SKIP_SPACE_TABS (s);
3189 s = mips_parse_argument_token (s, float_format);
3192 obstack_free (&mips_operand_tokens,
3193 obstack_finish (&mips_operand_tokens));
3196 SKIP_SPACE_TABS (s);
3198 mips_add_token (&token, OT_END);
3199 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3202 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3203 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3206 is_opcode_valid (const struct mips_opcode *mo)
3208 int isa = mips_opts.isa;
3209 int ase = mips_opts.ase;
3213 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3214 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3215 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3216 ase |= mips_ases[i].flags64;
3218 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3221 /* Check whether the instruction or macro requires single-precision or
3222 double-precision floating-point support. Note that this information is
3223 stored differently in the opcode table for insns and macros. */
3224 if (mo->pinfo == INSN_MACRO)
3226 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3227 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3231 fp_s = mo->pinfo & FP_S;
3232 fp_d = mo->pinfo & FP_D;
3235 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3238 if (fp_s && mips_opts.soft_float)
3244 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3245 selected ISA and architecture. */
3248 is_opcode_valid_16 (const struct mips_opcode *mo)
3250 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3253 /* Return TRUE if the size of the microMIPS opcode MO matches one
3254 explicitly requested. Always TRUE in the standard MIPS mode. */
3257 is_size_valid (const struct mips_opcode *mo)
3259 if (!mips_opts.micromips)
3262 if (mips_opts.insn32)
3264 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3266 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3269 if (!forced_insn_length)
3271 if (mo->pinfo == INSN_MACRO)
3273 return forced_insn_length == micromips_insn_length (mo);
3276 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3277 of the preceding instruction. Always TRUE in the standard MIPS mode.
3279 We don't accept macros in 16-bit delay slots to avoid a case where
3280 a macro expansion fails because it relies on a preceding 32-bit real
3281 instruction to have matched and does not handle the operands correctly.
3282 The only macros that may expand to 16-bit instructions are JAL that
3283 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3284 and BGT (that likewise cannot be placed in a delay slot) that decay to
3285 a NOP. In all these cases the macros precede any corresponding real
3286 instruction definitions in the opcode table, so they will match in the
3287 second pass where the size of the delay slot is ignored and therefore
3288 produce correct code. */
3291 is_delay_slot_valid (const struct mips_opcode *mo)
3293 if (!mips_opts.micromips)
3296 if (mo->pinfo == INSN_MACRO)
3297 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3298 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3299 && micromips_insn_length (mo) != 4)
3301 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3302 && micromips_insn_length (mo) != 2)
3308 /* For consistency checking, verify that all bits of OPCODE are specified
3309 either by the match/mask part of the instruction definition, or by the
3310 operand list. Also build up a list of operands in OPERANDS.
3312 INSN_BITS says which bits of the instruction are significant.
3313 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3314 provides the mips_operand description of each operand. DECODE_OPERAND
3315 is null for MIPS16 instructions. */
3318 validate_mips_insn (const struct mips_opcode *opcode,
3319 unsigned long insn_bits,
3320 const struct mips_operand *(*decode_operand) (const char *),
3321 struct mips_operand_array *operands)
3324 unsigned long used_bits, doubled, undefined, opno, mask;
3325 const struct mips_operand *operand;
3327 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3328 if ((mask & opcode->match) != opcode->match)
3330 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3331 opcode->name, opcode->args);
3336 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3337 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3338 for (s = opcode->args; *s; ++s)
3351 if (!decode_operand)
3352 operand = decode_mips16_operand (*s, FALSE);
3354 operand = decode_operand (s);
3355 if (!operand && opcode->pinfo != INSN_MACRO)
3357 as_bad (_("internal: unknown operand type: %s %s"),
3358 opcode->name, opcode->args);
3361 gas_assert (opno < MAX_OPERANDS);
3362 operands->operand[opno] = operand;
3363 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3365 used_bits = mips_insert_operand (operand, used_bits, -1);
3366 if (operand->type == OP_MDMX_IMM_REG)
3367 /* Bit 5 is the format selector (OB vs QH). The opcode table
3368 has separate entries for each format. */
3369 used_bits &= ~(1 << (operand->lsb + 5));
3370 if (operand->type == OP_ENTRY_EXIT_LIST)
3371 used_bits &= ~(mask & 0x700);
3373 /* Skip prefix characters. */
3374 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3379 doubled = used_bits & mask & insn_bits;
3382 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3383 " %s %s"), doubled, opcode->name, opcode->args);
3387 undefined = ~used_bits & insn_bits;
3388 if (opcode->pinfo != INSN_MACRO && undefined)
3390 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3391 undefined, opcode->name, opcode->args);
3394 used_bits &= ~insn_bits;
3397 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3398 used_bits, opcode->name, opcode->args);
3404 /* The MIPS16 version of validate_mips_insn. */
3407 validate_mips16_insn (const struct mips_opcode *opcode,
3408 struct mips_operand_array *operands)
3410 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3412 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3413 instruction. Use TMP to describe the full instruction. */
3414 struct mips_opcode tmp;
3419 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3421 return validate_mips_insn (opcode, 0xffff, 0, operands);
3424 /* The microMIPS version of validate_mips_insn. */
3427 validate_micromips_insn (const struct mips_opcode *opc,
3428 struct mips_operand_array *operands)
3430 unsigned long insn_bits;
3431 unsigned long major;
3432 unsigned int length;
3434 if (opc->pinfo == INSN_MACRO)
3435 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3438 length = micromips_insn_length (opc);
3439 if (length != 2 && length != 4)
3441 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3442 "%s %s"), length, opc->name, opc->args);
3445 major = opc->match >> (10 + 8 * (length - 2));
3446 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3447 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3449 as_bad (_("internal error: bad microMIPS opcode "
3450 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3454 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3455 insn_bits = 1 << 4 * length;
3456 insn_bits <<= 4 * length;
3458 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3462 /* This function is called once, at assembler startup time. It should set up
3463 all the tables, etc. that the MD part of the assembler will need. */
3468 const char *retval = NULL;
3472 if (mips_pic != NO_PIC)
3474 if (g_switch_seen && g_switch_value != 0)
3475 as_bad (_("-G may not be used in position-independent code"));
3478 else if (mips_abicalls)
3480 if (g_switch_seen && g_switch_value != 0)
3481 as_bad (_("-G may not be used with abicalls"));
3485 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3486 as_warn (_("could not set architecture and machine"));
3488 op_hash = hash_new ();
3490 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3491 for (i = 0; i < NUMOPCODES;)
3493 const char *name = mips_opcodes[i].name;
3495 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3498 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3499 mips_opcodes[i].name, retval);
3500 /* Probably a memory allocation problem? Give up now. */
3501 as_fatal (_("broken assembler, no assembly attempted"));
3505 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3506 decode_mips_operand, &mips_operands[i]))
3508 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3510 create_insn (&nop_insn, mips_opcodes + i);
3511 if (mips_fix_loongson2f_nop)
3512 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3513 nop_insn.fixed_p = 1;
3517 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3520 mips16_op_hash = hash_new ();
3521 mips16_operands = XCNEWVEC (struct mips_operand_array,
3522 bfd_mips16_num_opcodes);
3525 while (i < bfd_mips16_num_opcodes)
3527 const char *name = mips16_opcodes[i].name;
3529 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3531 as_fatal (_("internal: can't hash `%s': %s"),
3532 mips16_opcodes[i].name, retval);
3535 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3537 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3539 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3540 mips16_nop_insn.fixed_p = 1;
3544 while (i < bfd_mips16_num_opcodes
3545 && strcmp (mips16_opcodes[i].name, name) == 0);
3548 micromips_op_hash = hash_new ();
3549 micromips_operands = XCNEWVEC (struct mips_operand_array,
3550 bfd_micromips_num_opcodes);
3553 while (i < bfd_micromips_num_opcodes)
3555 const char *name = micromips_opcodes[i].name;
3557 retval = hash_insert (micromips_op_hash, name,
3558 (void *) µmips_opcodes[i]);
3560 as_fatal (_("internal: can't hash `%s': %s"),
3561 micromips_opcodes[i].name, retval);
3564 struct mips_cl_insn *micromips_nop_insn;
3566 if (!validate_micromips_insn (µmips_opcodes[i],
3567 µmips_operands[i]))
3570 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3572 if (micromips_insn_length (micromips_opcodes + i) == 2)
3573 micromips_nop_insn = µmips_nop16_insn;
3574 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3575 micromips_nop_insn = µmips_nop32_insn;
3579 if (micromips_nop_insn->insn_mo == NULL
3580 && strcmp (name, "nop") == 0)
3582 create_insn (micromips_nop_insn, micromips_opcodes + i);
3583 micromips_nop_insn->fixed_p = 1;
3587 while (++i < bfd_micromips_num_opcodes
3588 && strcmp (micromips_opcodes[i].name, name) == 0);
3592 as_fatal (_("broken assembler, no assembly attempted"));
3594 /* We add all the general register names to the symbol table. This
3595 helps us detect invalid uses of them. */
3596 for (i = 0; reg_names[i].name; i++)
3597 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3598 reg_names[i].num, /* & RNUM_MASK, */
3599 &zero_address_frag));
3601 for (i = 0; reg_names_n32n64[i].name; i++)
3602 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3603 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3604 &zero_address_frag));
3606 for (i = 0; reg_names_o32[i].name; i++)
3607 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3608 reg_names_o32[i].num, /* & RNUM_MASK, */
3609 &zero_address_frag));
3611 for (i = 0; i < 32; i++)
3615 /* R5900 VU0 floating-point register. */
3616 sprintf (regname, "$vf%d", i);
3617 symbol_table_insert (symbol_new (regname, reg_section,
3618 RTYPE_VF | i, &zero_address_frag));
3620 /* R5900 VU0 integer register. */
3621 sprintf (regname, "$vi%d", i);
3622 symbol_table_insert (symbol_new (regname, reg_section,
3623 RTYPE_VI | i, &zero_address_frag));
3626 sprintf (regname, "$w%d", i);
3627 symbol_table_insert (symbol_new (regname, reg_section,
3628 RTYPE_MSA | i, &zero_address_frag));
3631 obstack_init (&mips_operand_tokens);
3633 mips_no_prev_insn ();
3636 mips_cprmask[0] = 0;
3637 mips_cprmask[1] = 0;
3638 mips_cprmask[2] = 0;
3639 mips_cprmask[3] = 0;
3641 /* set the default alignment for the text section (2**2) */
3642 record_alignment (text_section, 2);
3644 bfd_set_gp_size (stdoutput, g_switch_value);
3646 /* On a native system other than VxWorks, sections must be aligned
3647 to 16 byte boundaries. When configured for an embedded ELF
3648 target, we don't bother. */
3649 if (strncmp (TARGET_OS, "elf", 3) != 0
3650 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3652 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3653 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3654 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3657 /* Create a .reginfo section for register masks and a .mdebug
3658 section for debugging information. */
3666 subseg = now_subseg;
3668 /* The ABI says this section should be loaded so that the
3669 running program can access it. However, we don't load it
3670 if we are configured for an embedded target */
3671 flags = SEC_READONLY | SEC_DATA;
3672 if (strncmp (TARGET_OS, "elf", 3) != 0)
3673 flags |= SEC_ALLOC | SEC_LOAD;
3675 if (mips_abi != N64_ABI)
3677 sec = subseg_new (".reginfo", (subsegT) 0);
3679 bfd_set_section_flags (stdoutput, sec, flags);
3680 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3682 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3686 /* The 64-bit ABI uses a .MIPS.options section rather than
3687 .reginfo section. */
3688 sec = subseg_new (".MIPS.options", (subsegT) 0);
3689 bfd_set_section_flags (stdoutput, sec, flags);
3690 bfd_set_section_alignment (stdoutput, sec, 3);
3692 /* Set up the option header. */
3694 Elf_Internal_Options opthdr;
3697 opthdr.kind = ODK_REGINFO;
3698 opthdr.size = (sizeof (Elf_External_Options)
3699 + sizeof (Elf64_External_RegInfo));
3702 f = frag_more (sizeof (Elf_External_Options));
3703 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3704 (Elf_External_Options *) f);
3706 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3710 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3711 bfd_set_section_flags (stdoutput, sec,
3712 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3713 bfd_set_section_alignment (stdoutput, sec, 3);
3714 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3716 if (ECOFF_DEBUGGING)
3718 sec = subseg_new (".mdebug", (subsegT) 0);
3719 (void) bfd_set_section_flags (stdoutput, sec,
3720 SEC_HAS_CONTENTS | SEC_READONLY);
3721 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3723 else if (mips_flag_pdr)
3725 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3726 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3727 SEC_READONLY | SEC_RELOC
3729 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3732 subseg_set (seg, subseg);
3735 if (mips_fix_vr4120)
3736 init_vr4120_conflicts ();
3740 fpabi_incompatible_with (int fpabi, const char *what)
3742 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3743 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3747 fpabi_requires (int fpabi, const char *what)
3749 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3750 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3753 /* Check -mabi and register sizes against the specified FP ABI. */
3755 check_fpabi (int fpabi)
3759 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3760 if (file_mips_opts.soft_float)
3761 fpabi_incompatible_with (fpabi, "softfloat");
3762 else if (file_mips_opts.single_float)
3763 fpabi_incompatible_with (fpabi, "singlefloat");
3764 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3765 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3766 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3767 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3770 case Val_GNU_MIPS_ABI_FP_XX:
3771 if (mips_abi != O32_ABI)
3772 fpabi_requires (fpabi, "-mabi=32");
3773 else if (file_mips_opts.soft_float)
3774 fpabi_incompatible_with (fpabi, "softfloat");
3775 else if (file_mips_opts.single_float)
3776 fpabi_incompatible_with (fpabi, "singlefloat");
3777 else if (file_mips_opts.fp != 0)
3778 fpabi_requires (fpabi, "fp=xx");
3781 case Val_GNU_MIPS_ABI_FP_64A:
3782 case Val_GNU_MIPS_ABI_FP_64:
3783 if (mips_abi != O32_ABI)
3784 fpabi_requires (fpabi, "-mabi=32");
3785 else if (file_mips_opts.soft_float)
3786 fpabi_incompatible_with (fpabi, "softfloat");
3787 else if (file_mips_opts.single_float)
3788 fpabi_incompatible_with (fpabi, "singlefloat");
3789 else if (file_mips_opts.fp != 64)
3790 fpabi_requires (fpabi, "fp=64");
3791 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3792 fpabi_incompatible_with (fpabi, "nooddspreg");
3793 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3794 fpabi_requires (fpabi, "nooddspreg");
3797 case Val_GNU_MIPS_ABI_FP_SINGLE:
3798 if (file_mips_opts.soft_float)
3799 fpabi_incompatible_with (fpabi, "softfloat");
3800 else if (!file_mips_opts.single_float)
3801 fpabi_requires (fpabi, "singlefloat");
3804 case Val_GNU_MIPS_ABI_FP_SOFT:
3805 if (!file_mips_opts.soft_float)
3806 fpabi_requires (fpabi, "softfloat");
3809 case Val_GNU_MIPS_ABI_FP_OLD_64:
3810 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3811 Tag_GNU_MIPS_ABI_FP, fpabi);
3814 case Val_GNU_MIPS_ABI_FP_NAN2008:
3815 /* Silently ignore compatibility value. */
3819 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3820 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3825 /* Perform consistency checks on the current options. */
3828 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3830 /* Check the size of integer registers agrees with the ABI and ISA. */
3831 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3832 as_bad (_("`gp=64' used with a 32-bit processor"));
3834 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3835 as_bad (_("`gp=32' used with a 64-bit ABI"));
3837 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3838 as_bad (_("`gp=64' used with a 32-bit ABI"));
3840 /* Check the size of the float registers agrees with the ABI and ISA. */
3844 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3845 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3846 else if (opts->single_float == 1)
3847 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3850 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3851 as_bad (_("`fp=64' used with a 32-bit fpu"));
3853 && ABI_NEEDS_32BIT_REGS (mips_abi)
3854 && !ISA_HAS_MXHC1 (opts->isa))
3855 as_warn (_("`fp=64' used with a 32-bit ABI"));
3859 && ABI_NEEDS_64BIT_REGS (mips_abi))
3860 as_warn (_("`fp=32' used with a 64-bit ABI"));
3861 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3862 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3865 as_bad (_("Unknown size of floating point registers"));
3869 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3870 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3872 if (opts->micromips == 1 && opts->mips16 == 1)
3873 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3874 else if (ISA_IS_R6 (opts->isa)
3875 && (opts->micromips == 1
3876 || opts->mips16 == 1))
3877 as_fatal (_("`%s' cannot be used with `%s'"),
3878 opts->micromips ? "micromips" : "mips16",
3879 mips_cpu_info_from_isa (opts->isa)->name);
3881 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3882 as_fatal (_("branch relaxation is not supported in `%s'"),
3883 mips_cpu_info_from_isa (opts->isa)->name);
3886 /* Perform consistency checks on the module level options exactly once.
3887 This is a deferred check that happens:
3888 at the first .set directive
3889 or, at the first pseudo op that generates code (inc .dc.a)
3890 or, at the first instruction
3894 file_mips_check_options (void)
3896 const struct mips_cpu_info *arch_info = 0;
3898 if (file_mips_opts_checked)
3901 /* The following code determines the register size.
3902 Similar code was added to GCC 3.3 (see override_options() in
3903 config/mips/mips.c). The GAS and GCC code should be kept in sync
3904 as much as possible. */
3906 if (file_mips_opts.gp < 0)
3908 /* Infer the integer register size from the ABI and processor.
3909 Restrict ourselves to 32-bit registers if that's all the
3910 processor has, or if the ABI cannot handle 64-bit registers. */
3911 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3912 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3916 if (file_mips_opts.fp < 0)
3918 /* No user specified float register size.
3919 ??? GAS treats single-float processors as though they had 64-bit
3920 float registers (although it complains when double-precision
3921 instructions are used). As things stand, saying they have 32-bit
3922 registers would lead to spurious "register must be even" messages.
3923 So here we assume float registers are never smaller than the
3925 if (file_mips_opts.gp == 64)
3926 /* 64-bit integer registers implies 64-bit float registers. */
3927 file_mips_opts.fp = 64;
3928 else if ((file_mips_opts.ase & FP64_ASES)
3929 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3930 /* Handle ASEs that require 64-bit float registers, if possible. */
3931 file_mips_opts.fp = 64;
3932 else if (ISA_IS_R6 (mips_opts.isa))
3933 /* R6 implies 64-bit float registers. */
3934 file_mips_opts.fp = 64;
3936 /* 32-bit float registers. */
3937 file_mips_opts.fp = 32;
3940 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3942 /* Disable operations on odd-numbered floating-point registers by default
3943 when using the FPXX ABI. */
3944 if (file_mips_opts.oddspreg < 0)
3946 if (file_mips_opts.fp == 0)
3947 file_mips_opts.oddspreg = 0;
3949 file_mips_opts.oddspreg = 1;
3952 /* End of GCC-shared inference code. */
3954 /* This flag is set when we have a 64-bit capable CPU but use only
3955 32-bit wide registers. Note that EABI does not use it. */
3956 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3957 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3958 || mips_abi == O32_ABI))
3961 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3962 as_bad (_("trap exception not supported at ISA 1"));
3964 /* If the selected architecture includes support for ASEs, enable
3965 generation of code for them. */
3966 if (file_mips_opts.mips16 == -1)
3967 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3968 if (file_mips_opts.micromips == -1)
3969 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3972 if (mips_nan2008 == -1)
3973 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3974 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3975 as_fatal (_("`%s' does not support legacy NaN"),
3976 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3978 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3979 being selected implicitly. */
3980 if (file_mips_opts.fp != 64)
3981 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3983 /* If the user didn't explicitly select or deselect a particular ASE,
3984 use the default setting for the CPU. */
3985 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3987 /* Set up the current options. These may change throughout assembly. */
3988 mips_opts = file_mips_opts;
3990 mips_check_isa_supports_ases ();
3991 mips_check_options (&file_mips_opts, TRUE);
3992 file_mips_opts_checked = TRUE;
3994 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3995 as_warn (_("could not set architecture and machine"));
3999 md_assemble (char *str)
4001 struct mips_cl_insn insn;
4002 bfd_reloc_code_real_type unused_reloc[3]
4003 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4005 file_mips_check_options ();
4007 imm_expr.X_op = O_absent;
4008 offset_expr.X_op = O_absent;
4009 offset_reloc[0] = BFD_RELOC_UNUSED;
4010 offset_reloc[1] = BFD_RELOC_UNUSED;
4011 offset_reloc[2] = BFD_RELOC_UNUSED;
4013 mips_mark_labels ();
4014 mips_assembling_insn = TRUE;
4015 clear_insn_error ();
4017 if (mips_opts.mips16)
4018 mips16_ip (str, &insn);
4021 mips_ip (str, &insn);
4022 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4023 str, insn.insn_opcode));
4027 report_insn_error (str);
4028 else if (insn.insn_mo->pinfo == INSN_MACRO)
4031 if (mips_opts.mips16)
4032 mips16_macro (&insn);
4039 if (offset_expr.X_op != O_absent)
4040 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4042 append_insn (&insn, NULL, unused_reloc, FALSE);
4045 mips_assembling_insn = FALSE;
4048 /* Convenience functions for abstracting away the differences between
4049 MIPS16 and non-MIPS16 relocations. */
4051 static inline bfd_boolean
4052 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4056 case BFD_RELOC_MIPS16_JMP:
4057 case BFD_RELOC_MIPS16_GPREL:
4058 case BFD_RELOC_MIPS16_GOT16:
4059 case BFD_RELOC_MIPS16_CALL16:
4060 case BFD_RELOC_MIPS16_HI16_S:
4061 case BFD_RELOC_MIPS16_HI16:
4062 case BFD_RELOC_MIPS16_LO16:
4070 static inline bfd_boolean
4071 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4075 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4076 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4077 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4078 case BFD_RELOC_MICROMIPS_GPREL16:
4079 case BFD_RELOC_MICROMIPS_JMP:
4080 case BFD_RELOC_MICROMIPS_HI16:
4081 case BFD_RELOC_MICROMIPS_HI16_S:
4082 case BFD_RELOC_MICROMIPS_LO16:
4083 case BFD_RELOC_MICROMIPS_LITERAL:
4084 case BFD_RELOC_MICROMIPS_GOT16:
4085 case BFD_RELOC_MICROMIPS_CALL16:
4086 case BFD_RELOC_MICROMIPS_GOT_HI16:
4087 case BFD_RELOC_MICROMIPS_GOT_LO16:
4088 case BFD_RELOC_MICROMIPS_CALL_HI16:
4089 case BFD_RELOC_MICROMIPS_CALL_LO16:
4090 case BFD_RELOC_MICROMIPS_SUB:
4091 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4092 case BFD_RELOC_MICROMIPS_GOT_OFST:
4093 case BFD_RELOC_MICROMIPS_GOT_DISP:
4094 case BFD_RELOC_MICROMIPS_HIGHEST:
4095 case BFD_RELOC_MICROMIPS_HIGHER:
4096 case BFD_RELOC_MICROMIPS_SCN_DISP:
4097 case BFD_RELOC_MICROMIPS_JALR:
4105 static inline bfd_boolean
4106 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4108 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4111 static inline bfd_boolean
4112 b_reloc_p (bfd_reloc_code_real_type reloc)
4114 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4115 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4116 || reloc == BFD_RELOC_16_PCREL_S2
4117 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4118 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4119 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4122 static inline bfd_boolean
4123 got16_reloc_p (bfd_reloc_code_real_type reloc)
4125 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4126 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4129 static inline bfd_boolean
4130 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4132 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4133 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4136 static inline bfd_boolean
4137 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4139 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4140 || reloc == BFD_RELOC_MICROMIPS_LO16);
4143 static inline bfd_boolean
4144 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4146 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4149 static inline bfd_boolean
4150 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4152 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4153 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4156 /* Return true if RELOC is a PC-relative relocation that does not have
4157 full address range. */
4159 static inline bfd_boolean
4160 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4164 case BFD_RELOC_16_PCREL_S2:
4165 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4166 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4167 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4168 case BFD_RELOC_MIPS_21_PCREL_S2:
4169 case BFD_RELOC_MIPS_26_PCREL_S2:
4170 case BFD_RELOC_MIPS_18_PCREL_S3:
4171 case BFD_RELOC_MIPS_19_PCREL_S2:
4174 case BFD_RELOC_32_PCREL:
4175 case BFD_RELOC_HI16_S_PCREL:
4176 case BFD_RELOC_LO16_PCREL:
4177 return HAVE_64BIT_ADDRESSES;
4184 /* Return true if the given relocation might need a matching %lo().
4185 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4186 need a matching %lo() when applied to local symbols. */
4188 static inline bfd_boolean
4189 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4191 return (HAVE_IN_PLACE_ADDENDS
4192 && (hi16_reloc_p (reloc)
4193 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4194 all GOT16 relocations evaluate to "G". */
4195 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4198 /* Return the type of %lo() reloc needed by RELOC, given that
4199 reloc_needs_lo_p. */
4201 static inline bfd_reloc_code_real_type
4202 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4204 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4205 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4209 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4212 static inline bfd_boolean
4213 fixup_has_matching_lo_p (fixS *fixp)
4215 return (fixp->fx_next != NULL
4216 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4217 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4218 && fixp->fx_offset == fixp->fx_next->fx_offset);
4221 /* Move all labels in LABELS to the current insertion point. TEXT_P
4222 says whether the labels refer to text or data. */
4225 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4227 struct insn_label_list *l;
4230 for (l = labels; l != NULL; l = l->next)
4232 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4233 symbol_set_frag (l->label, frag_now);
4234 val = (valueT) frag_now_fix ();
4235 /* MIPS16/microMIPS text labels are stored as odd. */
4236 if (text_p && HAVE_CODE_COMPRESSION)
4238 S_SET_VALUE (l->label, val);
4242 /* Move all labels in insn_labels to the current insertion point
4243 and treat them as text labels. */
4246 mips_move_text_labels (void)
4248 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4252 s_is_linkonce (symbolS *sym, segT from_seg)
4254 bfd_boolean linkonce = FALSE;
4255 segT symseg = S_GET_SEGMENT (sym);
4257 if (symseg != from_seg && !S_IS_LOCAL (sym))
4259 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4261 /* The GNU toolchain uses an extension for ELF: a section
4262 beginning with the magic string .gnu.linkonce is a
4263 linkonce section. */
4264 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4265 sizeof ".gnu.linkonce" - 1) == 0)
4271 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4272 linker to handle them specially, such as generating jalx instructions
4273 when needed. We also make them odd for the duration of the assembly,
4274 in order to generate the right sort of code. We will make them even
4275 in the adjust_symtab routine, while leaving them marked. This is
4276 convenient for the debugger and the disassembler. The linker knows
4277 to make them odd again. */
4280 mips_compressed_mark_label (symbolS *label)
4282 gas_assert (HAVE_CODE_COMPRESSION);
4284 if (mips_opts.mips16)
4285 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4287 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4288 if ((S_GET_VALUE (label) & 1) == 0
4289 /* Don't adjust the address if the label is global or weak, or
4290 in a link-once section, since we'll be emitting symbol reloc
4291 references to it which will be patched up by the linker, and
4292 the final value of the symbol may or may not be MIPS16/microMIPS. */
4293 && !S_IS_WEAK (label)
4294 && !S_IS_EXTERNAL (label)
4295 && !s_is_linkonce (label, now_seg))
4296 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4299 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4302 mips_compressed_mark_labels (void)
4304 struct insn_label_list *l;
4306 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4307 mips_compressed_mark_label (l->label);
4310 /* End the current frag. Make it a variant frag and record the
4314 relax_close_frag (void)
4316 mips_macro_warning.first_frag = frag_now;
4317 frag_var (rs_machine_dependent, 0, 0,
4318 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4319 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4321 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4322 mips_relax.first_fixup = 0;
4325 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4326 See the comment above RELAX_ENCODE for more details. */
4329 relax_start (symbolS *symbol)
4331 gas_assert (mips_relax.sequence == 0);
4332 mips_relax.sequence = 1;
4333 mips_relax.symbol = symbol;
4336 /* Start generating the second version of a relaxable sequence.
4337 See the comment above RELAX_ENCODE for more details. */
4342 gas_assert (mips_relax.sequence == 1);
4343 mips_relax.sequence = 2;
4346 /* End the current relaxable sequence. */
4351 gas_assert (mips_relax.sequence == 2);
4352 relax_close_frag ();
4353 mips_relax.sequence = 0;
4356 /* Return true if IP is a delayed branch or jump. */
4358 static inline bfd_boolean
4359 delayed_branch_p (const struct mips_cl_insn *ip)
4361 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4362 | INSN_COND_BRANCH_DELAY
4363 | INSN_COND_BRANCH_LIKELY)) != 0;
4366 /* Return true if IP is a compact branch or jump. */
4368 static inline bfd_boolean
4369 compact_branch_p (const struct mips_cl_insn *ip)
4371 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4372 | INSN2_COND_BRANCH)) != 0;
4375 /* Return true if IP is an unconditional branch or jump. */
4377 static inline bfd_boolean
4378 uncond_branch_p (const struct mips_cl_insn *ip)
4380 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4381 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4384 /* Return true if IP is a branch-likely instruction. */
4386 static inline bfd_boolean
4387 branch_likely_p (const struct mips_cl_insn *ip)
4389 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4392 /* Return the type of nop that should be used to fill the delay slot
4393 of delayed branch IP. */
4395 static struct mips_cl_insn *
4396 get_delay_slot_nop (const struct mips_cl_insn *ip)
4398 if (mips_opts.micromips
4399 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4400 return µmips_nop32_insn;
4404 /* Return a mask that has bit N set if OPCODE reads the register(s)
4408 insn_read_mask (const struct mips_opcode *opcode)
4410 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4413 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4417 insn_write_mask (const struct mips_opcode *opcode)
4419 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4422 /* Return a mask of the registers specified by operand OPERAND of INSN.
4423 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4427 operand_reg_mask (const struct mips_cl_insn *insn,
4428 const struct mips_operand *operand,
4429 unsigned int type_mask)
4431 unsigned int uval, vsel;
4433 switch (operand->type)
4440 case OP_ADDIUSP_INT:
4441 case OP_ENTRY_EXIT_LIST:
4442 case OP_REPEAT_DEST_REG:
4443 case OP_REPEAT_PREV_REG:
4446 case OP_VU0_MATCH_SUFFIX:
4451 case OP_OPTIONAL_REG:
4453 const struct mips_reg_operand *reg_op;
4455 reg_op = (const struct mips_reg_operand *) operand;
4456 if (!(type_mask & (1 << reg_op->reg_type)))
4458 uval = insn_extract_operand (insn, operand);
4459 return 1 << mips_decode_reg_operand (reg_op, uval);
4464 const struct mips_reg_pair_operand *pair_op;
4466 pair_op = (const struct mips_reg_pair_operand *) operand;
4467 if (!(type_mask & (1 << pair_op->reg_type)))
4469 uval = insn_extract_operand (insn, operand);
4470 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4473 case OP_CLO_CLZ_DEST:
4474 if (!(type_mask & (1 << OP_REG_GP)))
4476 uval = insn_extract_operand (insn, operand);
4477 return (1 << (uval & 31)) | (1 << (uval >> 5));
4480 if (!(type_mask & (1 << OP_REG_GP)))
4482 uval = insn_extract_operand (insn, operand);
4483 gas_assert ((uval & 31) == (uval >> 5));
4484 return 1 << (uval & 31);
4487 case OP_NON_ZERO_REG:
4488 if (!(type_mask & (1 << OP_REG_GP)))
4490 uval = insn_extract_operand (insn, operand);
4491 return 1 << (uval & 31);
4493 case OP_LWM_SWM_LIST:
4496 case OP_SAVE_RESTORE_LIST:
4499 case OP_MDMX_IMM_REG:
4500 if (!(type_mask & (1 << OP_REG_VEC)))
4502 uval = insn_extract_operand (insn, operand);
4504 if ((vsel & 0x18) == 0x18)
4506 return 1 << (uval & 31);
4509 if (!(type_mask & (1 << OP_REG_GP)))
4511 return 1 << insn_extract_operand (insn, operand);
4516 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4517 where bit N of OPNO_MASK is set if operand N should be included.
4518 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4522 insn_reg_mask (const struct mips_cl_insn *insn,
4523 unsigned int type_mask, unsigned int opno_mask)
4525 unsigned int opno, reg_mask;
4529 while (opno_mask != 0)
4532 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4539 /* Return the mask of core registers that IP reads. */
4542 gpr_read_mask (const struct mips_cl_insn *ip)
4544 unsigned long pinfo, pinfo2;
4547 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4548 pinfo = ip->insn_mo->pinfo;
4549 pinfo2 = ip->insn_mo->pinfo2;
4550 if (pinfo & INSN_UDI)
4552 /* UDI instructions have traditionally been assumed to read RS
4554 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4555 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4557 if (pinfo & INSN_READ_GPR_24)
4559 if (pinfo2 & INSN2_READ_GPR_16)
4561 if (pinfo2 & INSN2_READ_SP)
4563 if (pinfo2 & INSN2_READ_GPR_31)
4565 /* Don't include register 0. */
4569 /* Return the mask of core registers that IP writes. */
4572 gpr_write_mask (const struct mips_cl_insn *ip)
4574 unsigned long pinfo, pinfo2;
4577 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4578 pinfo = ip->insn_mo->pinfo;
4579 pinfo2 = ip->insn_mo->pinfo2;
4580 if (pinfo & INSN_WRITE_GPR_24)
4582 if (pinfo & INSN_WRITE_GPR_31)
4584 if (pinfo & INSN_UDI)
4585 /* UDI instructions have traditionally been assumed to write to RD. */
4586 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4587 if (pinfo2 & INSN2_WRITE_SP)
4589 /* Don't include register 0. */
4593 /* Return the mask of floating-point registers that IP reads. */
4596 fpr_read_mask (const struct mips_cl_insn *ip)
4598 unsigned long pinfo;
4601 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4602 | (1 << OP_REG_MSA)),
4603 insn_read_mask (ip->insn_mo));
4604 pinfo = ip->insn_mo->pinfo;
4605 /* Conservatively treat all operands to an FP_D instruction are doubles.
4606 (This is overly pessimistic for things like cvt.d.s.) */
4607 if (FPR_SIZE != 64 && (pinfo & FP_D))
4612 /* Return the mask of floating-point registers that IP writes. */
4615 fpr_write_mask (const struct mips_cl_insn *ip)
4617 unsigned long pinfo;
4620 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4621 | (1 << OP_REG_MSA)),
4622 insn_write_mask (ip->insn_mo));
4623 pinfo = ip->insn_mo->pinfo;
4624 /* Conservatively treat all operands to an FP_D instruction are doubles.
4625 (This is overly pessimistic for things like cvt.s.d.) */
4626 if (FPR_SIZE != 64 && (pinfo & FP_D))
4631 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4632 Check whether that is allowed. */
4635 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4637 const char *s = insn->name;
4638 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4640 && mips_opts.oddspreg;
4642 if (insn->pinfo == INSN_MACRO)
4643 /* Let a macro pass, we'll catch it later when it is expanded. */
4646 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4647 otherwise it depends on oddspreg. */
4648 if ((insn->pinfo & FP_S)
4649 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4650 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4651 return FPR_SIZE == 32 || oddspreg;
4653 /* Allow odd registers for single-precision ops and double-precision if the
4654 floating-point registers are 64-bit wide. */
4655 switch (insn->pinfo & (FP_S | FP_D))
4661 return FPR_SIZE == 64;
4666 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4667 s = strchr (insn->name, '.');
4668 if (s != NULL && opnum == 2)
4669 s = strchr (s + 1, '.');
4670 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4673 return FPR_SIZE == 64;
4676 /* Information about an instruction argument that we're trying to match. */
4677 struct mips_arg_info
4679 /* The instruction so far. */
4680 struct mips_cl_insn *insn;
4682 /* The first unconsumed operand token. */
4683 struct mips_operand_token *token;
4685 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4688 /* The 1-based argument number, for error reporting. This does not
4689 count elided optional registers, etc.. */
4692 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4693 unsigned int last_regno;
4695 /* If the first operand was an OP_REG, this is the register that it
4696 specified, otherwise it is ILLEGAL_REG. */
4697 unsigned int dest_regno;
4699 /* The value of the last OP_INT operand. Only used for OP_MSB,
4700 where it gives the lsb position. */
4701 unsigned int last_op_int;
4703 /* If true, match routines should assume that no later instruction
4704 alternative matches and should therefore be as accomodating as
4705 possible. Match routines should not report errors if something
4706 is only invalid for !LAX_MATCH. */
4707 bfd_boolean lax_match;
4709 /* True if a reference to the current AT register was seen. */
4710 bfd_boolean seen_at;
4713 /* Record that the argument is out of range. */
4716 match_out_of_range (struct mips_arg_info *arg)
4718 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4721 /* Record that the argument isn't constant but needs to be. */
4724 match_not_constant (struct mips_arg_info *arg)
4726 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4730 /* Try to match an OT_CHAR token for character CH. Consume the token
4731 and return true on success, otherwise return false. */
4734 match_char (struct mips_arg_info *arg, char ch)
4736 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4746 /* Try to get an expression from the next tokens in ARG. Consume the
4747 tokens and return true on success, storing the expression value in
4748 VALUE and relocation types in R. */
4751 match_expression (struct mips_arg_info *arg, expressionS *value,
4752 bfd_reloc_code_real_type *r)
4754 /* If the next token is a '(' that was parsed as being part of a base
4755 expression, assume we have an elided offset. The later match will fail
4756 if this turns out to be wrong. */
4757 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4759 value->X_op = O_constant;
4760 value->X_add_number = 0;
4761 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4765 /* Reject register-based expressions such as "0+$2" and "(($2))".
4766 For plain registers the default error seems more appropriate. */
4767 if (arg->token->type == OT_INTEGER
4768 && arg->token->u.integer.value.X_op == O_register)
4770 set_insn_error (arg->argnum, _("register value used as expression"));
4774 if (arg->token->type == OT_INTEGER)
4776 *value = arg->token->u.integer.value;
4777 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4783 (arg->argnum, _("operand %d must be an immediate expression"),
4788 /* Try to get a constant expression from the next tokens in ARG. Consume
4789 the tokens and return return true on success, storing the constant value
4790 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4794 match_const_int (struct mips_arg_info *arg, offsetT *value)
4797 bfd_reloc_code_real_type r[3];
4799 if (!match_expression (arg, &ex, r))
4802 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4803 *value = ex.X_add_number;
4806 match_not_constant (arg);
4812 /* Return the RTYPE_* flags for a register operand of type TYPE that
4813 appears in instruction OPCODE. */
4816 convert_reg_type (const struct mips_opcode *opcode,
4817 enum mips_reg_operand_type type)
4822 return RTYPE_NUM | RTYPE_GP;
4825 /* Allow vector register names for MDMX if the instruction is a 64-bit
4826 FPR load, store or move (including moves to and from GPRs). */
4827 if ((mips_opts.ase & ASE_MDMX)
4828 && (opcode->pinfo & FP_D)
4829 && (opcode->pinfo & (INSN_COPROC_MOVE
4830 | INSN_COPROC_MEMORY_DELAY
4833 | INSN_STORE_MEMORY)))
4834 return RTYPE_FPU | RTYPE_VEC;
4838 if (opcode->pinfo & (FP_D | FP_S))
4839 return RTYPE_CCC | RTYPE_FCC;
4843 if (opcode->membership & INSN_5400)
4845 return RTYPE_FPU | RTYPE_VEC;
4851 if (opcode->name[strlen (opcode->name) - 1] == '0')
4852 return RTYPE_NUM | RTYPE_CP0;
4859 return RTYPE_NUM | RTYPE_VI;
4862 return RTYPE_NUM | RTYPE_VF;
4864 case OP_REG_R5900_I:
4865 return RTYPE_R5900_I;
4867 case OP_REG_R5900_Q:
4868 return RTYPE_R5900_Q;
4870 case OP_REG_R5900_R:
4871 return RTYPE_R5900_R;
4873 case OP_REG_R5900_ACC:
4874 return RTYPE_R5900_ACC;
4879 case OP_REG_MSA_CTRL:
4885 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4888 check_regno (struct mips_arg_info *arg,
4889 enum mips_reg_operand_type type, unsigned int regno)
4891 if (AT && type == OP_REG_GP && regno == AT)
4892 arg->seen_at = TRUE;
4894 if (type == OP_REG_FP
4896 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4898 /* This was a warning prior to introducing O32 FPXX and FP64 support
4899 so maintain a warning for FP32 but raise an error for the new
4902 as_warn (_("float register should be even, was %d"), regno);
4904 as_bad (_("float register should be even, was %d"), regno);
4907 if (type == OP_REG_CCC)
4912 name = arg->insn->insn_mo->name;
4913 length = strlen (name);
4914 if ((regno & 1) != 0
4915 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4916 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4917 as_warn (_("condition code register should be even for %s, was %d"),
4920 if ((regno & 3) != 0
4921 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4922 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4927 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4928 a register of type TYPE. Return true on success, storing the register
4929 number in *REGNO and warning about any dubious uses. */
4932 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4933 unsigned int symval, unsigned int *regno)
4935 if (type == OP_REG_VEC)
4936 symval = mips_prefer_vec_regno (symval);
4937 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4940 *regno = symval & RNUM_MASK;
4941 check_regno (arg, type, *regno);
4945 /* Try to interpret the next token in ARG as a register of type TYPE.
4946 Consume the token and return true on success, storing the register
4947 number in *REGNO. Return false on failure. */
4950 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4951 unsigned int *regno)
4953 if (arg->token->type == OT_REG
4954 && match_regno (arg, type, arg->token->u.regno, regno))
4962 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4963 Consume the token and return true on success, storing the register numbers
4964 in *REGNO1 and *REGNO2. Return false on failure. */
4967 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4968 unsigned int *regno1, unsigned int *regno2)
4970 if (match_reg (arg, type, regno1))
4975 if (arg->token->type == OT_REG_RANGE
4976 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4977 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4978 && *regno1 <= *regno2)
4986 /* OP_INT matcher. */
4989 match_int_operand (struct mips_arg_info *arg,
4990 const struct mips_operand *operand_base)
4992 const struct mips_int_operand *operand;
4994 int min_val, max_val, factor;
4997 operand = (const struct mips_int_operand *) operand_base;
4998 factor = 1 << operand->shift;
4999 min_val = mips_int_operand_min (operand);
5000 max_val = mips_int_operand_max (operand);
5002 if (operand_base->lsb == 0
5003 && operand_base->size == 16
5004 && operand->shift == 0
5005 && operand->bias == 0
5006 && (operand->max_val == 32767 || operand->max_val == 65535))
5008 /* The operand can be relocated. */
5009 if (!match_expression (arg, &offset_expr, offset_reloc))
5012 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5013 /* Relocation operators were used. Accept the arguent and
5014 leave the relocation value in offset_expr and offset_relocs
5015 for the caller to process. */
5018 if (offset_expr.X_op != O_constant)
5020 /* Accept non-constant operands if no later alternative matches,
5021 leaving it for the caller to process. */
5022 if (!arg->lax_match)
5024 offset_reloc[0] = BFD_RELOC_LO16;
5028 /* Clear the global state; we're going to install the operand
5030 sval = offset_expr.X_add_number;
5031 offset_expr.X_op = O_absent;
5033 /* For compatibility with older assemblers, we accept
5034 0x8000-0xffff as signed 16-bit numbers when only
5035 signed numbers are allowed. */
5038 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5039 if (!arg->lax_match && sval <= max_val)
5045 if (!match_const_int (arg, &sval))
5049 arg->last_op_int = sval;
5051 if (sval < min_val || sval > max_val || sval % factor)
5053 match_out_of_range (arg);
5057 uval = (unsigned int) sval >> operand->shift;
5058 uval -= operand->bias;
5060 /* Handle -mfix-cn63xxp1. */
5062 && mips_fix_cn63xxp1
5063 && !mips_opts.micromips
5064 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5079 /* The rest must be changed to 28. */
5084 insn_insert_operand (arg->insn, operand_base, uval);
5088 /* OP_MAPPED_INT matcher. */
5091 match_mapped_int_operand (struct mips_arg_info *arg,
5092 const struct mips_operand *operand_base)
5094 const struct mips_mapped_int_operand *operand;
5095 unsigned int uval, num_vals;
5098 operand = (const struct mips_mapped_int_operand *) operand_base;
5099 if (!match_const_int (arg, &sval))
5102 num_vals = 1 << operand_base->size;
5103 for (uval = 0; uval < num_vals; uval++)
5104 if (operand->int_map[uval] == sval)
5106 if (uval == num_vals)
5108 match_out_of_range (arg);
5112 insn_insert_operand (arg->insn, operand_base, uval);
5116 /* OP_MSB matcher. */
5119 match_msb_operand (struct mips_arg_info *arg,
5120 const struct mips_operand *operand_base)
5122 const struct mips_msb_operand *operand;
5123 int min_val, max_val, max_high;
5124 offsetT size, sval, high;
5126 operand = (const struct mips_msb_operand *) operand_base;
5127 min_val = operand->bias;
5128 max_val = min_val + (1 << operand_base->size) - 1;
5129 max_high = operand->opsize;
5131 if (!match_const_int (arg, &size))
5134 high = size + arg->last_op_int;
5135 sval = operand->add_lsb ? high : size;
5137 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5139 match_out_of_range (arg);
5142 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5146 /* OP_REG matcher. */
5149 match_reg_operand (struct mips_arg_info *arg,
5150 const struct mips_operand *operand_base)
5152 const struct mips_reg_operand *operand;
5153 unsigned int regno, uval, num_vals;
5155 operand = (const struct mips_reg_operand *) operand_base;
5156 if (!match_reg (arg, operand->reg_type, ®no))
5159 if (operand->reg_map)
5161 num_vals = 1 << operand->root.size;
5162 for (uval = 0; uval < num_vals; uval++)
5163 if (operand->reg_map[uval] == regno)
5165 if (num_vals == uval)
5171 arg->last_regno = regno;
5172 if (arg->opnum == 1)
5173 arg->dest_regno = regno;
5174 insn_insert_operand (arg->insn, operand_base, uval);
5178 /* OP_REG_PAIR matcher. */
5181 match_reg_pair_operand (struct mips_arg_info *arg,
5182 const struct mips_operand *operand_base)
5184 const struct mips_reg_pair_operand *operand;
5185 unsigned int regno1, regno2, uval, num_vals;
5187 operand = (const struct mips_reg_pair_operand *) operand_base;
5188 if (!match_reg (arg, operand->reg_type, ®no1)
5189 || !match_char (arg, ',')
5190 || !match_reg (arg, operand->reg_type, ®no2))
5193 num_vals = 1 << operand_base->size;
5194 for (uval = 0; uval < num_vals; uval++)
5195 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5197 if (uval == num_vals)
5200 insn_insert_operand (arg->insn, operand_base, uval);
5204 /* OP_PCREL matcher. The caller chooses the relocation type. */
5207 match_pcrel_operand (struct mips_arg_info *arg)
5209 bfd_reloc_code_real_type r[3];
5211 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5214 /* OP_PERF_REG matcher. */
5217 match_perf_reg_operand (struct mips_arg_info *arg,
5218 const struct mips_operand *operand)
5222 if (!match_const_int (arg, &sval))
5227 || (mips_opts.arch == CPU_R5900
5228 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5229 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5231 set_insn_error (arg->argnum, _("invalid performance register"));
5235 insn_insert_operand (arg->insn, operand, sval);
5239 /* OP_ADDIUSP matcher. */
5242 match_addiusp_operand (struct mips_arg_info *arg,
5243 const struct mips_operand *operand)
5248 if (!match_const_int (arg, &sval))
5253 match_out_of_range (arg);
5258 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5260 match_out_of_range (arg);
5264 uval = (unsigned int) sval;
5265 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5266 insn_insert_operand (arg->insn, operand, uval);
5270 /* OP_CLO_CLZ_DEST matcher. */
5273 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5274 const struct mips_operand *operand)
5278 if (!match_reg (arg, OP_REG_GP, ®no))
5281 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5285 /* OP_CHECK_PREV matcher. */
5288 match_check_prev_operand (struct mips_arg_info *arg,
5289 const struct mips_operand *operand_base)
5291 const struct mips_check_prev_operand *operand;
5294 operand = (const struct mips_check_prev_operand *) operand_base;
5296 if (!match_reg (arg, OP_REG_GP, ®no))
5299 if (!operand->zero_ok && regno == 0)
5302 if ((operand->less_than_ok && regno < arg->last_regno)
5303 || (operand->greater_than_ok && regno > arg->last_regno)
5304 || (operand->equal_ok && regno == arg->last_regno))
5306 arg->last_regno = regno;
5307 insn_insert_operand (arg->insn, operand_base, regno);
5314 /* OP_SAME_RS_RT matcher. */
5317 match_same_rs_rt_operand (struct mips_arg_info *arg,
5318 const struct mips_operand *operand)
5322 if (!match_reg (arg, OP_REG_GP, ®no))
5327 set_insn_error (arg->argnum, _("the source register must not be $0"));
5331 arg->last_regno = regno;
5333 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5337 /* OP_LWM_SWM_LIST matcher. */
5340 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5341 const struct mips_operand *operand)
5343 unsigned int reglist, sregs, ra, regno1, regno2;
5344 struct mips_arg_info reset;
5347 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5351 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5356 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5359 while (match_char (arg, ',')
5360 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5363 if (operand->size == 2)
5365 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5371 and any permutations of these. */
5372 if ((reglist & 0xfff1ffff) != 0x80010000)
5375 sregs = (reglist >> 17) & 7;
5380 /* The list must include at least one of ra and s0-sN,
5381 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5382 which are $23 and $30 respectively.) E.g.:
5390 and any permutations of these. */
5391 if ((reglist & 0x3f00ffff) != 0)
5394 ra = (reglist >> 27) & 0x10;
5395 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5398 if ((sregs & -sregs) != sregs)
5401 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5405 /* OP_ENTRY_EXIT_LIST matcher. */
5408 match_entry_exit_operand (struct mips_arg_info *arg,
5409 const struct mips_operand *operand)
5412 bfd_boolean is_exit;
5414 /* The format is the same for both ENTRY and EXIT, but the constraints
5416 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5417 mask = (is_exit ? 7 << 3 : 0);
5420 unsigned int regno1, regno2;
5421 bfd_boolean is_freg;
5423 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5425 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5430 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5433 mask |= (5 + regno2) << 3;
5435 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5436 mask |= (regno2 - 3) << 3;
5437 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5438 mask |= (regno2 - 15) << 1;
5439 else if (regno1 == RA && regno2 == RA)
5444 while (match_char (arg, ','));
5446 insn_insert_operand (arg->insn, operand, mask);
5450 /* OP_SAVE_RESTORE_LIST matcher. */
5453 match_save_restore_list_operand (struct mips_arg_info *arg)
5455 unsigned int opcode, args, statics, sregs;
5456 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5459 opcode = arg->insn->insn_opcode;
5461 num_frame_sizes = 0;
5467 unsigned int regno1, regno2;
5469 if (arg->token->type == OT_INTEGER)
5471 /* Handle the frame size. */
5472 if (!match_const_int (arg, &frame_size))
5474 num_frame_sizes += 1;
5478 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5481 while (regno1 <= regno2)
5483 if (regno1 >= 4 && regno1 <= 7)
5485 if (num_frame_sizes == 0)
5487 args |= 1 << (regno1 - 4);
5489 /* statics $a0-$a3 */
5490 statics |= 1 << (regno1 - 4);
5492 else if (regno1 >= 16 && regno1 <= 23)
5494 sregs |= 1 << (regno1 - 16);
5495 else if (regno1 == 30)
5498 else if (regno1 == 31)
5499 /* Add $ra to insn. */
5509 while (match_char (arg, ','));
5511 /* Encode args/statics combination. */
5514 else if (args == 0xf)
5515 /* All $a0-$a3 are args. */
5516 opcode |= MIPS16_ALL_ARGS << 16;
5517 else if (statics == 0xf)
5518 /* All $a0-$a3 are statics. */
5519 opcode |= MIPS16_ALL_STATICS << 16;
5522 /* Count arg registers. */
5532 /* Count static registers. */
5534 while (statics & 0x8)
5536 statics = (statics << 1) & 0xf;
5542 /* Encode args/statics. */
5543 opcode |= ((num_args << 2) | num_statics) << 16;
5546 /* Encode $s0/$s1. */
5547 if (sregs & (1 << 0)) /* $s0 */
5549 if (sregs & (1 << 1)) /* $s1 */
5553 /* Encode $s2-$s8. */
5562 opcode |= num_sregs << 24;
5564 /* Encode frame size. */
5565 if (num_frame_sizes == 0)
5567 set_insn_error (arg->argnum, _("missing frame size"));
5570 if (num_frame_sizes > 1)
5572 set_insn_error (arg->argnum, _("frame size specified twice"));
5575 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5577 set_insn_error (arg->argnum, _("invalid frame size"));
5580 if (frame_size != 128 || (opcode >> 16) != 0)
5583 opcode |= (((frame_size & 0xf0) << 16)
5584 | (frame_size & 0x0f));
5587 /* Finally build the instruction. */
5588 if ((opcode >> 16) != 0 || frame_size == 0)
5589 opcode |= MIPS16_EXTEND;
5590 arg->insn->insn_opcode = opcode;
5594 /* OP_MDMX_IMM_REG matcher. */
5597 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5598 const struct mips_operand *operand)
5600 unsigned int regno, uval;
5602 const struct mips_opcode *opcode;
5604 /* The mips_opcode records whether this is an octobyte or quadhalf
5605 instruction. Start out with that bit in place. */
5606 opcode = arg->insn->insn_mo;
5607 uval = mips_extract_operand (operand, opcode->match);
5608 is_qh = (uval != 0);
5610 if (arg->token->type == OT_REG)
5612 if ((opcode->membership & INSN_5400)
5613 && strcmp (opcode->name, "rzu.ob") == 0)
5615 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5620 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5624 /* Check whether this is a vector register or a broadcast of
5625 a single element. */
5626 if (arg->token->type == OT_INTEGER_INDEX)
5628 if (arg->token->u.index > (is_qh ? 3 : 7))
5630 set_insn_error (arg->argnum, _("invalid element selector"));
5633 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5638 /* A full vector. */
5639 if ((opcode->membership & INSN_5400)
5640 && (strcmp (opcode->name, "sll.ob") == 0
5641 || strcmp (opcode->name, "srl.ob") == 0))
5643 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5649 uval |= MDMX_FMTSEL_VEC_QH << 5;
5651 uval |= MDMX_FMTSEL_VEC_OB << 5;
5659 if (!match_const_int (arg, &sval))
5661 if (sval < 0 || sval > 31)
5663 match_out_of_range (arg);
5666 uval |= (sval & 31);
5668 uval |= MDMX_FMTSEL_IMM_QH << 5;
5670 uval |= MDMX_FMTSEL_IMM_OB << 5;
5672 insn_insert_operand (arg->insn, operand, uval);
5676 /* OP_IMM_INDEX matcher. */
5679 match_imm_index_operand (struct mips_arg_info *arg,
5680 const struct mips_operand *operand)
5682 unsigned int max_val;
5684 if (arg->token->type != OT_INTEGER_INDEX)
5687 max_val = (1 << operand->size) - 1;
5688 if (arg->token->u.index > max_val)
5690 match_out_of_range (arg);
5693 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5698 /* OP_REG_INDEX matcher. */
5701 match_reg_index_operand (struct mips_arg_info *arg,
5702 const struct mips_operand *operand)
5706 if (arg->token->type != OT_REG_INDEX)
5709 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5712 insn_insert_operand (arg->insn, operand, regno);
5717 /* OP_PC matcher. */
5720 match_pc_operand (struct mips_arg_info *arg)
5722 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5730 /* OP_NON_ZERO_REG matcher. */
5733 match_non_zero_reg_operand (struct mips_arg_info *arg,
5734 const struct mips_operand *operand)
5738 if (!match_reg (arg, OP_REG_GP, ®no))
5744 arg->last_regno = regno;
5745 insn_insert_operand (arg->insn, operand, regno);
5749 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5750 register that we need to match. */
5753 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5757 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5760 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5761 the length of the value in bytes (4 for float, 8 for double) and
5762 USING_GPRS says whether the destination is a GPR rather than an FPR.
5764 Return the constant in IMM and OFFSET as follows:
5766 - If the constant should be loaded via memory, set IMM to O_absent and
5767 OFFSET to the memory address.
5769 - Otherwise, if the constant should be loaded into two 32-bit registers,
5770 set IMM to the O_constant to load into the high register and OFFSET
5771 to the corresponding value for the low register.
5773 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5775 These constants only appear as the last operand in an instruction,
5776 and every instruction that accepts them in any variant accepts them
5777 in all variants. This means we don't have to worry about backing out
5778 any changes if the instruction does not match. We just match
5779 unconditionally and report an error if the constant is invalid. */
5782 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5783 expressionS *offset, int length, bfd_boolean using_gprs)
5788 const char *newname;
5789 unsigned char *data;
5791 /* Where the constant is placed is based on how the MIPS assembler
5794 length == 4 && using_gprs -- immediate value only
5795 length == 8 && using_gprs -- .rdata or immediate value
5796 length == 4 && !using_gprs -- .lit4 or immediate value
5797 length == 8 && !using_gprs -- .lit8 or immediate value
5799 The .lit4 and .lit8 sections are only used if permitted by the
5801 if (arg->token->type != OT_FLOAT)
5803 set_insn_error (arg->argnum, _("floating-point expression required"));
5807 gas_assert (arg->token->u.flt.length == length);
5808 data = arg->token->u.flt.data;
5811 /* Handle 32-bit constants for which an immediate value is best. */
5814 || g_switch_value < 4
5815 || (data[0] == 0 && data[1] == 0)
5816 || (data[2] == 0 && data[3] == 0)))
5818 imm->X_op = O_constant;
5819 if (!target_big_endian)
5820 imm->X_add_number = bfd_getl32 (data);
5822 imm->X_add_number = bfd_getb32 (data);
5823 offset->X_op = O_absent;
5827 /* Handle 64-bit constants for which an immediate value is best. */
5829 && !mips_disable_float_construction
5830 /* Constants can only be constructed in GPRs and copied to FPRs if the
5831 GPRs are at least as wide as the FPRs or MTHC1 is available.
5832 Unlike most tests for 32-bit floating-point registers this check
5833 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5834 permit 64-bit moves without MXHC1.
5835 Force the constant into memory otherwise. */
5838 || ISA_HAS_MXHC1 (mips_opts.isa)
5840 && ((data[0] == 0 && data[1] == 0)
5841 || (data[2] == 0 && data[3] == 0))
5842 && ((data[4] == 0 && data[5] == 0)
5843 || (data[6] == 0 && data[7] == 0)))
5845 /* The value is simple enough to load with a couple of instructions.
5846 If using 32-bit registers, set IMM to the high order 32 bits and
5847 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5849 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5851 imm->X_op = O_constant;
5852 offset->X_op = O_constant;
5853 if (!target_big_endian)
5855 imm->X_add_number = bfd_getl32 (data + 4);
5856 offset->X_add_number = bfd_getl32 (data);
5860 imm->X_add_number = bfd_getb32 (data);
5861 offset->X_add_number = bfd_getb32 (data + 4);
5863 if (offset->X_add_number == 0)
5864 offset->X_op = O_absent;
5868 imm->X_op = O_constant;
5869 if (!target_big_endian)
5870 imm->X_add_number = bfd_getl64 (data);
5872 imm->X_add_number = bfd_getb64 (data);
5873 offset->X_op = O_absent;
5878 /* Switch to the right section. */
5880 subseg = now_subseg;
5883 gas_assert (!using_gprs && g_switch_value >= 4);
5888 if (using_gprs || g_switch_value < 8)
5889 newname = RDATA_SECTION_NAME;
5894 new_seg = subseg_new (newname, (subsegT) 0);
5895 bfd_set_section_flags (stdoutput, new_seg,
5896 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5897 frag_align (length == 4 ? 2 : 3, 0, 0);
5898 if (strncmp (TARGET_OS, "elf", 3) != 0)
5899 record_alignment (new_seg, 4);
5901 record_alignment (new_seg, length == 4 ? 2 : 3);
5903 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5905 /* Set the argument to the current address in the section. */
5906 imm->X_op = O_absent;
5907 offset->X_op = O_symbol;
5908 offset->X_add_symbol = symbol_temp_new_now ();
5909 offset->X_add_number = 0;
5911 /* Put the floating point number into the section. */
5912 p = frag_more (length);
5913 memcpy (p, data, length);
5915 /* Switch back to the original section. */
5916 subseg_set (seg, subseg);
5920 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5924 match_vu0_suffix_operand (struct mips_arg_info *arg,
5925 const struct mips_operand *operand,
5926 bfd_boolean match_p)
5930 /* The operand can be an XYZW mask or a single 2-bit channel index
5931 (with X being 0). */
5932 gas_assert (operand->size == 2 || operand->size == 4);
5934 /* The suffix can be omitted when it is already part of the opcode. */
5935 if (arg->token->type != OT_CHANNELS)
5938 uval = arg->token->u.channels;
5939 if (operand->size == 2)
5941 /* Check that a single bit is set and convert it into a 2-bit index. */
5942 if ((uval & -uval) != uval)
5944 uval = 4 - ffs (uval);
5947 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5952 insn_insert_operand (arg->insn, operand, uval);
5956 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5957 of the argument text if the match is successful, otherwise return null. */
5960 match_operand (struct mips_arg_info *arg,
5961 const struct mips_operand *operand)
5963 switch (operand->type)
5966 return match_int_operand (arg, operand);
5969 return match_mapped_int_operand (arg, operand);
5972 return match_msb_operand (arg, operand);
5975 case OP_OPTIONAL_REG:
5976 return match_reg_operand (arg, operand);
5979 return match_reg_pair_operand (arg, operand);
5982 return match_pcrel_operand (arg);
5985 return match_perf_reg_operand (arg, operand);
5987 case OP_ADDIUSP_INT:
5988 return match_addiusp_operand (arg, operand);
5990 case OP_CLO_CLZ_DEST:
5991 return match_clo_clz_dest_operand (arg, operand);
5993 case OP_LWM_SWM_LIST:
5994 return match_lwm_swm_list_operand (arg, operand);
5996 case OP_ENTRY_EXIT_LIST:
5997 return match_entry_exit_operand (arg, operand);
5999 case OP_SAVE_RESTORE_LIST:
6000 return match_save_restore_list_operand (arg);
6002 case OP_MDMX_IMM_REG:
6003 return match_mdmx_imm_reg_operand (arg, operand);
6005 case OP_REPEAT_DEST_REG:
6006 return match_tied_reg_operand (arg, arg->dest_regno);
6008 case OP_REPEAT_PREV_REG:
6009 return match_tied_reg_operand (arg, arg->last_regno);
6012 return match_pc_operand (arg);
6015 return match_vu0_suffix_operand (arg, operand, FALSE);
6017 case OP_VU0_MATCH_SUFFIX:
6018 return match_vu0_suffix_operand (arg, operand, TRUE);
6021 return match_imm_index_operand (arg, operand);
6024 return match_reg_index_operand (arg, operand);
6027 return match_same_rs_rt_operand (arg, operand);
6030 return match_check_prev_operand (arg, operand);
6032 case OP_NON_ZERO_REG:
6033 return match_non_zero_reg_operand (arg, operand);
6038 /* ARG is the state after successfully matching an instruction.
6039 Issue any queued-up warnings. */
6042 check_completed_insn (struct mips_arg_info *arg)
6047 as_warn (_("used $at without \".set noat\""));
6049 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6053 /* Return true if modifying general-purpose register REG needs a delay. */
6056 reg_needs_delay (unsigned int reg)
6058 unsigned long prev_pinfo;
6060 prev_pinfo = history[0].insn_mo->pinfo;
6061 if (!mips_opts.noreorder
6062 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6063 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6064 && (gpr_write_mask (&history[0]) & (1 << reg)))
6070 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6071 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6072 by VR4120 errata. */
6075 classify_vr4120_insn (const char *name)
6077 if (strncmp (name, "macc", 4) == 0)
6078 return FIX_VR4120_MACC;
6079 if (strncmp (name, "dmacc", 5) == 0)
6080 return FIX_VR4120_DMACC;
6081 if (strncmp (name, "mult", 4) == 0)
6082 return FIX_VR4120_MULT;
6083 if (strncmp (name, "dmult", 5) == 0)
6084 return FIX_VR4120_DMULT;
6085 if (strstr (name, "div"))
6086 return FIX_VR4120_DIV;
6087 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6088 return FIX_VR4120_MTHILO;
6089 return NUM_FIX_VR4120_CLASSES;
6092 #define INSN_ERET 0x42000018
6093 #define INSN_DERET 0x4200001f
6094 #define INSN_DMULT 0x1c
6095 #define INSN_DMULTU 0x1d
6097 /* Return the number of instructions that must separate INSN1 and INSN2,
6098 where INSN1 is the earlier instruction. Return the worst-case value
6099 for any INSN2 if INSN2 is null. */
6102 insns_between (const struct mips_cl_insn *insn1,
6103 const struct mips_cl_insn *insn2)
6105 unsigned long pinfo1, pinfo2;
6108 /* If INFO2 is null, pessimistically assume that all flags are set for
6109 the second instruction. */
6110 pinfo1 = insn1->insn_mo->pinfo;
6111 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6113 /* For most targets, write-after-read dependencies on the HI and LO
6114 registers must be separated by at least two instructions. */
6115 if (!hilo_interlocks)
6117 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6119 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6123 /* If we're working around r7000 errata, there must be two instructions
6124 between an mfhi or mflo and any instruction that uses the result. */
6125 if (mips_7000_hilo_fix
6126 && !mips_opts.micromips
6127 && MF_HILO_INSN (pinfo1)
6128 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6131 /* If we're working around 24K errata, one instruction is required
6132 if an ERET or DERET is followed by a branch instruction. */
6133 if (mips_fix_24k && !mips_opts.micromips)
6135 if (insn1->insn_opcode == INSN_ERET
6136 || insn1->insn_opcode == INSN_DERET)
6139 || insn2->insn_opcode == INSN_ERET
6140 || insn2->insn_opcode == INSN_DERET
6141 || delayed_branch_p (insn2))
6146 /* If we're working around PMC RM7000 errata, there must be three
6147 nops between a dmult and a load instruction. */
6148 if (mips_fix_rm7000 && !mips_opts.micromips)
6150 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6151 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6153 if (pinfo2 & INSN_LOAD_MEMORY)
6158 /* If working around VR4120 errata, check for combinations that need
6159 a single intervening instruction. */
6160 if (mips_fix_vr4120 && !mips_opts.micromips)
6162 unsigned int class1, class2;
6164 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6165 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6169 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6170 if (vr4120_conflicts[class1] & (1 << class2))
6175 if (!HAVE_CODE_COMPRESSION)
6177 /* Check for GPR or coprocessor load delays. All such delays
6178 are on the RT register. */
6179 /* Itbl support may require additional care here. */
6180 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6181 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6183 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6187 /* Check for generic coprocessor hazards.
6189 This case is not handled very well. There is no special
6190 knowledge of CP0 handling, and the coprocessors other than
6191 the floating point unit are not distinguished at all. */
6192 /* Itbl support may require additional care here. FIXME!
6193 Need to modify this to include knowledge about
6194 user specified delays! */
6195 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6196 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6198 /* Handle cases where INSN1 writes to a known general coprocessor
6199 register. There must be a one instruction delay before INSN2
6200 if INSN2 reads that register, otherwise no delay is needed. */
6201 mask = fpr_write_mask (insn1);
6204 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6209 /* Read-after-write dependencies on the control registers
6210 require a two-instruction gap. */
6211 if ((pinfo1 & INSN_WRITE_COND_CODE)
6212 && (pinfo2 & INSN_READ_COND_CODE))
6215 /* We don't know exactly what INSN1 does. If INSN2 is
6216 also a coprocessor instruction, assume there must be
6217 a one instruction gap. */
6218 if (pinfo2 & INSN_COP)
6223 /* Check for read-after-write dependencies on the coprocessor
6224 control registers in cases where INSN1 does not need a general
6225 coprocessor delay. This means that INSN1 is a floating point
6226 comparison instruction. */
6227 /* Itbl support may require additional care here. */
6228 else if (!cop_interlocks
6229 && (pinfo1 & INSN_WRITE_COND_CODE)
6230 && (pinfo2 & INSN_READ_COND_CODE))
6234 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6235 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6237 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6238 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6239 || (insn2 && delayed_branch_p (insn2))))
6245 /* Return the number of nops that would be needed to work around the
6246 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6247 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6248 that are contained within the first IGNORE instructions of HIST. */
6251 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6252 const struct mips_cl_insn *insn)
6257 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6258 are not affected by the errata. */
6260 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6261 || strcmp (insn->insn_mo->name, "mtlo") == 0
6262 || strcmp (insn->insn_mo->name, "mthi") == 0))
6265 /* Search for the first MFLO or MFHI. */
6266 for (i = 0; i < MAX_VR4130_NOPS; i++)
6267 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6269 /* Extract the destination register. */
6270 mask = gpr_write_mask (&hist[i]);
6272 /* No nops are needed if INSN reads that register. */
6273 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6276 /* ...or if any of the intervening instructions do. */
6277 for (j = 0; j < i; j++)
6278 if (gpr_read_mask (&hist[j]) & mask)
6282 return MAX_VR4130_NOPS - i;
6287 #define BASE_REG_EQ(INSN1, INSN2) \
6288 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6289 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6291 /* Return the minimum alignment for this store instruction. */
6294 fix_24k_align_to (const struct mips_opcode *mo)
6296 if (strcmp (mo->name, "sh") == 0)
6299 if (strcmp (mo->name, "swc1") == 0
6300 || strcmp (mo->name, "swc2") == 0
6301 || strcmp (mo->name, "sw") == 0
6302 || strcmp (mo->name, "sc") == 0
6303 || strcmp (mo->name, "s.s") == 0)
6306 if (strcmp (mo->name, "sdc1") == 0
6307 || strcmp (mo->name, "sdc2") == 0
6308 || strcmp (mo->name, "s.d") == 0)
6315 struct fix_24k_store_info
6317 /* Immediate offset, if any, for this store instruction. */
6319 /* Alignment required by this store instruction. */
6321 /* True for register offsets. */
6322 int register_offset;
6325 /* Comparison function used by qsort. */
6328 fix_24k_sort (const void *a, const void *b)
6330 const struct fix_24k_store_info *pos1 = a;
6331 const struct fix_24k_store_info *pos2 = b;
6333 return (pos1->off - pos2->off);
6336 /* INSN is a store instruction. Try to record the store information
6337 in STINFO. Return false if the information isn't known. */
6340 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6341 const struct mips_cl_insn *insn)
6343 /* The instruction must have a known offset. */
6344 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6347 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6348 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6352 /* Return the number of nops that would be needed to work around the 24k
6353 "lost data on stores during refill" errata if instruction INSN
6354 immediately followed the 2 instructions described by HIST.
6355 Ignore hazards that are contained within the first IGNORE
6356 instructions of HIST.
6358 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6359 for the data cache refills and store data. The following describes
6360 the scenario where the store data could be lost.
6362 * A data cache miss, due to either a load or a store, causing fill
6363 data to be supplied by the memory subsystem
6364 * The first three doublewords of fill data are returned and written
6366 * A sequence of four stores occurs in consecutive cycles around the
6367 final doubleword of the fill:
6371 * Zero, One or more instructions
6374 The four stores A-D must be to different doublewords of the line that
6375 is being filled. The fourth instruction in the sequence above permits
6376 the fill of the final doubleword to be transferred from the FSB into
6377 the cache. In the sequence above, the stores may be either integer
6378 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6379 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6380 different doublewords on the line. If the floating point unit is
6381 running in 1:2 mode, it is not possible to create the sequence above
6382 using only floating point store instructions.
6384 In this case, the cache line being filled is incorrectly marked
6385 invalid, thereby losing the data from any store to the line that
6386 occurs between the original miss and the completion of the five
6387 cycle sequence shown above.
6389 The workarounds are:
6391 * Run the data cache in write-through mode.
6392 * Insert a non-store instruction between
6393 Store A and Store B or Store B and Store C. */
6396 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6397 const struct mips_cl_insn *insn)
6399 struct fix_24k_store_info pos[3];
6400 int align, i, base_offset;
6405 /* If the previous instruction wasn't a store, there's nothing to
6407 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6410 /* If the instructions after the previous one are unknown, we have
6411 to assume the worst. */
6415 /* Check whether we are dealing with three consecutive stores. */
6416 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6417 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6420 /* If we don't know the relationship between the store addresses,
6421 assume the worst. */
6422 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6423 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6426 if (!fix_24k_record_store_info (&pos[0], insn)
6427 || !fix_24k_record_store_info (&pos[1], &hist[0])
6428 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6431 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6433 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6434 X bytes and such that the base register + X is known to be aligned
6437 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6441 align = pos[0].align_to;
6442 base_offset = pos[0].off;
6443 for (i = 1; i < 3; i++)
6444 if (align < pos[i].align_to)
6446 align = pos[i].align_to;
6447 base_offset = pos[i].off;
6449 for (i = 0; i < 3; i++)
6450 pos[i].off -= base_offset;
6453 pos[0].off &= ~align + 1;
6454 pos[1].off &= ~align + 1;
6455 pos[2].off &= ~align + 1;
6457 /* If any two stores write to the same chunk, they also write to the
6458 same doubleword. The offsets are still sorted at this point. */
6459 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6462 /* A range of at least 9 bytes is needed for the stores to be in
6463 non-overlapping doublewords. */
6464 if (pos[2].off - pos[0].off <= 8)
6467 if (pos[2].off - pos[1].off >= 24
6468 || pos[1].off - pos[0].off >= 24
6469 || pos[2].off - pos[0].off >= 32)
6475 /* Return the number of nops that would be needed if instruction INSN
6476 immediately followed the MAX_NOPS instructions given by HIST,
6477 where HIST[0] is the most recent instruction. Ignore hazards
6478 between INSN and the first IGNORE instructions in HIST.
6480 If INSN is null, return the worse-case number of nops for any
6484 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6485 const struct mips_cl_insn *insn)
6487 int i, nops, tmp_nops;
6490 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6492 tmp_nops = insns_between (hist + i, insn) - i;
6493 if (tmp_nops > nops)
6497 if (mips_fix_vr4130 && !mips_opts.micromips)
6499 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6500 if (tmp_nops > nops)
6504 if (mips_fix_24k && !mips_opts.micromips)
6506 tmp_nops = nops_for_24k (ignore, hist, insn);
6507 if (tmp_nops > nops)
6514 /* The variable arguments provide NUM_INSNS extra instructions that
6515 might be added to HIST. Return the largest number of nops that
6516 would be needed after the extended sequence, ignoring hazards
6517 in the first IGNORE instructions. */
6520 nops_for_sequence (int num_insns, int ignore,
6521 const struct mips_cl_insn *hist, ...)
6524 struct mips_cl_insn buffer[MAX_NOPS];
6525 struct mips_cl_insn *cursor;
6528 va_start (args, hist);
6529 cursor = buffer + num_insns;
6530 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6531 while (cursor > buffer)
6532 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6534 nops = nops_for_insn (ignore, buffer, NULL);
6539 /* Like nops_for_insn, but if INSN is a branch, take into account the
6540 worst-case delay for the branch target. */
6543 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6544 const struct mips_cl_insn *insn)
6548 nops = nops_for_insn (ignore, hist, insn);
6549 if (delayed_branch_p (insn))
6551 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6552 hist, insn, get_delay_slot_nop (insn));
6553 if (tmp_nops > nops)
6556 else if (compact_branch_p (insn))
6558 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6559 if (tmp_nops > nops)
6565 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6568 fix_loongson2f_nop (struct mips_cl_insn * ip)
6570 gas_assert (!HAVE_CODE_COMPRESSION);
6571 if (strcmp (ip->insn_mo->name, "nop") == 0)
6572 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6575 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6576 jr target pc &= 'hffff_ffff_cfff_ffff. */
6579 fix_loongson2f_jump (struct mips_cl_insn * ip)
6581 gas_assert (!HAVE_CODE_COMPRESSION);
6582 if (strcmp (ip->insn_mo->name, "j") == 0
6583 || strcmp (ip->insn_mo->name, "jr") == 0
6584 || strcmp (ip->insn_mo->name, "jalr") == 0)
6592 sreg = EXTRACT_OPERAND (0, RS, *ip);
6593 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6596 ep.X_op = O_constant;
6597 ep.X_add_number = 0xcfff0000;
6598 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6599 ep.X_add_number = 0xffff;
6600 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6601 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6606 fix_loongson2f (struct mips_cl_insn * ip)
6608 if (mips_fix_loongson2f_nop)
6609 fix_loongson2f_nop (ip);
6611 if (mips_fix_loongson2f_jump)
6612 fix_loongson2f_jump (ip);
6615 /* IP is a branch that has a delay slot, and we need to fill it
6616 automatically. Return true if we can do that by swapping IP
6617 with the previous instruction.
6618 ADDRESS_EXPR is an operand of the instruction to be used with
6622 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6623 bfd_reloc_code_real_type *reloc_type)
6625 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6626 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6627 unsigned int fpr_read, prev_fpr_write;
6629 /* -O2 and above is required for this optimization. */
6630 if (mips_optimize < 2)
6633 /* If we have seen .set volatile or .set nomove, don't optimize. */
6634 if (mips_opts.nomove)
6637 /* We can't swap if the previous instruction's position is fixed. */
6638 if (history[0].fixed_p)
6641 /* If the previous previous insn was in a .set noreorder, we can't
6642 swap. Actually, the MIPS assembler will swap in this situation.
6643 However, gcc configured -with-gnu-as will generate code like
6651 in which we can not swap the bne and INSN. If gcc is not configured
6652 -with-gnu-as, it does not output the .set pseudo-ops. */
6653 if (history[1].noreorder_p)
6656 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6657 This means that the previous instruction was a 4-byte one anyhow. */
6658 if (mips_opts.mips16 && history[0].fixp[0])
6661 /* If the branch is itself the target of a branch, we can not swap.
6662 We cheat on this; all we check for is whether there is a label on
6663 this instruction. If there are any branches to anything other than
6664 a label, users must use .set noreorder. */
6665 if (seg_info (now_seg)->label_list)
6668 /* If the previous instruction is in a variant frag other than this
6669 branch's one, we cannot do the swap. This does not apply to
6670 MIPS16 code, which uses variant frags for different purposes. */
6671 if (!mips_opts.mips16
6673 && history[0].frag->fr_type == rs_machine_dependent)
6676 /* We do not swap with instructions that cannot architecturally
6677 be placed in a branch delay slot, such as SYNC or ERET. We
6678 also refrain from swapping with a trap instruction, since it
6679 complicates trap handlers to have the trap instruction be in
6681 prev_pinfo = history[0].insn_mo->pinfo;
6682 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6685 /* Check for conflicts between the branch and the instructions
6686 before the candidate delay slot. */
6687 if (nops_for_insn (0, history + 1, ip) > 0)
6690 /* Check for conflicts between the swapped sequence and the
6691 target of the branch. */
6692 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6695 /* If the branch reads a register that the previous
6696 instruction sets, we can not swap. */
6697 gpr_read = gpr_read_mask (ip);
6698 prev_gpr_write = gpr_write_mask (&history[0]);
6699 if (gpr_read & prev_gpr_write)
6702 fpr_read = fpr_read_mask (ip);
6703 prev_fpr_write = fpr_write_mask (&history[0]);
6704 if (fpr_read & prev_fpr_write)
6707 /* If the branch writes a register that the previous
6708 instruction sets, we can not swap. */
6709 gpr_write = gpr_write_mask (ip);
6710 if (gpr_write & prev_gpr_write)
6713 /* If the branch writes a register that the previous
6714 instruction reads, we can not swap. */
6715 prev_gpr_read = gpr_read_mask (&history[0]);
6716 if (gpr_write & prev_gpr_read)
6719 /* If one instruction sets a condition code and the
6720 other one uses a condition code, we can not swap. */
6721 pinfo = ip->insn_mo->pinfo;
6722 if ((pinfo & INSN_READ_COND_CODE)
6723 && (prev_pinfo & INSN_WRITE_COND_CODE))
6725 if ((pinfo & INSN_WRITE_COND_CODE)
6726 && (prev_pinfo & INSN_READ_COND_CODE))
6729 /* If the previous instruction uses the PC, we can not swap. */
6730 prev_pinfo2 = history[0].insn_mo->pinfo2;
6731 if (prev_pinfo2 & INSN2_READ_PC)
6734 /* If the previous instruction has an incorrect size for a fixed
6735 branch delay slot in microMIPS mode, we cannot swap. */
6736 pinfo2 = ip->insn_mo->pinfo2;
6737 if (mips_opts.micromips
6738 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6739 && insn_length (history) != 2)
6741 if (mips_opts.micromips
6742 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6743 && insn_length (history) != 4)
6746 /* On R5900 short loops need to be fixed by inserting a nop in
6747 the branch delay slots.
6748 A short loop can be terminated too early. */
6749 if (mips_opts.arch == CPU_R5900
6750 /* Check if instruction has a parameter, ignore "j $31". */
6751 && (address_expr != NULL)
6752 /* Parameter must be 16 bit. */
6753 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6754 /* Branch to same segment. */
6755 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6756 /* Branch to same code fragment. */
6757 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6758 /* Can only calculate branch offset if value is known. */
6759 && symbol_constant_p (address_expr->X_add_symbol)
6760 /* Check if branch is really conditional. */
6761 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6762 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6763 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6766 /* Check if loop is shorter than 6 instructions including
6767 branch and delay slot. */
6768 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6775 /* When the loop includes branches or jumps,
6776 it is not a short loop. */
6777 for (i = 0; i < (distance / 4); i++)
6779 if ((history[i].cleared_p)
6780 || delayed_branch_p (&history[i]))
6788 /* Insert nop after branch to fix short loop. */
6797 /* Decide how we should add IP to the instruction stream.
6798 ADDRESS_EXPR is an operand of the instruction to be used with
6801 static enum append_method
6802 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6803 bfd_reloc_code_real_type *reloc_type)
6805 /* The relaxed version of a macro sequence must be inherently
6807 if (mips_relax.sequence == 2)
6810 /* We must not dabble with instructions in a ".set norerorder" block. */
6811 if (mips_opts.noreorder)
6814 /* Otherwise, it's our responsibility to fill branch delay slots. */
6815 if (delayed_branch_p (ip))
6817 if (!branch_likely_p (ip)
6818 && can_swap_branch_p (ip, address_expr, reloc_type))
6821 if (mips_opts.mips16
6822 && ISA_SUPPORTS_MIPS16E
6823 && gpr_read_mask (ip) != 0)
6824 return APPEND_ADD_COMPACT;
6826 return APPEND_ADD_WITH_NOP;
6832 /* IP is a MIPS16 instruction whose opcode we have just changed.
6833 Point IP->insn_mo to the new opcode's definition. */
6836 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6838 const struct mips_opcode *mo, *end;
6840 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6841 for (mo = ip->insn_mo; mo < end; mo++)
6842 if ((ip->insn_opcode & mo->mask) == mo->match)
6850 /* For microMIPS macros, we need to generate a local number label
6851 as the target of branches. */
6852 #define MICROMIPS_LABEL_CHAR '\037'
6853 static unsigned long micromips_target_label;
6854 static char micromips_target_name[32];
6857 micromips_label_name (void)
6859 char *p = micromips_target_name;
6860 char symbol_name_temporary[24];
6868 l = micromips_target_label;
6869 #ifdef LOCAL_LABEL_PREFIX
6870 *p++ = LOCAL_LABEL_PREFIX;
6873 *p++ = MICROMIPS_LABEL_CHAR;
6876 symbol_name_temporary[i++] = l % 10 + '0';
6881 *p++ = symbol_name_temporary[--i];
6884 return micromips_target_name;
6888 micromips_label_expr (expressionS *label_expr)
6890 label_expr->X_op = O_symbol;
6891 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6892 label_expr->X_add_number = 0;
6896 micromips_label_inc (void)
6898 micromips_target_label++;
6899 *micromips_target_name = '\0';
6903 micromips_add_label (void)
6907 s = colon (micromips_label_name ());
6908 micromips_label_inc ();
6909 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6912 /* If assembling microMIPS code, then return the microMIPS reloc
6913 corresponding to the requested one if any. Otherwise return
6914 the reloc unchanged. */
6916 static bfd_reloc_code_real_type
6917 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6919 static const bfd_reloc_code_real_type relocs[][2] =
6921 /* Keep sorted incrementally by the left-hand key. */
6922 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6923 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6924 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6925 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6926 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6927 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6928 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6929 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6930 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6931 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6932 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6933 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6934 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6935 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6936 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6937 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6938 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6939 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6940 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6941 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6942 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6943 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6944 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6945 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6946 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6947 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6948 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6950 bfd_reloc_code_real_type r;
6953 if (!mips_opts.micromips)
6955 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6961 return relocs[i][1];
6966 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6967 Return true on success, storing the resolved value in RESULT. */
6970 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6975 case BFD_RELOC_MIPS_HIGHEST:
6976 case BFD_RELOC_MICROMIPS_HIGHEST:
6977 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6980 case BFD_RELOC_MIPS_HIGHER:
6981 case BFD_RELOC_MICROMIPS_HIGHER:
6982 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6985 case BFD_RELOC_HI16_S:
6986 case BFD_RELOC_HI16_S_PCREL:
6987 case BFD_RELOC_MICROMIPS_HI16_S:
6988 case BFD_RELOC_MIPS16_HI16_S:
6989 *result = ((operand + 0x8000) >> 16) & 0xffff;
6992 case BFD_RELOC_HI16:
6993 case BFD_RELOC_MICROMIPS_HI16:
6994 case BFD_RELOC_MIPS16_HI16:
6995 *result = (operand >> 16) & 0xffff;
6998 case BFD_RELOC_LO16:
6999 case BFD_RELOC_LO16_PCREL:
7000 case BFD_RELOC_MICROMIPS_LO16:
7001 case BFD_RELOC_MIPS16_LO16:
7002 *result = operand & 0xffff;
7005 case BFD_RELOC_UNUSED:
7014 /* Output an instruction. IP is the instruction information.
7015 ADDRESS_EXPR is an operand of the instruction to be used with
7016 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7017 a macro expansion. */
7020 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7021 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7023 unsigned long prev_pinfo2, pinfo;
7024 bfd_boolean relaxed_branch = FALSE;
7025 enum append_method method;
7026 bfd_boolean relax32;
7029 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7030 fix_loongson2f (ip);
7032 file_ase_mips16 |= mips_opts.mips16;
7033 file_ase_micromips |= mips_opts.micromips;
7035 prev_pinfo2 = history[0].insn_mo->pinfo2;
7036 pinfo = ip->insn_mo->pinfo;
7038 if (mips_opts.micromips
7040 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7041 && micromips_insn_length (ip->insn_mo) != 2)
7042 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7043 && micromips_insn_length (ip->insn_mo) != 4)))
7044 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7045 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7047 if (address_expr == NULL)
7049 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7050 && reloc_type[1] == BFD_RELOC_UNUSED
7051 && reloc_type[2] == BFD_RELOC_UNUSED
7052 && address_expr->X_op == O_constant)
7054 switch (*reloc_type)
7056 case BFD_RELOC_MIPS_JMP:
7060 /* Shift is 2, unusually, for microMIPS JALX. */
7061 shift = (mips_opts.micromips
7062 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7063 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7064 as_bad (_("jump to misaligned address (0x%lx)"),
7065 (unsigned long) address_expr->X_add_number);
7066 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7072 case BFD_RELOC_MIPS16_JMP:
7073 if ((address_expr->X_add_number & 3) != 0)
7074 as_bad (_("jump to misaligned address (0x%lx)"),
7075 (unsigned long) address_expr->X_add_number);
7077 (((address_expr->X_add_number & 0x7c0000) << 3)
7078 | ((address_expr->X_add_number & 0xf800000) >> 7)
7079 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7083 case BFD_RELOC_16_PCREL_S2:
7087 shift = mips_opts.micromips ? 1 : 2;
7088 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7089 as_bad (_("branch to misaligned address (0x%lx)"),
7090 (unsigned long) address_expr->X_add_number);
7091 if (!mips_relax_branch)
7093 if ((address_expr->X_add_number + (1 << (shift + 15)))
7094 & ~((1 << (shift + 16)) - 1))
7095 as_bad (_("branch address range overflow (0x%lx)"),
7096 (unsigned long) address_expr->X_add_number);
7097 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7103 case BFD_RELOC_MIPS_21_PCREL_S2:
7108 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7109 as_bad (_("branch to misaligned address (0x%lx)"),
7110 (unsigned long) address_expr->X_add_number);
7111 if ((address_expr->X_add_number + (1 << (shift + 20)))
7112 & ~((1 << (shift + 21)) - 1))
7113 as_bad (_("branch address range overflow (0x%lx)"),
7114 (unsigned long) address_expr->X_add_number);
7115 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7120 case BFD_RELOC_MIPS_26_PCREL_S2:
7125 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7126 as_bad (_("branch to misaligned address (0x%lx)"),
7127 (unsigned long) address_expr->X_add_number);
7128 if ((address_expr->X_add_number + (1 << (shift + 25)))
7129 & ~((1 << (shift + 26)) - 1))
7130 as_bad (_("branch address range overflow (0x%lx)"),
7131 (unsigned long) address_expr->X_add_number);
7132 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7141 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7144 ip->insn_opcode |= value & 0xffff;
7152 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7154 /* There are a lot of optimizations we could do that we don't.
7155 In particular, we do not, in general, reorder instructions.
7156 If you use gcc with optimization, it will reorder
7157 instructions and generally do much more optimization then we
7158 do here; repeating all that work in the assembler would only
7159 benefit hand written assembly code, and does not seem worth
7161 int nops = (mips_optimize == 0
7162 ? nops_for_insn (0, history, NULL)
7163 : nops_for_insn_or_target (0, history, ip));
7167 unsigned long old_frag_offset;
7170 old_frag = frag_now;
7171 old_frag_offset = frag_now_fix ();
7173 for (i = 0; i < nops; i++)
7174 add_fixed_insn (NOP_INSN);
7175 insert_into_history (0, nops, NOP_INSN);
7179 listing_prev_line ();
7180 /* We may be at the start of a variant frag. In case we
7181 are, make sure there is enough space for the frag
7182 after the frags created by listing_prev_line. The
7183 argument to frag_grow here must be at least as large
7184 as the argument to all other calls to frag_grow in
7185 this file. We don't have to worry about being in the
7186 middle of a variant frag, because the variants insert
7187 all needed nop instructions themselves. */
7191 mips_move_text_labels ();
7193 #ifndef NO_ECOFF_DEBUGGING
7194 if (ECOFF_DEBUGGING)
7195 ecoff_fix_loc (old_frag, old_frag_offset);
7199 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7203 /* Work out how many nops in prev_nop_frag are needed by IP,
7204 ignoring hazards generated by the first prev_nop_frag_since
7206 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7207 gas_assert (nops <= prev_nop_frag_holds);
7209 /* Enforce NOPS as a minimum. */
7210 if (nops > prev_nop_frag_required)
7211 prev_nop_frag_required = nops;
7213 if (prev_nop_frag_holds == prev_nop_frag_required)
7215 /* Settle for the current number of nops. Update the history
7216 accordingly (for the benefit of any future .set reorder code). */
7217 prev_nop_frag = NULL;
7218 insert_into_history (prev_nop_frag_since,
7219 prev_nop_frag_holds, NOP_INSN);
7223 /* Allow this instruction to replace one of the nops that was
7224 tentatively added to prev_nop_frag. */
7225 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7226 prev_nop_frag_holds--;
7227 prev_nop_frag_since++;
7231 method = get_append_method (ip, address_expr, reloc_type);
7232 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7234 dwarf2_emit_insn (0);
7235 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7236 so "move" the instruction address accordingly.
7238 Also, it doesn't seem appropriate for the assembler to reorder .loc
7239 entries. If this instruction is a branch that we are going to swap
7240 with the previous instruction, the two instructions should be
7241 treated as a unit, and the debug information for both instructions
7242 should refer to the start of the branch sequence. Using the
7243 current position is certainly wrong when swapping a 32-bit branch
7244 and a 16-bit delay slot, since the current position would then be
7245 in the middle of a branch. */
7246 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7248 relax32 = (mips_relax_branch
7249 /* Don't try branch relaxation within .set nomacro, or within
7250 .set noat if we use $at for PIC computations. If it turns
7251 out that the branch was out-of-range, we'll get an error. */
7252 && !mips_opts.warn_about_macros
7253 && (mips_opts.at || mips_pic == NO_PIC)
7254 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7255 as they have no complementing branches. */
7256 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7258 if (!HAVE_CODE_COMPRESSION
7261 && *reloc_type == BFD_RELOC_16_PCREL_S2
7262 && delayed_branch_p (ip))
7264 relaxed_branch = TRUE;
7265 add_relaxed_insn (ip, (relaxed_branch_length
7267 uncond_branch_p (ip) ? -1
7268 : branch_likely_p (ip) ? 1
7272 uncond_branch_p (ip),
7273 branch_likely_p (ip),
7274 pinfo & INSN_WRITE_GPR_31,
7276 address_expr->X_add_symbol,
7277 address_expr->X_add_number);
7278 *reloc_type = BFD_RELOC_UNUSED;
7280 else if (mips_opts.micromips
7282 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7283 || *reloc_type > BFD_RELOC_UNUSED)
7284 && (delayed_branch_p (ip) || compact_branch_p (ip))
7285 /* Don't try branch relaxation when users specify
7286 16-bit/32-bit instructions. */
7287 && !forced_insn_length)
7289 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7290 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7291 int uncond = uncond_branch_p (ip) ? -1 : 0;
7292 int compact = compact_branch_p (ip);
7293 int al = pinfo & INSN_WRITE_GPR_31;
7296 gas_assert (address_expr != NULL);
7297 gas_assert (!mips_relax.sequence);
7299 relaxed_branch = TRUE;
7300 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7301 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
7302 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7304 address_expr->X_add_symbol,
7305 address_expr->X_add_number);
7306 *reloc_type = BFD_RELOC_UNUSED;
7308 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7310 /* We need to set up a variant frag. */
7311 gas_assert (address_expr != NULL);
7312 add_relaxed_insn (ip, 4, 0,
7314 (*reloc_type - BFD_RELOC_UNUSED,
7315 forced_insn_length == 2, forced_insn_length == 4,
7316 delayed_branch_p (&history[0]),
7317 history[0].mips16_absolute_jump_p),
7318 make_expr_symbol (address_expr), 0);
7320 else if (mips_opts.mips16 && insn_length (ip) == 2)
7322 if (!delayed_branch_p (ip))
7323 /* Make sure there is enough room to swap this instruction with
7324 a following jump instruction. */
7326 add_fixed_insn (ip);
7330 if (mips_opts.mips16
7331 && mips_opts.noreorder
7332 && delayed_branch_p (&history[0]))
7333 as_warn (_("extended instruction in delay slot"));
7335 if (mips_relax.sequence)
7337 /* If we've reached the end of this frag, turn it into a variant
7338 frag and record the information for the instructions we've
7340 if (frag_room () < 4)
7341 relax_close_frag ();
7342 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7345 if (mips_relax.sequence != 2)
7347 if (mips_macro_warning.first_insn_sizes[0] == 0)
7348 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7349 mips_macro_warning.sizes[0] += insn_length (ip);
7350 mips_macro_warning.insns[0]++;
7352 if (mips_relax.sequence != 1)
7354 if (mips_macro_warning.first_insn_sizes[1] == 0)
7355 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7356 mips_macro_warning.sizes[1] += insn_length (ip);
7357 mips_macro_warning.insns[1]++;
7360 if (mips_opts.mips16)
7363 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7365 add_fixed_insn (ip);
7368 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7370 bfd_reloc_code_real_type final_type[3];
7371 reloc_howto_type *howto0;
7372 reloc_howto_type *howto;
7375 /* Perform any necessary conversion to microMIPS relocations
7376 and find out how many relocations there actually are. */
7377 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7378 final_type[i] = micromips_map_reloc (reloc_type[i]);
7380 /* In a compound relocation, it is the final (outermost)
7381 operator that determines the relocated field. */
7382 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7387 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7388 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7389 bfd_get_reloc_size (howto),
7391 howto0 && howto0->pc_relative,
7394 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7395 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7396 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7398 /* These relocations can have an addend that won't fit in
7399 4 octets for 64bit assembly. */
7401 && ! howto->partial_inplace
7402 && (reloc_type[0] == BFD_RELOC_16
7403 || reloc_type[0] == BFD_RELOC_32
7404 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7405 || reloc_type[0] == BFD_RELOC_GPREL16
7406 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7407 || reloc_type[0] == BFD_RELOC_GPREL32
7408 || reloc_type[0] == BFD_RELOC_64
7409 || reloc_type[0] == BFD_RELOC_CTOR
7410 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7411 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7412 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7413 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7414 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7415 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7416 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7417 || hi16_reloc_p (reloc_type[0])
7418 || lo16_reloc_p (reloc_type[0])))
7419 ip->fixp[0]->fx_no_overflow = 1;
7421 /* These relocations can have an addend that won't fit in 2 octets. */
7422 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7423 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7424 ip->fixp[0]->fx_no_overflow = 1;
7426 if (mips_relax.sequence)
7428 if (mips_relax.first_fixup == 0)
7429 mips_relax.first_fixup = ip->fixp[0];
7431 else if (reloc_needs_lo_p (*reloc_type))
7433 struct mips_hi_fixup *hi_fixup;
7435 /* Reuse the last entry if it already has a matching %lo. */
7436 hi_fixup = mips_hi_fixup_list;
7438 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7440 hi_fixup = XNEW (struct mips_hi_fixup);
7441 hi_fixup->next = mips_hi_fixup_list;
7442 mips_hi_fixup_list = hi_fixup;
7444 hi_fixup->fixp = ip->fixp[0];
7445 hi_fixup->seg = now_seg;
7448 /* Add fixups for the second and third relocations, if given.
7449 Note that the ABI allows the second relocation to be
7450 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7451 moment we only use RSS_UNDEF, but we could add support
7452 for the others if it ever becomes necessary. */
7453 for (i = 1; i < 3; i++)
7454 if (reloc_type[i] != BFD_RELOC_UNUSED)
7456 ip->fixp[i] = fix_new (ip->frag, ip->where,
7457 ip->fixp[0]->fx_size, NULL, 0,
7458 FALSE, final_type[i]);
7460 /* Use fx_tcbit to mark compound relocs. */
7461 ip->fixp[0]->fx_tcbit = 1;
7462 ip->fixp[i]->fx_tcbit = 1;
7467 /* Update the register mask information. */
7468 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7469 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7474 insert_into_history (0, 1, ip);
7477 case APPEND_ADD_WITH_NOP:
7479 struct mips_cl_insn *nop;
7481 insert_into_history (0, 1, ip);
7482 nop = get_delay_slot_nop (ip);
7483 add_fixed_insn (nop);
7484 insert_into_history (0, 1, nop);
7485 if (mips_relax.sequence)
7486 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7490 case APPEND_ADD_COMPACT:
7491 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7492 gas_assert (mips_opts.mips16);
7493 ip->insn_opcode |= 0x0080;
7494 find_altered_mips16_opcode (ip);
7496 insert_into_history (0, 1, ip);
7501 struct mips_cl_insn delay = history[0];
7502 if (mips_opts.mips16)
7504 know (delay.frag == ip->frag);
7505 move_insn (ip, delay.frag, delay.where);
7506 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7508 else if (relaxed_branch || delay.frag != ip->frag)
7510 /* Add the delay slot instruction to the end of the
7511 current frag and shrink the fixed part of the
7512 original frag. If the branch occupies the tail of
7513 the latter, move it backwards to cover the gap. */
7514 delay.frag->fr_fix -= branch_disp;
7515 if (delay.frag == ip->frag)
7516 move_insn (ip, ip->frag, ip->where - branch_disp);
7517 add_fixed_insn (&delay);
7521 move_insn (&delay, ip->frag,
7522 ip->where - branch_disp + insn_length (ip));
7523 move_insn (ip, history[0].frag, history[0].where);
7527 insert_into_history (0, 1, &delay);
7532 /* If we have just completed an unconditional branch, clear the history. */
7533 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7534 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7538 mips_no_prev_insn ();
7540 for (i = 0; i < ARRAY_SIZE (history); i++)
7541 history[i].cleared_p = 1;
7544 /* We need to emit a label at the end of branch-likely macros. */
7545 if (emit_branch_likely_macro)
7547 emit_branch_likely_macro = FALSE;
7548 micromips_add_label ();
7551 /* We just output an insn, so the next one doesn't have a label. */
7552 mips_clear_insn_labels ();
7555 /* Forget that there was any previous instruction or label.
7556 When BRANCH is true, the branch history is also flushed. */
7559 mips_no_prev_insn (void)
7561 prev_nop_frag = NULL;
7562 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7563 mips_clear_insn_labels ();
7566 /* This function must be called before we emit something other than
7567 instructions. It is like mips_no_prev_insn except that it inserts
7568 any NOPS that might be needed by previous instructions. */
7571 mips_emit_delays (void)
7573 if (! mips_opts.noreorder)
7575 int nops = nops_for_insn (0, history, NULL);
7579 add_fixed_insn (NOP_INSN);
7580 mips_move_text_labels ();
7583 mips_no_prev_insn ();
7586 /* Start a (possibly nested) noreorder block. */
7589 start_noreorder (void)
7591 if (mips_opts.noreorder == 0)
7596 /* None of the instructions before the .set noreorder can be moved. */
7597 for (i = 0; i < ARRAY_SIZE (history); i++)
7598 history[i].fixed_p = 1;
7600 /* Insert any nops that might be needed between the .set noreorder
7601 block and the previous instructions. We will later remove any
7602 nops that turn out not to be needed. */
7603 nops = nops_for_insn (0, history, NULL);
7606 if (mips_optimize != 0)
7608 /* Record the frag which holds the nop instructions, so
7609 that we can remove them if we don't need them. */
7610 frag_grow (nops * NOP_INSN_SIZE);
7611 prev_nop_frag = frag_now;
7612 prev_nop_frag_holds = nops;
7613 prev_nop_frag_required = 0;
7614 prev_nop_frag_since = 0;
7617 for (; nops > 0; --nops)
7618 add_fixed_insn (NOP_INSN);
7620 /* Move on to a new frag, so that it is safe to simply
7621 decrease the size of prev_nop_frag. */
7622 frag_wane (frag_now);
7624 mips_move_text_labels ();
7626 mips_mark_labels ();
7627 mips_clear_insn_labels ();
7629 mips_opts.noreorder++;
7630 mips_any_noreorder = 1;
7633 /* End a nested noreorder block. */
7636 end_noreorder (void)
7638 mips_opts.noreorder--;
7639 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7641 /* Commit to inserting prev_nop_frag_required nops and go back to
7642 handling nop insertion the .set reorder way. */
7643 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7645 insert_into_history (prev_nop_frag_since,
7646 prev_nop_frag_required, NOP_INSN);
7647 prev_nop_frag = NULL;
7651 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7652 higher bits unset. */
7655 normalize_constant_expr (expressionS *ex)
7657 if (ex->X_op == O_constant
7658 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7659 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7663 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7664 all higher bits unset. */
7667 normalize_address_expr (expressionS *ex)
7669 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7670 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7671 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7672 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7676 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7677 Return true if the match was successful.
7679 OPCODE_EXTRA is a value that should be ORed into the opcode
7680 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7681 there are more alternatives after OPCODE and SOFT_MATCH is
7682 as for mips_arg_info. */
7685 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7686 struct mips_operand_token *tokens, unsigned int opcode_extra,
7687 bfd_boolean lax_match, bfd_boolean complete_p)
7690 struct mips_arg_info arg;
7691 const struct mips_operand *operand;
7694 imm_expr.X_op = O_absent;
7695 offset_expr.X_op = O_absent;
7696 offset_reloc[0] = BFD_RELOC_UNUSED;
7697 offset_reloc[1] = BFD_RELOC_UNUSED;
7698 offset_reloc[2] = BFD_RELOC_UNUSED;
7700 create_insn (insn, opcode);
7701 /* When no opcode suffix is specified, assume ".xyzw". */
7702 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7703 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7705 insn->insn_opcode |= opcode_extra;
7706 memset (&arg, 0, sizeof (arg));
7710 arg.last_regno = ILLEGAL_REG;
7711 arg.dest_regno = ILLEGAL_REG;
7712 arg.lax_match = lax_match;
7713 for (args = opcode->args;; ++args)
7715 if (arg.token->type == OT_END)
7717 /* Handle unary instructions in which only one operand is given.
7718 The source is then the same as the destination. */
7719 if (arg.opnum == 1 && *args == ',')
7721 operand = (mips_opts.micromips
7722 ? decode_micromips_operand (args + 1)
7723 : decode_mips_operand (args + 1));
7724 if (operand && mips_optional_operand_p (operand))
7732 /* Treat elided base registers as $0. */
7733 if (strcmp (args, "(b)") == 0)
7741 /* The register suffix is optional. */
7746 /* Fail the match if there were too few operands. */
7750 /* Successful match. */
7753 clear_insn_error ();
7754 if (arg.dest_regno == arg.last_regno
7755 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7759 (0, _("source and destination must be different"));
7760 else if (arg.last_regno == 31)
7762 (0, _("a destination register must be supplied"));
7764 else if (arg.last_regno == 31
7765 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7766 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7767 set_insn_error (0, _("the source register must not be $31"));
7768 check_completed_insn (&arg);
7772 /* Fail the match if the line has too many operands. */
7776 /* Handle characters that need to match exactly. */
7777 if (*args == '(' || *args == ')' || *args == ',')
7779 if (match_char (&arg, *args))
7786 if (arg.token->type == OT_DOUBLE_CHAR
7787 && arg.token->u.ch == *args)
7795 /* Handle special macro operands. Work out the properties of
7804 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7808 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7817 *offset_reloc = BFD_RELOC_MIPS_JMP;
7821 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7825 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7831 if (!match_const_int (&arg, &imm_expr.X_add_number))
7833 imm_expr.X_op = O_constant;
7835 normalize_constant_expr (&imm_expr);
7839 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7841 /* Assume that the offset has been elided and that what
7842 we saw was a base register. The match will fail later
7843 if that assumption turns out to be wrong. */
7844 offset_expr.X_op = O_constant;
7845 offset_expr.X_add_number = 0;
7849 if (!match_expression (&arg, &offset_expr, offset_reloc))
7851 normalize_address_expr (&offset_expr);
7856 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7862 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7868 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7874 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7880 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7884 *offset_reloc = BFD_RELOC_MIPS_JMP;
7888 gas_assert (mips_opts.micromips);
7894 if (!forced_insn_length)
7895 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7897 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7899 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7905 operand = (mips_opts.micromips
7906 ? decode_micromips_operand (args)
7907 : decode_mips_operand (args));
7911 /* Skip prefixes. */
7912 if (*args == '+' || *args == 'm' || *args == '-')
7915 if (mips_optional_operand_p (operand)
7917 && (arg.token[0].type != OT_REG
7918 || arg.token[1].type == OT_END))
7920 /* Assume that the register has been elided and is the
7921 same as the first operand. */
7926 if (!match_operand (&arg, operand))
7931 /* Like match_insn, but for MIPS16. */
7934 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7935 struct mips_operand_token *tokens)
7938 const struct mips_operand *operand;
7939 const struct mips_operand *ext_operand;
7940 struct mips_arg_info arg;
7943 create_insn (insn, opcode);
7944 imm_expr.X_op = O_absent;
7945 offset_expr.X_op = O_absent;
7946 offset_reloc[0] = BFD_RELOC_UNUSED;
7947 offset_reloc[1] = BFD_RELOC_UNUSED;
7948 offset_reloc[2] = BFD_RELOC_UNUSED;
7951 memset (&arg, 0, sizeof (arg));
7955 arg.last_regno = ILLEGAL_REG;
7956 arg.dest_regno = ILLEGAL_REG;
7958 for (args = opcode->args;; ++args)
7962 if (arg.token->type == OT_END)
7966 /* Handle unary instructions in which only one operand is given.
7967 The source is then the same as the destination. */
7968 if (arg.opnum == 1 && *args == ',')
7970 operand = decode_mips16_operand (args[1], FALSE);
7971 if (operand && mips_optional_operand_p (operand))
7979 /* Fail the match if there were too few operands. */
7983 /* Successful match. Stuff the immediate value in now, if
7985 clear_insn_error ();
7986 if (opcode->pinfo == INSN_MACRO)
7988 gas_assert (relax_char == 0 || relax_char == 'p');
7989 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7992 && offset_expr.X_op == O_constant
7993 && calculate_reloc (*offset_reloc,
7994 offset_expr.X_add_number,
7997 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7998 forced_insn_length, &insn->insn_opcode);
7999 offset_expr.X_op = O_absent;
8000 *offset_reloc = BFD_RELOC_UNUSED;
8002 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8004 if (forced_insn_length == 2)
8005 set_insn_error (0, _("invalid unextended operand value"));
8006 forced_insn_length = 4;
8007 insn->insn_opcode |= MIPS16_EXTEND;
8009 else if (relax_char)
8010 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8012 check_completed_insn (&arg);
8016 /* Fail the match if the line has too many operands. */
8020 /* Handle characters that need to match exactly. */
8021 if (*args == '(' || *args == ')' || *args == ',')
8023 if (match_char (&arg, *args))
8041 if (!match_const_int (&arg, &imm_expr.X_add_number))
8043 imm_expr.X_op = O_constant;
8045 normalize_constant_expr (&imm_expr);
8050 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8051 insn->insn_opcode <<= 16;
8055 operand = decode_mips16_operand (c, FALSE);
8059 /* '6' is a special case. It is used for BREAK and SDBBP,
8060 whose operands are only meaningful to the software that decodes
8061 them. This means that there is no architectural reason why
8062 they cannot be prefixed by EXTEND, but in practice,
8063 exception handlers will only look at the instruction
8064 itself. We therefore allow '6' to be extended when
8065 disassembling but not when assembling. */
8066 if (operand->type != OP_PCREL && c != '6')
8068 ext_operand = decode_mips16_operand (c, TRUE);
8069 if (operand != ext_operand)
8071 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8073 offset_expr.X_op = O_constant;
8074 offset_expr.X_add_number = 0;
8079 /* We need the OT_INTEGER check because some MIPS16
8080 immediate variants are listed before the register ones. */
8081 if (arg.token->type != OT_INTEGER
8082 || !match_expression (&arg, &offset_expr, offset_reloc))
8085 /* '8' is used for SLTI(U) and has traditionally not
8086 been allowed to take relocation operators. */
8087 if (offset_reloc[0] != BFD_RELOC_UNUSED
8088 && (ext_operand->size != 16 || c == '8'))
8096 if (mips_optional_operand_p (operand)
8098 && (arg.token[0].type != OT_REG
8099 || arg.token[1].type == OT_END))
8101 /* Assume that the register has been elided and is the
8102 same as the first operand. */
8107 if (!match_operand (&arg, operand))
8112 /* Record that the current instruction is invalid for the current ISA. */
8115 match_invalid_for_isa (void)
8118 (0, _("opcode not supported on this processor: %s (%s)"),
8119 mips_cpu_info_from_arch (mips_opts.arch)->name,
8120 mips_cpu_info_from_isa (mips_opts.isa)->name);
8123 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8124 Return true if a definite match or failure was found, storing any match
8125 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8126 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8127 tried and failed to match under normal conditions and now want to try a
8128 more relaxed match. */
8131 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8132 const struct mips_opcode *past, struct mips_operand_token *tokens,
8133 int opcode_extra, bfd_boolean lax_match)
8135 const struct mips_opcode *opcode;
8136 const struct mips_opcode *invalid_delay_slot;
8137 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8139 /* Search for a match, ignoring alternatives that don't satisfy the
8140 current ISA or forced_length. */
8141 invalid_delay_slot = 0;
8142 seen_valid_for_isa = FALSE;
8143 seen_valid_for_size = FALSE;
8147 gas_assert (strcmp (opcode->name, first->name) == 0);
8148 if (is_opcode_valid (opcode))
8150 seen_valid_for_isa = TRUE;
8151 if (is_size_valid (opcode))
8153 bfd_boolean delay_slot_ok;
8155 seen_valid_for_size = TRUE;
8156 delay_slot_ok = is_delay_slot_valid (opcode);
8157 if (match_insn (insn, opcode, tokens, opcode_extra,
8158 lax_match, delay_slot_ok))
8162 if (!invalid_delay_slot)
8163 invalid_delay_slot = opcode;
8172 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8174 /* If the only matches we found had the wrong length for the delay slot,
8175 pick the first such match. We'll issue an appropriate warning later. */
8176 if (invalid_delay_slot)
8178 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8184 /* Handle the case where we didn't try to match an instruction because
8185 all the alternatives were incompatible with the current ISA. */
8186 if (!seen_valid_for_isa)
8188 match_invalid_for_isa ();
8192 /* Handle the case where we didn't try to match an instruction because
8193 all the alternatives were of the wrong size. */
8194 if (!seen_valid_for_size)
8196 if (mips_opts.insn32)
8197 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8200 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8201 8 * forced_insn_length);
8208 /* Like match_insns, but for MIPS16. */
8211 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8212 struct mips_operand_token *tokens)
8214 const struct mips_opcode *opcode;
8215 bfd_boolean seen_valid_for_isa;
8217 /* Search for a match, ignoring alternatives that don't satisfy the
8218 current ISA. There are no separate entries for extended forms so
8219 we deal with forced_length later. */
8220 seen_valid_for_isa = FALSE;
8224 gas_assert (strcmp (opcode->name, first->name) == 0);
8225 if (is_opcode_valid_16 (opcode))
8227 seen_valid_for_isa = TRUE;
8228 if (match_mips16_insn (insn, opcode, tokens))
8233 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8234 && strcmp (opcode->name, first->name) == 0);
8236 /* Handle the case where we didn't try to match an instruction because
8237 all the alternatives were incompatible with the current ISA. */
8238 if (!seen_valid_for_isa)
8240 match_invalid_for_isa ();
8247 /* Set up global variables for the start of a new macro. */
8252 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8253 memset (&mips_macro_warning.first_insn_sizes, 0,
8254 sizeof (mips_macro_warning.first_insn_sizes));
8255 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8256 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8257 && delayed_branch_p (&history[0]));
8258 switch (history[0].insn_mo->pinfo2
8259 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8261 case INSN2_BRANCH_DELAY_32BIT:
8262 mips_macro_warning.delay_slot_length = 4;
8264 case INSN2_BRANCH_DELAY_16BIT:
8265 mips_macro_warning.delay_slot_length = 2;
8268 mips_macro_warning.delay_slot_length = 0;
8271 mips_macro_warning.first_frag = NULL;
8274 /* Given that a macro is longer than one instruction or of the wrong size,
8275 return the appropriate warning for it. Return null if no warning is
8276 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8277 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8278 and RELAX_NOMACRO. */
8281 macro_warning (relax_substateT subtype)
8283 if (subtype & RELAX_DELAY_SLOT)
8284 return _("macro instruction expanded into multiple instructions"
8285 " in a branch delay slot");
8286 else if (subtype & RELAX_NOMACRO)
8287 return _("macro instruction expanded into multiple instructions");
8288 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8289 | RELAX_DELAY_SLOT_SIZE_SECOND))
8290 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8291 ? _("macro instruction expanded into a wrong size instruction"
8292 " in a 16-bit branch delay slot")
8293 : _("macro instruction expanded into a wrong size instruction"
8294 " in a 32-bit branch delay slot"));
8299 /* Finish up a macro. Emit warnings as appropriate. */
8304 /* Relaxation warning flags. */
8305 relax_substateT subtype = 0;
8307 /* Check delay slot size requirements. */
8308 if (mips_macro_warning.delay_slot_length == 2)
8309 subtype |= RELAX_DELAY_SLOT_16BIT;
8310 if (mips_macro_warning.delay_slot_length != 0)
8312 if (mips_macro_warning.delay_slot_length
8313 != mips_macro_warning.first_insn_sizes[0])
8314 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8315 if (mips_macro_warning.delay_slot_length
8316 != mips_macro_warning.first_insn_sizes[1])
8317 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8320 /* Check instruction count requirements. */
8321 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8323 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8324 subtype |= RELAX_SECOND_LONGER;
8325 if (mips_opts.warn_about_macros)
8326 subtype |= RELAX_NOMACRO;
8327 if (mips_macro_warning.delay_slot_p)
8328 subtype |= RELAX_DELAY_SLOT;
8331 /* If both alternatives fail to fill a delay slot correctly,
8332 emit the warning now. */
8333 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8334 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8339 s = subtype & (RELAX_DELAY_SLOT_16BIT
8340 | RELAX_DELAY_SLOT_SIZE_FIRST
8341 | RELAX_DELAY_SLOT_SIZE_SECOND);
8342 msg = macro_warning (s);
8344 as_warn ("%s", msg);
8348 /* If both implementations are longer than 1 instruction, then emit the
8350 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8355 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8356 msg = macro_warning (s);
8358 as_warn ("%s", msg);
8362 /* If any flags still set, then one implementation might need a warning
8363 and the other either will need one of a different kind or none at all.
8364 Pass any remaining flags over to relaxation. */
8365 if (mips_macro_warning.first_frag != NULL)
8366 mips_macro_warning.first_frag->fr_subtype |= subtype;
8369 /* Instruction operand formats used in macros that vary between
8370 standard MIPS and microMIPS code. */
8372 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8373 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8374 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8375 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8376 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8377 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8378 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8379 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8381 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8382 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8383 : cop12_fmt[mips_opts.micromips])
8384 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8385 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8386 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8387 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8388 : mem12_fmt[mips_opts.micromips])
8389 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8390 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8391 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8393 /* Read a macro's relocation codes from *ARGS and store them in *R.
8394 The first argument in *ARGS will be either the code for a single
8395 relocation or -1 followed by the three codes that make up a
8396 composite relocation. */
8399 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8403 next = va_arg (*args, int);
8405 r[0] = (bfd_reloc_code_real_type) next;
8408 for (i = 0; i < 3; i++)
8409 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8410 /* This function is only used for 16-bit relocation fields.
8411 To make the macro code simpler, treat an unrelocated value
8412 in the same way as BFD_RELOC_LO16. */
8413 if (r[0] == BFD_RELOC_UNUSED)
8414 r[0] = BFD_RELOC_LO16;
8418 /* Build an instruction created by a macro expansion. This is passed
8419 a pointer to the count of instructions created so far, an
8420 expression, the name of the instruction to build, an operand format
8421 string, and corresponding arguments. */
8424 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8426 const struct mips_opcode *mo = NULL;
8427 bfd_reloc_code_real_type r[3];
8428 const struct mips_opcode *amo;
8429 const struct mips_operand *operand;
8430 struct hash_control *hash;
8431 struct mips_cl_insn insn;
8435 va_start (args, fmt);
8437 if (mips_opts.mips16)
8439 mips16_macro_build (ep, name, fmt, &args);
8444 r[0] = BFD_RELOC_UNUSED;
8445 r[1] = BFD_RELOC_UNUSED;
8446 r[2] = BFD_RELOC_UNUSED;
8447 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8448 amo = (struct mips_opcode *) hash_find (hash, name);
8450 gas_assert (strcmp (name, amo->name) == 0);
8454 /* Search until we get a match for NAME. It is assumed here that
8455 macros will never generate MDMX, MIPS-3D, or MT instructions.
8456 We try to match an instruction that fulfils the branch delay
8457 slot instruction length requirement (if any) of the previous
8458 instruction. While doing this we record the first instruction
8459 seen that matches all the other conditions and use it anyway
8460 if the requirement cannot be met; we will issue an appropriate
8461 warning later on. */
8462 if (strcmp (fmt, amo->args) == 0
8463 && amo->pinfo != INSN_MACRO
8464 && is_opcode_valid (amo)
8465 && is_size_valid (amo))
8467 if (is_delay_slot_valid (amo))
8477 gas_assert (amo->name);
8479 while (strcmp (name, amo->name) == 0);
8482 create_insn (&insn, mo);
8495 macro_read_relocs (&args, r);
8496 gas_assert (*r == BFD_RELOC_GPREL16
8497 || *r == BFD_RELOC_MIPS_HIGHER
8498 || *r == BFD_RELOC_HI16_S
8499 || *r == BFD_RELOC_LO16
8500 || *r == BFD_RELOC_MIPS_GOT_OFST);
8504 macro_read_relocs (&args, r);
8508 macro_read_relocs (&args, r);
8509 gas_assert (ep != NULL
8510 && (ep->X_op == O_constant
8511 || (ep->X_op == O_symbol
8512 && (*r == BFD_RELOC_MIPS_HIGHEST
8513 || *r == BFD_RELOC_HI16_S
8514 || *r == BFD_RELOC_HI16
8515 || *r == BFD_RELOC_GPREL16
8516 || *r == BFD_RELOC_MIPS_GOT_HI16
8517 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8521 gas_assert (ep != NULL);
8524 * This allows macro() to pass an immediate expression for
8525 * creating short branches without creating a symbol.
8527 * We don't allow branch relaxation for these branches, as
8528 * they should only appear in ".set nomacro" anyway.
8530 if (ep->X_op == O_constant)
8532 /* For microMIPS we always use relocations for branches.
8533 So we should not resolve immediate values. */
8534 gas_assert (!mips_opts.micromips);
8536 if ((ep->X_add_number & 3) != 0)
8537 as_bad (_("branch to misaligned address (0x%lx)"),
8538 (unsigned long) ep->X_add_number);
8539 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8540 as_bad (_("branch address range overflow (0x%lx)"),
8541 (unsigned long) ep->X_add_number);
8542 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8546 *r = BFD_RELOC_16_PCREL_S2;
8550 gas_assert (ep != NULL);
8551 *r = BFD_RELOC_MIPS_JMP;
8555 operand = (mips_opts.micromips
8556 ? decode_micromips_operand (fmt)
8557 : decode_mips_operand (fmt));
8561 uval = va_arg (args, int);
8562 if (operand->type == OP_CLO_CLZ_DEST)
8563 uval |= (uval << 5);
8564 insn_insert_operand (&insn, operand, uval);
8566 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8572 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8574 append_insn (&insn, ep, r, TRUE);
8578 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8581 struct mips_opcode *mo;
8582 struct mips_cl_insn insn;
8583 const struct mips_operand *operand;
8584 bfd_reloc_code_real_type r[3]
8585 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8587 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8589 gas_assert (strcmp (name, mo->name) == 0);
8591 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8594 gas_assert (mo->name);
8595 gas_assert (strcmp (name, mo->name) == 0);
8598 create_insn (&insn, mo);
8636 gas_assert (ep != NULL);
8638 if (ep->X_op != O_constant)
8639 *r = (int) BFD_RELOC_UNUSED + c;
8640 else if (calculate_reloc (*r, ep->X_add_number, &value))
8642 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8644 *r = BFD_RELOC_UNUSED;
8650 operand = decode_mips16_operand (c, FALSE);
8654 insn_insert_operand (&insn, operand, va_arg (*args, int));
8659 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8661 append_insn (&insn, ep, r, TRUE);
8665 * Generate a "jalr" instruction with a relocation hint to the called
8666 * function. This occurs in NewABI PIC code.
8669 macro_build_jalr (expressionS *ep, int cprestore)
8671 static const bfd_reloc_code_real_type jalr_relocs[2]
8672 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8673 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8677 if (MIPS_JALR_HINT_P (ep))
8682 if (mips_opts.micromips)
8684 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8685 ? "jalr" : "jalrs");
8686 if (MIPS_JALR_HINT_P (ep)
8688 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8689 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8691 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8694 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8695 if (MIPS_JALR_HINT_P (ep))
8696 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8700 * Generate a "lui" instruction.
8703 macro_build_lui (expressionS *ep, int regnum)
8705 gas_assert (! mips_opts.mips16);
8707 if (ep->X_op != O_constant)
8709 gas_assert (ep->X_op == O_symbol);
8710 /* _gp_disp is a special case, used from s_cpload.
8711 __gnu_local_gp is used if mips_no_shared. */
8712 gas_assert (mips_pic == NO_PIC
8714 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8715 || (! mips_in_shared
8716 && strcmp (S_GET_NAME (ep->X_add_symbol),
8717 "__gnu_local_gp") == 0));
8720 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8723 /* Generate a sequence of instructions to do a load or store from a constant
8724 offset off of a base register (breg) into/from a target register (treg),
8725 using AT if necessary. */
8727 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8728 int treg, int breg, int dbl)
8730 gas_assert (ep->X_op == O_constant);
8732 /* Sign-extending 32-bit constants makes their handling easier. */
8734 normalize_constant_expr (ep);
8736 /* Right now, this routine can only handle signed 32-bit constants. */
8737 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8738 as_warn (_("operand overflow"));
8740 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8742 /* Signed 16-bit offset will fit in the op. Easy! */
8743 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8747 /* 32-bit offset, need multiple instructions and AT, like:
8748 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8749 addu $tempreg,$tempreg,$breg
8750 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8751 to handle the complete offset. */
8752 macro_build_lui (ep, AT);
8753 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8754 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8757 as_bad (_("macro used $at after \".set noat\""));
8762 * Generates code to set the $at register to true (one)
8763 * if reg is less than the immediate expression.
8766 set_at (int reg, int unsignedp)
8768 if (imm_expr.X_add_number >= -0x8000
8769 && imm_expr.X_add_number < 0x8000)
8770 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8771 AT, reg, BFD_RELOC_LO16);
8774 load_register (AT, &imm_expr, GPR_SIZE == 64);
8775 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8779 /* Count the leading zeroes by performing a binary chop. This is a
8780 bulky bit of source, but performance is a LOT better for the
8781 majority of values than a simple loop to count the bits:
8782 for (lcnt = 0; (lcnt < 32); lcnt++)
8783 if ((v) & (1 << (31 - lcnt)))
8785 However it is not code size friendly, and the gain will drop a bit
8786 on certain cached systems.
8788 #define COUNT_TOP_ZEROES(v) \
8789 (((v) & ~0xffff) == 0 \
8790 ? ((v) & ~0xff) == 0 \
8791 ? ((v) & ~0xf) == 0 \
8792 ? ((v) & ~0x3) == 0 \
8793 ? ((v) & ~0x1) == 0 \
8798 : ((v) & ~0x7) == 0 \
8801 : ((v) & ~0x3f) == 0 \
8802 ? ((v) & ~0x1f) == 0 \
8805 : ((v) & ~0x7f) == 0 \
8808 : ((v) & ~0xfff) == 0 \
8809 ? ((v) & ~0x3ff) == 0 \
8810 ? ((v) & ~0x1ff) == 0 \
8813 : ((v) & ~0x7ff) == 0 \
8816 : ((v) & ~0x3fff) == 0 \
8817 ? ((v) & ~0x1fff) == 0 \
8820 : ((v) & ~0x7fff) == 0 \
8823 : ((v) & ~0xffffff) == 0 \
8824 ? ((v) & ~0xfffff) == 0 \
8825 ? ((v) & ~0x3ffff) == 0 \
8826 ? ((v) & ~0x1ffff) == 0 \
8829 : ((v) & ~0x7ffff) == 0 \
8832 : ((v) & ~0x3fffff) == 0 \
8833 ? ((v) & ~0x1fffff) == 0 \
8836 : ((v) & ~0x7fffff) == 0 \
8839 : ((v) & ~0xfffffff) == 0 \
8840 ? ((v) & ~0x3ffffff) == 0 \
8841 ? ((v) & ~0x1ffffff) == 0 \
8844 : ((v) & ~0x7ffffff) == 0 \
8847 : ((v) & ~0x3fffffff) == 0 \
8848 ? ((v) & ~0x1fffffff) == 0 \
8851 : ((v) & ~0x7fffffff) == 0 \
8856 * This routine generates the least number of instructions necessary to load
8857 * an absolute expression value into a register.
8860 load_register (int reg, expressionS *ep, int dbl)
8863 expressionS hi32, lo32;
8865 if (ep->X_op != O_big)
8867 gas_assert (ep->X_op == O_constant);
8869 /* Sign-extending 32-bit constants makes their handling easier. */
8871 normalize_constant_expr (ep);
8873 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8875 /* We can handle 16 bit signed values with an addiu to
8876 $zero. No need to ever use daddiu here, since $zero and
8877 the result are always correct in 32 bit mode. */
8878 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8881 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8883 /* We can handle 16 bit unsigned values with an ori to
8885 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8888 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8890 /* 32 bit values require an lui. */
8891 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8892 if ((ep->X_add_number & 0xffff) != 0)
8893 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8898 /* The value is larger than 32 bits. */
8900 if (!dbl || GPR_SIZE == 32)
8904 sprintf_vma (value, ep->X_add_number);
8905 as_bad (_("number (0x%s) larger than 32 bits"), value);
8906 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8910 if (ep->X_op != O_big)
8913 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8914 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8915 hi32.X_add_number &= 0xffffffff;
8917 lo32.X_add_number &= 0xffffffff;
8921 gas_assert (ep->X_add_number > 2);
8922 if (ep->X_add_number == 3)
8923 generic_bignum[3] = 0;
8924 else if (ep->X_add_number > 4)
8925 as_bad (_("number larger than 64 bits"));
8926 lo32.X_op = O_constant;
8927 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8928 hi32.X_op = O_constant;
8929 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8932 if (hi32.X_add_number == 0)
8937 unsigned long hi, lo;
8939 if (hi32.X_add_number == (offsetT) 0xffffffff)
8941 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8943 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8946 if (lo32.X_add_number & 0x80000000)
8948 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8949 if (lo32.X_add_number & 0xffff)
8950 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8955 /* Check for 16bit shifted constant. We know that hi32 is
8956 non-zero, so start the mask on the first bit of the hi32
8961 unsigned long himask, lomask;
8965 himask = 0xffff >> (32 - shift);
8966 lomask = (0xffff << shift) & 0xffffffff;
8970 himask = 0xffff << (shift - 32);
8973 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8974 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8978 tmp.X_op = O_constant;
8980 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8981 | (lo32.X_add_number >> shift));
8983 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8984 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8985 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8986 reg, reg, (shift >= 32) ? shift - 32 : shift);
8991 while (shift <= (64 - 16));
8993 /* Find the bit number of the lowest one bit, and store the
8994 shifted value in hi/lo. */
8995 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8996 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9000 while ((lo & 1) == 0)
9005 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9011 while ((hi & 1) == 0)
9020 /* Optimize if the shifted value is a (power of 2) - 1. */
9021 if ((hi == 0 && ((lo + 1) & lo) == 0)
9022 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9024 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9029 /* This instruction will set the register to be all
9031 tmp.X_op = O_constant;
9032 tmp.X_add_number = (offsetT) -1;
9033 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9037 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9038 reg, reg, (bit >= 32) ? bit - 32 : bit);
9040 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9041 reg, reg, (shift >= 32) ? shift - 32 : shift);
9046 /* Sign extend hi32 before calling load_register, because we can
9047 generally get better code when we load a sign extended value. */
9048 if ((hi32.X_add_number & 0x80000000) != 0)
9049 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9050 load_register (reg, &hi32, 0);
9053 if ((lo32.X_add_number & 0xffff0000) == 0)
9057 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9065 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9067 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9068 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9074 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9078 mid16.X_add_number >>= 16;
9079 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9080 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9083 if ((lo32.X_add_number & 0xffff) != 0)
9084 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9088 load_delay_nop (void)
9090 if (!gpr_interlocks)
9091 macro_build (NULL, "nop", "");
9094 /* Load an address into a register. */
9097 load_address (int reg, expressionS *ep, int *used_at)
9099 if (ep->X_op != O_constant
9100 && ep->X_op != O_symbol)
9102 as_bad (_("expression too complex"));
9103 ep->X_op = O_constant;
9106 if (ep->X_op == O_constant)
9108 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9112 if (mips_pic == NO_PIC)
9114 /* If this is a reference to a GP relative symbol, we want
9115 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9117 lui $reg,<sym> (BFD_RELOC_HI16_S)
9118 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9119 If we have an addend, we always use the latter form.
9121 With 64bit address space and a usable $at we want
9122 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9123 lui $at,<sym> (BFD_RELOC_HI16_S)
9124 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9125 daddiu $at,<sym> (BFD_RELOC_LO16)
9129 If $at is already in use, we use a path which is suboptimal
9130 on superscalar processors.
9131 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9132 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9134 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9136 daddiu $reg,<sym> (BFD_RELOC_LO16)
9138 For GP relative symbols in 64bit address space we can use
9139 the same sequence as in 32bit address space. */
9140 if (HAVE_64BIT_SYMBOLS)
9142 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9143 && !nopic_need_relax (ep->X_add_symbol, 1))
9145 relax_start (ep->X_add_symbol);
9146 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9147 mips_gp_register, BFD_RELOC_GPREL16);
9151 if (*used_at == 0 && mips_opts.at)
9153 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9154 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9155 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9156 BFD_RELOC_MIPS_HIGHER);
9157 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9158 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9159 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9164 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9165 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9166 BFD_RELOC_MIPS_HIGHER);
9167 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9168 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9169 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9170 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9173 if (mips_relax.sequence)
9178 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9179 && !nopic_need_relax (ep->X_add_symbol, 1))
9181 relax_start (ep->X_add_symbol);
9182 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9183 mips_gp_register, BFD_RELOC_GPREL16);
9186 macro_build_lui (ep, reg);
9187 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9188 reg, reg, BFD_RELOC_LO16);
9189 if (mips_relax.sequence)
9193 else if (!mips_big_got)
9197 /* If this is a reference to an external symbol, we want
9198 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9200 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9202 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9203 If there is a constant, it must be added in after.
9205 If we have NewABI, we want
9206 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9207 unless we're referencing a global symbol with a non-zero
9208 offset, in which case cst must be added separately. */
9211 if (ep->X_add_number)
9213 ex.X_add_number = ep->X_add_number;
9214 ep->X_add_number = 0;
9215 relax_start (ep->X_add_symbol);
9216 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9217 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9218 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9219 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9220 ex.X_op = O_constant;
9221 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9222 reg, reg, BFD_RELOC_LO16);
9223 ep->X_add_number = ex.X_add_number;
9226 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9227 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9228 if (mips_relax.sequence)
9233 ex.X_add_number = ep->X_add_number;
9234 ep->X_add_number = 0;
9235 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9236 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9238 relax_start (ep->X_add_symbol);
9240 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9244 if (ex.X_add_number != 0)
9246 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9247 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9248 ex.X_op = O_constant;
9249 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9250 reg, reg, BFD_RELOC_LO16);
9254 else if (mips_big_got)
9258 /* This is the large GOT case. If this is a reference to an
9259 external symbol, we want
9260 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9262 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9264 Otherwise, for a reference to a local symbol in old ABI, we want
9265 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9267 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9268 If there is a constant, it must be added in after.
9270 In the NewABI, for local symbols, with or without offsets, we want:
9271 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9272 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9276 ex.X_add_number = ep->X_add_number;
9277 ep->X_add_number = 0;
9278 relax_start (ep->X_add_symbol);
9279 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9280 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9281 reg, reg, mips_gp_register);
9282 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9283 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9284 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9285 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9286 else if (ex.X_add_number)
9288 ex.X_op = O_constant;
9289 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9293 ep->X_add_number = ex.X_add_number;
9295 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9296 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9297 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9298 BFD_RELOC_MIPS_GOT_OFST);
9303 ex.X_add_number = ep->X_add_number;
9304 ep->X_add_number = 0;
9305 relax_start (ep->X_add_symbol);
9306 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9307 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9308 reg, reg, mips_gp_register);
9309 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9310 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9312 if (reg_needs_delay (mips_gp_register))
9314 /* We need a nop before loading from $gp. This special
9315 check is required because the lui which starts the main
9316 instruction stream does not refer to $gp, and so will not
9317 insert the nop which may be required. */
9318 macro_build (NULL, "nop", "");
9320 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9321 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9323 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9327 if (ex.X_add_number != 0)
9329 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9330 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9331 ex.X_op = O_constant;
9332 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9340 if (!mips_opts.at && *used_at == 1)
9341 as_bad (_("macro used $at after \".set noat\""));
9344 /* Move the contents of register SOURCE into register DEST. */
9347 move_register (int dest, int source)
9349 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9350 instruction specifically requires a 32-bit one. */
9351 if (mips_opts.micromips
9352 && !mips_opts.insn32
9353 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9354 macro_build (NULL, "move", "mp,mj", dest, source);
9356 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9359 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9360 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9361 The two alternatives are:
9363 Global symbol Local sybmol
9364 ------------- ------------
9365 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9367 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9369 load_got_offset emits the first instruction and add_got_offset
9370 emits the second for a 16-bit offset or add_got_offset_hilo emits
9371 a sequence to add a 32-bit offset using a scratch register. */
9374 load_got_offset (int dest, expressionS *local)
9379 global.X_add_number = 0;
9381 relax_start (local->X_add_symbol);
9382 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9383 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9385 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9386 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9391 add_got_offset (int dest, expressionS *local)
9395 global.X_op = O_constant;
9396 global.X_op_symbol = NULL;
9397 global.X_add_symbol = NULL;
9398 global.X_add_number = local->X_add_number;
9400 relax_start (local->X_add_symbol);
9401 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9402 dest, dest, BFD_RELOC_LO16);
9404 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9409 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9412 int hold_mips_optimize;
9414 global.X_op = O_constant;
9415 global.X_op_symbol = NULL;
9416 global.X_add_symbol = NULL;
9417 global.X_add_number = local->X_add_number;
9419 relax_start (local->X_add_symbol);
9420 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9422 /* Set mips_optimize around the lui instruction to avoid
9423 inserting an unnecessary nop after the lw. */
9424 hold_mips_optimize = mips_optimize;
9426 macro_build_lui (&global, tmp);
9427 mips_optimize = hold_mips_optimize;
9428 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9434 /* Emit a sequence of instructions to emulate a branch likely operation.
9435 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9436 is its complementing branch with the original condition negated.
9437 CALL is set if the original branch specified the link operation.
9438 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9440 Code like this is produced in the noreorder mode:
9445 delay slot (executed only if branch taken)
9453 delay slot (executed only if branch taken)
9456 In the reorder mode the delay slot would be filled with a nop anyway,
9457 so code produced is simply:
9462 This function is used when producing code for the microMIPS ASE that
9463 does not implement branch likely instructions in hardware. */
9466 macro_build_branch_likely (const char *br, const char *brneg,
9467 int call, expressionS *ep, const char *fmt,
9468 unsigned int sreg, unsigned int treg)
9470 int noreorder = mips_opts.noreorder;
9473 gas_assert (mips_opts.micromips);
9477 micromips_label_expr (&expr1);
9478 macro_build (&expr1, brneg, fmt, sreg, treg);
9479 macro_build (NULL, "nop", "");
9480 macro_build (ep, call ? "bal" : "b", "p");
9482 /* Set to true so that append_insn adds a label. */
9483 emit_branch_likely_macro = TRUE;
9487 macro_build (ep, br, fmt, sreg, treg);
9488 macro_build (NULL, "nop", "");
9493 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9494 the condition code tested. EP specifies the branch target. */
9497 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9524 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9527 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9528 the register tested. EP specifies the branch target. */
9531 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9533 const char *brneg = NULL;
9543 br = mips_opts.micromips ? "bgez" : "bgezl";
9547 gas_assert (mips_opts.micromips);
9548 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9556 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9563 br = mips_opts.micromips ? "blez" : "blezl";
9570 br = mips_opts.micromips ? "bltz" : "bltzl";
9574 gas_assert (mips_opts.micromips);
9575 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9582 if (mips_opts.micromips && brneg)
9583 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9585 macro_build (ep, br, "s,p", sreg);
9588 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9589 TREG as the registers tested. EP specifies the branch target. */
9592 macro_build_branch_rsrt (int type, expressionS *ep,
9593 unsigned int sreg, unsigned int treg)
9595 const char *brneg = NULL;
9607 br = mips_opts.micromips ? "beq" : "beql";
9616 br = mips_opts.micromips ? "bne" : "bnel";
9622 if (mips_opts.micromips && brneg)
9623 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9625 macro_build (ep, br, "s,t,p", sreg, treg);
9628 /* Return the high part that should be loaded in order to make the low
9629 part of VALUE accessible using an offset of OFFBITS bits. */
9632 offset_high_part (offsetT value, unsigned int offbits)
9639 bias = 1 << (offbits - 1);
9640 low_mask = bias * 2 - 1;
9641 return (value + bias) & ~low_mask;
9644 /* Return true if the value stored in offset_expr and offset_reloc
9645 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9646 amount that the caller wants to add without inducing overflow
9647 and ALIGN is the known alignment of the value in bytes. */
9650 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9654 /* Accept any relocation operator if overflow isn't a concern. */
9655 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9658 /* These relocations are guaranteed not to overflow in correct links. */
9659 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9660 || gprel16_reloc_p (*offset_reloc))
9663 if (offset_expr.X_op == O_constant
9664 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9665 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9672 * This routine implements the seemingly endless macro or synthesized
9673 * instructions and addressing modes in the mips assembly language. Many
9674 * of these macros are simple and are similar to each other. These could
9675 * probably be handled by some kind of table or grammar approach instead of
9676 * this verbose method. Others are not simple macros but are more like
9677 * optimizing code generation.
9678 * One interesting optimization is when several store macros appear
9679 * consecutively that would load AT with the upper half of the same address.
9680 * The ensuing load upper instructions are ommited. This implies some kind
9681 * of global optimization. We currently only optimize within a single macro.
9682 * For many of the load and store macros if the address is specified as a
9683 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9684 * first load register 'at' with zero and use it as the base register. The
9685 * mips assembler simply uses register $zero. Just one tiny optimization
9689 macro (struct mips_cl_insn *ip, char *str)
9691 const struct mips_operand_array *operands;
9692 unsigned int breg, i;
9693 unsigned int tempreg;
9696 expressionS label_expr;
9711 bfd_boolean large_offset;
9713 int hold_mips_optimize;
9715 unsigned int op[MAX_OPERANDS];
9717 gas_assert (! mips_opts.mips16);
9719 operands = insn_operands (ip);
9720 for (i = 0; i < MAX_OPERANDS; i++)
9721 if (operands->operand[i])
9722 op[i] = insn_extract_operand (ip, operands->operand[i]);
9726 mask = ip->insn_mo->mask;
9728 label_expr.X_op = O_constant;
9729 label_expr.X_op_symbol = NULL;
9730 label_expr.X_add_symbol = NULL;
9731 label_expr.X_add_number = 0;
9733 expr1.X_op = O_constant;
9734 expr1.X_op_symbol = NULL;
9735 expr1.X_add_symbol = NULL;
9736 expr1.X_add_number = 1;
9752 if (mips_opts.micromips)
9753 micromips_label_expr (&label_expr);
9755 label_expr.X_add_number = 8;
9756 macro_build (&label_expr, "bgez", "s,p", op[1]);
9758 macro_build (NULL, "nop", "");
9760 move_register (op[0], op[1]);
9761 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9762 if (mips_opts.micromips)
9763 micromips_add_label ();
9780 if (!mips_opts.micromips)
9782 if (imm_expr.X_add_number >= -0x200
9783 && imm_expr.X_add_number < 0x200)
9785 macro_build (NULL, s, "t,r,.", op[0], op[1],
9786 (int) imm_expr.X_add_number);
9795 if (imm_expr.X_add_number >= -0x8000
9796 && imm_expr.X_add_number < 0x8000)
9798 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9803 load_register (AT, &imm_expr, dbl);
9804 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9823 if (imm_expr.X_add_number >= 0
9824 && imm_expr.X_add_number < 0x10000)
9826 if (mask != M_NOR_I)
9827 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9830 macro_build (&imm_expr, "ori", "t,r,i",
9831 op[0], op[1], BFD_RELOC_LO16);
9832 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9838 load_register (AT, &imm_expr, GPR_SIZE == 64);
9839 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9843 switch (imm_expr.X_add_number)
9846 macro_build (NULL, "nop", "");
9849 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9853 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9854 (int) imm_expr.X_add_number);
9857 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9858 (unsigned long) imm_expr.X_add_number);
9867 gas_assert (mips_opts.micromips);
9868 macro_build_branch_ccl (mask, &offset_expr,
9869 EXTRACT_OPERAND (1, BCC, *ip));
9876 if (imm_expr.X_add_number == 0)
9882 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9887 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9894 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9895 else if (op[0] == 0)
9896 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9900 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9901 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9902 &offset_expr, AT, ZERO);
9912 macro_build_branch_rs (mask, &offset_expr, op[0]);
9918 /* Check for > max integer. */
9919 if (imm_expr.X_add_number >= GPR_SMAX)
9922 /* Result is always false. */
9924 macro_build (NULL, "nop", "");
9926 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9929 ++imm_expr.X_add_number;
9933 if (mask == M_BGEL_I)
9935 if (imm_expr.X_add_number == 0)
9937 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9938 &offset_expr, op[0]);
9941 if (imm_expr.X_add_number == 1)
9943 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9944 &offset_expr, op[0]);
9947 if (imm_expr.X_add_number <= GPR_SMIN)
9950 /* result is always true */
9951 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9952 macro_build (&offset_expr, "b", "p");
9957 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9958 &offset_expr, AT, ZERO);
9966 else if (op[0] == 0)
9967 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9968 &offset_expr, ZERO, op[1]);
9972 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9973 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9974 &offset_expr, AT, ZERO);
9983 && imm_expr.X_add_number == -1))
9985 ++imm_expr.X_add_number;
9989 if (mask == M_BGEUL_I)
9991 if (imm_expr.X_add_number == 0)
9993 else if (imm_expr.X_add_number == 1)
9994 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9995 &offset_expr, op[0], ZERO);
10000 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10001 &offset_expr, AT, ZERO);
10009 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10010 else if (op[0] == 0)
10011 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10015 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10016 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10017 &offset_expr, AT, ZERO);
10025 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10026 &offset_expr, op[0], ZERO);
10027 else if (op[0] == 0)
10032 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10033 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10034 &offset_expr, AT, ZERO);
10042 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10043 else if (op[0] == 0)
10044 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10048 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10049 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10050 &offset_expr, AT, ZERO);
10057 if (imm_expr.X_add_number >= GPR_SMAX)
10059 ++imm_expr.X_add_number;
10063 if (mask == M_BLTL_I)
10065 if (imm_expr.X_add_number == 0)
10066 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10067 else if (imm_expr.X_add_number == 1)
10068 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10073 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10074 &offset_expr, AT, ZERO);
10082 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10083 &offset_expr, op[0], ZERO);
10084 else if (op[0] == 0)
10089 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10090 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10091 &offset_expr, AT, ZERO);
10100 && imm_expr.X_add_number == -1))
10102 ++imm_expr.X_add_number;
10106 if (mask == M_BLTUL_I)
10108 if (imm_expr.X_add_number == 0)
10110 else if (imm_expr.X_add_number == 1)
10111 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10112 &offset_expr, op[0], ZERO);
10117 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10118 &offset_expr, AT, ZERO);
10126 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10127 else if (op[0] == 0)
10128 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10132 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10133 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10134 &offset_expr, AT, ZERO);
10143 else if (op[0] == 0)
10144 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10145 &offset_expr, ZERO, op[1]);
10149 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10150 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10151 &offset_expr, AT, ZERO);
10167 as_warn (_("divide by zero"));
10169 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10171 macro_build (NULL, "break", BRK_FMT, 7);
10175 start_noreorder ();
10178 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10179 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10183 if (mips_opts.micromips)
10184 micromips_label_expr (&label_expr);
10186 label_expr.X_add_number = 8;
10187 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10188 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10189 macro_build (NULL, "break", BRK_FMT, 7);
10190 if (mips_opts.micromips)
10191 micromips_add_label ();
10193 expr1.X_add_number = -1;
10195 load_register (AT, &expr1, dbl);
10196 if (mips_opts.micromips)
10197 micromips_label_expr (&label_expr);
10199 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10200 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10203 expr1.X_add_number = 1;
10204 load_register (AT, &expr1, dbl);
10205 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10209 expr1.X_add_number = 0x80000000;
10210 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10214 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10215 /* We want to close the noreorder block as soon as possible, so
10216 that later insns are available for delay slot filling. */
10221 if (mips_opts.micromips)
10222 micromips_label_expr (&label_expr);
10224 label_expr.X_add_number = 8;
10225 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10226 macro_build (NULL, "nop", "");
10228 /* We want to close the noreorder block as soon as possible, so
10229 that later insns are available for delay slot filling. */
10232 macro_build (NULL, "break", BRK_FMT, 6);
10234 if (mips_opts.micromips)
10235 micromips_add_label ();
10236 macro_build (NULL, s, MFHL_FMT, op[0]);
10275 if (imm_expr.X_add_number == 0)
10277 as_warn (_("divide by zero"));
10279 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10281 macro_build (NULL, "break", BRK_FMT, 7);
10284 if (imm_expr.X_add_number == 1)
10286 if (strcmp (s2, "mflo") == 0)
10287 move_register (op[0], op[1]);
10289 move_register (op[0], ZERO);
10292 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10294 if (strcmp (s2, "mflo") == 0)
10295 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10297 move_register (op[0], ZERO);
10302 load_register (AT, &imm_expr, dbl);
10303 macro_build (NULL, s, "z,s,t", op[1], AT);
10304 macro_build (NULL, s2, MFHL_FMT, op[0]);
10323 start_noreorder ();
10326 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10327 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10328 /* We want to close the noreorder block as soon as possible, so
10329 that later insns are available for delay slot filling. */
10334 if (mips_opts.micromips)
10335 micromips_label_expr (&label_expr);
10337 label_expr.X_add_number = 8;
10338 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10339 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10341 /* We want to close the noreorder block as soon as possible, so
10342 that later insns are available for delay slot filling. */
10344 macro_build (NULL, "break", BRK_FMT, 7);
10345 if (mips_opts.micromips)
10346 micromips_add_label ();
10348 macro_build (NULL, s2, MFHL_FMT, op[0]);
10360 /* Load the address of a symbol into a register. If breg is not
10361 zero, we then add a base register to it. */
10364 if (dbl && GPR_SIZE == 32)
10365 as_warn (_("dla used to load 32-bit register; recommend using la "
10368 if (!dbl && HAVE_64BIT_OBJECTS)
10369 as_warn (_("la used to load 64-bit address; recommend using dla "
10372 if (small_offset_p (0, align, 16))
10374 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10375 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10379 if (mips_opts.at && (op[0] == breg))
10387 if (offset_expr.X_op != O_symbol
10388 && offset_expr.X_op != O_constant)
10390 as_bad (_("expression too complex"));
10391 offset_expr.X_op = O_constant;
10394 if (offset_expr.X_op == O_constant)
10395 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10396 else if (mips_pic == NO_PIC)
10398 /* If this is a reference to a GP relative symbol, we want
10399 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10401 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10402 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10403 If we have a constant, we need two instructions anyhow,
10404 so we may as well always use the latter form.
10406 With 64bit address space and a usable $at we want
10407 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10408 lui $at,<sym> (BFD_RELOC_HI16_S)
10409 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10410 daddiu $at,<sym> (BFD_RELOC_LO16)
10412 daddu $tempreg,$tempreg,$at
10414 If $at is already in use, we use a path which is suboptimal
10415 on superscalar processors.
10416 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10417 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10419 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10421 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10423 For GP relative symbols in 64bit address space we can use
10424 the same sequence as in 32bit address space. */
10425 if (HAVE_64BIT_SYMBOLS)
10427 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10428 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10430 relax_start (offset_expr.X_add_symbol);
10431 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10432 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10436 if (used_at == 0 && mips_opts.at)
10438 macro_build (&offset_expr, "lui", LUI_FMT,
10439 tempreg, BFD_RELOC_MIPS_HIGHEST);
10440 macro_build (&offset_expr, "lui", LUI_FMT,
10441 AT, BFD_RELOC_HI16_S);
10442 macro_build (&offset_expr, "daddiu", "t,r,j",
10443 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10444 macro_build (&offset_expr, "daddiu", "t,r,j",
10445 AT, AT, BFD_RELOC_LO16);
10446 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10447 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10452 macro_build (&offset_expr, "lui", LUI_FMT,
10453 tempreg, BFD_RELOC_MIPS_HIGHEST);
10454 macro_build (&offset_expr, "daddiu", "t,r,j",
10455 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10456 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10457 macro_build (&offset_expr, "daddiu", "t,r,j",
10458 tempreg, tempreg, BFD_RELOC_HI16_S);
10459 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10460 macro_build (&offset_expr, "daddiu", "t,r,j",
10461 tempreg, tempreg, BFD_RELOC_LO16);
10464 if (mips_relax.sequence)
10469 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10470 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10472 relax_start (offset_expr.X_add_symbol);
10473 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10474 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10477 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10478 as_bad (_("offset too large"));
10479 macro_build_lui (&offset_expr, tempreg);
10480 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10481 tempreg, tempreg, BFD_RELOC_LO16);
10482 if (mips_relax.sequence)
10486 else if (!mips_big_got && !HAVE_NEWABI)
10488 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10490 /* If this is a reference to an external symbol, and there
10491 is no constant, we want
10492 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10493 or for lca or if tempreg is PIC_CALL_REG
10494 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10495 For a local symbol, we want
10496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10498 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10500 If we have a small constant, and this is a reference to
10501 an external symbol, we want
10502 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10504 addiu $tempreg,$tempreg,<constant>
10505 For a local symbol, we want the same instruction
10506 sequence, but we output a BFD_RELOC_LO16 reloc on the
10509 If we have a large constant, and this is a reference to
10510 an external symbol, we want
10511 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10512 lui $at,<hiconstant>
10513 addiu $at,$at,<loconstant>
10514 addu $tempreg,$tempreg,$at
10515 For a local symbol, we want the same instruction
10516 sequence, but we output a BFD_RELOC_LO16 reloc on the
10520 if (offset_expr.X_add_number == 0)
10522 if (mips_pic == SVR4_PIC
10524 && (call || tempreg == PIC_CALL_REG))
10525 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10527 relax_start (offset_expr.X_add_symbol);
10528 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10529 lw_reloc_type, mips_gp_register);
10532 /* We're going to put in an addu instruction using
10533 tempreg, so we may as well insert the nop right
10538 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10539 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10541 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10542 tempreg, tempreg, BFD_RELOC_LO16);
10544 /* FIXME: If breg == 0, and the next instruction uses
10545 $tempreg, then if this variant case is used an extra
10546 nop will be generated. */
10548 else if (offset_expr.X_add_number >= -0x8000
10549 && offset_expr.X_add_number < 0x8000)
10551 load_got_offset (tempreg, &offset_expr);
10553 add_got_offset (tempreg, &offset_expr);
10557 expr1.X_add_number = offset_expr.X_add_number;
10558 offset_expr.X_add_number =
10559 SEXT_16BIT (offset_expr.X_add_number);
10560 load_got_offset (tempreg, &offset_expr);
10561 offset_expr.X_add_number = expr1.X_add_number;
10562 /* If we are going to add in a base register, and the
10563 target register and the base register are the same,
10564 then we are using AT as a temporary register. Since
10565 we want to load the constant into AT, we add our
10566 current AT (from the global offset table) and the
10567 register into the register now, and pretend we were
10568 not using a base register. */
10572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10577 add_got_offset_hilo (tempreg, &offset_expr, AT);
10581 else if (!mips_big_got && HAVE_NEWABI)
10583 int add_breg_early = 0;
10585 /* If this is a reference to an external, and there is no
10586 constant, or local symbol (*), with or without a
10588 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10589 or for lca or if tempreg is PIC_CALL_REG
10590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10592 If we have a small constant, and this is a reference to
10593 an external symbol, we want
10594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10595 addiu $tempreg,$tempreg,<constant>
10597 If we have a large constant, and this is a reference to
10598 an external symbol, we want
10599 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10600 lui $at,<hiconstant>
10601 addiu $at,$at,<loconstant>
10602 addu $tempreg,$tempreg,$at
10604 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10605 local symbols, even though it introduces an additional
10608 if (offset_expr.X_add_number)
10610 expr1.X_add_number = offset_expr.X_add_number;
10611 offset_expr.X_add_number = 0;
10613 relax_start (offset_expr.X_add_symbol);
10614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10615 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10617 if (expr1.X_add_number >= -0x8000
10618 && expr1.X_add_number < 0x8000)
10620 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10621 tempreg, tempreg, BFD_RELOC_LO16);
10623 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10627 /* If we are going to add in a base register, and the
10628 target register and the base register are the same,
10629 then we are using AT as a temporary register. Since
10630 we want to load the constant into AT, we add our
10631 current AT (from the global offset table) and the
10632 register into the register now, and pretend we were
10633 not using a base register. */
10638 gas_assert (tempreg == AT);
10639 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10642 add_breg_early = 1;
10645 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10652 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10655 offset_expr.X_add_number = expr1.X_add_number;
10657 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10658 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10659 if (add_breg_early)
10661 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10662 op[0], tempreg, breg);
10668 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10670 relax_start (offset_expr.X_add_symbol);
10671 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10672 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10674 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10675 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10680 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10681 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10684 else if (mips_big_got && !HAVE_NEWABI)
10687 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10688 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10689 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10691 /* This is the large GOT case. If this is a reference to an
10692 external symbol, and there is no constant, we want
10693 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10694 addu $tempreg,$tempreg,$gp
10695 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10696 or for lca or if tempreg is PIC_CALL_REG
10697 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10698 addu $tempreg,$tempreg,$gp
10699 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10700 For a local symbol, we want
10701 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10703 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10705 If we have a small constant, and this is a reference to
10706 an external symbol, we want
10707 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10708 addu $tempreg,$tempreg,$gp
10709 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10711 addiu $tempreg,$tempreg,<constant>
10712 For a local symbol, we want
10713 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10715 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10717 If we have a large constant, and this is a reference to
10718 an external symbol, we want
10719 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10720 addu $tempreg,$tempreg,$gp
10721 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10722 lui $at,<hiconstant>
10723 addiu $at,$at,<loconstant>
10724 addu $tempreg,$tempreg,$at
10725 For a local symbol, we want
10726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10727 lui $at,<hiconstant>
10728 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10729 addu $tempreg,$tempreg,$at
10732 expr1.X_add_number = offset_expr.X_add_number;
10733 offset_expr.X_add_number = 0;
10734 relax_start (offset_expr.X_add_symbol);
10735 gpdelay = reg_needs_delay (mips_gp_register);
10736 if (expr1.X_add_number == 0 && breg == 0
10737 && (call || tempreg == PIC_CALL_REG))
10739 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10740 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10742 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10743 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10744 tempreg, tempreg, mips_gp_register);
10745 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10746 tempreg, lw_reloc_type, tempreg);
10747 if (expr1.X_add_number == 0)
10751 /* We're going to put in an addu instruction using
10752 tempreg, so we may as well insert the nop right
10757 else if (expr1.X_add_number >= -0x8000
10758 && expr1.X_add_number < 0x8000)
10761 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10762 tempreg, tempreg, BFD_RELOC_LO16);
10768 /* If we are going to add in a base register, and the
10769 target register and the base register are the same,
10770 then we are using AT as a temporary register. Since
10771 we want to load the constant into AT, we add our
10772 current AT (from the global offset table) and the
10773 register into the register now, and pretend we were
10774 not using a base register. */
10779 gas_assert (tempreg == AT);
10781 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10786 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10787 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10791 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10796 /* This is needed because this instruction uses $gp, but
10797 the first instruction on the main stream does not. */
10798 macro_build (NULL, "nop", "");
10801 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10802 local_reloc_type, mips_gp_register);
10803 if (expr1.X_add_number >= -0x8000
10804 && expr1.X_add_number < 0x8000)
10807 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10808 tempreg, tempreg, BFD_RELOC_LO16);
10809 /* FIXME: If add_number is 0, and there was no base
10810 register, the external symbol case ended with a load,
10811 so if the symbol turns out to not be external, and
10812 the next instruction uses tempreg, an unnecessary nop
10813 will be inserted. */
10819 /* We must add in the base register now, as in the
10820 external symbol case. */
10821 gas_assert (tempreg == AT);
10823 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10826 /* We set breg to 0 because we have arranged to add
10827 it in in both cases. */
10831 macro_build_lui (&expr1, AT);
10832 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10833 AT, AT, BFD_RELOC_LO16);
10834 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10835 tempreg, tempreg, AT);
10840 else if (mips_big_got && HAVE_NEWABI)
10842 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10843 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10844 int add_breg_early = 0;
10846 /* This is the large GOT case. If this is a reference to an
10847 external symbol, and there is no constant, we want
10848 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10849 add $tempreg,$tempreg,$gp
10850 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10851 or for lca or if tempreg is PIC_CALL_REG
10852 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10853 add $tempreg,$tempreg,$gp
10854 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10856 If we have a small constant, and this is a reference to
10857 an external symbol, we want
10858 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10859 add $tempreg,$tempreg,$gp
10860 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10861 addi $tempreg,$tempreg,<constant>
10863 If we have a large constant, and this is a reference to
10864 an external symbol, we want
10865 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10866 addu $tempreg,$tempreg,$gp
10867 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10868 lui $at,<hiconstant>
10869 addi $at,$at,<loconstant>
10870 add $tempreg,$tempreg,$at
10872 If we have NewABI, and we know it's a local symbol, we want
10873 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10874 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10875 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10877 relax_start (offset_expr.X_add_symbol);
10879 expr1.X_add_number = offset_expr.X_add_number;
10880 offset_expr.X_add_number = 0;
10882 if (expr1.X_add_number == 0 && breg == 0
10883 && (call || tempreg == PIC_CALL_REG))
10885 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10886 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10888 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10889 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10890 tempreg, tempreg, mips_gp_register);
10891 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10892 tempreg, lw_reloc_type, tempreg);
10894 if (expr1.X_add_number == 0)
10896 else if (expr1.X_add_number >= -0x8000
10897 && expr1.X_add_number < 0x8000)
10899 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10900 tempreg, tempreg, BFD_RELOC_LO16);
10902 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10906 /* If we are going to add in a base register, and the
10907 target register and the base register are the same,
10908 then we are using AT as a temporary register. Since
10909 we want to load the constant into AT, we add our
10910 current AT (from the global offset table) and the
10911 register into the register now, and pretend we were
10912 not using a base register. */
10917 gas_assert (tempreg == AT);
10918 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10921 add_breg_early = 1;
10924 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10925 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10930 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10933 offset_expr.X_add_number = expr1.X_add_number;
10934 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10935 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10936 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10937 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10938 if (add_breg_early)
10940 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10941 op[0], tempreg, breg);
10951 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10955 gas_assert (!mips_opts.micromips);
10956 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10960 gas_assert (!mips_opts.micromips);
10961 macro_build (NULL, "c2", "C", 0x02);
10965 gas_assert (!mips_opts.micromips);
10966 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10970 gas_assert (!mips_opts.micromips);
10971 macro_build (NULL, "c2", "C", 3);
10975 gas_assert (!mips_opts.micromips);
10976 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10980 /* The j instruction may not be used in PIC code, since it
10981 requires an absolute address. We convert it to a b
10983 if (mips_pic == NO_PIC)
10984 macro_build (&offset_expr, "j", "a");
10986 macro_build (&offset_expr, "b", "p");
10989 /* The jal instructions must be handled as macros because when
10990 generating PIC code they expand to multi-instruction
10991 sequences. Normally they are simple instructions. */
10995 /* Fall through. */
10997 gas_assert (mips_opts.micromips);
10998 if (mips_opts.insn32)
11000 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11008 /* Fall through. */
11011 if (mips_pic == NO_PIC)
11013 s = jals ? "jalrs" : "jalr";
11014 if (mips_opts.micromips
11015 && !mips_opts.insn32
11017 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11018 macro_build (NULL, s, "mj", op[1]);
11020 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11024 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11025 && mips_cprestore_offset >= 0);
11027 if (op[1] != PIC_CALL_REG)
11028 as_warn (_("MIPS PIC call to register other than $25"));
11030 s = ((mips_opts.micromips
11031 && !mips_opts.insn32
11032 && (!mips_opts.noreorder || cprestore))
11033 ? "jalrs" : "jalr");
11034 if (mips_opts.micromips
11035 && !mips_opts.insn32
11037 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11038 macro_build (NULL, s, "mj", op[1]);
11040 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11041 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11043 if (mips_cprestore_offset < 0)
11044 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11047 if (!mips_frame_reg_valid)
11049 as_warn (_("no .frame pseudo-op used in PIC code"));
11050 /* Quiet this warning. */
11051 mips_frame_reg_valid = 1;
11053 if (!mips_cprestore_valid)
11055 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11056 /* Quiet this warning. */
11057 mips_cprestore_valid = 1;
11059 if (mips_opts.noreorder)
11060 macro_build (NULL, "nop", "");
11061 expr1.X_add_number = mips_cprestore_offset;
11062 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11065 HAVE_64BIT_ADDRESSES);
11073 gas_assert (mips_opts.micromips);
11074 if (mips_opts.insn32)
11076 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11080 /* Fall through. */
11082 if (mips_pic == NO_PIC)
11083 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11084 else if (mips_pic == SVR4_PIC)
11086 /* If this is a reference to an external symbol, and we are
11087 using a small GOT, we want
11088 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11092 lw $gp,cprestore($sp)
11093 The cprestore value is set using the .cprestore
11094 pseudo-op. If we are using a big GOT, we want
11095 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11097 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11101 lw $gp,cprestore($sp)
11102 If the symbol is not external, we want
11103 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11105 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11108 lw $gp,cprestore($sp)
11110 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11111 sequences above, minus nops, unless the symbol is local,
11112 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11118 relax_start (offset_expr.X_add_symbol);
11119 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11120 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11123 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11124 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11130 relax_start (offset_expr.X_add_symbol);
11131 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11132 BFD_RELOC_MIPS_CALL_HI16);
11133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11134 PIC_CALL_REG, mips_gp_register);
11135 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11136 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11139 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11140 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11142 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11143 PIC_CALL_REG, PIC_CALL_REG,
11144 BFD_RELOC_MIPS_GOT_OFST);
11148 macro_build_jalr (&offset_expr, 0);
11152 relax_start (offset_expr.X_add_symbol);
11155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11156 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11165 gpdelay = reg_needs_delay (mips_gp_register);
11166 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11167 BFD_RELOC_MIPS_CALL_HI16);
11168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11169 PIC_CALL_REG, mips_gp_register);
11170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11171 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11176 macro_build (NULL, "nop", "");
11178 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11179 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11182 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11183 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11185 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11187 if (mips_cprestore_offset < 0)
11188 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11191 if (!mips_frame_reg_valid)
11193 as_warn (_("no .frame pseudo-op used in PIC code"));
11194 /* Quiet this warning. */
11195 mips_frame_reg_valid = 1;
11197 if (!mips_cprestore_valid)
11199 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11200 /* Quiet this warning. */
11201 mips_cprestore_valid = 1;
11203 if (mips_opts.noreorder)
11204 macro_build (NULL, "nop", "");
11205 expr1.X_add_number = mips_cprestore_offset;
11206 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11209 HAVE_64BIT_ADDRESSES);
11213 else if (mips_pic == VXWORKS_PIC)
11214 as_bad (_("non-PIC jump used in PIC library"));
11321 gas_assert (!mips_opts.micromips);
11324 /* Itbl support may require additional care here. */
11330 /* Itbl support may require additional care here. */
11336 offbits = (mips_opts.micromips ? 12
11337 : ISA_IS_R6 (mips_opts.isa) ? 11
11339 /* Itbl support may require additional care here. */
11343 gas_assert (!mips_opts.micromips);
11346 /* Itbl support may require additional care here. */
11352 offbits = (mips_opts.micromips ? 12 : 16);
11357 offbits = (mips_opts.micromips ? 12 : 16);
11362 /* Itbl support may require additional care here. */
11368 offbits = (mips_opts.micromips ? 12
11369 : ISA_IS_R6 (mips_opts.isa) ? 11
11371 /* Itbl support may require additional care here. */
11377 /* Itbl support may require additional care here. */
11383 /* Itbl support may require additional care here. */
11389 offbits = (mips_opts.micromips ? 12 : 16);
11394 offbits = (mips_opts.micromips ? 12 : 16);
11399 offbits = (mips_opts.micromips ? 12
11400 : ISA_IS_R6 (mips_opts.isa) ? 9
11406 offbits = (mips_opts.micromips ? 12
11407 : ISA_IS_R6 (mips_opts.isa) ? 9
11413 offbits = (mips_opts.micromips ? 12 : 16);
11416 gas_assert (mips_opts.micromips);
11423 gas_assert (mips_opts.micromips);
11430 gas_assert (mips_opts.micromips);
11436 gas_assert (mips_opts.micromips);
11443 /* We don't want to use $0 as tempreg. */
11444 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11447 tempreg = op[0] + lp;
11463 gas_assert (!mips_opts.micromips);
11466 /* Itbl support may require additional care here. */
11472 /* Itbl support may require additional care here. */
11478 offbits = (mips_opts.micromips ? 12
11479 : ISA_IS_R6 (mips_opts.isa) ? 11
11481 /* Itbl support may require additional care here. */
11485 gas_assert (!mips_opts.micromips);
11488 /* Itbl support may require additional care here. */
11494 offbits = (mips_opts.micromips ? 12 : 16);
11499 offbits = (mips_opts.micromips ? 12 : 16);
11504 offbits = (mips_opts.micromips ? 12
11505 : ISA_IS_R6 (mips_opts.isa) ? 9
11511 offbits = (mips_opts.micromips ? 12
11512 : ISA_IS_R6 (mips_opts.isa) ? 9
11517 fmt = (mips_opts.micromips ? "k,~(b)"
11518 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11520 offbits = (mips_opts.micromips ? 12
11521 : ISA_IS_R6 (mips_opts.isa) ? 9
11531 fmt = (mips_opts.micromips ? "k,~(b)"
11532 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11534 offbits = (mips_opts.micromips ? 12
11535 : ISA_IS_R6 (mips_opts.isa) ? 9
11547 /* Itbl support may require additional care here. */
11552 offbits = (mips_opts.micromips ? 12
11553 : ISA_IS_R6 (mips_opts.isa) ? 11
11555 /* Itbl support may require additional care here. */
11561 /* Itbl support may require additional care here. */
11565 gas_assert (!mips_opts.micromips);
11568 /* Itbl support may require additional care here. */
11574 offbits = (mips_opts.micromips ? 12 : 16);
11579 offbits = (mips_opts.micromips ? 12 : 16);
11582 gas_assert (mips_opts.micromips);
11588 gas_assert (mips_opts.micromips);
11594 gas_assert (mips_opts.micromips);
11600 gas_assert (mips_opts.micromips);
11609 if (small_offset_p (0, align, 16))
11611 /* The first case exists for M_LD_AB and M_SD_AB, which are
11612 macros for o32 but which should act like normal instructions
11615 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11616 offset_reloc[1], offset_reloc[2], breg);
11617 else if (small_offset_p (0, align, offbits))
11620 macro_build (NULL, s, fmt, op[0], breg);
11622 macro_build (NULL, s, fmt, op[0],
11623 (int) offset_expr.X_add_number, breg);
11629 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11630 tempreg, breg, -1, offset_reloc[0],
11631 offset_reloc[1], offset_reloc[2]);
11633 macro_build (NULL, s, fmt, op[0], tempreg);
11635 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11643 if (offset_expr.X_op != O_constant
11644 && offset_expr.X_op != O_symbol)
11646 as_bad (_("expression too complex"));
11647 offset_expr.X_op = O_constant;
11650 if (HAVE_32BIT_ADDRESSES
11651 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11655 sprintf_vma (value, offset_expr.X_add_number);
11656 as_bad (_("number (0x%s) larger than 32 bits"), value);
11659 /* A constant expression in PIC code can be handled just as it
11660 is in non PIC code. */
11661 if (offset_expr.X_op == O_constant)
11663 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11664 offbits == 0 ? 16 : offbits);
11665 offset_expr.X_add_number -= expr1.X_add_number;
11667 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11669 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11670 tempreg, tempreg, breg);
11673 if (offset_expr.X_add_number != 0)
11674 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11675 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11676 macro_build (NULL, s, fmt, op[0], tempreg);
11678 else if (offbits == 16)
11679 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11681 macro_build (NULL, s, fmt, op[0],
11682 (int) offset_expr.X_add_number, tempreg);
11684 else if (offbits != 16)
11686 /* The offset field is too narrow to be used for a low-part
11687 relocation, so load the whole address into the auxillary
11689 load_address (tempreg, &offset_expr, &used_at);
11691 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11692 tempreg, tempreg, breg);
11694 macro_build (NULL, s, fmt, op[0], tempreg);
11696 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11698 else if (mips_pic == NO_PIC)
11700 /* If this is a reference to a GP relative symbol, and there
11701 is no base register, we want
11702 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11703 Otherwise, if there is no base register, we want
11704 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11705 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11706 If we have a constant, we need two instructions anyhow,
11707 so we always use the latter form.
11709 If we have a base register, and this is a reference to a
11710 GP relative symbol, we want
11711 addu $tempreg,$breg,$gp
11712 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11714 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11715 addu $tempreg,$tempreg,$breg
11716 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11717 With a constant we always use the latter case.
11719 With 64bit address space and no base register and $at usable,
11721 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11722 lui $at,<sym> (BFD_RELOC_HI16_S)
11723 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11726 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11727 If we have a base register, we want
11728 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11729 lui $at,<sym> (BFD_RELOC_HI16_S)
11730 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11734 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11736 Without $at we can't generate the optimal path for superscalar
11737 processors here since this would require two temporary registers.
11738 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11739 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11741 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11743 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11744 If we have a base register, we want
11745 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11746 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11748 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11750 daddu $tempreg,$tempreg,$breg
11751 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11753 For GP relative symbols in 64bit address space we can use
11754 the same sequence as in 32bit address space. */
11755 if (HAVE_64BIT_SYMBOLS)
11757 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11758 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11760 relax_start (offset_expr.X_add_symbol);
11763 macro_build (&offset_expr, s, fmt, op[0],
11764 BFD_RELOC_GPREL16, mips_gp_register);
11768 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11769 tempreg, breg, mips_gp_register);
11770 macro_build (&offset_expr, s, fmt, op[0],
11771 BFD_RELOC_GPREL16, tempreg);
11776 if (used_at == 0 && mips_opts.at)
11778 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11779 BFD_RELOC_MIPS_HIGHEST);
11780 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11782 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11783 tempreg, BFD_RELOC_MIPS_HIGHER);
11785 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11786 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11787 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11788 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11794 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11795 BFD_RELOC_MIPS_HIGHEST);
11796 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11797 tempreg, BFD_RELOC_MIPS_HIGHER);
11798 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11799 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11800 tempreg, BFD_RELOC_HI16_S);
11801 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11803 macro_build (NULL, "daddu", "d,v,t",
11804 tempreg, tempreg, breg);
11805 macro_build (&offset_expr, s, fmt, op[0],
11806 BFD_RELOC_LO16, tempreg);
11809 if (mips_relax.sequence)
11816 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11817 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11819 relax_start (offset_expr.X_add_symbol);
11820 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11824 macro_build_lui (&offset_expr, tempreg);
11825 macro_build (&offset_expr, s, fmt, op[0],
11826 BFD_RELOC_LO16, tempreg);
11827 if (mips_relax.sequence)
11832 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11833 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11835 relax_start (offset_expr.X_add_symbol);
11836 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11837 tempreg, breg, mips_gp_register);
11838 macro_build (&offset_expr, s, fmt, op[0],
11839 BFD_RELOC_GPREL16, tempreg);
11842 macro_build_lui (&offset_expr, tempreg);
11843 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11844 tempreg, tempreg, breg);
11845 macro_build (&offset_expr, s, fmt, op[0],
11846 BFD_RELOC_LO16, tempreg);
11847 if (mips_relax.sequence)
11851 else if (!mips_big_got)
11853 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11855 /* If this is a reference to an external symbol, we want
11856 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11858 <op> op[0],0($tempreg)
11860 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11862 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11863 <op> op[0],0($tempreg)
11865 For NewABI, we want
11866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11867 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11869 If there is a base register, we add it to $tempreg before
11870 the <op>. If there is a constant, we stick it in the
11871 <op> instruction. We don't handle constants larger than
11872 16 bits, because we have no way to load the upper 16 bits
11873 (actually, we could handle them for the subset of cases
11874 in which we are not using $at). */
11875 gas_assert (offset_expr.X_op == O_symbol);
11878 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11879 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11881 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11882 tempreg, tempreg, breg);
11883 macro_build (&offset_expr, s, fmt, op[0],
11884 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11887 expr1.X_add_number = offset_expr.X_add_number;
11888 offset_expr.X_add_number = 0;
11889 if (expr1.X_add_number < -0x8000
11890 || expr1.X_add_number >= 0x8000)
11891 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11892 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11893 lw_reloc_type, mips_gp_register);
11895 relax_start (offset_expr.X_add_symbol);
11897 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11898 tempreg, BFD_RELOC_LO16);
11901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11902 tempreg, tempreg, breg);
11903 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11905 else if (mips_big_got && !HAVE_NEWABI)
11909 /* If this is a reference to an external symbol, we want
11910 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11911 addu $tempreg,$tempreg,$gp
11912 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11913 <op> op[0],0($tempreg)
11915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11917 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11918 <op> op[0],0($tempreg)
11919 If there is a base register, we add it to $tempreg before
11920 the <op>. If there is a constant, we stick it in the
11921 <op> instruction. We don't handle constants larger than
11922 16 bits, because we have no way to load the upper 16 bits
11923 (actually, we could handle them for the subset of cases
11924 in which we are not using $at). */
11925 gas_assert (offset_expr.X_op == O_symbol);
11926 expr1.X_add_number = offset_expr.X_add_number;
11927 offset_expr.X_add_number = 0;
11928 if (expr1.X_add_number < -0x8000
11929 || expr1.X_add_number >= 0x8000)
11930 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11931 gpdelay = reg_needs_delay (mips_gp_register);
11932 relax_start (offset_expr.X_add_symbol);
11933 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11934 BFD_RELOC_MIPS_GOT_HI16);
11935 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11937 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11938 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11941 macro_build (NULL, "nop", "");
11942 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11943 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11945 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11946 tempreg, BFD_RELOC_LO16);
11950 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11951 tempreg, tempreg, breg);
11952 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11954 else if (mips_big_got && HAVE_NEWABI)
11956 /* If this is a reference to an external symbol, we want
11957 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11958 add $tempreg,$tempreg,$gp
11959 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11960 <op> op[0],<ofst>($tempreg)
11961 Otherwise, for local symbols, we want:
11962 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11963 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11964 gas_assert (offset_expr.X_op == O_symbol);
11965 expr1.X_add_number = offset_expr.X_add_number;
11966 offset_expr.X_add_number = 0;
11967 if (expr1.X_add_number < -0x8000
11968 || expr1.X_add_number >= 0x8000)
11969 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11970 relax_start (offset_expr.X_add_symbol);
11971 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11972 BFD_RELOC_MIPS_GOT_HI16);
11973 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11975 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11976 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11979 tempreg, tempreg, breg);
11980 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11983 offset_expr.X_add_number = expr1.X_add_number;
11984 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11985 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11987 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11988 tempreg, tempreg, breg);
11989 macro_build (&offset_expr, s, fmt, op[0],
11990 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11999 gas_assert (mips_opts.micromips);
12000 gas_assert (mips_opts.insn32);
12001 start_noreorder ();
12002 macro_build (NULL, "jr", "s", RA);
12003 expr1.X_add_number = op[0] << 2;
12004 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12009 gas_assert (mips_opts.micromips);
12010 gas_assert (mips_opts.insn32);
12011 macro_build (NULL, "jr", "s", op[0]);
12012 if (mips_opts.noreorder)
12013 macro_build (NULL, "nop", "");
12018 load_register (op[0], &imm_expr, 0);
12022 load_register (op[0], &imm_expr, 1);
12026 if (imm_expr.X_op == O_constant)
12029 load_register (AT, &imm_expr, 0);
12030 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12035 gas_assert (imm_expr.X_op == O_absent
12036 && offset_expr.X_op == O_symbol
12037 && strcmp (segment_name (S_GET_SEGMENT
12038 (offset_expr.X_add_symbol)),
12040 && offset_expr.X_add_number == 0);
12041 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12042 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12047 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12048 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12049 order 32 bits of the value and the low order 32 bits are either
12050 zero or in OFFSET_EXPR. */
12051 if (imm_expr.X_op == O_constant)
12053 if (GPR_SIZE == 64)
12054 load_register (op[0], &imm_expr, 1);
12059 if (target_big_endian)
12071 load_register (hreg, &imm_expr, 0);
12074 if (offset_expr.X_op == O_absent)
12075 move_register (lreg, 0);
12078 gas_assert (offset_expr.X_op == O_constant);
12079 load_register (lreg, &offset_expr, 0);
12085 gas_assert (imm_expr.X_op == O_absent);
12087 /* We know that sym is in the .rdata section. First we get the
12088 upper 16 bits of the address. */
12089 if (mips_pic == NO_PIC)
12091 macro_build_lui (&offset_expr, AT);
12096 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12097 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12101 /* Now we load the register(s). */
12102 if (GPR_SIZE == 64)
12105 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12106 BFD_RELOC_LO16, AT);
12111 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12112 BFD_RELOC_LO16, AT);
12115 /* FIXME: How in the world do we deal with the possible
12117 offset_expr.X_add_number += 4;
12118 macro_build (&offset_expr, "lw", "t,o(b)",
12119 op[0] + 1, BFD_RELOC_LO16, AT);
12125 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12126 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12127 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12128 the value and the low order 32 bits are either zero or in
12130 if (imm_expr.X_op == O_constant)
12133 load_register (AT, &imm_expr, FPR_SIZE == 64);
12134 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12135 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12138 if (ISA_HAS_MXHC1 (mips_opts.isa))
12139 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12140 else if (FPR_SIZE != 32)
12141 as_bad (_("Unable to generate `%s' compliant code "
12143 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12145 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12146 if (offset_expr.X_op == O_absent)
12147 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12150 gas_assert (offset_expr.X_op == O_constant);
12151 load_register (AT, &offset_expr, 0);
12152 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12158 gas_assert (imm_expr.X_op == O_absent
12159 && offset_expr.X_op == O_symbol
12160 && offset_expr.X_add_number == 0);
12161 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12162 if (strcmp (s, ".lit8") == 0)
12164 op[2] = mips_gp_register;
12165 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12166 offset_reloc[1] = BFD_RELOC_UNUSED;
12167 offset_reloc[2] = BFD_RELOC_UNUSED;
12171 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12173 if (mips_pic != NO_PIC)
12174 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12175 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12178 /* FIXME: This won't work for a 64 bit address. */
12179 macro_build_lui (&offset_expr, AT);
12183 offset_reloc[0] = BFD_RELOC_LO16;
12184 offset_reloc[1] = BFD_RELOC_UNUSED;
12185 offset_reloc[2] = BFD_RELOC_UNUSED;
12192 * The MIPS assembler seems to check for X_add_number not
12193 * being double aligned and generating:
12194 * lui at,%hi(foo+1)
12196 * addiu at,at,%lo(foo+1)
12199 * But, the resulting address is the same after relocation so why
12200 * generate the extra instruction?
12202 /* Itbl support may require additional care here. */
12205 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12214 gas_assert (!mips_opts.micromips);
12215 /* Itbl support may require additional care here. */
12218 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12238 if (GPR_SIZE == 64)
12248 if (GPR_SIZE == 64)
12256 /* Even on a big endian machine $fn comes before $fn+1. We have
12257 to adjust when loading from memory. We set coproc if we must
12258 load $fn+1 first. */
12259 /* Itbl support may require additional care here. */
12260 if (!target_big_endian)
12264 if (small_offset_p (0, align, 16))
12267 if (!small_offset_p (4, align, 16))
12269 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12270 -1, offset_reloc[0], offset_reloc[1],
12272 expr1.X_add_number = 0;
12276 offset_reloc[0] = BFD_RELOC_LO16;
12277 offset_reloc[1] = BFD_RELOC_UNUSED;
12278 offset_reloc[2] = BFD_RELOC_UNUSED;
12280 if (strcmp (s, "lw") == 0 && op[0] == breg)
12282 ep->X_add_number += 4;
12283 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12284 offset_reloc[1], offset_reloc[2], breg);
12285 ep->X_add_number -= 4;
12286 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12287 offset_reloc[1], offset_reloc[2], breg);
12291 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12292 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12294 ep->X_add_number += 4;
12295 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12296 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12302 if (offset_expr.X_op != O_symbol
12303 && offset_expr.X_op != O_constant)
12305 as_bad (_("expression too complex"));
12306 offset_expr.X_op = O_constant;
12309 if (HAVE_32BIT_ADDRESSES
12310 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12314 sprintf_vma (value, offset_expr.X_add_number);
12315 as_bad (_("number (0x%s) larger than 32 bits"), value);
12318 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12320 /* If this is a reference to a GP relative symbol, we want
12321 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12322 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12323 If we have a base register, we use this
12325 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12326 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12327 If this is not a GP relative symbol, we want
12328 lui $at,<sym> (BFD_RELOC_HI16_S)
12329 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12330 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12331 If there is a base register, we add it to $at after the
12332 lui instruction. If there is a constant, we always use
12334 if (offset_expr.X_op == O_symbol
12335 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12336 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12338 relax_start (offset_expr.X_add_symbol);
12341 tempreg = mips_gp_register;
12345 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12346 AT, breg, mips_gp_register);
12351 /* Itbl support may require additional care here. */
12352 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12353 BFD_RELOC_GPREL16, tempreg);
12354 offset_expr.X_add_number += 4;
12356 /* Set mips_optimize to 2 to avoid inserting an
12358 hold_mips_optimize = mips_optimize;
12360 /* Itbl support may require additional care here. */
12361 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12362 BFD_RELOC_GPREL16, tempreg);
12363 mips_optimize = hold_mips_optimize;
12367 offset_expr.X_add_number -= 4;
12370 if (offset_high_part (offset_expr.X_add_number, 16)
12371 != offset_high_part (offset_expr.X_add_number + 4, 16))
12373 load_address (AT, &offset_expr, &used_at);
12374 offset_expr.X_op = O_constant;
12375 offset_expr.X_add_number = 0;
12378 macro_build_lui (&offset_expr, AT);
12380 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12381 /* Itbl support may require additional care here. */
12382 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12383 BFD_RELOC_LO16, AT);
12384 /* FIXME: How do we handle overflow here? */
12385 offset_expr.X_add_number += 4;
12386 /* Itbl support may require additional care here. */
12387 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12388 BFD_RELOC_LO16, AT);
12389 if (mips_relax.sequence)
12392 else if (!mips_big_got)
12394 /* If this is a reference to an external symbol, we want
12395 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12398 <op> op[0]+1,4($at)
12400 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12402 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12403 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12404 If there is a base register we add it to $at before the
12405 lwc1 instructions. If there is a constant we include it
12406 in the lwc1 instructions. */
12408 expr1.X_add_number = offset_expr.X_add_number;
12409 if (expr1.X_add_number < -0x8000
12410 || expr1.X_add_number >= 0x8000 - 4)
12411 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12412 load_got_offset (AT, &offset_expr);
12415 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12417 /* Set mips_optimize to 2 to avoid inserting an undesired
12419 hold_mips_optimize = mips_optimize;
12422 /* Itbl support may require additional care here. */
12423 relax_start (offset_expr.X_add_symbol);
12424 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12425 BFD_RELOC_LO16, AT);
12426 expr1.X_add_number += 4;
12427 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12428 BFD_RELOC_LO16, AT);
12430 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12431 BFD_RELOC_LO16, AT);
12432 offset_expr.X_add_number += 4;
12433 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12434 BFD_RELOC_LO16, AT);
12437 mips_optimize = hold_mips_optimize;
12439 else if (mips_big_got)
12443 /* If this is a reference to an external symbol, we want
12444 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12446 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12449 <op> op[0]+1,4($at)
12451 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12453 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12454 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12455 If there is a base register we add it to $at before the
12456 lwc1 instructions. If there is a constant we include it
12457 in the lwc1 instructions. */
12459 expr1.X_add_number = offset_expr.X_add_number;
12460 offset_expr.X_add_number = 0;
12461 if (expr1.X_add_number < -0x8000
12462 || expr1.X_add_number >= 0x8000 - 4)
12463 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12464 gpdelay = reg_needs_delay (mips_gp_register);
12465 relax_start (offset_expr.X_add_symbol);
12466 macro_build (&offset_expr, "lui", LUI_FMT,
12467 AT, BFD_RELOC_MIPS_GOT_HI16);
12468 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12469 AT, AT, mips_gp_register);
12470 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12471 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12474 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12475 /* Itbl support may require additional care here. */
12476 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12477 BFD_RELOC_LO16, AT);
12478 expr1.X_add_number += 4;
12480 /* Set mips_optimize to 2 to avoid inserting an undesired
12482 hold_mips_optimize = mips_optimize;
12484 /* Itbl support may require additional care here. */
12485 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12486 BFD_RELOC_LO16, AT);
12487 mips_optimize = hold_mips_optimize;
12488 expr1.X_add_number -= 4;
12491 offset_expr.X_add_number = expr1.X_add_number;
12493 macro_build (NULL, "nop", "");
12494 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12495 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12499 /* Itbl support may require additional care here. */
12500 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12501 BFD_RELOC_LO16, AT);
12502 offset_expr.X_add_number += 4;
12504 /* Set mips_optimize to 2 to avoid inserting an undesired
12506 hold_mips_optimize = mips_optimize;
12508 /* Itbl support may require additional care here. */
12509 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12510 BFD_RELOC_LO16, AT);
12511 mips_optimize = hold_mips_optimize;
12525 gas_assert (!mips_opts.micromips);
12530 /* New code added to support COPZ instructions.
12531 This code builds table entries out of the macros in mip_opcodes.
12532 R4000 uses interlocks to handle coproc delays.
12533 Other chips (like the R3000) require nops to be inserted for delays.
12535 FIXME: Currently, we require that the user handle delays.
12536 In order to fill delay slots for non-interlocked chips,
12537 we must have a way to specify delays based on the coprocessor.
12538 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12539 What are the side-effects of the cop instruction?
12540 What cache support might we have and what are its effects?
12541 Both coprocessor & memory require delays. how long???
12542 What registers are read/set/modified?
12544 If an itbl is provided to interpret cop instructions,
12545 this knowledge can be encoded in the itbl spec. */
12559 gas_assert (!mips_opts.micromips);
12560 /* For now we just do C (same as Cz). The parameter will be
12561 stored in insn_opcode by mips_ip. */
12562 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12566 move_register (op[0], op[1]);
12570 gas_assert (mips_opts.micromips);
12571 gas_assert (mips_opts.insn32);
12572 move_register (micromips_to_32_reg_h_map1[op[0]],
12573 micromips_to_32_reg_m_map[op[1]]);
12574 move_register (micromips_to_32_reg_h_map2[op[0]],
12575 micromips_to_32_reg_n_map[op[2]]);
12581 if (mips_opts.arch == CPU_R5900)
12582 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12586 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12587 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12594 /* The MIPS assembler some times generates shifts and adds. I'm
12595 not trying to be that fancy. GCC should do this for us
12598 load_register (AT, &imm_expr, dbl);
12599 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12600 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12613 start_noreorder ();
12616 load_register (AT, &imm_expr, dbl);
12617 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12618 op[1], imm ? AT : op[2]);
12619 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12620 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12621 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12623 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12626 if (mips_opts.micromips)
12627 micromips_label_expr (&label_expr);
12629 label_expr.X_add_number = 8;
12630 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12631 macro_build (NULL, "nop", "");
12632 macro_build (NULL, "break", BRK_FMT, 6);
12633 if (mips_opts.micromips)
12634 micromips_add_label ();
12637 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12650 start_noreorder ();
12653 load_register (AT, &imm_expr, dbl);
12654 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12655 op[1], imm ? AT : op[2]);
12656 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12657 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12659 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12662 if (mips_opts.micromips)
12663 micromips_label_expr (&label_expr);
12665 label_expr.X_add_number = 8;
12666 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12667 macro_build (NULL, "nop", "");
12668 macro_build (NULL, "break", BRK_FMT, 6);
12669 if (mips_opts.micromips)
12670 micromips_add_label ();
12676 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12678 if (op[0] == op[1])
12685 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12686 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12690 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12691 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12692 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12693 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12697 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12699 if (op[0] == op[1])
12706 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12707 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12711 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12712 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12713 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12714 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12723 rot = imm_expr.X_add_number & 0x3f;
12724 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12726 rot = (64 - rot) & 0x3f;
12728 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12730 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12735 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12738 l = (rot < 0x20) ? "dsll" : "dsll32";
12739 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12742 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12743 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12744 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12752 rot = imm_expr.X_add_number & 0x1f;
12753 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12755 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12756 (32 - rot) & 0x1f);
12761 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12765 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12766 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12767 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12772 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12774 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12778 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12779 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12780 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12781 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12785 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12787 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12791 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12792 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12793 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12794 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12803 rot = imm_expr.X_add_number & 0x3f;
12804 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12807 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12809 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12814 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12817 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12818 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12821 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12822 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12823 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12831 rot = imm_expr.X_add_number & 0x1f;
12832 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12834 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12839 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12843 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12844 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12845 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12851 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12852 else if (op[2] == 0)
12853 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12856 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12857 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12862 if (imm_expr.X_add_number == 0)
12864 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12869 as_warn (_("instruction %s: result is always false"),
12870 ip->insn_mo->name);
12871 move_register (op[0], 0);
12874 if (CPU_HAS_SEQ (mips_opts.arch)
12875 && -512 <= imm_expr.X_add_number
12876 && imm_expr.X_add_number < 512)
12878 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12879 (int) imm_expr.X_add_number);
12882 if (imm_expr.X_add_number >= 0
12883 && imm_expr.X_add_number < 0x10000)
12884 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12885 else if (imm_expr.X_add_number > -0x8000
12886 && imm_expr.X_add_number < 0)
12888 imm_expr.X_add_number = -imm_expr.X_add_number;
12889 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
12890 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12892 else if (CPU_HAS_SEQ (mips_opts.arch))
12895 load_register (AT, &imm_expr, GPR_SIZE == 64);
12896 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12901 load_register (AT, &imm_expr, GPR_SIZE == 64);
12902 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12905 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12908 case M_SGE: /* X >= Y <==> not (X < Y) */
12914 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12915 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12918 case M_SGE_I: /* X >= I <==> not (X < I) */
12920 if (imm_expr.X_add_number >= -0x8000
12921 && imm_expr.X_add_number < 0x8000)
12922 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12923 op[0], op[1], BFD_RELOC_LO16);
12926 load_register (AT, &imm_expr, GPR_SIZE == 64);
12927 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12931 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12934 case M_SGT: /* X > Y <==> Y < X */
12940 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12943 case M_SGT_I: /* X > I <==> I < X */
12950 load_register (AT, &imm_expr, GPR_SIZE == 64);
12951 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12954 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12960 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12961 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12964 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12971 load_register (AT, &imm_expr, GPR_SIZE == 64);
12972 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12973 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12977 if (imm_expr.X_add_number >= -0x8000
12978 && imm_expr.X_add_number < 0x8000)
12980 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12985 load_register (AT, &imm_expr, GPR_SIZE == 64);
12986 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12990 if (imm_expr.X_add_number >= -0x8000
12991 && imm_expr.X_add_number < 0x8000)
12993 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12998 load_register (AT, &imm_expr, GPR_SIZE == 64);
12999 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13004 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13005 else if (op[2] == 0)
13006 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13009 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13010 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13015 if (imm_expr.X_add_number == 0)
13017 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13022 as_warn (_("instruction %s: result is always true"),
13023 ip->insn_mo->name);
13024 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13025 op[0], 0, BFD_RELOC_LO16);
13028 if (CPU_HAS_SEQ (mips_opts.arch)
13029 && -512 <= imm_expr.X_add_number
13030 && imm_expr.X_add_number < 512)
13032 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13033 (int) imm_expr.X_add_number);
13036 if (imm_expr.X_add_number >= 0
13037 && imm_expr.X_add_number < 0x10000)
13039 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13042 else if (imm_expr.X_add_number > -0x8000
13043 && imm_expr.X_add_number < 0)
13045 imm_expr.X_add_number = -imm_expr.X_add_number;
13046 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13047 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13049 else if (CPU_HAS_SEQ (mips_opts.arch))
13052 load_register (AT, &imm_expr, GPR_SIZE == 64);
13053 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13058 load_register (AT, &imm_expr, GPR_SIZE == 64);
13059 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13062 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13077 if (!mips_opts.micromips)
13079 if (imm_expr.X_add_number > -0x200
13080 && imm_expr.X_add_number <= 0x200)
13082 macro_build (NULL, s, "t,r,.", op[0], op[1],
13083 (int) -imm_expr.X_add_number);
13092 if (imm_expr.X_add_number > -0x8000
13093 && imm_expr.X_add_number <= 0x8000)
13095 imm_expr.X_add_number = -imm_expr.X_add_number;
13096 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13101 load_register (AT, &imm_expr, dbl);
13102 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13124 load_register (AT, &imm_expr, GPR_SIZE == 64);
13125 macro_build (NULL, s, "s,t", op[0], AT);
13130 gas_assert (!mips_opts.micromips);
13131 gas_assert (mips_opts.isa == ISA_MIPS1);
13135 * Is the double cfc1 instruction a bug in the mips assembler;
13136 * or is there a reason for it?
13138 start_noreorder ();
13139 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13140 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13141 macro_build (NULL, "nop", "");
13142 expr1.X_add_number = 3;
13143 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13144 expr1.X_add_number = 2;
13145 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13146 macro_build (NULL, "ctc1", "t,G", AT, RA);
13147 macro_build (NULL, "nop", "");
13148 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13150 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13151 macro_build (NULL, "nop", "");
13168 offbits = (mips_opts.micromips ? 12 : 16);
13174 offbits = (mips_opts.micromips ? 12 : 16);
13186 offbits = (mips_opts.micromips ? 12 : 16);
13193 offbits = (mips_opts.micromips ? 12 : 16);
13199 large_offset = !small_offset_p (off, align, offbits);
13201 expr1.X_add_number = 0;
13206 if (small_offset_p (0, align, 16))
13207 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13208 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13211 load_address (tempreg, ep, &used_at);
13213 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13214 tempreg, tempreg, breg);
13216 offset_reloc[0] = BFD_RELOC_LO16;
13217 offset_reloc[1] = BFD_RELOC_UNUSED;
13218 offset_reloc[2] = BFD_RELOC_UNUSED;
13223 else if (!ust && op[0] == breg)
13234 if (!target_big_endian)
13235 ep->X_add_number += off;
13237 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13239 macro_build (ep, s, "t,o(b)", tempreg, -1,
13240 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13242 if (!target_big_endian)
13243 ep->X_add_number -= off;
13245 ep->X_add_number += off;
13247 macro_build (NULL, s2, "t,~(b)",
13248 tempreg, (int) ep->X_add_number, breg);
13250 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13251 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13253 /* If necessary, move the result in tempreg to the final destination. */
13254 if (!ust && op[0] != tempreg)
13256 /* Protect second load's delay slot. */
13258 move_register (op[0], tempreg);
13264 if (target_big_endian == ust)
13265 ep->X_add_number += off;
13266 tempreg = ust || large_offset ? op[0] : AT;
13267 macro_build (ep, s, "t,o(b)", tempreg, -1,
13268 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13270 /* For halfword transfers we need a temporary register to shuffle
13271 bytes. Unfortunately for M_USH_A we have none available before
13272 the next store as AT holds the base address. We deal with this
13273 case by clobbering TREG and then restoring it as with ULH. */
13274 tempreg = ust == large_offset ? op[0] : AT;
13276 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13278 if (target_big_endian == ust)
13279 ep->X_add_number -= off;
13281 ep->X_add_number += off;
13282 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13283 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13285 /* For M_USH_A re-retrieve the LSB. */
13286 if (ust && large_offset)
13288 if (target_big_endian)
13289 ep->X_add_number += off;
13291 ep->X_add_number -= off;
13292 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13293 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13295 /* For ULH and M_USH_A OR the LSB in. */
13296 if (!ust || large_offset)
13298 tempreg = !large_offset ? AT : op[0];
13299 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13300 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13305 /* FIXME: Check if this is one of the itbl macros, since they
13306 are added dynamically. */
13307 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13310 if (!mips_opts.at && used_at)
13311 as_bad (_("macro used $at after \".set noat\""));
13314 /* Implement macros in mips16 mode. */
13317 mips16_macro (struct mips_cl_insn *ip)
13319 const struct mips_operand_array *operands;
13324 const char *s, *s2, *s3;
13325 unsigned int op[MAX_OPERANDS];
13328 mask = ip->insn_mo->mask;
13330 operands = insn_operands (ip);
13331 for (i = 0; i < MAX_OPERANDS; i++)
13332 if (operands->operand[i])
13333 op[i] = insn_extract_operand (ip, operands->operand[i]);
13337 expr1.X_op = O_constant;
13338 expr1.X_op_symbol = NULL;
13339 expr1.X_add_symbol = NULL;
13340 expr1.X_add_number = 1;
13359 start_noreorder ();
13360 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13361 expr1.X_add_number = 2;
13362 macro_build (&expr1, "bnez", "x,p", op[2]);
13363 macro_build (NULL, "break", "6", 7);
13365 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13366 since that causes an overflow. We should do that as well,
13367 but I don't see how to do the comparisons without a temporary
13370 macro_build (NULL, s, "x", op[0]);
13389 start_noreorder ();
13390 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13391 expr1.X_add_number = 2;
13392 macro_build (&expr1, "bnez", "x,p", op[2]);
13393 macro_build (NULL, "break", "6", 7);
13395 macro_build (NULL, s2, "x", op[0]);
13401 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13402 macro_build (NULL, "mflo", "x", op[0]);
13410 imm_expr.X_add_number = -imm_expr.X_add_number;
13411 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13415 imm_expr.X_add_number = -imm_expr.X_add_number;
13416 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13420 imm_expr.X_add_number = -imm_expr.X_add_number;
13421 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13443 goto do_reverse_branch;
13447 goto do_reverse_branch;
13459 goto do_reverse_branch;
13470 macro_build (NULL, s, "x,y", op[0], op[1]);
13471 macro_build (&offset_expr, s2, "p");
13498 goto do_addone_branch_i;
13503 goto do_addone_branch_i;
13518 goto do_addone_branch_i;
13524 do_addone_branch_i:
13525 ++imm_expr.X_add_number;
13528 macro_build (&imm_expr, s, s3, op[0]);
13529 macro_build (&offset_expr, s2, "p");
13533 expr1.X_add_number = 0;
13534 macro_build (&expr1, "slti", "x,8", op[1]);
13535 if (op[0] != op[1])
13536 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13537 expr1.X_add_number = 2;
13538 macro_build (&expr1, "bteqz", "p");
13539 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13544 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13545 opcode bits in *OPCODE_EXTRA. */
13547 static struct mips_opcode *
13548 mips_lookup_insn (struct hash_control *hash, const char *start,
13549 ssize_t length, unsigned int *opcode_extra)
13551 char *name, *dot, *p;
13552 unsigned int mask, suffix;
13554 struct mips_opcode *insn;
13556 /* Make a copy of the instruction so that we can fiddle with it. */
13557 name = xstrndup (start, length);
13559 /* Look up the instruction as-is. */
13560 insn = (struct mips_opcode *) hash_find (hash, name);
13564 dot = strchr (name, '.');
13567 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13568 p = mips_parse_vu0_channels (dot + 1, &mask);
13569 if (*p == 0 && mask != 0)
13572 insn = (struct mips_opcode *) hash_find (hash, name);
13574 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13576 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13582 if (mips_opts.micromips)
13584 /* See if there's an instruction size override suffix,
13585 either `16' or `32', at the end of the mnemonic proper,
13586 that defines the operation, i.e. before the first `.'
13587 character if any. Strip it and retry. */
13588 opend = dot != NULL ? dot - name : length;
13589 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13591 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13597 memcpy (name + opend - 2, name + opend, length - opend + 1);
13598 insn = (struct mips_opcode *) hash_find (hash, name);
13601 forced_insn_length = suffix;
13613 /* Assemble an instruction into its binary format. If the instruction
13614 is a macro, set imm_expr and offset_expr to the values associated
13615 with "I" and "A" operands respectively. Otherwise store the value
13616 of the relocatable field (if any) in offset_expr. In both cases
13617 set offset_reloc to the relocation operators applied to offset_expr. */
13620 mips_ip (char *str, struct mips_cl_insn *insn)
13622 const struct mips_opcode *first, *past;
13623 struct hash_control *hash;
13626 struct mips_operand_token *tokens;
13627 unsigned int opcode_extra;
13629 if (mips_opts.micromips)
13631 hash = micromips_op_hash;
13632 past = µmips_opcodes[bfd_micromips_num_opcodes];
13637 past = &mips_opcodes[NUMOPCODES];
13639 forced_insn_length = 0;
13642 /* We first try to match an instruction up to a space or to the end. */
13643 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13646 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13649 set_insn_error (0, _("unrecognized opcode"));
13653 if (strcmp (first->name, "li.s") == 0)
13655 else if (strcmp (first->name, "li.d") == 0)
13659 tokens = mips_parse_arguments (str + end, format);
13663 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13664 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13665 set_insn_error (0, _("invalid operands"));
13667 obstack_free (&mips_operand_tokens, tokens);
13670 /* As for mips_ip, but used when assembling MIPS16 code.
13671 Also set forced_insn_length to the resulting instruction size in
13672 bytes if the user explicitly requested a small or extended instruction. */
13675 mips16_ip (char *str, struct mips_cl_insn *insn)
13678 struct mips_opcode *first;
13679 struct mips_operand_token *tokens;
13681 forced_insn_length = 0;
13683 for (s = str; ISLOWER (*s); ++s)
13697 if (s[1] == 't' && s[2] == ' ')
13699 forced_insn_length = 2;
13703 else if (s[1] == 'e' && s[2] == ' ')
13705 forced_insn_length = 4;
13709 /* Fall through. */
13711 set_insn_error (0, _("unrecognized opcode"));
13715 if (mips_opts.noautoextend && !forced_insn_length)
13716 forced_insn_length = 2;
13719 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13724 set_insn_error (0, _("unrecognized opcode"));
13728 tokens = mips_parse_arguments (s, 0);
13732 if (!match_mips16_insns (insn, first, tokens))
13733 set_insn_error (0, _("invalid operands"));
13735 obstack_free (&mips_operand_tokens, tokens);
13738 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13739 NBITS is the number of significant bits in VAL. */
13741 static unsigned long
13742 mips16_immed_extend (offsetT val, unsigned int nbits)
13747 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13750 else if (nbits == 15)
13752 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13757 extval = ((val & 0x1f) << 6) | (val & 0x20);
13760 return (extval << 16) | val;
13763 /* Like decode_mips16_operand, but require the operand to be defined and
13764 require it to be an integer. */
13766 static const struct mips_int_operand *
13767 mips16_immed_operand (int type, bfd_boolean extended_p)
13769 const struct mips_operand *operand;
13771 operand = decode_mips16_operand (type, extended_p);
13772 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13774 return (const struct mips_int_operand *) operand;
13777 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13780 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13781 bfd_reloc_code_real_type reloc, offsetT sval)
13783 int min_val, max_val;
13785 min_val = mips_int_operand_min (operand);
13786 max_val = mips_int_operand_max (operand);
13787 if (reloc != BFD_RELOC_UNUSED)
13790 sval = SEXT_16BIT (sval);
13795 return (sval >= min_val
13797 && (sval & ((1 << operand->shift) - 1)) == 0);
13800 /* Install immediate value VAL into MIPS16 instruction *INSN,
13801 extending it if necessary. The instruction in *INSN may
13802 already be extended.
13804 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13805 if none. In the former case, VAL is a 16-bit number with no
13806 defined signedness.
13808 TYPE is the type of the immediate field. USER_INSN_LENGTH
13809 is the length that the user requested, or 0 if none. */
13812 mips16_immed (const char *file, unsigned int line, int type,
13813 bfd_reloc_code_real_type reloc, offsetT val,
13814 unsigned int user_insn_length, unsigned long *insn)
13816 const struct mips_int_operand *operand;
13817 unsigned int uval, length;
13819 operand = mips16_immed_operand (type, FALSE);
13820 if (!mips16_immed_in_range_p (operand, reloc, val))
13822 /* We need an extended instruction. */
13823 if (user_insn_length == 2)
13824 as_bad_where (file, line, _("invalid unextended operand value"));
13826 *insn |= MIPS16_EXTEND;
13828 else if (user_insn_length == 4)
13830 /* The operand doesn't force an unextended instruction to be extended.
13831 Warn if the user wanted an extended instruction anyway. */
13832 *insn |= MIPS16_EXTEND;
13833 as_warn_where (file, line,
13834 _("extended operand requested but not required"));
13837 length = mips16_opcode_length (*insn);
13840 operand = mips16_immed_operand (type, TRUE);
13841 if (!mips16_immed_in_range_p (operand, reloc, val))
13842 as_bad_where (file, line,
13843 _("operand value out of range for instruction"));
13845 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13847 *insn = mips_insert_operand (&operand->root, *insn, uval);
13849 *insn |= mips16_immed_extend (uval, operand->root.size);
13852 struct percent_op_match
13855 bfd_reloc_code_real_type reloc;
13858 static const struct percent_op_match mips_percent_op[] =
13860 {"%lo", BFD_RELOC_LO16},
13861 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13862 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13863 {"%call16", BFD_RELOC_MIPS_CALL16},
13864 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13865 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13866 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13867 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13868 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13869 {"%got", BFD_RELOC_MIPS_GOT16},
13870 {"%gp_rel", BFD_RELOC_GPREL16},
13871 {"%half", BFD_RELOC_16},
13872 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13873 {"%higher", BFD_RELOC_MIPS_HIGHER},
13874 {"%neg", BFD_RELOC_MIPS_SUB},
13875 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13876 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13877 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13878 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13879 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13880 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13881 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13882 {"%hi", BFD_RELOC_HI16_S},
13883 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13884 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
13887 static const struct percent_op_match mips16_percent_op[] =
13889 {"%lo", BFD_RELOC_MIPS16_LO16},
13890 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13891 {"%got", BFD_RELOC_MIPS16_GOT16},
13892 {"%call16", BFD_RELOC_MIPS16_CALL16},
13893 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13894 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13895 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13896 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13897 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13898 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13899 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13900 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13904 /* Return true if *STR points to a relocation operator. When returning true,
13905 move *STR over the operator and store its relocation code in *RELOC.
13906 Leave both *STR and *RELOC alone when returning false. */
13909 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13911 const struct percent_op_match *percent_op;
13914 if (mips_opts.mips16)
13916 percent_op = mips16_percent_op;
13917 limit = ARRAY_SIZE (mips16_percent_op);
13921 percent_op = mips_percent_op;
13922 limit = ARRAY_SIZE (mips_percent_op);
13925 for (i = 0; i < limit; i++)
13926 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13928 int len = strlen (percent_op[i].str);
13930 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13933 *str += strlen (percent_op[i].str);
13934 *reloc = percent_op[i].reloc;
13936 /* Check whether the output BFD supports this relocation.
13937 If not, issue an error and fall back on something safe. */
13938 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13940 as_bad (_("relocation %s isn't supported by the current ABI"),
13941 percent_op[i].str);
13942 *reloc = BFD_RELOC_UNUSED;
13950 /* Parse string STR as a 16-bit relocatable operand. Store the
13951 expression in *EP and the relocations in the array starting
13952 at RELOC. Return the number of relocation operators used.
13954 On exit, EXPR_END points to the first character after the expression. */
13957 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13960 bfd_reloc_code_real_type reversed_reloc[3];
13961 size_t reloc_index, i;
13962 int crux_depth, str_depth;
13965 /* Search for the start of the main expression, recoding relocations
13966 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13967 of the main expression and with CRUX_DEPTH containing the number
13968 of open brackets at that point. */
13975 crux_depth = str_depth;
13977 /* Skip over whitespace and brackets, keeping count of the number
13979 while (*str == ' ' || *str == '\t' || *str == '(')
13984 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13985 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13987 my_getExpression (ep, crux);
13990 /* Match every open bracket. */
13991 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13995 if (crux_depth > 0)
13996 as_bad (_("unclosed '('"));
14000 if (reloc_index != 0)
14002 prev_reloc_op_frag = frag_now;
14003 for (i = 0; i < reloc_index; i++)
14004 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14007 return reloc_index;
14011 my_getExpression (expressionS *ep, char *str)
14015 save_in = input_line_pointer;
14016 input_line_pointer = str;
14018 expr_end = input_line_pointer;
14019 input_line_pointer = save_in;
14023 md_atof (int type, char *litP, int *sizeP)
14025 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14029 md_number_to_chars (char *buf, valueT val, int n)
14031 if (target_big_endian)
14032 number_to_chars_bigendian (buf, val, n);
14034 number_to_chars_littleendian (buf, val, n);
14037 static int support_64bit_objects(void)
14039 const char **list, **l;
14042 list = bfd_target_list ();
14043 for (l = list; *l != NULL; l++)
14044 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14045 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14047 yes = (*l != NULL);
14052 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14053 NEW_VALUE. Warn if another value was already specified. Note:
14054 we have to defer parsing the -march and -mtune arguments in order
14055 to handle 'from-abi' correctly, since the ABI might be specified
14056 in a later argument. */
14059 mips_set_option_string (const char **string_ptr, const char *new_value)
14061 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14062 as_warn (_("a different %s was already specified, is now %s"),
14063 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14066 *string_ptr = new_value;
14070 md_parse_option (int c, const char *arg)
14074 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14075 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14077 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14078 c == mips_ases[i].option_on);
14084 case OPTION_CONSTRUCT_FLOATS:
14085 mips_disable_float_construction = 0;
14088 case OPTION_NO_CONSTRUCT_FLOATS:
14089 mips_disable_float_construction = 1;
14101 target_big_endian = 1;
14105 target_big_endian = 0;
14111 else if (arg[0] == '0')
14113 else if (arg[0] == '1')
14123 mips_debug = atoi (arg);
14127 file_mips_opts.isa = ISA_MIPS1;
14131 file_mips_opts.isa = ISA_MIPS2;
14135 file_mips_opts.isa = ISA_MIPS3;
14139 file_mips_opts.isa = ISA_MIPS4;
14143 file_mips_opts.isa = ISA_MIPS5;
14146 case OPTION_MIPS32:
14147 file_mips_opts.isa = ISA_MIPS32;
14150 case OPTION_MIPS32R2:
14151 file_mips_opts.isa = ISA_MIPS32R2;
14154 case OPTION_MIPS32R3:
14155 file_mips_opts.isa = ISA_MIPS32R3;
14158 case OPTION_MIPS32R5:
14159 file_mips_opts.isa = ISA_MIPS32R5;
14162 case OPTION_MIPS32R6:
14163 file_mips_opts.isa = ISA_MIPS32R6;
14166 case OPTION_MIPS64R2:
14167 file_mips_opts.isa = ISA_MIPS64R2;
14170 case OPTION_MIPS64R3:
14171 file_mips_opts.isa = ISA_MIPS64R3;
14174 case OPTION_MIPS64R5:
14175 file_mips_opts.isa = ISA_MIPS64R5;
14178 case OPTION_MIPS64R6:
14179 file_mips_opts.isa = ISA_MIPS64R6;
14182 case OPTION_MIPS64:
14183 file_mips_opts.isa = ISA_MIPS64;
14187 mips_set_option_string (&mips_tune_string, arg);
14191 mips_set_option_string (&mips_arch_string, arg);
14195 mips_set_option_string (&mips_arch_string, "4650");
14196 mips_set_option_string (&mips_tune_string, "4650");
14199 case OPTION_NO_M4650:
14203 mips_set_option_string (&mips_arch_string, "4010");
14204 mips_set_option_string (&mips_tune_string, "4010");
14207 case OPTION_NO_M4010:
14211 mips_set_option_string (&mips_arch_string, "4100");
14212 mips_set_option_string (&mips_tune_string, "4100");
14215 case OPTION_NO_M4100:
14219 mips_set_option_string (&mips_arch_string, "3900");
14220 mips_set_option_string (&mips_tune_string, "3900");
14223 case OPTION_NO_M3900:
14226 case OPTION_MICROMIPS:
14227 if (file_mips_opts.mips16 == 1)
14229 as_bad (_("-mmicromips cannot be used with -mips16"));
14232 file_mips_opts.micromips = 1;
14233 mips_no_prev_insn ();
14236 case OPTION_NO_MICROMIPS:
14237 file_mips_opts.micromips = 0;
14238 mips_no_prev_insn ();
14241 case OPTION_MIPS16:
14242 if (file_mips_opts.micromips == 1)
14244 as_bad (_("-mips16 cannot be used with -micromips"));
14247 file_mips_opts.mips16 = 1;
14248 mips_no_prev_insn ();
14251 case OPTION_NO_MIPS16:
14252 file_mips_opts.mips16 = 0;
14253 mips_no_prev_insn ();
14256 case OPTION_FIX_24K:
14260 case OPTION_NO_FIX_24K:
14264 case OPTION_FIX_RM7000:
14265 mips_fix_rm7000 = 1;
14268 case OPTION_NO_FIX_RM7000:
14269 mips_fix_rm7000 = 0;
14272 case OPTION_FIX_LOONGSON2F_JUMP:
14273 mips_fix_loongson2f_jump = TRUE;
14276 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14277 mips_fix_loongson2f_jump = FALSE;
14280 case OPTION_FIX_LOONGSON2F_NOP:
14281 mips_fix_loongson2f_nop = TRUE;
14284 case OPTION_NO_FIX_LOONGSON2F_NOP:
14285 mips_fix_loongson2f_nop = FALSE;
14288 case OPTION_FIX_VR4120:
14289 mips_fix_vr4120 = 1;
14292 case OPTION_NO_FIX_VR4120:
14293 mips_fix_vr4120 = 0;
14296 case OPTION_FIX_VR4130:
14297 mips_fix_vr4130 = 1;
14300 case OPTION_NO_FIX_VR4130:
14301 mips_fix_vr4130 = 0;
14304 case OPTION_FIX_CN63XXP1:
14305 mips_fix_cn63xxp1 = TRUE;
14308 case OPTION_NO_FIX_CN63XXP1:
14309 mips_fix_cn63xxp1 = FALSE;
14312 case OPTION_RELAX_BRANCH:
14313 mips_relax_branch = 1;
14316 case OPTION_NO_RELAX_BRANCH:
14317 mips_relax_branch = 0;
14320 case OPTION_INSN32:
14321 file_mips_opts.insn32 = TRUE;
14324 case OPTION_NO_INSN32:
14325 file_mips_opts.insn32 = FALSE;
14328 case OPTION_MSHARED:
14329 mips_in_shared = TRUE;
14332 case OPTION_MNO_SHARED:
14333 mips_in_shared = FALSE;
14336 case OPTION_MSYM32:
14337 file_mips_opts.sym32 = TRUE;
14340 case OPTION_MNO_SYM32:
14341 file_mips_opts.sym32 = FALSE;
14344 /* When generating ELF code, we permit -KPIC and -call_shared to
14345 select SVR4_PIC, and -non_shared to select no PIC. This is
14346 intended to be compatible with Irix 5. */
14347 case OPTION_CALL_SHARED:
14348 mips_pic = SVR4_PIC;
14349 mips_abicalls = TRUE;
14352 case OPTION_CALL_NONPIC:
14354 mips_abicalls = TRUE;
14357 case OPTION_NON_SHARED:
14359 mips_abicalls = FALSE;
14362 /* The -xgot option tells the assembler to use 32 bit offsets
14363 when accessing the got in SVR4_PIC mode. It is for Irix
14370 g_switch_value = atoi (arg);
14374 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14377 mips_abi = O32_ABI;
14381 mips_abi = N32_ABI;
14385 mips_abi = N64_ABI;
14386 if (!support_64bit_objects())
14387 as_fatal (_("no compiled in support for 64 bit object file format"));
14391 file_mips_opts.gp = 32;
14395 file_mips_opts.gp = 64;
14399 file_mips_opts.fp = 32;
14403 file_mips_opts.fp = 0;
14407 file_mips_opts.fp = 64;
14410 case OPTION_ODD_SPREG:
14411 file_mips_opts.oddspreg = 1;
14414 case OPTION_NO_ODD_SPREG:
14415 file_mips_opts.oddspreg = 0;
14418 case OPTION_SINGLE_FLOAT:
14419 file_mips_opts.single_float = 1;
14422 case OPTION_DOUBLE_FLOAT:
14423 file_mips_opts.single_float = 0;
14426 case OPTION_SOFT_FLOAT:
14427 file_mips_opts.soft_float = 1;
14430 case OPTION_HARD_FLOAT:
14431 file_mips_opts.soft_float = 0;
14435 if (strcmp (arg, "32") == 0)
14436 mips_abi = O32_ABI;
14437 else if (strcmp (arg, "o64") == 0)
14438 mips_abi = O64_ABI;
14439 else if (strcmp (arg, "n32") == 0)
14440 mips_abi = N32_ABI;
14441 else if (strcmp (arg, "64") == 0)
14443 mips_abi = N64_ABI;
14444 if (! support_64bit_objects())
14445 as_fatal (_("no compiled in support for 64 bit object file "
14448 else if (strcmp (arg, "eabi") == 0)
14449 mips_abi = EABI_ABI;
14452 as_fatal (_("invalid abi -mabi=%s"), arg);
14457 case OPTION_M7000_HILO_FIX:
14458 mips_7000_hilo_fix = TRUE;
14461 case OPTION_MNO_7000_HILO_FIX:
14462 mips_7000_hilo_fix = FALSE;
14465 case OPTION_MDEBUG:
14466 mips_flag_mdebug = TRUE;
14469 case OPTION_NO_MDEBUG:
14470 mips_flag_mdebug = FALSE;
14474 mips_flag_pdr = TRUE;
14477 case OPTION_NO_PDR:
14478 mips_flag_pdr = FALSE;
14481 case OPTION_MVXWORKS_PIC:
14482 mips_pic = VXWORKS_PIC;
14486 if (strcmp (arg, "2008") == 0)
14488 else if (strcmp (arg, "legacy") == 0)
14492 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14501 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14506 /* Set up globals to tune for the ISA or processor described by INFO. */
14509 mips_set_tune (const struct mips_cpu_info *info)
14512 mips_tune = info->cpu;
14517 mips_after_parse_args (void)
14519 const struct mips_cpu_info *arch_info = 0;
14520 const struct mips_cpu_info *tune_info = 0;
14522 /* GP relative stuff not working for PE */
14523 if (strncmp (TARGET_OS, "pe", 2) == 0)
14525 if (g_switch_seen && g_switch_value != 0)
14526 as_bad (_("-G not supported in this configuration"));
14527 g_switch_value = 0;
14530 if (mips_abi == NO_ABI)
14531 mips_abi = MIPS_DEFAULT_ABI;
14533 /* The following code determines the architecture.
14534 Similar code was added to GCC 3.3 (see override_options() in
14535 config/mips/mips.c). The GAS and GCC code should be kept in sync
14536 as much as possible. */
14538 if (mips_arch_string != 0)
14539 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14541 if (file_mips_opts.isa != ISA_UNKNOWN)
14543 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14544 ISA level specified by -mipsN, while arch_info->isa contains
14545 the -march selection (if any). */
14546 if (arch_info != 0)
14548 /* -march takes precedence over -mipsN, since it is more descriptive.
14549 There's no harm in specifying both as long as the ISA levels
14551 if (file_mips_opts.isa != arch_info->isa)
14552 as_bad (_("-%s conflicts with the other architecture options,"
14553 " which imply -%s"),
14554 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14555 mips_cpu_info_from_isa (arch_info->isa)->name);
14558 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14561 if (arch_info == 0)
14563 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14564 gas_assert (arch_info);
14567 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14568 as_bad (_("-march=%s is not compatible with the selected ABI"),
14571 file_mips_opts.arch = arch_info->cpu;
14572 file_mips_opts.isa = arch_info->isa;
14574 /* Set up initial mips_opts state. */
14575 mips_opts = file_mips_opts;
14577 /* The register size inference code is now placed in
14578 file_mips_check_options. */
14580 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14582 if (mips_tune_string != 0)
14583 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14585 if (tune_info == 0)
14586 mips_set_tune (arch_info);
14588 mips_set_tune (tune_info);
14590 if (mips_flag_mdebug < 0)
14591 mips_flag_mdebug = 0;
14595 mips_init_after_args (void)
14597 /* initialize opcodes */
14598 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14599 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14603 md_pcrel_from (fixS *fixP)
14605 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14606 switch (fixP->fx_r_type)
14608 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14609 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14610 /* Return the address of the delay slot. */
14613 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14614 case BFD_RELOC_MICROMIPS_JMP:
14615 case BFD_RELOC_16_PCREL_S2:
14616 case BFD_RELOC_MIPS_21_PCREL_S2:
14617 case BFD_RELOC_MIPS_26_PCREL_S2:
14618 case BFD_RELOC_MIPS_JMP:
14619 /* Return the address of the delay slot. */
14622 case BFD_RELOC_MIPS_18_PCREL_S3:
14623 /* Return the aligned address of the doubleword containing
14624 the instruction. */
14632 /* This is called before the symbol table is processed. In order to
14633 work with gcc when using mips-tfile, we must keep all local labels.
14634 However, in other cases, we want to discard them. If we were
14635 called with -g, but we didn't see any debugging information, it may
14636 mean that gcc is smuggling debugging information through to
14637 mips-tfile, in which case we must generate all local labels. */
14640 mips_frob_file_before_adjust (void)
14642 #ifndef NO_ECOFF_DEBUGGING
14643 if (ECOFF_DEBUGGING
14645 && ! ecoff_debugging_seen)
14646 flag_keep_locals = 1;
14650 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14651 the corresponding LO16 reloc. This is called before md_apply_fix and
14652 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14653 relocation operators.
14655 For our purposes, a %lo() expression matches a %got() or %hi()
14658 (a) it refers to the same symbol; and
14659 (b) the offset applied in the %lo() expression is no lower than
14660 the offset applied in the %got() or %hi().
14662 (b) allows us to cope with code like:
14665 lh $4,%lo(foo+2)($4)
14667 ...which is legal on RELA targets, and has a well-defined behaviour
14668 if the user knows that adding 2 to "foo" will not induce a carry to
14671 When several %lo()s match a particular %got() or %hi(), we use the
14672 following rules to distinguish them:
14674 (1) %lo()s with smaller offsets are a better match than %lo()s with
14677 (2) %lo()s with no matching %got() or %hi() are better than those
14678 that already have a matching %got() or %hi().
14680 (3) later %lo()s are better than earlier %lo()s.
14682 These rules are applied in order.
14684 (1) means, among other things, that %lo()s with identical offsets are
14685 chosen if they exist.
14687 (2) means that we won't associate several high-part relocations with
14688 the same low-part relocation unless there's no alternative. Having
14689 several high parts for the same low part is a GNU extension; this rule
14690 allows careful users to avoid it.
14692 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14693 with the last high-part relocation being at the front of the list.
14694 It therefore makes sense to choose the last matching low-part
14695 relocation, all other things being equal. It's also easier
14696 to code that way. */
14699 mips_frob_file (void)
14701 struct mips_hi_fixup *l;
14702 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14704 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14706 segment_info_type *seginfo;
14707 bfd_boolean matched_lo_p;
14708 fixS **hi_pos, **lo_pos, **pos;
14710 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14712 /* If a GOT16 relocation turns out to be against a global symbol,
14713 there isn't supposed to be a matching LO. Ignore %gots against
14714 constants; we'll report an error for those later. */
14715 if (got16_reloc_p (l->fixp->fx_r_type)
14716 && !(l->fixp->fx_addsy
14717 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14720 /* Check quickly whether the next fixup happens to be a matching %lo. */
14721 if (fixup_has_matching_lo_p (l->fixp))
14724 seginfo = seg_info (l->seg);
14726 /* Set HI_POS to the position of this relocation in the chain.
14727 Set LO_POS to the position of the chosen low-part relocation.
14728 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14729 relocation that matches an immediately-preceding high-part
14733 matched_lo_p = FALSE;
14734 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14736 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14738 if (*pos == l->fixp)
14741 if ((*pos)->fx_r_type == looking_for_rtype
14742 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14743 && (*pos)->fx_offset >= l->fixp->fx_offset
14745 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14747 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14750 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14751 && fixup_has_matching_lo_p (*pos));
14754 /* If we found a match, remove the high-part relocation from its
14755 current position and insert it before the low-part relocation.
14756 Make the offsets match so that fixup_has_matching_lo_p()
14759 We don't warn about unmatched high-part relocations since some
14760 versions of gcc have been known to emit dead "lui ...%hi(...)"
14762 if (lo_pos != NULL)
14764 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14765 if (l->fixp->fx_next != *lo_pos)
14767 *hi_pos = l->fixp->fx_next;
14768 l->fixp->fx_next = *lo_pos;
14776 mips_force_relocation (fixS *fixp)
14778 if (generic_force_reloc (fixp))
14781 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14782 so that the linker relaxation can update targets. */
14783 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14784 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14785 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14788 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14789 if (ISA_IS_R6 (file_mips_opts.isa)
14790 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14791 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14792 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14793 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14794 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14795 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14796 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14802 /* Read the instruction associated with RELOC from BUF. */
14804 static unsigned int
14805 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14807 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14808 return read_compressed_insn (buf, 4);
14810 return read_insn (buf);
14813 /* Write instruction INSN to BUF, given that it has been relocated
14817 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14818 unsigned long insn)
14820 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14821 write_compressed_insn (buf, insn, 4);
14823 write_insn (buf, insn);
14826 /* Apply a fixup to the object file. */
14829 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14832 unsigned long insn;
14833 reloc_howto_type *howto;
14835 if (fixP->fx_pcrel)
14836 switch (fixP->fx_r_type)
14838 case BFD_RELOC_16_PCREL_S2:
14839 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14840 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14841 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14842 case BFD_RELOC_32_PCREL:
14843 case BFD_RELOC_MIPS_21_PCREL_S2:
14844 case BFD_RELOC_MIPS_26_PCREL_S2:
14845 case BFD_RELOC_MIPS_18_PCREL_S3:
14846 case BFD_RELOC_MIPS_19_PCREL_S2:
14847 case BFD_RELOC_HI16_S_PCREL:
14848 case BFD_RELOC_LO16_PCREL:
14852 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14856 as_bad_where (fixP->fx_file, fixP->fx_line,
14857 _("PC-relative reference to a different section"));
14861 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14862 that have no MIPS ELF equivalent. */
14863 if (fixP->fx_r_type != BFD_RELOC_8)
14865 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14870 gas_assert (fixP->fx_size == 2
14871 || fixP->fx_size == 4
14872 || fixP->fx_r_type == BFD_RELOC_8
14873 || fixP->fx_r_type == BFD_RELOC_16
14874 || fixP->fx_r_type == BFD_RELOC_64
14875 || fixP->fx_r_type == BFD_RELOC_CTOR
14876 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14877 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14878 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14879 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14880 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
14881 || fixP->fx_r_type == BFD_RELOC_NONE);
14883 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14885 /* Don't treat parts of a composite relocation as done. There are two
14888 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14889 should nevertheless be emitted if the first part is.
14891 (2) In normal usage, composite relocations are never assembly-time
14892 constants. The easiest way of dealing with the pathological
14893 exceptions is to generate a relocation against STN_UNDEF and
14894 leave everything up to the linker. */
14895 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14898 switch (fixP->fx_r_type)
14900 case BFD_RELOC_MIPS_TLS_GD:
14901 case BFD_RELOC_MIPS_TLS_LDM:
14902 case BFD_RELOC_MIPS_TLS_DTPREL32:
14903 case BFD_RELOC_MIPS_TLS_DTPREL64:
14904 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14905 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14906 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14907 case BFD_RELOC_MIPS_TLS_TPREL32:
14908 case BFD_RELOC_MIPS_TLS_TPREL64:
14909 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14910 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14911 case BFD_RELOC_MICROMIPS_TLS_GD:
14912 case BFD_RELOC_MICROMIPS_TLS_LDM:
14913 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14914 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14915 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14916 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14917 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14918 case BFD_RELOC_MIPS16_TLS_GD:
14919 case BFD_RELOC_MIPS16_TLS_LDM:
14920 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14921 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14922 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14923 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14924 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14925 if (fixP->fx_addsy)
14926 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14928 as_bad_where (fixP->fx_file, fixP->fx_line,
14929 _("TLS relocation against a constant"));
14932 case BFD_RELOC_MIPS_JMP:
14933 case BFD_RELOC_MIPS_SHIFT5:
14934 case BFD_RELOC_MIPS_SHIFT6:
14935 case BFD_RELOC_MIPS_GOT_DISP:
14936 case BFD_RELOC_MIPS_GOT_PAGE:
14937 case BFD_RELOC_MIPS_GOT_OFST:
14938 case BFD_RELOC_MIPS_SUB:
14939 case BFD_RELOC_MIPS_INSERT_A:
14940 case BFD_RELOC_MIPS_INSERT_B:
14941 case BFD_RELOC_MIPS_DELETE:
14942 case BFD_RELOC_MIPS_HIGHEST:
14943 case BFD_RELOC_MIPS_HIGHER:
14944 case BFD_RELOC_MIPS_SCN_DISP:
14945 case BFD_RELOC_MIPS_REL16:
14946 case BFD_RELOC_MIPS_RELGOT:
14947 case BFD_RELOC_MIPS_JALR:
14948 case BFD_RELOC_HI16:
14949 case BFD_RELOC_HI16_S:
14950 case BFD_RELOC_LO16:
14951 case BFD_RELOC_GPREL16:
14952 case BFD_RELOC_MIPS_LITERAL:
14953 case BFD_RELOC_MIPS_CALL16:
14954 case BFD_RELOC_MIPS_GOT16:
14955 case BFD_RELOC_GPREL32:
14956 case BFD_RELOC_MIPS_GOT_HI16:
14957 case BFD_RELOC_MIPS_GOT_LO16:
14958 case BFD_RELOC_MIPS_CALL_HI16:
14959 case BFD_RELOC_MIPS_CALL_LO16:
14960 case BFD_RELOC_HI16_S_PCREL:
14961 case BFD_RELOC_LO16_PCREL:
14962 case BFD_RELOC_MIPS16_GPREL:
14963 case BFD_RELOC_MIPS16_GOT16:
14964 case BFD_RELOC_MIPS16_CALL16:
14965 case BFD_RELOC_MIPS16_HI16:
14966 case BFD_RELOC_MIPS16_HI16_S:
14967 case BFD_RELOC_MIPS16_LO16:
14968 case BFD_RELOC_MIPS16_JMP:
14969 case BFD_RELOC_MICROMIPS_JMP:
14970 case BFD_RELOC_MICROMIPS_GOT_DISP:
14971 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14972 case BFD_RELOC_MICROMIPS_GOT_OFST:
14973 case BFD_RELOC_MICROMIPS_SUB:
14974 case BFD_RELOC_MICROMIPS_HIGHEST:
14975 case BFD_RELOC_MICROMIPS_HIGHER:
14976 case BFD_RELOC_MICROMIPS_SCN_DISP:
14977 case BFD_RELOC_MICROMIPS_JALR:
14978 case BFD_RELOC_MICROMIPS_HI16:
14979 case BFD_RELOC_MICROMIPS_HI16_S:
14980 case BFD_RELOC_MICROMIPS_LO16:
14981 case BFD_RELOC_MICROMIPS_GPREL16:
14982 case BFD_RELOC_MICROMIPS_LITERAL:
14983 case BFD_RELOC_MICROMIPS_CALL16:
14984 case BFD_RELOC_MICROMIPS_GOT16:
14985 case BFD_RELOC_MICROMIPS_GOT_HI16:
14986 case BFD_RELOC_MICROMIPS_GOT_LO16:
14987 case BFD_RELOC_MICROMIPS_CALL_HI16:
14988 case BFD_RELOC_MICROMIPS_CALL_LO16:
14989 case BFD_RELOC_MIPS_EH:
14994 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14996 insn = read_reloc_insn (buf, fixP->fx_r_type);
14997 if (mips16_reloc_p (fixP->fx_r_type))
14998 insn |= mips16_immed_extend (value, 16);
15000 insn |= (value & 0xffff);
15001 write_reloc_insn (buf, fixP->fx_r_type, insn);
15004 as_bad_where (fixP->fx_file, fixP->fx_line,
15005 _("unsupported constant in relocation"));
15010 /* This is handled like BFD_RELOC_32, but we output a sign
15011 extended value if we are only 32 bits. */
15014 if (8 <= sizeof (valueT))
15015 md_number_to_chars (buf, *valP, 8);
15020 if ((*valP & 0x80000000) != 0)
15024 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15025 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15030 case BFD_RELOC_RVA:
15032 case BFD_RELOC_32_PCREL:
15035 /* If we are deleting this reloc entry, we must fill in the
15036 value now. This can happen if we have a .word which is not
15037 resolved when it appears but is later defined. */
15039 md_number_to_chars (buf, *valP, fixP->fx_size);
15042 case BFD_RELOC_MIPS_21_PCREL_S2:
15043 if ((*valP & 0x3) != 0)
15044 as_bad_where (fixP->fx_file, fixP->fx_line,
15045 _("branch to misaligned address (%lx)"), (long) *valP);
15046 if (!fixP->fx_done)
15049 if (*valP + 0x400000 <= 0x7fffff)
15051 insn = read_insn (buf);
15052 insn |= (*valP >> 2) & 0x1fffff;
15053 write_insn (buf, insn);
15056 as_bad_where (fixP->fx_file, fixP->fx_line,
15057 _("branch out of range"));
15060 case BFD_RELOC_MIPS_26_PCREL_S2:
15061 if ((*valP & 0x3) != 0)
15062 as_bad_where (fixP->fx_file, fixP->fx_line,
15063 _("branch to misaligned address (%lx)"), (long) *valP);
15064 if (!fixP->fx_done)
15067 if (*valP + 0x8000000 <= 0xfffffff)
15069 insn = read_insn (buf);
15070 insn |= (*valP >> 2) & 0x3ffffff;
15071 write_insn (buf, insn);
15074 as_bad_where (fixP->fx_file, fixP->fx_line,
15075 _("branch out of range"));
15078 case BFD_RELOC_MIPS_18_PCREL_S3:
15079 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15080 as_bad_where (fixP->fx_file, fixP->fx_line,
15081 _("PC-relative access using misaligned symbol (%lx)"),
15082 (long) S_GET_VALUE (fixP->fx_addsy));
15083 if ((fixP->fx_offset & 0x7) != 0)
15084 as_bad_where (fixP->fx_file, fixP->fx_line,
15085 _("PC-relative access using misaligned offset (%lx)"),
15086 (long) fixP->fx_offset);
15087 if (!fixP->fx_done)
15090 if (*valP + 0x100000 <= 0x1fffff)
15092 insn = read_insn (buf);
15093 insn |= (*valP >> 3) & 0x3ffff;
15094 write_insn (buf, insn);
15097 as_bad_where (fixP->fx_file, fixP->fx_line,
15098 _("PC-relative access out of range"));
15101 case BFD_RELOC_MIPS_19_PCREL_S2:
15102 if ((*valP & 0x3) != 0)
15103 as_bad_where (fixP->fx_file, fixP->fx_line,
15104 _("PC-relative access to misaligned address (%lx)"),
15106 if (!fixP->fx_done)
15109 if (*valP + 0x100000 <= 0x1fffff)
15111 insn = read_insn (buf);
15112 insn |= (*valP >> 2) & 0x7ffff;
15113 write_insn (buf, insn);
15116 as_bad_where (fixP->fx_file, fixP->fx_line,
15117 _("PC-relative access out of range"));
15120 case BFD_RELOC_16_PCREL_S2:
15121 if ((*valP & 0x3) != 0)
15122 as_bad_where (fixP->fx_file, fixP->fx_line,
15123 _("branch to misaligned address (%lx)"), (long) *valP);
15125 /* We need to save the bits in the instruction since fixup_segment()
15126 might be deleting the relocation entry (i.e., a branch within
15127 the current segment). */
15128 if (! fixP->fx_done)
15131 /* Update old instruction data. */
15132 insn = read_insn (buf);
15134 if (*valP + 0x20000 <= 0x3ffff)
15136 insn |= (*valP >> 2) & 0xffff;
15137 write_insn (buf, insn);
15139 else if (mips_pic == NO_PIC
15141 && fixP->fx_frag->fr_address >= text_section->vma
15142 && (fixP->fx_frag->fr_address
15143 < text_section->vma + bfd_get_section_size (text_section))
15144 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15145 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15146 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15148 /* The branch offset is too large. If this is an
15149 unconditional branch, and we are not generating PIC code,
15150 we can convert it to an absolute jump instruction. */
15151 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15152 insn = 0x0c000000; /* jal */
15154 insn = 0x08000000; /* j */
15155 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15157 fixP->fx_addsy = section_symbol (text_section);
15158 *valP += md_pcrel_from (fixP);
15159 write_insn (buf, insn);
15163 /* If we got here, we have branch-relaxation disabled,
15164 and there's nothing we can do to fix this instruction
15165 without turning it into a longer sequence. */
15166 as_bad_where (fixP->fx_file, fixP->fx_line,
15167 _("branch out of range"));
15171 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15172 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15173 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15174 /* We adjust the offset back to even. */
15175 if ((*valP & 0x1) != 0)
15178 if (! fixP->fx_done)
15181 /* Should never visit here, because we keep the relocation. */
15185 case BFD_RELOC_VTABLE_INHERIT:
15188 && !S_IS_DEFINED (fixP->fx_addsy)
15189 && !S_IS_WEAK (fixP->fx_addsy))
15190 S_SET_WEAK (fixP->fx_addsy);
15193 case BFD_RELOC_NONE:
15194 case BFD_RELOC_VTABLE_ENTRY:
15202 /* Remember value for tc_gen_reloc. */
15203 fixP->fx_addnumber = *valP;
15213 c = get_symbol_name (&name);
15214 p = (symbolS *) symbol_find_or_make (name);
15215 (void) restore_line_pointer (c);
15219 /* Align the current frag to a given power of two. If a particular
15220 fill byte should be used, FILL points to an integer that contains
15221 that byte, otherwise FILL is null.
15223 This function used to have the comment:
15225 The MIPS assembler also automatically adjusts any preceding label.
15227 The implementation therefore applied the adjustment to a maximum of
15228 one label. However, other label adjustments are applied to batches
15229 of labels, and adjusting just one caused problems when new labels
15230 were added for the sake of debugging or unwind information.
15231 We therefore adjust all preceding labels (given as LABELS) instead. */
15234 mips_align (int to, int *fill, struct insn_label_list *labels)
15236 mips_emit_delays ();
15237 mips_record_compressed_mode ();
15238 if (fill == NULL && subseg_text_p (now_seg))
15239 frag_align_code (to, 0);
15241 frag_align (to, fill ? *fill : 0, 0);
15242 record_alignment (now_seg, to);
15243 mips_move_labels (labels, FALSE);
15246 /* Align to a given power of two. .align 0 turns off the automatic
15247 alignment used by the data creating pseudo-ops. */
15250 s_align (int x ATTRIBUTE_UNUSED)
15252 int temp, fill_value, *fill_ptr;
15253 long max_alignment = 28;
15255 /* o Note that the assembler pulls down any immediately preceding label
15256 to the aligned address.
15257 o It's not documented but auto alignment is reinstated by
15258 a .align pseudo instruction.
15259 o Note also that after auto alignment is turned off the mips assembler
15260 issues an error on attempt to assemble an improperly aligned data item.
15263 temp = get_absolute_expression ();
15264 if (temp > max_alignment)
15265 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15268 as_warn (_("alignment negative, 0 assumed"));
15271 if (*input_line_pointer == ',')
15273 ++input_line_pointer;
15274 fill_value = get_absolute_expression ();
15275 fill_ptr = &fill_value;
15281 segment_info_type *si = seg_info (now_seg);
15282 struct insn_label_list *l = si->label_list;
15283 /* Auto alignment should be switched on by next section change. */
15285 mips_align (temp, fill_ptr, l);
15292 demand_empty_rest_of_line ();
15296 s_change_sec (int sec)
15300 /* The ELF backend needs to know that we are changing sections, so
15301 that .previous works correctly. We could do something like check
15302 for an obj_section_change_hook macro, but that might be confusing
15303 as it would not be appropriate to use it in the section changing
15304 functions in read.c, since obj-elf.c intercepts those. FIXME:
15305 This should be cleaner, somehow. */
15306 obj_elf_section_change_hook ();
15308 mips_emit_delays ();
15319 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15320 demand_empty_rest_of_line ();
15324 seg = subseg_new (RDATA_SECTION_NAME,
15325 (subsegT) get_absolute_expression ());
15326 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15327 | SEC_READONLY | SEC_RELOC
15329 if (strncmp (TARGET_OS, "elf", 3) != 0)
15330 record_alignment (seg, 4);
15331 demand_empty_rest_of_line ();
15335 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15336 bfd_set_section_flags (stdoutput, seg,
15337 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15338 if (strncmp (TARGET_OS, "elf", 3) != 0)
15339 record_alignment (seg, 4);
15340 demand_empty_rest_of_line ();
15344 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15345 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15346 if (strncmp (TARGET_OS, "elf", 3) != 0)
15347 record_alignment (seg, 4);
15348 demand_empty_rest_of_line ();
15356 s_change_section (int ignore ATTRIBUTE_UNUSED)
15359 char *section_name;
15364 int section_entry_size;
15365 int section_alignment;
15367 saved_ilp = input_line_pointer;
15368 endc = get_symbol_name (§ion_name);
15369 c = (endc == '"' ? input_line_pointer[1] : endc);
15371 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15373 /* Do we have .section Name<,"flags">? */
15374 if (c != ',' || (c == ',' && next_c == '"'))
15376 /* Just after name is now '\0'. */
15377 (void) restore_line_pointer (endc);
15378 input_line_pointer = saved_ilp;
15379 obj_elf_section (ignore);
15383 section_name = xstrdup (section_name);
15384 c = restore_line_pointer (endc);
15386 input_line_pointer++;
15388 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15390 section_type = get_absolute_expression ();
15394 if (*input_line_pointer++ == ',')
15395 section_flag = get_absolute_expression ();
15399 if (*input_line_pointer++ == ',')
15400 section_entry_size = get_absolute_expression ();
15402 section_entry_size = 0;
15404 if (*input_line_pointer++ == ',')
15405 section_alignment = get_absolute_expression ();
15407 section_alignment = 0;
15409 /* FIXME: really ignore? */
15410 (void) section_alignment;
15412 /* When using the generic form of .section (as implemented by obj-elf.c),
15413 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15414 traditionally had to fall back on the more common @progbits instead.
15416 There's nothing really harmful in this, since bfd will correct
15417 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15418 means that, for backwards compatibility, the special_section entries
15419 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15421 Even so, we shouldn't force users of the MIPS .section syntax to
15422 incorrectly label the sections as SHT_PROGBITS. The best compromise
15423 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15424 generic type-checking code. */
15425 if (section_type == SHT_MIPS_DWARF)
15426 section_type = SHT_PROGBITS;
15428 obj_elf_change_section (section_name, section_type, section_flag,
15429 section_entry_size, 0, 0, 0);
15431 if (now_seg->name != section_name)
15432 free (section_name);
15436 mips_enable_auto_align (void)
15442 s_cons (int log_size)
15444 segment_info_type *si = seg_info (now_seg);
15445 struct insn_label_list *l = si->label_list;
15447 mips_emit_delays ();
15448 if (log_size > 0 && auto_align)
15449 mips_align (log_size, 0, l);
15450 cons (1 << log_size);
15451 mips_clear_insn_labels ();
15455 s_float_cons (int type)
15457 segment_info_type *si = seg_info (now_seg);
15458 struct insn_label_list *l = si->label_list;
15460 mips_emit_delays ();
15465 mips_align (3, 0, l);
15467 mips_align (2, 0, l);
15471 mips_clear_insn_labels ();
15474 /* Handle .globl. We need to override it because on Irix 5 you are
15477 where foo is an undefined symbol, to mean that foo should be
15478 considered to be the address of a function. */
15481 s_mips_globl (int x ATTRIBUTE_UNUSED)
15490 c = get_symbol_name (&name);
15491 symbolP = symbol_find_or_make (name);
15492 S_SET_EXTERNAL (symbolP);
15494 *input_line_pointer = c;
15495 SKIP_WHITESPACE_AFTER_NAME ();
15497 /* On Irix 5, every global symbol that is not explicitly labelled as
15498 being a function is apparently labelled as being an object. */
15501 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15502 && (*input_line_pointer != ','))
15507 c = get_symbol_name (&secname);
15508 sec = bfd_get_section_by_name (stdoutput, secname);
15510 as_bad (_("%s: no such section"), secname);
15511 (void) restore_line_pointer (c);
15513 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15514 flag = BSF_FUNCTION;
15517 symbol_get_bfdsym (symbolP)->flags |= flag;
15519 c = *input_line_pointer;
15522 input_line_pointer++;
15523 SKIP_WHITESPACE ();
15524 if (is_end_of_line[(unsigned char) *input_line_pointer])
15530 demand_empty_rest_of_line ();
15534 s_option (int x ATTRIBUTE_UNUSED)
15539 c = get_symbol_name (&opt);
15543 /* FIXME: What does this mean? */
15545 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
15549 i = atoi (opt + 3);
15550 if (i != 0 && i != 2)
15551 as_bad (_(".option pic%d not supported"), i);
15552 else if (mips_pic == VXWORKS_PIC)
15553 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15558 mips_pic = SVR4_PIC;
15559 mips_abicalls = TRUE;
15562 if (mips_pic == SVR4_PIC)
15564 if (g_switch_seen && g_switch_value != 0)
15565 as_warn (_("-G may not be used with SVR4 PIC code"));
15566 g_switch_value = 0;
15567 bfd_set_gp_size (stdoutput, 0);
15571 as_warn (_("unrecognized option \"%s\""), opt);
15573 (void) restore_line_pointer (c);
15574 demand_empty_rest_of_line ();
15577 /* This structure is used to hold a stack of .set values. */
15579 struct mips_option_stack
15581 struct mips_option_stack *next;
15582 struct mips_set_options options;
15585 static struct mips_option_stack *mips_opts_stack;
15587 /* Return status for .set/.module option handling. */
15589 enum code_option_type
15591 /* Unrecognized option. */
15592 OPTION_TYPE_BAD = -1,
15594 /* Ordinary option. */
15595 OPTION_TYPE_NORMAL,
15597 /* ISA changing option. */
15601 /* Handle common .set/.module options. Return status indicating option
15604 static enum code_option_type
15605 parse_code_option (char * name)
15607 bfd_boolean isa_set = FALSE;
15608 const struct mips_ase *ase;
15610 if (strncmp (name, "at=", 3) == 0)
15612 char *s = name + 3;
15614 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15615 as_bad (_("unrecognized register name `%s'"), s);
15617 else if (strcmp (name, "at") == 0)
15618 mips_opts.at = ATREG;
15619 else if (strcmp (name, "noat") == 0)
15620 mips_opts.at = ZERO;
15621 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15622 mips_opts.nomove = 0;
15623 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15624 mips_opts.nomove = 1;
15625 else if (strcmp (name, "bopt") == 0)
15626 mips_opts.nobopt = 0;
15627 else if (strcmp (name, "nobopt") == 0)
15628 mips_opts.nobopt = 1;
15629 else if (strcmp (name, "gp=32") == 0)
15631 else if (strcmp (name, "gp=64") == 0)
15633 else if (strcmp (name, "fp=32") == 0)
15635 else if (strcmp (name, "fp=xx") == 0)
15637 else if (strcmp (name, "fp=64") == 0)
15639 else if (strcmp (name, "softfloat") == 0)
15640 mips_opts.soft_float = 1;
15641 else if (strcmp (name, "hardfloat") == 0)
15642 mips_opts.soft_float = 0;
15643 else if (strcmp (name, "singlefloat") == 0)
15644 mips_opts.single_float = 1;
15645 else if (strcmp (name, "doublefloat") == 0)
15646 mips_opts.single_float = 0;
15647 else if (strcmp (name, "nooddspreg") == 0)
15648 mips_opts.oddspreg = 0;
15649 else if (strcmp (name, "oddspreg") == 0)
15650 mips_opts.oddspreg = 1;
15651 else if (strcmp (name, "mips16") == 0
15652 || strcmp (name, "MIPS-16") == 0)
15653 mips_opts.mips16 = 1;
15654 else if (strcmp (name, "nomips16") == 0
15655 || strcmp (name, "noMIPS-16") == 0)
15656 mips_opts.mips16 = 0;
15657 else if (strcmp (name, "micromips") == 0)
15658 mips_opts.micromips = 1;
15659 else if (strcmp (name, "nomicromips") == 0)
15660 mips_opts.micromips = 0;
15661 else if (name[0] == 'n'
15663 && (ase = mips_lookup_ase (name + 2)))
15664 mips_set_ase (ase, &mips_opts, FALSE);
15665 else if ((ase = mips_lookup_ase (name)))
15666 mips_set_ase (ase, &mips_opts, TRUE);
15667 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15669 /* Permit the user to change the ISA and architecture on the fly.
15670 Needless to say, misuse can cause serious problems. */
15671 if (strncmp (name, "arch=", 5) == 0)
15673 const struct mips_cpu_info *p;
15675 p = mips_parse_cpu ("internal use", name + 5);
15677 as_bad (_("unknown architecture %s"), name + 5);
15680 mips_opts.arch = p->cpu;
15681 mips_opts.isa = p->isa;
15685 else if (strncmp (name, "mips", 4) == 0)
15687 const struct mips_cpu_info *p;
15689 p = mips_parse_cpu ("internal use", name);
15691 as_bad (_("unknown ISA level %s"), name + 4);
15694 mips_opts.arch = p->cpu;
15695 mips_opts.isa = p->isa;
15700 as_bad (_("unknown ISA or architecture %s"), name);
15702 else if (strcmp (name, "autoextend") == 0)
15703 mips_opts.noautoextend = 0;
15704 else if (strcmp (name, "noautoextend") == 0)
15705 mips_opts.noautoextend = 1;
15706 else if (strcmp (name, "insn32") == 0)
15707 mips_opts.insn32 = TRUE;
15708 else if (strcmp (name, "noinsn32") == 0)
15709 mips_opts.insn32 = FALSE;
15710 else if (strcmp (name, "sym32") == 0)
15711 mips_opts.sym32 = TRUE;
15712 else if (strcmp (name, "nosym32") == 0)
15713 mips_opts.sym32 = FALSE;
15715 return OPTION_TYPE_BAD;
15717 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
15720 /* Handle the .set pseudo-op. */
15723 s_mipsset (int x ATTRIBUTE_UNUSED)
15725 enum code_option_type type = OPTION_TYPE_NORMAL;
15726 char *name = input_line_pointer, ch;
15728 file_mips_check_options ();
15730 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15731 ++input_line_pointer;
15732 ch = *input_line_pointer;
15733 *input_line_pointer = '\0';
15735 if (strchr (name, ','))
15737 /* Generic ".set" directive; use the generic handler. */
15738 *input_line_pointer = ch;
15739 input_line_pointer = name;
15744 if (strcmp (name, "reorder") == 0)
15746 if (mips_opts.noreorder)
15749 else if (strcmp (name, "noreorder") == 0)
15751 if (!mips_opts.noreorder)
15752 start_noreorder ();
15754 else if (strcmp (name, "macro") == 0)
15755 mips_opts.warn_about_macros = 0;
15756 else if (strcmp (name, "nomacro") == 0)
15758 if (mips_opts.noreorder == 0)
15759 as_bad (_("`noreorder' must be set before `nomacro'"));
15760 mips_opts.warn_about_macros = 1;
15762 else if (strcmp (name, "gp=default") == 0)
15763 mips_opts.gp = file_mips_opts.gp;
15764 else if (strcmp (name, "fp=default") == 0)
15765 mips_opts.fp = file_mips_opts.fp;
15766 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15768 mips_opts.isa = file_mips_opts.isa;
15769 mips_opts.arch = file_mips_opts.arch;
15770 mips_opts.gp = file_mips_opts.gp;
15771 mips_opts.fp = file_mips_opts.fp;
15773 else if (strcmp (name, "push") == 0)
15775 struct mips_option_stack *s;
15777 s = XNEW (struct mips_option_stack);
15778 s->next = mips_opts_stack;
15779 s->options = mips_opts;
15780 mips_opts_stack = s;
15782 else if (strcmp (name, "pop") == 0)
15784 struct mips_option_stack *s;
15786 s = mips_opts_stack;
15788 as_bad (_(".set pop with no .set push"));
15791 /* If we're changing the reorder mode we need to handle
15792 delay slots correctly. */
15793 if (s->options.noreorder && ! mips_opts.noreorder)
15794 start_noreorder ();
15795 else if (! s->options.noreorder && mips_opts.noreorder)
15798 mips_opts = s->options;
15799 mips_opts_stack = s->next;
15805 type = parse_code_option (name);
15806 if (type == OPTION_TYPE_BAD)
15807 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15810 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15811 registers based on what is supported by the arch/cpu. */
15812 if (type == OPTION_TYPE_ISA)
15814 switch (mips_opts.isa)
15819 /* MIPS I cannot support FPXX. */
15821 /* fall-through. */
15828 if (mips_opts.fp != 0)
15844 if (mips_opts.fp != 0)
15846 if (mips_opts.arch == CPU_R5900)
15853 as_bad (_("unknown ISA level %s"), name + 4);
15858 mips_check_options (&mips_opts, FALSE);
15860 mips_check_isa_supports_ases ();
15861 *input_line_pointer = ch;
15862 demand_empty_rest_of_line ();
15865 /* Handle the .module pseudo-op. */
15868 s_module (int ignore ATTRIBUTE_UNUSED)
15870 char *name = input_line_pointer, ch;
15872 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15873 ++input_line_pointer;
15874 ch = *input_line_pointer;
15875 *input_line_pointer = '\0';
15877 if (!file_mips_opts_checked)
15879 if (parse_code_option (name) == OPTION_TYPE_BAD)
15880 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15882 /* Update module level settings from mips_opts. */
15883 file_mips_opts = mips_opts;
15886 as_bad (_(".module is not permitted after generating code"));
15888 *input_line_pointer = ch;
15889 demand_empty_rest_of_line ();
15892 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15893 .option pic2. It means to generate SVR4 PIC calls. */
15896 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15898 mips_pic = SVR4_PIC;
15899 mips_abicalls = TRUE;
15901 if (g_switch_seen && g_switch_value != 0)
15902 as_warn (_("-G may not be used with SVR4 PIC code"));
15903 g_switch_value = 0;
15905 bfd_set_gp_size (stdoutput, 0);
15906 demand_empty_rest_of_line ();
15909 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15910 PIC code. It sets the $gp register for the function based on the
15911 function address, which is in the register named in the argument.
15912 This uses a relocation against _gp_disp, which is handled specially
15913 by the linker. The result is:
15914 lui $gp,%hi(_gp_disp)
15915 addiu $gp,$gp,%lo(_gp_disp)
15916 addu $gp,$gp,.cpload argument
15917 The .cpload argument is normally $25 == $t9.
15919 The -mno-shared option changes this to:
15920 lui $gp,%hi(__gnu_local_gp)
15921 addiu $gp,$gp,%lo(__gnu_local_gp)
15922 and the argument is ignored. This saves an instruction, but the
15923 resulting code is not position independent; it uses an absolute
15924 address for __gnu_local_gp. Thus code assembled with -mno-shared
15925 can go into an ordinary executable, but not into a shared library. */
15928 s_cpload (int ignore ATTRIBUTE_UNUSED)
15934 file_mips_check_options ();
15936 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15937 .cpload is ignored. */
15938 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15944 if (mips_opts.mips16)
15946 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15947 ignore_rest_of_line ();
15951 /* .cpload should be in a .set noreorder section. */
15952 if (mips_opts.noreorder == 0)
15953 as_warn (_(".cpload not in noreorder section"));
15955 reg = tc_get_register (0);
15957 /* If we need to produce a 64-bit address, we are better off using
15958 the default instruction sequence. */
15959 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15961 ex.X_op = O_symbol;
15962 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15964 ex.X_op_symbol = NULL;
15965 ex.X_add_number = 0;
15967 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15968 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15970 mips_mark_labels ();
15971 mips_assembling_insn = TRUE;
15974 macro_build_lui (&ex, mips_gp_register);
15975 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15976 mips_gp_register, BFD_RELOC_LO16);
15978 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15979 mips_gp_register, reg);
15982 mips_assembling_insn = FALSE;
15983 demand_empty_rest_of_line ();
15986 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15987 .cpsetup $reg1, offset|$reg2, label
15989 If offset is given, this results in:
15990 sd $gp, offset($sp)
15991 lui $gp, %hi(%neg(%gp_rel(label)))
15992 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15993 daddu $gp, $gp, $reg1
15995 If $reg2 is given, this results in:
15997 lui $gp, %hi(%neg(%gp_rel(label)))
15998 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15999 daddu $gp, $gp, $reg1
16000 $reg1 is normally $25 == $t9.
16002 The -mno-shared option replaces the last three instructions with
16004 addiu $gp,$gp,%lo(_gp) */
16007 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16009 expressionS ex_off;
16010 expressionS ex_sym;
16013 file_mips_check_options ();
16015 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16016 We also need NewABI support. */
16017 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16023 if (mips_opts.mips16)
16025 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16026 ignore_rest_of_line ();
16030 reg1 = tc_get_register (0);
16031 SKIP_WHITESPACE ();
16032 if (*input_line_pointer != ',')
16034 as_bad (_("missing argument separator ',' for .cpsetup"));
16038 ++input_line_pointer;
16039 SKIP_WHITESPACE ();
16040 if (*input_line_pointer == '$')
16042 mips_cpreturn_register = tc_get_register (0);
16043 mips_cpreturn_offset = -1;
16047 mips_cpreturn_offset = get_absolute_expression ();
16048 mips_cpreturn_register = -1;
16050 SKIP_WHITESPACE ();
16051 if (*input_line_pointer != ',')
16053 as_bad (_("missing argument separator ',' for .cpsetup"));
16057 ++input_line_pointer;
16058 SKIP_WHITESPACE ();
16059 expression (&ex_sym);
16061 mips_mark_labels ();
16062 mips_assembling_insn = TRUE;
16065 if (mips_cpreturn_register == -1)
16067 ex_off.X_op = O_constant;
16068 ex_off.X_add_symbol = NULL;
16069 ex_off.X_op_symbol = NULL;
16070 ex_off.X_add_number = mips_cpreturn_offset;
16072 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16073 BFD_RELOC_LO16, SP);
16076 move_register (mips_cpreturn_register, mips_gp_register);
16078 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16080 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16081 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16084 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16085 mips_gp_register, -1, BFD_RELOC_GPREL16,
16086 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16089 mips_gp_register, reg1);
16095 ex.X_op = O_symbol;
16096 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16097 ex.X_op_symbol = NULL;
16098 ex.X_add_number = 0;
16100 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16101 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16103 macro_build_lui (&ex, mips_gp_register);
16104 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16105 mips_gp_register, BFD_RELOC_LO16);
16110 mips_assembling_insn = FALSE;
16111 demand_empty_rest_of_line ();
16115 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16117 file_mips_check_options ();
16119 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16120 .cplocal is ignored. */
16121 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16127 if (mips_opts.mips16)
16129 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16130 ignore_rest_of_line ();
16134 mips_gp_register = tc_get_register (0);
16135 demand_empty_rest_of_line ();
16138 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16139 offset from $sp. The offset is remembered, and after making a PIC
16140 call $gp is restored from that location. */
16143 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16147 file_mips_check_options ();
16149 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16150 .cprestore is ignored. */
16151 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16157 if (mips_opts.mips16)
16159 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16160 ignore_rest_of_line ();
16164 mips_cprestore_offset = get_absolute_expression ();
16165 mips_cprestore_valid = 1;
16167 ex.X_op = O_constant;
16168 ex.X_add_symbol = NULL;
16169 ex.X_op_symbol = NULL;
16170 ex.X_add_number = mips_cprestore_offset;
16172 mips_mark_labels ();
16173 mips_assembling_insn = TRUE;
16176 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16177 SP, HAVE_64BIT_ADDRESSES);
16180 mips_assembling_insn = FALSE;
16181 demand_empty_rest_of_line ();
16184 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16185 was given in the preceding .cpsetup, it results in:
16186 ld $gp, offset($sp)
16188 If a register $reg2 was given there, it results in:
16189 or $gp, $reg2, $0 */
16192 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16196 file_mips_check_options ();
16198 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16199 We also need NewABI support. */
16200 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16206 if (mips_opts.mips16)
16208 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16209 ignore_rest_of_line ();
16213 mips_mark_labels ();
16214 mips_assembling_insn = TRUE;
16217 if (mips_cpreturn_register == -1)
16219 ex.X_op = O_constant;
16220 ex.X_add_symbol = NULL;
16221 ex.X_op_symbol = NULL;
16222 ex.X_add_number = mips_cpreturn_offset;
16224 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16227 move_register (mips_gp_register, mips_cpreturn_register);
16231 mips_assembling_insn = FALSE;
16232 demand_empty_rest_of_line ();
16235 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16236 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16237 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16238 debug information or MIPS16 TLS. */
16241 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16242 bfd_reloc_code_real_type rtype)
16249 if (ex.X_op != O_symbol)
16251 as_bad (_("unsupported use of %s"), dirstr);
16252 ignore_rest_of_line ();
16255 p = frag_more (bytes);
16256 md_number_to_chars (p, 0, bytes);
16257 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16258 demand_empty_rest_of_line ();
16259 mips_clear_insn_labels ();
16262 /* Handle .dtprelword. */
16265 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16267 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16270 /* Handle .dtpreldword. */
16273 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16275 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16278 /* Handle .tprelword. */
16281 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16283 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16286 /* Handle .tpreldword. */
16289 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16291 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16294 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16295 code. It sets the offset to use in gp_rel relocations. */
16298 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16300 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16301 We also need NewABI support. */
16302 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16308 mips_gprel_offset = get_absolute_expression ();
16310 demand_empty_rest_of_line ();
16313 /* Handle the .gpword pseudo-op. This is used when generating PIC
16314 code. It generates a 32 bit GP relative reloc. */
16317 s_gpword (int ignore ATTRIBUTE_UNUSED)
16319 segment_info_type *si;
16320 struct insn_label_list *l;
16324 /* When not generating PIC code, this is treated as .word. */
16325 if (mips_pic != SVR4_PIC)
16331 si = seg_info (now_seg);
16332 l = si->label_list;
16333 mips_emit_delays ();
16335 mips_align (2, 0, l);
16338 mips_clear_insn_labels ();
16340 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16342 as_bad (_("unsupported use of .gpword"));
16343 ignore_rest_of_line ();
16347 md_number_to_chars (p, 0, 4);
16348 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16349 BFD_RELOC_GPREL32);
16351 demand_empty_rest_of_line ();
16355 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16357 segment_info_type *si;
16358 struct insn_label_list *l;
16362 /* When not generating PIC code, this is treated as .dword. */
16363 if (mips_pic != SVR4_PIC)
16369 si = seg_info (now_seg);
16370 l = si->label_list;
16371 mips_emit_delays ();
16373 mips_align (3, 0, l);
16376 mips_clear_insn_labels ();
16378 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16380 as_bad (_("unsupported use of .gpdword"));
16381 ignore_rest_of_line ();
16385 md_number_to_chars (p, 0, 8);
16386 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16387 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16389 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16390 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16391 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16393 demand_empty_rest_of_line ();
16396 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16397 tables. It generates a R_MIPS_EH reloc. */
16400 s_ehword (int ignore ATTRIBUTE_UNUSED)
16405 mips_emit_delays ();
16408 mips_clear_insn_labels ();
16410 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16412 as_bad (_("unsupported use of .ehword"));
16413 ignore_rest_of_line ();
16417 md_number_to_chars (p, 0, 4);
16418 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16419 BFD_RELOC_32_PCREL);
16421 demand_empty_rest_of_line ();
16424 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16425 tables in SVR4 PIC code. */
16428 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16432 file_mips_check_options ();
16434 /* This is ignored when not generating SVR4 PIC code. */
16435 if (mips_pic != SVR4_PIC)
16441 mips_mark_labels ();
16442 mips_assembling_insn = TRUE;
16444 /* Add $gp to the register named as an argument. */
16446 reg = tc_get_register (0);
16447 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16450 mips_assembling_insn = FALSE;
16451 demand_empty_rest_of_line ();
16454 /* Handle the .insn pseudo-op. This marks instruction labels in
16455 mips16/micromips mode. This permits the linker to handle them specially,
16456 such as generating jalx instructions when needed. We also make
16457 them odd for the duration of the assembly, in order to generate the
16458 right sort of code. We will make them even in the adjust_symtab
16459 routine, while leaving them marked. This is convenient for the
16460 debugger and the disassembler. The linker knows to make them odd
16464 s_insn (int ignore ATTRIBUTE_UNUSED)
16466 file_mips_check_options ();
16467 file_ase_mips16 |= mips_opts.mips16;
16468 file_ase_micromips |= mips_opts.micromips;
16470 mips_mark_labels ();
16472 demand_empty_rest_of_line ();
16475 /* Handle the .nan pseudo-op. */
16478 s_nan (int ignore ATTRIBUTE_UNUSED)
16480 static const char str_legacy[] = "legacy";
16481 static const char str_2008[] = "2008";
16484 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16486 if (i == sizeof (str_2008) - 1
16487 && memcmp (input_line_pointer, str_2008, i) == 0)
16489 else if (i == sizeof (str_legacy) - 1
16490 && memcmp (input_line_pointer, str_legacy, i) == 0)
16492 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16495 as_bad (_("`%s' does not support legacy NaN"),
16496 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16499 as_bad (_("bad .nan directive"));
16501 input_line_pointer += i;
16502 demand_empty_rest_of_line ();
16505 /* Handle a .stab[snd] directive. Ideally these directives would be
16506 implemented in a transparent way, so that removing them would not
16507 have any effect on the generated instructions. However, s_stab
16508 internally changes the section, so in practice we need to decide
16509 now whether the preceding label marks compressed code. We do not
16510 support changing the compression mode of a label after a .stab*
16511 directive, such as in:
16517 so the current mode wins. */
16520 s_mips_stab (int type)
16522 mips_mark_labels ();
16526 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16529 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16536 c = get_symbol_name (&name);
16537 symbolP = symbol_find_or_make (name);
16538 S_SET_WEAK (symbolP);
16539 *input_line_pointer = c;
16541 SKIP_WHITESPACE_AFTER_NAME ();
16543 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16545 if (S_IS_DEFINED (symbolP))
16547 as_bad (_("ignoring attempt to redefine symbol %s"),
16548 S_GET_NAME (symbolP));
16549 ignore_rest_of_line ();
16553 if (*input_line_pointer == ',')
16555 ++input_line_pointer;
16556 SKIP_WHITESPACE ();
16560 if (exp.X_op != O_symbol)
16562 as_bad (_("bad .weakext directive"));
16563 ignore_rest_of_line ();
16566 symbol_set_value_expression (symbolP, &exp);
16569 demand_empty_rest_of_line ();
16572 /* Parse a register string into a number. Called from the ECOFF code
16573 to parse .frame. The argument is non-zero if this is the frame
16574 register, so that we can record it in mips_frame_reg. */
16577 tc_get_register (int frame)
16581 SKIP_WHITESPACE ();
16582 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16586 mips_frame_reg = reg != 0 ? reg : SP;
16587 mips_frame_reg_valid = 1;
16588 mips_cprestore_valid = 0;
16594 md_section_align (asection *seg, valueT addr)
16596 int align = bfd_get_section_alignment (stdoutput, seg);
16598 /* We don't need to align ELF sections to the full alignment.
16599 However, Irix 5 may prefer that we align them at least to a 16
16600 byte boundary. We don't bother to align the sections if we
16601 are targeted for an embedded system. */
16602 if (strncmp (TARGET_OS, "elf", 3) == 0)
16607 return ((addr + (1 << align) - 1) & -(1 << align));
16610 /* Utility routine, called from above as well. If called while the
16611 input file is still being read, it's only an approximation. (For
16612 example, a symbol may later become defined which appeared to be
16613 undefined earlier.) */
16616 nopic_need_relax (symbolS *sym, int before_relaxing)
16621 if (g_switch_value > 0)
16623 const char *symname;
16626 /* Find out whether this symbol can be referenced off the $gp
16627 register. It can be if it is smaller than the -G size or if
16628 it is in the .sdata or .sbss section. Certain symbols can
16629 not be referenced off the $gp, although it appears as though
16631 symname = S_GET_NAME (sym);
16632 if (symname != (const char *) NULL
16633 && (strcmp (symname, "eprol") == 0
16634 || strcmp (symname, "etext") == 0
16635 || strcmp (symname, "_gp") == 0
16636 || strcmp (symname, "edata") == 0
16637 || strcmp (symname, "_fbss") == 0
16638 || strcmp (symname, "_fdata") == 0
16639 || strcmp (symname, "_ftext") == 0
16640 || strcmp (symname, "end") == 0
16641 || strcmp (symname, "_gp_disp") == 0))
16643 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16645 #ifndef NO_ECOFF_DEBUGGING
16646 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16647 && (symbol_get_obj (sym)->ecoff_extern_size
16648 <= g_switch_value))
16650 /* We must defer this decision until after the whole
16651 file has been read, since there might be a .extern
16652 after the first use of this symbol. */
16653 || (before_relaxing
16654 #ifndef NO_ECOFF_DEBUGGING
16655 && symbol_get_obj (sym)->ecoff_extern_size == 0
16657 && S_GET_VALUE (sym) == 0)
16658 || (S_GET_VALUE (sym) != 0
16659 && S_GET_VALUE (sym) <= g_switch_value)))
16663 const char *segname;
16665 segname = segment_name (S_GET_SEGMENT (sym));
16666 gas_assert (strcmp (segname, ".lit8") != 0
16667 && strcmp (segname, ".lit4") != 0);
16668 change = (strcmp (segname, ".sdata") != 0
16669 && strcmp (segname, ".sbss") != 0
16670 && strncmp (segname, ".sdata.", 7) != 0
16671 && strncmp (segname, ".sbss.", 6) != 0
16672 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16673 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16678 /* We are not optimizing for the $gp register. */
16683 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16686 pic_need_relax (symbolS *sym, asection *segtype)
16690 /* Handle the case of a symbol equated to another symbol. */
16691 while (symbol_equated_reloc_p (sym))
16695 /* It's possible to get a loop here in a badly written program. */
16696 n = symbol_get_value_expression (sym)->X_add_symbol;
16702 if (symbol_section_p (sym))
16705 symsec = S_GET_SEGMENT (sym);
16707 /* This must duplicate the test in adjust_reloc_syms. */
16708 return (!bfd_is_und_section (symsec)
16709 && !bfd_is_abs_section (symsec)
16710 && !bfd_is_com_section (symsec)
16711 && !s_is_linkonce (sym, segtype)
16712 /* A global or weak symbol is treated as external. */
16713 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16717 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16718 extended opcode. SEC is the section the frag is in. */
16721 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16724 const struct mips_int_operand *operand;
16729 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16731 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16734 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16735 operand = mips16_immed_operand (type, FALSE);
16737 sym_frag = symbol_get_frag (fragp->fr_symbol);
16738 val = S_GET_VALUE (fragp->fr_symbol);
16739 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16741 if (operand->root.type == OP_PCREL)
16743 const struct mips_pcrel_operand *pcrel_op;
16747 /* We won't have the section when we are called from
16748 mips_relax_frag. However, we will always have been called
16749 from md_estimate_size_before_relax first. If this is a
16750 branch to a different section, we mark it as such. If SEC is
16751 NULL, and the frag is not marked, then it must be a branch to
16752 the same section. */
16753 pcrel_op = (const struct mips_pcrel_operand *) operand;
16756 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16761 /* Must have been called from md_estimate_size_before_relax. */
16764 fragp->fr_subtype =
16765 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16767 /* FIXME: We should support this, and let the linker
16768 catch branches and loads that are out of range. */
16769 as_bad_where (fragp->fr_file, fragp->fr_line,
16770 _("unsupported PC relative reference to different section"));
16774 if (fragp != sym_frag && sym_frag->fr_address == 0)
16775 /* Assume non-extended on the first relaxation pass.
16776 The address we have calculated will be bogus if this is
16777 a forward branch to another frag, as the forward frag
16778 will have fr_address == 0. */
16782 /* In this case, we know for sure that the symbol fragment is in
16783 the same section. If the relax_marker of the symbol fragment
16784 differs from the relax_marker of this fragment, we have not
16785 yet adjusted the symbol fragment fr_address. We want to add
16786 in STRETCH in order to get a better estimate of the address.
16787 This particularly matters because of the shift bits. */
16789 && sym_frag->relax_marker != fragp->relax_marker)
16793 /* Adjust stretch for any alignment frag. Note that if have
16794 been expanding the earlier code, the symbol may be
16795 defined in what appears to be an earlier frag. FIXME:
16796 This doesn't handle the fr_subtype field, which specifies
16797 a maximum number of bytes to skip when doing an
16799 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16801 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16804 stretch = - ((- stretch)
16805 & ~ ((1 << (int) f->fr_offset) - 1));
16807 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16816 addr = fragp->fr_address + fragp->fr_fix;
16818 /* The base address rules are complicated. The base address of
16819 a branch is the following instruction. The base address of a
16820 PC relative load or add is the instruction itself, but if it
16821 is in a delay slot (in which case it can not be extended) use
16822 the address of the instruction whose delay slot it is in. */
16823 if (pcrel_op->include_isa_bit)
16827 /* If we are currently assuming that this frag should be
16828 extended, then, the current address is two bytes
16830 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16833 /* Ignore the low bit in the target, since it will be set
16834 for a text label. */
16837 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16839 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16842 val -= addr & -(1 << pcrel_op->align_log2);
16844 /* If any of the shifted bits are set, we must use an extended
16845 opcode. If the address depends on the size of this
16846 instruction, this can lead to a loop, so we arrange to always
16847 use an extended opcode. We only check this when we are in
16848 the main relaxation loop, when SEC is NULL. */
16849 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16851 fragp->fr_subtype =
16852 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16856 /* If we are about to mark a frag as extended because the value
16857 is precisely the next value above maxtiny, then there is a
16858 chance of an infinite loop as in the following code:
16863 In this case when the la is extended, foo is 0x3fc bytes
16864 away, so the la can be shrunk, but then foo is 0x400 away, so
16865 the la must be extended. To avoid this loop, we mark the
16866 frag as extended if it was small, and is about to become
16867 extended with the next value above maxtiny. */
16868 maxtiny = mips_int_operand_max (operand);
16869 if (val == maxtiny + (1 << operand->shift)
16870 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16873 fragp->fr_subtype =
16874 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16878 else if (symsec != absolute_section && sec != NULL)
16879 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16881 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16884 /* Compute the length of a branch sequence, and adjust the
16885 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16886 worst-case length is computed, with UPDATE being used to indicate
16887 whether an unconditional (-1), branch-likely (+1) or regular (0)
16888 branch is to be computed. */
16890 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16892 bfd_boolean toofar;
16896 && S_IS_DEFINED (fragp->fr_symbol)
16897 && !S_IS_WEAK (fragp->fr_symbol)
16898 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16903 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16905 addr = fragp->fr_address + fragp->fr_fix + 4;
16909 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16912 /* If the symbol is not defined or it's in a different segment,
16913 we emit the long sequence. */
16916 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16918 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16919 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16920 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16921 RELAX_BRANCH_LINK (fragp->fr_subtype),
16927 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16930 if (mips_pic != NO_PIC)
16932 /* Additional space for PIC loading of target address. */
16934 if (mips_opts.isa == ISA_MIPS1)
16935 /* Additional space for $at-stabilizing nop. */
16939 /* If branch is conditional. */
16940 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16947 /* Compute the length of a branch sequence, and adjust the
16948 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16949 worst-case length is computed, with UPDATE being used to indicate
16950 whether an unconditional (-1), or regular (0) branch is to be
16954 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16956 bfd_boolean toofar;
16960 && S_IS_DEFINED (fragp->fr_symbol)
16961 && !S_IS_WEAK (fragp->fr_symbol)
16962 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16967 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16968 /* Ignore the low bit in the target, since it will be set
16969 for a text label. */
16970 if ((val & 1) != 0)
16973 addr = fragp->fr_address + fragp->fr_fix + 4;
16977 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16980 /* If the symbol is not defined or it's in a different segment,
16981 we emit the long sequence. */
16984 if (fragp && update
16985 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16986 fragp->fr_subtype = (toofar
16987 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16988 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16993 bfd_boolean compact_known = fragp != NULL;
16994 bfd_boolean compact = FALSE;
16995 bfd_boolean uncond;
16998 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17000 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17002 uncond = update < 0;
17004 /* If label is out of range, we turn branch <br>:
17006 <br> label # 4 bytes
17012 nop # 2 bytes if compact && !PIC
17015 if (mips_pic == NO_PIC && (!compact_known || compact))
17018 /* If assembling PIC code, we further turn:
17024 lw/ld at, %got(label)(gp) # 4 bytes
17025 d/addiu at, %lo(label) # 4 bytes
17028 if (mips_pic != NO_PIC)
17031 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17033 <brneg> 0f # 4 bytes
17034 nop # 2 bytes if !compact
17037 length += (compact_known && compact) ? 4 : 6;
17043 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17044 bit accordingly. */
17047 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17049 bfd_boolean toofar;
17052 && S_IS_DEFINED (fragp->fr_symbol)
17053 && !S_IS_WEAK (fragp->fr_symbol)
17054 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17060 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17061 /* Ignore the low bit in the target, since it will be set
17062 for a text label. */
17063 if ((val & 1) != 0)
17066 /* Assume this is a 2-byte branch. */
17067 addr = fragp->fr_address + fragp->fr_fix + 2;
17069 /* We try to avoid the infinite loop by not adding 2 more bytes for
17074 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17076 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17077 else if (type == 'E')
17078 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17083 /* If the symbol is not defined or it's in a different segment,
17084 we emit a normal 32-bit branch. */
17087 if (fragp && update
17088 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17090 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17091 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17099 /* Estimate the size of a frag before relaxing. Unless this is the
17100 mips16, we are not really relaxing here, and the final size is
17101 encoded in the subtype information. For the mips16, we have to
17102 decide whether we are using an extended opcode or not. */
17105 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17109 if (RELAX_BRANCH_P (fragp->fr_subtype))
17112 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17114 return fragp->fr_var;
17117 if (RELAX_MIPS16_P (fragp->fr_subtype))
17118 /* We don't want to modify the EXTENDED bit here; it might get us
17119 into infinite loops. We change it only in mips_relax_frag(). */
17120 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17122 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17126 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17127 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17128 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17129 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17130 fragp->fr_var = length;
17135 if (mips_pic == NO_PIC)
17136 change = nopic_need_relax (fragp->fr_symbol, 0);
17137 else if (mips_pic == SVR4_PIC)
17138 change = pic_need_relax (fragp->fr_symbol, segtype);
17139 else if (mips_pic == VXWORKS_PIC)
17140 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17147 fragp->fr_subtype |= RELAX_USE_SECOND;
17148 return -RELAX_FIRST (fragp->fr_subtype);
17151 return -RELAX_SECOND (fragp->fr_subtype);
17154 /* This is called to see whether a reloc against a defined symbol
17155 should be converted into a reloc against a section. */
17158 mips_fix_adjustable (fixS *fixp)
17160 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17161 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17164 if (fixp->fx_addsy == NULL)
17167 /* Allow relocs used for EH tables. */
17168 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17171 /* If symbol SYM is in a mergeable section, relocations of the form
17172 SYM + 0 can usually be made section-relative. The mergeable data
17173 is then identified by the section offset rather than by the symbol.
17175 However, if we're generating REL LO16 relocations, the offset is split
17176 between the LO16 and parterning high part relocation. The linker will
17177 need to recalculate the complete offset in order to correctly identify
17180 The linker has traditionally not looked for the parterning high part
17181 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17182 placed anywhere. Rather than break backwards compatibility by changing
17183 this, it seems better not to force the issue, and instead keep the
17184 original symbol. This will work with either linker behavior. */
17185 if ((lo16_reloc_p (fixp->fx_r_type)
17186 || reloc_needs_lo_p (fixp->fx_r_type))
17187 && HAVE_IN_PLACE_ADDENDS
17188 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17191 /* There is no place to store an in-place offset for JALR relocations. */
17192 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17195 /* Likewise an in-range offset of limited PC-relative relocations may
17196 overflow the in-place relocatable field if recalculated against the
17197 start address of the symbol's containing section.
17199 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17200 section relative to allow linker relaxations to be performed later on. */
17201 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17202 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17205 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17206 to a floating-point stub. The same is true for non-R_MIPS16_26
17207 relocations against MIPS16 functions; in this case, the stub becomes
17208 the function's canonical address.
17210 Floating-point stubs are stored in unique .mips16.call.* or
17211 .mips16.fn.* sections. If a stub T for function F is in section S,
17212 the first relocation in section S must be against F; this is how the
17213 linker determines the target function. All relocations that might
17214 resolve to T must also be against F. We therefore have the following
17215 restrictions, which are given in an intentionally-redundant way:
17217 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17220 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17221 if that stub might be used.
17223 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17226 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17227 that stub might be used.
17229 There is a further restriction:
17231 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17232 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17233 R_MIPS_PC21_S2, R_MIPS_PC16, R_MICROMIPS_PC16_S1,
17234 R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) against MIPS16 or
17235 microMIPS symbols because we need to keep the MIPS16 or
17236 microMIPS symbol for the purpose of mode mismatch detection
17237 and JAL to JALX instruction conversion in the linker.
17239 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17240 against a MIPS16 symbol. We deal with (5) by additionally leaving
17241 alone any jump and branch relocations against a microMIPS symbol.
17243 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17244 relocation against some symbol R, no relocation against R may be
17245 reduced. (Note that this deals with (2) as well as (1) because
17246 relocations against global symbols will never be reduced on ELF
17247 targets.) This approach is a little simpler than trying to detect
17248 stub sections, and gives the "all or nothing" per-symbol consistency
17249 that we have for MIPS16 symbols. */
17250 if (fixp->fx_subsy == NULL
17251 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17252 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17253 && (jmp_reloc_p (fixp->fx_r_type)
17254 || b_reloc_p (fixp->fx_r_type)))
17255 || *symbol_get_tc (fixp->fx_addsy)))
17261 /* Translate internal representation of relocation info to BFD target
17265 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17267 static arelent *retval[4];
17269 bfd_reloc_code_real_type code;
17271 memset (retval, 0, sizeof(retval));
17272 reloc = retval[0] = XCNEW (arelent);
17273 reloc->sym_ptr_ptr = XNEW (asymbol *);
17274 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17275 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17277 if (fixp->fx_pcrel)
17279 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17280 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17281 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17282 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17283 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17284 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17285 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17286 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17287 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17288 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17289 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17291 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17292 Relocations want only the symbol offset. */
17293 switch (fixp->fx_r_type)
17295 case BFD_RELOC_MIPS_18_PCREL_S3:
17296 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
17299 reloc->addend = fixp->fx_addnumber + reloc->address;
17303 else if (HAVE_IN_PLACE_ADDENDS
17304 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17305 && (read_compressed_insn (fixp->fx_frag->fr_literal
17306 + fixp->fx_where, 4) >> 26) == 0x3c)
17308 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17309 addend accordingly. */
17310 reloc->addend = fixp->fx_addnumber >> 1;
17313 reloc->addend = fixp->fx_addnumber;
17315 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17316 entry to be used in the relocation's section offset. */
17317 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17319 reloc->address = reloc->addend;
17323 code = fixp->fx_r_type;
17325 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17326 if (reloc->howto == NULL)
17328 as_bad_where (fixp->fx_file, fixp->fx_line,
17329 _("cannot represent %s relocation in this object file"
17331 bfd_get_reloc_code_name (code));
17338 /* Relax a machine dependent frag. This returns the amount by which
17339 the current size of the frag should change. */
17342 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17344 if (RELAX_BRANCH_P (fragp->fr_subtype))
17346 offsetT old_var = fragp->fr_var;
17348 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17350 return fragp->fr_var - old_var;
17353 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17355 offsetT old_var = fragp->fr_var;
17356 offsetT new_var = 4;
17358 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17359 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17360 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17361 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17362 fragp->fr_var = new_var;
17364 return new_var - old_var;
17367 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17370 if (mips16_extended_frag (fragp, NULL, stretch))
17372 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17374 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17379 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17381 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17388 /* Convert a machine dependent frag. */
17391 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17393 if (RELAX_BRANCH_P (fragp->fr_subtype))
17396 unsigned long insn;
17400 buf = fragp->fr_literal + fragp->fr_fix;
17401 insn = read_insn (buf);
17403 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17405 /* We generate a fixup instead of applying it right now
17406 because, if there are linker relaxations, we're going to
17407 need the relocations. */
17408 exp.X_op = O_symbol;
17409 exp.X_add_symbol = fragp->fr_symbol;
17410 exp.X_add_number = fragp->fr_offset;
17412 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17413 BFD_RELOC_16_PCREL_S2);
17414 fixp->fx_file = fragp->fr_file;
17415 fixp->fx_line = fragp->fr_line;
17417 buf = write_insn (buf, insn);
17423 as_warn_where (fragp->fr_file, fragp->fr_line,
17424 _("relaxed out-of-range branch into a jump"));
17426 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17429 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17431 /* Reverse the branch. */
17432 switch ((insn >> 28) & 0xf)
17435 if ((insn & 0xff000000) == 0x47000000
17436 || (insn & 0xff600000) == 0x45600000)
17438 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17439 reversed by tweaking bit 23. */
17440 insn ^= 0x00800000;
17444 /* bc[0-3][tf]l? instructions can have the condition
17445 reversed by tweaking a single TF bit, and their
17446 opcodes all have 0x4???????. */
17447 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17448 insn ^= 0x00010000;
17453 /* bltz 0x04000000 bgez 0x04010000
17454 bltzal 0x04100000 bgezal 0x04110000 */
17455 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17456 insn ^= 0x00010000;
17460 /* beq 0x10000000 bne 0x14000000
17461 blez 0x18000000 bgtz 0x1c000000 */
17462 insn ^= 0x04000000;
17470 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17472 /* Clear the and-link bit. */
17473 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17475 /* bltzal 0x04100000 bgezal 0x04110000
17476 bltzall 0x04120000 bgezall 0x04130000 */
17477 insn &= ~0x00100000;
17480 /* Branch over the branch (if the branch was likely) or the
17481 full jump (not likely case). Compute the offset from the
17482 current instruction to branch to. */
17483 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17487 /* How many bytes in instructions we've already emitted? */
17488 i = buf - fragp->fr_literal - fragp->fr_fix;
17489 /* How many bytes in instructions from here to the end? */
17490 i = fragp->fr_var - i;
17492 /* Convert to instruction count. */
17494 /* Branch counts from the next instruction. */
17497 /* Branch over the jump. */
17498 buf = write_insn (buf, insn);
17501 buf = write_insn (buf, 0);
17503 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17505 /* beql $0, $0, 2f */
17507 /* Compute the PC offset from the current instruction to
17508 the end of the variable frag. */
17509 /* How many bytes in instructions we've already emitted? */
17510 i = buf - fragp->fr_literal - fragp->fr_fix;
17511 /* How many bytes in instructions from here to the end? */
17512 i = fragp->fr_var - i;
17513 /* Convert to instruction count. */
17515 /* Don't decrement i, because we want to branch over the
17519 buf = write_insn (buf, insn);
17520 buf = write_insn (buf, 0);
17524 if (mips_pic == NO_PIC)
17527 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17528 ? 0x0c000000 : 0x08000000);
17529 exp.X_op = O_symbol;
17530 exp.X_add_symbol = fragp->fr_symbol;
17531 exp.X_add_number = fragp->fr_offset;
17533 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17534 FALSE, BFD_RELOC_MIPS_JMP);
17535 fixp->fx_file = fragp->fr_file;
17536 fixp->fx_line = fragp->fr_line;
17538 buf = write_insn (buf, insn);
17542 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17544 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17545 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17546 insn |= at << OP_SH_RT;
17547 exp.X_op = O_symbol;
17548 exp.X_add_symbol = fragp->fr_symbol;
17549 exp.X_add_number = fragp->fr_offset;
17551 if (fragp->fr_offset)
17553 exp.X_add_symbol = make_expr_symbol (&exp);
17554 exp.X_add_number = 0;
17557 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17558 FALSE, BFD_RELOC_MIPS_GOT16);
17559 fixp->fx_file = fragp->fr_file;
17560 fixp->fx_line = fragp->fr_line;
17562 buf = write_insn (buf, insn);
17564 if (mips_opts.isa == ISA_MIPS1)
17566 buf = write_insn (buf, 0);
17568 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17569 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17570 insn |= at << OP_SH_RS | at << OP_SH_RT;
17572 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17573 FALSE, BFD_RELOC_LO16);
17574 fixp->fx_file = fragp->fr_file;
17575 fixp->fx_line = fragp->fr_line;
17577 buf = write_insn (buf, insn);
17580 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17584 insn |= at << OP_SH_RS;
17586 buf = write_insn (buf, insn);
17590 fragp->fr_fix += fragp->fr_var;
17591 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17595 /* Relax microMIPS branches. */
17596 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17598 char *buf = fragp->fr_literal + fragp->fr_fix;
17599 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17600 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17601 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17602 bfd_boolean short_ds;
17603 unsigned long insn;
17607 exp.X_op = O_symbol;
17608 exp.X_add_symbol = fragp->fr_symbol;
17609 exp.X_add_number = fragp->fr_offset;
17611 fragp->fr_fix += fragp->fr_var;
17613 /* Handle 16-bit branches that fit or are forced to fit. */
17614 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17616 /* We generate a fixup instead of applying it right now,
17617 because if there is linker relaxation, we're going to
17618 need the relocations. */
17620 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17621 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17622 else if (type == 'E')
17623 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17624 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17628 fixp->fx_file = fragp->fr_file;
17629 fixp->fx_line = fragp->fr_line;
17631 /* These relocations can have an addend that won't fit in
17633 fixp->fx_no_overflow = 1;
17638 /* Handle 32-bit branches that fit or are forced to fit. */
17639 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17640 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17642 /* We generate a fixup instead of applying it right now,
17643 because if there is linker relaxation, we're going to
17644 need the relocations. */
17645 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17646 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17647 fixp->fx_file = fragp->fr_file;
17648 fixp->fx_line = fragp->fr_line;
17654 /* Relax 16-bit branches to 32-bit branches. */
17657 insn = read_compressed_insn (buf, 2);
17659 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17660 insn = 0x94000000; /* beq */
17661 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17663 unsigned long regno;
17665 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17666 regno = micromips_to_32_reg_d_map [regno];
17667 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17668 insn |= regno << MICROMIPSOP_SH_RS;
17673 /* Nothing else to do, just write it out. */
17674 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17675 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17677 buf = write_compressed_insn (buf, insn, 4);
17678 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17683 insn = read_compressed_insn (buf, 4);
17685 /* Relax 32-bit branches to a sequence of instructions. */
17686 as_warn_where (fragp->fr_file, fragp->fr_line,
17687 _("relaxed out-of-range branch into a jump"));
17689 /* Set the short-delay-slot bit. */
17690 short_ds = al && (insn & 0x02000000) != 0;
17692 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17696 /* Reverse the branch. */
17697 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17698 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17699 insn ^= 0x20000000;
17700 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17701 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17702 || (insn & 0xffe00000) == 0x40800000 /* blez */
17703 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17704 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17705 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17706 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17707 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17708 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17709 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17710 insn ^= 0x00400000;
17711 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17712 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17713 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17714 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17715 insn ^= 0x00200000;
17716 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17718 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17720 insn ^= 0x00800000;
17726 /* Clear the and-link and short-delay-slot bits. */
17727 gas_assert ((insn & 0xfda00000) == 0x40200000);
17729 /* bltzal 0x40200000 bgezal 0x40600000 */
17730 /* bltzals 0x42200000 bgezals 0x42600000 */
17731 insn &= ~0x02200000;
17734 /* Make a label at the end for use with the branch. */
17735 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17736 micromips_label_inc ();
17737 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17740 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17741 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17742 fixp->fx_file = fragp->fr_file;
17743 fixp->fx_line = fragp->fr_line;
17745 /* Branch over the jump. */
17746 buf = write_compressed_insn (buf, insn, 4);
17749 buf = write_compressed_insn (buf, 0x0c00, 2);
17752 if (mips_pic == NO_PIC)
17754 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17756 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17757 insn = al ? jal : 0xd4000000;
17759 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17760 BFD_RELOC_MICROMIPS_JMP);
17761 fixp->fx_file = fragp->fr_file;
17762 fixp->fx_line = fragp->fr_line;
17764 buf = write_compressed_insn (buf, insn, 4);
17767 buf = write_compressed_insn (buf, 0x0c00, 2);
17771 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17772 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17773 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17775 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17776 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17777 insn |= at << MICROMIPSOP_SH_RT;
17779 if (exp.X_add_number)
17781 exp.X_add_symbol = make_expr_symbol (&exp);
17782 exp.X_add_number = 0;
17785 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17786 BFD_RELOC_MICROMIPS_GOT16);
17787 fixp->fx_file = fragp->fr_file;
17788 fixp->fx_line = fragp->fr_line;
17790 buf = write_compressed_insn (buf, insn, 4);
17792 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17793 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17794 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17796 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17797 BFD_RELOC_MICROMIPS_LO16);
17798 fixp->fx_file = fragp->fr_file;
17799 fixp->fx_line = fragp->fr_line;
17801 buf = write_compressed_insn (buf, insn, 4);
17803 /* jr/jrc/jalr/jalrs $at */
17804 insn = al ? jalr : jr;
17805 insn |= at << MICROMIPSOP_SH_MJ;
17807 buf = write_compressed_insn (buf, insn, 2);
17810 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17814 if (RELAX_MIPS16_P (fragp->fr_subtype))
17817 const struct mips_int_operand *operand;
17820 unsigned int user_length, length;
17821 unsigned long insn;
17824 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17825 operand = mips16_immed_operand (type, FALSE);
17827 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17828 val = resolve_symbol_value (fragp->fr_symbol);
17829 if (operand->root.type == OP_PCREL)
17831 const struct mips_pcrel_operand *pcrel_op;
17834 pcrel_op = (const struct mips_pcrel_operand *) operand;
17835 addr = fragp->fr_address + fragp->fr_fix;
17837 /* The rules for the base address of a PC relative reloc are
17838 complicated; see mips16_extended_frag. */
17839 if (pcrel_op->include_isa_bit)
17844 /* Ignore the low bit in the target, since it will be
17845 set for a text label. */
17848 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17850 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17853 addr &= -(1 << pcrel_op->align_log2);
17856 /* Make sure the section winds up with the alignment we have
17858 if (operand->shift > 0)
17859 record_alignment (asec, operand->shift);
17863 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17864 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17865 as_warn_where (fragp->fr_file, fragp->fr_line,
17866 _("extended instruction in delay slot"));
17868 buf = fragp->fr_literal + fragp->fr_fix;
17870 insn = read_compressed_insn (buf, 2);
17872 insn |= MIPS16_EXTEND;
17874 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17876 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17881 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17882 BFD_RELOC_UNUSED, val, user_length, &insn);
17884 length = (ext ? 4 : 2);
17885 gas_assert (mips16_opcode_length (insn) == length);
17886 write_compressed_insn (buf, insn, length);
17887 fragp->fr_fix += length;
17891 relax_substateT subtype = fragp->fr_subtype;
17892 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17893 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17897 first = RELAX_FIRST (subtype);
17898 second = RELAX_SECOND (subtype);
17899 fixp = (fixS *) fragp->fr_opcode;
17901 /* If the delay slot chosen does not match the size of the instruction,
17902 then emit a warning. */
17903 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17904 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17909 s = subtype & (RELAX_DELAY_SLOT_16BIT
17910 | RELAX_DELAY_SLOT_SIZE_FIRST
17911 | RELAX_DELAY_SLOT_SIZE_SECOND);
17912 msg = macro_warning (s);
17914 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17918 /* Possibly emit a warning if we've chosen the longer option. */
17919 if (use_second == second_longer)
17925 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17926 msg = macro_warning (s);
17928 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17932 /* Go through all the fixups for the first sequence. Disable them
17933 (by marking them as done) if we're going to use the second
17934 sequence instead. */
17936 && fixp->fx_frag == fragp
17937 && fixp->fx_where < fragp->fr_fix - second)
17939 if (subtype & RELAX_USE_SECOND)
17941 fixp = fixp->fx_next;
17944 /* Go through the fixups for the second sequence. Disable them if
17945 we're going to use the first sequence, otherwise adjust their
17946 addresses to account for the relaxation. */
17947 while (fixp && fixp->fx_frag == fragp)
17949 if (subtype & RELAX_USE_SECOND)
17950 fixp->fx_where -= first;
17953 fixp = fixp->fx_next;
17956 /* Now modify the frag contents. */
17957 if (subtype & RELAX_USE_SECOND)
17961 start = fragp->fr_literal + fragp->fr_fix - first - second;
17962 memmove (start, start + first, second);
17963 fragp->fr_fix -= first;
17966 fragp->fr_fix -= second;
17970 /* This function is called after the relocs have been generated.
17971 We've been storing mips16 text labels as odd. Here we convert them
17972 back to even for the convenience of the debugger. */
17975 mips_frob_file_after_relocs (void)
17978 unsigned int count, i;
17980 syms = bfd_get_outsymbols (stdoutput);
17981 count = bfd_get_symcount (stdoutput);
17982 for (i = 0; i < count; i++, syms++)
17983 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17984 && ((*syms)->value & 1) != 0)
17986 (*syms)->value &= ~1;
17987 /* If the symbol has an odd size, it was probably computed
17988 incorrectly, so adjust that as well. */
17989 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17990 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17994 /* This function is called whenever a label is defined, including fake
17995 labels instantiated off the dot special symbol. It is used when
17996 handling branch delays; if a branch has a label, we assume we cannot
17997 move it. This also bumps the value of the symbol by 1 in compressed
18001 mips_record_label (symbolS *sym)
18003 segment_info_type *si = seg_info (now_seg);
18004 struct insn_label_list *l;
18006 if (free_insn_labels == NULL)
18007 l = XNEW (struct insn_label_list);
18010 l = free_insn_labels;
18011 free_insn_labels = l->next;
18015 l->next = si->label_list;
18016 si->label_list = l;
18019 /* This function is called as tc_frob_label() whenever a label is defined
18020 and adds a DWARF-2 record we only want for true labels. */
18023 mips_define_label (symbolS *sym)
18025 mips_record_label (sym);
18026 dwarf2_emit_label (sym);
18029 /* This function is called by tc_new_dot_label whenever a new dot symbol
18033 mips_add_dot_label (symbolS *sym)
18035 mips_record_label (sym);
18036 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18037 mips_compressed_mark_label (sym);
18040 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18041 static unsigned int
18042 mips_convert_ase_flags (int ase)
18044 unsigned int ext_ases = 0;
18047 ext_ases |= AFL_ASE_DSP;
18048 if (ase & ASE_DSPR2)
18049 ext_ases |= AFL_ASE_DSPR2;
18050 if (ase & ASE_DSPR3)
18051 ext_ases |= AFL_ASE_DSPR3;
18053 ext_ases |= AFL_ASE_EVA;
18055 ext_ases |= AFL_ASE_MCU;
18056 if (ase & ASE_MDMX)
18057 ext_ases |= AFL_ASE_MDMX;
18058 if (ase & ASE_MIPS3D)
18059 ext_ases |= AFL_ASE_MIPS3D;
18061 ext_ases |= AFL_ASE_MT;
18062 if (ase & ASE_SMARTMIPS)
18063 ext_ases |= AFL_ASE_SMARTMIPS;
18064 if (ase & ASE_VIRT)
18065 ext_ases |= AFL_ASE_VIRT;
18067 ext_ases |= AFL_ASE_MSA;
18069 ext_ases |= AFL_ASE_XPA;
18073 /* Some special processing for a MIPS ELF file. */
18076 mips_elf_final_processing (void)
18079 Elf_Internal_ABIFlags_v0 flags;
18083 switch (file_mips_opts.isa)
18086 flags.isa_level = 1;
18089 flags.isa_level = 2;
18092 flags.isa_level = 3;
18095 flags.isa_level = 4;
18098 flags.isa_level = 5;
18101 flags.isa_level = 32;
18105 flags.isa_level = 32;
18109 flags.isa_level = 32;
18113 flags.isa_level = 32;
18117 flags.isa_level = 32;
18121 flags.isa_level = 64;
18125 flags.isa_level = 64;
18129 flags.isa_level = 64;
18133 flags.isa_level = 64;
18137 flags.isa_level = 64;
18142 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18143 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18144 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18145 : (file_mips_opts.fp == 64) ? AFL_REG_64
18147 flags.cpr2_size = AFL_REG_NONE;
18148 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18149 Tag_GNU_MIPS_ABI_FP);
18150 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18151 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18152 if (file_ase_mips16)
18153 flags.ases |= AFL_ASE_MIPS16;
18154 if (file_ase_micromips)
18155 flags.ases |= AFL_ASE_MICROMIPS;
18157 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18158 || file_mips_opts.fp == 64)
18159 && file_mips_opts.oddspreg)
18160 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18163 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18164 ((Elf_External_ABIFlags_v0 *)
18167 /* Write out the register information. */
18168 if (mips_abi != N64_ABI)
18172 s.ri_gprmask = mips_gprmask;
18173 s.ri_cprmask[0] = mips_cprmask[0];
18174 s.ri_cprmask[1] = mips_cprmask[1];
18175 s.ri_cprmask[2] = mips_cprmask[2];
18176 s.ri_cprmask[3] = mips_cprmask[3];
18177 /* The gp_value field is set by the MIPS ELF backend. */
18179 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18180 ((Elf32_External_RegInfo *)
18181 mips_regmask_frag));
18185 Elf64_Internal_RegInfo s;
18187 s.ri_gprmask = mips_gprmask;
18189 s.ri_cprmask[0] = mips_cprmask[0];
18190 s.ri_cprmask[1] = mips_cprmask[1];
18191 s.ri_cprmask[2] = mips_cprmask[2];
18192 s.ri_cprmask[3] = mips_cprmask[3];
18193 /* The gp_value field is set by the MIPS ELF backend. */
18195 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18196 ((Elf64_External_RegInfo *)
18197 mips_regmask_frag));
18200 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18201 sort of BFD interface for this. */
18202 if (mips_any_noreorder)
18203 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18204 if (mips_pic != NO_PIC)
18206 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18207 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18210 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18212 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18213 defined at present; this might need to change in future. */
18214 if (file_ase_mips16)
18215 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18216 if (file_ase_micromips)
18217 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18218 if (file_mips_opts.ase & ASE_MDMX)
18219 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18221 /* Set the MIPS ELF ABI flags. */
18222 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18223 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18224 else if (mips_abi == O64_ABI)
18225 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18226 else if (mips_abi == EABI_ABI)
18228 if (file_mips_opts.gp == 64)
18229 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18231 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18233 else if (mips_abi == N32_ABI)
18234 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18236 /* Nothing to do for N64_ABI. */
18238 if (mips_32bitmode)
18239 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18241 if (mips_nan2008 == 1)
18242 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18244 /* 32 bit code with 64 bit FP registers. */
18245 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18246 Tag_GNU_MIPS_ABI_FP);
18247 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18248 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18251 typedef struct proc {
18253 symbolS *func_end_sym;
18254 unsigned long reg_mask;
18255 unsigned long reg_offset;
18256 unsigned long fpreg_mask;
18257 unsigned long fpreg_offset;
18258 unsigned long frame_offset;
18259 unsigned long frame_reg;
18260 unsigned long pc_reg;
18263 static procS cur_proc;
18264 static procS *cur_proc_ptr;
18265 static int numprocs;
18267 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18268 as "2", and a normal nop as "0". */
18270 #define NOP_OPCODE_MIPS 0
18271 #define NOP_OPCODE_MIPS16 1
18272 #define NOP_OPCODE_MICROMIPS 2
18275 mips_nop_opcode (void)
18277 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18278 return NOP_OPCODE_MICROMIPS;
18279 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18280 return NOP_OPCODE_MIPS16;
18282 return NOP_OPCODE_MIPS;
18285 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18286 32-bit microMIPS NOPs here (if applicable). */
18289 mips_handle_align (fragS *fragp)
18293 int bytes, size, excess;
18296 if (fragp->fr_type != rs_align_code)
18299 p = fragp->fr_literal + fragp->fr_fix;
18301 switch (nop_opcode)
18303 case NOP_OPCODE_MICROMIPS:
18304 opcode = micromips_nop32_insn.insn_opcode;
18307 case NOP_OPCODE_MIPS16:
18308 opcode = mips16_nop_insn.insn_opcode;
18311 case NOP_OPCODE_MIPS:
18313 opcode = nop_insn.insn_opcode;
18318 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18319 excess = bytes % size;
18321 /* Handle the leading part if we're not inserting a whole number of
18322 instructions, and make it the end of the fixed part of the frag.
18323 Try to fit in a short microMIPS NOP if applicable and possible,
18324 and use zeroes otherwise. */
18325 gas_assert (excess < 4);
18326 fragp->fr_fix += excess;
18331 /* Fall through. */
18333 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18335 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18339 /* Fall through. */
18342 /* Fall through. */
18347 md_number_to_chars (p, opcode, size);
18348 fragp->fr_var = size;
18357 if (*input_line_pointer == '-')
18359 ++input_line_pointer;
18362 if (!ISDIGIT (*input_line_pointer))
18363 as_bad (_("expected simple number"));
18364 if (input_line_pointer[0] == '0')
18366 if (input_line_pointer[1] == 'x')
18368 input_line_pointer += 2;
18369 while (ISXDIGIT (*input_line_pointer))
18372 val |= hex_value (*input_line_pointer++);
18374 return negative ? -val : val;
18378 ++input_line_pointer;
18379 while (ISDIGIT (*input_line_pointer))
18382 val |= *input_line_pointer++ - '0';
18384 return negative ? -val : val;
18387 if (!ISDIGIT (*input_line_pointer))
18389 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18390 *input_line_pointer, *input_line_pointer);
18391 as_warn (_("invalid number"));
18394 while (ISDIGIT (*input_line_pointer))
18397 val += *input_line_pointer++ - '0';
18399 return negative ? -val : val;
18402 /* The .file directive; just like the usual .file directive, but there
18403 is an initial number which is the ECOFF file index. In the non-ECOFF
18404 case .file implies DWARF-2. */
18407 s_mips_file (int x ATTRIBUTE_UNUSED)
18409 static int first_file_directive = 0;
18411 if (ECOFF_DEBUGGING)
18420 filename = dwarf2_directive_file (0);
18422 /* Versions of GCC up to 3.1 start files with a ".file"
18423 directive even for stabs output. Make sure that this
18424 ".file" is handled. Note that you need a version of GCC
18425 after 3.1 in order to support DWARF-2 on MIPS. */
18426 if (filename != NULL && ! first_file_directive)
18428 (void) new_logical_line (filename, -1);
18429 s_app_file_string (filename, 0);
18431 first_file_directive = 1;
18435 /* The .loc directive, implying DWARF-2. */
18438 s_mips_loc (int x ATTRIBUTE_UNUSED)
18440 if (!ECOFF_DEBUGGING)
18441 dwarf2_directive_loc (0);
18444 /* The .end directive. */
18447 s_mips_end (int x ATTRIBUTE_UNUSED)
18451 /* Following functions need their own .frame and .cprestore directives. */
18452 mips_frame_reg_valid = 0;
18453 mips_cprestore_valid = 0;
18455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18458 demand_empty_rest_of_line ();
18463 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18464 as_warn (_(".end not in text section"));
18468 as_warn (_(".end directive without a preceding .ent directive"));
18469 demand_empty_rest_of_line ();
18475 gas_assert (S_GET_NAME (p));
18476 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18477 as_warn (_(".end symbol does not match .ent symbol"));
18479 if (debug_type == DEBUG_STABS)
18480 stabs_generate_asm_endfunc (S_GET_NAME (p),
18484 as_warn (_(".end directive missing or unknown symbol"));
18486 /* Create an expression to calculate the size of the function. */
18487 if (p && cur_proc_ptr)
18489 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18490 expressionS *exp = XNEW (expressionS);
18493 exp->X_op = O_subtract;
18494 exp->X_add_symbol = symbol_temp_new_now ();
18495 exp->X_op_symbol = p;
18496 exp->X_add_number = 0;
18498 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18501 /* Generate a .pdr section. */
18502 if (!ECOFF_DEBUGGING && mips_flag_pdr)
18504 segT saved_seg = now_seg;
18505 subsegT saved_subseg = now_subseg;
18509 #ifdef md_flush_pending_output
18510 md_flush_pending_output ();
18513 gas_assert (pdr_seg);
18514 subseg_set (pdr_seg, 0);
18516 /* Write the symbol. */
18517 exp.X_op = O_symbol;
18518 exp.X_add_symbol = p;
18519 exp.X_add_number = 0;
18520 emit_expr (&exp, 4);
18522 fragp = frag_more (7 * 4);
18524 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18525 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18526 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18527 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18528 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18529 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18530 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18532 subseg_set (saved_seg, saved_subseg);
18535 cur_proc_ptr = NULL;
18538 /* The .aent and .ent directives. */
18541 s_mips_ent (int aent)
18545 symbolP = get_symbol ();
18546 if (*input_line_pointer == ',')
18547 ++input_line_pointer;
18548 SKIP_WHITESPACE ();
18549 if (ISDIGIT (*input_line_pointer)
18550 || *input_line_pointer == '-')
18553 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18554 as_warn (_(".ent or .aent not in text section"));
18556 if (!aent && cur_proc_ptr)
18557 as_warn (_("missing .end"));
18561 /* This function needs its own .frame and .cprestore directives. */
18562 mips_frame_reg_valid = 0;
18563 mips_cprestore_valid = 0;
18565 cur_proc_ptr = &cur_proc;
18566 memset (cur_proc_ptr, '\0', sizeof (procS));
18568 cur_proc_ptr->func_sym = symbolP;
18572 if (debug_type == DEBUG_STABS)
18573 stabs_generate_asm_func (S_GET_NAME (symbolP),
18574 S_GET_NAME (symbolP));
18577 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18579 demand_empty_rest_of_line ();
18582 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18583 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18584 s_mips_frame is used so that we can set the PDR information correctly.
18585 We can't use the ecoff routines because they make reference to the ecoff
18586 symbol table (in the mdebug section). */
18589 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18591 if (ECOFF_DEBUGGING)
18597 if (cur_proc_ptr == (procS *) NULL)
18599 as_warn (_(".frame outside of .ent"));
18600 demand_empty_rest_of_line ();
18604 cur_proc_ptr->frame_reg = tc_get_register (1);
18606 SKIP_WHITESPACE ();
18607 if (*input_line_pointer++ != ','
18608 || get_absolute_expression_and_terminator (&val) != ',')
18610 as_warn (_("bad .frame directive"));
18611 --input_line_pointer;
18612 demand_empty_rest_of_line ();
18616 cur_proc_ptr->frame_offset = val;
18617 cur_proc_ptr->pc_reg = tc_get_register (0);
18619 demand_empty_rest_of_line ();
18623 /* The .fmask and .mask directives. If the mdebug section is present
18624 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18625 embedded targets, s_mips_mask is used so that we can set the PDR
18626 information correctly. We can't use the ecoff routines because they
18627 make reference to the ecoff symbol table (in the mdebug section). */
18630 s_mips_mask (int reg_type)
18632 if (ECOFF_DEBUGGING)
18633 s_ignore (reg_type);
18638 if (cur_proc_ptr == (procS *) NULL)
18640 as_warn (_(".mask/.fmask outside of .ent"));
18641 demand_empty_rest_of_line ();
18645 if (get_absolute_expression_and_terminator (&mask) != ',')
18647 as_warn (_("bad .mask/.fmask directive"));
18648 --input_line_pointer;
18649 demand_empty_rest_of_line ();
18653 off = get_absolute_expression ();
18655 if (reg_type == 'F')
18657 cur_proc_ptr->fpreg_mask = mask;
18658 cur_proc_ptr->fpreg_offset = off;
18662 cur_proc_ptr->reg_mask = mask;
18663 cur_proc_ptr->reg_offset = off;
18666 demand_empty_rest_of_line ();
18670 /* A table describing all the processors gas knows about. Names are
18671 matched in the order listed.
18673 To ease comparison, please keep this table in the same order as
18674 gcc's mips_cpu_info_table[]. */
18675 static const struct mips_cpu_info mips_cpu_info_table[] =
18677 /* Entries for generic ISAs */
18678 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18679 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18680 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18681 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18682 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18683 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18684 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18685 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18686 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
18687 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
18688 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18689 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
18690 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18691 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
18692 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
18695 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18696 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18697 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
18700 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
18703 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18704 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18705 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18706 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18707 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18708 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18709 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18710 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18711 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18712 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18713 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18714 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18715 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
18716 /* ST Microelectronics Loongson 2E and 2F cores */
18717 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18718 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
18721 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18722 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18723 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18724 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18725 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18726 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18727 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18728 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18729 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18730 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18731 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18732 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18733 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18734 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18735 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
18738 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18739 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18740 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18741 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18743 /* MIPS 32 Release 2 */
18744 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18745 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18746 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18747 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18748 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18749 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18750 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18751 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18752 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18753 ISA_MIPS32R2, CPU_MIPS32R2 },
18754 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18755 ISA_MIPS32R2, CPU_MIPS32R2 },
18756 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18757 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18758 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18759 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18760 /* Deprecated forms of the above. */
18761 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18762 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18763 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18764 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18765 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18766 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18767 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18768 /* Deprecated forms of the above. */
18769 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18770 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18771 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18772 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18773 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18774 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18775 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18776 /* Deprecated forms of the above. */
18777 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18778 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18779 /* 34Kn is a 34kc without DSP. */
18780 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18781 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18782 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18783 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18784 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18785 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18786 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18787 /* Deprecated forms of the above. */
18788 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18789 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18790 /* 1004K cores are multiprocessor versions of the 34K. */
18791 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18792 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18793 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18794 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18795 /* interaptiv is the new name for 1004kf */
18796 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18798 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18799 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18800 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18801 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
18804 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18805 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18806 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18807 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18809 /* Broadcom SB-1 CPU core */
18810 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18811 /* Broadcom SB-1A CPU core */
18812 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18814 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
18816 /* MIPS 64 Release 2 */
18818 /* Cavium Networks Octeon CPU core */
18819 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18820 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18821 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
18822 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
18825 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
18828 XLP is mostly like XLR, with the prominent exception that it is
18829 MIPS64R2 rather than MIPS64. */
18830 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
18832 /* MIPS 64 Release 6 */
18833 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18834 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18837 { NULL, 0, 0, 0, 0 }
18841 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18842 with a final "000" replaced by "k". Ignore case.
18844 Note: this function is shared between GCC and GAS. */
18847 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18849 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18850 given++, canonical++;
18852 return ((*given == 0 && *canonical == 0)
18853 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18857 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18858 CPU name. We've traditionally allowed a lot of variation here.
18860 Note: this function is shared between GCC and GAS. */
18863 mips_matching_cpu_name_p (const char *canonical, const char *given)
18865 /* First see if the name matches exactly, or with a final "000"
18866 turned into "k". */
18867 if (mips_strict_matching_cpu_name_p (canonical, given))
18870 /* If not, try comparing based on numerical designation alone.
18871 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18872 if (TOLOWER (*given) == 'r')
18874 if (!ISDIGIT (*given))
18877 /* Skip over some well-known prefixes in the canonical name,
18878 hoping to find a number there too. */
18879 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18881 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18883 else if (TOLOWER (canonical[0]) == 'r')
18886 return mips_strict_matching_cpu_name_p (canonical, given);
18890 /* Parse an option that takes the name of a processor as its argument.
18891 OPTION is the name of the option and CPU_STRING is the argument.
18892 Return the corresponding processor enumeration if the CPU_STRING is
18893 recognized, otherwise report an error and return null.
18895 A similar function exists in GCC. */
18897 static const struct mips_cpu_info *
18898 mips_parse_cpu (const char *option, const char *cpu_string)
18900 const struct mips_cpu_info *p;
18902 /* 'from-abi' selects the most compatible architecture for the given
18903 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18904 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18905 version. Look first at the -mgp options, if given, otherwise base
18906 the choice on MIPS_DEFAULT_64BIT.
18908 Treat NO_ABI like the EABIs. One reason to do this is that the
18909 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18910 architecture. This code picks MIPS I for 'mips' and MIPS III for
18911 'mips64', just as we did in the days before 'from-abi'. */
18912 if (strcasecmp (cpu_string, "from-abi") == 0)
18914 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18915 return mips_cpu_info_from_isa (ISA_MIPS1);
18917 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18918 return mips_cpu_info_from_isa (ISA_MIPS3);
18920 if (file_mips_opts.gp >= 0)
18921 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
18922 ? ISA_MIPS1 : ISA_MIPS3);
18924 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18929 /* 'default' has traditionally been a no-op. Probably not very useful. */
18930 if (strcasecmp (cpu_string, "default") == 0)
18933 for (p = mips_cpu_info_table; p->name != 0; p++)
18934 if (mips_matching_cpu_name_p (p->name, cpu_string))
18937 as_bad (_("bad value (%s) for %s"), cpu_string, option);
18941 /* Return the canonical processor information for ISA (a member of the
18942 ISA_MIPS* enumeration). */
18944 static const struct mips_cpu_info *
18945 mips_cpu_info_from_isa (int isa)
18949 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18950 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18951 && isa == mips_cpu_info_table[i].isa)
18952 return (&mips_cpu_info_table[i]);
18957 static const struct mips_cpu_info *
18958 mips_cpu_info_from_arch (int arch)
18962 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18963 if (arch == mips_cpu_info_table[i].cpu)
18964 return (&mips_cpu_info_table[i]);
18970 show (FILE *stream, const char *string, int *col_p, int *first_p)
18974 fprintf (stream, "%24s", "");
18979 fprintf (stream, ", ");
18983 if (*col_p + strlen (string) > 72)
18985 fprintf (stream, "\n%24s", "");
18989 fprintf (stream, "%s", string);
18990 *col_p += strlen (string);
18996 md_show_usage (FILE *stream)
19001 fprintf (stream, _("\
19003 -EB generate big endian output\n\
19004 -EL generate little endian output\n\
19005 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19006 -G NUM allow referencing objects up to NUM bytes\n\
19007 implicitly with the gp register [default 8]\n"));
19008 fprintf (stream, _("\
19009 -mips1 generate MIPS ISA I instructions\n\
19010 -mips2 generate MIPS ISA II instructions\n\
19011 -mips3 generate MIPS ISA III instructions\n\
19012 -mips4 generate MIPS ISA IV instructions\n\
19013 -mips5 generate MIPS ISA V instructions\n\
19014 -mips32 generate MIPS32 ISA instructions\n\
19015 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19016 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19017 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19018 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19019 -mips64 generate MIPS64 ISA instructions\n\
19020 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19021 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19022 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19023 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19024 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19028 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19029 show (stream, mips_cpu_info_table[i].name, &column, &first);
19030 show (stream, "from-abi", &column, &first);
19031 fputc ('\n', stream);
19033 fprintf (stream, _("\
19034 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19035 -no-mCPU don't generate code specific to CPU.\n\
19036 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19040 show (stream, "3900", &column, &first);
19041 show (stream, "4010", &column, &first);
19042 show (stream, "4100", &column, &first);
19043 show (stream, "4650", &column, &first);
19044 fputc ('\n', stream);
19046 fprintf (stream, _("\
19047 -mips16 generate mips16 instructions\n\
19048 -no-mips16 do not generate mips16 instructions\n"));
19049 fprintf (stream, _("\
19050 -mmicromips generate microMIPS instructions\n\
19051 -mno-micromips do not generate microMIPS instructions\n"));
19052 fprintf (stream, _("\
19053 -msmartmips generate smartmips instructions\n\
19054 -mno-smartmips do not generate smartmips instructions\n"));
19055 fprintf (stream, _("\
19056 -mdsp generate DSP instructions\n\
19057 -mno-dsp do not generate DSP instructions\n"));
19058 fprintf (stream, _("\
19059 -mdspr2 generate DSP R2 instructions\n\
19060 -mno-dspr2 do not generate DSP R2 instructions\n"));
19061 fprintf (stream, _("\
19062 -mdspr3 generate DSP R3 instructions\n\
19063 -mno-dspr3 do not generate DSP R3 instructions\n"));
19064 fprintf (stream, _("\
19065 -mmt generate MT instructions\n\
19066 -mno-mt do not generate MT instructions\n"));
19067 fprintf (stream, _("\
19068 -mmcu generate MCU instructions\n\
19069 -mno-mcu do not generate MCU instructions\n"));
19070 fprintf (stream, _("\
19071 -mmsa generate MSA instructions\n\
19072 -mno-msa do not generate MSA instructions\n"));
19073 fprintf (stream, _("\
19074 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19075 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19076 fprintf (stream, _("\
19077 -mvirt generate Virtualization instructions\n\
19078 -mno-virt do not generate Virtualization instructions\n"));
19079 fprintf (stream, _("\
19080 -minsn32 only generate 32-bit microMIPS instructions\n\
19081 -mno-insn32 generate all microMIPS instructions\n"));
19082 fprintf (stream, _("\
19083 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19084 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19085 -mfix-vr4120 work around certain VR4120 errata\n\
19086 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19087 -mfix-24k insert a nop after ERET and DERET instructions\n\
19088 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19089 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19090 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19091 -msym32 assume all symbols have 32-bit values\n\
19092 -O0 remove unneeded NOPs, do not swap branches\n\
19093 -O remove unneeded NOPs and swap branches\n\
19094 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19095 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19096 fprintf (stream, _("\
19097 -mhard-float allow floating-point instructions\n\
19098 -msoft-float do not allow floating-point instructions\n\
19099 -msingle-float only allow 32-bit floating-point operations\n\
19100 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19101 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19102 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19103 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19107 show (stream, "legacy", &column, &first);
19108 show (stream, "2008", &column, &first);
19110 fputc ('\n', stream);
19112 fprintf (stream, _("\
19113 -KPIC, -call_shared generate SVR4 position independent code\n\
19114 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19115 -mvxworks-pic generate VxWorks position independent code\n\
19116 -non_shared do not generate code that can operate with DSOs\n\
19117 -xgot assume a 32 bit GOT\n\
19118 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19119 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19120 position dependent (non shared) code\n\
19121 -mabi=ABI create ABI conformant object file for:\n"));
19125 show (stream, "32", &column, &first);
19126 show (stream, "o64", &column, &first);
19127 show (stream, "n32", &column, &first);
19128 show (stream, "64", &column, &first);
19129 show (stream, "eabi", &column, &first);
19131 fputc ('\n', stream);
19133 fprintf (stream, _("\
19134 -32 create o32 ABI object file (default)\n\
19135 -n32 create n32 ABI object file\n\
19136 -64 create 64 ABI object file\n"));
19141 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19143 if (HAVE_64BIT_SYMBOLS)
19144 return dwarf2_format_64bit_irix;
19146 return dwarf2_format_32bit;
19151 mips_dwarf2_addr_size (void)
19153 if (HAVE_64BIT_OBJECTS)
19159 /* Standard calling conventions leave the CFA at SP on entry. */
19161 mips_cfi_frame_initial_instructions (void)
19163 cfi_add_CFA_def_cfa_register (SP);
19167 tc_mips_regname_to_dw2regnum (char *regname)
19169 unsigned int regnum = -1;
19172 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19178 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19179 Given a symbolic attribute NAME, return the proper integer value.
19180 Returns -1 if the attribute is not known. */
19183 mips_convert_symbolic_attribute (const char *name)
19185 static const struct
19190 attribute_table[] =
19192 #define T(tag) {#tag, tag}
19193 T (Tag_GNU_MIPS_ABI_FP),
19194 T (Tag_GNU_MIPS_ABI_MSA),
19202 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19203 if (streq (name, attribute_table[i].name))
19204 return attribute_table[i].tag;
19212 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19214 mips_emit_delays ();
19216 as_warn (_("missing .end at end of assembly"));
19218 /* Just in case no code was emitted, do the consistency check. */
19219 file_mips_check_options ();
19221 /* Set a floating-point ABI if the user did not. */
19222 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19224 /* Perform consistency checks on the floating-point ABI. */
19225 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19226 Tag_GNU_MIPS_ABI_FP);
19227 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19228 check_fpabi (fpabi);
19232 /* Soft-float gets precedence over single-float, the two options should
19233 not be used together so this should not matter. */
19234 if (file_mips_opts.soft_float == 1)
19235 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19236 /* Single-float gets precedence over all double_float cases. */
19237 else if (file_mips_opts.single_float == 1)
19238 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19241 switch (file_mips_opts.fp)
19244 if (file_mips_opts.gp == 32)
19245 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19248 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19251 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19252 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19253 else if (file_mips_opts.gp == 32)
19254 fpabi = Val_GNU_MIPS_ABI_FP_64;
19256 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19261 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19262 Tag_GNU_MIPS_ABI_FP, fpabi);
19266 /* Returns the relocation type required for a particular CFI encoding. */
19268 bfd_reloc_code_real_type
19269 mips_cfi_reloc_for_encoding (int encoding)
19271 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19272 return BFD_RELOC_32_PCREL;
19273 else return BFD_RELOC_NONE;