1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 /* Return true if ISA supports 64-bit right rotate (dror et al.)
265 #define ISA_HAS_DROR(ISA) ( \
269 /* Return true if ISA supports 32-bit right rotate (ror et al.)
271 #define ISA_HAS_ROR(ISA) ( \
272 (ISA) == ISA_MIPS32R2 \
275 #define HAVE_32BIT_GPRS \
276 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
278 #define HAVE_32BIT_FPRS \
279 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
282 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
284 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
286 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
288 /* We can only have 64bit addresses if the object file format
290 #define HAVE_32BIT_ADDRESSES \
292 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS) \
294 && mips_pic != EMBEDDED_PIC))
296 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
298 /* Return true if the given CPU supports the MIPS16 ASE. */
299 #define CPU_HAS_MIPS16(cpu) \
300 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
301 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
303 /* Return true if the given CPU supports the MIPS3D ASE. */
304 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
307 /* Return true if the given CPU supports the MDMX ASE. */
308 #define CPU_HAS_MDMX(cpu) (FALSE \
311 /* True if CPU has a dror instruction. */
312 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
314 /* True if CPU has a ror instruction. */
315 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
317 /* Whether the processor uses hardware interlocks to protect
318 reads from the HI and LO registers, and thus does not
319 require nops to be inserted. */
321 #define hilo_interlocks (mips_arch == CPU_R4010 \
322 || mips_arch == CPU_VR5500 \
323 || mips_arch == CPU_SB1 \
326 /* Whether the processor uses hardware interlocks to protect reads
327 from the GPRs, and thus does not require nops to be inserted. */
328 #define gpr_interlocks \
329 (mips_opts.isa != ISA_MIPS1 \
330 || mips_arch == CPU_VR5400 \
331 || mips_arch == CPU_VR5500 \
332 || mips_arch == CPU_R3900)
334 /* As with other "interlocks" this is used by hardware that has FP
335 (co-processor) interlocks. */
336 /* Itbl support may require additional care here. */
337 #define cop_interlocks (mips_arch == CPU_R4300 \
338 || mips_arch == CPU_VR5400 \
339 || mips_arch == CPU_VR5500 \
340 || mips_arch == CPU_SB1 \
343 /* Is this a mfhi or mflo instruction? */
344 #define MF_HILO_INSN(PINFO) \
345 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
347 /* MIPS PIC level. */
349 enum mips_pic_level mips_pic;
351 /* Warn about all NOPS that the assembler generates. */
352 static int warn_nops = 0;
354 /* 1 if we should generate 32 bit offsets from the $gp register in
355 SVR4_PIC mode. Currently has no meaning in other modes. */
356 static int mips_big_got = 0;
358 /* 1 if trap instructions should used for overflow rather than break
360 static int mips_trap = 0;
362 /* 1 if double width floating point constants should not be constructed
363 by assembling two single width halves into two single width floating
364 point registers which just happen to alias the double width destination
365 register. On some architectures this aliasing can be disabled by a bit
366 in the status register, and the setting of this bit cannot be determined
367 automatically at assemble time. */
368 static int mips_disable_float_construction;
370 /* Non-zero if any .set noreorder directives were used. */
372 static int mips_any_noreorder;
374 /* Non-zero if nops should be inserted when the register referenced in
375 an mfhi/mflo instruction is read in the next two instructions. */
376 static int mips_7000_hilo_fix;
378 /* The size of the small data section. */
379 static unsigned int g_switch_value = 8;
380 /* Whether the -G option was used. */
381 static int g_switch_seen = 0;
386 /* If we can determine in advance that GP optimization won't be
387 possible, we can skip the relaxation stuff that tries to produce
388 GP-relative references. This makes delay slot optimization work
391 This function can only provide a guess, but it seems to work for
392 gcc output. It needs to guess right for gcc, otherwise gcc
393 will put what it thinks is a GP-relative instruction in a branch
396 I don't know if a fix is needed for the SVR4_PIC mode. I've only
397 fixed it for the non-PIC mode. KR 95/04/07 */
398 static int nopic_need_relax PARAMS ((symbolS *, int));
400 /* handle of the OPCODE hash table */
401 static struct hash_control *op_hash = NULL;
403 /* The opcode hash table we use for the mips16. */
404 static struct hash_control *mips16_op_hash = NULL;
406 /* This array holds the chars that always start a comment. If the
407 pre-processor is disabled, these aren't very useful */
408 const char comment_chars[] = "#";
410 /* This array holds the chars that only start a comment at the beginning of
411 a line. If the line seems to have the form '# 123 filename'
412 .line and .file directives will appear in the pre-processed output */
413 /* Note that input_file.c hand checks for '#' at the beginning of the
414 first line of the input file. This is because the compiler outputs
415 #NO_APP at the beginning of its output. */
416 /* Also note that C style comments are always supported. */
417 const char line_comment_chars[] = "#";
419 /* This array holds machine specific line separator characters. */
420 const char line_separator_chars[] = ";";
422 /* Chars that can be used to separate mant from exp in floating point nums */
423 const char EXP_CHARS[] = "eE";
425 /* Chars that mean this number is a floating point constant */
428 const char FLT_CHARS[] = "rRsSfFdDxXpP";
430 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
431 changed in read.c . Ideally it shouldn't have to know about it at all,
432 but nothing is ideal around here.
435 static char *insn_error;
437 static int auto_align = 1;
439 /* When outputting SVR4 PIC code, the assembler needs to know the
440 offset in the stack frame from which to restore the $gp register.
441 This is set by the .cprestore pseudo-op, and saved in this
443 static offsetT mips_cprestore_offset = -1;
445 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
446 more optimizations, it can use a register value instead of a memory-saved
447 offset and even an other register than $gp as global pointer. */
448 static offsetT mips_cpreturn_offset = -1;
449 static int mips_cpreturn_register = -1;
450 static int mips_gp_register = GP;
451 static int mips_gprel_offset = 0;
453 /* Whether mips_cprestore_offset has been set in the current function
454 (or whether it has already been warned about, if not). */
455 static int mips_cprestore_valid = 0;
457 /* This is the register which holds the stack frame, as set by the
458 .frame pseudo-op. This is needed to implement .cprestore. */
459 static int mips_frame_reg = SP;
461 /* Whether mips_frame_reg has been set in the current function
462 (or whether it has already been warned about, if not). */
463 static int mips_frame_reg_valid = 0;
465 /* To output NOP instructions correctly, we need to keep information
466 about the previous two instructions. */
468 /* Whether we are optimizing. The default value of 2 means to remove
469 unneeded NOPs and swap branch instructions when possible. A value
470 of 1 means to not swap branches. A value of 0 means to always
472 static int mips_optimize = 2;
474 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
475 equivalent to seeing no -g option at all. */
476 static int mips_debug = 0;
478 /* The previous instruction. */
479 static struct mips_cl_insn prev_insn;
481 /* The instruction before prev_insn. */
482 static struct mips_cl_insn prev_prev_insn;
484 /* If we don't want information for prev_insn or prev_prev_insn, we
485 point the insn_mo field at this dummy integer. */
486 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
488 /* Non-zero if prev_insn is valid. */
489 static int prev_insn_valid;
491 /* The frag for the previous instruction. */
492 static struct frag *prev_insn_frag;
494 /* The offset into prev_insn_frag for the previous instruction. */
495 static long prev_insn_where;
497 /* The reloc type for the previous instruction, if any. */
498 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
500 /* The reloc for the previous instruction, if any. */
501 static fixS *prev_insn_fixp[3];
503 /* Non-zero if the previous instruction was in a delay slot. */
504 static int prev_insn_is_delay_slot;
506 /* Non-zero if the previous instruction was in a .set noreorder. */
507 static int prev_insn_unreordered;
509 /* Non-zero if the previous instruction uses an extend opcode (if
511 static int prev_insn_extended;
513 /* Non-zero if the previous previous instruction was in a .set
515 static int prev_prev_insn_unreordered;
517 /* If this is set, it points to a frag holding nop instructions which
518 were inserted before the start of a noreorder section. If those
519 nops turn out to be unnecessary, the size of the frag can be
521 static fragS *prev_nop_frag;
523 /* The number of nop instructions we created in prev_nop_frag. */
524 static int prev_nop_frag_holds;
526 /* The number of nop instructions that we know we need in
528 static int prev_nop_frag_required;
530 /* The number of instructions we've seen since prev_nop_frag. */
531 static int prev_nop_frag_since;
533 /* For ECOFF and ELF, relocations against symbols are done in two
534 parts, with a HI relocation and a LO relocation. Each relocation
535 has only 16 bits of space to store an addend. This means that in
536 order for the linker to handle carries correctly, it must be able
537 to locate both the HI and the LO relocation. This means that the
538 relocations must appear in order in the relocation table.
540 In order to implement this, we keep track of each unmatched HI
541 relocation. We then sort them so that they immediately precede the
542 corresponding LO relocation. */
547 struct mips_hi_fixup *next;
550 /* The section this fixup is in. */
554 /* The list of unmatched HI relocs. */
556 static struct mips_hi_fixup *mips_hi_fixup_list;
558 /* The frag containing the last explicit relocation operator.
559 Null if explicit relocations have not been used. */
561 static fragS *prev_reloc_op_frag;
563 /* Map normal MIPS register numbers to mips16 register numbers. */
565 #define X ILLEGAL_REG
566 static const int mips32_to_16_reg_map[] =
568 X, X, 2, 3, 4, 5, 6, 7,
569 X, X, X, X, X, X, X, X,
570 0, 1, X, X, X, X, X, X,
571 X, X, X, X, X, X, X, X
575 /* Map mips16 register numbers to normal MIPS register numbers. */
577 static const unsigned int mips16_to_32_reg_map[] =
579 16, 17, 2, 3, 4, 5, 6, 7
582 static int mips_fix_4122_bugs;
584 /* We don't relax branches by default, since this causes us to expand
585 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
586 fail to compute the offset before expanding the macro to the most
587 efficient expansion. */
589 static int mips_relax_branch;
591 /* Since the MIPS does not have multiple forms of PC relative
592 instructions, we do not have to do relaxing as is done on other
593 platforms. However, we do have to handle GP relative addressing
594 correctly, which turns out to be a similar problem.
596 Every macro that refers to a symbol can occur in (at least) two
597 forms, one with GP relative addressing and one without. For
598 example, loading a global variable into a register generally uses
599 a macro instruction like this:
601 If i can be addressed off the GP register (this is true if it is in
602 the .sbss or .sdata section, or if it is known to be smaller than
603 the -G argument) this will generate the following instruction:
605 This instruction will use a GPREL reloc. If i can not be addressed
606 off the GP register, the following instruction sequence will be used:
609 In this case the first instruction will have a HI16 reloc, and the
610 second reloc will have a LO16 reloc. Both relocs will be against
613 The issue here is that we may not know whether i is GP addressable
614 until after we see the instruction that uses it. Therefore, we
615 want to be able to choose the final instruction sequence only at
616 the end of the assembly. This is similar to the way other
617 platforms choose the size of a PC relative instruction only at the
620 When generating position independent code we do not use GP
621 addressing in quite the same way, but the issue still arises as
622 external symbols and local symbols must be handled differently.
624 We handle these issues by actually generating both possible
625 instruction sequences. The longer one is put in a frag_var with
626 type rs_machine_dependent. We encode what to do with the frag in
627 the subtype field. We encode (1) the number of existing bytes to
628 replace, (2) the number of new bytes to use, (3) the offset from
629 the start of the existing bytes to the first reloc we must generate
630 (that is, the offset is applied from the start of the existing
631 bytes after they are replaced by the new bytes, if any), (4) the
632 offset from the start of the existing bytes to the second reloc,
633 (5) whether a third reloc is needed (the third reloc is always four
634 bytes after the second reloc), and (6) whether to warn if this
635 variant is used (this is sometimes needed if .set nomacro or .set
636 noat is in effect). All these numbers are reasonably small.
638 Generating two instruction sequences must be handled carefully to
639 ensure that delay slots are handled correctly. Fortunately, there
640 are a limited number of cases. When the second instruction
641 sequence is generated, append_insn is directed to maintain the
642 existing delay slot information, so it continues to apply to any
643 code after the second instruction sequence. This means that the
644 second instruction sequence must not impose any requirements not
645 required by the first instruction sequence.
647 These variant frags are then handled in functions called by the
648 machine independent code. md_estimate_size_before_relax returns
649 the final size of the frag. md_convert_frag sets up the final form
650 of the frag. tc_gen_reloc adjust the first reloc and adds a second
652 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
656 | (((reloc1) + 64) << 9) \
657 | (((reloc2) + 64) << 2) \
658 | ((reloc3) ? (1 << 1) : 0) \
660 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
661 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
662 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
663 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
664 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
665 #define RELAX_WARN(i) ((i) & 1)
667 /* Branch without likely bit. If label is out of range, we turn:
669 beq reg1, reg2, label
679 with the following opcode replacements:
686 bltzal <-> bgezal (with jal label instead of j label)
688 Even though keeping the delay slot instruction in the delay slot of
689 the branch would be more efficient, it would be very tricky to do
690 correctly, because we'd have to introduce a variable frag *after*
691 the delay slot instruction, and expand that instead. Let's do it
692 the easy way for now, even if the branch-not-taken case now costs
693 one additional instruction. Out-of-range branches are not supposed
694 to be common, anyway.
696 Branch likely. If label is out of range, we turn:
698 beql reg1, reg2, label
699 delay slot (annulled if branch not taken)
708 delay slot (executed only if branch taken)
711 It would be possible to generate a shorter sequence by losing the
712 likely bit, generating something like:
717 delay slot (executed only if branch taken)
729 bltzall -> bgezal (with jal label instead of j label)
730 bgezall -> bltzal (ditto)
733 but it's not clear that it would actually improve performance. */
734 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
737 | ((toofar) ? 1 : 0) \
739 | ((likely) ? 4 : 0) \
740 | ((uncond) ? 8 : 0)))
741 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
742 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
743 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
744 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
745 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
747 /* For mips16 code, we use an entirely different form of relaxation.
748 mips16 supports two versions of most instructions which take
749 immediate values: a small one which takes some small value, and a
750 larger one which takes a 16 bit value. Since branches also follow
751 this pattern, relaxing these values is required.
753 We can assemble both mips16 and normal MIPS code in a single
754 object. Therefore, we need to support this type of relaxation at
755 the same time that we support the relaxation described above. We
756 use the high bit of the subtype field to distinguish these cases.
758 The information we store for this type of relaxation is the
759 argument code found in the opcode file for this relocation, whether
760 the user explicitly requested a small or extended form, and whether
761 the relocation is in a jump or jal delay slot. That tells us the
762 size of the value, and how it should be stored. We also store
763 whether the fragment is considered to be extended or not. We also
764 store whether this is known to be a branch to a different section,
765 whether we have tried to relax this frag yet, and whether we have
766 ever extended a PC relative fragment because of a shift count. */
767 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
770 | ((small) ? 0x100 : 0) \
771 | ((ext) ? 0x200 : 0) \
772 | ((dslot) ? 0x400 : 0) \
773 | ((jal_dslot) ? 0x800 : 0))
774 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
775 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
776 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
777 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
778 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
779 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
780 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
781 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
782 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
783 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
784 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
785 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
787 /* Is the given value a sign-extended 32-bit value? */
788 #define IS_SEXT_32BIT_NUM(x) \
789 (((x) &~ (offsetT) 0x7fffffff) == 0 \
790 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
792 /* Is the given value a sign-extended 16-bit value? */
793 #define IS_SEXT_16BIT_NUM(x) \
794 (((x) &~ (offsetT) 0x7fff) == 0 \
795 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
798 /* Prototypes for static functions. */
801 #define internalError() \
802 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
804 #define internalError() as_fatal (_("MIPS internal Error"));
807 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
809 static inline bfd_boolean reloc_needs_lo_p
810 PARAMS ((bfd_reloc_code_real_type));
811 static inline bfd_boolean fixup_has_matching_lo_p
813 static int insn_uses_reg
814 PARAMS ((struct mips_cl_insn *ip, unsigned int reg,
815 enum mips_regclass class));
816 static int reg_needs_delay
817 PARAMS ((unsigned int));
818 static void mips16_mark_labels
820 static void append_insn
821 PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p,
822 bfd_reloc_code_real_type *r));
823 static void mips_no_prev_insn
825 static void mips_emit_delays
826 PARAMS ((bfd_boolean));
828 static void macro_build
829 PARAMS ((char *place, int *counter, expressionS * ep, const char *name,
830 const char *fmt, ...));
832 static void macro_build ();
834 static void mips16_macro_build
835 PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list));
836 static void macro_build_jalr
837 PARAMS ((int, expressionS *));
838 static void macro_build_lui
839 PARAMS ((char *place, int *counter, expressionS * ep, int regnum));
840 static void macro_build_ldst_constoffset
841 PARAMS ((char *place, int *counter, expressionS * ep, const char *op,
842 int valreg, int breg));
844 PARAMS ((int *counter, int reg, int unsignedp));
845 static void check_absolute_expr
846 PARAMS ((struct mips_cl_insn * ip, expressionS *));
847 static void load_register
848 PARAMS ((int *, int, expressionS *, int));
849 static void load_address
850 PARAMS ((int *, int, expressionS *, int *));
851 static void move_register
852 PARAMS ((int *, int, int));
854 PARAMS ((struct mips_cl_insn * ip));
855 static void mips16_macro
856 PARAMS ((struct mips_cl_insn * ip));
857 #ifdef LOSING_COMPILER
859 PARAMS ((struct mips_cl_insn * ip));
862 PARAMS ((char *str, struct mips_cl_insn * ip));
863 static void mips16_ip
864 PARAMS ((char *str, struct mips_cl_insn * ip));
865 static void mips16_immed
866 PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean,
867 bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *));
868 static bfd_boolean parse_relocation
869 PARAMS ((char **, bfd_reloc_code_real_type *));
870 static size_t my_getSmallExpression
871 PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *));
872 static void my_getExpression
873 PARAMS ((expressionS *, char *));
875 static int support_64bit_objects
878 static void mips_set_option_string
879 PARAMS ((const char **, const char *));
880 static symbolS *get_symbol
882 static void mips_align
883 PARAMS ((int to, int fill, symbolS *label));
886 static void s_change_sec
888 static void s_change_section
892 static void s_float_cons
894 static void s_mips_globl
898 static void s_mipsset
900 static void s_abicalls
904 static void s_cpsetup
906 static void s_cplocal
908 static void s_cprestore
910 static void s_cpreturn
912 static void s_gpvalue
916 static void s_gpdword
922 static void md_obj_begin
924 static void md_obj_end
926 static long get_number
928 static void s_mips_ent
930 static void s_mips_end
932 static void s_mips_frame
934 static void s_mips_mask
936 static void s_mips_stab
938 static void s_mips_weakext
940 static void s_mips_file
942 static void s_mips_loc
944 static bfd_boolean pic_need_relax
945 PARAMS ((symbolS *, asection *));
946 static int mips16_extended_frag
947 PARAMS ((fragS *, asection *, long));
948 static int relaxed_branch_length (fragS *, asection *, int);
949 static int validate_mips_insn
950 PARAMS ((const struct mips_opcode *));
952 PARAMS ((FILE *, const char *, int *, int *));
954 static int mips_need_elf_addend_fixup
958 /* Table and functions used to map between CPU/ISA names, and
959 ISA levels, and CPU numbers. */
963 const char *name; /* CPU or ISA name. */
964 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
965 int isa; /* ISA level. */
966 int cpu; /* CPU number (default CPU if ISA). */
969 static void mips_set_architecture
970 PARAMS ((const struct mips_cpu_info *));
971 static void mips_set_tune
972 PARAMS ((const struct mips_cpu_info *));
973 static bfd_boolean mips_strict_matching_cpu_name_p
974 PARAMS ((const char *, const char *));
975 static bfd_boolean mips_matching_cpu_name_p
976 PARAMS ((const char *, const char *));
977 static const struct mips_cpu_info *mips_parse_cpu
978 PARAMS ((const char *, const char *));
979 static const struct mips_cpu_info *mips_cpu_info_from_isa
984 The following pseudo-ops from the Kane and Heinrich MIPS book
985 should be defined here, but are currently unsupported: .alias,
986 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
988 The following pseudo-ops from the Kane and Heinrich MIPS book are
989 specific to the type of debugging information being generated, and
990 should be defined by the object format: .aent, .begin, .bend,
991 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
994 The following pseudo-ops from the Kane and Heinrich MIPS book are
995 not MIPS CPU specific, but are also not specific to the object file
996 format. This file is probably the best place to define them, but
997 they are not currently supported: .asm0, .endr, .lab, .repeat,
1000 static const pseudo_typeS mips_pseudo_table[] =
1002 /* MIPS specific pseudo-ops. */
1003 {"option", s_option, 0},
1004 {"set", s_mipsset, 0},
1005 {"rdata", s_change_sec, 'r'},
1006 {"sdata", s_change_sec, 's'},
1007 {"livereg", s_ignore, 0},
1008 {"abicalls", s_abicalls, 0},
1009 {"cpload", s_cpload, 0},
1010 {"cpsetup", s_cpsetup, 0},
1011 {"cplocal", s_cplocal, 0},
1012 {"cprestore", s_cprestore, 0},
1013 {"cpreturn", s_cpreturn, 0},
1014 {"gpvalue", s_gpvalue, 0},
1015 {"gpword", s_gpword, 0},
1016 {"gpdword", s_gpdword, 0},
1017 {"cpadd", s_cpadd, 0},
1018 {"insn", s_insn, 0},
1020 /* Relatively generic pseudo-ops that happen to be used on MIPS
1022 {"asciiz", stringer, 1},
1023 {"bss", s_change_sec, 'b'},
1025 {"half", s_cons, 1},
1026 {"dword", s_cons, 3},
1027 {"weakext", s_mips_weakext, 0},
1029 /* These pseudo-ops are defined in read.c, but must be overridden
1030 here for one reason or another. */
1031 {"align", s_align, 0},
1032 {"byte", s_cons, 0},
1033 {"data", s_change_sec, 'd'},
1034 {"double", s_float_cons, 'd'},
1035 {"float", s_float_cons, 'f'},
1036 {"globl", s_mips_globl, 0},
1037 {"global", s_mips_globl, 0},
1038 {"hword", s_cons, 1},
1040 {"long", s_cons, 2},
1041 {"octa", s_cons, 4},
1042 {"quad", s_cons, 3},
1043 {"section", s_change_section, 0},
1044 {"short", s_cons, 1},
1045 {"single", s_float_cons, 'f'},
1046 {"stabn", s_mips_stab, 'n'},
1047 {"text", s_change_sec, 't'},
1048 {"word", s_cons, 2},
1050 { "extern", ecoff_directive_extern, 0},
1055 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1057 /* These pseudo-ops should be defined by the object file format.
1058 However, a.out doesn't support them, so we have versions here. */
1059 {"aent", s_mips_ent, 1},
1060 {"bgnb", s_ignore, 0},
1061 {"end", s_mips_end, 0},
1062 {"endb", s_ignore, 0},
1063 {"ent", s_mips_ent, 0},
1064 {"file", s_mips_file, 0},
1065 {"fmask", s_mips_mask, 'F'},
1066 {"frame", s_mips_frame, 0},
1067 {"loc", s_mips_loc, 0},
1068 {"mask", s_mips_mask, 'R'},
1069 {"verstamp", s_ignore, 0},
1073 extern void pop_insert PARAMS ((const pseudo_typeS *));
1078 pop_insert (mips_pseudo_table);
1079 if (! ECOFF_DEBUGGING)
1080 pop_insert (mips_nonecoff_pseudo_table);
1083 /* Symbols labelling the current insn. */
1085 struct insn_label_list
1087 struct insn_label_list *next;
1091 static struct insn_label_list *insn_labels;
1092 static struct insn_label_list *free_insn_labels;
1094 static void mips_clear_insn_labels PARAMS ((void));
1097 mips_clear_insn_labels ()
1099 register struct insn_label_list **pl;
1101 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1107 static char *expr_end;
1109 /* Expressions which appear in instructions. These are set by
1112 static expressionS imm_expr;
1113 static expressionS offset_expr;
1115 /* Relocs associated with imm_expr and offset_expr. */
1117 static bfd_reloc_code_real_type imm_reloc[3]
1118 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1119 static bfd_reloc_code_real_type offset_reloc[3]
1120 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1122 /* These are set by mips16_ip if an explicit extension is used. */
1124 static bfd_boolean mips16_small, mips16_ext;
1127 /* The pdr segment for per procedure frame/regmask info. Not used for
1130 static segT pdr_seg;
1133 /* The default target format to use. */
1136 mips_target_format ()
1138 switch (OUTPUT_FLAVOR)
1140 case bfd_target_aout_flavour:
1141 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1142 case bfd_target_ecoff_flavour:
1143 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1144 case bfd_target_coff_flavour:
1146 case bfd_target_elf_flavour:
1148 /* This is traditional mips. */
1149 return (target_big_endian
1150 ? (HAVE_64BIT_OBJECTS
1151 ? "elf64-tradbigmips"
1153 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1154 : (HAVE_64BIT_OBJECTS
1155 ? "elf64-tradlittlemips"
1157 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1159 return (target_big_endian
1160 ? (HAVE_64BIT_OBJECTS
1163 ? "elf32-nbigmips" : "elf32-bigmips"))
1164 : (HAVE_64BIT_OBJECTS
1165 ? "elf64-littlemips"
1167 ? "elf32-nlittlemips" : "elf32-littlemips")));
1175 /* This function is called once, at assembler startup time. It should
1176 set up all the tables, etc. that the MD part of the assembler will need. */
1181 register const char *retval = NULL;
1185 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1186 as_warn (_("Could not set architecture and machine"));
1188 op_hash = hash_new ();
1190 for (i = 0; i < NUMOPCODES;)
1192 const char *name = mips_opcodes[i].name;
1194 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1197 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1198 mips_opcodes[i].name, retval);
1199 /* Probably a memory allocation problem? Give up now. */
1200 as_fatal (_("Broken assembler. No assembly attempted."));
1204 if (mips_opcodes[i].pinfo != INSN_MACRO)
1206 if (!validate_mips_insn (&mips_opcodes[i]))
1211 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1214 mips16_op_hash = hash_new ();
1217 while (i < bfd_mips16_num_opcodes)
1219 const char *name = mips16_opcodes[i].name;
1221 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1223 as_fatal (_("internal: can't hash `%s': %s"),
1224 mips16_opcodes[i].name, retval);
1227 if (mips16_opcodes[i].pinfo != INSN_MACRO
1228 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1229 != mips16_opcodes[i].match))
1231 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1232 mips16_opcodes[i].name, mips16_opcodes[i].args);
1237 while (i < bfd_mips16_num_opcodes
1238 && strcmp (mips16_opcodes[i].name, name) == 0);
1242 as_fatal (_("Broken assembler. No assembly attempted."));
1244 /* We add all the general register names to the symbol table. This
1245 helps us detect invalid uses of them. */
1246 for (i = 0; i < 32; i++)
1250 sprintf (buf, "$%d", i);
1251 symbol_table_insert (symbol_new (buf, reg_section, i,
1252 &zero_address_frag));
1254 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1255 &zero_address_frag));
1256 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1257 &zero_address_frag));
1258 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1259 &zero_address_frag));
1260 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1261 &zero_address_frag));
1262 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1263 &zero_address_frag));
1264 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1265 &zero_address_frag));
1266 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1267 &zero_address_frag));
1268 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1269 &zero_address_frag));
1270 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1271 &zero_address_frag));
1273 /* If we don't add these register names to the symbol table, they
1274 may end up being added as regular symbols by operand(), and then
1275 make it to the object file as undefined in case they're not
1276 regarded as local symbols. They're local in o32, since `$' is a
1277 local symbol prefix, but not in n32 or n64. */
1278 for (i = 0; i < 8; i++)
1282 sprintf (buf, "$fcc%i", i);
1283 symbol_table_insert (symbol_new (buf, reg_section, -1,
1284 &zero_address_frag));
1287 mips_no_prev_insn (FALSE);
1290 mips_cprmask[0] = 0;
1291 mips_cprmask[1] = 0;
1292 mips_cprmask[2] = 0;
1293 mips_cprmask[3] = 0;
1295 /* set the default alignment for the text section (2**2) */
1296 record_alignment (text_section, 2);
1298 if (USE_GLOBAL_POINTER_OPT)
1299 bfd_set_gp_size (stdoutput, g_switch_value);
1301 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1303 /* On a native system, sections must be aligned to 16 byte
1304 boundaries. When configured for an embedded ELF target, we
1306 if (strcmp (TARGET_OS, "elf") != 0)
1308 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1309 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1310 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1313 /* Create a .reginfo section for register masks and a .mdebug
1314 section for debugging information. */
1322 subseg = now_subseg;
1324 /* The ABI says this section should be loaded so that the
1325 running program can access it. However, we don't load it
1326 if we are configured for an embedded target */
1327 flags = SEC_READONLY | SEC_DATA;
1328 if (strcmp (TARGET_OS, "elf") != 0)
1329 flags |= SEC_ALLOC | SEC_LOAD;
1331 if (mips_abi != N64_ABI)
1333 sec = subseg_new (".reginfo", (subsegT) 0);
1335 bfd_set_section_flags (stdoutput, sec, flags);
1336 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1339 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1344 /* The 64-bit ABI uses a .MIPS.options section rather than
1345 .reginfo section. */
1346 sec = subseg_new (".MIPS.options", (subsegT) 0);
1347 bfd_set_section_flags (stdoutput, sec, flags);
1348 bfd_set_section_alignment (stdoutput, sec, 3);
1351 /* Set up the option header. */
1353 Elf_Internal_Options opthdr;
1356 opthdr.kind = ODK_REGINFO;
1357 opthdr.size = (sizeof (Elf_External_Options)
1358 + sizeof (Elf64_External_RegInfo));
1361 f = frag_more (sizeof (Elf_External_Options));
1362 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1363 (Elf_External_Options *) f);
1365 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1370 if (ECOFF_DEBUGGING)
1372 sec = subseg_new (".mdebug", (subsegT) 0);
1373 (void) bfd_set_section_flags (stdoutput, sec,
1374 SEC_HAS_CONTENTS | SEC_READONLY);
1375 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1378 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1380 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1381 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1382 SEC_READONLY | SEC_RELOC
1384 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1388 subseg_set (seg, subseg);
1392 if (! ECOFF_DEBUGGING)
1399 if (! ECOFF_DEBUGGING)
1407 struct mips_cl_insn insn;
1408 bfd_reloc_code_real_type unused_reloc[3]
1409 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1411 imm_expr.X_op = O_absent;
1412 offset_expr.X_op = O_absent;
1413 imm_reloc[0] = BFD_RELOC_UNUSED;
1414 imm_reloc[1] = BFD_RELOC_UNUSED;
1415 imm_reloc[2] = BFD_RELOC_UNUSED;
1416 offset_reloc[0] = BFD_RELOC_UNUSED;
1417 offset_reloc[1] = BFD_RELOC_UNUSED;
1418 offset_reloc[2] = BFD_RELOC_UNUSED;
1420 if (mips_opts.mips16)
1421 mips16_ip (str, &insn);
1424 mips_ip (str, &insn);
1425 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1426 str, insn.insn_opcode));
1431 as_bad ("%s `%s'", insn_error, str);
1435 if (insn.insn_mo->pinfo == INSN_MACRO)
1437 if (mips_opts.mips16)
1438 mips16_macro (&insn);
1444 if (imm_expr.X_op != O_absent)
1445 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1446 else if (offset_expr.X_op != O_absent)
1447 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1449 append_insn (NULL, &insn, NULL, unused_reloc);
1453 /* Return true if the given relocation might need a matching %lo().
1454 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1455 applied to local symbols. */
1457 static inline bfd_boolean
1458 reloc_needs_lo_p (reloc)
1459 bfd_reloc_code_real_type reloc;
1461 return (reloc == BFD_RELOC_HI16_S
1462 || reloc == BFD_RELOC_MIPS_GOT16);
1465 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1468 static inline bfd_boolean
1469 fixup_has_matching_lo_p (fixp)
1472 return (fixp->fx_next != NULL
1473 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1474 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1475 && fixp->fx_offset == fixp->fx_next->fx_offset);
1478 /* See whether instruction IP reads register REG. CLASS is the type
1482 insn_uses_reg (ip, reg, class)
1483 struct mips_cl_insn *ip;
1485 enum mips_regclass class;
1487 if (class == MIPS16_REG)
1489 assert (mips_opts.mips16);
1490 reg = mips16_to_32_reg_map[reg];
1491 class = MIPS_GR_REG;
1494 /* Don't report on general register ZERO, since it never changes. */
1495 if (class == MIPS_GR_REG && reg == ZERO)
1498 if (class == MIPS_FP_REG)
1500 assert (! mips_opts.mips16);
1501 /* If we are called with either $f0 or $f1, we must check $f0.
1502 This is not optimal, because it will introduce an unnecessary
1503 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1504 need to distinguish reading both $f0 and $f1 or just one of
1505 them. Note that we don't have to check the other way,
1506 because there is no instruction that sets both $f0 and $f1
1507 and requires a delay. */
1508 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1509 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1510 == (reg &~ (unsigned) 1)))
1512 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1513 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1514 == (reg &~ (unsigned) 1)))
1517 else if (! mips_opts.mips16)
1519 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1520 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1522 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1523 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1528 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1529 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1530 & MIPS16OP_MASK_RX)]
1533 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1534 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1535 & MIPS16OP_MASK_RY)]
1538 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1539 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1540 & MIPS16OP_MASK_MOVE32Z)]
1543 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1545 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1547 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1549 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1550 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1551 & MIPS16OP_MASK_REGR32) == reg)
1558 /* This function returns true if modifying a register requires a
1562 reg_needs_delay (reg)
1565 unsigned long prev_pinfo;
1567 prev_pinfo = prev_insn.insn_mo->pinfo;
1568 if (! mips_opts.noreorder
1569 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1570 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1571 || (! gpr_interlocks
1572 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1574 /* A load from a coprocessor or from memory. All load
1575 delays delay the use of general register rt for one
1576 instruction on the r3000. The r6000 and r4000 use
1578 /* Itbl support may require additional care here. */
1579 know (prev_pinfo & INSN_WRITE_GPR_T);
1580 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1587 /* Mark instruction labels in mips16 mode. This permits the linker to
1588 handle them specially, such as generating jalx instructions when
1589 needed. We also make them odd for the duration of the assembly, in
1590 order to generate the right sort of code. We will make them even
1591 in the adjust_symtab routine, while leaving them marked. This is
1592 convenient for the debugger and the disassembler. The linker knows
1593 to make them odd again. */
1596 mips16_mark_labels ()
1598 if (mips_opts.mips16)
1600 struct insn_label_list *l;
1603 for (l = insn_labels; l != NULL; l = l->next)
1606 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1607 S_SET_OTHER (l->label, STO_MIPS16);
1609 val = S_GET_VALUE (l->label);
1611 S_SET_VALUE (l->label, val + 1);
1616 /* Output an instruction. PLACE is where to put the instruction; if
1617 it is NULL, this uses frag_more to get room. IP is the instruction
1618 information. ADDRESS_EXPR is an operand of the instruction to be
1619 used with RELOC_TYPE. */
1622 append_insn (place, ip, address_expr, reloc_type)
1624 struct mips_cl_insn *ip;
1625 expressionS *address_expr;
1626 bfd_reloc_code_real_type *reloc_type;
1628 register unsigned long prev_pinfo, pinfo;
1633 /* Mark instruction labels in mips16 mode. */
1634 mips16_mark_labels ();
1636 prev_pinfo = prev_insn.insn_mo->pinfo;
1637 pinfo = ip->insn_mo->pinfo;
1639 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1643 /* If the previous insn required any delay slots, see if we need
1644 to insert a NOP or two. There are eight kinds of possible
1645 hazards, of which an instruction can have at most one type.
1646 (1) a load from memory delay
1647 (2) a load from a coprocessor delay
1648 (3) an unconditional branch delay
1649 (4) a conditional branch delay
1650 (5) a move to coprocessor register delay
1651 (6) a load coprocessor register from memory delay
1652 (7) a coprocessor condition code delay
1653 (8) a HI/LO special register delay
1655 There are a lot of optimizations we could do that we don't.
1656 In particular, we do not, in general, reorder instructions.
1657 If you use gcc with optimization, it will reorder
1658 instructions and generally do much more optimization then we
1659 do here; repeating all that work in the assembler would only
1660 benefit hand written assembly code, and does not seem worth
1663 /* This is how a NOP is emitted. */
1664 #define emit_nop() \
1666 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1667 : md_number_to_chars (frag_more (4), 0, 4))
1669 /* The previous insn might require a delay slot, depending upon
1670 the contents of the current insn. */
1671 if (! mips_opts.mips16
1672 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1673 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1674 && ! cop_interlocks)
1675 || (! gpr_interlocks
1676 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1678 /* A load from a coprocessor or from memory. All load
1679 delays delay the use of general register rt for one
1680 instruction on the r3000. The r6000 and r4000 use
1682 /* Itbl support may require additional care here. */
1683 know (prev_pinfo & INSN_WRITE_GPR_T);
1684 if (mips_optimize == 0
1685 || insn_uses_reg (ip,
1686 ((prev_insn.insn_opcode >> OP_SH_RT)
1691 else if (! mips_opts.mips16
1692 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1693 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1694 && ! cop_interlocks)
1695 || (mips_opts.isa == ISA_MIPS1
1696 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1698 /* A generic coprocessor delay. The previous instruction
1699 modified a coprocessor general or control register. If
1700 it modified a control register, we need to avoid any
1701 coprocessor instruction (this is probably not always
1702 required, but it sometimes is). If it modified a general
1703 register, we avoid using that register.
1705 On the r6000 and r4000 loading a coprocessor register
1706 from memory is interlocked, and does not require a delay.
1708 This case is not handled very well. There is no special
1709 knowledge of CP0 handling, and the coprocessors other
1710 than the floating point unit are not distinguished at
1712 /* Itbl support may require additional care here. FIXME!
1713 Need to modify this to include knowledge about
1714 user specified delays! */
1715 if (prev_pinfo & INSN_WRITE_FPR_T)
1717 if (mips_optimize == 0
1718 || insn_uses_reg (ip,
1719 ((prev_insn.insn_opcode >> OP_SH_FT)
1724 else if (prev_pinfo & INSN_WRITE_FPR_S)
1726 if (mips_optimize == 0
1727 || insn_uses_reg (ip,
1728 ((prev_insn.insn_opcode >> OP_SH_FS)
1735 /* We don't know exactly what the previous instruction
1736 does. If the current instruction uses a coprocessor
1737 register, we must insert a NOP. If previous
1738 instruction may set the condition codes, and the
1739 current instruction uses them, we must insert two
1741 /* Itbl support may require additional care here. */
1742 if (mips_optimize == 0
1743 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1744 && (pinfo & INSN_READ_COND_CODE)))
1746 else if (pinfo & INSN_COP)
1750 else if (! mips_opts.mips16
1751 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1752 && (prev_pinfo & INSN_WRITE_COND_CODE)
1753 && ! cop_interlocks)
1755 /* The previous instruction sets the coprocessor condition
1756 codes, but does not require a general coprocessor delay
1757 (this means it is a floating point comparison
1758 instruction). If this instruction uses the condition
1759 codes, we need to insert a single NOP. */
1760 /* Itbl support may require additional care here. */
1761 if (mips_optimize == 0
1762 || (pinfo & INSN_READ_COND_CODE))
1766 /* If we're fixing up mfhi/mflo for the r7000 and the
1767 previous insn was an mfhi/mflo and the current insn
1768 reads the register that the mfhi/mflo wrote to, then
1771 else if (mips_7000_hilo_fix
1772 && MF_HILO_INSN (prev_pinfo)
1773 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1780 /* If we're fixing up mfhi/mflo for the r7000 and the
1781 2nd previous insn was an mfhi/mflo and the current insn
1782 reads the register that the mfhi/mflo wrote to, then
1785 else if (mips_7000_hilo_fix
1786 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1787 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1795 else if (prev_pinfo & INSN_READ_LO)
1797 /* The previous instruction reads the LO register; if the
1798 current instruction writes to the LO register, we must
1799 insert two NOPS. Some newer processors have interlocks.
1800 Also the tx39's multiply instructions can be exectuted
1801 immediatly after a read from HI/LO (without the delay),
1802 though the tx39's divide insns still do require the
1804 if (! (hilo_interlocks
1805 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1806 && (mips_optimize == 0
1807 || (pinfo & INSN_WRITE_LO)))
1809 /* Most mips16 branch insns don't have a delay slot.
1810 If a read from LO is immediately followed by a branch
1811 to a write to LO we have a read followed by a write
1812 less than 2 insns away. We assume the target of
1813 a branch might be a write to LO, and insert a nop
1814 between a read and an immediately following branch. */
1815 else if (mips_opts.mips16
1816 && (mips_optimize == 0
1817 || (pinfo & MIPS16_INSN_BRANCH)))
1820 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1822 /* The previous instruction reads the HI register; if the
1823 current instruction writes to the HI register, we must
1824 insert a NOP. Some newer processors have interlocks.
1825 Also the note tx39's multiply above. */
1826 if (! (hilo_interlocks
1827 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1828 && (mips_optimize == 0
1829 || (pinfo & INSN_WRITE_HI)))
1831 /* Most mips16 branch insns don't have a delay slot.
1832 If a read from HI is immediately followed by a branch
1833 to a write to HI we have a read followed by a write
1834 less than 2 insns away. We assume the target of
1835 a branch might be a write to HI, and insert a nop
1836 between a read and an immediately following branch. */
1837 else if (mips_opts.mips16
1838 && (mips_optimize == 0
1839 || (pinfo & MIPS16_INSN_BRANCH)))
1843 /* If the previous instruction was in a noreorder section, then
1844 we don't want to insert the nop after all. */
1845 /* Itbl support may require additional care here. */
1846 if (prev_insn_unreordered)
1849 /* There are two cases which require two intervening
1850 instructions: 1) setting the condition codes using a move to
1851 coprocessor instruction which requires a general coprocessor
1852 delay and then reading the condition codes 2) reading the HI
1853 or LO register and then writing to it (except on processors
1854 which have interlocks). If we are not already emitting a NOP
1855 instruction, we must check for these cases compared to the
1856 instruction previous to the previous instruction. */
1857 if ((! mips_opts.mips16
1858 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1859 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1860 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1861 && (pinfo & INSN_READ_COND_CODE)
1862 && ! cop_interlocks)
1863 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1864 && (pinfo & INSN_WRITE_LO)
1865 && ! (hilo_interlocks
1866 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1867 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1868 && (pinfo & INSN_WRITE_HI)
1869 && ! (hilo_interlocks
1870 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1875 if (prev_prev_insn_unreordered)
1878 if (prev_prev_nop && nops == 0)
1881 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1883 /* We're out of bits in pinfo, so we must resort to string
1884 ops here. Shortcuts are selected based on opcodes being
1885 limited to the VR4122 instruction set. */
1887 const char *pn = prev_insn.insn_mo->name;
1888 const char *tn = ip->insn_mo->name;
1889 if (strncmp(pn, "macc", 4) == 0
1890 || strncmp(pn, "dmacc", 5) == 0)
1892 /* Errata 21 - [D]DIV[U] after [D]MACC */
1893 if (strstr (tn, "div"))
1898 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1899 if (pn[0] == 'd' /* dmacc */
1900 && (strncmp(tn, "dmult", 5) == 0
1901 || strncmp(tn, "dmacc", 5) == 0))
1906 /* Errata 24 - MT{LO,HI} after [D]MACC */
1907 if (strcmp (tn, "mtlo") == 0
1908 || strcmp (tn, "mthi") == 0)
1914 else if (strncmp(pn, "dmult", 5) == 0
1915 && (strncmp(tn, "dmult", 5) == 0
1916 || strncmp(tn, "dmacc", 5) == 0))
1918 /* Here is the rest of errata 23. */
1921 if (nops < min_nops)
1925 /* If we are being given a nop instruction, don't bother with
1926 one of the nops we would otherwise output. This will only
1927 happen when a nop instruction is used with mips_optimize set
1930 && ! mips_opts.noreorder
1931 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1934 /* Now emit the right number of NOP instructions. */
1935 if (nops > 0 && ! mips_opts.noreorder)
1938 unsigned long old_frag_offset;
1940 struct insn_label_list *l;
1942 old_frag = frag_now;
1943 old_frag_offset = frag_now_fix ();
1945 for (i = 0; i < nops; i++)
1950 listing_prev_line ();
1951 /* We may be at the start of a variant frag. In case we
1952 are, make sure there is enough space for the frag
1953 after the frags created by listing_prev_line. The
1954 argument to frag_grow here must be at least as large
1955 as the argument to all other calls to frag_grow in
1956 this file. We don't have to worry about being in the
1957 middle of a variant frag, because the variants insert
1958 all needed nop instructions themselves. */
1962 for (l = insn_labels; l != NULL; l = l->next)
1966 assert (S_GET_SEGMENT (l->label) == now_seg);
1967 symbol_set_frag (l->label, frag_now);
1968 val = (valueT) frag_now_fix ();
1969 /* mips16 text labels are stored as odd. */
1970 if (mips_opts.mips16)
1972 S_SET_VALUE (l->label, val);
1975 #ifndef NO_ECOFF_DEBUGGING
1976 if (ECOFF_DEBUGGING)
1977 ecoff_fix_loc (old_frag, old_frag_offset);
1980 else if (prev_nop_frag != NULL)
1982 /* We have a frag holding nops we may be able to remove. If
1983 we don't need any nops, we can decrease the size of
1984 prev_nop_frag by the size of one instruction. If we do
1985 need some nops, we count them in prev_nops_required. */
1986 if (prev_nop_frag_since == 0)
1990 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1991 --prev_nop_frag_holds;
1994 prev_nop_frag_required += nops;
1998 if (prev_prev_nop == 0)
2000 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2001 --prev_nop_frag_holds;
2004 ++prev_nop_frag_required;
2007 if (prev_nop_frag_holds <= prev_nop_frag_required)
2008 prev_nop_frag = NULL;
2010 ++prev_nop_frag_since;
2012 /* Sanity check: by the time we reach the second instruction
2013 after prev_nop_frag, we should have used up all the nops
2014 one way or another. */
2015 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2021 && (*reloc_type == BFD_RELOC_16_PCREL_S2
2022 || *reloc_type == BFD_RELOC_MIPSEMB_16_PCREL_S2)
2023 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2024 || pinfo & INSN_COND_BRANCH_LIKELY)
2025 && mips_relax_branch
2026 /* Don't try branch relaxation within .set nomacro, or within
2027 .set noat if we use $at for PIC computations. If it turns
2028 out that the branch was out-of-range, we'll get an error. */
2029 && !mips_opts.warn_about_macros
2030 && !(mips_opts.noat && mips_pic != NO_PIC)
2031 && !mips_opts.mips16)
2033 f = frag_var (rs_machine_dependent,
2034 relaxed_branch_length
2036 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2037 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2039 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2040 pinfo & INSN_COND_BRANCH_LIKELY,
2041 pinfo & INSN_WRITE_GPR_31,
2043 address_expr->X_add_symbol,
2044 address_expr->X_add_number,
2046 *reloc_type = BFD_RELOC_UNUSED;
2048 else if (*reloc_type > BFD_RELOC_UNUSED)
2050 /* We need to set up a variant frag. */
2051 assert (mips_opts.mips16 && address_expr != NULL);
2052 f = frag_var (rs_machine_dependent, 4, 0,
2053 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2054 mips16_small, mips16_ext,
2056 & INSN_UNCOND_BRANCH_DELAY),
2057 (*prev_insn_reloc_type
2058 == BFD_RELOC_MIPS16_JMP)),
2059 make_expr_symbol (address_expr), 0, NULL);
2061 else if (place != NULL)
2063 else if (mips_opts.mips16
2065 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2067 /* Make sure there is enough room to swap this instruction with
2068 a following jump instruction. */
2074 if (mips_opts.mips16
2075 && mips_opts.noreorder
2076 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2077 as_warn (_("extended instruction in delay slot"));
2082 fixp[0] = fixp[1] = fixp[2] = NULL;
2083 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2085 if (address_expr->X_op == O_constant)
2089 switch (*reloc_type)
2092 ip->insn_opcode |= address_expr->X_add_number;
2095 case BFD_RELOC_MIPS_HIGHEST:
2096 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2098 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2101 case BFD_RELOC_MIPS_HIGHER:
2102 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2103 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2106 case BFD_RELOC_HI16_S:
2107 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2111 case BFD_RELOC_HI16:
2112 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2115 case BFD_RELOC_LO16:
2116 case BFD_RELOC_MIPS_GOT_DISP:
2117 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2120 case BFD_RELOC_MIPS_JMP:
2121 if ((address_expr->X_add_number & 3) != 0)
2122 as_bad (_("jump to misaligned address (0x%lx)"),
2123 (unsigned long) address_expr->X_add_number);
2124 if (address_expr->X_add_number & ~0xfffffff)
2125 as_bad (_("jump address range overflow (0x%lx)"),
2126 (unsigned long) address_expr->X_add_number);
2127 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2130 case BFD_RELOC_MIPS16_JMP:
2131 if ((address_expr->X_add_number & 3) != 0)
2132 as_bad (_("jump to misaligned address (0x%lx)"),
2133 (unsigned long) address_expr->X_add_number);
2134 if (address_expr->X_add_number & ~0xfffffff)
2135 as_bad (_("jump address range overflow (0x%lx)"),
2136 (unsigned long) address_expr->X_add_number);
2138 (((address_expr->X_add_number & 0x7c0000) << 3)
2139 | ((address_expr->X_add_number & 0xf800000) >> 7)
2140 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2143 case BFD_RELOC_16_PCREL_S2:
2144 if ((address_expr->X_add_number & 3) != 0)
2145 as_bad (_("branch to misaligned address (0x%lx)"),
2146 (unsigned long) address_expr->X_add_number);
2147 if (mips_relax_branch)
2149 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
2150 as_bad (_("branch address range overflow (0x%lx)"),
2151 (unsigned long) address_expr->X_add_number);
2152 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
2155 case BFD_RELOC_MIPSEMB_16_PCREL_S2:
2165 /* Don't generate a reloc if we are writing into a variant frag. */
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2170 (*reloc_type == BFD_RELOC_16_PCREL_S2
2171 || *reloc_type == BFD_RELOC_MIPSEMB_16_PCREL_S2),
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2176 if (HAVE_64BIT_GPRS &&
2177 (*reloc_type == BFD_RELOC_16
2178 || *reloc_type == BFD_RELOC_32
2179 || *reloc_type == BFD_RELOC_MIPS_JMP
2180 || *reloc_type == BFD_RELOC_HI16_S
2181 || *reloc_type == BFD_RELOC_LO16
2182 || *reloc_type == BFD_RELOC_GPREL16
2183 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2184 || *reloc_type == BFD_RELOC_GPREL32
2185 || *reloc_type == BFD_RELOC_64
2186 || *reloc_type == BFD_RELOC_CTOR
2187 || *reloc_type == BFD_RELOC_MIPS_SUB
2188 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2189 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2190 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2191 || *reloc_type == BFD_RELOC_MIPS_REL16
2192 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2193 fixp[0]->fx_no_overflow = 1;
2195 if (reloc_needs_lo_p (*reloc_type))
2197 struct mips_hi_fixup *hi_fixup;
2199 /* Reuse the last entry if it already has a matching %lo. */
2200 hi_fixup = mips_hi_fixup_list;
2202 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2204 hi_fixup = ((struct mips_hi_fixup *)
2205 xmalloc (sizeof (struct mips_hi_fixup)));
2206 hi_fixup->next = mips_hi_fixup_list;
2207 mips_hi_fixup_list = hi_fixup;
2209 hi_fixup->fixp = fixp[0];
2210 hi_fixup->seg = now_seg;
2213 if (reloc_type[1] != BFD_RELOC_UNUSED)
2215 /* FIXME: This symbol can be one of
2216 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2217 address_expr->X_op = O_absent;
2218 address_expr->X_add_symbol = 0;
2219 address_expr->X_add_number = 0;
2221 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2222 4, address_expr, FALSE,
2225 /* These relocations can have an addend that won't fit in
2226 4 octets for 64bit assembly. */
2227 if (HAVE_64BIT_GPRS &&
2228 (*reloc_type == BFD_RELOC_16
2229 || *reloc_type == BFD_RELOC_32
2230 || *reloc_type == BFD_RELOC_MIPS_JMP
2231 || *reloc_type == BFD_RELOC_HI16_S
2232 || *reloc_type == BFD_RELOC_LO16
2233 || *reloc_type == BFD_RELOC_GPREL16
2234 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2235 || *reloc_type == BFD_RELOC_GPREL32
2236 || *reloc_type == BFD_RELOC_64
2237 || *reloc_type == BFD_RELOC_CTOR
2238 || *reloc_type == BFD_RELOC_MIPS_SUB
2239 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2240 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2241 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2242 || *reloc_type == BFD_RELOC_MIPS_REL16
2243 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2244 fixp[1]->fx_no_overflow = 1;
2246 if (reloc_type[2] != BFD_RELOC_UNUSED)
2248 address_expr->X_op = O_absent;
2249 address_expr->X_add_symbol = 0;
2250 address_expr->X_add_number = 0;
2252 fixp[2] = fix_new_exp (frag_now,
2253 f - frag_now->fr_literal, 4,
2254 address_expr, FALSE,
2257 /* These relocations can have an addend that won't fit in
2258 4 octets for 64bit assembly. */
2259 if (HAVE_64BIT_GPRS &&
2260 (*reloc_type == BFD_RELOC_16
2261 || *reloc_type == BFD_RELOC_32
2262 || *reloc_type == BFD_RELOC_MIPS_JMP
2263 || *reloc_type == BFD_RELOC_HI16_S
2264 || *reloc_type == BFD_RELOC_LO16
2265 || *reloc_type == BFD_RELOC_GPREL16
2266 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2267 || *reloc_type == BFD_RELOC_GPREL32
2268 || *reloc_type == BFD_RELOC_64
2269 || *reloc_type == BFD_RELOC_CTOR
2270 || *reloc_type == BFD_RELOC_MIPS_SUB
2271 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2272 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2273 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2274 || *reloc_type == BFD_RELOC_MIPS_REL16
2275 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2276 fixp[2]->fx_no_overflow = 1;
2283 if (! mips_opts.mips16)
2285 md_number_to_chars (f, ip->insn_opcode, 4);
2287 dwarf2_emit_insn (4);
2290 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2292 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2293 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2295 dwarf2_emit_insn (4);
2302 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2305 md_number_to_chars (f, ip->insn_opcode, 2);
2307 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2311 /* Update the register mask information. */
2312 if (! mips_opts.mips16)
2314 if (pinfo & INSN_WRITE_GPR_D)
2315 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2316 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2317 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2318 if (pinfo & INSN_READ_GPR_S)
2319 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2320 if (pinfo & INSN_WRITE_GPR_31)
2321 mips_gprmask |= 1 << RA;
2322 if (pinfo & INSN_WRITE_FPR_D)
2323 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2324 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2325 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2326 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2327 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2328 if ((pinfo & INSN_READ_FPR_R) != 0)
2329 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2330 if (pinfo & INSN_COP)
2332 /* We don't keep enough information to sort these cases out.
2333 The itbl support does keep this information however, although
2334 we currently don't support itbl fprmats as part of the cop
2335 instruction. May want to add this support in the future. */
2337 /* Never set the bit for $0, which is always zero. */
2338 mips_gprmask &= ~1 << 0;
2342 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2343 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2344 & MIPS16OP_MASK_RX);
2345 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2346 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2347 & MIPS16OP_MASK_RY);
2348 if (pinfo & MIPS16_INSN_WRITE_Z)
2349 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2350 & MIPS16OP_MASK_RZ);
2351 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2352 mips_gprmask |= 1 << TREG;
2353 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2354 mips_gprmask |= 1 << SP;
2355 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2356 mips_gprmask |= 1 << RA;
2357 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2358 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2359 if (pinfo & MIPS16_INSN_READ_Z)
2360 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2361 & MIPS16OP_MASK_MOVE32Z);
2362 if (pinfo & MIPS16_INSN_READ_GPR_X)
2363 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2364 & MIPS16OP_MASK_REGR32);
2367 if (place == NULL && ! mips_opts.noreorder)
2369 /* Filling the branch delay slot is more complex. We try to
2370 switch the branch with the previous instruction, which we can
2371 do if the previous instruction does not set up a condition
2372 that the branch tests and if the branch is not itself the
2373 target of any branch. */
2374 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2375 || (pinfo & INSN_COND_BRANCH_DELAY))
2377 if (mips_optimize < 2
2378 /* If we have seen .set volatile or .set nomove, don't
2380 || mips_opts.nomove != 0
2381 /* If we had to emit any NOP instructions, then we
2382 already know we can not swap. */
2384 /* If we don't even know the previous insn, we can not
2386 || ! prev_insn_valid
2387 /* If the previous insn is already in a branch delay
2388 slot, then we can not swap. */
2389 || prev_insn_is_delay_slot
2390 /* If the previous previous insn was in a .set
2391 noreorder, we can't swap. Actually, the MIPS
2392 assembler will swap in this situation. However, gcc
2393 configured -with-gnu-as will generate code like
2399 in which we can not swap the bne and INSN. If gcc is
2400 not configured -with-gnu-as, it does not output the
2401 .set pseudo-ops. We don't have to check
2402 prev_insn_unreordered, because prev_insn_valid will
2403 be 0 in that case. We don't want to use
2404 prev_prev_insn_valid, because we do want to be able
2405 to swap at the start of a function. */
2406 || prev_prev_insn_unreordered
2407 /* If the branch is itself the target of a branch, we
2408 can not swap. We cheat on this; all we check for is
2409 whether there is a label on this instruction. If
2410 there are any branches to anything other than a
2411 label, users must use .set noreorder. */
2412 || insn_labels != NULL
2413 /* If the previous instruction is in a variant frag, we
2414 can not do the swap. This does not apply to the
2415 mips16, which uses variant frags for different
2417 || (! mips_opts.mips16
2418 && prev_insn_frag->fr_type == rs_machine_dependent)
2419 /* If the branch reads the condition codes, we don't
2420 even try to swap, because in the sequence
2425 we can not swap, and I don't feel like handling that
2427 || (! mips_opts.mips16
2428 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2429 && (pinfo & INSN_READ_COND_CODE))
2430 /* We can not swap with an instruction that requires a
2431 delay slot, becase the target of the branch might
2432 interfere with that instruction. */
2433 || (! mips_opts.mips16
2434 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2436 /* Itbl support may require additional care here. */
2437 & (INSN_LOAD_COPROC_DELAY
2438 | INSN_COPROC_MOVE_DELAY
2439 | INSN_WRITE_COND_CODE)))
2440 || (! (hilo_interlocks
2441 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2445 || (! mips_opts.mips16
2447 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2448 || (! mips_opts.mips16
2449 && mips_opts.isa == ISA_MIPS1
2450 /* Itbl support may require additional care here. */
2451 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2452 /* We can not swap with a branch instruction. */
2454 & (INSN_UNCOND_BRANCH_DELAY
2455 | INSN_COND_BRANCH_DELAY
2456 | INSN_COND_BRANCH_LIKELY))
2457 /* We do not swap with a trap instruction, since it
2458 complicates trap handlers to have the trap
2459 instruction be in a delay slot. */
2460 || (prev_pinfo & INSN_TRAP)
2461 /* If the branch reads a register that the previous
2462 instruction sets, we can not swap. */
2463 || (! mips_opts.mips16
2464 && (prev_pinfo & INSN_WRITE_GPR_T)
2465 && insn_uses_reg (ip,
2466 ((prev_insn.insn_opcode >> OP_SH_RT)
2469 || (! mips_opts.mips16
2470 && (prev_pinfo & INSN_WRITE_GPR_D)
2471 && insn_uses_reg (ip,
2472 ((prev_insn.insn_opcode >> OP_SH_RD)
2475 || (mips_opts.mips16
2476 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2477 && insn_uses_reg (ip,
2478 ((prev_insn.insn_opcode
2480 & MIPS16OP_MASK_RX),
2482 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2483 && insn_uses_reg (ip,
2484 ((prev_insn.insn_opcode
2486 & MIPS16OP_MASK_RY),
2488 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2489 && insn_uses_reg (ip,
2490 ((prev_insn.insn_opcode
2492 & MIPS16OP_MASK_RZ),
2494 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2495 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2496 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2497 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2498 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2499 && insn_uses_reg (ip,
2500 MIPS16OP_EXTRACT_REG32R (prev_insn.
2503 /* If the branch writes a register that the previous
2504 instruction sets, we can not swap (we know that
2505 branches write only to RD or to $31). */
2506 || (! mips_opts.mips16
2507 && (prev_pinfo & INSN_WRITE_GPR_T)
2508 && (((pinfo & INSN_WRITE_GPR_D)
2509 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2510 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2511 || ((pinfo & INSN_WRITE_GPR_31)
2512 && (((prev_insn.insn_opcode >> OP_SH_RT)
2515 || (! mips_opts.mips16
2516 && (prev_pinfo & INSN_WRITE_GPR_D)
2517 && (((pinfo & INSN_WRITE_GPR_D)
2518 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2519 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2520 || ((pinfo & INSN_WRITE_GPR_31)
2521 && (((prev_insn.insn_opcode >> OP_SH_RD)
2524 || (mips_opts.mips16
2525 && (pinfo & MIPS16_INSN_WRITE_31)
2526 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2527 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2528 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2530 /* If the branch writes a register that the previous
2531 instruction reads, we can not swap (we know that
2532 branches only write to RD or to $31). */
2533 || (! mips_opts.mips16
2534 && (pinfo & INSN_WRITE_GPR_D)
2535 && insn_uses_reg (&prev_insn,
2536 ((ip->insn_opcode >> OP_SH_RD)
2539 || (! mips_opts.mips16
2540 && (pinfo & INSN_WRITE_GPR_31)
2541 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2542 || (mips_opts.mips16
2543 && (pinfo & MIPS16_INSN_WRITE_31)
2544 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2545 /* If we are generating embedded PIC code, the branch
2546 might be expanded into a sequence which uses $at, so
2547 we can't swap with an instruction which reads it. */
2548 || (mips_pic == EMBEDDED_PIC
2549 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2550 /* If the previous previous instruction has a load
2551 delay, and sets a register that the branch reads, we
2553 || (! mips_opts.mips16
2554 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2555 /* Itbl support may require additional care here. */
2556 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2557 || (! gpr_interlocks
2558 && (prev_prev_insn.insn_mo->pinfo
2559 & INSN_LOAD_MEMORY_DELAY)))
2560 && insn_uses_reg (ip,
2561 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2564 /* If one instruction sets a condition code and the
2565 other one uses a condition code, we can not swap. */
2566 || ((pinfo & INSN_READ_COND_CODE)
2567 && (prev_pinfo & INSN_WRITE_COND_CODE))
2568 || ((pinfo & INSN_WRITE_COND_CODE)
2569 && (prev_pinfo & INSN_READ_COND_CODE))
2570 /* If the previous instruction uses the PC, we can not
2572 || (mips_opts.mips16
2573 && (prev_pinfo & MIPS16_INSN_READ_PC))
2574 /* If the previous instruction was extended, we can not
2576 || (mips_opts.mips16 && prev_insn_extended)
2577 /* If the previous instruction had a fixup in mips16
2578 mode, we can not swap. This normally means that the
2579 previous instruction was a 4 byte branch anyhow. */
2580 || (mips_opts.mips16 && prev_insn_fixp[0])
2581 /* If the previous instruction is a sync, sync.l, or
2582 sync.p, we can not swap. */
2583 || (prev_pinfo & INSN_SYNC))
2585 /* We could do even better for unconditional branches to
2586 portions of this object file; we could pick up the
2587 instruction at the destination, put it in the delay
2588 slot, and bump the destination address. */
2590 /* Update the previous insn information. */
2591 prev_prev_insn = *ip;
2592 prev_insn.insn_mo = &dummy_opcode;
2596 /* It looks like we can actually do the swap. */
2597 if (! mips_opts.mips16)
2602 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2603 memcpy (temp, prev_f, 4);
2604 memcpy (prev_f, f, 4);
2605 memcpy (f, temp, 4);
2606 if (prev_insn_fixp[0])
2608 prev_insn_fixp[0]->fx_frag = frag_now;
2609 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2611 if (prev_insn_fixp[1])
2613 prev_insn_fixp[1]->fx_frag = frag_now;
2614 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2616 if (prev_insn_fixp[2])
2618 prev_insn_fixp[2]->fx_frag = frag_now;
2619 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2623 fixp[0]->fx_frag = prev_insn_frag;
2624 fixp[0]->fx_where = prev_insn_where;
2628 fixp[1]->fx_frag = prev_insn_frag;
2629 fixp[1]->fx_where = prev_insn_where;
2633 fixp[2]->fx_frag = prev_insn_frag;
2634 fixp[2]->fx_where = prev_insn_where;
2642 assert (prev_insn_fixp[0] == NULL);
2643 assert (prev_insn_fixp[1] == NULL);
2644 assert (prev_insn_fixp[2] == NULL);
2645 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2646 memcpy (temp, prev_f, 2);
2647 memcpy (prev_f, f, 2);
2648 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2650 assert (*reloc_type == BFD_RELOC_UNUSED);
2651 memcpy (f, temp, 2);
2655 memcpy (f, f + 2, 2);
2656 memcpy (f + 2, temp, 2);
2660 fixp[0]->fx_frag = prev_insn_frag;
2661 fixp[0]->fx_where = prev_insn_where;
2665 fixp[1]->fx_frag = prev_insn_frag;
2666 fixp[1]->fx_where = prev_insn_where;
2670 fixp[2]->fx_frag = prev_insn_frag;
2671 fixp[2]->fx_where = prev_insn_where;
2675 /* Update the previous insn information; leave prev_insn
2677 prev_prev_insn = *ip;
2679 prev_insn_is_delay_slot = 1;
2681 /* If that was an unconditional branch, forget the previous
2682 insn information. */
2683 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2685 prev_prev_insn.insn_mo = &dummy_opcode;
2686 prev_insn.insn_mo = &dummy_opcode;
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2697 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2699 /* We don't yet optimize a branch likely. What we should do
2700 is look at the target, copy the instruction found there
2701 into the delay slot, and increment the branch to jump to
2702 the next instruction. */
2704 /* Update the previous insn information. */
2705 prev_prev_insn = *ip;
2706 prev_insn.insn_mo = &dummy_opcode;
2707 prev_insn_fixp[0] = NULL;
2708 prev_insn_fixp[1] = NULL;
2709 prev_insn_fixp[2] = NULL;
2710 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2711 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2712 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2713 prev_insn_extended = 0;
2717 /* Update the previous insn information. */
2719 prev_prev_insn.insn_mo = &dummy_opcode;
2721 prev_prev_insn = prev_insn;
2724 /* Any time we see a branch, we always fill the delay slot
2725 immediately; since this insn is not a branch, we know it
2726 is not in a delay slot. */
2727 prev_insn_is_delay_slot = 0;
2729 prev_insn_fixp[0] = fixp[0];
2730 prev_insn_fixp[1] = fixp[1];
2731 prev_insn_fixp[2] = fixp[2];
2732 prev_insn_reloc_type[0] = reloc_type[0];
2733 prev_insn_reloc_type[1] = reloc_type[1];
2734 prev_insn_reloc_type[2] = reloc_type[2];
2735 if (mips_opts.mips16)
2736 prev_insn_extended = (ip->use_extend
2737 || *reloc_type > BFD_RELOC_UNUSED);
2740 prev_prev_insn_unreordered = prev_insn_unreordered;
2741 prev_insn_unreordered = 0;
2742 prev_insn_frag = frag_now;
2743 prev_insn_where = f - frag_now->fr_literal;
2744 prev_insn_valid = 1;
2746 else if (place == NULL)
2748 /* We need to record a bit of information even when we are not
2749 reordering, in order to determine the base address for mips16
2750 PC relative relocs. */
2751 prev_prev_insn = prev_insn;
2753 prev_insn_reloc_type[0] = reloc_type[0];
2754 prev_insn_reloc_type[1] = reloc_type[1];
2755 prev_insn_reloc_type[2] = reloc_type[2];
2756 prev_prev_insn_unreordered = prev_insn_unreordered;
2757 prev_insn_unreordered = 1;
2760 /* We just output an insn, so the next one doesn't have a label. */
2761 mips_clear_insn_labels ();
2764 /* This function forgets that there was any previous instruction or
2765 label. If PRESERVE is non-zero, it remembers enough information to
2766 know whether nops are needed before a noreorder section. */
2769 mips_no_prev_insn (preserve)
2774 prev_insn.insn_mo = &dummy_opcode;
2775 prev_prev_insn.insn_mo = &dummy_opcode;
2776 prev_nop_frag = NULL;
2777 prev_nop_frag_holds = 0;
2778 prev_nop_frag_required = 0;
2779 prev_nop_frag_since = 0;
2781 prev_insn_valid = 0;
2782 prev_insn_is_delay_slot = 0;
2783 prev_insn_unreordered = 0;
2784 prev_insn_extended = 0;
2785 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2786 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2787 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2788 prev_prev_insn_unreordered = 0;
2789 mips_clear_insn_labels ();
2792 /* This function must be called whenever we turn on noreorder or emit
2793 something other than instructions. It inserts any NOPS which might
2794 be needed by the previous instruction, and clears the information
2795 kept for the previous instructions. The INSNS parameter is true if
2796 instructions are to follow. */
2799 mips_emit_delays (insns)
2802 if (! mips_opts.noreorder)
2807 if ((! mips_opts.mips16
2808 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2809 && (! cop_interlocks
2810 && (prev_insn.insn_mo->pinfo
2811 & (INSN_LOAD_COPROC_DELAY
2812 | INSN_COPROC_MOVE_DELAY
2813 | INSN_WRITE_COND_CODE))))
2814 || (! hilo_interlocks
2815 && (prev_insn.insn_mo->pinfo
2818 || (! mips_opts.mips16
2820 && (prev_insn.insn_mo->pinfo
2821 & INSN_LOAD_MEMORY_DELAY))
2822 || (! mips_opts.mips16
2823 && mips_opts.isa == ISA_MIPS1
2824 && (prev_insn.insn_mo->pinfo
2825 & INSN_COPROC_MEMORY_DELAY)))
2827 /* Itbl support may require additional care here. */
2829 if ((! mips_opts.mips16
2830 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2831 && (! cop_interlocks
2832 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2833 || (! hilo_interlocks
2834 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2835 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2838 if (prev_insn_unreordered)
2841 else if ((! mips_opts.mips16
2842 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2843 && (! cop_interlocks
2844 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2845 || (! hilo_interlocks
2846 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2847 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2849 /* Itbl support may require additional care here. */
2850 if (! prev_prev_insn_unreordered)
2854 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2857 const char *pn = prev_insn.insn_mo->name;
2858 if (strncmp(pn, "macc", 4) == 0
2859 || strncmp(pn, "dmacc", 5) == 0
2860 || strncmp(pn, "dmult", 5) == 0)
2864 if (nops < min_nops)
2870 struct insn_label_list *l;
2874 /* Record the frag which holds the nop instructions, so
2875 that we can remove them if we don't need them. */
2876 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2877 prev_nop_frag = frag_now;
2878 prev_nop_frag_holds = nops;
2879 prev_nop_frag_required = 0;
2880 prev_nop_frag_since = 0;
2883 for (; nops > 0; --nops)
2888 /* Move on to a new frag, so that it is safe to simply
2889 decrease the size of prev_nop_frag. */
2890 frag_wane (frag_now);
2894 for (l = insn_labels; l != NULL; l = l->next)
2898 assert (S_GET_SEGMENT (l->label) == now_seg);
2899 symbol_set_frag (l->label, frag_now);
2900 val = (valueT) frag_now_fix ();
2901 /* mips16 text labels are stored as odd. */
2902 if (mips_opts.mips16)
2904 S_SET_VALUE (l->label, val);
2909 /* Mark instruction labels in mips16 mode. */
2911 mips16_mark_labels ();
2913 mips_no_prev_insn (insns);
2916 /* Build an instruction created by a macro expansion. This is passed
2917 a pointer to the count of instructions created so far, an
2918 expression, the name of the instruction to build, an operand format
2919 string, and corresponding arguments. */
2923 macro_build (char *place,
2931 macro_build (place, counter, ep, name, fmt, va_alist)
2940 struct mips_cl_insn insn;
2941 bfd_reloc_code_real_type r[3];
2945 va_start (args, fmt);
2951 * If the macro is about to expand into a second instruction,
2952 * print a warning if needed. We need to pass ip as a parameter
2953 * to generate a better warning message here...
2955 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2956 as_warn (_("Macro instruction expanded into multiple instructions"));
2959 * If the macro is about to expand into a second instruction,
2960 * and it is in a delay slot, print a warning.
2964 && mips_opts.noreorder
2965 && (prev_prev_insn.insn_mo->pinfo
2966 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2967 | INSN_COND_BRANCH_LIKELY)) != 0)
2968 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2971 ++*counter; /* bump instruction counter */
2973 if (mips_opts.mips16)
2975 mips16_macro_build (place, counter, ep, name, fmt, args);
2980 r[0] = BFD_RELOC_UNUSED;
2981 r[1] = BFD_RELOC_UNUSED;
2982 r[2] = BFD_RELOC_UNUSED;
2983 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2984 assert (insn.insn_mo);
2985 assert (strcmp (name, insn.insn_mo->name) == 0);
2987 /* Search until we get a match for NAME. */
2990 /* It is assumed here that macros will never generate
2991 MDMX or MIPS-3D instructions. */
2992 if (strcmp (fmt, insn.insn_mo->args) == 0
2993 && insn.insn_mo->pinfo != INSN_MACRO
2994 && OPCODE_IS_MEMBER (insn.insn_mo,
2996 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2998 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3002 assert (insn.insn_mo->name);
3003 assert (strcmp (name, insn.insn_mo->name) == 0);
3006 insn.insn_opcode = insn.insn_mo->match;
3022 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3026 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3031 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3037 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3042 int tmp = va_arg (args, int);
3044 insn.insn_opcode |= tmp << OP_SH_RT;
3045 insn.insn_opcode |= tmp << OP_SH_RD;
3051 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3058 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3062 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3066 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3070 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3074 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3081 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3087 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3088 assert (*r == BFD_RELOC_GPREL16
3089 || *r == BFD_RELOC_MIPS_LITERAL
3090 || *r == BFD_RELOC_MIPS_HIGHER
3091 || *r == BFD_RELOC_HI16_S
3092 || *r == BFD_RELOC_LO16
3093 || *r == BFD_RELOC_MIPS_GOT16
3094 || *r == BFD_RELOC_MIPS_CALL16
3095 || *r == BFD_RELOC_MIPS_GOT_DISP
3096 || *r == BFD_RELOC_MIPS_GOT_PAGE
3097 || *r == BFD_RELOC_MIPS_GOT_OFST
3098 || *r == BFD_RELOC_MIPS_GOT_LO16
3099 || *r == BFD_RELOC_MIPS_CALL_LO16
3100 || (ep->X_op == O_subtract
3101 && *r == BFD_RELOC_PCREL_LO16));
3105 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3107 && (ep->X_op == O_constant
3108 || (ep->X_op == O_symbol
3109 && (*r == BFD_RELOC_MIPS_HIGHEST
3110 || *r == BFD_RELOC_HI16_S
3111 || *r == BFD_RELOC_HI16
3112 || *r == BFD_RELOC_GPREL16
3113 || *r == BFD_RELOC_MIPS_GOT_HI16
3114 || *r == BFD_RELOC_MIPS_CALL_HI16))
3115 || (ep->X_op == O_subtract
3116 && *r == BFD_RELOC_PCREL_HI16_S)));
3120 assert (ep != NULL);
3123 * This allows macro() to pass an immediate expression for
3124 * creating short branches without creating a symbol.
3126 * We don't allow branch relaxation for these branches, as
3127 * they should only appear in ".set nomacro" anyway.
3129 if (ep->X_op == O_constant)
3131 if ((ep->X_add_number & 3) != 0)
3132 as_bad (_("branch to misaligned address (0x%lx)"),
3133 (unsigned long) ep->X_add_number);
3134 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3135 as_bad (_("branch address range overflow (0x%lx)"),
3136 (unsigned long) ep->X_add_number);
3137 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3142 if (mips_pic == EMBEDDED_PIC)
3143 *r = BFD_RELOC_MIPSEMB_16_PCREL_S2;
3145 *r = BFD_RELOC_16_PCREL_S2;
3150 assert (ep != NULL);
3151 *r = BFD_RELOC_MIPS_JMP;
3155 insn.insn_opcode |= va_arg (args, unsigned long);
3164 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3166 append_insn (place, &insn, ep, r);
3170 mips16_macro_build (place, counter, ep, name, fmt, args)
3172 int *counter ATTRIBUTE_UNUSED;
3178 struct mips_cl_insn insn;
3179 bfd_reloc_code_real_type r[3]
3180 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3182 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3183 assert (insn.insn_mo);
3184 assert (strcmp (name, insn.insn_mo->name) == 0);
3186 while (strcmp (fmt, insn.insn_mo->args) != 0
3187 || insn.insn_mo->pinfo == INSN_MACRO)
3190 assert (insn.insn_mo->name);
3191 assert (strcmp (name, insn.insn_mo->name) == 0);
3194 insn.insn_opcode = insn.insn_mo->match;
3195 insn.use_extend = FALSE;
3214 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3219 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3223 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3227 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3237 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3244 regno = va_arg (args, int);
3245 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3246 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3267 assert (ep != NULL);
3269 if (ep->X_op != O_constant)
3270 *r = (int) BFD_RELOC_UNUSED + c;
3273 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3274 FALSE, &insn.insn_opcode, &insn.use_extend,
3277 *r = BFD_RELOC_UNUSED;
3283 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3290 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3292 append_insn (place, &insn, ep, r);
3296 * Generate a "jalr" instruction with a relocation hint to the called
3297 * function. This occurs in NewABI PIC code.
3300 macro_build_jalr (icnt, ep)
3311 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3314 fix_new_exp (frag_now, f - frag_now->fr_literal,
3315 0, ep, FALSE, BFD_RELOC_MIPS_JALR);
3319 * Generate a "lui" instruction.
3322 macro_build_lui (place, counter, ep, regnum)
3328 expressionS high_expr;
3329 struct mips_cl_insn insn;
3330 bfd_reloc_code_real_type r[3]
3331 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3332 const char *name = "lui";
3333 const char *fmt = "t,u";
3335 assert (! mips_opts.mips16);
3341 high_expr.X_op = O_constant;
3342 high_expr.X_add_number = ep->X_add_number;
3345 if (high_expr.X_op == O_constant)
3347 /* we can compute the instruction now without a relocation entry */
3348 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3350 *r = BFD_RELOC_UNUSED;
3354 assert (ep->X_op == O_symbol);
3355 /* _gp_disp is a special case, used from s_cpload. */
3356 assert (mips_pic == NO_PIC
3358 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3359 *r = BFD_RELOC_HI16_S;
3363 * If the macro is about to expand into a second instruction,
3364 * print a warning if needed. We need to pass ip as a parameter
3365 * to generate a better warning message here...
3367 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3368 as_warn (_("Macro instruction expanded into multiple instructions"));
3371 ++*counter; /* bump instruction counter */
3373 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3374 assert (insn.insn_mo);
3375 assert (strcmp (name, insn.insn_mo->name) == 0);
3376 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3378 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3379 if (*r == BFD_RELOC_UNUSED)
3381 insn.insn_opcode |= high_expr.X_add_number;
3382 append_insn (place, &insn, NULL, r);
3385 append_insn (place, &insn, &high_expr, r);
3388 /* Generate a sequence of instructions to do a load or store from a constant
3389 offset off of a base register (breg) into/from a target register (treg),
3390 using AT if necessary. */
3392 macro_build_ldst_constoffset (place, counter, ep, op, treg, breg)
3399 assert (ep->X_op == O_constant);
3401 /* Right now, this routine can only handle signed 32-bit contants. */
3402 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3403 as_warn (_("operand overflow"));
3405 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3407 /* Signed 16-bit offset will fit in the op. Easy! */
3408 macro_build (place, counter, ep, op, "t,o(b)", treg,
3409 (int) BFD_RELOC_LO16, breg);
3413 /* 32-bit offset, need multiple instructions and AT, like:
3414 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3415 addu $tempreg,$tempreg,$breg
3416 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3417 to handle the complete offset. */
3418 macro_build_lui (place, counter, ep, AT);
3421 macro_build (place, counter, (expressionS *) NULL,
3422 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
3423 "d,v,t", AT, AT, breg);
3426 macro_build (place, counter, ep, op, "t,o(b)", treg,
3427 (int) BFD_RELOC_LO16, AT);
3430 as_warn (_("Macro used $at after \".set noat\""));
3435 * Generates code to set the $at register to true (one)
3436 * if reg is less than the immediate expression.
3439 set_at (counter, reg, unsignedp)
3444 if (imm_expr.X_op == O_constant
3445 && imm_expr.X_add_number >= -0x8000
3446 && imm_expr.X_add_number < 0x8000)
3447 macro_build ((char *) NULL, counter, &imm_expr,
3448 unsignedp ? "sltiu" : "slti",
3449 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3452 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3453 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3454 unsignedp ? "sltu" : "slt",
3455 "d,v,t", AT, reg, AT);
3459 /* Warn if an expression is not a constant. */
3462 check_absolute_expr (ip, ex)
3463 struct mips_cl_insn *ip;
3466 if (ex->X_op == O_big)
3467 as_bad (_("unsupported large constant"));
3468 else if (ex->X_op != O_constant)
3469 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3472 /* Count the leading zeroes by performing a binary chop. This is a
3473 bulky bit of source, but performance is a LOT better for the
3474 majority of values than a simple loop to count the bits:
3475 for (lcnt = 0; (lcnt < 32); lcnt++)
3476 if ((v) & (1 << (31 - lcnt)))
3478 However it is not code size friendly, and the gain will drop a bit
3479 on certain cached systems.
3481 #define COUNT_TOP_ZEROES(v) \
3482 (((v) & ~0xffff) == 0 \
3483 ? ((v) & ~0xff) == 0 \
3484 ? ((v) & ~0xf) == 0 \
3485 ? ((v) & ~0x3) == 0 \
3486 ? ((v) & ~0x1) == 0 \
3491 : ((v) & ~0x7) == 0 \
3494 : ((v) & ~0x3f) == 0 \
3495 ? ((v) & ~0x1f) == 0 \
3498 : ((v) & ~0x7f) == 0 \
3501 : ((v) & ~0xfff) == 0 \
3502 ? ((v) & ~0x3ff) == 0 \
3503 ? ((v) & ~0x1ff) == 0 \
3506 : ((v) & ~0x7ff) == 0 \
3509 : ((v) & ~0x3fff) == 0 \
3510 ? ((v) & ~0x1fff) == 0 \
3513 : ((v) & ~0x7fff) == 0 \
3516 : ((v) & ~0xffffff) == 0 \
3517 ? ((v) & ~0xfffff) == 0 \
3518 ? ((v) & ~0x3ffff) == 0 \
3519 ? ((v) & ~0x1ffff) == 0 \
3522 : ((v) & ~0x7ffff) == 0 \
3525 : ((v) & ~0x3fffff) == 0 \
3526 ? ((v) & ~0x1fffff) == 0 \
3529 : ((v) & ~0x7fffff) == 0 \
3532 : ((v) & ~0xfffffff) == 0 \
3533 ? ((v) & ~0x3ffffff) == 0 \
3534 ? ((v) & ~0x1ffffff) == 0 \
3537 : ((v) & ~0x7ffffff) == 0 \
3540 : ((v) & ~0x3fffffff) == 0 \
3541 ? ((v) & ~0x1fffffff) == 0 \
3544 : ((v) & ~0x7fffffff) == 0 \
3549 * This routine generates the least number of instructions neccessary to load
3550 * an absolute expression value into a register.
3553 load_register (counter, reg, ep, dbl)
3560 expressionS hi32, lo32;
3562 if (ep->X_op != O_big)
3564 assert (ep->X_op == O_constant);
3565 if (ep->X_add_number < 0x8000
3566 && (ep->X_add_number >= 0
3567 || (ep->X_add_number >= -0x8000
3570 || sizeof (ep->X_add_number) > 4))))
3572 /* We can handle 16 bit signed values with an addiu to
3573 $zero. No need to ever use daddiu here, since $zero and
3574 the result are always correct in 32 bit mode. */
3575 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3576 (int) BFD_RELOC_LO16);
3579 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3581 /* We can handle 16 bit unsigned values with an ori to
3583 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3584 (int) BFD_RELOC_LO16);
3587 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3590 || sizeof (ep->X_add_number) > 4
3591 || (ep->X_add_number & 0x80000000) == 0))
3592 || ((HAVE_32BIT_GPRS || ! dbl)
3593 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3596 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3597 == ~ (offsetT) 0xffffffff)))
3599 /* 32 bit values require an lui. */
3600 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3601 (int) BFD_RELOC_HI16);
3602 if ((ep->X_add_number & 0xffff) != 0)
3603 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3604 (int) BFD_RELOC_LO16);
3609 /* The value is larger than 32 bits. */
3611 if (HAVE_32BIT_GPRS)
3613 as_bad (_("Number (0x%lx) larger than 32 bits"),
3614 (unsigned long) ep->X_add_number);
3615 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3616 (int) BFD_RELOC_LO16);
3620 if (ep->X_op != O_big)
3623 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3624 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3625 hi32.X_add_number &= 0xffffffff;
3627 lo32.X_add_number &= 0xffffffff;
3631 assert (ep->X_add_number > 2);
3632 if (ep->X_add_number == 3)
3633 generic_bignum[3] = 0;
3634 else if (ep->X_add_number > 4)
3635 as_bad (_("Number larger than 64 bits"));
3636 lo32.X_op = O_constant;
3637 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3638 hi32.X_op = O_constant;
3639 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3642 if (hi32.X_add_number == 0)
3647 unsigned long hi, lo;
3649 if (hi32.X_add_number == (offsetT) 0xffffffff)
3651 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3653 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3654 reg, 0, (int) BFD_RELOC_LO16);
3657 if (lo32.X_add_number & 0x80000000)
3659 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3660 (int) BFD_RELOC_HI16);
3661 if (lo32.X_add_number & 0xffff)
3662 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3663 reg, reg, (int) BFD_RELOC_LO16);
3668 /* Check for 16bit shifted constant. We know that hi32 is
3669 non-zero, so start the mask on the first bit of the hi32
3674 unsigned long himask, lomask;
3678 himask = 0xffff >> (32 - shift);
3679 lomask = (0xffff << shift) & 0xffffffff;
3683 himask = 0xffff << (shift - 32);
3686 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3687 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3691 tmp.X_op = O_constant;
3693 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3694 | (lo32.X_add_number >> shift));
3696 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3697 macro_build ((char *) NULL, counter, &tmp,
3698 "ori", "t,r,i", reg, 0,
3699 (int) BFD_RELOC_LO16);
3700 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3701 (shift >= 32) ? "dsll32" : "dsll",
3703 (shift >= 32) ? shift - 32 : shift);
3708 while (shift <= (64 - 16));
3710 /* Find the bit number of the lowest one bit, and store the
3711 shifted value in hi/lo. */
3712 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3713 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3717 while ((lo & 1) == 0)
3722 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3728 while ((hi & 1) == 0)
3737 /* Optimize if the shifted value is a (power of 2) - 1. */
3738 if ((hi == 0 && ((lo + 1) & lo) == 0)
3739 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3741 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3746 /* This instruction will set the register to be all
3748 tmp.X_op = O_constant;
3749 tmp.X_add_number = (offsetT) -1;
3750 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3751 reg, 0, (int) BFD_RELOC_LO16);
3755 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3756 (bit >= 32) ? "dsll32" : "dsll",
3758 (bit >= 32) ? bit - 32 : bit);
3760 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3761 (shift >= 32) ? "dsrl32" : "dsrl",
3763 (shift >= 32) ? shift - 32 : shift);
3768 /* Sign extend hi32 before calling load_register, because we can
3769 generally get better code when we load a sign extended value. */
3770 if ((hi32.X_add_number & 0x80000000) != 0)
3771 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3772 load_register (counter, reg, &hi32, 0);
3775 if ((lo32.X_add_number & 0xffff0000) == 0)
3779 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3780 "dsll32", "d,w,<", reg, freg, 0);
3788 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3790 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3791 (int) BFD_RELOC_HI16);
3792 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3793 "dsrl32", "d,w,<", reg, reg, 0);
3799 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3800 "d,w,<", reg, freg, 16);
3804 mid16.X_add_number >>= 16;
3805 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3806 freg, (int) BFD_RELOC_LO16);
3807 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3808 "d,w,<", reg, reg, 16);
3811 if ((lo32.X_add_number & 0xffff) != 0)
3812 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3813 (int) BFD_RELOC_LO16);
3816 /* Load an address into a register. */
3819 load_address (counter, reg, ep, used_at)
3827 if (ep->X_op != O_constant
3828 && ep->X_op != O_symbol)
3830 as_bad (_("expression too complex"));
3831 ep->X_op = O_constant;
3834 if (ep->X_op == O_constant)
3836 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3840 if (mips_pic == NO_PIC)
3842 /* If this is a reference to a GP relative symbol, we want
3843 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3845 lui $reg,<sym> (BFD_RELOC_HI16_S)
3846 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3847 If we have an addend, we always use the latter form.
3849 With 64bit address space and a usable $at we want
3850 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3851 lui $at,<sym> (BFD_RELOC_HI16_S)
3852 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3853 daddiu $at,<sym> (BFD_RELOC_LO16)
3857 If $at is already in use, we use a path which is suboptimal
3858 on superscalar processors.
3859 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3860 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3862 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3864 daddiu $reg,<sym> (BFD_RELOC_LO16)
3866 if (HAVE_64BIT_ADDRESSES)
3868 /* We don't do GP optimization for now because RELAX_ENCODE can't
3869 hold the data for such large chunks. */
3871 if (*used_at == 0 && ! mips_opts.noat)
3873 macro_build (p, counter, ep, "lui", "t,u",
3874 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3875 macro_build (p, counter, ep, "lui", "t,u",
3876 AT, (int) BFD_RELOC_HI16_S);
3877 macro_build (p, counter, ep, "daddiu", "t,r,j",
3878 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3879 macro_build (p, counter, ep, "daddiu", "t,r,j",
3880 AT, AT, (int) BFD_RELOC_LO16);
3881 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3882 "d,w,<", reg, reg, 0);
3883 macro_build (p, counter, (expressionS *) NULL, "daddu",
3884 "d,v,t", reg, reg, AT);
3889 macro_build (p, counter, ep, "lui", "t,u",
3890 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3891 macro_build (p, counter, ep, "daddiu", "t,r,j",
3892 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3893 macro_build (p, counter, (expressionS *) NULL, "dsll",
3894 "d,w,<", reg, reg, 16);
3895 macro_build (p, counter, ep, "daddiu", "t,r,j",
3896 reg, reg, (int) BFD_RELOC_HI16_S);
3897 macro_build (p, counter, (expressionS *) NULL, "dsll",
3898 "d,w,<", reg, reg, 16);
3899 macro_build (p, counter, ep, "daddiu", "t,r,j",
3900 reg, reg, (int) BFD_RELOC_LO16);
3905 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3906 && ! nopic_need_relax (ep->X_add_symbol, 1))
3909 macro_build ((char *) NULL, counter, ep,
3910 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3911 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3912 p = frag_var (rs_machine_dependent, 8, 0,
3913 RELAX_ENCODE (4, 8, 0, 4, 0,
3914 mips_opts.warn_about_macros),
3915 ep->X_add_symbol, 0, NULL);
3917 macro_build_lui (p, counter, ep, reg);
3920 macro_build (p, counter, ep,
3921 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3922 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3925 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3929 /* If this is a reference to an external symbol, we want
3930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3932 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3934 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3935 If we have NewABI, we want
3936 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3937 If there is a constant, it must be added in after. */
3938 ex.X_add_number = ep->X_add_number;
3939 ep->X_add_number = 0;
3943 macro_build ((char *) NULL, counter, ep,
3944 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3945 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3949 macro_build ((char *) NULL, counter, ep,
3950 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3951 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3952 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3953 p = frag_var (rs_machine_dependent, 4, 0,
3954 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3955 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3956 macro_build (p, counter, ep,
3957 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3958 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3961 if (ex.X_add_number != 0)
3963 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3965 ex.X_op = O_constant;
3966 macro_build ((char *) NULL, counter, &ex,
3967 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3968 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3971 else if (mips_pic == SVR4_PIC)
3976 /* This is the large GOT case. If this is a reference to an
3977 external symbol, we want
3978 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3980 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3981 Otherwise, for a reference to a local symbol, we want
3982 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3984 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3985 If we have NewABI, we want
3986 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3987 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3988 If there is a constant, it must be added in after. */
3989 ex.X_add_number = ep->X_add_number;
3990 ep->X_add_number = 0;
3993 macro_build ((char *) NULL, counter, ep,
3994 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3995 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3996 macro_build (p, counter, ep,
3997 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3998 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
4002 if (reg_needs_delay (mips_gp_register))
4007 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
4008 (int) BFD_RELOC_MIPS_GOT_HI16);
4009 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4010 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
4011 reg, mips_gp_register);
4012 macro_build ((char *) NULL, counter, ep,
4013 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4014 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
4015 p = frag_var (rs_machine_dependent, 12 + off, 0,
4016 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
4017 mips_opts.warn_about_macros),
4018 ep->X_add_symbol, 0, NULL);
4021 /* We need a nop before loading from $gp. This special
4022 check is required because the lui which starts the main
4023 instruction stream does not refer to $gp, and so will not
4024 insert the nop which may be required. */
4025 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4028 macro_build (p, counter, ep,
4029 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
4030 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
4032 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4034 macro_build (p, counter, ep,
4035 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4036 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4039 if (ex.X_add_number != 0)
4041 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4042 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4043 ex.X_op = O_constant;
4044 macro_build ((char *) NULL, counter, &ex,
4045 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4046 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4049 else if (mips_pic == EMBEDDED_PIC)
4052 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4054 macro_build ((char *) NULL, counter, ep,
4055 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4056 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4062 /* Move the contents of register SOURCE into register DEST. */
4065 move_register (counter, dest, source)
4070 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4071 HAVE_32BIT_GPRS ? "addu" : "daddu",
4072 "d,v,t", dest, source, 0);
4077 * This routine implements the seemingly endless macro or synthesized
4078 * instructions and addressing modes in the mips assembly language. Many
4079 * of these macros are simple and are similar to each other. These could
4080 * probably be handled by some kind of table or grammer aproach instead of
4081 * this verbose method. Others are not simple macros but are more like
4082 * optimizing code generation.
4083 * One interesting optimization is when several store macros appear
4084 * consecutivly that would load AT with the upper half of the same address.
4085 * The ensuing load upper instructions are ommited. This implies some kind
4086 * of global optimization. We currently only optimize within a single macro.
4087 * For many of the load and store macros if the address is specified as a
4088 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4089 * first load register 'at' with zero and use it as the base register. The
4090 * mips assembler simply uses register $zero. Just one tiny optimization
4095 struct mips_cl_insn *ip;
4097 register int treg, sreg, dreg, breg;
4113 bfd_reloc_code_real_type r;
4114 int hold_mips_optimize;
4116 assert (! mips_opts.mips16);
4118 treg = (ip->insn_opcode >> 16) & 0x1f;
4119 dreg = (ip->insn_opcode >> 11) & 0x1f;
4120 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4121 mask = ip->insn_mo->mask;
4123 expr1.X_op = O_constant;
4124 expr1.X_op_symbol = NULL;
4125 expr1.X_add_symbol = NULL;
4126 expr1.X_add_number = 1;
4128 /* Umatched fixups should not be put in the same frag as a relaxable
4129 macro. For example, suppose we have:
4133 addiu $4,$4,%lo(l1) # 3
4135 If instructions 1 and 2 were put in the same frag, md_frob_file would
4136 move the fixup for #1 after the fixups for the "unrelaxed" version of
4137 #2. This would confuse tc_gen_reloc, which expects the relocations
4138 for #2 to be the last for that frag.
4140 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4141 it assumes that they belong to a relaxable macro. We mustn't put
4142 other uses of such relocations into a variant frag.
4144 To avoid both problems, finish the current frag it contains a
4145 %reloc() operator. The macro then goes into a new frag. */
4146 if (prev_reloc_op_frag == frag_now)
4148 frag_wane (frag_now);
4162 mips_emit_delays (TRUE);
4163 ++mips_opts.noreorder;
4164 mips_any_noreorder = 1;
4166 expr1.X_add_number = 8;
4167 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4169 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4172 move_register (&icnt, dreg, sreg);
4173 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4174 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4176 --mips_opts.noreorder;
4197 if (imm_expr.X_op == O_constant
4198 && imm_expr.X_add_number >= -0x8000
4199 && imm_expr.X_add_number < 0x8000)
4201 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4202 (int) BFD_RELOC_LO16);
4205 load_register (&icnt, AT, &imm_expr, dbl);
4206 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4226 if (imm_expr.X_op == O_constant
4227 && imm_expr.X_add_number >= 0
4228 && imm_expr.X_add_number < 0x10000)
4230 if (mask != M_NOR_I)
4231 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4232 sreg, (int) BFD_RELOC_LO16);
4235 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4236 treg, sreg, (int) BFD_RELOC_LO16);
4237 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4238 "d,v,t", treg, treg, 0);
4243 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4244 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4262 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4264 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4268 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4269 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4277 macro_build ((char *) NULL, &icnt, &offset_expr,
4278 likely ? "bgezl" : "bgez", "s,p", sreg);
4283 macro_build ((char *) NULL, &icnt, &offset_expr,
4284 likely ? "blezl" : "blez", "s,p", treg);
4287 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4289 macro_build ((char *) NULL, &icnt, &offset_expr,
4290 likely ? "beql" : "beq", "s,t,p", AT, 0);
4296 /* check for > max integer */
4297 maxnum = 0x7fffffff;
4298 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4305 if (imm_expr.X_op == O_constant
4306 && imm_expr.X_add_number >= maxnum
4307 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4310 /* result is always false */
4314 as_warn (_("Branch %s is always false (nop)"),
4316 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4322 as_warn (_("Branch likely %s is always false"),
4324 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4329 if (imm_expr.X_op != O_constant)
4330 as_bad (_("Unsupported large constant"));
4331 ++imm_expr.X_add_number;
4335 if (mask == M_BGEL_I)
4337 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4339 macro_build ((char *) NULL, &icnt, &offset_expr,
4340 likely ? "bgezl" : "bgez", "s,p", sreg);
4343 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4345 macro_build ((char *) NULL, &icnt, &offset_expr,
4346 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4349 maxnum = 0x7fffffff;
4350 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4357 maxnum = - maxnum - 1;
4358 if (imm_expr.X_op == O_constant
4359 && imm_expr.X_add_number <= maxnum
4360 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4363 /* result is always true */
4364 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4365 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4368 set_at (&icnt, sreg, 0);
4369 macro_build ((char *) NULL, &icnt, &offset_expr,
4370 likely ? "beql" : "beq", "s,t,p", AT, 0);
4380 macro_build ((char *) NULL, &icnt, &offset_expr,
4381 likely ? "beql" : "beq", "s,t,p", 0, treg);
4384 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4385 "d,v,t", AT, sreg, treg);
4386 macro_build ((char *) NULL, &icnt, &offset_expr,
4387 likely ? "beql" : "beq", "s,t,p", AT, 0);
4395 && imm_expr.X_op == O_constant
4396 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4398 if (imm_expr.X_op != O_constant)
4399 as_bad (_("Unsupported large constant"));
4400 ++imm_expr.X_add_number;
4404 if (mask == M_BGEUL_I)
4406 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4408 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4410 macro_build ((char *) NULL, &icnt, &offset_expr,
4411 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4414 set_at (&icnt, sreg, 1);
4415 macro_build ((char *) NULL, &icnt, &offset_expr,
4416 likely ? "beql" : "beq", "s,t,p", AT, 0);
4424 macro_build ((char *) NULL, &icnt, &offset_expr,
4425 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4430 macro_build ((char *) NULL, &icnt, &offset_expr,
4431 likely ? "bltzl" : "bltz", "s,p", treg);
4434 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4436 macro_build ((char *) NULL, &icnt, &offset_expr,
4437 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4445 macro_build ((char *) NULL, &icnt, &offset_expr,
4446 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4451 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4452 "d,v,t", AT, treg, sreg);
4453 macro_build ((char *) NULL, &icnt, &offset_expr,
4454 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4462 macro_build ((char *) NULL, &icnt, &offset_expr,
4463 likely ? "blezl" : "blez", "s,p", sreg);
4468 macro_build ((char *) NULL, &icnt, &offset_expr,
4469 likely ? "bgezl" : "bgez", "s,p", treg);
4472 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4474 macro_build ((char *) NULL, &icnt, &offset_expr,
4475 likely ? "beql" : "beq", "s,t,p", AT, 0);
4481 maxnum = 0x7fffffff;
4482 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4489 if (imm_expr.X_op == O_constant
4490 && imm_expr.X_add_number >= maxnum
4491 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4493 if (imm_expr.X_op != O_constant)
4494 as_bad (_("Unsupported large constant"));
4495 ++imm_expr.X_add_number;
4499 if (mask == M_BLTL_I)
4501 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4503 macro_build ((char *) NULL, &icnt, &offset_expr,
4504 likely ? "bltzl" : "bltz", "s,p", sreg);
4507 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4509 macro_build ((char *) NULL, &icnt, &offset_expr,
4510 likely ? "blezl" : "blez", "s,p", sreg);
4513 set_at (&icnt, sreg, 0);
4514 macro_build ((char *) NULL, &icnt, &offset_expr,
4515 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4523 macro_build ((char *) NULL, &icnt, &offset_expr,
4524 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4529 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4530 "d,v,t", AT, treg, sreg);
4531 macro_build ((char *) NULL, &icnt, &offset_expr,
4532 likely ? "beql" : "beq", "s,t,p", AT, 0);
4540 && imm_expr.X_op == O_constant
4541 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4543 if (imm_expr.X_op != O_constant)
4544 as_bad (_("Unsupported large constant"));
4545 ++imm_expr.X_add_number;
4549 if (mask == M_BLTUL_I)
4551 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4553 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4555 macro_build ((char *) NULL, &icnt, &offset_expr,
4556 likely ? "beql" : "beq",
4560 set_at (&icnt, sreg, 1);
4561 macro_build ((char *) NULL, &icnt, &offset_expr,
4562 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4570 macro_build ((char *) NULL, &icnt, &offset_expr,
4571 likely ? "bltzl" : "bltz", "s,p", sreg);
4576 macro_build ((char *) NULL, &icnt, &offset_expr,
4577 likely ? "bgtzl" : "bgtz", "s,p", treg);
4580 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4582 macro_build ((char *) NULL, &icnt, &offset_expr,
4583 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4593 macro_build ((char *) NULL, &icnt, &offset_expr,
4594 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4597 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4600 macro_build ((char *) NULL, &icnt, &offset_expr,
4601 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4616 as_warn (_("Divide by zero."));
4618 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4621 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4626 mips_emit_delays (TRUE);
4627 ++mips_opts.noreorder;
4628 mips_any_noreorder = 1;
4631 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4632 "s,t,q", treg, 0, 7);
4633 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4634 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4638 expr1.X_add_number = 8;
4639 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4640 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4641 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4642 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4645 expr1.X_add_number = -1;
4646 macro_build ((char *) NULL, &icnt, &expr1,
4647 dbl ? "daddiu" : "addiu",
4648 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4649 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4650 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4653 expr1.X_add_number = 1;
4654 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4655 (int) BFD_RELOC_LO16);
4656 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4657 "d,w,<", AT, AT, 31);
4661 expr1.X_add_number = 0x80000000;
4662 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4663 (int) BFD_RELOC_HI16);
4667 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4668 "s,t,q", sreg, AT, 6);
4669 /* We want to close the noreorder block as soon as possible, so
4670 that later insns are available for delay slot filling. */
4671 --mips_opts.noreorder;
4675 expr1.X_add_number = 8;
4676 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4680 /* We want to close the noreorder block as soon as possible, so
4681 that later insns are available for delay slot filling. */
4682 --mips_opts.noreorder;
4684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4687 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4726 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4728 as_warn (_("Divide by zero."));
4730 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4733 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4737 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4739 if (strcmp (s2, "mflo") == 0)
4740 move_register (&icnt, dreg, sreg);
4742 move_register (&icnt, dreg, 0);
4745 if (imm_expr.X_op == O_constant
4746 && imm_expr.X_add_number == -1
4747 && s[strlen (s) - 1] != 'u')
4749 if (strcmp (s2, "mflo") == 0)
4751 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4752 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4755 move_register (&icnt, dreg, 0);
4759 load_register (&icnt, AT, &imm_expr, dbl);
4760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4781 mips_emit_delays (TRUE);
4782 ++mips_opts.noreorder;
4783 mips_any_noreorder = 1;
4786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4787 "s,t,q", treg, 0, 7);
4788 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4790 /* We want to close the noreorder block as soon as possible, so
4791 that later insns are available for delay slot filling. */
4792 --mips_opts.noreorder;
4796 expr1.X_add_number = 8;
4797 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4798 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4801 /* We want to close the noreorder block as soon as possible, so
4802 that later insns are available for delay slot filling. */
4803 --mips_opts.noreorder;
4804 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4807 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4813 /* Load the address of a symbol into a register. If breg is not
4814 zero, we then add a base register to it. */
4816 if (dbl && HAVE_32BIT_GPRS)
4817 as_warn (_("dla used to load 32-bit register"));
4819 if (! dbl && HAVE_64BIT_OBJECTS)
4820 as_warn (_("la used to load 64-bit address"));
4822 if (offset_expr.X_op == O_constant
4823 && offset_expr.X_add_number >= -0x8000
4824 && offset_expr.X_add_number < 0x8000)
4826 macro_build ((char *) NULL, &icnt, &offset_expr,
4827 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4828 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4843 /* When generating embedded PIC code, we permit expressions of
4846 la $treg,foo-bar($breg)
4847 where bar is an address in the current section. These are used
4848 when getting the addresses of functions. We don't permit
4849 X_add_number to be non-zero, because if the symbol is
4850 external the relaxing code needs to know that any addend is
4851 purely the offset to X_op_symbol. */
4852 if (mips_pic == EMBEDDED_PIC
4853 && offset_expr.X_op == O_subtract
4854 && (symbol_constant_p (offset_expr.X_op_symbol)
4855 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4856 : (symbol_equated_p (offset_expr.X_op_symbol)
4858 (symbol_get_value_expression (offset_expr.X_op_symbol)
4861 && (offset_expr.X_add_number == 0
4862 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4868 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4869 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4873 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4874 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4875 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4876 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4877 "d,v,t", tempreg, tempreg, breg);
4879 macro_build ((char *) NULL, &icnt, &offset_expr,
4880 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4881 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4887 if (offset_expr.X_op != O_symbol
4888 && offset_expr.X_op != O_constant)
4890 as_bad (_("expression too complex"));
4891 offset_expr.X_op = O_constant;
4894 if (offset_expr.X_op == O_constant)
4895 load_register (&icnt, tempreg, &offset_expr,
4896 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4897 ? (dbl || HAVE_64BIT_ADDRESSES)
4898 : HAVE_64BIT_ADDRESSES));
4899 else if (mips_pic == NO_PIC)
4901 /* If this is a reference to a GP relative symbol, we want
4902 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4904 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4905 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4906 If we have a constant, we need two instructions anyhow,
4907 so we may as well always use the latter form.
4909 With 64bit address space and a usable $at we want
4910 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4911 lui $at,<sym> (BFD_RELOC_HI16_S)
4912 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4913 daddiu $at,<sym> (BFD_RELOC_LO16)
4915 daddu $tempreg,$tempreg,$at
4917 If $at is already in use, we use a path which is suboptimal
4918 on superscalar processors.
4919 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4920 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4922 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4924 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4927 if (HAVE_64BIT_ADDRESSES)
4929 /* We don't do GP optimization for now because RELAX_ENCODE can't
4930 hold the data for such large chunks. */
4932 if (used_at == 0 && ! mips_opts.noat)
4934 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4935 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4936 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4937 AT, (int) BFD_RELOC_HI16_S);
4938 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4939 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4940 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4941 AT, AT, (int) BFD_RELOC_LO16);
4942 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4943 "d,w,<", tempreg, tempreg, 0);
4944 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4945 "d,v,t", tempreg, tempreg, AT);
4950 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4951 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4952 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4953 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4954 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4955 tempreg, tempreg, 16);
4956 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4957 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4958 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4959 tempreg, tempreg, 16);
4960 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4961 tempreg, tempreg, (int) BFD_RELOC_LO16);
4966 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4967 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4970 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4971 "t,r,j", tempreg, mips_gp_register,
4972 (int) BFD_RELOC_GPREL16);
4973 p = frag_var (rs_machine_dependent, 8, 0,
4974 RELAX_ENCODE (4, 8, 0, 4, 0,
4975 mips_opts.warn_about_macros),
4976 offset_expr.X_add_symbol, 0, NULL);
4978 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4981 macro_build (p, &icnt, &offset_expr, "addiu",
4982 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4985 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4987 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4989 /* If this is a reference to an external symbol, and there
4990 is no constant, we want
4991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4992 or if tempreg is PIC_CALL_REG
4993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4994 For a local symbol, we want
4995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4997 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4999 If we have a small constant, and this is a reference to
5000 an external symbol, we want
5001 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5003 addiu $tempreg,$tempreg,<constant>
5004 For a local symbol, we want the same instruction
5005 sequence, but we output a BFD_RELOC_LO16 reloc on the
5008 If we have a large constant, and this is a reference to
5009 an external symbol, we want
5010 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5011 lui $at,<hiconstant>
5012 addiu $at,$at,<loconstant>
5013 addu $tempreg,$tempreg,$at
5014 For a local symbol, we want the same instruction
5015 sequence, but we output a BFD_RELOC_LO16 reloc on the
5018 For NewABI, we want for local or external data addresses
5019 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5020 For a local function symbol, we want
5021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5023 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5026 expr1.X_add_number = offset_expr.X_add_number;
5027 offset_expr.X_add_number = 0;
5029 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5030 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5031 else if (HAVE_NEWABI)
5032 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5033 macro_build ((char *) NULL, &icnt, &offset_expr,
5034 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5035 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
5036 if (expr1.X_add_number == 0)
5045 /* We're going to put in an addu instruction using
5046 tempreg, so we may as well insert the nop right
5048 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5052 p = frag_var (rs_machine_dependent, 8 - off, 0,
5053 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
5055 ? mips_opts.warn_about_macros
5057 offset_expr.X_add_symbol, 0, NULL);
5060 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5063 macro_build (p, &icnt, &expr1,
5064 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5065 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5066 /* FIXME: If breg == 0, and the next instruction uses
5067 $tempreg, then if this variant case is used an extra
5068 nop will be generated. */
5070 else if (expr1.X_add_number >= -0x8000
5071 && expr1.X_add_number < 0x8000)
5073 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5075 macro_build ((char *) NULL, &icnt, &expr1,
5076 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5077 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5078 frag_var (rs_machine_dependent, 0, 0,
5079 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5080 offset_expr.X_add_symbol, 0, NULL);
5086 /* If we are going to add in a base register, and the
5087 target register and the base register are the same,
5088 then we are using AT as a temporary register. Since
5089 we want to load the constant into AT, we add our
5090 current AT (from the global offset table) and the
5091 register into the register now, and pretend we were
5092 not using a base register. */
5097 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5099 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5100 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5101 "d,v,t", treg, AT, breg);
5107 /* Set mips_optimize around the lui instruction to avoid
5108 inserting an unnecessary nop after the lw. */
5109 hold_mips_optimize = mips_optimize;
5111 macro_build_lui (NULL, &icnt, &expr1, AT);
5112 mips_optimize = hold_mips_optimize;
5114 macro_build ((char *) NULL, &icnt, &expr1,
5115 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5116 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5117 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5118 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5119 "d,v,t", tempreg, tempreg, AT);
5120 frag_var (rs_machine_dependent, 0, 0,
5121 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5122 offset_expr.X_add_symbol, 0, NULL);
5126 else if (mips_pic == SVR4_PIC)
5130 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5131 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5132 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5134 /* This is the large GOT case. If this is a reference to an
5135 external symbol, and there is no constant, we want
5136 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5137 addu $tempreg,$tempreg,$gp
5138 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5139 or if tempreg is PIC_CALL_REG
5140 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5141 addu $tempreg,$tempreg,$gp
5142 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5143 For a local symbol, we want
5144 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5146 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5148 If we have a small constant, and this is a reference to
5149 an external symbol, we want
5150 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5151 addu $tempreg,$tempreg,$gp
5152 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5154 addiu $tempreg,$tempreg,<constant>
5155 For a local symbol, we want
5156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5158 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5160 If we have a large constant, and this is a reference to
5161 an external symbol, we want
5162 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5163 addu $tempreg,$tempreg,$gp
5164 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5165 lui $at,<hiconstant>
5166 addiu $at,$at,<loconstant>
5167 addu $tempreg,$tempreg,$at
5168 For a local symbol, we want
5169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5170 lui $at,<hiconstant>
5171 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5172 addu $tempreg,$tempreg,$at
5174 For NewABI, we want for local data addresses
5175 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5178 expr1.X_add_number = offset_expr.X_add_number;
5179 offset_expr.X_add_number = 0;
5181 if (reg_needs_delay (mips_gp_register))
5185 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5187 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5188 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5190 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5191 tempreg, lui_reloc_type);
5192 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5193 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5194 "d,v,t", tempreg, tempreg, mips_gp_register);
5195 macro_build ((char *) NULL, &icnt, &offset_expr,
5196 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5197 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5198 if (expr1.X_add_number == 0)
5206 /* We're going to put in an addu instruction using
5207 tempreg, so we may as well insert the nop right
5209 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5214 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5215 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5218 ? mips_opts.warn_about_macros
5220 offset_expr.X_add_symbol, 0, NULL);
5222 else if (expr1.X_add_number >= -0x8000
5223 && expr1.X_add_number < 0x8000)
5225 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5227 macro_build ((char *) NULL, &icnt, &expr1,
5228 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5229 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5231 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5232 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5234 ? mips_opts.warn_about_macros
5236 offset_expr.X_add_symbol, 0, NULL);
5242 /* If we are going to add in a base register, and the
5243 target register and the base register are the same,
5244 then we are using AT as a temporary register. Since
5245 we want to load the constant into AT, we add our
5246 current AT (from the global offset table) and the
5247 register into the register now, and pretend we were
5248 not using a base register. */
5256 assert (tempreg == AT);
5257 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5259 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5260 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5261 "d,v,t", treg, AT, breg);
5266 /* Set mips_optimize around the lui instruction to avoid
5267 inserting an unnecessary nop after the lw. */
5268 hold_mips_optimize = mips_optimize;
5270 macro_build_lui (NULL, &icnt, &expr1, AT);
5271 mips_optimize = hold_mips_optimize;
5273 macro_build ((char *) NULL, &icnt, &expr1,
5274 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5275 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5276 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5277 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5278 "d,v,t", dreg, dreg, AT);
5280 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5281 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5284 ? mips_opts.warn_about_macros
5286 offset_expr.X_add_symbol, 0, NULL);
5293 /* This is needed because this instruction uses $gp, but
5294 the first instruction on the main stream does not. */
5295 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5300 local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5301 macro_build (p, &icnt, &offset_expr,
5302 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5307 if (expr1.X_add_number == 0 && HAVE_NEWABI)
5309 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5312 if (expr1.X_add_number >= -0x8000
5313 && expr1.X_add_number < 0x8000)
5315 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5317 macro_build (p, &icnt, &expr1,
5318 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5319 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5320 /* FIXME: If add_number is 0, and there was no base
5321 register, the external symbol case ended with a load,
5322 so if the symbol turns out to not be external, and
5323 the next instruction uses tempreg, an unnecessary nop
5324 will be inserted. */
5330 /* We must add in the base register now, as in the
5331 external symbol case. */
5332 assert (tempreg == AT);
5333 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5335 macro_build (p, &icnt, (expressionS *) NULL,
5336 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5337 "d,v,t", treg, AT, breg);
5340 /* We set breg to 0 because we have arranged to add
5341 it in in both cases. */
5345 macro_build_lui (p, &icnt, &expr1, AT);
5347 macro_build (p, &icnt, &expr1,
5348 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5349 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5351 macro_build (p, &icnt, (expressionS *) NULL,
5352 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5353 "d,v,t", tempreg, tempreg, AT);
5357 else if (mips_pic == EMBEDDED_PIC)
5360 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5362 macro_build ((char *) NULL, &icnt, &offset_expr,
5363 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
5364 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5373 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5374 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5376 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5378 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5379 "d,v,t", treg, tempreg, breg);
5388 /* The j instruction may not be used in PIC code, since it
5389 requires an absolute address. We convert it to a b
5391 if (mips_pic == NO_PIC)
5392 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5394 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5397 /* The jal instructions must be handled as macros because when
5398 generating PIC code they expand to multi-instruction
5399 sequences. Normally they are simple instructions. */
5404 if (mips_pic == NO_PIC
5405 || mips_pic == EMBEDDED_PIC)
5406 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5408 else if (mips_pic == SVR4_PIC)
5410 if (sreg != PIC_CALL_REG)
5411 as_warn (_("MIPS PIC call to register other than $25"));
5413 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5417 if (mips_cprestore_offset < 0)
5418 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5421 if (! mips_frame_reg_valid)
5423 as_warn (_("No .frame pseudo-op used in PIC code"));
5424 /* Quiet this warning. */
5425 mips_frame_reg_valid = 1;
5427 if (! mips_cprestore_valid)
5429 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5430 /* Quiet this warning. */
5431 mips_cprestore_valid = 1;
5433 expr1.X_add_number = mips_cprestore_offset;
5434 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5435 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5436 mips_gp_register, mips_frame_reg);
5446 if (mips_pic == NO_PIC)
5447 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5448 else if (mips_pic == SVR4_PIC)
5452 /* If this is a reference to an external symbol, and we are
5453 using a small GOT, we want
5454 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5458 lw $gp,cprestore($sp)
5459 The cprestore value is set using the .cprestore
5460 pseudo-op. If we are using a big GOT, we want
5461 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5463 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5467 lw $gp,cprestore($sp)
5468 If the symbol is not external, we want
5469 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5471 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5474 lw $gp,cprestore($sp)
5476 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5477 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5481 macro_build ((char *) NULL, &icnt, &offset_expr,
5482 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5483 "t,o(b)", PIC_CALL_REG,
5484 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5485 macro_build_jalr (icnt, &offset_expr);
5492 macro_build ((char *) NULL, &icnt, &offset_expr,
5493 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5494 "t,o(b)", PIC_CALL_REG,
5495 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5496 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5498 p = frag_var (rs_machine_dependent, 4, 0,
5499 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5500 offset_expr.X_add_symbol, 0, NULL);
5506 if (reg_needs_delay (mips_gp_register))
5510 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5511 "t,u", PIC_CALL_REG,
5512 (int) BFD_RELOC_MIPS_CALL_HI16);
5513 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5514 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5515 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5517 macro_build ((char *) NULL, &icnt, &offset_expr,
5518 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5519 "t,o(b)", PIC_CALL_REG,
5520 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5521 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5523 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5524 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5526 offset_expr.X_add_symbol, 0, NULL);
5529 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5532 macro_build (p, &icnt, &offset_expr,
5533 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5534 "t,o(b)", PIC_CALL_REG,
5535 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5537 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5540 macro_build (p, &icnt, &offset_expr,
5541 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5542 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5543 (int) BFD_RELOC_LO16);
5544 macro_build_jalr (icnt, &offset_expr);
5546 if (mips_cprestore_offset < 0)
5547 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5550 if (! mips_frame_reg_valid)
5552 as_warn (_("No .frame pseudo-op used in PIC code"));
5553 /* Quiet this warning. */
5554 mips_frame_reg_valid = 1;
5556 if (! mips_cprestore_valid)
5558 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5559 /* Quiet this warning. */
5560 mips_cprestore_valid = 1;
5562 if (mips_opts.noreorder)
5563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5565 expr1.X_add_number = mips_cprestore_offset;
5566 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5567 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5568 mips_gp_register, mips_frame_reg);
5572 else if (mips_pic == EMBEDDED_PIC)
5574 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5575 /* The linker may expand the call to a longer sequence which
5576 uses $at, so we must break rather than return. */
5601 /* Itbl support may require additional care here. */
5606 /* Itbl support may require additional care here. */
5611 /* Itbl support may require additional care here. */
5616 /* Itbl support may require additional care here. */
5628 if (mips_arch == CPU_R4650)
5630 as_bad (_("opcode not supported on this processor"));
5634 /* Itbl support may require additional care here. */
5639 /* Itbl support may require additional care here. */
5644 /* Itbl support may require additional care here. */
5664 if (breg == treg || coproc || lr)
5686 /* Itbl support may require additional care here. */
5691 /* Itbl support may require additional care here. */
5696 /* Itbl support may require additional care here. */
5701 /* Itbl support may require additional care here. */
5717 if (mips_arch == CPU_R4650)
5719 as_bad (_("opcode not supported on this processor"));
5724 /* Itbl support may require additional care here. */
5728 /* Itbl support may require additional care here. */
5733 /* Itbl support may require additional care here. */
5745 /* Itbl support may require additional care here. */
5746 if (mask == M_LWC1_AB
5747 || mask == M_SWC1_AB
5748 || mask == M_LDC1_AB
5749 || mask == M_SDC1_AB
5758 /* For embedded PIC, we allow loads where the offset is calculated
5759 by subtracting a symbol in the current segment from an unknown
5760 symbol, relative to a base register, e.g.:
5761 <op> $treg, <sym>-<localsym>($breg)
5762 This is used by the compiler for switch statements. */
5763 if (mips_pic == EMBEDDED_PIC
5764 && offset_expr.X_op == O_subtract
5765 && (symbol_constant_p (offset_expr.X_op_symbol)
5766 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5767 : (symbol_equated_p (offset_expr.X_op_symbol)
5769 (symbol_get_value_expression (offset_expr.X_op_symbol)
5773 && (offset_expr.X_add_number == 0
5774 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5776 /* For this case, we output the instructions:
5777 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5778 addiu $tempreg,$tempreg,$breg
5779 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5780 If the relocation would fit entirely in 16 bits, it would be
5782 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5783 instead, but that seems quite difficult. */
5784 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5785 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5787 ((bfd_arch_bits_per_address (stdoutput) == 32
5788 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5789 ? "addu" : "daddu"),
5790 "d,v,t", tempreg, tempreg, breg);
5791 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5792 (int) BFD_RELOC_PCREL_LO16, tempreg);
5798 if (offset_expr.X_op != O_constant
5799 && offset_expr.X_op != O_symbol)
5801 as_bad (_("expression too complex"));
5802 offset_expr.X_op = O_constant;
5805 /* A constant expression in PIC code can be handled just as it
5806 is in non PIC code. */
5807 if (mips_pic == NO_PIC
5808 || offset_expr.X_op == O_constant)
5812 /* If this is a reference to a GP relative symbol, and there
5813 is no base register, we want
5814 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5815 Otherwise, if there is no base register, we want
5816 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5817 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5818 If we have a constant, we need two instructions anyhow,
5819 so we always use the latter form.
5821 If we have a base register, and this is a reference to a
5822 GP relative symbol, we want
5823 addu $tempreg,$breg,$gp
5824 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5826 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5827 addu $tempreg,$tempreg,$breg
5828 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5829 With a constant we always use the latter case.
5831 With 64bit address space and no base register and $at usable,
5833 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5834 lui $at,<sym> (BFD_RELOC_HI16_S)
5835 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5838 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5839 If we have a base register, we want
5840 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5841 lui $at,<sym> (BFD_RELOC_HI16_S)
5842 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5846 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5848 Without $at we can't generate the optimal path for superscalar
5849 processors here since this would require two temporary registers.
5850 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5851 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5853 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5855 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5856 If we have a base register, we want
5857 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5858 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5860 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5862 daddu $tempreg,$tempreg,$breg
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5865 If we have 64-bit addresses, as an optimization, for
5866 addresses which are 32-bit constants (e.g. kseg0/kseg1
5867 addresses) we fall back to the 32-bit address generation
5868 mechanism since it is more efficient. Note that due to
5869 the signed offset used by memory operations, the 32-bit
5870 range is shifted down by 32768 here. This code should
5871 probably attempt to generate 64-bit constants more
5872 efficiently in general.
5874 if (HAVE_64BIT_ADDRESSES
5875 && !(offset_expr.X_op == O_constant
5876 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5880 /* We don't do GP optimization for now because RELAX_ENCODE can't
5881 hold the data for such large chunks. */
5883 if (used_at == 0 && ! mips_opts.noat)
5885 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5886 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5887 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5888 AT, (int) BFD_RELOC_HI16_S);
5889 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5890 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5892 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5893 "d,v,t", AT, AT, breg);
5894 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5895 "d,w,<", tempreg, tempreg, 0);
5896 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5897 "d,v,t", tempreg, tempreg, AT);
5898 macro_build (p, &icnt, &offset_expr, s,
5899 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5904 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5905 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5906 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5907 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5908 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5909 "d,w,<", tempreg, tempreg, 16);
5910 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5911 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5912 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5913 "d,w,<", tempreg, tempreg, 16);
5915 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5916 "d,v,t", tempreg, tempreg, breg);
5917 macro_build (p, &icnt, &offset_expr, s,
5918 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5926 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5927 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5932 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5933 treg, (int) BFD_RELOC_GPREL16,
5935 p = frag_var (rs_machine_dependent, 8, 0,
5936 RELAX_ENCODE (4, 8, 0, 4, 0,
5937 (mips_opts.warn_about_macros
5939 && mips_opts.noat))),
5940 offset_expr.X_add_symbol, 0, NULL);
5943 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5946 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5947 (int) BFD_RELOC_LO16, tempreg);
5951 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5952 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5957 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5958 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5959 "d,v,t", tempreg, breg, mips_gp_register);
5960 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5961 treg, (int) BFD_RELOC_GPREL16, tempreg);
5962 p = frag_var (rs_machine_dependent, 12, 0,
5963 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5964 offset_expr.X_add_symbol, 0, NULL);
5966 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5969 macro_build (p, &icnt, (expressionS *) NULL,
5970 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5971 "d,v,t", tempreg, tempreg, breg);
5974 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5975 (int) BFD_RELOC_LO16, tempreg);
5978 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5981 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5983 /* If this is a reference to an external symbol, we want
5984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5986 <op> $treg,0($tempreg)
5988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5990 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5991 <op> $treg,0($tempreg)
5992 If we have NewABI, we want
5993 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5994 If there is a base register, we add it to $tempreg before
5995 the <op>. If there is a constant, we stick it in the
5996 <op> instruction. We don't handle constants larger than
5997 16 bits, because we have no way to load the upper 16 bits
5998 (actually, we could handle them for the subset of cases
5999 in which we are not using $at). */
6000 assert (offset_expr.X_op == O_symbol);
6001 expr1.X_add_number = offset_expr.X_add_number;
6002 offset_expr.X_add_number = 0;
6004 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
6005 if (expr1.X_add_number < -0x8000
6006 || expr1.X_add_number >= 0x8000)
6007 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6009 macro_build ((char *) NULL, &icnt, &offset_expr,
6010 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
6011 (int) lw_reloc_type, mips_gp_register);
6012 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6013 p = frag_var (rs_machine_dependent, 4, 0,
6014 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6015 offset_expr.X_add_symbol, 0, NULL);
6016 macro_build (p, &icnt, &offset_expr,
6017 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
6018 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
6020 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6021 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6022 "d,v,t", tempreg, tempreg, breg);
6023 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6024 (int) BFD_RELOC_LO16, tempreg);
6026 else if (mips_pic == SVR4_PIC)
6031 /* If this is a reference to an external symbol, we want
6032 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6033 addu $tempreg,$tempreg,$gp
6034 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6035 <op> $treg,0($tempreg)
6037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6039 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6040 <op> $treg,0($tempreg)
6041 If there is a base register, we add it to $tempreg before
6042 the <op>. If there is a constant, we stick it in the
6043 <op> instruction. We don't handle constants larger than
6044 16 bits, because we have no way to load the upper 16 bits
6045 (actually, we could handle them for the subset of cases
6046 in which we are not using $at).
6049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6050 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6051 <op> $treg,0($tempreg)
6053 assert (offset_expr.X_op == O_symbol);
6054 expr1.X_add_number = offset_expr.X_add_number;
6055 offset_expr.X_add_number = 0;
6056 if (expr1.X_add_number < -0x8000
6057 || expr1.X_add_number >= 0x8000)
6058 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6061 macro_build ((char *) NULL, &icnt, &offset_expr,
6062 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6063 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6065 macro_build ((char *) NULL, &icnt, &offset_expr,
6066 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
6067 "t,r,j", tempreg, tempreg,
6068 BFD_RELOC_MIPS_GOT_OFST);
6070 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6071 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6072 "d,v,t", tempreg, tempreg, breg);
6073 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6074 (int) BFD_RELOC_LO16, tempreg);
6081 if (reg_needs_delay (mips_gp_register))
6086 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6087 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
6088 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6089 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6090 "d,v,t", tempreg, tempreg, mips_gp_register);
6091 macro_build ((char *) NULL, &icnt, &offset_expr,
6092 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6093 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
6095 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6096 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6097 offset_expr.X_add_symbol, 0, NULL);
6100 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6103 macro_build (p, &icnt, &offset_expr,
6104 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6105 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
6108 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6110 macro_build (p, &icnt, &offset_expr,
6111 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
6112 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
6114 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6115 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6116 "d,v,t", tempreg, tempreg, breg);
6117 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6118 (int) BFD_RELOC_LO16, tempreg);
6120 else if (mips_pic == EMBEDDED_PIC)
6122 /* If there is no base register, we want
6123 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6124 If there is a base register, we want
6125 addu $tempreg,$breg,$gp
6126 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6128 assert (offset_expr.X_op == O_symbol);
6131 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6132 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
6137 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6138 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6139 "d,v,t", tempreg, breg, mips_gp_register);
6140 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6141 treg, (int) BFD_RELOC_GPREL16, tempreg);
6154 load_register (&icnt, treg, &imm_expr, 0);
6158 load_register (&icnt, treg, &imm_expr, 1);
6162 if (imm_expr.X_op == O_constant)
6164 load_register (&icnt, AT, &imm_expr, 0);
6165 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6166 "mtc1", "t,G", AT, treg);
6171 assert (offset_expr.X_op == O_symbol
6172 && strcmp (segment_name (S_GET_SEGMENT
6173 (offset_expr.X_add_symbol)),
6175 && offset_expr.X_add_number == 0);
6176 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6177 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6182 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6183 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6184 order 32 bits of the value and the low order 32 bits are either
6185 zero or in OFFSET_EXPR. */
6186 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6188 if (HAVE_64BIT_GPRS)
6189 load_register (&icnt, treg, &imm_expr, 1);
6194 if (target_big_endian)
6206 load_register (&icnt, hreg, &imm_expr, 0);
6209 if (offset_expr.X_op == O_absent)
6210 move_register (&icnt, lreg, 0);
6213 assert (offset_expr.X_op == O_constant);
6214 load_register (&icnt, lreg, &offset_expr, 0);
6221 /* We know that sym is in the .rdata section. First we get the
6222 upper 16 bits of the address. */
6223 if (mips_pic == NO_PIC)
6225 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6227 else if (mips_pic == SVR4_PIC)
6229 macro_build ((char *) NULL, &icnt, &offset_expr,
6230 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6231 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6234 else if (mips_pic == EMBEDDED_PIC)
6236 /* For embedded PIC we pick up the entire address off $gp in
6237 a single instruction. */
6238 macro_build ((char *) NULL, &icnt, &offset_expr,
6239 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
6240 mips_gp_register, (int) BFD_RELOC_GPREL16);
6241 offset_expr.X_op = O_constant;
6242 offset_expr.X_add_number = 0;
6247 /* Now we load the register(s). */
6248 if (HAVE_64BIT_GPRS)
6249 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
6250 treg, (int) BFD_RELOC_LO16, AT);
6253 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6254 treg, (int) BFD_RELOC_LO16, AT);
6257 /* FIXME: How in the world do we deal with the possible
6259 offset_expr.X_add_number += 4;
6260 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6261 treg + 1, (int) BFD_RELOC_LO16, AT);
6265 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6266 does not become a variant frag. */
6267 frag_wane (frag_now);
6273 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6274 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6275 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6276 the value and the low order 32 bits are either zero or in
6278 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6280 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6281 if (HAVE_64BIT_FPRS)
6283 assert (HAVE_64BIT_GPRS);
6284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6285 "dmtc1", "t,S", AT, treg);
6289 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6290 "mtc1", "t,G", AT, treg + 1);
6291 if (offset_expr.X_op == O_absent)
6292 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6293 "mtc1", "t,G", 0, treg);
6296 assert (offset_expr.X_op == O_constant);
6297 load_register (&icnt, AT, &offset_expr, 0);
6298 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6299 "mtc1", "t,G", AT, treg);
6305 assert (offset_expr.X_op == O_symbol
6306 && offset_expr.X_add_number == 0);
6307 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6308 if (strcmp (s, ".lit8") == 0)
6310 if (mips_opts.isa != ISA_MIPS1)
6312 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6313 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6317 breg = mips_gp_register;
6318 r = BFD_RELOC_MIPS_LITERAL;
6323 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6324 if (mips_pic == SVR4_PIC)
6325 macro_build ((char *) NULL, &icnt, &offset_expr,
6326 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6327 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6331 /* FIXME: This won't work for a 64 bit address. */
6332 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6335 if (mips_opts.isa != ISA_MIPS1)
6337 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6338 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6340 /* To avoid confusion in tc_gen_reloc, we must ensure
6341 that this does not become a variant frag. */
6342 frag_wane (frag_now);
6353 if (mips_arch == CPU_R4650)
6355 as_bad (_("opcode not supported on this processor"));
6358 /* Even on a big endian machine $fn comes before $fn+1. We have
6359 to adjust when loading from memory. */
6362 assert (mips_opts.isa == ISA_MIPS1);
6363 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6364 target_big_endian ? treg + 1 : treg,
6366 /* FIXME: A possible overflow which I don't know how to deal
6368 offset_expr.X_add_number += 4;
6369 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6370 target_big_endian ? treg : treg + 1,
6373 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6374 does not become a variant frag. */
6375 frag_wane (frag_now);
6384 * The MIPS assembler seems to check for X_add_number not
6385 * being double aligned and generating:
6388 * addiu at,at,%lo(foo+1)
6391 * But, the resulting address is the same after relocation so why
6392 * generate the extra instruction?
6394 if (mips_arch == CPU_R4650)
6396 as_bad (_("opcode not supported on this processor"));
6399 /* Itbl support may require additional care here. */
6401 if (mips_opts.isa != ISA_MIPS1)
6412 if (mips_arch == CPU_R4650)
6414 as_bad (_("opcode not supported on this processor"));
6418 if (mips_opts.isa != ISA_MIPS1)
6426 /* Itbl support may require additional care here. */
6431 if (HAVE_64BIT_GPRS)
6442 if (HAVE_64BIT_GPRS)
6452 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6453 loads for the case of doing a pair of loads to simulate an 'ld'.
6454 This is not currently done by the compiler, and assembly coders
6455 writing embedded-pic code can cope. */
6457 if (offset_expr.X_op != O_symbol
6458 && offset_expr.X_op != O_constant)
6460 as_bad (_("expression too complex"));
6461 offset_expr.X_op = O_constant;
6464 /* Even on a big endian machine $fn comes before $fn+1. We have
6465 to adjust when loading from memory. We set coproc if we must
6466 load $fn+1 first. */
6467 /* Itbl support may require additional care here. */
6468 if (! target_big_endian)
6471 if (mips_pic == NO_PIC
6472 || offset_expr.X_op == O_constant)
6476 /* If this is a reference to a GP relative symbol, we want
6477 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6478 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6479 If we have a base register, we use this
6481 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6482 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6483 If this is not a GP relative symbol, we want
6484 lui $at,<sym> (BFD_RELOC_HI16_S)
6485 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6486 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6487 If there is a base register, we add it to $at after the
6488 lui instruction. If there is a constant, we always use
6490 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6491 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6503 tempreg = mips_gp_register;
6510 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6511 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6512 "d,v,t", AT, breg, mips_gp_register);
6518 /* Itbl support may require additional care here. */
6519 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6520 coproc ? treg + 1 : treg,
6521 (int) BFD_RELOC_GPREL16, tempreg);
6522 offset_expr.X_add_number += 4;
6524 /* Set mips_optimize to 2 to avoid inserting an
6526 hold_mips_optimize = mips_optimize;
6528 /* Itbl support may require additional care here. */
6529 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6530 coproc ? treg : treg + 1,
6531 (int) BFD_RELOC_GPREL16, tempreg);
6532 mips_optimize = hold_mips_optimize;
6534 p = frag_var (rs_machine_dependent, 12 + off, 0,
6535 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6536 used_at && mips_opts.noat),
6537 offset_expr.X_add_symbol, 0, NULL);
6539 /* We just generated two relocs. When tc_gen_reloc
6540 handles this case, it will skip the first reloc and
6541 handle the second. The second reloc already has an
6542 extra addend of 4, which we added above. We must
6543 subtract it out, and then subtract another 4 to make
6544 the first reloc come out right. The second reloc
6545 will come out right because we are going to add 4 to
6546 offset_expr when we build its instruction below.
6548 If we have a symbol, then we don't want to include
6549 the offset, because it will wind up being included
6550 when we generate the reloc. */
6552 if (offset_expr.X_op == O_constant)
6553 offset_expr.X_add_number -= 8;
6556 offset_expr.X_add_number = -4;
6557 offset_expr.X_op = O_constant;
6560 macro_build_lui (p, &icnt, &offset_expr, AT);
6565 macro_build (p, &icnt, (expressionS *) NULL,
6566 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6567 "d,v,t", AT, breg, AT);
6571 /* Itbl support may require additional care here. */
6572 macro_build (p, &icnt, &offset_expr, s, fmt,
6573 coproc ? treg + 1 : treg,
6574 (int) BFD_RELOC_LO16, AT);
6577 /* FIXME: How do we handle overflow here? */
6578 offset_expr.X_add_number += 4;
6579 /* Itbl support may require additional care here. */
6580 macro_build (p, &icnt, &offset_expr, s, fmt,
6581 coproc ? treg : treg + 1,
6582 (int) BFD_RELOC_LO16, AT);
6584 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6588 /* If this is a reference to an external symbol, we want
6589 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6594 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6596 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6597 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6598 If there is a base register we add it to $at before the
6599 lwc1 instructions. If there is a constant we include it
6600 in the lwc1 instructions. */
6602 expr1.X_add_number = offset_expr.X_add_number;
6603 offset_expr.X_add_number = 0;
6604 if (expr1.X_add_number < -0x8000
6605 || expr1.X_add_number >= 0x8000 - 4)
6606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6611 frag_grow (24 + off);
6612 macro_build ((char *) NULL, &icnt, &offset_expr,
6613 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6614 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6615 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6618 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6619 "d,v,t", AT, breg, AT);
6620 /* Itbl support may require additional care here. */
6621 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6622 coproc ? treg + 1 : treg,
6623 (int) BFD_RELOC_LO16, AT);
6624 expr1.X_add_number += 4;
6626 /* Set mips_optimize to 2 to avoid inserting an undesired
6628 hold_mips_optimize = mips_optimize;
6630 /* Itbl support may require additional care here. */
6631 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6632 coproc ? treg : treg + 1,
6633 (int) BFD_RELOC_LO16, AT);
6634 mips_optimize = hold_mips_optimize;
6636 (void) frag_var (rs_machine_dependent, 0, 0,
6637 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6638 offset_expr.X_add_symbol, 0, NULL);
6640 else if (mips_pic == SVR4_PIC)
6645 /* If this is a reference to an external symbol, we want
6646 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6648 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6653 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6655 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6656 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6657 If there is a base register we add it to $at before the
6658 lwc1 instructions. If there is a constant we include it
6659 in the lwc1 instructions. */
6661 expr1.X_add_number = offset_expr.X_add_number;
6662 offset_expr.X_add_number = 0;
6663 if (expr1.X_add_number < -0x8000
6664 || expr1.X_add_number >= 0x8000 - 4)
6665 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6666 if (reg_needs_delay (mips_gp_register))
6675 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6676 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6678 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6679 "d,v,t", AT, AT, mips_gp_register);
6680 macro_build ((char *) NULL, &icnt, &offset_expr,
6681 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6682 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6683 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6685 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6686 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6687 "d,v,t", AT, breg, AT);
6688 /* Itbl support may require additional care here. */
6689 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6690 coproc ? treg + 1 : treg,
6691 (int) BFD_RELOC_LO16, AT);
6692 expr1.X_add_number += 4;
6694 /* Set mips_optimize to 2 to avoid inserting an undesired
6696 hold_mips_optimize = mips_optimize;
6698 /* Itbl support may require additional care here. */
6699 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6700 coproc ? treg : treg + 1,
6701 (int) BFD_RELOC_LO16, AT);
6702 mips_optimize = hold_mips_optimize;
6703 expr1.X_add_number -= 4;
6705 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6706 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6707 8 + gpdel + off, 1, 0),
6708 offset_expr.X_add_symbol, 0, NULL);
6711 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6714 macro_build (p, &icnt, &offset_expr,
6715 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6716 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6719 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6723 macro_build (p, &icnt, (expressionS *) NULL,
6724 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6725 "d,v,t", AT, breg, AT);
6728 /* Itbl support may require additional care here. */
6729 macro_build (p, &icnt, &expr1, s, fmt,
6730 coproc ? treg + 1 : treg,
6731 (int) BFD_RELOC_LO16, AT);
6733 expr1.X_add_number += 4;
6735 /* Set mips_optimize to 2 to avoid inserting an undesired
6737 hold_mips_optimize = mips_optimize;
6739 /* Itbl support may require additional care here. */
6740 macro_build (p, &icnt, &expr1, s, fmt,
6741 coproc ? treg : treg + 1,
6742 (int) BFD_RELOC_LO16, AT);
6743 mips_optimize = hold_mips_optimize;
6745 else if (mips_pic == EMBEDDED_PIC)
6747 /* If there is no base register, we use
6748 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6749 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6750 If we have a base register, we use
6752 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6753 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6757 tempreg = mips_gp_register;
6762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6763 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6764 "d,v,t", AT, breg, mips_gp_register);
6769 /* Itbl support may require additional care here. */
6770 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6771 coproc ? treg + 1 : treg,
6772 (int) BFD_RELOC_GPREL16, tempreg);
6773 offset_expr.X_add_number += 4;
6774 /* Itbl support may require additional care here. */
6775 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6776 coproc ? treg : treg + 1,
6777 (int) BFD_RELOC_GPREL16, tempreg);
6793 assert (HAVE_32BIT_ADDRESSES);
6794 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6795 (int) BFD_RELOC_LO16, breg);
6796 offset_expr.X_add_number += 4;
6797 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6798 (int) BFD_RELOC_LO16, breg);
6801 /* New code added to support COPZ instructions.
6802 This code builds table entries out of the macros in mip_opcodes.
6803 R4000 uses interlocks to handle coproc delays.
6804 Other chips (like the R3000) require nops to be inserted for delays.
6806 FIXME: Currently, we require that the user handle delays.
6807 In order to fill delay slots for non-interlocked chips,
6808 we must have a way to specify delays based on the coprocessor.
6809 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6810 What are the side-effects of the cop instruction?
6811 What cache support might we have and what are its effects?
6812 Both coprocessor & memory require delays. how long???
6813 What registers are read/set/modified?
6815 If an itbl is provided to interpret cop instructions,
6816 this knowledge can be encoded in the itbl spec. */
6830 /* For now we just do C (same as Cz). The parameter will be
6831 stored in insn_opcode by mips_ip. */
6832 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6837 move_register (&icnt, dreg, sreg);
6840 #ifdef LOSING_COMPILER
6842 /* Try and see if this is a new itbl instruction.
6843 This code builds table entries out of the macros in mip_opcodes.
6844 FIXME: For now we just assemble the expression and pass it's
6845 value along as a 32-bit immediate.
6846 We may want to have the assembler assemble this value,
6847 so that we gain the assembler's knowledge of delay slots,
6849 Would it be more efficient to use mask (id) here? */
6850 if (itbl_have_entries
6851 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6853 s = ip->insn_mo->name;
6855 coproc = ITBL_DECODE_PNUM (immed_expr);;
6856 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6863 as_warn (_("Macro used $at after \".set noat\""));
6868 struct mips_cl_insn *ip;
6870 register int treg, sreg, dreg, breg;
6886 bfd_reloc_code_real_type r;
6889 treg = (ip->insn_opcode >> 16) & 0x1f;
6890 dreg = (ip->insn_opcode >> 11) & 0x1f;
6891 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6892 mask = ip->insn_mo->mask;
6894 expr1.X_op = O_constant;
6895 expr1.X_op_symbol = NULL;
6896 expr1.X_add_symbol = NULL;
6897 expr1.X_add_number = 1;
6901 #endif /* LOSING_COMPILER */
6906 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6907 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6908 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6915 /* The MIPS assembler some times generates shifts and adds. I'm
6916 not trying to be that fancy. GCC should do this for us
6918 load_register (&icnt, AT, &imm_expr, dbl);
6919 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6920 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6921 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6935 mips_emit_delays (TRUE);
6936 ++mips_opts.noreorder;
6937 mips_any_noreorder = 1;
6939 load_register (&icnt, AT, &imm_expr, dbl);
6940 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6941 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6942 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6944 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6945 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6946 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6949 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6950 "s,t,q", dreg, AT, 6);
6953 expr1.X_add_number = 8;
6954 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6956 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6958 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6961 --mips_opts.noreorder;
6962 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6975 mips_emit_delays (TRUE);
6976 ++mips_opts.noreorder;
6977 mips_any_noreorder = 1;
6979 load_register (&icnt, AT, &imm_expr, dbl);
6980 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6981 dbl ? "dmultu" : "multu",
6982 "s,t", sreg, imm ? AT : treg);
6983 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6985 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6988 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6992 expr1.X_add_number = 8;
6993 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6994 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6996 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6999 --mips_opts.noreorder;
7003 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7015 macro_build ((char *) NULL, &icnt, NULL, "dnegu",
7016 "d,w", tempreg, treg);
7017 macro_build ((char *) NULL, &icnt, NULL, "drorv",
7018 "d,t,s", dreg, sreg, tempreg);
7023 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
7024 "d,v,t", AT, 0, treg);
7025 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7026 "d,t,s", AT, sreg, AT);
7027 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7028 "d,t,s", dreg, sreg, treg);
7029 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7030 "d,v,t", dreg, dreg, AT);
7034 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7046 macro_build ((char *) NULL, &icnt, NULL, "negu",
7047 "d,w", tempreg, treg);
7048 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7049 "d,t,s", dreg, sreg, tempreg);
7054 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7055 "d,v,t", AT, 0, treg);
7056 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7057 "d,t,s", AT, sreg, AT);
7058 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7059 "d,t,s", dreg, sreg, treg);
7060 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7061 "d,v,t", dreg, dreg, AT);
7069 if (imm_expr.X_op != O_constant)
7070 as_bad (_("Improper rotate count"));
7071 rot = imm_expr.X_add_number & 0x3f;
7072 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7074 rot = (64 - rot) & 0x3f;
7076 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7077 "d,w,<", dreg, sreg, rot - 32);
7079 macro_build ((char *) NULL, &icnt, NULL, "dror",
7080 "d,w,<", dreg, sreg, rot);
7085 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7086 "d,w,<", dreg, sreg, 0);
7089 l = (rot < 0x20) ? "dsll" : "dsll32";
7090 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7092 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7093 "d,w,<", AT, sreg, rot);
7094 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7095 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7096 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7097 "d,v,t", dreg, dreg, AT);
7105 if (imm_expr.X_op != O_constant)
7106 as_bad (_("Improper rotate count"));
7107 rot = imm_expr.X_add_number & 0x1f;
7108 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7110 macro_build ((char *) NULL, &icnt, NULL, "ror",
7111 "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7117 "d,w,<", dreg, sreg, 0);
7120 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7121 "d,w,<", AT, sreg, rot);
7122 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7123 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7124 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7125 "d,v,t", dreg, dreg, AT);
7130 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7132 macro_build ((char *) NULL, &icnt, NULL, "drorv",
7133 "d,t,s", dreg, sreg, treg);
7136 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
7137 "d,v,t", AT, 0, treg);
7138 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7139 "d,t,s", AT, sreg, AT);
7140 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7141 "d,t,s", dreg, sreg, treg);
7142 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7143 "d,v,t", dreg, dreg, AT);
7147 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7149 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7150 "d,t,s", dreg, sreg, treg);
7153 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7154 "d,v,t", AT, 0, treg);
7155 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7156 "d,t,s", AT, sreg, AT);
7157 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7158 "d,t,s", dreg, sreg, treg);
7159 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7160 "d,v,t", dreg, dreg, AT);
7168 if (imm_expr.X_op != O_constant)
7169 as_bad (_("Improper rotate count"));
7170 rot = imm_expr.X_add_number & 0x3f;
7171 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7174 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7175 "d,w,<", dreg, sreg, rot - 32);
7177 macro_build ((char *) NULL, &icnt, NULL, "dror",
7178 "d,w,<", dreg, sreg, rot);
7183 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7184 "d,w,<", dreg, sreg, 0);
7187 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7188 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7190 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7191 "d,w,<", AT, sreg, rot);
7192 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7193 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7194 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7195 "d,v,t", dreg, dreg, AT);
7203 if (imm_expr.X_op != O_constant)
7204 as_bad (_("Improper rotate count"));
7205 rot = imm_expr.X_add_number & 0x1f;
7206 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7208 macro_build ((char *) NULL, &icnt, NULL, "ror",
7209 "d,w,<", dreg, sreg, rot);
7214 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7215 "d,w,<", dreg, sreg, 0);
7218 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7219 "d,w,<", AT, sreg, rot);
7220 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7221 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7222 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7223 "d,v,t", dreg, dreg, AT);
7228 if (mips_arch == CPU_R4650)
7230 as_bad (_("opcode not supported on this processor"));
7233 assert (mips_opts.isa == ISA_MIPS1);
7234 /* Even on a big endian machine $fn comes before $fn+1. We have
7235 to adjust when storing to memory. */
7236 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7237 target_big_endian ? treg + 1 : treg,
7238 (int) BFD_RELOC_LO16, breg);
7239 offset_expr.X_add_number += 4;
7240 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7241 target_big_endian ? treg : treg + 1,
7242 (int) BFD_RELOC_LO16, breg);
7247 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7248 treg, (int) BFD_RELOC_LO16);
7250 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7251 sreg, (int) BFD_RELOC_LO16);
7254 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7255 "d,v,t", dreg, sreg, treg);
7256 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7257 dreg, (int) BFD_RELOC_LO16);
7262 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7264 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7265 sreg, (int) BFD_RELOC_LO16);
7270 as_warn (_("Instruction %s: result is always false"),
7272 move_register (&icnt, dreg, 0);
7275 if (imm_expr.X_op == O_constant
7276 && imm_expr.X_add_number >= 0
7277 && imm_expr.X_add_number < 0x10000)
7279 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
7280 sreg, (int) BFD_RELOC_LO16);
7283 else if (imm_expr.X_op == O_constant
7284 && imm_expr.X_add_number > -0x8000
7285 && imm_expr.X_add_number < 0)
7287 imm_expr.X_add_number = -imm_expr.X_add_number;
7288 macro_build ((char *) NULL, &icnt, &imm_expr,
7289 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7290 "t,r,j", dreg, sreg,
7291 (int) BFD_RELOC_LO16);
7296 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7297 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7298 "d,v,t", dreg, sreg, AT);
7301 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7302 (int) BFD_RELOC_LO16);
7307 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7313 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7315 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7316 (int) BFD_RELOC_LO16);
7319 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7321 if (imm_expr.X_op == O_constant
7322 && imm_expr.X_add_number >= -0x8000
7323 && imm_expr.X_add_number < 0x8000)
7325 macro_build ((char *) NULL, &icnt, &imm_expr,
7326 mask == M_SGE_I ? "slti" : "sltiu",
7327 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7332 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7333 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7334 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
7338 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7339 (int) BFD_RELOC_LO16);
7344 case M_SGT: /* sreg > treg <==> treg < sreg */
7350 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7354 case M_SGT_I: /* sreg > I <==> I < sreg */
7360 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7361 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7365 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7371 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7373 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7374 (int) BFD_RELOC_LO16);
7377 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7383 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7384 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7386 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7387 (int) BFD_RELOC_LO16);
7391 if (imm_expr.X_op == O_constant
7392 && imm_expr.X_add_number >= -0x8000
7393 && imm_expr.X_add_number < 0x8000)
7395 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
7396 dreg, sreg, (int) BFD_RELOC_LO16);
7399 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7400 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7405 if (imm_expr.X_op == O_constant
7406 && imm_expr.X_add_number >= -0x8000
7407 && imm_expr.X_add_number < 0x8000)
7409 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7410 dreg, sreg, (int) BFD_RELOC_LO16);
7413 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7414 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7415 "d,v,t", dreg, sreg, AT);
7420 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7421 "d,v,t", dreg, 0, treg);
7423 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7424 "d,v,t", dreg, 0, sreg);
7427 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7428 "d,v,t", dreg, sreg, treg);
7429 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7430 "d,v,t", dreg, 0, dreg);
7435 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7437 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7438 "d,v,t", dreg, 0, sreg);
7443 as_warn (_("Instruction %s: result is always true"),
7445 macro_build ((char *) NULL, &icnt, &expr1,
7446 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7447 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7450 if (imm_expr.X_op == O_constant
7451 && imm_expr.X_add_number >= 0
7452 && imm_expr.X_add_number < 0x10000)
7454 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7455 dreg, sreg, (int) BFD_RELOC_LO16);
7458 else if (imm_expr.X_op == O_constant
7459 && imm_expr.X_add_number > -0x8000
7460 && imm_expr.X_add_number < 0)
7462 imm_expr.X_add_number = -imm_expr.X_add_number;
7463 macro_build ((char *) NULL, &icnt, &imm_expr,
7464 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7465 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7470 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7471 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7472 "d,v,t", dreg, sreg, AT);
7475 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7476 "d,v,t", dreg, 0, dreg);
7484 if (imm_expr.X_op == O_constant
7485 && imm_expr.X_add_number > -0x8000
7486 && imm_expr.X_add_number <= 0x8000)
7488 imm_expr.X_add_number = -imm_expr.X_add_number;
7489 macro_build ((char *) NULL, &icnt, &imm_expr,
7490 dbl ? "daddi" : "addi",
7491 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7494 load_register (&icnt, AT, &imm_expr, dbl);
7495 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7496 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7502 if (imm_expr.X_op == O_constant
7503 && imm_expr.X_add_number > -0x8000
7504 && imm_expr.X_add_number <= 0x8000)
7506 imm_expr.X_add_number = -imm_expr.X_add_number;
7507 macro_build ((char *) NULL, &icnt, &imm_expr,
7508 dbl ? "daddiu" : "addiu",
7509 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7512 load_register (&icnt, AT, &imm_expr, dbl);
7513 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7514 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7535 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7536 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7542 assert (mips_opts.isa == ISA_MIPS1);
7543 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7544 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7547 * Is the double cfc1 instruction a bug in the mips assembler;
7548 * or is there a reason for it?
7550 mips_emit_delays (TRUE);
7551 ++mips_opts.noreorder;
7552 mips_any_noreorder = 1;
7553 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7555 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7557 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7558 expr1.X_add_number = 3;
7559 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7560 (int) BFD_RELOC_LO16);
7561 expr1.X_add_number = 2;
7562 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7563 (int) BFD_RELOC_LO16);
7564 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7566 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7568 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7569 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7571 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7572 --mips_opts.noreorder;
7581 if (offset_expr.X_add_number >= 0x7fff)
7582 as_bad (_("operand overflow"));
7583 /* avoid load delay */
7584 if (! target_big_endian)
7585 ++offset_expr.X_add_number;
7586 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7587 (int) BFD_RELOC_LO16, breg);
7588 if (! target_big_endian)
7589 --offset_expr.X_add_number;
7591 ++offset_expr.X_add_number;
7592 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7593 (int) BFD_RELOC_LO16, breg);
7594 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7596 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7610 if (offset_expr.X_add_number >= 0x8000 - off)
7611 as_bad (_("operand overflow"));
7612 if (! target_big_endian)
7613 offset_expr.X_add_number += off;
7614 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7615 (int) BFD_RELOC_LO16, breg);
7616 if (! target_big_endian)
7617 offset_expr.X_add_number -= off;
7619 offset_expr.X_add_number += off;
7620 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7621 (int) BFD_RELOC_LO16, breg);
7635 load_address (&icnt, AT, &offset_expr, &used_at);
7637 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7638 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7639 "d,v,t", AT, AT, breg);
7640 if (! target_big_endian)
7641 expr1.X_add_number = off;
7643 expr1.X_add_number = 0;
7644 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7645 (int) BFD_RELOC_LO16, AT);
7646 if (! target_big_endian)
7647 expr1.X_add_number = 0;
7649 expr1.X_add_number = off;
7650 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7651 (int) BFD_RELOC_LO16, AT);
7657 load_address (&icnt, AT, &offset_expr, &used_at);
7659 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7660 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7661 "d,v,t", AT, AT, breg);
7662 if (target_big_endian)
7663 expr1.X_add_number = 0;
7664 macro_build ((char *) NULL, &icnt, &expr1,
7665 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7666 (int) BFD_RELOC_LO16, AT);
7667 if (target_big_endian)
7668 expr1.X_add_number = 1;
7670 expr1.X_add_number = 0;
7671 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7672 (int) BFD_RELOC_LO16, AT);
7673 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7675 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7680 if (offset_expr.X_add_number >= 0x7fff)
7681 as_bad (_("operand overflow"));
7682 if (target_big_endian)
7683 ++offset_expr.X_add_number;
7684 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7685 (int) BFD_RELOC_LO16, breg);
7686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7688 if (target_big_endian)
7689 --offset_expr.X_add_number;
7691 ++offset_expr.X_add_number;
7692 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7693 (int) BFD_RELOC_LO16, breg);
7706 if (offset_expr.X_add_number >= 0x8000 - off)
7707 as_bad (_("operand overflow"));
7708 if (! target_big_endian)
7709 offset_expr.X_add_number += off;
7710 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7711 (int) BFD_RELOC_LO16, breg);
7712 if (! target_big_endian)
7713 offset_expr.X_add_number -= off;
7715 offset_expr.X_add_number += off;
7716 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7717 (int) BFD_RELOC_LO16, breg);
7731 load_address (&icnt, AT, &offset_expr, &used_at);
7733 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7734 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7735 "d,v,t", AT, AT, breg);
7736 if (! target_big_endian)
7737 expr1.X_add_number = off;
7739 expr1.X_add_number = 0;
7740 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7741 (int) BFD_RELOC_LO16, AT);
7742 if (! target_big_endian)
7743 expr1.X_add_number = 0;
7745 expr1.X_add_number = off;
7746 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7747 (int) BFD_RELOC_LO16, AT);
7752 load_address (&icnt, AT, &offset_expr, &used_at);
7754 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7755 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7756 "d,v,t", AT, AT, breg);
7757 if (! target_big_endian)
7758 expr1.X_add_number = 0;
7759 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7760 (int) BFD_RELOC_LO16, AT);
7761 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7763 if (! target_big_endian)
7764 expr1.X_add_number = 1;
7766 expr1.X_add_number = 0;
7767 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7768 (int) BFD_RELOC_LO16, AT);
7769 if (! target_big_endian)
7770 expr1.X_add_number = 0;
7772 expr1.X_add_number = 1;
7773 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7774 (int) BFD_RELOC_LO16, AT);
7775 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7777 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7782 /* FIXME: Check if this is one of the itbl macros, since they
7783 are added dynamically. */
7784 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7788 as_warn (_("Macro used $at after \".set noat\""));
7791 /* Implement macros in mips16 mode. */
7795 struct mips_cl_insn *ip;
7798 int xreg, yreg, zreg, tmp;
7802 const char *s, *s2, *s3;
7804 mask = ip->insn_mo->mask;
7806 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7807 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7808 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7812 expr1.X_op = O_constant;
7813 expr1.X_op_symbol = NULL;
7814 expr1.X_add_symbol = NULL;
7815 expr1.X_add_number = 1;
7834 mips_emit_delays (TRUE);
7835 ++mips_opts.noreorder;
7836 mips_any_noreorder = 1;
7837 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7838 dbl ? "ddiv" : "div",
7839 "0,x,y", xreg, yreg);
7840 expr1.X_add_number = 2;
7841 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7842 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7845 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7846 since that causes an overflow. We should do that as well,
7847 but I don't see how to do the comparisons without a temporary
7849 --mips_opts.noreorder;
7850 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7869 mips_emit_delays (TRUE);
7870 ++mips_opts.noreorder;
7871 mips_any_noreorder = 1;
7872 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7874 expr1.X_add_number = 2;
7875 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7876 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7878 --mips_opts.noreorder;
7879 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7885 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7886 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7887 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7896 if (imm_expr.X_op != O_constant)
7897 as_bad (_("Unsupported large constant"));
7898 imm_expr.X_add_number = -imm_expr.X_add_number;
7899 macro_build ((char *) NULL, &icnt, &imm_expr,
7900 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7904 if (imm_expr.X_op != O_constant)
7905 as_bad (_("Unsupported large constant"));
7906 imm_expr.X_add_number = -imm_expr.X_add_number;
7907 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7912 if (imm_expr.X_op != O_constant)
7913 as_bad (_("Unsupported large constant"));
7914 imm_expr.X_add_number = -imm_expr.X_add_number;
7915 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7938 goto do_reverse_branch;
7942 goto do_reverse_branch;
7954 goto do_reverse_branch;
7965 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7967 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7994 goto do_addone_branch_i;
7999 goto do_addone_branch_i;
8014 goto do_addone_branch_i;
8021 if (imm_expr.X_op != O_constant)
8022 as_bad (_("Unsupported large constant"));
8023 ++imm_expr.X_add_number;
8026 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
8027 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
8031 expr1.X_add_number = 0;
8032 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
8034 move_register (&icnt, xreg, yreg);
8035 expr1.X_add_number = 2;
8036 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
8037 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8038 "neg", "x,w", xreg, xreg);
8042 /* For consistency checking, verify that all bits are specified either
8043 by the match/mask part of the instruction definition, or by the
8046 validate_mips_insn (opc)
8047 const struct mips_opcode *opc;
8049 const char *p = opc->args;
8051 unsigned long used_bits = opc->mask;
8053 if ((used_bits & opc->match) != opc->match)
8055 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8056 opc->name, opc->args);
8059 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8069 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8070 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8071 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8072 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8073 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8075 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8076 c, opc->name, opc->args);
8080 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8081 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8083 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8084 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8085 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8086 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8088 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8089 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8091 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8092 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8094 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8095 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8096 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8097 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8098 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8099 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8100 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8101 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8102 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8103 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8104 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8105 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8106 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8107 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8108 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8109 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8110 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8112 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8113 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8114 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8115 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8117 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8118 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8119 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8120 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8121 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8122 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8123 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8124 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8125 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8128 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8129 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8130 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8131 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8132 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8136 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8137 c, opc->name, opc->args);
8141 if (used_bits != 0xffffffff)
8143 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8144 ~used_bits & 0xffffffff, opc->name, opc->args);
8150 /* This routine assembles an instruction into its binary format. As a
8151 side effect, it sets one of the global variables imm_reloc or
8152 offset_reloc to the type of relocation to do if one of the operands
8153 is an address expression. */
8158 struct mips_cl_insn *ip;
8163 struct mips_opcode *insn;
8166 unsigned int lastregno = 0;
8167 unsigned int lastpos = 0;
8168 unsigned int limlo, limhi;
8174 /* If the instruction contains a '.', we first try to match an instruction
8175 including the '.'. Then we try again without the '.'. */
8177 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8180 /* If we stopped on whitespace, then replace the whitespace with null for
8181 the call to hash_find. Save the character we replaced just in case we
8182 have to re-parse the instruction. */
8189 insn = (struct mips_opcode *) hash_find (op_hash, str);
8191 /* If we didn't find the instruction in the opcode table, try again, but
8192 this time with just the instruction up to, but not including the
8196 /* Restore the character we overwrite above (if any). */
8200 /* Scan up to the first '.' or whitespace. */
8202 *s != '\0' && *s != '.' && !ISSPACE (*s);
8206 /* If we did not find a '.', then we can quit now. */
8209 insn_error = "unrecognized opcode";
8213 /* Lookup the instruction in the hash table. */
8215 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8217 insn_error = "unrecognized opcode";
8227 assert (strcmp (insn->name, str) == 0);
8229 if (OPCODE_IS_MEMBER (insn,
8231 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8232 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8233 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8239 if (insn->pinfo != INSN_MACRO)
8241 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8247 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8248 && strcmp (insn->name, insn[1].name) == 0)
8257 static char buf[100];
8258 if (mips_arch_info->is_isa)
8260 _("opcode not supported at this ISA level (%s)"),
8261 mips_cpu_info_from_isa (mips_opts.isa)->name);
8264 _("opcode not supported on this processor: %s (%s)"),
8265 mips_arch_info->name,
8266 mips_cpu_info_from_isa (mips_opts.isa)->name);
8276 ip->insn_opcode = insn->match;
8278 for (args = insn->args;; ++args)
8282 s += strspn (s, " \t");
8286 case '\0': /* end of args */
8299 ip->insn_opcode |= lastregno << OP_SH_RS;
8303 ip->insn_opcode |= lastregno << OP_SH_RT;
8307 ip->insn_opcode |= lastregno << OP_SH_FT;
8311 ip->insn_opcode |= lastregno << OP_SH_FS;
8317 /* Handle optional base register.
8318 Either the base register is omitted or
8319 we must have a left paren. */
8320 /* This is dependent on the next operand specifier
8321 is a base register specification. */
8322 assert (args[1] == 'b' || args[1] == '5'
8323 || args[1] == '-' || args[1] == '4');
8327 case ')': /* these must match exactly */
8334 case '+': /* Opcode extension character. */
8337 case 'A': /* ins/ext position, becomes LSB. */
8340 my_getExpression (&imm_expr, s);
8341 check_absolute_expr (ip, &imm_expr);
8342 if ((unsigned long) imm_expr.X_add_number < limlo
8343 || (unsigned long) imm_expr.X_add_number > limhi)
8345 as_bad (_("Improper position (%lu)"),
8346 (unsigned long) imm_expr.X_add_number);
8347 imm_expr.X_add_number = limlo;
8349 lastpos = imm_expr.X_add_number;
8350 ip->insn_opcode |= (imm_expr.X_add_number
8351 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8352 imm_expr.X_op = O_absent;
8356 case 'B': /* ins size, becomes MSB. */
8359 my_getExpression (&imm_expr, s);
8360 check_absolute_expr (ip, &imm_expr);
8361 /* Check for negative input so that small negative numbers
8362 will not succeed incorrectly. The checks against
8363 (pos+size) transitively check "size" itself,
8364 assuming that "pos" is reasonable. */
8365 if ((long) imm_expr.X_add_number < 0
8366 || ((unsigned long) imm_expr.X_add_number
8368 || ((unsigned long) imm_expr.X_add_number
8371 as_bad (_("Improper insert size (%lu, position %lu)"),
8372 (unsigned long) imm_expr.X_add_number,
8373 (unsigned long) lastpos);
8374 imm_expr.X_add_number = limlo - lastpos;
8376 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8377 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8378 imm_expr.X_op = O_absent;
8382 case 'C': /* ext size, becomes MSBD. */
8385 my_getExpression (&imm_expr, s);
8386 check_absolute_expr (ip, &imm_expr);
8387 /* Check for negative input so that small negative numbers
8388 will not succeed incorrectly. The checks against
8389 (pos+size) transitively check "size" itself,
8390 assuming that "pos" is reasonable. */
8391 if ((long) imm_expr.X_add_number < 0
8392 || ((unsigned long) imm_expr.X_add_number
8394 || ((unsigned long) imm_expr.X_add_number
8397 as_bad (_("Improper extract size (%lu, position %lu)"),
8398 (unsigned long) imm_expr.X_add_number,
8399 (unsigned long) lastpos);
8400 imm_expr.X_add_number = limlo - lastpos;
8402 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8403 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8404 imm_expr.X_op = O_absent;
8409 /* +D is for disassembly only; never match. */
8413 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8414 *args, insn->name, insn->args);
8415 /* Further processing is fruitless. */
8420 case '<': /* must be at least one digit */
8422 * According to the manual, if the shift amount is greater
8423 * than 31 or less than 0, then the shift amount should be
8424 * mod 32. In reality the mips assembler issues an error.
8425 * We issue a warning and mask out all but the low 5 bits.
8427 my_getExpression (&imm_expr, s);
8428 check_absolute_expr (ip, &imm_expr);
8429 if ((unsigned long) imm_expr.X_add_number > 31)
8431 as_warn (_("Improper shift amount (%lu)"),
8432 (unsigned long) imm_expr.X_add_number);
8433 imm_expr.X_add_number &= OP_MASK_SHAMT;
8435 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8436 imm_expr.X_op = O_absent;
8440 case '>': /* shift amount minus 32 */
8441 my_getExpression (&imm_expr, s);
8442 check_absolute_expr (ip, &imm_expr);
8443 if ((unsigned long) imm_expr.X_add_number < 32
8444 || (unsigned long) imm_expr.X_add_number > 63)
8446 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8447 imm_expr.X_op = O_absent;
8451 case 'k': /* cache code */
8452 case 'h': /* prefx code */
8453 my_getExpression (&imm_expr, s);
8454 check_absolute_expr (ip, &imm_expr);
8455 if ((unsigned long) imm_expr.X_add_number > 31)
8457 as_warn (_("Invalid value for `%s' (%lu)"),
8459 (unsigned long) imm_expr.X_add_number);
8460 imm_expr.X_add_number &= 0x1f;
8463 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8465 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8466 imm_expr.X_op = O_absent;
8470 case 'c': /* break code */
8471 my_getExpression (&imm_expr, s);
8472 check_absolute_expr (ip, &imm_expr);
8473 if ((unsigned long) imm_expr.X_add_number > 1023)
8475 as_warn (_("Illegal break code (%lu)"),
8476 (unsigned long) imm_expr.X_add_number);
8477 imm_expr.X_add_number &= OP_MASK_CODE;
8479 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8480 imm_expr.X_op = O_absent;
8484 case 'q': /* lower break code */
8485 my_getExpression (&imm_expr, s);
8486 check_absolute_expr (ip, &imm_expr);
8487 if ((unsigned long) imm_expr.X_add_number > 1023)
8489 as_warn (_("Illegal lower break code (%lu)"),
8490 (unsigned long) imm_expr.X_add_number);
8491 imm_expr.X_add_number &= OP_MASK_CODE2;
8493 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8494 imm_expr.X_op = O_absent;
8498 case 'B': /* 20-bit syscall/break code. */
8499 my_getExpression (&imm_expr, s);
8500 check_absolute_expr (ip, &imm_expr);
8501 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8502 as_warn (_("Illegal 20-bit code (%lu)"),
8503 (unsigned long) imm_expr.X_add_number);
8504 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8505 imm_expr.X_op = O_absent;
8509 case 'C': /* Coprocessor code */
8510 my_getExpression (&imm_expr, s);
8511 check_absolute_expr (ip, &imm_expr);
8512 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8514 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8515 (unsigned long) imm_expr.X_add_number);
8516 imm_expr.X_add_number &= ((1 << 25) - 1);
8518 ip->insn_opcode |= imm_expr.X_add_number;
8519 imm_expr.X_op = O_absent;
8523 case 'J': /* 19-bit wait code. */
8524 my_getExpression (&imm_expr, s);
8525 check_absolute_expr (ip, &imm_expr);
8526 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8527 as_warn (_("Illegal 19-bit code (%lu)"),
8528 (unsigned long) imm_expr.X_add_number);
8529 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8530 imm_expr.X_op = O_absent;
8534 case 'P': /* Performance register */
8535 my_getExpression (&imm_expr, s);
8536 check_absolute_expr (ip, &imm_expr);
8537 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8539 as_warn (_("Invalid performance register (%lu)"),
8540 (unsigned long) imm_expr.X_add_number);
8541 imm_expr.X_add_number &= OP_MASK_PERFREG;
8543 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8544 imm_expr.X_op = O_absent;
8548 case 'b': /* base register */
8549 case 'd': /* destination register */
8550 case 's': /* source register */
8551 case 't': /* target register */
8552 case 'r': /* both target and source */
8553 case 'v': /* both dest and source */
8554 case 'w': /* both dest and target */
8555 case 'E': /* coprocessor target register */
8556 case 'G': /* coprocessor destination register */
8557 case 'K': /* 'rdhwr' destination register */
8558 case 'x': /* ignore register name */
8559 case 'z': /* must be zero register */
8560 case 'U': /* destination register (clo/clz). */
8575 while (ISDIGIT (*s));
8577 as_bad (_("Invalid register number (%d)"), regno);
8579 else if (*args == 'E' || *args == 'G' || *args == 'K')
8583 if (s[1] == 'r' && s[2] == 'a')
8588 else if (s[1] == 'f' && s[2] == 'p')
8593 else if (s[1] == 's' && s[2] == 'p')
8598 else if (s[1] == 'g' && s[2] == 'p')
8603 else if (s[1] == 'a' && s[2] == 't')
8608 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8613 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8618 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8623 else if (itbl_have_entries)
8628 p = s + 1; /* advance past '$' */
8629 n = itbl_get_field (&p); /* n is name */
8631 /* See if this is a register defined in an
8633 if (itbl_get_reg_val (n, &r))
8635 /* Get_field advances to the start of
8636 the next field, so we need to back
8637 rack to the end of the last field. */
8641 s = strchr (s, '\0');
8655 as_warn (_("Used $at without \".set noat\""));
8661 if (c == 'r' || c == 'v' || c == 'w')
8668 /* 'z' only matches $0. */
8669 if (c == 'z' && regno != 0)
8672 /* Now that we have assembled one operand, we use the args string
8673 * to figure out where it goes in the instruction. */
8680 ip->insn_opcode |= regno << OP_SH_RS;
8685 ip->insn_opcode |= regno << OP_SH_RD;
8688 ip->insn_opcode |= regno << OP_SH_RD;
8689 ip->insn_opcode |= regno << OP_SH_RT;
8694 ip->insn_opcode |= regno << OP_SH_RT;
8697 /* This case exists because on the r3000 trunc
8698 expands into a macro which requires a gp
8699 register. On the r6000 or r4000 it is
8700 assembled into a single instruction which
8701 ignores the register. Thus the insn version
8702 is MIPS_ISA2 and uses 'x', and the macro
8703 version is MIPS_ISA1 and uses 't'. */
8706 /* This case is for the div instruction, which
8707 acts differently if the destination argument
8708 is $0. This only matches $0, and is checked
8709 outside the switch. */
8712 /* Itbl operand; not yet implemented. FIXME ?? */
8714 /* What about all other operands like 'i', which
8715 can be specified in the opcode table? */
8725 ip->insn_opcode |= lastregno << OP_SH_RS;
8728 ip->insn_opcode |= lastregno << OP_SH_RT;
8733 case 'O': /* MDMX alignment immediate constant. */
8734 my_getExpression (&imm_expr, s);
8735 check_absolute_expr (ip, &imm_expr);
8736 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8738 as_warn ("Improper align amount (%ld), using low bits",
8739 (long) imm_expr.X_add_number);
8740 imm_expr.X_add_number &= OP_MASK_ALN;
8742 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8743 imm_expr.X_op = O_absent;
8747 case 'Q': /* MDMX vector, element sel, or const. */
8750 /* MDMX Immediate. */
8751 my_getExpression (&imm_expr, s);
8752 check_absolute_expr (ip, &imm_expr);
8753 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8755 as_warn (_("Invalid MDMX Immediate (%ld)"),
8756 (long) imm_expr.X_add_number);
8757 imm_expr.X_add_number &= OP_MASK_FT;
8759 imm_expr.X_add_number &= OP_MASK_FT;
8760 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8761 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8763 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8764 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8765 imm_expr.X_op = O_absent;
8769 /* Not MDMX Immediate. Fall through. */
8770 case 'X': /* MDMX destination register. */
8771 case 'Y': /* MDMX source register. */
8772 case 'Z': /* MDMX target register. */
8774 case 'D': /* floating point destination register */
8775 case 'S': /* floating point source register */
8776 case 'T': /* floating point target register */
8777 case 'R': /* floating point source register */
8781 /* Accept $fN for FP and MDMX register numbers, and in
8782 addition accept $vN for MDMX register numbers. */
8783 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8784 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8795 while (ISDIGIT (*s));
8798 as_bad (_("Invalid float register number (%d)"), regno);
8800 if ((regno & 1) != 0
8802 && ! (strcmp (str, "mtc1") == 0
8803 || strcmp (str, "mfc1") == 0
8804 || strcmp (str, "lwc1") == 0
8805 || strcmp (str, "swc1") == 0
8806 || strcmp (str, "l.s") == 0
8807 || strcmp (str, "s.s") == 0))
8808 as_warn (_("Float register should be even, was %d"),
8816 if (c == 'V' || c == 'W')
8827 ip->insn_opcode |= regno << OP_SH_FD;
8832 ip->insn_opcode |= regno << OP_SH_FS;
8835 /* This is like 'Z', but also needs to fix the MDMX
8836 vector/scalar select bits. Note that the
8837 scalar immediate case is handled above. */
8840 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8841 int max_el = (is_qh ? 3 : 7);
8843 my_getExpression(&imm_expr, s);
8844 check_absolute_expr (ip, &imm_expr);
8846 if (imm_expr.X_add_number > max_el)
8847 as_bad(_("Bad element selector %ld"),
8848 (long) imm_expr.X_add_number);
8849 imm_expr.X_add_number &= max_el;
8850 ip->insn_opcode |= (imm_expr.X_add_number
8854 as_warn(_("Expecting ']' found '%s'"), s);
8860 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8861 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8864 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8871 ip->insn_opcode |= regno << OP_SH_FT;
8874 ip->insn_opcode |= regno << OP_SH_FR;
8884 ip->insn_opcode |= lastregno << OP_SH_FS;
8887 ip->insn_opcode |= lastregno << OP_SH_FT;
8893 my_getExpression (&imm_expr, s);
8894 if (imm_expr.X_op != O_big
8895 && imm_expr.X_op != O_constant)
8896 insn_error = _("absolute expression required");
8901 my_getExpression (&offset_expr, s);
8902 *imm_reloc = BFD_RELOC_32;
8915 unsigned char temp[8];
8917 unsigned int length;
8922 /* These only appear as the last operand in an
8923 instruction, and every instruction that accepts
8924 them in any variant accepts them in all variants.
8925 This means we don't have to worry about backing out
8926 any changes if the instruction does not match.
8928 The difference between them is the size of the
8929 floating point constant and where it goes. For 'F'
8930 and 'L' the constant is 64 bits; for 'f' and 'l' it
8931 is 32 bits. Where the constant is placed is based
8932 on how the MIPS assembler does things:
8935 f -- immediate value
8938 The .lit4 and .lit8 sections are only used if
8939 permitted by the -G argument.
8941 When generating embedded PIC code, we use the
8942 .lit8 section but not the .lit4 section (we can do
8943 .lit4 inline easily; we need to put .lit8
8944 somewhere in the data segment, and using .lit8
8945 permits the linker to eventually combine identical
8948 The code below needs to know whether the target register
8949 is 32 or 64 bits wide. It relies on the fact 'f' and
8950 'F' are used with GPR-based instructions and 'l' and
8951 'L' are used with FPR-based instructions. */
8953 f64 = *args == 'F' || *args == 'L';
8954 using_gprs = *args == 'F' || *args == 'f';
8956 save_in = input_line_pointer;
8957 input_line_pointer = s;
8958 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8960 s = input_line_pointer;
8961 input_line_pointer = save_in;
8962 if (err != NULL && *err != '\0')
8964 as_bad (_("Bad floating point constant: %s"), err);
8965 memset (temp, '\0', sizeof temp);
8966 length = f64 ? 8 : 4;
8969 assert (length == (unsigned) (f64 ? 8 : 4));
8973 && (! USE_GLOBAL_POINTER_OPT
8974 || mips_pic == EMBEDDED_PIC
8975 || g_switch_value < 4
8976 || (temp[0] == 0 && temp[1] == 0)
8977 || (temp[2] == 0 && temp[3] == 0))))
8979 imm_expr.X_op = O_constant;
8980 if (! target_big_endian)
8981 imm_expr.X_add_number = bfd_getl32 (temp);
8983 imm_expr.X_add_number = bfd_getb32 (temp);
8986 && ! mips_disable_float_construction
8987 /* Constants can only be constructed in GPRs and
8988 copied to FPRs if the GPRs are at least as wide
8989 as the FPRs. Force the constant into memory if
8990 we are using 64-bit FPRs but the GPRs are only
8993 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8994 && ((temp[0] == 0 && temp[1] == 0)
8995 || (temp[2] == 0 && temp[3] == 0))
8996 && ((temp[4] == 0 && temp[5] == 0)
8997 || (temp[6] == 0 && temp[7] == 0)))
8999 /* The value is simple enough to load with a couple of
9000 instructions. If using 32-bit registers, set
9001 imm_expr to the high order 32 bits and offset_expr to
9002 the low order 32 bits. Otherwise, set imm_expr to
9003 the entire 64 bit constant. */
9004 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9006 imm_expr.X_op = O_constant;
9007 offset_expr.X_op = O_constant;
9008 if (! target_big_endian)
9010 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9011 offset_expr.X_add_number = bfd_getl32 (temp);
9015 imm_expr.X_add_number = bfd_getb32 (temp);
9016 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9018 if (offset_expr.X_add_number == 0)
9019 offset_expr.X_op = O_absent;
9021 else if (sizeof (imm_expr.X_add_number) > 4)
9023 imm_expr.X_op = O_constant;
9024 if (! target_big_endian)
9025 imm_expr.X_add_number = bfd_getl64 (temp);
9027 imm_expr.X_add_number = bfd_getb64 (temp);
9031 imm_expr.X_op = O_big;
9032 imm_expr.X_add_number = 4;
9033 if (! target_big_endian)
9035 generic_bignum[0] = bfd_getl16 (temp);
9036 generic_bignum[1] = bfd_getl16 (temp + 2);
9037 generic_bignum[2] = bfd_getl16 (temp + 4);
9038 generic_bignum[3] = bfd_getl16 (temp + 6);
9042 generic_bignum[0] = bfd_getb16 (temp + 6);
9043 generic_bignum[1] = bfd_getb16 (temp + 4);
9044 generic_bignum[2] = bfd_getb16 (temp + 2);
9045 generic_bignum[3] = bfd_getb16 (temp);
9051 const char *newname;
9054 /* Switch to the right section. */
9056 subseg = now_subseg;
9059 default: /* unused default case avoids warnings. */
9061 newname = RDATA_SECTION_NAME;
9062 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9063 || mips_pic == EMBEDDED_PIC)
9067 if (mips_pic == EMBEDDED_PIC)
9070 newname = RDATA_SECTION_NAME;
9073 assert (!USE_GLOBAL_POINTER_OPT
9074 || g_switch_value >= 4);
9078 new_seg = subseg_new (newname, (subsegT) 0);
9079 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9080 bfd_set_section_flags (stdoutput, new_seg,
9085 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9086 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9087 && strcmp (TARGET_OS, "elf") != 0)
9088 record_alignment (new_seg, 4);
9090 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9092 as_bad (_("Can't use floating point insn in this section"));
9094 /* Set the argument to the current address in the
9096 offset_expr.X_op = O_symbol;
9097 offset_expr.X_add_symbol =
9098 symbol_new ("L0\001", now_seg,
9099 (valueT) frag_now_fix (), frag_now);
9100 offset_expr.X_add_number = 0;
9102 /* Put the floating point number into the section. */
9103 p = frag_more ((int) length);
9104 memcpy (p, temp, length);
9106 /* Switch back to the original section. */
9107 subseg_set (seg, subseg);
9112 case 'i': /* 16 bit unsigned immediate */
9113 case 'j': /* 16 bit signed immediate */
9114 *imm_reloc = BFD_RELOC_LO16;
9115 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9118 offsetT minval, maxval;
9120 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9121 && strcmp (insn->name, insn[1].name) == 0);
9123 /* If the expression was written as an unsigned number,
9124 only treat it as signed if there are no more
9128 && sizeof (imm_expr.X_add_number) <= 4
9129 && imm_expr.X_op == O_constant
9130 && imm_expr.X_add_number < 0
9131 && imm_expr.X_unsigned
9135 /* For compatibility with older assemblers, we accept
9136 0x8000-0xffff as signed 16-bit numbers when only
9137 signed numbers are allowed. */
9139 minval = 0, maxval = 0xffff;
9141 minval = -0x8000, maxval = 0x7fff;
9143 minval = -0x8000, maxval = 0xffff;
9145 if (imm_expr.X_op != O_constant
9146 || imm_expr.X_add_number < minval
9147 || imm_expr.X_add_number > maxval)
9151 if (imm_expr.X_op == O_constant
9152 || imm_expr.X_op == O_big)
9153 as_bad (_("expression out of range"));
9159 case 'o': /* 16 bit offset */
9160 /* Check whether there is only a single bracketed expression
9161 left. If so, it must be the base register and the
9162 constant must be zero. */
9163 if (*s == '(' && strchr (s + 1, '(') == 0)
9165 offset_expr.X_op = O_constant;
9166 offset_expr.X_add_number = 0;
9170 /* If this value won't fit into a 16 bit offset, then go
9171 find a macro that will generate the 32 bit offset
9173 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9174 && (offset_expr.X_op != O_constant
9175 || offset_expr.X_add_number >= 0x8000
9176 || offset_expr.X_add_number < -0x8000))
9182 case 'p': /* pc relative offset */
9183 if (mips_pic == EMBEDDED_PIC)
9184 *offset_reloc = BFD_RELOC_MIPSEMB_16_PCREL_S2;
9186 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9187 my_getExpression (&offset_expr, s);
9191 case 'u': /* upper 16 bits */
9192 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9193 && imm_expr.X_op == O_constant
9194 && (imm_expr.X_add_number < 0
9195 || imm_expr.X_add_number >= 0x10000))
9196 as_bad (_("lui expression not in range 0..65535"));
9200 case 'a': /* 26 bit address */
9201 my_getExpression (&offset_expr, s);
9203 *offset_reloc = BFD_RELOC_MIPS_JMP;
9206 case 'N': /* 3 bit branch condition code */
9207 case 'M': /* 3 bit compare condition code */
9208 if (strncmp (s, "$fcc", 4) != 0)
9218 while (ISDIGIT (*s));
9220 as_bad (_("invalid condition code register $fcc%d"), regno);
9222 ip->insn_opcode |= regno << OP_SH_BCC;
9224 ip->insn_opcode |= regno << OP_SH_CCC;
9228 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9239 while (ISDIGIT (*s));
9242 c = 8; /* Invalid sel value. */
9245 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9246 ip->insn_opcode |= c;
9250 /* Must be at least one digit. */
9251 my_getExpression (&imm_expr, s);
9252 check_absolute_expr (ip, &imm_expr);
9254 if ((unsigned long) imm_expr.X_add_number
9255 > (unsigned long) OP_MASK_VECBYTE)
9257 as_bad (_("bad byte vector index (%ld)"),
9258 (long) imm_expr.X_add_number);
9259 imm_expr.X_add_number = 0;
9262 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9263 imm_expr.X_op = O_absent;
9268 my_getExpression (&imm_expr, s);
9269 check_absolute_expr (ip, &imm_expr);
9271 if ((unsigned long) imm_expr.X_add_number
9272 > (unsigned long) OP_MASK_VECALIGN)
9274 as_bad (_("bad byte vector index (%ld)"),
9275 (long) imm_expr.X_add_number);
9276 imm_expr.X_add_number = 0;
9279 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9280 imm_expr.X_op = O_absent;
9285 as_bad (_("bad char = '%c'\n"), *args);
9290 /* Args don't match. */
9291 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9292 !strcmp (insn->name, insn[1].name))
9296 insn_error = _("illegal operands");
9301 insn_error = _("illegal operands");
9306 /* This routine assembles an instruction into its binary format when
9307 assembling for the mips16. As a side effect, it sets one of the
9308 global variables imm_reloc or offset_reloc to the type of
9309 relocation to do if one of the operands is an address expression.
9310 It also sets mips16_small and mips16_ext if the user explicitly
9311 requested a small or extended instruction. */
9316 struct mips_cl_insn *ip;
9320 struct mips_opcode *insn;
9323 unsigned int lastregno = 0;
9328 mips16_small = FALSE;
9331 for (s = str; ISLOWER (*s); ++s)
9343 if (s[1] == 't' && s[2] == ' ')
9346 mips16_small = TRUE;
9350 else if (s[1] == 'e' && s[2] == ' ')
9359 insn_error = _("unknown opcode");
9363 if (mips_opts.noautoextend && ! mips16_ext)
9364 mips16_small = TRUE;
9366 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9368 insn_error = _("unrecognized opcode");
9375 assert (strcmp (insn->name, str) == 0);
9378 ip->insn_opcode = insn->match;
9379 ip->use_extend = FALSE;
9380 imm_expr.X_op = O_absent;
9381 imm_reloc[0] = BFD_RELOC_UNUSED;
9382 imm_reloc[1] = BFD_RELOC_UNUSED;
9383 imm_reloc[2] = BFD_RELOC_UNUSED;
9384 offset_expr.X_op = O_absent;
9385 offset_reloc[0] = BFD_RELOC_UNUSED;
9386 offset_reloc[1] = BFD_RELOC_UNUSED;
9387 offset_reloc[2] = BFD_RELOC_UNUSED;
9388 for (args = insn->args; 1; ++args)
9395 /* In this switch statement we call break if we did not find
9396 a match, continue if we did find a match, or return if we
9405 /* Stuff the immediate value in now, if we can. */
9406 if (imm_expr.X_op == O_constant
9407 && *imm_reloc > BFD_RELOC_UNUSED
9408 && insn->pinfo != INSN_MACRO)
9410 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9411 imm_expr.X_add_number, TRUE, mips16_small,
9412 mips16_ext, &ip->insn_opcode,
9413 &ip->use_extend, &ip->extend);
9414 imm_expr.X_op = O_absent;
9415 *imm_reloc = BFD_RELOC_UNUSED;
9429 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9432 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9448 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9450 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9477 while (ISDIGIT (*s));
9480 as_bad (_("invalid register number (%d)"), regno);
9486 if (s[1] == 'r' && s[2] == 'a')
9491 else if (s[1] == 'f' && s[2] == 'p')
9496 else if (s[1] == 's' && s[2] == 'p')
9501 else if (s[1] == 'g' && s[2] == 'p')
9506 else if (s[1] == 'a' && s[2] == 't')
9511 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9516 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9521 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9534 if (c == 'v' || c == 'w')
9536 regno = mips16_to_32_reg_map[lastregno];
9550 regno = mips32_to_16_reg_map[regno];
9555 regno = ILLEGAL_REG;
9560 regno = ILLEGAL_REG;
9565 regno = ILLEGAL_REG;
9570 if (regno == AT && ! mips_opts.noat)
9571 as_warn (_("used $at without \".set noat\""));
9578 if (regno == ILLEGAL_REG)
9585 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9589 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9592 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9595 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9601 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9604 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9605 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9615 if (strncmp (s, "$pc", 3) == 0)
9639 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9641 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9642 and generate the appropriate reloc. If the text
9643 inside %gprel is not a symbol name with an
9644 optional offset, then we generate a normal reloc
9645 and will probably fail later. */
9646 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9647 if (imm_expr.X_op == O_symbol)
9650 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9652 ip->use_extend = TRUE;
9659 /* Just pick up a normal expression. */
9660 my_getExpression (&imm_expr, s);
9663 if (imm_expr.X_op == O_register)
9665 /* What we thought was an expression turned out to
9668 if (s[0] == '(' && args[1] == '(')
9670 /* It looks like the expression was omitted
9671 before a register indirection, which means
9672 that the expression is implicitly zero. We
9673 still set up imm_expr, so that we handle
9674 explicit extensions correctly. */
9675 imm_expr.X_op = O_constant;
9676 imm_expr.X_add_number = 0;
9677 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9684 /* We need to relax this instruction. */
9685 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9694 /* We use offset_reloc rather than imm_reloc for the PC
9695 relative operands. This lets macros with both
9696 immediate and address operands work correctly. */
9697 my_getExpression (&offset_expr, s);
9699 if (offset_expr.X_op == O_register)
9702 /* We need to relax this instruction. */
9703 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9707 case '6': /* break code */
9708 my_getExpression (&imm_expr, s);
9709 check_absolute_expr (ip, &imm_expr);
9710 if ((unsigned long) imm_expr.X_add_number > 63)
9712 as_warn (_("Invalid value for `%s' (%lu)"),
9714 (unsigned long) imm_expr.X_add_number);
9715 imm_expr.X_add_number &= 0x3f;
9717 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9718 imm_expr.X_op = O_absent;
9722 case 'a': /* 26 bit address */
9723 my_getExpression (&offset_expr, s);
9725 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9726 ip->insn_opcode <<= 16;
9729 case 'l': /* register list for entry macro */
9730 case 'L': /* register list for exit macro */
9740 int freg, reg1, reg2;
9742 while (*s == ' ' || *s == ',')
9746 as_bad (_("can't parse register list"));
9758 while (ISDIGIT (*s))
9780 as_bad (_("invalid register list"));
9785 while (ISDIGIT (*s))
9792 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9797 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9802 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9803 mask |= (reg2 - 3) << 3;
9804 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9805 mask |= (reg2 - 15) << 1;
9806 else if (reg1 == RA && reg2 == RA)
9810 as_bad (_("invalid register list"));
9814 /* The mask is filled in in the opcode table for the
9815 benefit of the disassembler. We remove it before
9816 applying the actual mask. */
9817 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9818 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9822 case 'e': /* extend code */
9823 my_getExpression (&imm_expr, s);
9824 check_absolute_expr (ip, &imm_expr);
9825 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9827 as_warn (_("Invalid value for `%s' (%lu)"),
9829 (unsigned long) imm_expr.X_add_number);
9830 imm_expr.X_add_number &= 0x7ff;
9832 ip->insn_opcode |= imm_expr.X_add_number;
9833 imm_expr.X_op = O_absent;
9843 /* Args don't match. */
9844 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9845 strcmp (insn->name, insn[1].name) == 0)
9852 insn_error = _("illegal operands");
9858 /* This structure holds information we know about a mips16 immediate
9861 struct mips16_immed_operand
9863 /* The type code used in the argument string in the opcode table. */
9865 /* The number of bits in the short form of the opcode. */
9867 /* The number of bits in the extended form of the opcode. */
9869 /* The amount by which the short form is shifted when it is used;
9870 for example, the sw instruction has a shift count of 2. */
9872 /* The amount by which the short form is shifted when it is stored
9873 into the instruction code. */
9875 /* Non-zero if the short form is unsigned. */
9877 /* Non-zero if the extended form is unsigned. */
9879 /* Non-zero if the value is PC relative. */
9883 /* The mips16 immediate operand types. */
9885 static const struct mips16_immed_operand mips16_immed_operands[] =
9887 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9888 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9889 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9890 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9891 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9892 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9893 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9894 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9895 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9896 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9897 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9898 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9899 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9900 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9901 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9902 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9903 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9904 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9905 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9906 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9907 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9910 #define MIPS16_NUM_IMMED \
9911 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9913 /* Handle a mips16 instruction with an immediate value. This or's the
9914 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9915 whether an extended value is needed; if one is needed, it sets
9916 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9917 If SMALL is true, an unextended opcode was explicitly requested.
9918 If EXT is true, an extended opcode was explicitly requested. If
9919 WARN is true, warn if EXT does not match reality. */
9922 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9931 unsigned long *insn;
9932 bfd_boolean *use_extend;
9933 unsigned short *extend;
9935 register const struct mips16_immed_operand *op;
9936 int mintiny, maxtiny;
9937 bfd_boolean needext;
9939 op = mips16_immed_operands;
9940 while (op->type != type)
9943 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9948 if (type == '<' || type == '>' || type == '[' || type == ']')
9951 maxtiny = 1 << op->nbits;
9956 maxtiny = (1 << op->nbits) - 1;
9961 mintiny = - (1 << (op->nbits - 1));
9962 maxtiny = (1 << (op->nbits - 1)) - 1;
9965 /* Branch offsets have an implicit 0 in the lowest bit. */
9966 if (type == 'p' || type == 'q')
9969 if ((val & ((1 << op->shift) - 1)) != 0
9970 || val < (mintiny << op->shift)
9971 || val > (maxtiny << op->shift))
9976 if (warn && ext && ! needext)
9977 as_warn_where (file, line,
9978 _("extended operand requested but not required"));
9979 if (small && needext)
9980 as_bad_where (file, line, _("invalid unextended operand value"));
9982 if (small || (! ext && ! needext))
9986 *use_extend = FALSE;
9987 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9988 insnval <<= op->op_shift;
9993 long minext, maxext;
9999 maxext = (1 << op->extbits) - 1;
10003 minext = - (1 << (op->extbits - 1));
10004 maxext = (1 << (op->extbits - 1)) - 1;
10006 if (val < minext || val > maxext)
10007 as_bad_where (file, line,
10008 _("operand value out of range for instruction"));
10010 *use_extend = TRUE;
10011 if (op->extbits == 16)
10013 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10016 else if (op->extbits == 15)
10018 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10023 extval = ((val & 0x1f) << 6) | (val & 0x20);
10027 *extend = (unsigned short) extval;
10032 static const struct percent_op_match
10035 bfd_reloc_code_real_type reloc;
10038 {"%lo", BFD_RELOC_LO16},
10040 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10041 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10042 {"%call16", BFD_RELOC_MIPS_CALL16},
10043 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10044 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10045 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10046 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10047 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10048 {"%got", BFD_RELOC_MIPS_GOT16},
10049 {"%gp_rel", BFD_RELOC_GPREL16},
10050 {"%half", BFD_RELOC_16},
10051 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10052 {"%higher", BFD_RELOC_MIPS_HIGHER},
10053 {"%neg", BFD_RELOC_MIPS_SUB},
10055 {"%hi", BFD_RELOC_HI16_S}
10059 /* Return true if *STR points to a relocation operator. When returning true,
10060 move *STR over the operator and store its relocation code in *RELOC.
10061 Leave both *STR and *RELOC alone when returning false. */
10064 parse_relocation (str, reloc)
10066 bfd_reloc_code_real_type *reloc;
10070 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10071 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10073 *str += strlen (percent_op[i].str);
10074 *reloc = percent_op[i].reloc;
10076 /* Check whether the output BFD supports this relocation.
10077 If not, issue an error and fall back on something safe. */
10078 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10080 as_bad ("relocation %s isn't supported by the current ABI",
10081 percent_op[i].str);
10082 *reloc = BFD_RELOC_LO16;
10090 /* Parse string STR as a 16-bit relocatable operand. Store the
10091 expression in *EP and the relocations in the array starting
10092 at RELOC. Return the number of relocation operators used.
10094 On exit, EXPR_END points to the first character after the expression.
10095 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10098 my_getSmallExpression (ep, reloc, str)
10100 bfd_reloc_code_real_type *reloc;
10103 bfd_reloc_code_real_type reversed_reloc[3];
10104 size_t reloc_index, i;
10105 int crux_depth, str_depth;
10108 /* Search for the start of the main expression, recoding relocations
10109 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10110 of the main expression and with CRUX_DEPTH containing the number
10111 of open brackets at that point. */
10118 crux_depth = str_depth;
10120 /* Skip over whitespace and brackets, keeping count of the number
10122 while (*str == ' ' || *str == '\t' || *str == '(')
10127 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10128 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10130 my_getExpression (ep, crux);
10133 /* Match every open bracket. */
10134 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10138 if (crux_depth > 0)
10139 as_bad ("unclosed '('");
10143 if (reloc_index == 0)
10144 reloc[0] = BFD_RELOC_LO16;
10147 prev_reloc_op_frag = frag_now;
10148 for (i = 0; i < reloc_index; i++)
10149 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10152 return reloc_index;
10156 my_getExpression (ep, str)
10163 save_in = input_line_pointer;
10164 input_line_pointer = str;
10166 expr_end = input_line_pointer;
10167 input_line_pointer = save_in;
10169 /* If we are in mips16 mode, and this is an expression based on `.',
10170 then we bump the value of the symbol by 1 since that is how other
10171 text symbols are handled. We don't bother to handle complex
10172 expressions, just `.' plus or minus a constant. */
10173 if (mips_opts.mips16
10174 && ep->X_op == O_symbol
10175 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10176 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10177 && symbol_get_frag (ep->X_add_symbol) == frag_now
10178 && symbol_constant_p (ep->X_add_symbol)
10179 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10180 S_SET_VALUE (ep->X_add_symbol, val + 1);
10183 /* Turn a string in input_line_pointer into a floating point constant
10184 of type TYPE, and store the appropriate bytes in *LITP. The number
10185 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10186 returned, or NULL on OK. */
10189 md_atof (type, litP, sizeP)
10195 LITTLENUM_TYPE words[4];
10211 return _("bad call to md_atof");
10214 t = atof_ieee (input_line_pointer, type, words);
10216 input_line_pointer = t;
10220 if (! target_big_endian)
10222 for (i = prec - 1; i >= 0; i--)
10224 md_number_to_chars (litP, (valueT) words[i], 2);
10230 for (i = 0; i < prec; i++)
10232 md_number_to_chars (litP, (valueT) words[i], 2);
10241 md_number_to_chars (buf, val, n)
10246 if (target_big_endian)
10247 number_to_chars_bigendian (buf, val, n);
10249 number_to_chars_littleendian (buf, val, n);
10253 static int support_64bit_objects(void)
10255 const char **list, **l;
10258 list = bfd_target_list ();
10259 for (l = list; *l != NULL; l++)
10261 /* This is traditional mips */
10262 if (strcmp (*l, "elf64-tradbigmips") == 0
10263 || strcmp (*l, "elf64-tradlittlemips") == 0)
10265 if (strcmp (*l, "elf64-bigmips") == 0
10266 || strcmp (*l, "elf64-littlemips") == 0)
10269 yes = (*l != NULL);
10273 #endif /* OBJ_ELF */
10275 const char *md_shortopts = "nO::g::G:";
10277 struct option md_longopts[] =
10279 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10280 {"mips0", no_argument, NULL, OPTION_MIPS1},
10281 {"mips1", no_argument, NULL, OPTION_MIPS1},
10282 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10283 {"mips2", no_argument, NULL, OPTION_MIPS2},
10284 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10285 {"mips3", no_argument, NULL, OPTION_MIPS3},
10286 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10287 {"mips4", no_argument, NULL, OPTION_MIPS4},
10288 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10289 {"mips5", no_argument, NULL, OPTION_MIPS5},
10290 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10291 {"mips32", no_argument, NULL, OPTION_MIPS32},
10292 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10293 {"mips64", no_argument, NULL, OPTION_MIPS64},
10294 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10295 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10296 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10297 {"trap", no_argument, NULL, OPTION_TRAP},
10298 {"no-break", no_argument, NULL, OPTION_TRAP},
10299 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10300 {"break", no_argument, NULL, OPTION_BREAK},
10301 {"no-trap", no_argument, NULL, OPTION_BREAK},
10302 #define OPTION_EB (OPTION_MD_BASE + 11)
10303 {"EB", no_argument, NULL, OPTION_EB},
10304 #define OPTION_EL (OPTION_MD_BASE + 12)
10305 {"EL", no_argument, NULL, OPTION_EL},
10306 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10307 {"mips16", no_argument, NULL, OPTION_MIPS16},
10308 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10309 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10310 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10311 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10312 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10313 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10314 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10315 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10316 {"mfp32", no_argument, NULL, OPTION_FP32},
10317 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10318 {"mgp32", no_argument, NULL, OPTION_GP32},
10319 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10320 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10321 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10322 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10323 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10324 {"march", required_argument, NULL, OPTION_MARCH},
10325 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10326 {"mtune", required_argument, NULL, OPTION_MTUNE},
10327 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10328 {"mfp64", no_argument, NULL, OPTION_FP64},
10329 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10330 {"m4650", no_argument, NULL, OPTION_M4650},
10331 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10332 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10333 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10334 {"m4010", no_argument, NULL, OPTION_M4010},
10335 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10336 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10337 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10338 {"m4100", no_argument, NULL, OPTION_M4100},
10339 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10340 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10341 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10342 {"m3900", no_argument, NULL, OPTION_M3900},
10343 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10344 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10345 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10346 {"mgp64", no_argument, NULL, OPTION_GP64},
10347 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10348 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10349 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10350 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10351 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10352 {"mdmx", no_argument, NULL, OPTION_MDMX},
10353 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10354 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10355 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10356 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10357 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10358 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10359 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10360 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10361 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10362 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10363 #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41)
10364 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10366 #define OPTION_ELF_BASE (OPTION_MD_BASE + 42)
10367 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10368 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10369 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10370 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10371 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10372 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10373 {"xgot", no_argument, NULL, OPTION_XGOT},
10374 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10375 {"mabi", required_argument, NULL, OPTION_MABI},
10376 #define OPTION_32 (OPTION_ELF_BASE + 4)
10377 {"32", no_argument, NULL, OPTION_32},
10378 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10379 {"n32", no_argument, NULL, OPTION_N32},
10380 #define OPTION_64 (OPTION_ELF_BASE + 6)
10381 {"64", no_argument, NULL, OPTION_64},
10382 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10383 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10384 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10385 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10386 #endif /* OBJ_ELF */
10387 {NULL, no_argument, NULL, 0}
10389 size_t md_longopts_size = sizeof (md_longopts);
10391 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10392 NEW_VALUE. Warn if another value was already specified. Note:
10393 we have to defer parsing the -march and -mtune arguments in order
10394 to handle 'from-abi' correctly, since the ABI might be specified
10395 in a later argument. */
10398 mips_set_option_string (string_ptr, new_value)
10399 const char **string_ptr, *new_value;
10401 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10402 as_warn (_("A different %s was already specified, is now %s"),
10403 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10406 *string_ptr = new_value;
10410 md_parse_option (c, arg)
10416 case OPTION_CONSTRUCT_FLOATS:
10417 mips_disable_float_construction = 0;
10420 case OPTION_NO_CONSTRUCT_FLOATS:
10421 mips_disable_float_construction = 1;
10433 target_big_endian = 1;
10437 target_big_endian = 0;
10445 if (arg && arg[1] == '0')
10455 mips_debug = atoi (arg);
10456 /* When the MIPS assembler sees -g or -g2, it does not do
10457 optimizations which limit full symbolic debugging. We take
10458 that to be equivalent to -O0. */
10459 if (mips_debug == 2)
10464 file_mips_isa = ISA_MIPS1;
10468 file_mips_isa = ISA_MIPS2;
10472 file_mips_isa = ISA_MIPS3;
10476 file_mips_isa = ISA_MIPS4;
10480 file_mips_isa = ISA_MIPS5;
10483 case OPTION_MIPS32:
10484 file_mips_isa = ISA_MIPS32;
10487 case OPTION_MIPS32R2:
10488 file_mips_isa = ISA_MIPS32R2;
10491 case OPTION_MIPS64:
10492 file_mips_isa = ISA_MIPS64;
10496 mips_set_option_string (&mips_tune_string, arg);
10500 mips_set_option_string (&mips_arch_string, arg);
10504 mips_set_option_string (&mips_arch_string, "4650");
10505 mips_set_option_string (&mips_tune_string, "4650");
10508 case OPTION_NO_M4650:
10512 mips_set_option_string (&mips_arch_string, "4010");
10513 mips_set_option_string (&mips_tune_string, "4010");
10516 case OPTION_NO_M4010:
10520 mips_set_option_string (&mips_arch_string, "4100");
10521 mips_set_option_string (&mips_tune_string, "4100");
10524 case OPTION_NO_M4100:
10528 mips_set_option_string (&mips_arch_string, "3900");
10529 mips_set_option_string (&mips_tune_string, "3900");
10532 case OPTION_NO_M3900:
10536 mips_opts.ase_mdmx = 1;
10539 case OPTION_NO_MDMX:
10540 mips_opts.ase_mdmx = 0;
10543 case OPTION_MIPS16:
10544 mips_opts.mips16 = 1;
10545 mips_no_prev_insn (FALSE);
10548 case OPTION_NO_MIPS16:
10549 mips_opts.mips16 = 0;
10550 mips_no_prev_insn (FALSE);
10553 case OPTION_MIPS3D:
10554 mips_opts.ase_mips3d = 1;
10557 case OPTION_NO_MIPS3D:
10558 mips_opts.ase_mips3d = 0;
10561 case OPTION_MEMBEDDED_PIC:
10562 mips_pic = EMBEDDED_PIC;
10563 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10565 as_bad (_("-G may not be used with embedded PIC code"));
10568 g_switch_value = 0x7fffffff;
10571 case OPTION_FIX_VR4122:
10572 mips_fix_4122_bugs = 1;
10575 case OPTION_NO_FIX_VR4122:
10576 mips_fix_4122_bugs = 0;
10579 case OPTION_RELAX_BRANCH:
10580 mips_relax_branch = 1;
10583 case OPTION_NO_RELAX_BRANCH:
10584 mips_relax_branch = 0;
10588 /* When generating ELF code, we permit -KPIC and -call_shared to
10589 select SVR4_PIC, and -non_shared to select no PIC. This is
10590 intended to be compatible with Irix 5. */
10591 case OPTION_CALL_SHARED:
10592 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10594 as_bad (_("-call_shared is supported only for ELF format"));
10597 mips_pic = SVR4_PIC;
10598 if (g_switch_seen && g_switch_value != 0)
10600 as_bad (_("-G may not be used with SVR4 PIC code"));
10603 g_switch_value = 0;
10606 case OPTION_NON_SHARED:
10607 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10609 as_bad (_("-non_shared is supported only for ELF format"));
10615 /* The -xgot option tells the assembler to use 32 offsets when
10616 accessing the got in SVR4_PIC mode. It is for Irix
10621 #endif /* OBJ_ELF */
10624 if (! USE_GLOBAL_POINTER_OPT)
10626 as_bad (_("-G is not supported for this configuration"));
10629 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10631 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10635 g_switch_value = atoi (arg);
10640 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10643 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10645 as_bad (_("-32 is supported for ELF format only"));
10648 mips_abi = O32_ABI;
10652 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10654 as_bad (_("-n32 is supported for ELF format only"));
10657 mips_abi = N32_ABI;
10661 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10663 as_bad (_("-64 is supported for ELF format only"));
10666 mips_abi = N64_ABI;
10667 if (! support_64bit_objects())
10668 as_fatal (_("No compiled in support for 64 bit object file format"));
10670 #endif /* OBJ_ELF */
10673 file_mips_gp32 = 1;
10677 file_mips_gp32 = 0;
10681 file_mips_fp32 = 1;
10685 file_mips_fp32 = 0;
10690 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10692 as_bad (_("-mabi is supported for ELF format only"));
10695 if (strcmp (arg, "32") == 0)
10696 mips_abi = O32_ABI;
10697 else if (strcmp (arg, "o64") == 0)
10698 mips_abi = O64_ABI;
10699 else if (strcmp (arg, "n32") == 0)
10700 mips_abi = N32_ABI;
10701 else if (strcmp (arg, "64") == 0)
10703 mips_abi = N64_ABI;
10704 if (! support_64bit_objects())
10705 as_fatal (_("No compiled in support for 64 bit object file "
10708 else if (strcmp (arg, "eabi") == 0)
10709 mips_abi = EABI_ABI;
10712 as_fatal (_("invalid abi -mabi=%s"), arg);
10716 #endif /* OBJ_ELF */
10718 case OPTION_M7000_HILO_FIX:
10719 mips_7000_hilo_fix = TRUE;
10722 case OPTION_MNO_7000_HILO_FIX:
10723 mips_7000_hilo_fix = FALSE;
10727 case OPTION_MDEBUG:
10728 mips_flag_mdebug = TRUE;
10731 case OPTION_NO_MDEBUG:
10732 mips_flag_mdebug = FALSE;
10734 #endif /* OBJ_ELF */
10743 /* Set up globals to generate code for the ISA or processor
10744 described by INFO. */
10747 mips_set_architecture (info)
10748 const struct mips_cpu_info *info;
10752 mips_arch_info = info;
10753 mips_arch = info->cpu;
10754 mips_opts.isa = info->isa;
10759 /* Likewise for tuning. */
10762 mips_set_tune (info)
10763 const struct mips_cpu_info *info;
10767 mips_tune_info = info;
10768 mips_tune = info->cpu;
10774 mips_after_parse_args ()
10776 /* GP relative stuff not working for PE */
10777 if (strncmp (TARGET_OS, "pe", 2) == 0
10778 && g_switch_value != 0)
10781 as_bad (_("-G not supported in this configuration."));
10782 g_switch_value = 0;
10785 /* The following code determines the architecture and register size.
10786 Similar code was added to GCC 3.3 (see override_options() in
10787 config/mips/mips.c). The GAS and GCC code should be kept in sync
10788 as much as possible. */
10790 if (mips_arch_string != 0)
10791 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10793 if (mips_tune_string != 0)
10794 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10796 if (file_mips_isa != ISA_UNKNOWN)
10798 /* Handle -mipsN. At this point, file_mips_isa contains the
10799 ISA level specified by -mipsN, while mips_opts.isa contains
10800 the -march selection (if any). */
10801 if (mips_arch_info != 0)
10803 /* -march takes precedence over -mipsN, since it is more descriptive.
10804 There's no harm in specifying both as long as the ISA levels
10806 if (file_mips_isa != mips_opts.isa)
10807 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10808 mips_cpu_info_from_isa (file_mips_isa)->name,
10809 mips_cpu_info_from_isa (mips_opts.isa)->name);
10812 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10815 if (mips_arch_info == 0)
10816 mips_set_architecture (mips_parse_cpu ("default CPU",
10817 MIPS_CPU_STRING_DEFAULT));
10819 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10820 as_bad ("-march=%s is not compatible with the selected ABI",
10821 mips_arch_info->name);
10823 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10824 if (mips_tune_info == 0)
10825 mips_set_tune (mips_arch_info);
10827 if (file_mips_gp32 >= 0)
10829 /* The user specified the size of the integer registers. Make sure
10830 it agrees with the ABI and ISA. */
10831 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10832 as_bad (_("-mgp64 used with a 32-bit processor"));
10833 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10834 as_bad (_("-mgp32 used with a 64-bit ABI"));
10835 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10836 as_bad (_("-mgp64 used with a 32-bit ABI"));
10840 /* Infer the integer register size from the ABI and processor.
10841 Restrict ourselves to 32-bit registers if that's all the
10842 processor has, or if the ABI cannot handle 64-bit registers. */
10843 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10844 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10847 /* ??? GAS treats single-float processors as though they had 64-bit
10848 float registers (although it complains when double-precision
10849 instructions are used). As things stand, saying they have 32-bit
10850 registers would lead to spurious "register must be even" messages.
10851 So here we assume float registers are always the same size as
10852 integer ones, unless the user says otherwise. */
10853 if (file_mips_fp32 < 0)
10854 file_mips_fp32 = file_mips_gp32;
10856 /* End of GCC-shared inference code. */
10858 /* ??? When do we want this flag to be set? Who uses it? */
10859 if (file_mips_gp32 == 1
10860 && mips_abi == NO_ABI
10861 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10862 mips_32bitmode = 1;
10864 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10865 as_bad (_("trap exception not supported at ISA 1"));
10867 /* If the selected architecture includes support for ASEs, enable
10868 generation of code for them. */
10869 if (mips_opts.mips16 == -1)
10870 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10871 if (mips_opts.ase_mips3d == -1)
10872 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10873 if (mips_opts.ase_mdmx == -1)
10874 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10876 file_mips_isa = mips_opts.isa;
10877 file_ase_mips16 = mips_opts.mips16;
10878 file_ase_mips3d = mips_opts.ase_mips3d;
10879 file_ase_mdmx = mips_opts.ase_mdmx;
10880 mips_opts.gp32 = file_mips_gp32;
10881 mips_opts.fp32 = file_mips_fp32;
10883 if (mips_flag_mdebug < 0)
10885 #ifdef OBJ_MAYBE_ECOFF
10886 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10887 mips_flag_mdebug = 1;
10889 #endif /* OBJ_MAYBE_ECOFF */
10890 mips_flag_mdebug = 0;
10895 mips_init_after_args ()
10897 /* initialize opcodes */
10898 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10899 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10903 md_pcrel_from (fixP)
10906 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10907 && fixP->fx_addsy != (symbolS *) NULL
10908 && ! S_IS_DEFINED (fixP->fx_addsy))
10911 /* Return the address of the delay slot. */
10912 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10915 /* This is called before the symbol table is processed. In order to
10916 work with gcc when using mips-tfile, we must keep all local labels.
10917 However, in other cases, we want to discard them. If we were
10918 called with -g, but we didn't see any debugging information, it may
10919 mean that gcc is smuggling debugging information through to
10920 mips-tfile, in which case we must generate all local labels. */
10923 mips_frob_file_before_adjust ()
10925 #ifndef NO_ECOFF_DEBUGGING
10926 if (ECOFF_DEBUGGING
10928 && ! ecoff_debugging_seen)
10929 flag_keep_locals = 1;
10933 /* Sort any unmatched HI16_S relocs so that they immediately precede
10934 the corresponding LO reloc. This is called before md_apply_fix3 and
10935 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10936 explicit use of the %hi modifier. */
10941 struct mips_hi_fixup *l;
10943 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10945 segment_info_type *seginfo;
10948 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10950 /* If a GOT16 relocation turns out to be against a global symbol,
10951 there isn't supposed to be a matching LO. */
10952 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10953 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10956 /* Check quickly whether the next fixup happens to be a matching %lo. */
10957 if (fixup_has_matching_lo_p (l->fixp))
10960 /* Look through the fixups for this segment for a matching %lo.
10961 When we find one, move the %hi just in front of it. We do
10962 this in two passes. In the first pass, we try to find a
10963 unique %lo. In the second pass, we permit multiple %hi
10964 relocs for a single %lo (this is a GNU extension). */
10965 seginfo = seg_info (l->seg);
10966 for (pass = 0; pass < 2; pass++)
10971 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10973 /* Check whether this is a %lo fixup which matches l->fixp. */
10974 if (f->fx_r_type == BFD_RELOC_LO16
10975 && f->fx_addsy == l->fixp->fx_addsy
10976 && f->fx_offset == l->fixp->fx_offset
10979 || !reloc_needs_lo_p (prev->fx_r_type)
10980 || !fixup_has_matching_lo_p (prev)))
10984 /* Move l->fixp before f. */
10985 for (pf = &seginfo->fix_root;
10987 pf = &(*pf)->fx_next)
10988 assert (*pf != NULL);
10990 *pf = l->fixp->fx_next;
10992 l->fixp->fx_next = f;
10994 seginfo->fix_root = l->fixp;
10996 prev->fx_next = l->fixp;
11007 #if 0 /* GCC code motion plus incomplete dead code elimination
11008 can leave a %hi without a %lo. */
11010 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11011 _("Unmatched %%hi reloc"));
11017 /* When generating embedded PIC code we need to use a special
11018 relocation to represent the difference of two symbols in the .text
11019 section (switch tables use a difference of this sort). See
11020 include/coff/mips.h for details. This macro checks whether this
11021 fixup requires the special reloc. */
11022 #define SWITCH_TABLE(fixp) \
11023 ((fixp)->fx_r_type == BFD_RELOC_32 \
11024 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11025 && (fixp)->fx_addsy != NULL \
11026 && (fixp)->fx_subsy != NULL \
11027 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11028 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11030 /* When generating embedded PIC code we must keep all PC relative
11031 relocations, in case the linker has to relax a call. We also need
11032 to keep relocations for switch table entries.
11034 We may have combined relocations without symbols in the N32/N64 ABI.
11035 We have to prevent gas from dropping them. */
11038 mips_force_relocation (fixp)
11041 if (generic_force_reloc (fixp))
11045 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11046 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11047 || fixp->fx_r_type == BFD_RELOC_HI16_S
11048 || fixp->fx_r_type == BFD_RELOC_LO16))
11051 return (mips_pic == EMBEDDED_PIC
11053 || SWITCH_TABLE (fixp)
11054 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11055 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11060 mips_need_elf_addend_fixup (fixP)
11063 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11065 if (mips_pic == EMBEDDED_PIC
11066 && S_IS_WEAK (fixP->fx_addsy))
11068 if (mips_pic != EMBEDDED_PIC
11069 && (S_IS_WEAK (fixP->fx_addsy)
11070 || S_IS_EXTERNAL (fixP->fx_addsy))
11071 && !S_IS_COMMON (fixP->fx_addsy))
11073 if (symbol_used_in_reloc_p (fixP->fx_addsy)
11074 && (((bfd_get_section_flags (stdoutput,
11075 S_GET_SEGMENT (fixP->fx_addsy))
11076 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11077 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11079 sizeof (".gnu.linkonce") - 1)))
11085 /* Apply a fixup to the object file. */
11088 md_apply_fix3 (fixP, valP, seg)
11091 segT seg ATTRIBUTE_UNUSED;
11096 static int previous_fx_r_type = 0;
11098 /* FIXME: Maybe just return for all reloc types not listed below?
11099 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11100 if (fixP->fx_r_type == BFD_RELOC_8)
11103 assert (fixP->fx_size == 4
11104 || fixP->fx_r_type == BFD_RELOC_16
11105 || fixP->fx_r_type == BFD_RELOC_32
11106 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
11107 || fixP->fx_r_type == BFD_RELOC_HI16_S
11108 || fixP->fx_r_type == BFD_RELOC_LO16
11109 || fixP->fx_r_type == BFD_RELOC_GPREL16
11110 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
11111 || fixP->fx_r_type == BFD_RELOC_GPREL32
11112 || fixP->fx_r_type == BFD_RELOC_64
11113 || fixP->fx_r_type == BFD_RELOC_CTOR
11114 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11115 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
11116 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
11117 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
11118 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
11119 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
11120 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11121 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
11122 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
11126 /* If we aren't adjusting this fixup to be against the section
11127 symbol, we need to adjust the value. */
11129 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11131 if (mips_need_elf_addend_fixup (fixP))
11133 reloc_howto_type *howto;
11134 valueT symval = S_GET_VALUE (fixP->fx_addsy);
11138 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11139 if (value != 0 && howto && howto->partial_inplace
11140 && (! fixP->fx_pcrel || howto->pcrel_offset))
11142 /* In this case, the bfd_install_relocation routine will
11143 incorrectly add the symbol value back in. We just want
11144 the addend to appear in the object file.
11146 howto->pcrel_offset is added for R_MIPS_PC16, which is
11147 generated for code like
11158 /* Make sure the addend is still non-zero. If it became zero
11159 after the last operation, set it to a spurious value and
11160 subtract the same value from the object file's contents. */
11165 /* The in-place addends for LO16 relocations are signed;
11166 leave the matching HI16 in-place addends as zero. */
11167 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
11169 bfd_vma contents, mask, field;
11171 contents = bfd_get_bits (fixP->fx_frag->fr_literal
11174 target_big_endian);
11176 /* MASK has bits set where the relocation should go.
11177 FIELD is -value, shifted into the appropriate place
11178 for this relocation. */
11179 mask = 1 << (howto->bitsize - 1);
11180 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
11181 field = (-value >> howto->rightshift) << howto->bitpos;
11183 bfd_put_bits ((field & mask) | (contents & ~mask),
11184 fixP->fx_frag->fr_literal + fixP->fx_where,
11186 target_big_endian);
11192 /* This code was generated using trial and error and so is
11193 fragile and not trustworthy. If you change it, you should
11194 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11195 they still pass. */
11196 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
11198 value += fixP->fx_frag->fr_address + fixP->fx_where;
11200 /* BFD's REL handling, for MIPS, is _very_ weird.
11201 This gives the right results, but it can't possibly
11202 be the way things are supposed to work. */
11203 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11204 && fixP->fx_r_type != BFD_RELOC_MIPSEMB_16_PCREL_S2)
11205 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
11206 value += fixP->fx_frag->fr_address + fixP->fx_where;
11211 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
11213 /* We are not done if this is a composite relocation to set up gp. */
11214 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11215 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11216 || (fixP->fx_r_type == BFD_RELOC_64
11217 && (previous_fx_r_type == BFD_RELOC_GPREL32
11218 || previous_fx_r_type == BFD_RELOC_GPREL16))
11219 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11220 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11221 || fixP->fx_r_type == BFD_RELOC_LO16))))
11223 previous_fx_r_type = fixP->fx_r_type;
11225 switch (fixP->fx_r_type)
11227 case BFD_RELOC_MIPS_JMP:
11228 case BFD_RELOC_MIPS_SHIFT5:
11229 case BFD_RELOC_MIPS_SHIFT6:
11230 case BFD_RELOC_MIPS_GOT_DISP:
11231 case BFD_RELOC_MIPS_GOT_PAGE:
11232 case BFD_RELOC_MIPS_GOT_OFST:
11233 case BFD_RELOC_MIPS_SUB:
11234 case BFD_RELOC_MIPS_INSERT_A:
11235 case BFD_RELOC_MIPS_INSERT_B:
11236 case BFD_RELOC_MIPS_DELETE:
11237 case BFD_RELOC_MIPS_HIGHEST:
11238 case BFD_RELOC_MIPS_HIGHER:
11239 case BFD_RELOC_MIPS_SCN_DISP:
11240 case BFD_RELOC_MIPS_REL16:
11241 case BFD_RELOC_MIPS_RELGOT:
11242 case BFD_RELOC_MIPS_JALR:
11243 case BFD_RELOC_HI16:
11244 case BFD_RELOC_HI16_S:
11245 case BFD_RELOC_GPREL16:
11246 case BFD_RELOC_MIPS_LITERAL:
11247 case BFD_RELOC_MIPS_CALL16:
11248 case BFD_RELOC_MIPS_GOT16:
11249 case BFD_RELOC_GPREL32:
11250 case BFD_RELOC_MIPS_GOT_HI16:
11251 case BFD_RELOC_MIPS_GOT_LO16:
11252 case BFD_RELOC_MIPS_CALL_HI16:
11253 case BFD_RELOC_MIPS_CALL_LO16:
11254 case BFD_RELOC_MIPS16_GPREL:
11255 if (fixP->fx_pcrel)
11256 as_bad_where (fixP->fx_file, fixP->fx_line,
11257 _("Invalid PC relative reloc"));
11258 /* Nothing needed to do. The value comes from the reloc entry */
11261 case BFD_RELOC_MIPS16_JMP:
11262 /* We currently always generate a reloc against a symbol, which
11263 means that we don't want an addend even if the symbol is
11265 fixP->fx_addnumber = 0;
11268 case BFD_RELOC_PCREL_HI16_S:
11269 /* The addend for this is tricky if it is internal, so we just
11270 do everything here rather than in bfd_install_relocation. */
11271 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11276 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11278 /* For an external symbol adjust by the address to make it
11279 pcrel_offset. We use the address of the RELLO reloc
11280 which follows this one. */
11281 value += (fixP->fx_next->fx_frag->fr_address
11282 + fixP->fx_next->fx_where);
11284 value = ((value + 0x8000) >> 16) & 0xffff;
11285 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11286 if (target_big_endian)
11288 md_number_to_chars ((char *) buf, value, 2);
11291 case BFD_RELOC_PCREL_LO16:
11292 /* The addend for this is tricky if it is internal, so we just
11293 do everything here rather than in bfd_install_relocation. */
11294 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11299 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11300 value += fixP->fx_frag->fr_address + fixP->fx_where;
11301 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11302 if (target_big_endian)
11304 md_number_to_chars ((char *) buf, value, 2);
11308 /* This is handled like BFD_RELOC_32, but we output a sign
11309 extended value if we are only 32 bits. */
11311 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11313 if (8 <= sizeof (valueT))
11314 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11321 w1 = w2 = fixP->fx_where;
11322 if (target_big_endian)
11326 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11327 if ((value & 0x80000000) != 0)
11331 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11336 case BFD_RELOC_RVA:
11338 /* If we are deleting this reloc entry, we must fill in the
11339 value now. This can happen if we have a .word which is not
11340 resolved when it appears but is later defined. We also need
11341 to fill in the value if this is an embedded PIC switch table
11344 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11345 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11350 /* If we are deleting this reloc entry, we must fill in the
11352 assert (fixP->fx_size == 2);
11354 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11358 case BFD_RELOC_LO16:
11359 /* When handling an embedded PIC switch statement, we can wind
11360 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11363 if (value + 0x8000 > 0xffff)
11364 as_bad_where (fixP->fx_file, fixP->fx_line,
11365 _("relocation overflow"));
11366 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11367 if (target_big_endian)
11369 md_number_to_chars ((char *) buf, value, 2);
11373 case BFD_RELOC_16_PCREL_S2:
11374 case BFD_RELOC_MIPSEMB_16_PCREL_S2:
11375 if ((value & 0x3) != 0)
11376 as_bad_where (fixP->fx_file, fixP->fx_line,
11377 _("Branch to misaligned address (%lx)"), (long) value);
11380 * We need to save the bits in the instruction since fixup_segment()
11381 * might be deleting the relocation entry (i.e., a branch within
11382 * the current segment).
11384 if (!fixP->fx_done && (value != 0 || HAVE_NEWABI))
11386 /* If 'value' is zero, the remaining reloc code won't actually
11387 do the store, so it must be done here. This is probably
11388 a bug somewhere. */
11390 && (fixP->fx_addsy == NULL /* ??? */
11391 || ! S_IS_DEFINED (fixP->fx_addsy)))
11392 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11394 value = (offsetT) value >> 2;
11396 /* update old instruction data */
11397 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11398 if (target_big_endian)
11399 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11401 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11403 if (value + 0x8000 <= 0xffff)
11404 insn |= value & 0xffff;
11407 /* The branch offset is too large. If this is an
11408 unconditional branch, and we are not generating PIC code,
11409 we can convert it to an absolute jump instruction. */
11410 if (mips_pic == NO_PIC
11412 && fixP->fx_frag->fr_address >= text_section->vma
11413 && (fixP->fx_frag->fr_address
11414 < text_section->vma + text_section->_raw_size)
11415 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11416 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11417 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11419 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11420 insn = 0x0c000000; /* jal */
11422 insn = 0x08000000; /* j */
11423 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11425 fixP->fx_addsy = section_symbol (text_section);
11426 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11430 /* If we got here, we have branch-relaxation disabled,
11431 and there's nothing we can do to fix this instruction
11432 without turning it into a longer sequence. */
11433 as_bad_where (fixP->fx_file, fixP->fx_line,
11434 _("Branch out of range"));
11438 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11441 case BFD_RELOC_VTABLE_INHERIT:
11444 && !S_IS_DEFINED (fixP->fx_addsy)
11445 && !S_IS_WEAK (fixP->fx_addsy))
11446 S_SET_WEAK (fixP->fx_addsy);
11449 case BFD_RELOC_VTABLE_ENTRY:
11463 const struct mips_opcode *p;
11464 int treg, sreg, dreg, shamt;
11469 for (i = 0; i < NUMOPCODES; ++i)
11471 p = &mips_opcodes[i];
11472 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11474 printf ("%08lx %s\t", oc, p->name);
11475 treg = (oc >> 16) & 0x1f;
11476 sreg = (oc >> 21) & 0x1f;
11477 dreg = (oc >> 11) & 0x1f;
11478 shamt = (oc >> 6) & 0x1f;
11480 for (args = p->args;; ++args)
11491 printf ("%c", *args);
11495 assert (treg == sreg);
11496 printf ("$%d,$%d", treg, sreg);
11501 printf ("$%d", dreg);
11506 printf ("$%d", treg);
11510 printf ("0x%x", treg);
11515 printf ("$%d", sreg);
11519 printf ("0x%08lx", oc & 0x1ffffff);
11526 printf ("%d", imm);
11531 printf ("$%d", shamt);
11542 printf (_("%08lx UNDEFINED\n"), oc);
11553 name = input_line_pointer;
11554 c = get_symbol_end ();
11555 p = (symbolS *) symbol_find_or_make (name);
11556 *input_line_pointer = c;
11560 /* Align the current frag to a given power of two. The MIPS assembler
11561 also automatically adjusts any preceding label. */
11564 mips_align (to, fill, label)
11569 mips_emit_delays (FALSE);
11570 frag_align (to, fill, 0);
11571 record_alignment (now_seg, to);
11574 assert (S_GET_SEGMENT (label) == now_seg);
11575 symbol_set_frag (label, frag_now);
11576 S_SET_VALUE (label, (valueT) frag_now_fix ());
11580 /* Align to a given power of two. .align 0 turns off the automatic
11581 alignment used by the data creating pseudo-ops. */
11585 int x ATTRIBUTE_UNUSED;
11588 register long temp_fill;
11589 long max_alignment = 15;
11593 o Note that the assembler pulls down any immediately preceeding label
11594 to the aligned address.
11595 o It's not documented but auto alignment is reinstated by
11596 a .align pseudo instruction.
11597 o Note also that after auto alignment is turned off the mips assembler
11598 issues an error on attempt to assemble an improperly aligned data item.
11603 temp = get_absolute_expression ();
11604 if (temp > max_alignment)
11605 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11608 as_warn (_("Alignment negative: 0 assumed."));
11611 if (*input_line_pointer == ',')
11613 ++input_line_pointer;
11614 temp_fill = get_absolute_expression ();
11621 mips_align (temp, (int) temp_fill,
11622 insn_labels != NULL ? insn_labels->label : NULL);
11629 demand_empty_rest_of_line ();
11633 mips_flush_pending_output ()
11635 mips_emit_delays (FALSE);
11636 mips_clear_insn_labels ();
11645 /* When generating embedded PIC code, we only use the .text, .lit8,
11646 .sdata and .sbss sections. We change the .data and .rdata
11647 pseudo-ops to use .sdata. */
11648 if (mips_pic == EMBEDDED_PIC
11649 && (sec == 'd' || sec == 'r'))
11653 /* The ELF backend needs to know that we are changing sections, so
11654 that .previous works correctly. We could do something like check
11655 for an obj_section_change_hook macro, but that might be confusing
11656 as it would not be appropriate to use it in the section changing
11657 functions in read.c, since obj-elf.c intercepts those. FIXME:
11658 This should be cleaner, somehow. */
11659 obj_elf_section_change_hook ();
11662 mips_emit_delays (FALSE);
11672 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11673 demand_empty_rest_of_line ();
11677 if (USE_GLOBAL_POINTER_OPT)
11679 seg = subseg_new (RDATA_SECTION_NAME,
11680 (subsegT) get_absolute_expression ());
11681 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11683 bfd_set_section_flags (stdoutput, seg,
11689 if (strcmp (TARGET_OS, "elf") != 0)
11690 record_alignment (seg, 4);
11692 demand_empty_rest_of_line ();
11696 as_bad (_("No read only data section in this object file format"));
11697 demand_empty_rest_of_line ();
11703 if (USE_GLOBAL_POINTER_OPT)
11705 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11706 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11708 bfd_set_section_flags (stdoutput, seg,
11709 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11711 if (strcmp (TARGET_OS, "elf") != 0)
11712 record_alignment (seg, 4);
11714 demand_empty_rest_of_line ();
11719 as_bad (_("Global pointers not supported; recompile -G 0"));
11720 demand_empty_rest_of_line ();
11729 s_change_section (ignore)
11730 int ignore ATTRIBUTE_UNUSED;
11733 char *section_name;
11738 int section_entry_size;
11739 int section_alignment;
11741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11744 section_name = input_line_pointer;
11745 c = get_symbol_end ();
11747 next_c = *(input_line_pointer + 1);
11749 /* Do we have .section Name<,"flags">? */
11750 if (c != ',' || (c == ',' && next_c == '"'))
11752 /* just after name is now '\0'. */
11753 *input_line_pointer = c;
11754 input_line_pointer = section_name;
11755 obj_elf_section (ignore);
11758 input_line_pointer++;
11760 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11762 section_type = get_absolute_expression ();
11765 if (*input_line_pointer++ == ',')
11766 section_flag = get_absolute_expression ();
11769 if (*input_line_pointer++ == ',')
11770 section_entry_size = get_absolute_expression ();
11772 section_entry_size = 0;
11773 if (*input_line_pointer++ == ',')
11774 section_alignment = get_absolute_expression ();
11776 section_alignment = 0;
11778 section_name = xstrdup (section_name);
11780 obj_elf_change_section (section_name, section_type, section_flag,
11781 section_entry_size, 0, 0, 0);
11783 if (now_seg->name != section_name)
11784 free (section_name);
11785 #endif /* OBJ_ELF */
11789 mips_enable_auto_align ()
11800 label = insn_labels != NULL ? insn_labels->label : NULL;
11801 mips_emit_delays (FALSE);
11802 if (log_size > 0 && auto_align)
11803 mips_align (log_size, 0, label);
11804 mips_clear_insn_labels ();
11805 cons (1 << log_size);
11809 s_float_cons (type)
11814 label = insn_labels != NULL ? insn_labels->label : NULL;
11816 mips_emit_delays (FALSE);
11821 mips_align (3, 0, label);
11823 mips_align (2, 0, label);
11826 mips_clear_insn_labels ();
11831 /* Handle .globl. We need to override it because on Irix 5 you are
11834 where foo is an undefined symbol, to mean that foo should be
11835 considered to be the address of a function. */
11839 int x ATTRIBUTE_UNUSED;
11846 name = input_line_pointer;
11847 c = get_symbol_end ();
11848 symbolP = symbol_find_or_make (name);
11849 *input_line_pointer = c;
11850 SKIP_WHITESPACE ();
11852 /* On Irix 5, every global symbol that is not explicitly labelled as
11853 being a function is apparently labelled as being an object. */
11856 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11861 secname = input_line_pointer;
11862 c = get_symbol_end ();
11863 sec = bfd_get_section_by_name (stdoutput, secname);
11865 as_bad (_("%s: no such section"), secname);
11866 *input_line_pointer = c;
11868 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11869 flag = BSF_FUNCTION;
11872 symbol_get_bfdsym (symbolP)->flags |= flag;
11874 S_SET_EXTERNAL (symbolP);
11875 demand_empty_rest_of_line ();
11880 int x ATTRIBUTE_UNUSED;
11885 opt = input_line_pointer;
11886 c = get_symbol_end ();
11890 /* FIXME: What does this mean? */
11892 else if (strncmp (opt, "pic", 3) == 0)
11896 i = atoi (opt + 3);
11900 mips_pic = SVR4_PIC;
11902 as_bad (_(".option pic%d not supported"), i);
11904 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11906 if (g_switch_seen && g_switch_value != 0)
11907 as_warn (_("-G may not be used with SVR4 PIC code"));
11908 g_switch_value = 0;
11909 bfd_set_gp_size (stdoutput, 0);
11913 as_warn (_("Unrecognized option \"%s\""), opt);
11915 *input_line_pointer = c;
11916 demand_empty_rest_of_line ();
11919 /* This structure is used to hold a stack of .set values. */
11921 struct mips_option_stack
11923 struct mips_option_stack *next;
11924 struct mips_set_options options;
11927 static struct mips_option_stack *mips_opts_stack;
11929 /* Handle the .set pseudo-op. */
11933 int x ATTRIBUTE_UNUSED;
11935 char *name = input_line_pointer, ch;
11937 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11938 ++input_line_pointer;
11939 ch = *input_line_pointer;
11940 *input_line_pointer = '\0';
11942 if (strcmp (name, "reorder") == 0)
11944 if (mips_opts.noreorder && prev_nop_frag != NULL)
11946 /* If we still have pending nops, we can discard them. The
11947 usual nop handling will insert any that are still
11949 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11950 * (mips_opts.mips16 ? 2 : 4));
11951 prev_nop_frag = NULL;
11953 mips_opts.noreorder = 0;
11955 else if (strcmp (name, "noreorder") == 0)
11957 mips_emit_delays (TRUE);
11958 mips_opts.noreorder = 1;
11959 mips_any_noreorder = 1;
11961 else if (strcmp (name, "at") == 0)
11963 mips_opts.noat = 0;
11965 else if (strcmp (name, "noat") == 0)
11967 mips_opts.noat = 1;
11969 else if (strcmp (name, "macro") == 0)
11971 mips_opts.warn_about_macros = 0;
11973 else if (strcmp (name, "nomacro") == 0)
11975 if (mips_opts.noreorder == 0)
11976 as_bad (_("`noreorder' must be set before `nomacro'"));
11977 mips_opts.warn_about_macros = 1;
11979 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11981 mips_opts.nomove = 0;
11983 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11985 mips_opts.nomove = 1;
11987 else if (strcmp (name, "bopt") == 0)
11989 mips_opts.nobopt = 0;
11991 else if (strcmp (name, "nobopt") == 0)
11993 mips_opts.nobopt = 1;
11995 else if (strcmp (name, "mips16") == 0
11996 || strcmp (name, "MIPS-16") == 0)
11997 mips_opts.mips16 = 1;
11998 else if (strcmp (name, "nomips16") == 0
11999 || strcmp (name, "noMIPS-16") == 0)
12000 mips_opts.mips16 = 0;
12001 else if (strcmp (name, "mips3d") == 0)
12002 mips_opts.ase_mips3d = 1;
12003 else if (strcmp (name, "nomips3d") == 0)
12004 mips_opts.ase_mips3d = 0;
12005 else if (strcmp (name, "mdmx") == 0)
12006 mips_opts.ase_mdmx = 1;
12007 else if (strcmp (name, "nomdmx") == 0)
12008 mips_opts.ase_mdmx = 0;
12009 else if (strncmp (name, "mips", 4) == 0)
12013 /* Permit the user to change the ISA on the fly. Needless to
12014 say, misuse can cause serious problems. */
12015 if (strcmp (name, "mips0") == 0)
12018 mips_opts.isa = file_mips_isa;
12020 else if (strcmp (name, "mips1") == 0)
12021 mips_opts.isa = ISA_MIPS1;
12022 else if (strcmp (name, "mips2") == 0)
12023 mips_opts.isa = ISA_MIPS2;
12024 else if (strcmp (name, "mips3") == 0)
12025 mips_opts.isa = ISA_MIPS3;
12026 else if (strcmp (name, "mips4") == 0)
12027 mips_opts.isa = ISA_MIPS4;
12028 else if (strcmp (name, "mips5") == 0)
12029 mips_opts.isa = ISA_MIPS5;
12030 else if (strcmp (name, "mips32") == 0)
12031 mips_opts.isa = ISA_MIPS32;
12032 else if (strcmp (name, "mips32r2") == 0)
12033 mips_opts.isa = ISA_MIPS32R2;
12034 else if (strcmp (name, "mips64") == 0)
12035 mips_opts.isa = ISA_MIPS64;
12037 as_bad (_("unknown ISA level %s"), name + 4);
12039 switch (mips_opts.isa)
12047 mips_opts.gp32 = 1;
12048 mips_opts.fp32 = 1;
12054 mips_opts.gp32 = 0;
12055 mips_opts.fp32 = 0;
12058 as_bad (_("unknown ISA level %s"), name + 4);
12063 mips_opts.gp32 = file_mips_gp32;
12064 mips_opts.fp32 = file_mips_fp32;
12067 else if (strcmp (name, "autoextend") == 0)
12068 mips_opts.noautoextend = 0;
12069 else if (strcmp (name, "noautoextend") == 0)
12070 mips_opts.noautoextend = 1;
12071 else if (strcmp (name, "push") == 0)
12073 struct mips_option_stack *s;
12075 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12076 s->next = mips_opts_stack;
12077 s->options = mips_opts;
12078 mips_opts_stack = s;
12080 else if (strcmp (name, "pop") == 0)
12082 struct mips_option_stack *s;
12084 s = mips_opts_stack;
12086 as_bad (_(".set pop with no .set push"));
12089 /* If we're changing the reorder mode we need to handle
12090 delay slots correctly. */
12091 if (s->options.noreorder && ! mips_opts.noreorder)
12092 mips_emit_delays (TRUE);
12093 else if (! s->options.noreorder && mips_opts.noreorder)
12095 if (prev_nop_frag != NULL)
12097 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12098 * (mips_opts.mips16 ? 2 : 4));
12099 prev_nop_frag = NULL;
12103 mips_opts = s->options;
12104 mips_opts_stack = s->next;
12110 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12112 *input_line_pointer = ch;
12113 demand_empty_rest_of_line ();
12116 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12117 .option pic2. It means to generate SVR4 PIC calls. */
12120 s_abicalls (ignore)
12121 int ignore ATTRIBUTE_UNUSED;
12123 mips_pic = SVR4_PIC;
12124 if (USE_GLOBAL_POINTER_OPT)
12126 if (g_switch_seen && g_switch_value != 0)
12127 as_warn (_("-G may not be used with SVR4 PIC code"));
12128 g_switch_value = 0;
12130 bfd_set_gp_size (stdoutput, 0);
12131 demand_empty_rest_of_line ();
12134 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12135 PIC code. It sets the $gp register for the function based on the
12136 function address, which is in the register named in the argument.
12137 This uses a relocation against _gp_disp, which is handled specially
12138 by the linker. The result is:
12139 lui $gp,%hi(_gp_disp)
12140 addiu $gp,$gp,%lo(_gp_disp)
12141 addu $gp,$gp,.cpload argument
12142 The .cpload argument is normally $25 == $t9. */
12146 int ignore ATTRIBUTE_UNUSED;
12151 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12152 .cpload is ignored. */
12153 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12159 /* .cpload should be in a .set noreorder section. */
12160 if (mips_opts.noreorder == 0)
12161 as_warn (_(".cpload not in noreorder section"));
12163 ex.X_op = O_symbol;
12164 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12165 ex.X_op_symbol = NULL;
12166 ex.X_add_number = 0;
12168 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12169 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12171 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12172 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
12173 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
12175 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
12176 mips_gp_register, mips_gp_register, tc_get_register (0));
12178 demand_empty_rest_of_line ();
12181 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12182 .cpsetup $reg1, offset|$reg2, label
12184 If offset is given, this results in:
12185 sd $gp, offset($sp)
12186 lui $gp, %hi(%neg(%gp_rel(label)))
12187 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12188 daddu $gp, $gp, $reg1
12190 If $reg2 is given, this results in:
12191 daddu $reg2, $gp, $0
12192 lui $gp, %hi(%neg(%gp_rel(label)))
12193 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12194 daddu $gp, $gp, $reg1
12195 $reg1 is normally $25 == $t9. */
12198 int ignore ATTRIBUTE_UNUSED;
12200 expressionS ex_off;
12201 expressionS ex_sym;
12206 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12207 We also need NewABI support. */
12208 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12214 reg1 = tc_get_register (0);
12215 SKIP_WHITESPACE ();
12216 if (*input_line_pointer != ',')
12218 as_bad (_("missing argument separator ',' for .cpsetup"));
12222 ++input_line_pointer;
12223 SKIP_WHITESPACE ();
12224 if (*input_line_pointer == '$')
12226 mips_cpreturn_register = tc_get_register (0);
12227 mips_cpreturn_offset = -1;
12231 mips_cpreturn_offset = get_absolute_expression ();
12232 mips_cpreturn_register = -1;
12234 SKIP_WHITESPACE ();
12235 if (*input_line_pointer != ',')
12237 as_bad (_("missing argument separator ',' for .cpsetup"));
12241 ++input_line_pointer;
12242 SKIP_WHITESPACE ();
12243 expression (&ex_sym);
12245 if (mips_cpreturn_register == -1)
12247 ex_off.X_op = O_constant;
12248 ex_off.X_add_symbol = NULL;
12249 ex_off.X_op_symbol = NULL;
12250 ex_off.X_add_number = mips_cpreturn_offset;
12252 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
12253 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12256 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12257 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
12259 /* Ensure there's room for the next two instructions, so that `f'
12260 doesn't end up with an address in the wrong frag. */
12263 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12264 (int) BFD_RELOC_GPREL16);
12265 fix_new (frag_now, f - frag_now->fr_literal,
12266 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12267 fix_new (frag_now, f - frag_now->fr_literal,
12268 0, NULL, 0, 0, BFD_RELOC_HI16_S);
12271 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
12272 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
12273 fix_new (frag_now, f - frag_now->fr_literal,
12274 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12275 fix_new (frag_now, f - frag_now->fr_literal,
12276 0, NULL, 0, 0, BFD_RELOC_LO16);
12278 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12279 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
12280 mips_gp_register, mips_gp_register, reg1);
12282 demand_empty_rest_of_line ();
12287 int ignore ATTRIBUTE_UNUSED;
12289 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12290 .cplocal is ignored. */
12291 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12297 mips_gp_register = tc_get_register (0);
12298 demand_empty_rest_of_line ();
12301 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12302 offset from $sp. The offset is remembered, and after making a PIC
12303 call $gp is restored from that location. */
12306 s_cprestore (ignore)
12307 int ignore ATTRIBUTE_UNUSED;
12312 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12313 .cprestore is ignored. */
12314 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12320 mips_cprestore_offset = get_absolute_expression ();
12321 mips_cprestore_valid = 1;
12323 ex.X_op = O_constant;
12324 ex.X_add_symbol = NULL;
12325 ex.X_op_symbol = NULL;
12326 ex.X_add_number = mips_cprestore_offset;
12328 macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex,
12329 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
12330 mips_gp_register, SP);
12332 demand_empty_rest_of_line ();
12335 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12336 was given in the preceeding .gpsetup, it results in:
12337 ld $gp, offset($sp)
12339 If a register $reg2 was given there, it results in:
12340 daddiu $gp, $gp, $reg2
12343 s_cpreturn (ignore)
12344 int ignore ATTRIBUTE_UNUSED;
12349 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12350 We also need NewABI support. */
12351 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12357 if (mips_cpreturn_register == -1)
12359 ex.X_op = O_constant;
12360 ex.X_add_symbol = NULL;
12361 ex.X_op_symbol = NULL;
12362 ex.X_add_number = mips_cpreturn_offset;
12364 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12365 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12369 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12371 demand_empty_rest_of_line ();
12374 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12375 code. It sets the offset to use in gp_rel relocations. */
12379 int ignore ATTRIBUTE_UNUSED;
12381 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12382 We also need NewABI support. */
12383 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12389 mips_gprel_offset = get_absolute_expression ();
12391 demand_empty_rest_of_line ();
12394 /* Handle the .gpword pseudo-op. This is used when generating PIC
12395 code. It generates a 32 bit GP relative reloc. */
12399 int ignore ATTRIBUTE_UNUSED;
12405 /* When not generating PIC code, this is treated as .word. */
12406 if (mips_pic != SVR4_PIC)
12412 label = insn_labels != NULL ? insn_labels->label : NULL;
12413 mips_emit_delays (TRUE);
12415 mips_align (2, 0, label);
12416 mips_clear_insn_labels ();
12420 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12422 as_bad (_("Unsupported use of .gpword"));
12423 ignore_rest_of_line ();
12427 md_number_to_chars (p, (valueT) 0, 4);
12428 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12429 BFD_RELOC_GPREL32);
12431 demand_empty_rest_of_line ();
12436 int ignore ATTRIBUTE_UNUSED;
12442 /* When not generating PIC code, this is treated as .dword. */
12443 if (mips_pic != SVR4_PIC)
12449 label = insn_labels != NULL ? insn_labels->label : NULL;
12450 mips_emit_delays (TRUE);
12452 mips_align (3, 0, label);
12453 mips_clear_insn_labels ();
12457 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12459 as_bad (_("Unsupported use of .gpdword"));
12460 ignore_rest_of_line ();
12464 md_number_to_chars (p, (valueT) 0, 8);
12465 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12466 BFD_RELOC_GPREL32);
12468 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12469 ex.X_op = O_absent;
12470 ex.X_add_symbol = 0;
12471 ex.X_add_number = 0;
12472 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12475 demand_empty_rest_of_line ();
12478 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12479 tables in SVR4 PIC code. */
12483 int ignore ATTRIBUTE_UNUSED;
12488 /* This is ignored when not generating SVR4 PIC code. */
12489 if (mips_pic != SVR4_PIC)
12495 /* Add $gp to the register named as an argument. */
12496 reg = tc_get_register (0);
12497 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12498 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12499 "d,v,t", reg, reg, mips_gp_register);
12501 demand_empty_rest_of_line ();
12504 /* Handle the .insn pseudo-op. This marks instruction labels in
12505 mips16 mode. This permits the linker to handle them specially,
12506 such as generating jalx instructions when needed. We also make
12507 them odd for the duration of the assembly, in order to generate the
12508 right sort of code. We will make them even in the adjust_symtab
12509 routine, while leaving them marked. This is convenient for the
12510 debugger and the disassembler. The linker knows to make them odd
12515 int ignore ATTRIBUTE_UNUSED;
12517 mips16_mark_labels ();
12519 demand_empty_rest_of_line ();
12522 /* Handle a .stabn directive. We need these in order to mark a label
12523 as being a mips16 text label correctly. Sometimes the compiler
12524 will emit a label, followed by a .stabn, and then switch sections.
12525 If the label and .stabn are in mips16 mode, then the label is
12526 really a mips16 text label. */
12533 mips16_mark_labels ();
12538 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12542 s_mips_weakext (ignore)
12543 int ignore ATTRIBUTE_UNUSED;
12550 name = input_line_pointer;
12551 c = get_symbol_end ();
12552 symbolP = symbol_find_or_make (name);
12553 S_SET_WEAK (symbolP);
12554 *input_line_pointer = c;
12556 SKIP_WHITESPACE ();
12558 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12560 if (S_IS_DEFINED (symbolP))
12562 as_bad ("ignoring attempt to redefine symbol %s",
12563 S_GET_NAME (symbolP));
12564 ignore_rest_of_line ();
12568 if (*input_line_pointer == ',')
12570 ++input_line_pointer;
12571 SKIP_WHITESPACE ();
12575 if (exp.X_op != O_symbol)
12577 as_bad ("bad .weakext directive");
12578 ignore_rest_of_line ();
12581 symbol_set_value_expression (symbolP, &exp);
12584 demand_empty_rest_of_line ();
12587 /* Parse a register string into a number. Called from the ECOFF code
12588 to parse .frame. The argument is non-zero if this is the frame
12589 register, so that we can record it in mips_frame_reg. */
12592 tc_get_register (frame)
12597 SKIP_WHITESPACE ();
12598 if (*input_line_pointer++ != '$')
12600 as_warn (_("expected `$'"));
12603 else if (ISDIGIT (*input_line_pointer))
12605 reg = get_absolute_expression ();
12606 if (reg < 0 || reg >= 32)
12608 as_warn (_("Bad register number"));
12614 if (strncmp (input_line_pointer, "ra", 2) == 0)
12617 input_line_pointer += 2;
12619 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12622 input_line_pointer += 2;
12624 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12627 input_line_pointer += 2;
12629 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12632 input_line_pointer += 2;
12634 else if (strncmp (input_line_pointer, "at", 2) == 0)
12637 input_line_pointer += 2;
12639 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12642 input_line_pointer += 3;
12644 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12647 input_line_pointer += 3;
12649 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12652 input_line_pointer += 4;
12656 as_warn (_("Unrecognized register name"));
12658 while (ISALNUM(*input_line_pointer))
12659 input_line_pointer++;
12664 mips_frame_reg = reg != 0 ? reg : SP;
12665 mips_frame_reg_valid = 1;
12666 mips_cprestore_valid = 0;
12672 md_section_align (seg, addr)
12676 int align = bfd_get_section_alignment (stdoutput, seg);
12679 /* We don't need to align ELF sections to the full alignment.
12680 However, Irix 5 may prefer that we align them at least to a 16
12681 byte boundary. We don't bother to align the sections if we are
12682 targeted for an embedded system. */
12683 if (strcmp (TARGET_OS, "elf") == 0)
12689 return ((addr + (1 << align) - 1) & (-1 << align));
12692 /* Utility routine, called from above as well. If called while the
12693 input file is still being read, it's only an approximation. (For
12694 example, a symbol may later become defined which appeared to be
12695 undefined earlier.) */
12698 nopic_need_relax (sym, before_relaxing)
12700 int before_relaxing;
12705 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12707 const char *symname;
12710 /* Find out whether this symbol can be referenced off the $gp
12711 register. It can be if it is smaller than the -G size or if
12712 it is in the .sdata or .sbss section. Certain symbols can
12713 not be referenced off the $gp, although it appears as though
12715 symname = S_GET_NAME (sym);
12716 if (symname != (const char *) NULL
12717 && (strcmp (symname, "eprol") == 0
12718 || strcmp (symname, "etext") == 0
12719 || strcmp (symname, "_gp") == 0
12720 || strcmp (symname, "edata") == 0
12721 || strcmp (symname, "_fbss") == 0
12722 || strcmp (symname, "_fdata") == 0
12723 || strcmp (symname, "_ftext") == 0
12724 || strcmp (symname, "end") == 0
12725 || strcmp (symname, "_gp_disp") == 0))
12727 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12729 #ifndef NO_ECOFF_DEBUGGING
12730 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12731 && (symbol_get_obj (sym)->ecoff_extern_size
12732 <= g_switch_value))
12734 /* We must defer this decision until after the whole
12735 file has been read, since there might be a .extern
12736 after the first use of this symbol. */
12737 || (before_relaxing
12738 #ifndef NO_ECOFF_DEBUGGING
12739 && symbol_get_obj (sym)->ecoff_extern_size == 0
12741 && S_GET_VALUE (sym) == 0)
12742 || (S_GET_VALUE (sym) != 0
12743 && S_GET_VALUE (sym) <= g_switch_value)))
12747 const char *segname;
12749 segname = segment_name (S_GET_SEGMENT (sym));
12750 assert (strcmp (segname, ".lit8") != 0
12751 && strcmp (segname, ".lit4") != 0);
12752 change = (strcmp (segname, ".sdata") != 0
12753 && strcmp (segname, ".sbss") != 0
12754 && strncmp (segname, ".sdata.", 7) != 0
12755 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12760 /* We are not optimizing for the $gp register. */
12765 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12768 pic_need_relax (sym, segtype)
12773 bfd_boolean linkonce;
12775 /* Handle the case of a symbol equated to another symbol. */
12776 while (symbol_equated_reloc_p (sym))
12780 /* It's possible to get a loop here in a badly written
12782 n = symbol_get_value_expression (sym)->X_add_symbol;
12788 symsec = S_GET_SEGMENT (sym);
12790 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12792 if (symsec != segtype && ! S_IS_LOCAL (sym))
12794 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12798 /* The GNU toolchain uses an extension for ELF: a section
12799 beginning with the magic string .gnu.linkonce is a linkonce
12801 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12802 sizeof ".gnu.linkonce" - 1) == 0)
12806 /* This must duplicate the test in adjust_reloc_syms. */
12807 return (symsec != &bfd_und_section
12808 && symsec != &bfd_abs_section
12809 && ! bfd_is_com_section (symsec)
12812 /* A global or weak symbol is treated as external. */
12813 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12814 || (! S_IS_WEAK (sym)
12815 && (! S_IS_EXTERNAL (sym)
12816 || mips_pic == EMBEDDED_PIC)))
12822 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12823 extended opcode. SEC is the section the frag is in. */
12826 mips16_extended_frag (fragp, sec, stretch)
12832 register const struct mips16_immed_operand *op;
12834 int mintiny, maxtiny;
12838 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12840 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12843 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12844 op = mips16_immed_operands;
12845 while (op->type != type)
12848 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12853 if (type == '<' || type == '>' || type == '[' || type == ']')
12856 maxtiny = 1 << op->nbits;
12861 maxtiny = (1 << op->nbits) - 1;
12866 mintiny = - (1 << (op->nbits - 1));
12867 maxtiny = (1 << (op->nbits - 1)) - 1;
12870 sym_frag = symbol_get_frag (fragp->fr_symbol);
12871 val = S_GET_VALUE (fragp->fr_symbol);
12872 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12878 /* We won't have the section when we are called from
12879 mips_relax_frag. However, we will always have been called
12880 from md_estimate_size_before_relax first. If this is a
12881 branch to a different section, we mark it as such. If SEC is
12882 NULL, and the frag is not marked, then it must be a branch to
12883 the same section. */
12886 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12891 /* Must have been called from md_estimate_size_before_relax. */
12894 fragp->fr_subtype =
12895 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12897 /* FIXME: We should support this, and let the linker
12898 catch branches and loads that are out of range. */
12899 as_bad_where (fragp->fr_file, fragp->fr_line,
12900 _("unsupported PC relative reference to different section"));
12904 if (fragp != sym_frag && sym_frag->fr_address == 0)
12905 /* Assume non-extended on the first relaxation pass.
12906 The address we have calculated will be bogus if this is
12907 a forward branch to another frag, as the forward frag
12908 will have fr_address == 0. */
12912 /* In this case, we know for sure that the symbol fragment is in
12913 the same section. If the relax_marker of the symbol fragment
12914 differs from the relax_marker of this fragment, we have not
12915 yet adjusted the symbol fragment fr_address. We want to add
12916 in STRETCH in order to get a better estimate of the address.
12917 This particularly matters because of the shift bits. */
12919 && sym_frag->relax_marker != fragp->relax_marker)
12923 /* Adjust stretch for any alignment frag. Note that if have
12924 been expanding the earlier code, the symbol may be
12925 defined in what appears to be an earlier frag. FIXME:
12926 This doesn't handle the fr_subtype field, which specifies
12927 a maximum number of bytes to skip when doing an
12929 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12931 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12934 stretch = - ((- stretch)
12935 & ~ ((1 << (int) f->fr_offset) - 1));
12937 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12946 addr = fragp->fr_address + fragp->fr_fix;
12948 /* The base address rules are complicated. The base address of
12949 a branch is the following instruction. The base address of a
12950 PC relative load or add is the instruction itself, but if it
12951 is in a delay slot (in which case it can not be extended) use
12952 the address of the instruction whose delay slot it is in. */
12953 if (type == 'p' || type == 'q')
12957 /* If we are currently assuming that this frag should be
12958 extended, then, the current address is two bytes
12960 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12963 /* Ignore the low bit in the target, since it will be set
12964 for a text label. */
12965 if ((val & 1) != 0)
12968 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12970 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12973 val -= addr & ~ ((1 << op->shift) - 1);
12975 /* Branch offsets have an implicit 0 in the lowest bit. */
12976 if (type == 'p' || type == 'q')
12979 /* If any of the shifted bits are set, we must use an extended
12980 opcode. If the address depends on the size of this
12981 instruction, this can lead to a loop, so we arrange to always
12982 use an extended opcode. We only check this when we are in
12983 the main relaxation loop, when SEC is NULL. */
12984 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12986 fragp->fr_subtype =
12987 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12991 /* If we are about to mark a frag as extended because the value
12992 is precisely maxtiny + 1, then there is a chance of an
12993 infinite loop as in the following code:
12998 In this case when the la is extended, foo is 0x3fc bytes
12999 away, so the la can be shrunk, but then foo is 0x400 away, so
13000 the la must be extended. To avoid this loop, we mark the
13001 frag as extended if it was small, and is about to become
13002 extended with a value of maxtiny + 1. */
13003 if (val == ((maxtiny + 1) << op->shift)
13004 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13007 fragp->fr_subtype =
13008 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13012 else if (symsec != absolute_section && sec != NULL)
13013 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13015 if ((val & ((1 << op->shift) - 1)) != 0
13016 || val < (mintiny << op->shift)
13017 || val > (maxtiny << op->shift))
13023 /* Compute the length of a branch sequence, and adjust the
13024 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13025 worst-case length is computed, with UPDATE being used to indicate
13026 whether an unconditional (-1), branch-likely (+1) or regular (0)
13027 branch is to be computed. */
13029 relaxed_branch_length (fragp, sec, update)
13034 bfd_boolean toofar;
13038 && S_IS_DEFINED (fragp->fr_symbol)
13039 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13044 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13046 addr = fragp->fr_address + fragp->fr_fix + 4;
13050 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13053 /* If the symbol is not defined or it's in a different segment,
13054 assume the user knows what's going on and emit a short
13060 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13062 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13063 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13064 RELAX_BRANCH_LINK (fragp->fr_subtype),
13070 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13073 if (mips_pic != NO_PIC)
13075 /* Additional space for PIC loading of target address. */
13077 if (mips_opts.isa == ISA_MIPS1)
13078 /* Additional space for $at-stabilizing nop. */
13082 /* If branch is conditional. */
13083 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13090 /* Estimate the size of a frag before relaxing. Unless this is the
13091 mips16, we are not really relaxing here, and the final size is
13092 encoded in the subtype information. For the mips16, we have to
13093 decide whether we are using an extended opcode or not. */
13096 md_estimate_size_before_relax (fragp, segtype)
13102 if (RELAX_BRANCH_P (fragp->fr_subtype))
13105 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13107 return fragp->fr_var;
13110 if (RELAX_MIPS16_P (fragp->fr_subtype))
13111 /* We don't want to modify the EXTENDED bit here; it might get us
13112 into infinite loops. We change it only in mips_relax_frag(). */
13113 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13115 if (mips_pic == NO_PIC)
13116 change = nopic_need_relax (fragp->fr_symbol, 0);
13117 else if (mips_pic == SVR4_PIC)
13118 change = pic_need_relax (fragp->fr_symbol, segtype);
13124 /* Record the offset to the first reloc in the fr_opcode field.
13125 This lets md_convert_frag and tc_gen_reloc know that the code
13126 must be expanded. */
13127 fragp->fr_opcode = (fragp->fr_literal
13129 - RELAX_OLD (fragp->fr_subtype)
13130 + RELAX_RELOC1 (fragp->fr_subtype));
13131 /* FIXME: This really needs as_warn_where. */
13132 if (RELAX_WARN (fragp->fr_subtype))
13133 as_warn (_("AT used after \".set noat\" or macro used after "
13134 "\".set nomacro\""));
13136 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13142 /* This is called to see whether a reloc against a defined symbol
13143 should be converted into a reloc against a section. Don't adjust
13144 MIPS16 jump relocations, so we don't have to worry about the format
13145 of the offset in the .o file. Don't adjust relocations against
13146 mips16 symbols, so that the linker can find them if it needs to set
13150 mips_fix_adjustable (fixp)
13153 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13156 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13157 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13160 if (fixp->fx_addsy == NULL)
13164 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13165 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13166 && fixp->fx_subsy == NULL)
13173 /* Translate internal representation of relocation info to BFD target
13177 tc_gen_reloc (section, fixp)
13178 asection *section ATTRIBUTE_UNUSED;
13181 static arelent *retval[4];
13183 bfd_reloc_code_real_type code;
13185 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
13188 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13189 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13190 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13192 if (mips_pic == EMBEDDED_PIC
13193 && SWITCH_TABLE (fixp))
13195 /* For a switch table entry we use a special reloc. The addend
13196 is actually the difference between the reloc address and the
13198 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13199 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13200 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13201 fixp->fx_r_type = BFD_RELOC_GPREL32;
13203 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13205 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13206 reloc->addend = fixp->fx_addnumber;
13209 /* We use a special addend for an internal RELLO reloc. */
13210 if (symbol_section_p (fixp->fx_addsy))
13211 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13213 reloc->addend = fixp->fx_addnumber + reloc->address;
13216 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13218 assert (fixp->fx_next != NULL
13219 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13221 /* The reloc is relative to the RELLO; adjust the addend
13223 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13224 reloc->addend = fixp->fx_next->fx_addnumber;
13227 /* We use a special addend for an internal RELHI reloc. */
13228 if (symbol_section_p (fixp->fx_addsy))
13229 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13230 + fixp->fx_next->fx_where
13231 - S_GET_VALUE (fixp->fx_subsy));
13233 reloc->addend = (fixp->fx_addnumber
13234 + fixp->fx_next->fx_frag->fr_address
13235 + fixp->fx_next->fx_where);
13238 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13239 reloc->addend = fixp->fx_addnumber;
13242 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13243 /* A gruesome hack which is a result of the gruesome gas reloc
13245 reloc->addend = reloc->address;
13247 reloc->addend = -reloc->address;
13250 /* If this is a variant frag, we may need to adjust the existing
13251 reloc and generate a new one. */
13252 if (fixp->fx_frag->fr_opcode != NULL
13253 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13255 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13256 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13257 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13258 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13259 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13260 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13265 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13267 /* If this is not the last reloc in this frag, then we have two
13268 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13269 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13270 the second one handle all of them. */
13271 if (fixp->fx_next != NULL
13272 && fixp->fx_frag == fixp->fx_next->fx_frag)
13274 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13275 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13276 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13277 && (fixp->fx_next->fx_r_type
13278 == BFD_RELOC_MIPS_GOT_LO16))
13279 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13280 && (fixp->fx_next->fx_r_type
13281 == BFD_RELOC_MIPS_CALL_LO16)));
13286 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13287 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13288 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13290 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13291 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13292 reloc2->address = (reloc->address
13293 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13294 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13295 reloc2->addend = fixp->fx_addnumber;
13296 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13297 assert (reloc2->howto != NULL);
13299 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13303 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13306 reloc3->address += 4;
13309 if (mips_pic == NO_PIC)
13311 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13312 fixp->fx_r_type = BFD_RELOC_HI16_S;
13314 else if (mips_pic == SVR4_PIC)
13316 switch (fixp->fx_r_type)
13320 case BFD_RELOC_MIPS_GOT16:
13322 case BFD_RELOC_MIPS_GOT_LO16:
13323 case BFD_RELOC_MIPS_CALL_LO16:
13324 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13326 case BFD_RELOC_MIPS_CALL16:
13329 /* BFD_RELOC_MIPS_GOT16;*/
13330 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13331 reloc2->howto = bfd_reloc_type_lookup
13332 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13335 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13342 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13343 if (HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16)
13345 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13350 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13351 entry to be used in the relocation's section offset. */
13352 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13354 reloc->address = reloc->addend;
13358 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13359 fixup_segment converted a non-PC relative reloc into a PC
13360 relative reloc. In such a case, we need to convert the reloc
13362 code = fixp->fx_r_type;
13363 if (fixp->fx_pcrel)
13368 code = BFD_RELOC_8_PCREL;
13371 code = BFD_RELOC_16_PCREL;
13374 code = BFD_RELOC_32_PCREL;
13377 code = BFD_RELOC_64_PCREL;
13379 case BFD_RELOC_8_PCREL:
13380 case BFD_RELOC_16_PCREL:
13381 case BFD_RELOC_32_PCREL:
13382 case BFD_RELOC_64_PCREL:
13383 case BFD_RELOC_16_PCREL_S2:
13384 case BFD_RELOC_MIPSEMB_16_PCREL_S2:
13385 case BFD_RELOC_PCREL_HI16_S:
13386 case BFD_RELOC_PCREL_LO16:
13389 as_bad_where (fixp->fx_file, fixp->fx_line,
13390 _("Cannot make %s relocation PC relative"),
13391 bfd_get_reloc_code_name (code));
13396 /* md_apply_fix3 has a double-subtraction hack to get
13397 bfd_install_relocation to behave nicely. GPREL relocations are
13398 handled correctly without this hack, so undo it here. We can't
13399 stop md_apply_fix3 from subtracting twice in the first place since
13400 the fake addend is required for variant frags above. */
13401 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
13402 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
13403 && reloc->addend != 0
13404 && mips_need_elf_addend_fixup (fixp))
13405 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
13408 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13409 if (reloc->howto == NULL)
13411 as_bad_where (fixp->fx_file, fixp->fx_line,
13412 _("Can not represent %s relocation in this object file format"),
13413 bfd_get_reloc_code_name (code));
13420 /* Relax a machine dependent frag. This returns the amount by which
13421 the current size of the frag should change. */
13424 mips_relax_frag (sec, fragp, stretch)
13429 if (RELAX_BRANCH_P (fragp->fr_subtype))
13431 offsetT old_var = fragp->fr_var;
13433 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13435 return fragp->fr_var - old_var;
13438 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13441 if (mips16_extended_frag (fragp, NULL, stretch))
13443 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13445 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13450 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13452 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13459 /* Convert a machine dependent frag. */
13462 md_convert_frag (abfd, asec, fragp)
13463 bfd *abfd ATTRIBUTE_UNUSED;
13470 if (RELAX_BRANCH_P (fragp->fr_subtype))
13473 unsigned long insn;
13477 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13479 if (target_big_endian)
13480 insn = bfd_getb32 (buf);
13482 insn = bfd_getl32 (buf);
13484 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13486 /* We generate a fixup instead of applying it right now
13487 because, if there are linker relaxations, we're going to
13488 need the relocations. */
13489 exp.X_op = O_symbol;
13490 exp.X_add_symbol = fragp->fr_symbol;
13491 exp.X_add_number = fragp->fr_offset;
13493 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13494 4, &exp, 1, ((mips_pic == EMBEDDED_PIC)
13495 ? BFD_RELOC_MIPSEMB_16_PCREL_S2
13496 : BFD_RELOC_16_PCREL_S2));
13497 fixp->fx_file = fragp->fr_file;
13498 fixp->fx_line = fragp->fr_line;
13500 md_number_to_chars ((char *)buf, insn, 4);
13507 as_warn_where (fragp->fr_file, fragp->fr_line,
13508 _("relaxed out-of-range branch into a jump"));
13510 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13513 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13515 /* Reverse the branch. */
13516 switch ((insn >> 28) & 0xf)
13519 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13520 have the condition reversed by tweaking a single
13521 bit, and their opcodes all have 0x4???????. */
13522 assert ((insn & 0xf1000000) == 0x41000000);
13523 insn ^= 0x00010000;
13527 /* bltz 0x04000000 bgez 0x04010000
13528 bltzal 0x04100000 bgezal 0x04110000 */
13529 assert ((insn & 0xfc0e0000) == 0x04000000);
13530 insn ^= 0x00010000;
13534 /* beq 0x10000000 bne 0x14000000
13535 blez 0x18000000 bgtz 0x1c000000 */
13536 insn ^= 0x04000000;
13544 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13546 /* Clear the and-link bit. */
13547 assert ((insn & 0xfc1c0000) == 0x04100000);
13549 /* bltzal 0x04100000 bgezal 0x04110000
13550 bltzall 0x04120000 bgezall 0x04130000 */
13551 insn &= ~0x00100000;
13554 /* Branch over the branch (if the branch was likely) or the
13555 full jump (not likely case). Compute the offset from the
13556 current instruction to branch to. */
13557 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13561 /* How many bytes in instructions we've already emitted? */
13562 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13563 /* How many bytes in instructions from here to the end? */
13564 i = fragp->fr_var - i;
13566 /* Convert to instruction count. */
13568 /* Branch counts from the next instruction. */
13571 /* Branch over the jump. */
13572 md_number_to_chars ((char *)buf, insn, 4);
13576 md_number_to_chars ((char*)buf, 0, 4);
13579 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13581 /* beql $0, $0, 2f */
13583 /* Compute the PC offset from the current instruction to
13584 the end of the variable frag. */
13585 /* How many bytes in instructions we've already emitted? */
13586 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13587 /* How many bytes in instructions from here to the end? */
13588 i = fragp->fr_var - i;
13589 /* Convert to instruction count. */
13591 /* Don't decrement i, because we want to branch over the
13595 md_number_to_chars ((char *)buf, insn, 4);
13598 md_number_to_chars ((char *)buf, 0, 4);
13603 if (mips_pic == NO_PIC)
13606 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13607 ? 0x0c000000 : 0x08000000);
13608 exp.X_op = O_symbol;
13609 exp.X_add_symbol = fragp->fr_symbol;
13610 exp.X_add_number = fragp->fr_offset;
13612 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13613 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13614 fixp->fx_file = fragp->fr_file;
13615 fixp->fx_line = fragp->fr_line;
13617 md_number_to_chars ((char*)buf, insn, 4);
13622 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13623 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13624 exp.X_op = O_symbol;
13625 exp.X_add_symbol = fragp->fr_symbol;
13626 exp.X_add_number = fragp->fr_offset;
13628 if (fragp->fr_offset)
13630 exp.X_add_symbol = make_expr_symbol (&exp);
13631 exp.X_add_number = 0;
13634 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13635 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13636 fixp->fx_file = fragp->fr_file;
13637 fixp->fx_line = fragp->fr_line;
13639 md_number_to_chars ((char*)buf, insn, 4);
13642 if (mips_opts.isa == ISA_MIPS1)
13645 md_number_to_chars ((char*)buf, 0, 4);
13649 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13650 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13652 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13653 4, &exp, 0, BFD_RELOC_LO16);
13654 fixp->fx_file = fragp->fr_file;
13655 fixp->fx_line = fragp->fr_line;
13657 md_number_to_chars ((char*)buf, insn, 4);
13661 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13666 md_number_to_chars ((char*)buf, insn, 4);
13671 assert (buf == (bfd_byte *)fragp->fr_literal
13672 + fragp->fr_fix + fragp->fr_var);
13674 fragp->fr_fix += fragp->fr_var;
13679 if (RELAX_MIPS16_P (fragp->fr_subtype))
13682 register const struct mips16_immed_operand *op;
13683 bfd_boolean small, ext;
13686 unsigned long insn;
13687 bfd_boolean use_extend;
13688 unsigned short extend;
13690 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13691 op = mips16_immed_operands;
13692 while (op->type != type)
13695 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13706 resolve_symbol_value (fragp->fr_symbol);
13707 val = S_GET_VALUE (fragp->fr_symbol);
13712 addr = fragp->fr_address + fragp->fr_fix;
13714 /* The rules for the base address of a PC relative reloc are
13715 complicated; see mips16_extended_frag. */
13716 if (type == 'p' || type == 'q')
13721 /* Ignore the low bit in the target, since it will be
13722 set for a text label. */
13723 if ((val & 1) != 0)
13726 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13728 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13731 addr &= ~ (addressT) ((1 << op->shift) - 1);
13734 /* Make sure the section winds up with the alignment we have
13737 record_alignment (asec, op->shift);
13741 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13742 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13743 as_warn_where (fragp->fr_file, fragp->fr_line,
13744 _("extended instruction in delay slot"));
13746 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13748 if (target_big_endian)
13749 insn = bfd_getb16 (buf);
13751 insn = bfd_getl16 (buf);
13753 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13754 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13755 small, ext, &insn, &use_extend, &extend);
13759 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13760 fragp->fr_fix += 2;
13764 md_number_to_chars ((char *) buf, insn, 2);
13765 fragp->fr_fix += 2;
13770 if (fragp->fr_opcode == NULL)
13773 old = RELAX_OLD (fragp->fr_subtype);
13774 new = RELAX_NEW (fragp->fr_subtype);
13775 fixptr = fragp->fr_literal + fragp->fr_fix;
13778 memcpy (fixptr - old, fixptr, new);
13780 fragp->fr_fix += new - old;
13786 /* This function is called after the relocs have been generated.
13787 We've been storing mips16 text labels as odd. Here we convert them
13788 back to even for the convenience of the debugger. */
13791 mips_frob_file_after_relocs ()
13794 unsigned int count, i;
13796 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13799 syms = bfd_get_outsymbols (stdoutput);
13800 count = bfd_get_symcount (stdoutput);
13801 for (i = 0; i < count; i++, syms++)
13803 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13804 && ((*syms)->value & 1) != 0)
13806 (*syms)->value &= ~1;
13807 /* If the symbol has an odd size, it was probably computed
13808 incorrectly, so adjust that as well. */
13809 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13810 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13817 /* This function is called whenever a label is defined. It is used
13818 when handling branch delays; if a branch has a label, we assume we
13819 can not move it. */
13822 mips_define_label (sym)
13825 struct insn_label_list *l;
13827 if (free_insn_labels == NULL)
13828 l = (struct insn_label_list *) xmalloc (sizeof *l);
13831 l = free_insn_labels;
13832 free_insn_labels = l->next;
13836 l->next = insn_labels;
13840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13842 /* Some special processing for a MIPS ELF file. */
13845 mips_elf_final_processing ()
13847 /* Write out the register information. */
13848 if (mips_abi != N64_ABI)
13852 s.ri_gprmask = mips_gprmask;
13853 s.ri_cprmask[0] = mips_cprmask[0];
13854 s.ri_cprmask[1] = mips_cprmask[1];
13855 s.ri_cprmask[2] = mips_cprmask[2];
13856 s.ri_cprmask[3] = mips_cprmask[3];
13857 /* The gp_value field is set by the MIPS ELF backend. */
13859 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13860 ((Elf32_External_RegInfo *)
13861 mips_regmask_frag));
13865 Elf64_Internal_RegInfo s;
13867 s.ri_gprmask = mips_gprmask;
13869 s.ri_cprmask[0] = mips_cprmask[0];
13870 s.ri_cprmask[1] = mips_cprmask[1];
13871 s.ri_cprmask[2] = mips_cprmask[2];
13872 s.ri_cprmask[3] = mips_cprmask[3];
13873 /* The gp_value field is set by the MIPS ELF backend. */
13875 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13876 ((Elf64_External_RegInfo *)
13877 mips_regmask_frag));
13880 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13881 sort of BFD interface for this. */
13882 if (mips_any_noreorder)
13883 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13884 if (mips_pic != NO_PIC)
13885 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13887 /* Set MIPS ELF flags for ASEs. */
13888 if (file_ase_mips16)
13889 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13890 #if 0 /* XXX FIXME */
13891 if (file_ase_mips3d)
13892 elf_elfheader (stdoutput)->e_flags |= ???;
13895 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13897 /* Set the MIPS ELF ABI flags. */
13898 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13899 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13900 else if (mips_abi == O64_ABI)
13901 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13902 else if (mips_abi == EABI_ABI)
13904 if (!file_mips_gp32)
13905 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13907 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13909 else if (mips_abi == N32_ABI)
13910 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13912 /* Nothing to do for N64_ABI. */
13914 if (mips_32bitmode)
13915 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13918 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13920 typedef struct proc {
13922 unsigned long reg_mask;
13923 unsigned long reg_offset;
13924 unsigned long fpreg_mask;
13925 unsigned long fpreg_offset;
13926 unsigned long frame_offset;
13927 unsigned long frame_reg;
13928 unsigned long pc_reg;
13931 static procS cur_proc;
13932 static procS *cur_proc_ptr;
13933 static int numprocs;
13935 /* Fill in an rs_align_code fragment. */
13938 mips_handle_align (fragp)
13941 if (fragp->fr_type != rs_align_code)
13944 if (mips_opts.mips16)
13946 static const unsigned char be_nop[] = { 0x65, 0x00 };
13947 static const unsigned char le_nop[] = { 0x00, 0x65 };
13952 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13953 p = fragp->fr_literal + fragp->fr_fix;
13961 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13965 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13976 /* check for premature end, nesting errors, etc */
13978 as_warn (_("missing .end at end of assembly"));
13987 if (*input_line_pointer == '-')
13989 ++input_line_pointer;
13992 if (!ISDIGIT (*input_line_pointer))
13993 as_bad (_("expected simple number"));
13994 if (input_line_pointer[0] == '0')
13996 if (input_line_pointer[1] == 'x')
13998 input_line_pointer += 2;
13999 while (ISXDIGIT (*input_line_pointer))
14002 val |= hex_value (*input_line_pointer++);
14004 return negative ? -val : val;
14008 ++input_line_pointer;
14009 while (ISDIGIT (*input_line_pointer))
14012 val |= *input_line_pointer++ - '0';
14014 return negative ? -val : val;
14017 if (!ISDIGIT (*input_line_pointer))
14019 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14020 *input_line_pointer, *input_line_pointer);
14021 as_warn (_("invalid number"));
14024 while (ISDIGIT (*input_line_pointer))
14027 val += *input_line_pointer++ - '0';
14029 return negative ? -val : val;
14032 /* The .file directive; just like the usual .file directive, but there
14033 is an initial number which is the ECOFF file index. In the non-ECOFF
14034 case .file implies DWARF-2. */
14038 int x ATTRIBUTE_UNUSED;
14040 static int first_file_directive = 0;
14042 if (ECOFF_DEBUGGING)
14051 filename = dwarf2_directive_file (0);
14053 /* Versions of GCC up to 3.1 start files with a ".file"
14054 directive even for stabs output. Make sure that this
14055 ".file" is handled. Note that you need a version of GCC
14056 after 3.1 in order to support DWARF-2 on MIPS. */
14057 if (filename != NULL && ! first_file_directive)
14059 (void) new_logical_line (filename, -1);
14060 s_app_file_string (filename);
14062 first_file_directive = 1;
14066 /* The .loc directive, implying DWARF-2. */
14070 int x ATTRIBUTE_UNUSED;
14072 if (!ECOFF_DEBUGGING)
14073 dwarf2_directive_loc (0);
14076 /* The .end directive. */
14080 int x ATTRIBUTE_UNUSED;
14084 /* Following functions need their own .frame and .cprestore directives. */
14085 mips_frame_reg_valid = 0;
14086 mips_cprestore_valid = 0;
14088 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14091 demand_empty_rest_of_line ();
14096 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14097 as_warn (_(".end not in text section"));
14101 as_warn (_(".end directive without a preceding .ent directive."));
14102 demand_empty_rest_of_line ();
14108 assert (S_GET_NAME (p));
14109 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14110 as_warn (_(".end symbol does not match .ent symbol."));
14112 if (debug_type == DEBUG_STABS)
14113 stabs_generate_asm_endfunc (S_GET_NAME (p),
14117 as_warn (_(".end directive missing or unknown symbol"));
14120 /* Generate a .pdr section. */
14121 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14123 segT saved_seg = now_seg;
14124 subsegT saved_subseg = now_subseg;
14129 dot = frag_now_fix ();
14131 #ifdef md_flush_pending_output
14132 md_flush_pending_output ();
14136 subseg_set (pdr_seg, 0);
14138 /* Write the symbol. */
14139 exp.X_op = O_symbol;
14140 exp.X_add_symbol = p;
14141 exp.X_add_number = 0;
14142 emit_expr (&exp, 4);
14144 fragp = frag_more (7 * 4);
14146 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
14147 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
14148 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
14149 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
14150 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
14151 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
14152 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
14154 subseg_set (saved_seg, saved_subseg);
14156 #endif /* OBJ_ELF */
14158 cur_proc_ptr = NULL;
14161 /* The .aent and .ent directives. */
14169 symbolP = get_symbol ();
14170 if (*input_line_pointer == ',')
14171 ++input_line_pointer;
14172 SKIP_WHITESPACE ();
14173 if (ISDIGIT (*input_line_pointer)
14174 || *input_line_pointer == '-')
14177 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14178 as_warn (_(".ent or .aent not in text section."));
14180 if (!aent && cur_proc_ptr)
14181 as_warn (_("missing .end"));
14185 /* This function needs its own .frame and .cprestore directives. */
14186 mips_frame_reg_valid = 0;
14187 mips_cprestore_valid = 0;
14189 cur_proc_ptr = &cur_proc;
14190 memset (cur_proc_ptr, '\0', sizeof (procS));
14192 cur_proc_ptr->isym = symbolP;
14194 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14198 if (debug_type == DEBUG_STABS)
14199 stabs_generate_asm_func (S_GET_NAME (symbolP),
14200 S_GET_NAME (symbolP));
14203 demand_empty_rest_of_line ();
14206 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14207 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14208 s_mips_frame is used so that we can set the PDR information correctly.
14209 We can't use the ecoff routines because they make reference to the ecoff
14210 symbol table (in the mdebug section). */
14213 s_mips_frame (ignore)
14214 int ignore ATTRIBUTE_UNUSED;
14217 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14221 if (cur_proc_ptr == (procS *) NULL)
14223 as_warn (_(".frame outside of .ent"));
14224 demand_empty_rest_of_line ();
14228 cur_proc_ptr->frame_reg = tc_get_register (1);
14230 SKIP_WHITESPACE ();
14231 if (*input_line_pointer++ != ','
14232 || get_absolute_expression_and_terminator (&val) != ',')
14234 as_warn (_("Bad .frame directive"));
14235 --input_line_pointer;
14236 demand_empty_rest_of_line ();
14240 cur_proc_ptr->frame_offset = val;
14241 cur_proc_ptr->pc_reg = tc_get_register (0);
14243 demand_empty_rest_of_line ();
14246 #endif /* OBJ_ELF */
14250 /* The .fmask and .mask directives. If the mdebug section is present
14251 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14252 embedded targets, s_mips_mask is used so that we can set the PDR
14253 information correctly. We can't use the ecoff routines because they
14254 make reference to the ecoff symbol table (in the mdebug section). */
14257 s_mips_mask (reg_type)
14261 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14265 if (cur_proc_ptr == (procS *) NULL)
14267 as_warn (_(".mask/.fmask outside of .ent"));
14268 demand_empty_rest_of_line ();
14272 if (get_absolute_expression_and_terminator (&mask) != ',')
14274 as_warn (_("Bad .mask/.fmask directive"));
14275 --input_line_pointer;
14276 demand_empty_rest_of_line ();
14280 off = get_absolute_expression ();
14282 if (reg_type == 'F')
14284 cur_proc_ptr->fpreg_mask = mask;
14285 cur_proc_ptr->fpreg_offset = off;
14289 cur_proc_ptr->reg_mask = mask;
14290 cur_proc_ptr->reg_offset = off;
14293 demand_empty_rest_of_line ();
14296 #endif /* OBJ_ELF */
14297 s_ignore (reg_type);
14300 /* The .loc directive. */
14311 assert (now_seg == text_section);
14313 lineno = get_number ();
14314 addroff = frag_now_fix ();
14316 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14317 S_SET_TYPE (symbolP, N_SLINE);
14318 S_SET_OTHER (symbolP, 0);
14319 S_SET_DESC (symbolP, lineno);
14320 symbolP->sy_segment = now_seg;
14324 /* A table describing all the processors gas knows about. Names are
14325 matched in the order listed.
14327 To ease comparison, please keep this table in the same order as
14328 gcc's mips_cpu_info_table[]. */
14329 static const struct mips_cpu_info mips_cpu_info_table[] =
14331 /* Entries for generic ISAs */
14332 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14333 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14334 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14335 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14336 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14337 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14338 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14339 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14342 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14343 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14344 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14347 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14350 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14351 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14352 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14353 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14354 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14355 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14356 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14357 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14358 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14359 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14360 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14361 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14364 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14365 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14366 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14367 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14368 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14369 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14370 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14371 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14372 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14373 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14374 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14375 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
14378 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
14379 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14380 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14383 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14384 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14386 /* Broadcom SB-1 CPU core */
14387 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14394 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14395 with a final "000" replaced by "k". Ignore case.
14397 Note: this function is shared between GCC and GAS. */
14400 mips_strict_matching_cpu_name_p (canonical, given)
14401 const char *canonical, *given;
14403 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14404 given++, canonical++;
14406 return ((*given == 0 && *canonical == 0)
14407 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14411 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14412 CPU name. We've traditionally allowed a lot of variation here.
14414 Note: this function is shared between GCC and GAS. */
14417 mips_matching_cpu_name_p (canonical, given)
14418 const char *canonical, *given;
14420 /* First see if the name matches exactly, or with a final "000"
14421 turned into "k". */
14422 if (mips_strict_matching_cpu_name_p (canonical, given))
14425 /* If not, try comparing based on numerical designation alone.
14426 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14427 if (TOLOWER (*given) == 'r')
14429 if (!ISDIGIT (*given))
14432 /* Skip over some well-known prefixes in the canonical name,
14433 hoping to find a number there too. */
14434 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14436 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14438 else if (TOLOWER (canonical[0]) == 'r')
14441 return mips_strict_matching_cpu_name_p (canonical, given);
14445 /* Parse an option that takes the name of a processor as its argument.
14446 OPTION is the name of the option and CPU_STRING is the argument.
14447 Return the corresponding processor enumeration if the CPU_STRING is
14448 recognized, otherwise report an error and return null.
14450 A similar function exists in GCC. */
14452 static const struct mips_cpu_info *
14453 mips_parse_cpu (option, cpu_string)
14454 const char *option, *cpu_string;
14456 const struct mips_cpu_info *p;
14458 /* 'from-abi' selects the most compatible architecture for the given
14459 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14460 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14461 version. Look first at the -mgp options, if given, otherwise base
14462 the choice on MIPS_DEFAULT_64BIT.
14464 Treat NO_ABI like the EABIs. One reason to do this is that the
14465 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14466 architecture. This code picks MIPS I for 'mips' and MIPS III for
14467 'mips64', just as we did in the days before 'from-abi'. */
14468 if (strcasecmp (cpu_string, "from-abi") == 0)
14470 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14471 return mips_cpu_info_from_isa (ISA_MIPS1);
14473 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14474 return mips_cpu_info_from_isa (ISA_MIPS3);
14476 if (file_mips_gp32 >= 0)
14477 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14479 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14484 /* 'default' has traditionally been a no-op. Probably not very useful. */
14485 if (strcasecmp (cpu_string, "default") == 0)
14488 for (p = mips_cpu_info_table; p->name != 0; p++)
14489 if (mips_matching_cpu_name_p (p->name, cpu_string))
14492 as_bad ("Bad value (%s) for %s", cpu_string, option);
14496 /* Return the canonical processor information for ISA (a member of the
14497 ISA_MIPS* enumeration). */
14499 static const struct mips_cpu_info *
14500 mips_cpu_info_from_isa (isa)
14505 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14506 if (mips_cpu_info_table[i].is_isa
14507 && isa == mips_cpu_info_table[i].isa)
14508 return (&mips_cpu_info_table[i]);
14514 show (stream, string, col_p, first_p)
14516 const char *string;
14522 fprintf (stream, "%24s", "");
14527 fprintf (stream, ", ");
14531 if (*col_p + strlen (string) > 72)
14533 fprintf (stream, "\n%24s", "");
14537 fprintf (stream, "%s", string);
14538 *col_p += strlen (string);
14544 md_show_usage (stream)
14550 fprintf (stream, _("\
14552 -membedded-pic generate embedded position independent code\n\
14553 -EB generate big endian output\n\
14554 -EL generate little endian output\n\
14555 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14556 -G NUM allow referencing objects up to NUM bytes\n\
14557 implicitly with the gp register [default 8]\n"));
14558 fprintf (stream, _("\
14559 -mips1 generate MIPS ISA I instructions\n\
14560 -mips2 generate MIPS ISA II instructions\n\
14561 -mips3 generate MIPS ISA III instructions\n\
14562 -mips4 generate MIPS ISA IV instructions\n\
14563 -mips5 generate MIPS ISA V instructions\n\
14564 -mips32 generate MIPS32 ISA instructions\n\
14565 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14566 -mips64 generate MIPS64 ISA instructions\n\
14567 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14571 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14572 show (stream, mips_cpu_info_table[i].name, &column, &first);
14573 show (stream, "from-abi", &column, &first);
14574 fputc ('\n', stream);
14576 fprintf (stream, _("\
14577 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14578 -no-mCPU don't generate code specific to CPU.\n\
14579 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14583 show (stream, "3900", &column, &first);
14584 show (stream, "4010", &column, &first);
14585 show (stream, "4100", &column, &first);
14586 show (stream, "4650", &column, &first);
14587 fputc ('\n', stream);
14589 fprintf (stream, _("\
14590 -mips16 generate mips16 instructions\n\
14591 -no-mips16 do not generate mips16 instructions\n"));
14592 fprintf (stream, _("\
14593 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14594 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14595 -O0 remove unneeded NOPs, do not swap branches\n\
14596 -O remove unneeded NOPs and swap branches\n\
14597 -n warn about NOPs generated from macros\n\
14598 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14599 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14600 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14602 fprintf (stream, _("\
14603 -KPIC, -call_shared generate SVR4 position independent code\n\
14604 -non_shared do not generate position independent code\n\
14605 -xgot assume a 32 bit GOT\n\
14606 -mabi=ABI create ABI conformant object file for:\n"));
14610 show (stream, "32", &column, &first);
14611 show (stream, "o64", &column, &first);
14612 show (stream, "n32", &column, &first);
14613 show (stream, "64", &column, &first);
14614 show (stream, "eabi", &column, &first);
14616 fputc ('\n', stream);
14618 fprintf (stream, _("\
14619 -32 create o32 ABI object file (default)\n\
14620 -n32 create n32 ABI object file\n\
14621 -64 create 64 ABI object file\n"));
14626 mips_dwarf2_format ()
14628 if (mips_abi == N64_ABI)
14631 return dwarf2_format_64bit_irix;
14633 return dwarf2_format_64bit;
14637 return dwarf2_format_32bit;