1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format {
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error {
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error;
671 static int auto_align = 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset = -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset = -1;
683 static int mips_cpreturn_register = -1;
684 static int mips_gp_register = GP;
685 static int mips_gprel_offset = 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid = 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg = SP;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid = 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize = 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug = 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history[1 + MAX_NOPS];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array {
731 const struct mips_operand *operand[MAX_OPERANDS];
733 static struct mips_operand_array *mips_operands;
734 static struct mips_operand_array *mips16_operands;
735 static struct mips_operand_array *micromips_operands;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn;
739 static struct mips_cl_insn mips16_nop_insn;
740 static struct mips_cl_insn micromips_nop16_insn;
741 static struct mips_cl_insn micromips_nop32_insn;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS *prev_nop_frag;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup *next;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup *mips_hi_fixup_list;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS *prev_reloc_op_frag;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro = FALSE;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1226 static void append_insn
1227 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1228 bfd_boolean expansionp);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS *, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS *, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS *, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn *ip, char *str);
1237 static void mips16_macro (struct mips_cl_insn * ip);
1238 static void mips_ip (char *str, struct mips_cl_insn * ip);
1239 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS *, bfd_reloc_code_real_type *, char *);
1245 static void my_getExpression (expressionS *, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean pic_need_relax (symbolS *, asection *);
1282 static int relaxed_branch_length (fragS *, asection *, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name; /* CPU or ISA name. */
1292 int flags; /* MIPS_CPU_* flags. */
1293 int ase; /* Set of ASEs implemented by the CPU. */
1294 int isa; /* ISA level. */
1295 int cpu; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts = "O::g::G:";
1309 OPTION_MARCH = OPTION_MD_BASE,
1333 OPTION_NO_SMARTMIPS,
1339 OPTION_NO_MICROMIPS,
1342 OPTION_COMPAT_ARCH_BASE,
1351 OPTION_M7000_HILO_FIX,
1352 OPTION_MNO_7000_HILO_FIX,
1355 OPTION_FIX_LOONGSON2F_JUMP,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP,
1357 OPTION_FIX_LOONGSON2F_NOP,
1358 OPTION_NO_FIX_LOONGSON2F_NOP,
1360 OPTION_NO_FIX_VR4120,
1362 OPTION_NO_FIX_VR4130,
1363 OPTION_FIX_CN63XXP1,
1364 OPTION_NO_FIX_CN63XXP1,
1371 OPTION_CONSTRUCT_FLOATS,
1372 OPTION_NO_CONSTRUCT_FLOATS,
1375 OPTION_RELAX_BRANCH,
1376 OPTION_NO_RELAX_BRANCH,
1385 OPTION_SINGLE_FLOAT,
1386 OPTION_DOUBLE_FLOAT,
1399 OPTION_MVXWORKS_PIC,
1404 struct option md_longopts[] =
1406 /* Options which specify architecture. */
1407 {"march", required_argument, NULL, OPTION_MARCH},
1408 {"mtune", required_argument, NULL, OPTION_MTUNE},
1409 {"mips0", no_argument, NULL, OPTION_MIPS1},
1410 {"mips1", no_argument, NULL, OPTION_MIPS1},
1411 {"mips2", no_argument, NULL, OPTION_MIPS2},
1412 {"mips3", no_argument, NULL, OPTION_MIPS3},
1413 {"mips4", no_argument, NULL, OPTION_MIPS4},
1414 {"mips5", no_argument, NULL, OPTION_MIPS5},
1415 {"mips32", no_argument, NULL, OPTION_MIPS32},
1416 {"mips64", no_argument, NULL, OPTION_MIPS64},
1417 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1418 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument, NULL, OPTION_MIPS16},
1422 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1423 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1424 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1425 {"mdmx", no_argument, NULL, OPTION_MDMX},
1426 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1427 {"mdsp", no_argument, NULL, OPTION_DSP},
1428 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1429 {"mmt", no_argument, NULL, OPTION_MT},
1430 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1431 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1432 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1433 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1434 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1435 {"meva", no_argument, NULL, OPTION_EVA},
1436 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1437 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1438 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1439 {"mmcu", no_argument, NULL, OPTION_MCU},
1440 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1441 {"mvirt", no_argument, NULL, OPTION_VIRT},
1442 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument, NULL, OPTION_M4650},
1446 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1447 {"m4010", no_argument, NULL, OPTION_M4010},
1448 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1449 {"m4100", no_argument, NULL, OPTION_M4100},
1450 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1451 {"m3900", no_argument, NULL, OPTION_M3900},
1452 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1456 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1457 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1458 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1459 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1460 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1461 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1462 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1463 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1464 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1465 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1466 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1467 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1468 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1469 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1471 /* Miscellaneous options. */
1472 {"trap", no_argument, NULL, OPTION_TRAP},
1473 {"no-break", no_argument, NULL, OPTION_TRAP},
1474 {"break", no_argument, NULL, OPTION_BREAK},
1475 {"no-trap", no_argument, NULL, OPTION_BREAK},
1476 {"EB", no_argument, NULL, OPTION_EB},
1477 {"EL", no_argument, NULL, OPTION_EL},
1478 {"mfp32", no_argument, NULL, OPTION_FP32},
1479 {"mgp32", no_argument, NULL, OPTION_GP32},
1480 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1481 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1482 {"mfp64", no_argument, NULL, OPTION_FP64},
1483 {"mgp64", no_argument, NULL, OPTION_GP64},
1484 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1485 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1486 {"minsn32", no_argument, NULL, OPTION_INSN32},
1487 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1488 {"mshared", no_argument, NULL, OPTION_MSHARED},
1489 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1490 {"msym32", no_argument, NULL, OPTION_MSYM32},
1491 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1492 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1493 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1494 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1495 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument, NULL, OPTION_32},
1502 /* ELF-specific options. */
1503 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1504 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1505 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1506 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1507 {"xgot", no_argument, NULL, OPTION_XGOT},
1508 {"mabi", required_argument, NULL, OPTION_MABI},
1509 {"n32", no_argument, NULL, OPTION_N32},
1510 {"64", no_argument, NULL, OPTION_64},
1511 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1512 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1513 {"mpdr", no_argument, NULL, OPTION_PDR},
1514 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1515 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1516 {"mnan", required_argument, NULL, OPTION_NAN},
1518 {NULL, no_argument, NULL, 0}
1520 size_t md_longopts_size = sizeof (md_longopts);
1522 /* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1527 /* The name of the ASE, used in both the command-line and .set options. */
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64;
1539 /* The command-line options that turn the ASE on and off. */
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1547 int micromips32_rev;
1548 int micromips64_rev;
1551 /* A table of all supported ASEs. */
1552 static const struct mips_ase mips_ases[] = {
1553 { "dsp", ASE_DSP, ASE_DSP64,
1554 OPTION_DSP, OPTION_NO_DSP,
1557 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1558 OPTION_DSPR2, OPTION_NO_DSPR2,
1561 { "eva", ASE_EVA, 0,
1562 OPTION_EVA, OPTION_NO_EVA,
1565 { "mcu", ASE_MCU, 0,
1566 OPTION_MCU, OPTION_NO_MCU,
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX, 0,
1571 OPTION_MDMX, OPTION_NO_MDMX,
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D, 0,
1576 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1580 OPTION_MT, OPTION_NO_MT,
1583 { "smartmips", ASE_SMARTMIPS, 0,
1584 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1587 { "virt", ASE_VIRT, ASE_VIRT64,
1588 OPTION_VIRT, OPTION_NO_VIRT,
1592 /* The set of ASEs that require -mfp64. */
1593 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1595 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1596 static const unsigned int mips_ase_groups[] = {
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
1617 static const pseudo_typeS mips_pseudo_table[] =
1619 /* MIPS specific pseudo-ops. */
1620 {"option", s_option, 0},
1621 {"set", s_mipsset, 0},
1622 {"rdata", s_change_sec, 'r'},
1623 {"sdata", s_change_sec, 's'},
1624 {"livereg", s_ignore, 0},
1625 {"abicalls", s_abicalls, 0},
1626 {"cpload", s_cpload, 0},
1627 {"cpsetup", s_cpsetup, 0},
1628 {"cplocal", s_cplocal, 0},
1629 {"cprestore", s_cprestore, 0},
1630 {"cpreturn", s_cpreturn, 0},
1631 {"dtprelword", s_dtprelword, 0},
1632 {"dtpreldword", s_dtpreldword, 0},
1633 {"tprelword", s_tprelword, 0},
1634 {"tpreldword", s_tpreldword, 0},
1635 {"gpvalue", s_gpvalue, 0},
1636 {"gpword", s_gpword, 0},
1637 {"gpdword", s_gpdword, 0},
1638 {"ehword", s_ehword, 0},
1639 {"cpadd", s_cpadd, 0},
1640 {"insn", s_insn, 0},
1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
1645 {"asciiz", stringer, 8 + 1},
1646 {"bss", s_change_sec, 'b'},
1648 {"half", s_cons, 1},
1649 {"dword", s_cons, 3},
1650 {"weakext", s_mips_weakext, 0},
1651 {"origin", s_org, 0},
1652 {"repeat", s_rept, 0},
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec, 'B'},
1657 /* These pseudo-ops are defined in read.c, but must be overridden
1658 here for one reason or another. */
1659 {"align", s_align, 0},
1660 {"byte", s_cons, 0},
1661 {"data", s_change_sec, 'd'},
1662 {"double", s_float_cons, 'd'},
1663 {"float", s_float_cons, 'f'},
1664 {"globl", s_mips_globl, 0},
1665 {"global", s_mips_globl, 0},
1666 {"hword", s_cons, 1},
1668 {"long", s_cons, 2},
1669 {"octa", s_cons, 4},
1670 {"quad", s_cons, 3},
1671 {"section", s_change_section, 0},
1672 {"short", s_cons, 1},
1673 {"single", s_float_cons, 'f'},
1674 {"stabd", s_mips_stab, 'd'},
1675 {"stabn", s_mips_stab, 'n'},
1676 {"stabs", s_mips_stab, 's'},
1677 {"text", s_change_sec, 't'},
1678 {"word", s_cons, 2},
1680 { "extern", ecoff_directive_extern, 0},
1685 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
1689 {"aent", s_mips_ent, 1},
1690 {"bgnb", s_ignore, 0},
1691 {"end", s_mips_end, 0},
1692 {"endb", s_ignore, 0},
1693 {"ent", s_mips_ent, 0},
1694 {"file", s_mips_file, 0},
1695 {"fmask", s_mips_mask, 'F'},
1696 {"frame", s_mips_frame, 0},
1697 {"loc", s_mips_loc, 0},
1698 {"mask", s_mips_mask, 'R'},
1699 {"verstamp", s_ignore, 0},
1703 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1707 mips_address_bytes (void)
1709 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1712 extern void pop_insert (const pseudo_typeS *);
1715 mips_pop_insert (void)
1717 pop_insert (mips_pseudo_table);
1718 if (! ECOFF_DEBUGGING)
1719 pop_insert (mips_nonecoff_pseudo_table);
1722 /* Symbols labelling the current insn. */
1724 struct insn_label_list
1726 struct insn_label_list *next;
1730 static struct insn_label_list *free_insn_labels;
1731 #define label_list tc_segment_info_data.labels
1733 static void mips_clear_insn_labels (void);
1734 static void mips_mark_labels (void);
1735 static void mips_compressed_mark_labels (void);
1738 mips_clear_insn_labels (void)
1740 register struct insn_label_list **pl;
1741 segment_info_type *si;
1745 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1748 si = seg_info (now_seg);
1749 *pl = si->label_list;
1750 si->label_list = NULL;
1754 /* Mark instruction labels in MIPS16/microMIPS mode. */
1757 mips_mark_labels (void)
1759 if (HAVE_CODE_COMPRESSION)
1760 mips_compressed_mark_labels ();
1763 static char *expr_end;
1765 /* Expressions which appear in macro instructions. These are set by
1766 mips_ip and read by macro. */
1768 static expressionS imm_expr;
1769 static expressionS imm2_expr;
1771 /* The relocatable field in an instruction and the relocs associated
1772 with it. These variables are used for instructions like LUI and
1773 JAL as well as true offsets. They are also used for address
1774 operands in macros. */
1776 static expressionS offset_expr;
1777 static bfd_reloc_code_real_type offset_reloc[3]
1778 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1780 /* This is set to the resulting size of the instruction to be produced
1781 by mips16_ip if an explicit extension is used or by mips_ip if an
1782 explicit size is supplied. */
1784 static unsigned int forced_insn_length;
1786 /* True if we are assembling an instruction. All dot symbols defined during
1787 this time should be treated as code labels. */
1789 static bfd_boolean mips_assembling_insn;
1791 /* The pdr segment for per procedure frame/regmask info. Not used for
1794 static segT pdr_seg;
1796 /* The default target format to use. */
1798 #if defined (TE_FreeBSD)
1799 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1800 #elif defined (TE_TMIPS)
1801 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1803 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1807 mips_target_format (void)
1809 switch (OUTPUT_FLAVOR)
1811 case bfd_target_elf_flavour:
1813 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1814 return (target_big_endian
1815 ? "elf32-bigmips-vxworks"
1816 : "elf32-littlemips-vxworks");
1818 return (target_big_endian
1819 ? (HAVE_64BIT_OBJECTS
1820 ? ELF_TARGET ("elf64-", "big")
1822 ? ELF_TARGET ("elf32-n", "big")
1823 : ELF_TARGET ("elf32-", "big")))
1824 : (HAVE_64BIT_OBJECTS
1825 ? ELF_TARGET ("elf64-", "little")
1827 ? ELF_TARGET ("elf32-n", "little")
1828 : ELF_TARGET ("elf32-", "little"))));
1835 /* Return the ISA revision that is currently in use, or 0 if we are
1836 generating code for MIPS V or below. */
1841 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1844 /* microMIPS implies revision 2 or above. */
1845 if (mips_opts.micromips)
1848 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1854 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1857 mips_ase_mask (unsigned int flags)
1861 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1862 if (flags & mips_ase_groups[i])
1863 flags |= mips_ase_groups[i];
1867 /* Check whether the current ISA supports ASE. Issue a warning if
1871 mips_check_isa_supports_ase (const struct mips_ase *ase)
1875 static unsigned int warned_isa;
1876 static unsigned int warned_fp32;
1878 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1879 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1881 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1882 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1883 && (warned_isa & ase->flags) != ase->flags)
1885 warned_isa |= ase->flags;
1886 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1887 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1889 as_warn (_("The %d-bit %s architecture does not support the"
1890 " `%s' extension"), size, base, ase->name);
1892 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1893 ase->name, base, size, min_rev);
1895 if ((ase->flags & FP64_ASES)
1897 && (warned_fp32 & ase->flags) != ase->flags)
1899 warned_fp32 |= ase->flags;
1900 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1904 /* Check all enabled ASEs to see whether they are supported by the
1905 chosen architecture. */
1908 mips_check_isa_supports_ases (void)
1910 unsigned int i, mask;
1912 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1914 mask = mips_ase_mask (mips_ases[i].flags);
1915 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1916 mips_check_isa_supports_ase (&mips_ases[i]);
1920 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1921 that were affected. */
1924 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1928 mask = mips_ase_mask (ase->flags);
1929 mips_opts.ase &= ~mask;
1931 mips_opts.ase |= ase->flags;
1935 /* Return the ASE called NAME, or null if none. */
1937 static const struct mips_ase *
1938 mips_lookup_ase (const char *name)
1942 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1943 if (strcmp (name, mips_ases[i].name) == 0)
1944 return &mips_ases[i];
1948 /* Return the length of a microMIPS instruction in bytes. If bits of
1949 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1950 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1951 major opcode) will require further modifications to the opcode
1954 static inline unsigned int
1955 micromips_insn_length (const struct mips_opcode *mo)
1957 return (mo->mask >> 16) == 0 ? 2 : 4;
1960 /* Return the length of MIPS16 instruction OPCODE. */
1962 static inline unsigned int
1963 mips16_opcode_length (unsigned long opcode)
1965 return (opcode >> 16) == 0 ? 2 : 4;
1968 /* Return the length of instruction INSN. */
1970 static inline unsigned int
1971 insn_length (const struct mips_cl_insn *insn)
1973 if (mips_opts.micromips)
1974 return micromips_insn_length (insn->insn_mo);
1975 else if (mips_opts.mips16)
1976 return mips16_opcode_length (insn->insn_opcode);
1981 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1984 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1989 insn->insn_opcode = mo->match;
1992 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1993 insn->fixp[i] = NULL;
1994 insn->fixed_p = (mips_opts.noreorder > 0);
1995 insn->noreorder_p = (mips_opts.noreorder > 0);
1996 insn->mips16_absolute_jump_p = 0;
1997 insn->complete_p = 0;
1998 insn->cleared_p = 0;
2001 /* Get a list of all the operands in INSN. */
2003 static const struct mips_operand_array *
2004 insn_operands (const struct mips_cl_insn *insn)
2006 if (insn->insn_mo >= &mips_opcodes[0]
2007 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2008 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2010 if (insn->insn_mo >= &mips16_opcodes[0]
2011 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2012 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2014 if (insn->insn_mo >= µmips_opcodes[0]
2015 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2016 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2021 /* Get a description of operand OPNO of INSN. */
2023 static const struct mips_operand *
2024 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2026 const struct mips_operand_array *operands;
2028 operands = insn_operands (insn);
2029 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2031 return operands->operand[opno];
2034 /* Install UVAL as the value of OPERAND in INSN. */
2037 insn_insert_operand (struct mips_cl_insn *insn,
2038 const struct mips_operand *operand, unsigned int uval)
2040 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2043 /* Extract the value of OPERAND from INSN. */
2045 static inline unsigned
2046 insn_extract_operand (const struct mips_cl_insn *insn,
2047 const struct mips_operand *operand)
2049 return mips_extract_operand (operand, insn->insn_opcode);
2052 /* Record the current MIPS16/microMIPS mode in now_seg. */
2055 mips_record_compressed_mode (void)
2057 segment_info_type *si;
2059 si = seg_info (now_seg);
2060 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2061 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2062 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2063 si->tc_segment_info_data.micromips = mips_opts.micromips;
2066 /* Read a standard MIPS instruction from BUF. */
2068 static unsigned long
2069 read_insn (char *buf)
2071 if (target_big_endian)
2072 return bfd_getb32 ((bfd_byte *) buf);
2074 return bfd_getl32 ((bfd_byte *) buf);
2077 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2081 write_insn (char *buf, unsigned int insn)
2083 md_number_to_chars (buf, insn, 4);
2087 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2090 static unsigned long
2091 read_compressed_insn (char *buf, unsigned int length)
2097 for (i = 0; i < length; i += 2)
2100 if (target_big_endian)
2101 insn |= bfd_getb16 ((char *) buf);
2103 insn |= bfd_getl16 ((char *) buf);
2109 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2113 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2117 for (i = 0; i < length; i += 2)
2118 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2119 return buf + length;
2122 /* Install INSN at the location specified by its "frag" and "where" fields. */
2125 install_insn (const struct mips_cl_insn *insn)
2127 char *f = insn->frag->fr_literal + insn->where;
2128 if (HAVE_CODE_COMPRESSION)
2129 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2131 write_insn (f, insn->insn_opcode);
2132 mips_record_compressed_mode ();
2135 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2139 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2144 insn->where = where;
2145 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2146 if (insn->fixp[i] != NULL)
2148 insn->fixp[i]->fx_frag = frag;
2149 insn->fixp[i]->fx_where = where;
2151 install_insn (insn);
2154 /* Add INSN to the end of the output. */
2157 add_fixed_insn (struct mips_cl_insn *insn)
2159 char *f = frag_more (insn_length (insn));
2160 move_insn (insn, frag_now, f - frag_now->fr_literal);
2163 /* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2167 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2168 relax_substateT subtype, symbolS *symbol, offsetT offset)
2170 frag_grow (max_chars);
2171 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2173 frag_var (rs_machine_dependent, max_chars, var,
2174 subtype, symbol, offset, NULL);
2177 /* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2181 insert_into_history (unsigned int first, unsigned int n,
2182 const struct mips_cl_insn *insn)
2184 if (mips_relax.sequence != 2)
2188 for (i = ARRAY_SIZE (history); i-- > first;)
2190 history[i] = history[i - n];
2196 /* Clear the error in insn_error. */
2199 clear_insn_error (void)
2201 memset (&insn_error, 0, sizeof (insn_error));
2204 /* Possibly record error message MSG for the current instruction.
2205 If the error is about a particular argument, ARGNUM is the 1-based
2206 number of that argument, otherwise it is 0. FORMAT is the format
2207 of MSG. Return true if MSG was used, false if the current message
2211 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2216 /* Give priority to errors against specific arguments, and to
2217 the first whole-instruction message. */
2223 /* Keep insn_error if it is against a later argument. */
2224 if (argnum < insn_error.min_argnum)
2227 /* If both errors are against the same argument but are different,
2228 give up on reporting a specific error for this argument.
2229 See the comment about mips_insn_error for details. */
2230 if (argnum == insn_error.min_argnum
2232 && strcmp (insn_error.msg, msg) != 0)
2235 insn_error.min_argnum += 1;
2239 insn_error.min_argnum = argnum;
2240 insn_error.format = format;
2241 insn_error.msg = msg;
2245 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2246 as for set_insn_error_format. */
2249 set_insn_error (int argnum, const char *msg)
2251 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2254 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2255 as for set_insn_error_format. */
2258 set_insn_error_i (int argnum, const char *msg, int i)
2260 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2264 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2265 are as for set_insn_error_format. */
2268 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2270 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2272 insn_error.u.ss[0] = s1;
2273 insn_error.u.ss[1] = s2;
2277 /* Report the error in insn_error, which is against assembly code STR. */
2280 report_insn_error (const char *str)
2284 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2285 switch (insn_error.format)
2292 as_bad (msg, insn_error.u.i, str);
2296 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2301 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2302 the idea is to make it obvious at a glance that each errata is
2306 init_vr4120_conflicts (void)
2308 #define CONFLICT(FIRST, SECOND) \
2309 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2311 /* Errata 21 - [D]DIV[U] after [D]MACC */
2312 CONFLICT (MACC, DIV);
2313 CONFLICT (DMACC, DIV);
2315 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2316 CONFLICT (DMULT, DMULT);
2317 CONFLICT (DMULT, DMACC);
2318 CONFLICT (DMACC, DMULT);
2319 CONFLICT (DMACC, DMACC);
2321 /* Errata 24 - MT{LO,HI} after [D]MACC */
2322 CONFLICT (MACC, MTHILO);
2323 CONFLICT (DMACC, MTHILO);
2325 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2326 instruction is executed immediately after a MACC or DMACC
2327 instruction, the result of [either instruction] is incorrect." */
2328 CONFLICT (MACC, MULT);
2329 CONFLICT (MACC, DMULT);
2330 CONFLICT (DMACC, MULT);
2331 CONFLICT (DMACC, DMULT);
2333 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2334 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2335 DDIV or DDIVU instruction, the result of the MACC or
2336 DMACC instruction is incorrect.". */
2337 CONFLICT (DMULT, MACC);
2338 CONFLICT (DMULT, DMACC);
2339 CONFLICT (DIV, MACC);
2340 CONFLICT (DIV, DMACC);
2350 #define RNUM_MASK 0x00000ff
2351 #define RTYPE_MASK 0x0efff00
2352 #define RTYPE_NUM 0x0000100
2353 #define RTYPE_FPU 0x0000200
2354 #define RTYPE_FCC 0x0000400
2355 #define RTYPE_VEC 0x0000800
2356 #define RTYPE_GP 0x0001000
2357 #define RTYPE_CP0 0x0002000
2358 #define RTYPE_PC 0x0004000
2359 #define RTYPE_ACC 0x0008000
2360 #define RTYPE_CCC 0x0010000
2361 #define RTYPE_VI 0x0020000
2362 #define RTYPE_VF 0x0040000
2363 #define RTYPE_R5900_I 0x0080000
2364 #define RTYPE_R5900_Q 0x0100000
2365 #define RTYPE_R5900_R 0x0200000
2366 #define RTYPE_R5900_ACC 0x0400000
2367 #define RWARN 0x8000000
2369 #define GENERIC_REGISTER_NUMBERS \
2370 {"$0", RTYPE_NUM | 0}, \
2371 {"$1", RTYPE_NUM | 1}, \
2372 {"$2", RTYPE_NUM | 2}, \
2373 {"$3", RTYPE_NUM | 3}, \
2374 {"$4", RTYPE_NUM | 4}, \
2375 {"$5", RTYPE_NUM | 5}, \
2376 {"$6", RTYPE_NUM | 6}, \
2377 {"$7", RTYPE_NUM | 7}, \
2378 {"$8", RTYPE_NUM | 8}, \
2379 {"$9", RTYPE_NUM | 9}, \
2380 {"$10", RTYPE_NUM | 10}, \
2381 {"$11", RTYPE_NUM | 11}, \
2382 {"$12", RTYPE_NUM | 12}, \
2383 {"$13", RTYPE_NUM | 13}, \
2384 {"$14", RTYPE_NUM | 14}, \
2385 {"$15", RTYPE_NUM | 15}, \
2386 {"$16", RTYPE_NUM | 16}, \
2387 {"$17", RTYPE_NUM | 17}, \
2388 {"$18", RTYPE_NUM | 18}, \
2389 {"$19", RTYPE_NUM | 19}, \
2390 {"$20", RTYPE_NUM | 20}, \
2391 {"$21", RTYPE_NUM | 21}, \
2392 {"$22", RTYPE_NUM | 22}, \
2393 {"$23", RTYPE_NUM | 23}, \
2394 {"$24", RTYPE_NUM | 24}, \
2395 {"$25", RTYPE_NUM | 25}, \
2396 {"$26", RTYPE_NUM | 26}, \
2397 {"$27", RTYPE_NUM | 27}, \
2398 {"$28", RTYPE_NUM | 28}, \
2399 {"$29", RTYPE_NUM | 29}, \
2400 {"$30", RTYPE_NUM | 30}, \
2401 {"$31", RTYPE_NUM | 31}
2403 #define FPU_REGISTER_NAMES \
2404 {"$f0", RTYPE_FPU | 0}, \
2405 {"$f1", RTYPE_FPU | 1}, \
2406 {"$f2", RTYPE_FPU | 2}, \
2407 {"$f3", RTYPE_FPU | 3}, \
2408 {"$f4", RTYPE_FPU | 4}, \
2409 {"$f5", RTYPE_FPU | 5}, \
2410 {"$f6", RTYPE_FPU | 6}, \
2411 {"$f7", RTYPE_FPU | 7}, \
2412 {"$f8", RTYPE_FPU | 8}, \
2413 {"$f9", RTYPE_FPU | 9}, \
2414 {"$f10", RTYPE_FPU | 10}, \
2415 {"$f11", RTYPE_FPU | 11}, \
2416 {"$f12", RTYPE_FPU | 12}, \
2417 {"$f13", RTYPE_FPU | 13}, \
2418 {"$f14", RTYPE_FPU | 14}, \
2419 {"$f15", RTYPE_FPU | 15}, \
2420 {"$f16", RTYPE_FPU | 16}, \
2421 {"$f17", RTYPE_FPU | 17}, \
2422 {"$f18", RTYPE_FPU | 18}, \
2423 {"$f19", RTYPE_FPU | 19}, \
2424 {"$f20", RTYPE_FPU | 20}, \
2425 {"$f21", RTYPE_FPU | 21}, \
2426 {"$f22", RTYPE_FPU | 22}, \
2427 {"$f23", RTYPE_FPU | 23}, \
2428 {"$f24", RTYPE_FPU | 24}, \
2429 {"$f25", RTYPE_FPU | 25}, \
2430 {"$f26", RTYPE_FPU | 26}, \
2431 {"$f27", RTYPE_FPU | 27}, \
2432 {"$f28", RTYPE_FPU | 28}, \
2433 {"$f29", RTYPE_FPU | 29}, \
2434 {"$f30", RTYPE_FPU | 30}, \
2435 {"$f31", RTYPE_FPU | 31}
2437 #define FPU_CONDITION_CODE_NAMES \
2438 {"$fcc0", RTYPE_FCC | 0}, \
2439 {"$fcc1", RTYPE_FCC | 1}, \
2440 {"$fcc2", RTYPE_FCC | 2}, \
2441 {"$fcc3", RTYPE_FCC | 3}, \
2442 {"$fcc4", RTYPE_FCC | 4}, \
2443 {"$fcc5", RTYPE_FCC | 5}, \
2444 {"$fcc6", RTYPE_FCC | 6}, \
2445 {"$fcc7", RTYPE_FCC | 7}
2447 #define COPROC_CONDITION_CODE_NAMES \
2448 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2449 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2450 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2451 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2452 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2453 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2454 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2455 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2457 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2458 {"$a4", RTYPE_GP | 8}, \
2459 {"$a5", RTYPE_GP | 9}, \
2460 {"$a6", RTYPE_GP | 10}, \
2461 {"$a7", RTYPE_GP | 11}, \
2462 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2463 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2464 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2465 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2466 {"$t0", RTYPE_GP | 12}, \
2467 {"$t1", RTYPE_GP | 13}, \
2468 {"$t2", RTYPE_GP | 14}, \
2469 {"$t3", RTYPE_GP | 15}
2471 #define O32_SYMBOLIC_REGISTER_NAMES \
2472 {"$t0", RTYPE_GP | 8}, \
2473 {"$t1", RTYPE_GP | 9}, \
2474 {"$t2", RTYPE_GP | 10}, \
2475 {"$t3", RTYPE_GP | 11}, \
2476 {"$t4", RTYPE_GP | 12}, \
2477 {"$t5", RTYPE_GP | 13}, \
2478 {"$t6", RTYPE_GP | 14}, \
2479 {"$t7", RTYPE_GP | 15}, \
2480 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2481 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2482 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2483 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2485 /* Remaining symbolic register names */
2486 #define SYMBOLIC_REGISTER_NAMES \
2487 {"$zero", RTYPE_GP | 0}, \
2488 {"$at", RTYPE_GP | 1}, \
2489 {"$AT", RTYPE_GP | 1}, \
2490 {"$v0", RTYPE_GP | 2}, \
2491 {"$v1", RTYPE_GP | 3}, \
2492 {"$a0", RTYPE_GP | 4}, \
2493 {"$a1", RTYPE_GP | 5}, \
2494 {"$a2", RTYPE_GP | 6}, \
2495 {"$a3", RTYPE_GP | 7}, \
2496 {"$s0", RTYPE_GP | 16}, \
2497 {"$s1", RTYPE_GP | 17}, \
2498 {"$s2", RTYPE_GP | 18}, \
2499 {"$s3", RTYPE_GP | 19}, \
2500 {"$s4", RTYPE_GP | 20}, \
2501 {"$s5", RTYPE_GP | 21}, \
2502 {"$s6", RTYPE_GP | 22}, \
2503 {"$s7", RTYPE_GP | 23}, \
2504 {"$t8", RTYPE_GP | 24}, \
2505 {"$t9", RTYPE_GP | 25}, \
2506 {"$k0", RTYPE_GP | 26}, \
2507 {"$kt0", RTYPE_GP | 26}, \
2508 {"$k1", RTYPE_GP | 27}, \
2509 {"$kt1", RTYPE_GP | 27}, \
2510 {"$gp", RTYPE_GP | 28}, \
2511 {"$sp", RTYPE_GP | 29}, \
2512 {"$s8", RTYPE_GP | 30}, \
2513 {"$fp", RTYPE_GP | 30}, \
2514 {"$ra", RTYPE_GP | 31}
2516 #define MIPS16_SPECIAL_REGISTER_NAMES \
2517 {"$pc", RTYPE_PC | 0}
2519 #define MDMX_VECTOR_REGISTER_NAMES \
2520 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2521 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2522 {"$v2", RTYPE_VEC | 2}, \
2523 {"$v3", RTYPE_VEC | 3}, \
2524 {"$v4", RTYPE_VEC | 4}, \
2525 {"$v5", RTYPE_VEC | 5}, \
2526 {"$v6", RTYPE_VEC | 6}, \
2527 {"$v7", RTYPE_VEC | 7}, \
2528 {"$v8", RTYPE_VEC | 8}, \
2529 {"$v9", RTYPE_VEC | 9}, \
2530 {"$v10", RTYPE_VEC | 10}, \
2531 {"$v11", RTYPE_VEC | 11}, \
2532 {"$v12", RTYPE_VEC | 12}, \
2533 {"$v13", RTYPE_VEC | 13}, \
2534 {"$v14", RTYPE_VEC | 14}, \
2535 {"$v15", RTYPE_VEC | 15}, \
2536 {"$v16", RTYPE_VEC | 16}, \
2537 {"$v17", RTYPE_VEC | 17}, \
2538 {"$v18", RTYPE_VEC | 18}, \
2539 {"$v19", RTYPE_VEC | 19}, \
2540 {"$v20", RTYPE_VEC | 20}, \
2541 {"$v21", RTYPE_VEC | 21}, \
2542 {"$v22", RTYPE_VEC | 22}, \
2543 {"$v23", RTYPE_VEC | 23}, \
2544 {"$v24", RTYPE_VEC | 24}, \
2545 {"$v25", RTYPE_VEC | 25}, \
2546 {"$v26", RTYPE_VEC | 26}, \
2547 {"$v27", RTYPE_VEC | 27}, \
2548 {"$v28", RTYPE_VEC | 28}, \
2549 {"$v29", RTYPE_VEC | 29}, \
2550 {"$v30", RTYPE_VEC | 30}, \
2551 {"$v31", RTYPE_VEC | 31}
2553 #define R5900_I_NAMES \
2554 {"$I", RTYPE_R5900_I | 0}
2556 #define R5900_Q_NAMES \
2557 {"$Q", RTYPE_R5900_Q | 0}
2559 #define R5900_R_NAMES \
2560 {"$R", RTYPE_R5900_R | 0}
2562 #define R5900_ACC_NAMES \
2563 {"$ACC", RTYPE_R5900_ACC | 0 }
2565 #define MIPS_DSP_ACCUMULATOR_NAMES \
2566 {"$ac0", RTYPE_ACC | 0}, \
2567 {"$ac1", RTYPE_ACC | 1}, \
2568 {"$ac2", RTYPE_ACC | 2}, \
2569 {"$ac3", RTYPE_ACC | 3}
2571 static const struct regname reg_names[] = {
2572 GENERIC_REGISTER_NUMBERS,
2574 FPU_CONDITION_CODE_NAMES,
2575 COPROC_CONDITION_CODE_NAMES,
2577 /* The $txx registers depends on the abi,
2578 these will be added later into the symbol table from
2579 one of the tables below once mips_abi is set after
2580 parsing of arguments from the command line. */
2581 SYMBOLIC_REGISTER_NAMES,
2583 MIPS16_SPECIAL_REGISTER_NAMES,
2584 MDMX_VECTOR_REGISTER_NAMES,
2589 MIPS_DSP_ACCUMULATOR_NAMES,
2593 static const struct regname reg_names_o32[] = {
2594 O32_SYMBOLIC_REGISTER_NAMES,
2598 static const struct regname reg_names_n32n64[] = {
2599 N32N64_SYMBOLIC_REGISTER_NAMES,
2603 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2604 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2605 of these register symbols, return the associated vector register,
2606 otherwise return SYMVAL itself. */
2609 mips_prefer_vec_regno (unsigned int symval)
2611 if ((symval & -2) == (RTYPE_GP | 2))
2612 return RTYPE_VEC | (symval & 1);
2616 /* Return true if string [S, E) is a valid register name, storing its
2617 symbol value in *SYMVAL_PTR if so. */
2620 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2625 /* Terminate name. */
2629 /* Look up the name. */
2630 symbol = symbol_find (s);
2633 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2636 *symval_ptr = S_GET_VALUE (symbol);
2640 /* Return true if the string at *SPTR is a valid register name. Allow it
2641 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2644 When returning true, move *SPTR past the register, store the
2645 register's symbol value in *SYMVAL_PTR and the channel mask in
2646 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2647 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2648 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2651 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2652 unsigned int *channels_ptr)
2656 unsigned int channels, symval, bit;
2658 /* Find end of name. */
2660 if (is_name_beginner (*e))
2662 while (is_part_of_name (*e))
2666 if (!mips_parse_register_1 (s, e, &symval))
2671 /* Eat characters from the end of the string that are valid
2672 channel suffixes. The preceding register must be $ACC or
2673 end with a digit, so there is no ambiguity. */
2676 for (q = "wzyx"; *q; q++, bit <<= 1)
2677 if (m > s && m[-1] == *q)
2684 || !mips_parse_register_1 (s, m, &symval)
2685 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2690 *symval_ptr = symval;
2692 *channels_ptr = channels;
2696 /* Check if SPTR points at a valid register specifier according to TYPES.
2697 If so, then return 1, advance S to consume the specifier and store
2698 the register's number in REGNOP, otherwise return 0. */
2701 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2705 if (mips_parse_register (s, ®no, NULL))
2707 if (types & RTYPE_VEC)
2708 regno = mips_prefer_vec_regno (regno);
2717 as_warn (_("Unrecognized register name `%s'"), *s);
2722 return regno <= RNUM_MASK;
2725 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2726 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2729 mips_parse_vu0_channels (char *s, unsigned int *channels)
2734 for (i = 0; i < 4; i++)
2735 if (*s == "xyzw"[i])
2737 *channels |= 1 << (3 - i);
2743 /* Token types for parsed operand lists. */
2744 enum mips_operand_token_type {
2745 /* A plain register, e.g. $f2. */
2748 /* A 4-bit XYZW channel mask. */
2751 /* An element of a vector, e.g. $v0[1]. */
2754 /* A continuous range of registers, e.g. $s0-$s4. */
2757 /* A (possibly relocated) expression. */
2760 /* A floating-point value. */
2763 /* A single character. This can be '(', ')' or ',', but '(' only appears
2767 /* A doubled character, either "--" or "++". */
2770 /* The end of the operand list. */
2774 /* A parsed operand token. */
2775 struct mips_operand_token
2777 /* The type of token. */
2778 enum mips_operand_token_type type;
2781 /* The register symbol value for an OT_REG. */
2784 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2785 unsigned int channels;
2787 /* The register symbol value and index for an OT_REG_ELEMENT. */
2793 /* The two register symbol values involved in an OT_REG_RANGE. */
2795 unsigned int regno1;
2796 unsigned int regno2;
2799 /* The value of an OT_INTEGER. The value is represented as an
2800 expression and the relocation operators that were applied to
2801 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2802 relocation operators were used. */
2805 bfd_reloc_code_real_type relocs[3];
2808 /* The binary data for an OT_FLOAT constant, and the number of bytes
2811 unsigned char data[8];
2815 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2820 /* An obstack used to construct lists of mips_operand_tokens. */
2821 static struct obstack mips_operand_tokens;
2823 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2826 mips_add_token (struct mips_operand_token *token,
2827 enum mips_operand_token_type type)
2830 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2833 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2834 and OT_REG tokens for them if so, and return a pointer to the first
2835 unconsumed character. Return null otherwise. */
2838 mips_parse_base_start (char *s)
2840 struct mips_operand_token token;
2841 unsigned int regno, channels;
2842 bfd_boolean decrement_p;
2848 SKIP_SPACE_TABS (s);
2850 /* Only match "--" as part of a base expression. In other contexts "--X"
2851 is a double negative. */
2852 decrement_p = (s[0] == '-' && s[1] == '-');
2856 SKIP_SPACE_TABS (s);
2859 /* Allow a channel specifier because that leads to better error messages
2860 than treating something like "$vf0x++" as an expression. */
2861 if (!mips_parse_register (&s, ®no, &channels))
2865 mips_add_token (&token, OT_CHAR);
2870 mips_add_token (&token, OT_DOUBLE_CHAR);
2873 token.u.regno = regno;
2874 mips_add_token (&token, OT_REG);
2878 token.u.channels = channels;
2879 mips_add_token (&token, OT_CHANNELS);
2882 /* For consistency, only match "++" as part of base expressions too. */
2883 SKIP_SPACE_TABS (s);
2884 if (s[0] == '+' && s[1] == '+')
2888 mips_add_token (&token, OT_DOUBLE_CHAR);
2894 /* Parse one or more tokens from S. Return a pointer to the first
2895 unconsumed character on success. Return null if an error was found
2896 and store the error text in insn_error. FLOAT_FORMAT is as for
2897 mips_parse_arguments. */
2900 mips_parse_argument_token (char *s, char float_format)
2902 char *end, *save_in, *err;
2903 unsigned int regno1, regno2, channels;
2904 struct mips_operand_token token;
2906 /* First look for "($reg", since we want to treat that as an
2907 OT_CHAR and OT_REG rather than an expression. */
2908 end = mips_parse_base_start (s);
2912 /* Handle other characters that end up as OT_CHARs. */
2913 if (*s == ')' || *s == ',')
2916 mips_add_token (&token, OT_CHAR);
2921 /* Handle tokens that start with a register. */
2922 if (mips_parse_register (&s, ®no1, &channels))
2926 /* A register and a VU0 channel suffix. */
2927 token.u.regno = regno1;
2928 mips_add_token (&token, OT_REG);
2930 token.u.channels = channels;
2931 mips_add_token (&token, OT_CHANNELS);
2935 SKIP_SPACE_TABS (s);
2938 /* A register range. */
2940 SKIP_SPACE_TABS (s);
2941 if (!mips_parse_register (&s, ®no2, NULL))
2943 set_insn_error (0, _("Invalid register range"));
2947 token.u.reg_range.regno1 = regno1;
2948 token.u.reg_range.regno2 = regno2;
2949 mips_add_token (&token, OT_REG_RANGE);
2954 /* A vector element. */
2955 expressionS element;
2958 SKIP_SPACE_TABS (s);
2959 my_getExpression (&element, s);
2960 if (element.X_op != O_constant)
2962 set_insn_error (0, _("Vector element must be constant"));
2966 SKIP_SPACE_TABS (s);
2969 set_insn_error (0, _("Missing `]'"));
2974 token.u.reg_element.regno = regno1;
2975 token.u.reg_element.index = element.X_add_number;
2976 mips_add_token (&token, OT_REG_ELEMENT);
2980 /* Looks like just a plain register. */
2981 token.u.regno = regno1;
2982 mips_add_token (&token, OT_REG);
2988 /* First try to treat expressions as floats. */
2989 save_in = input_line_pointer;
2990 input_line_pointer = s;
2991 err = md_atof (float_format, (char *) token.u.flt.data,
2992 &token.u.flt.length);
2993 end = input_line_pointer;
2994 input_line_pointer = save_in;
2997 set_insn_error (0, err);
3002 mips_add_token (&token, OT_FLOAT);
3007 /* Treat everything else as an integer expression. */
3008 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3009 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3010 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3011 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3013 mips_add_token (&token, OT_INTEGER);
3017 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3018 if expressions should be treated as 32-bit floating-point constants,
3019 'd' if they should be treated as 64-bit floating-point constants,
3020 or 0 if they should be treated as integer expressions (the usual case).
3022 Return a list of tokens on success, otherwise return 0. The caller
3023 must obstack_free the list after use. */
3025 static struct mips_operand_token *
3026 mips_parse_arguments (char *s, char float_format)
3028 struct mips_operand_token token;
3030 SKIP_SPACE_TABS (s);
3033 s = mips_parse_argument_token (s, float_format);
3036 obstack_free (&mips_operand_tokens,
3037 obstack_finish (&mips_operand_tokens));
3040 SKIP_SPACE_TABS (s);
3042 mips_add_token (&token, OT_END);
3043 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3046 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3047 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3050 is_opcode_valid (const struct mips_opcode *mo)
3052 int isa = mips_opts.isa;
3053 int ase = mips_opts.ase;
3057 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3058 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3059 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3060 ase |= mips_ases[i].flags64;
3062 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3065 /* Check whether the instruction or macro requires single-precision or
3066 double-precision floating-point support. Note that this information is
3067 stored differently in the opcode table for insns and macros. */
3068 if (mo->pinfo == INSN_MACRO)
3070 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3071 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3075 fp_s = mo->pinfo & FP_S;
3076 fp_d = mo->pinfo & FP_D;
3079 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3082 if (fp_s && mips_opts.soft_float)
3088 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3089 selected ISA and architecture. */
3092 is_opcode_valid_16 (const struct mips_opcode *mo)
3094 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3097 /* Return TRUE if the size of the microMIPS opcode MO matches one
3098 explicitly requested. Always TRUE in the standard MIPS mode. */
3101 is_size_valid (const struct mips_opcode *mo)
3103 if (!mips_opts.micromips)
3106 if (mips_opts.insn32)
3108 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3110 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3113 if (!forced_insn_length)
3115 if (mo->pinfo == INSN_MACRO)
3117 return forced_insn_length == micromips_insn_length (mo);
3120 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3121 of the preceding instruction. Always TRUE in the standard MIPS mode.
3123 We don't accept macros in 16-bit delay slots to avoid a case where
3124 a macro expansion fails because it relies on a preceding 32-bit real
3125 instruction to have matched and does not handle the operands correctly.
3126 The only macros that may expand to 16-bit instructions are JAL that
3127 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3128 and BGT (that likewise cannot be placed in a delay slot) that decay to
3129 a NOP. In all these cases the macros precede any corresponding real
3130 instruction definitions in the opcode table, so they will match in the
3131 second pass where the size of the delay slot is ignored and therefore
3132 produce correct code. */
3135 is_delay_slot_valid (const struct mips_opcode *mo)
3137 if (!mips_opts.micromips)
3140 if (mo->pinfo == INSN_MACRO)
3141 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3142 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3143 && micromips_insn_length (mo) != 4)
3145 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3146 && micromips_insn_length (mo) != 2)
3152 /* For consistency checking, verify that all bits of OPCODE are specified
3153 either by the match/mask part of the instruction definition, or by the
3154 operand list. Also build up a list of operands in OPERANDS.
3156 INSN_BITS says which bits of the instruction are significant.
3157 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3158 provides the mips_operand description of each operand. DECODE_OPERAND
3159 is null for MIPS16 instructions. */
3162 validate_mips_insn (const struct mips_opcode *opcode,
3163 unsigned long insn_bits,
3164 const struct mips_operand *(*decode_operand) (const char *),
3165 struct mips_operand_array *operands)
3168 unsigned long used_bits, doubled, undefined, opno, mask;
3169 const struct mips_operand *operand;
3171 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3172 if ((mask & opcode->match) != opcode->match)
3174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3175 opcode->name, opcode->args);
3180 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3181 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3182 for (s = opcode->args; *s; ++s)
3195 if (!decode_operand)
3196 operand = decode_mips16_operand (*s, FALSE);
3198 operand = decode_operand (s);
3199 if (!operand && opcode->pinfo != INSN_MACRO)
3201 as_bad (_("internal: unknown operand type: %s %s"),
3202 opcode->name, opcode->args);
3205 gas_assert (opno < MAX_OPERANDS);
3206 operands->operand[opno] = operand;
3207 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3209 used_bits = mips_insert_operand (operand, used_bits, -1);
3210 if (operand->type == OP_MDMX_IMM_REG)
3211 /* Bit 5 is the format selector (OB vs QH). The opcode table
3212 has separate entries for each format. */
3213 used_bits &= ~(1 << (operand->lsb + 5));
3214 if (operand->type == OP_ENTRY_EXIT_LIST)
3215 used_bits &= ~(mask & 0x700);
3217 /* Skip prefix characters. */
3218 if (decode_operand && (*s == '+' || *s == 'm'))
3223 doubled = used_bits & mask & insn_bits;
3226 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3227 " %s %s"), doubled, opcode->name, opcode->args);
3231 undefined = ~used_bits & insn_bits;
3232 if (opcode->pinfo != INSN_MACRO && undefined)
3234 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3235 undefined, opcode->name, opcode->args);
3238 used_bits &= ~insn_bits;
3241 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3242 used_bits, opcode->name, opcode->args);
3248 /* The MIPS16 version of validate_mips_insn. */
3251 validate_mips16_insn (const struct mips_opcode *opcode,
3252 struct mips_operand_array *operands)
3254 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3256 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3257 instruction. Use TMP to describe the full instruction. */
3258 struct mips_opcode tmp;
3263 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3265 return validate_mips_insn (opcode, 0xffff, 0, operands);
3268 /* The microMIPS version of validate_mips_insn. */
3271 validate_micromips_insn (const struct mips_opcode *opc,
3272 struct mips_operand_array *operands)
3274 unsigned long insn_bits;
3275 unsigned long major;
3276 unsigned int length;
3278 if (opc->pinfo == INSN_MACRO)
3279 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3282 length = micromips_insn_length (opc);
3283 if (length != 2 && length != 4)
3285 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3286 "%s %s"), length, opc->name, opc->args);
3289 major = opc->match >> (10 + 8 * (length - 2));
3290 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3291 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3293 as_bad (_("Internal error: bad microMIPS opcode "
3294 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3298 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3299 insn_bits = 1 << 4 * length;
3300 insn_bits <<= 4 * length;
3302 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3306 /* This function is called once, at assembler startup time. It should set up
3307 all the tables, etc. that the MD part of the assembler will need. */
3312 const char *retval = NULL;
3316 if (mips_pic != NO_PIC)
3318 if (g_switch_seen && g_switch_value != 0)
3319 as_bad (_("-G may not be used in position-independent code"));
3323 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3324 as_warn (_("Could not set architecture and machine"));
3326 op_hash = hash_new ();
3328 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3329 for (i = 0; i < NUMOPCODES;)
3331 const char *name = mips_opcodes[i].name;
3333 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3336 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3337 mips_opcodes[i].name, retval);
3338 /* Probably a memory allocation problem? Give up now. */
3339 as_fatal (_("Broken assembler. No assembly attempted."));
3343 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3344 decode_mips_operand, &mips_operands[i]))
3346 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3348 create_insn (&nop_insn, mips_opcodes + i);
3349 if (mips_fix_loongson2f_nop)
3350 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3351 nop_insn.fixed_p = 1;
3355 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3358 mips16_op_hash = hash_new ();
3359 mips16_operands = XCNEWVEC (struct mips_operand_array,
3360 bfd_mips16_num_opcodes);
3363 while (i < bfd_mips16_num_opcodes)
3365 const char *name = mips16_opcodes[i].name;
3367 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3369 as_fatal (_("internal: can't hash `%s': %s"),
3370 mips16_opcodes[i].name, retval);
3373 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3375 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3377 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3378 mips16_nop_insn.fixed_p = 1;
3382 while (i < bfd_mips16_num_opcodes
3383 && strcmp (mips16_opcodes[i].name, name) == 0);
3386 micromips_op_hash = hash_new ();
3387 micromips_operands = XCNEWVEC (struct mips_operand_array,
3388 bfd_micromips_num_opcodes);
3391 while (i < bfd_micromips_num_opcodes)
3393 const char *name = micromips_opcodes[i].name;
3395 retval = hash_insert (micromips_op_hash, name,
3396 (void *) µmips_opcodes[i]);
3398 as_fatal (_("internal: can't hash `%s': %s"),
3399 micromips_opcodes[i].name, retval);
3402 struct mips_cl_insn *micromips_nop_insn;
3404 if (!validate_micromips_insn (µmips_opcodes[i],
3405 µmips_operands[i]))
3408 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3410 if (micromips_insn_length (micromips_opcodes + i) == 2)
3411 micromips_nop_insn = µmips_nop16_insn;
3412 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3413 micromips_nop_insn = µmips_nop32_insn;
3417 if (micromips_nop_insn->insn_mo == NULL
3418 && strcmp (name, "nop") == 0)
3420 create_insn (micromips_nop_insn, micromips_opcodes + i);
3421 micromips_nop_insn->fixed_p = 1;
3425 while (++i < bfd_micromips_num_opcodes
3426 && strcmp (micromips_opcodes[i].name, name) == 0);
3430 as_fatal (_("Broken assembler. No assembly attempted."));
3432 /* We add all the general register names to the symbol table. This
3433 helps us detect invalid uses of them. */
3434 for (i = 0; reg_names[i].name; i++)
3435 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3436 reg_names[i].num, /* & RNUM_MASK, */
3437 &zero_address_frag));
3439 for (i = 0; reg_names_n32n64[i].name; i++)
3440 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3441 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3442 &zero_address_frag));
3444 for (i = 0; reg_names_o32[i].name; i++)
3445 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3446 reg_names_o32[i].num, /* & RNUM_MASK, */
3447 &zero_address_frag));
3449 for (i = 0; i < 32; i++)
3453 /* R5900 VU0 floating-point register. */
3454 regname[sizeof (rename) - 1] = 0;
3455 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3456 symbol_table_insert (symbol_new (regname, reg_section,
3457 RTYPE_VF | i, &zero_address_frag));
3459 /* R5900 VU0 integer register. */
3460 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3461 symbol_table_insert (symbol_new (regname, reg_section,
3462 RTYPE_VI | i, &zero_address_frag));
3466 obstack_init (&mips_operand_tokens);
3468 mips_no_prev_insn ();
3471 mips_cprmask[0] = 0;
3472 mips_cprmask[1] = 0;
3473 mips_cprmask[2] = 0;
3474 mips_cprmask[3] = 0;
3476 /* set the default alignment for the text section (2**2) */
3477 record_alignment (text_section, 2);
3479 bfd_set_gp_size (stdoutput, g_switch_value);
3481 /* On a native system other than VxWorks, sections must be aligned
3482 to 16 byte boundaries. When configured for an embedded ELF
3483 target, we don't bother. */
3484 if (strncmp (TARGET_OS, "elf", 3) != 0
3485 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3487 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3488 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3489 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3492 /* Create a .reginfo section for register masks and a .mdebug
3493 section for debugging information. */
3501 subseg = now_subseg;
3503 /* The ABI says this section should be loaded so that the
3504 running program can access it. However, we don't load it
3505 if we are configured for an embedded target */
3506 flags = SEC_READONLY | SEC_DATA;
3507 if (strncmp (TARGET_OS, "elf", 3) != 0)
3508 flags |= SEC_ALLOC | SEC_LOAD;
3510 if (mips_abi != N64_ABI)
3512 sec = subseg_new (".reginfo", (subsegT) 0);
3514 bfd_set_section_flags (stdoutput, sec, flags);
3515 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3517 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3521 /* The 64-bit ABI uses a .MIPS.options section rather than
3522 .reginfo section. */
3523 sec = subseg_new (".MIPS.options", (subsegT) 0);
3524 bfd_set_section_flags (stdoutput, sec, flags);
3525 bfd_set_section_alignment (stdoutput, sec, 3);
3527 /* Set up the option header. */
3529 Elf_Internal_Options opthdr;
3532 opthdr.kind = ODK_REGINFO;
3533 opthdr.size = (sizeof (Elf_External_Options)
3534 + sizeof (Elf64_External_RegInfo));
3537 f = frag_more (sizeof (Elf_External_Options));
3538 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3539 (Elf_External_Options *) f);
3541 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3545 if (ECOFF_DEBUGGING)
3547 sec = subseg_new (".mdebug", (subsegT) 0);
3548 (void) bfd_set_section_flags (stdoutput, sec,
3549 SEC_HAS_CONTENTS | SEC_READONLY);
3550 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3552 else if (mips_flag_pdr)
3554 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3555 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3556 SEC_READONLY | SEC_RELOC
3558 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3561 subseg_set (seg, subseg);
3564 if (! ECOFF_DEBUGGING)
3567 if (mips_fix_vr4120)
3568 init_vr4120_conflicts ();
3574 mips_emit_delays ();
3575 if (! ECOFF_DEBUGGING)
3580 md_assemble (char *str)
3582 struct mips_cl_insn insn;
3583 bfd_reloc_code_real_type unused_reloc[3]
3584 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3586 imm_expr.X_op = O_absent;
3587 imm2_expr.X_op = O_absent;
3588 offset_expr.X_op = O_absent;
3589 offset_reloc[0] = BFD_RELOC_UNUSED;
3590 offset_reloc[1] = BFD_RELOC_UNUSED;
3591 offset_reloc[2] = BFD_RELOC_UNUSED;
3593 mips_mark_labels ();
3594 mips_assembling_insn = TRUE;
3595 clear_insn_error ();
3597 if (mips_opts.mips16)
3598 mips16_ip (str, &insn);
3601 mips_ip (str, &insn);
3602 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3603 str, insn.insn_opcode));
3607 report_insn_error (str);
3608 else if (insn.insn_mo->pinfo == INSN_MACRO)
3611 if (mips_opts.mips16)
3612 mips16_macro (&insn);
3619 if (offset_expr.X_op != O_absent)
3620 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3622 append_insn (&insn, NULL, unused_reloc, FALSE);
3625 mips_assembling_insn = FALSE;
3628 /* Convenience functions for abstracting away the differences between
3629 MIPS16 and non-MIPS16 relocations. */
3631 static inline bfd_boolean
3632 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3636 case BFD_RELOC_MIPS16_JMP:
3637 case BFD_RELOC_MIPS16_GPREL:
3638 case BFD_RELOC_MIPS16_GOT16:
3639 case BFD_RELOC_MIPS16_CALL16:
3640 case BFD_RELOC_MIPS16_HI16_S:
3641 case BFD_RELOC_MIPS16_HI16:
3642 case BFD_RELOC_MIPS16_LO16:
3650 static inline bfd_boolean
3651 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3655 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3656 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3657 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3658 case BFD_RELOC_MICROMIPS_GPREL16:
3659 case BFD_RELOC_MICROMIPS_JMP:
3660 case BFD_RELOC_MICROMIPS_HI16:
3661 case BFD_RELOC_MICROMIPS_HI16_S:
3662 case BFD_RELOC_MICROMIPS_LO16:
3663 case BFD_RELOC_MICROMIPS_LITERAL:
3664 case BFD_RELOC_MICROMIPS_GOT16:
3665 case BFD_RELOC_MICROMIPS_CALL16:
3666 case BFD_RELOC_MICROMIPS_GOT_HI16:
3667 case BFD_RELOC_MICROMIPS_GOT_LO16:
3668 case BFD_RELOC_MICROMIPS_CALL_HI16:
3669 case BFD_RELOC_MICROMIPS_CALL_LO16:
3670 case BFD_RELOC_MICROMIPS_SUB:
3671 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3672 case BFD_RELOC_MICROMIPS_GOT_OFST:
3673 case BFD_RELOC_MICROMIPS_GOT_DISP:
3674 case BFD_RELOC_MICROMIPS_HIGHEST:
3675 case BFD_RELOC_MICROMIPS_HIGHER:
3676 case BFD_RELOC_MICROMIPS_SCN_DISP:
3677 case BFD_RELOC_MICROMIPS_JALR:
3685 static inline bfd_boolean
3686 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3688 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3691 static inline bfd_boolean
3692 got16_reloc_p (bfd_reloc_code_real_type reloc)
3694 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3695 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3698 static inline bfd_boolean
3699 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3701 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3702 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3705 static inline bfd_boolean
3706 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3708 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3709 || reloc == BFD_RELOC_MICROMIPS_LO16);
3712 static inline bfd_boolean
3713 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3715 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3718 static inline bfd_boolean
3719 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3721 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3722 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3725 /* Return true if RELOC is a PC-relative relocation that does not have
3726 full address range. */
3728 static inline bfd_boolean
3729 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3733 case BFD_RELOC_16_PCREL_S2:
3734 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3735 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3736 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3739 case BFD_RELOC_32_PCREL:
3740 return HAVE_64BIT_ADDRESSES;
3747 /* Return true if the given relocation might need a matching %lo().
3748 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3749 need a matching %lo() when applied to local symbols. */
3751 static inline bfd_boolean
3752 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3754 return (HAVE_IN_PLACE_ADDENDS
3755 && (hi16_reloc_p (reloc)
3756 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3757 all GOT16 relocations evaluate to "G". */
3758 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3761 /* Return the type of %lo() reloc needed by RELOC, given that
3762 reloc_needs_lo_p. */
3764 static inline bfd_reloc_code_real_type
3765 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3767 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3768 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3772 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3775 static inline bfd_boolean
3776 fixup_has_matching_lo_p (fixS *fixp)
3778 return (fixp->fx_next != NULL
3779 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3780 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3781 && fixp->fx_offset == fixp->fx_next->fx_offset);
3784 /* Move all labels in LABELS to the current insertion point. TEXT_P
3785 says whether the labels refer to text or data. */
3788 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3790 struct insn_label_list *l;
3793 for (l = labels; l != NULL; l = l->next)
3795 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3796 symbol_set_frag (l->label, frag_now);
3797 val = (valueT) frag_now_fix ();
3798 /* MIPS16/microMIPS text labels are stored as odd. */
3799 if (text_p && HAVE_CODE_COMPRESSION)
3801 S_SET_VALUE (l->label, val);
3805 /* Move all labels in insn_labels to the current insertion point
3806 and treat them as text labels. */
3809 mips_move_text_labels (void)
3811 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3815 s_is_linkonce (symbolS *sym, segT from_seg)
3817 bfd_boolean linkonce = FALSE;
3818 segT symseg = S_GET_SEGMENT (sym);
3820 if (symseg != from_seg && !S_IS_LOCAL (sym))
3822 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3824 /* The GNU toolchain uses an extension for ELF: a section
3825 beginning with the magic string .gnu.linkonce is a
3826 linkonce section. */
3827 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3828 sizeof ".gnu.linkonce" - 1) == 0)
3834 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3835 linker to handle them specially, such as generating jalx instructions
3836 when needed. We also make them odd for the duration of the assembly,
3837 in order to generate the right sort of code. We will make them even
3838 in the adjust_symtab routine, while leaving them marked. This is
3839 convenient for the debugger and the disassembler. The linker knows
3840 to make them odd again. */
3843 mips_compressed_mark_label (symbolS *label)
3845 gas_assert (HAVE_CODE_COMPRESSION);
3847 if (mips_opts.mips16)
3848 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3850 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3851 if ((S_GET_VALUE (label) & 1) == 0
3852 /* Don't adjust the address if the label is global or weak, or
3853 in a link-once section, since we'll be emitting symbol reloc
3854 references to it which will be patched up by the linker, and
3855 the final value of the symbol may or may not be MIPS16/microMIPS. */
3856 && !S_IS_WEAK (label)
3857 && !S_IS_EXTERNAL (label)
3858 && !s_is_linkonce (label, now_seg))
3859 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3862 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3865 mips_compressed_mark_labels (void)
3867 struct insn_label_list *l;
3869 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3870 mips_compressed_mark_label (l->label);
3873 /* End the current frag. Make it a variant frag and record the
3877 relax_close_frag (void)
3879 mips_macro_warning.first_frag = frag_now;
3880 frag_var (rs_machine_dependent, 0, 0,
3881 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3882 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3884 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3885 mips_relax.first_fixup = 0;
3888 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3889 See the comment above RELAX_ENCODE for more details. */
3892 relax_start (symbolS *symbol)
3894 gas_assert (mips_relax.sequence == 0);
3895 mips_relax.sequence = 1;
3896 mips_relax.symbol = symbol;
3899 /* Start generating the second version of a relaxable sequence.
3900 See the comment above RELAX_ENCODE for more details. */
3905 gas_assert (mips_relax.sequence == 1);
3906 mips_relax.sequence = 2;
3909 /* End the current relaxable sequence. */
3914 gas_assert (mips_relax.sequence == 2);
3915 relax_close_frag ();
3916 mips_relax.sequence = 0;
3919 /* Return true if IP is a delayed branch or jump. */
3921 static inline bfd_boolean
3922 delayed_branch_p (const struct mips_cl_insn *ip)
3924 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3925 | INSN_COND_BRANCH_DELAY
3926 | INSN_COND_BRANCH_LIKELY)) != 0;
3929 /* Return true if IP is a compact branch or jump. */
3931 static inline bfd_boolean
3932 compact_branch_p (const struct mips_cl_insn *ip)
3934 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3935 | INSN2_COND_BRANCH)) != 0;
3938 /* Return true if IP is an unconditional branch or jump. */
3940 static inline bfd_boolean
3941 uncond_branch_p (const struct mips_cl_insn *ip)
3943 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3944 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3947 /* Return true if IP is a branch-likely instruction. */
3949 static inline bfd_boolean
3950 branch_likely_p (const struct mips_cl_insn *ip)
3952 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3955 /* Return the type of nop that should be used to fill the delay slot
3956 of delayed branch IP. */
3958 static struct mips_cl_insn *
3959 get_delay_slot_nop (const struct mips_cl_insn *ip)
3961 if (mips_opts.micromips
3962 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3963 return µmips_nop32_insn;
3967 /* Return a mask that has bit N set if OPCODE reads the register(s)
3971 insn_read_mask (const struct mips_opcode *opcode)
3973 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3976 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3980 insn_write_mask (const struct mips_opcode *opcode)
3982 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3985 /* Return a mask of the registers specified by operand OPERAND of INSN.
3986 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3990 operand_reg_mask (const struct mips_cl_insn *insn,
3991 const struct mips_operand *operand,
3992 unsigned int type_mask)
3994 unsigned int uval, vsel;
3996 switch (operand->type)
4003 case OP_ADDIUSP_INT:
4004 case OP_ENTRY_EXIT_LIST:
4005 case OP_REPEAT_DEST_REG:
4006 case OP_REPEAT_PREV_REG:
4009 case OP_VU0_MATCH_SUFFIX:
4013 case OP_OPTIONAL_REG:
4015 const struct mips_reg_operand *reg_op;
4017 reg_op = (const struct mips_reg_operand *) operand;
4018 if (!(type_mask & (1 << reg_op->reg_type)))
4020 uval = insn_extract_operand (insn, operand);
4021 return 1 << mips_decode_reg_operand (reg_op, uval);
4026 const struct mips_reg_pair_operand *pair_op;
4028 pair_op = (const struct mips_reg_pair_operand *) operand;
4029 if (!(type_mask & (1 << pair_op->reg_type)))
4031 uval = insn_extract_operand (insn, operand);
4032 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4035 case OP_CLO_CLZ_DEST:
4036 if (!(type_mask & (1 << OP_REG_GP)))
4038 uval = insn_extract_operand (insn, operand);
4039 return (1 << (uval & 31)) | (1 << (uval >> 5));
4041 case OP_LWM_SWM_LIST:
4044 case OP_SAVE_RESTORE_LIST:
4047 case OP_MDMX_IMM_REG:
4048 if (!(type_mask & (1 << OP_REG_VEC)))
4050 uval = insn_extract_operand (insn, operand);
4052 if ((vsel & 0x18) == 0x18)
4054 return 1 << (uval & 31);
4059 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4060 where bit N of OPNO_MASK is set if operand N should be included.
4061 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4065 insn_reg_mask (const struct mips_cl_insn *insn,
4066 unsigned int type_mask, unsigned int opno_mask)
4068 unsigned int opno, reg_mask;
4072 while (opno_mask != 0)
4075 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4082 /* Return the mask of core registers that IP reads. */
4085 gpr_read_mask (const struct mips_cl_insn *ip)
4087 unsigned long pinfo, pinfo2;
4090 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4091 pinfo = ip->insn_mo->pinfo;
4092 pinfo2 = ip->insn_mo->pinfo2;
4093 if (pinfo & INSN_UDI)
4095 /* UDI instructions have traditionally been assumed to read RS
4097 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4098 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4100 if (pinfo & INSN_READ_GPR_24)
4102 if (pinfo2 & INSN2_READ_GPR_16)
4104 if (pinfo2 & INSN2_READ_SP)
4106 if (pinfo2 & INSN2_READ_GPR_31)
4108 /* Don't include register 0. */
4112 /* Return the mask of core registers that IP writes. */
4115 gpr_write_mask (const struct mips_cl_insn *ip)
4117 unsigned long pinfo, pinfo2;
4120 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4121 pinfo = ip->insn_mo->pinfo;
4122 pinfo2 = ip->insn_mo->pinfo2;
4123 if (pinfo & INSN_WRITE_GPR_24)
4125 if (pinfo & INSN_WRITE_GPR_31)
4127 if (pinfo & INSN_UDI)
4128 /* UDI instructions have traditionally been assumed to write to RD. */
4129 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4130 if (pinfo2 & INSN2_WRITE_SP)
4132 /* Don't include register 0. */
4136 /* Return the mask of floating-point registers that IP reads. */
4139 fpr_read_mask (const struct mips_cl_insn *ip)
4141 unsigned long pinfo;
4144 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4145 insn_read_mask (ip->insn_mo));
4146 pinfo = ip->insn_mo->pinfo;
4147 /* Conservatively treat all operands to an FP_D instruction are doubles.
4148 (This is overly pessimistic for things like cvt.d.s.) */
4149 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4154 /* Return the mask of floating-point registers that IP writes. */
4157 fpr_write_mask (const struct mips_cl_insn *ip)
4159 unsigned long pinfo;
4162 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4163 insn_write_mask (ip->insn_mo));
4164 pinfo = ip->insn_mo->pinfo;
4165 /* Conservatively treat all operands to an FP_D instruction are doubles.
4166 (This is overly pessimistic for things like cvt.s.d.) */
4167 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4172 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4173 Check whether that is allowed. */
4176 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4178 const char *s = insn->name;
4180 if (insn->pinfo == INSN_MACRO)
4181 /* Let a macro pass, we'll catch it later when it is expanded. */
4184 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4186 /* Allow odd registers for single-precision ops. */
4187 switch (insn->pinfo & (FP_S | FP_D))
4198 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4199 s = strchr (insn->name, '.');
4200 if (s != NULL && opnum == 2)
4201 s = strchr (s + 1, '.');
4202 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4205 /* Single-precision coprocessor loads and moves are OK too. */
4206 if ((insn->pinfo & FP_S)
4207 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4208 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4214 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4215 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4216 this operand is normally printed in hex or decimal. */
4219 report_bad_range (struct mips_cl_insn *insn, int argnum,
4220 offsetT val, int min_val, int max_val,
4221 bfd_boolean print_hex)
4223 if (print_hex && val >= 0)
4224 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4226 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4228 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4230 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4232 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4234 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4237 /* Report an invalid combination of position and size operands for a bitfield
4238 operation. POS and SIZE are the values that were given. */
4241 report_bad_field (offsetT pos, offsetT size)
4243 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4244 (unsigned long) pos, (unsigned long) size);
4247 /* Information about an instruction argument that we're trying to match. */
4248 struct mips_arg_info
4250 /* The instruction so far. */
4251 struct mips_cl_insn *insn;
4253 /* The first unconsumed operand token. */
4254 struct mips_operand_token *token;
4256 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4259 /* The 1-based argument number, for error reporting. This does not
4260 count elided optional registers, etc.. */
4263 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4264 unsigned int last_regno;
4266 /* If the first operand was an OP_REG, this is the register that it
4267 specified, otherwise it is ILLEGAL_REG. */
4268 unsigned int dest_regno;
4270 /* The value of the last OP_INT operand. Only used for OP_MSB,
4271 where it gives the lsb position. */
4272 unsigned int last_op_int;
4274 /* If true, the OP_INT match routine should treat plain symbolic operands
4275 as if a relocation operator like %lo(...) had been used. This is only
4276 ever true if the operand can be relocated. */
4277 bfd_boolean allow_nonconst;
4279 /* When true, the OP_INT match routine should allow unsigned N-bit
4280 arguments to be used where a signed N-bit operand is expected. */
4281 bfd_boolean lax_max;
4283 /* True if a reference to the current AT register was seen. */
4284 bfd_boolean seen_at;
4287 /* Record that the argument is out of range. */
4290 match_out_of_range (struct mips_arg_info *arg)
4292 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4295 /* Record that the argument isn't constant but needs to be. */
4298 match_not_constant (struct mips_arg_info *arg)
4300 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4304 /* Try to match an OT_CHAR token for character CH. Consume the token
4305 and return true on success, otherwise return false. */
4308 match_char (struct mips_arg_info *arg, char ch)
4310 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4320 /* Try to get an expression from the next tokens in ARG. Consume the
4321 tokens and return true on success, storing the expression value in
4322 VALUE and relocation types in R. */
4325 match_expression (struct mips_arg_info *arg, expressionS *value,
4326 bfd_reloc_code_real_type *r)
4328 if (arg->token->type == OT_INTEGER)
4330 *value = arg->token->u.integer.value;
4331 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4336 /* Error-reporting is more consistent if we treat registers as O_register
4337 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4338 then handled in the same way. */
4339 if (arg->token->type == OT_REG)
4341 value->X_add_number = arg->token->u.regno;
4344 else if (arg->token[0].type == OT_CHAR
4345 && arg->token[0].u.ch == '('
4346 && arg->token[1].type == OT_REG
4347 && arg->token[2].type == OT_CHAR
4348 && arg->token[2].u.ch == ')')
4350 value->X_add_number = arg->token[1].u.regno;
4356 value->X_op = O_register;
4357 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4361 /* Try to get a constant expression from the next tokens in ARG. Consume
4362 the tokens and return return true on success, storing the constant value
4363 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4367 match_const_int (struct mips_arg_info *arg, offsetT *value)
4370 bfd_reloc_code_real_type r[3];
4372 if (!match_expression (arg, &ex, r))
4375 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4376 *value = ex.X_add_number;
4379 match_not_constant (arg);
4385 /* Return the RTYPE_* flags for a register operand of type TYPE that
4386 appears in instruction OPCODE. */
4389 convert_reg_type (const struct mips_opcode *opcode,
4390 enum mips_reg_operand_type type)
4395 return RTYPE_NUM | RTYPE_GP;
4398 /* Allow vector register names for MDMX if the instruction is a 64-bit
4399 FPR load, store or move (including moves to and from GPRs). */
4400 if ((mips_opts.ase & ASE_MDMX)
4401 && (opcode->pinfo & FP_D)
4402 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4403 | INSN_COPROC_MEMORY_DELAY
4404 | INSN_LOAD_COPROC_DELAY
4405 | INSN_LOAD_MEMORY_DELAY
4406 | INSN_STORE_MEMORY)))
4407 return RTYPE_FPU | RTYPE_VEC;
4411 if (opcode->pinfo & (FP_D | FP_S))
4412 return RTYPE_CCC | RTYPE_FCC;
4416 if (opcode->membership & INSN_5400)
4418 return RTYPE_FPU | RTYPE_VEC;
4424 if (opcode->name[strlen (opcode->name) - 1] == '0')
4425 return RTYPE_NUM | RTYPE_CP0;
4432 return RTYPE_NUM | RTYPE_VI;
4435 return RTYPE_NUM | RTYPE_VF;
4437 case OP_REG_R5900_I:
4438 return RTYPE_R5900_I;
4440 case OP_REG_R5900_Q:
4441 return RTYPE_R5900_Q;
4443 case OP_REG_R5900_R:
4444 return RTYPE_R5900_R;
4446 case OP_REG_R5900_ACC:
4447 return RTYPE_R5900_ACC;
4452 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4455 check_regno (struct mips_arg_info *arg,
4456 enum mips_reg_operand_type type, unsigned int regno)
4458 if (AT && type == OP_REG_GP && regno == AT)
4459 arg->seen_at = TRUE;
4461 if (type == OP_REG_FP
4464 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4465 as_warn (_("Float register should be even, was %d"), regno);
4467 if (type == OP_REG_CCC)
4472 name = arg->insn->insn_mo->name;
4473 length = strlen (name);
4474 if ((regno & 1) != 0
4475 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4476 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4477 as_warn (_("Condition code register should be even for %s, was %d"),
4480 if ((regno & 3) != 0
4481 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4482 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4487 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4488 a register of type TYPE. Return true on success, storing the register
4489 number in *REGNO and warning about any dubious uses. */
4492 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4493 unsigned int symval, unsigned int *regno)
4495 if (type == OP_REG_VEC)
4496 symval = mips_prefer_vec_regno (symval);
4497 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4500 *regno = symval & RNUM_MASK;
4501 check_regno (arg, type, *regno);
4505 /* Try to interpret the next token in ARG as a register of type TYPE.
4506 Consume the token and return true on success, storing the register
4507 number in *REGNO. Return false on failure. */
4510 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4511 unsigned int *regno)
4513 if (arg->token->type == OT_REG
4514 && match_regno (arg, type, arg->token->u.regno, regno))
4522 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4523 Consume the token and return true on success, storing the register numbers
4524 in *REGNO1 and *REGNO2. Return false on failure. */
4527 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4528 unsigned int *regno1, unsigned int *regno2)
4530 if (match_reg (arg, type, regno1))
4535 if (arg->token->type == OT_REG_RANGE
4536 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4537 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4538 && *regno1 <= *regno2)
4546 /* OP_INT matcher. */
4549 match_int_operand (struct mips_arg_info *arg,
4550 const struct mips_operand *operand_base)
4552 const struct mips_int_operand *operand;
4554 int min_val, max_val, factor;
4557 operand = (const struct mips_int_operand *) operand_base;
4558 factor = 1 << operand->shift;
4559 min_val = mips_int_operand_min (operand);
4560 max_val = mips_int_operand_max (operand);
4562 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4564 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4565 /* Assume we have an elided offset. The later match will fail
4566 if this turns out to be wrong. */
4568 else if (operand_base->lsb == 0
4569 && operand_base->size == 16
4570 && operand->shift == 0
4571 && operand->bias == 0
4572 && (operand->max_val == 32767 || operand->max_val == 65535))
4574 /* The operand can be relocated. */
4575 if (!match_expression (arg, &offset_expr, offset_reloc))
4578 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4579 /* Relocation operators were used. Accept the arguent and
4580 leave the relocation value in offset_expr and offset_relocs
4581 for the caller to process. */
4584 if (offset_expr.X_op != O_constant)
4586 /* If non-constant operands are allowed then leave them for
4587 the caller to process, otherwise fail the match. */
4588 if (!arg->allow_nonconst)
4590 match_not_constant (arg);
4593 offset_reloc[0] = BFD_RELOC_LO16;
4597 /* Clear the global state; we're going to install the operand
4599 sval = offset_expr.X_add_number;
4600 offset_expr.X_op = O_absent;
4604 if (!match_const_int (arg, &sval))
4608 arg->last_op_int = sval;
4610 if (sval < min_val || sval > max_val || sval % factor)
4612 match_out_of_range (arg);
4616 uval = (unsigned int) sval >> operand->shift;
4617 uval -= operand->bias;
4619 /* Handle -mfix-cn63xxp1. */
4621 && mips_fix_cn63xxp1
4622 && !mips_opts.micromips
4623 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4638 /* The rest must be changed to 28. */
4643 insn_insert_operand (arg->insn, operand_base, uval);
4647 /* OP_MAPPED_INT matcher. */
4650 match_mapped_int_operand (struct mips_arg_info *arg,
4651 const struct mips_operand *operand_base)
4653 const struct mips_mapped_int_operand *operand;
4654 unsigned int uval, num_vals;
4657 operand = (const struct mips_mapped_int_operand *) operand_base;
4658 if (!match_const_int (arg, &sval))
4661 num_vals = 1 << operand_base->size;
4662 for (uval = 0; uval < num_vals; uval++)
4663 if (operand->int_map[uval] == sval)
4665 if (uval == num_vals)
4667 match_out_of_range (arg);
4671 insn_insert_operand (arg->insn, operand_base, uval);
4675 /* OP_MSB matcher. */
4678 match_msb_operand (struct mips_arg_info *arg,
4679 const struct mips_operand *operand_base)
4681 const struct mips_msb_operand *operand;
4682 int min_val, max_val, max_high;
4683 offsetT size, sval, high;
4685 operand = (const struct mips_msb_operand *) operand_base;
4686 min_val = operand->bias;
4687 max_val = min_val + (1 << operand_base->size) - 1;
4688 max_high = operand->opsize;
4690 if (!match_const_int (arg, &size))
4693 high = size + arg->last_op_int;
4694 sval = operand->add_lsb ? high : size;
4696 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4698 match_out_of_range (arg);
4701 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4705 /* OP_REG matcher. */
4708 match_reg_operand (struct mips_arg_info *arg,
4709 const struct mips_operand *operand_base)
4711 const struct mips_reg_operand *operand;
4712 unsigned int regno, uval, num_vals;
4714 operand = (const struct mips_reg_operand *) operand_base;
4715 if (!match_reg (arg, operand->reg_type, ®no))
4718 if (operand->reg_map)
4720 num_vals = 1 << operand->root.size;
4721 for (uval = 0; uval < num_vals; uval++)
4722 if (operand->reg_map[uval] == regno)
4724 if (num_vals == uval)
4730 arg->last_regno = regno;
4731 if (arg->opnum == 1)
4732 arg->dest_regno = regno;
4733 insn_insert_operand (arg->insn, operand_base, uval);
4737 /* OP_REG_PAIR matcher. */
4740 match_reg_pair_operand (struct mips_arg_info *arg,
4741 const struct mips_operand *operand_base)
4743 const struct mips_reg_pair_operand *operand;
4744 unsigned int regno1, regno2, uval, num_vals;
4746 operand = (const struct mips_reg_pair_operand *) operand_base;
4747 if (!match_reg (arg, operand->reg_type, ®no1)
4748 || !match_char (arg, ',')
4749 || !match_reg (arg, operand->reg_type, ®no2))
4752 num_vals = 1 << operand_base->size;
4753 for (uval = 0; uval < num_vals; uval++)
4754 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4756 if (uval == num_vals)
4759 insn_insert_operand (arg->insn, operand_base, uval);
4763 /* OP_PCREL matcher. The caller chooses the relocation type. */
4766 match_pcrel_operand (struct mips_arg_info *arg)
4768 bfd_reloc_code_real_type r[3];
4770 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4773 /* OP_PERF_REG matcher. */
4776 match_perf_reg_operand (struct mips_arg_info *arg,
4777 const struct mips_operand *operand)
4781 if (!match_const_int (arg, &sval))
4786 || (mips_opts.arch == CPU_R5900
4787 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4788 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4790 set_insn_error (arg->argnum, _("invalid performance register"));
4794 insn_insert_operand (arg->insn, operand, sval);
4798 /* OP_ADDIUSP matcher. */
4801 match_addiusp_operand (struct mips_arg_info *arg,
4802 const struct mips_operand *operand)
4807 if (!match_const_int (arg, &sval))
4812 match_out_of_range (arg);
4817 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4819 match_out_of_range (arg);
4823 uval = (unsigned int) sval;
4824 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4825 insn_insert_operand (arg->insn, operand, uval);
4829 /* OP_CLO_CLZ_DEST matcher. */
4832 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4833 const struct mips_operand *operand)
4837 if (!match_reg (arg, OP_REG_GP, ®no))
4840 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4844 /* OP_LWM_SWM_LIST matcher. */
4847 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4848 const struct mips_operand *operand)
4850 unsigned int reglist, sregs, ra, regno1, regno2;
4851 struct mips_arg_info reset;
4854 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4858 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4863 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4866 while (match_char (arg, ',')
4867 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4870 if (operand->size == 2)
4872 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4878 and any permutations of these. */
4879 if ((reglist & 0xfff1ffff) != 0x80010000)
4882 sregs = (reglist >> 17) & 7;
4887 /* The list must include at least one of ra and s0-sN,
4888 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4889 which are $23 and $30 respectively.) E.g.:
4897 and any permutations of these. */
4898 if ((reglist & 0x3f00ffff) != 0)
4901 ra = (reglist >> 27) & 0x10;
4902 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4905 if ((sregs & -sregs) != sregs)
4908 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4912 /* OP_ENTRY_EXIT_LIST matcher. */
4915 match_entry_exit_operand (struct mips_arg_info *arg,
4916 const struct mips_operand *operand)
4919 bfd_boolean is_exit;
4921 /* The format is the same for both ENTRY and EXIT, but the constraints
4923 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4924 mask = (is_exit ? 7 << 3 : 0);
4927 unsigned int regno1, regno2;
4928 bfd_boolean is_freg;
4930 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4932 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4937 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4940 mask |= (5 + regno2) << 3;
4942 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4943 mask |= (regno2 - 3) << 3;
4944 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4945 mask |= (regno2 - 15) << 1;
4946 else if (regno1 == RA && regno2 == RA)
4951 while (match_char (arg, ','));
4953 insn_insert_operand (arg->insn, operand, mask);
4957 /* OP_SAVE_RESTORE_LIST matcher. */
4960 match_save_restore_list_operand (struct mips_arg_info *arg)
4962 unsigned int opcode, args, statics, sregs;
4963 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4966 opcode = arg->insn->insn_opcode;
4968 num_frame_sizes = 0;
4974 unsigned int regno1, regno2;
4976 if (arg->token->type == OT_INTEGER)
4978 /* Handle the frame size. */
4979 if (!match_const_int (arg, &frame_size))
4981 num_frame_sizes += 1;
4985 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4988 while (regno1 <= regno2)
4990 if (regno1 >= 4 && regno1 <= 7)
4992 if (num_frame_sizes == 0)
4994 args |= 1 << (regno1 - 4);
4996 /* statics $a0-$a3 */
4997 statics |= 1 << (regno1 - 4);
4999 else if (regno1 >= 16 && regno1 <= 23)
5001 sregs |= 1 << (regno1 - 16);
5002 else if (regno1 == 30)
5005 else if (regno1 == 31)
5006 /* Add $ra to insn. */
5016 while (match_char (arg, ','));
5018 /* Encode args/statics combination. */
5021 else if (args == 0xf)
5022 /* All $a0-$a3 are args. */
5023 opcode |= MIPS16_ALL_ARGS << 16;
5024 else if (statics == 0xf)
5025 /* All $a0-$a3 are statics. */
5026 opcode |= MIPS16_ALL_STATICS << 16;
5029 /* Count arg registers. */
5039 /* Count static registers. */
5041 while (statics & 0x8)
5043 statics = (statics << 1) & 0xf;
5049 /* Encode args/statics. */
5050 opcode |= ((num_args << 2) | num_statics) << 16;
5053 /* Encode $s0/$s1. */
5054 if (sregs & (1 << 0)) /* $s0 */
5056 if (sregs & (1 << 1)) /* $s1 */
5060 /* Encode $s2-$s8. */
5069 opcode |= num_sregs << 24;
5071 /* Encode frame size. */
5072 if (num_frame_sizes == 0)
5074 set_insn_error (arg->argnum, _("missing frame size"));
5077 if (num_frame_sizes > 1)
5079 set_insn_error (arg->argnum, _("frame size specified twice"));
5082 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5084 set_insn_error (arg->argnum, _("invalid frame size"));
5087 if (frame_size != 128 || (opcode >> 16) != 0)
5090 opcode |= (((frame_size & 0xf0) << 16)
5091 | (frame_size & 0x0f));
5094 /* Finally build the instruction. */
5095 if ((opcode >> 16) != 0 || frame_size == 0)
5096 opcode |= MIPS16_EXTEND;
5097 arg->insn->insn_opcode = opcode;
5101 /* OP_MDMX_IMM_REG matcher. */
5104 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5105 const struct mips_operand *operand)
5107 unsigned int regno, uval;
5109 const struct mips_opcode *opcode;
5111 /* The mips_opcode records whether this is an octobyte or quadhalf
5112 instruction. Start out with that bit in place. */
5113 opcode = arg->insn->insn_mo;
5114 uval = mips_extract_operand (operand, opcode->match);
5115 is_qh = (uval != 0);
5117 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
5119 if ((opcode->membership & INSN_5400)
5120 && strcmp (opcode->name, "rzu.ob") == 0)
5122 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5127 /* Check whether this is a vector register or a broadcast of
5128 a single element. */
5129 if (arg->token->type == OT_REG_ELEMENT)
5131 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
5134 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
5136 set_insn_error (arg->argnum, _("invalid element selector"));
5140 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
5144 /* A full vector. */
5145 if ((opcode->membership & INSN_5400)
5146 && (strcmp (opcode->name, "sll.ob") == 0
5147 || strcmp (opcode->name, "srl.ob") == 0))
5149 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5154 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5157 uval |= MDMX_FMTSEL_VEC_QH << 5;
5159 uval |= MDMX_FMTSEL_VEC_OB << 5;
5168 if (!match_const_int (arg, &sval))
5170 if (sval < 0 || sval > 31)
5172 match_out_of_range (arg);
5175 uval |= (sval & 31);
5177 uval |= MDMX_FMTSEL_IMM_QH << 5;
5179 uval |= MDMX_FMTSEL_IMM_OB << 5;
5181 insn_insert_operand (arg->insn, operand, uval);
5185 /* OP_PC matcher. */
5188 match_pc_operand (struct mips_arg_info *arg)
5190 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5198 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5199 register that we need to match. */
5202 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5206 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5209 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5210 the length of the value in bytes (4 for float, 8 for double) and
5211 USING_GPRS says whether the destination is a GPR rather than an FPR.
5213 Return the constant in IMM and OFFSET as follows:
5215 - If the constant should be loaded via memory, set IMM to O_absent and
5216 OFFSET to the memory address.
5218 - Otherwise, if the constant should be loaded into two 32-bit registers,
5219 set IMM to the O_constant to load into the high register and OFFSET
5220 to the corresponding value for the low register.
5222 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5224 These constants only appear as the last operand in an instruction,
5225 and every instruction that accepts them in any variant accepts them
5226 in all variants. This means we don't have to worry about backing out
5227 any changes if the instruction does not match. We just match
5228 unconditionally and report an error if the constant is invalid. */
5231 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5232 expressionS *offset, int length, bfd_boolean using_gprs)
5237 const char *newname;
5238 unsigned char *data;
5240 /* Where the constant is placed is based on how the MIPS assembler
5243 length == 4 && using_gprs -- immediate value only
5244 length == 8 && using_gprs -- .rdata or immediate value
5245 length == 4 && !using_gprs -- .lit4 or immediate value
5246 length == 8 && !using_gprs -- .lit8 or immediate value
5248 The .lit4 and .lit8 sections are only used if permitted by the
5250 if (arg->token->type != OT_FLOAT)
5252 set_insn_error (arg->argnum, _("floating-point expression required"));
5256 gas_assert (arg->token->u.flt.length == length);
5257 data = arg->token->u.flt.data;
5260 /* Handle 32-bit constants for which an immediate value is best. */
5263 || g_switch_value < 4
5264 || (data[0] == 0 && data[1] == 0)
5265 || (data[2] == 0 && data[3] == 0)))
5267 imm->X_op = O_constant;
5268 if (!target_big_endian)
5269 imm->X_add_number = bfd_getl32 (data);
5271 imm->X_add_number = bfd_getb32 (data);
5272 offset->X_op = O_absent;
5276 /* Handle 64-bit constants for which an immediate value is best. */
5278 && !mips_disable_float_construction
5279 /* Constants can only be constructed in GPRs and copied
5280 to FPRs if the GPRs are at least as wide as the FPRs.
5281 Force the constant into memory if we are using 64-bit FPRs
5282 but the GPRs are only 32 bits wide. */
5283 /* ??? No longer true with the addition of MTHC1, but this
5284 is legacy code... */
5285 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5286 && ((data[0] == 0 && data[1] == 0)
5287 || (data[2] == 0 && data[3] == 0))
5288 && ((data[4] == 0 && data[5] == 0)
5289 || (data[6] == 0 && data[7] == 0)))
5291 /* The value is simple enough to load with a couple of instructions.
5292 If using 32-bit registers, set IMM to the high order 32 bits and
5293 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5295 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5297 imm->X_op = O_constant;
5298 offset->X_op = O_constant;
5299 if (!target_big_endian)
5301 imm->X_add_number = bfd_getl32 (data + 4);
5302 offset->X_add_number = bfd_getl32 (data);
5306 imm->X_add_number = bfd_getb32 (data);
5307 offset->X_add_number = bfd_getb32 (data + 4);
5309 if (offset->X_add_number == 0)
5310 offset->X_op = O_absent;
5314 imm->X_op = O_constant;
5315 if (!target_big_endian)
5316 imm->X_add_number = bfd_getl64 (data);
5318 imm->X_add_number = bfd_getb64 (data);
5319 offset->X_op = O_absent;
5324 /* Switch to the right section. */
5326 subseg = now_subseg;
5329 gas_assert (!using_gprs && g_switch_value >= 4);
5334 if (using_gprs || g_switch_value < 8)
5335 newname = RDATA_SECTION_NAME;
5340 new_seg = subseg_new (newname, (subsegT) 0);
5341 bfd_set_section_flags (stdoutput, new_seg,
5342 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5343 frag_align (length == 4 ? 2 : 3, 0, 0);
5344 if (strncmp (TARGET_OS, "elf", 3) != 0)
5345 record_alignment (new_seg, 4);
5347 record_alignment (new_seg, length == 4 ? 2 : 3);
5349 as_bad (_("Can't use floating point insn in this section"));
5351 /* Set the argument to the current address in the section. */
5352 imm->X_op = O_absent;
5353 offset->X_op = O_symbol;
5354 offset->X_add_symbol = symbol_temp_new_now ();
5355 offset->X_add_number = 0;
5357 /* Put the floating point number into the section. */
5358 p = frag_more (length);
5359 memcpy (p, data, length);
5361 /* Switch back to the original section. */
5362 subseg_set (seg, subseg);
5366 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5370 match_vu0_suffix_operand (struct mips_arg_info *arg,
5371 const struct mips_operand *operand,
5372 bfd_boolean match_p)
5376 /* The operand can be an XYZW mask or a single 2-bit channel index
5377 (with X being 0). */
5378 gas_assert (operand->size == 2 || operand->size == 4);
5380 /* The suffix can be omitted when it is already part of the opcode. */
5381 if (arg->token->type != OT_CHANNELS)
5384 uval = arg->token->u.channels;
5385 if (operand->size == 2)
5387 /* Check that a single bit is set and convert it into a 2-bit index. */
5388 if ((uval & -uval) != uval)
5390 uval = 4 - ffs (uval);
5393 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5398 insn_insert_operand (arg->insn, operand, uval);
5402 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5403 of the argument text if the match is successful, otherwise return null. */
5406 match_operand (struct mips_arg_info *arg,
5407 const struct mips_operand *operand)
5409 switch (operand->type)
5412 return match_int_operand (arg, operand);
5415 return match_mapped_int_operand (arg, operand);
5418 return match_msb_operand (arg, operand);
5421 case OP_OPTIONAL_REG:
5422 return match_reg_operand (arg, operand);
5425 return match_reg_pair_operand (arg, operand);
5428 return match_pcrel_operand (arg);
5431 return match_perf_reg_operand (arg, operand);
5433 case OP_ADDIUSP_INT:
5434 return match_addiusp_operand (arg, operand);
5436 case OP_CLO_CLZ_DEST:
5437 return match_clo_clz_dest_operand (arg, operand);
5439 case OP_LWM_SWM_LIST:
5440 return match_lwm_swm_list_operand (arg, operand);
5442 case OP_ENTRY_EXIT_LIST:
5443 return match_entry_exit_operand (arg, operand);
5445 case OP_SAVE_RESTORE_LIST:
5446 return match_save_restore_list_operand (arg);
5448 case OP_MDMX_IMM_REG:
5449 return match_mdmx_imm_reg_operand (arg, operand);
5451 case OP_REPEAT_DEST_REG:
5452 return match_tied_reg_operand (arg, arg->dest_regno);
5454 case OP_REPEAT_PREV_REG:
5455 return match_tied_reg_operand (arg, arg->last_regno);
5458 return match_pc_operand (arg);
5461 return match_vu0_suffix_operand (arg, operand, FALSE);
5463 case OP_VU0_MATCH_SUFFIX:
5464 return match_vu0_suffix_operand (arg, operand, TRUE);
5469 /* ARG is the state after successfully matching an instruction.
5470 Issue any queued-up warnings. */
5473 check_completed_insn (struct mips_arg_info *arg)
5478 as_warn (_("Used $at without \".set noat\""));
5480 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5484 /* Return true if modifying general-purpose register REG needs a delay. */
5487 reg_needs_delay (unsigned int reg)
5489 unsigned long prev_pinfo;
5491 prev_pinfo = history[0].insn_mo->pinfo;
5492 if (!mips_opts.noreorder
5493 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5494 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5495 && (gpr_write_mask (&history[0]) & (1 << reg)))
5501 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5502 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5503 by VR4120 errata. */
5506 classify_vr4120_insn (const char *name)
5508 if (strncmp (name, "macc", 4) == 0)
5509 return FIX_VR4120_MACC;
5510 if (strncmp (name, "dmacc", 5) == 0)
5511 return FIX_VR4120_DMACC;
5512 if (strncmp (name, "mult", 4) == 0)
5513 return FIX_VR4120_MULT;
5514 if (strncmp (name, "dmult", 5) == 0)
5515 return FIX_VR4120_DMULT;
5516 if (strstr (name, "div"))
5517 return FIX_VR4120_DIV;
5518 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5519 return FIX_VR4120_MTHILO;
5520 return NUM_FIX_VR4120_CLASSES;
5523 #define INSN_ERET 0x42000018
5524 #define INSN_DERET 0x4200001f
5526 /* Return the number of instructions that must separate INSN1 and INSN2,
5527 where INSN1 is the earlier instruction. Return the worst-case value
5528 for any INSN2 if INSN2 is null. */
5531 insns_between (const struct mips_cl_insn *insn1,
5532 const struct mips_cl_insn *insn2)
5534 unsigned long pinfo1, pinfo2;
5537 /* If INFO2 is null, pessimistically assume that all flags are set for
5538 the second instruction. */
5539 pinfo1 = insn1->insn_mo->pinfo;
5540 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5542 /* For most targets, write-after-read dependencies on the HI and LO
5543 registers must be separated by at least two instructions. */
5544 if (!hilo_interlocks)
5546 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5548 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5552 /* If we're working around r7000 errata, there must be two instructions
5553 between an mfhi or mflo and any instruction that uses the result. */
5554 if (mips_7000_hilo_fix
5555 && !mips_opts.micromips
5556 && MF_HILO_INSN (pinfo1)
5557 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5560 /* If we're working around 24K errata, one instruction is required
5561 if an ERET or DERET is followed by a branch instruction. */
5562 if (mips_fix_24k && !mips_opts.micromips)
5564 if (insn1->insn_opcode == INSN_ERET
5565 || insn1->insn_opcode == INSN_DERET)
5568 || insn2->insn_opcode == INSN_ERET
5569 || insn2->insn_opcode == INSN_DERET
5570 || delayed_branch_p (insn2))
5575 /* If working around VR4120 errata, check for combinations that need
5576 a single intervening instruction. */
5577 if (mips_fix_vr4120 && !mips_opts.micromips)
5579 unsigned int class1, class2;
5581 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5582 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5586 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5587 if (vr4120_conflicts[class1] & (1 << class2))
5592 if (!HAVE_CODE_COMPRESSION)
5594 /* Check for GPR or coprocessor load delays. All such delays
5595 are on the RT register. */
5596 /* Itbl support may require additional care here. */
5597 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5598 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5600 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5604 /* Check for generic coprocessor hazards.
5606 This case is not handled very well. There is no special
5607 knowledge of CP0 handling, and the coprocessors other than
5608 the floating point unit are not distinguished at all. */
5609 /* Itbl support may require additional care here. FIXME!
5610 Need to modify this to include knowledge about
5611 user specified delays! */
5612 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5613 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5615 /* Handle cases where INSN1 writes to a known general coprocessor
5616 register. There must be a one instruction delay before INSN2
5617 if INSN2 reads that register, otherwise no delay is needed. */
5618 mask = fpr_write_mask (insn1);
5621 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5626 /* Read-after-write dependencies on the control registers
5627 require a two-instruction gap. */
5628 if ((pinfo1 & INSN_WRITE_COND_CODE)
5629 && (pinfo2 & INSN_READ_COND_CODE))
5632 /* We don't know exactly what INSN1 does. If INSN2 is
5633 also a coprocessor instruction, assume there must be
5634 a one instruction gap. */
5635 if (pinfo2 & INSN_COP)
5640 /* Check for read-after-write dependencies on the coprocessor
5641 control registers in cases where INSN1 does not need a general
5642 coprocessor delay. This means that INSN1 is a floating point
5643 comparison instruction. */
5644 /* Itbl support may require additional care here. */
5645 else if (!cop_interlocks
5646 && (pinfo1 & INSN_WRITE_COND_CODE)
5647 && (pinfo2 & INSN_READ_COND_CODE))
5654 /* Return the number of nops that would be needed to work around the
5655 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5656 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5657 that are contained within the first IGNORE instructions of HIST. */
5660 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5661 const struct mips_cl_insn *insn)
5666 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5667 are not affected by the errata. */
5669 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5670 || strcmp (insn->insn_mo->name, "mtlo") == 0
5671 || strcmp (insn->insn_mo->name, "mthi") == 0))
5674 /* Search for the first MFLO or MFHI. */
5675 for (i = 0; i < MAX_VR4130_NOPS; i++)
5676 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5678 /* Extract the destination register. */
5679 mask = gpr_write_mask (&hist[i]);
5681 /* No nops are needed if INSN reads that register. */
5682 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5685 /* ...or if any of the intervening instructions do. */
5686 for (j = 0; j < i; j++)
5687 if (gpr_read_mask (&hist[j]) & mask)
5691 return MAX_VR4130_NOPS - i;
5696 #define BASE_REG_EQ(INSN1, INSN2) \
5697 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5698 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5700 /* Return the minimum alignment for this store instruction. */
5703 fix_24k_align_to (const struct mips_opcode *mo)
5705 if (strcmp (mo->name, "sh") == 0)
5708 if (strcmp (mo->name, "swc1") == 0
5709 || strcmp (mo->name, "swc2") == 0
5710 || strcmp (mo->name, "sw") == 0
5711 || strcmp (mo->name, "sc") == 0
5712 || strcmp (mo->name, "s.s") == 0)
5715 if (strcmp (mo->name, "sdc1") == 0
5716 || strcmp (mo->name, "sdc2") == 0
5717 || strcmp (mo->name, "s.d") == 0)
5724 struct fix_24k_store_info
5726 /* Immediate offset, if any, for this store instruction. */
5728 /* Alignment required by this store instruction. */
5730 /* True for register offsets. */
5731 int register_offset;
5734 /* Comparison function used by qsort. */
5737 fix_24k_sort (const void *a, const void *b)
5739 const struct fix_24k_store_info *pos1 = a;
5740 const struct fix_24k_store_info *pos2 = b;
5742 return (pos1->off - pos2->off);
5745 /* INSN is a store instruction. Try to record the store information
5746 in STINFO. Return false if the information isn't known. */
5749 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5750 const struct mips_cl_insn *insn)
5752 /* The instruction must have a known offset. */
5753 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5756 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5757 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5761 /* Return the number of nops that would be needed to work around the 24k
5762 "lost data on stores during refill" errata if instruction INSN
5763 immediately followed the 2 instructions described by HIST.
5764 Ignore hazards that are contained within the first IGNORE
5765 instructions of HIST.
5767 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5768 for the data cache refills and store data. The following describes
5769 the scenario where the store data could be lost.
5771 * A data cache miss, due to either a load or a store, causing fill
5772 data to be supplied by the memory subsystem
5773 * The first three doublewords of fill data are returned and written
5775 * A sequence of four stores occurs in consecutive cycles around the
5776 final doubleword of the fill:
5780 * Zero, One or more instructions
5783 The four stores A-D must be to different doublewords of the line that
5784 is being filled. The fourth instruction in the sequence above permits
5785 the fill of the final doubleword to be transferred from the FSB into
5786 the cache. In the sequence above, the stores may be either integer
5787 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5788 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5789 different doublewords on the line. If the floating point unit is
5790 running in 1:2 mode, it is not possible to create the sequence above
5791 using only floating point store instructions.
5793 In this case, the cache line being filled is incorrectly marked
5794 invalid, thereby losing the data from any store to the line that
5795 occurs between the original miss and the completion of the five
5796 cycle sequence shown above.
5798 The workarounds are:
5800 * Run the data cache in write-through mode.
5801 * Insert a non-store instruction between
5802 Store A and Store B or Store B and Store C. */
5805 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5806 const struct mips_cl_insn *insn)
5808 struct fix_24k_store_info pos[3];
5809 int align, i, base_offset;
5814 /* If the previous instruction wasn't a store, there's nothing to
5816 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5819 /* If the instructions after the previous one are unknown, we have
5820 to assume the worst. */
5824 /* Check whether we are dealing with three consecutive stores. */
5825 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5826 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5829 /* If we don't know the relationship between the store addresses,
5830 assume the worst. */
5831 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5832 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5835 if (!fix_24k_record_store_info (&pos[0], insn)
5836 || !fix_24k_record_store_info (&pos[1], &hist[0])
5837 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5840 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5842 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5843 X bytes and such that the base register + X is known to be aligned
5846 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5850 align = pos[0].align_to;
5851 base_offset = pos[0].off;
5852 for (i = 1; i < 3; i++)
5853 if (align < pos[i].align_to)
5855 align = pos[i].align_to;
5856 base_offset = pos[i].off;
5858 for (i = 0; i < 3; i++)
5859 pos[i].off -= base_offset;
5862 pos[0].off &= ~align + 1;
5863 pos[1].off &= ~align + 1;
5864 pos[2].off &= ~align + 1;
5866 /* If any two stores write to the same chunk, they also write to the
5867 same doubleword. The offsets are still sorted at this point. */
5868 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5871 /* A range of at least 9 bytes is needed for the stores to be in
5872 non-overlapping doublewords. */
5873 if (pos[2].off - pos[0].off <= 8)
5876 if (pos[2].off - pos[1].off >= 24
5877 || pos[1].off - pos[0].off >= 24
5878 || pos[2].off - pos[0].off >= 32)
5884 /* Return the number of nops that would be needed if instruction INSN
5885 immediately followed the MAX_NOPS instructions given by HIST,
5886 where HIST[0] is the most recent instruction. Ignore hazards
5887 between INSN and the first IGNORE instructions in HIST.
5889 If INSN is null, return the worse-case number of nops for any
5893 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5894 const struct mips_cl_insn *insn)
5896 int i, nops, tmp_nops;
5899 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5901 tmp_nops = insns_between (hist + i, insn) - i;
5902 if (tmp_nops > nops)
5906 if (mips_fix_vr4130 && !mips_opts.micromips)
5908 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5909 if (tmp_nops > nops)
5913 if (mips_fix_24k && !mips_opts.micromips)
5915 tmp_nops = nops_for_24k (ignore, hist, insn);
5916 if (tmp_nops > nops)
5923 /* The variable arguments provide NUM_INSNS extra instructions that
5924 might be added to HIST. Return the largest number of nops that
5925 would be needed after the extended sequence, ignoring hazards
5926 in the first IGNORE instructions. */
5929 nops_for_sequence (int num_insns, int ignore,
5930 const struct mips_cl_insn *hist, ...)
5933 struct mips_cl_insn buffer[MAX_NOPS];
5934 struct mips_cl_insn *cursor;
5937 va_start (args, hist);
5938 cursor = buffer + num_insns;
5939 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5940 while (cursor > buffer)
5941 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5943 nops = nops_for_insn (ignore, buffer, NULL);
5948 /* Like nops_for_insn, but if INSN is a branch, take into account the
5949 worst-case delay for the branch target. */
5952 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5953 const struct mips_cl_insn *insn)
5957 nops = nops_for_insn (ignore, hist, insn);
5958 if (delayed_branch_p (insn))
5960 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5961 hist, insn, get_delay_slot_nop (insn));
5962 if (tmp_nops > nops)
5965 else if (compact_branch_p (insn))
5967 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5968 if (tmp_nops > nops)
5974 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5977 fix_loongson2f_nop (struct mips_cl_insn * ip)
5979 gas_assert (!HAVE_CODE_COMPRESSION);
5980 if (strcmp (ip->insn_mo->name, "nop") == 0)
5981 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5984 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5985 jr target pc &= 'hffff_ffff_cfff_ffff. */
5988 fix_loongson2f_jump (struct mips_cl_insn * ip)
5990 gas_assert (!HAVE_CODE_COMPRESSION);
5991 if (strcmp (ip->insn_mo->name, "j") == 0
5992 || strcmp (ip->insn_mo->name, "jr") == 0
5993 || strcmp (ip->insn_mo->name, "jalr") == 0)
6001 sreg = EXTRACT_OPERAND (0, RS, *ip);
6002 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6005 ep.X_op = O_constant;
6006 ep.X_add_number = 0xcfff0000;
6007 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6008 ep.X_add_number = 0xffff;
6009 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6010 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6015 fix_loongson2f (struct mips_cl_insn * ip)
6017 if (mips_fix_loongson2f_nop)
6018 fix_loongson2f_nop (ip);
6020 if (mips_fix_loongson2f_jump)
6021 fix_loongson2f_jump (ip);
6024 /* IP is a branch that has a delay slot, and we need to fill it
6025 automatically. Return true if we can do that by swapping IP
6026 with the previous instruction.
6027 ADDRESS_EXPR is an operand of the instruction to be used with
6031 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6032 bfd_reloc_code_real_type *reloc_type)
6034 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6035 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6037 /* -O2 and above is required for this optimization. */
6038 if (mips_optimize < 2)
6041 /* If we have seen .set volatile or .set nomove, don't optimize. */
6042 if (mips_opts.nomove)
6045 /* We can't swap if the previous instruction's position is fixed. */
6046 if (history[0].fixed_p)
6049 /* If the previous previous insn was in a .set noreorder, we can't
6050 swap. Actually, the MIPS assembler will swap in this situation.
6051 However, gcc configured -with-gnu-as will generate code like
6059 in which we can not swap the bne and INSN. If gcc is not configured
6060 -with-gnu-as, it does not output the .set pseudo-ops. */
6061 if (history[1].noreorder_p)
6064 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6065 This means that the previous instruction was a 4-byte one anyhow. */
6066 if (mips_opts.mips16 && history[0].fixp[0])
6069 /* If the branch is itself the target of a branch, we can not swap.
6070 We cheat on this; all we check for is whether there is a label on
6071 this instruction. If there are any branches to anything other than
6072 a label, users must use .set noreorder. */
6073 if (seg_info (now_seg)->label_list)
6076 /* If the previous instruction is in a variant frag other than this
6077 branch's one, we cannot do the swap. This does not apply to
6078 MIPS16 code, which uses variant frags for different purposes. */
6079 if (!mips_opts.mips16
6081 && history[0].frag->fr_type == rs_machine_dependent)
6084 /* We do not swap with instructions that cannot architecturally
6085 be placed in a branch delay slot, such as SYNC or ERET. We
6086 also refrain from swapping with a trap instruction, since it
6087 complicates trap handlers to have the trap instruction be in
6089 prev_pinfo = history[0].insn_mo->pinfo;
6090 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6093 /* Check for conflicts between the branch and the instructions
6094 before the candidate delay slot. */
6095 if (nops_for_insn (0, history + 1, ip) > 0)
6098 /* Check for conflicts between the swapped sequence and the
6099 target of the branch. */
6100 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6103 /* If the branch reads a register that the previous
6104 instruction sets, we can not swap. */
6105 gpr_read = gpr_read_mask (ip);
6106 prev_gpr_write = gpr_write_mask (&history[0]);
6107 if (gpr_read & prev_gpr_write)
6110 /* If the branch writes a register that the previous
6111 instruction sets, we can not swap. */
6112 gpr_write = gpr_write_mask (ip);
6113 if (gpr_write & prev_gpr_write)
6116 /* If the branch writes a register that the previous
6117 instruction reads, we can not swap. */
6118 prev_gpr_read = gpr_read_mask (&history[0]);
6119 if (gpr_write & prev_gpr_read)
6122 /* If one instruction sets a condition code and the
6123 other one uses a condition code, we can not swap. */
6124 pinfo = ip->insn_mo->pinfo;
6125 if ((pinfo & INSN_READ_COND_CODE)
6126 && (prev_pinfo & INSN_WRITE_COND_CODE))
6128 if ((pinfo & INSN_WRITE_COND_CODE)
6129 && (prev_pinfo & INSN_READ_COND_CODE))
6132 /* If the previous instruction uses the PC, we can not swap. */
6133 prev_pinfo2 = history[0].insn_mo->pinfo2;
6134 if (prev_pinfo2 & INSN2_READ_PC)
6137 /* If the previous instruction has an incorrect size for a fixed
6138 branch delay slot in microMIPS mode, we cannot swap. */
6139 pinfo2 = ip->insn_mo->pinfo2;
6140 if (mips_opts.micromips
6141 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6142 && insn_length (history) != 2)
6144 if (mips_opts.micromips
6145 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6146 && insn_length (history) != 4)
6149 /* On R5900 short loops need to be fixed by inserting a nop in
6150 the branch delay slots.
6151 A short loop can be terminated too early. */
6152 if (mips_opts.arch == CPU_R5900
6153 /* Check if instruction has a parameter, ignore "j $31". */
6154 && (address_expr != NULL)
6155 /* Parameter must be 16 bit. */
6156 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6157 /* Branch to same segment. */
6158 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6159 /* Branch to same code fragment. */
6160 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6161 /* Can only calculate branch offset if value is known. */
6162 && symbol_constant_p(address_expr->X_add_symbol)
6163 /* Check if branch is really conditional. */
6164 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6165 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6166 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6169 /* Check if loop is shorter than 6 instructions including
6170 branch and delay slot. */
6171 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6178 /* When the loop includes branches or jumps,
6179 it is not a short loop. */
6180 for (i = 0; i < (distance / 4); i++)
6182 if ((history[i].cleared_p)
6183 || delayed_branch_p(&history[i]))
6191 /* Insert nop after branch to fix short loop. */
6200 /* Decide how we should add IP to the instruction stream.
6201 ADDRESS_EXPR is an operand of the instruction to be used with
6204 static enum append_method
6205 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6206 bfd_reloc_code_real_type *reloc_type)
6208 /* The relaxed version of a macro sequence must be inherently
6210 if (mips_relax.sequence == 2)
6213 /* We must not dabble with instructions in a ".set norerorder" block. */
6214 if (mips_opts.noreorder)
6217 /* Otherwise, it's our responsibility to fill branch delay slots. */
6218 if (delayed_branch_p (ip))
6220 if (!branch_likely_p (ip)
6221 && can_swap_branch_p (ip, address_expr, reloc_type))
6224 if (mips_opts.mips16
6225 && ISA_SUPPORTS_MIPS16E
6226 && gpr_read_mask (ip) != 0)
6227 return APPEND_ADD_COMPACT;
6229 return APPEND_ADD_WITH_NOP;
6235 /* IP is a MIPS16 instruction whose opcode we have just changed.
6236 Point IP->insn_mo to the new opcode's definition. */
6239 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6241 const struct mips_opcode *mo, *end;
6243 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6244 for (mo = ip->insn_mo; mo < end; mo++)
6245 if ((ip->insn_opcode & mo->mask) == mo->match)
6253 /* For microMIPS macros, we need to generate a local number label
6254 as the target of branches. */
6255 #define MICROMIPS_LABEL_CHAR '\037'
6256 static unsigned long micromips_target_label;
6257 static char micromips_target_name[32];
6260 micromips_label_name (void)
6262 char *p = micromips_target_name;
6263 char symbol_name_temporary[24];
6271 l = micromips_target_label;
6272 #ifdef LOCAL_LABEL_PREFIX
6273 *p++ = LOCAL_LABEL_PREFIX;
6276 *p++ = MICROMIPS_LABEL_CHAR;
6279 symbol_name_temporary[i++] = l % 10 + '0';
6284 *p++ = symbol_name_temporary[--i];
6287 return micromips_target_name;
6291 micromips_label_expr (expressionS *label_expr)
6293 label_expr->X_op = O_symbol;
6294 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6295 label_expr->X_add_number = 0;
6299 micromips_label_inc (void)
6301 micromips_target_label++;
6302 *micromips_target_name = '\0';
6306 micromips_add_label (void)
6310 s = colon (micromips_label_name ());
6311 micromips_label_inc ();
6312 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6315 /* If assembling microMIPS code, then return the microMIPS reloc
6316 corresponding to the requested one if any. Otherwise return
6317 the reloc unchanged. */
6319 static bfd_reloc_code_real_type
6320 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6322 static const bfd_reloc_code_real_type relocs[][2] =
6324 /* Keep sorted incrementally by the left-hand key. */
6325 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6326 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6327 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6328 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6329 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6330 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6331 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6332 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6333 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6334 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6335 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6336 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6337 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6338 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6339 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6340 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6341 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6342 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6343 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6344 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6345 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6346 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6347 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6348 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6349 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6350 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6351 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6353 bfd_reloc_code_real_type r;
6356 if (!mips_opts.micromips)
6358 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6364 return relocs[i][1];
6369 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6370 Return true on success, storing the resolved value in RESULT. */
6373 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6378 case BFD_RELOC_MIPS_HIGHEST:
6379 case BFD_RELOC_MICROMIPS_HIGHEST:
6380 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6383 case BFD_RELOC_MIPS_HIGHER:
6384 case BFD_RELOC_MICROMIPS_HIGHER:
6385 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6388 case BFD_RELOC_HI16_S:
6389 case BFD_RELOC_MICROMIPS_HI16_S:
6390 case BFD_RELOC_MIPS16_HI16_S:
6391 *result = ((operand + 0x8000) >> 16) & 0xffff;
6394 case BFD_RELOC_HI16:
6395 case BFD_RELOC_MICROMIPS_HI16:
6396 case BFD_RELOC_MIPS16_HI16:
6397 *result = (operand >> 16) & 0xffff;
6400 case BFD_RELOC_LO16:
6401 case BFD_RELOC_MICROMIPS_LO16:
6402 case BFD_RELOC_MIPS16_LO16:
6403 *result = operand & 0xffff;
6406 case BFD_RELOC_UNUSED:
6415 /* Output an instruction. IP is the instruction information.
6416 ADDRESS_EXPR is an operand of the instruction to be used with
6417 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6418 a macro expansion. */
6421 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6422 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6424 unsigned long prev_pinfo2, pinfo;
6425 bfd_boolean relaxed_branch = FALSE;
6426 enum append_method method;
6427 bfd_boolean relax32;
6430 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6431 fix_loongson2f (ip);
6433 file_ase_mips16 |= mips_opts.mips16;
6434 file_ase_micromips |= mips_opts.micromips;
6436 prev_pinfo2 = history[0].insn_mo->pinfo2;
6437 pinfo = ip->insn_mo->pinfo;
6439 if (mips_opts.micromips
6441 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6442 && micromips_insn_length (ip->insn_mo) != 2)
6443 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6444 && micromips_insn_length (ip->insn_mo) != 4)))
6445 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6446 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6448 if (address_expr == NULL)
6450 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6451 && reloc_type[1] == BFD_RELOC_UNUSED
6452 && reloc_type[2] == BFD_RELOC_UNUSED
6453 && address_expr->X_op == O_constant)
6455 switch (*reloc_type)
6457 case BFD_RELOC_MIPS_JMP:
6461 shift = mips_opts.micromips ? 1 : 2;
6462 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6463 as_bad (_("jump to misaligned address (0x%lx)"),
6464 (unsigned long) address_expr->X_add_number);
6465 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6471 case BFD_RELOC_MIPS16_JMP:
6472 if ((address_expr->X_add_number & 3) != 0)
6473 as_bad (_("jump to misaligned address (0x%lx)"),
6474 (unsigned long) address_expr->X_add_number);
6476 (((address_expr->X_add_number & 0x7c0000) << 3)
6477 | ((address_expr->X_add_number & 0xf800000) >> 7)
6478 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6482 case BFD_RELOC_16_PCREL_S2:
6486 shift = mips_opts.micromips ? 1 : 2;
6487 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6488 as_bad (_("branch to misaligned address (0x%lx)"),
6489 (unsigned long) address_expr->X_add_number);
6490 if (!mips_relax_branch)
6492 if ((address_expr->X_add_number + (1 << (shift + 15)))
6493 & ~((1 << (shift + 16)) - 1))
6494 as_bad (_("branch address range overflow (0x%lx)"),
6495 (unsigned long) address_expr->X_add_number);
6496 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6506 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6509 ip->insn_opcode |= value & 0xffff;
6517 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6519 /* There are a lot of optimizations we could do that we don't.
6520 In particular, we do not, in general, reorder instructions.
6521 If you use gcc with optimization, it will reorder
6522 instructions and generally do much more optimization then we
6523 do here; repeating all that work in the assembler would only
6524 benefit hand written assembly code, and does not seem worth
6526 int nops = (mips_optimize == 0
6527 ? nops_for_insn (0, history, NULL)
6528 : nops_for_insn_or_target (0, history, ip));
6532 unsigned long old_frag_offset;
6535 old_frag = frag_now;
6536 old_frag_offset = frag_now_fix ();
6538 for (i = 0; i < nops; i++)
6539 add_fixed_insn (NOP_INSN);
6540 insert_into_history (0, nops, NOP_INSN);
6544 listing_prev_line ();
6545 /* We may be at the start of a variant frag. In case we
6546 are, make sure there is enough space for the frag
6547 after the frags created by listing_prev_line. The
6548 argument to frag_grow here must be at least as large
6549 as the argument to all other calls to frag_grow in
6550 this file. We don't have to worry about being in the
6551 middle of a variant frag, because the variants insert
6552 all needed nop instructions themselves. */
6556 mips_move_text_labels ();
6558 #ifndef NO_ECOFF_DEBUGGING
6559 if (ECOFF_DEBUGGING)
6560 ecoff_fix_loc (old_frag, old_frag_offset);
6564 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6568 /* Work out how many nops in prev_nop_frag are needed by IP,
6569 ignoring hazards generated by the first prev_nop_frag_since
6571 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6572 gas_assert (nops <= prev_nop_frag_holds);
6574 /* Enforce NOPS as a minimum. */
6575 if (nops > prev_nop_frag_required)
6576 prev_nop_frag_required = nops;
6578 if (prev_nop_frag_holds == prev_nop_frag_required)
6580 /* Settle for the current number of nops. Update the history
6581 accordingly (for the benefit of any future .set reorder code). */
6582 prev_nop_frag = NULL;
6583 insert_into_history (prev_nop_frag_since,
6584 prev_nop_frag_holds, NOP_INSN);
6588 /* Allow this instruction to replace one of the nops that was
6589 tentatively added to prev_nop_frag. */
6590 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6591 prev_nop_frag_holds--;
6592 prev_nop_frag_since++;
6596 method = get_append_method (ip, address_expr, reloc_type);
6597 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6599 dwarf2_emit_insn (0);
6600 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6601 so "move" the instruction address accordingly.
6603 Also, it doesn't seem appropriate for the assembler to reorder .loc
6604 entries. If this instruction is a branch that we are going to swap
6605 with the previous instruction, the two instructions should be
6606 treated as a unit, and the debug information for both instructions
6607 should refer to the start of the branch sequence. Using the
6608 current position is certainly wrong when swapping a 32-bit branch
6609 and a 16-bit delay slot, since the current position would then be
6610 in the middle of a branch. */
6611 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6613 relax32 = (mips_relax_branch
6614 /* Don't try branch relaxation within .set nomacro, or within
6615 .set noat if we use $at for PIC computations. If it turns
6616 out that the branch was out-of-range, we'll get an error. */
6617 && !mips_opts.warn_about_macros
6618 && (mips_opts.at || mips_pic == NO_PIC)
6619 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6620 as they have no complementing branches. */
6621 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6623 if (!HAVE_CODE_COMPRESSION
6626 && *reloc_type == BFD_RELOC_16_PCREL_S2
6627 && delayed_branch_p (ip))
6629 relaxed_branch = TRUE;
6630 add_relaxed_insn (ip, (relaxed_branch_length
6632 uncond_branch_p (ip) ? -1
6633 : branch_likely_p (ip) ? 1
6637 uncond_branch_p (ip),
6638 branch_likely_p (ip),
6639 pinfo & INSN_WRITE_GPR_31,
6641 address_expr->X_add_symbol,
6642 address_expr->X_add_number);
6643 *reloc_type = BFD_RELOC_UNUSED;
6645 else if (mips_opts.micromips
6647 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6648 || *reloc_type > BFD_RELOC_UNUSED)
6649 && (delayed_branch_p (ip) || compact_branch_p (ip))
6650 /* Don't try branch relaxation when users specify
6651 16-bit/32-bit instructions. */
6652 && !forced_insn_length)
6654 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6655 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6656 int uncond = uncond_branch_p (ip) ? -1 : 0;
6657 int compact = compact_branch_p (ip);
6658 int al = pinfo & INSN_WRITE_GPR_31;
6661 gas_assert (address_expr != NULL);
6662 gas_assert (!mips_relax.sequence);
6664 relaxed_branch = TRUE;
6665 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6666 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6667 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6669 address_expr->X_add_symbol,
6670 address_expr->X_add_number);
6671 *reloc_type = BFD_RELOC_UNUSED;
6673 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6675 /* We need to set up a variant frag. */
6676 gas_assert (address_expr != NULL);
6677 add_relaxed_insn (ip, 4, 0,
6679 (*reloc_type - BFD_RELOC_UNUSED,
6680 forced_insn_length == 2, forced_insn_length == 4,
6681 delayed_branch_p (&history[0]),
6682 history[0].mips16_absolute_jump_p),
6683 make_expr_symbol (address_expr), 0);
6685 else if (mips_opts.mips16 && insn_length (ip) == 2)
6687 if (!delayed_branch_p (ip))
6688 /* Make sure there is enough room to swap this instruction with
6689 a following jump instruction. */
6691 add_fixed_insn (ip);
6695 if (mips_opts.mips16
6696 && mips_opts.noreorder
6697 && delayed_branch_p (&history[0]))
6698 as_warn (_("extended instruction in delay slot"));
6700 if (mips_relax.sequence)
6702 /* If we've reached the end of this frag, turn it into a variant
6703 frag and record the information for the instructions we've
6705 if (frag_room () < 4)
6706 relax_close_frag ();
6707 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6710 if (mips_relax.sequence != 2)
6712 if (mips_macro_warning.first_insn_sizes[0] == 0)
6713 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6714 mips_macro_warning.sizes[0] += insn_length (ip);
6715 mips_macro_warning.insns[0]++;
6717 if (mips_relax.sequence != 1)
6719 if (mips_macro_warning.first_insn_sizes[1] == 0)
6720 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6721 mips_macro_warning.sizes[1] += insn_length (ip);
6722 mips_macro_warning.insns[1]++;
6725 if (mips_opts.mips16)
6728 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6730 add_fixed_insn (ip);
6733 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6735 bfd_reloc_code_real_type final_type[3];
6736 reloc_howto_type *howto0;
6737 reloc_howto_type *howto;
6740 /* Perform any necessary conversion to microMIPS relocations
6741 and find out how many relocations there actually are. */
6742 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6743 final_type[i] = micromips_map_reloc (reloc_type[i]);
6745 /* In a compound relocation, it is the final (outermost)
6746 operator that determines the relocated field. */
6747 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6752 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6753 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6754 bfd_get_reloc_size (howto),
6756 howto0 && howto0->pc_relative,
6759 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6760 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6761 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6763 /* These relocations can have an addend that won't fit in
6764 4 octets for 64bit assembly. */
6766 && ! howto->partial_inplace
6767 && (reloc_type[0] == BFD_RELOC_16
6768 || reloc_type[0] == BFD_RELOC_32
6769 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6770 || reloc_type[0] == BFD_RELOC_GPREL16
6771 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6772 || reloc_type[0] == BFD_RELOC_GPREL32
6773 || reloc_type[0] == BFD_RELOC_64
6774 || reloc_type[0] == BFD_RELOC_CTOR
6775 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6776 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6777 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6778 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6779 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6780 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6781 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6782 || hi16_reloc_p (reloc_type[0])
6783 || lo16_reloc_p (reloc_type[0])))
6784 ip->fixp[0]->fx_no_overflow = 1;
6786 /* These relocations can have an addend that won't fit in 2 octets. */
6787 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6788 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6789 ip->fixp[0]->fx_no_overflow = 1;
6791 if (mips_relax.sequence)
6793 if (mips_relax.first_fixup == 0)
6794 mips_relax.first_fixup = ip->fixp[0];
6796 else if (reloc_needs_lo_p (*reloc_type))
6798 struct mips_hi_fixup *hi_fixup;
6800 /* Reuse the last entry if it already has a matching %lo. */
6801 hi_fixup = mips_hi_fixup_list;
6803 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6805 hi_fixup = ((struct mips_hi_fixup *)
6806 xmalloc (sizeof (struct mips_hi_fixup)));
6807 hi_fixup->next = mips_hi_fixup_list;
6808 mips_hi_fixup_list = hi_fixup;
6810 hi_fixup->fixp = ip->fixp[0];
6811 hi_fixup->seg = now_seg;
6814 /* Add fixups for the second and third relocations, if given.
6815 Note that the ABI allows the second relocation to be
6816 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6817 moment we only use RSS_UNDEF, but we could add support
6818 for the others if it ever becomes necessary. */
6819 for (i = 1; i < 3; i++)
6820 if (reloc_type[i] != BFD_RELOC_UNUSED)
6822 ip->fixp[i] = fix_new (ip->frag, ip->where,
6823 ip->fixp[0]->fx_size, NULL, 0,
6824 FALSE, final_type[i]);
6826 /* Use fx_tcbit to mark compound relocs. */
6827 ip->fixp[0]->fx_tcbit = 1;
6828 ip->fixp[i]->fx_tcbit = 1;
6833 /* Update the register mask information. */
6834 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6835 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6840 insert_into_history (0, 1, ip);
6843 case APPEND_ADD_WITH_NOP:
6845 struct mips_cl_insn *nop;
6847 insert_into_history (0, 1, ip);
6848 nop = get_delay_slot_nop (ip);
6849 add_fixed_insn (nop);
6850 insert_into_history (0, 1, nop);
6851 if (mips_relax.sequence)
6852 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6856 case APPEND_ADD_COMPACT:
6857 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6858 gas_assert (mips_opts.mips16);
6859 ip->insn_opcode |= 0x0080;
6860 find_altered_mips16_opcode (ip);
6862 insert_into_history (0, 1, ip);
6867 struct mips_cl_insn delay = history[0];
6868 if (mips_opts.mips16)
6870 know (delay.frag == ip->frag);
6871 move_insn (ip, delay.frag, delay.where);
6872 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6874 else if (relaxed_branch || delay.frag != ip->frag)
6876 /* Add the delay slot instruction to the end of the
6877 current frag and shrink the fixed part of the
6878 original frag. If the branch occupies the tail of
6879 the latter, move it backwards to cover the gap. */
6880 delay.frag->fr_fix -= branch_disp;
6881 if (delay.frag == ip->frag)
6882 move_insn (ip, ip->frag, ip->where - branch_disp);
6883 add_fixed_insn (&delay);
6887 move_insn (&delay, ip->frag,
6888 ip->where - branch_disp + insn_length (ip));
6889 move_insn (ip, history[0].frag, history[0].where);
6893 insert_into_history (0, 1, &delay);
6898 /* If we have just completed an unconditional branch, clear the history. */
6899 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6900 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6904 mips_no_prev_insn ();
6906 for (i = 0; i < ARRAY_SIZE (history); i++)
6907 history[i].cleared_p = 1;
6910 /* We need to emit a label at the end of branch-likely macros. */
6911 if (emit_branch_likely_macro)
6913 emit_branch_likely_macro = FALSE;
6914 micromips_add_label ();
6917 /* We just output an insn, so the next one doesn't have a label. */
6918 mips_clear_insn_labels ();
6921 /* Forget that there was any previous instruction or label.
6922 When BRANCH is true, the branch history is also flushed. */
6925 mips_no_prev_insn (void)
6927 prev_nop_frag = NULL;
6928 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6929 mips_clear_insn_labels ();
6932 /* This function must be called before we emit something other than
6933 instructions. It is like mips_no_prev_insn except that it inserts
6934 any NOPS that might be needed by previous instructions. */
6937 mips_emit_delays (void)
6939 if (! mips_opts.noreorder)
6941 int nops = nops_for_insn (0, history, NULL);
6945 add_fixed_insn (NOP_INSN);
6946 mips_move_text_labels ();
6949 mips_no_prev_insn ();
6952 /* Start a (possibly nested) noreorder block. */
6955 start_noreorder (void)
6957 if (mips_opts.noreorder == 0)
6962 /* None of the instructions before the .set noreorder can be moved. */
6963 for (i = 0; i < ARRAY_SIZE (history); i++)
6964 history[i].fixed_p = 1;
6966 /* Insert any nops that might be needed between the .set noreorder
6967 block and the previous instructions. We will later remove any
6968 nops that turn out not to be needed. */
6969 nops = nops_for_insn (0, history, NULL);
6972 if (mips_optimize != 0)
6974 /* Record the frag which holds the nop instructions, so
6975 that we can remove them if we don't need them. */
6976 frag_grow (nops * NOP_INSN_SIZE);
6977 prev_nop_frag = frag_now;
6978 prev_nop_frag_holds = nops;
6979 prev_nop_frag_required = 0;
6980 prev_nop_frag_since = 0;
6983 for (; nops > 0; --nops)
6984 add_fixed_insn (NOP_INSN);
6986 /* Move on to a new frag, so that it is safe to simply
6987 decrease the size of prev_nop_frag. */
6988 frag_wane (frag_now);
6990 mips_move_text_labels ();
6992 mips_mark_labels ();
6993 mips_clear_insn_labels ();
6995 mips_opts.noreorder++;
6996 mips_any_noreorder = 1;
6999 /* End a nested noreorder block. */
7002 end_noreorder (void)
7004 mips_opts.noreorder--;
7005 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7007 /* Commit to inserting prev_nop_frag_required nops and go back to
7008 handling nop insertion the .set reorder way. */
7009 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7011 insert_into_history (prev_nop_frag_since,
7012 prev_nop_frag_required, NOP_INSN);
7013 prev_nop_frag = NULL;
7017 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7018 higher bits unset. */
7021 normalize_constant_expr (expressionS *ex)
7023 if (ex->X_op == O_constant
7024 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7025 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7029 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7030 all higher bits unset. */
7033 normalize_address_expr (expressionS *ex)
7035 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7036 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7037 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7038 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7042 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7043 Return true if the match was successful.
7045 OPCODE_EXTRA is a value that should be ORed into the opcode
7046 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7047 there are more alternatives after OPCODE and SOFT_MATCH is
7048 as for mips_arg_info. */
7051 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7052 struct mips_operand_token *tokens, unsigned int opcode_extra,
7053 bfd_boolean more_alts)
7056 struct mips_arg_info arg;
7057 const struct mips_operand *operand;
7060 imm_expr.X_op = O_absent;
7061 imm2_expr.X_op = O_absent;
7062 offset_expr.X_op = O_absent;
7063 offset_reloc[0] = BFD_RELOC_UNUSED;
7064 offset_reloc[1] = BFD_RELOC_UNUSED;
7065 offset_reloc[2] = BFD_RELOC_UNUSED;
7067 create_insn (insn, opcode);
7068 insn->insn_opcode |= opcode_extra;
7069 memset (&arg, 0, sizeof (arg));
7073 arg.last_regno = ILLEGAL_REG;
7074 arg.dest_regno = ILLEGAL_REG;
7075 for (args = opcode->args;; ++args)
7077 if (arg.token->type == OT_END)
7079 /* Handle unary instructions in which only one operand is given.
7080 The source is then the same as the destination. */
7081 if (arg.opnum == 1 && *args == ',')
7083 operand = (mips_opts.micromips
7084 ? decode_micromips_operand (args + 1)
7085 : decode_mips_operand (args + 1));
7086 if (operand && mips_optional_operand_p (operand))
7094 /* Treat elided base registers as $0. */
7095 if (strcmp (args, "(b)") == 0)
7103 /* The register suffix is optional. */
7108 /* Fail the match if there were too few operands. */
7112 /* Successful match. */
7113 clear_insn_error ();
7114 if (arg.dest_regno == arg.last_regno
7115 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7119 (0, _("Source and destination must be different"));
7120 else if (arg.last_regno == 31)
7122 (0, _("A destination register must be supplied"));
7124 check_completed_insn (&arg);
7128 /* Fail the match if the line has too many operands. */
7132 /* Handle characters that need to match exactly. */
7133 if (*args == '(' || *args == ')' || *args == ',')
7135 if (match_char (&arg, *args))
7142 if (arg.token->type == OT_DOUBLE_CHAR
7143 && arg.token->u.ch == *args)
7151 /* Handle special macro operands. Work out the properties of
7154 arg.lax_max = FALSE;
7161 /* "+I" is like "I", except that imm2_expr is used. */
7162 if (!match_const_int (&arg, &imm2_expr.X_add_number))
7164 imm2_expr.X_op = O_constant;
7165 if (HAVE_32BIT_GPRS)
7166 normalize_constant_expr (&imm2_expr);
7171 *offset_reloc = BFD_RELOC_MIPS_JMP;
7177 if (!match_const_int (&arg, &imm_expr.X_add_number))
7179 imm_expr.X_op = O_constant;
7180 if (HAVE_32BIT_GPRS)
7181 normalize_constant_expr (&imm_expr);
7185 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7187 /* Assume that the offset has been elided and that what
7188 we saw was a base register. The match will fail later
7189 if that assumption turns out to be wrong. */
7190 offset_expr.X_op = O_constant;
7191 offset_expr.X_add_number = 0;
7195 if (!match_expression (&arg, &offset_expr, offset_reloc))
7197 normalize_address_expr (&offset_expr);
7202 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7208 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7214 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7220 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7225 /* ??? This is the traditional behavior, but is flaky if
7226 there are alternative versions of the same instruction
7227 for different subarchitectures. The next alternative
7228 might not be suitable. */
7230 /* For compatibility with older assemblers, we accept
7231 0x8000-0xffff as signed 16-bit numbers when only
7232 signed numbers are allowed. */
7233 arg.lax_max = !more_alts;
7235 /* Only accept non-constant operands if this is the
7236 final alternative. Later alternatives might include
7237 a macro implementation. */
7238 arg.allow_nonconst = !more_alts;
7242 /* There are no macro implementations for out-of-range values. */
7243 arg.allow_nonconst = TRUE;
7247 /* There should always be a macro implementation. */
7248 arg.allow_nonconst = FALSE;
7252 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7256 *offset_reloc = BFD_RELOC_MIPS_JMP;
7260 gas_assert (mips_opts.micromips);
7266 if (!forced_insn_length)
7267 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7269 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7271 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7277 operand = (mips_opts.micromips
7278 ? decode_micromips_operand (args)
7279 : decode_mips_operand (args));
7283 /* Skip prefixes. */
7284 if (*args == '+' || *args == 'm')
7287 if (mips_optional_operand_p (operand)
7289 && (arg.token[0].type != OT_REG
7290 || arg.token[1].type == OT_END))
7292 /* Assume that the register has been elided and is the
7293 same as the first operand. */
7298 if (!match_operand (&arg, operand))
7303 /* Like match_insn, but for MIPS16. */
7306 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7307 struct mips_operand_token *tokens)
7310 const struct mips_operand *operand;
7311 const struct mips_operand *ext_operand;
7312 struct mips_arg_info arg;
7315 create_insn (insn, opcode);
7316 imm_expr.X_op = O_absent;
7317 imm2_expr.X_op = O_absent;
7318 offset_expr.X_op = O_absent;
7319 offset_reloc[0] = BFD_RELOC_UNUSED;
7320 offset_reloc[1] = BFD_RELOC_UNUSED;
7321 offset_reloc[2] = BFD_RELOC_UNUSED;
7324 memset (&arg, 0, sizeof (arg));
7328 arg.last_regno = ILLEGAL_REG;
7329 arg.dest_regno = ILLEGAL_REG;
7331 for (args = opcode->args;; ++args)
7335 if (arg.token->type == OT_END)
7339 /* Handle unary instructions in which only one operand is given.
7340 The source is then the same as the destination. */
7341 if (arg.opnum == 1 && *args == ',')
7343 operand = decode_mips16_operand (args[1], FALSE);
7344 if (operand && mips_optional_operand_p (operand))
7352 /* Fail the match if there were too few operands. */
7356 /* Successful match. Stuff the immediate value in now, if
7358 clear_insn_error ();
7359 if (opcode->pinfo == INSN_MACRO)
7361 gas_assert (relax_char == 0 || relax_char == 'p');
7362 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7365 && offset_expr.X_op == O_constant
7366 && calculate_reloc (*offset_reloc,
7367 offset_expr.X_add_number,
7370 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7371 forced_insn_length, &insn->insn_opcode);
7372 offset_expr.X_op = O_absent;
7373 *offset_reloc = BFD_RELOC_UNUSED;
7375 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7377 if (forced_insn_length == 2)
7378 set_insn_error (0, _("invalid unextended operand value"));
7379 forced_insn_length = 4;
7380 insn->insn_opcode |= MIPS16_EXTEND;
7382 else if (relax_char)
7383 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7385 check_completed_insn (&arg);
7389 /* Fail the match if the line has too many operands. */
7393 /* Handle characters that need to match exactly. */
7394 if (*args == '(' || *args == ')' || *args == ',')
7396 if (match_char (&arg, *args))
7414 if (!match_const_int (&arg, &imm_expr.X_add_number))
7416 imm_expr.X_op = O_constant;
7417 if (HAVE_32BIT_GPRS)
7418 normalize_constant_expr (&imm_expr);
7423 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7424 insn->insn_opcode <<= 16;
7428 operand = decode_mips16_operand (c, FALSE);
7432 /* '6' is a special case. It is used for BREAK and SDBBP,
7433 whose operands are only meaningful to the software that decodes
7434 them. This means that there is no architectural reason why
7435 they cannot be prefixed by EXTEND, but in practice,
7436 exception handlers will only look at the instruction
7437 itself. We therefore allow '6' to be extended when
7438 disassembling but not when assembling. */
7439 if (operand->type != OP_PCREL && c != '6')
7441 ext_operand = decode_mips16_operand (c, TRUE);
7442 if (operand != ext_operand)
7444 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7446 offset_expr.X_op = O_constant;
7447 offset_expr.X_add_number = 0;
7452 /* We need the OT_INTEGER check because some MIPS16
7453 immediate variants are listed before the register ones. */
7454 if (arg.token->type != OT_INTEGER
7455 || !match_expression (&arg, &offset_expr, offset_reloc))
7458 /* '8' is used for SLTI(U) and has traditionally not
7459 been allowed to take relocation operators. */
7460 if (offset_reloc[0] != BFD_RELOC_UNUSED
7461 && (ext_operand->size != 16 || c == '8'))
7469 if (mips_optional_operand_p (operand)
7471 && (arg.token[0].type != OT_REG
7472 || arg.token[1].type == OT_END))
7474 /* Assume that the register has been elided and is the
7475 same as the first operand. */
7480 if (!match_operand (&arg, operand))
7485 /* Set up global variables for the start of a new macro. */
7490 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
7491 memset (&mips_macro_warning.first_insn_sizes, 0,
7492 sizeof (mips_macro_warning.first_insn_sizes));
7493 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
7494 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
7495 && delayed_branch_p (&history[0]));
7496 switch (history[0].insn_mo->pinfo2
7497 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7499 case INSN2_BRANCH_DELAY_32BIT:
7500 mips_macro_warning.delay_slot_length = 4;
7502 case INSN2_BRANCH_DELAY_16BIT:
7503 mips_macro_warning.delay_slot_length = 2;
7506 mips_macro_warning.delay_slot_length = 0;
7509 mips_macro_warning.first_frag = NULL;
7512 /* Given that a macro is longer than one instruction or of the wrong size,
7513 return the appropriate warning for it. Return null if no warning is
7514 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7515 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7516 and RELAX_NOMACRO. */
7519 macro_warning (relax_substateT subtype)
7521 if (subtype & RELAX_DELAY_SLOT)
7522 return _("Macro instruction expanded into multiple instructions"
7523 " in a branch delay slot");
7524 else if (subtype & RELAX_NOMACRO)
7525 return _("Macro instruction expanded into multiple instructions");
7526 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7527 | RELAX_DELAY_SLOT_SIZE_SECOND))
7528 return ((subtype & RELAX_DELAY_SLOT_16BIT)
7529 ? _("Macro instruction expanded into a wrong size instruction"
7530 " in a 16-bit branch delay slot")
7531 : _("Macro instruction expanded into a wrong size instruction"
7532 " in a 32-bit branch delay slot"));
7537 /* Finish up a macro. Emit warnings as appropriate. */
7542 /* Relaxation warning flags. */
7543 relax_substateT subtype = 0;
7545 /* Check delay slot size requirements. */
7546 if (mips_macro_warning.delay_slot_length == 2)
7547 subtype |= RELAX_DELAY_SLOT_16BIT;
7548 if (mips_macro_warning.delay_slot_length != 0)
7550 if (mips_macro_warning.delay_slot_length
7551 != mips_macro_warning.first_insn_sizes[0])
7552 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7553 if (mips_macro_warning.delay_slot_length
7554 != mips_macro_warning.first_insn_sizes[1])
7555 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7558 /* Check instruction count requirements. */
7559 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7561 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
7562 subtype |= RELAX_SECOND_LONGER;
7563 if (mips_opts.warn_about_macros)
7564 subtype |= RELAX_NOMACRO;
7565 if (mips_macro_warning.delay_slot_p)
7566 subtype |= RELAX_DELAY_SLOT;
7569 /* If both alternatives fail to fill a delay slot correctly,
7570 emit the warning now. */
7571 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7572 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7577 s = subtype & (RELAX_DELAY_SLOT_16BIT
7578 | RELAX_DELAY_SLOT_SIZE_FIRST
7579 | RELAX_DELAY_SLOT_SIZE_SECOND);
7580 msg = macro_warning (s);
7582 as_warn ("%s", msg);
7586 /* If both implementations are longer than 1 instruction, then emit the
7588 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7593 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7594 msg = macro_warning (s);
7596 as_warn ("%s", msg);
7600 /* If any flags still set, then one implementation might need a warning
7601 and the other either will need one of a different kind or none at all.
7602 Pass any remaining flags over to relaxation. */
7603 if (mips_macro_warning.first_frag != NULL)
7604 mips_macro_warning.first_frag->fr_subtype |= subtype;
7607 /* Instruction operand formats used in macros that vary between
7608 standard MIPS and microMIPS code. */
7610 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
7611 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7612 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7613 static const char * const lui_fmt[2] = { "t,u", "s,u" };
7614 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
7615 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
7616 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7617 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7619 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7620 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7621 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7622 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7623 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7624 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7625 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7626 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7628 /* Read a macro's relocation codes from *ARGS and store them in *R.
7629 The first argument in *ARGS will be either the code for a single
7630 relocation or -1 followed by the three codes that make up a
7631 composite relocation. */
7634 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7638 next = va_arg (*args, int);
7640 r[0] = (bfd_reloc_code_real_type) next;
7643 for (i = 0; i < 3; i++)
7644 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7645 /* This function is only used for 16-bit relocation fields.
7646 To make the macro code simpler, treat an unrelocated value
7647 in the same way as BFD_RELOC_LO16. */
7648 if (r[0] == BFD_RELOC_UNUSED)
7649 r[0] = BFD_RELOC_LO16;
7653 /* Build an instruction created by a macro expansion. This is passed
7654 a pointer to the count of instructions created so far, an
7655 expression, the name of the instruction to build, an operand format
7656 string, and corresponding arguments. */
7659 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
7661 const struct mips_opcode *mo = NULL;
7662 bfd_reloc_code_real_type r[3];
7663 const struct mips_opcode *amo;
7664 const struct mips_operand *operand;
7665 struct hash_control *hash;
7666 struct mips_cl_insn insn;
7670 va_start (args, fmt);
7672 if (mips_opts.mips16)
7674 mips16_macro_build (ep, name, fmt, &args);
7679 r[0] = BFD_RELOC_UNUSED;
7680 r[1] = BFD_RELOC_UNUSED;
7681 r[2] = BFD_RELOC_UNUSED;
7682 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7683 amo = (struct mips_opcode *) hash_find (hash, name);
7685 gas_assert (strcmp (name, amo->name) == 0);
7689 /* Search until we get a match for NAME. It is assumed here that
7690 macros will never generate MDMX, MIPS-3D, or MT instructions.
7691 We try to match an instruction that fulfils the branch delay
7692 slot instruction length requirement (if any) of the previous
7693 instruction. While doing this we record the first instruction
7694 seen that matches all the other conditions and use it anyway
7695 if the requirement cannot be met; we will issue an appropriate
7696 warning later on. */
7697 if (strcmp (fmt, amo->args) == 0
7698 && amo->pinfo != INSN_MACRO
7699 && is_opcode_valid (amo)
7700 && is_size_valid (amo))
7702 if (is_delay_slot_valid (amo))
7712 gas_assert (amo->name);
7714 while (strcmp (name, amo->name) == 0);
7717 create_insn (&insn, mo);
7730 macro_read_relocs (&args, r);
7731 gas_assert (*r == BFD_RELOC_GPREL16
7732 || *r == BFD_RELOC_MIPS_HIGHER
7733 || *r == BFD_RELOC_HI16_S
7734 || *r == BFD_RELOC_LO16
7735 || *r == BFD_RELOC_MIPS_GOT_OFST);
7739 macro_read_relocs (&args, r);
7743 macro_read_relocs (&args, r);
7744 gas_assert (ep != NULL
7745 && (ep->X_op == O_constant
7746 || (ep->X_op == O_symbol
7747 && (*r == BFD_RELOC_MIPS_HIGHEST
7748 || *r == BFD_RELOC_HI16_S
7749 || *r == BFD_RELOC_HI16
7750 || *r == BFD_RELOC_GPREL16
7751 || *r == BFD_RELOC_MIPS_GOT_HI16
7752 || *r == BFD_RELOC_MIPS_CALL_HI16))));
7756 gas_assert (ep != NULL);
7759 * This allows macro() to pass an immediate expression for
7760 * creating short branches without creating a symbol.
7762 * We don't allow branch relaxation for these branches, as
7763 * they should only appear in ".set nomacro" anyway.
7765 if (ep->X_op == O_constant)
7767 /* For microMIPS we always use relocations for branches.
7768 So we should not resolve immediate values. */
7769 gas_assert (!mips_opts.micromips);
7771 if ((ep->X_add_number & 3) != 0)
7772 as_bad (_("branch to misaligned address (0x%lx)"),
7773 (unsigned long) ep->X_add_number);
7774 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7775 as_bad (_("branch address range overflow (0x%lx)"),
7776 (unsigned long) ep->X_add_number);
7777 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7781 *r = BFD_RELOC_16_PCREL_S2;
7785 gas_assert (ep != NULL);
7786 *r = BFD_RELOC_MIPS_JMP;
7790 operand = (mips_opts.micromips
7791 ? decode_micromips_operand (fmt)
7792 : decode_mips_operand (fmt));
7796 uval = va_arg (args, int);
7797 if (operand->type == OP_CLO_CLZ_DEST)
7798 uval |= (uval << 5);
7799 insn_insert_operand (&insn, operand, uval);
7801 if (*fmt == '+' || *fmt == 'm')
7807 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7809 append_insn (&insn, ep, r, TRUE);
7813 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
7816 struct mips_opcode *mo;
7817 struct mips_cl_insn insn;
7818 const struct mips_operand *operand;
7819 bfd_reloc_code_real_type r[3]
7820 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
7822 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
7824 gas_assert (strcmp (name, mo->name) == 0);
7826 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7829 gas_assert (mo->name);
7830 gas_assert (strcmp (name, mo->name) == 0);
7833 create_insn (&insn, mo);
7871 gas_assert (ep != NULL);
7873 if (ep->X_op != O_constant)
7874 *r = (int) BFD_RELOC_UNUSED + c;
7875 else if (calculate_reloc (*r, ep->X_add_number, &value))
7877 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
7879 *r = BFD_RELOC_UNUSED;
7885 operand = decode_mips16_operand (c, FALSE);
7889 insn_insert_operand (&insn, operand, va_arg (*args, int));
7894 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7896 append_insn (&insn, ep, r, TRUE);
7900 * Generate a "jalr" instruction with a relocation hint to the called
7901 * function. This occurs in NewABI PIC code.
7904 macro_build_jalr (expressionS *ep, int cprestore)
7906 static const bfd_reloc_code_real_type jalr_relocs[2]
7907 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7908 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7912 if (MIPS_JALR_HINT_P (ep))
7917 if (mips_opts.micromips)
7919 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7920 ? "jalr" : "jalrs");
7921 if (MIPS_JALR_HINT_P (ep)
7923 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7924 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7926 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7929 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7930 if (MIPS_JALR_HINT_P (ep))
7931 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7935 * Generate a "lui" instruction.
7938 macro_build_lui (expressionS *ep, int regnum)
7940 gas_assert (! mips_opts.mips16);
7942 if (ep->X_op != O_constant)
7944 gas_assert (ep->X_op == O_symbol);
7945 /* _gp_disp is a special case, used from s_cpload.
7946 __gnu_local_gp is used if mips_no_shared. */
7947 gas_assert (mips_pic == NO_PIC
7949 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7950 || (! mips_in_shared
7951 && strcmp (S_GET_NAME (ep->X_add_symbol),
7952 "__gnu_local_gp") == 0));
7955 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7958 /* Generate a sequence of instructions to do a load or store from a constant
7959 offset off of a base register (breg) into/from a target register (treg),
7960 using AT if necessary. */
7962 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7963 int treg, int breg, int dbl)
7965 gas_assert (ep->X_op == O_constant);
7967 /* Sign-extending 32-bit constants makes their handling easier. */
7969 normalize_constant_expr (ep);
7971 /* Right now, this routine can only handle signed 32-bit constants. */
7972 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7973 as_warn (_("operand overflow"));
7975 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7977 /* Signed 16-bit offset will fit in the op. Easy! */
7978 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7982 /* 32-bit offset, need multiple instructions and AT, like:
7983 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7984 addu $tempreg,$tempreg,$breg
7985 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7986 to handle the complete offset. */
7987 macro_build_lui (ep, AT);
7988 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7989 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7992 as_bad (_("Macro used $at after \".set noat\""));
7997 * Generates code to set the $at register to true (one)
7998 * if reg is less than the immediate expression.
8001 set_at (int reg, int unsignedp)
8003 if (imm_expr.X_op == O_constant
8004 && imm_expr.X_add_number >= -0x8000
8005 && imm_expr.X_add_number < 0x8000)
8006 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8007 AT, reg, BFD_RELOC_LO16);
8010 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8011 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8015 /* Count the leading zeroes by performing a binary chop. This is a
8016 bulky bit of source, but performance is a LOT better for the
8017 majority of values than a simple loop to count the bits:
8018 for (lcnt = 0; (lcnt < 32); lcnt++)
8019 if ((v) & (1 << (31 - lcnt)))
8021 However it is not code size friendly, and the gain will drop a bit
8022 on certain cached systems.
8024 #define COUNT_TOP_ZEROES(v) \
8025 (((v) & ~0xffff) == 0 \
8026 ? ((v) & ~0xff) == 0 \
8027 ? ((v) & ~0xf) == 0 \
8028 ? ((v) & ~0x3) == 0 \
8029 ? ((v) & ~0x1) == 0 \
8034 : ((v) & ~0x7) == 0 \
8037 : ((v) & ~0x3f) == 0 \
8038 ? ((v) & ~0x1f) == 0 \
8041 : ((v) & ~0x7f) == 0 \
8044 : ((v) & ~0xfff) == 0 \
8045 ? ((v) & ~0x3ff) == 0 \
8046 ? ((v) & ~0x1ff) == 0 \
8049 : ((v) & ~0x7ff) == 0 \
8052 : ((v) & ~0x3fff) == 0 \
8053 ? ((v) & ~0x1fff) == 0 \
8056 : ((v) & ~0x7fff) == 0 \
8059 : ((v) & ~0xffffff) == 0 \
8060 ? ((v) & ~0xfffff) == 0 \
8061 ? ((v) & ~0x3ffff) == 0 \
8062 ? ((v) & ~0x1ffff) == 0 \
8065 : ((v) & ~0x7ffff) == 0 \
8068 : ((v) & ~0x3fffff) == 0 \
8069 ? ((v) & ~0x1fffff) == 0 \
8072 : ((v) & ~0x7fffff) == 0 \
8075 : ((v) & ~0xfffffff) == 0 \
8076 ? ((v) & ~0x3ffffff) == 0 \
8077 ? ((v) & ~0x1ffffff) == 0 \
8080 : ((v) & ~0x7ffffff) == 0 \
8083 : ((v) & ~0x3fffffff) == 0 \
8084 ? ((v) & ~0x1fffffff) == 0 \
8087 : ((v) & ~0x7fffffff) == 0 \
8092 * This routine generates the least number of instructions necessary to load
8093 * an absolute expression value into a register.
8096 load_register (int reg, expressionS *ep, int dbl)
8099 expressionS hi32, lo32;
8101 if (ep->X_op != O_big)
8103 gas_assert (ep->X_op == O_constant);
8105 /* Sign-extending 32-bit constants makes their handling easier. */
8107 normalize_constant_expr (ep);
8109 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8111 /* We can handle 16 bit signed values with an addiu to
8112 $zero. No need to ever use daddiu here, since $zero and
8113 the result are always correct in 32 bit mode. */
8114 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8117 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8119 /* We can handle 16 bit unsigned values with an ori to
8121 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8124 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8126 /* 32 bit values require an lui. */
8127 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8128 if ((ep->X_add_number & 0xffff) != 0)
8129 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8134 /* The value is larger than 32 bits. */
8136 if (!dbl || HAVE_32BIT_GPRS)
8140 sprintf_vma (value, ep->X_add_number);
8141 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8142 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8146 if (ep->X_op != O_big)
8149 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8150 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8151 hi32.X_add_number &= 0xffffffff;
8153 lo32.X_add_number &= 0xffffffff;
8157 gas_assert (ep->X_add_number > 2);
8158 if (ep->X_add_number == 3)
8159 generic_bignum[3] = 0;
8160 else if (ep->X_add_number > 4)
8161 as_bad (_("Number larger than 64 bits"));
8162 lo32.X_op = O_constant;
8163 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8164 hi32.X_op = O_constant;
8165 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8168 if (hi32.X_add_number == 0)
8173 unsigned long hi, lo;
8175 if (hi32.X_add_number == (offsetT) 0xffffffff)
8177 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8179 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8182 if (lo32.X_add_number & 0x80000000)
8184 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8185 if (lo32.X_add_number & 0xffff)
8186 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8191 /* Check for 16bit shifted constant. We know that hi32 is
8192 non-zero, so start the mask on the first bit of the hi32
8197 unsigned long himask, lomask;
8201 himask = 0xffff >> (32 - shift);
8202 lomask = (0xffff << shift) & 0xffffffff;
8206 himask = 0xffff << (shift - 32);
8209 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8210 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8214 tmp.X_op = O_constant;
8216 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8217 | (lo32.X_add_number >> shift));
8219 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8220 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8221 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8222 reg, reg, (shift >= 32) ? shift - 32 : shift);
8227 while (shift <= (64 - 16));
8229 /* Find the bit number of the lowest one bit, and store the
8230 shifted value in hi/lo. */
8231 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8232 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8236 while ((lo & 1) == 0)
8241 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8247 while ((hi & 1) == 0)
8256 /* Optimize if the shifted value is a (power of 2) - 1. */
8257 if ((hi == 0 && ((lo + 1) & lo) == 0)
8258 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
8260 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
8265 /* This instruction will set the register to be all
8267 tmp.X_op = O_constant;
8268 tmp.X_add_number = (offsetT) -1;
8269 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8273 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8274 reg, reg, (bit >= 32) ? bit - 32 : bit);
8276 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
8277 reg, reg, (shift >= 32) ? shift - 32 : shift);
8282 /* Sign extend hi32 before calling load_register, because we can
8283 generally get better code when we load a sign extended value. */
8284 if ((hi32.X_add_number & 0x80000000) != 0)
8285 hi32.X_add_number |= ~(offsetT) 0xffffffff;
8286 load_register (reg, &hi32, 0);
8289 if ((lo32.X_add_number & 0xffff0000) == 0)
8293 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
8301 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
8303 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8304 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
8310 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
8314 mid16.X_add_number >>= 16;
8315 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8316 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8319 if ((lo32.X_add_number & 0xffff) != 0)
8320 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8324 load_delay_nop (void)
8326 if (!gpr_interlocks)
8327 macro_build (NULL, "nop", "");
8330 /* Load an address into a register. */
8333 load_address (int reg, expressionS *ep, int *used_at)
8335 if (ep->X_op != O_constant
8336 && ep->X_op != O_symbol)
8338 as_bad (_("expression too complex"));
8339 ep->X_op = O_constant;
8342 if (ep->X_op == O_constant)
8344 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
8348 if (mips_pic == NO_PIC)
8350 /* If this is a reference to a GP relative symbol, we want
8351 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8353 lui $reg,<sym> (BFD_RELOC_HI16_S)
8354 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8355 If we have an addend, we always use the latter form.
8357 With 64bit address space and a usable $at we want
8358 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8359 lui $at,<sym> (BFD_RELOC_HI16_S)
8360 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8361 daddiu $at,<sym> (BFD_RELOC_LO16)
8365 If $at is already in use, we use a path which is suboptimal
8366 on superscalar processors.
8367 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8368 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8370 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8372 daddiu $reg,<sym> (BFD_RELOC_LO16)
8374 For GP relative symbols in 64bit address space we can use
8375 the same sequence as in 32bit address space. */
8376 if (HAVE_64BIT_SYMBOLS)
8378 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8379 && !nopic_need_relax (ep->X_add_symbol, 1))
8381 relax_start (ep->X_add_symbol);
8382 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8383 mips_gp_register, BFD_RELOC_GPREL16);
8387 if (*used_at == 0 && mips_opts.at)
8389 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8390 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
8391 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8392 BFD_RELOC_MIPS_HIGHER);
8393 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
8394 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
8395 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
8400 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8401 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8402 BFD_RELOC_MIPS_HIGHER);
8403 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8404 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
8405 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8406 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
8409 if (mips_relax.sequence)
8414 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8415 && !nopic_need_relax (ep->X_add_symbol, 1))
8417 relax_start (ep->X_add_symbol);
8418 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8419 mips_gp_register, BFD_RELOC_GPREL16);
8422 macro_build_lui (ep, reg);
8423 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8424 reg, reg, BFD_RELOC_LO16);
8425 if (mips_relax.sequence)
8429 else if (!mips_big_got)
8433 /* If this is a reference to an external symbol, we want
8434 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8436 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8438 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8439 If there is a constant, it must be added in after.
8441 If we have NewABI, we want
8442 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8443 unless we're referencing a global symbol with a non-zero
8444 offset, in which case cst must be added separately. */
8447 if (ep->X_add_number)
8449 ex.X_add_number = ep->X_add_number;
8450 ep->X_add_number = 0;
8451 relax_start (ep->X_add_symbol);
8452 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8453 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8454 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8455 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8456 ex.X_op = O_constant;
8457 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8458 reg, reg, BFD_RELOC_LO16);
8459 ep->X_add_number = ex.X_add_number;
8462 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8463 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8464 if (mips_relax.sequence)
8469 ex.X_add_number = ep->X_add_number;
8470 ep->X_add_number = 0;
8471 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8472 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8474 relax_start (ep->X_add_symbol);
8476 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8480 if (ex.X_add_number != 0)
8482 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8483 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8484 ex.X_op = O_constant;
8485 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8486 reg, reg, BFD_RELOC_LO16);
8490 else if (mips_big_got)
8494 /* This is the large GOT case. If this is a reference to an
8495 external symbol, we want
8496 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8498 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8500 Otherwise, for a reference to a local symbol in old ABI, we want
8501 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8503 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8504 If there is a constant, it must be added in after.
8506 In the NewABI, for local symbols, with or without offsets, we want:
8507 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8508 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8512 ex.X_add_number = ep->X_add_number;
8513 ep->X_add_number = 0;
8514 relax_start (ep->X_add_symbol);
8515 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8516 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8517 reg, reg, mips_gp_register);
8518 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8519 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8520 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8521 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8522 else if (ex.X_add_number)
8524 ex.X_op = O_constant;
8525 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8529 ep->X_add_number = ex.X_add_number;
8531 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8532 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8533 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8534 BFD_RELOC_MIPS_GOT_OFST);
8539 ex.X_add_number = ep->X_add_number;
8540 ep->X_add_number = 0;
8541 relax_start (ep->X_add_symbol);
8542 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8544 reg, reg, mips_gp_register);
8545 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8546 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8548 if (reg_needs_delay (mips_gp_register))
8550 /* We need a nop before loading from $gp. This special
8551 check is required because the lui which starts the main
8552 instruction stream does not refer to $gp, and so will not
8553 insert the nop which may be required. */
8554 macro_build (NULL, "nop", "");
8556 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8557 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8559 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8563 if (ex.X_add_number != 0)
8565 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8566 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8567 ex.X_op = O_constant;
8568 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8576 if (!mips_opts.at && *used_at == 1)
8577 as_bad (_("Macro used $at after \".set noat\""));
8580 /* Move the contents of register SOURCE into register DEST. */
8583 move_register (int dest, int source)
8585 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8586 instruction specifically requires a 32-bit one. */
8587 if (mips_opts.micromips
8588 && !mips_opts.insn32
8589 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8590 macro_build (NULL, "move", "mp,mj", dest, source);
8592 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8596 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8597 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8598 The two alternatives are:
8600 Global symbol Local sybmol
8601 ------------- ------------
8602 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8604 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8606 load_got_offset emits the first instruction and add_got_offset
8607 emits the second for a 16-bit offset or add_got_offset_hilo emits
8608 a sequence to add a 32-bit offset using a scratch register. */
8611 load_got_offset (int dest, expressionS *local)
8616 global.X_add_number = 0;
8618 relax_start (local->X_add_symbol);
8619 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8620 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8622 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8623 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8628 add_got_offset (int dest, expressionS *local)
8632 global.X_op = O_constant;
8633 global.X_op_symbol = NULL;
8634 global.X_add_symbol = NULL;
8635 global.X_add_number = local->X_add_number;
8637 relax_start (local->X_add_symbol);
8638 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
8639 dest, dest, BFD_RELOC_LO16);
8641 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
8646 add_got_offset_hilo (int dest, expressionS *local, int tmp)
8649 int hold_mips_optimize;
8651 global.X_op = O_constant;
8652 global.X_op_symbol = NULL;
8653 global.X_add_symbol = NULL;
8654 global.X_add_number = local->X_add_number;
8656 relax_start (local->X_add_symbol);
8657 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8659 /* Set mips_optimize around the lui instruction to avoid
8660 inserting an unnecessary nop after the lw. */
8661 hold_mips_optimize = mips_optimize;
8663 macro_build_lui (&global, tmp);
8664 mips_optimize = hold_mips_optimize;
8665 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8671 /* Emit a sequence of instructions to emulate a branch likely operation.
8672 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8673 is its complementing branch with the original condition negated.
8674 CALL is set if the original branch specified the link operation.
8675 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8677 Code like this is produced in the noreorder mode:
8682 delay slot (executed only if branch taken)
8690 delay slot (executed only if branch taken)
8693 In the reorder mode the delay slot would be filled with a nop anyway,
8694 so code produced is simply:
8699 This function is used when producing code for the microMIPS ASE that
8700 does not implement branch likely instructions in hardware. */
8703 macro_build_branch_likely (const char *br, const char *brneg,
8704 int call, expressionS *ep, const char *fmt,
8705 unsigned int sreg, unsigned int treg)
8707 int noreorder = mips_opts.noreorder;
8710 gas_assert (mips_opts.micromips);
8714 micromips_label_expr (&expr1);
8715 macro_build (&expr1, brneg, fmt, sreg, treg);
8716 macro_build (NULL, "nop", "");
8717 macro_build (ep, call ? "bal" : "b", "p");
8719 /* Set to true so that append_insn adds a label. */
8720 emit_branch_likely_macro = TRUE;
8724 macro_build (ep, br, fmt, sreg, treg);
8725 macro_build (NULL, "nop", "");
8730 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8731 the condition code tested. EP specifies the branch target. */
8734 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8761 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8764 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8765 the register tested. EP specifies the branch target. */
8768 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8770 const char *brneg = NULL;
8780 br = mips_opts.micromips ? "bgez" : "bgezl";
8784 gas_assert (mips_opts.micromips);
8785 br = mips_opts.insn32 ? "bgezal" : "bgezals";
8793 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8800 br = mips_opts.micromips ? "blez" : "blezl";
8807 br = mips_opts.micromips ? "bltz" : "bltzl";
8811 gas_assert (mips_opts.micromips);
8812 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8819 if (mips_opts.micromips && brneg)
8820 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8822 macro_build (ep, br, "s,p", sreg);
8825 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8826 TREG as the registers tested. EP specifies the branch target. */
8829 macro_build_branch_rsrt (int type, expressionS *ep,
8830 unsigned int sreg, unsigned int treg)
8832 const char *brneg = NULL;
8844 br = mips_opts.micromips ? "beq" : "beql";
8853 br = mips_opts.micromips ? "bne" : "bnel";
8859 if (mips_opts.micromips && brneg)
8860 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8862 macro_build (ep, br, "s,t,p", sreg, treg);
8865 /* Return the high part that should be loaded in order to make the low
8866 part of VALUE accessible using an offset of OFFBITS bits. */
8869 offset_high_part (offsetT value, unsigned int offbits)
8876 bias = 1 << (offbits - 1);
8877 low_mask = bias * 2 - 1;
8878 return (value + bias) & ~low_mask;
8881 /* Return true if the value stored in offset_expr and offset_reloc
8882 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8883 amount that the caller wants to add without inducing overflow
8884 and ALIGN is the known alignment of the value in bytes. */
8887 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8891 /* Accept any relocation operator if overflow isn't a concern. */
8892 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8895 /* These relocations are guaranteed not to overflow in correct links. */
8896 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8897 || gprel16_reloc_p (*offset_reloc))
8900 if (offset_expr.X_op == O_constant
8901 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8902 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8909 * This routine implements the seemingly endless macro or synthesized
8910 * instructions and addressing modes in the mips assembly language. Many
8911 * of these macros are simple and are similar to each other. These could
8912 * probably be handled by some kind of table or grammar approach instead of
8913 * this verbose method. Others are not simple macros but are more like
8914 * optimizing code generation.
8915 * One interesting optimization is when several store macros appear
8916 * consecutively that would load AT with the upper half of the same address.
8917 * The ensuing load upper instructions are ommited. This implies some kind
8918 * of global optimization. We currently only optimize within a single macro.
8919 * For many of the load and store macros if the address is specified as a
8920 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8921 * first load register 'at' with zero and use it as the base register. The
8922 * mips assembler simply uses register $zero. Just one tiny optimization
8926 macro (struct mips_cl_insn *ip, char *str)
8928 const struct mips_operand_array *operands;
8929 unsigned int breg, i;
8930 unsigned int tempreg;
8933 expressionS label_expr;
8948 bfd_boolean large_offset;
8950 int hold_mips_optimize;
8952 unsigned int op[MAX_OPERANDS];
8954 gas_assert (! mips_opts.mips16);
8956 operands = insn_operands (ip);
8957 for (i = 0; i < MAX_OPERANDS; i++)
8958 if (operands->operand[i])
8959 op[i] = insn_extract_operand (ip, operands->operand[i]);
8963 mask = ip->insn_mo->mask;
8965 label_expr.X_op = O_constant;
8966 label_expr.X_op_symbol = NULL;
8967 label_expr.X_add_symbol = NULL;
8968 label_expr.X_add_number = 0;
8970 expr1.X_op = O_constant;
8971 expr1.X_op_symbol = NULL;
8972 expr1.X_add_symbol = NULL;
8973 expr1.X_add_number = 1;
8989 if (mips_opts.micromips)
8990 micromips_label_expr (&label_expr);
8992 label_expr.X_add_number = 8;
8993 macro_build (&label_expr, "bgez", "s,p", op[1]);
8995 macro_build (NULL, "nop", "");
8997 move_register (op[0], op[1]);
8998 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
8999 if (mips_opts.micromips)
9000 micromips_add_label ();
9017 if (!mips_opts.micromips)
9019 if (imm_expr.X_op == O_constant
9020 && imm_expr.X_add_number >= -0x200
9021 && imm_expr.X_add_number < 0x200)
9023 macro_build (NULL, s, "t,r,.", op[0], op[1], imm_expr.X_add_number);
9032 if (imm_expr.X_op == O_constant
9033 && imm_expr.X_add_number >= -0x8000
9034 && imm_expr.X_add_number < 0x8000)
9036 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9041 load_register (AT, &imm_expr, dbl);
9042 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9061 if (imm_expr.X_op == O_constant
9062 && imm_expr.X_add_number >= 0
9063 && imm_expr.X_add_number < 0x10000)
9065 if (mask != M_NOR_I)
9066 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9069 macro_build (&imm_expr, "ori", "t,r,i",
9070 op[0], op[1], BFD_RELOC_LO16);
9071 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9077 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9078 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9082 switch (imm_expr.X_add_number)
9085 macro_build (NULL, "nop", "");
9088 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9092 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9093 (int) imm_expr.X_add_number);
9096 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9097 (unsigned long) imm_expr.X_add_number);
9106 gas_assert (mips_opts.micromips);
9107 macro_build_branch_ccl (mask, &offset_expr,
9108 EXTRACT_OPERAND (1, BCC, *ip));
9115 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9121 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
9126 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9133 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9134 else if (op[0] == 0)
9135 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9139 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9140 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9141 &offset_expr, AT, ZERO);
9151 macro_build_branch_rs (mask, &offset_expr, op[0]);
9157 /* Check for > max integer. */
9158 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9161 /* Result is always false. */
9163 macro_build (NULL, "nop", "");
9165 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9168 if (imm_expr.X_op != O_constant)
9169 as_bad (_("Unsupported large constant"));
9170 ++imm_expr.X_add_number;
9174 if (mask == M_BGEL_I)
9176 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9178 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9179 &offset_expr, op[0]);
9182 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9184 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9185 &offset_expr, op[0]);
9188 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
9191 /* result is always true */
9192 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
9193 macro_build (&offset_expr, "b", "p");
9198 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9199 &offset_expr, AT, ZERO);
9207 else if (op[0] == 0)
9208 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9209 &offset_expr, ZERO, op[1]);
9213 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9214 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9215 &offset_expr, AT, ZERO);
9224 && imm_expr.X_op == O_constant
9225 && imm_expr.X_add_number == -1))
9227 if (imm_expr.X_op != O_constant)
9228 as_bad (_("Unsupported large constant"));
9229 ++imm_expr.X_add_number;
9233 if (mask == M_BGEUL_I)
9235 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9237 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9238 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9239 &offset_expr, op[0], ZERO);
9244 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9245 &offset_expr, AT, ZERO);
9253 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9254 else if (op[0] == 0)
9255 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9259 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9260 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9261 &offset_expr, AT, ZERO);
9269 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9270 &offset_expr, op[0], ZERO);
9271 else if (op[0] == 0)
9276 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9277 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9278 &offset_expr, AT, ZERO);
9286 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9287 else if (op[0] == 0)
9288 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
9292 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9293 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9294 &offset_expr, AT, ZERO);
9301 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9303 if (imm_expr.X_op != O_constant)
9304 as_bad (_("Unsupported large constant"));
9305 ++imm_expr.X_add_number;
9309 if (mask == M_BLTL_I)
9311 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9312 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9313 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9314 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9319 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9320 &offset_expr, AT, ZERO);
9328 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9329 &offset_expr, op[0], ZERO);
9330 else if (op[0] == 0)
9335 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9336 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9337 &offset_expr, AT, ZERO);
9346 && imm_expr.X_op == O_constant
9347 && imm_expr.X_add_number == -1))
9349 if (imm_expr.X_op != O_constant)
9350 as_bad (_("Unsupported large constant"));
9351 ++imm_expr.X_add_number;
9355 if (mask == M_BLTUL_I)
9357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9359 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9360 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9361 &offset_expr, op[0], ZERO);
9366 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9367 &offset_expr, AT, ZERO);
9375 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9376 else if (op[0] == 0)
9377 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
9381 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9382 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9383 &offset_expr, AT, ZERO);
9392 else if (op[0] == 0)
9393 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9394 &offset_expr, ZERO, op[1]);
9398 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9399 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9400 &offset_expr, AT, ZERO);
9406 /* Use unsigned arithmetic. */
9410 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9412 as_bad (_("Unsupported large constant"));
9417 pos = imm_expr.X_add_number;
9418 size = imm2_expr.X_add_number;
9423 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9426 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9428 report_bad_field (pos, size);
9432 if (size <= 32 && pos < 32)
9437 else if (size <= 32)
9447 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9454 /* Use unsigned arithmetic. */
9458 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9460 as_bad (_("Unsupported large constant"));
9465 pos = imm_expr.X_add_number;
9466 size = imm2_expr.X_add_number;
9471 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9474 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9476 report_bad_field (pos, size);
9480 if (pos < 32 && (pos + size - 1) < 32)
9495 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9496 (int) (pos + size - 1));
9512 as_warn (_("Divide by zero."));
9514 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9516 macro_build (NULL, "break", BRK_FMT, 7);
9523 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9524 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9528 if (mips_opts.micromips)
9529 micromips_label_expr (&label_expr);
9531 label_expr.X_add_number = 8;
9532 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9533 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9534 macro_build (NULL, "break", BRK_FMT, 7);
9535 if (mips_opts.micromips)
9536 micromips_add_label ();
9538 expr1.X_add_number = -1;
9540 load_register (AT, &expr1, dbl);
9541 if (mips_opts.micromips)
9542 micromips_label_expr (&label_expr);
9544 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
9545 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
9548 expr1.X_add_number = 1;
9549 load_register (AT, &expr1, dbl);
9550 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
9554 expr1.X_add_number = 0x80000000;
9555 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
9559 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
9560 /* We want to close the noreorder block as soon as possible, so
9561 that later insns are available for delay slot filling. */
9566 if (mips_opts.micromips)
9567 micromips_label_expr (&label_expr);
9569 label_expr.X_add_number = 8;
9570 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
9571 macro_build (NULL, "nop", "");
9573 /* We want to close the noreorder block as soon as possible, so
9574 that later insns are available for delay slot filling. */
9577 macro_build (NULL, "break", BRK_FMT, 6);
9579 if (mips_opts.micromips)
9580 micromips_add_label ();
9581 macro_build (NULL, s, MFHL_FMT, op[0]);
9620 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9622 as_warn (_("Divide by zero."));
9624 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9626 macro_build (NULL, "break", BRK_FMT, 7);
9629 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9631 if (strcmp (s2, "mflo") == 0)
9632 move_register (op[0], op[1]);
9634 move_register (op[0], ZERO);
9637 if (imm_expr.X_op == O_constant
9638 && imm_expr.X_add_number == -1
9639 && s[strlen (s) - 1] != 'u')
9641 if (strcmp (s2, "mflo") == 0)
9642 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
9644 move_register (op[0], ZERO);
9649 load_register (AT, &imm_expr, dbl);
9650 macro_build (NULL, s, "z,s,t", op[1], AT);
9651 macro_build (NULL, s2, MFHL_FMT, op[0]);
9673 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9674 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9675 /* We want to close the noreorder block as soon as possible, so
9676 that later insns are available for delay slot filling. */
9681 if (mips_opts.micromips)
9682 micromips_label_expr (&label_expr);
9684 label_expr.X_add_number = 8;
9685 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9686 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9688 /* We want to close the noreorder block as soon as possible, so
9689 that later insns are available for delay slot filling. */
9691 macro_build (NULL, "break", BRK_FMT, 7);
9692 if (mips_opts.micromips)
9693 micromips_add_label ();
9695 macro_build (NULL, s2, MFHL_FMT, op[0]);
9707 /* Load the address of a symbol into a register. If breg is not
9708 zero, we then add a base register to it. */
9711 if (dbl && HAVE_32BIT_GPRS)
9712 as_warn (_("dla used to load 32-bit register"));
9714 if (!dbl && HAVE_64BIT_OBJECTS)
9715 as_warn (_("la used to load 64-bit address"));
9717 if (small_offset_p (0, align, 16))
9719 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
9720 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9724 if (mips_opts.at && (op[0] == breg))
9732 if (offset_expr.X_op != O_symbol
9733 && offset_expr.X_op != O_constant)
9735 as_bad (_("Expression too complex"));
9736 offset_expr.X_op = O_constant;
9739 if (offset_expr.X_op == O_constant)
9740 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
9741 else if (mips_pic == NO_PIC)
9743 /* If this is a reference to a GP relative symbol, we want
9744 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9746 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9747 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9748 If we have a constant, we need two instructions anyhow,
9749 so we may as well always use the latter form.
9751 With 64bit address space and a usable $at we want
9752 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9753 lui $at,<sym> (BFD_RELOC_HI16_S)
9754 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9755 daddiu $at,<sym> (BFD_RELOC_LO16)
9757 daddu $tempreg,$tempreg,$at
9759 If $at is already in use, we use a path which is suboptimal
9760 on superscalar processors.
9761 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9762 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9764 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9766 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9768 For GP relative symbols in 64bit address space we can use
9769 the same sequence as in 32bit address space. */
9770 if (HAVE_64BIT_SYMBOLS)
9772 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9773 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9775 relax_start (offset_expr.X_add_symbol);
9776 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9777 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9781 if (used_at == 0 && mips_opts.at)
9783 macro_build (&offset_expr, "lui", LUI_FMT,
9784 tempreg, BFD_RELOC_MIPS_HIGHEST);
9785 macro_build (&offset_expr, "lui", LUI_FMT,
9786 AT, BFD_RELOC_HI16_S);
9787 macro_build (&offset_expr, "daddiu", "t,r,j",
9788 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9789 macro_build (&offset_expr, "daddiu", "t,r,j",
9790 AT, AT, BFD_RELOC_LO16);
9791 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9792 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9797 macro_build (&offset_expr, "lui", LUI_FMT,
9798 tempreg, BFD_RELOC_MIPS_HIGHEST);
9799 macro_build (&offset_expr, "daddiu", "t,r,j",
9800 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9801 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9802 macro_build (&offset_expr, "daddiu", "t,r,j",
9803 tempreg, tempreg, BFD_RELOC_HI16_S);
9804 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9805 macro_build (&offset_expr, "daddiu", "t,r,j",
9806 tempreg, tempreg, BFD_RELOC_LO16);
9809 if (mips_relax.sequence)
9814 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9815 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9817 relax_start (offset_expr.X_add_symbol);
9818 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9819 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9822 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9823 as_bad (_("Offset too large"));
9824 macro_build_lui (&offset_expr, tempreg);
9825 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9826 tempreg, tempreg, BFD_RELOC_LO16);
9827 if (mips_relax.sequence)
9831 else if (!mips_big_got && !HAVE_NEWABI)
9833 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9835 /* If this is a reference to an external symbol, and there
9836 is no constant, we want
9837 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9838 or for lca or if tempreg is PIC_CALL_REG
9839 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9840 For a local symbol, we want
9841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9843 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9845 If we have a small constant, and this is a reference to
9846 an external symbol, we want
9847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9849 addiu $tempreg,$tempreg,<constant>
9850 For a local symbol, we want the same instruction
9851 sequence, but we output a BFD_RELOC_LO16 reloc on the
9854 If we have a large constant, and this is a reference to
9855 an external symbol, we want
9856 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9857 lui $at,<hiconstant>
9858 addiu $at,$at,<loconstant>
9859 addu $tempreg,$tempreg,$at
9860 For a local symbol, we want the same instruction
9861 sequence, but we output a BFD_RELOC_LO16 reloc on the
9865 if (offset_expr.X_add_number == 0)
9867 if (mips_pic == SVR4_PIC
9869 && (call || tempreg == PIC_CALL_REG))
9870 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9872 relax_start (offset_expr.X_add_symbol);
9873 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9874 lw_reloc_type, mips_gp_register);
9877 /* We're going to put in an addu instruction using
9878 tempreg, so we may as well insert the nop right
9883 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9884 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9886 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9887 tempreg, tempreg, BFD_RELOC_LO16);
9889 /* FIXME: If breg == 0, and the next instruction uses
9890 $tempreg, then if this variant case is used an extra
9891 nop will be generated. */
9893 else if (offset_expr.X_add_number >= -0x8000
9894 && offset_expr.X_add_number < 0x8000)
9896 load_got_offset (tempreg, &offset_expr);
9898 add_got_offset (tempreg, &offset_expr);
9902 expr1.X_add_number = offset_expr.X_add_number;
9903 offset_expr.X_add_number =
9904 SEXT_16BIT (offset_expr.X_add_number);
9905 load_got_offset (tempreg, &offset_expr);
9906 offset_expr.X_add_number = expr1.X_add_number;
9907 /* If we are going to add in a base register, and the
9908 target register and the base register are the same,
9909 then we are using AT as a temporary register. Since
9910 we want to load the constant into AT, we add our
9911 current AT (from the global offset table) and the
9912 register into the register now, and pretend we were
9913 not using a base register. */
9917 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9922 add_got_offset_hilo (tempreg, &offset_expr, AT);
9926 else if (!mips_big_got && HAVE_NEWABI)
9928 int add_breg_early = 0;
9930 /* If this is a reference to an external, and there is no
9931 constant, or local symbol (*), with or without a
9933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9934 or for lca or if tempreg is PIC_CALL_REG
9935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9937 If we have a small constant, and this is a reference to
9938 an external symbol, we want
9939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9940 addiu $tempreg,$tempreg,<constant>
9942 If we have a large constant, and this is a reference to
9943 an external symbol, we want
9944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9945 lui $at,<hiconstant>
9946 addiu $at,$at,<loconstant>
9947 addu $tempreg,$tempreg,$at
9949 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9950 local symbols, even though it introduces an additional
9953 if (offset_expr.X_add_number)
9955 expr1.X_add_number = offset_expr.X_add_number;
9956 offset_expr.X_add_number = 0;
9958 relax_start (offset_expr.X_add_symbol);
9959 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9960 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9962 if (expr1.X_add_number >= -0x8000
9963 && expr1.X_add_number < 0x8000)
9965 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9966 tempreg, tempreg, BFD_RELOC_LO16);
9968 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9972 /* If we are going to add in a base register, and the
9973 target register and the base register are the same,
9974 then we are using AT as a temporary register. Since
9975 we want to load the constant into AT, we add our
9976 current AT (from the global offset table) and the
9977 register into the register now, and pretend we were
9978 not using a base register. */
9983 gas_assert (tempreg == AT);
9984 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9990 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9991 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9997 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10000 offset_expr.X_add_number = expr1.X_add_number;
10002 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10003 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10004 if (add_breg_early)
10006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10007 op[0], tempreg, breg);
10013 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10015 relax_start (offset_expr.X_add_symbol);
10016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10017 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10019 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10020 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10025 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10026 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10029 else if (mips_big_got && !HAVE_NEWABI)
10032 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10033 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10034 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10036 /* This is the large GOT case. If this is a reference to an
10037 external symbol, and there is no constant, we want
10038 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10039 addu $tempreg,$tempreg,$gp
10040 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10041 or for lca or if tempreg is PIC_CALL_REG
10042 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10043 addu $tempreg,$tempreg,$gp
10044 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10045 For a local symbol, we want
10046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10048 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10050 If we have a small constant, and this is a reference to
10051 an external symbol, we want
10052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10053 addu $tempreg,$tempreg,$gp
10054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10056 addiu $tempreg,$tempreg,<constant>
10057 For a local symbol, we want
10058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10060 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10062 If we have a large constant, and this is a reference to
10063 an external symbol, we want
10064 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10065 addu $tempreg,$tempreg,$gp
10066 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10067 lui $at,<hiconstant>
10068 addiu $at,$at,<loconstant>
10069 addu $tempreg,$tempreg,$at
10070 For a local symbol, we want
10071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10072 lui $at,<hiconstant>
10073 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10074 addu $tempreg,$tempreg,$at
10077 expr1.X_add_number = offset_expr.X_add_number;
10078 offset_expr.X_add_number = 0;
10079 relax_start (offset_expr.X_add_symbol);
10080 gpdelay = reg_needs_delay (mips_gp_register);
10081 if (expr1.X_add_number == 0 && breg == 0
10082 && (call || tempreg == PIC_CALL_REG))
10084 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10085 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10087 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10089 tempreg, tempreg, mips_gp_register);
10090 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10091 tempreg, lw_reloc_type, tempreg);
10092 if (expr1.X_add_number == 0)
10096 /* We're going to put in an addu instruction using
10097 tempreg, so we may as well insert the nop right
10102 else if (expr1.X_add_number >= -0x8000
10103 && expr1.X_add_number < 0x8000)
10106 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10107 tempreg, tempreg, BFD_RELOC_LO16);
10113 /* If we are going to add in a base register, and the
10114 target register and the base register are the same,
10115 then we are using AT as a temporary register. Since
10116 we want to load the constant into AT, we add our
10117 current AT (from the global offset table) and the
10118 register into the register now, and pretend we were
10119 not using a base register. */
10124 gas_assert (tempreg == AT);
10126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10131 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10132 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10136 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10141 /* This is needed because this instruction uses $gp, but
10142 the first instruction on the main stream does not. */
10143 macro_build (NULL, "nop", "");
10146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10147 local_reloc_type, mips_gp_register);
10148 if (expr1.X_add_number >= -0x8000
10149 && expr1.X_add_number < 0x8000)
10152 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10153 tempreg, tempreg, BFD_RELOC_LO16);
10154 /* FIXME: If add_number is 0, and there was no base
10155 register, the external symbol case ended with a load,
10156 so if the symbol turns out to not be external, and
10157 the next instruction uses tempreg, an unnecessary nop
10158 will be inserted. */
10164 /* We must add in the base register now, as in the
10165 external symbol case. */
10166 gas_assert (tempreg == AT);
10168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10171 /* We set breg to 0 because we have arranged to add
10172 it in in both cases. */
10176 macro_build_lui (&expr1, AT);
10177 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10178 AT, AT, BFD_RELOC_LO16);
10179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10180 tempreg, tempreg, AT);
10185 else if (mips_big_got && HAVE_NEWABI)
10187 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10188 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10189 int add_breg_early = 0;
10191 /* This is the large GOT case. If this is a reference to an
10192 external symbol, and there is no constant, we want
10193 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10194 add $tempreg,$tempreg,$gp
10195 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10196 or for lca or if tempreg is PIC_CALL_REG
10197 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10198 add $tempreg,$tempreg,$gp
10199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10201 If we have a small constant, and this is a reference to
10202 an external symbol, we want
10203 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10204 add $tempreg,$tempreg,$gp
10205 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10206 addi $tempreg,$tempreg,<constant>
10208 If we have a large constant, and this is a reference to
10209 an external symbol, we want
10210 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10211 addu $tempreg,$tempreg,$gp
10212 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10213 lui $at,<hiconstant>
10214 addi $at,$at,<loconstant>
10215 add $tempreg,$tempreg,$at
10217 If we have NewABI, and we know it's a local symbol, we want
10218 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10219 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10220 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10222 relax_start (offset_expr.X_add_symbol);
10224 expr1.X_add_number = offset_expr.X_add_number;
10225 offset_expr.X_add_number = 0;
10227 if (expr1.X_add_number == 0 && breg == 0
10228 && (call || tempreg == PIC_CALL_REG))
10230 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10231 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10233 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10234 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10235 tempreg, tempreg, mips_gp_register);
10236 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10237 tempreg, lw_reloc_type, tempreg);
10239 if (expr1.X_add_number == 0)
10241 else if (expr1.X_add_number >= -0x8000
10242 && expr1.X_add_number < 0x8000)
10244 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10245 tempreg, tempreg, BFD_RELOC_LO16);
10247 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10251 /* If we are going to add in a base register, and the
10252 target register and the base register are the same,
10253 then we are using AT as a temporary register. Since
10254 we want to load the constant into AT, we add our
10255 current AT (from the global offset table) and the
10256 register into the register now, and pretend we were
10257 not using a base register. */
10262 gas_assert (tempreg == AT);
10263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10266 add_breg_early = 1;
10269 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10275 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10278 offset_expr.X_add_number = expr1.X_add_number;
10279 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10280 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10281 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10282 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10283 if (add_breg_early)
10285 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10286 op[0], tempreg, breg);
10296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10300 gas_assert (!mips_opts.micromips);
10301 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10305 gas_assert (!mips_opts.micromips);
10306 macro_build (NULL, "c2", "C", 0x02);
10310 gas_assert (!mips_opts.micromips);
10311 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10315 gas_assert (!mips_opts.micromips);
10316 macro_build (NULL, "c2", "C", 3);
10320 gas_assert (!mips_opts.micromips);
10321 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10325 /* The j instruction may not be used in PIC code, since it
10326 requires an absolute address. We convert it to a b
10328 if (mips_pic == NO_PIC)
10329 macro_build (&offset_expr, "j", "a");
10331 macro_build (&offset_expr, "b", "p");
10334 /* The jal instructions must be handled as macros because when
10335 generating PIC code they expand to multi-instruction
10336 sequences. Normally they are simple instructions. */
10340 /* Fall through. */
10342 gas_assert (mips_opts.micromips);
10343 if (mips_opts.insn32)
10345 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10353 /* Fall through. */
10356 if (mips_pic == NO_PIC)
10358 s = jals ? "jalrs" : "jalr";
10359 if (mips_opts.micromips
10360 && !mips_opts.insn32
10362 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10363 macro_build (NULL, s, "mj", op[1]);
10365 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10369 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10370 && mips_cprestore_offset >= 0);
10372 if (op[1] != PIC_CALL_REG)
10373 as_warn (_("MIPS PIC call to register other than $25"));
10375 s = ((mips_opts.micromips
10376 && !mips_opts.insn32
10377 && (!mips_opts.noreorder || cprestore))
10378 ? "jalrs" : "jalr");
10379 if (mips_opts.micromips
10380 && !mips_opts.insn32
10382 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10383 macro_build (NULL, s, "mj", op[1]);
10385 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10386 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
10388 if (mips_cprestore_offset < 0)
10389 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10392 if (!mips_frame_reg_valid)
10394 as_warn (_("No .frame pseudo-op used in PIC code"));
10395 /* Quiet this warning. */
10396 mips_frame_reg_valid = 1;
10398 if (!mips_cprestore_valid)
10400 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10401 /* Quiet this warning. */
10402 mips_cprestore_valid = 1;
10404 if (mips_opts.noreorder)
10405 macro_build (NULL, "nop", "");
10406 expr1.X_add_number = mips_cprestore_offset;
10407 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10410 HAVE_64BIT_ADDRESSES);
10418 gas_assert (mips_opts.micromips);
10419 if (mips_opts.insn32)
10421 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10425 /* Fall through. */
10427 if (mips_pic == NO_PIC)
10428 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
10429 else if (mips_pic == SVR4_PIC)
10431 /* If this is a reference to an external symbol, and we are
10432 using a small GOT, we want
10433 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10437 lw $gp,cprestore($sp)
10438 The cprestore value is set using the .cprestore
10439 pseudo-op. If we are using a big GOT, we want
10440 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10442 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10446 lw $gp,cprestore($sp)
10447 If the symbol is not external, we want
10448 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10450 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10453 lw $gp,cprestore($sp)
10455 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10456 sequences above, minus nops, unless the symbol is local,
10457 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10463 relax_start (offset_expr.X_add_symbol);
10464 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10465 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10468 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10469 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
10475 relax_start (offset_expr.X_add_symbol);
10476 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10477 BFD_RELOC_MIPS_CALL_HI16);
10478 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10479 PIC_CALL_REG, mips_gp_register);
10480 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10481 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10484 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10485 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10487 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10488 PIC_CALL_REG, PIC_CALL_REG,
10489 BFD_RELOC_MIPS_GOT_OFST);
10493 macro_build_jalr (&offset_expr, 0);
10497 relax_start (offset_expr.X_add_symbol);
10500 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10501 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10510 gpdelay = reg_needs_delay (mips_gp_register);
10511 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10512 BFD_RELOC_MIPS_CALL_HI16);
10513 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10514 PIC_CALL_REG, mips_gp_register);
10515 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10516 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10521 macro_build (NULL, "nop", "");
10523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10524 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
10527 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10528 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
10530 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
10532 if (mips_cprestore_offset < 0)
10533 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10536 if (!mips_frame_reg_valid)
10538 as_warn (_("No .frame pseudo-op used in PIC code"));
10539 /* Quiet this warning. */
10540 mips_frame_reg_valid = 1;
10542 if (!mips_cprestore_valid)
10544 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10545 /* Quiet this warning. */
10546 mips_cprestore_valid = 1;
10548 if (mips_opts.noreorder)
10549 macro_build (NULL, "nop", "");
10550 expr1.X_add_number = mips_cprestore_offset;
10551 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10554 HAVE_64BIT_ADDRESSES);
10558 else if (mips_pic == VXWORKS_PIC)
10559 as_bad (_("Non-PIC jump used in PIC library"));
10666 gas_assert (!mips_opts.micromips);
10669 /* Itbl support may require additional care here. */
10675 /* Itbl support may require additional care here. */
10681 offbits = (mips_opts.micromips ? 12 : 16);
10682 /* Itbl support may require additional care here. */
10686 gas_assert (!mips_opts.micromips);
10689 /* Itbl support may require additional care here. */
10695 offbits = (mips_opts.micromips ? 12 : 16);
10700 offbits = (mips_opts.micromips ? 12 : 16);
10705 /* Itbl support may require additional care here. */
10711 offbits = (mips_opts.micromips ? 12 : 16);
10712 /* Itbl support may require additional care here. */
10718 /* Itbl support may require additional care here. */
10724 /* Itbl support may require additional care here. */
10730 offbits = (mips_opts.micromips ? 12 : 16);
10735 offbits = (mips_opts.micromips ? 12 : 16);
10740 offbits = (mips_opts.micromips ? 12 : 16);
10745 offbits = (mips_opts.micromips ? 12 : 16);
10750 offbits = (mips_opts.micromips ? 12 : 16);
10753 gas_assert (mips_opts.micromips);
10760 gas_assert (mips_opts.micromips);
10767 gas_assert (mips_opts.micromips);
10773 gas_assert (mips_opts.micromips);
10780 /* We don't want to use $0 as tempreg. */
10781 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
10784 tempreg = op[0] + lp;
10800 gas_assert (!mips_opts.micromips);
10803 /* Itbl support may require additional care here. */
10809 /* Itbl support may require additional care here. */
10815 offbits = (mips_opts.micromips ? 12 : 16);
10816 /* Itbl support may require additional care here. */
10820 gas_assert (!mips_opts.micromips);
10823 /* Itbl support may require additional care here. */
10829 offbits = (mips_opts.micromips ? 12 : 16);
10834 offbits = (mips_opts.micromips ? 12 : 16);
10839 offbits = (mips_opts.micromips ? 12 : 16);
10844 offbits = (mips_opts.micromips ? 12 : 16);
10848 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10849 offbits = (mips_opts.micromips ? 12 : 16);
10858 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10859 offbits = (mips_opts.micromips ? 12 : 16);
10870 /* Itbl support may require additional care here. */
10875 offbits = (mips_opts.micromips ? 12 : 16);
10876 /* Itbl support may require additional care here. */
10882 /* Itbl support may require additional care here. */
10886 gas_assert (!mips_opts.micromips);
10889 /* Itbl support may require additional care here. */
10895 offbits = (mips_opts.micromips ? 12 : 16);
10900 offbits = (mips_opts.micromips ? 12 : 16);
10903 gas_assert (mips_opts.micromips);
10909 gas_assert (mips_opts.micromips);
10915 gas_assert (mips_opts.micromips);
10921 gas_assert (mips_opts.micromips);
10930 if (small_offset_p (0, align, 16))
10932 /* The first case exists for M_LD_AB and M_SD_AB, which are
10933 macros for o32 but which should act like normal instructions
10936 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
10937 offset_reloc[1], offset_reloc[2], breg);
10938 else if (small_offset_p (0, align, offbits))
10941 macro_build (NULL, s, fmt, op[0], breg);
10943 macro_build (NULL, s, fmt, op[0],
10944 (int) offset_expr.X_add_number, breg);
10950 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10951 tempreg, breg, -1, offset_reloc[0],
10952 offset_reloc[1], offset_reloc[2]);
10954 macro_build (NULL, s, fmt, op[0], tempreg);
10956 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10964 if (offset_expr.X_op != O_constant
10965 && offset_expr.X_op != O_symbol)
10967 as_bad (_("Expression too complex"));
10968 offset_expr.X_op = O_constant;
10971 if (HAVE_32BIT_ADDRESSES
10972 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10976 sprintf_vma (value, offset_expr.X_add_number);
10977 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10980 /* A constant expression in PIC code can be handled just as it
10981 is in non PIC code. */
10982 if (offset_expr.X_op == O_constant)
10984 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10985 offbits == 0 ? 16 : offbits);
10986 offset_expr.X_add_number -= expr1.X_add_number;
10988 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10990 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10991 tempreg, tempreg, breg);
10994 if (offset_expr.X_add_number != 0)
10995 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10996 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10997 macro_build (NULL, s, fmt, op[0], tempreg);
10999 else if (offbits == 16)
11000 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11002 macro_build (NULL, s, fmt, op[0],
11003 (int) offset_expr.X_add_number, tempreg);
11005 else if (offbits != 16)
11007 /* The offset field is too narrow to be used for a low-part
11008 relocation, so load the whole address into the auxillary
11010 load_address (tempreg, &offset_expr, &used_at);
11012 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11013 tempreg, tempreg, breg);
11015 macro_build (NULL, s, fmt, op[0], tempreg);
11017 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11019 else if (mips_pic == NO_PIC)
11021 /* If this is a reference to a GP relative symbol, and there
11022 is no base register, we want
11023 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11024 Otherwise, if there is no base register, we want
11025 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11026 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11027 If we have a constant, we need two instructions anyhow,
11028 so we always use the latter form.
11030 If we have a base register, and this is a reference to a
11031 GP relative symbol, we want
11032 addu $tempreg,$breg,$gp
11033 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11035 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11036 addu $tempreg,$tempreg,$breg
11037 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11038 With a constant we always use the latter case.
11040 With 64bit address space and no base register and $at usable,
11042 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11043 lui $at,<sym> (BFD_RELOC_HI16_S)
11044 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11047 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11048 If we have a base register, we want
11049 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11050 lui $at,<sym> (BFD_RELOC_HI16_S)
11051 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11055 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11057 Without $at we can't generate the optimal path for superscalar
11058 processors here since this would require two temporary registers.
11059 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11060 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11062 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11064 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11065 If we have a base register, we want
11066 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11067 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11069 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11071 daddu $tempreg,$tempreg,$breg
11072 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11074 For GP relative symbols in 64bit address space we can use
11075 the same sequence as in 32bit address space. */
11076 if (HAVE_64BIT_SYMBOLS)
11078 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11079 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11081 relax_start (offset_expr.X_add_symbol);
11084 macro_build (&offset_expr, s, fmt, op[0],
11085 BFD_RELOC_GPREL16, mips_gp_register);
11089 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11090 tempreg, breg, mips_gp_register);
11091 macro_build (&offset_expr, s, fmt, op[0],
11092 BFD_RELOC_GPREL16, tempreg);
11097 if (used_at == 0 && mips_opts.at)
11099 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11100 BFD_RELOC_MIPS_HIGHEST);
11101 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11103 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11104 tempreg, BFD_RELOC_MIPS_HIGHER);
11106 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11107 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11108 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11109 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11115 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11116 BFD_RELOC_MIPS_HIGHEST);
11117 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11118 tempreg, BFD_RELOC_MIPS_HIGHER);
11119 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11120 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11121 tempreg, BFD_RELOC_HI16_S);
11122 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11124 macro_build (NULL, "daddu", "d,v,t",
11125 tempreg, tempreg, breg);
11126 macro_build (&offset_expr, s, fmt, op[0],
11127 BFD_RELOC_LO16, tempreg);
11130 if (mips_relax.sequence)
11137 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11138 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11140 relax_start (offset_expr.X_add_symbol);
11141 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11145 macro_build_lui (&offset_expr, tempreg);
11146 macro_build (&offset_expr, s, fmt, op[0],
11147 BFD_RELOC_LO16, tempreg);
11148 if (mips_relax.sequence)
11153 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11154 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11156 relax_start (offset_expr.X_add_symbol);
11157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11158 tempreg, breg, mips_gp_register);
11159 macro_build (&offset_expr, s, fmt, op[0],
11160 BFD_RELOC_GPREL16, tempreg);
11163 macro_build_lui (&offset_expr, tempreg);
11164 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11165 tempreg, tempreg, breg);
11166 macro_build (&offset_expr, s, fmt, op[0],
11167 BFD_RELOC_LO16, tempreg);
11168 if (mips_relax.sequence)
11172 else if (!mips_big_got)
11174 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11176 /* If this is a reference to an external symbol, we want
11177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11179 <op> op[0],0($tempreg)
11181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11183 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11184 <op> op[0],0($tempreg)
11186 For NewABI, we want
11187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11188 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11190 If there is a base register, we add it to $tempreg before
11191 the <op>. If there is a constant, we stick it in the
11192 <op> instruction. We don't handle constants larger than
11193 16 bits, because we have no way to load the upper 16 bits
11194 (actually, we could handle them for the subset of cases
11195 in which we are not using $at). */
11196 gas_assert (offset_expr.X_op == O_symbol);
11199 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11200 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11202 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11203 tempreg, tempreg, breg);
11204 macro_build (&offset_expr, s, fmt, op[0],
11205 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11208 expr1.X_add_number = offset_expr.X_add_number;
11209 offset_expr.X_add_number = 0;
11210 if (expr1.X_add_number < -0x8000
11211 || expr1.X_add_number >= 0x8000)
11212 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11213 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11214 lw_reloc_type, mips_gp_register);
11216 relax_start (offset_expr.X_add_symbol);
11218 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11219 tempreg, BFD_RELOC_LO16);
11222 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11223 tempreg, tempreg, breg);
11224 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11226 else if (mips_big_got && !HAVE_NEWABI)
11230 /* If this is a reference to an external symbol, we want
11231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11232 addu $tempreg,$tempreg,$gp
11233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11234 <op> op[0],0($tempreg)
11236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11238 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11239 <op> op[0],0($tempreg)
11240 If there is a base register, we add it to $tempreg before
11241 the <op>. If there is a constant, we stick it in the
11242 <op> instruction. We don't handle constants larger than
11243 16 bits, because we have no way to load the upper 16 bits
11244 (actually, we could handle them for the subset of cases
11245 in which we are not using $at). */
11246 gas_assert (offset_expr.X_op == O_symbol);
11247 expr1.X_add_number = offset_expr.X_add_number;
11248 offset_expr.X_add_number = 0;
11249 if (expr1.X_add_number < -0x8000
11250 || expr1.X_add_number >= 0x8000)
11251 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11252 gpdelay = reg_needs_delay (mips_gp_register);
11253 relax_start (offset_expr.X_add_symbol);
11254 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11255 BFD_RELOC_MIPS_GOT_HI16);
11256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11258 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11259 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11262 macro_build (NULL, "nop", "");
11263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11264 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11266 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11267 tempreg, BFD_RELOC_LO16);
11271 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11272 tempreg, tempreg, breg);
11273 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11275 else if (mips_big_got && HAVE_NEWABI)
11277 /* If this is a reference to an external symbol, we want
11278 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11279 add $tempreg,$tempreg,$gp
11280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11281 <op> op[0],<ofst>($tempreg)
11282 Otherwise, for local symbols, we want:
11283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11284 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11285 gas_assert (offset_expr.X_op == O_symbol);
11286 expr1.X_add_number = offset_expr.X_add_number;
11287 offset_expr.X_add_number = 0;
11288 if (expr1.X_add_number < -0x8000
11289 || expr1.X_add_number >= 0x8000)
11290 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11291 relax_start (offset_expr.X_add_symbol);
11292 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11293 BFD_RELOC_MIPS_GOT_HI16);
11294 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11296 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11297 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11299 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11300 tempreg, tempreg, breg);
11301 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11304 offset_expr.X_add_number = expr1.X_add_number;
11305 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11306 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11309 tempreg, tempreg, breg);
11310 macro_build (&offset_expr, s, fmt, op[0],
11311 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11320 gas_assert (mips_opts.micromips);
11321 gas_assert (mips_opts.insn32);
11322 start_noreorder ();
11323 macro_build (NULL, "jr", "s", RA);
11324 expr1.X_add_number = op[0] << 2;
11325 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11330 gas_assert (mips_opts.micromips);
11331 gas_assert (mips_opts.insn32);
11332 macro_build (NULL, "jr", "s", op[0]);
11333 if (mips_opts.noreorder)
11334 macro_build (NULL, "nop", "");
11339 load_register (op[0], &imm_expr, 0);
11343 load_register (op[0], &imm_expr, 1);
11347 if (imm_expr.X_op == O_constant)
11350 load_register (AT, &imm_expr, 0);
11351 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11356 gas_assert (offset_expr.X_op == O_symbol
11357 && strcmp (segment_name (S_GET_SEGMENT
11358 (offset_expr.X_add_symbol)),
11360 && offset_expr.X_add_number == 0);
11361 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
11362 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
11367 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11368 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11369 order 32 bits of the value and the low order 32 bits are either
11370 zero or in OFFSET_EXPR. */
11371 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11373 if (HAVE_64BIT_GPRS)
11374 load_register (op[0], &imm_expr, 1);
11379 if (target_big_endian)
11391 load_register (hreg, &imm_expr, 0);
11394 if (offset_expr.X_op == O_absent)
11395 move_register (lreg, 0);
11398 gas_assert (offset_expr.X_op == O_constant);
11399 load_register (lreg, &offset_expr, 0);
11406 /* We know that sym is in the .rdata section. First we get the
11407 upper 16 bits of the address. */
11408 if (mips_pic == NO_PIC)
11410 macro_build_lui (&offset_expr, AT);
11415 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11416 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11420 /* Now we load the register(s). */
11421 if (HAVE_64BIT_GPRS)
11424 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11425 BFD_RELOC_LO16, AT);
11430 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11431 BFD_RELOC_LO16, AT);
11434 /* FIXME: How in the world do we deal with the possible
11436 offset_expr.X_add_number += 4;
11437 macro_build (&offset_expr, "lw", "t,o(b)",
11438 op[0] + 1, BFD_RELOC_LO16, AT);
11444 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11445 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11446 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11447 the value and the low order 32 bits are either zero or in
11449 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11452 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
11453 if (HAVE_64BIT_FPRS)
11455 gas_assert (HAVE_64BIT_GPRS);
11456 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
11460 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
11461 if (offset_expr.X_op == O_absent)
11462 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
11465 gas_assert (offset_expr.X_op == O_constant);
11466 load_register (AT, &offset_expr, 0);
11467 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11473 gas_assert (offset_expr.X_op == O_symbol
11474 && offset_expr.X_add_number == 0);
11475 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11476 if (strcmp (s, ".lit8") == 0)
11478 op[2] = mips_gp_register;
11479 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11480 offset_reloc[1] = BFD_RELOC_UNUSED;
11481 offset_reloc[2] = BFD_RELOC_UNUSED;
11485 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
11487 if (mips_pic != NO_PIC)
11488 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11489 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11492 /* FIXME: This won't work for a 64 bit address. */
11493 macro_build_lui (&offset_expr, AT);
11497 offset_reloc[0] = BFD_RELOC_LO16;
11498 offset_reloc[1] = BFD_RELOC_UNUSED;
11499 offset_reloc[2] = BFD_RELOC_UNUSED;
11506 * The MIPS assembler seems to check for X_add_number not
11507 * being double aligned and generating:
11508 * lui at,%hi(foo+1)
11510 * addiu at,at,%lo(foo+1)
11513 * But, the resulting address is the same after relocation so why
11514 * generate the extra instruction?
11516 /* Itbl support may require additional care here. */
11519 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11528 gas_assert (!mips_opts.micromips);
11529 /* Itbl support may require additional care here. */
11532 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11552 if (HAVE_64BIT_GPRS)
11562 if (HAVE_64BIT_GPRS)
11570 /* Even on a big endian machine $fn comes before $fn+1. We have
11571 to adjust when loading from memory. We set coproc if we must
11572 load $fn+1 first. */
11573 /* Itbl support may require additional care here. */
11574 if (!target_big_endian)
11578 if (small_offset_p (0, align, 16))
11581 if (!small_offset_p (4, align, 16))
11583 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11584 -1, offset_reloc[0], offset_reloc[1],
11586 expr1.X_add_number = 0;
11590 offset_reloc[0] = BFD_RELOC_LO16;
11591 offset_reloc[1] = BFD_RELOC_UNUSED;
11592 offset_reloc[2] = BFD_RELOC_UNUSED;
11594 if (strcmp (s, "lw") == 0 && op[0] == breg)
11596 ep->X_add_number += 4;
11597 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
11598 offset_reloc[1], offset_reloc[2], breg);
11599 ep->X_add_number -= 4;
11600 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
11601 offset_reloc[1], offset_reloc[2], breg);
11605 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
11606 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11608 ep->X_add_number += 4;
11609 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
11610 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11616 if (offset_expr.X_op != O_symbol
11617 && offset_expr.X_op != O_constant)
11619 as_bad (_("Expression too complex"));
11620 offset_expr.X_op = O_constant;
11623 if (HAVE_32BIT_ADDRESSES
11624 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11628 sprintf_vma (value, offset_expr.X_add_number);
11629 as_bad (_("Number (0x%s) larger than 32 bits"), value);
11632 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
11634 /* If this is a reference to a GP relative symbol, we want
11635 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11636 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11637 If we have a base register, we use this
11639 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11640 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11641 If this is not a GP relative symbol, we want
11642 lui $at,<sym> (BFD_RELOC_HI16_S)
11643 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11644 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11645 If there is a base register, we add it to $at after the
11646 lui instruction. If there is a constant, we always use
11648 if (offset_expr.X_op == O_symbol
11649 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11650 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11652 relax_start (offset_expr.X_add_symbol);
11655 tempreg = mips_gp_register;
11659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11660 AT, breg, mips_gp_register);
11665 /* Itbl support may require additional care here. */
11666 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11667 BFD_RELOC_GPREL16, tempreg);
11668 offset_expr.X_add_number += 4;
11670 /* Set mips_optimize to 2 to avoid inserting an
11672 hold_mips_optimize = mips_optimize;
11674 /* Itbl support may require additional care here. */
11675 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11676 BFD_RELOC_GPREL16, tempreg);
11677 mips_optimize = hold_mips_optimize;
11681 offset_expr.X_add_number -= 4;
11684 if (offset_high_part (offset_expr.X_add_number, 16)
11685 != offset_high_part (offset_expr.X_add_number + 4, 16))
11687 load_address (AT, &offset_expr, &used_at);
11688 offset_expr.X_op = O_constant;
11689 offset_expr.X_add_number = 0;
11692 macro_build_lui (&offset_expr, AT);
11694 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11695 /* Itbl support may require additional care here. */
11696 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11697 BFD_RELOC_LO16, AT);
11698 /* FIXME: How do we handle overflow here? */
11699 offset_expr.X_add_number += 4;
11700 /* Itbl support may require additional care here. */
11701 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11702 BFD_RELOC_LO16, AT);
11703 if (mips_relax.sequence)
11706 else if (!mips_big_got)
11708 /* If this is a reference to an external symbol, we want
11709 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11712 <op> op[0]+1,4($at)
11714 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11716 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11717 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11718 If there is a base register we add it to $at before the
11719 lwc1 instructions. If there is a constant we include it
11720 in the lwc1 instructions. */
11722 expr1.X_add_number = offset_expr.X_add_number;
11723 if (expr1.X_add_number < -0x8000
11724 || expr1.X_add_number >= 0x8000 - 4)
11725 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11726 load_got_offset (AT, &offset_expr);
11729 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11731 /* Set mips_optimize to 2 to avoid inserting an undesired
11733 hold_mips_optimize = mips_optimize;
11736 /* Itbl support may require additional care here. */
11737 relax_start (offset_expr.X_add_symbol);
11738 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11739 BFD_RELOC_LO16, AT);
11740 expr1.X_add_number += 4;
11741 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11742 BFD_RELOC_LO16, AT);
11744 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11745 BFD_RELOC_LO16, AT);
11746 offset_expr.X_add_number += 4;
11747 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11748 BFD_RELOC_LO16, AT);
11751 mips_optimize = hold_mips_optimize;
11753 else if (mips_big_got)
11757 /* If this is a reference to an external symbol, we want
11758 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11760 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11763 <op> op[0]+1,4($at)
11765 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11767 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11768 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11769 If there is a base register we add it to $at before the
11770 lwc1 instructions. If there is a constant we include it
11771 in the lwc1 instructions. */
11773 expr1.X_add_number = offset_expr.X_add_number;
11774 offset_expr.X_add_number = 0;
11775 if (expr1.X_add_number < -0x8000
11776 || expr1.X_add_number >= 0x8000 - 4)
11777 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11778 gpdelay = reg_needs_delay (mips_gp_register);
11779 relax_start (offset_expr.X_add_symbol);
11780 macro_build (&offset_expr, "lui", LUI_FMT,
11781 AT, BFD_RELOC_MIPS_GOT_HI16);
11782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11783 AT, AT, mips_gp_register);
11784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11785 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
11788 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11789 /* Itbl support may require additional care here. */
11790 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11791 BFD_RELOC_LO16, AT);
11792 expr1.X_add_number += 4;
11794 /* Set mips_optimize to 2 to avoid inserting an undesired
11796 hold_mips_optimize = mips_optimize;
11798 /* Itbl support may require additional care here. */
11799 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11800 BFD_RELOC_LO16, AT);
11801 mips_optimize = hold_mips_optimize;
11802 expr1.X_add_number -= 4;
11805 offset_expr.X_add_number = expr1.X_add_number;
11807 macro_build (NULL, "nop", "");
11808 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11809 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11812 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11813 /* Itbl support may require additional care here. */
11814 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11815 BFD_RELOC_LO16, AT);
11816 offset_expr.X_add_number += 4;
11818 /* Set mips_optimize to 2 to avoid inserting an undesired
11820 hold_mips_optimize = mips_optimize;
11822 /* Itbl support may require additional care here. */
11823 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11824 BFD_RELOC_LO16, AT);
11825 mips_optimize = hold_mips_optimize;
11844 /* New code added to support COPZ instructions.
11845 This code builds table entries out of the macros in mip_opcodes.
11846 R4000 uses interlocks to handle coproc delays.
11847 Other chips (like the R3000) require nops to be inserted for delays.
11849 FIXME: Currently, we require that the user handle delays.
11850 In order to fill delay slots for non-interlocked chips,
11851 we must have a way to specify delays based on the coprocessor.
11852 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11853 What are the side-effects of the cop instruction?
11854 What cache support might we have and what are its effects?
11855 Both coprocessor & memory require delays. how long???
11856 What registers are read/set/modified?
11858 If an itbl is provided to interpret cop instructions,
11859 this knowledge can be encoded in the itbl spec. */
11873 gas_assert (!mips_opts.micromips);
11874 /* For now we just do C (same as Cz). The parameter will be
11875 stored in insn_opcode by mips_ip. */
11876 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11880 move_register (op[0], op[1]);
11884 gas_assert (mips_opts.micromips);
11885 gas_assert (mips_opts.insn32);
11886 move_register (micromips_to_32_reg_h_map1[op[0]],
11887 micromips_to_32_reg_m_map[op[1]]);
11888 move_register (micromips_to_32_reg_h_map2[op[0]],
11889 micromips_to_32_reg_n_map[op[2]]);
11895 if (mips_opts.arch == CPU_R5900)
11896 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11900 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11901 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11908 /* The MIPS assembler some times generates shifts and adds. I'm
11909 not trying to be that fancy. GCC should do this for us
11912 load_register (AT, &imm_expr, dbl);
11913 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11914 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11927 start_noreorder ();
11930 load_register (AT, &imm_expr, dbl);
11931 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11932 op[1], imm ? AT : op[2]);
11933 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11934 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
11935 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11937 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
11940 if (mips_opts.micromips)
11941 micromips_label_expr (&label_expr);
11943 label_expr.X_add_number = 8;
11944 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
11945 macro_build (NULL, "nop", "");
11946 macro_build (NULL, "break", BRK_FMT, 6);
11947 if (mips_opts.micromips)
11948 micromips_add_label ();
11951 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11964 start_noreorder ();
11967 load_register (AT, &imm_expr, dbl);
11968 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11969 op[1], imm ? AT : op[2]);
11970 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11971 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11973 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11976 if (mips_opts.micromips)
11977 micromips_label_expr (&label_expr);
11979 label_expr.X_add_number = 8;
11980 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11981 macro_build (NULL, "nop", "");
11982 macro_build (NULL, "break", BRK_FMT, 6);
11983 if (mips_opts.micromips)
11984 micromips_add_label ();
11990 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11992 if (op[0] == op[1])
11999 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12000 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12004 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12005 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12006 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12007 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12011 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12013 if (op[0] == op[1])
12020 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12021 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12025 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12026 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12027 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12028 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12037 if (imm_expr.X_op != O_constant)
12038 as_bad (_("Improper rotate count"));
12039 rot = imm_expr.X_add_number & 0x3f;
12040 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12042 rot = (64 - rot) & 0x3f;
12044 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12046 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12051 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12054 l = (rot < 0x20) ? "dsll" : "dsll32";
12055 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12058 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12059 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12060 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12068 if (imm_expr.X_op != O_constant)
12069 as_bad (_("Improper rotate count"));
12070 rot = imm_expr.X_add_number & 0x1f;
12071 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12073 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12074 (32 - rot) & 0x1f);
12079 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12083 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12084 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12085 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12090 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12092 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12096 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12097 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12098 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12099 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12103 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12105 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12109 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12110 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12111 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12112 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12121 if (imm_expr.X_op != O_constant)
12122 as_bad (_("Improper rotate count"));
12123 rot = imm_expr.X_add_number & 0x3f;
12124 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12127 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12129 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12134 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12137 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12138 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12141 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12142 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12143 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12151 if (imm_expr.X_op != O_constant)
12152 as_bad (_("Improper rotate count"));
12153 rot = imm_expr.X_add_number & 0x1f;
12154 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12156 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12161 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12165 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12166 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12167 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12173 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12174 else if (op[2] == 0)
12175 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12178 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12179 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12186 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12191 as_warn (_("Instruction %s: result is always false"),
12192 ip->insn_mo->name);
12193 move_register (op[0], 0);
12196 if (CPU_HAS_SEQ (mips_opts.arch)
12197 && -512 <= imm_expr.X_add_number
12198 && imm_expr.X_add_number < 512)
12200 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12201 (int) imm_expr.X_add_number);
12204 if (imm_expr.X_op == O_constant
12205 && imm_expr.X_add_number >= 0
12206 && imm_expr.X_add_number < 0x10000)
12207 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12208 else if (imm_expr.X_op == O_constant
12209 && imm_expr.X_add_number > -0x8000
12210 && imm_expr.X_add_number < 0)
12212 imm_expr.X_add_number = -imm_expr.X_add_number;
12213 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12214 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12216 else if (CPU_HAS_SEQ (mips_opts.arch))
12219 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12220 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12225 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12226 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12229 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12232 case M_SGE: /* X >= Y <==> not (X < Y) */
12238 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12239 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12242 case M_SGE_I: /* X >= I <==> not (X < I) */
12244 if (imm_expr.X_op == O_constant
12245 && imm_expr.X_add_number >= -0x8000
12246 && imm_expr.X_add_number < 0x8000)
12247 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12248 op[0], op[1], BFD_RELOC_LO16);
12251 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12252 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12256 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12259 case M_SGT: /* X > Y <==> Y < X */
12265 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12268 case M_SGT_I: /* X > I <==> I < X */
12275 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12276 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12279 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12285 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12286 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12289 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12296 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12297 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12298 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12302 if (imm_expr.X_op == O_constant
12303 && imm_expr.X_add_number >= -0x8000
12304 && imm_expr.X_add_number < 0x8000)
12306 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12311 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12312 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12316 if (imm_expr.X_op == O_constant
12317 && imm_expr.X_add_number >= -0x8000
12318 && imm_expr.X_add_number < 0x8000)
12320 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12325 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12326 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12331 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12332 else if (op[2] == 0)
12333 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12336 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12337 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12344 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12349 as_warn (_("Instruction %s: result is always true"),
12350 ip->insn_mo->name);
12351 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
12352 op[0], 0, BFD_RELOC_LO16);
12355 if (CPU_HAS_SEQ (mips_opts.arch)
12356 && -512 <= imm_expr.X_add_number
12357 && imm_expr.X_add_number < 512)
12359 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
12360 (int) imm_expr.X_add_number);
12363 if (imm_expr.X_op == O_constant
12364 && imm_expr.X_add_number >= 0
12365 && imm_expr.X_add_number < 0x10000)
12367 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12370 else if (imm_expr.X_op == O_constant
12371 && imm_expr.X_add_number > -0x8000
12372 && imm_expr.X_add_number < 0)
12374 imm_expr.X_add_number = -imm_expr.X_add_number;
12375 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12376 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12378 else if (CPU_HAS_SEQ (mips_opts.arch))
12381 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12382 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
12387 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12388 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12391 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12406 if (!mips_opts.micromips)
12408 if (imm_expr.X_op == O_constant
12409 && imm_expr.X_add_number > -0x200
12410 && imm_expr.X_add_number <= 0x200)
12412 macro_build (NULL, s, "t,r,.", op[0], op[1], -imm_expr.X_add_number);
12421 if (imm_expr.X_op == O_constant
12422 && imm_expr.X_add_number > -0x8000
12423 && imm_expr.X_add_number <= 0x8000)
12425 imm_expr.X_add_number = -imm_expr.X_add_number;
12426 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12431 load_register (AT, &imm_expr, dbl);
12432 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
12454 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12455 macro_build (NULL, s, "s,t", op[0], AT);
12460 gas_assert (!mips_opts.micromips);
12461 gas_assert (mips_opts.isa == ISA_MIPS1);
12465 * Is the double cfc1 instruction a bug in the mips assembler;
12466 * or is there a reason for it?
12468 start_noreorder ();
12469 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12470 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12471 macro_build (NULL, "nop", "");
12472 expr1.X_add_number = 3;
12473 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
12474 expr1.X_add_number = 2;
12475 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12476 macro_build (NULL, "ctc1", "t,G", AT, RA);
12477 macro_build (NULL, "nop", "");
12478 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
12480 macro_build (NULL, "ctc1", "t,G", op[2], RA);
12481 macro_build (NULL, "nop", "");
12498 offbits = (mips_opts.micromips ? 12 : 16);
12504 offbits = (mips_opts.micromips ? 12 : 16);
12516 offbits = (mips_opts.micromips ? 12 : 16);
12523 offbits = (mips_opts.micromips ? 12 : 16);
12529 large_offset = !small_offset_p (off, align, offbits);
12531 expr1.X_add_number = 0;
12536 if (small_offset_p (0, align, 16))
12537 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12538 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12541 load_address (tempreg, ep, &used_at);
12543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12544 tempreg, tempreg, breg);
12546 offset_reloc[0] = BFD_RELOC_LO16;
12547 offset_reloc[1] = BFD_RELOC_UNUSED;
12548 offset_reloc[2] = BFD_RELOC_UNUSED;
12553 else if (!ust && op[0] == breg)
12564 if (!target_big_endian)
12565 ep->X_add_number += off;
12567 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
12569 macro_build (ep, s, "t,o(b)", tempreg, -1,
12570 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12572 if (!target_big_endian)
12573 ep->X_add_number -= off;
12575 ep->X_add_number += off;
12577 macro_build (NULL, s2, "t,~(b)",
12578 tempreg, (int) ep->X_add_number, breg);
12580 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12581 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12583 /* If necessary, move the result in tempreg to the final destination. */
12584 if (!ust && op[0] != tempreg)
12586 /* Protect second load's delay slot. */
12588 move_register (op[0], tempreg);
12594 if (target_big_endian == ust)
12595 ep->X_add_number += off;
12596 tempreg = ust || large_offset ? op[0] : AT;
12597 macro_build (ep, s, "t,o(b)", tempreg, -1,
12598 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12600 /* For halfword transfers we need a temporary register to shuffle
12601 bytes. Unfortunately for M_USH_A we have none available before
12602 the next store as AT holds the base address. We deal with this
12603 case by clobbering TREG and then restoring it as with ULH. */
12604 tempreg = ust == large_offset ? op[0] : AT;
12606 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
12608 if (target_big_endian == ust)
12609 ep->X_add_number -= off;
12611 ep->X_add_number += off;
12612 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12613 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12615 /* For M_USH_A re-retrieve the LSB. */
12616 if (ust && large_offset)
12618 if (target_big_endian)
12619 ep->X_add_number += off;
12621 ep->X_add_number -= off;
12622 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12623 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
12625 /* For ULH and M_USH_A OR the LSB in. */
12626 if (!ust || large_offset)
12628 tempreg = !large_offset ? AT : op[0];
12629 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
12630 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12635 /* FIXME: Check if this is one of the itbl macros, since they
12636 are added dynamically. */
12637 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
12640 if (!mips_opts.at && used_at)
12641 as_bad (_("Macro used $at after \".set noat\""));
12644 /* Implement macros in mips16 mode. */
12647 mips16_macro (struct mips_cl_insn *ip)
12649 const struct mips_operand_array *operands;
12654 const char *s, *s2, *s3;
12655 unsigned int op[MAX_OPERANDS];
12658 mask = ip->insn_mo->mask;
12660 operands = insn_operands (ip);
12661 for (i = 0; i < MAX_OPERANDS; i++)
12662 if (operands->operand[i])
12663 op[i] = insn_extract_operand (ip, operands->operand[i]);
12667 expr1.X_op = O_constant;
12668 expr1.X_op_symbol = NULL;
12669 expr1.X_add_symbol = NULL;
12670 expr1.X_add_number = 1;
12689 start_noreorder ();
12690 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
12691 expr1.X_add_number = 2;
12692 macro_build (&expr1, "bnez", "x,p", op[2]);
12693 macro_build (NULL, "break", "6", 7);
12695 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12696 since that causes an overflow. We should do that as well,
12697 but I don't see how to do the comparisons without a temporary
12700 macro_build (NULL, s, "x", op[0]);
12719 start_noreorder ();
12720 macro_build (NULL, s, "0,x,y", op[1], op[2]);
12721 expr1.X_add_number = 2;
12722 macro_build (&expr1, "bnez", "x,p", op[2]);
12723 macro_build (NULL, "break", "6", 7);
12725 macro_build (NULL, s2, "x", op[0]);
12731 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12732 macro_build (NULL, "mflo", "x", op[0]);
12740 if (imm_expr.X_op != O_constant)
12741 as_bad (_("Unsupported large constant"));
12742 imm_expr.X_add_number = -imm_expr.X_add_number;
12743 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
12747 if (imm_expr.X_op != O_constant)
12748 as_bad (_("Unsupported large constant"));
12749 imm_expr.X_add_number = -imm_expr.X_add_number;
12750 macro_build (&imm_expr, "addiu", "x,k", op[0]);
12754 if (imm_expr.X_op != O_constant)
12755 as_bad (_("Unsupported large constant"));
12756 imm_expr.X_add_number = -imm_expr.X_add_number;
12757 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
12779 goto do_reverse_branch;
12783 goto do_reverse_branch;
12795 goto do_reverse_branch;
12806 macro_build (NULL, s, "x,y", op[0], op[1]);
12807 macro_build (&offset_expr, s2, "p");
12834 goto do_addone_branch_i;
12839 goto do_addone_branch_i;
12854 goto do_addone_branch_i;
12860 do_addone_branch_i:
12861 if (imm_expr.X_op != O_constant)
12862 as_bad (_("Unsupported large constant"));
12863 ++imm_expr.X_add_number;
12866 macro_build (&imm_expr, s, s3, op[0]);
12867 macro_build (&offset_expr, s2, "p");
12871 expr1.X_add_number = 0;
12872 macro_build (&expr1, "slti", "x,8", op[1]);
12873 if (op[0] != op[1])
12874 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
12875 expr1.X_add_number = 2;
12876 macro_build (&expr1, "bteqz", "p");
12877 macro_build (NULL, "neg", "x,w", op[0], op[0]);
12882 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12883 opcode bits in *OPCODE_EXTRA. */
12885 static struct mips_opcode *
12886 mips_lookup_insn (struct hash_control *hash, const char *start,
12887 ssize_t length, unsigned int *opcode_extra)
12889 char *name, *dot, *p;
12890 unsigned int mask, suffix;
12892 struct mips_opcode *insn;
12894 /* Make a copy of the instruction so that we can fiddle with it. */
12895 name = alloca (length + 1);
12896 memcpy (name, start, length);
12897 name[length] = '\0';
12899 /* Look up the instruction as-is. */
12900 insn = (struct mips_opcode *) hash_find (hash, name);
12904 dot = strchr (name, '.');
12907 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12908 p = mips_parse_vu0_channels (dot + 1, &mask);
12909 if (*p == 0 && mask != 0)
12912 insn = (struct mips_opcode *) hash_find (hash, name);
12914 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12916 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12922 if (mips_opts.micromips)
12924 /* See if there's an instruction size override suffix,
12925 either `16' or `32', at the end of the mnemonic proper,
12926 that defines the operation, i.e. before the first `.'
12927 character if any. Strip it and retry. */
12928 opend = dot != NULL ? dot - name : length;
12929 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12931 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12937 memcpy (name + opend - 2, name + opend, length - opend + 1);
12938 insn = (struct mips_opcode *) hash_find (hash, name);
12941 forced_insn_length = suffix;
12950 /* Assemble an instruction into its binary format. If the instruction
12951 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12952 associated with "I", "+I" and "A" operands respectively. Otherwise
12953 store the value of the relocatable field (if any) in offset_expr.
12954 In both cases set offset_reloc to the relocation operators applied
12958 mips_ip (char *str, struct mips_cl_insn *ip)
12960 bfd_boolean wrong_delay_slot_insns = FALSE;
12961 bfd_boolean need_delay_slot_ok = TRUE;
12962 struct mips_opcode *firstinsn = NULL;
12963 const struct mips_opcode *past;
12964 struct hash_control *hash;
12965 struct mips_opcode *first, *insn;
12968 struct mips_operand_token *tokens;
12969 unsigned int opcode_extra;
12971 if (mips_opts.micromips)
12973 hash = micromips_op_hash;
12974 past = µmips_opcodes[bfd_micromips_num_opcodes];
12979 past = &mips_opcodes[NUMOPCODES];
12981 forced_insn_length = 0;
12985 /* We first try to match an instruction up to a space or to the end. */
12986 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12989 first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
12992 set_insn_error (0, _("Unrecognized opcode"));
12995 /* When no opcode suffix is specified, assume ".xyzw". */
12996 if ((insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
12997 opcode_extra = 0xf << mips_vu0_channel_mask.lsb;
12999 if (strcmp (insn->name, "li.s") == 0)
13001 else if (strcmp (insn->name, "li.d") == 0)
13005 tokens = mips_parse_arguments (str + end, format);
13009 /* For microMIPS instructions placed in a fixed-length branch delay slot
13010 we make up to two passes over the relevant fragment of the opcode
13011 table. First we try instructions that meet the delay slot's length
13012 requirement. If none matched, then we retry with the remaining ones
13013 and if one matches, then we use it and then issue an appropriate
13014 warning later on. */
13017 bfd_boolean delay_slot_ok;
13018 bfd_boolean size_ok;
13020 bfd_boolean more_alts;
13022 gas_assert (strcmp (insn->name, first->name) == 0);
13024 ok = is_opcode_valid (insn);
13025 size_ok = is_size_valid (insn);
13026 delay_slot_ok = is_delay_slot_valid (insn);
13027 if (!delay_slot_ok && !wrong_delay_slot_insns)
13030 wrong_delay_slot_insns = TRUE;
13032 more_alts = (insn + 1 < past
13033 && strcmp (insn[0].name, insn[1].name) == 0);
13034 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
13041 if (wrong_delay_slot_insns && need_delay_slot_ok)
13043 gas_assert (firstinsn);
13044 need_delay_slot_ok = FALSE;
13052 (0, _("Opcode not supported on this processor: %s (%s)"),
13053 mips_cpu_info_from_arch (mips_opts.arch)->name,
13054 mips_cpu_info_from_isa (mips_opts.isa)->name);
13055 else if (mips_opts.insn32)
13057 (0, _("Opcode not supported in the `insn32' mode"));
13060 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
13061 8 * forced_insn_length);
13065 if (match_insn (ip, insn, tokens, opcode_extra,
13066 more_alts || (wrong_delay_slot_insns
13067 && need_delay_slot_ok)))
13070 /* Args don't match. */
13071 set_insn_error (0, _("Illegal operands"));
13077 if (wrong_delay_slot_insns && need_delay_slot_ok)
13079 gas_assert (firstinsn);
13080 need_delay_slot_ok = FALSE;
13087 obstack_free (&mips_operand_tokens, tokens);
13090 /* As for mips_ip, but used when assembling MIPS16 code.
13091 Also set forced_insn_length to the resulting instruction size in
13092 bytes if the user explicitly requested a small or extended instruction. */
13095 mips16_ip (char *str, struct mips_cl_insn *ip)
13098 struct mips_opcode *insn, *first;
13099 struct mips_operand_token *tokens;
13101 forced_insn_length = 0;
13103 for (s = str; ISLOWER (*s); ++s)
13117 if (s[1] == 't' && s[2] == ' ')
13119 forced_insn_length = 2;
13123 else if (s[1] == 'e' && s[2] == ' ')
13125 forced_insn_length = 4;
13129 /* Fall through. */
13131 set_insn_error (0, _("Unrecognized opcode"));
13135 if (mips_opts.noautoextend && !forced_insn_length)
13136 forced_insn_length = 2;
13139 first = insn = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13144 set_insn_error (0, _("Unrecognized opcode"));
13148 tokens = mips_parse_arguments (s, 0);
13155 bfd_boolean more_alts;
13157 gas_assert (strcmp (insn->name, first->name) == 0);
13159 ok = is_opcode_valid_16 (insn);
13160 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13161 && strcmp (insn[0].name, insn[1].name) == 0);
13172 (0, _("Opcode not supported on this processor: %s (%s)"),
13173 mips_cpu_info_from_arch (mips_opts.arch)->name,
13174 mips_cpu_info_from_isa (mips_opts.isa)->name);
13179 if (match_mips16_insn (ip, insn, tokens))
13182 /* Args don't match. */
13183 set_insn_error (0, _("Illegal operands"));
13191 obstack_free (&mips_operand_tokens, tokens);
13194 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13195 NBITS is the number of significant bits in VAL. */
13197 static unsigned long
13198 mips16_immed_extend (offsetT val, unsigned int nbits)
13203 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13206 else if (nbits == 15)
13208 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13213 extval = ((val & 0x1f) << 6) | (val & 0x20);
13216 return (extval << 16) | val;
13219 /* Like decode_mips16_operand, but require the operand to be defined and
13220 require it to be an integer. */
13222 static const struct mips_int_operand *
13223 mips16_immed_operand (int type, bfd_boolean extended_p)
13225 const struct mips_operand *operand;
13227 operand = decode_mips16_operand (type, extended_p);
13228 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13230 return (const struct mips_int_operand *) operand;
13233 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13236 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13237 bfd_reloc_code_real_type reloc, offsetT sval)
13239 int min_val, max_val;
13241 min_val = mips_int_operand_min (operand);
13242 max_val = mips_int_operand_max (operand);
13243 if (reloc != BFD_RELOC_UNUSED)
13246 sval = SEXT_16BIT (sval);
13251 return (sval >= min_val
13253 && (sval & ((1 << operand->shift) - 1)) == 0);
13256 /* Install immediate value VAL into MIPS16 instruction *INSN,
13257 extending it if necessary. The instruction in *INSN may
13258 already be extended.
13260 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13261 if none. In the former case, VAL is a 16-bit number with no
13262 defined signedness.
13264 TYPE is the type of the immediate field. USER_INSN_LENGTH
13265 is the length that the user requested, or 0 if none. */
13268 mips16_immed (char *file, unsigned int line, int type,
13269 bfd_reloc_code_real_type reloc, offsetT val,
13270 unsigned int user_insn_length, unsigned long *insn)
13272 const struct mips_int_operand *operand;
13273 unsigned int uval, length;
13275 operand = mips16_immed_operand (type, FALSE);
13276 if (!mips16_immed_in_range_p (operand, reloc, val))
13278 /* We need an extended instruction. */
13279 if (user_insn_length == 2)
13280 as_bad_where (file, line, _("invalid unextended operand value"));
13282 *insn |= MIPS16_EXTEND;
13284 else if (user_insn_length == 4)
13286 /* The operand doesn't force an unextended instruction to be extended.
13287 Warn if the user wanted an extended instruction anyway. */
13288 *insn |= MIPS16_EXTEND;
13289 as_warn_where (file, line,
13290 _("extended operand requested but not required"));
13293 length = mips16_opcode_length (*insn);
13296 operand = mips16_immed_operand (type, TRUE);
13297 if (!mips16_immed_in_range_p (operand, reloc, val))
13298 as_bad_where (file, line,
13299 _("operand value out of range for instruction"));
13301 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13303 *insn = mips_insert_operand (&operand->root, *insn, uval);
13305 *insn |= mips16_immed_extend (uval, operand->root.size);
13308 struct percent_op_match
13311 bfd_reloc_code_real_type reloc;
13314 static const struct percent_op_match mips_percent_op[] =
13316 {"%lo", BFD_RELOC_LO16},
13317 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13318 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13319 {"%call16", BFD_RELOC_MIPS_CALL16},
13320 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13321 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13322 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13323 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13324 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13325 {"%got", BFD_RELOC_MIPS_GOT16},
13326 {"%gp_rel", BFD_RELOC_GPREL16},
13327 {"%half", BFD_RELOC_16},
13328 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13329 {"%higher", BFD_RELOC_MIPS_HIGHER},
13330 {"%neg", BFD_RELOC_MIPS_SUB},
13331 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13332 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13333 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13334 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13335 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13336 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13337 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13338 {"%hi", BFD_RELOC_HI16_S}
13341 static const struct percent_op_match mips16_percent_op[] =
13343 {"%lo", BFD_RELOC_MIPS16_LO16},
13344 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13345 {"%got", BFD_RELOC_MIPS16_GOT16},
13346 {"%call16", BFD_RELOC_MIPS16_CALL16},
13347 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13348 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13349 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13350 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13351 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13352 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13353 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13354 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13358 /* Return true if *STR points to a relocation operator. When returning true,
13359 move *STR over the operator and store its relocation code in *RELOC.
13360 Leave both *STR and *RELOC alone when returning false. */
13363 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13365 const struct percent_op_match *percent_op;
13368 if (mips_opts.mips16)
13370 percent_op = mips16_percent_op;
13371 limit = ARRAY_SIZE (mips16_percent_op);
13375 percent_op = mips_percent_op;
13376 limit = ARRAY_SIZE (mips_percent_op);
13379 for (i = 0; i < limit; i++)
13380 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13382 int len = strlen (percent_op[i].str);
13384 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13387 *str += strlen (percent_op[i].str);
13388 *reloc = percent_op[i].reloc;
13390 /* Check whether the output BFD supports this relocation.
13391 If not, issue an error and fall back on something safe. */
13392 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13394 as_bad (_("relocation %s isn't supported by the current ABI"),
13395 percent_op[i].str);
13396 *reloc = BFD_RELOC_UNUSED;
13404 /* Parse string STR as a 16-bit relocatable operand. Store the
13405 expression in *EP and the relocations in the array starting
13406 at RELOC. Return the number of relocation operators used.
13408 On exit, EXPR_END points to the first character after the expression. */
13411 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13414 bfd_reloc_code_real_type reversed_reloc[3];
13415 size_t reloc_index, i;
13416 int crux_depth, str_depth;
13419 /* Search for the start of the main expression, recoding relocations
13420 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13421 of the main expression and with CRUX_DEPTH containing the number
13422 of open brackets at that point. */
13429 crux_depth = str_depth;
13431 /* Skip over whitespace and brackets, keeping count of the number
13433 while (*str == ' ' || *str == '\t' || *str == '(')
13438 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13439 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13441 my_getExpression (ep, crux);
13444 /* Match every open bracket. */
13445 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13449 if (crux_depth > 0)
13450 as_bad (_("unclosed '('"));
13454 if (reloc_index != 0)
13456 prev_reloc_op_frag = frag_now;
13457 for (i = 0; i < reloc_index; i++)
13458 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13461 return reloc_index;
13465 my_getExpression (expressionS *ep, char *str)
13469 save_in = input_line_pointer;
13470 input_line_pointer = str;
13472 expr_end = input_line_pointer;
13473 input_line_pointer = save_in;
13477 md_atof (int type, char *litP, int *sizeP)
13479 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13483 md_number_to_chars (char *buf, valueT val, int n)
13485 if (target_big_endian)
13486 number_to_chars_bigendian (buf, val, n);
13488 number_to_chars_littleendian (buf, val, n);
13491 static int support_64bit_objects(void)
13493 const char **list, **l;
13496 list = bfd_target_list ();
13497 for (l = list; *l != NULL; l++)
13498 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13499 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13501 yes = (*l != NULL);
13506 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13507 NEW_VALUE. Warn if another value was already specified. Note:
13508 we have to defer parsing the -march and -mtune arguments in order
13509 to handle 'from-abi' correctly, since the ABI might be specified
13510 in a later argument. */
13513 mips_set_option_string (const char **string_ptr, const char *new_value)
13515 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13516 as_warn (_("A different %s was already specified, is now %s"),
13517 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13520 *string_ptr = new_value;
13524 md_parse_option (int c, char *arg)
13528 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13529 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13531 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13532 c == mips_ases[i].option_on);
13538 case OPTION_CONSTRUCT_FLOATS:
13539 mips_disable_float_construction = 0;
13542 case OPTION_NO_CONSTRUCT_FLOATS:
13543 mips_disable_float_construction = 1;
13555 target_big_endian = 1;
13559 target_big_endian = 0;
13565 else if (arg[0] == '0')
13567 else if (arg[0] == '1')
13577 mips_debug = atoi (arg);
13581 file_mips_isa = ISA_MIPS1;
13585 file_mips_isa = ISA_MIPS2;
13589 file_mips_isa = ISA_MIPS3;
13593 file_mips_isa = ISA_MIPS4;
13597 file_mips_isa = ISA_MIPS5;
13600 case OPTION_MIPS32:
13601 file_mips_isa = ISA_MIPS32;
13604 case OPTION_MIPS32R2:
13605 file_mips_isa = ISA_MIPS32R2;
13608 case OPTION_MIPS64R2:
13609 file_mips_isa = ISA_MIPS64R2;
13612 case OPTION_MIPS64:
13613 file_mips_isa = ISA_MIPS64;
13617 mips_set_option_string (&mips_tune_string, arg);
13621 mips_set_option_string (&mips_arch_string, arg);
13625 mips_set_option_string (&mips_arch_string, "4650");
13626 mips_set_option_string (&mips_tune_string, "4650");
13629 case OPTION_NO_M4650:
13633 mips_set_option_string (&mips_arch_string, "4010");
13634 mips_set_option_string (&mips_tune_string, "4010");
13637 case OPTION_NO_M4010:
13641 mips_set_option_string (&mips_arch_string, "4100");
13642 mips_set_option_string (&mips_tune_string, "4100");
13645 case OPTION_NO_M4100:
13649 mips_set_option_string (&mips_arch_string, "3900");
13650 mips_set_option_string (&mips_tune_string, "3900");
13653 case OPTION_NO_M3900:
13656 case OPTION_MICROMIPS:
13657 if (mips_opts.mips16 == 1)
13659 as_bad (_("-mmicromips cannot be used with -mips16"));
13662 mips_opts.micromips = 1;
13663 mips_no_prev_insn ();
13666 case OPTION_NO_MICROMIPS:
13667 mips_opts.micromips = 0;
13668 mips_no_prev_insn ();
13671 case OPTION_MIPS16:
13672 if (mips_opts.micromips == 1)
13674 as_bad (_("-mips16 cannot be used with -micromips"));
13677 mips_opts.mips16 = 1;
13678 mips_no_prev_insn ();
13681 case OPTION_NO_MIPS16:
13682 mips_opts.mips16 = 0;
13683 mips_no_prev_insn ();
13686 case OPTION_FIX_24K:
13690 case OPTION_NO_FIX_24K:
13694 case OPTION_FIX_LOONGSON2F_JUMP:
13695 mips_fix_loongson2f_jump = TRUE;
13698 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13699 mips_fix_loongson2f_jump = FALSE;
13702 case OPTION_FIX_LOONGSON2F_NOP:
13703 mips_fix_loongson2f_nop = TRUE;
13706 case OPTION_NO_FIX_LOONGSON2F_NOP:
13707 mips_fix_loongson2f_nop = FALSE;
13710 case OPTION_FIX_VR4120:
13711 mips_fix_vr4120 = 1;
13714 case OPTION_NO_FIX_VR4120:
13715 mips_fix_vr4120 = 0;
13718 case OPTION_FIX_VR4130:
13719 mips_fix_vr4130 = 1;
13722 case OPTION_NO_FIX_VR4130:
13723 mips_fix_vr4130 = 0;
13726 case OPTION_FIX_CN63XXP1:
13727 mips_fix_cn63xxp1 = TRUE;
13730 case OPTION_NO_FIX_CN63XXP1:
13731 mips_fix_cn63xxp1 = FALSE;
13734 case OPTION_RELAX_BRANCH:
13735 mips_relax_branch = 1;
13738 case OPTION_NO_RELAX_BRANCH:
13739 mips_relax_branch = 0;
13742 case OPTION_INSN32:
13743 mips_opts.insn32 = TRUE;
13746 case OPTION_NO_INSN32:
13747 mips_opts.insn32 = FALSE;
13750 case OPTION_MSHARED:
13751 mips_in_shared = TRUE;
13754 case OPTION_MNO_SHARED:
13755 mips_in_shared = FALSE;
13758 case OPTION_MSYM32:
13759 mips_opts.sym32 = TRUE;
13762 case OPTION_MNO_SYM32:
13763 mips_opts.sym32 = FALSE;
13766 /* When generating ELF code, we permit -KPIC and -call_shared to
13767 select SVR4_PIC, and -non_shared to select no PIC. This is
13768 intended to be compatible with Irix 5. */
13769 case OPTION_CALL_SHARED:
13770 mips_pic = SVR4_PIC;
13771 mips_abicalls = TRUE;
13774 case OPTION_CALL_NONPIC:
13776 mips_abicalls = TRUE;
13779 case OPTION_NON_SHARED:
13781 mips_abicalls = FALSE;
13784 /* The -xgot option tells the assembler to use 32 bit offsets
13785 when accessing the got in SVR4_PIC mode. It is for Irix
13792 g_switch_value = atoi (arg);
13796 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13799 mips_abi = O32_ABI;
13803 mips_abi = N32_ABI;
13807 mips_abi = N64_ABI;
13808 if (!support_64bit_objects())
13809 as_fatal (_("No compiled in support for 64 bit object file format"));
13813 file_mips_gp32 = 1;
13817 file_mips_gp32 = 0;
13821 file_mips_fp32 = 1;
13825 file_mips_fp32 = 0;
13828 case OPTION_SINGLE_FLOAT:
13829 file_mips_single_float = 1;
13832 case OPTION_DOUBLE_FLOAT:
13833 file_mips_single_float = 0;
13836 case OPTION_SOFT_FLOAT:
13837 file_mips_soft_float = 1;
13840 case OPTION_HARD_FLOAT:
13841 file_mips_soft_float = 0;
13845 if (strcmp (arg, "32") == 0)
13846 mips_abi = O32_ABI;
13847 else if (strcmp (arg, "o64") == 0)
13848 mips_abi = O64_ABI;
13849 else if (strcmp (arg, "n32") == 0)
13850 mips_abi = N32_ABI;
13851 else if (strcmp (arg, "64") == 0)
13853 mips_abi = N64_ABI;
13854 if (! support_64bit_objects())
13855 as_fatal (_("No compiled in support for 64 bit object file "
13858 else if (strcmp (arg, "eabi") == 0)
13859 mips_abi = EABI_ABI;
13862 as_fatal (_("invalid abi -mabi=%s"), arg);
13867 case OPTION_M7000_HILO_FIX:
13868 mips_7000_hilo_fix = TRUE;
13871 case OPTION_MNO_7000_HILO_FIX:
13872 mips_7000_hilo_fix = FALSE;
13875 case OPTION_MDEBUG:
13876 mips_flag_mdebug = TRUE;
13879 case OPTION_NO_MDEBUG:
13880 mips_flag_mdebug = FALSE;
13884 mips_flag_pdr = TRUE;
13887 case OPTION_NO_PDR:
13888 mips_flag_pdr = FALSE;
13891 case OPTION_MVXWORKS_PIC:
13892 mips_pic = VXWORKS_PIC;
13896 if (strcmp (arg, "2008") == 0)
13897 mips_flag_nan2008 = TRUE;
13898 else if (strcmp (arg, "legacy") == 0)
13899 mips_flag_nan2008 = FALSE;
13902 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13911 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13916 /* Set up globals to generate code for the ISA or processor
13917 described by INFO. */
13920 mips_set_architecture (const struct mips_cpu_info *info)
13924 file_mips_arch = info->cpu;
13925 mips_opts.arch = info->cpu;
13926 mips_opts.isa = info->isa;
13931 /* Likewise for tuning. */
13934 mips_set_tune (const struct mips_cpu_info *info)
13937 mips_tune = info->cpu;
13942 mips_after_parse_args (void)
13944 const struct mips_cpu_info *arch_info = 0;
13945 const struct mips_cpu_info *tune_info = 0;
13947 /* GP relative stuff not working for PE */
13948 if (strncmp (TARGET_OS, "pe", 2) == 0)
13950 if (g_switch_seen && g_switch_value != 0)
13951 as_bad (_("-G not supported in this configuration."));
13952 g_switch_value = 0;
13955 if (mips_abi == NO_ABI)
13956 mips_abi = MIPS_DEFAULT_ABI;
13958 /* The following code determines the architecture and register size.
13959 Similar code was added to GCC 3.3 (see override_options() in
13960 config/mips/mips.c). The GAS and GCC code should be kept in sync
13961 as much as possible. */
13963 if (mips_arch_string != 0)
13964 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13966 if (file_mips_isa != ISA_UNKNOWN)
13968 /* Handle -mipsN. At this point, file_mips_isa contains the
13969 ISA level specified by -mipsN, while arch_info->isa contains
13970 the -march selection (if any). */
13971 if (arch_info != 0)
13973 /* -march takes precedence over -mipsN, since it is more descriptive.
13974 There's no harm in specifying both as long as the ISA levels
13976 if (file_mips_isa != arch_info->isa)
13977 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13978 mips_cpu_info_from_isa (file_mips_isa)->name,
13979 mips_cpu_info_from_isa (arch_info->isa)->name);
13982 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13985 if (arch_info == 0)
13987 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13988 gas_assert (arch_info);
13991 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13992 as_bad (_("-march=%s is not compatible with the selected ABI"),
13995 mips_set_architecture (arch_info);
13997 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13998 if (mips_tune_string != 0)
13999 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14001 if (tune_info == 0)
14002 mips_set_tune (arch_info);
14004 mips_set_tune (tune_info);
14006 if (file_mips_gp32 >= 0)
14008 /* The user specified the size of the integer registers. Make sure
14009 it agrees with the ABI and ISA. */
14010 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14011 as_bad (_("-mgp64 used with a 32-bit processor"));
14012 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14013 as_bad (_("-mgp32 used with a 64-bit ABI"));
14014 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14015 as_bad (_("-mgp64 used with a 32-bit ABI"));
14019 /* Infer the integer register size from the ABI and processor.
14020 Restrict ourselves to 32-bit registers if that's all the
14021 processor has, or if the ABI cannot handle 64-bit registers. */
14022 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14023 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14026 switch (file_mips_fp32)
14030 /* No user specified float register size.
14031 ??? GAS treats single-float processors as though they had 64-bit
14032 float registers (although it complains when double-precision
14033 instructions are used). As things stand, saying they have 32-bit
14034 registers would lead to spurious "register must be even" messages.
14035 So here we assume float registers are never smaller than the
14037 if (file_mips_gp32 == 0)
14038 /* 64-bit integer registers implies 64-bit float registers. */
14039 file_mips_fp32 = 0;
14040 else if ((mips_opts.ase & FP64_ASES)
14041 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14042 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14043 file_mips_fp32 = 0;
14045 /* 32-bit float registers. */
14046 file_mips_fp32 = 1;
14049 /* The user specified the size of the float registers. Check if it
14050 agrees with the ABI and ISA. */
14052 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14053 as_bad (_("-mfp64 used with a 32-bit fpu"));
14054 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14055 && !ISA_HAS_MXHC1 (mips_opts.isa))
14056 as_warn (_("-mfp64 used with a 32-bit ABI"));
14059 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14060 as_warn (_("-mfp32 used with a 64-bit ABI"));
14064 /* End of GCC-shared inference code. */
14066 /* This flag is set when we have a 64-bit capable CPU but use only
14067 32-bit wide registers. Note that EABI does not use it. */
14068 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14069 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14070 || mips_abi == O32_ABI))
14071 mips_32bitmode = 1;
14073 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14074 as_bad (_("trap exception not supported at ISA 1"));
14076 /* If the selected architecture includes support for ASEs, enable
14077 generation of code for them. */
14078 if (mips_opts.mips16 == -1)
14079 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
14080 if (mips_opts.micromips == -1)
14081 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
14083 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14084 ASEs from being selected implicitly. */
14085 if (file_mips_fp32 == 1)
14086 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
14088 /* If the user didn't explicitly select or deselect a particular ASE,
14089 use the default setting for the CPU. */
14090 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
14092 file_mips_isa = mips_opts.isa;
14093 file_ase = mips_opts.ase;
14094 mips_opts.gp32 = file_mips_gp32;
14095 mips_opts.fp32 = file_mips_fp32;
14096 mips_opts.soft_float = file_mips_soft_float;
14097 mips_opts.single_float = file_mips_single_float;
14099 mips_check_isa_supports_ases ();
14101 if (mips_flag_mdebug < 0)
14102 mips_flag_mdebug = 0;
14106 mips_init_after_args (void)
14108 /* initialize opcodes */
14109 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14110 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14114 md_pcrel_from (fixS *fixP)
14116 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14117 switch (fixP->fx_r_type)
14119 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14120 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14121 /* Return the address of the delay slot. */
14124 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14125 case BFD_RELOC_MICROMIPS_JMP:
14126 case BFD_RELOC_16_PCREL_S2:
14127 case BFD_RELOC_MIPS_JMP:
14128 /* Return the address of the delay slot. */
14131 case BFD_RELOC_32_PCREL:
14135 /* We have no relocation type for PC relative MIPS16 instructions. */
14136 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14137 as_bad_where (fixP->fx_file, fixP->fx_line,
14138 _("PC relative MIPS16 instruction references a different section"));
14143 /* This is called before the symbol table is processed. In order to
14144 work with gcc when using mips-tfile, we must keep all local labels.
14145 However, in other cases, we want to discard them. If we were
14146 called with -g, but we didn't see any debugging information, it may
14147 mean that gcc is smuggling debugging information through to
14148 mips-tfile, in which case we must generate all local labels. */
14151 mips_frob_file_before_adjust (void)
14153 #ifndef NO_ECOFF_DEBUGGING
14154 if (ECOFF_DEBUGGING
14156 && ! ecoff_debugging_seen)
14157 flag_keep_locals = 1;
14161 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14162 the corresponding LO16 reloc. This is called before md_apply_fix and
14163 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14164 relocation operators.
14166 For our purposes, a %lo() expression matches a %got() or %hi()
14169 (a) it refers to the same symbol; and
14170 (b) the offset applied in the %lo() expression is no lower than
14171 the offset applied in the %got() or %hi().
14173 (b) allows us to cope with code like:
14176 lh $4,%lo(foo+2)($4)
14178 ...which is legal on RELA targets, and has a well-defined behaviour
14179 if the user knows that adding 2 to "foo" will not induce a carry to
14182 When several %lo()s match a particular %got() or %hi(), we use the
14183 following rules to distinguish them:
14185 (1) %lo()s with smaller offsets are a better match than %lo()s with
14188 (2) %lo()s with no matching %got() or %hi() are better than those
14189 that already have a matching %got() or %hi().
14191 (3) later %lo()s are better than earlier %lo()s.
14193 These rules are applied in order.
14195 (1) means, among other things, that %lo()s with identical offsets are
14196 chosen if they exist.
14198 (2) means that we won't associate several high-part relocations with
14199 the same low-part relocation unless there's no alternative. Having
14200 several high parts for the same low part is a GNU extension; this rule
14201 allows careful users to avoid it.
14203 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14204 with the last high-part relocation being at the front of the list.
14205 It therefore makes sense to choose the last matching low-part
14206 relocation, all other things being equal. It's also easier
14207 to code that way. */
14210 mips_frob_file (void)
14212 struct mips_hi_fixup *l;
14213 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14215 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14217 segment_info_type *seginfo;
14218 bfd_boolean matched_lo_p;
14219 fixS **hi_pos, **lo_pos, **pos;
14221 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14223 /* If a GOT16 relocation turns out to be against a global symbol,
14224 there isn't supposed to be a matching LO. Ignore %gots against
14225 constants; we'll report an error for those later. */
14226 if (got16_reloc_p (l->fixp->fx_r_type)
14227 && !(l->fixp->fx_addsy
14228 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14231 /* Check quickly whether the next fixup happens to be a matching %lo. */
14232 if (fixup_has_matching_lo_p (l->fixp))
14235 seginfo = seg_info (l->seg);
14237 /* Set HI_POS to the position of this relocation in the chain.
14238 Set LO_POS to the position of the chosen low-part relocation.
14239 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14240 relocation that matches an immediately-preceding high-part
14244 matched_lo_p = FALSE;
14245 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14247 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14249 if (*pos == l->fixp)
14252 if ((*pos)->fx_r_type == looking_for_rtype
14253 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14254 && (*pos)->fx_offset >= l->fixp->fx_offset
14256 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14258 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14261 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14262 && fixup_has_matching_lo_p (*pos));
14265 /* If we found a match, remove the high-part relocation from its
14266 current position and insert it before the low-part relocation.
14267 Make the offsets match so that fixup_has_matching_lo_p()
14270 We don't warn about unmatched high-part relocations since some
14271 versions of gcc have been known to emit dead "lui ...%hi(...)"
14273 if (lo_pos != NULL)
14275 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14276 if (l->fixp->fx_next != *lo_pos)
14278 *hi_pos = l->fixp->fx_next;
14279 l->fixp->fx_next = *lo_pos;
14287 mips_force_relocation (fixS *fixp)
14289 if (generic_force_reloc (fixp))
14292 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14293 so that the linker relaxation can update targets. */
14294 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14295 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14296 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14302 /* Read the instruction associated with RELOC from BUF. */
14304 static unsigned int
14305 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14307 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14308 return read_compressed_insn (buf, 4);
14310 return read_insn (buf);
14313 /* Write instruction INSN to BUF, given that it has been relocated
14317 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14318 unsigned long insn)
14320 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14321 write_compressed_insn (buf, insn, 4);
14323 write_insn (buf, insn);
14326 /* Apply a fixup to the object file. */
14329 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14332 unsigned long insn;
14333 reloc_howto_type *howto;
14335 /* We ignore generic BFD relocations we don't know about. */
14336 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14340 gas_assert (fixP->fx_size == 2
14341 || fixP->fx_size == 4
14342 || fixP->fx_r_type == BFD_RELOC_16
14343 || fixP->fx_r_type == BFD_RELOC_64
14344 || fixP->fx_r_type == BFD_RELOC_CTOR
14345 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14346 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14347 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14348 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14349 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
14351 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14353 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14354 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14355 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14356 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14357 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
14359 /* Don't treat parts of a composite relocation as done. There are two
14362 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14363 should nevertheless be emitted if the first part is.
14365 (2) In normal usage, composite relocations are never assembly-time
14366 constants. The easiest way of dealing with the pathological
14367 exceptions is to generate a relocation against STN_UNDEF and
14368 leave everything up to the linker. */
14369 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14372 switch (fixP->fx_r_type)
14374 case BFD_RELOC_MIPS_TLS_GD:
14375 case BFD_RELOC_MIPS_TLS_LDM:
14376 case BFD_RELOC_MIPS_TLS_DTPREL32:
14377 case BFD_RELOC_MIPS_TLS_DTPREL64:
14378 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14379 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14380 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14381 case BFD_RELOC_MIPS_TLS_TPREL32:
14382 case BFD_RELOC_MIPS_TLS_TPREL64:
14383 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14384 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14385 case BFD_RELOC_MICROMIPS_TLS_GD:
14386 case BFD_RELOC_MICROMIPS_TLS_LDM:
14387 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14388 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14389 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14390 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14391 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14392 case BFD_RELOC_MIPS16_TLS_GD:
14393 case BFD_RELOC_MIPS16_TLS_LDM:
14394 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14395 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14396 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14397 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14398 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14399 if (!fixP->fx_addsy)
14401 as_bad_where (fixP->fx_file, fixP->fx_line,
14402 _("TLS relocation against a constant"));
14405 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14408 case BFD_RELOC_MIPS_JMP:
14409 case BFD_RELOC_MIPS_SHIFT5:
14410 case BFD_RELOC_MIPS_SHIFT6:
14411 case BFD_RELOC_MIPS_GOT_DISP:
14412 case BFD_RELOC_MIPS_GOT_PAGE:
14413 case BFD_RELOC_MIPS_GOT_OFST:
14414 case BFD_RELOC_MIPS_SUB:
14415 case BFD_RELOC_MIPS_INSERT_A:
14416 case BFD_RELOC_MIPS_INSERT_B:
14417 case BFD_RELOC_MIPS_DELETE:
14418 case BFD_RELOC_MIPS_HIGHEST:
14419 case BFD_RELOC_MIPS_HIGHER:
14420 case BFD_RELOC_MIPS_SCN_DISP:
14421 case BFD_RELOC_MIPS_REL16:
14422 case BFD_RELOC_MIPS_RELGOT:
14423 case BFD_RELOC_MIPS_JALR:
14424 case BFD_RELOC_HI16:
14425 case BFD_RELOC_HI16_S:
14426 case BFD_RELOC_LO16:
14427 case BFD_RELOC_GPREL16:
14428 case BFD_RELOC_MIPS_LITERAL:
14429 case BFD_RELOC_MIPS_CALL16:
14430 case BFD_RELOC_MIPS_GOT16:
14431 case BFD_RELOC_GPREL32:
14432 case BFD_RELOC_MIPS_GOT_HI16:
14433 case BFD_RELOC_MIPS_GOT_LO16:
14434 case BFD_RELOC_MIPS_CALL_HI16:
14435 case BFD_RELOC_MIPS_CALL_LO16:
14436 case BFD_RELOC_MIPS16_GPREL:
14437 case BFD_RELOC_MIPS16_GOT16:
14438 case BFD_RELOC_MIPS16_CALL16:
14439 case BFD_RELOC_MIPS16_HI16:
14440 case BFD_RELOC_MIPS16_HI16_S:
14441 case BFD_RELOC_MIPS16_LO16:
14442 case BFD_RELOC_MIPS16_JMP:
14443 case BFD_RELOC_MICROMIPS_JMP:
14444 case BFD_RELOC_MICROMIPS_GOT_DISP:
14445 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14446 case BFD_RELOC_MICROMIPS_GOT_OFST:
14447 case BFD_RELOC_MICROMIPS_SUB:
14448 case BFD_RELOC_MICROMIPS_HIGHEST:
14449 case BFD_RELOC_MICROMIPS_HIGHER:
14450 case BFD_RELOC_MICROMIPS_SCN_DISP:
14451 case BFD_RELOC_MICROMIPS_JALR:
14452 case BFD_RELOC_MICROMIPS_HI16:
14453 case BFD_RELOC_MICROMIPS_HI16_S:
14454 case BFD_RELOC_MICROMIPS_LO16:
14455 case BFD_RELOC_MICROMIPS_GPREL16:
14456 case BFD_RELOC_MICROMIPS_LITERAL:
14457 case BFD_RELOC_MICROMIPS_CALL16:
14458 case BFD_RELOC_MICROMIPS_GOT16:
14459 case BFD_RELOC_MICROMIPS_GOT_HI16:
14460 case BFD_RELOC_MICROMIPS_GOT_LO16:
14461 case BFD_RELOC_MICROMIPS_CALL_HI16:
14462 case BFD_RELOC_MICROMIPS_CALL_LO16:
14463 case BFD_RELOC_MIPS_EH:
14468 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14470 insn = read_reloc_insn (buf, fixP->fx_r_type);
14471 if (mips16_reloc_p (fixP->fx_r_type))
14472 insn |= mips16_immed_extend (value, 16);
14474 insn |= (value & 0xffff);
14475 write_reloc_insn (buf, fixP->fx_r_type, insn);
14478 as_bad_where (fixP->fx_file, fixP->fx_line,
14479 _("Unsupported constant in relocation"));
14484 /* This is handled like BFD_RELOC_32, but we output a sign
14485 extended value if we are only 32 bits. */
14488 if (8 <= sizeof (valueT))
14489 md_number_to_chars (buf, *valP, 8);
14494 if ((*valP & 0x80000000) != 0)
14498 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14499 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14504 case BFD_RELOC_RVA:
14506 case BFD_RELOC_32_PCREL:
14508 /* If we are deleting this reloc entry, we must fill in the
14509 value now. This can happen if we have a .word which is not
14510 resolved when it appears but is later defined. */
14512 md_number_to_chars (buf, *valP, fixP->fx_size);
14515 case BFD_RELOC_16_PCREL_S2:
14516 if ((*valP & 0x3) != 0)
14517 as_bad_where (fixP->fx_file, fixP->fx_line,
14518 _("Branch to misaligned address (%lx)"), (long) *valP);
14520 /* We need to save the bits in the instruction since fixup_segment()
14521 might be deleting the relocation entry (i.e., a branch within
14522 the current segment). */
14523 if (! fixP->fx_done)
14526 /* Update old instruction data. */
14527 insn = read_insn (buf);
14529 if (*valP + 0x20000 <= 0x3ffff)
14531 insn |= (*valP >> 2) & 0xffff;
14532 write_insn (buf, insn);
14534 else if (mips_pic == NO_PIC
14536 && fixP->fx_frag->fr_address >= text_section->vma
14537 && (fixP->fx_frag->fr_address
14538 < text_section->vma + bfd_get_section_size (text_section))
14539 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14540 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14541 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14543 /* The branch offset is too large. If this is an
14544 unconditional branch, and we are not generating PIC code,
14545 we can convert it to an absolute jump instruction. */
14546 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14547 insn = 0x0c000000; /* jal */
14549 insn = 0x08000000; /* j */
14550 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14552 fixP->fx_addsy = section_symbol (text_section);
14553 *valP += md_pcrel_from (fixP);
14554 write_insn (buf, insn);
14558 /* If we got here, we have branch-relaxation disabled,
14559 and there's nothing we can do to fix this instruction
14560 without turning it into a longer sequence. */
14561 as_bad_where (fixP->fx_file, fixP->fx_line,
14562 _("Branch out of range"));
14566 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14567 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14568 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14569 /* We adjust the offset back to even. */
14570 if ((*valP & 0x1) != 0)
14573 if (! fixP->fx_done)
14576 /* Should never visit here, because we keep the relocation. */
14580 case BFD_RELOC_VTABLE_INHERIT:
14583 && !S_IS_DEFINED (fixP->fx_addsy)
14584 && !S_IS_WEAK (fixP->fx_addsy))
14585 S_SET_WEAK (fixP->fx_addsy);
14588 case BFD_RELOC_VTABLE_ENTRY:
14596 /* Remember value for tc_gen_reloc. */
14597 fixP->fx_addnumber = *valP;
14607 name = input_line_pointer;
14608 c = get_symbol_end ();
14609 p = (symbolS *) symbol_find_or_make (name);
14610 *input_line_pointer = c;
14614 /* Align the current frag to a given power of two. If a particular
14615 fill byte should be used, FILL points to an integer that contains
14616 that byte, otherwise FILL is null.
14618 This function used to have the comment:
14620 The MIPS assembler also automatically adjusts any preceding label.
14622 The implementation therefore applied the adjustment to a maximum of
14623 one label. However, other label adjustments are applied to batches
14624 of labels, and adjusting just one caused problems when new labels
14625 were added for the sake of debugging or unwind information.
14626 We therefore adjust all preceding labels (given as LABELS) instead. */
14629 mips_align (int to, int *fill, struct insn_label_list *labels)
14631 mips_emit_delays ();
14632 mips_record_compressed_mode ();
14633 if (fill == NULL && subseg_text_p (now_seg))
14634 frag_align_code (to, 0);
14636 frag_align (to, fill ? *fill : 0, 0);
14637 record_alignment (now_seg, to);
14638 mips_move_labels (labels, FALSE);
14641 /* Align to a given power of two. .align 0 turns off the automatic
14642 alignment used by the data creating pseudo-ops. */
14645 s_align (int x ATTRIBUTE_UNUSED)
14647 int temp, fill_value, *fill_ptr;
14648 long max_alignment = 28;
14650 /* o Note that the assembler pulls down any immediately preceding label
14651 to the aligned address.
14652 o It's not documented but auto alignment is reinstated by
14653 a .align pseudo instruction.
14654 o Note also that after auto alignment is turned off the mips assembler
14655 issues an error on attempt to assemble an improperly aligned data item.
14658 temp = get_absolute_expression ();
14659 if (temp > max_alignment)
14660 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14663 as_warn (_("Alignment negative: 0 assumed."));
14666 if (*input_line_pointer == ',')
14668 ++input_line_pointer;
14669 fill_value = get_absolute_expression ();
14670 fill_ptr = &fill_value;
14676 segment_info_type *si = seg_info (now_seg);
14677 struct insn_label_list *l = si->label_list;
14678 /* Auto alignment should be switched on by next section change. */
14680 mips_align (temp, fill_ptr, l);
14687 demand_empty_rest_of_line ();
14691 s_change_sec (int sec)
14695 /* The ELF backend needs to know that we are changing sections, so
14696 that .previous works correctly. We could do something like check
14697 for an obj_section_change_hook macro, but that might be confusing
14698 as it would not be appropriate to use it in the section changing
14699 functions in read.c, since obj-elf.c intercepts those. FIXME:
14700 This should be cleaner, somehow. */
14701 obj_elf_section_change_hook ();
14703 mips_emit_delays ();
14714 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14715 demand_empty_rest_of_line ();
14719 seg = subseg_new (RDATA_SECTION_NAME,
14720 (subsegT) get_absolute_expression ());
14721 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14722 | SEC_READONLY | SEC_RELOC
14724 if (strncmp (TARGET_OS, "elf", 3) != 0)
14725 record_alignment (seg, 4);
14726 demand_empty_rest_of_line ();
14730 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14731 bfd_set_section_flags (stdoutput, seg,
14732 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14733 if (strncmp (TARGET_OS, "elf", 3) != 0)
14734 record_alignment (seg, 4);
14735 demand_empty_rest_of_line ();
14739 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14740 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14741 if (strncmp (TARGET_OS, "elf", 3) != 0)
14742 record_alignment (seg, 4);
14743 demand_empty_rest_of_line ();
14751 s_change_section (int ignore ATTRIBUTE_UNUSED)
14753 char *section_name;
14758 int section_entry_size;
14759 int section_alignment;
14761 section_name = input_line_pointer;
14762 c = get_symbol_end ();
14764 next_c = *(input_line_pointer + 1);
14766 /* Do we have .section Name<,"flags">? */
14767 if (c != ',' || (c == ',' && next_c == '"'))
14769 /* just after name is now '\0'. */
14770 *input_line_pointer = c;
14771 input_line_pointer = section_name;
14772 obj_elf_section (ignore);
14775 input_line_pointer++;
14777 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14779 section_type = get_absolute_expression ();
14782 if (*input_line_pointer++ == ',')
14783 section_flag = get_absolute_expression ();
14786 if (*input_line_pointer++ == ',')
14787 section_entry_size = get_absolute_expression ();
14789 section_entry_size = 0;
14790 if (*input_line_pointer++ == ',')
14791 section_alignment = get_absolute_expression ();
14793 section_alignment = 0;
14794 /* FIXME: really ignore? */
14795 (void) section_alignment;
14797 section_name = xstrdup (section_name);
14799 /* When using the generic form of .section (as implemented by obj-elf.c),
14800 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14801 traditionally had to fall back on the more common @progbits instead.
14803 There's nothing really harmful in this, since bfd will correct
14804 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14805 means that, for backwards compatibility, the special_section entries
14806 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14808 Even so, we shouldn't force users of the MIPS .section syntax to
14809 incorrectly label the sections as SHT_PROGBITS. The best compromise
14810 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14811 generic type-checking code. */
14812 if (section_type == SHT_MIPS_DWARF)
14813 section_type = SHT_PROGBITS;
14815 obj_elf_change_section (section_name, section_type, section_flag,
14816 section_entry_size, 0, 0, 0);
14818 if (now_seg->name != section_name)
14819 free (section_name);
14823 mips_enable_auto_align (void)
14829 s_cons (int log_size)
14831 segment_info_type *si = seg_info (now_seg);
14832 struct insn_label_list *l = si->label_list;
14834 mips_emit_delays ();
14835 if (log_size > 0 && auto_align)
14836 mips_align (log_size, 0, l);
14837 cons (1 << log_size);
14838 mips_clear_insn_labels ();
14842 s_float_cons (int type)
14844 segment_info_type *si = seg_info (now_seg);
14845 struct insn_label_list *l = si->label_list;
14847 mips_emit_delays ();
14852 mips_align (3, 0, l);
14854 mips_align (2, 0, l);
14858 mips_clear_insn_labels ();
14861 /* Handle .globl. We need to override it because on Irix 5 you are
14864 where foo is an undefined symbol, to mean that foo should be
14865 considered to be the address of a function. */
14868 s_mips_globl (int x ATTRIBUTE_UNUSED)
14877 name = input_line_pointer;
14878 c = get_symbol_end ();
14879 symbolP = symbol_find_or_make (name);
14880 S_SET_EXTERNAL (symbolP);
14882 *input_line_pointer = c;
14883 SKIP_WHITESPACE ();
14885 /* On Irix 5, every global symbol that is not explicitly labelled as
14886 being a function is apparently labelled as being an object. */
14889 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14890 && (*input_line_pointer != ','))
14895 secname = input_line_pointer;
14896 c = get_symbol_end ();
14897 sec = bfd_get_section_by_name (stdoutput, secname);
14899 as_bad (_("%s: no such section"), secname);
14900 *input_line_pointer = c;
14902 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14903 flag = BSF_FUNCTION;
14906 symbol_get_bfdsym (symbolP)->flags |= flag;
14908 c = *input_line_pointer;
14911 input_line_pointer++;
14912 SKIP_WHITESPACE ();
14913 if (is_end_of_line[(unsigned char) *input_line_pointer])
14919 demand_empty_rest_of_line ();
14923 s_option (int x ATTRIBUTE_UNUSED)
14928 opt = input_line_pointer;
14929 c = get_symbol_end ();
14933 /* FIXME: What does this mean? */
14935 else if (strncmp (opt, "pic", 3) == 0)
14939 i = atoi (opt + 3);
14944 mips_pic = SVR4_PIC;
14945 mips_abicalls = TRUE;
14948 as_bad (_(".option pic%d not supported"), i);
14950 if (mips_pic == SVR4_PIC)
14952 if (g_switch_seen && g_switch_value != 0)
14953 as_warn (_("-G may not be used with SVR4 PIC code"));
14954 g_switch_value = 0;
14955 bfd_set_gp_size (stdoutput, 0);
14959 as_warn (_("Unrecognized option \"%s\""), opt);
14961 *input_line_pointer = c;
14962 demand_empty_rest_of_line ();
14965 /* This structure is used to hold a stack of .set values. */
14967 struct mips_option_stack
14969 struct mips_option_stack *next;
14970 struct mips_set_options options;
14973 static struct mips_option_stack *mips_opts_stack;
14975 /* Handle the .set pseudo-op. */
14978 s_mipsset (int x ATTRIBUTE_UNUSED)
14980 char *name = input_line_pointer, ch;
14981 const struct mips_ase *ase;
14983 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14984 ++input_line_pointer;
14985 ch = *input_line_pointer;
14986 *input_line_pointer = '\0';
14988 if (strcmp (name, "reorder") == 0)
14990 if (mips_opts.noreorder)
14993 else if (strcmp (name, "noreorder") == 0)
14995 if (!mips_opts.noreorder)
14996 start_noreorder ();
14998 else if (strncmp (name, "at=", 3) == 0)
15000 char *s = name + 3;
15002 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15003 as_bad (_("Unrecognized register name `%s'"), s);
15005 else if (strcmp (name, "at") == 0)
15007 mips_opts.at = ATREG;
15009 else if (strcmp (name, "noat") == 0)
15011 mips_opts.at = ZERO;
15013 else if (strcmp (name, "macro") == 0)
15015 mips_opts.warn_about_macros = 0;
15017 else if (strcmp (name, "nomacro") == 0)
15019 if (mips_opts.noreorder == 0)
15020 as_bad (_("`noreorder' must be set before `nomacro'"));
15021 mips_opts.warn_about_macros = 1;
15023 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15025 mips_opts.nomove = 0;
15027 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15029 mips_opts.nomove = 1;
15031 else if (strcmp (name, "bopt") == 0)
15033 mips_opts.nobopt = 0;
15035 else if (strcmp (name, "nobopt") == 0)
15037 mips_opts.nobopt = 1;
15039 else if (strcmp (name, "gp=default") == 0)
15040 mips_opts.gp32 = file_mips_gp32;
15041 else if (strcmp (name, "gp=32") == 0)
15042 mips_opts.gp32 = 1;
15043 else if (strcmp (name, "gp=64") == 0)
15045 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
15046 as_warn (_("%s isa does not support 64-bit registers"),
15047 mips_cpu_info_from_isa (mips_opts.isa)->name);
15048 mips_opts.gp32 = 0;
15050 else if (strcmp (name, "fp=default") == 0)
15051 mips_opts.fp32 = file_mips_fp32;
15052 else if (strcmp (name, "fp=32") == 0)
15053 mips_opts.fp32 = 1;
15054 else if (strcmp (name, "fp=64") == 0)
15056 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15057 as_warn (_("%s isa does not support 64-bit floating point registers"),
15058 mips_cpu_info_from_isa (mips_opts.isa)->name);
15059 mips_opts.fp32 = 0;
15061 else if (strcmp (name, "softfloat") == 0)
15062 mips_opts.soft_float = 1;
15063 else if (strcmp (name, "hardfloat") == 0)
15064 mips_opts.soft_float = 0;
15065 else if (strcmp (name, "singlefloat") == 0)
15066 mips_opts.single_float = 1;
15067 else if (strcmp (name, "doublefloat") == 0)
15068 mips_opts.single_float = 0;
15069 else if (strcmp (name, "mips16") == 0
15070 || strcmp (name, "MIPS-16") == 0)
15072 if (mips_opts.micromips == 1)
15073 as_fatal (_("`mips16' cannot be used with `micromips'"));
15074 mips_opts.mips16 = 1;
15076 else if (strcmp (name, "nomips16") == 0
15077 || strcmp (name, "noMIPS-16") == 0)
15078 mips_opts.mips16 = 0;
15079 else if (strcmp (name, "micromips") == 0)
15081 if (mips_opts.mips16 == 1)
15082 as_fatal (_("`micromips' cannot be used with `mips16'"));
15083 mips_opts.micromips = 1;
15085 else if (strcmp (name, "nomicromips") == 0)
15086 mips_opts.micromips = 0;
15087 else if (name[0] == 'n'
15089 && (ase = mips_lookup_ase (name + 2)))
15090 mips_set_ase (ase, FALSE);
15091 else if ((ase = mips_lookup_ase (name)))
15092 mips_set_ase (ase, TRUE);
15093 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15097 /* Permit the user to change the ISA and architecture on the fly.
15098 Needless to say, misuse can cause serious problems. */
15099 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15102 mips_opts.isa = file_mips_isa;
15103 mips_opts.arch = file_mips_arch;
15105 else if (strncmp (name, "arch=", 5) == 0)
15107 const struct mips_cpu_info *p;
15109 p = mips_parse_cpu("internal use", name + 5);
15111 as_bad (_("unknown architecture %s"), name + 5);
15114 mips_opts.arch = p->cpu;
15115 mips_opts.isa = p->isa;
15118 else if (strncmp (name, "mips", 4) == 0)
15120 const struct mips_cpu_info *p;
15122 p = mips_parse_cpu("internal use", name);
15124 as_bad (_("unknown ISA level %s"), name + 4);
15127 mips_opts.arch = p->cpu;
15128 mips_opts.isa = p->isa;
15132 as_bad (_("unknown ISA or architecture %s"), name);
15134 switch (mips_opts.isa)
15142 mips_opts.gp32 = 1;
15143 mips_opts.fp32 = 1;
15150 mips_opts.gp32 = 0;
15151 if (mips_opts.arch == CPU_R5900)
15153 mips_opts.fp32 = 1;
15157 mips_opts.fp32 = 0;
15161 as_bad (_("unknown ISA level %s"), name + 4);
15166 mips_opts.gp32 = file_mips_gp32;
15167 mips_opts.fp32 = file_mips_fp32;
15170 else if (strcmp (name, "autoextend") == 0)
15171 mips_opts.noautoextend = 0;
15172 else if (strcmp (name, "noautoextend") == 0)
15173 mips_opts.noautoextend = 1;
15174 else if (strcmp (name, "insn32") == 0)
15175 mips_opts.insn32 = TRUE;
15176 else if (strcmp (name, "noinsn32") == 0)
15177 mips_opts.insn32 = FALSE;
15178 else if (strcmp (name, "push") == 0)
15180 struct mips_option_stack *s;
15182 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15183 s->next = mips_opts_stack;
15184 s->options = mips_opts;
15185 mips_opts_stack = s;
15187 else if (strcmp (name, "pop") == 0)
15189 struct mips_option_stack *s;
15191 s = mips_opts_stack;
15193 as_bad (_(".set pop with no .set push"));
15196 /* If we're changing the reorder mode we need to handle
15197 delay slots correctly. */
15198 if (s->options.noreorder && ! mips_opts.noreorder)
15199 start_noreorder ();
15200 else if (! s->options.noreorder && mips_opts.noreorder)
15203 mips_opts = s->options;
15204 mips_opts_stack = s->next;
15208 else if (strcmp (name, "sym32") == 0)
15209 mips_opts.sym32 = TRUE;
15210 else if (strcmp (name, "nosym32") == 0)
15211 mips_opts.sym32 = FALSE;
15212 else if (strchr (name, ','))
15214 /* Generic ".set" directive; use the generic handler. */
15215 *input_line_pointer = ch;
15216 input_line_pointer = name;
15222 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
15224 mips_check_isa_supports_ases ();
15225 *input_line_pointer = ch;
15226 demand_empty_rest_of_line ();
15229 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15230 .option pic2. It means to generate SVR4 PIC calls. */
15233 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15235 mips_pic = SVR4_PIC;
15236 mips_abicalls = TRUE;
15238 if (g_switch_seen && g_switch_value != 0)
15239 as_warn (_("-G may not be used with SVR4 PIC code"));
15240 g_switch_value = 0;
15242 bfd_set_gp_size (stdoutput, 0);
15243 demand_empty_rest_of_line ();
15246 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15247 PIC code. It sets the $gp register for the function based on the
15248 function address, which is in the register named in the argument.
15249 This uses a relocation against _gp_disp, which is handled specially
15250 by the linker. The result is:
15251 lui $gp,%hi(_gp_disp)
15252 addiu $gp,$gp,%lo(_gp_disp)
15253 addu $gp,$gp,.cpload argument
15254 The .cpload argument is normally $25 == $t9.
15256 The -mno-shared option changes this to:
15257 lui $gp,%hi(__gnu_local_gp)
15258 addiu $gp,$gp,%lo(__gnu_local_gp)
15259 and the argument is ignored. This saves an instruction, but the
15260 resulting code is not position independent; it uses an absolute
15261 address for __gnu_local_gp. Thus code assembled with -mno-shared
15262 can go into an ordinary executable, but not into a shared library. */
15265 s_cpload (int ignore ATTRIBUTE_UNUSED)
15271 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15272 .cpload is ignored. */
15273 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15279 if (mips_opts.mips16)
15281 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15282 ignore_rest_of_line ();
15286 /* .cpload should be in a .set noreorder section. */
15287 if (mips_opts.noreorder == 0)
15288 as_warn (_(".cpload not in noreorder section"));
15290 reg = tc_get_register (0);
15292 /* If we need to produce a 64-bit address, we are better off using
15293 the default instruction sequence. */
15294 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15296 ex.X_op = O_symbol;
15297 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15299 ex.X_op_symbol = NULL;
15300 ex.X_add_number = 0;
15302 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15303 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15305 mips_mark_labels ();
15306 mips_assembling_insn = TRUE;
15309 macro_build_lui (&ex, mips_gp_register);
15310 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15311 mips_gp_register, BFD_RELOC_LO16);
15313 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15314 mips_gp_register, reg);
15317 mips_assembling_insn = FALSE;
15318 demand_empty_rest_of_line ();
15321 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15322 .cpsetup $reg1, offset|$reg2, label
15324 If offset is given, this results in:
15325 sd $gp, offset($sp)
15326 lui $gp, %hi(%neg(%gp_rel(label)))
15327 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15328 daddu $gp, $gp, $reg1
15330 If $reg2 is given, this results in:
15331 daddu $reg2, $gp, $0
15332 lui $gp, %hi(%neg(%gp_rel(label)))
15333 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15334 daddu $gp, $gp, $reg1
15335 $reg1 is normally $25 == $t9.
15337 The -mno-shared option replaces the last three instructions with
15339 addiu $gp,$gp,%lo(_gp) */
15342 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15344 expressionS ex_off;
15345 expressionS ex_sym;
15348 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15349 We also need NewABI support. */
15350 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15356 if (mips_opts.mips16)
15358 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15359 ignore_rest_of_line ();
15363 reg1 = tc_get_register (0);
15364 SKIP_WHITESPACE ();
15365 if (*input_line_pointer != ',')
15367 as_bad (_("missing argument separator ',' for .cpsetup"));
15371 ++input_line_pointer;
15372 SKIP_WHITESPACE ();
15373 if (*input_line_pointer == '$')
15375 mips_cpreturn_register = tc_get_register (0);
15376 mips_cpreturn_offset = -1;
15380 mips_cpreturn_offset = get_absolute_expression ();
15381 mips_cpreturn_register = -1;
15383 SKIP_WHITESPACE ();
15384 if (*input_line_pointer != ',')
15386 as_bad (_("missing argument separator ',' for .cpsetup"));
15390 ++input_line_pointer;
15391 SKIP_WHITESPACE ();
15392 expression (&ex_sym);
15394 mips_mark_labels ();
15395 mips_assembling_insn = TRUE;
15398 if (mips_cpreturn_register == -1)
15400 ex_off.X_op = O_constant;
15401 ex_off.X_add_symbol = NULL;
15402 ex_off.X_op_symbol = NULL;
15403 ex_off.X_add_number = mips_cpreturn_offset;
15405 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15406 BFD_RELOC_LO16, SP);
15409 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15410 mips_gp_register, 0);
15412 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15414 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15415 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15418 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15419 mips_gp_register, -1, BFD_RELOC_GPREL16,
15420 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15422 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15423 mips_gp_register, reg1);
15429 ex.X_op = O_symbol;
15430 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15431 ex.X_op_symbol = NULL;
15432 ex.X_add_number = 0;
15434 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15435 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15437 macro_build_lui (&ex, mips_gp_register);
15438 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15439 mips_gp_register, BFD_RELOC_LO16);
15444 mips_assembling_insn = FALSE;
15445 demand_empty_rest_of_line ();
15449 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15451 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15452 .cplocal is ignored. */
15453 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15459 if (mips_opts.mips16)
15461 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15462 ignore_rest_of_line ();
15466 mips_gp_register = tc_get_register (0);
15467 demand_empty_rest_of_line ();
15470 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15471 offset from $sp. The offset is remembered, and after making a PIC
15472 call $gp is restored from that location. */
15475 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15479 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15480 .cprestore is ignored. */
15481 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15487 if (mips_opts.mips16)
15489 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15490 ignore_rest_of_line ();
15494 mips_cprestore_offset = get_absolute_expression ();
15495 mips_cprestore_valid = 1;
15497 ex.X_op = O_constant;
15498 ex.X_add_symbol = NULL;
15499 ex.X_op_symbol = NULL;
15500 ex.X_add_number = mips_cprestore_offset;
15502 mips_mark_labels ();
15503 mips_assembling_insn = TRUE;
15506 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15507 SP, HAVE_64BIT_ADDRESSES);
15510 mips_assembling_insn = FALSE;
15511 demand_empty_rest_of_line ();
15514 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15515 was given in the preceding .cpsetup, it results in:
15516 ld $gp, offset($sp)
15518 If a register $reg2 was given there, it results in:
15519 daddu $gp, $reg2, $0 */
15522 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15526 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15527 We also need NewABI support. */
15528 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15534 if (mips_opts.mips16)
15536 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15537 ignore_rest_of_line ();
15541 mips_mark_labels ();
15542 mips_assembling_insn = TRUE;
15545 if (mips_cpreturn_register == -1)
15547 ex.X_op = O_constant;
15548 ex.X_add_symbol = NULL;
15549 ex.X_op_symbol = NULL;
15550 ex.X_add_number = mips_cpreturn_offset;
15552 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15555 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15556 mips_cpreturn_register, 0);
15559 mips_assembling_insn = FALSE;
15560 demand_empty_rest_of_line ();
15563 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15564 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15565 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15566 debug information or MIPS16 TLS. */
15569 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15570 bfd_reloc_code_real_type rtype)
15577 if (ex.X_op != O_symbol)
15579 as_bad (_("Unsupported use of %s"), dirstr);
15580 ignore_rest_of_line ();
15583 p = frag_more (bytes);
15584 md_number_to_chars (p, 0, bytes);
15585 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15586 demand_empty_rest_of_line ();
15587 mips_clear_insn_labels ();
15590 /* Handle .dtprelword. */
15593 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15595 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15598 /* Handle .dtpreldword. */
15601 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15603 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15606 /* Handle .tprelword. */
15609 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15611 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15614 /* Handle .tpreldword. */
15617 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15619 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15622 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15623 code. It sets the offset to use in gp_rel relocations. */
15626 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15628 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15629 We also need NewABI support. */
15630 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15636 mips_gprel_offset = get_absolute_expression ();
15638 demand_empty_rest_of_line ();
15641 /* Handle the .gpword pseudo-op. This is used when generating PIC
15642 code. It generates a 32 bit GP relative reloc. */
15645 s_gpword (int ignore ATTRIBUTE_UNUSED)
15647 segment_info_type *si;
15648 struct insn_label_list *l;
15652 /* When not generating PIC code, this is treated as .word. */
15653 if (mips_pic != SVR4_PIC)
15659 si = seg_info (now_seg);
15660 l = si->label_list;
15661 mips_emit_delays ();
15663 mips_align (2, 0, l);
15666 mips_clear_insn_labels ();
15668 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15670 as_bad (_("Unsupported use of .gpword"));
15671 ignore_rest_of_line ();
15675 md_number_to_chars (p, 0, 4);
15676 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15677 BFD_RELOC_GPREL32);
15679 demand_empty_rest_of_line ();
15683 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15685 segment_info_type *si;
15686 struct insn_label_list *l;
15690 /* When not generating PIC code, this is treated as .dword. */
15691 if (mips_pic != SVR4_PIC)
15697 si = seg_info (now_seg);
15698 l = si->label_list;
15699 mips_emit_delays ();
15701 mips_align (3, 0, l);
15704 mips_clear_insn_labels ();
15706 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15708 as_bad (_("Unsupported use of .gpdword"));
15709 ignore_rest_of_line ();
15713 md_number_to_chars (p, 0, 8);
15714 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15715 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15717 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15718 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15719 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15721 demand_empty_rest_of_line ();
15724 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15725 tables. It generates a R_MIPS_EH reloc. */
15728 s_ehword (int ignore ATTRIBUTE_UNUSED)
15733 mips_emit_delays ();
15736 mips_clear_insn_labels ();
15738 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15740 as_bad (_("Unsupported use of .ehword"));
15741 ignore_rest_of_line ();
15745 md_number_to_chars (p, 0, 4);
15746 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15747 BFD_RELOC_MIPS_EH);
15749 demand_empty_rest_of_line ();
15752 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15753 tables in SVR4 PIC code. */
15756 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15760 /* This is ignored when not generating SVR4 PIC code. */
15761 if (mips_pic != SVR4_PIC)
15767 mips_mark_labels ();
15768 mips_assembling_insn = TRUE;
15770 /* Add $gp to the register named as an argument. */
15772 reg = tc_get_register (0);
15773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15776 mips_assembling_insn = FALSE;
15777 demand_empty_rest_of_line ();
15780 /* Handle the .insn pseudo-op. This marks instruction labels in
15781 mips16/micromips mode. This permits the linker to handle them specially,
15782 such as generating jalx instructions when needed. We also make
15783 them odd for the duration of the assembly, in order to generate the
15784 right sort of code. We will make them even in the adjust_symtab
15785 routine, while leaving them marked. This is convenient for the
15786 debugger and the disassembler. The linker knows to make them odd
15790 s_insn (int ignore ATTRIBUTE_UNUSED)
15792 mips_mark_labels ();
15794 demand_empty_rest_of_line ();
15797 /* Handle the .nan pseudo-op. */
15800 s_nan (int ignore ATTRIBUTE_UNUSED)
15802 static const char str_legacy[] = "legacy";
15803 static const char str_2008[] = "2008";
15806 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15808 if (i == sizeof (str_2008) - 1
15809 && memcmp (input_line_pointer, str_2008, i) == 0)
15810 mips_flag_nan2008 = TRUE;
15811 else if (i == sizeof (str_legacy) - 1
15812 && memcmp (input_line_pointer, str_legacy, i) == 0)
15813 mips_flag_nan2008 = FALSE;
15815 as_bad (_("Bad .nan directive"));
15817 input_line_pointer += i;
15818 demand_empty_rest_of_line ();
15821 /* Handle a .stab[snd] directive. Ideally these directives would be
15822 implemented in a transparent way, so that removing them would not
15823 have any effect on the generated instructions. However, s_stab
15824 internally changes the section, so in practice we need to decide
15825 now whether the preceding label marks compressed code. We do not
15826 support changing the compression mode of a label after a .stab*
15827 directive, such as in:
15833 so the current mode wins. */
15836 s_mips_stab (int type)
15838 mips_mark_labels ();
15842 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15845 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15852 name = input_line_pointer;
15853 c = get_symbol_end ();
15854 symbolP = symbol_find_or_make (name);
15855 S_SET_WEAK (symbolP);
15856 *input_line_pointer = c;
15858 SKIP_WHITESPACE ();
15860 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15862 if (S_IS_DEFINED (symbolP))
15864 as_bad (_("ignoring attempt to redefine symbol %s"),
15865 S_GET_NAME (symbolP));
15866 ignore_rest_of_line ();
15870 if (*input_line_pointer == ',')
15872 ++input_line_pointer;
15873 SKIP_WHITESPACE ();
15877 if (exp.X_op != O_symbol)
15879 as_bad (_("bad .weakext directive"));
15880 ignore_rest_of_line ();
15883 symbol_set_value_expression (symbolP, &exp);
15886 demand_empty_rest_of_line ();
15889 /* Parse a register string into a number. Called from the ECOFF code
15890 to parse .frame. The argument is non-zero if this is the frame
15891 register, so that we can record it in mips_frame_reg. */
15894 tc_get_register (int frame)
15898 SKIP_WHITESPACE ();
15899 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15903 mips_frame_reg = reg != 0 ? reg : SP;
15904 mips_frame_reg_valid = 1;
15905 mips_cprestore_valid = 0;
15911 md_section_align (asection *seg, valueT addr)
15913 int align = bfd_get_section_alignment (stdoutput, seg);
15915 /* We don't need to align ELF sections to the full alignment.
15916 However, Irix 5 may prefer that we align them at least to a 16
15917 byte boundary. We don't bother to align the sections if we
15918 are targeted for an embedded system. */
15919 if (strncmp (TARGET_OS, "elf", 3) == 0)
15924 return ((addr + (1 << align) - 1) & (-1 << align));
15927 /* Utility routine, called from above as well. If called while the
15928 input file is still being read, it's only an approximation. (For
15929 example, a symbol may later become defined which appeared to be
15930 undefined earlier.) */
15933 nopic_need_relax (symbolS *sym, int before_relaxing)
15938 if (g_switch_value > 0)
15940 const char *symname;
15943 /* Find out whether this symbol can be referenced off the $gp
15944 register. It can be if it is smaller than the -G size or if
15945 it is in the .sdata or .sbss section. Certain symbols can
15946 not be referenced off the $gp, although it appears as though
15948 symname = S_GET_NAME (sym);
15949 if (symname != (const char *) NULL
15950 && (strcmp (symname, "eprol") == 0
15951 || strcmp (symname, "etext") == 0
15952 || strcmp (symname, "_gp") == 0
15953 || strcmp (symname, "edata") == 0
15954 || strcmp (symname, "_fbss") == 0
15955 || strcmp (symname, "_fdata") == 0
15956 || strcmp (symname, "_ftext") == 0
15957 || strcmp (symname, "end") == 0
15958 || strcmp (symname, "_gp_disp") == 0))
15960 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15962 #ifndef NO_ECOFF_DEBUGGING
15963 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15964 && (symbol_get_obj (sym)->ecoff_extern_size
15965 <= g_switch_value))
15967 /* We must defer this decision until after the whole
15968 file has been read, since there might be a .extern
15969 after the first use of this symbol. */
15970 || (before_relaxing
15971 #ifndef NO_ECOFF_DEBUGGING
15972 && symbol_get_obj (sym)->ecoff_extern_size == 0
15974 && S_GET_VALUE (sym) == 0)
15975 || (S_GET_VALUE (sym) != 0
15976 && S_GET_VALUE (sym) <= g_switch_value)))
15980 const char *segname;
15982 segname = segment_name (S_GET_SEGMENT (sym));
15983 gas_assert (strcmp (segname, ".lit8") != 0
15984 && strcmp (segname, ".lit4") != 0);
15985 change = (strcmp (segname, ".sdata") != 0
15986 && strcmp (segname, ".sbss") != 0
15987 && strncmp (segname, ".sdata.", 7) != 0
15988 && strncmp (segname, ".sbss.", 6) != 0
15989 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15990 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15995 /* We are not optimizing for the $gp register. */
16000 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16003 pic_need_relax (symbolS *sym, asection *segtype)
16007 /* Handle the case of a symbol equated to another symbol. */
16008 while (symbol_equated_reloc_p (sym))
16012 /* It's possible to get a loop here in a badly written program. */
16013 n = symbol_get_value_expression (sym)->X_add_symbol;
16019 if (symbol_section_p (sym))
16022 symsec = S_GET_SEGMENT (sym);
16024 /* This must duplicate the test in adjust_reloc_syms. */
16025 return (!bfd_is_und_section (symsec)
16026 && !bfd_is_abs_section (symsec)
16027 && !bfd_is_com_section (symsec)
16028 && !s_is_linkonce (sym, segtype)
16029 /* A global or weak symbol is treated as external. */
16030 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16034 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16035 extended opcode. SEC is the section the frag is in. */
16038 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16041 const struct mips_int_operand *operand;
16046 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16048 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16051 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16052 operand = mips16_immed_operand (type, FALSE);
16054 sym_frag = symbol_get_frag (fragp->fr_symbol);
16055 val = S_GET_VALUE (fragp->fr_symbol);
16056 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16058 if (operand->root.type == OP_PCREL)
16060 const struct mips_pcrel_operand *pcrel_op;
16064 /* We won't have the section when we are called from
16065 mips_relax_frag. However, we will always have been called
16066 from md_estimate_size_before_relax first. If this is a
16067 branch to a different section, we mark it as such. If SEC is
16068 NULL, and the frag is not marked, then it must be a branch to
16069 the same section. */
16070 pcrel_op = (const struct mips_pcrel_operand *) operand;
16073 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16078 /* Must have been called from md_estimate_size_before_relax. */
16081 fragp->fr_subtype =
16082 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16084 /* FIXME: We should support this, and let the linker
16085 catch branches and loads that are out of range. */
16086 as_bad_where (fragp->fr_file, fragp->fr_line,
16087 _("unsupported PC relative reference to different section"));
16091 if (fragp != sym_frag && sym_frag->fr_address == 0)
16092 /* Assume non-extended on the first relaxation pass.
16093 The address we have calculated will be bogus if this is
16094 a forward branch to another frag, as the forward frag
16095 will have fr_address == 0. */
16099 /* In this case, we know for sure that the symbol fragment is in
16100 the same section. If the relax_marker of the symbol fragment
16101 differs from the relax_marker of this fragment, we have not
16102 yet adjusted the symbol fragment fr_address. We want to add
16103 in STRETCH in order to get a better estimate of the address.
16104 This particularly matters because of the shift bits. */
16106 && sym_frag->relax_marker != fragp->relax_marker)
16110 /* Adjust stretch for any alignment frag. Note that if have
16111 been expanding the earlier code, the symbol may be
16112 defined in what appears to be an earlier frag. FIXME:
16113 This doesn't handle the fr_subtype field, which specifies
16114 a maximum number of bytes to skip when doing an
16116 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16118 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16121 stretch = - ((- stretch)
16122 & ~ ((1 << (int) f->fr_offset) - 1));
16124 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16133 addr = fragp->fr_address + fragp->fr_fix;
16135 /* The base address rules are complicated. The base address of
16136 a branch is the following instruction. The base address of a
16137 PC relative load or add is the instruction itself, but if it
16138 is in a delay slot (in which case it can not be extended) use
16139 the address of the instruction whose delay slot it is in. */
16140 if (pcrel_op->include_isa_bit)
16144 /* If we are currently assuming that this frag should be
16145 extended, then, the current address is two bytes
16147 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16150 /* Ignore the low bit in the target, since it will be set
16151 for a text label. */
16154 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16156 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16159 val -= addr & -(1 << pcrel_op->align_log2);
16161 /* If any of the shifted bits are set, we must use an extended
16162 opcode. If the address depends on the size of this
16163 instruction, this can lead to a loop, so we arrange to always
16164 use an extended opcode. We only check this when we are in
16165 the main relaxation loop, when SEC is NULL. */
16166 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16168 fragp->fr_subtype =
16169 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16173 /* If we are about to mark a frag as extended because the value
16174 is precisely the next value above maxtiny, then there is a
16175 chance of an infinite loop as in the following code:
16180 In this case when the la is extended, foo is 0x3fc bytes
16181 away, so the la can be shrunk, but then foo is 0x400 away, so
16182 the la must be extended. To avoid this loop, we mark the
16183 frag as extended if it was small, and is about to become
16184 extended with the next value above maxtiny. */
16185 maxtiny = mips_int_operand_max (operand);
16186 if (val == maxtiny + (1 << operand->shift)
16187 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16190 fragp->fr_subtype =
16191 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16195 else if (symsec != absolute_section && sec != NULL)
16196 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16198 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16201 /* Compute the length of a branch sequence, and adjust the
16202 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16203 worst-case length is computed, with UPDATE being used to indicate
16204 whether an unconditional (-1), branch-likely (+1) or regular (0)
16205 branch is to be computed. */
16207 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16209 bfd_boolean toofar;
16213 && S_IS_DEFINED (fragp->fr_symbol)
16214 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16219 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16221 addr = fragp->fr_address + fragp->fr_fix + 4;
16225 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16228 /* If the symbol is not defined or it's in a different segment,
16229 assume the user knows what's going on and emit a short
16235 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16237 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16238 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16239 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16240 RELAX_BRANCH_LINK (fragp->fr_subtype),
16246 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16249 if (mips_pic != NO_PIC)
16251 /* Additional space for PIC loading of target address. */
16253 if (mips_opts.isa == ISA_MIPS1)
16254 /* Additional space for $at-stabilizing nop. */
16258 /* If branch is conditional. */
16259 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16266 /* Compute the length of a branch sequence, and adjust the
16267 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16268 worst-case length is computed, with UPDATE being used to indicate
16269 whether an unconditional (-1), or regular (0) branch is to be
16273 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16275 bfd_boolean toofar;
16279 && S_IS_DEFINED (fragp->fr_symbol)
16280 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16285 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16286 /* Ignore the low bit in the target, since it will be set
16287 for a text label. */
16288 if ((val & 1) != 0)
16291 addr = fragp->fr_address + fragp->fr_fix + 4;
16295 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16298 /* If the symbol is not defined or it's in a different segment,
16299 assume the user knows what's going on and emit a short
16305 if (fragp && update
16306 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16307 fragp->fr_subtype = (toofar
16308 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16309 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16314 bfd_boolean compact_known = fragp != NULL;
16315 bfd_boolean compact = FALSE;
16316 bfd_boolean uncond;
16319 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16321 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16323 uncond = update < 0;
16325 /* If label is out of range, we turn branch <br>:
16327 <br> label # 4 bytes
16333 nop # 2 bytes if compact && !PIC
16336 if (mips_pic == NO_PIC && (!compact_known || compact))
16339 /* If assembling PIC code, we further turn:
16345 lw/ld at, %got(label)(gp) # 4 bytes
16346 d/addiu at, %lo(label) # 4 bytes
16349 if (mips_pic != NO_PIC)
16352 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16354 <brneg> 0f # 4 bytes
16355 nop # 2 bytes if !compact
16358 length += (compact_known && compact) ? 4 : 6;
16364 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16365 bit accordingly. */
16368 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16370 bfd_boolean toofar;
16373 && S_IS_DEFINED (fragp->fr_symbol)
16374 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16380 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16381 /* Ignore the low bit in the target, since it will be set
16382 for a text label. */
16383 if ((val & 1) != 0)
16386 /* Assume this is a 2-byte branch. */
16387 addr = fragp->fr_address + fragp->fr_fix + 2;
16389 /* We try to avoid the infinite loop by not adding 2 more bytes for
16394 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16396 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16397 else if (type == 'E')
16398 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16403 /* If the symbol is not defined or it's in a different segment,
16404 we emit a normal 32-bit branch. */
16407 if (fragp && update
16408 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16410 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16411 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16419 /* Estimate the size of a frag before relaxing. Unless this is the
16420 mips16, we are not really relaxing here, and the final size is
16421 encoded in the subtype information. For the mips16, we have to
16422 decide whether we are using an extended opcode or not. */
16425 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16429 if (RELAX_BRANCH_P (fragp->fr_subtype))
16432 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16434 return fragp->fr_var;
16437 if (RELAX_MIPS16_P (fragp->fr_subtype))
16438 /* We don't want to modify the EXTENDED bit here; it might get us
16439 into infinite loops. We change it only in mips_relax_frag(). */
16440 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16442 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16446 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16447 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16448 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16449 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16450 fragp->fr_var = length;
16455 if (mips_pic == NO_PIC)
16456 change = nopic_need_relax (fragp->fr_symbol, 0);
16457 else if (mips_pic == SVR4_PIC)
16458 change = pic_need_relax (fragp->fr_symbol, segtype);
16459 else if (mips_pic == VXWORKS_PIC)
16460 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16467 fragp->fr_subtype |= RELAX_USE_SECOND;
16468 return -RELAX_FIRST (fragp->fr_subtype);
16471 return -RELAX_SECOND (fragp->fr_subtype);
16474 /* This is called to see whether a reloc against a defined symbol
16475 should be converted into a reloc against a section. */
16478 mips_fix_adjustable (fixS *fixp)
16480 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16481 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16484 if (fixp->fx_addsy == NULL)
16487 /* If symbol SYM is in a mergeable section, relocations of the form
16488 SYM + 0 can usually be made section-relative. The mergeable data
16489 is then identified by the section offset rather than by the symbol.
16491 However, if we're generating REL LO16 relocations, the offset is split
16492 between the LO16 and parterning high part relocation. The linker will
16493 need to recalculate the complete offset in order to correctly identify
16496 The linker has traditionally not looked for the parterning high part
16497 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16498 placed anywhere. Rather than break backwards compatibility by changing
16499 this, it seems better not to force the issue, and instead keep the
16500 original symbol. This will work with either linker behavior. */
16501 if ((lo16_reloc_p (fixp->fx_r_type)
16502 || reloc_needs_lo_p (fixp->fx_r_type))
16503 && HAVE_IN_PLACE_ADDENDS
16504 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16507 /* There is no place to store an in-place offset for JALR relocations.
16508 Likewise an in-range offset of limited PC-relative relocations may
16509 overflow the in-place relocatable field if recalculated against the
16510 start address of the symbol's containing section. */
16511 if (HAVE_IN_PLACE_ADDENDS
16512 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16513 || jalr_reloc_p (fixp->fx_r_type)))
16516 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16517 to a floating-point stub. The same is true for non-R_MIPS16_26
16518 relocations against MIPS16 functions; in this case, the stub becomes
16519 the function's canonical address.
16521 Floating-point stubs are stored in unique .mips16.call.* or
16522 .mips16.fn.* sections. If a stub T for function F is in section S,
16523 the first relocation in section S must be against F; this is how the
16524 linker determines the target function. All relocations that might
16525 resolve to T must also be against F. We therefore have the following
16526 restrictions, which are given in an intentionally-redundant way:
16528 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16531 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16532 if that stub might be used.
16534 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16537 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16538 that stub might be used.
16540 There is a further restriction:
16542 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16543 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16544 targets with in-place addends; the relocation field cannot
16545 encode the low bit.
16547 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16548 against a MIPS16 symbol. We deal with (5) by by not reducing any
16549 such relocations on REL targets.
16551 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16552 relocation against some symbol R, no relocation against R may be
16553 reduced. (Note that this deals with (2) as well as (1) because
16554 relocations against global symbols will never be reduced on ELF
16555 targets.) This approach is a little simpler than trying to detect
16556 stub sections, and gives the "all or nothing" per-symbol consistency
16557 that we have for MIPS16 symbols. */
16558 if (fixp->fx_subsy == NULL
16559 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16560 || *symbol_get_tc (fixp->fx_addsy)
16561 || (HAVE_IN_PLACE_ADDENDS
16562 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16563 && jmp_reloc_p (fixp->fx_r_type))))
16569 /* Translate internal representation of relocation info to BFD target
16573 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16575 static arelent *retval[4];
16577 bfd_reloc_code_real_type code;
16579 memset (retval, 0, sizeof(retval));
16580 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16581 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16582 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16583 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16585 if (fixp->fx_pcrel)
16587 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16588 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16589 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16590 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16591 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16593 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16594 Relocations want only the symbol offset. */
16595 reloc->addend = fixp->fx_addnumber + reloc->address;
16598 reloc->addend = fixp->fx_addnumber;
16600 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16601 entry to be used in the relocation's section offset. */
16602 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16604 reloc->address = reloc->addend;
16608 code = fixp->fx_r_type;
16610 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16611 if (reloc->howto == NULL)
16613 as_bad_where (fixp->fx_file, fixp->fx_line,
16614 _("Can not represent %s relocation in this object file format"),
16615 bfd_get_reloc_code_name (code));
16622 /* Relax a machine dependent frag. This returns the amount by which
16623 the current size of the frag should change. */
16626 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16628 if (RELAX_BRANCH_P (fragp->fr_subtype))
16630 offsetT old_var = fragp->fr_var;
16632 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16634 return fragp->fr_var - old_var;
16637 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16639 offsetT old_var = fragp->fr_var;
16640 offsetT new_var = 4;
16642 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16643 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16644 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16645 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16646 fragp->fr_var = new_var;
16648 return new_var - old_var;
16651 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16654 if (mips16_extended_frag (fragp, NULL, stretch))
16656 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16658 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16663 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16665 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16672 /* Convert a machine dependent frag. */
16675 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16677 if (RELAX_BRANCH_P (fragp->fr_subtype))
16680 unsigned long insn;
16684 buf = fragp->fr_literal + fragp->fr_fix;
16685 insn = read_insn (buf);
16687 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16689 /* We generate a fixup instead of applying it right now
16690 because, if there are linker relaxations, we're going to
16691 need the relocations. */
16692 exp.X_op = O_symbol;
16693 exp.X_add_symbol = fragp->fr_symbol;
16694 exp.X_add_number = fragp->fr_offset;
16696 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16697 BFD_RELOC_16_PCREL_S2);
16698 fixp->fx_file = fragp->fr_file;
16699 fixp->fx_line = fragp->fr_line;
16701 buf = write_insn (buf, insn);
16707 as_warn_where (fragp->fr_file, fragp->fr_line,
16708 _("Relaxed out-of-range branch into a jump"));
16710 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16713 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16715 /* Reverse the branch. */
16716 switch ((insn >> 28) & 0xf)
16719 /* bc[0-3][tf]l? instructions can have the condition
16720 reversed by tweaking a single TF bit, and their
16721 opcodes all have 0x4???????. */
16722 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16723 insn ^= 0x00010000;
16727 /* bltz 0x04000000 bgez 0x04010000
16728 bltzal 0x04100000 bgezal 0x04110000 */
16729 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16730 insn ^= 0x00010000;
16734 /* beq 0x10000000 bne 0x14000000
16735 blez 0x18000000 bgtz 0x1c000000 */
16736 insn ^= 0x04000000;
16744 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16746 /* Clear the and-link bit. */
16747 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16749 /* bltzal 0x04100000 bgezal 0x04110000
16750 bltzall 0x04120000 bgezall 0x04130000 */
16751 insn &= ~0x00100000;
16754 /* Branch over the branch (if the branch was likely) or the
16755 full jump (not likely case). Compute the offset from the
16756 current instruction to branch to. */
16757 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16761 /* How many bytes in instructions we've already emitted? */
16762 i = buf - fragp->fr_literal - fragp->fr_fix;
16763 /* How many bytes in instructions from here to the end? */
16764 i = fragp->fr_var - i;
16766 /* Convert to instruction count. */
16768 /* Branch counts from the next instruction. */
16771 /* Branch over the jump. */
16772 buf = write_insn (buf, insn);
16775 buf = write_insn (buf, 0);
16777 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16779 /* beql $0, $0, 2f */
16781 /* Compute the PC offset from the current instruction to
16782 the end of the variable frag. */
16783 /* How many bytes in instructions we've already emitted? */
16784 i = buf - fragp->fr_literal - fragp->fr_fix;
16785 /* How many bytes in instructions from here to the end? */
16786 i = fragp->fr_var - i;
16787 /* Convert to instruction count. */
16789 /* Don't decrement i, because we want to branch over the
16793 buf = write_insn (buf, insn);
16794 buf = write_insn (buf, 0);
16798 if (mips_pic == NO_PIC)
16801 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16802 ? 0x0c000000 : 0x08000000);
16803 exp.X_op = O_symbol;
16804 exp.X_add_symbol = fragp->fr_symbol;
16805 exp.X_add_number = fragp->fr_offset;
16807 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16808 FALSE, BFD_RELOC_MIPS_JMP);
16809 fixp->fx_file = fragp->fr_file;
16810 fixp->fx_line = fragp->fr_line;
16812 buf = write_insn (buf, insn);
16816 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16818 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16819 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16820 insn |= at << OP_SH_RT;
16821 exp.X_op = O_symbol;
16822 exp.X_add_symbol = fragp->fr_symbol;
16823 exp.X_add_number = fragp->fr_offset;
16825 if (fragp->fr_offset)
16827 exp.X_add_symbol = make_expr_symbol (&exp);
16828 exp.X_add_number = 0;
16831 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16832 FALSE, BFD_RELOC_MIPS_GOT16);
16833 fixp->fx_file = fragp->fr_file;
16834 fixp->fx_line = fragp->fr_line;
16836 buf = write_insn (buf, insn);
16838 if (mips_opts.isa == ISA_MIPS1)
16840 buf = write_insn (buf, 0);
16842 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16843 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16844 insn |= at << OP_SH_RS | at << OP_SH_RT;
16846 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16847 FALSE, BFD_RELOC_LO16);
16848 fixp->fx_file = fragp->fr_file;
16849 fixp->fx_line = fragp->fr_line;
16851 buf = write_insn (buf, insn);
16854 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16858 insn |= at << OP_SH_RS;
16860 buf = write_insn (buf, insn);
16864 fragp->fr_fix += fragp->fr_var;
16865 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16869 /* Relax microMIPS branches. */
16870 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16872 char *buf = fragp->fr_literal + fragp->fr_fix;
16873 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16874 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16875 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16876 bfd_boolean short_ds;
16877 unsigned long insn;
16881 exp.X_op = O_symbol;
16882 exp.X_add_symbol = fragp->fr_symbol;
16883 exp.X_add_number = fragp->fr_offset;
16885 fragp->fr_fix += fragp->fr_var;
16887 /* Handle 16-bit branches that fit or are forced to fit. */
16888 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16890 /* We generate a fixup instead of applying it right now,
16891 because if there is linker relaxation, we're going to
16892 need the relocations. */
16894 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16895 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16896 else if (type == 'E')
16897 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16898 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16902 fixp->fx_file = fragp->fr_file;
16903 fixp->fx_line = fragp->fr_line;
16905 /* These relocations can have an addend that won't fit in
16907 fixp->fx_no_overflow = 1;
16912 /* Handle 32-bit branches that fit or are forced to fit. */
16913 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16914 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16916 /* We generate a fixup instead of applying it right now,
16917 because if there is linker relaxation, we're going to
16918 need the relocations. */
16919 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16920 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16921 fixp->fx_file = fragp->fr_file;
16922 fixp->fx_line = fragp->fr_line;
16928 /* Relax 16-bit branches to 32-bit branches. */
16931 insn = read_compressed_insn (buf, 2);
16933 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16934 insn = 0x94000000; /* beq */
16935 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16937 unsigned long regno;
16939 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16940 regno = micromips_to_32_reg_d_map [regno];
16941 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16942 insn |= regno << MICROMIPSOP_SH_RS;
16947 /* Nothing else to do, just write it out. */
16948 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16949 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16951 buf = write_compressed_insn (buf, insn, 4);
16952 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16957 insn = read_compressed_insn (buf, 4);
16959 /* Relax 32-bit branches to a sequence of instructions. */
16960 as_warn_where (fragp->fr_file, fragp->fr_line,
16961 _("Relaxed out-of-range branch into a jump"));
16963 /* Set the short-delay-slot bit. */
16964 short_ds = al && (insn & 0x02000000) != 0;
16966 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16970 /* Reverse the branch. */
16971 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16972 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16973 insn ^= 0x20000000;
16974 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16975 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16976 || (insn & 0xffe00000) == 0x40800000 /* blez */
16977 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16978 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16979 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16980 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16981 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16982 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16983 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16984 insn ^= 0x00400000;
16985 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16986 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16987 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16988 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16989 insn ^= 0x00200000;
16995 /* Clear the and-link and short-delay-slot bits. */
16996 gas_assert ((insn & 0xfda00000) == 0x40200000);
16998 /* bltzal 0x40200000 bgezal 0x40600000 */
16999 /* bltzals 0x42200000 bgezals 0x42600000 */
17000 insn &= ~0x02200000;
17003 /* Make a label at the end for use with the branch. */
17004 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17005 micromips_label_inc ();
17006 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17009 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17010 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17011 fixp->fx_file = fragp->fr_file;
17012 fixp->fx_line = fragp->fr_line;
17014 /* Branch over the jump. */
17015 buf = write_compressed_insn (buf, insn, 4);
17018 buf = write_compressed_insn (buf, 0x0c00, 2);
17021 if (mips_pic == NO_PIC)
17023 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17025 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17026 insn = al ? jal : 0xd4000000;
17028 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17029 BFD_RELOC_MICROMIPS_JMP);
17030 fixp->fx_file = fragp->fr_file;
17031 fixp->fx_line = fragp->fr_line;
17033 buf = write_compressed_insn (buf, insn, 4);
17036 buf = write_compressed_insn (buf, 0x0c00, 2);
17040 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17041 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17042 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17044 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17045 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17046 insn |= at << MICROMIPSOP_SH_RT;
17048 if (exp.X_add_number)
17050 exp.X_add_symbol = make_expr_symbol (&exp);
17051 exp.X_add_number = 0;
17054 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17055 BFD_RELOC_MICROMIPS_GOT16);
17056 fixp->fx_file = fragp->fr_file;
17057 fixp->fx_line = fragp->fr_line;
17059 buf = write_compressed_insn (buf, insn, 4);
17061 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17062 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17063 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17065 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17066 BFD_RELOC_MICROMIPS_LO16);
17067 fixp->fx_file = fragp->fr_file;
17068 fixp->fx_line = fragp->fr_line;
17070 buf = write_compressed_insn (buf, insn, 4);
17072 /* jr/jrc/jalr/jalrs $at */
17073 insn = al ? jalr : jr;
17074 insn |= at << MICROMIPSOP_SH_MJ;
17076 buf = write_compressed_insn (buf, insn, 2);
17079 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17083 if (RELAX_MIPS16_P (fragp->fr_subtype))
17086 const struct mips_int_operand *operand;
17089 unsigned int user_length, length;
17090 unsigned long insn;
17093 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17094 operand = mips16_immed_operand (type, FALSE);
17096 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17097 val = resolve_symbol_value (fragp->fr_symbol);
17098 if (operand->root.type == OP_PCREL)
17100 const struct mips_pcrel_operand *pcrel_op;
17103 pcrel_op = (const struct mips_pcrel_operand *) operand;
17104 addr = fragp->fr_address + fragp->fr_fix;
17106 /* The rules for the base address of a PC relative reloc are
17107 complicated; see mips16_extended_frag. */
17108 if (pcrel_op->include_isa_bit)
17113 /* Ignore the low bit in the target, since it will be
17114 set for a text label. */
17117 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17119 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17122 addr &= -(1 << pcrel_op->align_log2);
17125 /* Make sure the section winds up with the alignment we have
17127 if (operand->shift > 0)
17128 record_alignment (asec, operand->shift);
17132 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17133 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17134 as_warn_where (fragp->fr_file, fragp->fr_line,
17135 _("extended instruction in delay slot"));
17137 buf = fragp->fr_literal + fragp->fr_fix;
17139 insn = read_compressed_insn (buf, 2);
17141 insn |= MIPS16_EXTEND;
17143 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17145 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17150 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17151 BFD_RELOC_UNUSED, val, user_length, &insn);
17153 length = (ext ? 4 : 2);
17154 gas_assert (mips16_opcode_length (insn) == length);
17155 write_compressed_insn (buf, insn, length);
17156 fragp->fr_fix += length;
17160 relax_substateT subtype = fragp->fr_subtype;
17161 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17162 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17166 first = RELAX_FIRST (subtype);
17167 second = RELAX_SECOND (subtype);
17168 fixp = (fixS *) fragp->fr_opcode;
17170 /* If the delay slot chosen does not match the size of the instruction,
17171 then emit a warning. */
17172 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17173 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17178 s = subtype & (RELAX_DELAY_SLOT_16BIT
17179 | RELAX_DELAY_SLOT_SIZE_FIRST
17180 | RELAX_DELAY_SLOT_SIZE_SECOND);
17181 msg = macro_warning (s);
17183 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17187 /* Possibly emit a warning if we've chosen the longer option. */
17188 if (use_second == second_longer)
17194 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17195 msg = macro_warning (s);
17197 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17201 /* Go through all the fixups for the first sequence. Disable them
17202 (by marking them as done) if we're going to use the second
17203 sequence instead. */
17205 && fixp->fx_frag == fragp
17206 && fixp->fx_where < fragp->fr_fix - second)
17208 if (subtype & RELAX_USE_SECOND)
17210 fixp = fixp->fx_next;
17213 /* Go through the fixups for the second sequence. Disable them if
17214 we're going to use the first sequence, otherwise adjust their
17215 addresses to account for the relaxation. */
17216 while (fixp && fixp->fx_frag == fragp)
17218 if (subtype & RELAX_USE_SECOND)
17219 fixp->fx_where -= first;
17222 fixp = fixp->fx_next;
17225 /* Now modify the frag contents. */
17226 if (subtype & RELAX_USE_SECOND)
17230 start = fragp->fr_literal + fragp->fr_fix - first - second;
17231 memmove (start, start + first, second);
17232 fragp->fr_fix -= first;
17235 fragp->fr_fix -= second;
17239 /* This function is called after the relocs have been generated.
17240 We've been storing mips16 text labels as odd. Here we convert them
17241 back to even for the convenience of the debugger. */
17244 mips_frob_file_after_relocs (void)
17247 unsigned int count, i;
17249 syms = bfd_get_outsymbols (stdoutput);
17250 count = bfd_get_symcount (stdoutput);
17251 for (i = 0; i < count; i++, syms++)
17252 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17253 && ((*syms)->value & 1) != 0)
17255 (*syms)->value &= ~1;
17256 /* If the symbol has an odd size, it was probably computed
17257 incorrectly, so adjust that as well. */
17258 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17259 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17263 /* This function is called whenever a label is defined, including fake
17264 labels instantiated off the dot special symbol. It is used when
17265 handling branch delays; if a branch has a label, we assume we cannot
17266 move it. This also bumps the value of the symbol by 1 in compressed
17270 mips_record_label (symbolS *sym)
17272 segment_info_type *si = seg_info (now_seg);
17273 struct insn_label_list *l;
17275 if (free_insn_labels == NULL)
17276 l = (struct insn_label_list *) xmalloc (sizeof *l);
17279 l = free_insn_labels;
17280 free_insn_labels = l->next;
17284 l->next = si->label_list;
17285 si->label_list = l;
17288 /* This function is called as tc_frob_label() whenever a label is defined
17289 and adds a DWARF-2 record we only want for true labels. */
17292 mips_define_label (symbolS *sym)
17294 mips_record_label (sym);
17295 dwarf2_emit_label (sym);
17298 /* This function is called by tc_new_dot_label whenever a new dot symbol
17302 mips_add_dot_label (symbolS *sym)
17304 mips_record_label (sym);
17305 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17306 mips_compressed_mark_label (sym);
17309 /* Some special processing for a MIPS ELF file. */
17312 mips_elf_final_processing (void)
17314 /* Write out the register information. */
17315 if (mips_abi != N64_ABI)
17319 s.ri_gprmask = mips_gprmask;
17320 s.ri_cprmask[0] = mips_cprmask[0];
17321 s.ri_cprmask[1] = mips_cprmask[1];
17322 s.ri_cprmask[2] = mips_cprmask[2];
17323 s.ri_cprmask[3] = mips_cprmask[3];
17324 /* The gp_value field is set by the MIPS ELF backend. */
17326 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17327 ((Elf32_External_RegInfo *)
17328 mips_regmask_frag));
17332 Elf64_Internal_RegInfo s;
17334 s.ri_gprmask = mips_gprmask;
17336 s.ri_cprmask[0] = mips_cprmask[0];
17337 s.ri_cprmask[1] = mips_cprmask[1];
17338 s.ri_cprmask[2] = mips_cprmask[2];
17339 s.ri_cprmask[3] = mips_cprmask[3];
17340 /* The gp_value field is set by the MIPS ELF backend. */
17342 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17343 ((Elf64_External_RegInfo *)
17344 mips_regmask_frag));
17347 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17348 sort of BFD interface for this. */
17349 if (mips_any_noreorder)
17350 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17351 if (mips_pic != NO_PIC)
17353 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
17354 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17357 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17359 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17360 defined at present; this might need to change in future. */
17361 if (file_ase_mips16)
17362 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17363 if (file_ase_micromips)
17364 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17365 if (file_ase & ASE_MDMX)
17366 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17368 /* Set the MIPS ELF ABI flags. */
17369 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17370 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17371 else if (mips_abi == O64_ABI)
17372 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17373 else if (mips_abi == EABI_ABI)
17375 if (!file_mips_gp32)
17376 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17378 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17380 else if (mips_abi == N32_ABI)
17381 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17383 /* Nothing to do for N64_ABI. */
17385 if (mips_32bitmode)
17386 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17388 if (mips_flag_nan2008)
17389 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17391 #if 0 /* XXX FIXME */
17392 /* 32 bit code with 64 bit FP registers. */
17393 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17394 elf_elfheader (stdoutput)->e_flags |= ???;
17398 typedef struct proc {
17400 symbolS *func_end_sym;
17401 unsigned long reg_mask;
17402 unsigned long reg_offset;
17403 unsigned long fpreg_mask;
17404 unsigned long fpreg_offset;
17405 unsigned long frame_offset;
17406 unsigned long frame_reg;
17407 unsigned long pc_reg;
17410 static procS cur_proc;
17411 static procS *cur_proc_ptr;
17412 static int numprocs;
17414 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17415 as "2", and a normal nop as "0". */
17417 #define NOP_OPCODE_MIPS 0
17418 #define NOP_OPCODE_MIPS16 1
17419 #define NOP_OPCODE_MICROMIPS 2
17422 mips_nop_opcode (void)
17424 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17425 return NOP_OPCODE_MICROMIPS;
17426 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17427 return NOP_OPCODE_MIPS16;
17429 return NOP_OPCODE_MIPS;
17432 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17433 32-bit microMIPS NOPs here (if applicable). */
17436 mips_handle_align (fragS *fragp)
17440 int bytes, size, excess;
17443 if (fragp->fr_type != rs_align_code)
17446 p = fragp->fr_literal + fragp->fr_fix;
17448 switch (nop_opcode)
17450 case NOP_OPCODE_MICROMIPS:
17451 opcode = micromips_nop32_insn.insn_opcode;
17454 case NOP_OPCODE_MIPS16:
17455 opcode = mips16_nop_insn.insn_opcode;
17458 case NOP_OPCODE_MIPS:
17460 opcode = nop_insn.insn_opcode;
17465 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17466 excess = bytes % size;
17468 /* Handle the leading part if we're not inserting a whole number of
17469 instructions, and make it the end of the fixed part of the frag.
17470 Try to fit in a short microMIPS NOP if applicable and possible,
17471 and use zeroes otherwise. */
17472 gas_assert (excess < 4);
17473 fragp->fr_fix += excess;
17478 /* Fall through. */
17480 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17482 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17486 /* Fall through. */
17489 /* Fall through. */
17494 md_number_to_chars (p, opcode, size);
17495 fragp->fr_var = size;
17499 md_obj_begin (void)
17506 /* Check for premature end, nesting errors, etc. */
17508 as_warn (_("missing .end at end of assembly"));
17517 if (*input_line_pointer == '-')
17519 ++input_line_pointer;
17522 if (!ISDIGIT (*input_line_pointer))
17523 as_bad (_("expected simple number"));
17524 if (input_line_pointer[0] == '0')
17526 if (input_line_pointer[1] == 'x')
17528 input_line_pointer += 2;
17529 while (ISXDIGIT (*input_line_pointer))
17532 val |= hex_value (*input_line_pointer++);
17534 return negative ? -val : val;
17538 ++input_line_pointer;
17539 while (ISDIGIT (*input_line_pointer))
17542 val |= *input_line_pointer++ - '0';
17544 return negative ? -val : val;
17547 if (!ISDIGIT (*input_line_pointer))
17549 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17550 *input_line_pointer, *input_line_pointer);
17551 as_warn (_("invalid number"));
17554 while (ISDIGIT (*input_line_pointer))
17557 val += *input_line_pointer++ - '0';
17559 return negative ? -val : val;
17562 /* The .file directive; just like the usual .file directive, but there
17563 is an initial number which is the ECOFF file index. In the non-ECOFF
17564 case .file implies DWARF-2. */
17567 s_mips_file (int x ATTRIBUTE_UNUSED)
17569 static int first_file_directive = 0;
17571 if (ECOFF_DEBUGGING)
17580 filename = dwarf2_directive_file (0);
17582 /* Versions of GCC up to 3.1 start files with a ".file"
17583 directive even for stabs output. Make sure that this
17584 ".file" is handled. Note that you need a version of GCC
17585 after 3.1 in order to support DWARF-2 on MIPS. */
17586 if (filename != NULL && ! first_file_directive)
17588 (void) new_logical_line (filename, -1);
17589 s_app_file_string (filename, 0);
17591 first_file_directive = 1;
17595 /* The .loc directive, implying DWARF-2. */
17598 s_mips_loc (int x ATTRIBUTE_UNUSED)
17600 if (!ECOFF_DEBUGGING)
17601 dwarf2_directive_loc (0);
17604 /* The .end directive. */
17607 s_mips_end (int x ATTRIBUTE_UNUSED)
17611 /* Following functions need their own .frame and .cprestore directives. */
17612 mips_frame_reg_valid = 0;
17613 mips_cprestore_valid = 0;
17615 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17618 demand_empty_rest_of_line ();
17623 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17624 as_warn (_(".end not in text section"));
17628 as_warn (_(".end directive without a preceding .ent directive."));
17629 demand_empty_rest_of_line ();
17635 gas_assert (S_GET_NAME (p));
17636 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17637 as_warn (_(".end symbol does not match .ent symbol."));
17639 if (debug_type == DEBUG_STABS)
17640 stabs_generate_asm_endfunc (S_GET_NAME (p),
17644 as_warn (_(".end directive missing or unknown symbol"));
17646 /* Create an expression to calculate the size of the function. */
17647 if (p && cur_proc_ptr)
17649 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17650 expressionS *exp = xmalloc (sizeof (expressionS));
17653 exp->X_op = O_subtract;
17654 exp->X_add_symbol = symbol_temp_new_now ();
17655 exp->X_op_symbol = p;
17656 exp->X_add_number = 0;
17658 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17661 /* Generate a .pdr section. */
17662 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17664 segT saved_seg = now_seg;
17665 subsegT saved_subseg = now_subseg;
17669 #ifdef md_flush_pending_output
17670 md_flush_pending_output ();
17673 gas_assert (pdr_seg);
17674 subseg_set (pdr_seg, 0);
17676 /* Write the symbol. */
17677 exp.X_op = O_symbol;
17678 exp.X_add_symbol = p;
17679 exp.X_add_number = 0;
17680 emit_expr (&exp, 4);
17682 fragp = frag_more (7 * 4);
17684 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17685 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17686 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17687 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17688 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17689 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17690 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17692 subseg_set (saved_seg, saved_subseg);
17695 cur_proc_ptr = NULL;
17698 /* The .aent and .ent directives. */
17701 s_mips_ent (int aent)
17705 symbolP = get_symbol ();
17706 if (*input_line_pointer == ',')
17707 ++input_line_pointer;
17708 SKIP_WHITESPACE ();
17709 if (ISDIGIT (*input_line_pointer)
17710 || *input_line_pointer == '-')
17713 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17714 as_warn (_(".ent or .aent not in text section."));
17716 if (!aent && cur_proc_ptr)
17717 as_warn (_("missing .end"));
17721 /* This function needs its own .frame and .cprestore directives. */
17722 mips_frame_reg_valid = 0;
17723 mips_cprestore_valid = 0;
17725 cur_proc_ptr = &cur_proc;
17726 memset (cur_proc_ptr, '\0', sizeof (procS));
17728 cur_proc_ptr->func_sym = symbolP;
17732 if (debug_type == DEBUG_STABS)
17733 stabs_generate_asm_func (S_GET_NAME (symbolP),
17734 S_GET_NAME (symbolP));
17737 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17739 demand_empty_rest_of_line ();
17742 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17743 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17744 s_mips_frame is used so that we can set the PDR information correctly.
17745 We can't use the ecoff routines because they make reference to the ecoff
17746 symbol table (in the mdebug section). */
17749 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17751 if (ECOFF_DEBUGGING)
17757 if (cur_proc_ptr == (procS *) NULL)
17759 as_warn (_(".frame outside of .ent"));
17760 demand_empty_rest_of_line ();
17764 cur_proc_ptr->frame_reg = tc_get_register (1);
17766 SKIP_WHITESPACE ();
17767 if (*input_line_pointer++ != ','
17768 || get_absolute_expression_and_terminator (&val) != ',')
17770 as_warn (_("Bad .frame directive"));
17771 --input_line_pointer;
17772 demand_empty_rest_of_line ();
17776 cur_proc_ptr->frame_offset = val;
17777 cur_proc_ptr->pc_reg = tc_get_register (0);
17779 demand_empty_rest_of_line ();
17783 /* The .fmask and .mask directives. If the mdebug section is present
17784 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17785 embedded targets, s_mips_mask is used so that we can set the PDR
17786 information correctly. We can't use the ecoff routines because they
17787 make reference to the ecoff symbol table (in the mdebug section). */
17790 s_mips_mask (int reg_type)
17792 if (ECOFF_DEBUGGING)
17793 s_ignore (reg_type);
17798 if (cur_proc_ptr == (procS *) NULL)
17800 as_warn (_(".mask/.fmask outside of .ent"));
17801 demand_empty_rest_of_line ();
17805 if (get_absolute_expression_and_terminator (&mask) != ',')
17807 as_warn (_("Bad .mask/.fmask directive"));
17808 --input_line_pointer;
17809 demand_empty_rest_of_line ();
17813 off = get_absolute_expression ();
17815 if (reg_type == 'F')
17817 cur_proc_ptr->fpreg_mask = mask;
17818 cur_proc_ptr->fpreg_offset = off;
17822 cur_proc_ptr->reg_mask = mask;
17823 cur_proc_ptr->reg_offset = off;
17826 demand_empty_rest_of_line ();
17830 /* A table describing all the processors gas knows about. Names are
17831 matched in the order listed.
17833 To ease comparison, please keep this table in the same order as
17834 gcc's mips_cpu_info_table[]. */
17835 static const struct mips_cpu_info mips_cpu_info_table[] =
17837 /* Entries for generic ISAs */
17838 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17839 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17840 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17841 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17842 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17843 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17844 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17845 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17846 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17849 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17850 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17851 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17854 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17857 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17858 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17859 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17860 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17861 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17862 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17863 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17864 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17865 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17866 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17867 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17868 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17869 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17870 /* ST Microelectronics Loongson 2E and 2F cores */
17871 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17872 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17875 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17876 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17877 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17878 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17879 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17880 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17881 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17882 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17883 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17884 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17885 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17886 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17887 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17888 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17889 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17892 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17893 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17894 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17895 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17897 /* MIPS 32 Release 2 */
17898 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17899 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17900 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17901 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17902 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17903 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17904 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17905 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17906 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17907 ISA_MIPS32R2, CPU_MIPS32R2 },
17908 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17909 ISA_MIPS32R2, CPU_MIPS32R2 },
17910 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17911 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17912 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17913 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17914 /* Deprecated forms of the above. */
17915 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17916 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17917 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17918 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17919 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17920 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17921 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17922 /* Deprecated forms of the above. */
17923 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17924 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17925 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17926 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17927 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17928 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17929 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17930 /* Deprecated forms of the above. */
17931 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17932 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17933 /* 34Kn is a 34kc without DSP. */
17934 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17935 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17936 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17937 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17938 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17939 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17940 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17941 /* Deprecated forms of the above. */
17942 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17943 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17944 /* 1004K cores are multiprocessor versions of the 34K. */
17945 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17946 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17947 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17948 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17951 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17952 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17953 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17954 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17956 /* Broadcom SB-1 CPU core */
17957 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17958 /* Broadcom SB-1A CPU core */
17959 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17961 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17963 /* MIPS 64 Release 2 */
17965 /* Cavium Networks Octeon CPU core */
17966 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17967 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17968 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17971 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17974 XLP is mostly like XLR, with the prominent exception that it is
17975 MIPS64R2 rather than MIPS64. */
17976 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17979 { NULL, 0, 0, 0, 0 }
17983 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17984 with a final "000" replaced by "k". Ignore case.
17986 Note: this function is shared between GCC and GAS. */
17989 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17991 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17992 given++, canonical++;
17994 return ((*given == 0 && *canonical == 0)
17995 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17999 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18000 CPU name. We've traditionally allowed a lot of variation here.
18002 Note: this function is shared between GCC and GAS. */
18005 mips_matching_cpu_name_p (const char *canonical, const char *given)
18007 /* First see if the name matches exactly, or with a final "000"
18008 turned into "k". */
18009 if (mips_strict_matching_cpu_name_p (canonical, given))
18012 /* If not, try comparing based on numerical designation alone.
18013 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18014 if (TOLOWER (*given) == 'r')
18016 if (!ISDIGIT (*given))
18019 /* Skip over some well-known prefixes in the canonical name,
18020 hoping to find a number there too. */
18021 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18023 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18025 else if (TOLOWER (canonical[0]) == 'r')
18028 return mips_strict_matching_cpu_name_p (canonical, given);
18032 /* Parse an option that takes the name of a processor as its argument.
18033 OPTION is the name of the option and CPU_STRING is the argument.
18034 Return the corresponding processor enumeration if the CPU_STRING is
18035 recognized, otherwise report an error and return null.
18037 A similar function exists in GCC. */
18039 static const struct mips_cpu_info *
18040 mips_parse_cpu (const char *option, const char *cpu_string)
18042 const struct mips_cpu_info *p;
18044 /* 'from-abi' selects the most compatible architecture for the given
18045 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18046 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18047 version. Look first at the -mgp options, if given, otherwise base
18048 the choice on MIPS_DEFAULT_64BIT.
18050 Treat NO_ABI like the EABIs. One reason to do this is that the
18051 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18052 architecture. This code picks MIPS I for 'mips' and MIPS III for
18053 'mips64', just as we did in the days before 'from-abi'. */
18054 if (strcasecmp (cpu_string, "from-abi") == 0)
18056 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18057 return mips_cpu_info_from_isa (ISA_MIPS1);
18059 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18060 return mips_cpu_info_from_isa (ISA_MIPS3);
18062 if (file_mips_gp32 >= 0)
18063 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
18065 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18070 /* 'default' has traditionally been a no-op. Probably not very useful. */
18071 if (strcasecmp (cpu_string, "default") == 0)
18074 for (p = mips_cpu_info_table; p->name != 0; p++)
18075 if (mips_matching_cpu_name_p (p->name, cpu_string))
18078 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
18082 /* Return the canonical processor information for ISA (a member of the
18083 ISA_MIPS* enumeration). */
18085 static const struct mips_cpu_info *
18086 mips_cpu_info_from_isa (int isa)
18090 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18091 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18092 && isa == mips_cpu_info_table[i].isa)
18093 return (&mips_cpu_info_table[i]);
18098 static const struct mips_cpu_info *
18099 mips_cpu_info_from_arch (int arch)
18103 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18104 if (arch == mips_cpu_info_table[i].cpu)
18105 return (&mips_cpu_info_table[i]);
18111 show (FILE *stream, const char *string, int *col_p, int *first_p)
18115 fprintf (stream, "%24s", "");
18120 fprintf (stream, ", ");
18124 if (*col_p + strlen (string) > 72)
18126 fprintf (stream, "\n%24s", "");
18130 fprintf (stream, "%s", string);
18131 *col_p += strlen (string);
18137 md_show_usage (FILE *stream)
18142 fprintf (stream, _("\
18144 -EB generate big endian output\n\
18145 -EL generate little endian output\n\
18146 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18147 -G NUM allow referencing objects up to NUM bytes\n\
18148 implicitly with the gp register [default 8]\n"));
18149 fprintf (stream, _("\
18150 -mips1 generate MIPS ISA I instructions\n\
18151 -mips2 generate MIPS ISA II instructions\n\
18152 -mips3 generate MIPS ISA III instructions\n\
18153 -mips4 generate MIPS ISA IV instructions\n\
18154 -mips5 generate MIPS ISA V instructions\n\
18155 -mips32 generate MIPS32 ISA instructions\n\
18156 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18157 -mips64 generate MIPS64 ISA instructions\n\
18158 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18159 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18163 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18164 show (stream, mips_cpu_info_table[i].name, &column, &first);
18165 show (stream, "from-abi", &column, &first);
18166 fputc ('\n', stream);
18168 fprintf (stream, _("\
18169 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18170 -no-mCPU don't generate code specific to CPU.\n\
18171 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18175 show (stream, "3900", &column, &first);
18176 show (stream, "4010", &column, &first);
18177 show (stream, "4100", &column, &first);
18178 show (stream, "4650", &column, &first);
18179 fputc ('\n', stream);
18181 fprintf (stream, _("\
18182 -mips16 generate mips16 instructions\n\
18183 -no-mips16 do not generate mips16 instructions\n"));
18184 fprintf (stream, _("\
18185 -mmicromips generate microMIPS instructions\n\
18186 -mno-micromips do not generate microMIPS instructions\n"));
18187 fprintf (stream, _("\
18188 -msmartmips generate smartmips instructions\n\
18189 -mno-smartmips do not generate smartmips instructions\n"));
18190 fprintf (stream, _("\
18191 -mdsp generate DSP instructions\n\
18192 -mno-dsp do not generate DSP instructions\n"));
18193 fprintf (stream, _("\
18194 -mdspr2 generate DSP R2 instructions\n\
18195 -mno-dspr2 do not generate DSP R2 instructions\n"));
18196 fprintf (stream, _("\
18197 -mmt generate MT instructions\n\
18198 -mno-mt do not generate MT instructions\n"));
18199 fprintf (stream, _("\
18200 -mmcu generate MCU instructions\n\
18201 -mno-mcu do not generate MCU instructions\n"));
18202 fprintf (stream, _("\
18203 -mvirt generate Virtualization instructions\n\
18204 -mno-virt do not generate Virtualization instructions\n"));
18205 fprintf (stream, _("\
18206 -minsn32 only generate 32-bit microMIPS instructions\n\
18207 -mno-insn32 generate all microMIPS instructions\n"));
18208 fprintf (stream, _("\
18209 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18210 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18211 -mfix-vr4120 work around certain VR4120 errata\n\
18212 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18213 -mfix-24k insert a nop after ERET and DERET instructions\n\
18214 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18215 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18216 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18217 -msym32 assume all symbols have 32-bit values\n\
18218 -O0 remove unneeded NOPs, do not swap branches\n\
18219 -O remove unneeded NOPs and swap branches\n\
18220 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18221 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18222 fprintf (stream, _("\
18223 -mhard-float allow floating-point instructions\n\
18224 -msoft-float do not allow floating-point instructions\n\
18225 -msingle-float only allow 32-bit floating-point operations\n\
18226 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18227 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18228 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18229 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18233 show (stream, "legacy", &column, &first);
18234 show (stream, "2008", &column, &first);
18236 fputc ('\n', stream);
18238 fprintf (stream, _("\
18239 -KPIC, -call_shared generate SVR4 position independent code\n\
18240 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18241 -mvxworks-pic generate VxWorks position independent code\n\
18242 -non_shared do not generate code that can operate with DSOs\n\
18243 -xgot assume a 32 bit GOT\n\
18244 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18245 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18246 position dependent (non shared) code\n\
18247 -mabi=ABI create ABI conformant object file for:\n"));
18251 show (stream, "32", &column, &first);
18252 show (stream, "o64", &column, &first);
18253 show (stream, "n32", &column, &first);
18254 show (stream, "64", &column, &first);
18255 show (stream, "eabi", &column, &first);
18257 fputc ('\n', stream);
18259 fprintf (stream, _("\
18260 -32 create o32 ABI object file (default)\n\
18261 -n32 create n32 ABI object file\n\
18262 -64 create 64 ABI object file\n"));
18267 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
18269 if (HAVE_64BIT_SYMBOLS)
18270 return dwarf2_format_64bit_irix;
18272 return dwarf2_format_32bit;
18277 mips_dwarf2_addr_size (void)
18279 if (HAVE_64BIT_OBJECTS)
18285 /* Standard calling conventions leave the CFA at SP on entry. */
18287 mips_cfi_frame_initial_instructions (void)
18289 cfi_add_CFA_def_cfa_register (SP);
18293 tc_mips_regname_to_dw2regnum (char *regname)
18295 unsigned int regnum = -1;
18298 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))