1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi = NO_ABI;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls = FALSE;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32 = -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32 = -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts =
202 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask;
209 unsigned long mips_cprmask[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa = ISA_UNKNOWN;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch = CPU_UNKNOWN;
228 static const char *mips_arch_string;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune = CPU_UNKNOWN;
233 static const char *mips_tune_string;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode = 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* True if relocations are stored in-place. */
283 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
285 /* We can only have 64bit addresses if the object file format supports it. */
286 #define HAVE_32BIT_ADDRESSES \
288 || (bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS)) \
291 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
293 /* Addresses are loaded in different ways, depending on the address size
294 in use. The n32 ABI Documentation also mandates the use of additions
295 with overflow checking, but existing implementations don't follow it. */
296 #define ADDRESS_ADD_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
299 #define ADDRESS_ADDI_INSN \
300 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
302 #define ADDRESS_LOAD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
305 #define ADDRESS_STORE_INSN \
306 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
308 /* Return true if the given CPU supports the MIPS16 ASE. */
309 #define CPU_HAS_MIPS16(cpu) \
310 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
311 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
313 /* Return true if the given CPU supports the MIPS3D ASE. */
314 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
317 /* Return true if the given CPU supports the MDMX ASE. */
318 #define CPU_HAS_MDMX(cpu) (FALSE \
321 /* True if CPU has a dror instruction. */
322 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
324 /* True if CPU has a ror instruction. */
325 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
327 /* True if mflo and mfhi can be immediately followed by instructions
328 which write to the HI and LO registers.
330 According to MIPS specifications, MIPS ISAs I, II, and III need
331 (at least) two instructions between the reads of HI/LO and
332 instructions which write them, and later ISAs do not. Contradicting
333 the MIPS specifications, some MIPS IV processor user manuals (e.g.
334 the UM for the NEC Vr5000) document needing the instructions between
335 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
336 MIPS64 and later ISAs to have the interlocks, plus any specific
337 earlier-ISA CPUs for which CPU documentation declares that the
338 instructions are really interlocked. */
339 #define hilo_interlocks \
340 (mips_opts.isa == ISA_MIPS32 \
341 || mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_R10000 \
346 || mips_opts.arch == CPU_R12000 \
347 || mips_opts.arch == CPU_RM7000 \
348 || mips_opts.arch == CPU_VR5500 \
351 /* Whether the processor uses hardware interlocks to protect reads
352 from the GPRs after they are loaded from memory, and thus does not
353 require nops to be inserted. This applies to instructions marked
354 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
356 #define gpr_interlocks \
357 (mips_opts.isa != ISA_MIPS1 \
358 || mips_opts.arch == CPU_R3900)
360 /* Whether the processor uses hardware interlocks to avoid delays
361 required by coprocessor instructions, and thus does not require
362 nops to be inserted. This applies to instructions marked
363 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
364 between instructions marked INSN_WRITE_COND_CODE and ones marked
365 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
366 levels I, II, and III. */
367 /* Itbl support may require additional care here. */
368 #define cop_interlocks \
369 ((mips_opts.isa != ISA_MIPS1 \
370 && mips_opts.isa != ISA_MIPS2 \
371 && mips_opts.isa != ISA_MIPS3) \
372 || mips_opts.arch == CPU_R4300 \
375 /* Whether the processor uses hardware interlocks to protect reads
376 from coprocessor registers after they are loaded from memory, and
377 thus does not require nops to be inserted. This applies to
378 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
379 requires at MIPS ISA level I. */
380 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
382 /* Is this a mfhi or mflo instruction? */
383 #define MF_HILO_INSN(PINFO) \
384 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
386 /* MIPS PIC level. */
388 enum mips_pic_level mips_pic;
390 /* 1 if we should generate 32 bit offsets from the $gp register in
391 SVR4_PIC mode. Currently has no meaning in other modes. */
392 static int mips_big_got = 0;
394 /* 1 if trap instructions should used for overflow rather than break
396 static int mips_trap = 0;
398 /* 1 if double width floating point constants should not be constructed
399 by assembling two single width halves into two single width floating
400 point registers which just happen to alias the double width destination
401 register. On some architectures this aliasing can be disabled by a bit
402 in the status register, and the setting of this bit cannot be determined
403 automatically at assemble time. */
404 static int mips_disable_float_construction;
406 /* Non-zero if any .set noreorder directives were used. */
408 static int mips_any_noreorder;
410 /* Non-zero if nops should be inserted when the register referenced in
411 an mfhi/mflo instruction is read in the next two instructions. */
412 static int mips_7000_hilo_fix;
414 /* The size of the small data section. */
415 static unsigned int g_switch_value = 8;
416 /* Whether the -G option was used. */
417 static int g_switch_seen = 0;
422 /* If we can determine in advance that GP optimization won't be
423 possible, we can skip the relaxation stuff that tries to produce
424 GP-relative references. This makes delay slot optimization work
427 This function can only provide a guess, but it seems to work for
428 gcc output. It needs to guess right for gcc, otherwise gcc
429 will put what it thinks is a GP-relative instruction in a branch
432 I don't know if a fix is needed for the SVR4_PIC mode. I've only
433 fixed it for the non-PIC mode. KR 95/04/07 */
434 static int nopic_need_relax (symbolS *, int);
436 /* handle of the OPCODE hash table */
437 static struct hash_control *op_hash = NULL;
439 /* The opcode hash table we use for the mips16. */
440 static struct hash_control *mips16_op_hash = NULL;
442 /* This array holds the chars that always start a comment. If the
443 pre-processor is disabled, these aren't very useful */
444 const char comment_chars[] = "#";
446 /* This array holds the chars that only start a comment at the beginning of
447 a line. If the line seems to have the form '# 123 filename'
448 .line and .file directives will appear in the pre-processed output */
449 /* Note that input_file.c hand checks for '#' at the beginning of the
450 first line of the input file. This is because the compiler outputs
451 #NO_APP at the beginning of its output. */
452 /* Also note that C style comments are always supported. */
453 const char line_comment_chars[] = "#";
455 /* This array holds machine specific line separator characters. */
456 const char line_separator_chars[] = ";";
458 /* Chars that can be used to separate mant from exp in floating point nums */
459 const char EXP_CHARS[] = "eE";
461 /* Chars that mean this number is a floating point constant */
464 const char FLT_CHARS[] = "rRsSfFdDxXpP";
466 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
467 changed in read.c . Ideally it shouldn't have to know about it at all,
468 but nothing is ideal around here.
471 static char *insn_error;
473 static int auto_align = 1;
475 /* When outputting SVR4 PIC code, the assembler needs to know the
476 offset in the stack frame from which to restore the $gp register.
477 This is set by the .cprestore pseudo-op, and saved in this
479 static offsetT mips_cprestore_offset = -1;
481 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
482 more optimizations, it can use a register value instead of a memory-saved
483 offset and even an other register than $gp as global pointer. */
484 static offsetT mips_cpreturn_offset = -1;
485 static int mips_cpreturn_register = -1;
486 static int mips_gp_register = GP;
487 static int mips_gprel_offset = 0;
489 /* Whether mips_cprestore_offset has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_cprestore_valid = 0;
493 /* This is the register which holds the stack frame, as set by the
494 .frame pseudo-op. This is needed to implement .cprestore. */
495 static int mips_frame_reg = SP;
497 /* Whether mips_frame_reg has been set in the current function
498 (or whether it has already been warned about, if not). */
499 static int mips_frame_reg_valid = 0;
501 /* To output NOP instructions correctly, we need to keep information
502 about the previous two instructions. */
504 /* Whether we are optimizing. The default value of 2 means to remove
505 unneeded NOPs and swap branch instructions when possible. A value
506 of 1 means to not swap branches. A value of 0 means to always
508 static int mips_optimize = 2;
510 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
511 equivalent to seeing no -g option at all. */
512 static int mips_debug = 0;
514 /* The previous instruction. */
515 static struct mips_cl_insn prev_insn;
517 /* The instruction before prev_insn. */
518 static struct mips_cl_insn prev_prev_insn;
520 /* If we don't want information for prev_insn or prev_prev_insn, we
521 point the insn_mo field at this dummy integer. */
522 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
524 /* Non-zero if prev_insn is valid. */
525 static int prev_insn_valid;
527 /* The frag for the previous instruction. */
528 static struct frag *prev_insn_frag;
530 /* The offset into prev_insn_frag for the previous instruction. */
531 static long prev_insn_where;
533 /* The reloc type for the previous instruction, if any. */
534 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
536 /* The reloc for the previous instruction, if any. */
537 static fixS *prev_insn_fixp[3];
539 /* Non-zero if the previous instruction was in a delay slot. */
540 static int prev_insn_is_delay_slot;
542 /* Non-zero if the previous instruction was in a .set noreorder. */
543 static int prev_insn_unreordered;
545 /* Non-zero if the previous instruction uses an extend opcode (if
547 static int prev_insn_extended;
549 /* Non-zero if the previous previous instruction was in a .set
551 static int prev_prev_insn_unreordered;
553 /* If this is set, it points to a frag holding nop instructions which
554 were inserted before the start of a noreorder section. If those
555 nops turn out to be unnecessary, the size of the frag can be
557 static fragS *prev_nop_frag;
559 /* The number of nop instructions we created in prev_nop_frag. */
560 static int prev_nop_frag_holds;
562 /* The number of nop instructions that we know we need in
564 static int prev_nop_frag_required;
566 /* The number of instructions we've seen since prev_nop_frag. */
567 static int prev_nop_frag_since;
569 /* For ECOFF and ELF, relocations against symbols are done in two
570 parts, with a HI relocation and a LO relocation. Each relocation
571 has only 16 bits of space to store an addend. This means that in
572 order for the linker to handle carries correctly, it must be able
573 to locate both the HI and the LO relocation. This means that the
574 relocations must appear in order in the relocation table.
576 In order to implement this, we keep track of each unmatched HI
577 relocation. We then sort them so that they immediately precede the
578 corresponding LO relocation. */
583 struct mips_hi_fixup *next;
586 /* The section this fixup is in. */
590 /* The list of unmatched HI relocs. */
592 static struct mips_hi_fixup *mips_hi_fixup_list;
594 /* The frag containing the last explicit relocation operator.
595 Null if explicit relocations have not been used. */
597 static fragS *prev_reloc_op_frag;
599 /* Map normal MIPS register numbers to mips16 register numbers. */
601 #define X ILLEGAL_REG
602 static const int mips32_to_16_reg_map[] =
604 X, X, 2, 3, 4, 5, 6, 7,
605 X, X, X, X, X, X, X, X,
606 0, 1, X, X, X, X, X, X,
607 X, X, X, X, X, X, X, X
611 /* Map mips16 register numbers to normal MIPS register numbers. */
613 static const unsigned int mips16_to_32_reg_map[] =
615 16, 17, 2, 3, 4, 5, 6, 7
618 static int mips_fix_vr4120;
620 /* We don't relax branches by default, since this causes us to expand
621 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
622 fail to compute the offset before expanding the macro to the most
623 efficient expansion. */
625 static int mips_relax_branch;
627 /* The expansion of many macros depends on the type of symbol that
628 they refer to. For example, when generating position-dependent code,
629 a macro that refers to a symbol may have two different expansions,
630 one which uses GP-relative addresses and one which uses absolute
631 addresses. When generating SVR4-style PIC, a macro may have
632 different expansions for local and global symbols.
634 We handle these situations by generating both sequences and putting
635 them in variant frags. In position-dependent code, the first sequence
636 will be the GP-relative one and the second sequence will be the
637 absolute one. In SVR4 PIC, the first sequence will be for global
638 symbols and the second will be for local symbols.
640 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
641 SECOND are the lengths of the two sequences in bytes. These fields
642 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
643 the subtype has the following flags:
646 Set if it has been decided that we should use the second
647 sequence instead of the first.
650 Set in the first variant frag if the macro's second implementation
651 is longer than its first. This refers to the macro as a whole,
652 not an individual relaxation.
655 Set in the first variant frag if the macro appeared in a .set nomacro
656 block and if one alternative requires a warning but the other does not.
659 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
662 The frag's "opcode" points to the first fixup for relaxable code.
664 Relaxable macros are generated using a sequence such as:
666 relax_start (SYMBOL);
667 ... generate first expansion ...
669 ... generate second expansion ...
672 The code and fixups for the unwanted alternative are discarded
673 by md_convert_frag. */
674 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
676 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
677 #define RELAX_SECOND(X) ((X) & 0xff)
678 #define RELAX_USE_SECOND 0x10000
679 #define RELAX_SECOND_LONGER 0x20000
680 #define RELAX_NOMACRO 0x40000
681 #define RELAX_DELAY_SLOT 0x80000
683 /* Branch without likely bit. If label is out of range, we turn:
685 beq reg1, reg2, label
695 with the following opcode replacements:
702 bltzal <-> bgezal (with jal label instead of j label)
704 Even though keeping the delay slot instruction in the delay slot of
705 the branch would be more efficient, it would be very tricky to do
706 correctly, because we'd have to introduce a variable frag *after*
707 the delay slot instruction, and expand that instead. Let's do it
708 the easy way for now, even if the branch-not-taken case now costs
709 one additional instruction. Out-of-range branches are not supposed
710 to be common, anyway.
712 Branch likely. If label is out of range, we turn:
714 beql reg1, reg2, label
715 delay slot (annulled if branch not taken)
724 delay slot (executed only if branch taken)
727 It would be possible to generate a shorter sequence by losing the
728 likely bit, generating something like:
733 delay slot (executed only if branch taken)
745 bltzall -> bgezal (with jal label instead of j label)
746 bgezall -> bltzal (ditto)
749 but it's not clear that it would actually improve performance. */
750 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
753 | ((toofar) ? 1 : 0) \
755 | ((likely) ? 4 : 0) \
756 | ((uncond) ? 8 : 0)))
757 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
758 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
759 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
760 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
761 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
763 /* For mips16 code, we use an entirely different form of relaxation.
764 mips16 supports two versions of most instructions which take
765 immediate values: a small one which takes some small value, and a
766 larger one which takes a 16 bit value. Since branches also follow
767 this pattern, relaxing these values is required.
769 We can assemble both mips16 and normal MIPS code in a single
770 object. Therefore, we need to support this type of relaxation at
771 the same time that we support the relaxation described above. We
772 use the high bit of the subtype field to distinguish these cases.
774 The information we store for this type of relaxation is the
775 argument code found in the opcode file for this relocation, whether
776 the user explicitly requested a small or extended form, and whether
777 the relocation is in a jump or jal delay slot. That tells us the
778 size of the value, and how it should be stored. We also store
779 whether the fragment is considered to be extended or not. We also
780 store whether this is known to be a branch to a different section,
781 whether we have tried to relax this frag yet, and whether we have
782 ever extended a PC relative fragment because of a shift count. */
783 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
786 | ((small) ? 0x100 : 0) \
787 | ((ext) ? 0x200 : 0) \
788 | ((dslot) ? 0x400 : 0) \
789 | ((jal_dslot) ? 0x800 : 0))
790 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
791 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
792 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
793 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
794 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
795 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
796 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
797 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
798 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
799 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
800 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
801 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
803 /* Is the given value a sign-extended 32-bit value? */
804 #define IS_SEXT_32BIT_NUM(x) \
805 (((x) &~ (offsetT) 0x7fffffff) == 0 \
806 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
808 /* Is the given value a sign-extended 16-bit value? */
809 #define IS_SEXT_16BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fff) == 0 \
811 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
814 /* Global variables used when generating relaxable macros. See the
815 comment above RELAX_ENCODE for more details about how relaxation
818 /* 0 if we're not emitting a relaxable macro.
819 1 if we're emitting the first of the two relaxation alternatives.
820 2 if we're emitting the second alternative. */
823 /* The first relaxable fixup in the current frag. (In other words,
824 the first fixup that refers to relaxable code.) */
827 /* sizes[0] says how many bytes of the first alternative are stored in
828 the current frag. Likewise sizes[1] for the second alternative. */
829 unsigned int sizes[2];
831 /* The symbol on which the choice of sequence depends. */
835 /* Global variables used to decide whether a macro needs a warning. */
837 /* True if the macro is in a branch delay slot. */
838 bfd_boolean delay_slot_p;
840 /* For relaxable macros, sizes[0] is the length of the first alternative
841 in bytes and sizes[1] is the length of the second alternative.
842 For non-relaxable macros, both elements give the length of the
844 unsigned int sizes[2];
846 /* The first variant frag for this macro. */
848 } mips_macro_warning;
850 /* Prototypes for static functions. */
852 #define internalError() \
853 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
855 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
857 static void append_insn
858 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
859 static void mips_no_prev_insn (int);
860 static void mips16_macro_build
861 (expressionS *, const char *, const char *, va_list);
862 static void load_register (int, expressionS *, int);
863 static void macro_start (void);
864 static void macro_end (void);
865 static void macro (struct mips_cl_insn * ip);
866 static void mips16_macro (struct mips_cl_insn * ip);
867 #ifdef LOSING_COMPILER
868 static void macro2 (struct mips_cl_insn * ip);
870 static void mips_ip (char *str, struct mips_cl_insn * ip);
871 static void mips16_ip (char *str, struct mips_cl_insn * ip);
872 static void mips16_immed
873 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
874 unsigned long *, bfd_boolean *, unsigned short *);
875 static size_t my_getSmallExpression
876 (expressionS *, bfd_reloc_code_real_type *, char *);
877 static void my_getExpression (expressionS *, char *);
878 static void s_align (int);
879 static void s_change_sec (int);
880 static void s_change_section (int);
881 static void s_cons (int);
882 static void s_float_cons (int);
883 static void s_mips_globl (int);
884 static void s_option (int);
885 static void s_mipsset (int);
886 static void s_abicalls (int);
887 static void s_cpload (int);
888 static void s_cpsetup (int);
889 static void s_cplocal (int);
890 static void s_cprestore (int);
891 static void s_cpreturn (int);
892 static void s_gpvalue (int);
893 static void s_gpword (int);
894 static void s_gpdword (int);
895 static void s_cpadd (int);
896 static void s_insn (int);
897 static void md_obj_begin (void);
898 static void md_obj_end (void);
899 static void s_mips_ent (int);
900 static void s_mips_end (int);
901 static void s_mips_frame (int);
902 static void s_mips_mask (int reg_type);
903 static void s_mips_stab (int);
904 static void s_mips_weakext (int);
905 static void s_mips_file (int);
906 static void s_mips_loc (int);
907 static bfd_boolean pic_need_relax (symbolS *, asection *);
908 static int relaxed_branch_length (fragS *, asection *, int);
909 static int validate_mips_insn (const struct mips_opcode *);
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name; /* CPU or ISA name. */
917 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
918 int isa; /* ISA level. */
919 int cpu; /* CPU number (default CPU if ISA). */
922 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
923 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
924 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
928 The following pseudo-ops from the Kane and Heinrich MIPS book
929 should be defined here, but are currently unsupported: .alias,
930 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
932 The following pseudo-ops from the Kane and Heinrich MIPS book are
933 specific to the type of debugging information being generated, and
934 should be defined by the object format: .aent, .begin, .bend,
935 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
938 The following pseudo-ops from the Kane and Heinrich MIPS book are
939 not MIPS CPU specific, but are also not specific to the object file
940 format. This file is probably the best place to define them, but
941 they are not currently supported: .asm0, .endr, .lab, .repeat,
944 static const pseudo_typeS mips_pseudo_table[] =
946 /* MIPS specific pseudo-ops. */
947 {"option", s_option, 0},
948 {"set", s_mipsset, 0},
949 {"rdata", s_change_sec, 'r'},
950 {"sdata", s_change_sec, 's'},
951 {"livereg", s_ignore, 0},
952 {"abicalls", s_abicalls, 0},
953 {"cpload", s_cpload, 0},
954 {"cpsetup", s_cpsetup, 0},
955 {"cplocal", s_cplocal, 0},
956 {"cprestore", s_cprestore, 0},
957 {"cpreturn", s_cpreturn, 0},
958 {"gpvalue", s_gpvalue, 0},
959 {"gpword", s_gpword, 0},
960 {"gpdword", s_gpdword, 0},
961 {"cpadd", s_cpadd, 0},
964 /* Relatively generic pseudo-ops that happen to be used on MIPS
966 {"asciiz", stringer, 1},
967 {"bss", s_change_sec, 'b'},
970 {"dword", s_cons, 3},
971 {"weakext", s_mips_weakext, 0},
973 /* These pseudo-ops are defined in read.c, but must be overridden
974 here for one reason or another. */
975 {"align", s_align, 0},
977 {"data", s_change_sec, 'd'},
978 {"double", s_float_cons, 'd'},
979 {"float", s_float_cons, 'f'},
980 {"globl", s_mips_globl, 0},
981 {"global", s_mips_globl, 0},
982 {"hword", s_cons, 1},
987 {"section", s_change_section, 0},
988 {"short", s_cons, 1},
989 {"single", s_float_cons, 'f'},
990 {"stabn", s_mips_stab, 'n'},
991 {"text", s_change_sec, 't'},
994 { "extern", ecoff_directive_extern, 0},
999 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1001 /* These pseudo-ops should be defined by the object file format.
1002 However, a.out doesn't support them, so we have versions here. */
1003 {"aent", s_mips_ent, 1},
1004 {"bgnb", s_ignore, 0},
1005 {"end", s_mips_end, 0},
1006 {"endb", s_ignore, 0},
1007 {"ent", s_mips_ent, 0},
1008 {"file", s_mips_file, 0},
1009 {"fmask", s_mips_mask, 'F'},
1010 {"frame", s_mips_frame, 0},
1011 {"loc", s_mips_loc, 0},
1012 {"mask", s_mips_mask, 'R'},
1013 {"verstamp", s_ignore, 0},
1017 extern void pop_insert (const pseudo_typeS *);
1020 mips_pop_insert (void)
1022 pop_insert (mips_pseudo_table);
1023 if (! ECOFF_DEBUGGING)
1024 pop_insert (mips_nonecoff_pseudo_table);
1027 /* Symbols labelling the current insn. */
1029 struct insn_label_list
1031 struct insn_label_list *next;
1035 static struct insn_label_list *insn_labels;
1036 static struct insn_label_list *free_insn_labels;
1038 static void mips_clear_insn_labels (void);
1041 mips_clear_insn_labels (void)
1043 register struct insn_label_list **pl;
1045 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1051 static char *expr_end;
1053 /* Expressions which appear in instructions. These are set by
1056 static expressionS imm_expr;
1057 static expressionS imm2_expr;
1058 static expressionS offset_expr;
1060 /* Relocs associated with imm_expr and offset_expr. */
1062 static bfd_reloc_code_real_type imm_reloc[3]
1063 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1064 static bfd_reloc_code_real_type offset_reloc[3]
1065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1067 /* These are set by mips16_ip if an explicit extension is used. */
1069 static bfd_boolean mips16_small, mips16_ext;
1072 /* The pdr segment for per procedure frame/regmask info. Not used for
1075 static segT pdr_seg;
1078 /* The default target format to use. */
1081 mips_target_format (void)
1083 switch (OUTPUT_FLAVOR)
1085 case bfd_target_ecoff_flavour:
1086 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1087 case bfd_target_coff_flavour:
1089 case bfd_target_elf_flavour:
1091 /* This is traditional mips. */
1092 return (target_big_endian
1093 ? (HAVE_64BIT_OBJECTS
1094 ? "elf64-tradbigmips"
1096 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1097 : (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradlittlemips"
1100 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1106 ? "elf32-nbigmips" : "elf32-bigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-littlemips"
1110 ? "elf32-nlittlemips" : "elf32-littlemips")));
1118 /* This function is called once, at assembler startup time. It should
1119 set up all the tables, etc. that the MD part of the assembler will need. */
1124 register const char *retval = NULL;
1128 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1129 as_warn (_("Could not set architecture and machine"));
1131 op_hash = hash_new ();
1133 for (i = 0; i < NUMOPCODES;)
1135 const char *name = mips_opcodes[i].name;
1137 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1140 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1141 mips_opcodes[i].name, retval);
1142 /* Probably a memory allocation problem? Give up now. */
1143 as_fatal (_("Broken assembler. No assembly attempted."));
1147 if (mips_opcodes[i].pinfo != INSN_MACRO)
1149 if (!validate_mips_insn (&mips_opcodes[i]))
1154 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1157 mips16_op_hash = hash_new ();
1160 while (i < bfd_mips16_num_opcodes)
1162 const char *name = mips16_opcodes[i].name;
1164 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1166 as_fatal (_("internal: can't hash `%s': %s"),
1167 mips16_opcodes[i].name, retval);
1170 if (mips16_opcodes[i].pinfo != INSN_MACRO
1171 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1172 != mips16_opcodes[i].match))
1174 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1175 mips16_opcodes[i].name, mips16_opcodes[i].args);
1180 while (i < bfd_mips16_num_opcodes
1181 && strcmp (mips16_opcodes[i].name, name) == 0);
1185 as_fatal (_("Broken assembler. No assembly attempted."));
1187 /* We add all the general register names to the symbol table. This
1188 helps us detect invalid uses of them. */
1189 for (i = 0; i < 32; i++)
1193 sprintf (buf, "$%d", i);
1194 symbol_table_insert (symbol_new (buf, reg_section, i,
1195 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1208 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1214 &zero_address_frag));
1216 /* If we don't add these register names to the symbol table, they
1217 may end up being added as regular symbols by operand(), and then
1218 make it to the object file as undefined in case they're not
1219 regarded as local symbols. They're local in o32, since `$' is a
1220 local symbol prefix, but not in n32 or n64. */
1221 for (i = 0; i < 8; i++)
1225 sprintf (buf, "$fcc%i", i);
1226 symbol_table_insert (symbol_new (buf, reg_section, -1,
1227 &zero_address_frag));
1230 mips_no_prev_insn (FALSE);
1233 mips_cprmask[0] = 0;
1234 mips_cprmask[1] = 0;
1235 mips_cprmask[2] = 0;
1236 mips_cprmask[3] = 0;
1238 /* set the default alignment for the text section (2**2) */
1239 record_alignment (text_section, 2);
1241 bfd_set_gp_size (stdoutput, g_switch_value);
1243 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1245 /* On a native system, sections must be aligned to 16 byte
1246 boundaries. When configured for an embedded ELF target, we
1248 if (strcmp (TARGET_OS, "elf") != 0)
1250 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1251 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1252 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1255 /* Create a .reginfo section for register masks and a .mdebug
1256 section for debugging information. */
1264 subseg = now_subseg;
1266 /* The ABI says this section should be loaded so that the
1267 running program can access it. However, we don't load it
1268 if we are configured for an embedded target */
1269 flags = SEC_READONLY | SEC_DATA;
1270 if (strcmp (TARGET_OS, "elf") != 0)
1271 flags |= SEC_ALLOC | SEC_LOAD;
1273 if (mips_abi != N64_ABI)
1275 sec = subseg_new (".reginfo", (subsegT) 0);
1277 bfd_set_section_flags (stdoutput, sec, flags);
1278 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1281 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1286 /* The 64-bit ABI uses a .MIPS.options section rather than
1287 .reginfo section. */
1288 sec = subseg_new (".MIPS.options", (subsegT) 0);
1289 bfd_set_section_flags (stdoutput, sec, flags);
1290 bfd_set_section_alignment (stdoutput, sec, 3);
1293 /* Set up the option header. */
1295 Elf_Internal_Options opthdr;
1298 opthdr.kind = ODK_REGINFO;
1299 opthdr.size = (sizeof (Elf_External_Options)
1300 + sizeof (Elf64_External_RegInfo));
1303 f = frag_more (sizeof (Elf_External_Options));
1304 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1305 (Elf_External_Options *) f);
1307 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1312 if (ECOFF_DEBUGGING)
1314 sec = subseg_new (".mdebug", (subsegT) 0);
1315 (void) bfd_set_section_flags (stdoutput, sec,
1316 SEC_HAS_CONTENTS | SEC_READONLY);
1317 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1320 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1322 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1323 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1324 SEC_READONLY | SEC_RELOC
1326 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1330 subseg_set (seg, subseg);
1334 if (! ECOFF_DEBUGGING)
1341 if (! ECOFF_DEBUGGING)
1346 md_assemble (char *str)
1348 struct mips_cl_insn insn;
1349 bfd_reloc_code_real_type unused_reloc[3]
1350 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1352 imm_expr.X_op = O_absent;
1353 imm2_expr.X_op = O_absent;
1354 offset_expr.X_op = O_absent;
1355 imm_reloc[0] = BFD_RELOC_UNUSED;
1356 imm_reloc[1] = BFD_RELOC_UNUSED;
1357 imm_reloc[2] = BFD_RELOC_UNUSED;
1358 offset_reloc[0] = BFD_RELOC_UNUSED;
1359 offset_reloc[1] = BFD_RELOC_UNUSED;
1360 offset_reloc[2] = BFD_RELOC_UNUSED;
1362 if (mips_opts.mips16)
1363 mips16_ip (str, &insn);
1366 mips_ip (str, &insn);
1367 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1368 str, insn.insn_opcode));
1373 as_bad ("%s `%s'", insn_error, str);
1377 if (insn.insn_mo->pinfo == INSN_MACRO)
1380 if (mips_opts.mips16)
1381 mips16_macro (&insn);
1388 if (imm_expr.X_op != O_absent)
1389 append_insn (&insn, &imm_expr, imm_reloc);
1390 else if (offset_expr.X_op != O_absent)
1391 append_insn (&insn, &offset_expr, offset_reloc);
1393 append_insn (&insn, NULL, unused_reloc);
1397 /* Return true if the given relocation might need a matching %lo().
1398 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1399 applied to local symbols. */
1401 static inline bfd_boolean
1402 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1404 return (HAVE_IN_PLACE_ADDENDS
1405 && (reloc == BFD_RELOC_HI16_S
1406 || reloc == BFD_RELOC_MIPS_GOT16));
1409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1412 static inline bfd_boolean
1413 fixup_has_matching_lo_p (fixS *fixp)
1415 return (fixp->fx_next != NULL
1416 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1417 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1418 && fixp->fx_offset == fixp->fx_next->fx_offset);
1421 /* See whether instruction IP reads register REG. CLASS is the type
1425 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1426 enum mips_regclass class)
1428 if (class == MIPS16_REG)
1430 assert (mips_opts.mips16);
1431 reg = mips16_to_32_reg_map[reg];
1432 class = MIPS_GR_REG;
1435 /* Don't report on general register ZERO, since it never changes. */
1436 if (class == MIPS_GR_REG && reg == ZERO)
1439 if (class == MIPS_FP_REG)
1441 assert (! mips_opts.mips16);
1442 /* If we are called with either $f0 or $f1, we must check $f0.
1443 This is not optimal, because it will introduce an unnecessary
1444 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1445 need to distinguish reading both $f0 and $f1 or just one of
1446 them. Note that we don't have to check the other way,
1447 because there is no instruction that sets both $f0 and $f1
1448 and requires a delay. */
1449 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1450 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1451 == (reg &~ (unsigned) 1)))
1453 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1454 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1455 == (reg &~ (unsigned) 1)))
1458 else if (! mips_opts.mips16)
1460 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1461 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1463 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1464 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1469 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1470 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1471 & MIPS16OP_MASK_RX)]
1474 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1475 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1476 & MIPS16OP_MASK_RY)]
1479 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1480 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1481 & MIPS16OP_MASK_MOVE32Z)]
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1488 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1490 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1491 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1492 & MIPS16OP_MASK_REGR32) == reg)
1499 /* This function returns true if modifying a register requires a
1503 reg_needs_delay (unsigned int reg)
1505 unsigned long prev_pinfo;
1507 prev_pinfo = prev_insn.insn_mo->pinfo;
1508 if (! mips_opts.noreorder
1509 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1510 && ! gpr_interlocks)
1511 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1512 && ! cop_interlocks)))
1514 /* A load from a coprocessor or from memory. All load delays
1515 delay the use of general register rt for one instruction. */
1516 /* Itbl support may require additional care here. */
1517 know (prev_pinfo & INSN_WRITE_GPR_T);
1518 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1525 /* Mark instruction labels in mips16 mode. This permits the linker to
1526 handle them specially, such as generating jalx instructions when
1527 needed. We also make them odd for the duration of the assembly, in
1528 order to generate the right sort of code. We will make them even
1529 in the adjust_symtab routine, while leaving them marked. This is
1530 convenient for the debugger and the disassembler. The linker knows
1531 to make them odd again. */
1534 mips16_mark_labels (void)
1536 if (mips_opts.mips16)
1538 struct insn_label_list *l;
1541 for (l = insn_labels; l != NULL; l = l->next)
1544 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1545 S_SET_OTHER (l->label, STO_MIPS16);
1547 val = S_GET_VALUE (l->label);
1549 S_SET_VALUE (l->label, val + 1);
1554 /* End the current frag. Make it a variant frag and record the
1558 relax_close_frag (void)
1560 mips_macro_warning.first_frag = frag_now;
1561 frag_var (rs_machine_dependent, 0, 0,
1562 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1563 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1565 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1566 mips_relax.first_fixup = 0;
1569 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1570 See the comment above RELAX_ENCODE for more details. */
1573 relax_start (symbolS *symbol)
1575 assert (mips_relax.sequence == 0);
1576 mips_relax.sequence = 1;
1577 mips_relax.symbol = symbol;
1580 /* Start generating the second version of a relaxable sequence.
1581 See the comment above RELAX_ENCODE for more details. */
1586 assert (mips_relax.sequence == 1);
1587 mips_relax.sequence = 2;
1590 /* End the current relaxable sequence. */
1595 assert (mips_relax.sequence == 2);
1596 relax_close_frag ();
1597 mips_relax.sequence = 0;
1600 /* Output an instruction. IP is the instruction information.
1601 ADDRESS_EXPR is an operand of the instruction to be used with
1605 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1606 bfd_reloc_code_real_type *reloc_type)
1608 register unsigned long prev_pinfo, pinfo;
1612 relax_stateT prev_insn_frag_type = 0;
1613 bfd_boolean relaxed_branch = FALSE;
1614 bfd_boolean force_new_frag = FALSE;
1616 /* Mark instruction labels in mips16 mode. */
1617 mips16_mark_labels ();
1619 prev_pinfo = prev_insn.insn_mo->pinfo;
1620 pinfo = ip->insn_mo->pinfo;
1622 if (mips_relax.sequence != 2
1623 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1627 /* If the previous insn required any delay slots, see if we need
1628 to insert a NOP or two. There are eight kinds of possible
1629 hazards, of which an instruction can have at most one type.
1630 (1) a load from memory delay
1631 (2) a load from a coprocessor delay
1632 (3) an unconditional branch delay
1633 (4) a conditional branch delay
1634 (5) a move to coprocessor register delay
1635 (6) a load coprocessor register from memory delay
1636 (7) a coprocessor condition code delay
1637 (8) a HI/LO special register delay
1639 There are a lot of optimizations we could do that we don't.
1640 In particular, we do not, in general, reorder instructions.
1641 If you use gcc with optimization, it will reorder
1642 instructions and generally do much more optimization then we
1643 do here; repeating all that work in the assembler would only
1644 benefit hand written assembly code, and does not seem worth
1647 /* This is how a NOP is emitted. */
1648 #define emit_nop() \
1650 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1651 : md_number_to_chars (frag_more (4), 0, 4))
1653 /* The previous insn might require a delay slot, depending upon
1654 the contents of the current insn. */
1655 if (! mips_opts.mips16
1656 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1657 && ! gpr_interlocks)
1658 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1659 && ! cop_interlocks)))
1661 /* A load from a coprocessor or from memory. All load
1662 delays delay the use of general register rt for one
1664 /* Itbl support may require additional care here. */
1665 know (prev_pinfo & INSN_WRITE_GPR_T);
1666 if (mips_optimize == 0
1667 || insn_uses_reg (ip,
1668 ((prev_insn.insn_opcode >> OP_SH_RT)
1673 else if (! mips_opts.mips16
1674 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1675 && ! cop_interlocks)
1676 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1677 && ! cop_mem_interlocks)))
1679 /* A generic coprocessor delay. The previous instruction
1680 modified a coprocessor general or control register. If
1681 it modified a control register, we need to avoid any
1682 coprocessor instruction (this is probably not always
1683 required, but it sometimes is). If it modified a general
1684 register, we avoid using that register.
1686 This case is not handled very well. There is no special
1687 knowledge of CP0 handling, and the coprocessors other
1688 than the floating point unit are not distinguished at
1690 /* Itbl support may require additional care here. FIXME!
1691 Need to modify this to include knowledge about
1692 user specified delays! */
1693 if (prev_pinfo & INSN_WRITE_FPR_T)
1695 if (mips_optimize == 0
1696 || insn_uses_reg (ip,
1697 ((prev_insn.insn_opcode >> OP_SH_FT)
1702 else if (prev_pinfo & INSN_WRITE_FPR_S)
1704 if (mips_optimize == 0
1705 || insn_uses_reg (ip,
1706 ((prev_insn.insn_opcode >> OP_SH_FS)
1713 /* We don't know exactly what the previous instruction
1714 does. If the current instruction uses a coprocessor
1715 register, we must insert a NOP. If previous
1716 instruction may set the condition codes, and the
1717 current instruction uses them, we must insert two
1719 /* Itbl support may require additional care here. */
1720 if (mips_optimize == 0
1721 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1722 && (pinfo & INSN_READ_COND_CODE)))
1724 else if (pinfo & INSN_COP)
1728 else if (! mips_opts.mips16
1729 && (prev_pinfo & INSN_WRITE_COND_CODE)
1730 && ! cop_interlocks)
1732 /* The previous instruction sets the coprocessor condition
1733 codes, but does not require a general coprocessor delay
1734 (this means it is a floating point comparison
1735 instruction). If this instruction uses the condition
1736 codes, we need to insert a single NOP. */
1737 /* Itbl support may require additional care here. */
1738 if (mips_optimize == 0
1739 || (pinfo & INSN_READ_COND_CODE))
1743 /* If we're fixing up mfhi/mflo for the r7000 and the
1744 previous insn was an mfhi/mflo and the current insn
1745 reads the register that the mfhi/mflo wrote to, then
1748 else if (mips_7000_hilo_fix
1749 && MF_HILO_INSN (prev_pinfo)
1750 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1757 /* If we're fixing up mfhi/mflo for the r7000 and the
1758 2nd previous insn was an mfhi/mflo and the current insn
1759 reads the register that the mfhi/mflo wrote to, then
1762 else if (mips_7000_hilo_fix
1763 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1764 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1772 else if (prev_pinfo & INSN_READ_LO)
1774 /* The previous instruction reads the LO register; if the
1775 current instruction writes to the LO register, we must
1776 insert two NOPS. Some newer processors have interlocks.
1777 Also the tx39's multiply instructions can be executed
1778 immediately after a read from HI/LO (without the delay),
1779 though the tx39's divide insns still do require the
1781 if (! (hilo_interlocks
1782 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1783 && (mips_optimize == 0
1784 || (pinfo & INSN_WRITE_LO)))
1786 /* Most mips16 branch insns don't have a delay slot.
1787 If a read from LO is immediately followed by a branch
1788 to a write to LO we have a read followed by a write
1789 less than 2 insns away. We assume the target of
1790 a branch might be a write to LO, and insert a nop
1791 between a read and an immediately following branch. */
1792 else if (mips_opts.mips16
1793 && (mips_optimize == 0
1794 || (pinfo & MIPS16_INSN_BRANCH)))
1797 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1799 /* The previous instruction reads the HI register; if the
1800 current instruction writes to the HI register, we must
1801 insert a NOP. Some newer processors have interlocks.
1802 Also the note tx39's multiply above. */
1803 if (! (hilo_interlocks
1804 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1805 && (mips_optimize == 0
1806 || (pinfo & INSN_WRITE_HI)))
1808 /* Most mips16 branch insns don't have a delay slot.
1809 If a read from HI is immediately followed by a branch
1810 to a write to HI we have a read followed by a write
1811 less than 2 insns away. We assume the target of
1812 a branch might be a write to HI, and insert a nop
1813 between a read and an immediately following branch. */
1814 else if (mips_opts.mips16
1815 && (mips_optimize == 0
1816 || (pinfo & MIPS16_INSN_BRANCH)))
1820 /* If the previous instruction was in a noreorder section, then
1821 we don't want to insert the nop after all. */
1822 /* Itbl support may require additional care here. */
1823 if (prev_insn_unreordered)
1826 /* There are two cases which require two intervening
1827 instructions: 1) setting the condition codes using a move to
1828 coprocessor instruction which requires a general coprocessor
1829 delay and then reading the condition codes 2) reading the HI
1830 or LO register and then writing to it (except on processors
1831 which have interlocks). If we are not already emitting a NOP
1832 instruction, we must check for these cases compared to the
1833 instruction previous to the previous instruction. */
1834 if ((! mips_opts.mips16
1835 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1836 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1837 && (pinfo & INSN_READ_COND_CODE)
1838 && ! cop_interlocks)
1839 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1840 && (pinfo & INSN_WRITE_LO)
1841 && ! (hilo_interlocks
1842 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1843 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1844 && (pinfo & INSN_WRITE_HI)
1845 && ! (hilo_interlocks
1846 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1851 if (prev_prev_insn_unreordered)
1854 if (prev_prev_nop && nops == 0)
1857 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1859 /* We're out of bits in pinfo, so we must resort to string
1860 ops here. Shortcuts are selected based on opcodes being
1861 limited to the VR4120 instruction set. */
1863 const char *pn = prev_insn.insn_mo->name;
1864 const char *tn = ip->insn_mo->name;
1865 if (strncmp (pn, "macc", 4) == 0
1866 || strncmp (pn, "dmacc", 5) == 0)
1868 /* Errata 21 - [D]DIV[U] after [D]MACC */
1869 if (strstr (tn, "div"))
1872 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1873 instruction is executed immediately after a MACC or
1874 DMACC instruction, the result of [either instruction]
1876 if (strncmp (tn, "mult", 4) == 0
1877 || strncmp (tn, "dmult", 5) == 0)
1880 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1881 Applies on top of VR4181A MD(1) errata. */
1882 if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn, "mtlo") == 0
1887 || strcmp (tn, "mthi") == 0)
1890 else if (strncmp (pn, "dmult", 5) == 0
1891 && (strncmp (tn, "dmult", 5) == 0
1892 || strncmp (tn, "dmacc", 5) == 0))
1894 /* Here is the rest of errata 23. */
1897 else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
1898 && (strncmp (tn, "macc", 4) == 0
1899 || strncmp (tn, "dmacc", 5) == 0))
1901 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1902 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1903 DDIV or DDIVU instruction, the result of the MACC or
1904 DMACC instruction is incorrect.". This partly overlaps
1905 the workaround for errata 23. */
1908 if (nops < min_nops)
1912 /* If we are being given a nop instruction, don't bother with
1913 one of the nops we would otherwise output. This will only
1914 happen when a nop instruction is used with mips_optimize set
1917 && ! mips_opts.noreorder
1918 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1921 /* Now emit the right number of NOP instructions. */
1922 if (nops > 0 && ! mips_opts.noreorder)
1925 unsigned long old_frag_offset;
1927 struct insn_label_list *l;
1929 old_frag = frag_now;
1930 old_frag_offset = frag_now_fix ();
1932 for (i = 0; i < nops; i++)
1937 listing_prev_line ();
1938 /* We may be at the start of a variant frag. In case we
1939 are, make sure there is enough space for the frag
1940 after the frags created by listing_prev_line. The
1941 argument to frag_grow here must be at least as large
1942 as the argument to all other calls to frag_grow in
1943 this file. We don't have to worry about being in the
1944 middle of a variant frag, because the variants insert
1945 all needed nop instructions themselves. */
1949 for (l = insn_labels; l != NULL; l = l->next)
1953 assert (S_GET_SEGMENT (l->label) == now_seg);
1954 symbol_set_frag (l->label, frag_now);
1955 val = (valueT) frag_now_fix ();
1956 /* mips16 text labels are stored as odd. */
1957 if (mips_opts.mips16)
1959 S_SET_VALUE (l->label, val);
1962 #ifndef NO_ECOFF_DEBUGGING
1963 if (ECOFF_DEBUGGING)
1964 ecoff_fix_loc (old_frag, old_frag_offset);
1967 else if (prev_nop_frag != NULL)
1969 /* We have a frag holding nops we may be able to remove. If
1970 we don't need any nops, we can decrease the size of
1971 prev_nop_frag by the size of one instruction. If we do
1972 need some nops, we count them in prev_nops_required. */
1973 if (prev_nop_frag_since == 0)
1977 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1978 --prev_nop_frag_holds;
1981 prev_nop_frag_required += nops;
1985 if (prev_prev_nop == 0)
1987 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1988 --prev_nop_frag_holds;
1991 ++prev_nop_frag_required;
1994 if (prev_nop_frag_holds <= prev_nop_frag_required)
1995 prev_nop_frag = NULL;
1997 ++prev_nop_frag_since;
1999 /* Sanity check: by the time we reach the second instruction
2000 after prev_nop_frag, we should have used up all the nops
2001 one way or another. */
2002 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2006 /* Record the frag type before frag_var. */
2008 prev_insn_frag_type = prev_insn_frag->fr_type;
2011 && *reloc_type == BFD_RELOC_16_PCREL_S2
2012 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2013 || pinfo & INSN_COND_BRANCH_LIKELY)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts.warn_about_macros
2019 && !(mips_opts.noat && mips_pic != NO_PIC)
2020 && !mips_opts.mips16)
2022 relaxed_branch = TRUE;
2023 f = frag_var (rs_machine_dependent,
2024 relaxed_branch_length
2026 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2027 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2029 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2030 pinfo & INSN_COND_BRANCH_LIKELY,
2031 pinfo & INSN_WRITE_GPR_31,
2033 address_expr->X_add_symbol,
2034 address_expr->X_add_number,
2036 *reloc_type = BFD_RELOC_UNUSED;
2038 else if (*reloc_type > BFD_RELOC_UNUSED)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts.mips16 && address_expr != NULL);
2042 f = frag_var (rs_machine_dependent, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2044 mips16_small, mips16_ext,
2046 & INSN_UNCOND_BRANCH_DELAY),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP)),
2049 make_expr_symbol (address_expr), 0, NULL);
2051 else if (mips_opts.mips16
2053 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2055 /* Make sure there is enough room to swap this instruction with
2056 a following jump instruction. */
2062 if (mips_opts.mips16
2063 && mips_opts.noreorder
2064 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2065 as_warn (_("extended instruction in delay slot"));
2067 if (mips_relax.sequence)
2069 /* If we've reached the end of this frag, turn it into a variant
2070 frag and record the information for the instructions we've
2072 if (frag_room () < 4)
2073 relax_close_frag ();
2074 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2077 if (mips_relax.sequence != 2)
2078 mips_macro_warning.sizes[0] += 4;
2079 if (mips_relax.sequence != 1)
2080 mips_macro_warning.sizes[1] += 4;
2085 fixp[0] = fixp[1] = fixp[2] = NULL;
2086 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2088 if (address_expr->X_op == O_constant)
2092 switch (*reloc_type)
2095 ip->insn_opcode |= address_expr->X_add_number;
2098 case BFD_RELOC_MIPS_HIGHEST:
2099 tmp = (address_expr->X_add_number
2100 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2102 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2105 case BFD_RELOC_MIPS_HIGHER:
2106 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2107 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2110 case BFD_RELOC_HI16_S:
2111 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2115 case BFD_RELOC_HI16:
2116 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2119 case BFD_RELOC_LO16:
2120 case BFD_RELOC_MIPS_GOT_DISP:
2121 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2124 case BFD_RELOC_MIPS_JMP:
2125 if ((address_expr->X_add_number & 3) != 0)
2126 as_bad (_("jump to misaligned address (0x%lx)"),
2127 (unsigned long) address_expr->X_add_number);
2128 if (address_expr->X_add_number & ~0xfffffff)
2129 as_bad (_("jump address range overflow (0x%lx)"),
2130 (unsigned long) address_expr->X_add_number);
2131 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2134 case BFD_RELOC_MIPS16_JMP:
2135 if ((address_expr->X_add_number & 3) != 0)
2136 as_bad (_("jump to misaligned address (0x%lx)"),
2137 (unsigned long) address_expr->X_add_number);
2138 if (address_expr->X_add_number & ~0xfffffff)
2139 as_bad (_("jump address range overflow (0x%lx)"),
2140 (unsigned long) address_expr->X_add_number);
2142 (((address_expr->X_add_number & 0x7c0000) << 3)
2143 | ((address_expr->X_add_number & 0xf800000) >> 7)
2144 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2147 case BFD_RELOC_16_PCREL_S2:
2157 reloc_howto_type *howto;
2160 /* In a compound relocation, it is the final (outermost)
2161 operator that determines the relocated field. */
2162 for (i = 1; i < 3; i++)
2163 if (reloc_type[i] == BFD_RELOC_UNUSED)
2166 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2167 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2168 bfd_get_reloc_size(howto),
2170 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2173 /* These relocations can have an addend that won't fit in
2174 4 octets for 64bit assembly. */
2176 && ! howto->partial_inplace
2177 && (reloc_type[0] == BFD_RELOC_16
2178 || reloc_type[0] == BFD_RELOC_32
2179 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2180 || reloc_type[0] == BFD_RELOC_HI16_S
2181 || reloc_type[0] == BFD_RELOC_LO16
2182 || reloc_type[0] == BFD_RELOC_GPREL16
2183 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2184 || reloc_type[0] == BFD_RELOC_GPREL32
2185 || reloc_type[0] == BFD_RELOC_64
2186 || reloc_type[0] == BFD_RELOC_CTOR
2187 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2188 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2190 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2191 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2192 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2193 fixp[0]->fx_no_overflow = 1;
2195 if (mips_relax.sequence)
2197 if (mips_relax.first_fixup == 0)
2198 mips_relax.first_fixup = fixp[0];
2200 else if (reloc_needs_lo_p (*reloc_type))
2202 struct mips_hi_fixup *hi_fixup;
2204 /* Reuse the last entry if it already has a matching %lo. */
2205 hi_fixup = mips_hi_fixup_list;
2207 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2209 hi_fixup = ((struct mips_hi_fixup *)
2210 xmalloc (sizeof (struct mips_hi_fixup)));
2211 hi_fixup->next = mips_hi_fixup_list;
2212 mips_hi_fixup_list = hi_fixup;
2214 hi_fixup->fixp = fixp[0];
2215 hi_fixup->seg = now_seg;
2218 /* Add fixups for the second and third relocations, if given.
2219 Note that the ABI allows the second relocation to be
2220 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2221 moment we only use RSS_UNDEF, but we could add support
2222 for the others if it ever becomes necessary. */
2223 for (i = 1; i < 3; i++)
2224 if (reloc_type[i] != BFD_RELOC_UNUSED)
2226 address_expr->X_op = O_absent;
2227 address_expr->X_add_symbol = 0;
2228 address_expr->X_add_number = 0;
2230 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2231 fixp[0]->fx_size, address_expr,
2232 FALSE, reloc_type[i]);
2237 if (! mips_opts.mips16)
2239 md_number_to_chars (f, ip->insn_opcode, 4);
2241 dwarf2_emit_insn (4);
2244 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2246 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2247 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2249 /* The value passed to dwarf2_emit_insn is the distance between
2250 the end of the current instruction and the address that should
2251 be recorded in the debug tables. Since we want to use ISA-encoded
2252 addresses in MIPS16 debug info, the value is one byte less than
2253 the real instruction length. */
2254 dwarf2_emit_insn (3);
2261 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2264 md_number_to_chars (f, ip->insn_opcode, 2);
2266 dwarf2_emit_insn (ip->use_extend ? 3 : 1);
2270 /* Update the register mask information. */
2271 if (! mips_opts.mips16)
2273 if (pinfo & INSN_WRITE_GPR_D)
2274 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2275 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2276 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2277 if (pinfo & INSN_READ_GPR_S)
2278 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2279 if (pinfo & INSN_WRITE_GPR_31)
2280 mips_gprmask |= 1 << RA;
2281 if (pinfo & INSN_WRITE_FPR_D)
2282 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2283 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2284 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2285 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2286 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2287 if ((pinfo & INSN_READ_FPR_R) != 0)
2288 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2289 if (pinfo & INSN_COP)
2291 /* We don't keep enough information to sort these cases out.
2292 The itbl support does keep this information however, although
2293 we currently don't support itbl fprmats as part of the cop
2294 instruction. May want to add this support in the future. */
2296 /* Never set the bit for $0, which is always zero. */
2297 mips_gprmask &= ~1 << 0;
2301 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2302 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2303 & MIPS16OP_MASK_RX);
2304 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2305 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2306 & MIPS16OP_MASK_RY);
2307 if (pinfo & MIPS16_INSN_WRITE_Z)
2308 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2309 & MIPS16OP_MASK_RZ);
2310 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2311 mips_gprmask |= 1 << TREG;
2312 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2313 mips_gprmask |= 1 << SP;
2314 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2315 mips_gprmask |= 1 << RA;
2316 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2317 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2318 if (pinfo & MIPS16_INSN_READ_Z)
2319 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2320 & MIPS16OP_MASK_MOVE32Z);
2321 if (pinfo & MIPS16_INSN_READ_GPR_X)
2322 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2323 & MIPS16OP_MASK_REGR32);
2326 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2328 /* Filling the branch delay slot is more complex. We try to
2329 switch the branch with the previous instruction, which we can
2330 do if the previous instruction does not set up a condition
2331 that the branch tests and if the branch is not itself the
2332 target of any branch. */
2333 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2334 || (pinfo & INSN_COND_BRANCH_DELAY))
2336 if (mips_optimize < 2
2337 /* If we have seen .set volatile or .set nomove, don't
2339 || mips_opts.nomove != 0
2340 /* If we had to emit any NOP instructions, then we
2341 already know we can not swap. */
2343 /* If we don't even know the previous insn, we can not
2345 || ! prev_insn_valid
2346 /* If the previous insn is already in a branch delay
2347 slot, then we can not swap. */
2348 || prev_insn_is_delay_slot
2349 /* If the previous previous insn was in a .set
2350 noreorder, we can't swap. Actually, the MIPS
2351 assembler will swap in this situation. However, gcc
2352 configured -with-gnu-as will generate code like
2358 in which we can not swap the bne and INSN. If gcc is
2359 not configured -with-gnu-as, it does not output the
2360 .set pseudo-ops. We don't have to check
2361 prev_insn_unreordered, because prev_insn_valid will
2362 be 0 in that case. We don't want to use
2363 prev_prev_insn_valid, because we do want to be able
2364 to swap at the start of a function. */
2365 || prev_prev_insn_unreordered
2366 /* If the branch is itself the target of a branch, we
2367 can not swap. We cheat on this; all we check for is
2368 whether there is a label on this instruction. If
2369 there are any branches to anything other than a
2370 label, users must use .set noreorder. */
2371 || insn_labels != NULL
2372 /* If the previous instruction is in a variant frag
2373 other than this branch's one, we cannot do the swap.
2374 This does not apply to the mips16, which uses variant
2375 frags for different purposes. */
2376 || (! mips_opts.mips16
2377 && prev_insn_frag_type == rs_machine_dependent)
2378 /* If the branch reads the condition codes, we don't
2379 even try to swap, because in the sequence
2384 we can not swap, and I don't feel like handling that
2386 || (! mips_opts.mips16
2387 && (pinfo & INSN_READ_COND_CODE)
2388 && ! cop_interlocks)
2389 /* We can not swap with an instruction that requires a
2390 delay slot, because the target of the branch might
2391 interfere with that instruction. */
2392 || (! mips_opts.mips16
2394 /* Itbl support may require additional care here. */
2395 & (INSN_LOAD_COPROC_DELAY
2396 | INSN_COPROC_MOVE_DELAY
2397 | INSN_WRITE_COND_CODE))
2398 && ! cop_interlocks)
2399 || (! (hilo_interlocks
2400 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2404 || (! mips_opts.mips16
2405 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2406 && ! gpr_interlocks)
2407 || (! mips_opts.mips16
2408 /* Itbl support may require additional care here. */
2409 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2410 && ! cop_mem_interlocks)
2411 /* We can not swap with a branch instruction. */
2413 & (INSN_UNCOND_BRANCH_DELAY
2414 | INSN_COND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_LIKELY))
2416 /* We do not swap with a trap instruction, since it
2417 complicates trap handlers to have the trap
2418 instruction be in a delay slot. */
2419 || (prev_pinfo & INSN_TRAP)
2420 /* If the branch reads a register that the previous
2421 instruction sets, we can not swap. */
2422 || (! mips_opts.mips16
2423 && (prev_pinfo & INSN_WRITE_GPR_T)
2424 && insn_uses_reg (ip,
2425 ((prev_insn.insn_opcode >> OP_SH_RT)
2428 || (! mips_opts.mips16
2429 && (prev_pinfo & INSN_WRITE_GPR_D)
2430 && insn_uses_reg (ip,
2431 ((prev_insn.insn_opcode >> OP_SH_RD)
2434 || (mips_opts.mips16
2435 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2436 && insn_uses_reg (ip,
2437 ((prev_insn.insn_opcode
2439 & MIPS16OP_MASK_RX),
2441 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2442 && insn_uses_reg (ip,
2443 ((prev_insn.insn_opcode
2445 & MIPS16OP_MASK_RY),
2447 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2448 && insn_uses_reg (ip,
2449 ((prev_insn.insn_opcode
2451 & MIPS16OP_MASK_RZ),
2453 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2454 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2455 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2456 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2457 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2458 && insn_uses_reg (ip,
2459 MIPS16OP_EXTRACT_REG32R (prev_insn.
2462 /* If the branch writes a register that the previous
2463 instruction sets, we can not swap (we know that
2464 branches write only to RD or to $31). */
2465 || (! mips_opts.mips16
2466 && (prev_pinfo & INSN_WRITE_GPR_T)
2467 && (((pinfo & INSN_WRITE_GPR_D)
2468 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2469 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2470 || ((pinfo & INSN_WRITE_GPR_31)
2471 && (((prev_insn.insn_opcode >> OP_SH_RT)
2474 || (! mips_opts.mips16
2475 && (prev_pinfo & INSN_WRITE_GPR_D)
2476 && (((pinfo & INSN_WRITE_GPR_D)
2477 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2478 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2479 || ((pinfo & INSN_WRITE_GPR_31)
2480 && (((prev_insn.insn_opcode >> OP_SH_RD)
2483 || (mips_opts.mips16
2484 && (pinfo & MIPS16_INSN_WRITE_31)
2485 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2486 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2487 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2489 /* If the branch writes a register that the previous
2490 instruction reads, we can not swap (we know that
2491 branches only write to RD or to $31). */
2492 || (! mips_opts.mips16
2493 && (pinfo & INSN_WRITE_GPR_D)
2494 && insn_uses_reg (&prev_insn,
2495 ((ip->insn_opcode >> OP_SH_RD)
2498 || (! mips_opts.mips16
2499 && (pinfo & INSN_WRITE_GPR_31)
2500 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2501 || (mips_opts.mips16
2502 && (pinfo & MIPS16_INSN_WRITE_31)
2503 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2504 /* If the previous previous instruction has a load
2505 delay, and sets a register that the branch reads, we
2507 || (! mips_opts.mips16
2508 /* Itbl support may require additional care here. */
2509 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2510 && ! cop_interlocks)
2511 || ((prev_prev_insn.insn_mo->pinfo
2512 & INSN_LOAD_MEMORY_DELAY)
2513 && ! gpr_interlocks))
2514 && insn_uses_reg (ip,
2515 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2518 /* If one instruction sets a condition code and the
2519 other one uses a condition code, we can not swap. */
2520 || ((pinfo & INSN_READ_COND_CODE)
2521 && (prev_pinfo & INSN_WRITE_COND_CODE))
2522 || ((pinfo & INSN_WRITE_COND_CODE)
2523 && (prev_pinfo & INSN_READ_COND_CODE))
2524 /* If the previous instruction uses the PC, we can not
2526 || (mips_opts.mips16
2527 && (prev_pinfo & MIPS16_INSN_READ_PC))
2528 /* If the previous instruction was extended, we can not
2530 || (mips_opts.mips16 && prev_insn_extended)
2531 /* If the previous instruction had a fixup in mips16
2532 mode, we can not swap. This normally means that the
2533 previous instruction was a 4 byte branch anyhow. */
2534 || (mips_opts.mips16 && prev_insn_fixp[0])
2535 /* If the previous instruction is a sync, sync.l, or
2536 sync.p, we can not swap. */
2537 || (prev_pinfo & INSN_SYNC))
2539 /* We could do even better for unconditional branches to
2540 portions of this object file; we could pick up the
2541 instruction at the destination, put it in the delay
2542 slot, and bump the destination address. */
2544 /* Update the previous insn information. */
2545 prev_prev_insn = *ip;
2546 prev_insn.insn_mo = &dummy_opcode;
2550 /* It looks like we can actually do the swap. */
2551 if (! mips_opts.mips16)
2556 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2557 if (!relaxed_branch)
2559 /* If this is not a relaxed branch, then just
2560 swap the instructions. */
2561 memcpy (temp, prev_f, 4);
2562 memcpy (prev_f, f, 4);
2563 memcpy (f, temp, 4);
2567 /* If this is a relaxed branch, then we move the
2568 instruction to be placed in the delay slot to
2569 the current frag, shrinking the fixed part of
2570 the originating frag. If the branch occupies
2571 the tail of the latter, we move it backwards,
2572 into the space freed by the moved instruction. */
2574 memcpy (f, prev_f, 4);
2575 prev_insn_frag->fr_fix -= 4;
2576 if (prev_insn_frag->fr_type == rs_machine_dependent)
2577 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2580 if (prev_insn_fixp[0])
2582 prev_insn_fixp[0]->fx_frag = frag_now;
2583 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2585 if (prev_insn_fixp[1])
2587 prev_insn_fixp[1]->fx_frag = frag_now;
2588 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2590 if (prev_insn_fixp[2])
2592 prev_insn_fixp[2]->fx_frag = frag_now;
2593 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2595 if (prev_insn_fixp[0] && HAVE_NEWABI
2596 && prev_insn_frag != frag_now
2597 && (prev_insn_fixp[0]->fx_r_type
2598 == BFD_RELOC_MIPS_GOT_DISP
2599 || (prev_insn_fixp[0]->fx_r_type
2600 == BFD_RELOC_MIPS_CALL16)))
2602 /* To avoid confusion in tc_gen_reloc, we must
2603 ensure that this does not become a variant
2605 force_new_frag = TRUE;
2608 if (!relaxed_branch)
2612 fixp[0]->fx_frag = prev_insn_frag;
2613 fixp[0]->fx_where = prev_insn_where;
2617 fixp[1]->fx_frag = prev_insn_frag;
2618 fixp[1]->fx_where = prev_insn_where;
2622 fixp[2]->fx_frag = prev_insn_frag;
2623 fixp[2]->fx_where = prev_insn_where;
2626 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2629 fixp[0]->fx_where -= 4;
2631 fixp[1]->fx_where -= 4;
2633 fixp[2]->fx_where -= 4;
2641 assert (prev_insn_fixp[0] == NULL);
2642 assert (prev_insn_fixp[1] == NULL);
2643 assert (prev_insn_fixp[2] == NULL);
2644 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2645 memcpy (temp, prev_f, 2);
2646 memcpy (prev_f, f, 2);
2647 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2649 assert (*reloc_type == BFD_RELOC_UNUSED);
2650 memcpy (f, temp, 2);
2654 memcpy (f, f + 2, 2);
2655 memcpy (f + 2, temp, 2);
2659 fixp[0]->fx_frag = prev_insn_frag;
2660 fixp[0]->fx_where = prev_insn_where;
2664 fixp[1]->fx_frag = prev_insn_frag;
2665 fixp[1]->fx_where = prev_insn_where;
2669 fixp[2]->fx_frag = prev_insn_frag;
2670 fixp[2]->fx_where = prev_insn_where;
2674 /* Update the previous insn information; leave prev_insn
2676 prev_prev_insn = *ip;
2678 prev_insn_is_delay_slot = 1;
2680 /* If that was an unconditional branch, forget the previous
2681 insn information. */
2682 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2684 prev_prev_insn.insn_mo = &dummy_opcode;
2685 prev_insn.insn_mo = &dummy_opcode;
2688 prev_insn_fixp[0] = NULL;
2689 prev_insn_fixp[1] = NULL;
2690 prev_insn_fixp[2] = NULL;
2691 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2692 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2694 prev_insn_extended = 0;
2696 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2698 /* We don't yet optimize a branch likely. What we should do
2699 is look at the target, copy the instruction found there
2700 into the delay slot, and increment the branch to jump to
2701 the next instruction. */
2703 /* Update the previous insn information. */
2704 prev_prev_insn = *ip;
2705 prev_insn.insn_mo = &dummy_opcode;
2706 prev_insn_fixp[0] = NULL;
2707 prev_insn_fixp[1] = NULL;
2708 prev_insn_fixp[2] = NULL;
2709 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2710 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2711 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2712 prev_insn_extended = 0;
2716 /* Update the previous insn information. */
2718 prev_prev_insn.insn_mo = &dummy_opcode;
2720 prev_prev_insn = prev_insn;
2723 /* Any time we see a branch, we always fill the delay slot
2724 immediately; since this insn is not a branch, we know it
2725 is not in a delay slot. */
2726 prev_insn_is_delay_slot = 0;
2728 prev_insn_fixp[0] = fixp[0];
2729 prev_insn_fixp[1] = fixp[1];
2730 prev_insn_fixp[2] = fixp[2];
2731 prev_insn_reloc_type[0] = reloc_type[0];
2732 prev_insn_reloc_type[1] = reloc_type[1];
2733 prev_insn_reloc_type[2] = reloc_type[2];
2734 if (mips_opts.mips16)
2735 prev_insn_extended = (ip->use_extend
2736 || *reloc_type > BFD_RELOC_UNUSED);
2739 prev_prev_insn_unreordered = prev_insn_unreordered;
2740 prev_insn_unreordered = 0;
2741 prev_insn_frag = frag_now;
2742 prev_insn_where = f - frag_now->fr_literal;
2743 prev_insn_valid = 1;
2745 else if (mips_relax.sequence != 2)
2747 /* We need to record a bit of information even when we are not
2748 reordering, in order to determine the base address for mips16
2749 PC relative relocs. */
2750 prev_prev_insn = prev_insn;
2752 prev_insn_reloc_type[0] = reloc_type[0];
2753 prev_insn_reloc_type[1] = reloc_type[1];
2754 prev_insn_reloc_type[2] = reloc_type[2];
2755 prev_prev_insn_unreordered = prev_insn_unreordered;
2756 prev_insn_unreordered = 1;
2759 /* We just output an insn, so the next one doesn't have a label. */
2760 mips_clear_insn_labels ();
2763 /* This function forgets that there was any previous instruction or
2764 label. If PRESERVE is non-zero, it remembers enough information to
2765 know whether nops are needed before a noreorder section. */
2768 mips_no_prev_insn (int preserve)
2772 prev_insn.insn_mo = &dummy_opcode;
2773 prev_prev_insn.insn_mo = &dummy_opcode;
2774 prev_nop_frag = NULL;
2775 prev_nop_frag_holds = 0;
2776 prev_nop_frag_required = 0;
2777 prev_nop_frag_since = 0;
2779 prev_insn_valid = 0;
2780 prev_insn_is_delay_slot = 0;
2781 prev_insn_unreordered = 0;
2782 prev_insn_extended = 0;
2783 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2784 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2785 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2786 prev_prev_insn_unreordered = 0;
2787 mips_clear_insn_labels ();
2790 /* This function must be called whenever we turn on noreorder or emit
2791 something other than instructions. It inserts any NOPS which might
2792 be needed by the previous instruction, and clears the information
2793 kept for the previous instructions. The INSNS parameter is true if
2794 instructions are to follow. */
2797 mips_emit_delays (bfd_boolean insns)
2799 if (! mips_opts.noreorder)
2804 if ((! mips_opts.mips16
2805 && ((prev_insn.insn_mo->pinfo
2806 & (INSN_LOAD_COPROC_DELAY
2807 | INSN_COPROC_MOVE_DELAY
2808 | INSN_WRITE_COND_CODE))
2809 && ! cop_interlocks))
2810 || (! hilo_interlocks
2811 && (prev_insn.insn_mo->pinfo
2814 || (! mips_opts.mips16
2815 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2816 && ! gpr_interlocks)
2817 || (! mips_opts.mips16
2818 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2819 && ! cop_mem_interlocks))
2821 /* Itbl support may require additional care here. */
2823 if ((! mips_opts.mips16
2824 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2825 && ! cop_interlocks))
2826 || (! hilo_interlocks
2827 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2828 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2831 if (prev_insn_unreordered)
2834 else if ((! mips_opts.mips16
2835 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2836 && ! cop_interlocks))
2837 || (! hilo_interlocks
2838 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2839 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2841 /* Itbl support may require additional care here. */
2842 if (! prev_prev_insn_unreordered)
2846 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2849 const char *pn = prev_insn.insn_mo->name;
2850 if (strncmp (pn, "macc", 4) == 0
2851 || strncmp (pn, "dmacc", 5) == 0
2852 || strncmp (pn, "dmult", 5) == 0
2853 || strstr (pn, "div"))
2855 if (nops < min_nops)
2861 struct insn_label_list *l;
2865 /* Record the frag which holds the nop instructions, so
2866 that we can remove them if we don't need them. */
2867 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2868 prev_nop_frag = frag_now;
2869 prev_nop_frag_holds = nops;
2870 prev_nop_frag_required = 0;
2871 prev_nop_frag_since = 0;
2874 for (; nops > 0; --nops)
2879 /* Move on to a new frag, so that it is safe to simply
2880 decrease the size of prev_nop_frag. */
2881 frag_wane (frag_now);
2885 for (l = insn_labels; l != NULL; l = l->next)
2889 assert (S_GET_SEGMENT (l->label) == now_seg);
2890 symbol_set_frag (l->label, frag_now);
2891 val = (valueT) frag_now_fix ();
2892 /* mips16 text labels are stored as odd. */
2893 if (mips_opts.mips16)
2895 S_SET_VALUE (l->label, val);
2900 /* Mark instruction labels in mips16 mode. */
2902 mips16_mark_labels ();
2904 mips_no_prev_insn (insns);
2907 /* Set up global variables for the start of a new macro. */
2912 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2913 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2914 && (prev_insn.insn_mo->pinfo
2915 & (INSN_UNCOND_BRANCH_DELAY
2916 | INSN_COND_BRANCH_DELAY
2917 | INSN_COND_BRANCH_LIKELY)) != 0);
2920 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2921 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2922 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2925 macro_warning (relax_substateT subtype)
2927 if (subtype & RELAX_DELAY_SLOT)
2928 return _("Macro instruction expanded into multiple instructions"
2929 " in a branch delay slot");
2930 else if (subtype & RELAX_NOMACRO)
2931 return _("Macro instruction expanded into multiple instructions");
2936 /* Finish up a macro. Emit warnings as appropriate. */
2941 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2943 relax_substateT subtype;
2945 /* Set up the relaxation warning flags. */
2947 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2948 subtype |= RELAX_SECOND_LONGER;
2949 if (mips_opts.warn_about_macros)
2950 subtype |= RELAX_NOMACRO;
2951 if (mips_macro_warning.delay_slot_p)
2952 subtype |= RELAX_DELAY_SLOT;
2954 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2956 /* Either the macro has a single implementation or both
2957 implementations are longer than 4 bytes. Emit the
2959 const char *msg = macro_warning (subtype);
2965 /* One implementation might need a warning but the other
2966 definitely doesn't. */
2967 mips_macro_warning.first_frag->fr_subtype |= subtype;
2972 /* Build an instruction created by a macro expansion. This is passed
2973 a pointer to the count of instructions created so far, an
2974 expression, the name of the instruction to build, an operand format
2975 string, and corresponding arguments. */
2978 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2980 struct mips_cl_insn insn;
2981 bfd_reloc_code_real_type r[3];
2984 va_start (args, fmt);
2986 if (mips_opts.mips16)
2988 mips16_macro_build (ep, name, fmt, args);
2993 r[0] = BFD_RELOC_UNUSED;
2994 r[1] = BFD_RELOC_UNUSED;
2995 r[2] = BFD_RELOC_UNUSED;
2996 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2997 assert (insn.insn_mo);
2998 assert (strcmp (name, insn.insn_mo->name) == 0);
3000 /* Search until we get a match for NAME. */
3003 /* It is assumed here that macros will never generate
3004 MDMX or MIPS-3D instructions. */
3005 if (strcmp (fmt, insn.insn_mo->args) == 0
3006 && insn.insn_mo->pinfo != INSN_MACRO
3007 && OPCODE_IS_MEMBER (insn.insn_mo,
3009 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3011 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3015 assert (insn.insn_mo->name);
3016 assert (strcmp (name, insn.insn_mo->name) == 0);
3019 insn.insn_opcode = insn.insn_mo->match;
3037 insn.insn_opcode |= (va_arg (args, int)
3038 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3043 /* Note that in the macro case, these arguments are already
3044 in MSB form. (When handling the instruction in the
3045 non-macro case, these arguments are sizes from which
3046 MSB values must be calculated.) */
3047 insn.insn_opcode |= (va_arg (args, int)
3048 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3054 /* Note that in the macro case, these arguments are already
3055 in MSBD form. (When handling the instruction in the
3056 non-macro case, these arguments are sizes from which
3057 MSBD values must be calculated.) */
3058 insn.insn_opcode |= (va_arg (args, int)
3059 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3070 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3074 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3079 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3085 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3090 int tmp = va_arg (args, int);
3092 insn.insn_opcode |= tmp << OP_SH_RT;
3093 insn.insn_opcode |= tmp << OP_SH_RD;
3099 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3106 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3110 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3114 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3118 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3122 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3129 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3135 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3136 assert (*r == BFD_RELOC_GPREL16
3137 || *r == BFD_RELOC_MIPS_LITERAL
3138 || *r == BFD_RELOC_MIPS_HIGHER
3139 || *r == BFD_RELOC_HI16_S
3140 || *r == BFD_RELOC_LO16
3141 || *r == BFD_RELOC_MIPS_GOT16
3142 || *r == BFD_RELOC_MIPS_CALL16
3143 || *r == BFD_RELOC_MIPS_GOT_DISP
3144 || *r == BFD_RELOC_MIPS_GOT_PAGE
3145 || *r == BFD_RELOC_MIPS_GOT_OFST
3146 || *r == BFD_RELOC_MIPS_GOT_LO16
3147 || *r == BFD_RELOC_MIPS_CALL_LO16);
3151 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3153 && (ep->X_op == O_constant
3154 || (ep->X_op == O_symbol
3155 && (*r == BFD_RELOC_MIPS_HIGHEST
3156 || *r == BFD_RELOC_HI16_S
3157 || *r == BFD_RELOC_HI16
3158 || *r == BFD_RELOC_GPREL16
3159 || *r == BFD_RELOC_MIPS_GOT_HI16
3160 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3164 assert (ep != NULL);
3166 * This allows macro() to pass an immediate expression for
3167 * creating short branches without creating a symbol.
3168 * Note that the expression still might come from the assembly
3169 * input, in which case the value is not checked for range nor
3170 * is a relocation entry generated (yuck).
3172 if (ep->X_op == O_constant)
3174 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3178 *r = BFD_RELOC_16_PCREL_S2;
3182 assert (ep != NULL);
3183 *r = BFD_RELOC_MIPS_JMP;
3187 insn.insn_opcode |= va_arg (args, unsigned long);
3196 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3198 append_insn (&insn, ep, r);
3202 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3205 struct mips_cl_insn insn;
3206 bfd_reloc_code_real_type r[3]
3207 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3209 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3210 assert (insn.insn_mo);
3211 assert (strcmp (name, insn.insn_mo->name) == 0);
3213 while (strcmp (fmt, insn.insn_mo->args) != 0
3214 || insn.insn_mo->pinfo == INSN_MACRO)
3217 assert (insn.insn_mo->name);
3218 assert (strcmp (name, insn.insn_mo->name) == 0);
3221 insn.insn_opcode = insn.insn_mo->match;
3222 insn.use_extend = FALSE;
3241 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3246 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3250 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3254 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3264 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3271 regno = va_arg (args, int);
3272 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3273 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3294 assert (ep != NULL);
3296 if (ep->X_op != O_constant)
3297 *r = (int) BFD_RELOC_UNUSED + c;
3300 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3301 FALSE, &insn.insn_opcode, &insn.use_extend,
3304 *r = BFD_RELOC_UNUSED;
3310 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3317 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3319 append_insn (&insn, ep, r);
3323 * Generate a "jalr" instruction with a relocation hint to the called
3324 * function. This occurs in NewABI PIC code.
3327 macro_build_jalr (expressionS *ep)
3336 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3338 fix_new_exp (frag_now, f - frag_now->fr_literal,
3339 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3343 * Generate a "lui" instruction.
3346 macro_build_lui (expressionS *ep, int regnum)
3348 expressionS high_expr;
3349 struct mips_cl_insn insn;
3350 bfd_reloc_code_real_type r[3]
3351 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3352 const char *name = "lui";
3353 const char *fmt = "t,u";
3355 assert (! mips_opts.mips16);
3359 if (high_expr.X_op == O_constant)
3361 /* we can compute the instruction now without a relocation entry */
3362 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3364 *r = BFD_RELOC_UNUSED;
3368 assert (ep->X_op == O_symbol);
3369 /* _gp_disp is a special case, used from s_cpload. */
3370 assert (mips_pic == NO_PIC
3372 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3373 *r = BFD_RELOC_HI16_S;
3376 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3377 assert (insn.insn_mo);
3378 assert (strcmp (name, insn.insn_mo->name) == 0);
3379 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3381 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3382 if (*r == BFD_RELOC_UNUSED)
3384 insn.insn_opcode |= high_expr.X_add_number;
3385 append_insn (&insn, NULL, r);
3388 append_insn (&insn, &high_expr, r);
3391 /* Generate a sequence of instructions to do a load or store from a constant
3392 offset off of a base register (breg) into/from a target register (treg),
3393 using AT if necessary. */
3395 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3396 int treg, int breg, int dbl)
3398 assert (ep->X_op == O_constant);
3400 /* Sign-extending 32-bit constants makes their handling easier. */
3401 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3402 == ~((bfd_vma) 0x7fffffff)))
3404 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3405 as_bad (_("constant too large"));
3407 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3411 /* Right now, this routine can only handle signed 32-bit constants. */
3412 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3413 as_warn (_("operand overflow"));
3415 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3417 /* Signed 16-bit offset will fit in the op. Easy! */
3418 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3422 /* 32-bit offset, need multiple instructions and AT, like:
3423 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3424 addu $tempreg,$tempreg,$breg
3425 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3426 to handle the complete offset. */
3427 macro_build_lui (ep, AT);
3428 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3429 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3432 as_warn (_("Macro used $at after \".set noat\""));
3437 * Generates code to set the $at register to true (one)
3438 * if reg is less than the immediate expression.
3441 set_at (int reg, int unsignedp)
3443 if (imm_expr.X_op == O_constant
3444 && imm_expr.X_add_number >= -0x8000
3445 && imm_expr.X_add_number < 0x8000)
3446 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3447 AT, reg, BFD_RELOC_LO16);
3450 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3451 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3456 normalize_constant_expr (expressionS *ex)
3458 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3459 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3463 /* Warn if an expression is not a constant. */
3466 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3468 if (ex->X_op == O_big)
3469 as_bad (_("unsupported large constant"));
3470 else if (ex->X_op != O_constant)
3471 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3473 normalize_constant_expr (ex);
3476 /* Count the leading zeroes by performing a binary chop. This is a
3477 bulky bit of source, but performance is a LOT better for the
3478 majority of values than a simple loop to count the bits:
3479 for (lcnt = 0; (lcnt < 32); lcnt++)
3480 if ((v) & (1 << (31 - lcnt)))
3482 However it is not code size friendly, and the gain will drop a bit
3483 on certain cached systems.
3485 #define COUNT_TOP_ZEROES(v) \
3486 (((v) & ~0xffff) == 0 \
3487 ? ((v) & ~0xff) == 0 \
3488 ? ((v) & ~0xf) == 0 \
3489 ? ((v) & ~0x3) == 0 \
3490 ? ((v) & ~0x1) == 0 \
3495 : ((v) & ~0x7) == 0 \
3498 : ((v) & ~0x3f) == 0 \
3499 ? ((v) & ~0x1f) == 0 \
3502 : ((v) & ~0x7f) == 0 \
3505 : ((v) & ~0xfff) == 0 \
3506 ? ((v) & ~0x3ff) == 0 \
3507 ? ((v) & ~0x1ff) == 0 \
3510 : ((v) & ~0x7ff) == 0 \
3513 : ((v) & ~0x3fff) == 0 \
3514 ? ((v) & ~0x1fff) == 0 \
3517 : ((v) & ~0x7fff) == 0 \
3520 : ((v) & ~0xffffff) == 0 \
3521 ? ((v) & ~0xfffff) == 0 \
3522 ? ((v) & ~0x3ffff) == 0 \
3523 ? ((v) & ~0x1ffff) == 0 \
3526 : ((v) & ~0x7ffff) == 0 \
3529 : ((v) & ~0x3fffff) == 0 \
3530 ? ((v) & ~0x1fffff) == 0 \
3533 : ((v) & ~0x7fffff) == 0 \
3536 : ((v) & ~0xfffffff) == 0 \
3537 ? ((v) & ~0x3ffffff) == 0 \
3538 ? ((v) & ~0x1ffffff) == 0 \
3541 : ((v) & ~0x7ffffff) == 0 \
3544 : ((v) & ~0x3fffffff) == 0 \
3545 ? ((v) & ~0x1fffffff) == 0 \
3548 : ((v) & ~0x7fffffff) == 0 \
3553 * This routine generates the least number of instructions necessary to load
3554 * an absolute expression value into a register.
3557 load_register (int reg, expressionS *ep, int dbl)
3560 expressionS hi32, lo32;
3562 if (ep->X_op != O_big)
3564 assert (ep->X_op == O_constant);
3566 /* Sign-extending 32-bit constants makes their handling easier. */
3567 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3568 == ~((bfd_vma) 0x7fffffff)))
3570 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3571 as_bad (_("constant too large"));
3573 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3577 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3579 /* We can handle 16 bit signed values with an addiu to
3580 $zero. No need to ever use daddiu here, since $zero and
3581 the result are always correct in 32 bit mode. */
3582 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3585 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3587 /* We can handle 16 bit unsigned values with an ori to
3589 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3592 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3594 /* 32 bit values require an lui. */
3595 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3596 if ((ep->X_add_number & 0xffff) != 0)
3597 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3602 /* The value is larger than 32 bits. */
3604 if (HAVE_32BIT_GPRS)
3606 as_bad (_("Number (0x%lx) larger than 32 bits"),
3607 (unsigned long) ep->X_add_number);
3608 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3612 if (ep->X_op != O_big)
3615 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3616 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3617 hi32.X_add_number &= 0xffffffff;
3619 lo32.X_add_number &= 0xffffffff;
3623 assert (ep->X_add_number > 2);
3624 if (ep->X_add_number == 3)
3625 generic_bignum[3] = 0;
3626 else if (ep->X_add_number > 4)
3627 as_bad (_("Number larger than 64 bits"));
3628 lo32.X_op = O_constant;
3629 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3630 hi32.X_op = O_constant;
3631 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3634 if (hi32.X_add_number == 0)
3639 unsigned long hi, lo;
3641 if (hi32.X_add_number == (offsetT) 0xffffffff)
3643 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3645 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3648 if (lo32.X_add_number & 0x80000000)
3650 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3651 if (lo32.X_add_number & 0xffff)
3652 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3657 /* Check for 16bit shifted constant. We know that hi32 is
3658 non-zero, so start the mask on the first bit of the hi32
3663 unsigned long himask, lomask;
3667 himask = 0xffff >> (32 - shift);
3668 lomask = (0xffff << shift) & 0xffffffff;
3672 himask = 0xffff << (shift - 32);
3675 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3676 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3680 tmp.X_op = O_constant;
3682 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3683 | (lo32.X_add_number >> shift));
3685 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3686 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3687 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3688 reg, reg, (shift >= 32) ? shift - 32 : shift);
3693 while (shift <= (64 - 16));
3695 /* Find the bit number of the lowest one bit, and store the
3696 shifted value in hi/lo. */
3697 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3698 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3702 while ((lo & 1) == 0)
3707 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3713 while ((hi & 1) == 0)
3722 /* Optimize if the shifted value is a (power of 2) - 1. */
3723 if ((hi == 0 && ((lo + 1) & lo) == 0)
3724 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3726 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3731 /* This instruction will set the register to be all
3733 tmp.X_op = O_constant;
3734 tmp.X_add_number = (offsetT) -1;
3735 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3739 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3740 reg, reg, (bit >= 32) ? bit - 32 : bit);
3742 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3743 reg, reg, (shift >= 32) ? shift - 32 : shift);
3748 /* Sign extend hi32 before calling load_register, because we can
3749 generally get better code when we load a sign extended value. */
3750 if ((hi32.X_add_number & 0x80000000) != 0)
3751 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3752 load_register (reg, &hi32, 0);
3755 if ((lo32.X_add_number & 0xffff0000) == 0)
3759 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3767 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3769 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3770 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3776 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3780 mid16.X_add_number >>= 16;
3781 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3782 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3785 if ((lo32.X_add_number & 0xffff) != 0)
3786 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3790 load_delay_nop (void)
3792 if (!gpr_interlocks)
3793 macro_build (NULL, "nop", "");
3796 /* Load an address into a register. */
3799 load_address (int reg, expressionS *ep, int *used_at)
3801 if (ep->X_op != O_constant
3802 && ep->X_op != O_symbol)
3804 as_bad (_("expression too complex"));
3805 ep->X_op = O_constant;
3808 if (ep->X_op == O_constant)
3810 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3814 if (mips_pic == NO_PIC)
3816 /* If this is a reference to a GP relative symbol, we want
3817 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3819 lui $reg,<sym> (BFD_RELOC_HI16_S)
3820 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3821 If we have an addend, we always use the latter form.
3823 With 64bit address space and a usable $at we want
3824 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3825 lui $at,<sym> (BFD_RELOC_HI16_S)
3826 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3827 daddiu $at,<sym> (BFD_RELOC_LO16)
3831 If $at is already in use, we use a path which is suboptimal
3832 on superscalar processors.
3833 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3834 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3836 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3838 daddiu $reg,<sym> (BFD_RELOC_LO16)
3840 if (HAVE_64BIT_ADDRESSES)
3842 /* ??? We don't provide a GP-relative alternative for these macros.
3843 It used not to be possible with the original relaxation code,
3844 but it could be done now. */
3846 if (*used_at == 0 && ! mips_opts.noat)
3848 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3849 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3850 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3851 BFD_RELOC_MIPS_HIGHER);
3852 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3853 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3854 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3859 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3860 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3861 BFD_RELOC_MIPS_HIGHER);
3862 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3863 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3864 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3865 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3870 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3871 && ! nopic_need_relax (ep->X_add_symbol, 1))
3873 relax_start (ep->X_add_symbol);
3874 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3875 mips_gp_register, BFD_RELOC_GPREL16);
3878 macro_build_lui (ep, reg);
3879 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3880 reg, reg, BFD_RELOC_LO16);
3881 if (mips_relax.sequence)
3885 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3889 /* If this is a reference to an external symbol, we want
3890 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3892 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3894 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3895 If there is a constant, it must be added in after.
3897 If we have NewABI, we want
3898 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3899 unless we're referencing a global symbol with a non-zero
3900 offset, in which case cst must be added separately. */
3903 if (ep->X_add_number)
3905 ex.X_add_number = ep->X_add_number;
3906 ep->X_add_number = 0;
3907 relax_start (ep->X_add_symbol);
3908 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3909 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3910 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3912 ex.X_op = O_constant;
3913 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3914 reg, reg, BFD_RELOC_LO16);
3915 ep->X_add_number = ex.X_add_number;
3918 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3919 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3920 if (mips_relax.sequence)
3925 ex.X_add_number = ep->X_add_number;
3926 ep->X_add_number = 0;
3927 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3928 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3930 relax_start (ep->X_add_symbol);
3932 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3936 if (ex.X_add_number != 0)
3938 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3939 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3940 ex.X_op = O_constant;
3941 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3942 reg, reg, BFD_RELOC_LO16);
3946 else if (mips_pic == SVR4_PIC)
3950 /* This is the large GOT case. If this is a reference to an
3951 external symbol, we want
3952 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3954 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3956 Otherwise, for a reference to a local symbol in old ABI, we want
3957 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3959 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3960 If there is a constant, it must be added in after.
3962 In the NewABI, for local symbols, with or without offsets, we want:
3963 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3964 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3968 ex.X_add_number = ep->X_add_number;
3969 ep->X_add_number = 0;
3970 relax_start (ep->X_add_symbol);
3971 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3972 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3973 reg, reg, mips_gp_register);
3974 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3975 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3976 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3977 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3978 else if (ex.X_add_number)
3980 ex.X_op = O_constant;
3981 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3985 ep->X_add_number = ex.X_add_number;
3987 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3988 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3989 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3990 BFD_RELOC_MIPS_GOT_OFST);
3995 ex.X_add_number = ep->X_add_number;
3996 ep->X_add_number = 0;
3997 relax_start (ep->X_add_symbol);
3998 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4000 reg, reg, mips_gp_register);
4001 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4002 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4004 if (reg_needs_delay (mips_gp_register))
4006 /* We need a nop before loading from $gp. This special
4007 check is required because the lui which starts the main
4008 instruction stream does not refer to $gp, and so will not
4009 insert the nop which may be required. */
4010 macro_build (NULL, "nop", "");
4012 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4013 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4015 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4019 if (ex.X_add_number != 0)
4021 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4022 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4023 ex.X_op = O_constant;
4024 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4033 /* Move the contents of register SOURCE into register DEST. */
4036 move_register (int dest, int source)
4038 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4042 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4043 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4044 The two alternatives are:
4046 Global symbol Local sybmol
4047 ------------- ------------
4048 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4050 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4052 load_got_offset emits the first instruction and add_got_offset
4053 emits the second for a 16-bit offset or add_got_offset_hilo emits
4054 a sequence to add a 32-bit offset using a scratch register. */
4057 load_got_offset (int dest, expressionS *local)
4062 global.X_add_number = 0;
4064 relax_start (local->X_add_symbol);
4065 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4066 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4068 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4069 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4074 add_got_offset (int dest, expressionS *local)
4078 global.X_op = O_constant;
4079 global.X_op_symbol = NULL;
4080 global.X_add_symbol = NULL;
4081 global.X_add_number = local->X_add_number;
4083 relax_start (local->X_add_symbol);
4084 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4085 dest, dest, BFD_RELOC_LO16);
4087 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4092 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4095 int hold_mips_optimize;
4097 global.X_op = O_constant;
4098 global.X_op_symbol = NULL;
4099 global.X_add_symbol = NULL;
4100 global.X_add_number = local->X_add_number;
4102 relax_start (local->X_add_symbol);
4103 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4105 /* Set mips_optimize around the lui instruction to avoid
4106 inserting an unnecessary nop after the lw. */
4107 hold_mips_optimize = mips_optimize;
4109 macro_build_lui (&global, tmp);
4110 mips_optimize = hold_mips_optimize;
4111 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4114 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4119 * This routine implements the seemingly endless macro or synthesized
4120 * instructions and addressing modes in the mips assembly language. Many
4121 * of these macros are simple and are similar to each other. These could
4122 * probably be handled by some kind of table or grammar approach instead of
4123 * this verbose method. Others are not simple macros but are more like
4124 * optimizing code generation.
4125 * One interesting optimization is when several store macros appear
4126 * consecutively that would load AT with the upper half of the same address.
4127 * The ensuing load upper instructions are ommited. This implies some kind
4128 * of global optimization. We currently only optimize within a single macro.
4129 * For many of the load and store macros if the address is specified as a
4130 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4131 * first load register 'at' with zero and use it as the base register. The
4132 * mips assembler simply uses register $zero. Just one tiny optimization
4136 macro (struct mips_cl_insn *ip)
4138 register int treg, sreg, dreg, breg;
4154 bfd_reloc_code_real_type r;
4155 int hold_mips_optimize;
4157 assert (! mips_opts.mips16);
4159 treg = (ip->insn_opcode >> 16) & 0x1f;
4160 dreg = (ip->insn_opcode >> 11) & 0x1f;
4161 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4162 mask = ip->insn_mo->mask;
4164 expr1.X_op = O_constant;
4165 expr1.X_op_symbol = NULL;
4166 expr1.X_add_symbol = NULL;
4167 expr1.X_add_number = 1;
4179 mips_emit_delays (TRUE);
4180 ++mips_opts.noreorder;
4181 mips_any_noreorder = 1;
4183 expr1.X_add_number = 8;
4184 macro_build (&expr1, "bgez", "s,p", sreg);
4186 macro_build (NULL, "nop", "", 0);
4188 move_register (dreg, sreg);
4189 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4191 --mips_opts.noreorder;
4212 if (imm_expr.X_op == O_constant
4213 && imm_expr.X_add_number >= -0x8000
4214 && imm_expr.X_add_number < 0x8000)
4216 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4219 load_register (AT, &imm_expr, dbl);
4220 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4239 if (imm_expr.X_op == O_constant
4240 && imm_expr.X_add_number >= 0
4241 && imm_expr.X_add_number < 0x10000)
4243 if (mask != M_NOR_I)
4244 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4247 macro_build (&imm_expr, "ori", "t,r,i",
4248 treg, sreg, BFD_RELOC_LO16);
4249 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4254 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4255 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4272 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4274 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4277 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4278 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4286 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4291 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4294 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4295 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4301 /* check for > max integer */
4302 maxnum = 0x7fffffff;
4303 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4310 if (imm_expr.X_op == O_constant
4311 && imm_expr.X_add_number >= maxnum
4312 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4315 /* result is always false */
4317 macro_build (NULL, "nop", "", 0);
4319 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4322 if (imm_expr.X_op != O_constant)
4323 as_bad (_("Unsupported large constant"));
4324 ++imm_expr.X_add_number;
4328 if (mask == M_BGEL_I)
4330 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4332 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4335 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4337 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4340 maxnum = 0x7fffffff;
4341 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4348 maxnum = - maxnum - 1;
4349 if (imm_expr.X_op == O_constant
4350 && imm_expr.X_add_number <= maxnum
4351 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4354 /* result is always true */
4355 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4356 macro_build (&offset_expr, "b", "p");
4360 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4370 macro_build (&offset_expr, likely ? "beql" : "beq",
4374 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4375 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4383 && imm_expr.X_op == O_constant
4384 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4386 if (imm_expr.X_op != O_constant)
4387 as_bad (_("Unsupported large constant"));
4388 ++imm_expr.X_add_number;
4392 if (mask == M_BGEUL_I)
4394 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4396 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4398 macro_build (&offset_expr, likely ? "bnel" : "bne",
4403 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4411 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4416 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4419 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4420 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4428 macro_build (&offset_expr, likely ? "bnel" : "bne",
4434 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4435 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4443 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4448 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4451 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4452 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4458 maxnum = 0x7fffffff;
4459 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4466 if (imm_expr.X_op == O_constant
4467 && imm_expr.X_add_number >= maxnum
4468 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4470 if (imm_expr.X_op != O_constant)
4471 as_bad (_("Unsupported large constant"));
4472 ++imm_expr.X_add_number;
4476 if (mask == M_BLTL_I)
4478 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4480 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4483 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4485 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4489 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4497 macro_build (&offset_expr, likely ? "beql" : "beq",
4503 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4504 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4512 && imm_expr.X_op == O_constant
4513 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4515 if (imm_expr.X_op != O_constant)
4516 as_bad (_("Unsupported large constant"));
4517 ++imm_expr.X_add_number;
4521 if (mask == M_BLTUL_I)
4523 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4525 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4527 macro_build (&offset_expr, likely ? "beql" : "beq",
4532 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4540 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4545 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4548 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4549 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4559 macro_build (&offset_expr, likely ? "bnel" : "bne",
4563 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4564 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4572 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4574 as_bad (_("Unsupported large constant"));
4579 pos = (unsigned long) imm_expr.X_add_number;
4580 size = (unsigned long) imm2_expr.X_add_number;
4585 as_bad (_("Improper position (%lu)"), pos);
4588 if (size == 0 || size > 64
4589 || (pos + size - 1) > 63)
4591 as_bad (_("Improper extract size (%lu, position %lu)"),
4596 if (size <= 32 && pos < 32)
4601 else if (size <= 32)
4611 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4620 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4622 as_bad (_("Unsupported large constant"));
4627 pos = (unsigned long) imm_expr.X_add_number;
4628 size = (unsigned long) imm2_expr.X_add_number;
4633 as_bad (_("Improper position (%lu)"), pos);
4636 if (size == 0 || size > 64
4637 || (pos + size - 1) > 63)
4639 as_bad (_("Improper insert size (%lu, position %lu)"),
4644 if (pos < 32 && (pos + size - 1) < 32)
4659 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4676 as_warn (_("Divide by zero."));
4678 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4680 macro_build (NULL, "break", "c", 7);
4684 mips_emit_delays (TRUE);
4685 ++mips_opts.noreorder;
4686 mips_any_noreorder = 1;
4689 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4690 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4694 expr1.X_add_number = 8;
4695 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4696 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4697 macro_build (NULL, "break", "c", 7);
4699 expr1.X_add_number = -1;
4700 load_register (AT, &expr1, dbl);
4701 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4702 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4705 expr1.X_add_number = 1;
4706 load_register (AT, &expr1, dbl);
4707 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4711 expr1.X_add_number = 0x80000000;
4712 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4716 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4717 /* We want to close the noreorder block as soon as possible, so
4718 that later insns are available for delay slot filling. */
4719 --mips_opts.noreorder;
4723 expr1.X_add_number = 8;
4724 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4725 macro_build (NULL, "nop", "", 0);
4727 /* We want to close the noreorder block as soon as possible, so
4728 that later insns are available for delay slot filling. */
4729 --mips_opts.noreorder;
4731 macro_build (NULL, "break", "c", 6);
4733 macro_build (NULL, s, "d", dreg);
4772 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4774 as_warn (_("Divide by zero."));
4776 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4778 macro_build (NULL, "break", "c", 7);
4781 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4783 if (strcmp (s2, "mflo") == 0)
4784 move_register (dreg, sreg);
4786 move_register (dreg, 0);
4789 if (imm_expr.X_op == O_constant
4790 && imm_expr.X_add_number == -1
4791 && s[strlen (s) - 1] != 'u')
4793 if (strcmp (s2, "mflo") == 0)
4795 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4798 move_register (dreg, 0);
4802 load_register (AT, &imm_expr, dbl);
4803 macro_build (NULL, s, "z,s,t", sreg, AT);
4804 macro_build (NULL, s2, "d", dreg);
4823 mips_emit_delays (TRUE);
4824 ++mips_opts.noreorder;
4825 mips_any_noreorder = 1;
4828 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4829 macro_build (NULL, s, "z,s,t", sreg, treg);
4830 /* We want to close the noreorder block as soon as possible, so
4831 that later insns are available for delay slot filling. */
4832 --mips_opts.noreorder;
4836 expr1.X_add_number = 8;
4837 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4838 macro_build (NULL, s, "z,s,t", sreg, treg);
4840 /* We want to close the noreorder block as soon as possible, so
4841 that later insns are available for delay slot filling. */
4842 --mips_opts.noreorder;
4843 macro_build (NULL, "break", "c", 7);
4845 macro_build (NULL, s2, "d", dreg);
4857 /* Load the address of a symbol into a register. If breg is not
4858 zero, we then add a base register to it. */
4860 if (dbl && HAVE_32BIT_GPRS)
4861 as_warn (_("dla used to load 32-bit register"));
4863 if (! dbl && HAVE_64BIT_OBJECTS)
4864 as_warn (_("la used to load 64-bit address"));
4866 if (offset_expr.X_op == O_constant
4867 && offset_expr.X_add_number >= -0x8000
4868 && offset_expr.X_add_number < 0x8000)
4870 macro_build (&offset_expr,
4871 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4872 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4887 if (offset_expr.X_op != O_symbol
4888 && offset_expr.X_op != O_constant)
4890 as_bad (_("expression too complex"));
4891 offset_expr.X_op = O_constant;
4894 if (offset_expr.X_op == O_constant)
4895 load_register (tempreg, &offset_expr,
4897 ? (dbl || HAVE_64BIT_ADDRESSES)
4898 : HAVE_64BIT_ADDRESSES));
4899 else if (mips_pic == NO_PIC)
4901 /* If this is a reference to a GP relative symbol, we want
4902 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4904 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4905 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4906 If we have a constant, we need two instructions anyhow,
4907 so we may as well always use the latter form.
4909 With 64bit address space and a usable $at we want
4910 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4911 lui $at,<sym> (BFD_RELOC_HI16_S)
4912 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4913 daddiu $at,<sym> (BFD_RELOC_LO16)
4915 daddu $tempreg,$tempreg,$at
4917 If $at is already in use, we use a path which is suboptimal
4918 on superscalar processors.
4919 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4920 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4922 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4924 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4926 if (HAVE_64BIT_ADDRESSES)
4928 /* ??? We don't provide a GP-relative alternative for
4929 these macros. It used not to be possible with the
4930 original relaxation code, but it could be done now. */
4932 if (used_at == 0 && ! mips_opts.noat)
4934 macro_build (&offset_expr, "lui", "t,u",
4935 tempreg, BFD_RELOC_MIPS_HIGHEST);
4936 macro_build (&offset_expr, "lui", "t,u",
4937 AT, BFD_RELOC_HI16_S);
4938 macro_build (&offset_expr, "daddiu", "t,r,j",
4939 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4940 macro_build (&offset_expr, "daddiu", "t,r,j",
4941 AT, AT, BFD_RELOC_LO16);
4942 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4943 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4948 macro_build (&offset_expr, "lui", "t,u",
4949 tempreg, BFD_RELOC_MIPS_HIGHEST);
4950 macro_build (&offset_expr, "daddiu", "t,r,j",
4951 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4952 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4953 macro_build (&offset_expr, "daddiu", "t,r,j",
4954 tempreg, tempreg, BFD_RELOC_HI16_S);
4955 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4956 macro_build (&offset_expr, "daddiu", "t,r,j",
4957 tempreg, tempreg, BFD_RELOC_LO16);
4962 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4963 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4965 relax_start (offset_expr.X_add_symbol);
4966 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4967 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4970 macro_build_lui (&offset_expr, tempreg);
4971 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4972 tempreg, tempreg, BFD_RELOC_LO16);
4973 if (mips_relax.sequence)
4977 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4979 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4981 /* If this is a reference to an external symbol, and there
4982 is no constant, we want
4983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4984 or for lca or if tempreg is PIC_CALL_REG
4985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4986 For a local symbol, we want
4987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4989 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4991 If we have a small constant, and this is a reference to
4992 an external symbol, we want
4993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4995 addiu $tempreg,$tempreg,<constant>
4996 For a local symbol, we want the same instruction
4997 sequence, but we output a BFD_RELOC_LO16 reloc on the
5000 If we have a large constant, and this is a reference to
5001 an external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5003 lui $at,<hiconstant>
5004 addiu $at,$at,<loconstant>
5005 addu $tempreg,$tempreg,$at
5006 For a local symbol, we want the same instruction
5007 sequence, but we output a BFD_RELOC_LO16 reloc on the
5011 if (offset_expr.X_add_number == 0)
5013 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5014 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5016 relax_start (offset_expr.X_add_symbol);
5017 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5018 lw_reloc_type, mips_gp_register);
5021 /* We're going to put in an addu instruction using
5022 tempreg, so we may as well insert the nop right
5027 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5028 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5030 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5031 tempreg, tempreg, BFD_RELOC_LO16);
5033 /* FIXME: If breg == 0, and the next instruction uses
5034 $tempreg, then if this variant case is used an extra
5035 nop will be generated. */
5037 else if (offset_expr.X_add_number >= -0x8000
5038 && offset_expr.X_add_number < 0x8000)
5040 load_got_offset (tempreg, &offset_expr);
5042 add_got_offset (tempreg, &offset_expr);
5046 expr1.X_add_number = offset_expr.X_add_number;
5047 offset_expr.X_add_number =
5048 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5049 load_got_offset (tempreg, &offset_expr);
5050 offset_expr.X_add_number = expr1.X_add_number;
5051 /* If we are going to add in a base register, and the
5052 target register and the base register are the same,
5053 then we are using AT as a temporary register. Since
5054 we want to load the constant into AT, we add our
5055 current AT (from the global offset table) and the
5056 register into the register now, and pretend we were
5057 not using a base register. */
5061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5066 add_got_offset_hilo (tempreg, &offset_expr, AT);
5070 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5072 int add_breg_early = 0;
5074 /* If this is a reference to an external, and there is no
5075 constant, or local symbol (*), with or without a
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5078 or for lca or if tempreg is PIC_CALL_REG
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5081 If we have a small constant, and this is a reference to
5082 an external symbol, we want
5083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5084 addiu $tempreg,$tempreg,<constant>
5086 If we have a large constant, and this is a reference to
5087 an external symbol, we want
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5089 lui $at,<hiconstant>
5090 addiu $at,$at,<loconstant>
5091 addu $tempreg,$tempreg,$at
5093 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5094 local symbols, even though it introduces an additional
5097 if (offset_expr.X_add_number)
5099 expr1.X_add_number = offset_expr.X_add_number;
5100 offset_expr.X_add_number = 0;
5102 relax_start (offset_expr.X_add_symbol);
5103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5104 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5106 if (expr1.X_add_number >= -0x8000
5107 && expr1.X_add_number < 0x8000)
5109 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5110 tempreg, tempreg, BFD_RELOC_LO16);
5112 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5116 /* If we are going to add in a base register, and the
5117 target register and the base register are the same,
5118 then we are using AT as a temporary register. Since
5119 we want to load the constant into AT, we add our
5120 current AT (from the global offset table) and the
5121 register into the register now, and pretend we were
5122 not using a base register. */
5127 assert (tempreg == AT);
5128 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5134 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5135 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5141 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5144 offset_expr.X_add_number = expr1.X_add_number;
5146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5147 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5151 treg, tempreg, breg);
5157 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5159 relax_start (offset_expr.X_add_symbol);
5160 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5161 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5163 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5164 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5169 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5170 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5173 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5176 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5177 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5178 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5180 /* This is the large GOT case. If this is a reference to an
5181 external symbol, and there is no constant, we want
5182 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5183 addu $tempreg,$tempreg,$gp
5184 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5185 or for lca or if tempreg is PIC_CALL_REG
5186 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5187 addu $tempreg,$tempreg,$gp
5188 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5189 For a local symbol, we want
5190 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5192 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5194 If we have a small constant, and this is a reference to
5195 an external symbol, we want
5196 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5197 addu $tempreg,$tempreg,$gp
5198 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5200 addiu $tempreg,$tempreg,<constant>
5201 For a local symbol, we want
5202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5204 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5206 If we have a large constant, and this is a reference to
5207 an external symbol, we want
5208 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5209 addu $tempreg,$tempreg,$gp
5210 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5211 lui $at,<hiconstant>
5212 addiu $at,$at,<loconstant>
5213 addu $tempreg,$tempreg,$at
5214 For a local symbol, we want
5215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5216 lui $at,<hiconstant>
5217 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5218 addu $tempreg,$tempreg,$at
5221 expr1.X_add_number = offset_expr.X_add_number;
5222 offset_expr.X_add_number = 0;
5223 relax_start (offset_expr.X_add_symbol);
5224 gpdelay = reg_needs_delay (mips_gp_register);
5225 if (expr1.X_add_number == 0 && breg == 0
5226 && (call || tempreg == PIC_CALL_REG))
5228 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5229 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5231 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5233 tempreg, tempreg, mips_gp_register);
5234 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5235 tempreg, lw_reloc_type, tempreg);
5236 if (expr1.X_add_number == 0)
5240 /* We're going to put in an addu instruction using
5241 tempreg, so we may as well insert the nop right
5246 else if (expr1.X_add_number >= -0x8000
5247 && expr1.X_add_number < 0x8000)
5250 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5251 tempreg, tempreg, BFD_RELOC_LO16);
5257 /* If we are going to add in a base register, and the
5258 target register and the base register are the same,
5259 then we are using AT as a temporary register. Since
5260 we want to load the constant into AT, we add our
5261 current AT (from the global offset table) and the
5262 register into the register now, and pretend we were
5263 not using a base register. */
5268 assert (tempreg == AT);
5270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5275 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5276 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5280 offset_expr.X_add_number =
5281 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5286 /* This is needed because this instruction uses $gp, but
5287 the first instruction on the main stream does not. */
5288 macro_build (NULL, "nop", "");
5291 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5292 local_reloc_type, mips_gp_register);
5293 if (expr1.X_add_number >= -0x8000
5294 && expr1.X_add_number < 0x8000)
5297 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5298 tempreg, tempreg, BFD_RELOC_LO16);
5299 /* FIXME: If add_number is 0, and there was no base
5300 register, the external symbol case ended with a load,
5301 so if the symbol turns out to not be external, and
5302 the next instruction uses tempreg, an unnecessary nop
5303 will be inserted. */
5309 /* We must add in the base register now, as in the
5310 external symbol case. */
5311 assert (tempreg == AT);
5313 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5316 /* We set breg to 0 because we have arranged to add
5317 it in in both cases. */
5321 macro_build_lui (&expr1, AT);
5322 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5323 AT, AT, BFD_RELOC_LO16);
5324 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5325 tempreg, tempreg, AT);
5329 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5331 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5332 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5333 int add_breg_early = 0;
5335 /* This is the large GOT case. If this is a reference to an
5336 external symbol, and there is no constant, we want
5337 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5338 add $tempreg,$tempreg,$gp
5339 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5340 or for lca or if tempreg is PIC_CALL_REG
5341 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5342 add $tempreg,$tempreg,$gp
5343 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5345 If we have a small constant, and this is a reference to
5346 an external symbol, we want
5347 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5348 add $tempreg,$tempreg,$gp
5349 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5350 addi $tempreg,$tempreg,<constant>
5352 If we have a large constant, and this is a reference to
5353 an external symbol, we want
5354 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5355 addu $tempreg,$tempreg,$gp
5356 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5357 lui $at,<hiconstant>
5358 addi $at,$at,<loconstant>
5359 add $tempreg,$tempreg,$at
5361 If we have NewABI, and we know it's a local symbol, we want
5362 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5363 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5364 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5366 relax_start (offset_expr.X_add_symbol);
5368 expr1.X_add_number = offset_expr.X_add_number;
5369 offset_expr.X_add_number = 0;
5371 if (expr1.X_add_number == 0 && breg == 0
5372 && (call || tempreg == PIC_CALL_REG))
5374 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5375 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5377 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5379 tempreg, tempreg, mips_gp_register);
5380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5381 tempreg, lw_reloc_type, tempreg);
5383 if (expr1.X_add_number == 0)
5385 else if (expr1.X_add_number >= -0x8000
5386 && expr1.X_add_number < 0x8000)
5388 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5389 tempreg, tempreg, BFD_RELOC_LO16);
5391 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5395 /* If we are going to add in a base register, and the
5396 target register and the base register are the same,
5397 then we are using AT as a temporary register. Since
5398 we want to load the constant into AT, we add our
5399 current AT (from the global offset table) and the
5400 register into the register now, and pretend we were
5401 not using a base register. */
5406 assert (tempreg == AT);
5407 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5413 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5419 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5422 offset_expr.X_add_number = expr1.X_add_number;
5423 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5424 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5425 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5426 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5430 treg, tempreg, breg);
5443 if (mips_pic == NO_PIC)
5444 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5446 s = ADDRESS_ADD_INSN;
5448 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5457 /* The j instruction may not be used in PIC code, since it
5458 requires an absolute address. We convert it to a b
5460 if (mips_pic == NO_PIC)
5461 macro_build (&offset_expr, "j", "a");
5463 macro_build (&offset_expr, "b", "p");
5466 /* The jal instructions must be handled as macros because when
5467 generating PIC code they expand to multi-instruction
5468 sequences. Normally they are simple instructions. */
5473 if (mips_pic == NO_PIC)
5474 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5475 else if (mips_pic == SVR4_PIC)
5477 if (sreg != PIC_CALL_REG)
5478 as_warn (_("MIPS PIC call to register other than $25"));
5480 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5483 if (mips_cprestore_offset < 0)
5484 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5487 if (! mips_frame_reg_valid)
5489 as_warn (_("No .frame pseudo-op used in PIC code"));
5490 /* Quiet this warning. */
5491 mips_frame_reg_valid = 1;
5493 if (! mips_cprestore_valid)
5495 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5496 /* Quiet this warning. */
5497 mips_cprestore_valid = 1;
5499 expr1.X_add_number = mips_cprestore_offset;
5500 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5503 HAVE_64BIT_ADDRESSES);
5513 if (mips_pic == NO_PIC)
5514 macro_build (&offset_expr, "jal", "a");
5515 else if (mips_pic == SVR4_PIC)
5517 /* If this is a reference to an external symbol, and we are
5518 using a small GOT, we want
5519 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5523 lw $gp,cprestore($sp)
5524 The cprestore value is set using the .cprestore
5525 pseudo-op. If we are using a big GOT, we want
5526 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5528 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5532 lw $gp,cprestore($sp)
5533 If the symbol is not external, we want
5534 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5536 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5539 lw $gp,cprestore($sp)
5541 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5542 sequences above, minus nops, unless the symbol is local,
5543 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5549 relax_start (offset_expr.X_add_symbol);
5550 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5551 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5554 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5555 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5561 relax_start (offset_expr.X_add_symbol);
5562 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5563 BFD_RELOC_MIPS_CALL_HI16);
5564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5565 PIC_CALL_REG, mips_gp_register);
5566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5567 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5570 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5571 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5573 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5574 PIC_CALL_REG, PIC_CALL_REG,
5575 BFD_RELOC_MIPS_GOT_OFST);
5579 macro_build_jalr (&offset_expr);
5583 relax_start (offset_expr.X_add_symbol);
5586 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5587 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5596 gpdelay = reg_needs_delay (mips_gp_register);
5597 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5598 BFD_RELOC_MIPS_CALL_HI16);
5599 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5600 PIC_CALL_REG, mips_gp_register);
5601 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5602 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5607 macro_build (NULL, "nop", "");
5609 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5610 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5613 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5614 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5616 macro_build_jalr (&offset_expr);
5618 if (mips_cprestore_offset < 0)
5619 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5622 if (! mips_frame_reg_valid)
5624 as_warn (_("No .frame pseudo-op used in PIC code"));
5625 /* Quiet this warning. */
5626 mips_frame_reg_valid = 1;
5628 if (! mips_cprestore_valid)
5630 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5631 /* Quiet this warning. */
5632 mips_cprestore_valid = 1;
5634 if (mips_opts.noreorder)
5635 macro_build (NULL, "nop", "");
5636 expr1.X_add_number = mips_cprestore_offset;
5637 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5640 HAVE_64BIT_ADDRESSES);
5666 /* Itbl support may require additional care here. */
5671 /* Itbl support may require additional care here. */
5676 /* Itbl support may require additional care here. */
5681 /* Itbl support may require additional care here. */
5693 if (mips_opts.arch == CPU_R4650)
5695 as_bad (_("opcode not supported on this processor"));
5699 /* Itbl support may require additional care here. */
5704 /* Itbl support may require additional care here. */
5709 /* Itbl support may require additional care here. */
5729 if (breg == treg || coproc || lr)
5751 /* Itbl support may require additional care here. */
5756 /* Itbl support may require additional care here. */
5761 /* Itbl support may require additional care here. */
5766 /* Itbl support may require additional care here. */
5782 if (mips_opts.arch == CPU_R4650)
5784 as_bad (_("opcode not supported on this processor"));
5789 /* Itbl support may require additional care here. */
5793 /* Itbl support may require additional care here. */
5798 /* Itbl support may require additional care here. */
5810 /* Itbl support may require additional care here. */
5811 if (mask == M_LWC1_AB
5812 || mask == M_SWC1_AB
5813 || mask == M_LDC1_AB
5814 || mask == M_SDC1_AB
5823 /* Sign-extending 32-bit constants makes their handling easier.
5824 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5826 if ((! HAVE_64BIT_ADDRESSES
5827 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5828 && (offset_expr.X_op == O_constant)
5829 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5830 == ~((bfd_vma) 0x7fffffff)))
5832 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5833 as_bad (_("constant too large"));
5835 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5836 ^ 0x80000000) - 0x80000000);
5839 if (offset_expr.X_op != O_constant
5840 && offset_expr.X_op != O_symbol)
5842 as_bad (_("expression too complex"));
5843 offset_expr.X_op = O_constant;
5846 /* A constant expression in PIC code can be handled just as it
5847 is in non PIC code. */
5848 if (mips_pic == NO_PIC
5849 || offset_expr.X_op == O_constant)
5851 /* If this is a reference to a GP relative symbol, and there
5852 is no base register, we want
5853 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5854 Otherwise, if there is no base register, we want
5855 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5856 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5857 If we have a constant, we need two instructions anyhow,
5858 so we always use the latter form.
5860 If we have a base register, and this is a reference to a
5861 GP relative symbol, we want
5862 addu $tempreg,$breg,$gp
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5865 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5866 addu $tempreg,$tempreg,$breg
5867 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5868 With a constant we always use the latter case.
5870 With 64bit address space and no base register and $at usable,
5872 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5873 lui $at,<sym> (BFD_RELOC_HI16_S)
5874 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5877 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5878 If we have a base register, we want
5879 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5880 lui $at,<sym> (BFD_RELOC_HI16_S)
5881 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5885 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5887 Without $at we can't generate the optimal path for superscalar
5888 processors here since this would require two temporary registers.
5889 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5890 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5892 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5894 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5895 If we have a base register, we want
5896 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5897 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5899 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5901 daddu $tempreg,$tempreg,$breg
5902 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5904 If we have 64-bit addresses, as an optimization, for
5905 addresses which are 32-bit constants (e.g. kseg0/kseg1
5906 addresses) we fall back to the 32-bit address generation
5907 mechanism since it is more efficient. Note that due to
5908 the signed offset used by memory operations, the 32-bit
5909 range is shifted down by 32768 here. This code should
5910 probably attempt to generate 64-bit constants more
5911 efficiently in general.
5913 As an extension for architectures with 64-bit registers,
5914 we don't truncate 64-bit addresses given as literal
5915 constants down to 32 bits, to support existing practice
5916 in the mips64 Linux (the kernel), that compiles source
5917 files with -mabi=64, assembling them as o32 or n32 (with
5918 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5919 the whole kernel is loaded into a memory region that is
5920 addressable with sign-extended 32-bit addresses, it is
5921 wasteful to compute the upper 32 bits of every
5922 non-literal address, that takes more space and time.
5923 Some day this should probably be implemented as an
5924 assembler option, such that the kernel doesn't have to
5925 use such ugly hacks, even though it will still have to
5926 end up converting the binary to ELF32 for a number of
5927 platforms whose boot loaders don't support ELF64
5929 if ((HAVE_64BIT_ADDRESSES
5930 && ! (offset_expr.X_op == O_constant
5931 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5933 && offset_expr.X_op == O_constant
5934 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5936 /* ??? We don't provide a GP-relative alternative for
5937 these macros. It used not to be possible with the
5938 original relaxation code, but it could be done now. */
5940 if (used_at == 0 && ! mips_opts.noat)
5942 macro_build (&offset_expr, "lui", "t,u", tempreg,
5943 BFD_RELOC_MIPS_HIGHEST);
5944 macro_build (&offset_expr, "lui", "t,u", AT,
5946 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5947 tempreg, BFD_RELOC_MIPS_HIGHER);
5949 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
5950 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5951 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5952 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
5958 macro_build (&offset_expr, "lui", "t,u", tempreg,
5959 BFD_RELOC_MIPS_HIGHEST);
5960 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5961 tempreg, BFD_RELOC_MIPS_HIGHER);
5962 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5963 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5964 tempreg, BFD_RELOC_HI16_S);
5965 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5967 macro_build (NULL, "daddu", "d,v,t",
5968 tempreg, tempreg, breg);
5969 macro_build (&offset_expr, s, fmt, treg,
5970 BFD_RELOC_LO16, tempreg);
5976 if (offset_expr.X_op == O_constant
5977 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
5978 as_bad (_("load/store address overflow (max 32 bits)"));
5982 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5983 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5985 relax_start (offset_expr.X_add_symbol);
5986 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
5991 macro_build_lui (&offset_expr, tempreg);
5992 macro_build (&offset_expr, s, fmt, treg,
5993 BFD_RELOC_LO16, tempreg);
5994 if (mips_relax.sequence)
5999 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6000 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6002 relax_start (offset_expr.X_add_symbol);
6003 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6004 tempreg, breg, mips_gp_register);
6005 macro_build (&offset_expr, s, fmt, treg,
6006 BFD_RELOC_GPREL16, tempreg);
6009 macro_build_lui (&offset_expr, tempreg);
6010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6011 tempreg, tempreg, breg);
6012 macro_build (&offset_expr, s, fmt, treg,
6013 BFD_RELOC_LO16, tempreg);
6014 if (mips_relax.sequence)
6018 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6020 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6022 /* If this is a reference to an external symbol, we want
6023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6025 <op> $treg,0($tempreg)
6027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6029 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6030 <op> $treg,0($tempreg)
6033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6034 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6036 If there is a base register, we add it to $tempreg before
6037 the <op>. If there is a constant, we stick it in the
6038 <op> instruction. We don't handle constants larger than
6039 16 bits, because we have no way to load the upper 16 bits
6040 (actually, we could handle them for the subset of cases
6041 in which we are not using $at). */
6042 assert (offset_expr.X_op == O_symbol);
6045 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6046 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6048 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6049 tempreg, tempreg, breg);
6050 macro_build (&offset_expr, s, fmt, treg,
6051 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6058 expr1.X_add_number = offset_expr.X_add_number;
6059 offset_expr.X_add_number = 0;
6060 if (expr1.X_add_number < -0x8000
6061 || expr1.X_add_number >= 0x8000)
6062 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6063 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6064 lw_reloc_type, mips_gp_register);
6066 relax_start (offset_expr.X_add_symbol);
6068 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6069 tempreg, BFD_RELOC_LO16);
6072 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6073 tempreg, tempreg, breg);
6074 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6076 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6080 /* If this is a reference to an external symbol, we want
6081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6082 addu $tempreg,$tempreg,$gp
6083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6084 <op> $treg,0($tempreg)
6086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6088 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6089 <op> $treg,0($tempreg)
6090 If there is a base register, we add it to $tempreg before
6091 the <op>. If there is a constant, we stick it in the
6092 <op> instruction. We don't handle constants larger than
6093 16 bits, because we have no way to load the upper 16 bits
6094 (actually, we could handle them for the subset of cases
6095 in which we are not using $at). */
6096 assert (offset_expr.X_op == O_symbol);
6097 expr1.X_add_number = offset_expr.X_add_number;
6098 offset_expr.X_add_number = 0;
6099 if (expr1.X_add_number < -0x8000
6100 || expr1.X_add_number >= 0x8000)
6101 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6102 gpdelay = reg_needs_delay (mips_gp_register);
6103 relax_start (offset_expr.X_add_symbol);
6104 macro_build (&offset_expr, "lui", "t,u", tempreg,
6105 BFD_RELOC_MIPS_GOT_HI16);
6106 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6108 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6109 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6112 macro_build (NULL, "nop", "");
6113 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6114 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6116 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6117 tempreg, BFD_RELOC_LO16);
6121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6122 tempreg, tempreg, breg);
6123 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6125 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6127 /* If this is a reference to an external symbol, we want
6128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6129 add $tempreg,$tempreg,$gp
6130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6131 <op> $treg,<ofst>($tempreg)
6132 Otherwise, for local symbols, we want:
6133 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6134 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6135 assert (offset_expr.X_op == O_symbol);
6136 expr1.X_add_number = offset_expr.X_add_number;
6137 offset_expr.X_add_number = 0;
6138 if (expr1.X_add_number < -0x8000
6139 || expr1.X_add_number >= 0x8000)
6140 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6141 relax_start (offset_expr.X_add_symbol);
6142 macro_build (&offset_expr, "lui", "t,u", tempreg,
6143 BFD_RELOC_MIPS_GOT_HI16);
6144 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6147 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6150 tempreg, tempreg, breg);
6151 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6154 offset_expr.X_add_number = expr1.X_add_number;
6155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6156 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6158 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6159 tempreg, tempreg, breg);
6160 macro_build (&offset_expr, s, fmt, treg,
6161 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6174 load_register (treg, &imm_expr, 0);
6178 load_register (treg, &imm_expr, 1);
6182 if (imm_expr.X_op == O_constant)
6184 load_register (AT, &imm_expr, 0);
6185 macro_build (NULL, "mtc1", "t,G", AT, treg);
6190 assert (offset_expr.X_op == O_symbol
6191 && strcmp (segment_name (S_GET_SEGMENT
6192 (offset_expr.X_add_symbol)),
6194 && offset_expr.X_add_number == 0);
6195 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6196 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6201 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6202 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6203 order 32 bits of the value and the low order 32 bits are either
6204 zero or in OFFSET_EXPR. */
6205 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6207 if (HAVE_64BIT_GPRS)
6208 load_register (treg, &imm_expr, 1);
6213 if (target_big_endian)
6225 load_register (hreg, &imm_expr, 0);
6228 if (offset_expr.X_op == O_absent)
6229 move_register (lreg, 0);
6232 assert (offset_expr.X_op == O_constant);
6233 load_register (lreg, &offset_expr, 0);
6240 /* We know that sym is in the .rdata section. First we get the
6241 upper 16 bits of the address. */
6242 if (mips_pic == NO_PIC)
6244 macro_build_lui (&offset_expr, AT);
6246 else if (mips_pic == SVR4_PIC)
6248 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6249 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6254 /* Now we load the register(s). */
6255 if (HAVE_64BIT_GPRS)
6256 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6259 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6262 /* FIXME: How in the world do we deal with the possible
6264 offset_expr.X_add_number += 4;
6265 macro_build (&offset_expr, "lw", "t,o(b)",
6266 treg + 1, BFD_RELOC_LO16, AT);
6272 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6273 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6274 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6275 the value and the low order 32 bits are either zero or in
6277 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6279 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6280 if (HAVE_64BIT_FPRS)
6282 assert (HAVE_64BIT_GPRS);
6283 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6287 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6288 if (offset_expr.X_op == O_absent)
6289 macro_build (NULL, "mtc1", "t,G", 0, treg);
6292 assert (offset_expr.X_op == O_constant);
6293 load_register (AT, &offset_expr, 0);
6294 macro_build (NULL, "mtc1", "t,G", AT, treg);
6300 assert (offset_expr.X_op == O_symbol
6301 && offset_expr.X_add_number == 0);
6302 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6303 if (strcmp (s, ".lit8") == 0)
6305 if (mips_opts.isa != ISA_MIPS1)
6307 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6308 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6311 breg = mips_gp_register;
6312 r = BFD_RELOC_MIPS_LITERAL;
6317 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6318 if (mips_pic == SVR4_PIC)
6319 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6320 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6323 /* FIXME: This won't work for a 64 bit address. */
6324 macro_build_lui (&offset_expr, AT);
6327 if (mips_opts.isa != ISA_MIPS1)
6329 macro_build (&offset_expr, "ldc1", "T,o(b)",
6330 treg, BFD_RELOC_LO16, AT);
6339 if (mips_opts.arch == CPU_R4650)
6341 as_bad (_("opcode not supported on this processor"));
6344 /* Even on a big endian machine $fn comes before $fn+1. We have
6345 to adjust when loading from memory. */
6348 assert (mips_opts.isa == ISA_MIPS1);
6349 macro_build (&offset_expr, "lwc1", "T,o(b)",
6350 target_big_endian ? treg + 1 : treg, r, breg);
6351 /* FIXME: A possible overflow which I don't know how to deal
6353 offset_expr.X_add_number += 4;
6354 macro_build (&offset_expr, "lwc1", "T,o(b)",
6355 target_big_endian ? treg : treg + 1, r, breg);
6363 * The MIPS assembler seems to check for X_add_number not
6364 * being double aligned and generating:
6367 * addiu at,at,%lo(foo+1)
6370 * But, the resulting address is the same after relocation so why
6371 * generate the extra instruction?
6373 if (mips_opts.arch == CPU_R4650)
6375 as_bad (_("opcode not supported on this processor"));
6378 /* Itbl support may require additional care here. */
6380 if (mips_opts.isa != ISA_MIPS1)
6391 if (mips_opts.arch == CPU_R4650)
6393 as_bad (_("opcode not supported on this processor"));
6397 if (mips_opts.isa != ISA_MIPS1)
6405 /* Itbl support may require additional care here. */
6410 if (HAVE_64BIT_GPRS)
6421 if (HAVE_64BIT_GPRS)
6431 if (offset_expr.X_op != O_symbol
6432 && offset_expr.X_op != O_constant)
6434 as_bad (_("expression too complex"));
6435 offset_expr.X_op = O_constant;
6438 /* Even on a big endian machine $fn comes before $fn+1. We have
6439 to adjust when loading from memory. We set coproc if we must
6440 load $fn+1 first. */
6441 /* Itbl support may require additional care here. */
6442 if (! target_big_endian)
6445 if (mips_pic == NO_PIC
6446 || offset_expr.X_op == O_constant)
6448 /* If this is a reference to a GP relative symbol, we want
6449 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6450 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6451 If we have a base register, we use this
6453 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6454 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6455 If this is not a GP relative symbol, we want
6456 lui $at,<sym> (BFD_RELOC_HI16_S)
6457 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6458 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6459 If there is a base register, we add it to $at after the
6460 lui instruction. If there is a constant, we always use
6462 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6463 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6467 relax_start (offset_expr.X_add_symbol);
6470 tempreg = mips_gp_register;
6475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6476 AT, breg, mips_gp_register);
6481 /* Itbl support may require additional care here. */
6482 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6483 BFD_RELOC_GPREL16, tempreg);
6484 offset_expr.X_add_number += 4;
6486 /* Set mips_optimize to 2 to avoid inserting an
6488 hold_mips_optimize = mips_optimize;
6490 /* Itbl support may require additional care here. */
6491 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6492 BFD_RELOC_GPREL16, tempreg);
6493 mips_optimize = hold_mips_optimize;
6497 /* We just generated two relocs. When tc_gen_reloc
6498 handles this case, it will skip the first reloc and
6499 handle the second. The second reloc already has an
6500 extra addend of 4, which we added above. We must
6501 subtract it out, and then subtract another 4 to make
6502 the first reloc come out right. The second reloc
6503 will come out right because we are going to add 4 to
6504 offset_expr when we build its instruction below.
6506 If we have a symbol, then we don't want to include
6507 the offset, because it will wind up being included
6508 when we generate the reloc. */
6510 if (offset_expr.X_op == O_constant)
6511 offset_expr.X_add_number -= 8;
6514 offset_expr.X_add_number = -4;
6515 offset_expr.X_op = O_constant;
6518 macro_build_lui (&offset_expr, AT);
6520 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6521 /* Itbl support may require additional care here. */
6522 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6523 BFD_RELOC_LO16, AT);
6524 /* FIXME: How do we handle overflow here? */
6525 offset_expr.X_add_number += 4;
6526 /* Itbl support may require additional care here. */
6527 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6528 BFD_RELOC_LO16, AT);
6529 if (mips_relax.sequence)
6532 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6534 /* If this is a reference to an external symbol, we want
6535 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6540 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6542 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6543 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6544 If there is a base register we add it to $at before the
6545 lwc1 instructions. If there is a constant we include it
6546 in the lwc1 instructions. */
6548 expr1.X_add_number = offset_expr.X_add_number;
6549 if (expr1.X_add_number < -0x8000
6550 || expr1.X_add_number >= 0x8000 - 4)
6551 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6552 load_got_offset (AT, &offset_expr);
6555 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6557 /* Set mips_optimize to 2 to avoid inserting an undesired
6559 hold_mips_optimize = mips_optimize;
6562 /* Itbl support may require additional care here. */
6563 relax_start (offset_expr.X_add_symbol);
6564 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6565 BFD_RELOC_LO16, AT);
6566 expr1.X_add_number += 4;
6567 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6568 BFD_RELOC_LO16, AT);
6570 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6571 BFD_RELOC_LO16, AT);
6572 offset_expr.X_add_number += 4;
6573 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6574 BFD_RELOC_LO16, AT);
6577 mips_optimize = hold_mips_optimize;
6579 else if (mips_pic == SVR4_PIC)
6583 /* If this is a reference to an external symbol, we want
6584 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6586 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6593 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6594 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6595 If there is a base register we add it to $at before the
6596 lwc1 instructions. If there is a constant we include it
6597 in the lwc1 instructions. */
6599 expr1.X_add_number = offset_expr.X_add_number;
6600 offset_expr.X_add_number = 0;
6601 if (expr1.X_add_number < -0x8000
6602 || expr1.X_add_number >= 0x8000 - 4)
6603 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6604 gpdelay = reg_needs_delay (mips_gp_register);
6605 relax_start (offset_expr.X_add_symbol);
6606 macro_build (&offset_expr, "lui", "t,u",
6607 AT, BFD_RELOC_MIPS_GOT_HI16);
6608 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6609 AT, AT, mips_gp_register);
6610 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6611 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6614 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6615 /* Itbl support may require additional care here. */
6616 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6617 BFD_RELOC_LO16, AT);
6618 expr1.X_add_number += 4;
6620 /* Set mips_optimize to 2 to avoid inserting an undesired
6622 hold_mips_optimize = mips_optimize;
6624 /* Itbl support may require additional care here. */
6625 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6626 BFD_RELOC_LO16, AT);
6627 mips_optimize = hold_mips_optimize;
6628 expr1.X_add_number -= 4;
6631 offset_expr.X_add_number = expr1.X_add_number;
6633 macro_build (NULL, "nop", "");
6634 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6635 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6638 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6639 /* Itbl support may require additional care here. */
6640 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6641 BFD_RELOC_LO16, AT);
6642 offset_expr.X_add_number += 4;
6644 /* Set mips_optimize to 2 to avoid inserting an undesired
6646 hold_mips_optimize = mips_optimize;
6648 /* Itbl support may require additional care here. */
6649 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6650 BFD_RELOC_LO16, AT);
6651 mips_optimize = hold_mips_optimize;
6668 assert (HAVE_32BIT_ADDRESSES);
6669 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6670 offset_expr.X_add_number += 4;
6671 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6674 /* New code added to support COPZ instructions.
6675 This code builds table entries out of the macros in mip_opcodes.
6676 R4000 uses interlocks to handle coproc delays.
6677 Other chips (like the R3000) require nops to be inserted for delays.
6679 FIXME: Currently, we require that the user handle delays.
6680 In order to fill delay slots for non-interlocked chips,
6681 we must have a way to specify delays based on the coprocessor.
6682 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6683 What are the side-effects of the cop instruction?
6684 What cache support might we have and what are its effects?
6685 Both coprocessor & memory require delays. how long???
6686 What registers are read/set/modified?
6688 If an itbl is provided to interpret cop instructions,
6689 this knowledge can be encoded in the itbl spec. */
6703 /* For now we just do C (same as Cz). The parameter will be
6704 stored in insn_opcode by mips_ip. */
6705 macro_build (NULL, s, "C", ip->insn_opcode);
6709 move_register (dreg, sreg);
6712 #ifdef LOSING_COMPILER
6714 /* Try and see if this is a new itbl instruction.
6715 This code builds table entries out of the macros in mip_opcodes.
6716 FIXME: For now we just assemble the expression and pass it's
6717 value along as a 32-bit immediate.
6718 We may want to have the assembler assemble this value,
6719 so that we gain the assembler's knowledge of delay slots,
6721 Would it be more efficient to use mask (id) here? */
6722 if (itbl_have_entries
6723 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6725 s = ip->insn_mo->name;
6727 coproc = ITBL_DECODE_PNUM (immed_expr);;
6728 macro_build (&immed_expr, s, "C");
6735 as_warn (_("Macro used $at after \".set noat\""));
6739 macro2 (struct mips_cl_insn *ip)
6741 register int treg, sreg, dreg, breg;
6756 bfd_reloc_code_real_type r;
6758 treg = (ip->insn_opcode >> 16) & 0x1f;
6759 dreg = (ip->insn_opcode >> 11) & 0x1f;
6760 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6761 mask = ip->insn_mo->mask;
6763 expr1.X_op = O_constant;
6764 expr1.X_op_symbol = NULL;
6765 expr1.X_add_symbol = NULL;
6766 expr1.X_add_number = 1;
6770 #endif /* LOSING_COMPILER */
6775 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6776 macro_build (NULL, "mflo", "d", dreg);
6782 /* The MIPS assembler some times generates shifts and adds. I'm
6783 not trying to be that fancy. GCC should do this for us
6785 load_register (AT, &imm_expr, dbl);
6786 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6787 macro_build (NULL, "mflo", "d", dreg);
6800 mips_emit_delays (TRUE);
6801 ++mips_opts.noreorder;
6802 mips_any_noreorder = 1;
6804 load_register (AT, &imm_expr, dbl);
6805 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6806 macro_build (NULL, "mflo", "d", dreg);
6807 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6808 macro_build (NULL, "mfhi", "d", AT);
6810 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6813 expr1.X_add_number = 8;
6814 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6815 macro_build (NULL, "nop", "", 0);
6816 macro_build (NULL, "break", "c", 6);
6818 --mips_opts.noreorder;
6819 macro_build (NULL, "mflo", "d", dreg);
6832 mips_emit_delays (TRUE);
6833 ++mips_opts.noreorder;
6834 mips_any_noreorder = 1;
6836 load_register (AT, &imm_expr, dbl);
6837 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6838 sreg, imm ? AT : treg);
6839 macro_build (NULL, "mfhi", "d", AT);
6840 macro_build (NULL, "mflo", "d", dreg);
6842 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6845 expr1.X_add_number = 8;
6846 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6847 macro_build (NULL, "nop", "", 0);
6848 macro_build (NULL, "break", "c", 6);
6850 --mips_opts.noreorder;
6854 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6866 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6867 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6872 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6873 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6874 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6875 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6879 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6891 macro_build (NULL, "negu", "d,w", tempreg, treg);
6892 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6897 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6898 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6899 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6900 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6908 if (imm_expr.X_op != O_constant)
6909 as_bad (_("Improper rotate count"));
6910 rot = imm_expr.X_add_number & 0x3f;
6911 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6913 rot = (64 - rot) & 0x3f;
6915 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6917 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6922 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
6925 l = (rot < 0x20) ? "dsll" : "dsll32";
6926 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6928 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
6929 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6930 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6938 if (imm_expr.X_op != O_constant)
6939 as_bad (_("Improper rotate count"));
6940 rot = imm_expr.X_add_number & 0x1f;
6941 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6943 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6948 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
6951 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
6952 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6953 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6958 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6960 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
6963 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6964 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
6965 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
6966 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6970 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6972 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
6975 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6976 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
6977 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
6978 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6986 if (imm_expr.X_op != O_constant)
6987 as_bad (_("Improper rotate count"));
6988 rot = imm_expr.X_add_number & 0x3f;
6989 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6992 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6994 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6999 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7002 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7003 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7005 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7006 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7007 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7015 if (imm_expr.X_op != O_constant)
7016 as_bad (_("Improper rotate count"));
7017 rot = imm_expr.X_add_number & 0x1f;
7018 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7020 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7025 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7028 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7029 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7030 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7035 if (mips_opts.arch == CPU_R4650)
7037 as_bad (_("opcode not supported on this processor"));
7040 assert (mips_opts.isa == ISA_MIPS1);
7041 /* Even on a big endian machine $fn comes before $fn+1. We have
7042 to adjust when storing to memory. */
7043 macro_build (&offset_expr, "swc1", "T,o(b)",
7044 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7045 offset_expr.X_add_number += 4;
7046 macro_build (&offset_expr, "swc1", "T,o(b)",
7047 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7052 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7054 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7057 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7058 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7063 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7065 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7070 as_warn (_("Instruction %s: result is always false"),
7072 move_register (dreg, 0);
7075 if (imm_expr.X_op == O_constant
7076 && imm_expr.X_add_number >= 0
7077 && imm_expr.X_add_number < 0x10000)
7079 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7082 else if (imm_expr.X_op == O_constant
7083 && imm_expr.X_add_number > -0x8000
7084 && imm_expr.X_add_number < 0)
7086 imm_expr.X_add_number = -imm_expr.X_add_number;
7087 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7088 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7093 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7094 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7097 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7102 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7108 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7109 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7112 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7114 if (imm_expr.X_op == O_constant
7115 && imm_expr.X_add_number >= -0x8000
7116 && imm_expr.X_add_number < 0x8000)
7118 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7119 dreg, sreg, BFD_RELOC_LO16);
7124 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7125 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7129 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7134 case M_SGT: /* sreg > treg <==> treg < sreg */
7140 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7143 case M_SGT_I: /* sreg > I <==> I < sreg */
7149 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7150 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7153 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7159 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7160 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7163 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7169 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7170 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7171 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7175 if (imm_expr.X_op == O_constant
7176 && imm_expr.X_add_number >= -0x8000
7177 && imm_expr.X_add_number < 0x8000)
7179 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7182 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7183 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7187 if (imm_expr.X_op == O_constant
7188 && imm_expr.X_add_number >= -0x8000
7189 && imm_expr.X_add_number < 0x8000)
7191 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7195 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7196 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7201 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7203 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7206 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7207 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7212 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7214 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7219 as_warn (_("Instruction %s: result is always true"),
7221 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7222 dreg, 0, BFD_RELOC_LO16);
7225 if (imm_expr.X_op == O_constant
7226 && imm_expr.X_add_number >= 0
7227 && imm_expr.X_add_number < 0x10000)
7229 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7232 else if (imm_expr.X_op == O_constant
7233 && imm_expr.X_add_number > -0x8000
7234 && imm_expr.X_add_number < 0)
7236 imm_expr.X_add_number = -imm_expr.X_add_number;
7237 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7238 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7243 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7244 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7247 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7255 if (imm_expr.X_op == O_constant
7256 && imm_expr.X_add_number > -0x8000
7257 && imm_expr.X_add_number <= 0x8000)
7259 imm_expr.X_add_number = -imm_expr.X_add_number;
7260 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7261 dreg, sreg, BFD_RELOC_LO16);
7264 load_register (AT, &imm_expr, dbl);
7265 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7271 if (imm_expr.X_op == O_constant
7272 && imm_expr.X_add_number > -0x8000
7273 && imm_expr.X_add_number <= 0x8000)
7275 imm_expr.X_add_number = -imm_expr.X_add_number;
7276 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7277 dreg, sreg, BFD_RELOC_LO16);
7280 load_register (AT, &imm_expr, dbl);
7281 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7302 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7303 macro_build (NULL, s, "s,t", sreg, AT);
7308 assert (mips_opts.isa == ISA_MIPS1);
7309 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7310 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7313 * Is the double cfc1 instruction a bug in the mips assembler;
7314 * or is there a reason for it?
7316 mips_emit_delays (TRUE);
7317 ++mips_opts.noreorder;
7318 mips_any_noreorder = 1;
7319 macro_build (NULL, "cfc1", "t,G", treg, RA);
7320 macro_build (NULL, "cfc1", "t,G", treg, RA);
7321 macro_build (NULL, "nop", "");
7322 expr1.X_add_number = 3;
7323 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7324 expr1.X_add_number = 2;
7325 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7326 macro_build (NULL, "ctc1", "t,G", AT, RA);
7327 macro_build (NULL, "nop", "");
7328 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7330 macro_build (NULL, "ctc1", "t,G", treg, RA);
7331 macro_build (NULL, "nop", "");
7332 --mips_opts.noreorder;
7341 if (offset_expr.X_add_number >= 0x7fff)
7342 as_bad (_("operand overflow"));
7343 if (! target_big_endian)
7344 ++offset_expr.X_add_number;
7345 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7346 if (! target_big_endian)
7347 --offset_expr.X_add_number;
7349 ++offset_expr.X_add_number;
7350 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7351 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7352 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7365 if (offset_expr.X_add_number >= 0x8000 - off)
7366 as_bad (_("operand overflow"));
7371 if (! target_big_endian)
7372 offset_expr.X_add_number += off;
7373 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7374 if (! target_big_endian)
7375 offset_expr.X_add_number -= off;
7377 offset_expr.X_add_number += off;
7378 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7380 /* If necessary, move the result in tempreg the final destination. */
7381 if (treg == tempreg)
7383 /* Protect second load's delay slot. */
7385 move_register (treg, tempreg);
7399 load_address (AT, &offset_expr, &used_at);
7401 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7402 if (! target_big_endian)
7403 expr1.X_add_number = off;
7405 expr1.X_add_number = 0;
7406 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7407 if (! target_big_endian)
7408 expr1.X_add_number = 0;
7410 expr1.X_add_number = off;
7411 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7417 load_address (AT, &offset_expr, &used_at);
7419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7420 if (target_big_endian)
7421 expr1.X_add_number = 0;
7422 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7423 treg, BFD_RELOC_LO16, AT);
7424 if (target_big_endian)
7425 expr1.X_add_number = 1;
7427 expr1.X_add_number = 0;
7428 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7429 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7430 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7434 if (offset_expr.X_add_number >= 0x7fff)
7435 as_bad (_("operand overflow"));
7436 if (target_big_endian)
7437 ++offset_expr.X_add_number;
7438 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7439 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7440 if (target_big_endian)
7441 --offset_expr.X_add_number;
7443 ++offset_expr.X_add_number;
7444 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7457 if (offset_expr.X_add_number >= 0x8000 - off)
7458 as_bad (_("operand overflow"));
7459 if (! target_big_endian)
7460 offset_expr.X_add_number += off;
7461 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7462 if (! target_big_endian)
7463 offset_expr.X_add_number -= off;
7465 offset_expr.X_add_number += off;
7466 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7480 load_address (AT, &offset_expr, &used_at);
7482 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7483 if (! target_big_endian)
7484 expr1.X_add_number = off;
7486 expr1.X_add_number = 0;
7487 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7488 if (! target_big_endian)
7489 expr1.X_add_number = 0;
7491 expr1.X_add_number = off;
7492 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7497 load_address (AT, &offset_expr, &used_at);
7499 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7500 if (! target_big_endian)
7501 expr1.X_add_number = 0;
7502 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7503 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7504 if (! target_big_endian)
7505 expr1.X_add_number = 1;
7507 expr1.X_add_number = 0;
7508 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7509 if (! target_big_endian)
7510 expr1.X_add_number = 0;
7512 expr1.X_add_number = 1;
7513 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7514 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7515 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7519 /* FIXME: Check if this is one of the itbl macros, since they
7520 are added dynamically. */
7521 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7525 as_warn (_("Macro used $at after \".set noat\""));
7528 /* Implement macros in mips16 mode. */
7531 mips16_macro (struct mips_cl_insn *ip)
7534 int xreg, yreg, zreg, tmp;
7537 const char *s, *s2, *s3;
7539 mask = ip->insn_mo->mask;
7541 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7542 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7543 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7545 expr1.X_op = O_constant;
7546 expr1.X_op_symbol = NULL;
7547 expr1.X_add_symbol = NULL;
7548 expr1.X_add_number = 1;
7567 mips_emit_delays (TRUE);
7568 ++mips_opts.noreorder;
7569 mips_any_noreorder = 1;
7570 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7571 expr1.X_add_number = 2;
7572 macro_build (&expr1, "bnez", "x,p", yreg);
7573 macro_build (NULL, "break", "6", 7);
7575 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7576 since that causes an overflow. We should do that as well,
7577 but I don't see how to do the comparisons without a temporary
7579 --mips_opts.noreorder;
7580 macro_build (NULL, s, "x", zreg);
7599 mips_emit_delays (TRUE);
7600 ++mips_opts.noreorder;
7601 mips_any_noreorder = 1;
7602 macro_build (NULL, s, "0,x,y", xreg, yreg);
7603 expr1.X_add_number = 2;
7604 macro_build (&expr1, "bnez", "x,p", yreg);
7605 macro_build (NULL, "break", "6", 7);
7606 --mips_opts.noreorder;
7607 macro_build (NULL, s2, "x", zreg);
7613 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7614 macro_build (NULL, "mflo", "x", zreg);
7622 if (imm_expr.X_op != O_constant)
7623 as_bad (_("Unsupported large constant"));
7624 imm_expr.X_add_number = -imm_expr.X_add_number;
7625 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7629 if (imm_expr.X_op != O_constant)
7630 as_bad (_("Unsupported large constant"));
7631 imm_expr.X_add_number = -imm_expr.X_add_number;
7632 macro_build (&imm_expr, "addiu", "x,k", xreg);
7636 if (imm_expr.X_op != O_constant)
7637 as_bad (_("Unsupported large constant"));
7638 imm_expr.X_add_number = -imm_expr.X_add_number;
7639 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7661 goto do_reverse_branch;
7665 goto do_reverse_branch;
7677 goto do_reverse_branch;
7688 macro_build (NULL, s, "x,y", xreg, yreg);
7689 macro_build (&offset_expr, s2, "p");
7716 goto do_addone_branch_i;
7721 goto do_addone_branch_i;
7736 goto do_addone_branch_i;
7743 if (imm_expr.X_op != O_constant)
7744 as_bad (_("Unsupported large constant"));
7745 ++imm_expr.X_add_number;
7748 macro_build (&imm_expr, s, s3, xreg);
7749 macro_build (&offset_expr, s2, "p");
7753 expr1.X_add_number = 0;
7754 macro_build (&expr1, "slti", "x,8", yreg);
7756 move_register (xreg, yreg);
7757 expr1.X_add_number = 2;
7758 macro_build (&expr1, "bteqz", "p");
7759 macro_build (NULL, "neg", "x,w", xreg, xreg);
7763 /* For consistency checking, verify that all bits are specified either
7764 by the match/mask part of the instruction definition, or by the
7767 validate_mips_insn (const struct mips_opcode *opc)
7769 const char *p = opc->args;
7771 unsigned long used_bits = opc->mask;
7773 if ((used_bits & opc->match) != opc->match)
7775 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7776 opc->name, opc->args);
7779 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7789 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7790 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7791 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7792 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7793 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7794 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7795 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7796 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7797 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7800 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7801 c, opc->name, opc->args);
7805 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7806 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7808 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7809 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7810 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7811 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7813 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7814 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7816 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7817 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7819 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7820 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7821 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7822 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7823 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7824 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7825 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7826 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7827 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7828 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7829 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7830 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7831 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7832 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7833 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7834 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7835 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7837 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7838 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7839 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7840 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7842 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7843 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7844 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7845 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7846 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7847 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7848 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7849 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7850 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7853 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7854 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7855 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7856 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7857 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7861 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7862 c, opc->name, opc->args);
7866 if (used_bits != 0xffffffff)
7868 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7869 ~used_bits & 0xffffffff, opc->name, opc->args);
7875 /* This routine assembles an instruction into its binary format. As a
7876 side effect, it sets one of the global variables imm_reloc or
7877 offset_reloc to the type of relocation to do if one of the operands
7878 is an address expression. */
7881 mips_ip (char *str, struct mips_cl_insn *ip)
7886 struct mips_opcode *insn;
7889 unsigned int lastregno = 0;
7890 unsigned int lastpos = 0;
7891 unsigned int limlo, limhi;
7897 /* If the instruction contains a '.', we first try to match an instruction
7898 including the '.'. Then we try again without the '.'. */
7900 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7903 /* If we stopped on whitespace, then replace the whitespace with null for
7904 the call to hash_find. Save the character we replaced just in case we
7905 have to re-parse the instruction. */
7912 insn = (struct mips_opcode *) hash_find (op_hash, str);
7914 /* If we didn't find the instruction in the opcode table, try again, but
7915 this time with just the instruction up to, but not including the
7919 /* Restore the character we overwrite above (if any). */
7923 /* Scan up to the first '.' or whitespace. */
7925 *s != '\0' && *s != '.' && !ISSPACE (*s);
7929 /* If we did not find a '.', then we can quit now. */
7932 insn_error = "unrecognized opcode";
7936 /* Lookup the instruction in the hash table. */
7938 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7940 insn_error = "unrecognized opcode";
7950 assert (strcmp (insn->name, str) == 0);
7952 if (OPCODE_IS_MEMBER (insn,
7954 | (file_ase_mips16 ? INSN_MIPS16 : 0)
7955 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7956 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7962 if (insn->pinfo != INSN_MACRO)
7964 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7970 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7971 && strcmp (insn->name, insn[1].name) == 0)
7980 static char buf[100];
7982 _("opcode not supported on this processor: %s (%s)"),
7983 mips_cpu_info_from_arch (mips_opts.arch)->name,
7984 mips_cpu_info_from_isa (mips_opts.isa)->name);
7994 ip->insn_opcode = insn->match;
7996 for (args = insn->args;; ++args)
8000 s += strspn (s, " \t");
8004 case '\0': /* end of args */
8017 ip->insn_opcode |= lastregno << OP_SH_RS;
8021 ip->insn_opcode |= lastregno << OP_SH_RT;
8025 ip->insn_opcode |= lastregno << OP_SH_FT;
8029 ip->insn_opcode |= lastregno << OP_SH_FS;
8035 /* Handle optional base register.
8036 Either the base register is omitted or
8037 we must have a left paren. */
8038 /* This is dependent on the next operand specifier
8039 is a base register specification. */
8040 assert (args[1] == 'b' || args[1] == '5'
8041 || args[1] == '-' || args[1] == '4');
8045 case ')': /* these must match exactly */
8052 case '+': /* Opcode extension character. */
8055 case 'A': /* ins/ext position, becomes LSB. */
8064 my_getExpression (&imm_expr, s);
8065 check_absolute_expr (ip, &imm_expr);
8066 if ((unsigned long) imm_expr.X_add_number < limlo
8067 || (unsigned long) imm_expr.X_add_number > limhi)
8069 as_bad (_("Improper position (%lu)"),
8070 (unsigned long) imm_expr.X_add_number);
8071 imm_expr.X_add_number = limlo;
8073 lastpos = imm_expr.X_add_number;
8074 ip->insn_opcode |= (imm_expr.X_add_number
8075 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8076 imm_expr.X_op = O_absent;
8080 case 'B': /* ins size, becomes MSB. */
8089 my_getExpression (&imm_expr, s);
8090 check_absolute_expr (ip, &imm_expr);
8091 /* Check for negative input so that small negative numbers
8092 will not succeed incorrectly. The checks against
8093 (pos+size) transitively check "size" itself,
8094 assuming that "pos" is reasonable. */
8095 if ((long) imm_expr.X_add_number < 0
8096 || ((unsigned long) imm_expr.X_add_number
8098 || ((unsigned long) imm_expr.X_add_number
8101 as_bad (_("Improper insert size (%lu, position %lu)"),
8102 (unsigned long) imm_expr.X_add_number,
8103 (unsigned long) lastpos);
8104 imm_expr.X_add_number = limlo - lastpos;
8106 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8107 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8108 imm_expr.X_op = O_absent;
8112 case 'C': /* ext size, becomes MSBD. */
8125 my_getExpression (&imm_expr, s);
8126 check_absolute_expr (ip, &imm_expr);
8127 /* Check for negative input so that small negative numbers
8128 will not succeed incorrectly. The checks against
8129 (pos+size) transitively check "size" itself,
8130 assuming that "pos" is reasonable. */
8131 if ((long) imm_expr.X_add_number < 0
8132 || ((unsigned long) imm_expr.X_add_number
8134 || ((unsigned long) imm_expr.X_add_number
8137 as_bad (_("Improper extract size (%lu, position %lu)"),
8138 (unsigned long) imm_expr.X_add_number,
8139 (unsigned long) lastpos);
8140 imm_expr.X_add_number = limlo - lastpos;
8142 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8143 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8144 imm_expr.X_op = O_absent;
8149 /* +D is for disassembly only; never match. */
8153 /* "+I" is like "I", except that imm2_expr is used. */
8154 my_getExpression (&imm2_expr, s);
8155 if (imm2_expr.X_op != O_big
8156 && imm2_expr.X_op != O_constant)
8157 insn_error = _("absolute expression required");
8158 normalize_constant_expr (&imm2_expr);
8163 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8164 *args, insn->name, insn->args);
8165 /* Further processing is fruitless. */
8170 case '<': /* must be at least one digit */
8172 * According to the manual, if the shift amount is greater
8173 * than 31 or less than 0, then the shift amount should be
8174 * mod 32. In reality the mips assembler issues an error.
8175 * We issue a warning and mask out all but the low 5 bits.
8177 my_getExpression (&imm_expr, s);
8178 check_absolute_expr (ip, &imm_expr);
8179 if ((unsigned long) imm_expr.X_add_number > 31)
8181 as_warn (_("Improper shift amount (%lu)"),
8182 (unsigned long) imm_expr.X_add_number);
8183 imm_expr.X_add_number &= OP_MASK_SHAMT;
8185 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8186 imm_expr.X_op = O_absent;
8190 case '>': /* shift amount minus 32 */
8191 my_getExpression (&imm_expr, s);
8192 check_absolute_expr (ip, &imm_expr);
8193 if ((unsigned long) imm_expr.X_add_number < 32
8194 || (unsigned long) imm_expr.X_add_number > 63)
8196 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8197 imm_expr.X_op = O_absent;
8201 case 'k': /* cache code */
8202 case 'h': /* prefx code */
8203 my_getExpression (&imm_expr, s);
8204 check_absolute_expr (ip, &imm_expr);
8205 if ((unsigned long) imm_expr.X_add_number > 31)
8207 as_warn (_("Invalid value for `%s' (%lu)"),
8209 (unsigned long) imm_expr.X_add_number);
8210 imm_expr.X_add_number &= 0x1f;
8213 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8215 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8216 imm_expr.X_op = O_absent;
8220 case 'c': /* break code */
8221 my_getExpression (&imm_expr, s);
8222 check_absolute_expr (ip, &imm_expr);
8223 if ((unsigned long) imm_expr.X_add_number > 1023)
8225 as_warn (_("Illegal break code (%lu)"),
8226 (unsigned long) imm_expr.X_add_number);
8227 imm_expr.X_add_number &= OP_MASK_CODE;
8229 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8230 imm_expr.X_op = O_absent;
8234 case 'q': /* lower break code */
8235 my_getExpression (&imm_expr, s);
8236 check_absolute_expr (ip, &imm_expr);
8237 if ((unsigned long) imm_expr.X_add_number > 1023)
8239 as_warn (_("Illegal lower break code (%lu)"),
8240 (unsigned long) imm_expr.X_add_number);
8241 imm_expr.X_add_number &= OP_MASK_CODE2;
8243 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8244 imm_expr.X_op = O_absent;
8248 case 'B': /* 20-bit syscall/break code. */
8249 my_getExpression (&imm_expr, s);
8250 check_absolute_expr (ip, &imm_expr);
8251 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8252 as_warn (_("Illegal 20-bit code (%lu)"),
8253 (unsigned long) imm_expr.X_add_number);
8254 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8255 imm_expr.X_op = O_absent;
8259 case 'C': /* Coprocessor code */
8260 my_getExpression (&imm_expr, s);
8261 check_absolute_expr (ip, &imm_expr);
8262 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8264 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8265 (unsigned long) imm_expr.X_add_number);
8266 imm_expr.X_add_number &= ((1 << 25) - 1);
8268 ip->insn_opcode |= imm_expr.X_add_number;
8269 imm_expr.X_op = O_absent;
8273 case 'J': /* 19-bit wait code. */
8274 my_getExpression (&imm_expr, s);
8275 check_absolute_expr (ip, &imm_expr);
8276 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8277 as_warn (_("Illegal 19-bit code (%lu)"),
8278 (unsigned long) imm_expr.X_add_number);
8279 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8280 imm_expr.X_op = O_absent;
8284 case 'P': /* Performance register */
8285 my_getExpression (&imm_expr, s);
8286 check_absolute_expr (ip, &imm_expr);
8287 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8289 as_warn (_("Invalid performance register (%lu)"),
8290 (unsigned long) imm_expr.X_add_number);
8291 imm_expr.X_add_number &= OP_MASK_PERFREG;
8293 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8294 imm_expr.X_op = O_absent;
8298 case 'b': /* base register */
8299 case 'd': /* destination register */
8300 case 's': /* source register */
8301 case 't': /* target register */
8302 case 'r': /* both target and source */
8303 case 'v': /* both dest and source */
8304 case 'w': /* both dest and target */
8305 case 'E': /* coprocessor target register */
8306 case 'G': /* coprocessor destination register */
8307 case 'K': /* 'rdhwr' destination register */
8308 case 'x': /* ignore register name */
8309 case 'z': /* must be zero register */
8310 case 'U': /* destination register (clo/clz). */
8325 while (ISDIGIT (*s));
8327 as_bad (_("Invalid register number (%d)"), regno);
8329 else if (*args == 'E' || *args == 'G' || *args == 'K')
8333 if (s[1] == 'r' && s[2] == 'a')
8338 else if (s[1] == 'f' && s[2] == 'p')
8343 else if (s[1] == 's' && s[2] == 'p')
8348 else if (s[1] == 'g' && s[2] == 'p')
8353 else if (s[1] == 'a' && s[2] == 't')
8358 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8363 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8368 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8373 else if (itbl_have_entries)
8378 p = s + 1; /* advance past '$' */
8379 n = itbl_get_field (&p); /* n is name */
8381 /* See if this is a register defined in an
8383 if (itbl_get_reg_val (n, &r))
8385 /* Get_field advances to the start of
8386 the next field, so we need to back
8387 rack to the end of the last field. */
8391 s = strchr (s, '\0');
8405 as_warn (_("Used $at without \".set noat\""));
8411 if (c == 'r' || c == 'v' || c == 'w')
8418 /* 'z' only matches $0. */
8419 if (c == 'z' && regno != 0)
8422 /* Now that we have assembled one operand, we use the args string
8423 * to figure out where it goes in the instruction. */
8430 ip->insn_opcode |= regno << OP_SH_RS;
8435 ip->insn_opcode |= regno << OP_SH_RD;
8438 ip->insn_opcode |= regno << OP_SH_RD;
8439 ip->insn_opcode |= regno << OP_SH_RT;
8444 ip->insn_opcode |= regno << OP_SH_RT;
8447 /* This case exists because on the r3000 trunc
8448 expands into a macro which requires a gp
8449 register. On the r6000 or r4000 it is
8450 assembled into a single instruction which
8451 ignores the register. Thus the insn version
8452 is MIPS_ISA2 and uses 'x', and the macro
8453 version is MIPS_ISA1 and uses 't'. */
8456 /* This case is for the div instruction, which
8457 acts differently if the destination argument
8458 is $0. This only matches $0, and is checked
8459 outside the switch. */
8462 /* Itbl operand; not yet implemented. FIXME ?? */
8464 /* What about all other operands like 'i', which
8465 can be specified in the opcode table? */
8475 ip->insn_opcode |= lastregno << OP_SH_RS;
8478 ip->insn_opcode |= lastregno << OP_SH_RT;
8483 case 'O': /* MDMX alignment immediate constant. */
8484 my_getExpression (&imm_expr, s);
8485 check_absolute_expr (ip, &imm_expr);
8486 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8488 as_warn ("Improper align amount (%ld), using low bits",
8489 (long) imm_expr.X_add_number);
8490 imm_expr.X_add_number &= OP_MASK_ALN;
8492 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8493 imm_expr.X_op = O_absent;
8497 case 'Q': /* MDMX vector, element sel, or const. */
8500 /* MDMX Immediate. */
8501 my_getExpression (&imm_expr, s);
8502 check_absolute_expr (ip, &imm_expr);
8503 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8505 as_warn (_("Invalid MDMX Immediate (%ld)"),
8506 (long) imm_expr.X_add_number);
8507 imm_expr.X_add_number &= OP_MASK_FT;
8509 imm_expr.X_add_number &= OP_MASK_FT;
8510 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8511 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8513 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8514 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8515 imm_expr.X_op = O_absent;
8519 /* Not MDMX Immediate. Fall through. */
8520 case 'X': /* MDMX destination register. */
8521 case 'Y': /* MDMX source register. */
8522 case 'Z': /* MDMX target register. */
8524 case 'D': /* floating point destination register */
8525 case 'S': /* floating point source register */
8526 case 'T': /* floating point target register */
8527 case 'R': /* floating point source register */
8531 /* Accept $fN for FP and MDMX register numbers, and in
8532 addition accept $vN for MDMX register numbers. */
8533 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8534 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8545 while (ISDIGIT (*s));
8548 as_bad (_("Invalid float register number (%d)"), regno);
8550 if ((regno & 1) != 0
8552 && ! (strcmp (str, "mtc1") == 0
8553 || strcmp (str, "mfc1") == 0
8554 || strcmp (str, "lwc1") == 0
8555 || strcmp (str, "swc1") == 0
8556 || strcmp (str, "l.s") == 0
8557 || strcmp (str, "s.s") == 0))
8558 as_warn (_("Float register should be even, was %d"),
8566 if (c == 'V' || c == 'W')
8577 ip->insn_opcode |= regno << OP_SH_FD;
8582 ip->insn_opcode |= regno << OP_SH_FS;
8585 /* This is like 'Z', but also needs to fix the MDMX
8586 vector/scalar select bits. Note that the
8587 scalar immediate case is handled above. */
8590 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8591 int max_el = (is_qh ? 3 : 7);
8593 my_getExpression(&imm_expr, s);
8594 check_absolute_expr (ip, &imm_expr);
8596 if (imm_expr.X_add_number > max_el)
8597 as_bad(_("Bad element selector %ld"),
8598 (long) imm_expr.X_add_number);
8599 imm_expr.X_add_number &= max_el;
8600 ip->insn_opcode |= (imm_expr.X_add_number
8604 as_warn(_("Expecting ']' found '%s'"), s);
8610 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8611 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8614 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8621 ip->insn_opcode |= regno << OP_SH_FT;
8624 ip->insn_opcode |= regno << OP_SH_FR;
8634 ip->insn_opcode |= lastregno << OP_SH_FS;
8637 ip->insn_opcode |= lastregno << OP_SH_FT;
8643 my_getExpression (&imm_expr, s);
8644 if (imm_expr.X_op != O_big
8645 && imm_expr.X_op != O_constant)
8646 insn_error = _("absolute expression required");
8647 normalize_constant_expr (&imm_expr);
8652 my_getExpression (&offset_expr, s);
8653 *imm_reloc = BFD_RELOC_32;
8666 unsigned char temp[8];
8668 unsigned int length;
8673 /* These only appear as the last operand in an
8674 instruction, and every instruction that accepts
8675 them in any variant accepts them in all variants.
8676 This means we don't have to worry about backing out
8677 any changes if the instruction does not match.
8679 The difference between them is the size of the
8680 floating point constant and where it goes. For 'F'
8681 and 'L' the constant is 64 bits; for 'f' and 'l' it
8682 is 32 bits. Where the constant is placed is based
8683 on how the MIPS assembler does things:
8686 f -- immediate value
8689 The .lit4 and .lit8 sections are only used if
8690 permitted by the -G argument.
8692 The code below needs to know whether the target register
8693 is 32 or 64 bits wide. It relies on the fact 'f' and
8694 'F' are used with GPR-based instructions and 'l' and
8695 'L' are used with FPR-based instructions. */
8697 f64 = *args == 'F' || *args == 'L';
8698 using_gprs = *args == 'F' || *args == 'f';
8700 save_in = input_line_pointer;
8701 input_line_pointer = s;
8702 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8704 s = input_line_pointer;
8705 input_line_pointer = save_in;
8706 if (err != NULL && *err != '\0')
8708 as_bad (_("Bad floating point constant: %s"), err);
8709 memset (temp, '\0', sizeof temp);
8710 length = f64 ? 8 : 4;
8713 assert (length == (unsigned) (f64 ? 8 : 4));
8717 && (g_switch_value < 4
8718 || (temp[0] == 0 && temp[1] == 0)
8719 || (temp[2] == 0 && temp[3] == 0))))
8721 imm_expr.X_op = O_constant;
8722 if (! target_big_endian)
8723 imm_expr.X_add_number = bfd_getl32 (temp);
8725 imm_expr.X_add_number = bfd_getb32 (temp);
8728 && ! mips_disable_float_construction
8729 /* Constants can only be constructed in GPRs and
8730 copied to FPRs if the GPRs are at least as wide
8731 as the FPRs. Force the constant into memory if
8732 we are using 64-bit FPRs but the GPRs are only
8735 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8736 && ((temp[0] == 0 && temp[1] == 0)
8737 || (temp[2] == 0 && temp[3] == 0))
8738 && ((temp[4] == 0 && temp[5] == 0)
8739 || (temp[6] == 0 && temp[7] == 0)))
8741 /* The value is simple enough to load with a couple of
8742 instructions. If using 32-bit registers, set
8743 imm_expr to the high order 32 bits and offset_expr to
8744 the low order 32 bits. Otherwise, set imm_expr to
8745 the entire 64 bit constant. */
8746 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8748 imm_expr.X_op = O_constant;
8749 offset_expr.X_op = O_constant;
8750 if (! target_big_endian)
8752 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8753 offset_expr.X_add_number = bfd_getl32 (temp);
8757 imm_expr.X_add_number = bfd_getb32 (temp);
8758 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8760 if (offset_expr.X_add_number == 0)
8761 offset_expr.X_op = O_absent;
8763 else if (sizeof (imm_expr.X_add_number) > 4)
8765 imm_expr.X_op = O_constant;
8766 if (! target_big_endian)
8767 imm_expr.X_add_number = bfd_getl64 (temp);
8769 imm_expr.X_add_number = bfd_getb64 (temp);
8773 imm_expr.X_op = O_big;
8774 imm_expr.X_add_number = 4;
8775 if (! target_big_endian)
8777 generic_bignum[0] = bfd_getl16 (temp);
8778 generic_bignum[1] = bfd_getl16 (temp + 2);
8779 generic_bignum[2] = bfd_getl16 (temp + 4);
8780 generic_bignum[3] = bfd_getl16 (temp + 6);
8784 generic_bignum[0] = bfd_getb16 (temp + 6);
8785 generic_bignum[1] = bfd_getb16 (temp + 4);
8786 generic_bignum[2] = bfd_getb16 (temp + 2);
8787 generic_bignum[3] = bfd_getb16 (temp);
8793 const char *newname;
8796 /* Switch to the right section. */
8798 subseg = now_subseg;
8801 default: /* unused default case avoids warnings. */
8803 newname = RDATA_SECTION_NAME;
8804 if (g_switch_value >= 8)
8808 newname = RDATA_SECTION_NAME;
8811 assert (g_switch_value >= 4);
8815 new_seg = subseg_new (newname, (subsegT) 0);
8816 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8817 bfd_set_section_flags (stdoutput, new_seg,
8822 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8823 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8824 && strcmp (TARGET_OS, "elf") != 0)
8825 record_alignment (new_seg, 4);
8827 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8829 as_bad (_("Can't use floating point insn in this section"));
8831 /* Set the argument to the current address in the
8833 offset_expr.X_op = O_symbol;
8834 offset_expr.X_add_symbol =
8835 symbol_new ("L0\001", now_seg,
8836 (valueT) frag_now_fix (), frag_now);
8837 offset_expr.X_add_number = 0;
8839 /* Put the floating point number into the section. */
8840 p = frag_more ((int) length);
8841 memcpy (p, temp, length);
8843 /* Switch back to the original section. */
8844 subseg_set (seg, subseg);
8849 case 'i': /* 16 bit unsigned immediate */
8850 case 'j': /* 16 bit signed immediate */
8851 *imm_reloc = BFD_RELOC_LO16;
8852 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
8855 offsetT minval, maxval;
8857 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
8858 && strcmp (insn->name, insn[1].name) == 0);
8860 /* If the expression was written as an unsigned number,
8861 only treat it as signed if there are no more
8865 && sizeof (imm_expr.X_add_number) <= 4
8866 && imm_expr.X_op == O_constant
8867 && imm_expr.X_add_number < 0
8868 && imm_expr.X_unsigned
8872 /* For compatibility with older assemblers, we accept
8873 0x8000-0xffff as signed 16-bit numbers when only
8874 signed numbers are allowed. */
8876 minval = 0, maxval = 0xffff;
8878 minval = -0x8000, maxval = 0x7fff;
8880 minval = -0x8000, maxval = 0xffff;
8882 if (imm_expr.X_op != O_constant
8883 || imm_expr.X_add_number < minval
8884 || imm_expr.X_add_number > maxval)
8888 if (imm_expr.X_op == O_constant
8889 || imm_expr.X_op == O_big)
8890 as_bad (_("expression out of range"));
8896 case 'o': /* 16 bit offset */
8897 /* Check whether there is only a single bracketed expression
8898 left. If so, it must be the base register and the
8899 constant must be zero. */
8900 if (*s == '(' && strchr (s + 1, '(') == 0)
8902 offset_expr.X_op = O_constant;
8903 offset_expr.X_add_number = 0;
8907 /* If this value won't fit into a 16 bit offset, then go
8908 find a macro that will generate the 32 bit offset
8910 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
8911 && (offset_expr.X_op != O_constant
8912 || offset_expr.X_add_number >= 0x8000
8913 || offset_expr.X_add_number < -0x8000))
8919 case 'p': /* pc relative offset */
8920 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8921 my_getExpression (&offset_expr, s);
8925 case 'u': /* upper 16 bits */
8926 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
8927 && imm_expr.X_op == O_constant
8928 && (imm_expr.X_add_number < 0
8929 || imm_expr.X_add_number >= 0x10000))
8930 as_bad (_("lui expression not in range 0..65535"));
8934 case 'a': /* 26 bit address */
8935 my_getExpression (&offset_expr, s);
8937 *offset_reloc = BFD_RELOC_MIPS_JMP;
8940 case 'N': /* 3 bit branch condition code */
8941 case 'M': /* 3 bit compare condition code */
8942 if (strncmp (s, "$fcc", 4) != 0)
8952 while (ISDIGIT (*s));
8954 as_bad (_("Invalid condition code register $fcc%d"), regno);
8955 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
8956 || strcmp(str + strlen(str) - 5, "any2f") == 0
8957 || strcmp(str + strlen(str) - 5, "any2t") == 0)
8958 && (regno & 1) != 0)
8959 as_warn(_("Condition code register should be even for %s, was %d"),
8961 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
8962 || strcmp(str + strlen(str) - 5, "any4t") == 0)
8963 && (regno & 3) != 0)
8964 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8967 ip->insn_opcode |= regno << OP_SH_BCC;
8969 ip->insn_opcode |= regno << OP_SH_CCC;
8973 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8984 while (ISDIGIT (*s));
8987 c = 8; /* Invalid sel value. */
8990 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8991 ip->insn_opcode |= c;
8995 /* Must be at least one digit. */
8996 my_getExpression (&imm_expr, s);
8997 check_absolute_expr (ip, &imm_expr);
8999 if ((unsigned long) imm_expr.X_add_number
9000 > (unsigned long) OP_MASK_VECBYTE)
9002 as_bad (_("bad byte vector index (%ld)"),
9003 (long) imm_expr.X_add_number);
9004 imm_expr.X_add_number = 0;
9007 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9008 imm_expr.X_op = O_absent;
9013 my_getExpression (&imm_expr, s);
9014 check_absolute_expr (ip, &imm_expr);
9016 if ((unsigned long) imm_expr.X_add_number
9017 > (unsigned long) OP_MASK_VECALIGN)
9019 as_bad (_("bad byte vector index (%ld)"),
9020 (long) imm_expr.X_add_number);
9021 imm_expr.X_add_number = 0;
9024 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9025 imm_expr.X_op = O_absent;
9030 as_bad (_("bad char = '%c'\n"), *args);
9035 /* Args don't match. */
9036 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9037 !strcmp (insn->name, insn[1].name))
9041 insn_error = _("illegal operands");
9046 insn_error = _("illegal operands");
9051 /* This routine assembles an instruction into its binary format when
9052 assembling for the mips16. As a side effect, it sets one of the
9053 global variables imm_reloc or offset_reloc to the type of
9054 relocation to do if one of the operands is an address expression.
9055 It also sets mips16_small and mips16_ext if the user explicitly
9056 requested a small or extended instruction. */
9059 mips16_ip (char *str, struct mips_cl_insn *ip)
9063 struct mips_opcode *insn;
9066 unsigned int lastregno = 0;
9071 mips16_small = FALSE;
9074 for (s = str; ISLOWER (*s); ++s)
9086 if (s[1] == 't' && s[2] == ' ')
9089 mips16_small = TRUE;
9093 else if (s[1] == 'e' && s[2] == ' ')
9102 insn_error = _("unknown opcode");
9106 if (mips_opts.noautoextend && ! mips16_ext)
9107 mips16_small = TRUE;
9109 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9111 insn_error = _("unrecognized opcode");
9118 assert (strcmp (insn->name, str) == 0);
9121 ip->insn_opcode = insn->match;
9122 ip->use_extend = FALSE;
9123 imm_expr.X_op = O_absent;
9124 imm_reloc[0] = BFD_RELOC_UNUSED;
9125 imm_reloc[1] = BFD_RELOC_UNUSED;
9126 imm_reloc[2] = BFD_RELOC_UNUSED;
9127 imm2_expr.X_op = O_absent;
9128 offset_expr.X_op = O_absent;
9129 offset_reloc[0] = BFD_RELOC_UNUSED;
9130 offset_reloc[1] = BFD_RELOC_UNUSED;
9131 offset_reloc[2] = BFD_RELOC_UNUSED;
9132 for (args = insn->args; 1; ++args)
9139 /* In this switch statement we call break if we did not find
9140 a match, continue if we did find a match, or return if we
9149 /* Stuff the immediate value in now, if we can. */
9150 if (imm_expr.X_op == O_constant
9151 && *imm_reloc > BFD_RELOC_UNUSED
9152 && insn->pinfo != INSN_MACRO)
9154 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9155 imm_expr.X_add_number, TRUE, mips16_small,
9156 mips16_ext, &ip->insn_opcode,
9157 &ip->use_extend, &ip->extend);
9158 imm_expr.X_op = O_absent;
9159 *imm_reloc = BFD_RELOC_UNUSED;
9173 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9176 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9192 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9194 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9221 while (ISDIGIT (*s));
9224 as_bad (_("invalid register number (%d)"), regno);
9230 if (s[1] == 'r' && s[2] == 'a')
9235 else if (s[1] == 'f' && s[2] == 'p')
9240 else if (s[1] == 's' && s[2] == 'p')
9245 else if (s[1] == 'g' && s[2] == 'p')
9250 else if (s[1] == 'a' && s[2] == 't')
9255 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9260 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9265 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9278 if (c == 'v' || c == 'w')
9280 regno = mips16_to_32_reg_map[lastregno];
9294 regno = mips32_to_16_reg_map[regno];
9299 regno = ILLEGAL_REG;
9304 regno = ILLEGAL_REG;
9309 regno = ILLEGAL_REG;
9314 if (regno == AT && ! mips_opts.noat)
9315 as_warn (_("used $at without \".set noat\""));
9322 if (regno == ILLEGAL_REG)
9329 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9333 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9336 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9339 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9345 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9348 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9349 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9359 if (strncmp (s, "$pc", 3) == 0)
9383 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9385 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9386 and generate the appropriate reloc. If the text
9387 inside %gprel is not a symbol name with an
9388 optional offset, then we generate a normal reloc
9389 and will probably fail later. */
9390 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9391 if (imm_expr.X_op == O_symbol)
9394 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9396 ip->use_extend = TRUE;
9403 /* Just pick up a normal expression. */
9404 my_getExpression (&imm_expr, s);
9407 if (imm_expr.X_op == O_register)
9409 /* What we thought was an expression turned out to
9412 if (s[0] == '(' && args[1] == '(')
9414 /* It looks like the expression was omitted
9415 before a register indirection, which means
9416 that the expression is implicitly zero. We
9417 still set up imm_expr, so that we handle
9418 explicit extensions correctly. */
9419 imm_expr.X_op = O_constant;
9420 imm_expr.X_add_number = 0;
9421 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9428 /* We need to relax this instruction. */
9429 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9438 /* We use offset_reloc rather than imm_reloc for the PC
9439 relative operands. This lets macros with both
9440 immediate and address operands work correctly. */
9441 my_getExpression (&offset_expr, s);
9443 if (offset_expr.X_op == O_register)
9446 /* We need to relax this instruction. */
9447 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9451 case '6': /* break code */
9452 my_getExpression (&imm_expr, s);
9453 check_absolute_expr (ip, &imm_expr);
9454 if ((unsigned long) imm_expr.X_add_number > 63)
9456 as_warn (_("Invalid value for `%s' (%lu)"),
9458 (unsigned long) imm_expr.X_add_number);
9459 imm_expr.X_add_number &= 0x3f;
9461 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9462 imm_expr.X_op = O_absent;
9466 case 'a': /* 26 bit address */
9467 my_getExpression (&offset_expr, s);
9469 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9470 ip->insn_opcode <<= 16;
9473 case 'l': /* register list for entry macro */
9474 case 'L': /* register list for exit macro */
9484 int freg, reg1, reg2;
9486 while (*s == ' ' || *s == ',')
9490 as_bad (_("can't parse register list"));
9502 while (ISDIGIT (*s))
9524 as_bad (_("invalid register list"));
9529 while (ISDIGIT (*s))
9536 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9541 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9546 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9547 mask |= (reg2 - 3) << 3;
9548 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9549 mask |= (reg2 - 15) << 1;
9550 else if (reg1 == RA && reg2 == RA)
9554 as_bad (_("invalid register list"));
9558 /* The mask is filled in in the opcode table for the
9559 benefit of the disassembler. We remove it before
9560 applying the actual mask. */
9561 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9562 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9566 case 'e': /* extend code */
9567 my_getExpression (&imm_expr, s);
9568 check_absolute_expr (ip, &imm_expr);
9569 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9571 as_warn (_("Invalid value for `%s' (%lu)"),
9573 (unsigned long) imm_expr.X_add_number);
9574 imm_expr.X_add_number &= 0x7ff;
9576 ip->insn_opcode |= imm_expr.X_add_number;
9577 imm_expr.X_op = O_absent;
9587 /* Args don't match. */
9588 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9589 strcmp (insn->name, insn[1].name) == 0)
9596 insn_error = _("illegal operands");
9602 /* This structure holds information we know about a mips16 immediate
9605 struct mips16_immed_operand
9607 /* The type code used in the argument string in the opcode table. */
9609 /* The number of bits in the short form of the opcode. */
9611 /* The number of bits in the extended form of the opcode. */
9613 /* The amount by which the short form is shifted when it is used;
9614 for example, the sw instruction has a shift count of 2. */
9616 /* The amount by which the short form is shifted when it is stored
9617 into the instruction code. */
9619 /* Non-zero if the short form is unsigned. */
9621 /* Non-zero if the extended form is unsigned. */
9623 /* Non-zero if the value is PC relative. */
9627 /* The mips16 immediate operand types. */
9629 static const struct mips16_immed_operand mips16_immed_operands[] =
9631 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9632 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9633 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9634 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9635 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9636 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9637 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9638 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9639 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9640 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9641 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9642 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9643 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9644 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9645 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9646 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9647 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9648 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9649 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9650 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9651 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9654 #define MIPS16_NUM_IMMED \
9655 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9657 /* Handle a mips16 instruction with an immediate value. This or's the
9658 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9659 whether an extended value is needed; if one is needed, it sets
9660 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9661 If SMALL is true, an unextended opcode was explicitly requested.
9662 If EXT is true, an extended opcode was explicitly requested. If
9663 WARN is true, warn if EXT does not match reality. */
9666 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9667 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9668 unsigned long *insn, bfd_boolean *use_extend,
9669 unsigned short *extend)
9671 register const struct mips16_immed_operand *op;
9672 int mintiny, maxtiny;
9673 bfd_boolean needext;
9675 op = mips16_immed_operands;
9676 while (op->type != type)
9679 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9684 if (type == '<' || type == '>' || type == '[' || type == ']')
9687 maxtiny = 1 << op->nbits;
9692 maxtiny = (1 << op->nbits) - 1;
9697 mintiny = - (1 << (op->nbits - 1));
9698 maxtiny = (1 << (op->nbits - 1)) - 1;
9701 /* Branch offsets have an implicit 0 in the lowest bit. */
9702 if (type == 'p' || type == 'q')
9705 if ((val & ((1 << op->shift) - 1)) != 0
9706 || val < (mintiny << op->shift)
9707 || val > (maxtiny << op->shift))
9712 if (warn && ext && ! needext)
9713 as_warn_where (file, line,
9714 _("extended operand requested but not required"));
9715 if (small && needext)
9716 as_bad_where (file, line, _("invalid unextended operand value"));
9718 if (small || (! ext && ! needext))
9722 *use_extend = FALSE;
9723 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9724 insnval <<= op->op_shift;
9729 long minext, maxext;
9735 maxext = (1 << op->extbits) - 1;
9739 minext = - (1 << (op->extbits - 1));
9740 maxext = (1 << (op->extbits - 1)) - 1;
9742 if (val < minext || val > maxext)
9743 as_bad_where (file, line,
9744 _("operand value out of range for instruction"));
9747 if (op->extbits == 16)
9749 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9752 else if (op->extbits == 15)
9754 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9759 extval = ((val & 0x1f) << 6) | (val & 0x20);
9763 *extend = (unsigned short) extval;
9768 static const struct percent_op_match
9771 bfd_reloc_code_real_type reloc;
9774 {"%lo", BFD_RELOC_LO16},
9776 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9777 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9778 {"%call16", BFD_RELOC_MIPS_CALL16},
9779 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9780 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9781 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9782 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9783 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9784 {"%got", BFD_RELOC_MIPS_GOT16},
9785 {"%gp_rel", BFD_RELOC_GPREL16},
9786 {"%half", BFD_RELOC_16},
9787 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9788 {"%higher", BFD_RELOC_MIPS_HIGHER},
9789 {"%neg", BFD_RELOC_MIPS_SUB},
9791 {"%hi", BFD_RELOC_HI16_S}
9795 /* Return true if *STR points to a relocation operator. When returning true,
9796 move *STR over the operator and store its relocation code in *RELOC.
9797 Leave both *STR and *RELOC alone when returning false. */
9800 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9804 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9805 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9807 *str += strlen (percent_op[i].str);
9808 *reloc = percent_op[i].reloc;
9810 /* Check whether the output BFD supports this relocation.
9811 If not, issue an error and fall back on something safe. */
9812 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9814 as_bad ("relocation %s isn't supported by the current ABI",
9816 *reloc = BFD_RELOC_LO16;
9824 /* Parse string STR as a 16-bit relocatable operand. Store the
9825 expression in *EP and the relocations in the array starting
9826 at RELOC. Return the number of relocation operators used.
9828 On exit, EXPR_END points to the first character after the expression.
9829 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
9832 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
9835 bfd_reloc_code_real_type reversed_reloc[3];
9836 size_t reloc_index, i;
9837 int crux_depth, str_depth;
9840 /* Search for the start of the main expression, recoding relocations
9841 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9842 of the main expression and with CRUX_DEPTH containing the number
9843 of open brackets at that point. */
9850 crux_depth = str_depth;
9852 /* Skip over whitespace and brackets, keeping count of the number
9854 while (*str == ' ' || *str == '\t' || *str == '(')
9859 && reloc_index < (HAVE_NEWABI ? 3 : 1)
9860 && parse_relocation (&str, &reversed_reloc[reloc_index]));
9862 my_getExpression (ep, crux);
9865 /* Match every open bracket. */
9866 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
9871 as_bad ("unclosed '('");
9875 if (reloc_index == 0)
9876 reloc[0] = BFD_RELOC_LO16;
9879 prev_reloc_op_frag = frag_now;
9880 for (i = 0; i < reloc_index; i++)
9881 reloc[i] = reversed_reloc[reloc_index - 1 - i];
9888 my_getExpression (expressionS *ep, char *str)
9893 save_in = input_line_pointer;
9894 input_line_pointer = str;
9896 expr_end = input_line_pointer;
9897 input_line_pointer = save_in;
9899 /* If we are in mips16 mode, and this is an expression based on `.',
9900 then we bump the value of the symbol by 1 since that is how other
9901 text symbols are handled. We don't bother to handle complex
9902 expressions, just `.' plus or minus a constant. */
9903 if (mips_opts.mips16
9904 && ep->X_op == O_symbol
9905 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9906 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9907 && symbol_get_frag (ep->X_add_symbol) == frag_now
9908 && symbol_constant_p (ep->X_add_symbol)
9909 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9910 S_SET_VALUE (ep->X_add_symbol, val + 1);
9913 /* Turn a string in input_line_pointer into a floating point constant
9914 of type TYPE, and store the appropriate bytes in *LITP. The number
9915 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9916 returned, or NULL on OK. */
9919 md_atof (int type, char *litP, int *sizeP)
9922 LITTLENUM_TYPE words[4];
9938 return _("bad call to md_atof");
9941 t = atof_ieee (input_line_pointer, type, words);
9943 input_line_pointer = t;
9947 if (! target_big_endian)
9949 for (i = prec - 1; i >= 0; i--)
9951 md_number_to_chars (litP, words[i], 2);
9957 for (i = 0; i < prec; i++)
9959 md_number_to_chars (litP, words[i], 2);
9968 md_number_to_chars (char *buf, valueT val, int n)
9970 if (target_big_endian)
9971 number_to_chars_bigendian (buf, val, n);
9973 number_to_chars_littleendian (buf, val, n);
9977 static int support_64bit_objects(void)
9979 const char **list, **l;
9982 list = bfd_target_list ();
9983 for (l = list; *l != NULL; l++)
9985 /* This is traditional mips */
9986 if (strcmp (*l, "elf64-tradbigmips") == 0
9987 || strcmp (*l, "elf64-tradlittlemips") == 0)
9989 if (strcmp (*l, "elf64-bigmips") == 0
9990 || strcmp (*l, "elf64-littlemips") == 0)
9997 #endif /* OBJ_ELF */
9999 const char *md_shortopts = "O::g::G:";
10001 struct option md_longopts[] =
10003 /* Options which specify architecture. */
10004 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10005 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10006 {"march", required_argument, NULL, OPTION_MARCH},
10007 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10008 {"mtune", required_argument, NULL, OPTION_MTUNE},
10009 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10010 {"mips0", no_argument, NULL, OPTION_MIPS1},
10011 {"mips1", no_argument, NULL, OPTION_MIPS1},
10012 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10013 {"mips2", no_argument, NULL, OPTION_MIPS2},
10014 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10015 {"mips3", no_argument, NULL, OPTION_MIPS3},
10016 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10017 {"mips4", no_argument, NULL, OPTION_MIPS4},
10018 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10019 {"mips5", no_argument, NULL, OPTION_MIPS5},
10020 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10021 {"mips32", no_argument, NULL, OPTION_MIPS32},
10022 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10023 {"mips64", no_argument, NULL, OPTION_MIPS64},
10024 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10025 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10026 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10027 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10029 /* Options which specify Application Specific Extensions (ASEs). */
10030 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10031 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10032 {"mips16", no_argument, NULL, OPTION_MIPS16},
10033 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10034 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10035 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10036 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10037 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10038 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10039 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10040 {"mdmx", no_argument, NULL, OPTION_MDMX},
10041 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10042 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10044 /* Old-style architecture options. Don't add more of these. */
10045 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10046 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10047 {"m4650", no_argument, NULL, OPTION_M4650},
10048 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10049 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10050 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10051 {"m4010", no_argument, NULL, OPTION_M4010},
10052 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10053 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10054 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10055 {"m4100", no_argument, NULL, OPTION_M4100},
10056 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10057 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10058 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10059 {"m3900", no_argument, NULL, OPTION_M3900},
10060 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10061 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10063 /* Options which enable bug fixes. */
10064 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10065 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10066 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10067 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10068 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10069 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10070 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10071 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10072 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10073 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10075 /* Miscellaneous options. */
10076 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10077 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10078 {"trap", no_argument, NULL, OPTION_TRAP},
10079 {"no-break", no_argument, NULL, OPTION_TRAP},
10080 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10081 {"break", no_argument, NULL, OPTION_BREAK},
10082 {"no-trap", no_argument, NULL, OPTION_BREAK},
10083 #define OPTION_EB (OPTION_MISC_BASE + 2)
10084 {"EB", no_argument, NULL, OPTION_EB},
10085 #define OPTION_EL (OPTION_MISC_BASE + 3)
10086 {"EL", no_argument, NULL, OPTION_EL},
10087 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10088 {"mfp32", no_argument, NULL, OPTION_FP32},
10089 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10090 {"mgp32", no_argument, NULL, OPTION_GP32},
10091 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10092 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10093 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10094 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10095 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10096 {"mfp64", no_argument, NULL, OPTION_FP64},
10097 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10098 {"mgp64", no_argument, NULL, OPTION_GP64},
10099 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10100 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10101 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10102 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10104 /* ELF-specific options. */
10106 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10107 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10108 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10109 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10110 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10111 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10112 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10113 {"xgot", no_argument, NULL, OPTION_XGOT},
10114 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10115 {"mabi", required_argument, NULL, OPTION_MABI},
10116 #define OPTION_32 (OPTION_ELF_BASE + 4)
10117 {"32", no_argument, NULL, OPTION_32},
10118 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10119 {"n32", no_argument, NULL, OPTION_N32},
10120 #define OPTION_64 (OPTION_ELF_BASE + 6)
10121 {"64", no_argument, NULL, OPTION_64},
10122 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10123 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10124 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10125 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10126 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10127 {"mpdr", no_argument, NULL, OPTION_PDR},
10128 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10129 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10130 #endif /* OBJ_ELF */
10132 {NULL, no_argument, NULL, 0}
10134 size_t md_longopts_size = sizeof (md_longopts);
10136 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10137 NEW_VALUE. Warn if another value was already specified. Note:
10138 we have to defer parsing the -march and -mtune arguments in order
10139 to handle 'from-abi' correctly, since the ABI might be specified
10140 in a later argument. */
10143 mips_set_option_string (const char **string_ptr, const char *new_value)
10145 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10146 as_warn (_("A different %s was already specified, is now %s"),
10147 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10150 *string_ptr = new_value;
10154 md_parse_option (int c, char *arg)
10158 case OPTION_CONSTRUCT_FLOATS:
10159 mips_disable_float_construction = 0;
10162 case OPTION_NO_CONSTRUCT_FLOATS:
10163 mips_disable_float_construction = 1;
10175 target_big_endian = 1;
10179 target_big_endian = 0;
10183 if (arg && arg[1] == '0')
10193 mips_debug = atoi (arg);
10194 /* When the MIPS assembler sees -g or -g2, it does not do
10195 optimizations which limit full symbolic debugging. We take
10196 that to be equivalent to -O0. */
10197 if (mips_debug == 2)
10202 file_mips_isa = ISA_MIPS1;
10206 file_mips_isa = ISA_MIPS2;
10210 file_mips_isa = ISA_MIPS3;
10214 file_mips_isa = ISA_MIPS4;
10218 file_mips_isa = ISA_MIPS5;
10221 case OPTION_MIPS32:
10222 file_mips_isa = ISA_MIPS32;
10225 case OPTION_MIPS32R2:
10226 file_mips_isa = ISA_MIPS32R2;
10229 case OPTION_MIPS64R2:
10230 file_mips_isa = ISA_MIPS64R2;
10233 case OPTION_MIPS64:
10234 file_mips_isa = ISA_MIPS64;
10238 mips_set_option_string (&mips_tune_string, arg);
10242 mips_set_option_string (&mips_arch_string, arg);
10246 mips_set_option_string (&mips_arch_string, "4650");
10247 mips_set_option_string (&mips_tune_string, "4650");
10250 case OPTION_NO_M4650:
10254 mips_set_option_string (&mips_arch_string, "4010");
10255 mips_set_option_string (&mips_tune_string, "4010");
10258 case OPTION_NO_M4010:
10262 mips_set_option_string (&mips_arch_string, "4100");
10263 mips_set_option_string (&mips_tune_string, "4100");
10266 case OPTION_NO_M4100:
10270 mips_set_option_string (&mips_arch_string, "3900");
10271 mips_set_option_string (&mips_tune_string, "3900");
10274 case OPTION_NO_M3900:
10278 mips_opts.ase_mdmx = 1;
10281 case OPTION_NO_MDMX:
10282 mips_opts.ase_mdmx = 0;
10285 case OPTION_MIPS16:
10286 mips_opts.mips16 = 1;
10287 mips_no_prev_insn (FALSE);
10290 case OPTION_NO_MIPS16:
10291 mips_opts.mips16 = 0;
10292 mips_no_prev_insn (FALSE);
10295 case OPTION_MIPS3D:
10296 mips_opts.ase_mips3d = 1;
10299 case OPTION_NO_MIPS3D:
10300 mips_opts.ase_mips3d = 0;
10303 case OPTION_FIX_VR4120:
10304 mips_fix_vr4120 = 1;
10307 case OPTION_NO_FIX_VR4120:
10308 mips_fix_vr4120 = 0;
10311 case OPTION_RELAX_BRANCH:
10312 mips_relax_branch = 1;
10315 case OPTION_NO_RELAX_BRANCH:
10316 mips_relax_branch = 0;
10320 /* When generating ELF code, we permit -KPIC and -call_shared to
10321 select SVR4_PIC, and -non_shared to select no PIC. This is
10322 intended to be compatible with Irix 5. */
10323 case OPTION_CALL_SHARED:
10324 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10326 as_bad (_("-call_shared is supported only for ELF format"));
10329 mips_pic = SVR4_PIC;
10330 mips_abicalls = TRUE;
10331 if (g_switch_seen && g_switch_value != 0)
10333 as_bad (_("-G may not be used with SVR4 PIC code"));
10336 g_switch_value = 0;
10339 case OPTION_NON_SHARED:
10340 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10342 as_bad (_("-non_shared is supported only for ELF format"));
10346 mips_abicalls = FALSE;
10349 /* The -xgot option tells the assembler to use 32 offsets when
10350 accessing the got in SVR4_PIC mode. It is for Irix
10355 #endif /* OBJ_ELF */
10358 if (mips_pic == SVR4_PIC)
10360 as_bad (_("-G may not be used with SVR4 PIC code"));
10364 g_switch_value = atoi (arg);
10369 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10372 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10374 as_bad (_("-32 is supported for ELF format only"));
10377 mips_abi = O32_ABI;
10381 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10383 as_bad (_("-n32 is supported for ELF format only"));
10386 mips_abi = N32_ABI;
10390 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10392 as_bad (_("-64 is supported for ELF format only"));
10395 mips_abi = N64_ABI;
10396 if (! support_64bit_objects())
10397 as_fatal (_("No compiled in support for 64 bit object file format"));
10399 #endif /* OBJ_ELF */
10402 file_mips_gp32 = 1;
10406 file_mips_gp32 = 0;
10410 file_mips_fp32 = 1;
10414 file_mips_fp32 = 0;
10419 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10421 as_bad (_("-mabi is supported for ELF format only"));
10424 if (strcmp (arg, "32") == 0)
10425 mips_abi = O32_ABI;
10426 else if (strcmp (arg, "o64") == 0)
10427 mips_abi = O64_ABI;
10428 else if (strcmp (arg, "n32") == 0)
10429 mips_abi = N32_ABI;
10430 else if (strcmp (arg, "64") == 0)
10432 mips_abi = N64_ABI;
10433 if (! support_64bit_objects())
10434 as_fatal (_("No compiled in support for 64 bit object file "
10437 else if (strcmp (arg, "eabi") == 0)
10438 mips_abi = EABI_ABI;
10441 as_fatal (_("invalid abi -mabi=%s"), arg);
10445 #endif /* OBJ_ELF */
10447 case OPTION_M7000_HILO_FIX:
10448 mips_7000_hilo_fix = TRUE;
10451 case OPTION_MNO_7000_HILO_FIX:
10452 mips_7000_hilo_fix = FALSE;
10456 case OPTION_MDEBUG:
10457 mips_flag_mdebug = TRUE;
10460 case OPTION_NO_MDEBUG:
10461 mips_flag_mdebug = FALSE;
10465 mips_flag_pdr = TRUE;
10468 case OPTION_NO_PDR:
10469 mips_flag_pdr = FALSE;
10471 #endif /* OBJ_ELF */
10480 /* Set up globals to generate code for the ISA or processor
10481 described by INFO. */
10484 mips_set_architecture (const struct mips_cpu_info *info)
10488 file_mips_arch = info->cpu;
10489 mips_opts.arch = info->cpu;
10490 mips_opts.isa = info->isa;
10495 /* Likewise for tuning. */
10498 mips_set_tune (const struct mips_cpu_info *info)
10501 mips_tune = info->cpu;
10506 mips_after_parse_args (void)
10508 const struct mips_cpu_info *arch_info = 0;
10509 const struct mips_cpu_info *tune_info = 0;
10511 /* GP relative stuff not working for PE */
10512 if (strncmp (TARGET_OS, "pe", 2) == 0
10513 && g_switch_value != 0)
10516 as_bad (_("-G not supported in this configuration."));
10517 g_switch_value = 0;
10520 if (mips_abi == NO_ABI)
10521 mips_abi = MIPS_DEFAULT_ABI;
10523 /* The following code determines the architecture and register size.
10524 Similar code was added to GCC 3.3 (see override_options() in
10525 config/mips/mips.c). The GAS and GCC code should be kept in sync
10526 as much as possible. */
10528 if (mips_arch_string != 0)
10529 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10531 if (file_mips_isa != ISA_UNKNOWN)
10533 /* Handle -mipsN. At this point, file_mips_isa contains the
10534 ISA level specified by -mipsN, while arch_info->isa contains
10535 the -march selection (if any). */
10536 if (arch_info != 0)
10538 /* -march takes precedence over -mipsN, since it is more descriptive.
10539 There's no harm in specifying both as long as the ISA levels
10541 if (file_mips_isa != arch_info->isa)
10542 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10543 mips_cpu_info_from_isa (file_mips_isa)->name,
10544 mips_cpu_info_from_isa (arch_info->isa)->name);
10547 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10550 if (arch_info == 0)
10551 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10553 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10554 as_bad ("-march=%s is not compatible with the selected ABI",
10557 mips_set_architecture (arch_info);
10559 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10560 if (mips_tune_string != 0)
10561 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10563 if (tune_info == 0)
10564 mips_set_tune (arch_info);
10566 mips_set_tune (tune_info);
10568 if (file_mips_gp32 >= 0)
10570 /* The user specified the size of the integer registers. Make sure
10571 it agrees with the ABI and ISA. */
10572 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10573 as_bad (_("-mgp64 used with a 32-bit processor"));
10574 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10575 as_bad (_("-mgp32 used with a 64-bit ABI"));
10576 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10577 as_bad (_("-mgp64 used with a 32-bit ABI"));
10581 /* Infer the integer register size from the ABI and processor.
10582 Restrict ourselves to 32-bit registers if that's all the
10583 processor has, or if the ABI cannot handle 64-bit registers. */
10584 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10585 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10588 /* ??? GAS treats single-float processors as though they had 64-bit
10589 float registers (although it complains when double-precision
10590 instructions are used). As things stand, saying they have 32-bit
10591 registers would lead to spurious "register must be even" messages.
10592 So here we assume float registers are always the same size as
10593 integer ones, unless the user says otherwise. */
10594 if (file_mips_fp32 < 0)
10595 file_mips_fp32 = file_mips_gp32;
10597 /* End of GCC-shared inference code. */
10599 /* This flag is set when we have a 64-bit capable CPU but use only
10600 32-bit wide registers. Note that EABI does not use it. */
10601 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10602 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10603 || mips_abi == O32_ABI))
10604 mips_32bitmode = 1;
10606 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10607 as_bad (_("trap exception not supported at ISA 1"));
10609 /* If the selected architecture includes support for ASEs, enable
10610 generation of code for them. */
10611 if (mips_opts.mips16 == -1)
10612 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10613 if (mips_opts.ase_mips3d == -1)
10614 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10615 if (mips_opts.ase_mdmx == -1)
10616 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10618 file_mips_isa = mips_opts.isa;
10619 file_ase_mips16 = mips_opts.mips16;
10620 file_ase_mips3d = mips_opts.ase_mips3d;
10621 file_ase_mdmx = mips_opts.ase_mdmx;
10622 mips_opts.gp32 = file_mips_gp32;
10623 mips_opts.fp32 = file_mips_fp32;
10625 if (mips_flag_mdebug < 0)
10627 #ifdef OBJ_MAYBE_ECOFF
10628 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10629 mips_flag_mdebug = 1;
10631 #endif /* OBJ_MAYBE_ECOFF */
10632 mips_flag_mdebug = 0;
10637 mips_init_after_args (void)
10639 /* initialize opcodes */
10640 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10641 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10645 md_pcrel_from (fixS *fixP)
10647 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10648 switch (fixP->fx_r_type)
10650 case BFD_RELOC_16_PCREL_S2:
10651 case BFD_RELOC_MIPS_JMP:
10652 /* Return the address of the delay slot. */
10659 /* This is called before the symbol table is processed. In order to
10660 work with gcc when using mips-tfile, we must keep all local labels.
10661 However, in other cases, we want to discard them. If we were
10662 called with -g, but we didn't see any debugging information, it may
10663 mean that gcc is smuggling debugging information through to
10664 mips-tfile, in which case we must generate all local labels. */
10667 mips_frob_file_before_adjust (void)
10669 #ifndef NO_ECOFF_DEBUGGING
10670 if (ECOFF_DEBUGGING
10672 && ! ecoff_debugging_seen)
10673 flag_keep_locals = 1;
10677 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10678 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10679 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10680 relocation operators.
10682 For our purposes, a %lo() expression matches a %got() or %hi()
10685 (a) it refers to the same symbol; and
10686 (b) the offset applied in the %lo() expression is no lower than
10687 the offset applied in the %got() or %hi().
10689 (b) allows us to cope with code like:
10692 lh $4,%lo(foo+2)($4)
10694 ...which is legal on RELA targets, and has a well-defined behaviour
10695 if the user knows that adding 2 to "foo" will not induce a carry to
10698 When several %lo()s match a particular %got() or %hi(), we use the
10699 following rules to distinguish them:
10701 (1) %lo()s with smaller offsets are a better match than %lo()s with
10704 (2) %lo()s with no matching %got() or %hi() are better than those
10705 that already have a matching %got() or %hi().
10707 (3) later %lo()s are better than earlier %lo()s.
10709 These rules are applied in order.
10711 (1) means, among other things, that %lo()s with identical offsets are
10712 chosen if they exist.
10714 (2) means that we won't associate several high-part relocations with
10715 the same low-part relocation unless there's no alternative. Having
10716 several high parts for the same low part is a GNU extension; this rule
10717 allows careful users to avoid it.
10719 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10720 with the last high-part relocation being at the front of the list.
10721 It therefore makes sense to choose the last matching low-part
10722 relocation, all other things being equal. It's also easier
10723 to code that way. */
10726 mips_frob_file (void)
10728 struct mips_hi_fixup *l;
10730 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10732 segment_info_type *seginfo;
10733 bfd_boolean matched_lo_p;
10734 fixS **hi_pos, **lo_pos, **pos;
10736 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10738 /* If a GOT16 relocation turns out to be against a global symbol,
10739 there isn't supposed to be a matching LO. */
10740 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10741 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10744 /* Check quickly whether the next fixup happens to be a matching %lo. */
10745 if (fixup_has_matching_lo_p (l->fixp))
10748 seginfo = seg_info (l->seg);
10750 /* Set HI_POS to the position of this relocation in the chain.
10751 Set LO_POS to the position of the chosen low-part relocation.
10752 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10753 relocation that matches an immediately-preceding high-part
10757 matched_lo_p = FALSE;
10758 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10760 if (*pos == l->fixp)
10763 if ((*pos)->fx_r_type == BFD_RELOC_LO16
10764 && (*pos)->fx_addsy == l->fixp->fx_addsy
10765 && (*pos)->fx_offset >= l->fixp->fx_offset
10767 || (*pos)->fx_offset < (*lo_pos)->fx_offset
10769 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
10772 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
10773 && fixup_has_matching_lo_p (*pos));
10776 /* If we found a match, remove the high-part relocation from its
10777 current position and insert it before the low-part relocation.
10778 Make the offsets match so that fixup_has_matching_lo_p()
10781 We don't warn about unmatched high-part relocations since some
10782 versions of gcc have been known to emit dead "lui ...%hi(...)"
10784 if (lo_pos != NULL)
10786 l->fixp->fx_offset = (*lo_pos)->fx_offset;
10787 if (l->fixp->fx_next != *lo_pos)
10789 *hi_pos = l->fixp->fx_next;
10790 l->fixp->fx_next = *lo_pos;
10797 /* We may have combined relocations without symbols in the N32/N64 ABI.
10798 We have to prevent gas from dropping them. */
10801 mips_force_relocation (fixS *fixp)
10803 if (generic_force_reloc (fixp))
10807 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10808 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10809 || fixp->fx_r_type == BFD_RELOC_HI16_S
10810 || fixp->fx_r_type == BFD_RELOC_LO16))
10816 /* This hook is called before a fix is simplified. We don't really
10817 decide whether to skip a fix here. Rather, we turn global symbols
10818 used as branch targets into local symbols, such that they undergo
10819 simplification. We can only do this if the symbol is defined and
10820 it is in the same section as the branch. If this doesn't hold, we
10821 emit a better error message than just saying the relocation is not
10822 valid for the selected object format.
10824 FIXP is the fix-up we're going to try to simplify, SEG is the
10825 segment in which the fix up occurs. The return value should be
10826 non-zero to indicate the fix-up is valid for further
10827 simplifications. */
10830 mips_validate_fix (struct fix *fixP, asection *seg)
10832 /* There's a lot of discussion on whether it should be possible to
10833 use R_MIPS_PC16 to represent branch relocations. The outcome
10834 seems to be that it can, but gas/bfd are very broken in creating
10835 RELA relocations for this, so for now we only accept branches to
10836 symbols in the same section. Anything else is of dubious value,
10837 since there's no guarantee that at link time the symbol would be
10838 in range. Even for branches to local symbols this is arguably
10839 wrong, since it we assume the symbol is not going to be
10840 overridden, which should be possible per ELF library semantics,
10841 but then, there isn't a dynamic relocation that could be used to
10842 this effect, and the target would likely be out of range as well.
10844 Unfortunately, it seems that there is too much code out there
10845 that relies on branches to symbols that are global to be resolved
10846 as if they were local, like the IRIX tools do, so we do it as
10847 well, but with a warning so that people are reminded to fix their
10848 code. If we ever get back to using R_MIPS_PC16 for branch
10849 targets, this entire block should go away (and probably the
10850 whole function). */
10852 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
10853 && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
10854 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
10855 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
10858 if (! S_IS_DEFINED (fixP->fx_addsy))
10860 as_bad_where (fixP->fx_file, fixP->fx_line,
10861 _("Cannot branch to undefined symbol."));
10862 /* Avoid any further errors about this fixup. */
10865 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
10867 as_bad_where (fixP->fx_file, fixP->fx_line,
10868 _("Cannot branch to symbol in another section."));
10871 else if (S_IS_EXTERNAL (fixP->fx_addsy))
10873 symbolS *sym = fixP->fx_addsy;
10875 if (mips_pic == SVR4_PIC)
10876 as_warn_where (fixP->fx_file, fixP->fx_line,
10877 _("Pretending global symbol used as branch target is local."));
10879 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
10880 S_GET_SEGMENT (sym),
10882 symbol_get_frag (sym));
10883 copy_symbol_attributes (fixP->fx_addsy, sym);
10884 S_CLEAR_EXTERNAL (fixP->fx_addsy);
10885 assert (symbol_resolved_p (sym));
10886 symbol_mark_resolved (fixP->fx_addsy);
10893 /* Apply a fixup to the object file. */
10896 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10900 static int previous_fx_r_type = 0;
10901 reloc_howto_type *howto;
10903 /* We ignore generic BFD relocations we don't know about. */
10904 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10908 assert (fixP->fx_size == 4
10909 || fixP->fx_r_type == BFD_RELOC_16
10910 || fixP->fx_r_type == BFD_RELOC_64
10911 || fixP->fx_r_type == BFD_RELOC_CTOR
10912 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10913 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10914 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10916 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
10918 /* We are not done if this is a composite relocation to set up gp. */
10919 assert (! fixP->fx_pcrel);
10920 if (fixP->fx_addsy == NULL
10921 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10922 || (fixP->fx_r_type == BFD_RELOC_64
10923 && (previous_fx_r_type == BFD_RELOC_GPREL32
10924 || previous_fx_r_type == BFD_RELOC_GPREL16))
10925 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
10926 && (fixP->fx_r_type == BFD_RELOC_HI16_S
10927 || fixP->fx_r_type == BFD_RELOC_LO16))))
10929 previous_fx_r_type = fixP->fx_r_type;
10931 switch (fixP->fx_r_type)
10933 case BFD_RELOC_MIPS_JMP:
10934 case BFD_RELOC_MIPS_SHIFT5:
10935 case BFD_RELOC_MIPS_SHIFT6:
10936 case BFD_RELOC_MIPS_GOT_DISP:
10937 case BFD_RELOC_MIPS_GOT_PAGE:
10938 case BFD_RELOC_MIPS_GOT_OFST:
10939 case BFD_RELOC_MIPS_SUB:
10940 case BFD_RELOC_MIPS_INSERT_A:
10941 case BFD_RELOC_MIPS_INSERT_B:
10942 case BFD_RELOC_MIPS_DELETE:
10943 case BFD_RELOC_MIPS_HIGHEST:
10944 case BFD_RELOC_MIPS_HIGHER:
10945 case BFD_RELOC_MIPS_SCN_DISP:
10946 case BFD_RELOC_MIPS_REL16:
10947 case BFD_RELOC_MIPS_RELGOT:
10948 case BFD_RELOC_MIPS_JALR:
10949 case BFD_RELOC_HI16:
10950 case BFD_RELOC_HI16_S:
10951 case BFD_RELOC_GPREL16:
10952 case BFD_RELOC_MIPS_LITERAL:
10953 case BFD_RELOC_MIPS_CALL16:
10954 case BFD_RELOC_MIPS_GOT16:
10955 case BFD_RELOC_GPREL32:
10956 case BFD_RELOC_MIPS_GOT_HI16:
10957 case BFD_RELOC_MIPS_GOT_LO16:
10958 case BFD_RELOC_MIPS_CALL_HI16:
10959 case BFD_RELOC_MIPS_CALL_LO16:
10960 case BFD_RELOC_MIPS16_GPREL:
10961 assert (! fixP->fx_pcrel);
10962 /* Nothing needed to do. The value comes from the reloc entry */
10965 case BFD_RELOC_MIPS16_JMP:
10966 /* We currently always generate a reloc against a symbol, which
10967 means that we don't want an addend even if the symbol is
10973 /* This is handled like BFD_RELOC_32, but we output a sign
10974 extended value if we are only 32 bits. */
10977 if (8 <= sizeof (valueT))
10978 md_number_to_chars (buf, *valP, 8);
10983 if ((*valP & 0x80000000) != 0)
10987 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
10989 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
10995 case BFD_RELOC_RVA:
10997 /* If we are deleting this reloc entry, we must fill in the
10998 value now. This can happen if we have a .word which is not
10999 resolved when it appears but is later defined. */
11001 md_number_to_chars (buf, *valP, 4);
11005 /* If we are deleting this reloc entry, we must fill in the
11007 assert (fixP->fx_size == 2);
11009 md_number_to_chars (buf, *valP, 2);
11012 case BFD_RELOC_LO16:
11013 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11014 may be safe to remove, but if so it's not obvious. */
11015 /* When handling an embedded PIC switch statement, we can wind
11016 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11019 if (*valP + 0x8000 > 0xffff)
11020 as_bad_where (fixP->fx_file, fixP->fx_line,
11021 _("relocation overflow"));
11022 if (target_big_endian)
11024 md_number_to_chars (buf, *valP, 2);
11028 case BFD_RELOC_16_PCREL_S2:
11029 if ((*valP & 0x3) != 0)
11030 as_bad_where (fixP->fx_file, fixP->fx_line,
11031 _("Branch to odd address (%lx)"), (long) *valP);
11034 * We need to save the bits in the instruction since fixup_segment()
11035 * might be deleting the relocation entry (i.e., a branch within
11036 * the current segment).
11038 if (! fixP->fx_done)
11041 /* update old instruction data */
11042 if (target_big_endian)
11043 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11045 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11047 if (*valP + 0x20000 <= 0x3ffff)
11049 insn |= (*valP >> 2) & 0xffff;
11050 md_number_to_chars (buf, insn, 4);
11052 else if (mips_pic == NO_PIC
11054 && fixP->fx_frag->fr_address >= text_section->vma
11055 && (fixP->fx_frag->fr_address
11056 < text_section->vma + bfd_get_section_size (text_section))
11057 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11058 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11059 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11061 /* The branch offset is too large. If this is an
11062 unconditional branch, and we are not generating PIC code,
11063 we can convert it to an absolute jump instruction. */
11064 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11065 insn = 0x0c000000; /* jal */
11067 insn = 0x08000000; /* j */
11068 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11070 fixP->fx_addsy = section_symbol (text_section);
11071 *valP += md_pcrel_from (fixP);
11072 md_number_to_chars (buf, insn, 4);
11076 /* If we got here, we have branch-relaxation disabled,
11077 and there's nothing we can do to fix this instruction
11078 without turning it into a longer sequence. */
11079 as_bad_where (fixP->fx_file, fixP->fx_line,
11080 _("Branch out of range"));
11084 case BFD_RELOC_VTABLE_INHERIT:
11087 && !S_IS_DEFINED (fixP->fx_addsy)
11088 && !S_IS_WEAK (fixP->fx_addsy))
11089 S_SET_WEAK (fixP->fx_addsy);
11092 case BFD_RELOC_VTABLE_ENTRY:
11100 /* Remember value for tc_gen_reloc. */
11101 fixP->fx_addnumber = *valP;
11106 printInsn (unsigned long oc)
11108 const struct mips_opcode *p;
11109 int treg, sreg, dreg, shamt;
11114 for (i = 0; i < NUMOPCODES; ++i)
11116 p = &mips_opcodes[i];
11117 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11119 printf ("%08lx %s\t", oc, p->name);
11120 treg = (oc >> 16) & 0x1f;
11121 sreg = (oc >> 21) & 0x1f;
11122 dreg = (oc >> 11) & 0x1f;
11123 shamt = (oc >> 6) & 0x1f;
11125 for (args = p->args;; ++args)
11136 printf ("%c", *args);
11140 assert (treg == sreg);
11141 printf ("$%d,$%d", treg, sreg);
11146 printf ("$%d", dreg);
11151 printf ("$%d", treg);
11155 printf ("0x%x", treg);
11160 printf ("$%d", sreg);
11164 printf ("0x%08lx", oc & 0x1ffffff);
11171 printf ("%d", imm);
11176 printf ("$%d", shamt);
11187 printf (_("%08lx UNDEFINED\n"), oc);
11198 name = input_line_pointer;
11199 c = get_symbol_end ();
11200 p = (symbolS *) symbol_find_or_make (name);
11201 *input_line_pointer = c;
11205 /* Align the current frag to a given power of two. The MIPS assembler
11206 also automatically adjusts any preceding label. */
11209 mips_align (int to, int fill, symbolS *label)
11211 mips_emit_delays (FALSE);
11212 frag_align (to, fill, 0);
11213 record_alignment (now_seg, to);
11216 assert (S_GET_SEGMENT (label) == now_seg);
11217 symbol_set_frag (label, frag_now);
11218 S_SET_VALUE (label, (valueT) frag_now_fix ());
11222 /* Align to a given power of two. .align 0 turns off the automatic
11223 alignment used by the data creating pseudo-ops. */
11226 s_align (int x ATTRIBUTE_UNUSED)
11229 register long temp_fill;
11230 long max_alignment = 15;
11234 o Note that the assembler pulls down any immediately preceding label
11235 to the aligned address.
11236 o It's not documented but auto alignment is reinstated by
11237 a .align pseudo instruction.
11238 o Note also that after auto alignment is turned off the mips assembler
11239 issues an error on attempt to assemble an improperly aligned data item.
11244 temp = get_absolute_expression ();
11245 if (temp > max_alignment)
11246 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11249 as_warn (_("Alignment negative: 0 assumed."));
11252 if (*input_line_pointer == ',')
11254 ++input_line_pointer;
11255 temp_fill = get_absolute_expression ();
11262 mips_align (temp, (int) temp_fill,
11263 insn_labels != NULL ? insn_labels->label : NULL);
11270 demand_empty_rest_of_line ();
11274 mips_flush_pending_output (void)
11276 mips_emit_delays (FALSE);
11277 mips_clear_insn_labels ();
11281 s_change_sec (int sec)
11286 /* The ELF backend needs to know that we are changing sections, so
11287 that .previous works correctly. We could do something like check
11288 for an obj_section_change_hook macro, but that might be confusing
11289 as it would not be appropriate to use it in the section changing
11290 functions in read.c, since obj-elf.c intercepts those. FIXME:
11291 This should be cleaner, somehow. */
11292 obj_elf_section_change_hook ();
11295 mips_emit_delays (FALSE);
11305 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11306 demand_empty_rest_of_line ();
11310 seg = subseg_new (RDATA_SECTION_NAME,
11311 (subsegT) get_absolute_expression ());
11312 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11314 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11315 | SEC_READONLY | SEC_RELOC
11317 if (strcmp (TARGET_OS, "elf") != 0)
11318 record_alignment (seg, 4);
11320 demand_empty_rest_of_line ();
11324 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11325 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11327 bfd_set_section_flags (stdoutput, seg,
11328 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11329 if (strcmp (TARGET_OS, "elf") != 0)
11330 record_alignment (seg, 4);
11332 demand_empty_rest_of_line ();
11340 s_change_section (int ignore ATTRIBUTE_UNUSED)
11343 char *section_name;
11348 int section_entry_size;
11349 int section_alignment;
11351 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11354 section_name = input_line_pointer;
11355 c = get_symbol_end ();
11357 next_c = *(input_line_pointer + 1);
11359 /* Do we have .section Name<,"flags">? */
11360 if (c != ',' || (c == ',' && next_c == '"'))
11362 /* just after name is now '\0'. */
11363 *input_line_pointer = c;
11364 input_line_pointer = section_name;
11365 obj_elf_section (ignore);
11368 input_line_pointer++;
11370 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11372 section_type = get_absolute_expression ();
11375 if (*input_line_pointer++ == ',')
11376 section_flag = get_absolute_expression ();
11379 if (*input_line_pointer++ == ',')
11380 section_entry_size = get_absolute_expression ();
11382 section_entry_size = 0;
11383 if (*input_line_pointer++ == ',')
11384 section_alignment = get_absolute_expression ();
11386 section_alignment = 0;
11388 section_name = xstrdup (section_name);
11390 /* When using the generic form of .section (as implemented by obj-elf.c),
11391 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11392 traditionally had to fall back on the more common @progbits instead.
11394 There's nothing really harmful in this, since bfd will correct
11395 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11396 means that, for backwards compatibiltiy, the special_section entries
11397 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11399 Even so, we shouldn't force users of the MIPS .section syntax to
11400 incorrectly label the sections as SHT_PROGBITS. The best compromise
11401 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11402 generic type-checking code. */
11403 if (section_type == SHT_MIPS_DWARF)
11404 section_type = SHT_PROGBITS;
11406 obj_elf_change_section (section_name, section_type, section_flag,
11407 section_entry_size, 0, 0, 0);
11409 if (now_seg->name != section_name)
11410 free (section_name);
11411 #endif /* OBJ_ELF */
11415 mips_enable_auto_align (void)
11421 s_cons (int log_size)
11425 label = insn_labels != NULL ? insn_labels->label : NULL;
11426 mips_emit_delays (FALSE);
11427 if (log_size > 0 && auto_align)
11428 mips_align (log_size, 0, label);
11429 mips_clear_insn_labels ();
11430 cons (1 << log_size);
11434 s_float_cons (int type)
11438 label = insn_labels != NULL ? insn_labels->label : NULL;
11440 mips_emit_delays (FALSE);
11445 mips_align (3, 0, label);
11447 mips_align (2, 0, label);
11450 mips_clear_insn_labels ();
11455 /* Handle .globl. We need to override it because on Irix 5 you are
11458 where foo is an undefined symbol, to mean that foo should be
11459 considered to be the address of a function. */
11462 s_mips_globl (int x ATTRIBUTE_UNUSED)
11469 name = input_line_pointer;
11470 c = get_symbol_end ();
11471 symbolP = symbol_find_or_make (name);
11472 *input_line_pointer = c;
11473 SKIP_WHITESPACE ();
11475 /* On Irix 5, every global symbol that is not explicitly labelled as
11476 being a function is apparently labelled as being an object. */
11479 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11484 secname = input_line_pointer;
11485 c = get_symbol_end ();
11486 sec = bfd_get_section_by_name (stdoutput, secname);
11488 as_bad (_("%s: no such section"), secname);
11489 *input_line_pointer = c;
11491 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11492 flag = BSF_FUNCTION;
11495 symbol_get_bfdsym (symbolP)->flags |= flag;
11497 S_SET_EXTERNAL (symbolP);
11498 demand_empty_rest_of_line ();
11502 s_option (int x ATTRIBUTE_UNUSED)
11507 opt = input_line_pointer;
11508 c = get_symbol_end ();
11512 /* FIXME: What does this mean? */
11514 else if (strncmp (opt, "pic", 3) == 0)
11518 i = atoi (opt + 3);
11523 mips_pic = SVR4_PIC;
11524 mips_abicalls = TRUE;
11527 as_bad (_(".option pic%d not supported"), i);
11529 if (mips_pic == SVR4_PIC)
11531 if (g_switch_seen && g_switch_value != 0)
11532 as_warn (_("-G may not be used with SVR4 PIC code"));
11533 g_switch_value = 0;
11534 bfd_set_gp_size (stdoutput, 0);
11538 as_warn (_("Unrecognized option \"%s\""), opt);
11540 *input_line_pointer = c;
11541 demand_empty_rest_of_line ();
11544 /* This structure is used to hold a stack of .set values. */
11546 struct mips_option_stack
11548 struct mips_option_stack *next;
11549 struct mips_set_options options;
11552 static struct mips_option_stack *mips_opts_stack;
11554 /* Handle the .set pseudo-op. */
11557 s_mipsset (int x ATTRIBUTE_UNUSED)
11559 char *name = input_line_pointer, ch;
11561 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11562 ++input_line_pointer;
11563 ch = *input_line_pointer;
11564 *input_line_pointer = '\0';
11566 if (strcmp (name, "reorder") == 0)
11568 if (mips_opts.noreorder && prev_nop_frag != NULL)
11570 /* If we still have pending nops, we can discard them. The
11571 usual nop handling will insert any that are still
11573 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11574 * (mips_opts.mips16 ? 2 : 4));
11575 prev_nop_frag = NULL;
11577 mips_opts.noreorder = 0;
11579 else if (strcmp (name, "noreorder") == 0)
11581 mips_emit_delays (TRUE);
11582 mips_opts.noreorder = 1;
11583 mips_any_noreorder = 1;
11585 else if (strcmp (name, "at") == 0)
11587 mips_opts.noat = 0;
11589 else if (strcmp (name, "noat") == 0)
11591 mips_opts.noat = 1;
11593 else if (strcmp (name, "macro") == 0)
11595 mips_opts.warn_about_macros = 0;
11597 else if (strcmp (name, "nomacro") == 0)
11599 if (mips_opts.noreorder == 0)
11600 as_bad (_("`noreorder' must be set before `nomacro'"));
11601 mips_opts.warn_about_macros = 1;
11603 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11605 mips_opts.nomove = 0;
11607 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11609 mips_opts.nomove = 1;
11611 else if (strcmp (name, "bopt") == 0)
11613 mips_opts.nobopt = 0;
11615 else if (strcmp (name, "nobopt") == 0)
11617 mips_opts.nobopt = 1;
11619 else if (strcmp (name, "mips16") == 0
11620 || strcmp (name, "MIPS-16") == 0)
11621 mips_opts.mips16 = 1;
11622 else if (strcmp (name, "nomips16") == 0
11623 || strcmp (name, "noMIPS-16") == 0)
11624 mips_opts.mips16 = 0;
11625 else if (strcmp (name, "mips3d") == 0)
11626 mips_opts.ase_mips3d = 1;
11627 else if (strcmp (name, "nomips3d") == 0)
11628 mips_opts.ase_mips3d = 0;
11629 else if (strcmp (name, "mdmx") == 0)
11630 mips_opts.ase_mdmx = 1;
11631 else if (strcmp (name, "nomdmx") == 0)
11632 mips_opts.ase_mdmx = 0;
11633 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11637 /* Permit the user to change the ISA and architecture on the fly.
11638 Needless to say, misuse can cause serious problems. */
11639 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11642 mips_opts.isa = file_mips_isa;
11643 mips_opts.arch = file_mips_arch;
11645 else if (strncmp (name, "arch=", 5) == 0)
11647 const struct mips_cpu_info *p;
11649 p = mips_parse_cpu("internal use", name + 5);
11651 as_bad (_("unknown architecture %s"), name + 5);
11654 mips_opts.arch = p->cpu;
11655 mips_opts.isa = p->isa;
11658 else if (strncmp (name, "mips", 4) == 0)
11660 const struct mips_cpu_info *p;
11662 p = mips_parse_cpu("internal use", name);
11664 as_bad (_("unknown ISA level %s"), name + 4);
11667 mips_opts.arch = p->cpu;
11668 mips_opts.isa = p->isa;
11672 as_bad (_("unknown ISA or architecture %s"), name);
11674 switch (mips_opts.isa)
11682 mips_opts.gp32 = 1;
11683 mips_opts.fp32 = 1;
11690 mips_opts.gp32 = 0;
11691 mips_opts.fp32 = 0;
11694 as_bad (_("unknown ISA level %s"), name + 4);
11699 mips_opts.gp32 = file_mips_gp32;
11700 mips_opts.fp32 = file_mips_fp32;
11703 else if (strcmp (name, "autoextend") == 0)
11704 mips_opts.noautoextend = 0;
11705 else if (strcmp (name, "noautoextend") == 0)
11706 mips_opts.noautoextend = 1;
11707 else if (strcmp (name, "push") == 0)
11709 struct mips_option_stack *s;
11711 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11712 s->next = mips_opts_stack;
11713 s->options = mips_opts;
11714 mips_opts_stack = s;
11716 else if (strcmp (name, "pop") == 0)
11718 struct mips_option_stack *s;
11720 s = mips_opts_stack;
11722 as_bad (_(".set pop with no .set push"));
11725 /* If we're changing the reorder mode we need to handle
11726 delay slots correctly. */
11727 if (s->options.noreorder && ! mips_opts.noreorder)
11728 mips_emit_delays (TRUE);
11729 else if (! s->options.noreorder && mips_opts.noreorder)
11731 if (prev_nop_frag != NULL)
11733 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11734 * (mips_opts.mips16 ? 2 : 4));
11735 prev_nop_frag = NULL;
11739 mips_opts = s->options;
11740 mips_opts_stack = s->next;
11746 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11748 *input_line_pointer = ch;
11749 demand_empty_rest_of_line ();
11752 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11753 .option pic2. It means to generate SVR4 PIC calls. */
11756 s_abicalls (int ignore ATTRIBUTE_UNUSED)
11758 mips_pic = SVR4_PIC;
11759 mips_abicalls = TRUE;
11761 if (g_switch_seen && g_switch_value != 0)
11762 as_warn (_("-G may not be used with SVR4 PIC code"));
11763 g_switch_value = 0;
11765 bfd_set_gp_size (stdoutput, 0);
11766 demand_empty_rest_of_line ();
11769 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11770 PIC code. It sets the $gp register for the function based on the
11771 function address, which is in the register named in the argument.
11772 This uses a relocation against _gp_disp, which is handled specially
11773 by the linker. The result is:
11774 lui $gp,%hi(_gp_disp)
11775 addiu $gp,$gp,%lo(_gp_disp)
11776 addu $gp,$gp,.cpload argument
11777 The .cpload argument is normally $25 == $t9. */
11780 s_cpload (int ignore ATTRIBUTE_UNUSED)
11784 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11785 .cpload is ignored. */
11786 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11792 /* .cpload should be in a .set noreorder section. */
11793 if (mips_opts.noreorder == 0)
11794 as_warn (_(".cpload not in noreorder section"));
11796 ex.X_op = O_symbol;
11797 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11798 ex.X_op_symbol = NULL;
11799 ex.X_add_number = 0;
11801 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11802 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11805 macro_build_lui (&ex, mips_gp_register);
11806 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11807 mips_gp_register, BFD_RELOC_LO16);
11808 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
11809 mips_gp_register, tc_get_register (0));
11812 demand_empty_rest_of_line ();
11815 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11816 .cpsetup $reg1, offset|$reg2, label
11818 If offset is given, this results in:
11819 sd $gp, offset($sp)
11820 lui $gp, %hi(%neg(%gp_rel(label)))
11821 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11822 daddu $gp, $gp, $reg1
11824 If $reg2 is given, this results in:
11825 daddu $reg2, $gp, $0
11826 lui $gp, %hi(%neg(%gp_rel(label)))
11827 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11828 daddu $gp, $gp, $reg1
11829 $reg1 is normally $25 == $t9. */
11831 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
11833 expressionS ex_off;
11834 expressionS ex_sym;
11838 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11839 We also need NewABI support. */
11840 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11846 reg1 = tc_get_register (0);
11847 SKIP_WHITESPACE ();
11848 if (*input_line_pointer != ',')
11850 as_bad (_("missing argument separator ',' for .cpsetup"));
11854 ++input_line_pointer;
11855 SKIP_WHITESPACE ();
11856 if (*input_line_pointer == '$')
11858 mips_cpreturn_register = tc_get_register (0);
11859 mips_cpreturn_offset = -1;
11863 mips_cpreturn_offset = get_absolute_expression ();
11864 mips_cpreturn_register = -1;
11866 SKIP_WHITESPACE ();
11867 if (*input_line_pointer != ',')
11869 as_bad (_("missing argument separator ',' for .cpsetup"));
11873 ++input_line_pointer;
11874 SKIP_WHITESPACE ();
11875 expression (&ex_sym);
11878 if (mips_cpreturn_register == -1)
11880 ex_off.X_op = O_constant;
11881 ex_off.X_add_symbol = NULL;
11882 ex_off.X_op_symbol = NULL;
11883 ex_off.X_add_number = mips_cpreturn_offset;
11885 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
11886 BFD_RELOC_LO16, SP);
11889 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
11890 mips_gp_register, 0);
11892 /* Ensure there's room for the next two instructions, so that `f'
11893 doesn't end up with an address in the wrong frag. */
11896 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
11897 fix_new (frag_now, f - frag_now->fr_literal,
11898 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11899 fix_new (frag_now, f - frag_now->fr_literal,
11900 4, NULL, 0, 0, BFD_RELOC_HI16_S);
11903 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
11904 mips_gp_register, BFD_RELOC_GPREL16);
11905 fix_new (frag_now, f - frag_now->fr_literal,
11906 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11907 fix_new (frag_now, f - frag_now->fr_literal,
11908 4, NULL, 0, 0, BFD_RELOC_LO16);
11910 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
11911 mips_gp_register, reg1);
11914 demand_empty_rest_of_line ();
11918 s_cplocal (int ignore ATTRIBUTE_UNUSED)
11920 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11921 .cplocal is ignored. */
11922 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11928 mips_gp_register = tc_get_register (0);
11929 demand_empty_rest_of_line ();
11932 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11933 offset from $sp. The offset is remembered, and after making a PIC
11934 call $gp is restored from that location. */
11937 s_cprestore (int ignore ATTRIBUTE_UNUSED)
11941 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11942 .cprestore is ignored. */
11943 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11949 mips_cprestore_offset = get_absolute_expression ();
11950 mips_cprestore_valid = 1;
11952 ex.X_op = O_constant;
11953 ex.X_add_symbol = NULL;
11954 ex.X_op_symbol = NULL;
11955 ex.X_add_number = mips_cprestore_offset;
11958 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
11959 SP, HAVE_64BIT_ADDRESSES);
11962 demand_empty_rest_of_line ();
11965 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11966 was given in the preceding .cpsetup, it results in:
11967 ld $gp, offset($sp)
11969 If a register $reg2 was given there, it results in:
11970 daddu $gp, $reg2, $0
11973 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
11977 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11978 We also need NewABI support. */
11979 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11986 if (mips_cpreturn_register == -1)
11988 ex.X_op = O_constant;
11989 ex.X_add_symbol = NULL;
11990 ex.X_op_symbol = NULL;
11991 ex.X_add_number = mips_cpreturn_offset;
11993 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
11996 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
11997 mips_cpreturn_register, 0);
12000 demand_empty_rest_of_line ();
12003 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12004 code. It sets the offset to use in gp_rel relocations. */
12007 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12009 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12010 We also need NewABI support. */
12011 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12017 mips_gprel_offset = get_absolute_expression ();
12019 demand_empty_rest_of_line ();
12022 /* Handle the .gpword pseudo-op. This is used when generating PIC
12023 code. It generates a 32 bit GP relative reloc. */
12026 s_gpword (int ignore ATTRIBUTE_UNUSED)
12032 /* When not generating PIC code, this is treated as .word. */
12033 if (mips_pic != SVR4_PIC)
12039 label = insn_labels != NULL ? insn_labels->label : NULL;
12040 mips_emit_delays (TRUE);
12042 mips_align (2, 0, label);
12043 mips_clear_insn_labels ();
12047 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12049 as_bad (_("Unsupported use of .gpword"));
12050 ignore_rest_of_line ();
12054 md_number_to_chars (p, 0, 4);
12055 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12056 BFD_RELOC_GPREL32);
12058 demand_empty_rest_of_line ();
12062 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12068 /* When not generating PIC code, this is treated as .dword. */
12069 if (mips_pic != SVR4_PIC)
12075 label = insn_labels != NULL ? insn_labels->label : NULL;
12076 mips_emit_delays (TRUE);
12078 mips_align (3, 0, label);
12079 mips_clear_insn_labels ();
12083 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12085 as_bad (_("Unsupported use of .gpdword"));
12086 ignore_rest_of_line ();
12090 md_number_to_chars (p, 0, 8);
12091 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12092 BFD_RELOC_GPREL32);
12094 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12095 ex.X_op = O_absent;
12096 ex.X_add_symbol = 0;
12097 ex.X_add_number = 0;
12098 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12101 demand_empty_rest_of_line ();
12104 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12105 tables in SVR4 PIC code. */
12108 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12112 /* This is ignored when not generating SVR4 PIC code. */
12113 if (mips_pic != SVR4_PIC)
12119 /* Add $gp to the register named as an argument. */
12121 reg = tc_get_register (0);
12122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12125 demand_empty_rest_of_line ();
12128 /* Handle the .insn pseudo-op. This marks instruction labels in
12129 mips16 mode. This permits the linker to handle them specially,
12130 such as generating jalx instructions when needed. We also make
12131 them odd for the duration of the assembly, in order to generate the
12132 right sort of code. We will make them even in the adjust_symtab
12133 routine, while leaving them marked. This is convenient for the
12134 debugger and the disassembler. The linker knows to make them odd
12138 s_insn (int ignore ATTRIBUTE_UNUSED)
12140 mips16_mark_labels ();
12142 demand_empty_rest_of_line ();
12145 /* Handle a .stabn directive. We need these in order to mark a label
12146 as being a mips16 text label correctly. Sometimes the compiler
12147 will emit a label, followed by a .stabn, and then switch sections.
12148 If the label and .stabn are in mips16 mode, then the label is
12149 really a mips16 text label. */
12152 s_mips_stab (int type)
12155 mips16_mark_labels ();
12160 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12164 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12171 name = input_line_pointer;
12172 c = get_symbol_end ();
12173 symbolP = symbol_find_or_make (name);
12174 S_SET_WEAK (symbolP);
12175 *input_line_pointer = c;
12177 SKIP_WHITESPACE ();
12179 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12181 if (S_IS_DEFINED (symbolP))
12183 as_bad ("ignoring attempt to redefine symbol %s",
12184 S_GET_NAME (symbolP));
12185 ignore_rest_of_line ();
12189 if (*input_line_pointer == ',')
12191 ++input_line_pointer;
12192 SKIP_WHITESPACE ();
12196 if (exp.X_op != O_symbol)
12198 as_bad ("bad .weakext directive");
12199 ignore_rest_of_line ();
12202 symbol_set_value_expression (symbolP, &exp);
12205 demand_empty_rest_of_line ();
12208 /* Parse a register string into a number. Called from the ECOFF code
12209 to parse .frame. The argument is non-zero if this is the frame
12210 register, so that we can record it in mips_frame_reg. */
12213 tc_get_register (int frame)
12217 SKIP_WHITESPACE ();
12218 if (*input_line_pointer++ != '$')
12220 as_warn (_("expected `$'"));
12223 else if (ISDIGIT (*input_line_pointer))
12225 reg = get_absolute_expression ();
12226 if (reg < 0 || reg >= 32)
12228 as_warn (_("Bad register number"));
12234 if (strncmp (input_line_pointer, "ra", 2) == 0)
12237 input_line_pointer += 2;
12239 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12242 input_line_pointer += 2;
12244 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12247 input_line_pointer += 2;
12249 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12252 input_line_pointer += 2;
12254 else if (strncmp (input_line_pointer, "at", 2) == 0)
12257 input_line_pointer += 2;
12259 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12262 input_line_pointer += 3;
12264 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12267 input_line_pointer += 3;
12269 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12272 input_line_pointer += 4;
12276 as_warn (_("Unrecognized register name"));
12278 while (ISALNUM(*input_line_pointer))
12279 input_line_pointer++;
12284 mips_frame_reg = reg != 0 ? reg : SP;
12285 mips_frame_reg_valid = 1;
12286 mips_cprestore_valid = 0;
12292 md_section_align (asection *seg, valueT addr)
12294 int align = bfd_get_section_alignment (stdoutput, seg);
12297 /* We don't need to align ELF sections to the full alignment.
12298 However, Irix 5 may prefer that we align them at least to a 16
12299 byte boundary. We don't bother to align the sections if we are
12300 targeted for an embedded system. */
12301 if (strcmp (TARGET_OS, "elf") == 0)
12307 return ((addr + (1 << align) - 1) & (-1 << align));
12310 /* Utility routine, called from above as well. If called while the
12311 input file is still being read, it's only an approximation. (For
12312 example, a symbol may later become defined which appeared to be
12313 undefined earlier.) */
12316 nopic_need_relax (symbolS *sym, int before_relaxing)
12321 if (g_switch_value > 0)
12323 const char *symname;
12326 /* Find out whether this symbol can be referenced off the $gp
12327 register. It can be if it is smaller than the -G size or if
12328 it is in the .sdata or .sbss section. Certain symbols can
12329 not be referenced off the $gp, although it appears as though
12331 symname = S_GET_NAME (sym);
12332 if (symname != (const char *) NULL
12333 && (strcmp (symname, "eprol") == 0
12334 || strcmp (symname, "etext") == 0
12335 || strcmp (symname, "_gp") == 0
12336 || strcmp (symname, "edata") == 0
12337 || strcmp (symname, "_fbss") == 0
12338 || strcmp (symname, "_fdata") == 0
12339 || strcmp (symname, "_ftext") == 0
12340 || strcmp (symname, "end") == 0
12341 || strcmp (symname, "_gp_disp") == 0))
12343 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12345 #ifndef NO_ECOFF_DEBUGGING
12346 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12347 && (symbol_get_obj (sym)->ecoff_extern_size
12348 <= g_switch_value))
12350 /* We must defer this decision until after the whole
12351 file has been read, since there might be a .extern
12352 after the first use of this symbol. */
12353 || (before_relaxing
12354 #ifndef NO_ECOFF_DEBUGGING
12355 && symbol_get_obj (sym)->ecoff_extern_size == 0
12357 && S_GET_VALUE (sym) == 0)
12358 || (S_GET_VALUE (sym) != 0
12359 && S_GET_VALUE (sym) <= g_switch_value)))
12363 const char *segname;
12365 segname = segment_name (S_GET_SEGMENT (sym));
12366 assert (strcmp (segname, ".lit8") != 0
12367 && strcmp (segname, ".lit4") != 0);
12368 change = (strcmp (segname, ".sdata") != 0
12369 && strcmp (segname, ".sbss") != 0
12370 && strncmp (segname, ".sdata.", 7) != 0
12371 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12376 /* We are not optimizing for the $gp register. */
12381 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12384 pic_need_relax (symbolS *sym, asection *segtype)
12387 bfd_boolean linkonce;
12389 /* Handle the case of a symbol equated to another symbol. */
12390 while (symbol_equated_reloc_p (sym))
12394 /* It's possible to get a loop here in a badly written
12396 n = symbol_get_value_expression (sym)->X_add_symbol;
12402 symsec = S_GET_SEGMENT (sym);
12404 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12406 if (symsec != segtype && ! S_IS_LOCAL (sym))
12408 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12412 /* The GNU toolchain uses an extension for ELF: a section
12413 beginning with the magic string .gnu.linkonce is a linkonce
12415 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12416 sizeof ".gnu.linkonce" - 1) == 0)
12420 /* This must duplicate the test in adjust_reloc_syms. */
12421 return (symsec != &bfd_und_section
12422 && symsec != &bfd_abs_section
12423 && ! bfd_is_com_section (symsec)
12426 /* A global or weak symbol is treated as external. */
12427 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12428 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12434 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12435 extended opcode. SEC is the section the frag is in. */
12438 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12441 register const struct mips16_immed_operand *op;
12443 int mintiny, maxtiny;
12447 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12449 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12452 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12453 op = mips16_immed_operands;
12454 while (op->type != type)
12457 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12462 if (type == '<' || type == '>' || type == '[' || type == ']')
12465 maxtiny = 1 << op->nbits;
12470 maxtiny = (1 << op->nbits) - 1;
12475 mintiny = - (1 << (op->nbits - 1));
12476 maxtiny = (1 << (op->nbits - 1)) - 1;
12479 sym_frag = symbol_get_frag (fragp->fr_symbol);
12480 val = S_GET_VALUE (fragp->fr_symbol);
12481 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12487 /* We won't have the section when we are called from
12488 mips_relax_frag. However, we will always have been called
12489 from md_estimate_size_before_relax first. If this is a
12490 branch to a different section, we mark it as such. If SEC is
12491 NULL, and the frag is not marked, then it must be a branch to
12492 the same section. */
12495 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12500 /* Must have been called from md_estimate_size_before_relax. */
12503 fragp->fr_subtype =
12504 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12506 /* FIXME: We should support this, and let the linker
12507 catch branches and loads that are out of range. */
12508 as_bad_where (fragp->fr_file, fragp->fr_line,
12509 _("unsupported PC relative reference to different section"));
12513 if (fragp != sym_frag && sym_frag->fr_address == 0)
12514 /* Assume non-extended on the first relaxation pass.
12515 The address we have calculated will be bogus if this is
12516 a forward branch to another frag, as the forward frag
12517 will have fr_address == 0. */
12521 /* In this case, we know for sure that the symbol fragment is in
12522 the same section. If the relax_marker of the symbol fragment
12523 differs from the relax_marker of this fragment, we have not
12524 yet adjusted the symbol fragment fr_address. We want to add
12525 in STRETCH in order to get a better estimate of the address.
12526 This particularly matters because of the shift bits. */
12528 && sym_frag->relax_marker != fragp->relax_marker)
12532 /* Adjust stretch for any alignment frag. Note that if have
12533 been expanding the earlier code, the symbol may be
12534 defined in what appears to be an earlier frag. FIXME:
12535 This doesn't handle the fr_subtype field, which specifies
12536 a maximum number of bytes to skip when doing an
12538 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12540 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12543 stretch = - ((- stretch)
12544 & ~ ((1 << (int) f->fr_offset) - 1));
12546 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12555 addr = fragp->fr_address + fragp->fr_fix;
12557 /* The base address rules are complicated. The base address of
12558 a branch is the following instruction. The base address of a
12559 PC relative load or add is the instruction itself, but if it
12560 is in a delay slot (in which case it can not be extended) use
12561 the address of the instruction whose delay slot it is in. */
12562 if (type == 'p' || type == 'q')
12566 /* If we are currently assuming that this frag should be
12567 extended, then, the current address is two bytes
12569 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12572 /* Ignore the low bit in the target, since it will be set
12573 for a text label. */
12574 if ((val & 1) != 0)
12577 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12579 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12582 val -= addr & ~ ((1 << op->shift) - 1);
12584 /* Branch offsets have an implicit 0 in the lowest bit. */
12585 if (type == 'p' || type == 'q')
12588 /* If any of the shifted bits are set, we must use an extended
12589 opcode. If the address depends on the size of this
12590 instruction, this can lead to a loop, so we arrange to always
12591 use an extended opcode. We only check this when we are in
12592 the main relaxation loop, when SEC is NULL. */
12593 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12595 fragp->fr_subtype =
12596 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12600 /* If we are about to mark a frag as extended because the value
12601 is precisely maxtiny + 1, then there is a chance of an
12602 infinite loop as in the following code:
12607 In this case when the la is extended, foo is 0x3fc bytes
12608 away, so the la can be shrunk, but then foo is 0x400 away, so
12609 the la must be extended. To avoid this loop, we mark the
12610 frag as extended if it was small, and is about to become
12611 extended with a value of maxtiny + 1. */
12612 if (val == ((maxtiny + 1) << op->shift)
12613 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12616 fragp->fr_subtype =
12617 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12621 else if (symsec != absolute_section && sec != NULL)
12622 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12624 if ((val & ((1 << op->shift) - 1)) != 0
12625 || val < (mintiny << op->shift)
12626 || val > (maxtiny << op->shift))
12632 /* Compute the length of a branch sequence, and adjust the
12633 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12634 worst-case length is computed, with UPDATE being used to indicate
12635 whether an unconditional (-1), branch-likely (+1) or regular (0)
12636 branch is to be computed. */
12638 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12640 bfd_boolean toofar;
12644 && S_IS_DEFINED (fragp->fr_symbol)
12645 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12650 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12652 addr = fragp->fr_address + fragp->fr_fix + 4;
12656 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12659 /* If the symbol is not defined or it's in a different segment,
12660 assume the user knows what's going on and emit a short
12666 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12668 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12669 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12670 RELAX_BRANCH_LINK (fragp->fr_subtype),
12676 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12679 if (mips_pic != NO_PIC)
12681 /* Additional space for PIC loading of target address. */
12683 if (mips_opts.isa == ISA_MIPS1)
12684 /* Additional space for $at-stabilizing nop. */
12688 /* If branch is conditional. */
12689 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12696 /* Estimate the size of a frag before relaxing. Unless this is the
12697 mips16, we are not really relaxing here, and the final size is
12698 encoded in the subtype information. For the mips16, we have to
12699 decide whether we are using an extended opcode or not. */
12702 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12706 if (RELAX_BRANCH_P (fragp->fr_subtype))
12709 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12711 return fragp->fr_var;
12714 if (RELAX_MIPS16_P (fragp->fr_subtype))
12715 /* We don't want to modify the EXTENDED bit here; it might get us
12716 into infinite loops. We change it only in mips_relax_frag(). */
12717 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12719 if (mips_pic == NO_PIC)
12720 change = nopic_need_relax (fragp->fr_symbol, 0);
12721 else if (mips_pic == SVR4_PIC)
12722 change = pic_need_relax (fragp->fr_symbol, segtype);
12728 fragp->fr_subtype |= RELAX_USE_SECOND;
12729 return -RELAX_FIRST (fragp->fr_subtype);
12732 return -RELAX_SECOND (fragp->fr_subtype);
12735 /* This is called to see whether a reloc against a defined symbol
12736 should be converted into a reloc against a section. */
12739 mips_fix_adjustable (fixS *fixp)
12741 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12742 about the format of the offset in the .o file. */
12743 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12746 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12747 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12750 if (fixp->fx_addsy == NULL)
12753 /* If symbol SYM is in a mergeable section, relocations of the form
12754 SYM + 0 can usually be made section-relative. The mergeable data
12755 is then identified by the section offset rather than by the symbol.
12757 However, if we're generating REL LO16 relocations, the offset is split
12758 between the LO16 and parterning high part relocation. The linker will
12759 need to recalculate the complete offset in order to correctly identify
12762 The linker has traditionally not looked for the parterning high part
12763 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12764 placed anywhere. Rather than break backwards compatibility by changing
12765 this, it seems better not to force the issue, and instead keep the
12766 original symbol. This will work with either linker behavior. */
12767 if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
12768 && HAVE_IN_PLACE_ADDENDS
12769 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
12773 /* Don't adjust relocations against mips16 symbols, so that the linker
12774 can find them if it needs to set up a stub. */
12775 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12776 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12777 && fixp->fx_subsy == NULL)
12784 /* Translate internal representation of relocation info to BFD target
12788 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12790 static arelent *retval[4];
12792 bfd_reloc_code_real_type code;
12794 memset (retval, 0, sizeof(retval));
12795 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
12796 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12797 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12798 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12800 assert (! fixp->fx_pcrel);
12801 reloc->addend = fixp->fx_addnumber;
12803 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12804 entry to be used in the relocation's section offset. */
12805 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12807 reloc->address = reloc->addend;
12811 code = fixp->fx_r_type;
12813 /* To support a PC relative reloc, we used a Cygnus extension.
12814 We check for that here to make sure that we don't let such a
12815 reloc escape normally. (FIXME: This was formerly used by
12816 embedded-PIC support, but is now used by branch handling in
12817 general. That probably should be fixed.) */
12818 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12819 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12820 && code == BFD_RELOC_16_PCREL_S2)
12821 reloc->howto = NULL;
12823 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12825 if (reloc->howto == NULL)
12827 as_bad_where (fixp->fx_file, fixp->fx_line,
12828 _("Can not represent %s relocation in this object file format"),
12829 bfd_get_reloc_code_name (code));
12836 /* Relax a machine dependent frag. This returns the amount by which
12837 the current size of the frag should change. */
12840 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
12842 if (RELAX_BRANCH_P (fragp->fr_subtype))
12844 offsetT old_var = fragp->fr_var;
12846 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
12848 return fragp->fr_var - old_var;
12851 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12854 if (mips16_extended_frag (fragp, NULL, stretch))
12856 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12858 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12863 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12865 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12872 /* Convert a machine dependent frag. */
12875 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
12877 if (RELAX_BRANCH_P (fragp->fr_subtype))
12880 unsigned long insn;
12884 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
12886 if (target_big_endian)
12887 insn = bfd_getb32 (buf);
12889 insn = bfd_getl32 (buf);
12891 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12893 /* We generate a fixup instead of applying it right now
12894 because, if there are linker relaxations, we're going to
12895 need the relocations. */
12896 exp.X_op = O_symbol;
12897 exp.X_add_symbol = fragp->fr_symbol;
12898 exp.X_add_number = fragp->fr_offset;
12900 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
12902 BFD_RELOC_16_PCREL_S2);
12903 fixp->fx_file = fragp->fr_file;
12904 fixp->fx_line = fragp->fr_line;
12906 md_number_to_chars (buf, insn, 4);
12913 as_warn_where (fragp->fr_file, fragp->fr_line,
12914 _("relaxed out-of-range branch into a jump"));
12916 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
12919 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12921 /* Reverse the branch. */
12922 switch ((insn >> 28) & 0xf)
12925 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12926 have the condition reversed by tweaking a single
12927 bit, and their opcodes all have 0x4???????. */
12928 assert ((insn & 0xf1000000) == 0x41000000);
12929 insn ^= 0x00010000;
12933 /* bltz 0x04000000 bgez 0x04010000
12934 bltzal 0x04100000 bgezal 0x04110000 */
12935 assert ((insn & 0xfc0e0000) == 0x04000000);
12936 insn ^= 0x00010000;
12940 /* beq 0x10000000 bne 0x14000000
12941 blez 0x18000000 bgtz 0x1c000000 */
12942 insn ^= 0x04000000;
12950 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
12952 /* Clear the and-link bit. */
12953 assert ((insn & 0xfc1c0000) == 0x04100000);
12955 /* bltzal 0x04100000 bgezal 0x04110000
12956 bltzall 0x04120000 bgezall 0x04130000 */
12957 insn &= ~0x00100000;
12960 /* Branch over the branch (if the branch was likely) or the
12961 full jump (not likely case). Compute the offset from the
12962 current instruction to branch to. */
12963 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12967 /* How many bytes in instructions we've already emitted? */
12968 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12969 /* How many bytes in instructions from here to the end? */
12970 i = fragp->fr_var - i;
12972 /* Convert to instruction count. */
12974 /* Branch counts from the next instruction. */
12977 /* Branch over the jump. */
12978 md_number_to_chars (buf, insn, 4);
12982 md_number_to_chars (buf, 0, 4);
12985 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12987 /* beql $0, $0, 2f */
12989 /* Compute the PC offset from the current instruction to
12990 the end of the variable frag. */
12991 /* How many bytes in instructions we've already emitted? */
12992 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12993 /* How many bytes in instructions from here to the end? */
12994 i = fragp->fr_var - i;
12995 /* Convert to instruction count. */
12997 /* Don't decrement i, because we want to branch over the
13001 md_number_to_chars (buf, insn, 4);
13004 md_number_to_chars (buf, 0, 4);
13009 if (mips_pic == NO_PIC)
13012 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13013 ? 0x0c000000 : 0x08000000);
13014 exp.X_op = O_symbol;
13015 exp.X_add_symbol = fragp->fr_symbol;
13016 exp.X_add_number = fragp->fr_offset;
13018 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13019 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13020 fixp->fx_file = fragp->fr_file;
13021 fixp->fx_line = fragp->fr_line;
13023 md_number_to_chars (buf, insn, 4);
13028 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13029 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13030 exp.X_op = O_symbol;
13031 exp.X_add_symbol = fragp->fr_symbol;
13032 exp.X_add_number = fragp->fr_offset;
13034 if (fragp->fr_offset)
13036 exp.X_add_symbol = make_expr_symbol (&exp);
13037 exp.X_add_number = 0;
13040 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13041 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13042 fixp->fx_file = fragp->fr_file;
13043 fixp->fx_line = fragp->fr_line;
13045 md_number_to_chars (buf, insn, 4);
13048 if (mips_opts.isa == ISA_MIPS1)
13051 md_number_to_chars (buf, 0, 4);
13055 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13056 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13058 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13059 4, &exp, 0, BFD_RELOC_LO16);
13060 fixp->fx_file = fragp->fr_file;
13061 fixp->fx_line = fragp->fr_line;
13063 md_number_to_chars (buf, insn, 4);
13067 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13072 md_number_to_chars (buf, insn, 4);
13077 assert (buf == (bfd_byte *)fragp->fr_literal
13078 + fragp->fr_fix + fragp->fr_var);
13080 fragp->fr_fix += fragp->fr_var;
13085 if (RELAX_MIPS16_P (fragp->fr_subtype))
13088 register const struct mips16_immed_operand *op;
13089 bfd_boolean small, ext;
13092 unsigned long insn;
13093 bfd_boolean use_extend;
13094 unsigned short extend;
13096 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13097 op = mips16_immed_operands;
13098 while (op->type != type)
13101 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13112 resolve_symbol_value (fragp->fr_symbol);
13113 val = S_GET_VALUE (fragp->fr_symbol);
13118 addr = fragp->fr_address + fragp->fr_fix;
13120 /* The rules for the base address of a PC relative reloc are
13121 complicated; see mips16_extended_frag. */
13122 if (type == 'p' || type == 'q')
13127 /* Ignore the low bit in the target, since it will be
13128 set for a text label. */
13129 if ((val & 1) != 0)
13132 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13134 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13137 addr &= ~ (addressT) ((1 << op->shift) - 1);
13140 /* Make sure the section winds up with the alignment we have
13143 record_alignment (asec, op->shift);
13147 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13148 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13149 as_warn_where (fragp->fr_file, fragp->fr_line,
13150 _("extended instruction in delay slot"));
13152 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13154 if (target_big_endian)
13155 insn = bfd_getb16 (buf);
13157 insn = bfd_getl16 (buf);
13159 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13160 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13161 small, ext, &insn, &use_extend, &extend);
13165 md_number_to_chars (buf, 0xf000 | extend, 2);
13166 fragp->fr_fix += 2;
13170 md_number_to_chars (buf, insn, 2);
13171 fragp->fr_fix += 2;
13179 first = RELAX_FIRST (fragp->fr_subtype);
13180 second = RELAX_SECOND (fragp->fr_subtype);
13181 fixp = (fixS *) fragp->fr_opcode;
13183 /* Possibly emit a warning if we've chosen the longer option. */
13184 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13185 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13187 const char *msg = macro_warning (fragp->fr_subtype);
13189 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13192 /* Go through all the fixups for the first sequence. Disable them
13193 (by marking them as done) if we're going to use the second
13194 sequence instead. */
13196 && fixp->fx_frag == fragp
13197 && fixp->fx_where < fragp->fr_fix - second)
13199 if (fragp->fr_subtype & RELAX_USE_SECOND)
13201 fixp = fixp->fx_next;
13204 /* Go through the fixups for the second sequence. Disable them if
13205 we're going to use the first sequence, otherwise adjust their
13206 addresses to account for the relaxation. */
13207 while (fixp && fixp->fx_frag == fragp)
13209 if (fragp->fr_subtype & RELAX_USE_SECOND)
13210 fixp->fx_where -= first;
13213 fixp = fixp->fx_next;
13216 /* Now modify the frag contents. */
13217 if (fragp->fr_subtype & RELAX_USE_SECOND)
13221 start = fragp->fr_literal + fragp->fr_fix - first - second;
13222 memmove (start, start + first, second);
13223 fragp->fr_fix -= first;
13226 fragp->fr_fix -= second;
13232 /* This function is called after the relocs have been generated.
13233 We've been storing mips16 text labels as odd. Here we convert them
13234 back to even for the convenience of the debugger. */
13237 mips_frob_file_after_relocs (void)
13240 unsigned int count, i;
13242 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13245 syms = bfd_get_outsymbols (stdoutput);
13246 count = bfd_get_symcount (stdoutput);
13247 for (i = 0; i < count; i++, syms++)
13249 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13250 && ((*syms)->value & 1) != 0)
13252 (*syms)->value &= ~1;
13253 /* If the symbol has an odd size, it was probably computed
13254 incorrectly, so adjust that as well. */
13255 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13256 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13263 /* This function is called whenever a label is defined. It is used
13264 when handling branch delays; if a branch has a label, we assume we
13265 can not move it. */
13268 mips_define_label (symbolS *sym)
13270 struct insn_label_list *l;
13272 if (free_insn_labels == NULL)
13273 l = (struct insn_label_list *) xmalloc (sizeof *l);
13276 l = free_insn_labels;
13277 free_insn_labels = l->next;
13281 l->next = insn_labels;
13285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13287 /* Some special processing for a MIPS ELF file. */
13290 mips_elf_final_processing (void)
13292 /* Write out the register information. */
13293 if (mips_abi != N64_ABI)
13297 s.ri_gprmask = mips_gprmask;
13298 s.ri_cprmask[0] = mips_cprmask[0];
13299 s.ri_cprmask[1] = mips_cprmask[1];
13300 s.ri_cprmask[2] = mips_cprmask[2];
13301 s.ri_cprmask[3] = mips_cprmask[3];
13302 /* The gp_value field is set by the MIPS ELF backend. */
13304 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13305 ((Elf32_External_RegInfo *)
13306 mips_regmask_frag));
13310 Elf64_Internal_RegInfo s;
13312 s.ri_gprmask = mips_gprmask;
13314 s.ri_cprmask[0] = mips_cprmask[0];
13315 s.ri_cprmask[1] = mips_cprmask[1];
13316 s.ri_cprmask[2] = mips_cprmask[2];
13317 s.ri_cprmask[3] = mips_cprmask[3];
13318 /* The gp_value field is set by the MIPS ELF backend. */
13320 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13321 ((Elf64_External_RegInfo *)
13322 mips_regmask_frag));
13325 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13326 sort of BFD interface for this. */
13327 if (mips_any_noreorder)
13328 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13329 if (mips_pic != NO_PIC)
13331 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13332 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13335 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13337 /* Set MIPS ELF flags for ASEs. */
13338 if (file_ase_mips16)
13339 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13340 #if 0 /* XXX FIXME */
13341 if (file_ase_mips3d)
13342 elf_elfheader (stdoutput)->e_flags |= ???;
13345 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13347 /* Set the MIPS ELF ABI flags. */
13348 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13349 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13350 else if (mips_abi == O64_ABI)
13351 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13352 else if (mips_abi == EABI_ABI)
13354 if (!file_mips_gp32)
13355 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13357 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13359 else if (mips_abi == N32_ABI)
13360 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13362 /* Nothing to do for N64_ABI. */
13364 if (mips_32bitmode)
13365 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13368 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13370 typedef struct proc {
13372 unsigned long reg_mask;
13373 unsigned long reg_offset;
13374 unsigned long fpreg_mask;
13375 unsigned long fpreg_offset;
13376 unsigned long frame_offset;
13377 unsigned long frame_reg;
13378 unsigned long pc_reg;
13381 static procS cur_proc;
13382 static procS *cur_proc_ptr;
13383 static int numprocs;
13385 /* Fill in an rs_align_code fragment. */
13388 mips_handle_align (fragS *fragp)
13390 if (fragp->fr_type != rs_align_code)
13393 if (mips_opts.mips16)
13395 static const unsigned char be_nop[] = { 0x65, 0x00 };
13396 static const unsigned char le_nop[] = { 0x00, 0x65 };
13401 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13402 p = fragp->fr_literal + fragp->fr_fix;
13410 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13414 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13418 md_obj_begin (void)
13425 /* check for premature end, nesting errors, etc */
13427 as_warn (_("missing .end at end of assembly"));
13436 if (*input_line_pointer == '-')
13438 ++input_line_pointer;
13441 if (!ISDIGIT (*input_line_pointer))
13442 as_bad (_("expected simple number"));
13443 if (input_line_pointer[0] == '0')
13445 if (input_line_pointer[1] == 'x')
13447 input_line_pointer += 2;
13448 while (ISXDIGIT (*input_line_pointer))
13451 val |= hex_value (*input_line_pointer++);
13453 return negative ? -val : val;
13457 ++input_line_pointer;
13458 while (ISDIGIT (*input_line_pointer))
13461 val |= *input_line_pointer++ - '0';
13463 return negative ? -val : val;
13466 if (!ISDIGIT (*input_line_pointer))
13468 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13469 *input_line_pointer, *input_line_pointer);
13470 as_warn (_("invalid number"));
13473 while (ISDIGIT (*input_line_pointer))
13476 val += *input_line_pointer++ - '0';
13478 return negative ? -val : val;
13481 /* The .file directive; just like the usual .file directive, but there
13482 is an initial number which is the ECOFF file index. In the non-ECOFF
13483 case .file implies DWARF-2. */
13486 s_mips_file (int x ATTRIBUTE_UNUSED)
13488 static int first_file_directive = 0;
13490 if (ECOFF_DEBUGGING)
13499 filename = dwarf2_directive_file (0);
13501 /* Versions of GCC up to 3.1 start files with a ".file"
13502 directive even for stabs output. Make sure that this
13503 ".file" is handled. Note that you need a version of GCC
13504 after 3.1 in order to support DWARF-2 on MIPS. */
13505 if (filename != NULL && ! first_file_directive)
13507 (void) new_logical_line (filename, -1);
13508 s_app_file_string (filename);
13510 first_file_directive = 1;
13514 /* The .loc directive, implying DWARF-2. */
13517 s_mips_loc (int x ATTRIBUTE_UNUSED)
13519 if (!ECOFF_DEBUGGING)
13520 dwarf2_directive_loc (0);
13523 /* The .end directive. */
13526 s_mips_end (int x ATTRIBUTE_UNUSED)
13530 /* Following functions need their own .frame and .cprestore directives. */
13531 mips_frame_reg_valid = 0;
13532 mips_cprestore_valid = 0;
13534 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13537 demand_empty_rest_of_line ();
13542 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13543 as_warn (_(".end not in text section"));
13547 as_warn (_(".end directive without a preceding .ent directive."));
13548 demand_empty_rest_of_line ();
13554 assert (S_GET_NAME (p));
13555 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13556 as_warn (_(".end symbol does not match .ent symbol."));
13558 if (debug_type == DEBUG_STABS)
13559 stabs_generate_asm_endfunc (S_GET_NAME (p),
13563 as_warn (_(".end directive missing or unknown symbol"));
13566 /* Generate a .pdr section. */
13567 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13570 segT saved_seg = now_seg;
13571 subsegT saved_subseg = now_subseg;
13576 dot = frag_now_fix ();
13578 #ifdef md_flush_pending_output
13579 md_flush_pending_output ();
13583 subseg_set (pdr_seg, 0);
13585 /* Write the symbol. */
13586 exp.X_op = O_symbol;
13587 exp.X_add_symbol = p;
13588 exp.X_add_number = 0;
13589 emit_expr (&exp, 4);
13591 fragp = frag_more (7 * 4);
13593 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13594 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13595 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13596 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13597 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13598 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13599 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13601 subseg_set (saved_seg, saved_subseg);
13603 #endif /* OBJ_ELF */
13605 cur_proc_ptr = NULL;
13608 /* The .aent and .ent directives. */
13611 s_mips_ent (int aent)
13615 symbolP = get_symbol ();
13616 if (*input_line_pointer == ',')
13617 ++input_line_pointer;
13618 SKIP_WHITESPACE ();
13619 if (ISDIGIT (*input_line_pointer)
13620 || *input_line_pointer == '-')
13623 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13624 as_warn (_(".ent or .aent not in text section."));
13626 if (!aent && cur_proc_ptr)
13627 as_warn (_("missing .end"));
13631 /* This function needs its own .frame and .cprestore directives. */
13632 mips_frame_reg_valid = 0;
13633 mips_cprestore_valid = 0;
13635 cur_proc_ptr = &cur_proc;
13636 memset (cur_proc_ptr, '\0', sizeof (procS));
13638 cur_proc_ptr->isym = symbolP;
13640 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13644 if (debug_type == DEBUG_STABS)
13645 stabs_generate_asm_func (S_GET_NAME (symbolP),
13646 S_GET_NAME (symbolP));
13649 demand_empty_rest_of_line ();
13652 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13653 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13654 s_mips_frame is used so that we can set the PDR information correctly.
13655 We can't use the ecoff routines because they make reference to the ecoff
13656 symbol table (in the mdebug section). */
13659 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13662 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13666 if (cur_proc_ptr == (procS *) NULL)
13668 as_warn (_(".frame outside of .ent"));
13669 demand_empty_rest_of_line ();
13673 cur_proc_ptr->frame_reg = tc_get_register (1);
13675 SKIP_WHITESPACE ();
13676 if (*input_line_pointer++ != ','
13677 || get_absolute_expression_and_terminator (&val) != ',')
13679 as_warn (_("Bad .frame directive"));
13680 --input_line_pointer;
13681 demand_empty_rest_of_line ();
13685 cur_proc_ptr->frame_offset = val;
13686 cur_proc_ptr->pc_reg = tc_get_register (0);
13688 demand_empty_rest_of_line ();
13691 #endif /* OBJ_ELF */
13695 /* The .fmask and .mask directives. If the mdebug section is present
13696 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13697 embedded targets, s_mips_mask is used so that we can set the PDR
13698 information correctly. We can't use the ecoff routines because they
13699 make reference to the ecoff symbol table (in the mdebug section). */
13702 s_mips_mask (int reg_type)
13705 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13709 if (cur_proc_ptr == (procS *) NULL)
13711 as_warn (_(".mask/.fmask outside of .ent"));
13712 demand_empty_rest_of_line ();
13716 if (get_absolute_expression_and_terminator (&mask) != ',')
13718 as_warn (_("Bad .mask/.fmask directive"));
13719 --input_line_pointer;
13720 demand_empty_rest_of_line ();
13724 off = get_absolute_expression ();
13726 if (reg_type == 'F')
13728 cur_proc_ptr->fpreg_mask = mask;
13729 cur_proc_ptr->fpreg_offset = off;
13733 cur_proc_ptr->reg_mask = mask;
13734 cur_proc_ptr->reg_offset = off;
13737 demand_empty_rest_of_line ();
13740 #endif /* OBJ_ELF */
13741 s_ignore (reg_type);
13744 /* The .loc directive. */
13754 assert (now_seg == text_section);
13756 lineno = get_number ();
13757 addroff = frag_now_fix ();
13759 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13760 S_SET_TYPE (symbolP, N_SLINE);
13761 S_SET_OTHER (symbolP, 0);
13762 S_SET_DESC (symbolP, lineno);
13763 symbolP->sy_segment = now_seg;
13767 /* A table describing all the processors gas knows about. Names are
13768 matched in the order listed.
13770 To ease comparison, please keep this table in the same order as
13771 gcc's mips_cpu_info_table[]. */
13772 static const struct mips_cpu_info mips_cpu_info_table[] =
13774 /* Entries for generic ISAs */
13775 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13776 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13777 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13778 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13779 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13780 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13781 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
13782 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13783 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
13786 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13787 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13788 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13791 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13794 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13795 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13796 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13797 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13798 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
13799 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
13800 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
13801 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13802 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13803 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13804 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13805 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13808 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13809 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13810 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13811 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13812 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
13813 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
13814 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13815 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13816 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13817 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13818 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13819 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
13820 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
13823 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
13824 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13825 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13828 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13829 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13831 /* Broadcom SB-1 CPU core */
13832 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13839 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13840 with a final "000" replaced by "k". Ignore case.
13842 Note: this function is shared between GCC and GAS. */
13845 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13847 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13848 given++, canonical++;
13850 return ((*given == 0 && *canonical == 0)
13851 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13855 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13856 CPU name. We've traditionally allowed a lot of variation here.
13858 Note: this function is shared between GCC and GAS. */
13861 mips_matching_cpu_name_p (const char *canonical, const char *given)
13863 /* First see if the name matches exactly, or with a final "000"
13864 turned into "k". */
13865 if (mips_strict_matching_cpu_name_p (canonical, given))
13868 /* If not, try comparing based on numerical designation alone.
13869 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13870 if (TOLOWER (*given) == 'r')
13872 if (!ISDIGIT (*given))
13875 /* Skip over some well-known prefixes in the canonical name,
13876 hoping to find a number there too. */
13877 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13879 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13881 else if (TOLOWER (canonical[0]) == 'r')
13884 return mips_strict_matching_cpu_name_p (canonical, given);
13888 /* Parse an option that takes the name of a processor as its argument.
13889 OPTION is the name of the option and CPU_STRING is the argument.
13890 Return the corresponding processor enumeration if the CPU_STRING is
13891 recognized, otherwise report an error and return null.
13893 A similar function exists in GCC. */
13895 static const struct mips_cpu_info *
13896 mips_parse_cpu (const char *option, const char *cpu_string)
13898 const struct mips_cpu_info *p;
13900 /* 'from-abi' selects the most compatible architecture for the given
13901 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13902 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13903 version. Look first at the -mgp options, if given, otherwise base
13904 the choice on MIPS_DEFAULT_64BIT.
13906 Treat NO_ABI like the EABIs. One reason to do this is that the
13907 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13908 architecture. This code picks MIPS I for 'mips' and MIPS III for
13909 'mips64', just as we did in the days before 'from-abi'. */
13910 if (strcasecmp (cpu_string, "from-abi") == 0)
13912 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13913 return mips_cpu_info_from_isa (ISA_MIPS1);
13915 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13916 return mips_cpu_info_from_isa (ISA_MIPS3);
13918 if (file_mips_gp32 >= 0)
13919 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13921 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13926 /* 'default' has traditionally been a no-op. Probably not very useful. */
13927 if (strcasecmp (cpu_string, "default") == 0)
13930 for (p = mips_cpu_info_table; p->name != 0; p++)
13931 if (mips_matching_cpu_name_p (p->name, cpu_string))
13934 as_bad ("Bad value (%s) for %s", cpu_string, option);
13938 /* Return the canonical processor information for ISA (a member of the
13939 ISA_MIPS* enumeration). */
13941 static const struct mips_cpu_info *
13942 mips_cpu_info_from_isa (int isa)
13946 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13947 if (mips_cpu_info_table[i].is_isa
13948 && isa == mips_cpu_info_table[i].isa)
13949 return (&mips_cpu_info_table[i]);
13954 static const struct mips_cpu_info *
13955 mips_cpu_info_from_arch (int arch)
13959 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13960 if (arch == mips_cpu_info_table[i].cpu)
13961 return (&mips_cpu_info_table[i]);
13967 show (FILE *stream, const char *string, int *col_p, int *first_p)
13971 fprintf (stream, "%24s", "");
13976 fprintf (stream, ", ");
13980 if (*col_p + strlen (string) > 72)
13982 fprintf (stream, "\n%24s", "");
13986 fprintf (stream, "%s", string);
13987 *col_p += strlen (string);
13993 md_show_usage (FILE *stream)
13998 fprintf (stream, _("\
14000 -EB generate big endian output\n\
14001 -EL generate little endian output\n\
14002 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14003 -G NUM allow referencing objects up to NUM bytes\n\
14004 implicitly with the gp register [default 8]\n"));
14005 fprintf (stream, _("\
14006 -mips1 generate MIPS ISA I instructions\n\
14007 -mips2 generate MIPS ISA II instructions\n\
14008 -mips3 generate MIPS ISA III instructions\n\
14009 -mips4 generate MIPS ISA IV instructions\n\
14010 -mips5 generate MIPS ISA V instructions\n\
14011 -mips32 generate MIPS32 ISA instructions\n\
14012 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14013 -mips64 generate MIPS64 ISA instructions\n\
14014 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14015 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14019 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14020 show (stream, mips_cpu_info_table[i].name, &column, &first);
14021 show (stream, "from-abi", &column, &first);
14022 fputc ('\n', stream);
14024 fprintf (stream, _("\
14025 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14026 -no-mCPU don't generate code specific to CPU.\n\
14027 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14031 show (stream, "3900", &column, &first);
14032 show (stream, "4010", &column, &first);
14033 show (stream, "4100", &column, &first);
14034 show (stream, "4650", &column, &first);
14035 fputc ('\n', stream);
14037 fprintf (stream, _("\
14038 -mips16 generate mips16 instructions\n\
14039 -no-mips16 do not generate mips16 instructions\n"));
14040 fprintf (stream, _("\
14041 -mfix-vr4120 work around certain VR4120 errata\n\
14042 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14043 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14044 -O0 remove unneeded NOPs, do not swap branches\n\
14045 -O remove unneeded NOPs and swap branches\n\
14046 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14047 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14048 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14050 fprintf (stream, _("\
14051 -KPIC, -call_shared generate SVR4 position independent code\n\
14052 -non_shared do not generate position independent code\n\
14053 -xgot assume a 32 bit GOT\n\
14054 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14055 -mabi=ABI create ABI conformant object file for:\n"));
14059 show (stream, "32", &column, &first);
14060 show (stream, "o64", &column, &first);
14061 show (stream, "n32", &column, &first);
14062 show (stream, "64", &column, &first);
14063 show (stream, "eabi", &column, &first);
14065 fputc ('\n', stream);
14067 fprintf (stream, _("\
14068 -32 create o32 ABI object file (default)\n\
14069 -n32 create n32 ABI object file\n\
14070 -64 create 64 ABI object file\n"));
14075 mips_dwarf2_format (void)
14077 if (mips_abi == N64_ABI)
14080 return dwarf2_format_64bit_irix;
14082 return dwarf2_format_64bit;
14086 return dwarf2_format_32bit;
14090 mips_dwarf2_addr_size (void)
14092 if (mips_abi == N64_ABI)