1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32 = -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32 = -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float = 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float = 0;
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
296 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
298 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask;
305 unsigned long mips_cprmask[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa = ISA_UNKNOWN;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2 \
354 || mips_opts.micromips)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2 \
364 || mips_opts.micromips)
366 /* True if -mmt was passed or implied by arguments passed on the
367 command line (e.g., by -march). */
368 static int file_ase_mt;
370 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
371 || mips_opts.isa == ISA_MIPS64R2)
373 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
374 || mips_opts.isa == ISA_MIPS64R2 \
375 || mips_opts.micromips)
377 /* The argument of the -march= flag. The architecture we are assembling. */
378 static int file_mips_arch = CPU_UNKNOWN;
379 static const char *mips_arch_string;
381 /* The argument of the -mtune= flag. The architecture for which we
383 static int mips_tune = CPU_UNKNOWN;
384 static const char *mips_tune_string;
386 /* True when generating 32-bit code for a 64-bit processor. */
387 static int mips_32bitmode = 0;
389 /* True if the given ABI requires 32-bit registers. */
390 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
392 /* Likewise 64-bit registers. */
393 #define ABI_NEEDS_64BIT_REGS(ABI) \
395 || (ABI) == N64_ABI \
398 /* Return true if ISA supports 64 bit wide gp registers. */
399 #define ISA_HAS_64BIT_REGS(ISA) \
400 ((ISA) == ISA_MIPS3 \
401 || (ISA) == ISA_MIPS4 \
402 || (ISA) == ISA_MIPS5 \
403 || (ISA) == ISA_MIPS64 \
404 || (ISA) == ISA_MIPS64R2)
406 /* Return true if ISA supports 64 bit wide float registers. */
407 #define ISA_HAS_64BIT_FPRS(ISA) \
408 ((ISA) == ISA_MIPS3 \
409 || (ISA) == ISA_MIPS4 \
410 || (ISA) == ISA_MIPS5 \
411 || (ISA) == ISA_MIPS32R2 \
412 || (ISA) == ISA_MIPS64 \
413 || (ISA) == ISA_MIPS64R2)
415 /* Return true if ISA supports 64-bit right rotate (dror et al.)
417 #define ISA_HAS_DROR(ISA) \
418 ((ISA) == ISA_MIPS64R2 \
419 || (mips_opts.micromips \
420 && ISA_HAS_64BIT_REGS (ISA)) \
423 /* Return true if ISA supports 32-bit right rotate (ror et al.)
425 #define ISA_HAS_ROR(ISA) \
426 ((ISA) == ISA_MIPS32R2 \
427 || (ISA) == ISA_MIPS64R2 \
428 || mips_opts.ase_smartmips \
429 || mips_opts.micromips \
432 /* Return true if ISA supports single-precision floats in odd registers. */
433 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
434 ((ISA) == ISA_MIPS32 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports move to/from high part of a 64-bit
440 floating-point register. */
441 #define ISA_HAS_MXHC1(ISA) \
442 ((ISA) == ISA_MIPS32R2 \
443 || (ISA) == ISA_MIPS64R2)
445 #define HAVE_32BIT_GPRS \
446 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
448 #define HAVE_32BIT_FPRS \
449 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
451 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
452 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
454 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
456 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
458 /* True if relocations are stored in-place. */
459 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
461 /* The ABI-derived address size. */
462 #define HAVE_64BIT_ADDRESSES \
463 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
464 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
466 /* The size of symbolic constants (i.e., expressions of the form
467 "SYMBOL" or "SYMBOL + OFFSET"). */
468 #define HAVE_32BIT_SYMBOLS \
469 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
470 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
472 /* Addresses are loaded in different ways, depending on the address size
473 in use. The n32 ABI Documentation also mandates the use of additions
474 with overflow checking, but existing implementations don't follow it. */
475 #define ADDRESS_ADD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
478 #define ADDRESS_ADDI_INSN \
479 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
481 #define ADDRESS_LOAD_INSN \
482 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
484 #define ADDRESS_STORE_INSN \
485 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
487 /* Return true if the given CPU supports the MIPS16 ASE. */
488 #define CPU_HAS_MIPS16(cpu) \
489 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
490 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
492 /* Return true if the given CPU supports the microMIPS ASE. */
493 #define CPU_HAS_MICROMIPS(cpu) 0
495 /* True if CPU has a dror instruction. */
496 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
498 /* True if CPU has a ror instruction. */
499 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
501 /* True if CPU is in the Octeon family */
502 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
504 /* True if CPU has seq/sne and seqi/snei instructions. */
505 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
507 /* True, if CPU has support for ldc1 and sdc1. */
508 #define CPU_HAS_LDC1_SDC1(CPU) \
509 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
511 /* True if mflo and mfhi can be immediately followed by instructions
512 which write to the HI and LO registers.
514 According to MIPS specifications, MIPS ISAs I, II, and III need
515 (at least) two instructions between the reads of HI/LO and
516 instructions which write them, and later ISAs do not. Contradicting
517 the MIPS specifications, some MIPS IV processor user manuals (e.g.
518 the UM for the NEC Vr5000) document needing the instructions between
519 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
520 MIPS64 and later ISAs to have the interlocks, plus any specific
521 earlier-ISA CPUs for which CPU documentation declares that the
522 instructions are really interlocked. */
523 #define hilo_interlocks \
524 (mips_opts.isa == ISA_MIPS32 \
525 || mips_opts.isa == ISA_MIPS32R2 \
526 || mips_opts.isa == ISA_MIPS64 \
527 || mips_opts.isa == ISA_MIPS64R2 \
528 || mips_opts.arch == CPU_R4010 \
529 || mips_opts.arch == CPU_R5900 \
530 || mips_opts.arch == CPU_R10000 \
531 || mips_opts.arch == CPU_R12000 \
532 || mips_opts.arch == CPU_R14000 \
533 || mips_opts.arch == CPU_R16000 \
534 || mips_opts.arch == CPU_RM7000 \
535 || mips_opts.arch == CPU_VR5500 \
536 || mips_opts.micromips \
539 /* Whether the processor uses hardware interlocks to protect reads
540 from the GPRs after they are loaded from memory, and thus does not
541 require nops to be inserted. This applies to instructions marked
542 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
543 level I and microMIPS mode instructions are always interlocked. */
544 #define gpr_interlocks \
545 (mips_opts.isa != ISA_MIPS1 \
546 || mips_opts.arch == CPU_R3900 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.micromips \
551 /* Whether the processor uses hardware interlocks to avoid delays
552 required by coprocessor instructions, and thus does not require
553 nops to be inserted. This applies to instructions marked
554 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
555 between instructions marked INSN_WRITE_COND_CODE and ones marked
556 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
557 levels I, II, and III and microMIPS mode instructions are always
559 /* Itbl support may require additional care here. */
560 #define cop_interlocks \
561 ((mips_opts.isa != ISA_MIPS1 \
562 && mips_opts.isa != ISA_MIPS2 \
563 && mips_opts.isa != ISA_MIPS3) \
564 || mips_opts.arch == CPU_R4300 \
565 || mips_opts.micromips \
568 /* Whether the processor uses hardware interlocks to protect reads
569 from coprocessor registers after they are loaded from memory, and
570 thus does not require nops to be inserted. This applies to
571 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
572 requires at MIPS ISA level I and microMIPS mode instructions are
573 always interlocked. */
574 #define cop_mem_interlocks \
575 (mips_opts.isa != ISA_MIPS1 \
576 || mips_opts.micromips \
579 /* Is this a mfhi or mflo instruction? */
580 #define MF_HILO_INSN(PINFO) \
581 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
583 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
584 has been selected. This implies, in particular, that addresses of text
585 labels have their LSB set. */
586 #define HAVE_CODE_COMPRESSION \
587 ((mips_opts.mips16 | mips_opts.micromips) != 0)
589 /* MIPS PIC level. */
591 enum mips_pic_level mips_pic;
593 /* 1 if we should generate 32 bit offsets from the $gp register in
594 SVR4_PIC mode. Currently has no meaning in other modes. */
595 static int mips_big_got = 0;
597 /* 1 if trap instructions should used for overflow rather than break
599 static int mips_trap = 0;
601 /* 1 if double width floating point constants should not be constructed
602 by assembling two single width halves into two single width floating
603 point registers which just happen to alias the double width destination
604 register. On some architectures this aliasing can be disabled by a bit
605 in the status register, and the setting of this bit cannot be determined
606 automatically at assemble time. */
607 static int mips_disable_float_construction;
609 /* Non-zero if any .set noreorder directives were used. */
611 static int mips_any_noreorder;
613 /* Non-zero if nops should be inserted when the register referenced in
614 an mfhi/mflo instruction is read in the next two instructions. */
615 static int mips_7000_hilo_fix;
617 /* The size of objects in the small data section. */
618 static unsigned int g_switch_value = 8;
619 /* Whether the -G option was used. */
620 static int g_switch_seen = 0;
625 /* If we can determine in advance that GP optimization won't be
626 possible, we can skip the relaxation stuff that tries to produce
627 GP-relative references. This makes delay slot optimization work
630 This function can only provide a guess, but it seems to work for
631 gcc output. It needs to guess right for gcc, otherwise gcc
632 will put what it thinks is a GP-relative instruction in a branch
635 I don't know if a fix is needed for the SVR4_PIC mode. I've only
636 fixed it for the non-PIC mode. KR 95/04/07 */
637 static int nopic_need_relax (symbolS *, int);
639 /* handle of the OPCODE hash table */
640 static struct hash_control *op_hash = NULL;
642 /* The opcode hash table we use for the mips16. */
643 static struct hash_control *mips16_op_hash = NULL;
645 /* The opcode hash table we use for the microMIPS ASE. */
646 static struct hash_control *micromips_op_hash = NULL;
648 /* This array holds the chars that always start a comment. If the
649 pre-processor is disabled, these aren't very useful */
650 const char comment_chars[] = "#";
652 /* This array holds the chars that only start a comment at the beginning of
653 a line. If the line seems to have the form '# 123 filename'
654 .line and .file directives will appear in the pre-processed output */
655 /* Note that input_file.c hand checks for '#' at the beginning of the
656 first line of the input file. This is because the compiler outputs
657 #NO_APP at the beginning of its output. */
658 /* Also note that C style comments are always supported. */
659 const char line_comment_chars[] = "#";
661 /* This array holds machine specific line separator characters. */
662 const char line_separator_chars[] = ";";
664 /* Chars that can be used to separate mant from exp in floating point nums */
665 const char EXP_CHARS[] = "eE";
667 /* Chars that mean this number is a floating point constant */
670 const char FLT_CHARS[] = "rRsSfFdDxXpP";
672 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
673 changed in read.c . Ideally it shouldn't have to know about it at all,
674 but nothing is ideal around here.
677 static char *insn_error;
679 static int auto_align = 1;
681 /* When outputting SVR4 PIC code, the assembler needs to know the
682 offset in the stack frame from which to restore the $gp register.
683 This is set by the .cprestore pseudo-op, and saved in this
685 static offsetT mips_cprestore_offset = -1;
687 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
688 more optimizations, it can use a register value instead of a memory-saved
689 offset and even an other register than $gp as global pointer. */
690 static offsetT mips_cpreturn_offset = -1;
691 static int mips_cpreturn_register = -1;
692 static int mips_gp_register = GP;
693 static int mips_gprel_offset = 0;
695 /* Whether mips_cprestore_offset has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_cprestore_valid = 0;
699 /* This is the register which holds the stack frame, as set by the
700 .frame pseudo-op. This is needed to implement .cprestore. */
701 static int mips_frame_reg = SP;
703 /* Whether mips_frame_reg has been set in the current function
704 (or whether it has already been warned about, if not). */
705 static int mips_frame_reg_valid = 0;
707 /* To output NOP instructions correctly, we need to keep information
708 about the previous two instructions. */
710 /* Whether we are optimizing. The default value of 2 means to remove
711 unneeded NOPs and swap branch instructions when possible. A value
712 of 1 means to not swap branches. A value of 0 means to always
714 static int mips_optimize = 2;
716 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
717 equivalent to seeing no -g option at all. */
718 static int mips_debug = 0;
720 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
721 #define MAX_VR4130_NOPS 4
723 /* The maximum number of NOPs needed to fill delay slots. */
724 #define MAX_DELAY_NOPS 2
726 /* The maximum number of NOPs needed for any purpose. */
729 /* A list of previous instructions, with index 0 being the most recent.
730 We need to look back MAX_NOPS instructions when filling delay slots
731 or working around processor errata. We need to look back one
732 instruction further if we're thinking about using history[0] to
733 fill a branch delay slot. */
734 static struct mips_cl_insn history[1 + MAX_NOPS];
736 /* Nop instructions used by emit_nop. */
737 static struct mips_cl_insn nop_insn;
738 static struct mips_cl_insn mips16_nop_insn;
739 static struct mips_cl_insn micromips_nop16_insn;
740 static struct mips_cl_insn micromips_nop32_insn;
742 /* The appropriate nop for the current mode. */
743 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
744 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
746 /* The size of NOP_INSN in bytes. */
747 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
749 /* If this is set, it points to a frag holding nop instructions which
750 were inserted before the start of a noreorder section. If those
751 nops turn out to be unnecessary, the size of the frag can be
753 static fragS *prev_nop_frag;
755 /* The number of nop instructions we created in prev_nop_frag. */
756 static int prev_nop_frag_holds;
758 /* The number of nop instructions that we know we need in
760 static int prev_nop_frag_required;
762 /* The number of instructions we've seen since prev_nop_frag. */
763 static int prev_nop_frag_since;
765 /* For ECOFF and ELF, relocations against symbols are done in two
766 parts, with a HI relocation and a LO relocation. Each relocation
767 has only 16 bits of space to store an addend. This means that in
768 order for the linker to handle carries correctly, it must be able
769 to locate both the HI and the LO relocation. This means that the
770 relocations must appear in order in the relocation table.
772 In order to implement this, we keep track of each unmatched HI
773 relocation. We then sort them so that they immediately precede the
774 corresponding LO relocation. */
779 struct mips_hi_fixup *next;
782 /* The section this fixup is in. */
786 /* The list of unmatched HI relocs. */
788 static struct mips_hi_fixup *mips_hi_fixup_list;
790 /* The frag containing the last explicit relocation operator.
791 Null if explicit relocations have not been used. */
793 static fragS *prev_reloc_op_frag;
795 /* Map normal MIPS register numbers to mips16 register numbers. */
797 #define X ILLEGAL_REG
798 static const int mips32_to_16_reg_map[] =
800 X, X, 2, 3, 4, 5, 6, 7,
801 X, X, X, X, X, X, X, X,
802 0, 1, X, X, X, X, X, X,
803 X, X, X, X, X, X, X, X
807 /* Map mips16 register numbers to normal MIPS register numbers. */
809 static const unsigned int mips16_to_32_reg_map[] =
811 16, 17, 2, 3, 4, 5, 6, 7
814 /* Map normal MIPS register numbers to microMIPS register numbers. */
816 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
824 #define X ILLEGAL_REG
825 /* reg type h: 4, 5, 6. */
826 static const int mips32_to_micromips_reg_h_map[] =
828 X, X, X, X, 4, 5, 6, X,
829 X, X, X, X, X, X, X, X,
830 X, X, X, X, X, X, X, X,
831 X, X, X, X, X, X, X, X
834 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
835 static const int mips32_to_micromips_reg_m_map[] =
837 0, X, 2, 3, X, X, X, X,
838 X, X, X, X, X, X, X, X,
839 4, 1, 5, 6, 7, X, X, X,
840 X, X, X, X, X, X, X, X
843 /* reg type q: 0, 2-7. 17. */
844 static const int mips32_to_micromips_reg_q_map[] =
846 0, X, 2, 3, 4, 5, 6, 7,
847 X, X, X, X, X, X, X, X,
848 X, 1, X, X, X, X, X, X,
849 X, X, X, X, X, X, X, X
852 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
855 /* Map microMIPS register numbers to normal MIPS register numbers. */
857 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
864 /* The microMIPS registers with type h. */
865 static const unsigned int micromips_to_32_reg_h_map[] =
867 5, 5, 6, 4, 4, 4, 4, 4
870 /* The microMIPS registers with type i. */
871 static const unsigned int micromips_to_32_reg_i_map[] =
873 6, 7, 7, 21, 22, 5, 6, 7
876 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
878 /* The microMIPS registers with type m. */
879 static const unsigned int micromips_to_32_reg_m_map[] =
881 0, 17, 2, 3, 16, 18, 19, 20
884 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
886 /* The microMIPS registers with type q. */
887 static const unsigned int micromips_to_32_reg_q_map[] =
889 0, 17, 2, 3, 4, 5, 6, 7
892 /* microMIPS imm type B. */
893 static const int micromips_imm_b_map[] =
895 1, 4, 8, 12, 16, 20, 24, -1
898 /* microMIPS imm type C. */
899 static const int micromips_imm_c_map[] =
901 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
904 /* Classifies the kind of instructions we're interested in when
905 implementing -mfix-vr4120. */
906 enum fix_vr4120_class
914 NUM_FIX_VR4120_CLASSES
917 /* ...likewise -mfix-loongson2f-jump. */
918 static bfd_boolean mips_fix_loongson2f_jump;
920 /* ...likewise -mfix-loongson2f-nop. */
921 static bfd_boolean mips_fix_loongson2f_nop;
923 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
924 static bfd_boolean mips_fix_loongson2f;
926 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
927 there must be at least one other instruction between an instruction
928 of type X and an instruction of type Y. */
929 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
931 /* True if -mfix-vr4120 is in force. */
932 static int mips_fix_vr4120;
934 /* ...likewise -mfix-vr4130. */
935 static int mips_fix_vr4130;
937 /* ...likewise -mfix-24k. */
938 static int mips_fix_24k;
940 /* ...likewise -mfix-cn63xxp1 */
941 static bfd_boolean mips_fix_cn63xxp1;
943 /* We don't relax branches by default, since this causes us to expand
944 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
945 fail to compute the offset before expanding the macro to the most
946 efficient expansion. */
948 static int mips_relax_branch;
950 /* The expansion of many macros depends on the type of symbol that
951 they refer to. For example, when generating position-dependent code,
952 a macro that refers to a symbol may have two different expansions,
953 one which uses GP-relative addresses and one which uses absolute
954 addresses. When generating SVR4-style PIC, a macro may have
955 different expansions for local and global symbols.
957 We handle these situations by generating both sequences and putting
958 them in variant frags. In position-dependent code, the first sequence
959 will be the GP-relative one and the second sequence will be the
960 absolute one. In SVR4 PIC, the first sequence will be for global
961 symbols and the second will be for local symbols.
963 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
964 SECOND are the lengths of the two sequences in bytes. These fields
965 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
966 the subtype has the following flags:
969 Set if it has been decided that we should use the second
970 sequence instead of the first.
973 Set in the first variant frag if the macro's second implementation
974 is longer than its first. This refers to the macro as a whole,
975 not an individual relaxation.
978 Set in the first variant frag if the macro appeared in a .set nomacro
979 block and if one alternative requires a warning but the other does not.
982 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
985 RELAX_DELAY_SLOT_16BIT
986 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
989 RELAX_DELAY_SLOT_SIZE_FIRST
990 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
991 the macro is of the wrong size for the branch delay slot.
993 RELAX_DELAY_SLOT_SIZE_SECOND
994 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
995 the macro is of the wrong size for the branch delay slot.
997 The frag's "opcode" points to the first fixup for relaxable code.
999 Relaxable macros are generated using a sequence such as:
1001 relax_start (SYMBOL);
1002 ... generate first expansion ...
1004 ... generate second expansion ...
1007 The code and fixups for the unwanted alternative are discarded
1008 by md_convert_frag. */
1009 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1011 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1012 #define RELAX_SECOND(X) ((X) & 0xff)
1013 #define RELAX_USE_SECOND 0x10000
1014 #define RELAX_SECOND_LONGER 0x20000
1015 #define RELAX_NOMACRO 0x40000
1016 #define RELAX_DELAY_SLOT 0x80000
1017 #define RELAX_DELAY_SLOT_16BIT 0x100000
1018 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1019 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1021 /* Branch without likely bit. If label is out of range, we turn:
1023 beq reg1, reg2, label
1033 with the following opcode replacements:
1040 bltzal <-> bgezal (with jal label instead of j label)
1042 Even though keeping the delay slot instruction in the delay slot of
1043 the branch would be more efficient, it would be very tricky to do
1044 correctly, because we'd have to introduce a variable frag *after*
1045 the delay slot instruction, and expand that instead. Let's do it
1046 the easy way for now, even if the branch-not-taken case now costs
1047 one additional instruction. Out-of-range branches are not supposed
1048 to be common, anyway.
1050 Branch likely. If label is out of range, we turn:
1052 beql reg1, reg2, label
1053 delay slot (annulled if branch not taken)
1062 delay slot (executed only if branch taken)
1065 It would be possible to generate a shorter sequence by losing the
1066 likely bit, generating something like:
1071 delay slot (executed only if branch taken)
1083 bltzall -> bgezal (with jal label instead of j label)
1084 bgezall -> bltzal (ditto)
1087 but it's not clear that it would actually improve performance. */
1088 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1089 ((relax_substateT) \
1092 | ((toofar) ? 0x20 : 0) \
1093 | ((link) ? 0x40 : 0) \
1094 | ((likely) ? 0x80 : 0) \
1095 | ((uncond) ? 0x100 : 0)))
1096 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1097 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1098 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1099 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1100 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1101 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1103 /* For mips16 code, we use an entirely different form of relaxation.
1104 mips16 supports two versions of most instructions which take
1105 immediate values: a small one which takes some small value, and a
1106 larger one which takes a 16 bit value. Since branches also follow
1107 this pattern, relaxing these values is required.
1109 We can assemble both mips16 and normal MIPS code in a single
1110 object. Therefore, we need to support this type of relaxation at
1111 the same time that we support the relaxation described above. We
1112 use the high bit of the subtype field to distinguish these cases.
1114 The information we store for this type of relaxation is the
1115 argument code found in the opcode file for this relocation, whether
1116 the user explicitly requested a small or extended form, and whether
1117 the relocation is in a jump or jal delay slot. That tells us the
1118 size of the value, and how it should be stored. We also store
1119 whether the fragment is considered to be extended or not. We also
1120 store whether this is known to be a branch to a different section,
1121 whether we have tried to relax this frag yet, and whether we have
1122 ever extended a PC relative fragment because of a shift count. */
1123 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1126 | ((small) ? 0x100 : 0) \
1127 | ((ext) ? 0x200 : 0) \
1128 | ((dslot) ? 0x400 : 0) \
1129 | ((jal_dslot) ? 0x800 : 0))
1130 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1131 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1132 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1133 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1134 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1135 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1136 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1137 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1138 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1139 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1140 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1141 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1143 /* For microMIPS code, we use relaxation similar to one we use for
1144 MIPS16 code. Some instructions that take immediate values support
1145 two encodings: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. As some branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both microMIPS and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use one of the high bits of the subtype field to distinguish these
1155 The information we store for this type of relaxation is the argument
1156 code found in the opcode file for this relocation, the register
1157 selected as the assembler temporary, whether the branch is
1158 unconditional, whether it is compact, whether it stores the link
1159 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1160 branches to a sequence of instructions is enabled, and whether the
1161 displacement of a branch is too large to fit as an immediate argument
1162 of a 16-bit and a 32-bit branch, respectively. */
1163 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((uncond) ? 0x2000 : 0) \
1169 | ((compact) ? 0x4000 : 0) \
1170 | ((link) ? 0x8000 : 0) \
1171 | ((relax32) ? 0x10000 : 0) \
1172 | ((toofar16) ? 0x20000 : 0) \
1173 | ((toofar32) ? 0x40000 : 0))
1174 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1175 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1176 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1177 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1178 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1179 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1180 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1182 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1185 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1189 /* Sign-extend 16-bit value X. */
1190 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1253 #define MIPS16_EXTEND (0xf000U << 16)
1255 /* Whether or not we are emitting a branch-likely macro. */
1256 static bfd_boolean emit_branch_likely_macro = FALSE;
1258 /* Global variables used when generating relaxable macros. See the
1259 comment above RELAX_ENCODE for more details about how relaxation
1262 /* 0 if we're not emitting a relaxable macro.
1263 1 if we're emitting the first of the two relaxation alternatives.
1264 2 if we're emitting the second alternative. */
1267 /* The first relaxable fixup in the current frag. (In other words,
1268 the first fixup that refers to relaxable code.) */
1271 /* sizes[0] says how many bytes of the first alternative are stored in
1272 the current frag. Likewise sizes[1] for the second alternative. */
1273 unsigned int sizes[2];
1275 /* The symbol on which the choice of sequence depends. */
1279 /* Global variables used to decide whether a macro needs a warning. */
1281 /* True if the macro is in a branch delay slot. */
1282 bfd_boolean delay_slot_p;
1284 /* Set to the length in bytes required if the macro is in a delay slot
1285 that requires a specific length of instruction, otherwise zero. */
1286 unsigned int delay_slot_length;
1288 /* For relaxable macros, sizes[0] is the length of the first alternative
1289 in bytes and sizes[1] is the length of the second alternative.
1290 For non-relaxable macros, both elements give the length of the
1292 unsigned int sizes[2];
1294 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1295 instruction of the first alternative in bytes and first_insn_sizes[1]
1296 is the length of the first instruction of the second alternative.
1297 For non-relaxable macros, both elements give the length of the first
1298 instruction in bytes.
1300 Set to zero if we haven't yet seen the first instruction. */
1301 unsigned int first_insn_sizes[2];
1303 /* For relaxable macros, insns[0] is the number of instructions for the
1304 first alternative and insns[1] is the number of instructions for the
1307 For non-relaxable macros, both elements give the number of
1308 instructions for the macro. */
1309 unsigned int insns[2];
1311 /* The first variant frag for this macro. */
1313 } mips_macro_warning;
1315 /* Prototypes for static functions. */
1317 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1319 static void append_insn
1320 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1321 bfd_boolean expansionp);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS *, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS *, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS *, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn * ip);
1330 static void mips16_macro (struct mips_cl_insn * ip);
1331 static void mips_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1333 static void mips16_immed
1334 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1335 unsigned int, unsigned long *);
1336 static size_t my_getSmallExpression
1337 (expressionS *, bfd_reloc_code_real_type *, char *);
1338 static void my_getExpression (expressionS *, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_tprelword (int);
1356 static void s_tpreldword (int);
1357 static void s_gpvalue (int);
1358 static void s_gpword (int);
1359 static void s_gpdword (int);
1360 static void s_cpadd (int);
1361 static void s_insn (int);
1362 static void md_obj_begin (void);
1363 static void md_obj_end (void);
1364 static void s_mips_ent (int);
1365 static void s_mips_end (int);
1366 static void s_mips_frame (int);
1367 static void s_mips_mask (int reg_type);
1368 static void s_mips_stab (int);
1369 static void s_mips_weakext (int);
1370 static void s_mips_file (int);
1371 static void s_mips_loc (int);
1372 static bfd_boolean pic_need_relax (symbolS *, asection *);
1373 static int relaxed_branch_length (fragS *, asection *, int);
1374 static int validate_mips_insn (const struct mips_opcode *);
1375 static int validate_micromips_insn (const struct mips_opcode *);
1376 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1377 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1379 /* Table and functions used to map between CPU/ISA names, and
1380 ISA levels, and CPU numbers. */
1382 struct mips_cpu_info
1384 const char *name; /* CPU or ISA name. */
1385 int flags; /* ASEs available, or ISA flag. */
1386 int isa; /* ISA level. */
1387 int cpu; /* CPU number (default CPU if ISA). */
1390 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1391 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1392 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1393 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1394 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1395 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1396 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1397 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1399 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1400 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1401 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1405 The following pseudo-ops from the Kane and Heinrich MIPS book
1406 should be defined here, but are currently unsupported: .alias,
1407 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1409 The following pseudo-ops from the Kane and Heinrich MIPS book are
1410 specific to the type of debugging information being generated, and
1411 should be defined by the object format: .aent, .begin, .bend,
1412 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1415 The following pseudo-ops from the Kane and Heinrich MIPS book are
1416 not MIPS CPU specific, but are also not specific to the object file
1417 format. This file is probably the best place to define them, but
1418 they are not currently supported: .asm0, .endr, .lab, .struct. */
1420 static const pseudo_typeS mips_pseudo_table[] =
1422 /* MIPS specific pseudo-ops. */
1423 {"option", s_option, 0},
1424 {"set", s_mipsset, 0},
1425 {"rdata", s_change_sec, 'r'},
1426 {"sdata", s_change_sec, 's'},
1427 {"livereg", s_ignore, 0},
1428 {"abicalls", s_abicalls, 0},
1429 {"cpload", s_cpload, 0},
1430 {"cpsetup", s_cpsetup, 0},
1431 {"cplocal", s_cplocal, 0},
1432 {"cprestore", s_cprestore, 0},
1433 {"cpreturn", s_cpreturn, 0},
1434 {"dtprelword", s_dtprelword, 0},
1435 {"dtpreldword", s_dtpreldword, 0},
1436 {"tprelword", s_tprelword, 0},
1437 {"tpreldword", s_tpreldword, 0},
1438 {"gpvalue", s_gpvalue, 0},
1439 {"gpword", s_gpword, 0},
1440 {"gpdword", s_gpdword, 0},
1441 {"cpadd", s_cpadd, 0},
1442 {"insn", s_insn, 0},
1444 /* Relatively generic pseudo-ops that happen to be used on MIPS
1446 {"asciiz", stringer, 8 + 1},
1447 {"bss", s_change_sec, 'b'},
1449 {"half", s_cons, 1},
1450 {"dword", s_cons, 3},
1451 {"weakext", s_mips_weakext, 0},
1452 {"origin", s_org, 0},
1453 {"repeat", s_rept, 0},
1455 /* For MIPS this is non-standard, but we define it for consistency. */
1456 {"sbss", s_change_sec, 'B'},
1458 /* These pseudo-ops are defined in read.c, but must be overridden
1459 here for one reason or another. */
1460 {"align", s_align, 0},
1461 {"byte", s_cons, 0},
1462 {"data", s_change_sec, 'd'},
1463 {"double", s_float_cons, 'd'},
1464 {"float", s_float_cons, 'f'},
1465 {"globl", s_mips_globl, 0},
1466 {"global", s_mips_globl, 0},
1467 {"hword", s_cons, 1},
1469 {"long", s_cons, 2},
1470 {"octa", s_cons, 4},
1471 {"quad", s_cons, 3},
1472 {"section", s_change_section, 0},
1473 {"short", s_cons, 1},
1474 {"single", s_float_cons, 'f'},
1475 {"stabn", s_mips_stab, 'n'},
1476 {"text", s_change_sec, 't'},
1477 {"word", s_cons, 2},
1479 { "extern", ecoff_directive_extern, 0},
1484 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1486 /* These pseudo-ops should be defined by the object file format.
1487 However, a.out doesn't support them, so we have versions here. */
1488 {"aent", s_mips_ent, 1},
1489 {"bgnb", s_ignore, 0},
1490 {"end", s_mips_end, 0},
1491 {"endb", s_ignore, 0},
1492 {"ent", s_mips_ent, 0},
1493 {"file", s_mips_file, 0},
1494 {"fmask", s_mips_mask, 'F'},
1495 {"frame", s_mips_frame, 0},
1496 {"loc", s_mips_loc, 0},
1497 {"mask", s_mips_mask, 'R'},
1498 {"verstamp", s_ignore, 0},
1502 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1503 purpose of the `.dc.a' internal pseudo-op. */
1506 mips_address_bytes (void)
1508 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1511 extern void pop_insert (const pseudo_typeS *);
1514 mips_pop_insert (void)
1516 pop_insert (mips_pseudo_table);
1517 if (! ECOFF_DEBUGGING)
1518 pop_insert (mips_nonecoff_pseudo_table);
1521 /* Symbols labelling the current insn. */
1523 struct insn_label_list
1525 struct insn_label_list *next;
1529 static struct insn_label_list *free_insn_labels;
1530 #define label_list tc_segment_info_data.labels
1532 static void mips_clear_insn_labels (void);
1533 static void mips_mark_labels (void);
1534 static void mips_compressed_mark_labels (void);
1537 mips_clear_insn_labels (void)
1539 register struct insn_label_list **pl;
1540 segment_info_type *si;
1544 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1547 si = seg_info (now_seg);
1548 *pl = si->label_list;
1549 si->label_list = NULL;
1553 /* Mark instruction labels in MIPS16/microMIPS mode. */
1556 mips_mark_labels (void)
1558 if (HAVE_CODE_COMPRESSION)
1559 mips_compressed_mark_labels ();
1562 static char *expr_end;
1564 /* Expressions which appear in instructions. These are set by
1567 static expressionS imm_expr;
1568 static expressionS imm2_expr;
1569 static expressionS offset_expr;
1571 /* Relocs associated with imm_expr and offset_expr. */
1573 static bfd_reloc_code_real_type imm_reloc[3]
1574 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1575 static bfd_reloc_code_real_type offset_reloc[3]
1576 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1578 /* This is set to the resulting size of the instruction to be produced
1579 by mips16_ip if an explicit extension is used or by mips_ip if an
1580 explicit size is supplied. */
1582 static unsigned int forced_insn_length;
1584 /* True if we are assembling an instruction. All dot symbols defined during
1585 this time should be treated as code labels. */
1587 static bfd_boolean mips_assembling_insn;
1590 /* The pdr segment for per procedure frame/regmask info. Not used for
1593 static segT pdr_seg;
1596 /* The default target format to use. */
1598 #if defined (TE_FreeBSD)
1599 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1600 #elif defined (TE_TMIPS)
1601 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1603 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1607 mips_target_format (void)
1609 switch (OUTPUT_FLAVOR)
1611 case bfd_target_ecoff_flavour:
1612 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1613 case bfd_target_coff_flavour:
1615 case bfd_target_elf_flavour:
1617 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1618 return (target_big_endian
1619 ? "elf32-bigmips-vxworks"
1620 : "elf32-littlemips-vxworks");
1622 return (target_big_endian
1623 ? (HAVE_64BIT_OBJECTS
1624 ? ELF_TARGET ("elf64-", "big")
1626 ? ELF_TARGET ("elf32-n", "big")
1627 : ELF_TARGET ("elf32-", "big")))
1628 : (HAVE_64BIT_OBJECTS
1629 ? ELF_TARGET ("elf64-", "little")
1631 ? ELF_TARGET ("elf32-n", "little")
1632 : ELF_TARGET ("elf32-", "little"))));
1639 /* Return the length of a microMIPS instruction in bytes. If bits of
1640 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1641 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1642 major opcode) will require further modifications to the opcode
1645 static inline unsigned int
1646 micromips_insn_length (const struct mips_opcode *mo)
1648 return (mo->mask >> 16) == 0 ? 2 : 4;
1651 /* Return the length of MIPS16 instruction OPCODE. */
1653 static inline unsigned int
1654 mips16_opcode_length (unsigned long opcode)
1656 return (opcode >> 16) == 0 ? 2 : 4;
1659 /* Return the length of instruction INSN. */
1661 static inline unsigned int
1662 insn_length (const struct mips_cl_insn *insn)
1664 if (mips_opts.micromips)
1665 return micromips_insn_length (insn->insn_mo);
1666 else if (mips_opts.mips16)
1667 return mips16_opcode_length (insn->insn_opcode);
1672 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1675 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1680 insn->insn_opcode = mo->match;
1683 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1684 insn->fixp[i] = NULL;
1685 insn->fixed_p = (mips_opts.noreorder > 0);
1686 insn->noreorder_p = (mips_opts.noreorder > 0);
1687 insn->mips16_absolute_jump_p = 0;
1688 insn->complete_p = 0;
1689 insn->cleared_p = 0;
1692 /* Record the current MIPS16/microMIPS mode in now_seg. */
1695 mips_record_compressed_mode (void)
1697 segment_info_type *si;
1699 si = seg_info (now_seg);
1700 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1701 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1702 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1703 si->tc_segment_info_data.micromips = mips_opts.micromips;
1706 /* Read a standard MIPS instruction from BUF. */
1708 static unsigned long
1709 read_insn (char *buf)
1711 if (target_big_endian)
1712 return bfd_getb32 ((bfd_byte *) buf);
1714 return bfd_getl32 ((bfd_byte *) buf);
1717 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1721 write_insn (char *buf, unsigned int insn)
1723 md_number_to_chars (buf, insn, 4);
1727 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1728 has length LENGTH. */
1730 static unsigned long
1731 read_compressed_insn (char *buf, unsigned int length)
1737 for (i = 0; i < length; i += 2)
1740 if (target_big_endian)
1741 insn |= bfd_getb16 ((char *) buf);
1743 insn |= bfd_getl16 ((char *) buf);
1749 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1750 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1753 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1757 for (i = 0; i < length; i += 2)
1758 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1759 return buf + length;
1762 /* Install INSN at the location specified by its "frag" and "where" fields. */
1765 install_insn (const struct mips_cl_insn *insn)
1767 char *f = insn->frag->fr_literal + insn->where;
1768 if (HAVE_CODE_COMPRESSION)
1769 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1771 write_insn (f, insn->insn_opcode);
1772 mips_record_compressed_mode ();
1775 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1776 and install the opcode in the new location. */
1779 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1784 insn->where = where;
1785 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1786 if (insn->fixp[i] != NULL)
1788 insn->fixp[i]->fx_frag = frag;
1789 insn->fixp[i]->fx_where = where;
1791 install_insn (insn);
1794 /* Add INSN to the end of the output. */
1797 add_fixed_insn (struct mips_cl_insn *insn)
1799 char *f = frag_more (insn_length (insn));
1800 move_insn (insn, frag_now, f - frag_now->fr_literal);
1803 /* Start a variant frag and move INSN to the start of the variant part,
1804 marking it as fixed. The other arguments are as for frag_var. */
1807 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1808 relax_substateT subtype, symbolS *symbol, offsetT offset)
1810 frag_grow (max_chars);
1811 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1813 frag_var (rs_machine_dependent, max_chars, var,
1814 subtype, symbol, offset, NULL);
1817 /* Insert N copies of INSN into the history buffer, starting at
1818 position FIRST. Neither FIRST nor N need to be clipped. */
1821 insert_into_history (unsigned int first, unsigned int n,
1822 const struct mips_cl_insn *insn)
1824 if (mips_relax.sequence != 2)
1828 for (i = ARRAY_SIZE (history); i-- > first;)
1830 history[i] = history[i - n];
1836 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1837 the idea is to make it obvious at a glance that each errata is
1841 init_vr4120_conflicts (void)
1843 #define CONFLICT(FIRST, SECOND) \
1844 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1846 /* Errata 21 - [D]DIV[U] after [D]MACC */
1847 CONFLICT (MACC, DIV);
1848 CONFLICT (DMACC, DIV);
1850 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1851 CONFLICT (DMULT, DMULT);
1852 CONFLICT (DMULT, DMACC);
1853 CONFLICT (DMACC, DMULT);
1854 CONFLICT (DMACC, DMACC);
1856 /* Errata 24 - MT{LO,HI} after [D]MACC */
1857 CONFLICT (MACC, MTHILO);
1858 CONFLICT (DMACC, MTHILO);
1860 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1861 instruction is executed immediately after a MACC or DMACC
1862 instruction, the result of [either instruction] is incorrect." */
1863 CONFLICT (MACC, MULT);
1864 CONFLICT (MACC, DMULT);
1865 CONFLICT (DMACC, MULT);
1866 CONFLICT (DMACC, DMULT);
1868 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1869 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1870 DDIV or DDIVU instruction, the result of the MACC or
1871 DMACC instruction is incorrect.". */
1872 CONFLICT (DMULT, MACC);
1873 CONFLICT (DMULT, DMACC);
1874 CONFLICT (DIV, MACC);
1875 CONFLICT (DIV, DMACC);
1885 #define RTYPE_MASK 0x1ff00
1886 #define RTYPE_NUM 0x00100
1887 #define RTYPE_FPU 0x00200
1888 #define RTYPE_FCC 0x00400
1889 #define RTYPE_VEC 0x00800
1890 #define RTYPE_GP 0x01000
1891 #define RTYPE_CP0 0x02000
1892 #define RTYPE_PC 0x04000
1893 #define RTYPE_ACC 0x08000
1894 #define RTYPE_CCC 0x10000
1895 #define RNUM_MASK 0x000ff
1896 #define RWARN 0x80000
1898 #define GENERIC_REGISTER_NUMBERS \
1899 {"$0", RTYPE_NUM | 0}, \
1900 {"$1", RTYPE_NUM | 1}, \
1901 {"$2", RTYPE_NUM | 2}, \
1902 {"$3", RTYPE_NUM | 3}, \
1903 {"$4", RTYPE_NUM | 4}, \
1904 {"$5", RTYPE_NUM | 5}, \
1905 {"$6", RTYPE_NUM | 6}, \
1906 {"$7", RTYPE_NUM | 7}, \
1907 {"$8", RTYPE_NUM | 8}, \
1908 {"$9", RTYPE_NUM | 9}, \
1909 {"$10", RTYPE_NUM | 10}, \
1910 {"$11", RTYPE_NUM | 11}, \
1911 {"$12", RTYPE_NUM | 12}, \
1912 {"$13", RTYPE_NUM | 13}, \
1913 {"$14", RTYPE_NUM | 14}, \
1914 {"$15", RTYPE_NUM | 15}, \
1915 {"$16", RTYPE_NUM | 16}, \
1916 {"$17", RTYPE_NUM | 17}, \
1917 {"$18", RTYPE_NUM | 18}, \
1918 {"$19", RTYPE_NUM | 19}, \
1919 {"$20", RTYPE_NUM | 20}, \
1920 {"$21", RTYPE_NUM | 21}, \
1921 {"$22", RTYPE_NUM | 22}, \
1922 {"$23", RTYPE_NUM | 23}, \
1923 {"$24", RTYPE_NUM | 24}, \
1924 {"$25", RTYPE_NUM | 25}, \
1925 {"$26", RTYPE_NUM | 26}, \
1926 {"$27", RTYPE_NUM | 27}, \
1927 {"$28", RTYPE_NUM | 28}, \
1928 {"$29", RTYPE_NUM | 29}, \
1929 {"$30", RTYPE_NUM | 30}, \
1930 {"$31", RTYPE_NUM | 31}
1932 #define FPU_REGISTER_NAMES \
1933 {"$f0", RTYPE_FPU | 0}, \
1934 {"$f1", RTYPE_FPU | 1}, \
1935 {"$f2", RTYPE_FPU | 2}, \
1936 {"$f3", RTYPE_FPU | 3}, \
1937 {"$f4", RTYPE_FPU | 4}, \
1938 {"$f5", RTYPE_FPU | 5}, \
1939 {"$f6", RTYPE_FPU | 6}, \
1940 {"$f7", RTYPE_FPU | 7}, \
1941 {"$f8", RTYPE_FPU | 8}, \
1942 {"$f9", RTYPE_FPU | 9}, \
1943 {"$f10", RTYPE_FPU | 10}, \
1944 {"$f11", RTYPE_FPU | 11}, \
1945 {"$f12", RTYPE_FPU | 12}, \
1946 {"$f13", RTYPE_FPU | 13}, \
1947 {"$f14", RTYPE_FPU | 14}, \
1948 {"$f15", RTYPE_FPU | 15}, \
1949 {"$f16", RTYPE_FPU | 16}, \
1950 {"$f17", RTYPE_FPU | 17}, \
1951 {"$f18", RTYPE_FPU | 18}, \
1952 {"$f19", RTYPE_FPU | 19}, \
1953 {"$f20", RTYPE_FPU | 20}, \
1954 {"$f21", RTYPE_FPU | 21}, \
1955 {"$f22", RTYPE_FPU | 22}, \
1956 {"$f23", RTYPE_FPU | 23}, \
1957 {"$f24", RTYPE_FPU | 24}, \
1958 {"$f25", RTYPE_FPU | 25}, \
1959 {"$f26", RTYPE_FPU | 26}, \
1960 {"$f27", RTYPE_FPU | 27}, \
1961 {"$f28", RTYPE_FPU | 28}, \
1962 {"$f29", RTYPE_FPU | 29}, \
1963 {"$f30", RTYPE_FPU | 30}, \
1964 {"$f31", RTYPE_FPU | 31}
1966 #define FPU_CONDITION_CODE_NAMES \
1967 {"$fcc0", RTYPE_FCC | 0}, \
1968 {"$fcc1", RTYPE_FCC | 1}, \
1969 {"$fcc2", RTYPE_FCC | 2}, \
1970 {"$fcc3", RTYPE_FCC | 3}, \
1971 {"$fcc4", RTYPE_FCC | 4}, \
1972 {"$fcc5", RTYPE_FCC | 5}, \
1973 {"$fcc6", RTYPE_FCC | 6}, \
1974 {"$fcc7", RTYPE_FCC | 7}
1976 #define COPROC_CONDITION_CODE_NAMES \
1977 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1978 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1979 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1980 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1981 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1982 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1983 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1984 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1986 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1987 {"$a4", RTYPE_GP | 8}, \
1988 {"$a5", RTYPE_GP | 9}, \
1989 {"$a6", RTYPE_GP | 10}, \
1990 {"$a7", RTYPE_GP | 11}, \
1991 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1992 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1993 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1994 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1995 {"$t0", RTYPE_GP | 12}, \
1996 {"$t1", RTYPE_GP | 13}, \
1997 {"$t2", RTYPE_GP | 14}, \
1998 {"$t3", RTYPE_GP | 15}
2000 #define O32_SYMBOLIC_REGISTER_NAMES \
2001 {"$t0", RTYPE_GP | 8}, \
2002 {"$t1", RTYPE_GP | 9}, \
2003 {"$t2", RTYPE_GP | 10}, \
2004 {"$t3", RTYPE_GP | 11}, \
2005 {"$t4", RTYPE_GP | 12}, \
2006 {"$t5", RTYPE_GP | 13}, \
2007 {"$t6", RTYPE_GP | 14}, \
2008 {"$t7", RTYPE_GP | 15}, \
2009 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2010 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2011 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2012 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2014 /* Remaining symbolic register names */
2015 #define SYMBOLIC_REGISTER_NAMES \
2016 {"$zero", RTYPE_GP | 0}, \
2017 {"$at", RTYPE_GP | 1}, \
2018 {"$AT", RTYPE_GP | 1}, \
2019 {"$v0", RTYPE_GP | 2}, \
2020 {"$v1", RTYPE_GP | 3}, \
2021 {"$a0", RTYPE_GP | 4}, \
2022 {"$a1", RTYPE_GP | 5}, \
2023 {"$a2", RTYPE_GP | 6}, \
2024 {"$a3", RTYPE_GP | 7}, \
2025 {"$s0", RTYPE_GP | 16}, \
2026 {"$s1", RTYPE_GP | 17}, \
2027 {"$s2", RTYPE_GP | 18}, \
2028 {"$s3", RTYPE_GP | 19}, \
2029 {"$s4", RTYPE_GP | 20}, \
2030 {"$s5", RTYPE_GP | 21}, \
2031 {"$s6", RTYPE_GP | 22}, \
2032 {"$s7", RTYPE_GP | 23}, \
2033 {"$t8", RTYPE_GP | 24}, \
2034 {"$t9", RTYPE_GP | 25}, \
2035 {"$k0", RTYPE_GP | 26}, \
2036 {"$kt0", RTYPE_GP | 26}, \
2037 {"$k1", RTYPE_GP | 27}, \
2038 {"$kt1", RTYPE_GP | 27}, \
2039 {"$gp", RTYPE_GP | 28}, \
2040 {"$sp", RTYPE_GP | 29}, \
2041 {"$s8", RTYPE_GP | 30}, \
2042 {"$fp", RTYPE_GP | 30}, \
2043 {"$ra", RTYPE_GP | 31}
2045 #define MIPS16_SPECIAL_REGISTER_NAMES \
2046 {"$pc", RTYPE_PC | 0}
2048 #define MDMX_VECTOR_REGISTER_NAMES \
2049 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2050 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2051 {"$v2", RTYPE_VEC | 2}, \
2052 {"$v3", RTYPE_VEC | 3}, \
2053 {"$v4", RTYPE_VEC | 4}, \
2054 {"$v5", RTYPE_VEC | 5}, \
2055 {"$v6", RTYPE_VEC | 6}, \
2056 {"$v7", RTYPE_VEC | 7}, \
2057 {"$v8", RTYPE_VEC | 8}, \
2058 {"$v9", RTYPE_VEC | 9}, \
2059 {"$v10", RTYPE_VEC | 10}, \
2060 {"$v11", RTYPE_VEC | 11}, \
2061 {"$v12", RTYPE_VEC | 12}, \
2062 {"$v13", RTYPE_VEC | 13}, \
2063 {"$v14", RTYPE_VEC | 14}, \
2064 {"$v15", RTYPE_VEC | 15}, \
2065 {"$v16", RTYPE_VEC | 16}, \
2066 {"$v17", RTYPE_VEC | 17}, \
2067 {"$v18", RTYPE_VEC | 18}, \
2068 {"$v19", RTYPE_VEC | 19}, \
2069 {"$v20", RTYPE_VEC | 20}, \
2070 {"$v21", RTYPE_VEC | 21}, \
2071 {"$v22", RTYPE_VEC | 22}, \
2072 {"$v23", RTYPE_VEC | 23}, \
2073 {"$v24", RTYPE_VEC | 24}, \
2074 {"$v25", RTYPE_VEC | 25}, \
2075 {"$v26", RTYPE_VEC | 26}, \
2076 {"$v27", RTYPE_VEC | 27}, \
2077 {"$v28", RTYPE_VEC | 28}, \
2078 {"$v29", RTYPE_VEC | 29}, \
2079 {"$v30", RTYPE_VEC | 30}, \
2080 {"$v31", RTYPE_VEC | 31}
2082 #define MIPS_DSP_ACCUMULATOR_NAMES \
2083 {"$ac0", RTYPE_ACC | 0}, \
2084 {"$ac1", RTYPE_ACC | 1}, \
2085 {"$ac2", RTYPE_ACC | 2}, \
2086 {"$ac3", RTYPE_ACC | 3}
2088 static const struct regname reg_names[] = {
2089 GENERIC_REGISTER_NUMBERS,
2091 FPU_CONDITION_CODE_NAMES,
2092 COPROC_CONDITION_CODE_NAMES,
2094 /* The $txx registers depends on the abi,
2095 these will be added later into the symbol table from
2096 one of the tables below once mips_abi is set after
2097 parsing of arguments from the command line. */
2098 SYMBOLIC_REGISTER_NAMES,
2100 MIPS16_SPECIAL_REGISTER_NAMES,
2101 MDMX_VECTOR_REGISTER_NAMES,
2102 MIPS_DSP_ACCUMULATOR_NAMES,
2106 static const struct regname reg_names_o32[] = {
2107 O32_SYMBOLIC_REGISTER_NAMES,
2111 static const struct regname reg_names_n32n64[] = {
2112 N32N64_SYMBOLIC_REGISTER_NAMES,
2116 /* Check if S points at a valid register specifier according to TYPES.
2117 If so, then return 1, advance S to consume the specifier and store
2118 the register's number in REGNOP, otherwise return 0. */
2121 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2128 /* Find end of name. */
2130 if (is_name_beginner (*e))
2132 while (is_part_of_name (*e))
2135 /* Terminate name. */
2139 /* Look for a register symbol. */
2140 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2142 int r = S_GET_VALUE (symbolP);
2144 reg = r & RNUM_MASK;
2145 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2146 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2147 reg = (r & RNUM_MASK) - 2;
2149 /* Else see if this is a register defined in an itbl entry. */
2150 else if ((types & RTYPE_GP) && itbl_have_entries)
2157 if (itbl_get_reg_val (n, &r))
2158 reg = r & RNUM_MASK;
2161 /* Advance to next token if a register was recognised. */
2164 else if (types & RWARN)
2165 as_warn (_("Unrecognized register name `%s'"), *s);
2173 /* Check if S points at a valid register list according to TYPES.
2174 If so, then return 1, advance S to consume the list and store
2175 the registers present on the list as a bitmask of ones in REGLISTP,
2176 otherwise return 0. A valid list comprises a comma-separated
2177 enumeration of valid single registers and/or dash-separated
2178 contiguous register ranges as determined by their numbers.
2180 As a special exception if one of s0-s7 registers is specified as
2181 the range's lower delimiter and s8 (fp) is its upper one, then no
2182 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2183 are selected; they have to be listed separately if needed. */
2186 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2188 unsigned int reglist = 0;
2189 unsigned int lastregno;
2190 bfd_boolean ok = TRUE;
2191 unsigned int regmask;
2192 char *s_endlist = *s;
2196 while (reg_lookup (s, types, ®no))
2202 ok = reg_lookup (s, types, &lastregno);
2203 if (ok && lastregno < regno)
2209 if (lastregno == FP && regno >= S0 && regno <= S7)
2214 regmask = 1 << lastregno;
2215 regmask = (regmask << 1) - 1;
2216 regmask ^= (1 << regno) - 1;
2230 *reglistp = reglist;
2231 return ok && reglist != 0;
2234 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2235 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2238 is_opcode_valid (const struct mips_opcode *mo)
2240 int isa = mips_opts.isa;
2243 if (mips_opts.ase_mdmx)
2245 if (mips_opts.ase_dsp)
2247 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2249 if (mips_opts.ase_dspr2)
2251 if (mips_opts.ase_mt)
2253 if (mips_opts.ase_mips3d)
2255 if (mips_opts.ase_smartmips)
2256 isa |= INSN_SMARTMIPS;
2257 if (mips_opts.ase_mcu)
2260 if (!opcode_is_member (mo, isa, mips_opts.arch))
2263 /* Check whether the instruction or macro requires single-precision or
2264 double-precision floating-point support. Note that this information is
2265 stored differently in the opcode table for insns and macros. */
2266 if (mo->pinfo == INSN_MACRO)
2268 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2269 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2273 fp_s = mo->pinfo & FP_S;
2274 fp_d = mo->pinfo & FP_D;
2277 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2280 if (fp_s && mips_opts.soft_float)
2286 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2287 selected ISA and architecture. */
2290 is_opcode_valid_16 (const struct mips_opcode *mo)
2292 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2295 /* Return TRUE if the size of the microMIPS opcode MO matches one
2296 explicitly requested. Always TRUE in the standard MIPS mode. */
2299 is_size_valid (const struct mips_opcode *mo)
2301 if (!mips_opts.micromips)
2304 if (!forced_insn_length)
2306 if (mo->pinfo == INSN_MACRO)
2308 return forced_insn_length == micromips_insn_length (mo);
2311 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2312 of the preceding instruction. Always TRUE in the standard MIPS mode.
2314 We don't accept macros in 16-bit delay slots to avoid a case where
2315 a macro expansion fails because it relies on a preceding 32-bit real
2316 instruction to have matched and does not handle the operands correctly.
2317 The only macros that may expand to 16-bit instructions are JAL that
2318 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2319 and BGT (that likewise cannot be placed in a delay slot) that decay to
2320 a NOP. In all these cases the macros precede any corresponding real
2321 instruction definitions in the opcode table, so they will match in the
2322 second pass where the size of the delay slot is ignored and therefore
2323 produce correct code. */
2326 is_delay_slot_valid (const struct mips_opcode *mo)
2328 if (!mips_opts.micromips)
2331 if (mo->pinfo == INSN_MACRO)
2332 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2333 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2334 && micromips_insn_length (mo) != 4)
2336 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2337 && micromips_insn_length (mo) != 2)
2343 /* This function is called once, at assembler startup time. It should set up
2344 all the tables, etc. that the MD part of the assembler will need. */
2349 const char *retval = NULL;
2353 if (mips_pic != NO_PIC)
2355 if (g_switch_seen && g_switch_value != 0)
2356 as_bad (_("-G may not be used in position-independent code"));
2360 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2361 as_warn (_("Could not set architecture and machine"));
2363 op_hash = hash_new ();
2365 for (i = 0; i < NUMOPCODES;)
2367 const char *name = mips_opcodes[i].name;
2369 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2372 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2373 mips_opcodes[i].name, retval);
2374 /* Probably a memory allocation problem? Give up now. */
2375 as_fatal (_("Broken assembler. No assembly attempted."));
2379 if (mips_opcodes[i].pinfo != INSN_MACRO)
2381 if (!validate_mips_insn (&mips_opcodes[i]))
2383 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2385 create_insn (&nop_insn, mips_opcodes + i);
2386 if (mips_fix_loongson2f_nop)
2387 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2388 nop_insn.fixed_p = 1;
2393 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2396 mips16_op_hash = hash_new ();
2399 while (i < bfd_mips16_num_opcodes)
2401 const char *name = mips16_opcodes[i].name;
2403 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2405 as_fatal (_("internal: can't hash `%s': %s"),
2406 mips16_opcodes[i].name, retval);
2409 if (mips16_opcodes[i].pinfo != INSN_MACRO
2410 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2411 != mips16_opcodes[i].match))
2413 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2414 mips16_opcodes[i].name, mips16_opcodes[i].args);
2417 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2419 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2420 mips16_nop_insn.fixed_p = 1;
2424 while (i < bfd_mips16_num_opcodes
2425 && strcmp (mips16_opcodes[i].name, name) == 0);
2428 micromips_op_hash = hash_new ();
2431 while (i < bfd_micromips_num_opcodes)
2433 const char *name = micromips_opcodes[i].name;
2435 retval = hash_insert (micromips_op_hash, name,
2436 (void *) µmips_opcodes[i]);
2438 as_fatal (_("internal: can't hash `%s': %s"),
2439 micromips_opcodes[i].name, retval);
2441 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2443 struct mips_cl_insn *micromips_nop_insn;
2445 if (!validate_micromips_insn (µmips_opcodes[i]))
2448 if (micromips_insn_length (micromips_opcodes + i) == 2)
2449 micromips_nop_insn = µmips_nop16_insn;
2450 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2451 micromips_nop_insn = µmips_nop32_insn;
2455 if (micromips_nop_insn->insn_mo == NULL
2456 && strcmp (name, "nop") == 0)
2458 create_insn (micromips_nop_insn, micromips_opcodes + i);
2459 micromips_nop_insn->fixed_p = 1;
2462 while (++i < bfd_micromips_num_opcodes
2463 && strcmp (micromips_opcodes[i].name, name) == 0);
2467 as_fatal (_("Broken assembler. No assembly attempted."));
2469 /* We add all the general register names to the symbol table. This
2470 helps us detect invalid uses of them. */
2471 for (i = 0; reg_names[i].name; i++)
2472 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2473 reg_names[i].num, /* & RNUM_MASK, */
2474 &zero_address_frag));
2476 for (i = 0; reg_names_n32n64[i].name; i++)
2477 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2478 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2479 &zero_address_frag));
2481 for (i = 0; reg_names_o32[i].name; i++)
2482 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2483 reg_names_o32[i].num, /* & RNUM_MASK, */
2484 &zero_address_frag));
2486 mips_no_prev_insn ();
2489 mips_cprmask[0] = 0;
2490 mips_cprmask[1] = 0;
2491 mips_cprmask[2] = 0;
2492 mips_cprmask[3] = 0;
2494 /* set the default alignment for the text section (2**2) */
2495 record_alignment (text_section, 2);
2497 bfd_set_gp_size (stdoutput, g_switch_value);
2502 /* On a native system other than VxWorks, sections must be aligned
2503 to 16 byte boundaries. When configured for an embedded ELF
2504 target, we don't bother. */
2505 if (strncmp (TARGET_OS, "elf", 3) != 0
2506 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2508 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2509 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2510 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2513 /* Create a .reginfo section for register masks and a .mdebug
2514 section for debugging information. */
2522 subseg = now_subseg;
2524 /* The ABI says this section should be loaded so that the
2525 running program can access it. However, we don't load it
2526 if we are configured for an embedded target */
2527 flags = SEC_READONLY | SEC_DATA;
2528 if (strncmp (TARGET_OS, "elf", 3) != 0)
2529 flags |= SEC_ALLOC | SEC_LOAD;
2531 if (mips_abi != N64_ABI)
2533 sec = subseg_new (".reginfo", (subsegT) 0);
2535 bfd_set_section_flags (stdoutput, sec, flags);
2536 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2538 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2542 /* The 64-bit ABI uses a .MIPS.options section rather than
2543 .reginfo section. */
2544 sec = subseg_new (".MIPS.options", (subsegT) 0);
2545 bfd_set_section_flags (stdoutput, sec, flags);
2546 bfd_set_section_alignment (stdoutput, sec, 3);
2548 /* Set up the option header. */
2550 Elf_Internal_Options opthdr;
2553 opthdr.kind = ODK_REGINFO;
2554 opthdr.size = (sizeof (Elf_External_Options)
2555 + sizeof (Elf64_External_RegInfo));
2558 f = frag_more (sizeof (Elf_External_Options));
2559 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2560 (Elf_External_Options *) f);
2562 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2566 if (ECOFF_DEBUGGING)
2568 sec = subseg_new (".mdebug", (subsegT) 0);
2569 (void) bfd_set_section_flags (stdoutput, sec,
2570 SEC_HAS_CONTENTS | SEC_READONLY);
2571 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2573 else if (mips_flag_pdr)
2575 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2576 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2577 SEC_READONLY | SEC_RELOC
2579 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2582 subseg_set (seg, subseg);
2585 #endif /* OBJ_ELF */
2587 if (! ECOFF_DEBUGGING)
2590 if (mips_fix_vr4120)
2591 init_vr4120_conflicts ();
2597 mips_emit_delays ();
2598 if (! ECOFF_DEBUGGING)
2603 md_assemble (char *str)
2605 struct mips_cl_insn insn;
2606 bfd_reloc_code_real_type unused_reloc[3]
2607 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2609 imm_expr.X_op = O_absent;
2610 imm2_expr.X_op = O_absent;
2611 offset_expr.X_op = O_absent;
2612 imm_reloc[0] = BFD_RELOC_UNUSED;
2613 imm_reloc[1] = BFD_RELOC_UNUSED;
2614 imm_reloc[2] = BFD_RELOC_UNUSED;
2615 offset_reloc[0] = BFD_RELOC_UNUSED;
2616 offset_reloc[1] = BFD_RELOC_UNUSED;
2617 offset_reloc[2] = BFD_RELOC_UNUSED;
2619 mips_mark_labels ();
2620 mips_assembling_insn = TRUE;
2622 if (mips_opts.mips16)
2623 mips16_ip (str, &insn);
2626 mips_ip (str, &insn);
2627 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2628 str, insn.insn_opcode));
2632 as_bad ("%s `%s'", insn_error, str);
2633 else if (insn.insn_mo->pinfo == INSN_MACRO)
2636 if (mips_opts.mips16)
2637 mips16_macro (&insn);
2644 if (imm_expr.X_op != O_absent)
2645 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2646 else if (offset_expr.X_op != O_absent)
2647 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2649 append_insn (&insn, NULL, unused_reloc, FALSE);
2652 mips_assembling_insn = FALSE;
2655 /* Convenience functions for abstracting away the differences between
2656 MIPS16 and non-MIPS16 relocations. */
2658 static inline bfd_boolean
2659 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2663 case BFD_RELOC_MIPS16_JMP:
2664 case BFD_RELOC_MIPS16_GPREL:
2665 case BFD_RELOC_MIPS16_GOT16:
2666 case BFD_RELOC_MIPS16_CALL16:
2667 case BFD_RELOC_MIPS16_HI16_S:
2668 case BFD_RELOC_MIPS16_HI16:
2669 case BFD_RELOC_MIPS16_LO16:
2677 static inline bfd_boolean
2678 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2682 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2683 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2684 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2685 case BFD_RELOC_MICROMIPS_GPREL16:
2686 case BFD_RELOC_MICROMIPS_JMP:
2687 case BFD_RELOC_MICROMIPS_HI16:
2688 case BFD_RELOC_MICROMIPS_HI16_S:
2689 case BFD_RELOC_MICROMIPS_LO16:
2690 case BFD_RELOC_MICROMIPS_LITERAL:
2691 case BFD_RELOC_MICROMIPS_GOT16:
2692 case BFD_RELOC_MICROMIPS_CALL16:
2693 case BFD_RELOC_MICROMIPS_GOT_HI16:
2694 case BFD_RELOC_MICROMIPS_GOT_LO16:
2695 case BFD_RELOC_MICROMIPS_CALL_HI16:
2696 case BFD_RELOC_MICROMIPS_CALL_LO16:
2697 case BFD_RELOC_MICROMIPS_SUB:
2698 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2699 case BFD_RELOC_MICROMIPS_GOT_OFST:
2700 case BFD_RELOC_MICROMIPS_GOT_DISP:
2701 case BFD_RELOC_MICROMIPS_HIGHEST:
2702 case BFD_RELOC_MICROMIPS_HIGHER:
2703 case BFD_RELOC_MICROMIPS_SCN_DISP:
2704 case BFD_RELOC_MICROMIPS_JALR:
2712 static inline bfd_boolean
2713 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2715 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2718 static inline bfd_boolean
2719 got16_reloc_p (bfd_reloc_code_real_type reloc)
2721 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2722 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2725 static inline bfd_boolean
2726 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2728 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2729 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2732 static inline bfd_boolean
2733 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2735 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2736 || reloc == BFD_RELOC_MICROMIPS_LO16);
2739 static inline bfd_boolean
2740 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2742 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2745 /* Return true if the given relocation might need a matching %lo().
2746 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2747 need a matching %lo() when applied to local symbols. */
2749 static inline bfd_boolean
2750 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2752 return (HAVE_IN_PLACE_ADDENDS
2753 && (hi16_reloc_p (reloc)
2754 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2755 all GOT16 relocations evaluate to "G". */
2756 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2759 /* Return the type of %lo() reloc needed by RELOC, given that
2760 reloc_needs_lo_p. */
2762 static inline bfd_reloc_code_real_type
2763 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2765 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2766 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2770 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2773 static inline bfd_boolean
2774 fixup_has_matching_lo_p (fixS *fixp)
2776 return (fixp->fx_next != NULL
2777 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2778 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2779 && fixp->fx_offset == fixp->fx_next->fx_offset);
2782 /* This function returns true if modifying a register requires a
2786 reg_needs_delay (unsigned int reg)
2788 unsigned long prev_pinfo;
2790 prev_pinfo = history[0].insn_mo->pinfo;
2791 if (! mips_opts.noreorder
2792 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2793 && ! gpr_interlocks)
2794 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2795 && ! cop_interlocks)))
2797 /* A load from a coprocessor or from memory. All load delays
2798 delay the use of general register rt for one instruction. */
2799 /* Itbl support may require additional care here. */
2800 know (prev_pinfo & INSN_WRITE_GPR_T);
2801 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2808 /* Move all labels in LABELS to the current insertion point. TEXT_P
2809 says whether the labels refer to text or data. */
2812 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2814 struct insn_label_list *l;
2817 for (l = labels; l != NULL; l = l->next)
2819 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2820 symbol_set_frag (l->label, frag_now);
2821 val = (valueT) frag_now_fix ();
2822 /* MIPS16/microMIPS text labels are stored as odd. */
2823 if (text_p && HAVE_CODE_COMPRESSION)
2825 S_SET_VALUE (l->label, val);
2829 /* Move all labels in insn_labels to the current insertion point
2830 and treat them as text labels. */
2833 mips_move_text_labels (void)
2835 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2839 s_is_linkonce (symbolS *sym, segT from_seg)
2841 bfd_boolean linkonce = FALSE;
2842 segT symseg = S_GET_SEGMENT (sym);
2844 if (symseg != from_seg && !S_IS_LOCAL (sym))
2846 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2849 /* The GNU toolchain uses an extension for ELF: a section
2850 beginning with the magic string .gnu.linkonce is a
2851 linkonce section. */
2852 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2853 sizeof ".gnu.linkonce" - 1) == 0)
2860 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2861 linker to handle them specially, such as generating jalx instructions
2862 when needed. We also make them odd for the duration of the assembly,
2863 in order to generate the right sort of code. We will make them even
2864 in the adjust_symtab routine, while leaving them marked. This is
2865 convenient for the debugger and the disassembler. The linker knows
2866 to make them odd again. */
2869 mips_compressed_mark_label (symbolS *label)
2871 gas_assert (HAVE_CODE_COMPRESSION);
2873 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2876 if (mips_opts.mips16)
2877 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2879 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2882 if ((S_GET_VALUE (label) & 1) == 0
2883 /* Don't adjust the address if the label is global or weak, or
2884 in a link-once section, since we'll be emitting symbol reloc
2885 references to it which will be patched up by the linker, and
2886 the final value of the symbol may or may not be MIPS16/microMIPS. */
2887 && !S_IS_WEAK (label)
2888 && !S_IS_EXTERNAL (label)
2889 && !s_is_linkonce (label, now_seg))
2890 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2893 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2896 mips_compressed_mark_labels (void)
2898 struct insn_label_list *l;
2900 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2901 mips_compressed_mark_label (l->label);
2904 /* End the current frag. Make it a variant frag and record the
2908 relax_close_frag (void)
2910 mips_macro_warning.first_frag = frag_now;
2911 frag_var (rs_machine_dependent, 0, 0,
2912 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2913 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2915 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2916 mips_relax.first_fixup = 0;
2919 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2920 See the comment above RELAX_ENCODE for more details. */
2923 relax_start (symbolS *symbol)
2925 gas_assert (mips_relax.sequence == 0);
2926 mips_relax.sequence = 1;
2927 mips_relax.symbol = symbol;
2930 /* Start generating the second version of a relaxable sequence.
2931 See the comment above RELAX_ENCODE for more details. */
2936 gas_assert (mips_relax.sequence == 1);
2937 mips_relax.sequence = 2;
2940 /* End the current relaxable sequence. */
2945 gas_assert (mips_relax.sequence == 2);
2946 relax_close_frag ();
2947 mips_relax.sequence = 0;
2950 /* Return true if IP is a delayed branch or jump. */
2952 static inline bfd_boolean
2953 delayed_branch_p (const struct mips_cl_insn *ip)
2955 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2956 | INSN_COND_BRANCH_DELAY
2957 | INSN_COND_BRANCH_LIKELY)) != 0;
2960 /* Return true if IP is a compact branch or jump. */
2962 static inline bfd_boolean
2963 compact_branch_p (const struct mips_cl_insn *ip)
2965 if (mips_opts.mips16)
2966 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2967 | MIPS16_INSN_COND_BRANCH)) != 0;
2969 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2970 | INSN2_COND_BRANCH)) != 0;
2973 /* Return true if IP is an unconditional branch or jump. */
2975 static inline bfd_boolean
2976 uncond_branch_p (const struct mips_cl_insn *ip)
2978 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2979 || (mips_opts.mips16
2980 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2981 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2984 /* Return true if IP is a branch-likely instruction. */
2986 static inline bfd_boolean
2987 branch_likely_p (const struct mips_cl_insn *ip)
2989 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2992 /* Return the type of nop that should be used to fill the delay slot
2993 of delayed branch IP. */
2995 static struct mips_cl_insn *
2996 get_delay_slot_nop (const struct mips_cl_insn *ip)
2998 if (mips_opts.micromips
2999 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3000 return µmips_nop32_insn;
3004 /* Return the mask of core registers that IP reads or writes. */
3007 gpr_mod_mask (const struct mips_cl_insn *ip)
3009 unsigned long pinfo2;
3013 pinfo2 = ip->insn_mo->pinfo2;
3014 if (mips_opts.micromips)
3016 if (pinfo2 & INSN2_MOD_GPR_MD)
3017 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3018 if (pinfo2 & INSN2_MOD_GPR_MF)
3019 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3020 if (pinfo2 & INSN2_MOD_SP)
3026 /* Return the mask of core registers that IP reads. */
3029 gpr_read_mask (const struct mips_cl_insn *ip)
3031 unsigned long pinfo, pinfo2;
3034 mask = gpr_mod_mask (ip);
3035 pinfo = ip->insn_mo->pinfo;
3036 pinfo2 = ip->insn_mo->pinfo2;
3037 if (mips_opts.mips16)
3039 if (pinfo & MIPS16_INSN_READ_X)
3040 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3041 if (pinfo & MIPS16_INSN_READ_Y)
3042 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3043 if (pinfo & MIPS16_INSN_READ_T)
3045 if (pinfo & MIPS16_INSN_READ_SP)
3047 if (pinfo & MIPS16_INSN_READ_31)
3049 if (pinfo & MIPS16_INSN_READ_Z)
3050 mask |= 1 << (mips16_to_32_reg_map
3051 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3052 if (pinfo & MIPS16_INSN_READ_GPR_X)
3053 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3057 if (pinfo2 & INSN2_READ_GPR_D)
3058 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3059 if (pinfo & INSN_READ_GPR_T)
3060 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3061 if (pinfo & INSN_READ_GPR_S)
3062 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3063 if (pinfo2 & INSN2_READ_GP)
3065 if (pinfo2 & INSN2_READ_GPR_31)
3067 if (pinfo2 & INSN2_READ_GPR_Z)
3068 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3070 if (mips_opts.micromips)
3072 if (pinfo2 & INSN2_READ_GPR_MC)
3073 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3074 if (pinfo2 & INSN2_READ_GPR_ME)
3075 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3076 if (pinfo2 & INSN2_READ_GPR_MG)
3077 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3078 if (pinfo2 & INSN2_READ_GPR_MJ)
3079 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3080 if (pinfo2 & INSN2_READ_GPR_MMN)
3082 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3083 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3085 if (pinfo2 & INSN2_READ_GPR_MP)
3086 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3087 if (pinfo2 & INSN2_READ_GPR_MQ)
3088 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3090 /* Don't include register 0. */
3094 /* Return the mask of core registers that IP writes. */
3097 gpr_write_mask (const struct mips_cl_insn *ip)
3099 unsigned long pinfo, pinfo2;
3102 mask = gpr_mod_mask (ip);
3103 pinfo = ip->insn_mo->pinfo;
3104 pinfo2 = ip->insn_mo->pinfo2;
3105 if (mips_opts.mips16)
3107 if (pinfo & MIPS16_INSN_WRITE_X)
3108 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3109 if (pinfo & MIPS16_INSN_WRITE_Y)
3110 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3111 if (pinfo & MIPS16_INSN_WRITE_Z)
3112 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3113 if (pinfo & MIPS16_INSN_WRITE_T)
3115 if (pinfo & MIPS16_INSN_WRITE_SP)
3117 if (pinfo & MIPS16_INSN_WRITE_31)
3119 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3120 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3124 if (pinfo & INSN_WRITE_GPR_D)
3125 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3126 if (pinfo & INSN_WRITE_GPR_T)
3127 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3128 if (pinfo & INSN_WRITE_GPR_S)
3129 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3130 if (pinfo & INSN_WRITE_GPR_31)
3132 if (pinfo2 & INSN2_WRITE_GPR_Z)
3133 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3135 if (mips_opts.micromips)
3137 if (pinfo2 & INSN2_WRITE_GPR_MB)
3138 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3139 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3141 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3142 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3144 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3145 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3146 if (pinfo2 & INSN2_WRITE_GPR_MP)
3147 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3149 /* Don't include register 0. */
3153 /* Return the mask of floating-point registers that IP reads. */
3156 fpr_read_mask (const struct mips_cl_insn *ip)
3158 unsigned long pinfo, pinfo2;
3162 pinfo = ip->insn_mo->pinfo;
3163 pinfo2 = ip->insn_mo->pinfo2;
3164 if (!mips_opts.mips16)
3166 if (pinfo2 & INSN2_READ_FPR_D)
3167 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3168 if (pinfo & INSN_READ_FPR_S)
3169 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3170 if (pinfo & INSN_READ_FPR_T)
3171 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3172 if (pinfo & INSN_READ_FPR_R)
3173 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3174 if (pinfo2 & INSN2_READ_FPR_Z)
3175 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3177 /* Conservatively treat all operands to an FP_D instruction are doubles.
3178 (This is overly pessimistic for things like cvt.d.s.) */
3179 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3184 /* Return the mask of floating-point registers that IP writes. */
3187 fpr_write_mask (const struct mips_cl_insn *ip)
3189 unsigned long pinfo, pinfo2;
3193 pinfo = ip->insn_mo->pinfo;
3194 pinfo2 = ip->insn_mo->pinfo2;
3195 if (!mips_opts.mips16)
3197 if (pinfo & INSN_WRITE_FPR_D)
3198 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3199 if (pinfo & INSN_WRITE_FPR_S)
3200 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3201 if (pinfo & INSN_WRITE_FPR_T)
3202 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3203 if (pinfo2 & INSN2_WRITE_FPR_Z)
3204 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3206 /* Conservatively treat all operands to an FP_D instruction are doubles.
3207 (This is overly pessimistic for things like cvt.s.d.) */
3208 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3213 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3214 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3215 by VR4120 errata. */
3218 classify_vr4120_insn (const char *name)
3220 if (strncmp (name, "macc", 4) == 0)
3221 return FIX_VR4120_MACC;
3222 if (strncmp (name, "dmacc", 5) == 0)
3223 return FIX_VR4120_DMACC;
3224 if (strncmp (name, "mult", 4) == 0)
3225 return FIX_VR4120_MULT;
3226 if (strncmp (name, "dmult", 5) == 0)
3227 return FIX_VR4120_DMULT;
3228 if (strstr (name, "div"))
3229 return FIX_VR4120_DIV;
3230 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3231 return FIX_VR4120_MTHILO;
3232 return NUM_FIX_VR4120_CLASSES;
3235 #define INSN_ERET 0x42000018
3236 #define INSN_DERET 0x4200001f
3238 /* Return the number of instructions that must separate INSN1 and INSN2,
3239 where INSN1 is the earlier instruction. Return the worst-case value
3240 for any INSN2 if INSN2 is null. */
3243 insns_between (const struct mips_cl_insn *insn1,
3244 const struct mips_cl_insn *insn2)
3246 unsigned long pinfo1, pinfo2;
3249 /* This function needs to know which pinfo flags are set for INSN2
3250 and which registers INSN2 uses. The former is stored in PINFO2 and
3251 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3252 will have every flag set and INSN2_USES_GPR will always return true. */
3253 pinfo1 = insn1->insn_mo->pinfo;
3254 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3256 #define INSN2_USES_GPR(REG) \
3257 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3259 /* For most targets, write-after-read dependencies on the HI and LO
3260 registers must be separated by at least two instructions. */
3261 if (!hilo_interlocks)
3263 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3265 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3269 /* If we're working around r7000 errata, there must be two instructions
3270 between an mfhi or mflo and any instruction that uses the result. */
3271 if (mips_7000_hilo_fix
3272 && !mips_opts.micromips
3273 && MF_HILO_INSN (pinfo1)
3274 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3277 /* If we're working around 24K errata, one instruction is required
3278 if an ERET or DERET is followed by a branch instruction. */
3279 if (mips_fix_24k && !mips_opts.micromips)
3281 if (insn1->insn_opcode == INSN_ERET
3282 || insn1->insn_opcode == INSN_DERET)
3285 || insn2->insn_opcode == INSN_ERET
3286 || insn2->insn_opcode == INSN_DERET
3287 || delayed_branch_p (insn2))
3292 /* If working around VR4120 errata, check for combinations that need
3293 a single intervening instruction. */
3294 if (mips_fix_vr4120 && !mips_opts.micromips)
3296 unsigned int class1, class2;
3298 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3299 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3303 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3304 if (vr4120_conflicts[class1] & (1 << class2))
3309 if (!HAVE_CODE_COMPRESSION)
3311 /* Check for GPR or coprocessor load delays. All such delays
3312 are on the RT register. */
3313 /* Itbl support may require additional care here. */
3314 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3315 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3317 know (pinfo1 & INSN_WRITE_GPR_T);
3318 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3322 /* Check for generic coprocessor hazards.
3324 This case is not handled very well. There is no special
3325 knowledge of CP0 handling, and the coprocessors other than
3326 the floating point unit are not distinguished at all. */
3327 /* Itbl support may require additional care here. FIXME!
3328 Need to modify this to include knowledge about
3329 user specified delays! */
3330 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3331 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3333 /* Handle cases where INSN1 writes to a known general coprocessor
3334 register. There must be a one instruction delay before INSN2
3335 if INSN2 reads that register, otherwise no delay is needed. */
3336 mask = fpr_write_mask (insn1);
3339 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3344 /* Read-after-write dependencies on the control registers
3345 require a two-instruction gap. */
3346 if ((pinfo1 & INSN_WRITE_COND_CODE)
3347 && (pinfo2 & INSN_READ_COND_CODE))
3350 /* We don't know exactly what INSN1 does. If INSN2 is
3351 also a coprocessor instruction, assume there must be
3352 a one instruction gap. */
3353 if (pinfo2 & INSN_COP)
3358 /* Check for read-after-write dependencies on the coprocessor
3359 control registers in cases where INSN1 does not need a general
3360 coprocessor delay. This means that INSN1 is a floating point
3361 comparison instruction. */
3362 /* Itbl support may require additional care here. */
3363 else if (!cop_interlocks
3364 && (pinfo1 & INSN_WRITE_COND_CODE)
3365 && (pinfo2 & INSN_READ_COND_CODE))
3369 #undef INSN2_USES_GPR
3374 /* Return the number of nops that would be needed to work around the
3375 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3376 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3377 that are contained within the first IGNORE instructions of HIST. */
3380 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3381 const struct mips_cl_insn *insn)
3386 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3387 are not affected by the errata. */
3389 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3390 || strcmp (insn->insn_mo->name, "mtlo") == 0
3391 || strcmp (insn->insn_mo->name, "mthi") == 0))
3394 /* Search for the first MFLO or MFHI. */
3395 for (i = 0; i < MAX_VR4130_NOPS; i++)
3396 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3398 /* Extract the destination register. */
3399 mask = gpr_write_mask (&hist[i]);
3401 /* No nops are needed if INSN reads that register. */
3402 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3405 /* ...or if any of the intervening instructions do. */
3406 for (j = 0; j < i; j++)
3407 if (gpr_read_mask (&hist[j]) & mask)
3411 return MAX_VR4130_NOPS - i;
3416 #define BASE_REG_EQ(INSN1, INSN2) \
3417 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3418 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3420 /* Return the minimum alignment for this store instruction. */
3423 fix_24k_align_to (const struct mips_opcode *mo)
3425 if (strcmp (mo->name, "sh") == 0)
3428 if (strcmp (mo->name, "swc1") == 0
3429 || strcmp (mo->name, "swc2") == 0
3430 || strcmp (mo->name, "sw") == 0
3431 || strcmp (mo->name, "sc") == 0
3432 || strcmp (mo->name, "s.s") == 0)
3435 if (strcmp (mo->name, "sdc1") == 0
3436 || strcmp (mo->name, "sdc2") == 0
3437 || strcmp (mo->name, "s.d") == 0)
3444 struct fix_24k_store_info
3446 /* Immediate offset, if any, for this store instruction. */
3448 /* Alignment required by this store instruction. */
3450 /* True for register offsets. */
3451 int register_offset;
3454 /* Comparison function used by qsort. */
3457 fix_24k_sort (const void *a, const void *b)
3459 const struct fix_24k_store_info *pos1 = a;
3460 const struct fix_24k_store_info *pos2 = b;
3462 return (pos1->off - pos2->off);
3465 /* INSN is a store instruction. Try to record the store information
3466 in STINFO. Return false if the information isn't known. */
3469 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3470 const struct mips_cl_insn *insn)
3472 /* The instruction must have a known offset. */
3473 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3476 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3477 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3481 /* Return the number of nops that would be needed to work around the 24k
3482 "lost data on stores during refill" errata if instruction INSN
3483 immediately followed the 2 instructions described by HIST.
3484 Ignore hazards that are contained within the first IGNORE
3485 instructions of HIST.
3487 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3488 for the data cache refills and store data. The following describes
3489 the scenario where the store data could be lost.
3491 * A data cache miss, due to either a load or a store, causing fill
3492 data to be supplied by the memory subsystem
3493 * The first three doublewords of fill data are returned and written
3495 * A sequence of four stores occurs in consecutive cycles around the
3496 final doubleword of the fill:
3500 * Zero, One or more instructions
3503 The four stores A-D must be to different doublewords of the line that
3504 is being filled. The fourth instruction in the sequence above permits
3505 the fill of the final doubleword to be transferred from the FSB into
3506 the cache. In the sequence above, the stores may be either integer
3507 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3508 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3509 different doublewords on the line. If the floating point unit is
3510 running in 1:2 mode, it is not possible to create the sequence above
3511 using only floating point store instructions.
3513 In this case, the cache line being filled is incorrectly marked
3514 invalid, thereby losing the data from any store to the line that
3515 occurs between the original miss and the completion of the five
3516 cycle sequence shown above.
3518 The workarounds are:
3520 * Run the data cache in write-through mode.
3521 * Insert a non-store instruction between
3522 Store A and Store B or Store B and Store C. */
3525 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3526 const struct mips_cl_insn *insn)
3528 struct fix_24k_store_info pos[3];
3529 int align, i, base_offset;
3534 /* If the previous instruction wasn't a store, there's nothing to
3536 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3539 /* If the instructions after the previous one are unknown, we have
3540 to assume the worst. */
3544 /* Check whether we are dealing with three consecutive stores. */
3545 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3546 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3549 /* If we don't know the relationship between the store addresses,
3550 assume the worst. */
3551 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3552 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3555 if (!fix_24k_record_store_info (&pos[0], insn)
3556 || !fix_24k_record_store_info (&pos[1], &hist[0])
3557 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3560 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3562 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3563 X bytes and such that the base register + X is known to be aligned
3566 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3570 align = pos[0].align_to;
3571 base_offset = pos[0].off;
3572 for (i = 1; i < 3; i++)
3573 if (align < pos[i].align_to)
3575 align = pos[i].align_to;
3576 base_offset = pos[i].off;
3578 for (i = 0; i < 3; i++)
3579 pos[i].off -= base_offset;
3582 pos[0].off &= ~align + 1;
3583 pos[1].off &= ~align + 1;
3584 pos[2].off &= ~align + 1;
3586 /* If any two stores write to the same chunk, they also write to the
3587 same doubleword. The offsets are still sorted at this point. */
3588 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3591 /* A range of at least 9 bytes is needed for the stores to be in
3592 non-overlapping doublewords. */
3593 if (pos[2].off - pos[0].off <= 8)
3596 if (pos[2].off - pos[1].off >= 24
3597 || pos[1].off - pos[0].off >= 24
3598 || pos[2].off - pos[0].off >= 32)
3604 /* Return the number of nops that would be needed if instruction INSN
3605 immediately followed the MAX_NOPS instructions given by HIST,
3606 where HIST[0] is the most recent instruction. Ignore hazards
3607 between INSN and the first IGNORE instructions in HIST.
3609 If INSN is null, return the worse-case number of nops for any
3613 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3614 const struct mips_cl_insn *insn)
3616 int i, nops, tmp_nops;
3619 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3621 tmp_nops = insns_between (hist + i, insn) - i;
3622 if (tmp_nops > nops)
3626 if (mips_fix_vr4130 && !mips_opts.micromips)
3628 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3629 if (tmp_nops > nops)
3633 if (mips_fix_24k && !mips_opts.micromips)
3635 tmp_nops = nops_for_24k (ignore, hist, insn);
3636 if (tmp_nops > nops)
3643 /* The variable arguments provide NUM_INSNS extra instructions that
3644 might be added to HIST. Return the largest number of nops that
3645 would be needed after the extended sequence, ignoring hazards
3646 in the first IGNORE instructions. */
3649 nops_for_sequence (int num_insns, int ignore,
3650 const struct mips_cl_insn *hist, ...)
3653 struct mips_cl_insn buffer[MAX_NOPS];
3654 struct mips_cl_insn *cursor;
3657 va_start (args, hist);
3658 cursor = buffer + num_insns;
3659 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3660 while (cursor > buffer)
3661 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3663 nops = nops_for_insn (ignore, buffer, NULL);
3668 /* Like nops_for_insn, but if INSN is a branch, take into account the
3669 worst-case delay for the branch target. */
3672 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3673 const struct mips_cl_insn *insn)
3677 nops = nops_for_insn (ignore, hist, insn);
3678 if (delayed_branch_p (insn))
3680 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3681 hist, insn, get_delay_slot_nop (insn));
3682 if (tmp_nops > nops)
3685 else if (compact_branch_p (insn))
3687 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3688 if (tmp_nops > nops)
3694 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3697 fix_loongson2f_nop (struct mips_cl_insn * ip)
3699 gas_assert (!HAVE_CODE_COMPRESSION);
3700 if (strcmp (ip->insn_mo->name, "nop") == 0)
3701 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3704 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3705 jr target pc &= 'hffff_ffff_cfff_ffff. */
3708 fix_loongson2f_jump (struct mips_cl_insn * ip)
3710 gas_assert (!HAVE_CODE_COMPRESSION);
3711 if (strcmp (ip->insn_mo->name, "j") == 0
3712 || strcmp (ip->insn_mo->name, "jr") == 0
3713 || strcmp (ip->insn_mo->name, "jalr") == 0)
3721 sreg = EXTRACT_OPERAND (0, RS, *ip);
3722 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3725 ep.X_op = O_constant;
3726 ep.X_add_number = 0xcfff0000;
3727 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3728 ep.X_add_number = 0xffff;
3729 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3730 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3735 fix_loongson2f (struct mips_cl_insn * ip)
3737 if (mips_fix_loongson2f_nop)
3738 fix_loongson2f_nop (ip);
3740 if (mips_fix_loongson2f_jump)
3741 fix_loongson2f_jump (ip);
3744 /* IP is a branch that has a delay slot, and we need to fill it
3745 automatically. Return true if we can do that by swapping IP
3746 with the previous instruction.
3747 ADDRESS_EXPR is an operand of the instruction to be used with
3751 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3752 bfd_reloc_code_real_type *reloc_type)
3754 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3755 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3757 /* -O2 and above is required for this optimization. */
3758 if (mips_optimize < 2)
3761 /* If we have seen .set volatile or .set nomove, don't optimize. */
3762 if (mips_opts.nomove)
3765 /* We can't swap if the previous instruction's position is fixed. */
3766 if (history[0].fixed_p)
3769 /* If the previous previous insn was in a .set noreorder, we can't
3770 swap. Actually, the MIPS assembler will swap in this situation.
3771 However, gcc configured -with-gnu-as will generate code like
3779 in which we can not swap the bne and INSN. If gcc is not configured
3780 -with-gnu-as, it does not output the .set pseudo-ops. */
3781 if (history[1].noreorder_p)
3784 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3785 This means that the previous instruction was a 4-byte one anyhow. */
3786 if (mips_opts.mips16 && history[0].fixp[0])
3789 /* If the branch is itself the target of a branch, we can not swap.
3790 We cheat on this; all we check for is whether there is a label on
3791 this instruction. If there are any branches to anything other than
3792 a label, users must use .set noreorder. */
3793 if (seg_info (now_seg)->label_list)
3796 /* If the previous instruction is in a variant frag other than this
3797 branch's one, we cannot do the swap. This does not apply to
3798 MIPS16 code, which uses variant frags for different purposes. */
3799 if (!mips_opts.mips16
3801 && history[0].frag->fr_type == rs_machine_dependent)
3804 /* We do not swap with instructions that cannot architecturally
3805 be placed in a branch delay slot, such as SYNC or ERET. We
3806 also refrain from swapping with a trap instruction, since it
3807 complicates trap handlers to have the trap instruction be in
3809 prev_pinfo = history[0].insn_mo->pinfo;
3810 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3813 /* Check for conflicts between the branch and the instructions
3814 before the candidate delay slot. */
3815 if (nops_for_insn (0, history + 1, ip) > 0)
3818 /* Check for conflicts between the swapped sequence and the
3819 target of the branch. */
3820 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3823 /* If the branch reads a register that the previous
3824 instruction sets, we can not swap. */
3825 gpr_read = gpr_read_mask (ip);
3826 prev_gpr_write = gpr_write_mask (&history[0]);
3827 if (gpr_read & prev_gpr_write)
3830 /* If the branch writes a register that the previous
3831 instruction sets, we can not swap. */
3832 gpr_write = gpr_write_mask (ip);
3833 if (gpr_write & prev_gpr_write)
3836 /* If the branch writes a register that the previous
3837 instruction reads, we can not swap. */
3838 prev_gpr_read = gpr_read_mask (&history[0]);
3839 if (gpr_write & prev_gpr_read)
3842 /* If one instruction sets a condition code and the
3843 other one uses a condition code, we can not swap. */
3844 pinfo = ip->insn_mo->pinfo;
3845 if ((pinfo & INSN_READ_COND_CODE)
3846 && (prev_pinfo & INSN_WRITE_COND_CODE))
3848 if ((pinfo & INSN_WRITE_COND_CODE)
3849 && (prev_pinfo & INSN_READ_COND_CODE))
3852 /* If the previous instruction uses the PC, we can not swap. */
3853 prev_pinfo2 = history[0].insn_mo->pinfo2;
3854 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3856 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3859 /* If the previous instruction has an incorrect size for a fixed
3860 branch delay slot in microMIPS mode, we cannot swap. */
3861 pinfo2 = ip->insn_mo->pinfo2;
3862 if (mips_opts.micromips
3863 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3864 && insn_length (history) != 2)
3866 if (mips_opts.micromips
3867 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3868 && insn_length (history) != 4)
3871 /* On R5900 short loops need to be fixed by inserting a nop in
3872 the branch delay slots.
3873 A short loop can be terminated too early. */
3874 if (mips_opts.arch == CPU_R5900
3875 /* Check if instruction has a parameter, ignore "j $31". */
3876 && (address_expr != NULL)
3877 /* Parameter must be 16 bit. */
3878 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3879 /* Branch to same segment. */
3880 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3881 /* Branch to same code fragment. */
3882 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3883 /* Can only calculate branch offset if value is known. */
3884 && symbol_constant_p(address_expr->X_add_symbol)
3885 /* Check if branch is really conditional. */
3886 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3887 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3888 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3891 /* Check if loop is shorter than 6 instructions including
3892 branch and delay slot. */
3893 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3900 /* When the loop includes branches or jumps,
3901 it is not a short loop. */
3902 for (i = 0; i < (distance / 4); i++)
3904 if ((history[i].cleared_p)
3905 || delayed_branch_p(&history[i]))
3913 /* Insert nop after branch to fix short loop. */
3922 /* Decide how we should add IP to the instruction stream.
3923 ADDRESS_EXPR is an operand of the instruction to be used with
3926 static enum append_method
3927 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3928 bfd_reloc_code_real_type *reloc_type)
3930 unsigned long pinfo;
3932 /* The relaxed version of a macro sequence must be inherently
3934 if (mips_relax.sequence == 2)
3937 /* We must not dabble with instructions in a ".set norerorder" block. */
3938 if (mips_opts.noreorder)
3941 /* Otherwise, it's our responsibility to fill branch delay slots. */
3942 if (delayed_branch_p (ip))
3944 if (!branch_likely_p (ip)
3945 && can_swap_branch_p (ip, address_expr, reloc_type))
3948 pinfo = ip->insn_mo->pinfo;
3949 if (mips_opts.mips16
3950 && ISA_SUPPORTS_MIPS16E
3951 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3952 return APPEND_ADD_COMPACT;
3954 return APPEND_ADD_WITH_NOP;
3960 /* IP is a MIPS16 instruction whose opcode we have just changed.
3961 Point IP->insn_mo to the new opcode's definition. */
3964 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3966 const struct mips_opcode *mo, *end;
3968 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3969 for (mo = ip->insn_mo; mo < end; mo++)
3970 if ((ip->insn_opcode & mo->mask) == mo->match)
3978 /* For microMIPS macros, we need to generate a local number label
3979 as the target of branches. */
3980 #define MICROMIPS_LABEL_CHAR '\037'
3981 static unsigned long micromips_target_label;
3982 static char micromips_target_name[32];
3985 micromips_label_name (void)
3987 char *p = micromips_target_name;
3988 char symbol_name_temporary[24];
3996 l = micromips_target_label;
3997 #ifdef LOCAL_LABEL_PREFIX
3998 *p++ = LOCAL_LABEL_PREFIX;
4001 *p++ = MICROMIPS_LABEL_CHAR;
4004 symbol_name_temporary[i++] = l % 10 + '0';
4009 *p++ = symbol_name_temporary[--i];
4012 return micromips_target_name;
4016 micromips_label_expr (expressionS *label_expr)
4018 label_expr->X_op = O_symbol;
4019 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4020 label_expr->X_add_number = 0;
4024 micromips_label_inc (void)
4026 micromips_target_label++;
4027 *micromips_target_name = '\0';
4031 micromips_add_label (void)
4035 s = colon (micromips_label_name ());
4036 micromips_label_inc ();
4037 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4039 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4045 /* If assembling microMIPS code, then return the microMIPS reloc
4046 corresponding to the requested one if any. Otherwise return
4047 the reloc unchanged. */
4049 static bfd_reloc_code_real_type
4050 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4052 static const bfd_reloc_code_real_type relocs[][2] =
4054 /* Keep sorted incrementally by the left-hand key. */
4055 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4056 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4057 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4058 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4059 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4060 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4061 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4062 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4063 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4064 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4065 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4066 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4067 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4068 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4069 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4070 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4071 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4072 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4073 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4074 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4075 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4076 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4077 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4078 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4079 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4080 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4081 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4083 bfd_reloc_code_real_type r;
4086 if (!mips_opts.micromips)
4088 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4094 return relocs[i][1];
4099 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4100 Return true on success, storing the resolved value in RESULT. */
4103 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4108 case BFD_RELOC_MIPS_HIGHEST:
4109 case BFD_RELOC_MICROMIPS_HIGHEST:
4110 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4113 case BFD_RELOC_MIPS_HIGHER:
4114 case BFD_RELOC_MICROMIPS_HIGHER:
4115 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4118 case BFD_RELOC_HI16_S:
4119 case BFD_RELOC_MICROMIPS_HI16_S:
4120 case BFD_RELOC_MIPS16_HI16_S:
4121 *result = ((operand + 0x8000) >> 16) & 0xffff;
4124 case BFD_RELOC_HI16:
4125 case BFD_RELOC_MICROMIPS_HI16:
4126 case BFD_RELOC_MIPS16_HI16:
4127 *result = (operand >> 16) & 0xffff;
4130 case BFD_RELOC_LO16:
4131 case BFD_RELOC_MICROMIPS_LO16:
4132 case BFD_RELOC_MIPS16_LO16:
4133 *result = operand & 0xffff;
4136 case BFD_RELOC_UNUSED:
4145 /* Output an instruction. IP is the instruction information.
4146 ADDRESS_EXPR is an operand of the instruction to be used with
4147 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4148 a macro expansion. */
4151 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4152 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4154 unsigned long prev_pinfo2, pinfo;
4155 bfd_boolean relaxed_branch = FALSE;
4156 enum append_method method;
4157 bfd_boolean relax32;
4160 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4161 fix_loongson2f (ip);
4163 file_ase_mips16 |= mips_opts.mips16;
4164 file_ase_micromips |= mips_opts.micromips;
4166 prev_pinfo2 = history[0].insn_mo->pinfo2;
4167 pinfo = ip->insn_mo->pinfo;
4169 if (mips_opts.micromips
4171 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4172 && micromips_insn_length (ip->insn_mo) != 2)
4173 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4174 && micromips_insn_length (ip->insn_mo) != 4)))
4175 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4176 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4178 if (address_expr == NULL)
4180 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4181 && reloc_type[1] == BFD_RELOC_UNUSED
4182 && reloc_type[2] == BFD_RELOC_UNUSED
4183 && address_expr->X_op == O_constant)
4185 switch (*reloc_type)
4187 case BFD_RELOC_MIPS_JMP:
4191 shift = mips_opts.micromips ? 1 : 2;
4192 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4193 as_bad (_("jump to misaligned address (0x%lx)"),
4194 (unsigned long) address_expr->X_add_number);
4195 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4201 case BFD_RELOC_MIPS16_JMP:
4202 if ((address_expr->X_add_number & 3) != 0)
4203 as_bad (_("jump to misaligned address (0x%lx)"),
4204 (unsigned long) address_expr->X_add_number);
4206 (((address_expr->X_add_number & 0x7c0000) << 3)
4207 | ((address_expr->X_add_number & 0xf800000) >> 7)
4208 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4212 case BFD_RELOC_16_PCREL_S2:
4216 shift = mips_opts.micromips ? 1 : 2;
4217 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4218 as_bad (_("branch to misaligned address (0x%lx)"),
4219 (unsigned long) address_expr->X_add_number);
4220 if (!mips_relax_branch)
4222 if ((address_expr->X_add_number + (1 << (shift + 15)))
4223 & ~((1 << (shift + 16)) - 1))
4224 as_bad (_("branch address range overflow (0x%lx)"),
4225 (unsigned long) address_expr->X_add_number);
4226 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4236 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4239 ip->insn_opcode |= value & 0xffff;
4247 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4249 /* There are a lot of optimizations we could do that we don't.
4250 In particular, we do not, in general, reorder instructions.
4251 If you use gcc with optimization, it will reorder
4252 instructions and generally do much more optimization then we
4253 do here; repeating all that work in the assembler would only
4254 benefit hand written assembly code, and does not seem worth
4256 int nops = (mips_optimize == 0
4257 ? nops_for_insn (0, history, NULL)
4258 : nops_for_insn_or_target (0, history, ip));
4262 unsigned long old_frag_offset;
4265 old_frag = frag_now;
4266 old_frag_offset = frag_now_fix ();
4268 for (i = 0; i < nops; i++)
4269 add_fixed_insn (NOP_INSN);
4270 insert_into_history (0, nops, NOP_INSN);
4274 listing_prev_line ();
4275 /* We may be at the start of a variant frag. In case we
4276 are, make sure there is enough space for the frag
4277 after the frags created by listing_prev_line. The
4278 argument to frag_grow here must be at least as large
4279 as the argument to all other calls to frag_grow in
4280 this file. We don't have to worry about being in the
4281 middle of a variant frag, because the variants insert
4282 all needed nop instructions themselves. */
4286 mips_move_text_labels ();
4288 #ifndef NO_ECOFF_DEBUGGING
4289 if (ECOFF_DEBUGGING)
4290 ecoff_fix_loc (old_frag, old_frag_offset);
4294 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4298 /* Work out how many nops in prev_nop_frag are needed by IP,
4299 ignoring hazards generated by the first prev_nop_frag_since
4301 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4302 gas_assert (nops <= prev_nop_frag_holds);
4304 /* Enforce NOPS as a minimum. */
4305 if (nops > prev_nop_frag_required)
4306 prev_nop_frag_required = nops;
4308 if (prev_nop_frag_holds == prev_nop_frag_required)
4310 /* Settle for the current number of nops. Update the history
4311 accordingly (for the benefit of any future .set reorder code). */
4312 prev_nop_frag = NULL;
4313 insert_into_history (prev_nop_frag_since,
4314 prev_nop_frag_holds, NOP_INSN);
4318 /* Allow this instruction to replace one of the nops that was
4319 tentatively added to prev_nop_frag. */
4320 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4321 prev_nop_frag_holds--;
4322 prev_nop_frag_since++;
4326 method = get_append_method (ip, address_expr, reloc_type);
4327 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4330 /* The value passed to dwarf2_emit_insn is the distance between
4331 the beginning of the current instruction and the address that
4332 should be recorded in the debug tables. This is normally the
4335 For MIPS16/microMIPS debug info we want to use ISA-encoded
4336 addresses, so we use -1 for an address higher by one than the
4339 If the instruction produced is a branch that we will swap with
4340 the preceding instruction, then we add the displacement by which
4341 the branch will be moved backwards. This is more appropriate
4342 and for MIPS16/microMIPS code also prevents a debugger from
4343 placing a breakpoint in the middle of the branch (and corrupting
4344 code if software breakpoints are used). */
4345 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4348 relax32 = (mips_relax_branch
4349 /* Don't try branch relaxation within .set nomacro, or within
4350 .set noat if we use $at for PIC computations. If it turns
4351 out that the branch was out-of-range, we'll get an error. */
4352 && !mips_opts.warn_about_macros
4353 && (mips_opts.at || mips_pic == NO_PIC)
4354 /* Don't relax BPOSGE32/64 as they have no complementing
4356 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4358 if (!HAVE_CODE_COMPRESSION
4361 && *reloc_type == BFD_RELOC_16_PCREL_S2
4362 && delayed_branch_p (ip))
4364 relaxed_branch = TRUE;
4365 add_relaxed_insn (ip, (relaxed_branch_length
4367 uncond_branch_p (ip) ? -1
4368 : branch_likely_p (ip) ? 1
4372 uncond_branch_p (ip),
4373 branch_likely_p (ip),
4374 pinfo & INSN_WRITE_GPR_31,
4376 address_expr->X_add_symbol,
4377 address_expr->X_add_number);
4378 *reloc_type = BFD_RELOC_UNUSED;
4380 else if (mips_opts.micromips
4382 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4383 || *reloc_type > BFD_RELOC_UNUSED)
4384 && (delayed_branch_p (ip) || compact_branch_p (ip))
4385 /* Don't try branch relaxation when users specify
4386 16-bit/32-bit instructions. */
4387 && !forced_insn_length)
4389 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4390 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4391 int uncond = uncond_branch_p (ip) ? -1 : 0;
4392 int compact = compact_branch_p (ip);
4393 int al = pinfo & INSN_WRITE_GPR_31;
4396 gas_assert (address_expr != NULL);
4397 gas_assert (!mips_relax.sequence);
4399 relaxed_branch = TRUE;
4400 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4401 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4402 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4404 address_expr->X_add_symbol,
4405 address_expr->X_add_number);
4406 *reloc_type = BFD_RELOC_UNUSED;
4408 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4410 /* We need to set up a variant frag. */
4411 gas_assert (address_expr != NULL);
4412 add_relaxed_insn (ip, 4, 0,
4414 (*reloc_type - BFD_RELOC_UNUSED,
4415 forced_insn_length == 2, forced_insn_length == 4,
4416 delayed_branch_p (&history[0]),
4417 history[0].mips16_absolute_jump_p),
4418 make_expr_symbol (address_expr), 0);
4420 else if (mips_opts.mips16 && insn_length (ip) == 2)
4422 if (!delayed_branch_p (ip))
4423 /* Make sure there is enough room to swap this instruction with
4424 a following jump instruction. */
4426 add_fixed_insn (ip);
4430 if (mips_opts.mips16
4431 && mips_opts.noreorder
4432 && delayed_branch_p (&history[0]))
4433 as_warn (_("extended instruction in delay slot"));
4435 if (mips_relax.sequence)
4437 /* If we've reached the end of this frag, turn it into a variant
4438 frag and record the information for the instructions we've
4440 if (frag_room () < 4)
4441 relax_close_frag ();
4442 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4445 if (mips_relax.sequence != 2)
4447 if (mips_macro_warning.first_insn_sizes[0] == 0)
4448 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4449 mips_macro_warning.sizes[0] += insn_length (ip);
4450 mips_macro_warning.insns[0]++;
4452 if (mips_relax.sequence != 1)
4454 if (mips_macro_warning.first_insn_sizes[1] == 0)
4455 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4456 mips_macro_warning.sizes[1] += insn_length (ip);
4457 mips_macro_warning.insns[1]++;
4460 if (mips_opts.mips16)
4463 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4465 add_fixed_insn (ip);
4468 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4470 bfd_reloc_code_real_type final_type[3];
4471 reloc_howto_type *howto0;
4472 reloc_howto_type *howto;
4475 /* Perform any necessary conversion to microMIPS relocations
4476 and find out how many relocations there actually are. */
4477 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4478 final_type[i] = micromips_map_reloc (reloc_type[i]);
4480 /* In a compound relocation, it is the final (outermost)
4481 operator that determines the relocated field. */
4482 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4486 /* To reproduce this failure try assembling gas/testsuites/
4487 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4489 as_bad (_("Unsupported MIPS relocation number %d"),
4491 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4495 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4496 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4497 bfd_get_reloc_size (howto),
4499 howto0 && howto0->pc_relative,
4502 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4503 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4504 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4506 /* These relocations can have an addend that won't fit in
4507 4 octets for 64bit assembly. */
4509 && ! howto->partial_inplace
4510 && (reloc_type[0] == BFD_RELOC_16
4511 || reloc_type[0] == BFD_RELOC_32
4512 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4513 || reloc_type[0] == BFD_RELOC_GPREL16
4514 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4515 || reloc_type[0] == BFD_RELOC_GPREL32
4516 || reloc_type[0] == BFD_RELOC_64
4517 || reloc_type[0] == BFD_RELOC_CTOR
4518 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4519 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4520 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4521 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4522 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4523 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4524 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4525 || hi16_reloc_p (reloc_type[0])
4526 || lo16_reloc_p (reloc_type[0])))
4527 ip->fixp[0]->fx_no_overflow = 1;
4529 /* These relocations can have an addend that won't fit in 2 octets. */
4530 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4531 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4532 ip->fixp[0]->fx_no_overflow = 1;
4534 if (mips_relax.sequence)
4536 if (mips_relax.first_fixup == 0)
4537 mips_relax.first_fixup = ip->fixp[0];
4539 else if (reloc_needs_lo_p (*reloc_type))
4541 struct mips_hi_fixup *hi_fixup;
4543 /* Reuse the last entry if it already has a matching %lo. */
4544 hi_fixup = mips_hi_fixup_list;
4546 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4548 hi_fixup = ((struct mips_hi_fixup *)
4549 xmalloc (sizeof (struct mips_hi_fixup)));
4550 hi_fixup->next = mips_hi_fixup_list;
4551 mips_hi_fixup_list = hi_fixup;
4553 hi_fixup->fixp = ip->fixp[0];
4554 hi_fixup->seg = now_seg;
4557 /* Add fixups for the second and third relocations, if given.
4558 Note that the ABI allows the second relocation to be
4559 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4560 moment we only use RSS_UNDEF, but we could add support
4561 for the others if it ever becomes necessary. */
4562 for (i = 1; i < 3; i++)
4563 if (reloc_type[i] != BFD_RELOC_UNUSED)
4565 ip->fixp[i] = fix_new (ip->frag, ip->where,
4566 ip->fixp[0]->fx_size, NULL, 0,
4567 FALSE, final_type[i]);
4569 /* Use fx_tcbit to mark compound relocs. */
4570 ip->fixp[0]->fx_tcbit = 1;
4571 ip->fixp[i]->fx_tcbit = 1;
4576 /* Update the register mask information. */
4577 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4578 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4583 insert_into_history (0, 1, ip);
4586 case APPEND_ADD_WITH_NOP:
4588 struct mips_cl_insn *nop;
4590 insert_into_history (0, 1, ip);
4591 nop = get_delay_slot_nop (ip);
4592 add_fixed_insn (nop);
4593 insert_into_history (0, 1, nop);
4594 if (mips_relax.sequence)
4595 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4599 case APPEND_ADD_COMPACT:
4600 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4601 gas_assert (mips_opts.mips16);
4602 ip->insn_opcode |= 0x0080;
4603 find_altered_mips16_opcode (ip);
4605 insert_into_history (0, 1, ip);
4610 struct mips_cl_insn delay = history[0];
4611 if (mips_opts.mips16)
4613 know (delay.frag == ip->frag);
4614 move_insn (ip, delay.frag, delay.where);
4615 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4617 else if (relaxed_branch || delay.frag != ip->frag)
4619 /* Add the delay slot instruction to the end of the
4620 current frag and shrink the fixed part of the
4621 original frag. If the branch occupies the tail of
4622 the latter, move it backwards to cover the gap. */
4623 delay.frag->fr_fix -= branch_disp;
4624 if (delay.frag == ip->frag)
4625 move_insn (ip, ip->frag, ip->where - branch_disp);
4626 add_fixed_insn (&delay);
4630 move_insn (&delay, ip->frag,
4631 ip->where - branch_disp + insn_length (ip));
4632 move_insn (ip, history[0].frag, history[0].where);
4636 insert_into_history (0, 1, &delay);
4641 /* If we have just completed an unconditional branch, clear the history. */
4642 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4643 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4647 mips_no_prev_insn ();
4649 for (i = 0; i < ARRAY_SIZE (history); i++)
4650 history[i].cleared_p = 1;
4653 /* We need to emit a label at the end of branch-likely macros. */
4654 if (emit_branch_likely_macro)
4656 emit_branch_likely_macro = FALSE;
4657 micromips_add_label ();
4660 /* We just output an insn, so the next one doesn't have a label. */
4661 mips_clear_insn_labels ();
4664 /* Forget that there was any previous instruction or label.
4665 When BRANCH is true, the branch history is also flushed. */
4668 mips_no_prev_insn (void)
4670 prev_nop_frag = NULL;
4671 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4672 mips_clear_insn_labels ();
4675 /* This function must be called before we emit something other than
4676 instructions. It is like mips_no_prev_insn except that it inserts
4677 any NOPS that might be needed by previous instructions. */
4680 mips_emit_delays (void)
4682 if (! mips_opts.noreorder)
4684 int nops = nops_for_insn (0, history, NULL);
4688 add_fixed_insn (NOP_INSN);
4689 mips_move_text_labels ();
4692 mips_no_prev_insn ();
4695 /* Start a (possibly nested) noreorder block. */
4698 start_noreorder (void)
4700 if (mips_opts.noreorder == 0)
4705 /* None of the instructions before the .set noreorder can be moved. */
4706 for (i = 0; i < ARRAY_SIZE (history); i++)
4707 history[i].fixed_p = 1;
4709 /* Insert any nops that might be needed between the .set noreorder
4710 block and the previous instructions. We will later remove any
4711 nops that turn out not to be needed. */
4712 nops = nops_for_insn (0, history, NULL);
4715 if (mips_optimize != 0)
4717 /* Record the frag which holds the nop instructions, so
4718 that we can remove them if we don't need them. */
4719 frag_grow (nops * NOP_INSN_SIZE);
4720 prev_nop_frag = frag_now;
4721 prev_nop_frag_holds = nops;
4722 prev_nop_frag_required = 0;
4723 prev_nop_frag_since = 0;
4726 for (; nops > 0; --nops)
4727 add_fixed_insn (NOP_INSN);
4729 /* Move on to a new frag, so that it is safe to simply
4730 decrease the size of prev_nop_frag. */
4731 frag_wane (frag_now);
4733 mips_move_text_labels ();
4735 mips_mark_labels ();
4736 mips_clear_insn_labels ();
4738 mips_opts.noreorder++;
4739 mips_any_noreorder = 1;
4742 /* End a nested noreorder block. */
4745 end_noreorder (void)
4747 mips_opts.noreorder--;
4748 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4750 /* Commit to inserting prev_nop_frag_required nops and go back to
4751 handling nop insertion the .set reorder way. */
4752 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4754 insert_into_history (prev_nop_frag_since,
4755 prev_nop_frag_required, NOP_INSN);
4756 prev_nop_frag = NULL;
4760 /* Set up global variables for the start of a new macro. */
4765 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4766 memset (&mips_macro_warning.first_insn_sizes, 0,
4767 sizeof (mips_macro_warning.first_insn_sizes));
4768 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4769 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4770 && delayed_branch_p (&history[0]));
4771 switch (history[0].insn_mo->pinfo2
4772 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4774 case INSN2_BRANCH_DELAY_32BIT:
4775 mips_macro_warning.delay_slot_length = 4;
4777 case INSN2_BRANCH_DELAY_16BIT:
4778 mips_macro_warning.delay_slot_length = 2;
4781 mips_macro_warning.delay_slot_length = 0;
4784 mips_macro_warning.first_frag = NULL;
4787 /* Given that a macro is longer than one instruction or of the wrong size,
4788 return the appropriate warning for it. Return null if no warning is
4789 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4790 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4791 and RELAX_NOMACRO. */
4794 macro_warning (relax_substateT subtype)
4796 if (subtype & RELAX_DELAY_SLOT)
4797 return _("Macro instruction expanded into multiple instructions"
4798 " in a branch delay slot");
4799 else if (subtype & RELAX_NOMACRO)
4800 return _("Macro instruction expanded into multiple instructions");
4801 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4802 | RELAX_DELAY_SLOT_SIZE_SECOND))
4803 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4804 ? _("Macro instruction expanded into a wrong size instruction"
4805 " in a 16-bit branch delay slot")
4806 : _("Macro instruction expanded into a wrong size instruction"
4807 " in a 32-bit branch delay slot"));
4812 /* Finish up a macro. Emit warnings as appropriate. */
4817 /* Relaxation warning flags. */
4818 relax_substateT subtype = 0;
4820 /* Check delay slot size requirements. */
4821 if (mips_macro_warning.delay_slot_length == 2)
4822 subtype |= RELAX_DELAY_SLOT_16BIT;
4823 if (mips_macro_warning.delay_slot_length != 0)
4825 if (mips_macro_warning.delay_slot_length
4826 != mips_macro_warning.first_insn_sizes[0])
4827 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4828 if (mips_macro_warning.delay_slot_length
4829 != mips_macro_warning.first_insn_sizes[1])
4830 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4833 /* Check instruction count requirements. */
4834 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4836 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4837 subtype |= RELAX_SECOND_LONGER;
4838 if (mips_opts.warn_about_macros)
4839 subtype |= RELAX_NOMACRO;
4840 if (mips_macro_warning.delay_slot_p)
4841 subtype |= RELAX_DELAY_SLOT;
4844 /* If both alternatives fail to fill a delay slot correctly,
4845 emit the warning now. */
4846 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4847 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4852 s = subtype & (RELAX_DELAY_SLOT_16BIT
4853 | RELAX_DELAY_SLOT_SIZE_FIRST
4854 | RELAX_DELAY_SLOT_SIZE_SECOND);
4855 msg = macro_warning (s);
4857 as_warn ("%s", msg);
4861 /* If both implementations are longer than 1 instruction, then emit the
4863 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4868 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4869 msg = macro_warning (s);
4871 as_warn ("%s", msg);
4875 /* If any flags still set, then one implementation might need a warning
4876 and the other either will need one of a different kind or none at all.
4877 Pass any remaining flags over to relaxation. */
4878 if (mips_macro_warning.first_frag != NULL)
4879 mips_macro_warning.first_frag->fr_subtype |= subtype;
4882 /* Instruction operand formats used in macros that vary between
4883 standard MIPS and microMIPS code. */
4885 static const char * const brk_fmt[2] = { "c", "mF" };
4886 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4887 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4888 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4889 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4890 static const char * const mfhl_fmt[2] = { "d", "mj" };
4891 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4892 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4894 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4895 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4896 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4897 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4898 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4899 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4900 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4901 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4903 /* Read a macro's relocation codes from *ARGS and store them in *R.
4904 The first argument in *ARGS will be either the code for a single
4905 relocation or -1 followed by the three codes that make up a
4906 composite relocation. */
4909 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4913 next = va_arg (*args, int);
4915 r[0] = (bfd_reloc_code_real_type) next;
4917 for (i = 0; i < 3; i++)
4918 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4921 /* Build an instruction created by a macro expansion. This is passed
4922 a pointer to the count of instructions created so far, an
4923 expression, the name of the instruction to build, an operand format
4924 string, and corresponding arguments. */
4927 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4929 const struct mips_opcode *mo = NULL;
4930 bfd_reloc_code_real_type r[3];
4931 const struct mips_opcode *amo;
4932 struct hash_control *hash;
4933 struct mips_cl_insn insn;
4936 va_start (args, fmt);
4938 if (mips_opts.mips16)
4940 mips16_macro_build (ep, name, fmt, &args);
4945 r[0] = BFD_RELOC_UNUSED;
4946 r[1] = BFD_RELOC_UNUSED;
4947 r[2] = BFD_RELOC_UNUSED;
4948 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4949 amo = (struct mips_opcode *) hash_find (hash, name);
4951 gas_assert (strcmp (name, amo->name) == 0);
4955 /* Search until we get a match for NAME. It is assumed here that
4956 macros will never generate MDMX, MIPS-3D, or MT instructions.
4957 We try to match an instruction that fulfils the branch delay
4958 slot instruction length requirement (if any) of the previous
4959 instruction. While doing this we record the first instruction
4960 seen that matches all the other conditions and use it anyway
4961 if the requirement cannot be met; we will issue an appropriate
4962 warning later on. */
4963 if (strcmp (fmt, amo->args) == 0
4964 && amo->pinfo != INSN_MACRO
4965 && is_opcode_valid (amo)
4966 && is_size_valid (amo))
4968 if (is_delay_slot_valid (amo))
4978 gas_assert (amo->name);
4980 while (strcmp (name, amo->name) == 0);
4983 create_insn (&insn, mo);
5001 INSERT_OPERAND (mips_opts.micromips,
5002 EXTLSB, insn, va_arg (args, int));
5007 /* Note that in the macro case, these arguments are already
5008 in MSB form. (When handling the instruction in the
5009 non-macro case, these arguments are sizes from which
5010 MSB values must be calculated.) */
5011 INSERT_OPERAND (mips_opts.micromips,
5012 INSMSB, insn, va_arg (args, int));
5018 /* Note that in the macro case, these arguments are already
5019 in MSBD form. (When handling the instruction in the
5020 non-macro case, these arguments are sizes from which
5021 MSBD values must be calculated.) */
5022 INSERT_OPERAND (mips_opts.micromips,
5023 EXTMSBD, insn, va_arg (args, int));
5027 gas_assert (!mips_opts.micromips);
5028 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5037 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5041 gas_assert (mips_opts.micromips);
5045 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5049 gas_assert (!mips_opts.micromips);
5050 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5054 gas_assert (!mips_opts.micromips);
5056 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5060 if (mips_opts.micromips)
5061 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5063 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5067 gas_assert (!mips_opts.micromips);
5069 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5073 gas_assert (!mips_opts.micromips);
5075 int tmp = va_arg (args, int);
5077 INSERT_OPERAND (0, RT, insn, tmp);
5078 INSERT_OPERAND (0, RD, insn, tmp);
5084 gas_assert (!mips_opts.micromips);
5085 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5092 INSERT_OPERAND (mips_opts.micromips,
5093 SHAMT, insn, va_arg (args, int));
5097 gas_assert (!mips_opts.micromips);
5098 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5102 gas_assert (!mips_opts.micromips);
5103 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5107 gas_assert (!mips_opts.micromips);
5108 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5112 gas_assert (!mips_opts.micromips);
5113 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5120 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5125 macro_read_relocs (&args, r);
5126 gas_assert (*r == BFD_RELOC_GPREL16
5127 || *r == BFD_RELOC_MIPS_HIGHER
5128 || *r == BFD_RELOC_HI16_S
5129 || *r == BFD_RELOC_LO16
5130 || *r == BFD_RELOC_MIPS_GOT_OFST);
5134 macro_read_relocs (&args, r);
5138 macro_read_relocs (&args, r);
5139 gas_assert (ep != NULL
5140 && (ep->X_op == O_constant
5141 || (ep->X_op == O_symbol
5142 && (*r == BFD_RELOC_MIPS_HIGHEST
5143 || *r == BFD_RELOC_HI16_S
5144 || *r == BFD_RELOC_HI16
5145 || *r == BFD_RELOC_GPREL16
5146 || *r == BFD_RELOC_MIPS_GOT_HI16
5147 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5151 gas_assert (ep != NULL);
5154 * This allows macro() to pass an immediate expression for
5155 * creating short branches without creating a symbol.
5157 * We don't allow branch relaxation for these branches, as
5158 * they should only appear in ".set nomacro" anyway.
5160 if (ep->X_op == O_constant)
5162 /* For microMIPS we always use relocations for branches.
5163 So we should not resolve immediate values. */
5164 gas_assert (!mips_opts.micromips);
5166 if ((ep->X_add_number & 3) != 0)
5167 as_bad (_("branch to misaligned address (0x%lx)"),
5168 (unsigned long) ep->X_add_number);
5169 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5170 as_bad (_("branch address range overflow (0x%lx)"),
5171 (unsigned long) ep->X_add_number);
5172 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5176 *r = BFD_RELOC_16_PCREL_S2;
5180 gas_assert (ep != NULL);
5181 *r = BFD_RELOC_MIPS_JMP;
5185 gas_assert (!mips_opts.micromips);
5186 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5190 INSERT_OPERAND (mips_opts.micromips,
5191 CACHE, insn, va_arg (args, unsigned long));
5195 gas_assert (mips_opts.micromips);
5196 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5200 gas_assert (mips_opts.micromips);
5201 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5205 INSERT_OPERAND (mips_opts.micromips,
5206 3BITPOS, insn, va_arg (args, unsigned int));
5210 INSERT_OPERAND (mips_opts.micromips,
5211 OFFSET12, insn, va_arg (args, unsigned long));
5215 gas_assert (mips_opts.micromips);
5216 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5219 case 'm': /* Opcode extension character. */
5220 gas_assert (mips_opts.micromips);
5224 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5228 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5232 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5246 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5248 append_insn (&insn, ep, r, TRUE);
5252 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5255 struct mips_opcode *mo;
5256 struct mips_cl_insn insn;
5257 bfd_reloc_code_real_type r[3]
5258 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5260 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5262 gas_assert (strcmp (name, mo->name) == 0);
5264 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5267 gas_assert (mo->name);
5268 gas_assert (strcmp (name, mo->name) == 0);
5271 create_insn (&insn, mo);
5289 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5294 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5298 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5302 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5312 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5319 regno = va_arg (*args, int);
5320 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5321 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5344 gas_assert (ep != NULL);
5346 if (ep->X_op != O_constant)
5347 *r = (int) BFD_RELOC_UNUSED + c;
5348 else if (calculate_reloc (*r, ep->X_add_number, &value))
5350 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5352 *r = BFD_RELOC_UNUSED;
5358 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5365 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5367 append_insn (&insn, ep, r, TRUE);
5371 * Sign-extend 32-bit mode constants that have bit 31 set and all
5372 * higher bits unset.
5375 normalize_constant_expr (expressionS *ex)
5377 if (ex->X_op == O_constant
5378 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5379 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5384 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5385 * all higher bits unset.
5388 normalize_address_expr (expressionS *ex)
5390 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5391 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5392 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5393 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5398 * Generate a "jalr" instruction with a relocation hint to the called
5399 * function. This occurs in NewABI PIC code.
5402 macro_build_jalr (expressionS *ep, int cprestore)
5404 static const bfd_reloc_code_real_type jalr_relocs[2]
5405 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5406 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5410 if (MIPS_JALR_HINT_P (ep))
5415 if (mips_opts.micromips)
5417 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5418 if (MIPS_JALR_HINT_P (ep)
5419 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5420 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5422 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5425 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5426 if (MIPS_JALR_HINT_P (ep))
5427 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5431 * Generate a "lui" instruction.
5434 macro_build_lui (expressionS *ep, int regnum)
5436 gas_assert (! mips_opts.mips16);
5438 if (ep->X_op != O_constant)
5440 gas_assert (ep->X_op == O_symbol);
5441 /* _gp_disp is a special case, used from s_cpload.
5442 __gnu_local_gp is used if mips_no_shared. */
5443 gas_assert (mips_pic == NO_PIC
5445 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5446 || (! mips_in_shared
5447 && strcmp (S_GET_NAME (ep->X_add_symbol),
5448 "__gnu_local_gp") == 0));
5451 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5454 /* Generate a sequence of instructions to do a load or store from a constant
5455 offset off of a base register (breg) into/from a target register (treg),
5456 using AT if necessary. */
5458 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5459 int treg, int breg, int dbl)
5461 gas_assert (ep->X_op == O_constant);
5463 /* Sign-extending 32-bit constants makes their handling easier. */
5465 normalize_constant_expr (ep);
5467 /* Right now, this routine can only handle signed 32-bit constants. */
5468 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5469 as_warn (_("operand overflow"));
5471 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5473 /* Signed 16-bit offset will fit in the op. Easy! */
5474 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5478 /* 32-bit offset, need multiple instructions and AT, like:
5479 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5480 addu $tempreg,$tempreg,$breg
5481 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5482 to handle the complete offset. */
5483 macro_build_lui (ep, AT);
5484 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5485 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5488 as_bad (_("Macro used $at after \".set noat\""));
5493 * Generates code to set the $at register to true (one)
5494 * if reg is less than the immediate expression.
5497 set_at (int reg, int unsignedp)
5499 if (imm_expr.X_op == O_constant
5500 && imm_expr.X_add_number >= -0x8000
5501 && imm_expr.X_add_number < 0x8000)
5502 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5503 AT, reg, BFD_RELOC_LO16);
5506 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5507 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5511 /* Warn if an expression is not a constant. */
5514 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5516 if (ex->X_op == O_big)
5517 as_bad (_("unsupported large constant"));
5518 else if (ex->X_op != O_constant)
5519 as_bad (_("Instruction %s requires absolute expression"),
5522 if (HAVE_32BIT_GPRS)
5523 normalize_constant_expr (ex);
5526 /* Count the leading zeroes by performing a binary chop. This is a
5527 bulky bit of source, but performance is a LOT better for the
5528 majority of values than a simple loop to count the bits:
5529 for (lcnt = 0; (lcnt < 32); lcnt++)
5530 if ((v) & (1 << (31 - lcnt)))
5532 However it is not code size friendly, and the gain will drop a bit
5533 on certain cached systems.
5535 #define COUNT_TOP_ZEROES(v) \
5536 (((v) & ~0xffff) == 0 \
5537 ? ((v) & ~0xff) == 0 \
5538 ? ((v) & ~0xf) == 0 \
5539 ? ((v) & ~0x3) == 0 \
5540 ? ((v) & ~0x1) == 0 \
5545 : ((v) & ~0x7) == 0 \
5548 : ((v) & ~0x3f) == 0 \
5549 ? ((v) & ~0x1f) == 0 \
5552 : ((v) & ~0x7f) == 0 \
5555 : ((v) & ~0xfff) == 0 \
5556 ? ((v) & ~0x3ff) == 0 \
5557 ? ((v) & ~0x1ff) == 0 \
5560 : ((v) & ~0x7ff) == 0 \
5563 : ((v) & ~0x3fff) == 0 \
5564 ? ((v) & ~0x1fff) == 0 \
5567 : ((v) & ~0x7fff) == 0 \
5570 : ((v) & ~0xffffff) == 0 \
5571 ? ((v) & ~0xfffff) == 0 \
5572 ? ((v) & ~0x3ffff) == 0 \
5573 ? ((v) & ~0x1ffff) == 0 \
5576 : ((v) & ~0x7ffff) == 0 \
5579 : ((v) & ~0x3fffff) == 0 \
5580 ? ((v) & ~0x1fffff) == 0 \
5583 : ((v) & ~0x7fffff) == 0 \
5586 : ((v) & ~0xfffffff) == 0 \
5587 ? ((v) & ~0x3ffffff) == 0 \
5588 ? ((v) & ~0x1ffffff) == 0 \
5591 : ((v) & ~0x7ffffff) == 0 \
5594 : ((v) & ~0x3fffffff) == 0 \
5595 ? ((v) & ~0x1fffffff) == 0 \
5598 : ((v) & ~0x7fffffff) == 0 \
5603 * This routine generates the least number of instructions necessary to load
5604 * an absolute expression value into a register.
5607 load_register (int reg, expressionS *ep, int dbl)
5610 expressionS hi32, lo32;
5612 if (ep->X_op != O_big)
5614 gas_assert (ep->X_op == O_constant);
5616 /* Sign-extending 32-bit constants makes their handling easier. */
5618 normalize_constant_expr (ep);
5620 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5622 /* We can handle 16 bit signed values with an addiu to
5623 $zero. No need to ever use daddiu here, since $zero and
5624 the result are always correct in 32 bit mode. */
5625 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5628 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5630 /* We can handle 16 bit unsigned values with an ori to
5632 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5635 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5637 /* 32 bit values require an lui. */
5638 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5639 if ((ep->X_add_number & 0xffff) != 0)
5640 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5645 /* The value is larger than 32 bits. */
5647 if (!dbl || HAVE_32BIT_GPRS)
5651 sprintf_vma (value, ep->X_add_number);
5652 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5653 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5657 if (ep->X_op != O_big)
5660 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5661 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5662 hi32.X_add_number &= 0xffffffff;
5664 lo32.X_add_number &= 0xffffffff;
5668 gas_assert (ep->X_add_number > 2);
5669 if (ep->X_add_number == 3)
5670 generic_bignum[3] = 0;
5671 else if (ep->X_add_number > 4)
5672 as_bad (_("Number larger than 64 bits"));
5673 lo32.X_op = O_constant;
5674 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5675 hi32.X_op = O_constant;
5676 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5679 if (hi32.X_add_number == 0)
5684 unsigned long hi, lo;
5686 if (hi32.X_add_number == (offsetT) 0xffffffff)
5688 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5690 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5693 if (lo32.X_add_number & 0x80000000)
5695 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5696 if (lo32.X_add_number & 0xffff)
5697 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5702 /* Check for 16bit shifted constant. We know that hi32 is
5703 non-zero, so start the mask on the first bit of the hi32
5708 unsigned long himask, lomask;
5712 himask = 0xffff >> (32 - shift);
5713 lomask = (0xffff << shift) & 0xffffffff;
5717 himask = 0xffff << (shift - 32);
5720 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5721 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5725 tmp.X_op = O_constant;
5727 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5728 | (lo32.X_add_number >> shift));
5730 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5731 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5732 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5733 reg, reg, (shift >= 32) ? shift - 32 : shift);
5738 while (shift <= (64 - 16));
5740 /* Find the bit number of the lowest one bit, and store the
5741 shifted value in hi/lo. */
5742 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5743 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5747 while ((lo & 1) == 0)
5752 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5758 while ((hi & 1) == 0)
5767 /* Optimize if the shifted value is a (power of 2) - 1. */
5768 if ((hi == 0 && ((lo + 1) & lo) == 0)
5769 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5771 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5776 /* This instruction will set the register to be all
5778 tmp.X_op = O_constant;
5779 tmp.X_add_number = (offsetT) -1;
5780 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5784 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5785 reg, reg, (bit >= 32) ? bit - 32 : bit);
5787 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5788 reg, reg, (shift >= 32) ? shift - 32 : shift);
5793 /* Sign extend hi32 before calling load_register, because we can
5794 generally get better code when we load a sign extended value. */
5795 if ((hi32.X_add_number & 0x80000000) != 0)
5796 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5797 load_register (reg, &hi32, 0);
5800 if ((lo32.X_add_number & 0xffff0000) == 0)
5804 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5812 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5814 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5815 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5821 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5825 mid16.X_add_number >>= 16;
5826 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5827 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5830 if ((lo32.X_add_number & 0xffff) != 0)
5831 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5835 load_delay_nop (void)
5837 if (!gpr_interlocks)
5838 macro_build (NULL, "nop", "");
5841 /* Load an address into a register. */
5844 load_address (int reg, expressionS *ep, int *used_at)
5846 if (ep->X_op != O_constant
5847 && ep->X_op != O_symbol)
5849 as_bad (_("expression too complex"));
5850 ep->X_op = O_constant;
5853 if (ep->X_op == O_constant)
5855 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5859 if (mips_pic == NO_PIC)
5861 /* If this is a reference to a GP relative symbol, we want
5862 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5864 lui $reg,<sym> (BFD_RELOC_HI16_S)
5865 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5866 If we have an addend, we always use the latter form.
5868 With 64bit address space and a usable $at we want
5869 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5870 lui $at,<sym> (BFD_RELOC_HI16_S)
5871 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5872 daddiu $at,<sym> (BFD_RELOC_LO16)
5876 If $at is already in use, we use a path which is suboptimal
5877 on superscalar processors.
5878 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5879 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5881 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5883 daddiu $reg,<sym> (BFD_RELOC_LO16)
5885 For GP relative symbols in 64bit address space we can use
5886 the same sequence as in 32bit address space. */
5887 if (HAVE_64BIT_SYMBOLS)
5889 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5890 && !nopic_need_relax (ep->X_add_symbol, 1))
5892 relax_start (ep->X_add_symbol);
5893 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5894 mips_gp_register, BFD_RELOC_GPREL16);
5898 if (*used_at == 0 && mips_opts.at)
5900 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5901 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5902 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5903 BFD_RELOC_MIPS_HIGHER);
5904 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5905 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5906 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5911 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5912 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5913 BFD_RELOC_MIPS_HIGHER);
5914 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5915 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5916 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5917 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5920 if (mips_relax.sequence)
5925 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5926 && !nopic_need_relax (ep->X_add_symbol, 1))
5928 relax_start (ep->X_add_symbol);
5929 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5930 mips_gp_register, BFD_RELOC_GPREL16);
5933 macro_build_lui (ep, reg);
5934 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5935 reg, reg, BFD_RELOC_LO16);
5936 if (mips_relax.sequence)
5940 else if (!mips_big_got)
5944 /* If this is a reference to an external symbol, we want
5945 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5947 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5949 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5950 If there is a constant, it must be added in after.
5952 If we have NewABI, we want
5953 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5954 unless we're referencing a global symbol with a non-zero
5955 offset, in which case cst must be added separately. */
5958 if (ep->X_add_number)
5960 ex.X_add_number = ep->X_add_number;
5961 ep->X_add_number = 0;
5962 relax_start (ep->X_add_symbol);
5963 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5964 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5965 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5966 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5967 ex.X_op = O_constant;
5968 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5969 reg, reg, BFD_RELOC_LO16);
5970 ep->X_add_number = ex.X_add_number;
5973 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5974 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5975 if (mips_relax.sequence)
5980 ex.X_add_number = ep->X_add_number;
5981 ep->X_add_number = 0;
5982 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5983 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5985 relax_start (ep->X_add_symbol);
5987 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5991 if (ex.X_add_number != 0)
5993 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5994 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5995 ex.X_op = O_constant;
5996 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5997 reg, reg, BFD_RELOC_LO16);
6001 else if (mips_big_got)
6005 /* This is the large GOT case. If this is a reference to an
6006 external symbol, we want
6007 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6009 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6011 Otherwise, for a reference to a local symbol in old ABI, we want
6012 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6014 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6015 If there is a constant, it must be added in after.
6017 In the NewABI, for local symbols, with or without offsets, we want:
6018 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6019 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6023 ex.X_add_number = ep->X_add_number;
6024 ep->X_add_number = 0;
6025 relax_start (ep->X_add_symbol);
6026 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6027 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6028 reg, reg, mips_gp_register);
6029 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6030 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6031 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6032 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6033 else if (ex.X_add_number)
6035 ex.X_op = O_constant;
6036 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6040 ep->X_add_number = ex.X_add_number;
6042 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6043 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6044 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6045 BFD_RELOC_MIPS_GOT_OFST);
6050 ex.X_add_number = ep->X_add_number;
6051 ep->X_add_number = 0;
6052 relax_start (ep->X_add_symbol);
6053 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6055 reg, reg, mips_gp_register);
6056 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6057 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6059 if (reg_needs_delay (mips_gp_register))
6061 /* We need a nop before loading from $gp. This special
6062 check is required because the lui which starts the main
6063 instruction stream does not refer to $gp, and so will not
6064 insert the nop which may be required. */
6065 macro_build (NULL, "nop", "");
6067 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6068 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6070 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6074 if (ex.X_add_number != 0)
6076 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6077 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6078 ex.X_op = O_constant;
6079 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6087 if (!mips_opts.at && *used_at == 1)
6088 as_bad (_("Macro used $at after \".set noat\""));
6091 /* Move the contents of register SOURCE into register DEST. */
6094 move_register (int dest, int source)
6096 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6097 instruction specifically requires a 32-bit one. */
6098 if (mips_opts.micromips
6099 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6100 macro_build (NULL, "move", "mp,mj", dest, source);
6102 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6106 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6107 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6108 The two alternatives are:
6110 Global symbol Local sybmol
6111 ------------- ------------
6112 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6114 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6116 load_got_offset emits the first instruction and add_got_offset
6117 emits the second for a 16-bit offset or add_got_offset_hilo emits
6118 a sequence to add a 32-bit offset using a scratch register. */
6121 load_got_offset (int dest, expressionS *local)
6126 global.X_add_number = 0;
6128 relax_start (local->X_add_symbol);
6129 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6130 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6132 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6133 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6138 add_got_offset (int dest, expressionS *local)
6142 global.X_op = O_constant;
6143 global.X_op_symbol = NULL;
6144 global.X_add_symbol = NULL;
6145 global.X_add_number = local->X_add_number;
6147 relax_start (local->X_add_symbol);
6148 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6149 dest, dest, BFD_RELOC_LO16);
6151 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6156 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6159 int hold_mips_optimize;
6161 global.X_op = O_constant;
6162 global.X_op_symbol = NULL;
6163 global.X_add_symbol = NULL;
6164 global.X_add_number = local->X_add_number;
6166 relax_start (local->X_add_symbol);
6167 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6169 /* Set mips_optimize around the lui instruction to avoid
6170 inserting an unnecessary nop after the lw. */
6171 hold_mips_optimize = mips_optimize;
6173 macro_build_lui (&global, tmp);
6174 mips_optimize = hold_mips_optimize;
6175 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6181 /* Emit a sequence of instructions to emulate a branch likely operation.
6182 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6183 is its complementing branch with the original condition negated.
6184 CALL is set if the original branch specified the link operation.
6185 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6187 Code like this is produced in the noreorder mode:
6192 delay slot (executed only if branch taken)
6200 delay slot (executed only if branch taken)
6203 In the reorder mode the delay slot would be filled with a nop anyway,
6204 so code produced is simply:
6209 This function is used when producing code for the microMIPS ASE that
6210 does not implement branch likely instructions in hardware. */
6213 macro_build_branch_likely (const char *br, const char *brneg,
6214 int call, expressionS *ep, const char *fmt,
6215 unsigned int sreg, unsigned int treg)
6217 int noreorder = mips_opts.noreorder;
6220 gas_assert (mips_opts.micromips);
6224 micromips_label_expr (&expr1);
6225 macro_build (&expr1, brneg, fmt, sreg, treg);
6226 macro_build (NULL, "nop", "");
6227 macro_build (ep, call ? "bal" : "b", "p");
6229 /* Set to true so that append_insn adds a label. */
6230 emit_branch_likely_macro = TRUE;
6234 macro_build (ep, br, fmt, sreg, treg);
6235 macro_build (NULL, "nop", "");
6240 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6241 the condition code tested. EP specifies the branch target. */
6244 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6271 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6274 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6275 the register tested. EP specifies the branch target. */
6278 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6280 const char *brneg = NULL;
6290 br = mips_opts.micromips ? "bgez" : "bgezl";
6294 gas_assert (mips_opts.micromips);
6303 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6310 br = mips_opts.micromips ? "blez" : "blezl";
6317 br = mips_opts.micromips ? "bltz" : "bltzl";
6321 gas_assert (mips_opts.micromips);
6329 if (mips_opts.micromips && brneg)
6330 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6332 macro_build (ep, br, "s,p", sreg);
6335 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6336 TREG as the registers tested. EP specifies the branch target. */
6339 macro_build_branch_rsrt (int type, expressionS *ep,
6340 unsigned int sreg, unsigned int treg)
6342 const char *brneg = NULL;
6354 br = mips_opts.micromips ? "beq" : "beql";
6363 br = mips_opts.micromips ? "bne" : "bnel";
6369 if (mips_opts.micromips && brneg)
6370 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6372 macro_build (ep, br, "s,t,p", sreg, treg);
6377 * This routine implements the seemingly endless macro or synthesized
6378 * instructions and addressing modes in the mips assembly language. Many
6379 * of these macros are simple and are similar to each other. These could
6380 * probably be handled by some kind of table or grammar approach instead of
6381 * this verbose method. Others are not simple macros but are more like
6382 * optimizing code generation.
6383 * One interesting optimization is when several store macros appear
6384 * consecutively that would load AT with the upper half of the same address.
6385 * The ensuing load upper instructions are ommited. This implies some kind
6386 * of global optimization. We currently only optimize within a single macro.
6387 * For many of the load and store macros if the address is specified as a
6388 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6389 * first load register 'at' with zero and use it as the base register. The
6390 * mips assembler simply uses register $zero. Just one tiny optimization
6394 macro (struct mips_cl_insn *ip)
6396 unsigned int treg, sreg, dreg, breg;
6397 unsigned int tempreg;
6400 expressionS label_expr;
6419 bfd_reloc_code_real_type r;
6420 int hold_mips_optimize;
6422 gas_assert (! mips_opts.mips16);
6424 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6425 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6426 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6427 mask = ip->insn_mo->mask;
6429 label_expr.X_op = O_constant;
6430 label_expr.X_op_symbol = NULL;
6431 label_expr.X_add_symbol = NULL;
6432 label_expr.X_add_number = 0;
6434 expr1.X_op = O_constant;
6435 expr1.X_op_symbol = NULL;
6436 expr1.X_add_symbol = NULL;
6437 expr1.X_add_number = 1;
6452 if (mips_opts.micromips)
6453 micromips_label_expr (&label_expr);
6455 label_expr.X_add_number = 8;
6456 macro_build (&label_expr, "bgez", "s,p", sreg);
6458 macro_build (NULL, "nop", "");
6460 move_register (dreg, sreg);
6461 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6462 if (mips_opts.micromips)
6463 micromips_add_label ();
6480 if (!mips_opts.micromips)
6482 if (imm_expr.X_op == O_constant
6483 && imm_expr.X_add_number >= -0x200
6484 && imm_expr.X_add_number < 0x200)
6486 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6495 if (imm_expr.X_op == O_constant
6496 && imm_expr.X_add_number >= -0x8000
6497 && imm_expr.X_add_number < 0x8000)
6499 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6504 load_register (AT, &imm_expr, dbl);
6505 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6524 if (imm_expr.X_op == O_constant
6525 && imm_expr.X_add_number >= 0
6526 && imm_expr.X_add_number < 0x10000)
6528 if (mask != M_NOR_I)
6529 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6532 macro_build (&imm_expr, "ori", "t,r,i",
6533 treg, sreg, BFD_RELOC_LO16);
6534 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6540 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6541 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6545 switch (imm_expr.X_add_number)
6548 macro_build (NULL, "nop", "");
6551 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6555 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6556 (int) imm_expr.X_add_number);
6559 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6560 (unsigned long) imm_expr.X_add_number);
6569 gas_assert (mips_opts.micromips);
6570 macro_build_branch_ccl (mask, &offset_expr,
6571 EXTRACT_OPERAND (1, BCC, *ip));
6578 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6584 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6589 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6596 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6598 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6602 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6603 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6604 &offset_expr, AT, ZERO);
6614 macro_build_branch_rs (mask, &offset_expr, sreg);
6620 /* Check for > max integer. */
6621 maxnum = 0x7fffffff;
6622 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6629 if (imm_expr.X_op == O_constant
6630 && imm_expr.X_add_number >= maxnum
6631 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6634 /* Result is always false. */
6636 macro_build (NULL, "nop", "");
6638 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6641 if (imm_expr.X_op != O_constant)
6642 as_bad (_("Unsupported large constant"));
6643 ++imm_expr.X_add_number;
6647 if (mask == M_BGEL_I)
6649 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6651 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6652 &offset_expr, sreg);
6655 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6657 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6658 &offset_expr, sreg);
6661 maxnum = 0x7fffffff;
6662 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6669 maxnum = - maxnum - 1;
6670 if (imm_expr.X_op == O_constant
6671 && imm_expr.X_add_number <= maxnum
6672 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6675 /* result is always true */
6676 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6677 macro_build (&offset_expr, "b", "p");
6682 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6683 &offset_expr, AT, ZERO);
6692 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6693 &offset_expr, ZERO, treg);
6697 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6698 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6699 &offset_expr, AT, ZERO);
6708 && imm_expr.X_op == O_constant
6709 && imm_expr.X_add_number == -1))
6711 if (imm_expr.X_op != O_constant)
6712 as_bad (_("Unsupported large constant"));
6713 ++imm_expr.X_add_number;
6717 if (mask == M_BGEUL_I)
6719 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6721 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6722 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6723 &offset_expr, sreg, ZERO);
6728 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6729 &offset_expr, AT, ZERO);
6737 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6739 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6743 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6744 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6745 &offset_expr, AT, ZERO);
6753 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6754 &offset_expr, sreg, ZERO);
6760 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6761 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6762 &offset_expr, AT, ZERO);
6770 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6772 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6776 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6777 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6778 &offset_expr, AT, ZERO);
6785 maxnum = 0x7fffffff;
6786 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6793 if (imm_expr.X_op == O_constant
6794 && imm_expr.X_add_number >= maxnum
6795 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6797 if (imm_expr.X_op != O_constant)
6798 as_bad (_("Unsupported large constant"));
6799 ++imm_expr.X_add_number;
6803 if (mask == M_BLTL_I)
6805 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6806 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6807 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6808 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6813 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6814 &offset_expr, AT, ZERO);
6822 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6823 &offset_expr, sreg, ZERO);
6829 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6830 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6831 &offset_expr, AT, ZERO);
6840 && imm_expr.X_op == O_constant
6841 && imm_expr.X_add_number == -1))
6843 if (imm_expr.X_op != O_constant)
6844 as_bad (_("Unsupported large constant"));
6845 ++imm_expr.X_add_number;
6849 if (mask == M_BLTUL_I)
6851 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6853 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6854 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6855 &offset_expr, sreg, ZERO);
6860 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6861 &offset_expr, AT, ZERO);
6869 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6871 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6875 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6876 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6877 &offset_expr, AT, ZERO);
6887 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6888 &offset_expr, ZERO, treg);
6892 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6893 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6894 &offset_expr, AT, ZERO);
6900 /* Use unsigned arithmetic. */
6904 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6906 as_bad (_("Unsupported large constant"));
6911 pos = imm_expr.X_add_number;
6912 size = imm2_expr.X_add_number;
6917 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6920 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6922 as_bad (_("Improper extract size (%lu, position %lu)"),
6923 (unsigned long) size, (unsigned long) pos);
6927 if (size <= 32 && pos < 32)
6932 else if (size <= 32)
6942 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6949 /* Use unsigned arithmetic. */
6953 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6955 as_bad (_("Unsupported large constant"));
6960 pos = imm_expr.X_add_number;
6961 size = imm2_expr.X_add_number;
6966 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6969 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6971 as_bad (_("Improper insert size (%lu, position %lu)"),
6972 (unsigned long) size, (unsigned long) pos);
6976 if (pos < 32 && (pos + size - 1) < 32)
6991 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6992 (int) (pos + size - 1));
7008 as_warn (_("Divide by zero."));
7010 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7012 macro_build (NULL, "break", BRK_FMT, 7);
7019 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7020 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7024 if (mips_opts.micromips)
7025 micromips_label_expr (&label_expr);
7027 label_expr.X_add_number = 8;
7028 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7029 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7030 macro_build (NULL, "break", BRK_FMT, 7);
7031 if (mips_opts.micromips)
7032 micromips_add_label ();
7034 expr1.X_add_number = -1;
7036 load_register (AT, &expr1, dbl);
7037 if (mips_opts.micromips)
7038 micromips_label_expr (&label_expr);
7040 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7041 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7044 expr1.X_add_number = 1;
7045 load_register (AT, &expr1, dbl);
7046 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7050 expr1.X_add_number = 0x80000000;
7051 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7055 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7056 /* We want to close the noreorder block as soon as possible, so
7057 that later insns are available for delay slot filling. */
7062 if (mips_opts.micromips)
7063 micromips_label_expr (&label_expr);
7065 label_expr.X_add_number = 8;
7066 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7067 macro_build (NULL, "nop", "");
7069 /* We want to close the noreorder block as soon as possible, so
7070 that later insns are available for delay slot filling. */
7073 macro_build (NULL, "break", BRK_FMT, 6);
7075 if (mips_opts.micromips)
7076 micromips_add_label ();
7077 macro_build (NULL, s, MFHL_FMT, dreg);
7116 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7118 as_warn (_("Divide by zero."));
7120 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7122 macro_build (NULL, "break", BRK_FMT, 7);
7125 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7127 if (strcmp (s2, "mflo") == 0)
7128 move_register (dreg, sreg);
7130 move_register (dreg, ZERO);
7133 if (imm_expr.X_op == O_constant
7134 && imm_expr.X_add_number == -1
7135 && s[strlen (s) - 1] != 'u')
7137 if (strcmp (s2, "mflo") == 0)
7139 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7142 move_register (dreg, ZERO);
7147 load_register (AT, &imm_expr, dbl);
7148 macro_build (NULL, s, "z,s,t", sreg, AT);
7149 macro_build (NULL, s2, MFHL_FMT, dreg);
7171 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7172 macro_build (NULL, s, "z,s,t", sreg, treg);
7173 /* We want to close the noreorder block as soon as possible, so
7174 that later insns are available for delay slot filling. */
7179 if (mips_opts.micromips)
7180 micromips_label_expr (&label_expr);
7182 label_expr.X_add_number = 8;
7183 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7184 macro_build (NULL, s, "z,s,t", sreg, treg);
7186 /* We want to close the noreorder block as soon as possible, so
7187 that later insns are available for delay slot filling. */
7189 macro_build (NULL, "break", BRK_FMT, 7);
7190 if (mips_opts.micromips)
7191 micromips_add_label ();
7193 macro_build (NULL, s2, MFHL_FMT, dreg);
7205 /* Load the address of a symbol into a register. If breg is not
7206 zero, we then add a base register to it. */
7208 if (dbl && HAVE_32BIT_GPRS)
7209 as_warn (_("dla used to load 32-bit register"));
7211 if (!dbl && HAVE_64BIT_OBJECTS)
7212 as_warn (_("la used to load 64-bit address"));
7214 if (offset_expr.X_op == O_constant
7215 && offset_expr.X_add_number >= -0x8000
7216 && offset_expr.X_add_number < 0x8000)
7218 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7219 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7223 if (mips_opts.at && (treg == breg))
7233 if (offset_expr.X_op != O_symbol
7234 && offset_expr.X_op != O_constant)
7236 as_bad (_("Expression too complex"));
7237 offset_expr.X_op = O_constant;
7240 if (offset_expr.X_op == O_constant)
7241 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7242 else if (mips_pic == NO_PIC)
7244 /* If this is a reference to a GP relative symbol, we want
7245 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7247 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7248 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7249 If we have a constant, we need two instructions anyhow,
7250 so we may as well always use the latter form.
7252 With 64bit address space and a usable $at we want
7253 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7254 lui $at,<sym> (BFD_RELOC_HI16_S)
7255 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7256 daddiu $at,<sym> (BFD_RELOC_LO16)
7258 daddu $tempreg,$tempreg,$at
7260 If $at is already in use, we use a path which is suboptimal
7261 on superscalar processors.
7262 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7263 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7265 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7267 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7269 For GP relative symbols in 64bit address space we can use
7270 the same sequence as in 32bit address space. */
7271 if (HAVE_64BIT_SYMBOLS)
7273 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7274 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7276 relax_start (offset_expr.X_add_symbol);
7277 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7278 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7282 if (used_at == 0 && mips_opts.at)
7284 macro_build (&offset_expr, "lui", LUI_FMT,
7285 tempreg, BFD_RELOC_MIPS_HIGHEST);
7286 macro_build (&offset_expr, "lui", LUI_FMT,
7287 AT, BFD_RELOC_HI16_S);
7288 macro_build (&offset_expr, "daddiu", "t,r,j",
7289 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7290 macro_build (&offset_expr, "daddiu", "t,r,j",
7291 AT, AT, BFD_RELOC_LO16);
7292 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7293 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7298 macro_build (&offset_expr, "lui", LUI_FMT,
7299 tempreg, BFD_RELOC_MIPS_HIGHEST);
7300 macro_build (&offset_expr, "daddiu", "t,r,j",
7301 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7302 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7303 macro_build (&offset_expr, "daddiu", "t,r,j",
7304 tempreg, tempreg, BFD_RELOC_HI16_S);
7305 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7306 macro_build (&offset_expr, "daddiu", "t,r,j",
7307 tempreg, tempreg, BFD_RELOC_LO16);
7310 if (mips_relax.sequence)
7315 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7316 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7318 relax_start (offset_expr.X_add_symbol);
7319 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7320 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7323 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7324 as_bad (_("Offset too large"));
7325 macro_build_lui (&offset_expr, tempreg);
7326 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7327 tempreg, tempreg, BFD_RELOC_LO16);
7328 if (mips_relax.sequence)
7332 else if (!mips_big_got && !HAVE_NEWABI)
7334 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7336 /* If this is a reference to an external symbol, and there
7337 is no constant, we want
7338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7339 or for lca or if tempreg is PIC_CALL_REG
7340 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7341 For a local symbol, we want
7342 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7344 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7346 If we have a small constant, and this is a reference to
7347 an external symbol, we want
7348 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7350 addiu $tempreg,$tempreg,<constant>
7351 For a local symbol, we want the same instruction
7352 sequence, but we output a BFD_RELOC_LO16 reloc on the
7355 If we have a large constant, and this is a reference to
7356 an external symbol, we want
7357 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7358 lui $at,<hiconstant>
7359 addiu $at,$at,<loconstant>
7360 addu $tempreg,$tempreg,$at
7361 For a local symbol, we want the same instruction
7362 sequence, but we output a BFD_RELOC_LO16 reloc on the
7366 if (offset_expr.X_add_number == 0)
7368 if (mips_pic == SVR4_PIC
7370 && (call || tempreg == PIC_CALL_REG))
7371 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7373 relax_start (offset_expr.X_add_symbol);
7374 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7375 lw_reloc_type, mips_gp_register);
7378 /* We're going to put in an addu instruction using
7379 tempreg, so we may as well insert the nop right
7384 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7385 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7387 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7388 tempreg, tempreg, BFD_RELOC_LO16);
7390 /* FIXME: If breg == 0, and the next instruction uses
7391 $tempreg, then if this variant case is used an extra
7392 nop will be generated. */
7394 else if (offset_expr.X_add_number >= -0x8000
7395 && offset_expr.X_add_number < 0x8000)
7397 load_got_offset (tempreg, &offset_expr);
7399 add_got_offset (tempreg, &offset_expr);
7403 expr1.X_add_number = offset_expr.X_add_number;
7404 offset_expr.X_add_number =
7405 SEXT_16BIT (offset_expr.X_add_number);
7406 load_got_offset (tempreg, &offset_expr);
7407 offset_expr.X_add_number = expr1.X_add_number;
7408 /* If we are going to add in a base register, and the
7409 target register and the base register are the same,
7410 then we are using AT as a temporary register. Since
7411 we want to load the constant into AT, we add our
7412 current AT (from the global offset table) and the
7413 register into the register now, and pretend we were
7414 not using a base register. */
7418 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7423 add_got_offset_hilo (tempreg, &offset_expr, AT);
7427 else if (!mips_big_got && HAVE_NEWABI)
7429 int add_breg_early = 0;
7431 /* If this is a reference to an external, and there is no
7432 constant, or local symbol (*), with or without a
7434 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7435 or for lca or if tempreg is PIC_CALL_REG
7436 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7438 If we have a small constant, and this is a reference to
7439 an external symbol, we want
7440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7441 addiu $tempreg,$tempreg,<constant>
7443 If we have a large constant, and this is a reference to
7444 an external symbol, we want
7445 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7446 lui $at,<hiconstant>
7447 addiu $at,$at,<loconstant>
7448 addu $tempreg,$tempreg,$at
7450 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7451 local symbols, even though it introduces an additional
7454 if (offset_expr.X_add_number)
7456 expr1.X_add_number = offset_expr.X_add_number;
7457 offset_expr.X_add_number = 0;
7459 relax_start (offset_expr.X_add_symbol);
7460 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7461 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7463 if (expr1.X_add_number >= -0x8000
7464 && expr1.X_add_number < 0x8000)
7466 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7467 tempreg, tempreg, BFD_RELOC_LO16);
7469 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7471 /* If we are going to add in a base register, and the
7472 target register and the base register are the same,
7473 then we are using AT as a temporary register. Since
7474 we want to load the constant into AT, we add our
7475 current AT (from the global offset table) and the
7476 register into the register now, and pretend we were
7477 not using a base register. */
7482 gas_assert (tempreg == AT);
7483 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7489 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7490 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7496 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7499 offset_expr.X_add_number = expr1.X_add_number;
7501 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7502 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7505 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7506 treg, tempreg, breg);
7512 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7514 relax_start (offset_expr.X_add_symbol);
7515 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7516 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7518 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7519 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7524 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7525 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7528 else if (mips_big_got && !HAVE_NEWABI)
7531 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7532 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7533 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7535 /* This is the large GOT case. If this is a reference to an
7536 external symbol, and there is no constant, we want
7537 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7538 addu $tempreg,$tempreg,$gp
7539 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7540 or for lca or if tempreg is PIC_CALL_REG
7541 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7542 addu $tempreg,$tempreg,$gp
7543 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7544 For a local symbol, we want
7545 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7547 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7549 If we have a small constant, and this is a reference to
7550 an external symbol, we want
7551 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7552 addu $tempreg,$tempreg,$gp
7553 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7555 addiu $tempreg,$tempreg,<constant>
7556 For a local symbol, we want
7557 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7559 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7561 If we have a large constant, and this is a reference to
7562 an external symbol, we want
7563 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7564 addu $tempreg,$tempreg,$gp
7565 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7566 lui $at,<hiconstant>
7567 addiu $at,$at,<loconstant>
7568 addu $tempreg,$tempreg,$at
7569 For a local symbol, we want
7570 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7571 lui $at,<hiconstant>
7572 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7573 addu $tempreg,$tempreg,$at
7576 expr1.X_add_number = offset_expr.X_add_number;
7577 offset_expr.X_add_number = 0;
7578 relax_start (offset_expr.X_add_symbol);
7579 gpdelay = reg_needs_delay (mips_gp_register);
7580 if (expr1.X_add_number == 0 && breg == 0
7581 && (call || tempreg == PIC_CALL_REG))
7583 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7584 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7586 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7587 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7588 tempreg, tempreg, mips_gp_register);
7589 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7590 tempreg, lw_reloc_type, tempreg);
7591 if (expr1.X_add_number == 0)
7595 /* We're going to put in an addu instruction using
7596 tempreg, so we may as well insert the nop right
7601 else if (expr1.X_add_number >= -0x8000
7602 && expr1.X_add_number < 0x8000)
7605 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7606 tempreg, tempreg, BFD_RELOC_LO16);
7610 /* If we are going to add in a base register, and the
7611 target register and the base register are the same,
7612 then we are using AT as a temporary register. Since
7613 we want to load the constant into AT, we add our
7614 current AT (from the global offset table) and the
7615 register into the register now, and pretend we were
7616 not using a base register. */
7621 gas_assert (tempreg == AT);
7623 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7628 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7629 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7633 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7638 /* This is needed because this instruction uses $gp, but
7639 the first instruction on the main stream does not. */
7640 macro_build (NULL, "nop", "");
7643 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7644 local_reloc_type, mips_gp_register);
7645 if (expr1.X_add_number >= -0x8000
7646 && expr1.X_add_number < 0x8000)
7649 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7650 tempreg, tempreg, BFD_RELOC_LO16);
7651 /* FIXME: If add_number is 0, and there was no base
7652 register, the external symbol case ended with a load,
7653 so if the symbol turns out to not be external, and
7654 the next instruction uses tempreg, an unnecessary nop
7655 will be inserted. */
7661 /* We must add in the base register now, as in the
7662 external symbol case. */
7663 gas_assert (tempreg == AT);
7665 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7668 /* We set breg to 0 because we have arranged to add
7669 it in in both cases. */
7673 macro_build_lui (&expr1, AT);
7674 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7675 AT, AT, BFD_RELOC_LO16);
7676 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7677 tempreg, tempreg, AT);
7682 else if (mips_big_got && HAVE_NEWABI)
7684 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7685 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7686 int add_breg_early = 0;
7688 /* This is the large GOT case. If this is a reference to an
7689 external symbol, and there is no constant, we want
7690 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7691 add $tempreg,$tempreg,$gp
7692 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7693 or for lca or if tempreg is PIC_CALL_REG
7694 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7695 add $tempreg,$tempreg,$gp
7696 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7698 If we have a small constant, and this is a reference to
7699 an external symbol, we want
7700 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7701 add $tempreg,$tempreg,$gp
7702 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7703 addi $tempreg,$tempreg,<constant>
7705 If we have a large constant, and this is a reference to
7706 an external symbol, we want
7707 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7708 addu $tempreg,$tempreg,$gp
7709 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7710 lui $at,<hiconstant>
7711 addi $at,$at,<loconstant>
7712 add $tempreg,$tempreg,$at
7714 If we have NewABI, and we know it's a local symbol, we want
7715 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7716 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7717 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7719 relax_start (offset_expr.X_add_symbol);
7721 expr1.X_add_number = offset_expr.X_add_number;
7722 offset_expr.X_add_number = 0;
7724 if (expr1.X_add_number == 0 && breg == 0
7725 && (call || tempreg == PIC_CALL_REG))
7727 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7728 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7730 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7731 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7732 tempreg, tempreg, mips_gp_register);
7733 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7734 tempreg, lw_reloc_type, tempreg);
7736 if (expr1.X_add_number == 0)
7738 else if (expr1.X_add_number >= -0x8000
7739 && expr1.X_add_number < 0x8000)
7741 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7742 tempreg, tempreg, BFD_RELOC_LO16);
7744 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7746 /* If we are going to add in a base register, and the
7747 target register and the base register are the same,
7748 then we are using AT as a temporary register. Since
7749 we want to load the constant into AT, we add our
7750 current AT (from the global offset table) and the
7751 register into the register now, and pretend we were
7752 not using a base register. */
7757 gas_assert (tempreg == AT);
7758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7764 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7765 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7770 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7773 offset_expr.X_add_number = expr1.X_add_number;
7774 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7775 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7776 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7777 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7780 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7781 treg, tempreg, breg);
7791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7795 gas_assert (!mips_opts.micromips);
7797 unsigned long temp = (treg << 16) | (0x01);
7798 macro_build (NULL, "c2", "C", temp);
7803 gas_assert (!mips_opts.micromips);
7805 unsigned long temp = (0x02);
7806 macro_build (NULL, "c2", "C", temp);
7811 gas_assert (!mips_opts.micromips);
7813 unsigned long temp = (treg << 16) | (0x02);
7814 macro_build (NULL, "c2", "C", temp);
7819 gas_assert (!mips_opts.micromips);
7820 macro_build (NULL, "c2", "C", 3);
7824 gas_assert (!mips_opts.micromips);
7826 unsigned long temp = (treg << 16) | 0x03;
7827 macro_build (NULL, "c2", "C", temp);
7832 /* The j instruction may not be used in PIC code, since it
7833 requires an absolute address. We convert it to a b
7835 if (mips_pic == NO_PIC)
7836 macro_build (&offset_expr, "j", "a");
7838 macro_build (&offset_expr, "b", "p");
7841 /* The jal instructions must be handled as macros because when
7842 generating PIC code they expand to multi-instruction
7843 sequences. Normally they are simple instructions. */
7848 gas_assert (mips_opts.micromips);
7856 if (mips_pic == NO_PIC)
7858 s = jals ? "jalrs" : "jalr";
7859 if (mips_opts.micromips
7861 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7862 macro_build (NULL, s, "mj", sreg);
7864 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7868 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7869 && mips_cprestore_offset >= 0);
7871 if (sreg != PIC_CALL_REG)
7872 as_warn (_("MIPS PIC call to register other than $25"));
7874 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7875 ? "jalrs" : "jalr");
7876 if (mips_opts.micromips
7878 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7879 macro_build (NULL, s, "mj", sreg);
7881 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7882 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7884 if (mips_cprestore_offset < 0)
7885 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7888 if (!mips_frame_reg_valid)
7890 as_warn (_("No .frame pseudo-op used in PIC code"));
7891 /* Quiet this warning. */
7892 mips_frame_reg_valid = 1;
7894 if (!mips_cprestore_valid)
7896 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7897 /* Quiet this warning. */
7898 mips_cprestore_valid = 1;
7900 if (mips_opts.noreorder)
7901 macro_build (NULL, "nop", "");
7902 expr1.X_add_number = mips_cprestore_offset;
7903 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7906 HAVE_64BIT_ADDRESSES);
7914 gas_assert (mips_opts.micromips);
7918 if (mips_pic == NO_PIC)
7919 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7920 else if (mips_pic == SVR4_PIC)
7922 /* If this is a reference to an external symbol, and we are
7923 using a small GOT, we want
7924 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7928 lw $gp,cprestore($sp)
7929 The cprestore value is set using the .cprestore
7930 pseudo-op. If we are using a big GOT, we want
7931 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7933 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7937 lw $gp,cprestore($sp)
7938 If the symbol is not external, we want
7939 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7941 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7944 lw $gp,cprestore($sp)
7946 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7947 sequences above, minus nops, unless the symbol is local,
7948 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7954 relax_start (offset_expr.X_add_symbol);
7955 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7956 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7959 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7960 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7966 relax_start (offset_expr.X_add_symbol);
7967 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7968 BFD_RELOC_MIPS_CALL_HI16);
7969 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7970 PIC_CALL_REG, mips_gp_register);
7971 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7972 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7975 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7976 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7978 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7979 PIC_CALL_REG, PIC_CALL_REG,
7980 BFD_RELOC_MIPS_GOT_OFST);
7984 macro_build_jalr (&offset_expr, 0);
7988 relax_start (offset_expr.X_add_symbol);
7991 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7992 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8001 gpdelay = reg_needs_delay (mips_gp_register);
8002 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8003 BFD_RELOC_MIPS_CALL_HI16);
8004 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8005 PIC_CALL_REG, mips_gp_register);
8006 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8007 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8012 macro_build (NULL, "nop", "");
8014 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8015 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8018 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8019 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8021 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8023 if (mips_cprestore_offset < 0)
8024 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8027 if (!mips_frame_reg_valid)
8029 as_warn (_("No .frame pseudo-op used in PIC code"));
8030 /* Quiet this warning. */
8031 mips_frame_reg_valid = 1;
8033 if (!mips_cprestore_valid)
8035 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8036 /* Quiet this warning. */
8037 mips_cprestore_valid = 1;
8039 if (mips_opts.noreorder)
8040 macro_build (NULL, "nop", "");
8041 expr1.X_add_number = mips_cprestore_offset;
8042 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8045 HAVE_64BIT_ADDRESSES);
8049 else if (mips_pic == VXWORKS_PIC)
8050 as_bad (_("Non-PIC jump used in PIC library"));
8060 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8068 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8099 gas_assert (!mips_opts.micromips);
8102 /* Itbl support may require additional care here. */
8109 /* Itbl support may require additional care here. */
8117 off12 = mips_opts.micromips;
8118 /* Itbl support may require additional care here. */
8123 gas_assert (!mips_opts.micromips);
8126 /* Itbl support may require additional care here. */
8134 off12 = mips_opts.micromips;
8141 off12 = mips_opts.micromips;
8147 /* Itbl support may require additional care here. */
8155 off12 = mips_opts.micromips;
8156 /* Itbl support may require additional care here. */
8163 /* Itbl support may require additional care here. */
8171 off12 = mips_opts.micromips;
8178 off12 = mips_opts.micromips;
8185 off12 = mips_opts.micromips;
8192 off12 = mips_opts.micromips;
8199 off12 = mips_opts.micromips;
8204 gas_assert (mips_opts.micromips);
8213 gas_assert (mips_opts.micromips);
8222 gas_assert (mips_opts.micromips);
8230 gas_assert (mips_opts.micromips);
8237 if (breg == treg + lp)
8240 tempreg = treg + lp;
8260 gas_assert (!mips_opts.micromips);
8263 /* Itbl support may require additional care here. */
8270 /* Itbl support may require additional care here. */
8278 off12 = mips_opts.micromips;
8279 /* Itbl support may require additional care here. */
8284 gas_assert (!mips_opts.micromips);
8287 /* Itbl support may require additional care here. */
8295 off12 = mips_opts.micromips;
8302 off12 = mips_opts.micromips;
8309 off12 = mips_opts.micromips;
8316 off12 = mips_opts.micromips;
8322 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8323 off12 = mips_opts.micromips;
8329 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8330 off12 = mips_opts.micromips;
8337 /* Itbl support may require additional care here. */
8344 off12 = mips_opts.micromips;
8345 /* Itbl support may require additional care here. */
8350 gas_assert (!mips_opts.micromips);
8353 /* Itbl support may require additional care here. */
8361 off12 = mips_opts.micromips;
8368 off12 = mips_opts.micromips;
8373 gas_assert (mips_opts.micromips);
8381 gas_assert (mips_opts.micromips);
8389 gas_assert (mips_opts.micromips);
8397 gas_assert (mips_opts.micromips);
8406 if (offset_expr.X_op != O_constant
8407 && offset_expr.X_op != O_symbol)
8409 as_bad (_("Expression too complex"));
8410 offset_expr.X_op = O_constant;
8413 if (HAVE_32BIT_ADDRESSES
8414 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8418 sprintf_vma (value, offset_expr.X_add_number);
8419 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8422 /* A constant expression in PIC code can be handled just as it
8423 is in non PIC code. */
8424 if (offset_expr.X_op == O_constant)
8428 expr1.X_add_number = offset_expr.X_add_number;
8429 normalize_address_expr (&expr1);
8430 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8432 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8433 & ~(bfd_vma) 0xffff);
8436 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8438 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8439 & ~(bfd_vma) 0xfff);
8444 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8446 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8447 tempreg, tempreg, breg);
8452 if (offset_expr.X_add_number == 0)
8455 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8456 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8457 macro_build (NULL, s, fmt, treg, tempreg);
8460 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8462 macro_build (NULL, s, fmt,
8463 treg, (unsigned long) offset_expr.X_add_number, breg);
8465 else if (off12 || off0)
8467 /* A 12-bit or 0-bit offset field is too narrow to be used
8468 for a low-part relocation, so load the whole address into
8469 the auxillary register. In the case of "A(b)" addresses,
8470 we first load absolute address "A" into the register and
8471 then add base register "b". In the case of "o(b)" addresses,
8472 we simply need to add 16-bit offset "o" to base register "b", and
8473 offset_reloc already contains the relocations associated
8477 load_address (tempreg, &offset_expr, &used_at);
8479 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8480 tempreg, tempreg, breg);
8483 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8485 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8486 expr1.X_add_number = 0;
8488 macro_build (NULL, s, fmt, treg, tempreg);
8490 macro_build (NULL, s, fmt,
8491 treg, (unsigned long) expr1.X_add_number, tempreg);
8493 else if (mips_pic == NO_PIC)
8495 /* If this is a reference to a GP relative symbol, and there
8496 is no base register, we want
8497 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8498 Otherwise, if there is no base register, we want
8499 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8500 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8501 If we have a constant, we need two instructions anyhow,
8502 so we always use the latter form.
8504 If we have a base register, and this is a reference to a
8505 GP relative symbol, we want
8506 addu $tempreg,$breg,$gp
8507 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8509 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8510 addu $tempreg,$tempreg,$breg
8511 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8512 With a constant we always use the latter case.
8514 With 64bit address space and no base register and $at usable,
8516 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8517 lui $at,<sym> (BFD_RELOC_HI16_S)
8518 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8521 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8522 If we have a base register, we want
8523 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8524 lui $at,<sym> (BFD_RELOC_HI16_S)
8525 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8529 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8531 Without $at we can't generate the optimal path for superscalar
8532 processors here since this would require two temporary registers.
8533 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8534 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8536 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8538 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8539 If we have a base register, we want
8540 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8541 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8543 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8545 daddu $tempreg,$tempreg,$breg
8546 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8548 For GP relative symbols in 64bit address space we can use
8549 the same sequence as in 32bit address space. */
8550 if (HAVE_64BIT_SYMBOLS)
8552 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8553 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8555 relax_start (offset_expr.X_add_symbol);
8558 macro_build (&offset_expr, s, fmt, treg,
8559 BFD_RELOC_GPREL16, mips_gp_register);
8563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8564 tempreg, breg, mips_gp_register);
8565 macro_build (&offset_expr, s, fmt, treg,
8566 BFD_RELOC_GPREL16, tempreg);
8571 if (used_at == 0 && mips_opts.at)
8573 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8574 BFD_RELOC_MIPS_HIGHEST);
8575 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8577 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8578 tempreg, BFD_RELOC_MIPS_HIGHER);
8580 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8581 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8582 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8583 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8589 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8590 BFD_RELOC_MIPS_HIGHEST);
8591 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8592 tempreg, BFD_RELOC_MIPS_HIGHER);
8593 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8594 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8595 tempreg, BFD_RELOC_HI16_S);
8596 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8598 macro_build (NULL, "daddu", "d,v,t",
8599 tempreg, tempreg, breg);
8600 macro_build (&offset_expr, s, fmt, treg,
8601 BFD_RELOC_LO16, tempreg);
8604 if (mips_relax.sequence)
8611 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8612 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8614 relax_start (offset_expr.X_add_symbol);
8615 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8619 macro_build_lui (&offset_expr, tempreg);
8620 macro_build (&offset_expr, s, fmt, treg,
8621 BFD_RELOC_LO16, tempreg);
8622 if (mips_relax.sequence)
8627 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8628 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8630 relax_start (offset_expr.X_add_symbol);
8631 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8632 tempreg, breg, mips_gp_register);
8633 macro_build (&offset_expr, s, fmt, treg,
8634 BFD_RELOC_GPREL16, tempreg);
8637 macro_build_lui (&offset_expr, tempreg);
8638 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8639 tempreg, tempreg, breg);
8640 macro_build (&offset_expr, s, fmt, treg,
8641 BFD_RELOC_LO16, tempreg);
8642 if (mips_relax.sequence)
8646 else if (!mips_big_got)
8648 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8650 /* If this is a reference to an external symbol, we want
8651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8653 <op> $treg,0($tempreg)
8655 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8657 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8658 <op> $treg,0($tempreg)
8661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8662 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8664 If there is a base register, we add it to $tempreg before
8665 the <op>. If there is a constant, we stick it in the
8666 <op> instruction. We don't handle constants larger than
8667 16 bits, because we have no way to load the upper 16 bits
8668 (actually, we could handle them for the subset of cases
8669 in which we are not using $at). */
8670 gas_assert (offset_expr.X_op == O_symbol);
8673 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8674 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8676 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8677 tempreg, tempreg, breg);
8678 macro_build (&offset_expr, s, fmt, treg,
8679 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8682 expr1.X_add_number = offset_expr.X_add_number;
8683 offset_expr.X_add_number = 0;
8684 if (expr1.X_add_number < -0x8000
8685 || expr1.X_add_number >= 0x8000)
8686 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8687 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8688 lw_reloc_type, mips_gp_register);
8690 relax_start (offset_expr.X_add_symbol);
8692 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8693 tempreg, BFD_RELOC_LO16);
8696 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8697 tempreg, tempreg, breg);
8698 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8700 else if (mips_big_got && !HAVE_NEWABI)
8704 /* If this is a reference to an external symbol, we want
8705 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8706 addu $tempreg,$tempreg,$gp
8707 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8708 <op> $treg,0($tempreg)
8710 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8712 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8713 <op> $treg,0($tempreg)
8714 If there is a base register, we add it to $tempreg before
8715 the <op>. If there is a constant, we stick it in the
8716 <op> instruction. We don't handle constants larger than
8717 16 bits, because we have no way to load the upper 16 bits
8718 (actually, we could handle them for the subset of cases
8719 in which we are not using $at). */
8720 gas_assert (offset_expr.X_op == O_symbol);
8721 expr1.X_add_number = offset_expr.X_add_number;
8722 offset_expr.X_add_number = 0;
8723 if (expr1.X_add_number < -0x8000
8724 || expr1.X_add_number >= 0x8000)
8725 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8726 gpdelay = reg_needs_delay (mips_gp_register);
8727 relax_start (offset_expr.X_add_symbol);
8728 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8729 BFD_RELOC_MIPS_GOT_HI16);
8730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8732 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8733 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8736 macro_build (NULL, "nop", "");
8737 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8738 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8740 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8741 tempreg, BFD_RELOC_LO16);
8745 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8746 tempreg, tempreg, breg);
8747 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8749 else if (mips_big_got && HAVE_NEWABI)
8751 /* If this is a reference to an external symbol, we want
8752 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8753 add $tempreg,$tempreg,$gp
8754 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8755 <op> $treg,<ofst>($tempreg)
8756 Otherwise, for local symbols, we want:
8757 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8758 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8759 gas_assert (offset_expr.X_op == O_symbol);
8760 expr1.X_add_number = offset_expr.X_add_number;
8761 offset_expr.X_add_number = 0;
8762 if (expr1.X_add_number < -0x8000
8763 || expr1.X_add_number >= 0x8000)
8764 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8765 relax_start (offset_expr.X_add_symbol);
8766 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8767 BFD_RELOC_MIPS_GOT_HI16);
8768 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8770 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8771 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8774 tempreg, tempreg, breg);
8775 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8778 offset_expr.X_add_number = expr1.X_add_number;
8779 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8780 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8783 tempreg, tempreg, breg);
8784 macro_build (&offset_expr, s, fmt, treg,
8785 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8795 load_register (treg, &imm_expr, 0);
8799 load_register (treg, &imm_expr, 1);
8803 if (imm_expr.X_op == O_constant)
8806 load_register (AT, &imm_expr, 0);
8807 macro_build (NULL, "mtc1", "t,G", AT, treg);
8812 gas_assert (offset_expr.X_op == O_symbol
8813 && strcmp (segment_name (S_GET_SEGMENT
8814 (offset_expr.X_add_symbol)),
8816 && offset_expr.X_add_number == 0);
8817 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8818 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8823 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8824 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8825 order 32 bits of the value and the low order 32 bits are either
8826 zero or in OFFSET_EXPR. */
8827 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8829 if (HAVE_64BIT_GPRS)
8830 load_register (treg, &imm_expr, 1);
8835 if (target_big_endian)
8847 load_register (hreg, &imm_expr, 0);
8850 if (offset_expr.X_op == O_absent)
8851 move_register (lreg, 0);
8854 gas_assert (offset_expr.X_op == O_constant);
8855 load_register (lreg, &offset_expr, 0);
8862 /* We know that sym is in the .rdata section. First we get the
8863 upper 16 bits of the address. */
8864 if (mips_pic == NO_PIC)
8866 macro_build_lui (&offset_expr, AT);
8871 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8872 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8876 /* Now we load the register(s). */
8877 if (HAVE_64BIT_GPRS)
8880 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8885 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8888 /* FIXME: How in the world do we deal with the possible
8890 offset_expr.X_add_number += 4;
8891 macro_build (&offset_expr, "lw", "t,o(b)",
8892 treg + 1, BFD_RELOC_LO16, AT);
8898 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8899 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8900 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8901 the value and the low order 32 bits are either zero or in
8903 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8906 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8907 if (HAVE_64BIT_FPRS)
8909 gas_assert (HAVE_64BIT_GPRS);
8910 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8914 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8915 if (offset_expr.X_op == O_absent)
8916 macro_build (NULL, "mtc1", "t,G", 0, treg);
8919 gas_assert (offset_expr.X_op == O_constant);
8920 load_register (AT, &offset_expr, 0);
8921 macro_build (NULL, "mtc1", "t,G", AT, treg);
8927 gas_assert (offset_expr.X_op == O_symbol
8928 && offset_expr.X_add_number == 0);
8929 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8930 if (strcmp (s, ".lit8") == 0)
8932 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
8934 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8935 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8938 breg = mips_gp_register;
8939 r = BFD_RELOC_MIPS_LITERAL;
8944 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8946 if (mips_pic != NO_PIC)
8947 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8948 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8951 /* FIXME: This won't work for a 64 bit address. */
8952 macro_build_lui (&offset_expr, AT);
8955 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
8957 macro_build (&offset_expr, "ldc1", "T,o(b)",
8958 treg, BFD_RELOC_LO16, AT);
8967 /* Even on a big endian machine $fn comes before $fn+1. We have
8968 to adjust when loading from memory. */
8971 gas_assert (!mips_opts.micromips);
8972 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
8973 macro_build (&offset_expr, "lwc1", "T,o(b)",
8974 target_big_endian ? treg + 1 : treg, r, breg);
8975 /* FIXME: A possible overflow which I don't know how to deal
8977 offset_expr.X_add_number += 4;
8978 macro_build (&offset_expr, "lwc1", "T,o(b)",
8979 target_big_endian ? treg : treg + 1, r, breg);
8983 gas_assert (!mips_opts.micromips);
8984 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
8985 /* Even on a big endian machine $fn comes before $fn+1. We have
8986 to adjust when storing to memory. */
8987 macro_build (&offset_expr, "swc1", "T,o(b)",
8988 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8989 offset_expr.X_add_number += 4;
8990 macro_build (&offset_expr, "swc1", "T,o(b)",
8991 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8995 gas_assert (!mips_opts.micromips);
8997 * The MIPS assembler seems to check for X_add_number not
8998 * being double aligned and generating:
9001 * addiu at,at,%lo(foo+1)
9004 * But, the resulting address is the same after relocation so why
9005 * generate the extra instruction?
9007 /* Itbl support may require additional care here. */
9010 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9019 gas_assert (!mips_opts.micromips);
9020 /* Itbl support may require additional care here. */
9023 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9043 if (HAVE_64BIT_GPRS)
9053 if (HAVE_64BIT_GPRS)
9061 if (offset_expr.X_op != O_symbol
9062 && offset_expr.X_op != O_constant)
9064 as_bad (_("Expression too complex"));
9065 offset_expr.X_op = O_constant;
9068 if (HAVE_32BIT_ADDRESSES
9069 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9073 sprintf_vma (value, offset_expr.X_add_number);
9074 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9077 /* Even on a big endian machine $fn comes before $fn+1. We have
9078 to adjust when loading from memory. We set coproc if we must
9079 load $fn+1 first. */
9080 /* Itbl support may require additional care here. */
9081 if (!target_big_endian)
9084 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9086 /* If this is a reference to a GP relative symbol, we want
9087 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9088 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9089 If we have a base register, we use this
9091 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9092 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9093 If this is not a GP relative symbol, we want
9094 lui $at,<sym> (BFD_RELOC_HI16_S)
9095 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9096 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9097 If there is a base register, we add it to $at after the
9098 lui instruction. If there is a constant, we always use
9100 if (offset_expr.X_op == O_symbol
9101 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9102 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9104 relax_start (offset_expr.X_add_symbol);
9107 tempreg = mips_gp_register;
9111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9112 AT, breg, mips_gp_register);
9117 /* Itbl support may require additional care here. */
9118 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9119 BFD_RELOC_GPREL16, tempreg);
9120 offset_expr.X_add_number += 4;
9122 /* Set mips_optimize to 2 to avoid inserting an
9124 hold_mips_optimize = mips_optimize;
9126 /* Itbl support may require additional care here. */
9127 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9128 BFD_RELOC_GPREL16, tempreg);
9129 mips_optimize = hold_mips_optimize;
9133 offset_expr.X_add_number -= 4;
9136 macro_build_lui (&offset_expr, AT);
9138 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9139 /* Itbl support may require additional care here. */
9140 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9141 BFD_RELOC_LO16, AT);
9142 /* FIXME: How do we handle overflow here? */
9143 offset_expr.X_add_number += 4;
9144 /* Itbl support may require additional care here. */
9145 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9146 BFD_RELOC_LO16, AT);
9147 if (mips_relax.sequence)
9150 else if (!mips_big_got)
9152 /* If this is a reference to an external symbol, we want
9153 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9158 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9160 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9161 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9162 If there is a base register we add it to $at before the
9163 lwc1 instructions. If there is a constant we include it
9164 in the lwc1 instructions. */
9166 expr1.X_add_number = offset_expr.X_add_number;
9167 if (expr1.X_add_number < -0x8000
9168 || expr1.X_add_number >= 0x8000 - 4)
9169 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9170 load_got_offset (AT, &offset_expr);
9173 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9175 /* Set mips_optimize to 2 to avoid inserting an undesired
9177 hold_mips_optimize = mips_optimize;
9180 /* Itbl support may require additional care here. */
9181 relax_start (offset_expr.X_add_symbol);
9182 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9183 BFD_RELOC_LO16, AT);
9184 expr1.X_add_number += 4;
9185 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9186 BFD_RELOC_LO16, AT);
9188 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9189 BFD_RELOC_LO16, AT);
9190 offset_expr.X_add_number += 4;
9191 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9192 BFD_RELOC_LO16, AT);
9195 mips_optimize = hold_mips_optimize;
9197 else if (mips_big_got)
9201 /* If this is a reference to an external symbol, we want
9202 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9204 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9209 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9211 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9212 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9213 If there is a base register we add it to $at before the
9214 lwc1 instructions. If there is a constant we include it
9215 in the lwc1 instructions. */
9217 expr1.X_add_number = offset_expr.X_add_number;
9218 offset_expr.X_add_number = 0;
9219 if (expr1.X_add_number < -0x8000
9220 || expr1.X_add_number >= 0x8000 - 4)
9221 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9222 gpdelay = reg_needs_delay (mips_gp_register);
9223 relax_start (offset_expr.X_add_symbol);
9224 macro_build (&offset_expr, "lui", LUI_FMT,
9225 AT, BFD_RELOC_MIPS_GOT_HI16);
9226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9227 AT, AT, mips_gp_register);
9228 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9229 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9233 /* Itbl support may require additional care here. */
9234 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9235 BFD_RELOC_LO16, AT);
9236 expr1.X_add_number += 4;
9238 /* Set mips_optimize to 2 to avoid inserting an undesired
9240 hold_mips_optimize = mips_optimize;
9242 /* Itbl support may require additional care here. */
9243 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9244 BFD_RELOC_LO16, AT);
9245 mips_optimize = hold_mips_optimize;
9246 expr1.X_add_number -= 4;
9249 offset_expr.X_add_number = expr1.X_add_number;
9251 macro_build (NULL, "nop", "");
9252 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9253 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9257 /* Itbl support may require additional care here. */
9258 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9259 BFD_RELOC_LO16, AT);
9260 offset_expr.X_add_number += 4;
9262 /* Set mips_optimize to 2 to avoid inserting an undesired
9264 hold_mips_optimize = mips_optimize;
9266 /* Itbl support may require additional care here. */
9267 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9268 BFD_RELOC_LO16, AT);
9269 mips_optimize = hold_mips_optimize;
9278 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9281 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9283 macro_build (&offset_expr, s, "t,o(b)", treg,
9284 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9286 if (!HAVE_64BIT_GPRS)
9288 offset_expr.X_add_number += 4;
9289 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9290 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9311 /* New code added to support COPZ instructions.
9312 This code builds table entries out of the macros in mip_opcodes.
9313 R4000 uses interlocks to handle coproc delays.
9314 Other chips (like the R3000) require nops to be inserted for delays.
9316 FIXME: Currently, we require that the user handle delays.
9317 In order to fill delay slots for non-interlocked chips,
9318 we must have a way to specify delays based on the coprocessor.
9319 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9320 What are the side-effects of the cop instruction?
9321 What cache support might we have and what are its effects?
9322 Both coprocessor & memory require delays. how long???
9323 What registers are read/set/modified?
9325 If an itbl is provided to interpret cop instructions,
9326 this knowledge can be encoded in the itbl spec. */
9340 gas_assert (!mips_opts.micromips);
9341 /* For now we just do C (same as Cz). The parameter will be
9342 stored in insn_opcode by mips_ip. */
9343 macro_build (NULL, s, "C", ip->insn_opcode);
9347 move_register (dreg, sreg);
9353 if (mips_opts.arch == CPU_R5900)
9355 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9359 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9360 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9367 /* The MIPS assembler some times generates shifts and adds. I'm
9368 not trying to be that fancy. GCC should do this for us
9371 load_register (AT, &imm_expr, dbl);
9372 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9373 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9389 load_register (AT, &imm_expr, dbl);
9390 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9391 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9392 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9393 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9395 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9398 if (mips_opts.micromips)
9399 micromips_label_expr (&label_expr);
9401 label_expr.X_add_number = 8;
9402 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9403 macro_build (NULL, "nop", "");
9404 macro_build (NULL, "break", BRK_FMT, 6);
9405 if (mips_opts.micromips)
9406 micromips_add_label ();
9409 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9425 load_register (AT, &imm_expr, dbl);
9426 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9427 sreg, imm ? AT : treg);
9428 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9429 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9431 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9434 if (mips_opts.micromips)
9435 micromips_label_expr (&label_expr);
9437 label_expr.X_add_number = 8;
9438 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9439 macro_build (NULL, "nop", "");
9440 macro_build (NULL, "break", BRK_FMT, 6);
9441 if (mips_opts.micromips)
9442 micromips_add_label ();
9448 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9459 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9460 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9464 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9465 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9466 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9467 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9471 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9482 macro_build (NULL, "negu", "d,w", tempreg, treg);
9483 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9487 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9488 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9489 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9490 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9499 if (imm_expr.X_op != O_constant)
9500 as_bad (_("Improper rotate count"));
9501 rot = imm_expr.X_add_number & 0x3f;
9502 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9504 rot = (64 - rot) & 0x3f;
9506 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9508 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9513 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9516 l = (rot < 0x20) ? "dsll" : "dsll32";
9517 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9520 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9521 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9522 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9530 if (imm_expr.X_op != O_constant)
9531 as_bad (_("Improper rotate count"));
9532 rot = imm_expr.X_add_number & 0x1f;
9533 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9535 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9540 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9544 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9545 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9546 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9551 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9553 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9557 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9558 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9559 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9560 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9564 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9566 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9570 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9571 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9572 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9573 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9582 if (imm_expr.X_op != O_constant)
9583 as_bad (_("Improper rotate count"));
9584 rot = imm_expr.X_add_number & 0x3f;
9585 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9588 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9590 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9595 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9598 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9599 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9602 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9603 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9604 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9612 if (imm_expr.X_op != O_constant)
9613 as_bad (_("Improper rotate count"));
9614 rot = imm_expr.X_add_number & 0x1f;
9615 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9617 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9622 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9626 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9627 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9628 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9634 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9636 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9639 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9640 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9645 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9647 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9652 as_warn (_("Instruction %s: result is always false"),
9654 move_register (dreg, 0);
9657 if (CPU_HAS_SEQ (mips_opts.arch)
9658 && -512 <= imm_expr.X_add_number
9659 && imm_expr.X_add_number < 512)
9661 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9662 (int) imm_expr.X_add_number);
9665 if (imm_expr.X_op == O_constant
9666 && imm_expr.X_add_number >= 0
9667 && imm_expr.X_add_number < 0x10000)
9669 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9671 else if (imm_expr.X_op == O_constant
9672 && imm_expr.X_add_number > -0x8000
9673 && imm_expr.X_add_number < 0)
9675 imm_expr.X_add_number = -imm_expr.X_add_number;
9676 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9677 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9679 else if (CPU_HAS_SEQ (mips_opts.arch))
9682 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9683 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9688 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9689 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9692 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9695 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9701 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9702 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9705 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9707 if (imm_expr.X_op == O_constant
9708 && imm_expr.X_add_number >= -0x8000
9709 && imm_expr.X_add_number < 0x8000)
9711 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9712 dreg, sreg, BFD_RELOC_LO16);
9716 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9717 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9721 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9724 case M_SGT: /* sreg > treg <==> treg < sreg */
9730 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9733 case M_SGT_I: /* sreg > I <==> I < sreg */
9740 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9741 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9744 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9750 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9751 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9754 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9761 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9762 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9763 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9767 if (imm_expr.X_op == O_constant
9768 && imm_expr.X_add_number >= -0x8000
9769 && imm_expr.X_add_number < 0x8000)
9771 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9775 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9776 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9780 if (imm_expr.X_op == O_constant
9781 && imm_expr.X_add_number >= -0x8000
9782 && imm_expr.X_add_number < 0x8000)
9784 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9789 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9790 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9795 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9797 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9800 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9801 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9806 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9808 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9813 as_warn (_("Instruction %s: result is always true"),
9815 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9816 dreg, 0, BFD_RELOC_LO16);
9819 if (CPU_HAS_SEQ (mips_opts.arch)
9820 && -512 <= imm_expr.X_add_number
9821 && imm_expr.X_add_number < 512)
9823 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9824 (int) imm_expr.X_add_number);
9827 if (imm_expr.X_op == O_constant
9828 && imm_expr.X_add_number >= 0
9829 && imm_expr.X_add_number < 0x10000)
9831 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9833 else if (imm_expr.X_op == O_constant
9834 && imm_expr.X_add_number > -0x8000
9835 && imm_expr.X_add_number < 0)
9837 imm_expr.X_add_number = -imm_expr.X_add_number;
9838 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9839 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9841 else if (CPU_HAS_SEQ (mips_opts.arch))
9844 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9845 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9850 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9851 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9854 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9869 if (!mips_opts.micromips)
9871 if (imm_expr.X_op == O_constant
9872 && imm_expr.X_add_number > -0x200
9873 && imm_expr.X_add_number <= 0x200)
9875 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9884 if (imm_expr.X_op == O_constant
9885 && imm_expr.X_add_number > -0x8000
9886 && imm_expr.X_add_number <= 0x8000)
9888 imm_expr.X_add_number = -imm_expr.X_add_number;
9889 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9894 load_register (AT, &imm_expr, dbl);
9895 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9917 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9918 macro_build (NULL, s, "s,t", sreg, AT);
9923 gas_assert (!mips_opts.micromips);
9924 gas_assert (mips_opts.isa == ISA_MIPS1);
9926 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9927 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9930 * Is the double cfc1 instruction a bug in the mips assembler;
9931 * or is there a reason for it?
9934 macro_build (NULL, "cfc1", "t,G", treg, RA);
9935 macro_build (NULL, "cfc1", "t,G", treg, RA);
9936 macro_build (NULL, "nop", "");
9937 expr1.X_add_number = 3;
9938 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9939 expr1.X_add_number = 2;
9940 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9941 macro_build (NULL, "ctc1", "t,G", AT, RA);
9942 macro_build (NULL, "nop", "");
9943 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9945 macro_build (NULL, "ctc1", "t,G", treg, RA);
9946 macro_build (NULL, "nop", "");
9969 off12 = mips_opts.micromips;
9977 off12 = mips_opts.micromips;
9993 off12 = mips_opts.micromips;
10002 off12 = mips_opts.micromips;
10007 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10008 as_bad (_("Operand overflow"));
10011 expr1.X_add_number = 0;
10016 load_address (tempreg, ep, &used_at);
10018 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10019 tempreg, tempreg, breg);
10025 && (offset_expr.X_op != O_constant
10026 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10027 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10031 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10032 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10037 else if (!ust && treg == breg)
10048 if (!target_big_endian)
10049 ep->X_add_number += off;
10051 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10053 macro_build (NULL, s, "t,~(b)",
10054 tempreg, (unsigned long) ep->X_add_number, breg);
10056 if (!target_big_endian)
10057 ep->X_add_number -= off;
10059 ep->X_add_number += off;
10061 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10063 macro_build (NULL, s2, "t,~(b)",
10064 tempreg, (unsigned long) ep->X_add_number, breg);
10066 /* If necessary, move the result in tempreg to the final destination. */
10067 if (!ust && treg != tempreg)
10069 /* Protect second load's delay slot. */
10071 move_register (treg, tempreg);
10077 if (target_big_endian == ust)
10078 ep->X_add_number += off;
10079 tempreg = ust || ab ? treg : AT;
10080 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10082 /* For halfword transfers we need a temporary register to shuffle
10083 bytes. Unfortunately for M_USH_A we have none available before
10084 the next store as AT holds the base address. We deal with this
10085 case by clobbering TREG and then restoring it as with ULH. */
10086 tempreg = ust == ab ? treg : AT;
10088 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10090 if (target_big_endian == ust)
10091 ep->X_add_number -= off;
10093 ep->X_add_number += off;
10094 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10096 /* For M_USH_A re-retrieve the LSB. */
10099 if (target_big_endian)
10100 ep->X_add_number += off;
10102 ep->X_add_number -= off;
10103 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10105 /* For ULH and M_USH_A OR the LSB in. */
10108 tempreg = !ab ? AT : treg;
10109 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10110 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10115 /* FIXME: Check if this is one of the itbl macros, since they
10116 are added dynamically. */
10117 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10120 if (!mips_opts.at && used_at)
10121 as_bad (_("Macro used $at after \".set noat\""));
10124 /* Implement macros in mips16 mode. */
10127 mips16_macro (struct mips_cl_insn *ip)
10130 int xreg, yreg, zreg, tmp;
10133 const char *s, *s2, *s3;
10135 mask = ip->insn_mo->mask;
10137 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10138 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10139 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10141 expr1.X_op = O_constant;
10142 expr1.X_op_symbol = NULL;
10143 expr1.X_add_symbol = NULL;
10144 expr1.X_add_number = 1;
10163 start_noreorder ();
10164 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10165 expr1.X_add_number = 2;
10166 macro_build (&expr1, "bnez", "x,p", yreg);
10167 macro_build (NULL, "break", "6", 7);
10169 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10170 since that causes an overflow. We should do that as well,
10171 but I don't see how to do the comparisons without a temporary
10174 macro_build (NULL, s, "x", zreg);
10193 start_noreorder ();
10194 macro_build (NULL, s, "0,x,y", xreg, yreg);
10195 expr1.X_add_number = 2;
10196 macro_build (&expr1, "bnez", "x,p", yreg);
10197 macro_build (NULL, "break", "6", 7);
10199 macro_build (NULL, s2, "x", zreg);
10205 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10206 macro_build (NULL, "mflo", "x", zreg);
10214 if (imm_expr.X_op != O_constant)
10215 as_bad (_("Unsupported large constant"));
10216 imm_expr.X_add_number = -imm_expr.X_add_number;
10217 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10221 if (imm_expr.X_op != O_constant)
10222 as_bad (_("Unsupported large constant"));
10223 imm_expr.X_add_number = -imm_expr.X_add_number;
10224 macro_build (&imm_expr, "addiu", "x,k", xreg);
10228 if (imm_expr.X_op != O_constant)
10229 as_bad (_("Unsupported large constant"));
10230 imm_expr.X_add_number = -imm_expr.X_add_number;
10231 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10253 goto do_reverse_branch;
10257 goto do_reverse_branch;
10269 goto do_reverse_branch;
10280 macro_build (NULL, s, "x,y", xreg, yreg);
10281 macro_build (&offset_expr, s2, "p");
10308 goto do_addone_branch_i;
10313 goto do_addone_branch_i;
10328 goto do_addone_branch_i;
10334 do_addone_branch_i:
10335 if (imm_expr.X_op != O_constant)
10336 as_bad (_("Unsupported large constant"));
10337 ++imm_expr.X_add_number;
10340 macro_build (&imm_expr, s, s3, xreg);
10341 macro_build (&offset_expr, s2, "p");
10345 expr1.X_add_number = 0;
10346 macro_build (&expr1, "slti", "x,8", yreg);
10348 move_register (xreg, yreg);
10349 expr1.X_add_number = 2;
10350 macro_build (&expr1, "bteqz", "p");
10351 macro_build (NULL, "neg", "x,w", xreg, xreg);
10355 /* For consistency checking, verify that all bits are specified either
10356 by the match/mask part of the instruction definition, or by the
10359 validate_mips_insn (const struct mips_opcode *opc)
10361 const char *p = opc->args;
10363 unsigned long used_bits = opc->mask;
10365 if ((used_bits & opc->match) != opc->match)
10367 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10368 opc->name, opc->args);
10371 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10381 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10382 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10383 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10384 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10385 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10386 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10387 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10388 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10389 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10390 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10391 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10392 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10393 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10395 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10396 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10397 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10398 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10399 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10400 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10401 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10402 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10403 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10404 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10405 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10406 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10407 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10408 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10409 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10412 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10413 c, opc->name, opc->args);
10417 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10418 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10420 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10421 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10422 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10423 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10425 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10426 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10428 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10429 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10431 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10432 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10433 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10434 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10435 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10436 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10437 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10438 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10439 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10440 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10441 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10442 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10443 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10444 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10445 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10446 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10447 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10449 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10450 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10451 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10452 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10454 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10455 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10456 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10457 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10458 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10459 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10460 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10461 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10462 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10465 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10466 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10467 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10468 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10469 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10472 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10473 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10474 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10475 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10476 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10477 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10478 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10479 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10480 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10481 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10482 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10483 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10484 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10485 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10486 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10487 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10488 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10489 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10490 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10491 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10493 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10494 c, opc->name, opc->args);
10498 if (used_bits != 0xffffffff)
10500 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10501 ~used_bits & 0xffffffff, opc->name, opc->args);
10507 /* For consistency checking, verify that the length implied matches the
10508 major opcode and that all bits are specified either by the match/mask
10509 part of the instruction definition, or by the operand list. */
10512 validate_micromips_insn (const struct mips_opcode *opc)
10514 unsigned long match = opc->match;
10515 unsigned long mask = opc->mask;
10516 const char *p = opc->args;
10517 unsigned long insn_bits;
10518 unsigned long used_bits;
10519 unsigned long major;
10520 unsigned int length;
10524 if ((mask & match) != match)
10526 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10527 opc->name, opc->args);
10530 length = micromips_insn_length (opc);
10531 if (length != 2 && length != 4)
10533 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10534 "%s %s"), length, opc->name, opc->args);
10537 major = match >> (10 + 8 * (length - 2));
10538 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10539 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10541 as_bad (_("Internal error: bad microMIPS opcode "
10542 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10546 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10547 insn_bits = 1 << 4 * length;
10548 insn_bits <<= 4 * length;
10551 #define USE_BITS(field) \
10552 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10563 case 'A': USE_BITS (EXTLSB); break;
10564 case 'B': USE_BITS (INSMSB); break;
10565 case 'C': USE_BITS (EXTMSBD); break;
10566 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10567 case 'E': USE_BITS (EXTLSB); break;
10568 case 'F': USE_BITS (INSMSB); break;
10569 case 'G': USE_BITS (EXTMSBD); break;
10570 case 'H': USE_BITS (EXTMSBD); break;
10572 as_bad (_("Internal error: bad mips opcode "
10573 "(unknown extension operand type `%c%c'): %s %s"),
10574 e, c, opc->name, opc->args);
10582 case 'A': USE_BITS (IMMA); break;
10583 case 'B': USE_BITS (IMMB); break;
10584 case 'C': USE_BITS (IMMC); break;
10585 case 'D': USE_BITS (IMMD); break;
10586 case 'E': USE_BITS (IMME); break;
10587 case 'F': USE_BITS (IMMF); break;
10588 case 'G': USE_BITS (IMMG); break;
10589 case 'H': USE_BITS (IMMH); break;
10590 case 'I': USE_BITS (IMMI); break;
10591 case 'J': USE_BITS (IMMJ); break;
10592 case 'L': USE_BITS (IMML); break;
10593 case 'M': USE_BITS (IMMM); break;
10594 case 'N': USE_BITS (IMMN); break;
10595 case 'O': USE_BITS (IMMO); break;
10596 case 'P': USE_BITS (IMMP); break;
10597 case 'Q': USE_BITS (IMMQ); break;
10598 case 'U': USE_BITS (IMMU); break;
10599 case 'W': USE_BITS (IMMW); break;
10600 case 'X': USE_BITS (IMMX); break;
10601 case 'Y': USE_BITS (IMMY); break;
10604 case 'b': USE_BITS (MB); break;
10605 case 'c': USE_BITS (MC); break;
10606 case 'd': USE_BITS (MD); break;
10607 case 'e': USE_BITS (ME); break;
10608 case 'f': USE_BITS (MF); break;
10609 case 'g': USE_BITS (MG); break;
10610 case 'h': USE_BITS (MH); break;
10611 case 'i': USE_BITS (MI); break;
10612 case 'j': USE_BITS (MJ); break;
10613 case 'l': USE_BITS (ML); break;
10614 case 'm': USE_BITS (MM); break;
10615 case 'n': USE_BITS (MN); break;
10616 case 'p': USE_BITS (MP); break;
10617 case 'q': USE_BITS (MQ); break;
10625 as_bad (_("Internal error: bad mips opcode "
10626 "(unknown extension operand type `%c%c'): %s %s"),
10627 e, c, opc->name, opc->args);
10631 case '.': USE_BITS (OFFSET10); break;
10632 case '1': USE_BITS (STYPE); break;
10633 case '2': USE_BITS (BP); break;
10634 case '3': USE_BITS (SA3); break;
10635 case '4': USE_BITS (SA4); break;
10636 case '5': USE_BITS (IMM8); break;
10637 case '6': USE_BITS (RS); break;
10638 case '7': USE_BITS (DSPACC); break;
10639 case '8': USE_BITS (WRDSP); break;
10640 case '0': USE_BITS (DSPSFT); break;
10641 case '<': USE_BITS (SHAMT); break;
10642 case '>': USE_BITS (SHAMT); break;
10643 case '@': USE_BITS (IMM10); break;
10644 case 'B': USE_BITS (CODE10); break;
10645 case 'C': USE_BITS (COPZ); break;
10646 case 'D': USE_BITS (FD); break;
10647 case 'E': USE_BITS (RT); break;
10648 case 'G': USE_BITS (RS); break;
10649 case 'H': USE_BITS (SEL); break;
10650 case 'K': USE_BITS (RS); break;
10651 case 'M': USE_BITS (CCC); break;
10652 case 'N': USE_BITS (BCC); break;
10653 case 'R': USE_BITS (FR); break;
10654 case 'S': USE_BITS (FS); break;
10655 case 'T': USE_BITS (FT); break;
10656 case 'V': USE_BITS (FS); break;
10657 case '\\': USE_BITS (3BITPOS); break;
10658 case '^': USE_BITS (RD); break;
10659 case 'a': USE_BITS (TARGET); break;
10660 case 'b': USE_BITS (RS); break;
10661 case 'c': USE_BITS (CODE); break;
10662 case 'd': USE_BITS (RD); break;
10663 case 'h': USE_BITS (PREFX); break;
10664 case 'i': USE_BITS (IMMEDIATE); break;
10665 case 'j': USE_BITS (DELTA); break;
10666 case 'k': USE_BITS (CACHE); break;
10667 case 'n': USE_BITS (RT); break;
10668 case 'o': USE_BITS (DELTA); break;
10669 case 'p': USE_BITS (DELTA); break;
10670 case 'q': USE_BITS (CODE2); break;
10671 case 'r': USE_BITS (RS); break;
10672 case 's': USE_BITS (RS); break;
10673 case 't': USE_BITS (RT); break;
10674 case 'u': USE_BITS (IMMEDIATE); break;
10675 case 'v': USE_BITS (RS); break;
10676 case 'w': USE_BITS (RT); break;
10677 case 'y': USE_BITS (RS3); break;
10679 case '|': USE_BITS (TRAP); break;
10680 case '~': USE_BITS (OFFSET12); break;
10682 as_bad (_("Internal error: bad microMIPS opcode "
10683 "(unknown operand type `%c'): %s %s"),
10684 c, opc->name, opc->args);
10688 if (used_bits != insn_bits)
10690 if (~used_bits & insn_bits)
10691 as_bad (_("Internal error: bad microMIPS opcode "
10692 "(bits 0x%lx undefined): %s %s"),
10693 ~used_bits & insn_bits, opc->name, opc->args);
10694 if (used_bits & ~insn_bits)
10695 as_bad (_("Internal error: bad microMIPS opcode "
10696 "(bits 0x%lx defined): %s %s"),
10697 used_bits & ~insn_bits, opc->name, opc->args);
10703 /* UDI immediates. */
10704 struct mips_immed {
10706 unsigned int shift;
10707 unsigned long mask;
10711 static const struct mips_immed mips_immed[] = {
10712 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10713 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10714 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10715 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10719 /* Check whether an odd floating-point register is allowed. */
10721 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10723 const char *s = insn->name;
10725 if (insn->pinfo == INSN_MACRO)
10726 /* Let a macro pass, we'll catch it later when it is expanded. */
10729 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10731 /* Allow odd registers for single-precision ops. */
10732 switch (insn->pinfo & (FP_S | FP_D))
10736 return 1; /* both single precision - ok */
10738 return 0; /* both double precision - fail */
10743 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10744 s = strchr (insn->name, '.');
10746 s = s != NULL ? strchr (s + 1, '.') : NULL;
10747 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10750 /* Single-precision coprocessor loads and moves are OK too. */
10751 if ((insn->pinfo & FP_S)
10752 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10753 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10759 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10760 taking bits from BIT up. */
10762 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10764 return (ep->X_op == O_constant
10765 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10766 && ep->X_add_number >= min << bit
10767 && ep->X_add_number < max << bit);
10770 /* This routine assembles an instruction into its binary format. As a
10771 side effect, it sets one of the global variables imm_reloc or
10772 offset_reloc to the type of relocation to do if one of the operands
10773 is an address expression. */
10776 mips_ip (char *str, struct mips_cl_insn *ip)
10778 bfd_boolean wrong_delay_slot_insns = FALSE;
10779 bfd_boolean need_delay_slot_ok = TRUE;
10780 struct mips_opcode *firstinsn = NULL;
10781 const struct mips_opcode *past;
10782 struct hash_control *hash;
10786 struct mips_opcode *insn;
10788 unsigned int regno;
10789 unsigned int lastregno;
10790 unsigned int destregno = 0;
10791 unsigned int lastpos = 0;
10792 unsigned int limlo, limhi;
10794 offsetT min_range, max_range;
10798 unsigned int rtype;
10804 if (mips_opts.micromips)
10806 hash = micromips_op_hash;
10807 past = µmips_opcodes[bfd_micromips_num_opcodes];
10812 past = &mips_opcodes[NUMOPCODES];
10814 forced_insn_length = 0;
10817 /* We first try to match an instruction up to a space or to the end. */
10818 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10821 /* Make a copy of the instruction so that we can fiddle with it. */
10822 name = alloca (end + 1);
10823 memcpy (name, str, end);
10828 insn = (struct mips_opcode *) hash_find (hash, name);
10830 if (insn != NULL || !mips_opts.micromips)
10832 if (forced_insn_length)
10835 /* See if there's an instruction size override suffix,
10836 either `16' or `32', at the end of the mnemonic proper,
10837 that defines the operation, i.e. before the first `.'
10838 character if any. Strip it and retry. */
10839 dot = strchr (name, '.');
10840 opend = dot != NULL ? dot - name : end;
10843 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10844 forced_insn_length = 2;
10845 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10846 forced_insn_length = 4;
10849 memcpy (name + opend - 2, name + opend, end - opend + 1);
10853 insn_error = _("Unrecognized opcode");
10857 /* For microMIPS instructions placed in a fixed-length branch delay slot
10858 we make up to two passes over the relevant fragment of the opcode
10859 table. First we try instructions that meet the delay slot's length
10860 requirement. If none matched, then we retry with the remaining ones
10861 and if one matches, then we use it and then issue an appropriate
10862 warning later on. */
10863 argsStart = s = str + end;
10866 bfd_boolean delay_slot_ok;
10867 bfd_boolean size_ok;
10870 gas_assert (strcmp (insn->name, name) == 0);
10872 ok = is_opcode_valid (insn);
10873 size_ok = is_size_valid (insn);
10874 delay_slot_ok = is_delay_slot_valid (insn);
10875 if (!delay_slot_ok && !wrong_delay_slot_insns)
10878 wrong_delay_slot_insns = TRUE;
10880 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10882 static char buf[256];
10884 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10889 if (wrong_delay_slot_insns && need_delay_slot_ok)
10891 gas_assert (firstinsn);
10892 need_delay_slot_ok = FALSE;
10902 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10903 mips_cpu_info_from_arch (mips_opts.arch)->name,
10904 mips_cpu_info_from_isa (mips_opts.isa)->name);
10906 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10907 8 * forced_insn_length);
10913 create_insn (ip, insn);
10916 lastregno = 0xffffffff;
10917 for (args = insn->args;; ++args)
10921 s += strspn (s, " \t");
10925 case '\0': /* end of args */
10931 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10932 code) or 14 (for microMIPS code). */
10933 my_getExpression (&imm_expr, s);
10934 check_absolute_expr (ip, &imm_expr);
10935 if ((unsigned long) imm_expr.X_add_number != 1
10936 && (unsigned long) imm_expr.X_add_number != 3)
10938 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10939 (unsigned long) imm_expr.X_add_number);
10941 INSERT_OPERAND (mips_opts.micromips,
10942 BP, *ip, imm_expr.X_add_number);
10943 imm_expr.X_op = O_absent;
10948 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10949 code) or 21 (for microMIPS code). */
10951 unsigned long mask = (mips_opts.micromips
10952 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10954 my_getExpression (&imm_expr, s);
10955 check_absolute_expr (ip, &imm_expr);
10956 if ((unsigned long) imm_expr.X_add_number > mask)
10957 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10958 mask, (unsigned long) imm_expr.X_add_number);
10959 INSERT_OPERAND (mips_opts.micromips,
10960 SA3, *ip, imm_expr.X_add_number);
10961 imm_expr.X_op = O_absent;
10967 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10968 code) or 21 (for microMIPS code). */
10970 unsigned long mask = (mips_opts.micromips
10971 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10973 my_getExpression (&imm_expr, s);
10974 check_absolute_expr (ip, &imm_expr);
10975 if ((unsigned long) imm_expr.X_add_number > mask)
10976 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10977 mask, (unsigned long) imm_expr.X_add_number);
10978 INSERT_OPERAND (mips_opts.micromips,
10979 SA4, *ip, imm_expr.X_add_number);
10980 imm_expr.X_op = O_absent;
10986 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10987 code) or 16 (for microMIPS code). */
10989 unsigned long mask = (mips_opts.micromips
10990 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10992 my_getExpression (&imm_expr, s);
10993 check_absolute_expr (ip, &imm_expr);
10994 if ((unsigned long) imm_expr.X_add_number > mask)
10995 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10996 mask, (unsigned long) imm_expr.X_add_number);
10997 INSERT_OPERAND (mips_opts.micromips,
10998 IMM8, *ip, imm_expr.X_add_number);
10999 imm_expr.X_op = O_absent;
11005 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11006 code) or 21 (for microMIPS code). */
11008 unsigned long mask = (mips_opts.micromips
11009 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11011 my_getExpression (&imm_expr, s);
11012 check_absolute_expr (ip, &imm_expr);
11013 if ((unsigned long) imm_expr.X_add_number > mask)
11014 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11015 mask, (unsigned long) imm_expr.X_add_number);
11016 INSERT_OPERAND (mips_opts.micromips,
11017 RS, *ip, imm_expr.X_add_number);
11018 imm_expr.X_op = O_absent;
11023 case '7': /* Four DSP accumulators in bits 11,12. */
11024 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11025 && s[3] >= '0' && s[3] <= '3')
11027 regno = s[3] - '0';
11029 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11033 as_bad (_("Invalid dsp acc register"));
11037 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11038 code) or 14 (for microMIPS code). */
11040 unsigned long mask = (mips_opts.micromips
11041 ? MICROMIPSOP_MASK_WRDSP
11044 my_getExpression (&imm_expr, s);
11045 check_absolute_expr (ip, &imm_expr);
11046 if ((unsigned long) imm_expr.X_add_number > mask)
11047 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11048 mask, (unsigned long) imm_expr.X_add_number);
11049 INSERT_OPERAND (mips_opts.micromips,
11050 WRDSP, *ip, imm_expr.X_add_number);
11051 imm_expr.X_op = O_absent;
11056 case '9': /* Four DSP accumulators in bits 21,22. */
11057 gas_assert (!mips_opts.micromips);
11058 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11059 && s[3] >= '0' && s[3] <= '3')
11061 regno = s[3] - '0';
11063 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11067 as_bad (_("Invalid dsp acc register"));
11071 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11072 code) or 20 (for microMIPS code). */
11074 long mask = (mips_opts.micromips
11075 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11077 my_getExpression (&imm_expr, s);
11078 check_absolute_expr (ip, &imm_expr);
11079 min_range = -((mask + 1) >> 1);
11080 max_range = ((mask + 1) >> 1) - 1;
11081 if (imm_expr.X_add_number < min_range
11082 || imm_expr.X_add_number > max_range)
11083 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11084 (long) min_range, (long) max_range,
11085 (long) imm_expr.X_add_number);
11086 INSERT_OPERAND (mips_opts.micromips,
11087 DSPSFT, *ip, imm_expr.X_add_number);
11088 imm_expr.X_op = O_absent;
11093 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11094 gas_assert (!mips_opts.micromips);
11095 my_getExpression (&imm_expr, s);
11096 check_absolute_expr (ip, &imm_expr);
11097 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11099 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11101 (unsigned long) imm_expr.X_add_number);
11103 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11104 imm_expr.X_op = O_absent;
11108 case ':': /* DSP 7-bit signed immediate in bit 19. */
11109 gas_assert (!mips_opts.micromips);
11110 my_getExpression (&imm_expr, s);
11111 check_absolute_expr (ip, &imm_expr);
11112 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11113 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11114 if (imm_expr.X_add_number < min_range ||
11115 imm_expr.X_add_number > max_range)
11117 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11118 (long) min_range, (long) max_range,
11119 (long) imm_expr.X_add_number);
11121 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11122 imm_expr.X_op = O_absent;
11126 case '@': /* DSP 10-bit signed immediate in bit 16. */
11128 long mask = (mips_opts.micromips
11129 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11131 my_getExpression (&imm_expr, s);
11132 check_absolute_expr (ip, &imm_expr);
11133 min_range = -((mask + 1) >> 1);
11134 max_range = ((mask + 1) >> 1) - 1;
11135 if (imm_expr.X_add_number < min_range
11136 || imm_expr.X_add_number > max_range)
11137 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11138 (long) min_range, (long) max_range,
11139 (long) imm_expr.X_add_number);
11140 INSERT_OPERAND (mips_opts.micromips,
11141 IMM10, *ip, imm_expr.X_add_number);
11142 imm_expr.X_op = O_absent;
11147 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11148 gas_assert (mips_opts.micromips);
11149 my_getExpression (&imm_expr, s);
11150 check_absolute_expr (ip, &imm_expr);
11151 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11152 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11153 MICROMIPSOP_MASK_RD,
11154 (unsigned long) imm_expr.X_add_number);
11155 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11156 imm_expr.X_op = O_absent;
11160 case '!': /* MT usermode flag bit. */
11161 gas_assert (!mips_opts.micromips);
11162 my_getExpression (&imm_expr, s);
11163 check_absolute_expr (ip, &imm_expr);
11164 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11165 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11166 (unsigned long) imm_expr.X_add_number);
11167 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11168 imm_expr.X_op = O_absent;
11172 case '$': /* MT load high flag bit. */
11173 gas_assert (!mips_opts.micromips);
11174 my_getExpression (&imm_expr, s);
11175 check_absolute_expr (ip, &imm_expr);
11176 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11177 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11178 (unsigned long) imm_expr.X_add_number);
11179 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11180 imm_expr.X_op = O_absent;
11184 case '*': /* Four DSP accumulators in bits 18,19. */
11185 gas_assert (!mips_opts.micromips);
11186 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11187 s[3] >= '0' && s[3] <= '3')
11189 regno = s[3] - '0';
11191 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11195 as_bad (_("Invalid dsp/smartmips acc register"));
11198 case '&': /* Four DSP accumulators in bits 13,14. */
11199 gas_assert (!mips_opts.micromips);
11200 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11201 s[3] >= '0' && s[3] <= '3')
11203 regno = s[3] - '0';
11205 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11209 as_bad (_("Invalid dsp/smartmips acc register"));
11212 case '\\': /* 3-bit bit position. */
11214 unsigned long mask = (mips_opts.micromips
11215 ? MICROMIPSOP_MASK_3BITPOS
11216 : OP_MASK_3BITPOS);
11218 my_getExpression (&imm_expr, s);
11219 check_absolute_expr (ip, &imm_expr);
11220 if ((unsigned long) imm_expr.X_add_number > mask)
11221 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11223 mask, (unsigned long) imm_expr.X_add_number);
11224 INSERT_OPERAND (mips_opts.micromips,
11225 3BITPOS, *ip, imm_expr.X_add_number);
11226 imm_expr.X_op = O_absent;
11240 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11244 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11248 gas_assert (!mips_opts.micromips);
11249 INSERT_OPERAND (0, FT, *ip, lastregno);
11253 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11259 /* Handle optional base register.
11260 Either the base register is omitted or
11261 we must have a left paren. */
11262 /* This is dependent on the next operand specifier
11263 is a base register specification. */
11264 gas_assert (args[1] == 'b'
11265 || (mips_opts.micromips
11267 && (args[2] == 'l' || args[2] == 'n'
11268 || args[2] == 's' || args[2] == 'a')));
11269 if (*s == '\0' && args[1] == 'b')
11271 /* Fall through. */
11273 case ')': /* These must match exactly. */
11278 case '[': /* These must match exactly. */
11280 gas_assert (!mips_opts.micromips);
11285 case '+': /* Opcode extension character. */
11288 case '1': /* UDI immediates. */
11292 gas_assert (!mips_opts.micromips);
11294 const struct mips_immed *imm = mips_immed;
11296 while (imm->type && imm->type != *args)
11300 my_getExpression (&imm_expr, s);
11301 check_absolute_expr (ip, &imm_expr);
11302 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11304 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11305 imm->desc ? imm->desc : ip->insn_mo->name,
11306 (unsigned long) imm_expr.X_add_number,
11307 (unsigned long) imm_expr.X_add_number);
11308 imm_expr.X_add_number &= imm->mask;
11310 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11312 imm_expr.X_op = O_absent;
11317 case 'A': /* ins/ext position, becomes LSB. */
11326 my_getExpression (&imm_expr, s);
11327 check_absolute_expr (ip, &imm_expr);
11328 if ((unsigned long) imm_expr.X_add_number < limlo
11329 || (unsigned long) imm_expr.X_add_number > limhi)
11331 as_bad (_("Improper position (%lu)"),
11332 (unsigned long) imm_expr.X_add_number);
11333 imm_expr.X_add_number = limlo;
11335 lastpos = imm_expr.X_add_number;
11336 INSERT_OPERAND (mips_opts.micromips,
11337 EXTLSB, *ip, imm_expr.X_add_number);
11338 imm_expr.X_op = O_absent;
11342 case 'B': /* ins size, becomes MSB. */
11351 my_getExpression (&imm_expr, s);
11352 check_absolute_expr (ip, &imm_expr);
11353 /* Check for negative input so that small negative numbers
11354 will not succeed incorrectly. The checks against
11355 (pos+size) transitively check "size" itself,
11356 assuming that "pos" is reasonable. */
11357 if ((long) imm_expr.X_add_number < 0
11358 || ((unsigned long) imm_expr.X_add_number
11360 || ((unsigned long) imm_expr.X_add_number
11361 + lastpos) > limhi)
11363 as_bad (_("Improper insert size (%lu, position %lu)"),
11364 (unsigned long) imm_expr.X_add_number,
11365 (unsigned long) lastpos);
11366 imm_expr.X_add_number = limlo - lastpos;
11368 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11369 lastpos + imm_expr.X_add_number - 1);
11370 imm_expr.X_op = O_absent;
11374 case 'C': /* ext size, becomes MSBD. */
11387 my_getExpression (&imm_expr, s);
11388 check_absolute_expr (ip, &imm_expr);
11389 /* Check for negative input so that small negative numbers
11390 will not succeed incorrectly. The checks against
11391 (pos+size) transitively check "size" itself,
11392 assuming that "pos" is reasonable. */
11393 if ((long) imm_expr.X_add_number < 0
11394 || ((unsigned long) imm_expr.X_add_number
11396 || ((unsigned long) imm_expr.X_add_number
11397 + lastpos) > limhi)
11399 as_bad (_("Improper extract size (%lu, position %lu)"),
11400 (unsigned long) imm_expr.X_add_number,
11401 (unsigned long) lastpos);
11402 imm_expr.X_add_number = limlo - lastpos;
11404 INSERT_OPERAND (mips_opts.micromips,
11405 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11406 imm_expr.X_op = O_absent;
11411 /* +D is for disassembly only; never match. */
11415 /* "+I" is like "I", except that imm2_expr is used. */
11416 my_getExpression (&imm2_expr, s);
11417 if (imm2_expr.X_op != O_big
11418 && imm2_expr.X_op != O_constant)
11419 insn_error = _("absolute expression required");
11420 if (HAVE_32BIT_GPRS)
11421 normalize_constant_expr (&imm2_expr);
11425 case 'T': /* Coprocessor register. */
11426 gas_assert (!mips_opts.micromips);
11427 /* +T is for disassembly only; never match. */
11430 case 't': /* Coprocessor register number. */
11431 gas_assert (!mips_opts.micromips);
11432 if (s[0] == '$' && ISDIGIT (s[1]))
11442 while (ISDIGIT (*s));
11444 as_bad (_("Invalid register number (%d)"), regno);
11447 INSERT_OPERAND (0, RT, *ip, regno);
11452 as_bad (_("Invalid coprocessor 0 register number"));
11456 /* bbit[01] and bbit[01]32 bit index. Give error if index
11457 is not in the valid range. */
11458 gas_assert (!mips_opts.micromips);
11459 my_getExpression (&imm_expr, s);
11460 check_absolute_expr (ip, &imm_expr);
11461 if ((unsigned) imm_expr.X_add_number > 31)
11463 as_bad (_("Improper bit index (%lu)"),
11464 (unsigned long) imm_expr.X_add_number);
11465 imm_expr.X_add_number = 0;
11467 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11468 imm_expr.X_op = O_absent;
11473 /* bbit[01] bit index when bbit is used but we generate
11474 bbit[01]32 because the index is over 32. Move to the
11475 next candidate if index is not in the valid range. */
11476 gas_assert (!mips_opts.micromips);
11477 my_getExpression (&imm_expr, s);
11478 check_absolute_expr (ip, &imm_expr);
11479 if ((unsigned) imm_expr.X_add_number < 32
11480 || (unsigned) imm_expr.X_add_number > 63)
11482 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11483 imm_expr.X_op = O_absent;
11488 /* cins, cins32, exts and exts32 position field. Give error
11489 if it's not in the valid range. */
11490 gas_assert (!mips_opts.micromips);
11491 my_getExpression (&imm_expr, s);
11492 check_absolute_expr (ip, &imm_expr);
11493 if ((unsigned) imm_expr.X_add_number > 31)
11495 as_bad (_("Improper position (%lu)"),
11496 (unsigned long) imm_expr.X_add_number);
11497 imm_expr.X_add_number = 0;
11499 /* Make the pos explicit to simplify +S. */
11500 lastpos = imm_expr.X_add_number + 32;
11501 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11502 imm_expr.X_op = O_absent;
11507 /* cins, cins32, exts and exts32 position field. Move to
11508 the next candidate if it's not in the valid range. */
11509 gas_assert (!mips_opts.micromips);
11510 my_getExpression (&imm_expr, s);
11511 check_absolute_expr (ip, &imm_expr);
11512 if ((unsigned) imm_expr.X_add_number < 32
11513 || (unsigned) imm_expr.X_add_number > 63)
11515 lastpos = imm_expr.X_add_number;
11516 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11517 imm_expr.X_op = O_absent;
11522 /* cins and exts length-minus-one field. */
11523 gas_assert (!mips_opts.micromips);
11524 my_getExpression (&imm_expr, s);
11525 check_absolute_expr (ip, &imm_expr);
11526 if ((unsigned long) imm_expr.X_add_number > 31)
11528 as_bad (_("Improper size (%lu)"),
11529 (unsigned long) imm_expr.X_add_number);
11530 imm_expr.X_add_number = 0;
11532 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11533 imm_expr.X_op = O_absent;
11538 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11539 length-minus-one field. */
11540 gas_assert (!mips_opts.micromips);
11541 my_getExpression (&imm_expr, s);
11542 check_absolute_expr (ip, &imm_expr);
11543 if ((long) imm_expr.X_add_number < 0
11544 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11546 as_bad (_("Improper size (%lu)"),
11547 (unsigned long) imm_expr.X_add_number);
11548 imm_expr.X_add_number = 0;
11550 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11551 imm_expr.X_op = O_absent;
11556 /* seqi/snei immediate field. */
11557 gas_assert (!mips_opts.micromips);
11558 my_getExpression (&imm_expr, s);
11559 check_absolute_expr (ip, &imm_expr);
11560 if ((long) imm_expr.X_add_number < -512
11561 || (long) imm_expr.X_add_number >= 512)
11563 as_bad (_("Improper immediate (%ld)"),
11564 (long) imm_expr.X_add_number);
11565 imm_expr.X_add_number = 0;
11567 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11568 imm_expr.X_op = O_absent;
11572 case 'a': /* 8-bit signed offset in bit 6 */
11573 gas_assert (!mips_opts.micromips);
11574 my_getExpression (&imm_expr, s);
11575 check_absolute_expr (ip, &imm_expr);
11576 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11577 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11578 if (imm_expr.X_add_number < min_range
11579 || imm_expr.X_add_number > max_range)
11581 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11582 (long) min_range, (long) max_range,
11583 (long) imm_expr.X_add_number);
11585 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11586 imm_expr.X_op = O_absent;
11590 case 'b': /* 8-bit signed offset in bit 3 */
11591 gas_assert (!mips_opts.micromips);
11592 my_getExpression (&imm_expr, s);
11593 check_absolute_expr (ip, &imm_expr);
11594 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11595 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11596 if (imm_expr.X_add_number < min_range
11597 || imm_expr.X_add_number > max_range)
11599 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11600 (long) min_range, (long) max_range,
11601 (long) imm_expr.X_add_number);
11603 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11604 imm_expr.X_op = O_absent;
11608 case 'c': /* 9-bit signed offset in bit 6 */
11609 gas_assert (!mips_opts.micromips);
11610 my_getExpression (&imm_expr, s);
11611 check_absolute_expr (ip, &imm_expr);
11612 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11613 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11614 /* We check the offset range before adjusted. */
11617 if (imm_expr.X_add_number < min_range
11618 || imm_expr.X_add_number > max_range)
11620 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11621 (long) min_range, (long) max_range,
11622 (long) imm_expr.X_add_number);
11624 if (imm_expr.X_add_number & 0xf)
11626 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11627 (long) imm_expr.X_add_number);
11629 /* Right shift 4 bits to adjust the offset operand. */
11630 INSERT_OPERAND (0, OFFSET_C, *ip,
11631 imm_expr.X_add_number >> 4);
11632 imm_expr.X_op = O_absent;
11637 gas_assert (!mips_opts.micromips);
11638 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11640 if (regno == AT && mips_opts.at)
11642 if (mips_opts.at == ATREG)
11643 as_warn (_("used $at without \".set noat\""));
11645 as_warn (_("used $%u with \".set at=$%u\""),
11646 regno, mips_opts.at);
11648 INSERT_OPERAND (0, RZ, *ip, regno);
11652 gas_assert (!mips_opts.micromips);
11653 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11655 INSERT_OPERAND (0, FZ, *ip, regno);
11659 as_bad (_("Internal error: bad %s opcode "
11660 "(unknown extension operand type `+%c'): %s %s"),
11661 mips_opts.micromips ? "microMIPS" : "MIPS",
11662 *args, insn->name, insn->args);
11663 /* Further processing is fruitless. */
11668 case '.': /* 10-bit offset. */
11669 gas_assert (mips_opts.micromips);
11670 case '~': /* 12-bit offset. */
11672 int shift = *args == '.' ? 9 : 11;
11675 /* Check whether there is only a single bracketed expression
11676 left. If so, it must be the base register and the
11677 constant must be zero. */
11678 if (*s == '(' && strchr (s + 1, '(') == 0)
11681 /* If this value won't fit into the offset, then go find
11682 a macro that will generate a 16- or 32-bit offset code
11684 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11685 if ((i == 0 && (imm_expr.X_op != O_constant
11686 || imm_expr.X_add_number >= 1 << shift
11687 || imm_expr.X_add_number < -1 << shift))
11690 imm_expr.X_op = O_absent;
11694 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11696 INSERT_OPERAND (mips_opts.micromips,
11697 OFFSET12, *ip, imm_expr.X_add_number);
11698 imm_expr.X_op = O_absent;
11703 case '<': /* must be at least one digit */
11705 * According to the manual, if the shift amount is greater
11706 * than 31 or less than 0, then the shift amount should be
11707 * mod 32. In reality the mips assembler issues an error.
11708 * We issue a warning and mask out all but the low 5 bits.
11710 my_getExpression (&imm_expr, s);
11711 check_absolute_expr (ip, &imm_expr);
11712 if ((unsigned long) imm_expr.X_add_number > 31)
11713 as_warn (_("Improper shift amount (%lu)"),
11714 (unsigned long) imm_expr.X_add_number);
11715 INSERT_OPERAND (mips_opts.micromips,
11716 SHAMT, *ip, imm_expr.X_add_number);
11717 imm_expr.X_op = O_absent;
11721 case '>': /* shift amount minus 32 */
11722 my_getExpression (&imm_expr, s);
11723 check_absolute_expr (ip, &imm_expr);
11724 if ((unsigned long) imm_expr.X_add_number < 32
11725 || (unsigned long) imm_expr.X_add_number > 63)
11727 INSERT_OPERAND (mips_opts.micromips,
11728 SHAMT, *ip, imm_expr.X_add_number - 32);
11729 imm_expr.X_op = O_absent;
11733 case 'k': /* CACHE code. */
11734 case 'h': /* PREFX code. */
11735 case '1': /* SYNC type. */
11736 my_getExpression (&imm_expr, s);
11737 check_absolute_expr (ip, &imm_expr);
11738 if ((unsigned long) imm_expr.X_add_number > 31)
11739 as_warn (_("Invalid value for `%s' (%lu)"),
11741 (unsigned long) imm_expr.X_add_number);
11745 if (mips_fix_cn63xxp1
11746 && !mips_opts.micromips
11747 && strcmp ("pref", insn->name) == 0)
11748 switch (imm_expr.X_add_number)
11757 case 31: /* These are ok. */
11760 default: /* The rest must be changed to 28. */
11761 imm_expr.X_add_number = 28;
11764 INSERT_OPERAND (mips_opts.micromips,
11765 CACHE, *ip, imm_expr.X_add_number);
11768 INSERT_OPERAND (mips_opts.micromips,
11769 PREFX, *ip, imm_expr.X_add_number);
11772 INSERT_OPERAND (mips_opts.micromips,
11773 STYPE, *ip, imm_expr.X_add_number);
11776 imm_expr.X_op = O_absent;
11780 case 'c': /* BREAK code. */
11782 unsigned long mask = (mips_opts.micromips
11783 ? MICROMIPSOP_MASK_CODE
11786 my_getExpression (&imm_expr, s);
11787 check_absolute_expr (ip, &imm_expr);
11788 if ((unsigned long) imm_expr.X_add_number > mask)
11789 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11791 mask, (unsigned long) imm_expr.X_add_number);
11792 INSERT_OPERAND (mips_opts.micromips,
11793 CODE, *ip, imm_expr.X_add_number);
11794 imm_expr.X_op = O_absent;
11799 case 'q': /* Lower BREAK code. */
11801 unsigned long mask = (mips_opts.micromips
11802 ? MICROMIPSOP_MASK_CODE2
11805 my_getExpression (&imm_expr, s);
11806 check_absolute_expr (ip, &imm_expr);
11807 if ((unsigned long) imm_expr.X_add_number > mask)
11808 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11810 mask, (unsigned long) imm_expr.X_add_number);
11811 INSERT_OPERAND (mips_opts.micromips,
11812 CODE2, *ip, imm_expr.X_add_number);
11813 imm_expr.X_op = O_absent;
11818 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11820 unsigned long mask = (mips_opts.micromips
11821 ? MICROMIPSOP_MASK_CODE10
11824 my_getExpression (&imm_expr, s);
11825 check_absolute_expr (ip, &imm_expr);
11826 if ((unsigned long) imm_expr.X_add_number > mask)
11827 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11829 mask, (unsigned long) imm_expr.X_add_number);
11830 if (mips_opts.micromips)
11831 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11833 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11834 imm_expr.X_op = O_absent;
11839 case 'C': /* 25- or 23-bit coprocessor code. */
11841 unsigned long mask = (mips_opts.micromips
11842 ? MICROMIPSOP_MASK_COPZ
11845 my_getExpression (&imm_expr, s);
11846 check_absolute_expr (ip, &imm_expr);
11847 if ((unsigned long) imm_expr.X_add_number > mask)
11848 as_warn (_("Coproccesor code > %u bits (%lu)"),
11849 mips_opts.micromips ? 23U : 25U,
11850 (unsigned long) imm_expr.X_add_number);
11851 INSERT_OPERAND (mips_opts.micromips,
11852 COPZ, *ip, imm_expr.X_add_number);
11853 imm_expr.X_op = O_absent;
11858 case 'J': /* 19-bit WAIT code. */
11859 gas_assert (!mips_opts.micromips);
11860 my_getExpression (&imm_expr, s);
11861 check_absolute_expr (ip, &imm_expr);
11862 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11864 as_warn (_("Illegal 19-bit code (%lu)"),
11865 (unsigned long) imm_expr.X_add_number);
11866 imm_expr.X_add_number &= OP_MASK_CODE19;
11868 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11869 imm_expr.X_op = O_absent;
11873 case 'P': /* Performance register. */
11874 gas_assert (!mips_opts.micromips);
11875 my_getExpression (&imm_expr, s);
11876 check_absolute_expr (ip, &imm_expr);
11877 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11878 as_warn (_("Invalid performance register (%lu)"),
11879 (unsigned long) imm_expr.X_add_number);
11880 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
11881 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
11882 as_warn (_("Invalid performance register (%lu)"),
11883 (unsigned long) imm_expr.X_add_number);
11884 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11885 imm_expr.X_op = O_absent;
11889 case 'G': /* Coprocessor destination register. */
11891 unsigned long opcode = ip->insn_opcode;
11892 unsigned long mask;
11893 unsigned int types;
11896 if (mips_opts.micromips)
11898 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11899 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11900 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11904 case 0x000000fc: /* mfc0 */
11905 case 0x000002fc: /* mtc0 */
11906 case 0x580000fc: /* dmfc0 */
11907 case 0x580002fc: /* dmtc0 */
11917 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11918 cop0 = opcode == OP_OP_COP0;
11920 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11921 ok = reg_lookup (&s, types, ®no);
11922 if (mips_opts.micromips)
11923 INSERT_OPERAND (1, RS, *ip, regno);
11925 INSERT_OPERAND (0, RD, *ip, regno);
11934 case 'y': /* ALNV.PS source register. */
11935 gas_assert (mips_opts.micromips);
11937 case 'x': /* Ignore register name. */
11938 case 'U': /* Destination register (CLO/CLZ). */
11939 case 'g': /* Coprocessor destination register. */
11940 gas_assert (!mips_opts.micromips);
11941 case 'b': /* Base register. */
11942 case 'd': /* Destination register. */
11943 case 's': /* Source register. */
11944 case 't': /* Target register. */
11945 case 'r': /* Both target and source. */
11946 case 'v': /* Both dest and source. */
11947 case 'w': /* Both dest and target. */
11948 case 'E': /* Coprocessor target register. */
11949 case 'K': /* RDHWR destination register. */
11950 case 'z': /* Must be zero register. */
11953 if (*args == 'E' || *args == 'K')
11954 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11957 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11958 if (regno == AT && mips_opts.at)
11960 if (mips_opts.at == ATREG)
11961 as_warn (_("Used $at without \".set noat\""));
11963 as_warn (_("Used $%u with \".set at=$%u\""),
11964 regno, mips_opts.at);
11974 if (c == 'r' || c == 'v' || c == 'w')
11981 /* 'z' only matches $0. */
11982 if (c == 'z' && regno != 0)
11985 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11987 if (regno == lastregno)
11990 = _("Source and destination must be different");
11993 if (regno == 31 && lastregno == 0xffffffff)
11996 = _("A destination register must be supplied");
12000 /* Now that we have assembled one operand, we use the args
12001 string to figure out where it goes in the instruction. */
12008 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12012 if (mips_opts.micromips)
12013 INSERT_OPERAND (1, RS, *ip, regno);
12015 INSERT_OPERAND (0, RD, *ip, regno);
12020 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12024 gas_assert (!mips_opts.micromips);
12025 INSERT_OPERAND (0, RD, *ip, regno);
12026 INSERT_OPERAND (0, RT, *ip, regno);
12032 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12036 gas_assert (mips_opts.micromips);
12037 INSERT_OPERAND (1, RS3, *ip, regno);
12041 /* This case exists because on the r3000 trunc
12042 expands into a macro which requires a gp
12043 register. On the r6000 or r4000 it is
12044 assembled into a single instruction which
12045 ignores the register. Thus the insn version
12046 is MIPS_ISA2 and uses 'x', and the macro
12047 version is MIPS_ISA1 and uses 't'. */
12051 /* This case is for the div instruction, which
12052 acts differently if the destination argument
12053 is $0. This only matches $0, and is checked
12054 outside the switch. */
12064 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12068 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12073 case 'O': /* MDMX alignment immediate constant. */
12074 gas_assert (!mips_opts.micromips);
12075 my_getExpression (&imm_expr, s);
12076 check_absolute_expr (ip, &imm_expr);
12077 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12078 as_warn (_("Improper align amount (%ld), using low bits"),
12079 (long) imm_expr.X_add_number);
12080 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12081 imm_expr.X_op = O_absent;
12085 case 'Q': /* MDMX vector, element sel, or const. */
12088 /* MDMX Immediate. */
12089 gas_assert (!mips_opts.micromips);
12090 my_getExpression (&imm_expr, s);
12091 check_absolute_expr (ip, &imm_expr);
12092 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12093 as_warn (_("Invalid MDMX Immediate (%ld)"),
12094 (long) imm_expr.X_add_number);
12095 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12096 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12097 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12099 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12100 imm_expr.X_op = O_absent;
12104 /* Not MDMX Immediate. Fall through. */
12105 case 'X': /* MDMX destination register. */
12106 case 'Y': /* MDMX source register. */
12107 case 'Z': /* MDMX target register. */
12110 gas_assert (!mips_opts.micromips);
12111 case 'D': /* Floating point destination register. */
12112 case 'S': /* Floating point source register. */
12113 case 'T': /* Floating point target register. */
12114 case 'R': /* Floating point source register. */
12118 || (mips_opts.ase_mdmx
12119 && (ip->insn_mo->pinfo & FP_D)
12120 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12121 | INSN_COPROC_MEMORY_DELAY
12122 | INSN_LOAD_COPROC_DELAY
12123 | INSN_LOAD_MEMORY_DELAY
12124 | INSN_STORE_MEMORY))))
12125 rtype |= RTYPE_VEC;
12127 if (reg_lookup (&s, rtype, ®no))
12129 if ((regno & 1) != 0
12131 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12132 as_warn (_("Float register should be even, was %d"),
12140 if (c == 'V' || c == 'W')
12151 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12157 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12161 /* This is like 'Z', but also needs to fix the MDMX
12162 vector/scalar select bits. Note that the
12163 scalar immediate case is handled above. */
12166 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12167 int max_el = (is_qh ? 3 : 7);
12169 my_getExpression(&imm_expr, s);
12170 check_absolute_expr (ip, &imm_expr);
12172 if (imm_expr.X_add_number > max_el)
12173 as_bad (_("Bad element selector %ld"),
12174 (long) imm_expr.X_add_number);
12175 imm_expr.X_add_number &= max_el;
12176 ip->insn_opcode |= (imm_expr.X_add_number
12179 imm_expr.X_op = O_absent;
12181 as_warn (_("Expecting ']' found '%s'"), s);
12187 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12188 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12191 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12194 /* Fall through. */
12198 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12202 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12212 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12216 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12222 my_getExpression (&imm_expr, s);
12223 if (imm_expr.X_op != O_big
12224 && imm_expr.X_op != O_constant)
12225 insn_error = _("absolute expression required");
12226 if (HAVE_32BIT_GPRS)
12227 normalize_constant_expr (&imm_expr);
12232 my_getExpression (&offset_expr, s);
12233 normalize_address_expr (&offset_expr);
12234 *imm_reloc = BFD_RELOC_32;
12247 unsigned char temp[8];
12249 unsigned int length;
12254 /* These only appear as the last operand in an
12255 instruction, and every instruction that accepts
12256 them in any variant accepts them in all variants.
12257 This means we don't have to worry about backing out
12258 any changes if the instruction does not match.
12260 The difference between them is the size of the
12261 floating point constant and where it goes. For 'F'
12262 and 'L' the constant is 64 bits; for 'f' and 'l' it
12263 is 32 bits. Where the constant is placed is based
12264 on how the MIPS assembler does things:
12267 f -- immediate value
12270 The .lit4 and .lit8 sections are only used if
12271 permitted by the -G argument.
12273 The code below needs to know whether the target register
12274 is 32 or 64 bits wide. It relies on the fact 'f' and
12275 'F' are used with GPR-based instructions and 'l' and
12276 'L' are used with FPR-based instructions. */
12278 f64 = *args == 'F' || *args == 'L';
12279 using_gprs = *args == 'F' || *args == 'f';
12281 save_in = input_line_pointer;
12282 input_line_pointer = s;
12283 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12285 s = input_line_pointer;
12286 input_line_pointer = save_in;
12287 if (err != NULL && *err != '\0')
12289 as_bad (_("Bad floating point constant: %s"), err);
12290 memset (temp, '\0', sizeof temp);
12291 length = f64 ? 8 : 4;
12294 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12298 && (g_switch_value < 4
12299 || (temp[0] == 0 && temp[1] == 0)
12300 || (temp[2] == 0 && temp[3] == 0))))
12302 imm_expr.X_op = O_constant;
12303 if (!target_big_endian)
12304 imm_expr.X_add_number = bfd_getl32 (temp);
12306 imm_expr.X_add_number = bfd_getb32 (temp);
12308 else if (length > 4
12309 && !mips_disable_float_construction
12310 /* Constants can only be constructed in GPRs and
12311 copied to FPRs if the GPRs are at least as wide
12312 as the FPRs. Force the constant into memory if
12313 we are using 64-bit FPRs but the GPRs are only
12316 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12317 && ((temp[0] == 0 && temp[1] == 0)
12318 || (temp[2] == 0 && temp[3] == 0))
12319 && ((temp[4] == 0 && temp[5] == 0)
12320 || (temp[6] == 0 && temp[7] == 0)))
12322 /* The value is simple enough to load with a couple of
12323 instructions. If using 32-bit registers, set
12324 imm_expr to the high order 32 bits and offset_expr to
12325 the low order 32 bits. Otherwise, set imm_expr to
12326 the entire 64 bit constant. */
12327 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12329 imm_expr.X_op = O_constant;
12330 offset_expr.X_op = O_constant;
12331 if (!target_big_endian)
12333 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12334 offset_expr.X_add_number = bfd_getl32 (temp);
12338 imm_expr.X_add_number = bfd_getb32 (temp);
12339 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12341 if (offset_expr.X_add_number == 0)
12342 offset_expr.X_op = O_absent;
12344 else if (sizeof (imm_expr.X_add_number) > 4)
12346 imm_expr.X_op = O_constant;
12347 if (!target_big_endian)
12348 imm_expr.X_add_number = bfd_getl64 (temp);
12350 imm_expr.X_add_number = bfd_getb64 (temp);
12354 imm_expr.X_op = O_big;
12355 imm_expr.X_add_number = 4;
12356 if (!target_big_endian)
12358 generic_bignum[0] = bfd_getl16 (temp);
12359 generic_bignum[1] = bfd_getl16 (temp + 2);
12360 generic_bignum[2] = bfd_getl16 (temp + 4);
12361 generic_bignum[3] = bfd_getl16 (temp + 6);
12365 generic_bignum[0] = bfd_getb16 (temp + 6);
12366 generic_bignum[1] = bfd_getb16 (temp + 4);
12367 generic_bignum[2] = bfd_getb16 (temp + 2);
12368 generic_bignum[3] = bfd_getb16 (temp);
12374 const char *newname;
12377 /* Switch to the right section. */
12379 subseg = now_subseg;
12382 default: /* unused default case avoids warnings. */
12384 newname = RDATA_SECTION_NAME;
12385 if (g_switch_value >= 8)
12389 newname = RDATA_SECTION_NAME;
12392 gas_assert (g_switch_value >= 4);
12396 new_seg = subseg_new (newname, (subsegT) 0);
12398 bfd_set_section_flags (stdoutput, new_seg,
12403 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12404 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12405 record_alignment (new_seg, 4);
12407 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12408 if (seg == now_seg)
12409 as_bad (_("Can't use floating point insn in this section"));
12411 /* Set the argument to the current address in the
12413 offset_expr.X_op = O_symbol;
12414 offset_expr.X_add_symbol = symbol_temp_new_now ();
12415 offset_expr.X_add_number = 0;
12417 /* Put the floating point number into the section. */
12418 p = frag_more ((int) length);
12419 memcpy (p, temp, length);
12421 /* Switch back to the original section. */
12422 subseg_set (seg, subseg);
12427 case 'i': /* 16-bit unsigned immediate. */
12428 case 'j': /* 16-bit signed immediate. */
12429 *imm_reloc = BFD_RELOC_LO16;
12430 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12433 offsetT minval, maxval;
12435 more = (insn + 1 < past
12436 && strcmp (insn->name, insn[1].name) == 0);
12438 /* If the expression was written as an unsigned number,
12439 only treat it as signed if there are no more
12443 && sizeof (imm_expr.X_add_number) <= 4
12444 && imm_expr.X_op == O_constant
12445 && imm_expr.X_add_number < 0
12446 && imm_expr.X_unsigned
12447 && HAVE_64BIT_GPRS)
12450 /* For compatibility with older assemblers, we accept
12451 0x8000-0xffff as signed 16-bit numbers when only
12452 signed numbers are allowed. */
12454 minval = 0, maxval = 0xffff;
12456 minval = -0x8000, maxval = 0x7fff;
12458 minval = -0x8000, maxval = 0xffff;
12460 if (imm_expr.X_op != O_constant
12461 || imm_expr.X_add_number < minval
12462 || imm_expr.X_add_number > maxval)
12466 if (imm_expr.X_op == O_constant
12467 || imm_expr.X_op == O_big)
12468 as_bad (_("Expression out of range"));
12474 case 'o': /* 16-bit offset. */
12475 offset_reloc[0] = BFD_RELOC_LO16;
12476 offset_reloc[1] = BFD_RELOC_UNUSED;
12477 offset_reloc[2] = BFD_RELOC_UNUSED;
12479 /* Check whether there is only a single bracketed expression
12480 left. If so, it must be the base register and the
12481 constant must be zero. */
12482 if (*s == '(' && strchr (s + 1, '(') == 0)
12484 offset_expr.X_op = O_constant;
12485 offset_expr.X_add_number = 0;
12489 /* If this value won't fit into a 16 bit offset, then go
12490 find a macro that will generate the 32 bit offset
12492 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12493 && (offset_expr.X_op != O_constant
12494 || offset_expr.X_add_number >= 0x8000
12495 || offset_expr.X_add_number < -0x8000))
12501 case 'p': /* PC-relative offset. */
12502 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12503 my_getExpression (&offset_expr, s);
12507 case 'u': /* Upper 16 bits. */
12508 *imm_reloc = BFD_RELOC_LO16;
12509 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12510 && imm_expr.X_op == O_constant
12511 && (imm_expr.X_add_number < 0
12512 || imm_expr.X_add_number >= 0x10000))
12513 as_bad (_("lui expression (%lu) not in range 0..65535"),
12514 (unsigned long) imm_expr.X_add_number);
12518 case 'a': /* 26-bit address. */
12519 *offset_reloc = BFD_RELOC_MIPS_JMP;
12520 my_getExpression (&offset_expr, s);
12524 case 'N': /* 3-bit branch condition code. */
12525 case 'M': /* 3-bit compare condition code. */
12527 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12528 rtype |= RTYPE_FCC;
12529 if (!reg_lookup (&s, rtype, ®no))
12531 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12532 || strcmp (str + strlen (str) - 5, "any2f") == 0
12533 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12534 && (regno & 1) != 0)
12535 as_warn (_("Condition code register should be even for %s, "
12538 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12539 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12540 && (regno & 3) != 0)
12541 as_warn (_("Condition code register should be 0 or 4 for %s, "
12545 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12547 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12551 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12562 while (ISDIGIT (*s));
12565 c = 8; /* Invalid sel value. */
12568 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12569 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12573 gas_assert (!mips_opts.micromips);
12574 /* Must be at least one digit. */
12575 my_getExpression (&imm_expr, s);
12576 check_absolute_expr (ip, &imm_expr);
12578 if ((unsigned long) imm_expr.X_add_number
12579 > (unsigned long) OP_MASK_VECBYTE)
12581 as_bad (_("bad byte vector index (%ld)"),
12582 (long) imm_expr.X_add_number);
12583 imm_expr.X_add_number = 0;
12586 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12587 imm_expr.X_op = O_absent;
12592 gas_assert (!mips_opts.micromips);
12593 my_getExpression (&imm_expr, s);
12594 check_absolute_expr (ip, &imm_expr);
12596 if ((unsigned long) imm_expr.X_add_number
12597 > (unsigned long) OP_MASK_VECALIGN)
12599 as_bad (_("bad byte vector index (%ld)"),
12600 (long) imm_expr.X_add_number);
12601 imm_expr.X_add_number = 0;
12604 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12605 imm_expr.X_op = O_absent;
12609 case 'm': /* Opcode extension character. */
12610 gas_assert (mips_opts.micromips);
12615 if (strncmp (s, "$pc", 3) == 0)
12643 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12644 if (regno == AT && mips_opts.at)
12646 if (mips_opts.at == ATREG)
12647 as_warn (_("Used $at without \".set noat\""));
12649 as_warn (_("Used $%u with \".set at=$%u\""),
12650 regno, mips_opts.at);
12656 gas_assert (args[1] == ',');
12662 gas_assert (args[1] == ',');
12664 continue; /* Nothing to do. */
12670 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12672 if (regno == lastregno)
12675 = _("Source and destination must be different");
12678 if (regno == 31 && lastregno == 0xffffffff)
12681 = _("A destination register must be supplied");
12692 gas_assert (args[1] == ',');
12699 gas_assert (args[1] == ',');
12702 continue; /* Nothing to do. */
12706 /* Make sure regno is the same as lastregno. */
12707 if (c == 't' && regno != lastregno)
12710 /* Make sure regno is the same as destregno. */
12711 if (c == 'x' && regno != destregno)
12714 /* We need to save regno, before regno maps to the
12715 microMIPS register encoding. */
12725 regno = ILLEGAL_REG;
12729 regno = mips32_to_micromips_reg_b_map[regno];
12733 regno = mips32_to_micromips_reg_c_map[regno];
12737 regno = mips32_to_micromips_reg_d_map[regno];
12741 regno = mips32_to_micromips_reg_e_map[regno];
12745 regno = mips32_to_micromips_reg_f_map[regno];
12749 regno = mips32_to_micromips_reg_g_map[regno];
12753 regno = mips32_to_micromips_reg_h_map[regno];
12757 switch (EXTRACT_OPERAND (1, MI, *ip))
12762 else if (regno == 22)
12764 else if (regno == 5)
12766 else if (regno == 6)
12768 else if (regno == 7)
12771 regno = ILLEGAL_REG;
12777 else if (regno == 7)
12780 regno = ILLEGAL_REG;
12787 regno = ILLEGAL_REG;
12791 regno = ILLEGAL_REG;
12797 regno = mips32_to_micromips_reg_l_map[regno];
12801 regno = mips32_to_micromips_reg_m_map[regno];
12805 regno = mips32_to_micromips_reg_n_map[regno];
12809 regno = mips32_to_micromips_reg_q_map[regno];
12814 regno = ILLEGAL_REG;
12819 regno = ILLEGAL_REG;
12824 regno = ILLEGAL_REG;
12827 case 'j': /* Do nothing. */
12837 if (regno == ILLEGAL_REG)
12843 INSERT_OPERAND (1, MB, *ip, regno);
12847 INSERT_OPERAND (1, MC, *ip, regno);
12851 INSERT_OPERAND (1, MD, *ip, regno);
12855 INSERT_OPERAND (1, ME, *ip, regno);
12859 INSERT_OPERAND (1, MF, *ip, regno);
12863 INSERT_OPERAND (1, MG, *ip, regno);
12867 INSERT_OPERAND (1, MH, *ip, regno);
12871 INSERT_OPERAND (1, MI, *ip, regno);
12875 INSERT_OPERAND (1, MJ, *ip, regno);
12879 INSERT_OPERAND (1, ML, *ip, regno);
12883 INSERT_OPERAND (1, MM, *ip, regno);
12887 INSERT_OPERAND (1, MN, *ip, regno);
12891 INSERT_OPERAND (1, MP, *ip, regno);
12895 INSERT_OPERAND (1, MQ, *ip, regno);
12898 case 'a': /* Do nothing. */
12899 case 's': /* Do nothing. */
12900 case 't': /* Do nothing. */
12901 case 'x': /* Do nothing. */
12902 case 'y': /* Do nothing. */
12903 case 'z': /* Do nothing. */
12913 bfd_reloc_code_real_type r[3];
12917 /* Check whether there is only a single bracketed
12918 expression left. If so, it must be the base register
12919 and the constant must be zero. */
12920 if (*s == '(' && strchr (s + 1, '(') == 0)
12922 INSERT_OPERAND (1, IMMA, *ip, 0);
12926 if (my_getSmallExpression (&ep, r, s) > 0
12927 || !expr_const_in_range (&ep, -64, 64, 2))
12930 imm = ep.X_add_number >> 2;
12931 INSERT_OPERAND (1, IMMA, *ip, imm);
12938 bfd_reloc_code_real_type r[3];
12942 if (my_getSmallExpression (&ep, r, s) > 0
12943 || ep.X_op != O_constant)
12946 for (imm = 0; imm < 8; imm++)
12947 if (micromips_imm_b_map[imm] == ep.X_add_number)
12952 INSERT_OPERAND (1, IMMB, *ip, imm);
12959 bfd_reloc_code_real_type r[3];
12963 if (my_getSmallExpression (&ep, r, s) > 0
12964 || ep.X_op != O_constant)
12967 for (imm = 0; imm < 16; imm++)
12968 if (micromips_imm_c_map[imm] == ep.X_add_number)
12973 INSERT_OPERAND (1, IMMC, *ip, imm);
12978 case 'D': /* pc relative offset */
12979 case 'E': /* pc relative offset */
12980 my_getExpression (&offset_expr, s);
12981 if (offset_expr.X_op == O_register)
12984 if (!forced_insn_length)
12985 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12987 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12989 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12995 bfd_reloc_code_real_type r[3];
12999 if (my_getSmallExpression (&ep, r, s) > 0
13000 || !expr_const_in_range (&ep, 0, 16, 0))
13003 imm = ep.X_add_number;
13004 INSERT_OPERAND (1, IMMF, *ip, imm);
13011 bfd_reloc_code_real_type r[3];
13015 /* Check whether there is only a single bracketed
13016 expression left. If so, it must be the base register
13017 and the constant must be zero. */
13018 if (*s == '(' && strchr (s + 1, '(') == 0)
13020 INSERT_OPERAND (1, IMMG, *ip, 0);
13024 if (my_getSmallExpression (&ep, r, s) > 0
13025 || !expr_const_in_range (&ep, -1, 15, 0))
13028 imm = ep.X_add_number & 15;
13029 INSERT_OPERAND (1, IMMG, *ip, imm);
13036 bfd_reloc_code_real_type r[3];
13040 /* Check whether there is only a single bracketed
13041 expression left. If so, it must be the base register
13042 and the constant must be zero. */
13043 if (*s == '(' && strchr (s + 1, '(') == 0)
13045 INSERT_OPERAND (1, IMMH, *ip, 0);
13049 if (my_getSmallExpression (&ep, r, s) > 0
13050 || !expr_const_in_range (&ep, 0, 16, 1))
13053 imm = ep.X_add_number >> 1;
13054 INSERT_OPERAND (1, IMMH, *ip, imm);
13061 bfd_reloc_code_real_type r[3];
13065 if (my_getSmallExpression (&ep, r, s) > 0
13066 || !expr_const_in_range (&ep, -1, 127, 0))
13069 imm = ep.X_add_number & 127;
13070 INSERT_OPERAND (1, IMMI, *ip, imm);
13077 bfd_reloc_code_real_type r[3];
13081 /* Check whether there is only a single bracketed
13082 expression left. If so, it must be the base register
13083 and the constant must be zero. */
13084 if (*s == '(' && strchr (s + 1, '(') == 0)
13086 INSERT_OPERAND (1, IMMJ, *ip, 0);
13090 if (my_getSmallExpression (&ep, r, s) > 0
13091 || !expr_const_in_range (&ep, 0, 16, 2))
13094 imm = ep.X_add_number >> 2;
13095 INSERT_OPERAND (1, IMMJ, *ip, imm);
13102 bfd_reloc_code_real_type r[3];
13106 /* Check whether there is only a single bracketed
13107 expression left. If so, it must be the base register
13108 and the constant must be zero. */
13109 if (*s == '(' && strchr (s + 1, '(') == 0)
13111 INSERT_OPERAND (1, IMML, *ip, 0);
13115 if (my_getSmallExpression (&ep, r, s) > 0
13116 || !expr_const_in_range (&ep, 0, 16, 0))
13119 imm = ep.X_add_number;
13120 INSERT_OPERAND (1, IMML, *ip, imm);
13127 bfd_reloc_code_real_type r[3];
13131 if (my_getSmallExpression (&ep, r, s) > 0
13132 || !expr_const_in_range (&ep, 1, 9, 0))
13135 imm = ep.X_add_number & 7;
13136 INSERT_OPERAND (1, IMMM, *ip, imm);
13141 case 'N': /* Register list for lwm and swm. */
13143 /* A comma-separated list of registers and/or
13144 dash-separated contiguous ranges including
13145 both ra and a set of one or more registers
13146 starting at s0 up to s3 which have to be
13153 and any permutations of these. */
13154 unsigned int reglist;
13157 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13160 if ((reglist & 0xfff1ffff) != 0x80010000)
13163 reglist = (reglist >> 17) & 7;
13165 if ((reglist & -reglist) != reglist)
13168 imm = ffs (reglist) - 1;
13169 INSERT_OPERAND (1, IMMN, *ip, imm);
13173 case 'O': /* sdbbp 4-bit code. */
13175 bfd_reloc_code_real_type r[3];
13179 if (my_getSmallExpression (&ep, r, s) > 0
13180 || !expr_const_in_range (&ep, 0, 16, 0))
13183 imm = ep.X_add_number;
13184 INSERT_OPERAND (1, IMMO, *ip, imm);
13191 bfd_reloc_code_real_type r[3];
13195 if (my_getSmallExpression (&ep, r, s) > 0
13196 || !expr_const_in_range (&ep, 0, 32, 2))
13199 imm = ep.X_add_number >> 2;
13200 INSERT_OPERAND (1, IMMP, *ip, imm);
13207 bfd_reloc_code_real_type r[3];
13211 if (my_getSmallExpression (&ep, r, s) > 0
13212 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13215 imm = ep.X_add_number >> 2;
13216 INSERT_OPERAND (1, IMMQ, *ip, imm);
13223 bfd_reloc_code_real_type r[3];
13227 /* Check whether there is only a single bracketed
13228 expression left. If so, it must be the base register
13229 and the constant must be zero. */
13230 if (*s == '(' && strchr (s + 1, '(') == 0)
13232 INSERT_OPERAND (1, IMMU, *ip, 0);
13236 if (my_getSmallExpression (&ep, r, s) > 0
13237 || !expr_const_in_range (&ep, 0, 32, 2))
13240 imm = ep.X_add_number >> 2;
13241 INSERT_OPERAND (1, IMMU, *ip, imm);
13248 bfd_reloc_code_real_type r[3];
13252 if (my_getSmallExpression (&ep, r, s) > 0
13253 || !expr_const_in_range (&ep, 0, 64, 2))
13256 imm = ep.X_add_number >> 2;
13257 INSERT_OPERAND (1, IMMW, *ip, imm);
13264 bfd_reloc_code_real_type r[3];
13268 if (my_getSmallExpression (&ep, r, s) > 0
13269 || !expr_const_in_range (&ep, -8, 8, 0))
13272 imm = ep.X_add_number;
13273 INSERT_OPERAND (1, IMMX, *ip, imm);
13280 bfd_reloc_code_real_type r[3];
13284 if (my_getSmallExpression (&ep, r, s) > 0
13285 || expr_const_in_range (&ep, -2, 2, 2)
13286 || !expr_const_in_range (&ep, -258, 258, 2))
13289 imm = ep.X_add_number >> 2;
13290 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13291 INSERT_OPERAND (1, IMMY, *ip, imm);
13298 bfd_reloc_code_real_type r[3];
13301 if (my_getSmallExpression (&ep, r, s) > 0
13302 || !expr_const_in_range (&ep, 0, 1, 0))
13309 as_bad (_("Internal error: bad microMIPS opcode "
13310 "(unknown extension operand type `m%c'): %s %s"),
13311 *args, insn->name, insn->args);
13312 /* Further processing is fruitless. */
13317 case 'n': /* Register list for 32-bit lwm and swm. */
13318 gas_assert (mips_opts.micromips);
13320 /* A comma-separated list of registers and/or
13321 dash-separated contiguous ranges including
13322 at least one of ra and a set of one or more
13323 registers starting at s0 up to s7 and then
13324 s8 which have to be consecutive, e.g.:
13332 and any permutations of these. */
13333 unsigned int reglist;
13337 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13340 if ((reglist & 0x3f00ffff) != 0)
13343 ra = (reglist >> 27) & 0x10;
13344 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13346 if ((reglist & -reglist) != reglist)
13349 imm = (ffs (reglist) - 1) | ra;
13350 INSERT_OPERAND (1, RT, *ip, imm);
13351 imm_expr.X_op = O_absent;
13355 case '|': /* 4-bit trap code. */
13356 gas_assert (mips_opts.micromips);
13357 my_getExpression (&imm_expr, s);
13358 check_absolute_expr (ip, &imm_expr);
13359 if ((unsigned long) imm_expr.X_add_number
13360 > MICROMIPSOP_MASK_TRAP)
13361 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13362 (unsigned long) imm_expr.X_add_number,
13363 ip->insn_mo->name);
13364 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13365 imm_expr.X_op = O_absent;
13370 as_bad (_("Bad char = '%c'\n"), *args);
13375 /* Args don't match. */
13377 insn_error = _("Illegal operands");
13378 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13383 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13385 gas_assert (firstinsn);
13386 need_delay_slot_ok = FALSE;
13395 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13397 /* This routine assembles an instruction into its binary format when
13398 assembling for the mips16. As a side effect, it sets one of the
13399 global variables imm_reloc or offset_reloc to the type of relocation
13400 to do if one of the operands is an address expression. It also sets
13401 forced_insn_length to the resulting instruction size in bytes if the
13402 user explicitly requested a small or extended instruction. */
13405 mips16_ip (char *str, struct mips_cl_insn *ip)
13409 struct mips_opcode *insn;
13411 unsigned int regno;
13412 unsigned int lastregno = 0;
13418 forced_insn_length = 0;
13420 for (s = str; ISLOWER (*s); ++s)
13432 if (s[1] == 't' && s[2] == ' ')
13435 forced_insn_length = 2;
13439 else if (s[1] == 'e' && s[2] == ' ')
13442 forced_insn_length = 4;
13446 /* Fall through. */
13448 insn_error = _("unknown opcode");
13452 if (mips_opts.noautoextend && !forced_insn_length)
13453 forced_insn_length = 2;
13455 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13457 insn_error = _("unrecognized opcode");
13466 gas_assert (strcmp (insn->name, str) == 0);
13468 ok = is_opcode_valid_16 (insn);
13471 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13472 && strcmp (insn->name, insn[1].name) == 0)
13481 static char buf[100];
13483 _("Opcode not supported on this processor: %s (%s)"),
13484 mips_cpu_info_from_arch (mips_opts.arch)->name,
13485 mips_cpu_info_from_isa (mips_opts.isa)->name);
13492 create_insn (ip, insn);
13493 imm_expr.X_op = O_absent;
13494 imm_reloc[0] = BFD_RELOC_UNUSED;
13495 imm_reloc[1] = BFD_RELOC_UNUSED;
13496 imm_reloc[2] = BFD_RELOC_UNUSED;
13497 imm2_expr.X_op = O_absent;
13498 offset_expr.X_op = O_absent;
13499 offset_reloc[0] = BFD_RELOC_UNUSED;
13500 offset_reloc[1] = BFD_RELOC_UNUSED;
13501 offset_reloc[2] = BFD_RELOC_UNUSED;
13502 for (args = insn->args; 1; ++args)
13509 /* In this switch statement we call break if we did not find
13510 a match, continue if we did find a match, or return if we
13521 /* Stuff the immediate value in now, if we can. */
13522 if (imm_expr.X_op == O_constant
13523 && *imm_reloc > BFD_RELOC_UNUSED
13524 && insn->pinfo != INSN_MACRO
13525 && calculate_reloc (*offset_reloc,
13526 imm_expr.X_add_number, &value))
13528 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13529 *offset_reloc, value, forced_insn_length,
13531 imm_expr.X_op = O_absent;
13532 *imm_reloc = BFD_RELOC_UNUSED;
13533 *offset_reloc = BFD_RELOC_UNUSED;
13547 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13550 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13566 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13568 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13572 /* Fall through. */
13583 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13585 if (c == 'v' || c == 'w')
13588 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13590 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13601 if (c == 'v' || c == 'w')
13603 regno = mips16_to_32_reg_map[lastregno];
13617 regno = mips32_to_16_reg_map[regno];
13622 regno = ILLEGAL_REG;
13627 regno = ILLEGAL_REG;
13632 regno = ILLEGAL_REG;
13637 if (regno == AT && mips_opts.at)
13639 if (mips_opts.at == ATREG)
13640 as_warn (_("used $at without \".set noat\""));
13642 as_warn (_("used $%u with \".set at=$%u\""),
13643 regno, mips_opts.at);
13651 if (regno == ILLEGAL_REG)
13658 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13662 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13665 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13668 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13674 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13677 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13678 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13688 if (strncmp (s, "$pc", 3) == 0)
13705 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13708 if (imm_expr.X_op != O_constant)
13710 forced_insn_length = 4;
13711 ip->insn_opcode |= MIPS16_EXTEND;
13715 /* We need to relax this instruction. */
13716 *offset_reloc = *imm_reloc;
13717 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13722 *imm_reloc = BFD_RELOC_UNUSED;
13723 /* Fall through. */
13730 my_getExpression (&imm_expr, s);
13731 if (imm_expr.X_op == O_register)
13733 /* What we thought was an expression turned out to
13736 if (s[0] == '(' && args[1] == '(')
13738 /* It looks like the expression was omitted
13739 before a register indirection, which means
13740 that the expression is implicitly zero. We
13741 still set up imm_expr, so that we handle
13742 explicit extensions correctly. */
13743 imm_expr.X_op = O_constant;
13744 imm_expr.X_add_number = 0;
13745 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13752 /* We need to relax this instruction. */
13753 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13762 /* We use offset_reloc rather than imm_reloc for the PC
13763 relative operands. This lets macros with both
13764 immediate and address operands work correctly. */
13765 my_getExpression (&offset_expr, s);
13767 if (offset_expr.X_op == O_register)
13770 /* We need to relax this instruction. */
13771 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13775 case '6': /* break code */
13776 my_getExpression (&imm_expr, s);
13777 check_absolute_expr (ip, &imm_expr);
13778 if ((unsigned long) imm_expr.X_add_number > 63)
13779 as_warn (_("Invalid value for `%s' (%lu)"),
13781 (unsigned long) imm_expr.X_add_number);
13782 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13783 imm_expr.X_op = O_absent;
13787 case 'a': /* 26 bit address */
13788 my_getExpression (&offset_expr, s);
13790 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13791 ip->insn_opcode <<= 16;
13794 case 'l': /* register list for entry macro */
13795 case 'L': /* register list for exit macro */
13805 unsigned int freg, reg1, reg2;
13807 while (*s == ' ' || *s == ',')
13809 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13811 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13815 as_bad (_("can't parse register list"));
13825 if (!reg_lookup (&s, freg ? RTYPE_FPU
13826 : (RTYPE_GP | RTYPE_NUM), ®2))
13828 as_bad (_("invalid register list"));
13832 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13834 mask &= ~ (7 << 3);
13837 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13839 mask &= ~ (7 << 3);
13842 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13843 mask |= (reg2 - 3) << 3;
13844 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13845 mask |= (reg2 - 15) << 1;
13846 else if (reg1 == RA && reg2 == RA)
13850 as_bad (_("invalid register list"));
13854 /* The mask is filled in in the opcode table for the
13855 benefit of the disassembler. We remove it before
13856 applying the actual mask. */
13857 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13858 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13862 case 'm': /* Register list for save insn. */
13863 case 'M': /* Register list for restore insn. */
13865 int opcode = ip->insn_opcode;
13866 int framesz = 0, seen_framesz = 0;
13867 int nargs = 0, statics = 0, sregs = 0;
13871 unsigned int reg1, reg2;
13873 SKIP_SPACE_TABS (s);
13876 SKIP_SPACE_TABS (s);
13878 my_getExpression (&imm_expr, s);
13879 if (imm_expr.X_op == O_constant)
13881 /* Handle the frame size. */
13884 as_bad (_("more than one frame size in list"));
13888 framesz = imm_expr.X_add_number;
13889 imm_expr.X_op = O_absent;
13894 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13896 as_bad (_("can't parse register list"));
13908 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13911 as_bad (_("can't parse register list"));
13916 while (reg1 <= reg2)
13918 if (reg1 >= 4 && reg1 <= 7)
13922 nargs |= 1 << (reg1 - 4);
13924 /* statics $a0-$a3 */
13925 statics |= 1 << (reg1 - 4);
13927 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13930 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13932 else if (reg1 == 31)
13934 /* Add $ra to insn. */
13939 as_bad (_("unexpected register in list"));
13947 /* Encode args/statics combination. */
13948 if (nargs & statics)
13949 as_bad (_("arg/static registers overlap"));
13950 else if (nargs == 0xf)
13951 /* All $a0-$a3 are args. */
13952 opcode |= MIPS16_ALL_ARGS << 16;
13953 else if (statics == 0xf)
13954 /* All $a0-$a3 are statics. */
13955 opcode |= MIPS16_ALL_STATICS << 16;
13958 int narg = 0, nstat = 0;
13960 /* Count arg registers. */
13961 while (nargs & 0x1)
13967 as_bad (_("invalid arg register list"));
13969 /* Count static registers. */
13970 while (statics & 0x8)
13972 statics = (statics << 1) & 0xf;
13976 as_bad (_("invalid static register list"));
13978 /* Encode args/statics. */
13979 opcode |= ((narg << 2) | nstat) << 16;
13982 /* Encode $s0/$s1. */
13983 if (sregs & (1 << 0)) /* $s0 */
13985 if (sregs & (1 << 1)) /* $s1 */
13991 /* Count regs $s2-$s8. */
13999 as_bad (_("invalid static register list"));
14000 /* Encode $s2-$s8. */
14001 opcode |= nsreg << 24;
14004 /* Encode frame size. */
14006 as_bad (_("missing frame size"));
14007 else if ((framesz & 7) != 0 || framesz < 0
14008 || framesz > 0xff * 8)
14009 as_bad (_("invalid frame size"));
14010 else if (framesz != 128 || (opcode >> 16) != 0)
14013 opcode |= (((framesz & 0xf0) << 16)
14014 | (framesz & 0x0f));
14017 /* Finally build the instruction. */
14018 if ((opcode >> 16) != 0 || framesz == 0)
14019 opcode |= MIPS16_EXTEND;
14020 ip->insn_opcode = opcode;
14024 case 'e': /* extend code */
14025 my_getExpression (&imm_expr, s);
14026 check_absolute_expr (ip, &imm_expr);
14027 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14029 as_warn (_("Invalid value for `%s' (%lu)"),
14031 (unsigned long) imm_expr.X_add_number);
14032 imm_expr.X_add_number &= 0x7ff;
14034 ip->insn_opcode |= imm_expr.X_add_number;
14035 imm_expr.X_op = O_absent;
14045 /* Args don't match. */
14046 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14047 strcmp (insn->name, insn[1].name) == 0)
14054 insn_error = _("illegal operands");
14060 /* This structure holds information we know about a mips16 immediate
14063 struct mips16_immed_operand
14065 /* The type code used in the argument string in the opcode table. */
14067 /* The number of bits in the short form of the opcode. */
14069 /* The number of bits in the extended form of the opcode. */
14071 /* The amount by which the short form is shifted when it is used;
14072 for example, the sw instruction has a shift count of 2. */
14074 /* The amount by which the short form is shifted when it is stored
14075 into the instruction code. */
14077 /* Non-zero if the short form is unsigned. */
14079 /* Non-zero if the extended form is unsigned. */
14081 /* Non-zero if the value is PC relative. */
14085 /* The mips16 immediate operand types. */
14087 static const struct mips16_immed_operand mips16_immed_operands[] =
14089 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14090 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14091 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14092 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14093 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14094 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14095 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14096 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14097 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14098 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14099 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14100 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14101 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14102 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14103 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14104 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14105 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14106 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14107 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14108 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14109 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14112 #define MIPS16_NUM_IMMED \
14113 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14115 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14116 NBITS is the number of significant bits in VAL. */
14118 static unsigned long
14119 mips16_immed_extend (offsetT val, unsigned int nbits)
14124 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14127 else if (nbits == 15)
14129 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14134 extval = ((val & 0x1f) << 6) | (val & 0x20);
14137 return (extval << 16) | val;
14140 /* Install immediate value VAL into MIPS16 instruction *INSN,
14141 extending it if necessary. The instruction in *INSN may
14142 already be extended.
14144 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14145 if none. In the former case, VAL is a 16-bit number with no
14146 defined signedness.
14148 TYPE is the type of the immediate field. USER_INSN_LENGTH
14149 is the length that the user requested, or 0 if none. */
14152 mips16_immed (char *file, unsigned int line, int type,
14153 bfd_reloc_code_real_type reloc, offsetT val,
14154 unsigned int user_insn_length, unsigned long *insn)
14156 const struct mips16_immed_operand *op;
14157 int mintiny, maxtiny;
14159 op = mips16_immed_operands;
14160 while (op->type != type)
14163 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14168 if (type == '<' || type == '>' || type == '[' || type == ']')
14171 maxtiny = 1 << op->nbits;
14176 maxtiny = (1 << op->nbits) - 1;
14178 if (reloc != BFD_RELOC_UNUSED)
14183 mintiny = - (1 << (op->nbits - 1));
14184 maxtiny = (1 << (op->nbits - 1)) - 1;
14185 if (reloc != BFD_RELOC_UNUSED)
14186 val = SEXT_16BIT (val);
14189 /* Branch offsets have an implicit 0 in the lowest bit. */
14190 if (type == 'p' || type == 'q')
14193 if ((val & ((1 << op->shift) - 1)) != 0
14194 || val < (mintiny << op->shift)
14195 || val > (maxtiny << op->shift))
14197 /* We need an extended instruction. */
14198 if (user_insn_length == 2)
14199 as_bad_where (file, line, _("invalid unextended operand value"));
14201 *insn |= MIPS16_EXTEND;
14203 else if (user_insn_length == 4)
14205 /* The operand doesn't force an unextended instruction to be extended.
14206 Warn if the user wanted an extended instruction anyway. */
14207 *insn |= MIPS16_EXTEND;
14208 as_warn_where (file, line,
14209 _("extended operand requested but not required"));
14212 if (mips16_opcode_length (*insn) == 2)
14216 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14217 insnval <<= op->op_shift;
14222 long minext, maxext;
14224 if (reloc == BFD_RELOC_UNUSED)
14229 maxext = (1 << op->extbits) - 1;
14233 minext = - (1 << (op->extbits - 1));
14234 maxext = (1 << (op->extbits - 1)) - 1;
14236 if (val < minext || val > maxext)
14237 as_bad_where (file, line,
14238 _("operand value out of range for instruction"));
14241 *insn |= mips16_immed_extend (val, op->extbits);
14245 struct percent_op_match
14248 bfd_reloc_code_real_type reloc;
14251 static const struct percent_op_match mips_percent_op[] =
14253 {"%lo", BFD_RELOC_LO16},
14255 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14256 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14257 {"%call16", BFD_RELOC_MIPS_CALL16},
14258 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14259 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14260 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14261 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14262 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14263 {"%got", BFD_RELOC_MIPS_GOT16},
14264 {"%gp_rel", BFD_RELOC_GPREL16},
14265 {"%half", BFD_RELOC_16},
14266 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14267 {"%higher", BFD_RELOC_MIPS_HIGHER},
14268 {"%neg", BFD_RELOC_MIPS_SUB},
14269 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14270 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14271 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14272 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14273 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14274 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14275 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14277 {"%hi", BFD_RELOC_HI16_S}
14280 static const struct percent_op_match mips16_percent_op[] =
14282 {"%lo", BFD_RELOC_MIPS16_LO16},
14283 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14284 {"%got", BFD_RELOC_MIPS16_GOT16},
14285 {"%call16", BFD_RELOC_MIPS16_CALL16},
14286 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14287 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14288 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14289 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14290 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14291 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14292 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14293 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14297 /* Return true if *STR points to a relocation operator. When returning true,
14298 move *STR over the operator and store its relocation code in *RELOC.
14299 Leave both *STR and *RELOC alone when returning false. */
14302 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14304 const struct percent_op_match *percent_op;
14307 if (mips_opts.mips16)
14309 percent_op = mips16_percent_op;
14310 limit = ARRAY_SIZE (mips16_percent_op);
14314 percent_op = mips_percent_op;
14315 limit = ARRAY_SIZE (mips_percent_op);
14318 for (i = 0; i < limit; i++)
14319 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14321 int len = strlen (percent_op[i].str);
14323 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14326 *str += strlen (percent_op[i].str);
14327 *reloc = percent_op[i].reloc;
14329 /* Check whether the output BFD supports this relocation.
14330 If not, issue an error and fall back on something safe. */
14331 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14333 as_bad (_("relocation %s isn't supported by the current ABI"),
14334 percent_op[i].str);
14335 *reloc = BFD_RELOC_UNUSED;
14343 /* Parse string STR as a 16-bit relocatable operand. Store the
14344 expression in *EP and the relocations in the array starting
14345 at RELOC. Return the number of relocation operators used.
14347 On exit, EXPR_END points to the first character after the expression. */
14350 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14353 bfd_reloc_code_real_type reversed_reloc[3];
14354 size_t reloc_index, i;
14355 int crux_depth, str_depth;
14358 /* Search for the start of the main expression, recoding relocations
14359 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14360 of the main expression and with CRUX_DEPTH containing the number
14361 of open brackets at that point. */
14368 crux_depth = str_depth;
14370 /* Skip over whitespace and brackets, keeping count of the number
14372 while (*str == ' ' || *str == '\t' || *str == '(')
14377 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14378 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14380 my_getExpression (ep, crux);
14383 /* Match every open bracket. */
14384 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14388 if (crux_depth > 0)
14389 as_bad (_("unclosed '('"));
14393 if (reloc_index != 0)
14395 prev_reloc_op_frag = frag_now;
14396 for (i = 0; i < reloc_index; i++)
14397 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14400 return reloc_index;
14404 my_getExpression (expressionS *ep, char *str)
14408 save_in = input_line_pointer;
14409 input_line_pointer = str;
14411 expr_end = input_line_pointer;
14412 input_line_pointer = save_in;
14416 md_atof (int type, char *litP, int *sizeP)
14418 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14422 md_number_to_chars (char *buf, valueT val, int n)
14424 if (target_big_endian)
14425 number_to_chars_bigendian (buf, val, n);
14427 number_to_chars_littleendian (buf, val, n);
14431 static int support_64bit_objects(void)
14433 const char **list, **l;
14436 list = bfd_target_list ();
14437 for (l = list; *l != NULL; l++)
14438 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14439 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14441 yes = (*l != NULL);
14445 #endif /* OBJ_ELF */
14447 const char *md_shortopts = "O::g::G:";
14451 OPTION_MARCH = OPTION_MD_BASE,
14473 OPTION_NO_SMARTMIPS,
14477 OPTION_NO_MICROMIPS,
14480 OPTION_COMPAT_ARCH_BASE,
14489 OPTION_M7000_HILO_FIX,
14490 OPTION_MNO_7000_HILO_FIX,
14493 OPTION_FIX_LOONGSON2F_JUMP,
14494 OPTION_NO_FIX_LOONGSON2F_JUMP,
14495 OPTION_FIX_LOONGSON2F_NOP,
14496 OPTION_NO_FIX_LOONGSON2F_NOP,
14498 OPTION_NO_FIX_VR4120,
14500 OPTION_NO_FIX_VR4130,
14501 OPTION_FIX_CN63XXP1,
14502 OPTION_NO_FIX_CN63XXP1,
14509 OPTION_CONSTRUCT_FLOATS,
14510 OPTION_NO_CONSTRUCT_FLOATS,
14513 OPTION_RELAX_BRANCH,
14514 OPTION_NO_RELAX_BRANCH,
14521 OPTION_SINGLE_FLOAT,
14522 OPTION_DOUBLE_FLOAT,
14525 OPTION_CALL_SHARED,
14526 OPTION_CALL_NONPIC,
14536 OPTION_MVXWORKS_PIC,
14537 #endif /* OBJ_ELF */
14541 struct option md_longopts[] =
14543 /* Options which specify architecture. */
14544 {"march", required_argument, NULL, OPTION_MARCH},
14545 {"mtune", required_argument, NULL, OPTION_MTUNE},
14546 {"mips0", no_argument, NULL, OPTION_MIPS1},
14547 {"mips1", no_argument, NULL, OPTION_MIPS1},
14548 {"mips2", no_argument, NULL, OPTION_MIPS2},
14549 {"mips3", no_argument, NULL, OPTION_MIPS3},
14550 {"mips4", no_argument, NULL, OPTION_MIPS4},
14551 {"mips5", no_argument, NULL, OPTION_MIPS5},
14552 {"mips32", no_argument, NULL, OPTION_MIPS32},
14553 {"mips64", no_argument, NULL, OPTION_MIPS64},
14554 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14555 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14557 /* Options which specify Application Specific Extensions (ASEs). */
14558 {"mips16", no_argument, NULL, OPTION_MIPS16},
14559 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14560 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14561 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14562 {"mdmx", no_argument, NULL, OPTION_MDMX},
14563 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14564 {"mdsp", no_argument, NULL, OPTION_DSP},
14565 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14566 {"mmt", no_argument, NULL, OPTION_MT},
14567 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14568 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14569 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14570 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14571 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14572 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14573 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14574 {"mmcu", no_argument, NULL, OPTION_MCU},
14575 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14577 /* Old-style architecture options. Don't add more of these. */
14578 {"m4650", no_argument, NULL, OPTION_M4650},
14579 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14580 {"m4010", no_argument, NULL, OPTION_M4010},
14581 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14582 {"m4100", no_argument, NULL, OPTION_M4100},
14583 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14584 {"m3900", no_argument, NULL, OPTION_M3900},
14585 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14587 /* Options which enable bug fixes. */
14588 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14589 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14590 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14591 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14592 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14593 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14594 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14595 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14596 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14597 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14598 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14599 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14600 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14601 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14602 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14604 /* Miscellaneous options. */
14605 {"trap", no_argument, NULL, OPTION_TRAP},
14606 {"no-break", no_argument, NULL, OPTION_TRAP},
14607 {"break", no_argument, NULL, OPTION_BREAK},
14608 {"no-trap", no_argument, NULL, OPTION_BREAK},
14609 {"EB", no_argument, NULL, OPTION_EB},
14610 {"EL", no_argument, NULL, OPTION_EL},
14611 {"mfp32", no_argument, NULL, OPTION_FP32},
14612 {"mgp32", no_argument, NULL, OPTION_GP32},
14613 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14614 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14615 {"mfp64", no_argument, NULL, OPTION_FP64},
14616 {"mgp64", no_argument, NULL, OPTION_GP64},
14617 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14618 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14619 {"mshared", no_argument, NULL, OPTION_MSHARED},
14620 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14621 {"msym32", no_argument, NULL, OPTION_MSYM32},
14622 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14623 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14624 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14625 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14626 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14628 /* Strictly speaking this next option is ELF specific,
14629 but we allow it for other ports as well in order to
14630 make testing easier. */
14631 {"32", no_argument, NULL, OPTION_32},
14633 /* ELF-specific options. */
14635 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14636 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14637 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14638 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14639 {"xgot", no_argument, NULL, OPTION_XGOT},
14640 {"mabi", required_argument, NULL, OPTION_MABI},
14641 {"n32", no_argument, NULL, OPTION_N32},
14642 {"64", no_argument, NULL, OPTION_64},
14643 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14644 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14645 {"mpdr", no_argument, NULL, OPTION_PDR},
14646 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14647 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14648 #endif /* OBJ_ELF */
14650 {NULL, no_argument, NULL, 0}
14652 size_t md_longopts_size = sizeof (md_longopts);
14654 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14655 NEW_VALUE. Warn if another value was already specified. Note:
14656 we have to defer parsing the -march and -mtune arguments in order
14657 to handle 'from-abi' correctly, since the ABI might be specified
14658 in a later argument. */
14661 mips_set_option_string (const char **string_ptr, const char *new_value)
14663 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14664 as_warn (_("A different %s was already specified, is now %s"),
14665 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14668 *string_ptr = new_value;
14672 md_parse_option (int c, char *arg)
14676 case OPTION_CONSTRUCT_FLOATS:
14677 mips_disable_float_construction = 0;
14680 case OPTION_NO_CONSTRUCT_FLOATS:
14681 mips_disable_float_construction = 1;
14693 target_big_endian = 1;
14697 target_big_endian = 0;
14703 else if (arg[0] == '0')
14705 else if (arg[0] == '1')
14715 mips_debug = atoi (arg);
14719 file_mips_isa = ISA_MIPS1;
14723 file_mips_isa = ISA_MIPS2;
14727 file_mips_isa = ISA_MIPS3;
14731 file_mips_isa = ISA_MIPS4;
14735 file_mips_isa = ISA_MIPS5;
14738 case OPTION_MIPS32:
14739 file_mips_isa = ISA_MIPS32;
14742 case OPTION_MIPS32R2:
14743 file_mips_isa = ISA_MIPS32R2;
14746 case OPTION_MIPS64R2:
14747 file_mips_isa = ISA_MIPS64R2;
14750 case OPTION_MIPS64:
14751 file_mips_isa = ISA_MIPS64;
14755 mips_set_option_string (&mips_tune_string, arg);
14759 mips_set_option_string (&mips_arch_string, arg);
14763 mips_set_option_string (&mips_arch_string, "4650");
14764 mips_set_option_string (&mips_tune_string, "4650");
14767 case OPTION_NO_M4650:
14771 mips_set_option_string (&mips_arch_string, "4010");
14772 mips_set_option_string (&mips_tune_string, "4010");
14775 case OPTION_NO_M4010:
14779 mips_set_option_string (&mips_arch_string, "4100");
14780 mips_set_option_string (&mips_tune_string, "4100");
14783 case OPTION_NO_M4100:
14787 mips_set_option_string (&mips_arch_string, "3900");
14788 mips_set_option_string (&mips_tune_string, "3900");
14791 case OPTION_NO_M3900:
14795 mips_opts.ase_mdmx = 1;
14798 case OPTION_NO_MDMX:
14799 mips_opts.ase_mdmx = 0;
14803 mips_opts.ase_dsp = 1;
14804 mips_opts.ase_dspr2 = 0;
14807 case OPTION_NO_DSP:
14808 mips_opts.ase_dsp = 0;
14809 mips_opts.ase_dspr2 = 0;
14813 mips_opts.ase_dspr2 = 1;
14814 mips_opts.ase_dsp = 1;
14817 case OPTION_NO_DSPR2:
14818 mips_opts.ase_dspr2 = 0;
14819 mips_opts.ase_dsp = 0;
14823 mips_opts.ase_mt = 1;
14827 mips_opts.ase_mt = 0;
14831 mips_opts.ase_mcu = 1;
14834 case OPTION_NO_MCU:
14835 mips_opts.ase_mcu = 0;
14838 case OPTION_MICROMIPS:
14839 if (mips_opts.mips16 == 1)
14841 as_bad (_("-mmicromips cannot be used with -mips16"));
14844 mips_opts.micromips = 1;
14845 mips_no_prev_insn ();
14848 case OPTION_NO_MICROMIPS:
14849 mips_opts.micromips = 0;
14850 mips_no_prev_insn ();
14853 case OPTION_MIPS16:
14854 if (mips_opts.micromips == 1)
14856 as_bad (_("-mips16 cannot be used with -micromips"));
14859 mips_opts.mips16 = 1;
14860 mips_no_prev_insn ();
14863 case OPTION_NO_MIPS16:
14864 mips_opts.mips16 = 0;
14865 mips_no_prev_insn ();
14868 case OPTION_MIPS3D:
14869 mips_opts.ase_mips3d = 1;
14872 case OPTION_NO_MIPS3D:
14873 mips_opts.ase_mips3d = 0;
14876 case OPTION_SMARTMIPS:
14877 mips_opts.ase_smartmips = 1;
14880 case OPTION_NO_SMARTMIPS:
14881 mips_opts.ase_smartmips = 0;
14884 case OPTION_FIX_24K:
14888 case OPTION_NO_FIX_24K:
14892 case OPTION_FIX_LOONGSON2F_JUMP:
14893 mips_fix_loongson2f_jump = TRUE;
14896 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14897 mips_fix_loongson2f_jump = FALSE;
14900 case OPTION_FIX_LOONGSON2F_NOP:
14901 mips_fix_loongson2f_nop = TRUE;
14904 case OPTION_NO_FIX_LOONGSON2F_NOP:
14905 mips_fix_loongson2f_nop = FALSE;
14908 case OPTION_FIX_VR4120:
14909 mips_fix_vr4120 = 1;
14912 case OPTION_NO_FIX_VR4120:
14913 mips_fix_vr4120 = 0;
14916 case OPTION_FIX_VR4130:
14917 mips_fix_vr4130 = 1;
14920 case OPTION_NO_FIX_VR4130:
14921 mips_fix_vr4130 = 0;
14924 case OPTION_FIX_CN63XXP1:
14925 mips_fix_cn63xxp1 = TRUE;
14928 case OPTION_NO_FIX_CN63XXP1:
14929 mips_fix_cn63xxp1 = FALSE;
14932 case OPTION_RELAX_BRANCH:
14933 mips_relax_branch = 1;
14936 case OPTION_NO_RELAX_BRANCH:
14937 mips_relax_branch = 0;
14940 case OPTION_MSHARED:
14941 mips_in_shared = TRUE;
14944 case OPTION_MNO_SHARED:
14945 mips_in_shared = FALSE;
14948 case OPTION_MSYM32:
14949 mips_opts.sym32 = TRUE;
14952 case OPTION_MNO_SYM32:
14953 mips_opts.sym32 = FALSE;
14957 /* When generating ELF code, we permit -KPIC and -call_shared to
14958 select SVR4_PIC, and -non_shared to select no PIC. This is
14959 intended to be compatible with Irix 5. */
14960 case OPTION_CALL_SHARED:
14963 as_bad (_("-call_shared is supported only for ELF format"));
14966 mips_pic = SVR4_PIC;
14967 mips_abicalls = TRUE;
14970 case OPTION_CALL_NONPIC:
14973 as_bad (_("-call_nonpic is supported only for ELF format"));
14977 mips_abicalls = TRUE;
14980 case OPTION_NON_SHARED:
14983 as_bad (_("-non_shared is supported only for ELF format"));
14987 mips_abicalls = FALSE;
14990 /* The -xgot option tells the assembler to use 32 bit offsets
14991 when accessing the got in SVR4_PIC mode. It is for Irix
14996 #endif /* OBJ_ELF */
14999 g_switch_value = atoi (arg);
15003 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15007 mips_abi = O32_ABI;
15008 /* We silently ignore -32 for non-ELF targets. This greatly
15009 simplifies the construction of the MIPS GAS test cases. */
15016 as_bad (_("-n32 is supported for ELF format only"));
15019 mips_abi = N32_ABI;
15025 as_bad (_("-64 is supported for ELF format only"));
15028 mips_abi = N64_ABI;
15029 if (!support_64bit_objects())
15030 as_fatal (_("No compiled in support for 64 bit object file format"));
15032 #endif /* OBJ_ELF */
15035 file_mips_gp32 = 1;
15039 file_mips_gp32 = 0;
15043 file_mips_fp32 = 1;
15047 file_mips_fp32 = 0;
15050 case OPTION_SINGLE_FLOAT:
15051 file_mips_single_float = 1;
15054 case OPTION_DOUBLE_FLOAT:
15055 file_mips_single_float = 0;
15058 case OPTION_SOFT_FLOAT:
15059 file_mips_soft_float = 1;
15062 case OPTION_HARD_FLOAT:
15063 file_mips_soft_float = 0;
15070 as_bad (_("-mabi is supported for ELF format only"));
15073 if (strcmp (arg, "32") == 0)
15074 mips_abi = O32_ABI;
15075 else if (strcmp (arg, "o64") == 0)
15076 mips_abi = O64_ABI;
15077 else if (strcmp (arg, "n32") == 0)
15078 mips_abi = N32_ABI;
15079 else if (strcmp (arg, "64") == 0)
15081 mips_abi = N64_ABI;
15082 if (! support_64bit_objects())
15083 as_fatal (_("No compiled in support for 64 bit object file "
15086 else if (strcmp (arg, "eabi") == 0)
15087 mips_abi = EABI_ABI;
15090 as_fatal (_("invalid abi -mabi=%s"), arg);
15094 #endif /* OBJ_ELF */
15096 case OPTION_M7000_HILO_FIX:
15097 mips_7000_hilo_fix = TRUE;
15100 case OPTION_MNO_7000_HILO_FIX:
15101 mips_7000_hilo_fix = FALSE;
15105 case OPTION_MDEBUG:
15106 mips_flag_mdebug = TRUE;
15109 case OPTION_NO_MDEBUG:
15110 mips_flag_mdebug = FALSE;
15114 mips_flag_pdr = TRUE;
15117 case OPTION_NO_PDR:
15118 mips_flag_pdr = FALSE;
15121 case OPTION_MVXWORKS_PIC:
15122 mips_pic = VXWORKS_PIC;
15124 #endif /* OBJ_ELF */
15130 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15135 /* Set up globals to generate code for the ISA or processor
15136 described by INFO. */
15139 mips_set_architecture (const struct mips_cpu_info *info)
15143 file_mips_arch = info->cpu;
15144 mips_opts.arch = info->cpu;
15145 mips_opts.isa = info->isa;
15150 /* Likewise for tuning. */
15153 mips_set_tune (const struct mips_cpu_info *info)
15156 mips_tune = info->cpu;
15161 mips_after_parse_args (void)
15163 const struct mips_cpu_info *arch_info = 0;
15164 const struct mips_cpu_info *tune_info = 0;
15166 /* GP relative stuff not working for PE */
15167 if (strncmp (TARGET_OS, "pe", 2) == 0)
15169 if (g_switch_seen && g_switch_value != 0)
15170 as_bad (_("-G not supported in this configuration."));
15171 g_switch_value = 0;
15174 if (mips_abi == NO_ABI)
15175 mips_abi = MIPS_DEFAULT_ABI;
15177 /* The following code determines the architecture and register size.
15178 Similar code was added to GCC 3.3 (see override_options() in
15179 config/mips/mips.c). The GAS and GCC code should be kept in sync
15180 as much as possible. */
15182 if (mips_arch_string != 0)
15183 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15185 if (file_mips_isa != ISA_UNKNOWN)
15187 /* Handle -mipsN. At this point, file_mips_isa contains the
15188 ISA level specified by -mipsN, while arch_info->isa contains
15189 the -march selection (if any). */
15190 if (arch_info != 0)
15192 /* -march takes precedence over -mipsN, since it is more descriptive.
15193 There's no harm in specifying both as long as the ISA levels
15195 if (file_mips_isa != arch_info->isa)
15196 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15197 mips_cpu_info_from_isa (file_mips_isa)->name,
15198 mips_cpu_info_from_isa (arch_info->isa)->name);
15201 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15204 if (arch_info == 0)
15206 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15207 gas_assert (arch_info);
15210 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15211 as_bad (_("-march=%s is not compatible with the selected ABI"),
15214 mips_set_architecture (arch_info);
15216 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15217 if (mips_tune_string != 0)
15218 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15220 if (tune_info == 0)
15221 mips_set_tune (arch_info);
15223 mips_set_tune (tune_info);
15225 if (file_mips_gp32 >= 0)
15227 /* The user specified the size of the integer registers. Make sure
15228 it agrees with the ABI and ISA. */
15229 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15230 as_bad (_("-mgp64 used with a 32-bit processor"));
15231 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15232 as_bad (_("-mgp32 used with a 64-bit ABI"));
15233 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15234 as_bad (_("-mgp64 used with a 32-bit ABI"));
15238 /* Infer the integer register size from the ABI and processor.
15239 Restrict ourselves to 32-bit registers if that's all the
15240 processor has, or if the ABI cannot handle 64-bit registers. */
15241 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15242 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15245 switch (file_mips_fp32)
15249 /* No user specified float register size.
15250 ??? GAS treats single-float processors as though they had 64-bit
15251 float registers (although it complains when double-precision
15252 instructions are used). As things stand, saying they have 32-bit
15253 registers would lead to spurious "register must be even" messages.
15254 So here we assume float registers are never smaller than the
15256 if (file_mips_gp32 == 0)
15257 /* 64-bit integer registers implies 64-bit float registers. */
15258 file_mips_fp32 = 0;
15259 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15260 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15261 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15262 file_mips_fp32 = 0;
15264 /* 32-bit float registers. */
15265 file_mips_fp32 = 1;
15268 /* The user specified the size of the float registers. Check if it
15269 agrees with the ABI and ISA. */
15271 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15272 as_bad (_("-mfp64 used with a 32-bit fpu"));
15273 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15274 && !ISA_HAS_MXHC1 (mips_opts.isa))
15275 as_warn (_("-mfp64 used with a 32-bit ABI"));
15278 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15279 as_warn (_("-mfp32 used with a 64-bit ABI"));
15283 /* End of GCC-shared inference code. */
15285 /* This flag is set when we have a 64-bit capable CPU but use only
15286 32-bit wide registers. Note that EABI does not use it. */
15287 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15288 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15289 || mips_abi == O32_ABI))
15290 mips_32bitmode = 1;
15292 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15293 as_bad (_("trap exception not supported at ISA 1"));
15295 /* If the selected architecture includes support for ASEs, enable
15296 generation of code for them. */
15297 if (mips_opts.mips16 == -1)
15298 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15299 if (mips_opts.micromips == -1)
15300 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15301 if (mips_opts.ase_mips3d == -1)
15302 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15303 && file_mips_fp32 == 0) ? 1 : 0;
15304 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15305 as_bad (_("-mfp32 used with -mips3d"));
15307 if (mips_opts.ase_mdmx == -1)
15308 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15309 && file_mips_fp32 == 0) ? 1 : 0;
15310 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15311 as_bad (_("-mfp32 used with -mdmx"));
15313 if (mips_opts.ase_smartmips == -1)
15314 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15315 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15316 as_warn (_("%s ISA does not support SmartMIPS"),
15317 mips_cpu_info_from_isa (mips_opts.isa)->name);
15319 if (mips_opts.ase_dsp == -1)
15320 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15321 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15322 as_warn (_("%s ISA does not support DSP ASE"),
15323 mips_cpu_info_from_isa (mips_opts.isa)->name);
15325 if (mips_opts.ase_dspr2 == -1)
15327 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15328 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15330 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15331 as_warn (_("%s ISA does not support DSP R2 ASE"),
15332 mips_cpu_info_from_isa (mips_opts.isa)->name);
15334 if (mips_opts.ase_mt == -1)
15335 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15336 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15337 as_warn (_("%s ISA does not support MT ASE"),
15338 mips_cpu_info_from_isa (mips_opts.isa)->name);
15340 if (mips_opts.ase_mcu == -1)
15341 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15342 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15343 as_warn (_("%s ISA does not support MCU ASE"),
15344 mips_cpu_info_from_isa (mips_opts.isa)->name);
15346 file_mips_isa = mips_opts.isa;
15347 file_ase_mips3d = mips_opts.ase_mips3d;
15348 file_ase_mdmx = mips_opts.ase_mdmx;
15349 file_ase_smartmips = mips_opts.ase_smartmips;
15350 file_ase_dsp = mips_opts.ase_dsp;
15351 file_ase_dspr2 = mips_opts.ase_dspr2;
15352 file_ase_mt = mips_opts.ase_mt;
15353 mips_opts.gp32 = file_mips_gp32;
15354 mips_opts.fp32 = file_mips_fp32;
15355 mips_opts.soft_float = file_mips_soft_float;
15356 mips_opts.single_float = file_mips_single_float;
15358 if (mips_flag_mdebug < 0)
15360 #ifdef OBJ_MAYBE_ECOFF
15361 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15362 mips_flag_mdebug = 1;
15364 #endif /* OBJ_MAYBE_ECOFF */
15365 mips_flag_mdebug = 0;
15370 mips_init_after_args (void)
15372 /* initialize opcodes */
15373 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15374 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15378 md_pcrel_from (fixS *fixP)
15380 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15381 switch (fixP->fx_r_type)
15383 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15384 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15385 /* Return the address of the delay slot. */
15388 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15389 case BFD_RELOC_MICROMIPS_JMP:
15390 case BFD_RELOC_16_PCREL_S2:
15391 case BFD_RELOC_MIPS_JMP:
15392 /* Return the address of the delay slot. */
15396 /* We have no relocation type for PC relative MIPS16 instructions. */
15397 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15398 as_bad_where (fixP->fx_file, fixP->fx_line,
15399 _("PC relative MIPS16 instruction references a different section"));
15404 /* This is called before the symbol table is processed. In order to
15405 work with gcc when using mips-tfile, we must keep all local labels.
15406 However, in other cases, we want to discard them. If we were
15407 called with -g, but we didn't see any debugging information, it may
15408 mean that gcc is smuggling debugging information through to
15409 mips-tfile, in which case we must generate all local labels. */
15412 mips_frob_file_before_adjust (void)
15414 #ifndef NO_ECOFF_DEBUGGING
15415 if (ECOFF_DEBUGGING
15417 && ! ecoff_debugging_seen)
15418 flag_keep_locals = 1;
15422 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15423 the corresponding LO16 reloc. This is called before md_apply_fix and
15424 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15425 relocation operators.
15427 For our purposes, a %lo() expression matches a %got() or %hi()
15430 (a) it refers to the same symbol; and
15431 (b) the offset applied in the %lo() expression is no lower than
15432 the offset applied in the %got() or %hi().
15434 (b) allows us to cope with code like:
15437 lh $4,%lo(foo+2)($4)
15439 ...which is legal on RELA targets, and has a well-defined behaviour
15440 if the user knows that adding 2 to "foo" will not induce a carry to
15443 When several %lo()s match a particular %got() or %hi(), we use the
15444 following rules to distinguish them:
15446 (1) %lo()s with smaller offsets are a better match than %lo()s with
15449 (2) %lo()s with no matching %got() or %hi() are better than those
15450 that already have a matching %got() or %hi().
15452 (3) later %lo()s are better than earlier %lo()s.
15454 These rules are applied in order.
15456 (1) means, among other things, that %lo()s with identical offsets are
15457 chosen if they exist.
15459 (2) means that we won't associate several high-part relocations with
15460 the same low-part relocation unless there's no alternative. Having
15461 several high parts for the same low part is a GNU extension; this rule
15462 allows careful users to avoid it.
15464 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15465 with the last high-part relocation being at the front of the list.
15466 It therefore makes sense to choose the last matching low-part
15467 relocation, all other things being equal. It's also easier
15468 to code that way. */
15471 mips_frob_file (void)
15473 struct mips_hi_fixup *l;
15474 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15476 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15478 segment_info_type *seginfo;
15479 bfd_boolean matched_lo_p;
15480 fixS **hi_pos, **lo_pos, **pos;
15482 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15484 /* If a GOT16 relocation turns out to be against a global symbol,
15485 there isn't supposed to be a matching LO. Ignore %gots against
15486 constants; we'll report an error for those later. */
15487 if (got16_reloc_p (l->fixp->fx_r_type)
15488 && !(l->fixp->fx_addsy
15489 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15492 /* Check quickly whether the next fixup happens to be a matching %lo. */
15493 if (fixup_has_matching_lo_p (l->fixp))
15496 seginfo = seg_info (l->seg);
15498 /* Set HI_POS to the position of this relocation in the chain.
15499 Set LO_POS to the position of the chosen low-part relocation.
15500 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15501 relocation that matches an immediately-preceding high-part
15505 matched_lo_p = FALSE;
15506 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15508 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15510 if (*pos == l->fixp)
15513 if ((*pos)->fx_r_type == looking_for_rtype
15514 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15515 && (*pos)->fx_offset >= l->fixp->fx_offset
15517 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15519 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15522 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15523 && fixup_has_matching_lo_p (*pos));
15526 /* If we found a match, remove the high-part relocation from its
15527 current position and insert it before the low-part relocation.
15528 Make the offsets match so that fixup_has_matching_lo_p()
15531 We don't warn about unmatched high-part relocations since some
15532 versions of gcc have been known to emit dead "lui ...%hi(...)"
15534 if (lo_pos != NULL)
15536 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15537 if (l->fixp->fx_next != *lo_pos)
15539 *hi_pos = l->fixp->fx_next;
15540 l->fixp->fx_next = *lo_pos;
15548 mips_force_relocation (fixS *fixp)
15550 if (generic_force_reloc (fixp))
15553 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15554 so that the linker relaxation can update targets. */
15555 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15556 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15557 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15563 /* Read the instruction associated with RELOC from BUF. */
15565 static unsigned int
15566 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15568 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15569 return read_compressed_insn (buf, 4);
15571 return read_insn (buf);
15574 /* Write instruction INSN to BUF, given that it has been relocated
15578 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15579 unsigned long insn)
15581 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15582 write_compressed_insn (buf, insn, 4);
15584 write_insn (buf, insn);
15587 /* Apply a fixup to the object file. */
15590 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15593 unsigned long insn;
15594 reloc_howto_type *howto;
15596 /* We ignore generic BFD relocations we don't know about. */
15597 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15601 gas_assert (fixP->fx_size == 2
15602 || fixP->fx_size == 4
15603 || fixP->fx_r_type == BFD_RELOC_16
15604 || fixP->fx_r_type == BFD_RELOC_64
15605 || fixP->fx_r_type == BFD_RELOC_CTOR
15606 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15607 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15608 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15609 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15610 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15612 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15614 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15615 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15616 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15617 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15619 /* Don't treat parts of a composite relocation as done. There are two
15622 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15623 should nevertheless be emitted if the first part is.
15625 (2) In normal usage, composite relocations are never assembly-time
15626 constants. The easiest way of dealing with the pathological
15627 exceptions is to generate a relocation against STN_UNDEF and
15628 leave everything up to the linker. */
15629 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15632 switch (fixP->fx_r_type)
15634 case BFD_RELOC_MIPS_TLS_GD:
15635 case BFD_RELOC_MIPS_TLS_LDM:
15636 case BFD_RELOC_MIPS_TLS_DTPREL32:
15637 case BFD_RELOC_MIPS_TLS_DTPREL64:
15638 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15639 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15640 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15641 case BFD_RELOC_MIPS_TLS_TPREL32:
15642 case BFD_RELOC_MIPS_TLS_TPREL64:
15643 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15644 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15645 case BFD_RELOC_MICROMIPS_TLS_GD:
15646 case BFD_RELOC_MICROMIPS_TLS_LDM:
15647 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15648 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15649 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15650 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15651 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15652 case BFD_RELOC_MIPS16_TLS_GD:
15653 case BFD_RELOC_MIPS16_TLS_LDM:
15654 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15655 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15656 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15657 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15658 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15659 if (!fixP->fx_addsy)
15661 as_bad_where (fixP->fx_file, fixP->fx_line,
15662 _("TLS relocation against a constant"));
15665 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15668 case BFD_RELOC_MIPS_JMP:
15669 case BFD_RELOC_MIPS_SHIFT5:
15670 case BFD_RELOC_MIPS_SHIFT6:
15671 case BFD_RELOC_MIPS_GOT_DISP:
15672 case BFD_RELOC_MIPS_GOT_PAGE:
15673 case BFD_RELOC_MIPS_GOT_OFST:
15674 case BFD_RELOC_MIPS_SUB:
15675 case BFD_RELOC_MIPS_INSERT_A:
15676 case BFD_RELOC_MIPS_INSERT_B:
15677 case BFD_RELOC_MIPS_DELETE:
15678 case BFD_RELOC_MIPS_HIGHEST:
15679 case BFD_RELOC_MIPS_HIGHER:
15680 case BFD_RELOC_MIPS_SCN_DISP:
15681 case BFD_RELOC_MIPS_REL16:
15682 case BFD_RELOC_MIPS_RELGOT:
15683 case BFD_RELOC_MIPS_JALR:
15684 case BFD_RELOC_HI16:
15685 case BFD_RELOC_HI16_S:
15686 case BFD_RELOC_LO16:
15687 case BFD_RELOC_GPREL16:
15688 case BFD_RELOC_MIPS_LITERAL:
15689 case BFD_RELOC_MIPS_CALL16:
15690 case BFD_RELOC_MIPS_GOT16:
15691 case BFD_RELOC_GPREL32:
15692 case BFD_RELOC_MIPS_GOT_HI16:
15693 case BFD_RELOC_MIPS_GOT_LO16:
15694 case BFD_RELOC_MIPS_CALL_HI16:
15695 case BFD_RELOC_MIPS_CALL_LO16:
15696 case BFD_RELOC_MIPS16_GPREL:
15697 case BFD_RELOC_MIPS16_GOT16:
15698 case BFD_RELOC_MIPS16_CALL16:
15699 case BFD_RELOC_MIPS16_HI16:
15700 case BFD_RELOC_MIPS16_HI16_S:
15701 case BFD_RELOC_MIPS16_LO16:
15702 case BFD_RELOC_MIPS16_JMP:
15703 case BFD_RELOC_MICROMIPS_JMP:
15704 case BFD_RELOC_MICROMIPS_GOT_DISP:
15705 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15706 case BFD_RELOC_MICROMIPS_GOT_OFST:
15707 case BFD_RELOC_MICROMIPS_SUB:
15708 case BFD_RELOC_MICROMIPS_HIGHEST:
15709 case BFD_RELOC_MICROMIPS_HIGHER:
15710 case BFD_RELOC_MICROMIPS_SCN_DISP:
15711 case BFD_RELOC_MICROMIPS_JALR:
15712 case BFD_RELOC_MICROMIPS_HI16:
15713 case BFD_RELOC_MICROMIPS_HI16_S:
15714 case BFD_RELOC_MICROMIPS_LO16:
15715 case BFD_RELOC_MICROMIPS_GPREL16:
15716 case BFD_RELOC_MICROMIPS_LITERAL:
15717 case BFD_RELOC_MICROMIPS_CALL16:
15718 case BFD_RELOC_MICROMIPS_GOT16:
15719 case BFD_RELOC_MICROMIPS_GOT_HI16:
15720 case BFD_RELOC_MICROMIPS_GOT_LO16:
15721 case BFD_RELOC_MICROMIPS_CALL_HI16:
15722 case BFD_RELOC_MICROMIPS_CALL_LO16:
15727 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15729 insn = read_reloc_insn (buf, fixP->fx_r_type);
15730 if (mips16_reloc_p (fixP->fx_r_type))
15731 insn |= mips16_immed_extend (value, 16);
15733 insn |= (value & 0xffff);
15734 write_reloc_insn (buf, fixP->fx_r_type, insn);
15737 as_bad_where (fixP->fx_file, fixP->fx_line,
15738 _("Unsupported constant in relocation"));
15743 /* This is handled like BFD_RELOC_32, but we output a sign
15744 extended value if we are only 32 bits. */
15747 if (8 <= sizeof (valueT))
15748 md_number_to_chars (buf, *valP, 8);
15753 if ((*valP & 0x80000000) != 0)
15757 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15758 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15763 case BFD_RELOC_RVA:
15766 /* If we are deleting this reloc entry, we must fill in the
15767 value now. This can happen if we have a .word which is not
15768 resolved when it appears but is later defined. */
15770 md_number_to_chars (buf, *valP, fixP->fx_size);
15773 case BFD_RELOC_16_PCREL_S2:
15774 if ((*valP & 0x3) != 0)
15775 as_bad_where (fixP->fx_file, fixP->fx_line,
15776 _("Branch to misaligned address (%lx)"), (long) *valP);
15778 /* We need to save the bits in the instruction since fixup_segment()
15779 might be deleting the relocation entry (i.e., a branch within
15780 the current segment). */
15781 if (! fixP->fx_done)
15784 /* Update old instruction data. */
15785 insn = read_insn (buf);
15787 if (*valP + 0x20000 <= 0x3ffff)
15789 insn |= (*valP >> 2) & 0xffff;
15790 write_insn (buf, insn);
15792 else if (mips_pic == NO_PIC
15794 && fixP->fx_frag->fr_address >= text_section->vma
15795 && (fixP->fx_frag->fr_address
15796 < text_section->vma + bfd_get_section_size (text_section))
15797 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15798 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15799 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15801 /* The branch offset is too large. If this is an
15802 unconditional branch, and we are not generating PIC code,
15803 we can convert it to an absolute jump instruction. */
15804 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15805 insn = 0x0c000000; /* jal */
15807 insn = 0x08000000; /* j */
15808 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15810 fixP->fx_addsy = section_symbol (text_section);
15811 *valP += md_pcrel_from (fixP);
15812 write_insn (buf, insn);
15816 /* If we got here, we have branch-relaxation disabled,
15817 and there's nothing we can do to fix this instruction
15818 without turning it into a longer sequence. */
15819 as_bad_where (fixP->fx_file, fixP->fx_line,
15820 _("Branch out of range"));
15824 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15825 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15826 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15827 /* We adjust the offset back to even. */
15828 if ((*valP & 0x1) != 0)
15831 if (! fixP->fx_done)
15834 /* Should never visit here, because we keep the relocation. */
15838 case BFD_RELOC_VTABLE_INHERIT:
15841 && !S_IS_DEFINED (fixP->fx_addsy)
15842 && !S_IS_WEAK (fixP->fx_addsy))
15843 S_SET_WEAK (fixP->fx_addsy);
15846 case BFD_RELOC_VTABLE_ENTRY:
15854 /* Remember value for tc_gen_reloc. */
15855 fixP->fx_addnumber = *valP;
15865 name = input_line_pointer;
15866 c = get_symbol_end ();
15867 p = (symbolS *) symbol_find_or_make (name);
15868 *input_line_pointer = c;
15872 /* Align the current frag to a given power of two. If a particular
15873 fill byte should be used, FILL points to an integer that contains
15874 that byte, otherwise FILL is null.
15876 This function used to have the comment:
15878 The MIPS assembler also automatically adjusts any preceding label.
15880 The implementation therefore applied the adjustment to a maximum of
15881 one label. However, other label adjustments are applied to batches
15882 of labels, and adjusting just one caused problems when new labels
15883 were added for the sake of debugging or unwind information.
15884 We therefore adjust all preceding labels (given as LABELS) instead. */
15887 mips_align (int to, int *fill, struct insn_label_list *labels)
15889 mips_emit_delays ();
15890 mips_record_compressed_mode ();
15891 if (fill == NULL && subseg_text_p (now_seg))
15892 frag_align_code (to, 0);
15894 frag_align (to, fill ? *fill : 0, 0);
15895 record_alignment (now_seg, to);
15896 mips_move_labels (labels, FALSE);
15899 /* Align to a given power of two. .align 0 turns off the automatic
15900 alignment used by the data creating pseudo-ops. */
15903 s_align (int x ATTRIBUTE_UNUSED)
15905 int temp, fill_value, *fill_ptr;
15906 long max_alignment = 28;
15908 /* o Note that the assembler pulls down any immediately preceding label
15909 to the aligned address.
15910 o It's not documented but auto alignment is reinstated by
15911 a .align pseudo instruction.
15912 o Note also that after auto alignment is turned off the mips assembler
15913 issues an error on attempt to assemble an improperly aligned data item.
15916 temp = get_absolute_expression ();
15917 if (temp > max_alignment)
15918 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15921 as_warn (_("Alignment negative: 0 assumed."));
15924 if (*input_line_pointer == ',')
15926 ++input_line_pointer;
15927 fill_value = get_absolute_expression ();
15928 fill_ptr = &fill_value;
15934 segment_info_type *si = seg_info (now_seg);
15935 struct insn_label_list *l = si->label_list;
15936 /* Auto alignment should be switched on by next section change. */
15938 mips_align (temp, fill_ptr, l);
15945 demand_empty_rest_of_line ();
15949 s_change_sec (int sec)
15954 /* The ELF backend needs to know that we are changing sections, so
15955 that .previous works correctly. We could do something like check
15956 for an obj_section_change_hook macro, but that might be confusing
15957 as it would not be appropriate to use it in the section changing
15958 functions in read.c, since obj-elf.c intercepts those. FIXME:
15959 This should be cleaner, somehow. */
15961 obj_elf_section_change_hook ();
15964 mips_emit_delays ();
15975 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15976 demand_empty_rest_of_line ();
15980 seg = subseg_new (RDATA_SECTION_NAME,
15981 (subsegT) get_absolute_expression ());
15984 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15985 | SEC_READONLY | SEC_RELOC
15987 if (strncmp (TARGET_OS, "elf", 3) != 0)
15988 record_alignment (seg, 4);
15990 demand_empty_rest_of_line ();
15994 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15997 bfd_set_section_flags (stdoutput, seg,
15998 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15999 if (strncmp (TARGET_OS, "elf", 3) != 0)
16000 record_alignment (seg, 4);
16002 demand_empty_rest_of_line ();
16006 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16009 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16010 if (strncmp (TARGET_OS, "elf", 3) != 0)
16011 record_alignment (seg, 4);
16013 demand_empty_rest_of_line ();
16021 s_change_section (int ignore ATTRIBUTE_UNUSED)
16024 char *section_name;
16029 int section_entry_size;
16030 int section_alignment;
16035 section_name = input_line_pointer;
16036 c = get_symbol_end ();
16038 next_c = *(input_line_pointer + 1);
16040 /* Do we have .section Name<,"flags">? */
16041 if (c != ',' || (c == ',' && next_c == '"'))
16043 /* just after name is now '\0'. */
16044 *input_line_pointer = c;
16045 input_line_pointer = section_name;
16046 obj_elf_section (ignore);
16049 input_line_pointer++;
16051 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16053 section_type = get_absolute_expression ();
16056 if (*input_line_pointer++ == ',')
16057 section_flag = get_absolute_expression ();
16060 if (*input_line_pointer++ == ',')
16061 section_entry_size = get_absolute_expression ();
16063 section_entry_size = 0;
16064 if (*input_line_pointer++ == ',')
16065 section_alignment = get_absolute_expression ();
16067 section_alignment = 0;
16068 /* FIXME: really ignore? */
16069 (void) section_alignment;
16071 section_name = xstrdup (section_name);
16073 /* When using the generic form of .section (as implemented by obj-elf.c),
16074 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16075 traditionally had to fall back on the more common @progbits instead.
16077 There's nothing really harmful in this, since bfd will correct
16078 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16079 means that, for backwards compatibility, the special_section entries
16080 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16082 Even so, we shouldn't force users of the MIPS .section syntax to
16083 incorrectly label the sections as SHT_PROGBITS. The best compromise
16084 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16085 generic type-checking code. */
16086 if (section_type == SHT_MIPS_DWARF)
16087 section_type = SHT_PROGBITS;
16089 obj_elf_change_section (section_name, section_type, section_flag,
16090 section_entry_size, 0, 0, 0);
16092 if (now_seg->name != section_name)
16093 free (section_name);
16094 #endif /* OBJ_ELF */
16098 mips_enable_auto_align (void)
16104 s_cons (int log_size)
16106 segment_info_type *si = seg_info (now_seg);
16107 struct insn_label_list *l = si->label_list;
16109 mips_emit_delays ();
16110 if (log_size > 0 && auto_align)
16111 mips_align (log_size, 0, l);
16112 cons (1 << log_size);
16113 mips_clear_insn_labels ();
16117 s_float_cons (int type)
16119 segment_info_type *si = seg_info (now_seg);
16120 struct insn_label_list *l = si->label_list;
16122 mips_emit_delays ();
16127 mips_align (3, 0, l);
16129 mips_align (2, 0, l);
16133 mips_clear_insn_labels ();
16136 /* Handle .globl. We need to override it because on Irix 5 you are
16139 where foo is an undefined symbol, to mean that foo should be
16140 considered to be the address of a function. */
16143 s_mips_globl (int x ATTRIBUTE_UNUSED)
16152 name = input_line_pointer;
16153 c = get_symbol_end ();
16154 symbolP = symbol_find_or_make (name);
16155 S_SET_EXTERNAL (symbolP);
16157 *input_line_pointer = c;
16158 SKIP_WHITESPACE ();
16160 /* On Irix 5, every global symbol that is not explicitly labelled as
16161 being a function is apparently labelled as being an object. */
16164 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16165 && (*input_line_pointer != ','))
16170 secname = input_line_pointer;
16171 c = get_symbol_end ();
16172 sec = bfd_get_section_by_name (stdoutput, secname);
16174 as_bad (_("%s: no such section"), secname);
16175 *input_line_pointer = c;
16177 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16178 flag = BSF_FUNCTION;
16181 symbol_get_bfdsym (symbolP)->flags |= flag;
16183 c = *input_line_pointer;
16186 input_line_pointer++;
16187 SKIP_WHITESPACE ();
16188 if (is_end_of_line[(unsigned char) *input_line_pointer])
16194 demand_empty_rest_of_line ();
16198 s_option (int x ATTRIBUTE_UNUSED)
16203 opt = input_line_pointer;
16204 c = get_symbol_end ();
16208 /* FIXME: What does this mean? */
16210 else if (strncmp (opt, "pic", 3) == 0)
16214 i = atoi (opt + 3);
16219 mips_pic = SVR4_PIC;
16220 mips_abicalls = TRUE;
16223 as_bad (_(".option pic%d not supported"), i);
16225 if (mips_pic == SVR4_PIC)
16227 if (g_switch_seen && g_switch_value != 0)
16228 as_warn (_("-G may not be used with SVR4 PIC code"));
16229 g_switch_value = 0;
16230 bfd_set_gp_size (stdoutput, 0);
16234 as_warn (_("Unrecognized option \"%s\""), opt);
16236 *input_line_pointer = c;
16237 demand_empty_rest_of_line ();
16240 /* This structure is used to hold a stack of .set values. */
16242 struct mips_option_stack
16244 struct mips_option_stack *next;
16245 struct mips_set_options options;
16248 static struct mips_option_stack *mips_opts_stack;
16250 /* Handle the .set pseudo-op. */
16253 s_mipsset (int x ATTRIBUTE_UNUSED)
16255 char *name = input_line_pointer, ch;
16257 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16258 ++input_line_pointer;
16259 ch = *input_line_pointer;
16260 *input_line_pointer = '\0';
16262 if (strcmp (name, "reorder") == 0)
16264 if (mips_opts.noreorder)
16267 else if (strcmp (name, "noreorder") == 0)
16269 if (!mips_opts.noreorder)
16270 start_noreorder ();
16272 else if (strncmp (name, "at=", 3) == 0)
16274 char *s = name + 3;
16276 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16277 as_bad (_("Unrecognized register name `%s'"), s);
16279 else if (strcmp (name, "at") == 0)
16281 mips_opts.at = ATREG;
16283 else if (strcmp (name, "noat") == 0)
16285 mips_opts.at = ZERO;
16287 else if (strcmp (name, "macro") == 0)
16289 mips_opts.warn_about_macros = 0;
16291 else if (strcmp (name, "nomacro") == 0)
16293 if (mips_opts.noreorder == 0)
16294 as_bad (_("`noreorder' must be set before `nomacro'"));
16295 mips_opts.warn_about_macros = 1;
16297 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16299 mips_opts.nomove = 0;
16301 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16303 mips_opts.nomove = 1;
16305 else if (strcmp (name, "bopt") == 0)
16307 mips_opts.nobopt = 0;
16309 else if (strcmp (name, "nobopt") == 0)
16311 mips_opts.nobopt = 1;
16313 else if (strcmp (name, "gp=default") == 0)
16314 mips_opts.gp32 = file_mips_gp32;
16315 else if (strcmp (name, "gp=32") == 0)
16316 mips_opts.gp32 = 1;
16317 else if (strcmp (name, "gp=64") == 0)
16319 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16320 as_warn (_("%s isa does not support 64-bit registers"),
16321 mips_cpu_info_from_isa (mips_opts.isa)->name);
16322 mips_opts.gp32 = 0;
16324 else if (strcmp (name, "fp=default") == 0)
16325 mips_opts.fp32 = file_mips_fp32;
16326 else if (strcmp (name, "fp=32") == 0)
16327 mips_opts.fp32 = 1;
16328 else if (strcmp (name, "fp=64") == 0)
16330 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16331 as_warn (_("%s isa does not support 64-bit floating point registers"),
16332 mips_cpu_info_from_isa (mips_opts.isa)->name);
16333 mips_opts.fp32 = 0;
16335 else if (strcmp (name, "softfloat") == 0)
16336 mips_opts.soft_float = 1;
16337 else if (strcmp (name, "hardfloat") == 0)
16338 mips_opts.soft_float = 0;
16339 else if (strcmp (name, "singlefloat") == 0)
16340 mips_opts.single_float = 1;
16341 else if (strcmp (name, "doublefloat") == 0)
16342 mips_opts.single_float = 0;
16343 else if (strcmp (name, "mips16") == 0
16344 || strcmp (name, "MIPS-16") == 0)
16346 if (mips_opts.micromips == 1)
16347 as_fatal (_("`mips16' cannot be used with `micromips'"));
16348 mips_opts.mips16 = 1;
16350 else if (strcmp (name, "nomips16") == 0
16351 || strcmp (name, "noMIPS-16") == 0)
16352 mips_opts.mips16 = 0;
16353 else if (strcmp (name, "micromips") == 0)
16355 if (mips_opts.mips16 == 1)
16356 as_fatal (_("`micromips' cannot be used with `mips16'"));
16357 mips_opts.micromips = 1;
16359 else if (strcmp (name, "nomicromips") == 0)
16360 mips_opts.micromips = 0;
16361 else if (strcmp (name, "smartmips") == 0)
16363 if (!ISA_SUPPORTS_SMARTMIPS)
16364 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16365 mips_cpu_info_from_isa (mips_opts.isa)->name);
16366 mips_opts.ase_smartmips = 1;
16368 else if (strcmp (name, "nosmartmips") == 0)
16369 mips_opts.ase_smartmips = 0;
16370 else if (strcmp (name, "mips3d") == 0)
16371 mips_opts.ase_mips3d = 1;
16372 else if (strcmp (name, "nomips3d") == 0)
16373 mips_opts.ase_mips3d = 0;
16374 else if (strcmp (name, "mdmx") == 0)
16375 mips_opts.ase_mdmx = 1;
16376 else if (strcmp (name, "nomdmx") == 0)
16377 mips_opts.ase_mdmx = 0;
16378 else if (strcmp (name, "dsp") == 0)
16380 if (!ISA_SUPPORTS_DSP_ASE)
16381 as_warn (_("%s ISA does not support DSP ASE"),
16382 mips_cpu_info_from_isa (mips_opts.isa)->name);
16383 mips_opts.ase_dsp = 1;
16384 mips_opts.ase_dspr2 = 0;
16386 else if (strcmp (name, "nodsp") == 0)
16388 mips_opts.ase_dsp = 0;
16389 mips_opts.ase_dspr2 = 0;
16391 else if (strcmp (name, "dspr2") == 0)
16393 if (!ISA_SUPPORTS_DSPR2_ASE)
16394 as_warn (_("%s ISA does not support DSP R2 ASE"),
16395 mips_cpu_info_from_isa (mips_opts.isa)->name);
16396 mips_opts.ase_dspr2 = 1;
16397 mips_opts.ase_dsp = 1;
16399 else if (strcmp (name, "nodspr2") == 0)
16401 mips_opts.ase_dspr2 = 0;
16402 mips_opts.ase_dsp = 0;
16404 else if (strcmp (name, "mt") == 0)
16406 if (!ISA_SUPPORTS_MT_ASE)
16407 as_warn (_("%s ISA does not support MT ASE"),
16408 mips_cpu_info_from_isa (mips_opts.isa)->name);
16409 mips_opts.ase_mt = 1;
16411 else if (strcmp (name, "nomt") == 0)
16412 mips_opts.ase_mt = 0;
16413 else if (strcmp (name, "mcu") == 0)
16414 mips_opts.ase_mcu = 1;
16415 else if (strcmp (name, "nomcu") == 0)
16416 mips_opts.ase_mcu = 0;
16417 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16421 /* Permit the user to change the ISA and architecture on the fly.
16422 Needless to say, misuse can cause serious problems. */
16423 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16426 mips_opts.isa = file_mips_isa;
16427 mips_opts.arch = file_mips_arch;
16429 else if (strncmp (name, "arch=", 5) == 0)
16431 const struct mips_cpu_info *p;
16433 p = mips_parse_cpu("internal use", name + 5);
16435 as_bad (_("unknown architecture %s"), name + 5);
16438 mips_opts.arch = p->cpu;
16439 mips_opts.isa = p->isa;
16442 else if (strncmp (name, "mips", 4) == 0)
16444 const struct mips_cpu_info *p;
16446 p = mips_parse_cpu("internal use", name);
16448 as_bad (_("unknown ISA level %s"), name + 4);
16451 mips_opts.arch = p->cpu;
16452 mips_opts.isa = p->isa;
16456 as_bad (_("unknown ISA or architecture %s"), name);
16458 switch (mips_opts.isa)
16466 mips_opts.gp32 = 1;
16467 mips_opts.fp32 = 1;
16474 mips_opts.gp32 = 0;
16475 if (mips_opts.arch == CPU_R5900)
16477 mips_opts.fp32 = 1;
16481 mips_opts.fp32 = 0;
16485 as_bad (_("unknown ISA level %s"), name + 4);
16490 mips_opts.gp32 = file_mips_gp32;
16491 mips_opts.fp32 = file_mips_fp32;
16494 else if (strcmp (name, "autoextend") == 0)
16495 mips_opts.noautoextend = 0;
16496 else if (strcmp (name, "noautoextend") == 0)
16497 mips_opts.noautoextend = 1;
16498 else if (strcmp (name, "push") == 0)
16500 struct mips_option_stack *s;
16502 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16503 s->next = mips_opts_stack;
16504 s->options = mips_opts;
16505 mips_opts_stack = s;
16507 else if (strcmp (name, "pop") == 0)
16509 struct mips_option_stack *s;
16511 s = mips_opts_stack;
16513 as_bad (_(".set pop with no .set push"));
16516 /* If we're changing the reorder mode we need to handle
16517 delay slots correctly. */
16518 if (s->options.noreorder && ! mips_opts.noreorder)
16519 start_noreorder ();
16520 else if (! s->options.noreorder && mips_opts.noreorder)
16523 mips_opts = s->options;
16524 mips_opts_stack = s->next;
16528 else if (strcmp (name, "sym32") == 0)
16529 mips_opts.sym32 = TRUE;
16530 else if (strcmp (name, "nosym32") == 0)
16531 mips_opts.sym32 = FALSE;
16532 else if (strchr (name, ','))
16534 /* Generic ".set" directive; use the generic handler. */
16535 *input_line_pointer = ch;
16536 input_line_pointer = name;
16542 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16544 *input_line_pointer = ch;
16545 demand_empty_rest_of_line ();
16548 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16549 .option pic2. It means to generate SVR4 PIC calls. */
16552 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16554 mips_pic = SVR4_PIC;
16555 mips_abicalls = TRUE;
16557 if (g_switch_seen && g_switch_value != 0)
16558 as_warn (_("-G may not be used with SVR4 PIC code"));
16559 g_switch_value = 0;
16561 bfd_set_gp_size (stdoutput, 0);
16562 demand_empty_rest_of_line ();
16565 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16566 PIC code. It sets the $gp register for the function based on the
16567 function address, which is in the register named in the argument.
16568 This uses a relocation against _gp_disp, which is handled specially
16569 by the linker. The result is:
16570 lui $gp,%hi(_gp_disp)
16571 addiu $gp,$gp,%lo(_gp_disp)
16572 addu $gp,$gp,.cpload argument
16573 The .cpload argument is normally $25 == $t9.
16575 The -mno-shared option changes this to:
16576 lui $gp,%hi(__gnu_local_gp)
16577 addiu $gp,$gp,%lo(__gnu_local_gp)
16578 and the argument is ignored. This saves an instruction, but the
16579 resulting code is not position independent; it uses an absolute
16580 address for __gnu_local_gp. Thus code assembled with -mno-shared
16581 can go into an ordinary executable, but not into a shared library. */
16584 s_cpload (int ignore ATTRIBUTE_UNUSED)
16590 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16591 .cpload is ignored. */
16592 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16598 if (mips_opts.mips16)
16600 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16601 ignore_rest_of_line ();
16605 /* .cpload should be in a .set noreorder section. */
16606 if (mips_opts.noreorder == 0)
16607 as_warn (_(".cpload not in noreorder section"));
16609 reg = tc_get_register (0);
16611 /* If we need to produce a 64-bit address, we are better off using
16612 the default instruction sequence. */
16613 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16615 ex.X_op = O_symbol;
16616 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16618 ex.X_op_symbol = NULL;
16619 ex.X_add_number = 0;
16621 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16622 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16624 mips_mark_labels ();
16625 mips_assembling_insn = TRUE;
16628 macro_build_lui (&ex, mips_gp_register);
16629 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16630 mips_gp_register, BFD_RELOC_LO16);
16632 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16633 mips_gp_register, reg);
16636 mips_assembling_insn = FALSE;
16637 demand_empty_rest_of_line ();
16640 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16641 .cpsetup $reg1, offset|$reg2, label
16643 If offset is given, this results in:
16644 sd $gp, offset($sp)
16645 lui $gp, %hi(%neg(%gp_rel(label)))
16646 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16647 daddu $gp, $gp, $reg1
16649 If $reg2 is given, this results in:
16650 daddu $reg2, $gp, $0
16651 lui $gp, %hi(%neg(%gp_rel(label)))
16652 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16653 daddu $gp, $gp, $reg1
16654 $reg1 is normally $25 == $t9.
16656 The -mno-shared option replaces the last three instructions with
16658 addiu $gp,$gp,%lo(_gp) */
16661 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16663 expressionS ex_off;
16664 expressionS ex_sym;
16667 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16668 We also need NewABI support. */
16669 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16675 if (mips_opts.mips16)
16677 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16678 ignore_rest_of_line ();
16682 reg1 = tc_get_register (0);
16683 SKIP_WHITESPACE ();
16684 if (*input_line_pointer != ',')
16686 as_bad (_("missing argument separator ',' for .cpsetup"));
16690 ++input_line_pointer;
16691 SKIP_WHITESPACE ();
16692 if (*input_line_pointer == '$')
16694 mips_cpreturn_register = tc_get_register (0);
16695 mips_cpreturn_offset = -1;
16699 mips_cpreturn_offset = get_absolute_expression ();
16700 mips_cpreturn_register = -1;
16702 SKIP_WHITESPACE ();
16703 if (*input_line_pointer != ',')
16705 as_bad (_("missing argument separator ',' for .cpsetup"));
16709 ++input_line_pointer;
16710 SKIP_WHITESPACE ();
16711 expression (&ex_sym);
16713 mips_mark_labels ();
16714 mips_assembling_insn = TRUE;
16717 if (mips_cpreturn_register == -1)
16719 ex_off.X_op = O_constant;
16720 ex_off.X_add_symbol = NULL;
16721 ex_off.X_op_symbol = NULL;
16722 ex_off.X_add_number = mips_cpreturn_offset;
16724 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16725 BFD_RELOC_LO16, SP);
16728 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16729 mips_gp_register, 0);
16731 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16733 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16734 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16737 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16738 mips_gp_register, -1, BFD_RELOC_GPREL16,
16739 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16741 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16742 mips_gp_register, reg1);
16748 ex.X_op = O_symbol;
16749 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16750 ex.X_op_symbol = NULL;
16751 ex.X_add_number = 0;
16753 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16754 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16756 macro_build_lui (&ex, mips_gp_register);
16757 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16758 mips_gp_register, BFD_RELOC_LO16);
16763 mips_assembling_insn = FALSE;
16764 demand_empty_rest_of_line ();
16768 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16770 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16771 .cplocal is ignored. */
16772 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16778 if (mips_opts.mips16)
16780 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16781 ignore_rest_of_line ();
16785 mips_gp_register = tc_get_register (0);
16786 demand_empty_rest_of_line ();
16789 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16790 offset from $sp. The offset is remembered, and after making a PIC
16791 call $gp is restored from that location. */
16794 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16798 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16799 .cprestore is ignored. */
16800 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16806 if (mips_opts.mips16)
16808 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16809 ignore_rest_of_line ();
16813 mips_cprestore_offset = get_absolute_expression ();
16814 mips_cprestore_valid = 1;
16816 ex.X_op = O_constant;
16817 ex.X_add_symbol = NULL;
16818 ex.X_op_symbol = NULL;
16819 ex.X_add_number = mips_cprestore_offset;
16821 mips_mark_labels ();
16822 mips_assembling_insn = TRUE;
16825 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16826 SP, HAVE_64BIT_ADDRESSES);
16829 mips_assembling_insn = FALSE;
16830 demand_empty_rest_of_line ();
16833 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16834 was given in the preceding .cpsetup, it results in:
16835 ld $gp, offset($sp)
16837 If a register $reg2 was given there, it results in:
16838 daddu $gp, $reg2, $0 */
16841 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16845 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16846 We also need NewABI support. */
16847 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16853 if (mips_opts.mips16)
16855 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16856 ignore_rest_of_line ();
16860 mips_mark_labels ();
16861 mips_assembling_insn = TRUE;
16864 if (mips_cpreturn_register == -1)
16866 ex.X_op = O_constant;
16867 ex.X_add_symbol = NULL;
16868 ex.X_op_symbol = NULL;
16869 ex.X_add_number = mips_cpreturn_offset;
16871 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16874 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16875 mips_cpreturn_register, 0);
16878 mips_assembling_insn = FALSE;
16879 demand_empty_rest_of_line ();
16882 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16883 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16884 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16885 debug information or MIPS16 TLS. */
16888 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16889 bfd_reloc_code_real_type rtype)
16896 if (ex.X_op != O_symbol)
16898 as_bad (_("Unsupported use of %s"), dirstr);
16899 ignore_rest_of_line ();
16902 p = frag_more (bytes);
16903 md_number_to_chars (p, 0, bytes);
16904 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16905 demand_empty_rest_of_line ();
16906 mips_clear_insn_labels ();
16909 /* Handle .dtprelword. */
16912 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16914 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16917 /* Handle .dtpreldword. */
16920 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16922 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16925 /* Handle .tprelword. */
16928 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16930 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16933 /* Handle .tpreldword. */
16936 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16938 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16941 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16942 code. It sets the offset to use in gp_rel relocations. */
16945 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16947 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16948 We also need NewABI support. */
16949 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16955 mips_gprel_offset = get_absolute_expression ();
16957 demand_empty_rest_of_line ();
16960 /* Handle the .gpword pseudo-op. This is used when generating PIC
16961 code. It generates a 32 bit GP relative reloc. */
16964 s_gpword (int ignore ATTRIBUTE_UNUSED)
16966 segment_info_type *si;
16967 struct insn_label_list *l;
16971 /* When not generating PIC code, this is treated as .word. */
16972 if (mips_pic != SVR4_PIC)
16978 si = seg_info (now_seg);
16979 l = si->label_list;
16980 mips_emit_delays ();
16982 mips_align (2, 0, l);
16985 mips_clear_insn_labels ();
16987 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16989 as_bad (_("Unsupported use of .gpword"));
16990 ignore_rest_of_line ();
16994 md_number_to_chars (p, 0, 4);
16995 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16996 BFD_RELOC_GPREL32);
16998 demand_empty_rest_of_line ();
17002 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17004 segment_info_type *si;
17005 struct insn_label_list *l;
17009 /* When not generating PIC code, this is treated as .dword. */
17010 if (mips_pic != SVR4_PIC)
17016 si = seg_info (now_seg);
17017 l = si->label_list;
17018 mips_emit_delays ();
17020 mips_align (3, 0, l);
17023 mips_clear_insn_labels ();
17025 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17027 as_bad (_("Unsupported use of .gpdword"));
17028 ignore_rest_of_line ();
17032 md_number_to_chars (p, 0, 8);
17033 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17034 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17036 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17037 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17038 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17040 demand_empty_rest_of_line ();
17043 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17044 tables in SVR4 PIC code. */
17047 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17051 /* This is ignored when not generating SVR4 PIC code. */
17052 if (mips_pic != SVR4_PIC)
17058 mips_mark_labels ();
17059 mips_assembling_insn = TRUE;
17061 /* Add $gp to the register named as an argument. */
17063 reg = tc_get_register (0);
17064 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17067 mips_assembling_insn = FALSE;
17068 demand_empty_rest_of_line ();
17071 /* Handle the .insn pseudo-op. This marks instruction labels in
17072 mips16/micromips mode. This permits the linker to handle them specially,
17073 such as generating jalx instructions when needed. We also make
17074 them odd for the duration of the assembly, in order to generate the
17075 right sort of code. We will make them even in the adjust_symtab
17076 routine, while leaving them marked. This is convenient for the
17077 debugger and the disassembler. The linker knows to make them odd
17081 s_insn (int ignore ATTRIBUTE_UNUSED)
17083 mips_mark_labels ();
17085 demand_empty_rest_of_line ();
17088 /* Handle a .stabn directive. We need these in order to mark a label
17089 as being a mips16 text label correctly. Sometimes the compiler
17090 will emit a label, followed by a .stabn, and then switch sections.
17091 If the label and .stabn are in mips16 mode, then the label is
17092 really a mips16 text label. */
17095 s_mips_stab (int type)
17098 mips_mark_labels ();
17103 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17106 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17113 name = input_line_pointer;
17114 c = get_symbol_end ();
17115 symbolP = symbol_find_or_make (name);
17116 S_SET_WEAK (symbolP);
17117 *input_line_pointer = c;
17119 SKIP_WHITESPACE ();
17121 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17123 if (S_IS_DEFINED (symbolP))
17125 as_bad (_("ignoring attempt to redefine symbol %s"),
17126 S_GET_NAME (symbolP));
17127 ignore_rest_of_line ();
17131 if (*input_line_pointer == ',')
17133 ++input_line_pointer;
17134 SKIP_WHITESPACE ();
17138 if (exp.X_op != O_symbol)
17140 as_bad (_("bad .weakext directive"));
17141 ignore_rest_of_line ();
17144 symbol_set_value_expression (symbolP, &exp);
17147 demand_empty_rest_of_line ();
17150 /* Parse a register string into a number. Called from the ECOFF code
17151 to parse .frame. The argument is non-zero if this is the frame
17152 register, so that we can record it in mips_frame_reg. */
17155 tc_get_register (int frame)
17159 SKIP_WHITESPACE ();
17160 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17164 mips_frame_reg = reg != 0 ? reg : SP;
17165 mips_frame_reg_valid = 1;
17166 mips_cprestore_valid = 0;
17172 md_section_align (asection *seg, valueT addr)
17174 int align = bfd_get_section_alignment (stdoutput, seg);
17178 /* We don't need to align ELF sections to the full alignment.
17179 However, Irix 5 may prefer that we align them at least to a 16
17180 byte boundary. We don't bother to align the sections if we
17181 are targeted for an embedded system. */
17182 if (strncmp (TARGET_OS, "elf", 3) == 0)
17188 return ((addr + (1 << align) - 1) & (-1 << align));
17191 /* Utility routine, called from above as well. If called while the
17192 input file is still being read, it's only an approximation. (For
17193 example, a symbol may later become defined which appeared to be
17194 undefined earlier.) */
17197 nopic_need_relax (symbolS *sym, int before_relaxing)
17202 if (g_switch_value > 0)
17204 const char *symname;
17207 /* Find out whether this symbol can be referenced off the $gp
17208 register. It can be if it is smaller than the -G size or if
17209 it is in the .sdata or .sbss section. Certain symbols can
17210 not be referenced off the $gp, although it appears as though
17212 symname = S_GET_NAME (sym);
17213 if (symname != (const char *) NULL
17214 && (strcmp (symname, "eprol") == 0
17215 || strcmp (symname, "etext") == 0
17216 || strcmp (symname, "_gp") == 0
17217 || strcmp (symname, "edata") == 0
17218 || strcmp (symname, "_fbss") == 0
17219 || strcmp (symname, "_fdata") == 0
17220 || strcmp (symname, "_ftext") == 0
17221 || strcmp (symname, "end") == 0
17222 || strcmp (symname, "_gp_disp") == 0))
17224 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17226 #ifndef NO_ECOFF_DEBUGGING
17227 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17228 && (symbol_get_obj (sym)->ecoff_extern_size
17229 <= g_switch_value))
17231 /* We must defer this decision until after the whole
17232 file has been read, since there might be a .extern
17233 after the first use of this symbol. */
17234 || (before_relaxing
17235 #ifndef NO_ECOFF_DEBUGGING
17236 && symbol_get_obj (sym)->ecoff_extern_size == 0
17238 && S_GET_VALUE (sym) == 0)
17239 || (S_GET_VALUE (sym) != 0
17240 && S_GET_VALUE (sym) <= g_switch_value)))
17244 const char *segname;
17246 segname = segment_name (S_GET_SEGMENT (sym));
17247 gas_assert (strcmp (segname, ".lit8") != 0
17248 && strcmp (segname, ".lit4") != 0);
17249 change = (strcmp (segname, ".sdata") != 0
17250 && strcmp (segname, ".sbss") != 0
17251 && strncmp (segname, ".sdata.", 7) != 0
17252 && strncmp (segname, ".sbss.", 6) != 0
17253 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17254 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17259 /* We are not optimizing for the $gp register. */
17264 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17267 pic_need_relax (symbolS *sym, asection *segtype)
17271 /* Handle the case of a symbol equated to another symbol. */
17272 while (symbol_equated_reloc_p (sym))
17276 /* It's possible to get a loop here in a badly written program. */
17277 n = symbol_get_value_expression (sym)->X_add_symbol;
17283 if (symbol_section_p (sym))
17286 symsec = S_GET_SEGMENT (sym);
17288 /* This must duplicate the test in adjust_reloc_syms. */
17289 return (!bfd_is_und_section (symsec)
17290 && !bfd_is_abs_section (symsec)
17291 && !bfd_is_com_section (symsec)
17292 && !s_is_linkonce (sym, segtype)
17294 /* A global or weak symbol is treated as external. */
17295 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17301 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17302 extended opcode. SEC is the section the frag is in. */
17305 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17308 const struct mips16_immed_operand *op;
17310 int mintiny, maxtiny;
17314 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17316 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17319 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17320 op = mips16_immed_operands;
17321 while (op->type != type)
17324 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17329 if (type == '<' || type == '>' || type == '[' || type == ']')
17332 maxtiny = 1 << op->nbits;
17337 maxtiny = (1 << op->nbits) - 1;
17342 mintiny = - (1 << (op->nbits - 1));
17343 maxtiny = (1 << (op->nbits - 1)) - 1;
17346 sym_frag = symbol_get_frag (fragp->fr_symbol);
17347 val = S_GET_VALUE (fragp->fr_symbol);
17348 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17354 /* We won't have the section when we are called from
17355 mips_relax_frag. However, we will always have been called
17356 from md_estimate_size_before_relax first. If this is a
17357 branch to a different section, we mark it as such. If SEC is
17358 NULL, and the frag is not marked, then it must be a branch to
17359 the same section. */
17362 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17367 /* Must have been called from md_estimate_size_before_relax. */
17370 fragp->fr_subtype =
17371 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17373 /* FIXME: We should support this, and let the linker
17374 catch branches and loads that are out of range. */
17375 as_bad_where (fragp->fr_file, fragp->fr_line,
17376 _("unsupported PC relative reference to different section"));
17380 if (fragp != sym_frag && sym_frag->fr_address == 0)
17381 /* Assume non-extended on the first relaxation pass.
17382 The address we have calculated will be bogus if this is
17383 a forward branch to another frag, as the forward frag
17384 will have fr_address == 0. */
17388 /* In this case, we know for sure that the symbol fragment is in
17389 the same section. If the relax_marker of the symbol fragment
17390 differs from the relax_marker of this fragment, we have not
17391 yet adjusted the symbol fragment fr_address. We want to add
17392 in STRETCH in order to get a better estimate of the address.
17393 This particularly matters because of the shift bits. */
17395 && sym_frag->relax_marker != fragp->relax_marker)
17399 /* Adjust stretch for any alignment frag. Note that if have
17400 been expanding the earlier code, the symbol may be
17401 defined in what appears to be an earlier frag. FIXME:
17402 This doesn't handle the fr_subtype field, which specifies
17403 a maximum number of bytes to skip when doing an
17405 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17407 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17410 stretch = - ((- stretch)
17411 & ~ ((1 << (int) f->fr_offset) - 1));
17413 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17422 addr = fragp->fr_address + fragp->fr_fix;
17424 /* The base address rules are complicated. The base address of
17425 a branch is the following instruction. The base address of a
17426 PC relative load or add is the instruction itself, but if it
17427 is in a delay slot (in which case it can not be extended) use
17428 the address of the instruction whose delay slot it is in. */
17429 if (type == 'p' || type == 'q')
17433 /* If we are currently assuming that this frag should be
17434 extended, then, the current address is two bytes
17436 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17439 /* Ignore the low bit in the target, since it will be set
17440 for a text label. */
17441 if ((val & 1) != 0)
17444 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17446 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17449 val -= addr & ~ ((1 << op->shift) - 1);
17451 /* Branch offsets have an implicit 0 in the lowest bit. */
17452 if (type == 'p' || type == 'q')
17455 /* If any of the shifted bits are set, we must use an extended
17456 opcode. If the address depends on the size of this
17457 instruction, this can lead to a loop, so we arrange to always
17458 use an extended opcode. We only check this when we are in
17459 the main relaxation loop, when SEC is NULL. */
17460 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17462 fragp->fr_subtype =
17463 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17467 /* If we are about to mark a frag as extended because the value
17468 is precisely maxtiny + 1, then there is a chance of an
17469 infinite loop as in the following code:
17474 In this case when the la is extended, foo is 0x3fc bytes
17475 away, so the la can be shrunk, but then foo is 0x400 away, so
17476 the la must be extended. To avoid this loop, we mark the
17477 frag as extended if it was small, and is about to become
17478 extended with a value of maxtiny + 1. */
17479 if (val == ((maxtiny + 1) << op->shift)
17480 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17483 fragp->fr_subtype =
17484 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17488 else if (symsec != absolute_section && sec != NULL)
17489 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17491 if ((val & ((1 << op->shift) - 1)) != 0
17492 || val < (mintiny << op->shift)
17493 || val > (maxtiny << op->shift))
17499 /* Compute the length of a branch sequence, and adjust the
17500 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17501 worst-case length is computed, with UPDATE being used to indicate
17502 whether an unconditional (-1), branch-likely (+1) or regular (0)
17503 branch is to be computed. */
17505 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17507 bfd_boolean toofar;
17511 && S_IS_DEFINED (fragp->fr_symbol)
17512 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17517 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17519 addr = fragp->fr_address + fragp->fr_fix + 4;
17523 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17526 /* If the symbol is not defined or it's in a different segment,
17527 assume the user knows what's going on and emit a short
17533 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17535 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17536 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17537 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17538 RELAX_BRANCH_LINK (fragp->fr_subtype),
17544 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17547 if (mips_pic != NO_PIC)
17549 /* Additional space for PIC loading of target address. */
17551 if (mips_opts.isa == ISA_MIPS1)
17552 /* Additional space for $at-stabilizing nop. */
17556 /* If branch is conditional. */
17557 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17564 /* Compute the length of a branch sequence, and adjust the
17565 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17566 worst-case length is computed, with UPDATE being used to indicate
17567 whether an unconditional (-1), or regular (0) branch is to be
17571 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17573 bfd_boolean toofar;
17577 && S_IS_DEFINED (fragp->fr_symbol)
17578 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17583 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17584 /* Ignore the low bit in the target, since it will be set
17585 for a text label. */
17586 if ((val & 1) != 0)
17589 addr = fragp->fr_address + fragp->fr_fix + 4;
17593 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17596 /* If the symbol is not defined or it's in a different segment,
17597 assume the user knows what's going on and emit a short
17603 if (fragp && update
17604 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17605 fragp->fr_subtype = (toofar
17606 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17607 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17612 bfd_boolean compact_known = fragp != NULL;
17613 bfd_boolean compact = FALSE;
17614 bfd_boolean uncond;
17617 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17619 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17621 uncond = update < 0;
17623 /* If label is out of range, we turn branch <br>:
17625 <br> label # 4 bytes
17631 nop # 2 bytes if compact && !PIC
17634 if (mips_pic == NO_PIC && (!compact_known || compact))
17637 /* If assembling PIC code, we further turn:
17643 lw/ld at, %got(label)(gp) # 4 bytes
17644 d/addiu at, %lo(label) # 4 bytes
17647 if (mips_pic != NO_PIC)
17650 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17652 <brneg> 0f # 4 bytes
17653 nop # 2 bytes if !compact
17656 length += (compact_known && compact) ? 4 : 6;
17662 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17663 bit accordingly. */
17666 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17668 bfd_boolean toofar;
17671 && S_IS_DEFINED (fragp->fr_symbol)
17672 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17678 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17679 /* Ignore the low bit in the target, since it will be set
17680 for a text label. */
17681 if ((val & 1) != 0)
17684 /* Assume this is a 2-byte branch. */
17685 addr = fragp->fr_address + fragp->fr_fix + 2;
17687 /* We try to avoid the infinite loop by not adding 2 more bytes for
17692 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17694 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17695 else if (type == 'E')
17696 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17701 /* If the symbol is not defined or it's in a different segment,
17702 we emit a normal 32-bit branch. */
17705 if (fragp && update
17706 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17708 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17709 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17717 /* Estimate the size of a frag before relaxing. Unless this is the
17718 mips16, we are not really relaxing here, and the final size is
17719 encoded in the subtype information. For the mips16, we have to
17720 decide whether we are using an extended opcode or not. */
17723 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17727 if (RELAX_BRANCH_P (fragp->fr_subtype))
17730 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17732 return fragp->fr_var;
17735 if (RELAX_MIPS16_P (fragp->fr_subtype))
17736 /* We don't want to modify the EXTENDED bit here; it might get us
17737 into infinite loops. We change it only in mips_relax_frag(). */
17738 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17740 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17744 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17745 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17746 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17747 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17748 fragp->fr_var = length;
17753 if (mips_pic == NO_PIC)
17754 change = nopic_need_relax (fragp->fr_symbol, 0);
17755 else if (mips_pic == SVR4_PIC)
17756 change = pic_need_relax (fragp->fr_symbol, segtype);
17757 else if (mips_pic == VXWORKS_PIC)
17758 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17765 fragp->fr_subtype |= RELAX_USE_SECOND;
17766 return -RELAX_FIRST (fragp->fr_subtype);
17769 return -RELAX_SECOND (fragp->fr_subtype);
17772 /* This is called to see whether a reloc against a defined symbol
17773 should be converted into a reloc against a section. */
17776 mips_fix_adjustable (fixS *fixp)
17778 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17779 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17782 if (fixp->fx_addsy == NULL)
17785 /* If symbol SYM is in a mergeable section, relocations of the form
17786 SYM + 0 can usually be made section-relative. The mergeable data
17787 is then identified by the section offset rather than by the symbol.
17789 However, if we're generating REL LO16 relocations, the offset is split
17790 between the LO16 and parterning high part relocation. The linker will
17791 need to recalculate the complete offset in order to correctly identify
17794 The linker has traditionally not looked for the parterning high part
17795 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17796 placed anywhere. Rather than break backwards compatibility by changing
17797 this, it seems better not to force the issue, and instead keep the
17798 original symbol. This will work with either linker behavior. */
17799 if ((lo16_reloc_p (fixp->fx_r_type)
17800 || reloc_needs_lo_p (fixp->fx_r_type))
17801 && HAVE_IN_PLACE_ADDENDS
17802 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17805 /* There is no place to store an in-place offset for JALR relocations.
17806 Likewise an in-range offset of PC-relative relocations may overflow
17807 the in-place relocatable field if recalculated against the start
17808 address of the symbol's containing section. */
17809 if (HAVE_IN_PLACE_ADDENDS
17810 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17814 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17815 to a floating-point stub. The same is true for non-R_MIPS16_26
17816 relocations against MIPS16 functions; in this case, the stub becomes
17817 the function's canonical address.
17819 Floating-point stubs are stored in unique .mips16.call.* or
17820 .mips16.fn.* sections. If a stub T for function F is in section S,
17821 the first relocation in section S must be against F; this is how the
17822 linker determines the target function. All relocations that might
17823 resolve to T must also be against F. We therefore have the following
17824 restrictions, which are given in an intentionally-redundant way:
17826 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17829 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17830 if that stub might be used.
17832 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17835 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17836 that stub might be used.
17838 There is a further restriction:
17840 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17841 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17842 targets with in-place addends; the relocation field cannot
17843 encode the low bit.
17845 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17846 against a MIPS16 symbol. We deal with (5) by by not reducing any
17847 such relocations on REL targets.
17849 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17850 relocation against some symbol R, no relocation against R may be
17851 reduced. (Note that this deals with (2) as well as (1) because
17852 relocations against global symbols will never be reduced on ELF
17853 targets.) This approach is a little simpler than trying to detect
17854 stub sections, and gives the "all or nothing" per-symbol consistency
17855 that we have for MIPS16 symbols. */
17857 && fixp->fx_subsy == NULL
17858 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17859 || *symbol_get_tc (fixp->fx_addsy)
17860 || (HAVE_IN_PLACE_ADDENDS
17861 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17862 && jmp_reloc_p (fixp->fx_r_type))))
17869 /* Translate internal representation of relocation info to BFD target
17873 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17875 static arelent *retval[4];
17877 bfd_reloc_code_real_type code;
17879 memset (retval, 0, sizeof(retval));
17880 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17881 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17882 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17883 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17885 if (fixp->fx_pcrel)
17887 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17888 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17889 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17890 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17892 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17893 Relocations want only the symbol offset. */
17894 reloc->addend = fixp->fx_addnumber + reloc->address;
17897 /* A gruesome hack which is a result of the gruesome gas
17898 reloc handling. What's worse, for COFF (as opposed to
17899 ECOFF), we might need yet another copy of reloc->address.
17900 See bfd_install_relocation. */
17901 reloc->addend += reloc->address;
17905 reloc->addend = fixp->fx_addnumber;
17907 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17908 entry to be used in the relocation's section offset. */
17909 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17911 reloc->address = reloc->addend;
17915 code = fixp->fx_r_type;
17917 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17918 if (reloc->howto == NULL)
17920 as_bad_where (fixp->fx_file, fixp->fx_line,
17921 _("Can not represent %s relocation in this object file format"),
17922 bfd_get_reloc_code_name (code));
17929 /* Relax a machine dependent frag. This returns the amount by which
17930 the current size of the frag should change. */
17933 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17935 if (RELAX_BRANCH_P (fragp->fr_subtype))
17937 offsetT old_var = fragp->fr_var;
17939 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17941 return fragp->fr_var - old_var;
17944 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17946 offsetT old_var = fragp->fr_var;
17947 offsetT new_var = 4;
17949 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17950 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17951 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17952 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17953 fragp->fr_var = new_var;
17955 return new_var - old_var;
17958 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17961 if (mips16_extended_frag (fragp, NULL, stretch))
17963 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17965 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17970 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17972 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17979 /* Convert a machine dependent frag. */
17982 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17984 if (RELAX_BRANCH_P (fragp->fr_subtype))
17987 unsigned long insn;
17991 buf = fragp->fr_literal + fragp->fr_fix;
17992 insn = read_insn (buf);
17994 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17996 /* We generate a fixup instead of applying it right now
17997 because, if there are linker relaxations, we're going to
17998 need the relocations. */
17999 exp.X_op = O_symbol;
18000 exp.X_add_symbol = fragp->fr_symbol;
18001 exp.X_add_number = fragp->fr_offset;
18003 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18004 BFD_RELOC_16_PCREL_S2);
18005 fixp->fx_file = fragp->fr_file;
18006 fixp->fx_line = fragp->fr_line;
18008 buf = write_insn (buf, insn);
18014 as_warn_where (fragp->fr_file, fragp->fr_line,
18015 _("Relaxed out-of-range branch into a jump"));
18017 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18020 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18022 /* Reverse the branch. */
18023 switch ((insn >> 28) & 0xf)
18026 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18027 have the condition reversed by tweaking a single
18028 bit, and their opcodes all have 0x4???????. */
18029 gas_assert ((insn & 0xf1000000) == 0x41000000);
18030 insn ^= 0x00010000;
18034 /* bltz 0x04000000 bgez 0x04010000
18035 bltzal 0x04100000 bgezal 0x04110000 */
18036 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18037 insn ^= 0x00010000;
18041 /* beq 0x10000000 bne 0x14000000
18042 blez 0x18000000 bgtz 0x1c000000 */
18043 insn ^= 0x04000000;
18051 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18053 /* Clear the and-link bit. */
18054 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18056 /* bltzal 0x04100000 bgezal 0x04110000
18057 bltzall 0x04120000 bgezall 0x04130000 */
18058 insn &= ~0x00100000;
18061 /* Branch over the branch (if the branch was likely) or the
18062 full jump (not likely case). Compute the offset from the
18063 current instruction to branch to. */
18064 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18068 /* How many bytes in instructions we've already emitted? */
18069 i = buf - fragp->fr_literal - fragp->fr_fix;
18070 /* How many bytes in instructions from here to the end? */
18071 i = fragp->fr_var - i;
18073 /* Convert to instruction count. */
18075 /* Branch counts from the next instruction. */
18078 /* Branch over the jump. */
18079 buf = write_insn (buf, insn);
18082 buf = write_insn (buf, 0);
18084 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18086 /* beql $0, $0, 2f */
18088 /* Compute the PC offset from the current instruction to
18089 the end of the variable frag. */
18090 /* How many bytes in instructions we've already emitted? */
18091 i = buf - fragp->fr_literal - fragp->fr_fix;
18092 /* How many bytes in instructions from here to the end? */
18093 i = fragp->fr_var - i;
18094 /* Convert to instruction count. */
18096 /* Don't decrement i, because we want to branch over the
18100 buf = write_insn (buf, insn);
18101 buf = write_insn (buf, 0);
18105 if (mips_pic == NO_PIC)
18108 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18109 ? 0x0c000000 : 0x08000000);
18110 exp.X_op = O_symbol;
18111 exp.X_add_symbol = fragp->fr_symbol;
18112 exp.X_add_number = fragp->fr_offset;
18114 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18115 FALSE, BFD_RELOC_MIPS_JMP);
18116 fixp->fx_file = fragp->fr_file;
18117 fixp->fx_line = fragp->fr_line;
18119 buf = write_insn (buf, insn);
18123 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18125 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18126 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18127 insn |= at << OP_SH_RT;
18128 exp.X_op = O_symbol;
18129 exp.X_add_symbol = fragp->fr_symbol;
18130 exp.X_add_number = fragp->fr_offset;
18132 if (fragp->fr_offset)
18134 exp.X_add_symbol = make_expr_symbol (&exp);
18135 exp.X_add_number = 0;
18138 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18139 FALSE, BFD_RELOC_MIPS_GOT16);
18140 fixp->fx_file = fragp->fr_file;
18141 fixp->fx_line = fragp->fr_line;
18143 buf = write_insn (buf, insn);
18145 if (mips_opts.isa == ISA_MIPS1)
18147 buf = write_insn (buf, 0);
18149 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18150 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18151 insn |= at << OP_SH_RS | at << OP_SH_RT;
18153 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18154 FALSE, BFD_RELOC_LO16);
18155 fixp->fx_file = fragp->fr_file;
18156 fixp->fx_line = fragp->fr_line;
18158 buf = write_insn (buf, insn);
18161 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18165 insn |= at << OP_SH_RS;
18167 buf = write_insn (buf, insn);
18171 fragp->fr_fix += fragp->fr_var;
18172 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18176 /* Relax microMIPS branches. */
18177 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18179 char *buf = fragp->fr_literal + fragp->fr_fix;
18180 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18181 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18182 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18183 bfd_boolean short_ds;
18184 unsigned long insn;
18188 exp.X_op = O_symbol;
18189 exp.X_add_symbol = fragp->fr_symbol;
18190 exp.X_add_number = fragp->fr_offset;
18192 fragp->fr_fix += fragp->fr_var;
18194 /* Handle 16-bit branches that fit or are forced to fit. */
18195 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18197 /* We generate a fixup instead of applying it right now,
18198 because if there is linker relaxation, we're going to
18199 need the relocations. */
18201 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18202 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18203 else if (type == 'E')
18204 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18205 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18209 fixp->fx_file = fragp->fr_file;
18210 fixp->fx_line = fragp->fr_line;
18212 /* These relocations can have an addend that won't fit in
18214 fixp->fx_no_overflow = 1;
18219 /* Handle 32-bit branches that fit or are forced to fit. */
18220 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18221 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18223 /* We generate a fixup instead of applying it right now,
18224 because if there is linker relaxation, we're going to
18225 need the relocations. */
18226 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18227 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18228 fixp->fx_file = fragp->fr_file;
18229 fixp->fx_line = fragp->fr_line;
18235 /* Relax 16-bit branches to 32-bit branches. */
18238 insn = read_compressed_insn (buf, 2);
18240 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18241 insn = 0x94000000; /* beq */
18242 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18244 unsigned long regno;
18246 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18247 regno = micromips_to_32_reg_d_map [regno];
18248 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18249 insn |= regno << MICROMIPSOP_SH_RS;
18254 /* Nothing else to do, just write it out. */
18255 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18256 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18258 buf = write_compressed_insn (buf, insn, 4);
18259 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18264 insn = read_compressed_insn (buf, 4);
18266 /* Relax 32-bit branches to a sequence of instructions. */
18267 as_warn_where (fragp->fr_file, fragp->fr_line,
18268 _("Relaxed out-of-range branch into a jump"));
18270 /* Set the short-delay-slot bit. */
18271 short_ds = al && (insn & 0x02000000) != 0;
18273 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18277 /* Reverse the branch. */
18278 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18279 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18280 insn ^= 0x20000000;
18281 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18282 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18283 || (insn & 0xffe00000) == 0x40800000 /* blez */
18284 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18285 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18286 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18287 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18288 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18289 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18290 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18291 insn ^= 0x00400000;
18292 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18293 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18294 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18295 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18296 insn ^= 0x00200000;
18302 /* Clear the and-link and short-delay-slot bits. */
18303 gas_assert ((insn & 0xfda00000) == 0x40200000);
18305 /* bltzal 0x40200000 bgezal 0x40600000 */
18306 /* bltzals 0x42200000 bgezals 0x42600000 */
18307 insn &= ~0x02200000;
18310 /* Make a label at the end for use with the branch. */
18311 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18312 micromips_label_inc ();
18313 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18315 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18319 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18320 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18321 fixp->fx_file = fragp->fr_file;
18322 fixp->fx_line = fragp->fr_line;
18324 /* Branch over the jump. */
18325 buf = write_compressed_insn (buf, insn, 4);
18328 buf = write_compressed_insn (buf, 0x0c00, 2);
18331 if (mips_pic == NO_PIC)
18333 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18335 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18336 insn = al ? jal : 0xd4000000;
18338 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18339 BFD_RELOC_MICROMIPS_JMP);
18340 fixp->fx_file = fragp->fr_file;
18341 fixp->fx_line = fragp->fr_line;
18343 buf = write_compressed_insn (buf, insn, 4);
18346 buf = write_compressed_insn (buf, 0x0c00, 2);
18350 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18351 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18352 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18354 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18355 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18356 insn |= at << MICROMIPSOP_SH_RT;
18358 if (exp.X_add_number)
18360 exp.X_add_symbol = make_expr_symbol (&exp);
18361 exp.X_add_number = 0;
18364 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18365 BFD_RELOC_MICROMIPS_GOT16);
18366 fixp->fx_file = fragp->fr_file;
18367 fixp->fx_line = fragp->fr_line;
18369 buf = write_compressed_insn (buf, insn, 4);
18371 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18372 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18373 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18375 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18376 BFD_RELOC_MICROMIPS_LO16);
18377 fixp->fx_file = fragp->fr_file;
18378 fixp->fx_line = fragp->fr_line;
18380 buf = write_compressed_insn (buf, insn, 4);
18382 /* jr/jrc/jalr/jalrs $at */
18383 insn = al ? jalr : jr;
18384 insn |= at << MICROMIPSOP_SH_MJ;
18386 buf = write_compressed_insn (buf, insn, 2);
18389 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18393 if (RELAX_MIPS16_P (fragp->fr_subtype))
18396 const struct mips16_immed_operand *op;
18399 unsigned int user_length, length;
18400 unsigned long insn;
18403 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18404 op = mips16_immed_operands;
18405 while (op->type != type)
18408 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18409 val = resolve_symbol_value (fragp->fr_symbol);
18414 addr = fragp->fr_address + fragp->fr_fix;
18416 /* The rules for the base address of a PC relative reloc are
18417 complicated; see mips16_extended_frag. */
18418 if (type == 'p' || type == 'q')
18423 /* Ignore the low bit in the target, since it will be
18424 set for a text label. */
18425 if ((val & 1) != 0)
18428 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18430 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18433 addr &= ~ (addressT) ((1 << op->shift) - 1);
18436 /* Make sure the section winds up with the alignment we have
18439 record_alignment (asec, op->shift);
18443 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18444 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18445 as_warn_where (fragp->fr_file, fragp->fr_line,
18446 _("extended instruction in delay slot"));
18448 buf = fragp->fr_literal + fragp->fr_fix;
18450 insn = read_compressed_insn (buf, 2);
18452 insn |= MIPS16_EXTEND;
18454 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18456 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18461 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18462 BFD_RELOC_UNUSED, val, user_length, &insn);
18464 length = (ext ? 4 : 2);
18465 gas_assert (mips16_opcode_length (insn) == length);
18466 write_compressed_insn (buf, insn, length);
18467 fragp->fr_fix += length;
18471 relax_substateT subtype = fragp->fr_subtype;
18472 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18473 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18477 first = RELAX_FIRST (subtype);
18478 second = RELAX_SECOND (subtype);
18479 fixp = (fixS *) fragp->fr_opcode;
18481 /* If the delay slot chosen does not match the size of the instruction,
18482 then emit a warning. */
18483 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18484 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18489 s = subtype & (RELAX_DELAY_SLOT_16BIT
18490 | RELAX_DELAY_SLOT_SIZE_FIRST
18491 | RELAX_DELAY_SLOT_SIZE_SECOND);
18492 msg = macro_warning (s);
18494 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18498 /* Possibly emit a warning if we've chosen the longer option. */
18499 if (use_second == second_longer)
18505 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18506 msg = macro_warning (s);
18508 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18512 /* Go through all the fixups for the first sequence. Disable them
18513 (by marking them as done) if we're going to use the second
18514 sequence instead. */
18516 && fixp->fx_frag == fragp
18517 && fixp->fx_where < fragp->fr_fix - second)
18519 if (subtype & RELAX_USE_SECOND)
18521 fixp = fixp->fx_next;
18524 /* Go through the fixups for the second sequence. Disable them if
18525 we're going to use the first sequence, otherwise adjust their
18526 addresses to account for the relaxation. */
18527 while (fixp && fixp->fx_frag == fragp)
18529 if (subtype & RELAX_USE_SECOND)
18530 fixp->fx_where -= first;
18533 fixp = fixp->fx_next;
18536 /* Now modify the frag contents. */
18537 if (subtype & RELAX_USE_SECOND)
18541 start = fragp->fr_literal + fragp->fr_fix - first - second;
18542 memmove (start, start + first, second);
18543 fragp->fr_fix -= first;
18546 fragp->fr_fix -= second;
18552 /* This function is called after the relocs have been generated.
18553 We've been storing mips16 text labels as odd. Here we convert them
18554 back to even for the convenience of the debugger. */
18557 mips_frob_file_after_relocs (void)
18560 unsigned int count, i;
18565 syms = bfd_get_outsymbols (stdoutput);
18566 count = bfd_get_symcount (stdoutput);
18567 for (i = 0; i < count; i++, syms++)
18568 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18569 && ((*syms)->value & 1) != 0)
18571 (*syms)->value &= ~1;
18572 /* If the symbol has an odd size, it was probably computed
18573 incorrectly, so adjust that as well. */
18574 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18575 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18581 /* This function is called whenever a label is defined, including fake
18582 labels instantiated off the dot special symbol. It is used when
18583 handling branch delays; if a branch has a label, we assume we cannot
18584 move it. This also bumps the value of the symbol by 1 in compressed
18588 mips_record_label (symbolS *sym)
18590 segment_info_type *si = seg_info (now_seg);
18591 struct insn_label_list *l;
18593 if (free_insn_labels == NULL)
18594 l = (struct insn_label_list *) xmalloc (sizeof *l);
18597 l = free_insn_labels;
18598 free_insn_labels = l->next;
18602 l->next = si->label_list;
18603 si->label_list = l;
18606 /* This function is called as tc_frob_label() whenever a label is defined
18607 and adds a DWARF-2 record we only want for true labels. */
18610 mips_define_label (symbolS *sym)
18612 mips_record_label (sym);
18614 dwarf2_emit_label (sym);
18618 /* This function is called by tc_new_dot_label whenever a new dot symbol
18622 mips_add_dot_label (symbolS *sym)
18624 mips_record_label (sym);
18625 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18626 mips_compressed_mark_label (sym);
18629 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18631 /* Some special processing for a MIPS ELF file. */
18634 mips_elf_final_processing (void)
18636 /* Write out the register information. */
18637 if (mips_abi != N64_ABI)
18641 s.ri_gprmask = mips_gprmask;
18642 s.ri_cprmask[0] = mips_cprmask[0];
18643 s.ri_cprmask[1] = mips_cprmask[1];
18644 s.ri_cprmask[2] = mips_cprmask[2];
18645 s.ri_cprmask[3] = mips_cprmask[3];
18646 /* The gp_value field is set by the MIPS ELF backend. */
18648 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18649 ((Elf32_External_RegInfo *)
18650 mips_regmask_frag));
18654 Elf64_Internal_RegInfo s;
18656 s.ri_gprmask = mips_gprmask;
18658 s.ri_cprmask[0] = mips_cprmask[0];
18659 s.ri_cprmask[1] = mips_cprmask[1];
18660 s.ri_cprmask[2] = mips_cprmask[2];
18661 s.ri_cprmask[3] = mips_cprmask[3];
18662 /* The gp_value field is set by the MIPS ELF backend. */
18664 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18665 ((Elf64_External_RegInfo *)
18666 mips_regmask_frag));
18669 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18670 sort of BFD interface for this. */
18671 if (mips_any_noreorder)
18672 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18673 if (mips_pic != NO_PIC)
18675 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18676 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18679 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18681 /* Set MIPS ELF flags for ASEs. */
18682 /* We may need to define a new flag for DSP ASE, and set this flag when
18683 file_ase_dsp is true. */
18684 /* Same for DSP R2. */
18685 /* We may need to define a new flag for MT ASE, and set this flag when
18686 file_ase_mt is true. */
18687 if (file_ase_mips16)
18688 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18689 if (file_ase_micromips)
18690 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18691 #if 0 /* XXX FIXME */
18692 if (file_ase_mips3d)
18693 elf_elfheader (stdoutput)->e_flags |= ???;
18696 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18698 /* Set the MIPS ELF ABI flags. */
18699 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18700 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18701 else if (mips_abi == O64_ABI)
18702 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18703 else if (mips_abi == EABI_ABI)
18705 if (!file_mips_gp32)
18706 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18708 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18710 else if (mips_abi == N32_ABI)
18711 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18713 /* Nothing to do for N64_ABI. */
18715 if (mips_32bitmode)
18716 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18718 #if 0 /* XXX FIXME */
18719 /* 32 bit code with 64 bit FP registers. */
18720 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18721 elf_elfheader (stdoutput)->e_flags |= ???;
18725 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18727 typedef struct proc {
18729 symbolS *func_end_sym;
18730 unsigned long reg_mask;
18731 unsigned long reg_offset;
18732 unsigned long fpreg_mask;
18733 unsigned long fpreg_offset;
18734 unsigned long frame_offset;
18735 unsigned long frame_reg;
18736 unsigned long pc_reg;
18739 static procS cur_proc;
18740 static procS *cur_proc_ptr;
18741 static int numprocs;
18743 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18744 as "2", and a normal nop as "0". */
18746 #define NOP_OPCODE_MIPS 0
18747 #define NOP_OPCODE_MIPS16 1
18748 #define NOP_OPCODE_MICROMIPS 2
18751 mips_nop_opcode (void)
18753 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18754 return NOP_OPCODE_MICROMIPS;
18755 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18756 return NOP_OPCODE_MIPS16;
18758 return NOP_OPCODE_MIPS;
18761 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18762 32-bit microMIPS NOPs here (if applicable). */
18765 mips_handle_align (fragS *fragp)
18769 int bytes, size, excess;
18772 if (fragp->fr_type != rs_align_code)
18775 p = fragp->fr_literal + fragp->fr_fix;
18777 switch (nop_opcode)
18779 case NOP_OPCODE_MICROMIPS:
18780 opcode = micromips_nop32_insn.insn_opcode;
18783 case NOP_OPCODE_MIPS16:
18784 opcode = mips16_nop_insn.insn_opcode;
18787 case NOP_OPCODE_MIPS:
18789 opcode = nop_insn.insn_opcode;
18794 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18795 excess = bytes % size;
18797 /* Handle the leading part if we're not inserting a whole number of
18798 instructions, and make it the end of the fixed part of the frag.
18799 Try to fit in a short microMIPS NOP if applicable and possible,
18800 and use zeroes otherwise. */
18801 gas_assert (excess < 4);
18802 fragp->fr_fix += excess;
18807 /* Fall through. */
18809 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18811 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18815 /* Fall through. */
18818 /* Fall through. */
18823 md_number_to_chars (p, opcode, size);
18824 fragp->fr_var = size;
18828 md_obj_begin (void)
18835 /* Check for premature end, nesting errors, etc. */
18837 as_warn (_("missing .end at end of assembly"));
18846 if (*input_line_pointer == '-')
18848 ++input_line_pointer;
18851 if (!ISDIGIT (*input_line_pointer))
18852 as_bad (_("expected simple number"));
18853 if (input_line_pointer[0] == '0')
18855 if (input_line_pointer[1] == 'x')
18857 input_line_pointer += 2;
18858 while (ISXDIGIT (*input_line_pointer))
18861 val |= hex_value (*input_line_pointer++);
18863 return negative ? -val : val;
18867 ++input_line_pointer;
18868 while (ISDIGIT (*input_line_pointer))
18871 val |= *input_line_pointer++ - '0';
18873 return negative ? -val : val;
18876 if (!ISDIGIT (*input_line_pointer))
18878 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18879 *input_line_pointer, *input_line_pointer);
18880 as_warn (_("invalid number"));
18883 while (ISDIGIT (*input_line_pointer))
18886 val += *input_line_pointer++ - '0';
18888 return negative ? -val : val;
18891 /* The .file directive; just like the usual .file directive, but there
18892 is an initial number which is the ECOFF file index. In the non-ECOFF
18893 case .file implies DWARF-2. */
18896 s_mips_file (int x ATTRIBUTE_UNUSED)
18898 static int first_file_directive = 0;
18900 if (ECOFF_DEBUGGING)
18909 filename = dwarf2_directive_file (0);
18911 /* Versions of GCC up to 3.1 start files with a ".file"
18912 directive even for stabs output. Make sure that this
18913 ".file" is handled. Note that you need a version of GCC
18914 after 3.1 in order to support DWARF-2 on MIPS. */
18915 if (filename != NULL && ! first_file_directive)
18917 (void) new_logical_line (filename, -1);
18918 s_app_file_string (filename, 0);
18920 first_file_directive = 1;
18924 /* The .loc directive, implying DWARF-2. */
18927 s_mips_loc (int x ATTRIBUTE_UNUSED)
18929 if (!ECOFF_DEBUGGING)
18930 dwarf2_directive_loc (0);
18933 /* The .end directive. */
18936 s_mips_end (int x ATTRIBUTE_UNUSED)
18940 /* Following functions need their own .frame and .cprestore directives. */
18941 mips_frame_reg_valid = 0;
18942 mips_cprestore_valid = 0;
18944 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18947 demand_empty_rest_of_line ();
18952 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18953 as_warn (_(".end not in text section"));
18957 as_warn (_(".end directive without a preceding .ent directive."));
18958 demand_empty_rest_of_line ();
18964 gas_assert (S_GET_NAME (p));
18965 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18966 as_warn (_(".end symbol does not match .ent symbol."));
18968 if (debug_type == DEBUG_STABS)
18969 stabs_generate_asm_endfunc (S_GET_NAME (p),
18973 as_warn (_(".end directive missing or unknown symbol"));
18976 /* Create an expression to calculate the size of the function. */
18977 if (p && cur_proc_ptr)
18979 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18980 expressionS *exp = xmalloc (sizeof (expressionS));
18983 exp->X_op = O_subtract;
18984 exp->X_add_symbol = symbol_temp_new_now ();
18985 exp->X_op_symbol = p;
18986 exp->X_add_number = 0;
18988 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18991 /* Generate a .pdr section. */
18992 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18994 segT saved_seg = now_seg;
18995 subsegT saved_subseg = now_subseg;
18999 #ifdef md_flush_pending_output
19000 md_flush_pending_output ();
19003 gas_assert (pdr_seg);
19004 subseg_set (pdr_seg, 0);
19006 /* Write the symbol. */
19007 exp.X_op = O_symbol;
19008 exp.X_add_symbol = p;
19009 exp.X_add_number = 0;
19010 emit_expr (&exp, 4);
19012 fragp = frag_more (7 * 4);
19014 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19015 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19016 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19017 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19018 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19019 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19020 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19022 subseg_set (saved_seg, saved_subseg);
19024 #endif /* OBJ_ELF */
19026 cur_proc_ptr = NULL;
19029 /* The .aent and .ent directives. */
19032 s_mips_ent (int aent)
19036 symbolP = get_symbol ();
19037 if (*input_line_pointer == ',')
19038 ++input_line_pointer;
19039 SKIP_WHITESPACE ();
19040 if (ISDIGIT (*input_line_pointer)
19041 || *input_line_pointer == '-')
19044 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19045 as_warn (_(".ent or .aent not in text section."));
19047 if (!aent && cur_proc_ptr)
19048 as_warn (_("missing .end"));
19052 /* This function needs its own .frame and .cprestore directives. */
19053 mips_frame_reg_valid = 0;
19054 mips_cprestore_valid = 0;
19056 cur_proc_ptr = &cur_proc;
19057 memset (cur_proc_ptr, '\0', sizeof (procS));
19059 cur_proc_ptr->func_sym = symbolP;
19063 if (debug_type == DEBUG_STABS)
19064 stabs_generate_asm_func (S_GET_NAME (symbolP),
19065 S_GET_NAME (symbolP));
19068 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19070 demand_empty_rest_of_line ();
19073 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19074 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19075 s_mips_frame is used so that we can set the PDR information correctly.
19076 We can't use the ecoff routines because they make reference to the ecoff
19077 symbol table (in the mdebug section). */
19080 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19083 if (IS_ELF && !ECOFF_DEBUGGING)
19087 if (cur_proc_ptr == (procS *) NULL)
19089 as_warn (_(".frame outside of .ent"));
19090 demand_empty_rest_of_line ();
19094 cur_proc_ptr->frame_reg = tc_get_register (1);
19096 SKIP_WHITESPACE ();
19097 if (*input_line_pointer++ != ','
19098 || get_absolute_expression_and_terminator (&val) != ',')
19100 as_warn (_("Bad .frame directive"));
19101 --input_line_pointer;
19102 demand_empty_rest_of_line ();
19106 cur_proc_ptr->frame_offset = val;
19107 cur_proc_ptr->pc_reg = tc_get_register (0);
19109 demand_empty_rest_of_line ();
19112 #endif /* OBJ_ELF */
19116 /* The .fmask and .mask directives. If the mdebug section is present
19117 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19118 embedded targets, s_mips_mask is used so that we can set the PDR
19119 information correctly. We can't use the ecoff routines because they
19120 make reference to the ecoff symbol table (in the mdebug section). */
19123 s_mips_mask (int reg_type)
19126 if (IS_ELF && !ECOFF_DEBUGGING)
19130 if (cur_proc_ptr == (procS *) NULL)
19132 as_warn (_(".mask/.fmask outside of .ent"));
19133 demand_empty_rest_of_line ();
19137 if (get_absolute_expression_and_terminator (&mask) != ',')
19139 as_warn (_("Bad .mask/.fmask directive"));
19140 --input_line_pointer;
19141 demand_empty_rest_of_line ();
19145 off = get_absolute_expression ();
19147 if (reg_type == 'F')
19149 cur_proc_ptr->fpreg_mask = mask;
19150 cur_proc_ptr->fpreg_offset = off;
19154 cur_proc_ptr->reg_mask = mask;
19155 cur_proc_ptr->reg_offset = off;
19158 demand_empty_rest_of_line ();
19161 #endif /* OBJ_ELF */
19162 s_ignore (reg_type);
19165 /* A table describing all the processors gas knows about. Names are
19166 matched in the order listed.
19168 To ease comparison, please keep this table in the same order as
19169 gcc's mips_cpu_info_table[]. */
19170 static const struct mips_cpu_info mips_cpu_info_table[] =
19172 /* Entries for generic ISAs */
19173 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19174 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19175 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19176 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19177 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19178 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19179 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19180 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19181 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19184 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19185 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19186 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19189 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19192 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19193 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19194 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19195 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19196 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19197 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19198 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19199 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19200 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19201 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19202 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19203 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19204 { "r5900", 0, ISA_MIPS3, CPU_R5900 },
19205 /* ST Microelectronics Loongson 2E and 2F cores */
19206 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19207 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19210 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19211 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19212 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19213 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19214 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19215 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19216 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19217 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19218 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19219 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19220 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19221 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19222 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19223 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19224 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19227 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19228 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19229 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19230 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19232 /* MIPS 32 Release 2 */
19233 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19234 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19235 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19236 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19237 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19238 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19239 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19240 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19241 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19242 ISA_MIPS32R2, CPU_MIPS32R2 },
19243 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19244 ISA_MIPS32R2, CPU_MIPS32R2 },
19245 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19246 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19247 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19248 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19249 /* Deprecated forms of the above. */
19250 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19251 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19252 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19253 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19254 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19255 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19256 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19257 /* Deprecated forms of the above. */
19258 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19259 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19260 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19261 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19262 ISA_MIPS32R2, CPU_MIPS32R2 },
19263 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19264 ISA_MIPS32R2, CPU_MIPS32R2 },
19265 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19266 ISA_MIPS32R2, CPU_MIPS32R2 },
19267 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19268 ISA_MIPS32R2, CPU_MIPS32R2 },
19269 /* Deprecated forms of the above. */
19270 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19271 ISA_MIPS32R2, CPU_MIPS32R2 },
19272 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19273 ISA_MIPS32R2, CPU_MIPS32R2 },
19274 /* 34Kn is a 34kc without DSP. */
19275 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19276 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19277 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19278 ISA_MIPS32R2, CPU_MIPS32R2 },
19279 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19280 ISA_MIPS32R2, CPU_MIPS32R2 },
19281 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19282 ISA_MIPS32R2, CPU_MIPS32R2 },
19283 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19284 ISA_MIPS32R2, CPU_MIPS32R2 },
19285 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19286 ISA_MIPS32R2, CPU_MIPS32R2 },
19287 /* Deprecated forms of the above. */
19288 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19289 ISA_MIPS32R2, CPU_MIPS32R2 },
19290 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19291 ISA_MIPS32R2, CPU_MIPS32R2 },
19292 /* 1004K cores are multiprocessor versions of the 34K. */
19293 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19294 ISA_MIPS32R2, CPU_MIPS32R2 },
19295 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19296 ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19298 ISA_MIPS32R2, CPU_MIPS32R2 },
19299 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19300 ISA_MIPS32R2, CPU_MIPS32R2 },
19303 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19304 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19305 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19306 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19308 /* Broadcom SB-1 CPU core */
19309 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19310 ISA_MIPS64, CPU_SB1 },
19311 /* Broadcom SB-1A CPU core */
19312 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19313 ISA_MIPS64, CPU_SB1 },
19315 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19317 /* MIPS 64 Release 2 */
19319 /* Cavium Networks Octeon CPU core */
19320 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19321 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19322 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19325 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19328 XLP is mostly like XLR, with the prominent exception that it is
19329 MIPS64R2 rather than MIPS64. */
19330 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19337 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19338 with a final "000" replaced by "k". Ignore case.
19340 Note: this function is shared between GCC and GAS. */
19343 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19345 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19346 given++, canonical++;
19348 return ((*given == 0 && *canonical == 0)
19349 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19353 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19354 CPU name. We've traditionally allowed a lot of variation here.
19356 Note: this function is shared between GCC and GAS. */
19359 mips_matching_cpu_name_p (const char *canonical, const char *given)
19361 /* First see if the name matches exactly, or with a final "000"
19362 turned into "k". */
19363 if (mips_strict_matching_cpu_name_p (canonical, given))
19366 /* If not, try comparing based on numerical designation alone.
19367 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19368 if (TOLOWER (*given) == 'r')
19370 if (!ISDIGIT (*given))
19373 /* Skip over some well-known prefixes in the canonical name,
19374 hoping to find a number there too. */
19375 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19377 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19379 else if (TOLOWER (canonical[0]) == 'r')
19382 return mips_strict_matching_cpu_name_p (canonical, given);
19386 /* Parse an option that takes the name of a processor as its argument.
19387 OPTION is the name of the option and CPU_STRING is the argument.
19388 Return the corresponding processor enumeration if the CPU_STRING is
19389 recognized, otherwise report an error and return null.
19391 A similar function exists in GCC. */
19393 static const struct mips_cpu_info *
19394 mips_parse_cpu (const char *option, const char *cpu_string)
19396 const struct mips_cpu_info *p;
19398 /* 'from-abi' selects the most compatible architecture for the given
19399 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19400 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19401 version. Look first at the -mgp options, if given, otherwise base
19402 the choice on MIPS_DEFAULT_64BIT.
19404 Treat NO_ABI like the EABIs. One reason to do this is that the
19405 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19406 architecture. This code picks MIPS I for 'mips' and MIPS III for
19407 'mips64', just as we did in the days before 'from-abi'. */
19408 if (strcasecmp (cpu_string, "from-abi") == 0)
19410 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19411 return mips_cpu_info_from_isa (ISA_MIPS1);
19413 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19414 return mips_cpu_info_from_isa (ISA_MIPS3);
19416 if (file_mips_gp32 >= 0)
19417 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19419 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19424 /* 'default' has traditionally been a no-op. Probably not very useful. */
19425 if (strcasecmp (cpu_string, "default") == 0)
19428 for (p = mips_cpu_info_table; p->name != 0; p++)
19429 if (mips_matching_cpu_name_p (p->name, cpu_string))
19432 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19436 /* Return the canonical processor information for ISA (a member of the
19437 ISA_MIPS* enumeration). */
19439 static const struct mips_cpu_info *
19440 mips_cpu_info_from_isa (int isa)
19444 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19445 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19446 && isa == mips_cpu_info_table[i].isa)
19447 return (&mips_cpu_info_table[i]);
19452 static const struct mips_cpu_info *
19453 mips_cpu_info_from_arch (int arch)
19457 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19458 if (arch == mips_cpu_info_table[i].cpu)
19459 return (&mips_cpu_info_table[i]);
19465 show (FILE *stream, const char *string, int *col_p, int *first_p)
19469 fprintf (stream, "%24s", "");
19474 fprintf (stream, ", ");
19478 if (*col_p + strlen (string) > 72)
19480 fprintf (stream, "\n%24s", "");
19484 fprintf (stream, "%s", string);
19485 *col_p += strlen (string);
19491 md_show_usage (FILE *stream)
19496 fprintf (stream, _("\
19498 -EB generate big endian output\n\
19499 -EL generate little endian output\n\
19500 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19501 -G NUM allow referencing objects up to NUM bytes\n\
19502 implicitly with the gp register [default 8]\n"));
19503 fprintf (stream, _("\
19504 -mips1 generate MIPS ISA I instructions\n\
19505 -mips2 generate MIPS ISA II instructions\n\
19506 -mips3 generate MIPS ISA III instructions\n\
19507 -mips4 generate MIPS ISA IV instructions\n\
19508 -mips5 generate MIPS ISA V instructions\n\
19509 -mips32 generate MIPS32 ISA instructions\n\
19510 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19511 -mips64 generate MIPS64 ISA instructions\n\
19512 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19513 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19517 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19518 show (stream, mips_cpu_info_table[i].name, &column, &first);
19519 show (stream, "from-abi", &column, &first);
19520 fputc ('\n', stream);
19522 fprintf (stream, _("\
19523 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19524 -no-mCPU don't generate code specific to CPU.\n\
19525 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19529 show (stream, "3900", &column, &first);
19530 show (stream, "4010", &column, &first);
19531 show (stream, "4100", &column, &first);
19532 show (stream, "4650", &column, &first);
19533 fputc ('\n', stream);
19535 fprintf (stream, _("\
19536 -mips16 generate mips16 instructions\n\
19537 -no-mips16 do not generate mips16 instructions\n"));
19538 fprintf (stream, _("\
19539 -mmicromips generate microMIPS instructions\n\
19540 -mno-micromips do not generate microMIPS instructions\n"));
19541 fprintf (stream, _("\
19542 -msmartmips generate smartmips instructions\n\
19543 -mno-smartmips do not generate smartmips instructions\n"));
19544 fprintf (stream, _("\
19545 -mdsp generate DSP instructions\n\
19546 -mno-dsp do not generate DSP instructions\n"));
19547 fprintf (stream, _("\
19548 -mdspr2 generate DSP R2 instructions\n\
19549 -mno-dspr2 do not generate DSP R2 instructions\n"));
19550 fprintf (stream, _("\
19551 -mmt generate MT instructions\n\
19552 -mno-mt do not generate MT instructions\n"));
19553 fprintf (stream, _("\
19554 -mmcu generate MCU instructions\n\
19555 -mno-mcu do not generate MCU instructions\n"));
19556 fprintf (stream, _("\
19557 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19558 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19559 -mfix-vr4120 work around certain VR4120 errata\n\
19560 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19561 -mfix-24k insert a nop after ERET and DERET instructions\n\
19562 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19563 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19564 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19565 -msym32 assume all symbols have 32-bit values\n\
19566 -O0 remove unneeded NOPs, do not swap branches\n\
19567 -O remove unneeded NOPs and swap branches\n\
19568 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19569 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19570 fprintf (stream, _("\
19571 -mhard-float allow floating-point instructions\n\
19572 -msoft-float do not allow floating-point instructions\n\
19573 -msingle-float only allow 32-bit floating-point operations\n\
19574 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19575 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19578 fprintf (stream, _("\
19579 -KPIC, -call_shared generate SVR4 position independent code\n\
19580 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19581 -mvxworks-pic generate VxWorks position independent code\n\
19582 -non_shared do not generate code that can operate with DSOs\n\
19583 -xgot assume a 32 bit GOT\n\
19584 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19585 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19586 position dependent (non shared) code\n\
19587 -mabi=ABI create ABI conformant object file for:\n"));
19591 show (stream, "32", &column, &first);
19592 show (stream, "o64", &column, &first);
19593 show (stream, "n32", &column, &first);
19594 show (stream, "64", &column, &first);
19595 show (stream, "eabi", &column, &first);
19597 fputc ('\n', stream);
19599 fprintf (stream, _("\
19600 -32 create o32 ABI object file (default)\n\
19601 -n32 create n32 ABI object file\n\
19602 -64 create 64 ABI object file\n"));
19608 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19610 if (HAVE_64BIT_SYMBOLS)
19611 return dwarf2_format_64bit_irix;
19613 return dwarf2_format_32bit;
19618 mips_dwarf2_addr_size (void)
19620 if (HAVE_64BIT_OBJECTS)
19626 /* Standard calling conventions leave the CFA at SP on entry. */
19628 mips_cfi_frame_initial_instructions (void)
19630 cfi_add_CFA_def_cfa_register (SP);
19634 tc_mips_regname_to_dw2regnum (char *regname)
19636 unsigned int regnum = -1;
19639 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))