1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
299 /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
300 /* soft_float */ FALSE, /* single_float */ FALSE
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* MIPS ISA we are using for this output file. */
310 static int file_mips_isa = ISA_UNKNOWN;
312 /* True if any MIPS16 code was produced. */
313 static int file_ase_mips16;
315 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
316 || mips_opts.isa == ISA_MIPS32R2 \
317 || mips_opts.isa == ISA_MIPS64 \
318 || mips_opts.isa == ISA_MIPS64R2)
320 /* True if any microMIPS code was produced. */
321 static int file_ase_micromips;
323 /* True if we want to create R_MIPS_JALR for jalr $25. */
325 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
327 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
328 because there's no place for any addend, the only acceptable
329 expression is a bare symbol. */
330 #define MIPS_JALR_HINT_P(EXPR) \
331 (!HAVE_IN_PLACE_ADDENDS \
332 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
335 /* True if -mips3d was passed or implied by arguments passed on the
336 command line (e.g., by -march). */
337 static int file_ase_mips3d;
339 /* True if -mdmx was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mdmx;
343 /* True if -msmartmips was passed or implied by arguments passed on the
344 command line (e.g., by -march). */
345 static int file_ase_smartmips;
347 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
348 || mips_opts.isa == ISA_MIPS32R2)
350 /* True if -mdsp was passed or implied by arguments passed on the
351 command line (e.g., by -march). */
352 static int file_ase_dsp;
354 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
355 || mips_opts.isa == ISA_MIPS64R2 \
356 || mips_opts.micromips)
358 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
360 /* True if -mdspr2 was passed or implied by arguments passed on the
361 command line (e.g., by -march). */
362 static int file_ase_dspr2;
364 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
365 || mips_opts.isa == ISA_MIPS64R2 \
366 || mips_opts.micromips)
368 /* True if -mmt was passed or implied by arguments passed on the
369 command line (e.g., by -march). */
370 static int file_ase_mt;
372 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
376 || mips_opts.isa == ISA_MIPS64R2 \
377 || mips_opts.micromips)
379 /* True if -mvirt was passed or implied by arguments passed on the
380 command line (e.g., by -march). */
381 static int file_ase_virt;
383 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
384 || mips_opts.isa == ISA_MIPS64R2)
386 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2)
388 /* The argument of the -march= flag. The architecture we are assembling. */
389 static int file_mips_arch = CPU_UNKNOWN;
390 static const char *mips_arch_string;
392 /* The argument of the -mtune= flag. The architecture for which we
394 static int mips_tune = CPU_UNKNOWN;
395 static const char *mips_tune_string;
397 /* True when generating 32-bit code for a 64-bit processor. */
398 static int mips_32bitmode = 0;
400 /* True if the given ABI requires 32-bit registers. */
401 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
403 /* Likewise 64-bit registers. */
404 #define ABI_NEEDS_64BIT_REGS(ABI) \
406 || (ABI) == N64_ABI \
409 /* Return true if ISA supports 64 bit wide gp registers. */
410 #define ISA_HAS_64BIT_REGS(ISA) \
411 ((ISA) == ISA_MIPS3 \
412 || (ISA) == ISA_MIPS4 \
413 || (ISA) == ISA_MIPS5 \
414 || (ISA) == ISA_MIPS64 \
415 || (ISA) == ISA_MIPS64R2)
417 /* Return true if ISA supports 64 bit wide float registers. */
418 #define ISA_HAS_64BIT_FPRS(ISA) \
419 ((ISA) == ISA_MIPS3 \
420 || (ISA) == ISA_MIPS4 \
421 || (ISA) == ISA_MIPS5 \
422 || (ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64 \
424 || (ISA) == ISA_MIPS64R2)
426 /* Return true if ISA supports 64-bit right rotate (dror et al.)
428 #define ISA_HAS_DROR(ISA) \
429 ((ISA) == ISA_MIPS64R2 \
430 || (mips_opts.micromips \
431 && ISA_HAS_64BIT_REGS (ISA)) \
434 /* Return true if ISA supports 32-bit right rotate (ror et al.)
436 #define ISA_HAS_ROR(ISA) \
437 ((ISA) == ISA_MIPS32R2 \
438 || (ISA) == ISA_MIPS64R2 \
439 || mips_opts.ase_smartmips \
440 || mips_opts.micromips \
443 /* Return true if ISA supports single-precision floats in odd registers. */
444 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
445 ((ISA) == ISA_MIPS32 \
446 || (ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS64 \
448 || (ISA) == ISA_MIPS64R2)
450 /* Return true if ISA supports move to/from high part of a 64-bit
451 floating-point register. */
452 #define ISA_HAS_MXHC1(ISA) \
453 ((ISA) == ISA_MIPS32R2 \
454 || (ISA) == ISA_MIPS64R2)
456 #define HAVE_32BIT_GPRS \
457 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
459 #define HAVE_32BIT_FPRS \
460 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
462 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
463 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
515 /* True if CPU has seq/sne and seqi/snei instructions. */
516 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
518 /* True, if CPU has support for ldc1 and sdc1. */
519 #define CPU_HAS_LDC1_SDC1(CPU) \
520 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
522 /* True if mflo and mfhi can be immediately followed by instructions
523 which write to the HI and LO registers.
525 According to MIPS specifications, MIPS ISAs I, II, and III need
526 (at least) two instructions between the reads of HI/LO and
527 instructions which write them, and later ISAs do not. Contradicting
528 the MIPS specifications, some MIPS IV processor user manuals (e.g.
529 the UM for the NEC Vr5000) document needing the instructions between
530 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
531 MIPS64 and later ISAs to have the interlocks, plus any specific
532 earlier-ISA CPUs for which CPU documentation declares that the
533 instructions are really interlocked. */
534 #define hilo_interlocks \
535 (mips_opts.isa == ISA_MIPS32 \
536 || mips_opts.isa == ISA_MIPS32R2 \
537 || mips_opts.isa == ISA_MIPS64 \
538 || mips_opts.isa == ISA_MIPS64R2 \
539 || mips_opts.arch == CPU_R4010 \
540 || mips_opts.arch == CPU_R5900 \
541 || mips_opts.arch == CPU_R10000 \
542 || mips_opts.arch == CPU_R12000 \
543 || mips_opts.arch == CPU_R14000 \
544 || mips_opts.arch == CPU_R16000 \
545 || mips_opts.arch == CPU_RM7000 \
546 || mips_opts.arch == CPU_VR5500 \
547 || mips_opts.micromips \
550 /* Whether the processor uses hardware interlocks to protect reads
551 from the GPRs after they are loaded from memory, and thus does not
552 require nops to be inserted. This applies to instructions marked
553 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
554 level I and microMIPS mode instructions are always interlocked. */
555 #define gpr_interlocks \
556 (mips_opts.isa != ISA_MIPS1 \
557 || mips_opts.arch == CPU_R3900 \
558 || mips_opts.arch == CPU_R5900 \
559 || mips_opts.micromips \
562 /* Whether the processor uses hardware interlocks to avoid delays
563 required by coprocessor instructions, and thus does not require
564 nops to be inserted. This applies to instructions marked
565 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
566 between instructions marked INSN_WRITE_COND_CODE and ones marked
567 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
568 levels I, II, and III and microMIPS mode instructions are always
570 /* Itbl support may require additional care here. */
571 #define cop_interlocks \
572 ((mips_opts.isa != ISA_MIPS1 \
573 && mips_opts.isa != ISA_MIPS2 \
574 && mips_opts.isa != ISA_MIPS3) \
575 || mips_opts.arch == CPU_R4300 \
576 || mips_opts.micromips \
579 /* Whether the processor uses hardware interlocks to protect reads
580 from coprocessor registers after they are loaded from memory, and
581 thus does not require nops to be inserted. This applies to
582 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
583 requires at MIPS ISA level I and microMIPS mode instructions are
584 always interlocked. */
585 #define cop_mem_interlocks \
586 (mips_opts.isa != ISA_MIPS1 \
587 || mips_opts.micromips \
590 /* Is this a mfhi or mflo instruction? */
591 #define MF_HILO_INSN(PINFO) \
592 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
594 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
595 has been selected. This implies, in particular, that addresses of text
596 labels have their LSB set. */
597 #define HAVE_CODE_COMPRESSION \
598 ((mips_opts.mips16 | mips_opts.micromips) != 0)
600 /* MIPS PIC level. */
602 enum mips_pic_level mips_pic;
604 /* 1 if we should generate 32 bit offsets from the $gp register in
605 SVR4_PIC mode. Currently has no meaning in other modes. */
606 static int mips_big_got = 0;
608 /* 1 if trap instructions should used for overflow rather than break
610 static int mips_trap = 0;
612 /* 1 if double width floating point constants should not be constructed
613 by assembling two single width halves into two single width floating
614 point registers which just happen to alias the double width destination
615 register. On some architectures this aliasing can be disabled by a bit
616 in the status register, and the setting of this bit cannot be determined
617 automatically at assemble time. */
618 static int mips_disable_float_construction;
620 /* Non-zero if any .set noreorder directives were used. */
622 static int mips_any_noreorder;
624 /* Non-zero if nops should be inserted when the register referenced in
625 an mfhi/mflo instruction is read in the next two instructions. */
626 static int mips_7000_hilo_fix;
628 /* The size of objects in the small data section. */
629 static unsigned int g_switch_value = 8;
630 /* Whether the -G option was used. */
631 static int g_switch_seen = 0;
636 /* If we can determine in advance that GP optimization won't be
637 possible, we can skip the relaxation stuff that tries to produce
638 GP-relative references. This makes delay slot optimization work
641 This function can only provide a guess, but it seems to work for
642 gcc output. It needs to guess right for gcc, otherwise gcc
643 will put what it thinks is a GP-relative instruction in a branch
646 I don't know if a fix is needed for the SVR4_PIC mode. I've only
647 fixed it for the non-PIC mode. KR 95/04/07 */
648 static int nopic_need_relax (symbolS *, int);
650 /* handle of the OPCODE hash table */
651 static struct hash_control *op_hash = NULL;
653 /* The opcode hash table we use for the mips16. */
654 static struct hash_control *mips16_op_hash = NULL;
656 /* The opcode hash table we use for the microMIPS ASE. */
657 static struct hash_control *micromips_op_hash = NULL;
659 /* This array holds the chars that always start a comment. If the
660 pre-processor is disabled, these aren't very useful */
661 const char comment_chars[] = "#";
663 /* This array holds the chars that only start a comment at the beginning of
664 a line. If the line seems to have the form '# 123 filename'
665 .line and .file directives will appear in the pre-processed output */
666 /* Note that input_file.c hand checks for '#' at the beginning of the
667 first line of the input file. This is because the compiler outputs
668 #NO_APP at the beginning of its output. */
669 /* Also note that C style comments are always supported. */
670 const char line_comment_chars[] = "#";
672 /* This array holds machine specific line separator characters. */
673 const char line_separator_chars[] = ";";
675 /* Chars that can be used to separate mant from exp in floating point nums */
676 const char EXP_CHARS[] = "eE";
678 /* Chars that mean this number is a floating point constant */
681 const char FLT_CHARS[] = "rRsSfFdDxXpP";
683 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
684 changed in read.c . Ideally it shouldn't have to know about it at all,
685 but nothing is ideal around here.
688 static char *insn_error;
690 static int auto_align = 1;
692 /* When outputting SVR4 PIC code, the assembler needs to know the
693 offset in the stack frame from which to restore the $gp register.
694 This is set by the .cprestore pseudo-op, and saved in this
696 static offsetT mips_cprestore_offset = -1;
698 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
699 more optimizations, it can use a register value instead of a memory-saved
700 offset and even an other register than $gp as global pointer. */
701 static offsetT mips_cpreturn_offset = -1;
702 static int mips_cpreturn_register = -1;
703 static int mips_gp_register = GP;
704 static int mips_gprel_offset = 0;
706 /* Whether mips_cprestore_offset has been set in the current function
707 (or whether it has already been warned about, if not). */
708 static int mips_cprestore_valid = 0;
710 /* This is the register which holds the stack frame, as set by the
711 .frame pseudo-op. This is needed to implement .cprestore. */
712 static int mips_frame_reg = SP;
714 /* Whether mips_frame_reg has been set in the current function
715 (or whether it has already been warned about, if not). */
716 static int mips_frame_reg_valid = 0;
718 /* To output NOP instructions correctly, we need to keep information
719 about the previous two instructions. */
721 /* Whether we are optimizing. The default value of 2 means to remove
722 unneeded NOPs and swap branch instructions when possible. A value
723 of 1 means to not swap branches. A value of 0 means to always
725 static int mips_optimize = 2;
727 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
728 equivalent to seeing no -g option at all. */
729 static int mips_debug = 0;
731 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
732 #define MAX_VR4130_NOPS 4
734 /* The maximum number of NOPs needed to fill delay slots. */
735 #define MAX_DELAY_NOPS 2
737 /* The maximum number of NOPs needed for any purpose. */
740 /* A list of previous instructions, with index 0 being the most recent.
741 We need to look back MAX_NOPS instructions when filling delay slots
742 or working around processor errata. We need to look back one
743 instruction further if we're thinking about using history[0] to
744 fill a branch delay slot. */
745 static struct mips_cl_insn history[1 + MAX_NOPS];
747 /* Nop instructions used by emit_nop. */
748 static struct mips_cl_insn nop_insn;
749 static struct mips_cl_insn mips16_nop_insn;
750 static struct mips_cl_insn micromips_nop16_insn;
751 static struct mips_cl_insn micromips_nop32_insn;
753 /* The appropriate nop for the current mode. */
754 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
755 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
757 /* The size of NOP_INSN in bytes. */
758 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
760 /* If this is set, it points to a frag holding nop instructions which
761 were inserted before the start of a noreorder section. If those
762 nops turn out to be unnecessary, the size of the frag can be
764 static fragS *prev_nop_frag;
766 /* The number of nop instructions we created in prev_nop_frag. */
767 static int prev_nop_frag_holds;
769 /* The number of nop instructions that we know we need in
771 static int prev_nop_frag_required;
773 /* The number of instructions we've seen since prev_nop_frag. */
774 static int prev_nop_frag_since;
776 /* For ECOFF and ELF, relocations against symbols are done in two
777 parts, with a HI relocation and a LO relocation. Each relocation
778 has only 16 bits of space to store an addend. This means that in
779 order for the linker to handle carries correctly, it must be able
780 to locate both the HI and the LO relocation. This means that the
781 relocations must appear in order in the relocation table.
783 In order to implement this, we keep track of each unmatched HI
784 relocation. We then sort them so that they immediately precede the
785 corresponding LO relocation. */
790 struct mips_hi_fixup *next;
793 /* The section this fixup is in. */
797 /* The list of unmatched HI relocs. */
799 static struct mips_hi_fixup *mips_hi_fixup_list;
801 /* The frag containing the last explicit relocation operator.
802 Null if explicit relocations have not been used. */
804 static fragS *prev_reloc_op_frag;
806 /* Map normal MIPS register numbers to mips16 register numbers. */
808 #define X ILLEGAL_REG
809 static const int mips32_to_16_reg_map[] =
811 X, X, 2, 3, 4, 5, 6, 7,
812 X, X, X, X, X, X, X, X,
813 0, 1, X, X, X, X, X, X,
814 X, X, X, X, X, X, X, X
818 /* Map mips16 register numbers to normal MIPS register numbers. */
820 static const unsigned int mips16_to_32_reg_map[] =
822 16, 17, 2, 3, 4, 5, 6, 7
825 /* Map normal MIPS register numbers to microMIPS register numbers. */
827 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
828 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
829 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
830 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
831 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
832 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
833 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
835 #define X ILLEGAL_REG
836 /* reg type h: 4, 5, 6. */
837 static const int mips32_to_micromips_reg_h_map[] =
839 X, X, X, X, 4, 5, 6, X,
840 X, X, X, X, X, X, X, X,
841 X, X, X, X, X, X, X, X,
842 X, X, X, X, X, X, X, X
845 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
846 static const int mips32_to_micromips_reg_m_map[] =
848 0, X, 2, 3, X, X, X, X,
849 X, X, X, X, X, X, X, X,
850 4, 1, 5, 6, 7, X, X, X,
851 X, X, X, X, X, X, X, X
854 /* reg type q: 0, 2-7. 17. */
855 static const int mips32_to_micromips_reg_q_map[] =
857 0, X, 2, 3, 4, 5, 6, 7,
858 X, X, X, X, X, X, X, X,
859 X, 1, X, X, X, X, X, X,
860 X, X, X, X, X, X, X, X
863 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
866 /* Map microMIPS register numbers to normal MIPS register numbers. */
868 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
869 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
870 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
871 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
872 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
873 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
875 /* The microMIPS registers with type h. */
876 static const unsigned int micromips_to_32_reg_h_map[] =
878 5, 5, 6, 4, 4, 4, 4, 4
881 /* The microMIPS registers with type i. */
882 static const unsigned int micromips_to_32_reg_i_map[] =
884 6, 7, 7, 21, 22, 5, 6, 7
887 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
889 /* The microMIPS registers with type m. */
890 static const unsigned int micromips_to_32_reg_m_map[] =
892 0, 17, 2, 3, 16, 18, 19, 20
895 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
897 /* The microMIPS registers with type q. */
898 static const unsigned int micromips_to_32_reg_q_map[] =
900 0, 17, 2, 3, 4, 5, 6, 7
903 /* microMIPS imm type B. */
904 static const int micromips_imm_b_map[] =
906 1, 4, 8, 12, 16, 20, 24, -1
909 /* microMIPS imm type C. */
910 static const int micromips_imm_c_map[] =
912 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
915 /* Classifies the kind of instructions we're interested in when
916 implementing -mfix-vr4120. */
917 enum fix_vr4120_class
925 NUM_FIX_VR4120_CLASSES
928 /* ...likewise -mfix-loongson2f-jump. */
929 static bfd_boolean mips_fix_loongson2f_jump;
931 /* ...likewise -mfix-loongson2f-nop. */
932 static bfd_boolean mips_fix_loongson2f_nop;
934 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
935 static bfd_boolean mips_fix_loongson2f;
937 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
938 there must be at least one other instruction between an instruction
939 of type X and an instruction of type Y. */
940 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
942 /* True if -mfix-vr4120 is in force. */
943 static int mips_fix_vr4120;
945 /* ...likewise -mfix-vr4130. */
946 static int mips_fix_vr4130;
948 /* ...likewise -mfix-24k. */
949 static int mips_fix_24k;
951 /* ...likewise -mfix-cn63xxp1 */
952 static bfd_boolean mips_fix_cn63xxp1;
954 /* We don't relax branches by default, since this causes us to expand
955 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
956 fail to compute the offset before expanding the macro to the most
957 efficient expansion. */
959 static int mips_relax_branch;
961 /* The expansion of many macros depends on the type of symbol that
962 they refer to. For example, when generating position-dependent code,
963 a macro that refers to a symbol may have two different expansions,
964 one which uses GP-relative addresses and one which uses absolute
965 addresses. When generating SVR4-style PIC, a macro may have
966 different expansions for local and global symbols.
968 We handle these situations by generating both sequences and putting
969 them in variant frags. In position-dependent code, the first sequence
970 will be the GP-relative one and the second sequence will be the
971 absolute one. In SVR4 PIC, the first sequence will be for global
972 symbols and the second will be for local symbols.
974 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
975 SECOND are the lengths of the two sequences in bytes. These fields
976 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
977 the subtype has the following flags:
980 Set if it has been decided that we should use the second
981 sequence instead of the first.
984 Set in the first variant frag if the macro's second implementation
985 is longer than its first. This refers to the macro as a whole,
986 not an individual relaxation.
989 Set in the first variant frag if the macro appeared in a .set nomacro
990 block and if one alternative requires a warning but the other does not.
993 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
996 RELAX_DELAY_SLOT_16BIT
997 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1000 RELAX_DELAY_SLOT_SIZE_FIRST
1001 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1002 the macro is of the wrong size for the branch delay slot.
1004 RELAX_DELAY_SLOT_SIZE_SECOND
1005 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1006 the macro is of the wrong size for the branch delay slot.
1008 The frag's "opcode" points to the first fixup for relaxable code.
1010 Relaxable macros are generated using a sequence such as:
1012 relax_start (SYMBOL);
1013 ... generate first expansion ...
1015 ... generate second expansion ...
1018 The code and fixups for the unwanted alternative are discarded
1019 by md_convert_frag. */
1020 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1022 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1023 #define RELAX_SECOND(X) ((X) & 0xff)
1024 #define RELAX_USE_SECOND 0x10000
1025 #define RELAX_SECOND_LONGER 0x20000
1026 #define RELAX_NOMACRO 0x40000
1027 #define RELAX_DELAY_SLOT 0x80000
1028 #define RELAX_DELAY_SLOT_16BIT 0x100000
1029 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1030 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1032 /* Branch without likely bit. If label is out of range, we turn:
1034 beq reg1, reg2, label
1044 with the following opcode replacements:
1051 bltzal <-> bgezal (with jal label instead of j label)
1053 Even though keeping the delay slot instruction in the delay slot of
1054 the branch would be more efficient, it would be very tricky to do
1055 correctly, because we'd have to introduce a variable frag *after*
1056 the delay slot instruction, and expand that instead. Let's do it
1057 the easy way for now, even if the branch-not-taken case now costs
1058 one additional instruction. Out-of-range branches are not supposed
1059 to be common, anyway.
1061 Branch likely. If label is out of range, we turn:
1063 beql reg1, reg2, label
1064 delay slot (annulled if branch not taken)
1073 delay slot (executed only if branch taken)
1076 It would be possible to generate a shorter sequence by losing the
1077 likely bit, generating something like:
1082 delay slot (executed only if branch taken)
1094 bltzall -> bgezal (with jal label instead of j label)
1095 bgezall -> bltzal (ditto)
1098 but it's not clear that it would actually improve performance. */
1099 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1100 ((relax_substateT) \
1103 | ((toofar) ? 0x20 : 0) \
1104 | ((link) ? 0x40 : 0) \
1105 | ((likely) ? 0x80 : 0) \
1106 | ((uncond) ? 0x100 : 0)))
1107 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1108 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1109 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1110 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1111 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1112 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1114 /* For mips16 code, we use an entirely different form of relaxation.
1115 mips16 supports two versions of most instructions which take
1116 immediate values: a small one which takes some small value, and a
1117 larger one which takes a 16 bit value. Since branches also follow
1118 this pattern, relaxing these values is required.
1120 We can assemble both mips16 and normal MIPS code in a single
1121 object. Therefore, we need to support this type of relaxation at
1122 the same time that we support the relaxation described above. We
1123 use the high bit of the subtype field to distinguish these cases.
1125 The information we store for this type of relaxation is the
1126 argument code found in the opcode file for this relocation, whether
1127 the user explicitly requested a small or extended form, and whether
1128 the relocation is in a jump or jal delay slot. That tells us the
1129 size of the value, and how it should be stored. We also store
1130 whether the fragment is considered to be extended or not. We also
1131 store whether this is known to be a branch to a different section,
1132 whether we have tried to relax this frag yet, and whether we have
1133 ever extended a PC relative fragment because of a shift count. */
1134 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1137 | ((small) ? 0x100 : 0) \
1138 | ((ext) ? 0x200 : 0) \
1139 | ((dslot) ? 0x400 : 0) \
1140 | ((jal_dslot) ? 0x800 : 0))
1141 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1142 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1143 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1144 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1145 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1146 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1147 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1148 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1149 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1150 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1151 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1152 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1154 /* For microMIPS code, we use relaxation similar to one we use for
1155 MIPS16 code. Some instructions that take immediate values support
1156 two encodings: a small one which takes some small value, and a
1157 larger one which takes a 16 bit value. As some branches also follow
1158 this pattern, relaxing these values is required.
1160 We can assemble both microMIPS and normal MIPS code in a single
1161 object. Therefore, we need to support this type of relaxation at
1162 the same time that we support the relaxation described above. We
1163 use one of the high bits of the subtype field to distinguish these
1166 The information we store for this type of relaxation is the argument
1167 code found in the opcode file for this relocation, the register
1168 selected as the assembler temporary, whether the branch is
1169 unconditional, whether it is compact, whether it stores the link
1170 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1171 branches to a sequence of instructions is enabled, and whether the
1172 displacement of a branch is too large to fit as an immediate argument
1173 of a 16-bit and a 32-bit branch, respectively. */
1174 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1175 relax32, toofar16, toofar32) \
1178 | (((at) & 0x1f) << 8) \
1179 | ((uncond) ? 0x2000 : 0) \
1180 | ((compact) ? 0x4000 : 0) \
1181 | ((link) ? 0x8000 : 0) \
1182 | ((relax32) ? 0x10000 : 0) \
1183 | ((toofar16) ? 0x20000 : 0) \
1184 | ((toofar32) ? 0x40000 : 0))
1185 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1186 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1187 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1188 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1189 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1190 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1191 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1193 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1195 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1196 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1198 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1200 /* Sign-extend 16-bit value X. */
1201 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1203 /* Is the given value a sign-extended 32-bit value? */
1204 #define IS_SEXT_32BIT_NUM(x) \
1205 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1206 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1208 /* Is the given value a sign-extended 16-bit value? */
1209 #define IS_SEXT_16BIT_NUM(x) \
1210 (((x) &~ (offsetT) 0x7fff) == 0 \
1211 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1213 /* Is the given value a sign-extended 12-bit value? */
1214 #define IS_SEXT_12BIT_NUM(x) \
1215 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1217 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1218 #define IS_ZEXT_32BIT_NUM(x) \
1219 (((x) &~ (offsetT) 0xffffffff) == 0 \
1220 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1222 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1223 VALUE << SHIFT. VALUE is evaluated exactly once. */
1224 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1225 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1226 | (((VALUE) & (MASK)) << (SHIFT)))
1228 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1230 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1231 (((STRUCT) >> (SHIFT)) & (MASK))
1233 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1234 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1236 include/opcode/mips.h specifies operand fields using the macros
1237 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1238 with "MIPS16OP" instead of "OP". */
1239 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1242 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1243 OP_MASK_##FIELD, OP_SH_##FIELD); \
1245 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1248 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1249 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1250 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1252 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1253 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1255 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1256 : EXTRACT_BITS ((INSN).insn_opcode, \
1257 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1258 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1259 EXTRACT_BITS ((INSN).insn_opcode, \
1260 MIPS16OP_MASK_##FIELD, \
1261 MIPS16OP_SH_##FIELD)
1263 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1264 #define MIPS16_EXTEND (0xf000U << 16)
1266 /* Whether or not we are emitting a branch-likely macro. */
1267 static bfd_boolean emit_branch_likely_macro = FALSE;
1269 /* Global variables used when generating relaxable macros. See the
1270 comment above RELAX_ENCODE for more details about how relaxation
1273 /* 0 if we're not emitting a relaxable macro.
1274 1 if we're emitting the first of the two relaxation alternatives.
1275 2 if we're emitting the second alternative. */
1278 /* The first relaxable fixup in the current frag. (In other words,
1279 the first fixup that refers to relaxable code.) */
1282 /* sizes[0] says how many bytes of the first alternative are stored in
1283 the current frag. Likewise sizes[1] for the second alternative. */
1284 unsigned int sizes[2];
1286 /* The symbol on which the choice of sequence depends. */
1290 /* Global variables used to decide whether a macro needs a warning. */
1292 /* True if the macro is in a branch delay slot. */
1293 bfd_boolean delay_slot_p;
1295 /* Set to the length in bytes required if the macro is in a delay slot
1296 that requires a specific length of instruction, otherwise zero. */
1297 unsigned int delay_slot_length;
1299 /* For relaxable macros, sizes[0] is the length of the first alternative
1300 in bytes and sizes[1] is the length of the second alternative.
1301 For non-relaxable macros, both elements give the length of the
1303 unsigned int sizes[2];
1305 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1306 instruction of the first alternative in bytes and first_insn_sizes[1]
1307 is the length of the first instruction of the second alternative.
1308 For non-relaxable macros, both elements give the length of the first
1309 instruction in bytes.
1311 Set to zero if we haven't yet seen the first instruction. */
1312 unsigned int first_insn_sizes[2];
1314 /* For relaxable macros, insns[0] is the number of instructions for the
1315 first alternative and insns[1] is the number of instructions for the
1318 For non-relaxable macros, both elements give the number of
1319 instructions for the macro. */
1320 unsigned int insns[2];
1322 /* The first variant frag for this macro. */
1324 } mips_macro_warning;
1326 /* Prototypes for static functions. */
1328 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1330 static void append_insn
1331 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1332 bfd_boolean expansionp);
1333 static void mips_no_prev_insn (void);
1334 static void macro_build (expressionS *, const char *, const char *, ...);
1335 static void mips16_macro_build
1336 (expressionS *, const char *, const char *, va_list *);
1337 static void load_register (int, expressionS *, int);
1338 static void macro_start (void);
1339 static void macro_end (void);
1340 static void macro (struct mips_cl_insn * ip);
1341 static void mips16_macro (struct mips_cl_insn * ip);
1342 static void mips_ip (char *str, struct mips_cl_insn * ip);
1343 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1344 static void mips16_immed
1345 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1346 unsigned int, unsigned long *);
1347 static size_t my_getSmallExpression
1348 (expressionS *, bfd_reloc_code_real_type *, char *);
1349 static void my_getExpression (expressionS *, char *);
1350 static void s_align (int);
1351 static void s_change_sec (int);
1352 static void s_change_section (int);
1353 static void s_cons (int);
1354 static void s_float_cons (int);
1355 static void s_mips_globl (int);
1356 static void s_option (int);
1357 static void s_mipsset (int);
1358 static void s_abicalls (int);
1359 static void s_cpload (int);
1360 static void s_cpsetup (int);
1361 static void s_cplocal (int);
1362 static void s_cprestore (int);
1363 static void s_cpreturn (int);
1364 static void s_dtprelword (int);
1365 static void s_dtpreldword (int);
1366 static void s_tprelword (int);
1367 static void s_tpreldword (int);
1368 static void s_gpvalue (int);
1369 static void s_gpword (int);
1370 static void s_gpdword (int);
1371 static void s_cpadd (int);
1372 static void s_insn (int);
1373 static void md_obj_begin (void);
1374 static void md_obj_end (void);
1375 static void s_mips_ent (int);
1376 static void s_mips_end (int);
1377 static void s_mips_frame (int);
1378 static void s_mips_mask (int reg_type);
1379 static void s_mips_stab (int);
1380 static void s_mips_weakext (int);
1381 static void s_mips_file (int);
1382 static void s_mips_loc (int);
1383 static bfd_boolean pic_need_relax (symbolS *, asection *);
1384 static int relaxed_branch_length (fragS *, asection *, int);
1385 static int validate_mips_insn (const struct mips_opcode *);
1386 static int validate_micromips_insn (const struct mips_opcode *);
1387 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1388 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1390 /* Table and functions used to map between CPU/ISA names, and
1391 ISA levels, and CPU numbers. */
1393 struct mips_cpu_info
1395 const char *name; /* CPU or ISA name. */
1396 int flags; /* ASEs available, or ISA flag. */
1397 int isa; /* ISA level. */
1398 int cpu; /* CPU number (default CPU if ISA). */
1401 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1402 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1403 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1404 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1405 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1406 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1407 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1408 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1409 #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
1411 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1412 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1413 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1417 The following pseudo-ops from the Kane and Heinrich MIPS book
1418 should be defined here, but are currently unsupported: .alias,
1419 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1421 The following pseudo-ops from the Kane and Heinrich MIPS book are
1422 specific to the type of debugging information being generated, and
1423 should be defined by the object format: .aent, .begin, .bend,
1424 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1427 The following pseudo-ops from the Kane and Heinrich MIPS book are
1428 not MIPS CPU specific, but are also not specific to the object file
1429 format. This file is probably the best place to define them, but
1430 they are not currently supported: .asm0, .endr, .lab, .struct. */
1432 static const pseudo_typeS mips_pseudo_table[] =
1434 /* MIPS specific pseudo-ops. */
1435 {"option", s_option, 0},
1436 {"set", s_mipsset, 0},
1437 {"rdata", s_change_sec, 'r'},
1438 {"sdata", s_change_sec, 's'},
1439 {"livereg", s_ignore, 0},
1440 {"abicalls", s_abicalls, 0},
1441 {"cpload", s_cpload, 0},
1442 {"cpsetup", s_cpsetup, 0},
1443 {"cplocal", s_cplocal, 0},
1444 {"cprestore", s_cprestore, 0},
1445 {"cpreturn", s_cpreturn, 0},
1446 {"dtprelword", s_dtprelword, 0},
1447 {"dtpreldword", s_dtpreldword, 0},
1448 {"tprelword", s_tprelword, 0},
1449 {"tpreldword", s_tpreldword, 0},
1450 {"gpvalue", s_gpvalue, 0},
1451 {"gpword", s_gpword, 0},
1452 {"gpdword", s_gpdword, 0},
1453 {"cpadd", s_cpadd, 0},
1454 {"insn", s_insn, 0},
1456 /* Relatively generic pseudo-ops that happen to be used on MIPS
1458 {"asciiz", stringer, 8 + 1},
1459 {"bss", s_change_sec, 'b'},
1461 {"half", s_cons, 1},
1462 {"dword", s_cons, 3},
1463 {"weakext", s_mips_weakext, 0},
1464 {"origin", s_org, 0},
1465 {"repeat", s_rept, 0},
1467 /* For MIPS this is non-standard, but we define it for consistency. */
1468 {"sbss", s_change_sec, 'B'},
1470 /* These pseudo-ops are defined in read.c, but must be overridden
1471 here for one reason or another. */
1472 {"align", s_align, 0},
1473 {"byte", s_cons, 0},
1474 {"data", s_change_sec, 'd'},
1475 {"double", s_float_cons, 'd'},
1476 {"float", s_float_cons, 'f'},
1477 {"globl", s_mips_globl, 0},
1478 {"global", s_mips_globl, 0},
1479 {"hword", s_cons, 1},
1481 {"long", s_cons, 2},
1482 {"octa", s_cons, 4},
1483 {"quad", s_cons, 3},
1484 {"section", s_change_section, 0},
1485 {"short", s_cons, 1},
1486 {"single", s_float_cons, 'f'},
1487 {"stabd", s_mips_stab, 'd'},
1488 {"stabn", s_mips_stab, 'n'},
1489 {"stabs", s_mips_stab, 's'},
1490 {"text", s_change_sec, 't'},
1491 {"word", s_cons, 2},
1493 { "extern", ecoff_directive_extern, 0},
1498 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1500 /* These pseudo-ops should be defined by the object file format.
1501 However, a.out doesn't support them, so we have versions here. */
1502 {"aent", s_mips_ent, 1},
1503 {"bgnb", s_ignore, 0},
1504 {"end", s_mips_end, 0},
1505 {"endb", s_ignore, 0},
1506 {"ent", s_mips_ent, 0},
1507 {"file", s_mips_file, 0},
1508 {"fmask", s_mips_mask, 'F'},
1509 {"frame", s_mips_frame, 0},
1510 {"loc", s_mips_loc, 0},
1511 {"mask", s_mips_mask, 'R'},
1512 {"verstamp", s_ignore, 0},
1516 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1517 purpose of the `.dc.a' internal pseudo-op. */
1520 mips_address_bytes (void)
1522 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1525 extern void pop_insert (const pseudo_typeS *);
1528 mips_pop_insert (void)
1530 pop_insert (mips_pseudo_table);
1531 if (! ECOFF_DEBUGGING)
1532 pop_insert (mips_nonecoff_pseudo_table);
1535 /* Symbols labelling the current insn. */
1537 struct insn_label_list
1539 struct insn_label_list *next;
1543 static struct insn_label_list *free_insn_labels;
1544 #define label_list tc_segment_info_data.labels
1546 static void mips_clear_insn_labels (void);
1547 static void mips_mark_labels (void);
1548 static void mips_compressed_mark_labels (void);
1551 mips_clear_insn_labels (void)
1553 register struct insn_label_list **pl;
1554 segment_info_type *si;
1558 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1561 si = seg_info (now_seg);
1562 *pl = si->label_list;
1563 si->label_list = NULL;
1567 /* Mark instruction labels in MIPS16/microMIPS mode. */
1570 mips_mark_labels (void)
1572 if (HAVE_CODE_COMPRESSION)
1573 mips_compressed_mark_labels ();
1576 static char *expr_end;
1578 /* Expressions which appear in instructions. These are set by
1581 static expressionS imm_expr;
1582 static expressionS imm2_expr;
1583 static expressionS offset_expr;
1585 /* Relocs associated with imm_expr and offset_expr. */
1587 static bfd_reloc_code_real_type imm_reloc[3]
1588 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1589 static bfd_reloc_code_real_type offset_reloc[3]
1590 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1592 /* This is set to the resulting size of the instruction to be produced
1593 by mips16_ip if an explicit extension is used or by mips_ip if an
1594 explicit size is supplied. */
1596 static unsigned int forced_insn_length;
1598 /* True if we are assembling an instruction. All dot symbols defined during
1599 this time should be treated as code labels. */
1601 static bfd_boolean mips_assembling_insn;
1604 /* The pdr segment for per procedure frame/regmask info. Not used for
1607 static segT pdr_seg;
1610 /* The default target format to use. */
1612 #if defined (TE_FreeBSD)
1613 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1614 #elif defined (TE_TMIPS)
1615 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1617 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1621 mips_target_format (void)
1623 switch (OUTPUT_FLAVOR)
1625 case bfd_target_ecoff_flavour:
1626 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1627 case bfd_target_coff_flavour:
1629 case bfd_target_elf_flavour:
1631 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1632 return (target_big_endian
1633 ? "elf32-bigmips-vxworks"
1634 : "elf32-littlemips-vxworks");
1636 return (target_big_endian
1637 ? (HAVE_64BIT_OBJECTS
1638 ? ELF_TARGET ("elf64-", "big")
1640 ? ELF_TARGET ("elf32-n", "big")
1641 : ELF_TARGET ("elf32-", "big")))
1642 : (HAVE_64BIT_OBJECTS
1643 ? ELF_TARGET ("elf64-", "little")
1645 ? ELF_TARGET ("elf32-n", "little")
1646 : ELF_TARGET ("elf32-", "little"))));
1653 /* Return the length of a microMIPS instruction in bytes. If bits of
1654 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1655 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1656 major opcode) will require further modifications to the opcode
1659 static inline unsigned int
1660 micromips_insn_length (const struct mips_opcode *mo)
1662 return (mo->mask >> 16) == 0 ? 2 : 4;
1665 /* Return the length of MIPS16 instruction OPCODE. */
1667 static inline unsigned int
1668 mips16_opcode_length (unsigned long opcode)
1670 return (opcode >> 16) == 0 ? 2 : 4;
1673 /* Return the length of instruction INSN. */
1675 static inline unsigned int
1676 insn_length (const struct mips_cl_insn *insn)
1678 if (mips_opts.micromips)
1679 return micromips_insn_length (insn->insn_mo);
1680 else if (mips_opts.mips16)
1681 return mips16_opcode_length (insn->insn_opcode);
1686 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1689 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1694 insn->insn_opcode = mo->match;
1697 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1698 insn->fixp[i] = NULL;
1699 insn->fixed_p = (mips_opts.noreorder > 0);
1700 insn->noreorder_p = (mips_opts.noreorder > 0);
1701 insn->mips16_absolute_jump_p = 0;
1702 insn->complete_p = 0;
1703 insn->cleared_p = 0;
1706 /* Record the current MIPS16/microMIPS mode in now_seg. */
1709 mips_record_compressed_mode (void)
1711 segment_info_type *si;
1713 si = seg_info (now_seg);
1714 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1715 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1716 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1717 si->tc_segment_info_data.micromips = mips_opts.micromips;
1720 /* Read a standard MIPS instruction from BUF. */
1722 static unsigned long
1723 read_insn (char *buf)
1725 if (target_big_endian)
1726 return bfd_getb32 ((bfd_byte *) buf);
1728 return bfd_getl32 ((bfd_byte *) buf);
1731 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1735 write_insn (char *buf, unsigned int insn)
1737 md_number_to_chars (buf, insn, 4);
1741 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1742 has length LENGTH. */
1744 static unsigned long
1745 read_compressed_insn (char *buf, unsigned int length)
1751 for (i = 0; i < length; i += 2)
1754 if (target_big_endian)
1755 insn |= bfd_getb16 ((char *) buf);
1757 insn |= bfd_getl16 ((char *) buf);
1763 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1764 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1767 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1771 for (i = 0; i < length; i += 2)
1772 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1773 return buf + length;
1776 /* Install INSN at the location specified by its "frag" and "where" fields. */
1779 install_insn (const struct mips_cl_insn *insn)
1781 char *f = insn->frag->fr_literal + insn->where;
1782 if (HAVE_CODE_COMPRESSION)
1783 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1785 write_insn (f, insn->insn_opcode);
1786 mips_record_compressed_mode ();
1789 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1790 and install the opcode in the new location. */
1793 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1798 insn->where = where;
1799 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1800 if (insn->fixp[i] != NULL)
1802 insn->fixp[i]->fx_frag = frag;
1803 insn->fixp[i]->fx_where = where;
1805 install_insn (insn);
1808 /* Add INSN to the end of the output. */
1811 add_fixed_insn (struct mips_cl_insn *insn)
1813 char *f = frag_more (insn_length (insn));
1814 move_insn (insn, frag_now, f - frag_now->fr_literal);
1817 /* Start a variant frag and move INSN to the start of the variant part,
1818 marking it as fixed. The other arguments are as for frag_var. */
1821 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1822 relax_substateT subtype, symbolS *symbol, offsetT offset)
1824 frag_grow (max_chars);
1825 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1827 frag_var (rs_machine_dependent, max_chars, var,
1828 subtype, symbol, offset, NULL);
1831 /* Insert N copies of INSN into the history buffer, starting at
1832 position FIRST. Neither FIRST nor N need to be clipped. */
1835 insert_into_history (unsigned int first, unsigned int n,
1836 const struct mips_cl_insn *insn)
1838 if (mips_relax.sequence != 2)
1842 for (i = ARRAY_SIZE (history); i-- > first;)
1844 history[i] = history[i - n];
1850 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1851 the idea is to make it obvious at a glance that each errata is
1855 init_vr4120_conflicts (void)
1857 #define CONFLICT(FIRST, SECOND) \
1858 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1860 /* Errata 21 - [D]DIV[U] after [D]MACC */
1861 CONFLICT (MACC, DIV);
1862 CONFLICT (DMACC, DIV);
1864 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1865 CONFLICT (DMULT, DMULT);
1866 CONFLICT (DMULT, DMACC);
1867 CONFLICT (DMACC, DMULT);
1868 CONFLICT (DMACC, DMACC);
1870 /* Errata 24 - MT{LO,HI} after [D]MACC */
1871 CONFLICT (MACC, MTHILO);
1872 CONFLICT (DMACC, MTHILO);
1874 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1875 instruction is executed immediately after a MACC or DMACC
1876 instruction, the result of [either instruction] is incorrect." */
1877 CONFLICT (MACC, MULT);
1878 CONFLICT (MACC, DMULT);
1879 CONFLICT (DMACC, MULT);
1880 CONFLICT (DMACC, DMULT);
1882 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1883 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1884 DDIV or DDIVU instruction, the result of the MACC or
1885 DMACC instruction is incorrect.". */
1886 CONFLICT (DMULT, MACC);
1887 CONFLICT (DMULT, DMACC);
1888 CONFLICT (DIV, MACC);
1889 CONFLICT (DIV, DMACC);
1899 #define RTYPE_MASK 0x1ff00
1900 #define RTYPE_NUM 0x00100
1901 #define RTYPE_FPU 0x00200
1902 #define RTYPE_FCC 0x00400
1903 #define RTYPE_VEC 0x00800
1904 #define RTYPE_GP 0x01000
1905 #define RTYPE_CP0 0x02000
1906 #define RTYPE_PC 0x04000
1907 #define RTYPE_ACC 0x08000
1908 #define RTYPE_CCC 0x10000
1909 #define RNUM_MASK 0x000ff
1910 #define RWARN 0x80000
1912 #define GENERIC_REGISTER_NUMBERS \
1913 {"$0", RTYPE_NUM | 0}, \
1914 {"$1", RTYPE_NUM | 1}, \
1915 {"$2", RTYPE_NUM | 2}, \
1916 {"$3", RTYPE_NUM | 3}, \
1917 {"$4", RTYPE_NUM | 4}, \
1918 {"$5", RTYPE_NUM | 5}, \
1919 {"$6", RTYPE_NUM | 6}, \
1920 {"$7", RTYPE_NUM | 7}, \
1921 {"$8", RTYPE_NUM | 8}, \
1922 {"$9", RTYPE_NUM | 9}, \
1923 {"$10", RTYPE_NUM | 10}, \
1924 {"$11", RTYPE_NUM | 11}, \
1925 {"$12", RTYPE_NUM | 12}, \
1926 {"$13", RTYPE_NUM | 13}, \
1927 {"$14", RTYPE_NUM | 14}, \
1928 {"$15", RTYPE_NUM | 15}, \
1929 {"$16", RTYPE_NUM | 16}, \
1930 {"$17", RTYPE_NUM | 17}, \
1931 {"$18", RTYPE_NUM | 18}, \
1932 {"$19", RTYPE_NUM | 19}, \
1933 {"$20", RTYPE_NUM | 20}, \
1934 {"$21", RTYPE_NUM | 21}, \
1935 {"$22", RTYPE_NUM | 22}, \
1936 {"$23", RTYPE_NUM | 23}, \
1937 {"$24", RTYPE_NUM | 24}, \
1938 {"$25", RTYPE_NUM | 25}, \
1939 {"$26", RTYPE_NUM | 26}, \
1940 {"$27", RTYPE_NUM | 27}, \
1941 {"$28", RTYPE_NUM | 28}, \
1942 {"$29", RTYPE_NUM | 29}, \
1943 {"$30", RTYPE_NUM | 30}, \
1944 {"$31", RTYPE_NUM | 31}
1946 #define FPU_REGISTER_NAMES \
1947 {"$f0", RTYPE_FPU | 0}, \
1948 {"$f1", RTYPE_FPU | 1}, \
1949 {"$f2", RTYPE_FPU | 2}, \
1950 {"$f3", RTYPE_FPU | 3}, \
1951 {"$f4", RTYPE_FPU | 4}, \
1952 {"$f5", RTYPE_FPU | 5}, \
1953 {"$f6", RTYPE_FPU | 6}, \
1954 {"$f7", RTYPE_FPU | 7}, \
1955 {"$f8", RTYPE_FPU | 8}, \
1956 {"$f9", RTYPE_FPU | 9}, \
1957 {"$f10", RTYPE_FPU | 10}, \
1958 {"$f11", RTYPE_FPU | 11}, \
1959 {"$f12", RTYPE_FPU | 12}, \
1960 {"$f13", RTYPE_FPU | 13}, \
1961 {"$f14", RTYPE_FPU | 14}, \
1962 {"$f15", RTYPE_FPU | 15}, \
1963 {"$f16", RTYPE_FPU | 16}, \
1964 {"$f17", RTYPE_FPU | 17}, \
1965 {"$f18", RTYPE_FPU | 18}, \
1966 {"$f19", RTYPE_FPU | 19}, \
1967 {"$f20", RTYPE_FPU | 20}, \
1968 {"$f21", RTYPE_FPU | 21}, \
1969 {"$f22", RTYPE_FPU | 22}, \
1970 {"$f23", RTYPE_FPU | 23}, \
1971 {"$f24", RTYPE_FPU | 24}, \
1972 {"$f25", RTYPE_FPU | 25}, \
1973 {"$f26", RTYPE_FPU | 26}, \
1974 {"$f27", RTYPE_FPU | 27}, \
1975 {"$f28", RTYPE_FPU | 28}, \
1976 {"$f29", RTYPE_FPU | 29}, \
1977 {"$f30", RTYPE_FPU | 30}, \
1978 {"$f31", RTYPE_FPU | 31}
1980 #define FPU_CONDITION_CODE_NAMES \
1981 {"$fcc0", RTYPE_FCC | 0}, \
1982 {"$fcc1", RTYPE_FCC | 1}, \
1983 {"$fcc2", RTYPE_FCC | 2}, \
1984 {"$fcc3", RTYPE_FCC | 3}, \
1985 {"$fcc4", RTYPE_FCC | 4}, \
1986 {"$fcc5", RTYPE_FCC | 5}, \
1987 {"$fcc6", RTYPE_FCC | 6}, \
1988 {"$fcc7", RTYPE_FCC | 7}
1990 #define COPROC_CONDITION_CODE_NAMES \
1991 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1992 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1993 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1994 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1995 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1996 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1997 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1998 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2000 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2001 {"$a4", RTYPE_GP | 8}, \
2002 {"$a5", RTYPE_GP | 9}, \
2003 {"$a6", RTYPE_GP | 10}, \
2004 {"$a7", RTYPE_GP | 11}, \
2005 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2006 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2007 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2008 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2009 {"$t0", RTYPE_GP | 12}, \
2010 {"$t1", RTYPE_GP | 13}, \
2011 {"$t2", RTYPE_GP | 14}, \
2012 {"$t3", RTYPE_GP | 15}
2014 #define O32_SYMBOLIC_REGISTER_NAMES \
2015 {"$t0", RTYPE_GP | 8}, \
2016 {"$t1", RTYPE_GP | 9}, \
2017 {"$t2", RTYPE_GP | 10}, \
2018 {"$t3", RTYPE_GP | 11}, \
2019 {"$t4", RTYPE_GP | 12}, \
2020 {"$t5", RTYPE_GP | 13}, \
2021 {"$t6", RTYPE_GP | 14}, \
2022 {"$t7", RTYPE_GP | 15}, \
2023 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2024 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2025 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2026 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2028 /* Remaining symbolic register names */
2029 #define SYMBOLIC_REGISTER_NAMES \
2030 {"$zero", RTYPE_GP | 0}, \
2031 {"$at", RTYPE_GP | 1}, \
2032 {"$AT", RTYPE_GP | 1}, \
2033 {"$v0", RTYPE_GP | 2}, \
2034 {"$v1", RTYPE_GP | 3}, \
2035 {"$a0", RTYPE_GP | 4}, \
2036 {"$a1", RTYPE_GP | 5}, \
2037 {"$a2", RTYPE_GP | 6}, \
2038 {"$a3", RTYPE_GP | 7}, \
2039 {"$s0", RTYPE_GP | 16}, \
2040 {"$s1", RTYPE_GP | 17}, \
2041 {"$s2", RTYPE_GP | 18}, \
2042 {"$s3", RTYPE_GP | 19}, \
2043 {"$s4", RTYPE_GP | 20}, \
2044 {"$s5", RTYPE_GP | 21}, \
2045 {"$s6", RTYPE_GP | 22}, \
2046 {"$s7", RTYPE_GP | 23}, \
2047 {"$t8", RTYPE_GP | 24}, \
2048 {"$t9", RTYPE_GP | 25}, \
2049 {"$k0", RTYPE_GP | 26}, \
2050 {"$kt0", RTYPE_GP | 26}, \
2051 {"$k1", RTYPE_GP | 27}, \
2052 {"$kt1", RTYPE_GP | 27}, \
2053 {"$gp", RTYPE_GP | 28}, \
2054 {"$sp", RTYPE_GP | 29}, \
2055 {"$s8", RTYPE_GP | 30}, \
2056 {"$fp", RTYPE_GP | 30}, \
2057 {"$ra", RTYPE_GP | 31}
2059 #define MIPS16_SPECIAL_REGISTER_NAMES \
2060 {"$pc", RTYPE_PC | 0}
2062 #define MDMX_VECTOR_REGISTER_NAMES \
2063 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2064 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2065 {"$v2", RTYPE_VEC | 2}, \
2066 {"$v3", RTYPE_VEC | 3}, \
2067 {"$v4", RTYPE_VEC | 4}, \
2068 {"$v5", RTYPE_VEC | 5}, \
2069 {"$v6", RTYPE_VEC | 6}, \
2070 {"$v7", RTYPE_VEC | 7}, \
2071 {"$v8", RTYPE_VEC | 8}, \
2072 {"$v9", RTYPE_VEC | 9}, \
2073 {"$v10", RTYPE_VEC | 10}, \
2074 {"$v11", RTYPE_VEC | 11}, \
2075 {"$v12", RTYPE_VEC | 12}, \
2076 {"$v13", RTYPE_VEC | 13}, \
2077 {"$v14", RTYPE_VEC | 14}, \
2078 {"$v15", RTYPE_VEC | 15}, \
2079 {"$v16", RTYPE_VEC | 16}, \
2080 {"$v17", RTYPE_VEC | 17}, \
2081 {"$v18", RTYPE_VEC | 18}, \
2082 {"$v19", RTYPE_VEC | 19}, \
2083 {"$v20", RTYPE_VEC | 20}, \
2084 {"$v21", RTYPE_VEC | 21}, \
2085 {"$v22", RTYPE_VEC | 22}, \
2086 {"$v23", RTYPE_VEC | 23}, \
2087 {"$v24", RTYPE_VEC | 24}, \
2088 {"$v25", RTYPE_VEC | 25}, \
2089 {"$v26", RTYPE_VEC | 26}, \
2090 {"$v27", RTYPE_VEC | 27}, \
2091 {"$v28", RTYPE_VEC | 28}, \
2092 {"$v29", RTYPE_VEC | 29}, \
2093 {"$v30", RTYPE_VEC | 30}, \
2094 {"$v31", RTYPE_VEC | 31}
2096 #define MIPS_DSP_ACCUMULATOR_NAMES \
2097 {"$ac0", RTYPE_ACC | 0}, \
2098 {"$ac1", RTYPE_ACC | 1}, \
2099 {"$ac2", RTYPE_ACC | 2}, \
2100 {"$ac3", RTYPE_ACC | 3}
2102 static const struct regname reg_names[] = {
2103 GENERIC_REGISTER_NUMBERS,
2105 FPU_CONDITION_CODE_NAMES,
2106 COPROC_CONDITION_CODE_NAMES,
2108 /* The $txx registers depends on the abi,
2109 these will be added later into the symbol table from
2110 one of the tables below once mips_abi is set after
2111 parsing of arguments from the command line. */
2112 SYMBOLIC_REGISTER_NAMES,
2114 MIPS16_SPECIAL_REGISTER_NAMES,
2115 MDMX_VECTOR_REGISTER_NAMES,
2116 MIPS_DSP_ACCUMULATOR_NAMES,
2120 static const struct regname reg_names_o32[] = {
2121 O32_SYMBOLIC_REGISTER_NAMES,
2125 static const struct regname reg_names_n32n64[] = {
2126 N32N64_SYMBOLIC_REGISTER_NAMES,
2130 /* Check if S points at a valid register specifier according to TYPES.
2131 If so, then return 1, advance S to consume the specifier and store
2132 the register's number in REGNOP, otherwise return 0. */
2135 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2142 /* Find end of name. */
2144 if (is_name_beginner (*e))
2146 while (is_part_of_name (*e))
2149 /* Terminate name. */
2153 /* Look for a register symbol. */
2154 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2156 int r = S_GET_VALUE (symbolP);
2158 reg = r & RNUM_MASK;
2159 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2160 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2161 reg = (r & RNUM_MASK) - 2;
2163 /* Else see if this is a register defined in an itbl entry. */
2164 else if ((types & RTYPE_GP) && itbl_have_entries)
2171 if (itbl_get_reg_val (n, &r))
2172 reg = r & RNUM_MASK;
2175 /* Advance to next token if a register was recognised. */
2178 else if (types & RWARN)
2179 as_warn (_("Unrecognized register name `%s'"), *s);
2187 /* Check if S points at a valid register list according to TYPES.
2188 If so, then return 1, advance S to consume the list and store
2189 the registers present on the list as a bitmask of ones in REGLISTP,
2190 otherwise return 0. A valid list comprises a comma-separated
2191 enumeration of valid single registers and/or dash-separated
2192 contiguous register ranges as determined by their numbers.
2194 As a special exception if one of s0-s7 registers is specified as
2195 the range's lower delimiter and s8 (fp) is its upper one, then no
2196 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2197 are selected; they have to be listed separately if needed. */
2200 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2202 unsigned int reglist = 0;
2203 unsigned int lastregno;
2204 bfd_boolean ok = TRUE;
2205 unsigned int regmask;
2206 char *s_endlist = *s;
2210 while (reg_lookup (s, types, ®no))
2216 ok = reg_lookup (s, types, &lastregno);
2217 if (ok && lastregno < regno)
2223 if (lastregno == FP && regno >= S0 && regno <= S7)
2228 regmask = 1 << lastregno;
2229 regmask = (regmask << 1) - 1;
2230 regmask ^= (1 << regno) - 1;
2244 *reglistp = reglist;
2245 return ok && reglist != 0;
2248 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2249 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2252 is_opcode_valid (const struct mips_opcode *mo)
2254 int isa = mips_opts.isa;
2257 if (mips_opts.ase_mdmx)
2259 if (mips_opts.ase_dsp)
2261 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2263 if (mips_opts.ase_dspr2)
2265 if (mips_opts.ase_mt)
2267 if (mips_opts.ase_mips3d)
2269 if (mips_opts.ase_smartmips)
2270 isa |= INSN_SMARTMIPS;
2271 if (mips_opts.ase_mcu)
2273 if (mips_opts.ase_virt)
2275 if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
2278 if (!opcode_is_member (mo, isa, mips_opts.arch))
2281 /* Check whether the instruction or macro requires single-precision or
2282 double-precision floating-point support. Note that this information is
2283 stored differently in the opcode table for insns and macros. */
2284 if (mo->pinfo == INSN_MACRO)
2286 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2287 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2291 fp_s = mo->pinfo & FP_S;
2292 fp_d = mo->pinfo & FP_D;
2295 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2298 if (fp_s && mips_opts.soft_float)
2304 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2305 selected ISA and architecture. */
2308 is_opcode_valid_16 (const struct mips_opcode *mo)
2310 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2313 /* Return TRUE if the size of the microMIPS opcode MO matches one
2314 explicitly requested. Always TRUE in the standard MIPS mode. */
2317 is_size_valid (const struct mips_opcode *mo)
2319 if (!mips_opts.micromips)
2322 if (!forced_insn_length)
2324 if (mo->pinfo == INSN_MACRO)
2326 return forced_insn_length == micromips_insn_length (mo);
2329 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2330 of the preceding instruction. Always TRUE in the standard MIPS mode.
2332 We don't accept macros in 16-bit delay slots to avoid a case where
2333 a macro expansion fails because it relies on a preceding 32-bit real
2334 instruction to have matched and does not handle the operands correctly.
2335 The only macros that may expand to 16-bit instructions are JAL that
2336 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2337 and BGT (that likewise cannot be placed in a delay slot) that decay to
2338 a NOP. In all these cases the macros precede any corresponding real
2339 instruction definitions in the opcode table, so they will match in the
2340 second pass where the size of the delay slot is ignored and therefore
2341 produce correct code. */
2344 is_delay_slot_valid (const struct mips_opcode *mo)
2346 if (!mips_opts.micromips)
2349 if (mo->pinfo == INSN_MACRO)
2350 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2351 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2352 && micromips_insn_length (mo) != 4)
2354 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2355 && micromips_insn_length (mo) != 2)
2361 /* This function is called once, at assembler startup time. It should set up
2362 all the tables, etc. that the MD part of the assembler will need. */
2367 const char *retval = NULL;
2371 if (mips_pic != NO_PIC)
2373 if (g_switch_seen && g_switch_value != 0)
2374 as_bad (_("-G may not be used in position-independent code"));
2378 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2379 as_warn (_("Could not set architecture and machine"));
2381 op_hash = hash_new ();
2383 for (i = 0; i < NUMOPCODES;)
2385 const char *name = mips_opcodes[i].name;
2387 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2390 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2391 mips_opcodes[i].name, retval);
2392 /* Probably a memory allocation problem? Give up now. */
2393 as_fatal (_("Broken assembler. No assembly attempted."));
2397 if (mips_opcodes[i].pinfo != INSN_MACRO)
2399 if (!validate_mips_insn (&mips_opcodes[i]))
2401 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2403 create_insn (&nop_insn, mips_opcodes + i);
2404 if (mips_fix_loongson2f_nop)
2405 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2406 nop_insn.fixed_p = 1;
2411 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2414 mips16_op_hash = hash_new ();
2417 while (i < bfd_mips16_num_opcodes)
2419 const char *name = mips16_opcodes[i].name;
2421 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2423 as_fatal (_("internal: can't hash `%s': %s"),
2424 mips16_opcodes[i].name, retval);
2427 if (mips16_opcodes[i].pinfo != INSN_MACRO
2428 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2429 != mips16_opcodes[i].match))
2431 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2432 mips16_opcodes[i].name, mips16_opcodes[i].args);
2435 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2437 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2438 mips16_nop_insn.fixed_p = 1;
2442 while (i < bfd_mips16_num_opcodes
2443 && strcmp (mips16_opcodes[i].name, name) == 0);
2446 micromips_op_hash = hash_new ();
2449 while (i < bfd_micromips_num_opcodes)
2451 const char *name = micromips_opcodes[i].name;
2453 retval = hash_insert (micromips_op_hash, name,
2454 (void *) µmips_opcodes[i]);
2456 as_fatal (_("internal: can't hash `%s': %s"),
2457 micromips_opcodes[i].name, retval);
2459 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2461 struct mips_cl_insn *micromips_nop_insn;
2463 if (!validate_micromips_insn (µmips_opcodes[i]))
2466 if (micromips_insn_length (micromips_opcodes + i) == 2)
2467 micromips_nop_insn = µmips_nop16_insn;
2468 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2469 micromips_nop_insn = µmips_nop32_insn;
2473 if (micromips_nop_insn->insn_mo == NULL
2474 && strcmp (name, "nop") == 0)
2476 create_insn (micromips_nop_insn, micromips_opcodes + i);
2477 micromips_nop_insn->fixed_p = 1;
2480 while (++i < bfd_micromips_num_opcodes
2481 && strcmp (micromips_opcodes[i].name, name) == 0);
2485 as_fatal (_("Broken assembler. No assembly attempted."));
2487 /* We add all the general register names to the symbol table. This
2488 helps us detect invalid uses of them. */
2489 for (i = 0; reg_names[i].name; i++)
2490 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2491 reg_names[i].num, /* & RNUM_MASK, */
2492 &zero_address_frag));
2494 for (i = 0; reg_names_n32n64[i].name; i++)
2495 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2496 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2497 &zero_address_frag));
2499 for (i = 0; reg_names_o32[i].name; i++)
2500 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2501 reg_names_o32[i].num, /* & RNUM_MASK, */
2502 &zero_address_frag));
2504 mips_no_prev_insn ();
2507 mips_cprmask[0] = 0;
2508 mips_cprmask[1] = 0;
2509 mips_cprmask[2] = 0;
2510 mips_cprmask[3] = 0;
2512 /* set the default alignment for the text section (2**2) */
2513 record_alignment (text_section, 2);
2515 bfd_set_gp_size (stdoutput, g_switch_value);
2520 /* On a native system other than VxWorks, sections must be aligned
2521 to 16 byte boundaries. When configured for an embedded ELF
2522 target, we don't bother. */
2523 if (strncmp (TARGET_OS, "elf", 3) != 0
2524 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2526 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2527 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2528 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2531 /* Create a .reginfo section for register masks and a .mdebug
2532 section for debugging information. */
2540 subseg = now_subseg;
2542 /* The ABI says this section should be loaded so that the
2543 running program can access it. However, we don't load it
2544 if we are configured for an embedded target */
2545 flags = SEC_READONLY | SEC_DATA;
2546 if (strncmp (TARGET_OS, "elf", 3) != 0)
2547 flags |= SEC_ALLOC | SEC_LOAD;
2549 if (mips_abi != N64_ABI)
2551 sec = subseg_new (".reginfo", (subsegT) 0);
2553 bfd_set_section_flags (stdoutput, sec, flags);
2554 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2556 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2560 /* The 64-bit ABI uses a .MIPS.options section rather than
2561 .reginfo section. */
2562 sec = subseg_new (".MIPS.options", (subsegT) 0);
2563 bfd_set_section_flags (stdoutput, sec, flags);
2564 bfd_set_section_alignment (stdoutput, sec, 3);
2566 /* Set up the option header. */
2568 Elf_Internal_Options opthdr;
2571 opthdr.kind = ODK_REGINFO;
2572 opthdr.size = (sizeof (Elf_External_Options)
2573 + sizeof (Elf64_External_RegInfo));
2576 f = frag_more (sizeof (Elf_External_Options));
2577 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2578 (Elf_External_Options *) f);
2580 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2584 if (ECOFF_DEBUGGING)
2586 sec = subseg_new (".mdebug", (subsegT) 0);
2587 (void) bfd_set_section_flags (stdoutput, sec,
2588 SEC_HAS_CONTENTS | SEC_READONLY);
2589 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2591 else if (mips_flag_pdr)
2593 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2594 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2595 SEC_READONLY | SEC_RELOC
2597 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2600 subseg_set (seg, subseg);
2603 #endif /* OBJ_ELF */
2605 if (! ECOFF_DEBUGGING)
2608 if (mips_fix_vr4120)
2609 init_vr4120_conflicts ();
2615 mips_emit_delays ();
2616 if (! ECOFF_DEBUGGING)
2621 md_assemble (char *str)
2623 struct mips_cl_insn insn;
2624 bfd_reloc_code_real_type unused_reloc[3]
2625 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2627 imm_expr.X_op = O_absent;
2628 imm2_expr.X_op = O_absent;
2629 offset_expr.X_op = O_absent;
2630 imm_reloc[0] = BFD_RELOC_UNUSED;
2631 imm_reloc[1] = BFD_RELOC_UNUSED;
2632 imm_reloc[2] = BFD_RELOC_UNUSED;
2633 offset_reloc[0] = BFD_RELOC_UNUSED;
2634 offset_reloc[1] = BFD_RELOC_UNUSED;
2635 offset_reloc[2] = BFD_RELOC_UNUSED;
2637 mips_mark_labels ();
2638 mips_assembling_insn = TRUE;
2640 if (mips_opts.mips16)
2641 mips16_ip (str, &insn);
2644 mips_ip (str, &insn);
2645 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2646 str, insn.insn_opcode));
2650 as_bad ("%s `%s'", insn_error, str);
2651 else if (insn.insn_mo->pinfo == INSN_MACRO)
2654 if (mips_opts.mips16)
2655 mips16_macro (&insn);
2662 if (imm_expr.X_op != O_absent)
2663 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2664 else if (offset_expr.X_op != O_absent)
2665 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2667 append_insn (&insn, NULL, unused_reloc, FALSE);
2670 mips_assembling_insn = FALSE;
2673 /* Convenience functions for abstracting away the differences between
2674 MIPS16 and non-MIPS16 relocations. */
2676 static inline bfd_boolean
2677 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2681 case BFD_RELOC_MIPS16_JMP:
2682 case BFD_RELOC_MIPS16_GPREL:
2683 case BFD_RELOC_MIPS16_GOT16:
2684 case BFD_RELOC_MIPS16_CALL16:
2685 case BFD_RELOC_MIPS16_HI16_S:
2686 case BFD_RELOC_MIPS16_HI16:
2687 case BFD_RELOC_MIPS16_LO16:
2695 static inline bfd_boolean
2696 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2700 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2701 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2702 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2703 case BFD_RELOC_MICROMIPS_GPREL16:
2704 case BFD_RELOC_MICROMIPS_JMP:
2705 case BFD_RELOC_MICROMIPS_HI16:
2706 case BFD_RELOC_MICROMIPS_HI16_S:
2707 case BFD_RELOC_MICROMIPS_LO16:
2708 case BFD_RELOC_MICROMIPS_LITERAL:
2709 case BFD_RELOC_MICROMIPS_GOT16:
2710 case BFD_RELOC_MICROMIPS_CALL16:
2711 case BFD_RELOC_MICROMIPS_GOT_HI16:
2712 case BFD_RELOC_MICROMIPS_GOT_LO16:
2713 case BFD_RELOC_MICROMIPS_CALL_HI16:
2714 case BFD_RELOC_MICROMIPS_CALL_LO16:
2715 case BFD_RELOC_MICROMIPS_SUB:
2716 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2717 case BFD_RELOC_MICROMIPS_GOT_OFST:
2718 case BFD_RELOC_MICROMIPS_GOT_DISP:
2719 case BFD_RELOC_MICROMIPS_HIGHEST:
2720 case BFD_RELOC_MICROMIPS_HIGHER:
2721 case BFD_RELOC_MICROMIPS_SCN_DISP:
2722 case BFD_RELOC_MICROMIPS_JALR:
2730 static inline bfd_boolean
2731 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2733 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2736 static inline bfd_boolean
2737 got16_reloc_p (bfd_reloc_code_real_type reloc)
2739 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2740 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2743 static inline bfd_boolean
2744 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2746 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2747 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2750 static inline bfd_boolean
2751 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2753 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2754 || reloc == BFD_RELOC_MICROMIPS_LO16);
2757 static inline bfd_boolean
2758 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2760 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2763 /* Return true if RELOC is a PC-relative relocation that does not have
2764 full address range. */
2766 static inline bfd_boolean
2767 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
2771 case BFD_RELOC_16_PCREL_S2:
2772 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2773 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2774 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2777 case BFD_RELOC_32_PCREL:
2778 return HAVE_64BIT_ADDRESSES;
2785 /* Return true if the given relocation might need a matching %lo().
2786 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2787 need a matching %lo() when applied to local symbols. */
2789 static inline bfd_boolean
2790 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2792 return (HAVE_IN_PLACE_ADDENDS
2793 && (hi16_reloc_p (reloc)
2794 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2795 all GOT16 relocations evaluate to "G". */
2796 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2799 /* Return the type of %lo() reloc needed by RELOC, given that
2800 reloc_needs_lo_p. */
2802 static inline bfd_reloc_code_real_type
2803 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2805 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2806 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2810 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2813 static inline bfd_boolean
2814 fixup_has_matching_lo_p (fixS *fixp)
2816 return (fixp->fx_next != NULL
2817 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2818 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2819 && fixp->fx_offset == fixp->fx_next->fx_offset);
2822 /* This function returns true if modifying a register requires a
2826 reg_needs_delay (unsigned int reg)
2828 unsigned long prev_pinfo;
2830 prev_pinfo = history[0].insn_mo->pinfo;
2831 if (! mips_opts.noreorder
2832 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2833 && ! gpr_interlocks)
2834 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2835 && ! cop_interlocks)))
2837 /* A load from a coprocessor or from memory. All load delays
2838 delay the use of general register rt for one instruction. */
2839 /* Itbl support may require additional care here. */
2840 know (prev_pinfo & INSN_WRITE_GPR_T);
2841 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2848 /* Move all labels in LABELS to the current insertion point. TEXT_P
2849 says whether the labels refer to text or data. */
2852 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2854 struct insn_label_list *l;
2857 for (l = labels; l != NULL; l = l->next)
2859 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2860 symbol_set_frag (l->label, frag_now);
2861 val = (valueT) frag_now_fix ();
2862 /* MIPS16/microMIPS text labels are stored as odd. */
2863 if (text_p && HAVE_CODE_COMPRESSION)
2865 S_SET_VALUE (l->label, val);
2869 /* Move all labels in insn_labels to the current insertion point
2870 and treat them as text labels. */
2873 mips_move_text_labels (void)
2875 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2879 s_is_linkonce (symbolS *sym, segT from_seg)
2881 bfd_boolean linkonce = FALSE;
2882 segT symseg = S_GET_SEGMENT (sym);
2884 if (symseg != from_seg && !S_IS_LOCAL (sym))
2886 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2889 /* The GNU toolchain uses an extension for ELF: a section
2890 beginning with the magic string .gnu.linkonce is a
2891 linkonce section. */
2892 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2893 sizeof ".gnu.linkonce" - 1) == 0)
2900 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2901 linker to handle them specially, such as generating jalx instructions
2902 when needed. We also make them odd for the duration of the assembly,
2903 in order to generate the right sort of code. We will make them even
2904 in the adjust_symtab routine, while leaving them marked. This is
2905 convenient for the debugger and the disassembler. The linker knows
2906 to make them odd again. */
2909 mips_compressed_mark_label (symbolS *label)
2911 gas_assert (HAVE_CODE_COMPRESSION);
2913 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2916 if (mips_opts.mips16)
2917 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2919 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2922 if ((S_GET_VALUE (label) & 1) == 0
2923 /* Don't adjust the address if the label is global or weak, or
2924 in a link-once section, since we'll be emitting symbol reloc
2925 references to it which will be patched up by the linker, and
2926 the final value of the symbol may or may not be MIPS16/microMIPS. */
2927 && !S_IS_WEAK (label)
2928 && !S_IS_EXTERNAL (label)
2929 && !s_is_linkonce (label, now_seg))
2930 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2933 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2936 mips_compressed_mark_labels (void)
2938 struct insn_label_list *l;
2940 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2941 mips_compressed_mark_label (l->label);
2944 /* End the current frag. Make it a variant frag and record the
2948 relax_close_frag (void)
2950 mips_macro_warning.first_frag = frag_now;
2951 frag_var (rs_machine_dependent, 0, 0,
2952 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2953 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2955 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2956 mips_relax.first_fixup = 0;
2959 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2960 See the comment above RELAX_ENCODE for more details. */
2963 relax_start (symbolS *symbol)
2965 gas_assert (mips_relax.sequence == 0);
2966 mips_relax.sequence = 1;
2967 mips_relax.symbol = symbol;
2970 /* Start generating the second version of a relaxable sequence.
2971 See the comment above RELAX_ENCODE for more details. */
2976 gas_assert (mips_relax.sequence == 1);
2977 mips_relax.sequence = 2;
2980 /* End the current relaxable sequence. */
2985 gas_assert (mips_relax.sequence == 2);
2986 relax_close_frag ();
2987 mips_relax.sequence = 0;
2990 /* Return true if IP is a delayed branch or jump. */
2992 static inline bfd_boolean
2993 delayed_branch_p (const struct mips_cl_insn *ip)
2995 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2996 | INSN_COND_BRANCH_DELAY
2997 | INSN_COND_BRANCH_LIKELY)) != 0;
3000 /* Return true if IP is a compact branch or jump. */
3002 static inline bfd_boolean
3003 compact_branch_p (const struct mips_cl_insn *ip)
3005 if (mips_opts.mips16)
3006 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3007 | MIPS16_INSN_COND_BRANCH)) != 0;
3009 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3010 | INSN2_COND_BRANCH)) != 0;
3013 /* Return true if IP is an unconditional branch or jump. */
3015 static inline bfd_boolean
3016 uncond_branch_p (const struct mips_cl_insn *ip)
3018 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3019 || (mips_opts.mips16
3020 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3021 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3024 /* Return true if IP is a branch-likely instruction. */
3026 static inline bfd_boolean
3027 branch_likely_p (const struct mips_cl_insn *ip)
3029 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3032 /* Return the type of nop that should be used to fill the delay slot
3033 of delayed branch IP. */
3035 static struct mips_cl_insn *
3036 get_delay_slot_nop (const struct mips_cl_insn *ip)
3038 if (mips_opts.micromips
3039 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3040 return µmips_nop32_insn;
3044 /* Return the mask of core registers that IP reads or writes. */
3047 gpr_mod_mask (const struct mips_cl_insn *ip)
3049 unsigned long pinfo2;
3053 pinfo2 = ip->insn_mo->pinfo2;
3054 if (mips_opts.micromips)
3056 if (pinfo2 & INSN2_MOD_GPR_MD)
3057 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3058 if (pinfo2 & INSN2_MOD_GPR_MF)
3059 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3060 if (pinfo2 & INSN2_MOD_SP)
3066 /* Return the mask of core registers that IP reads. */
3069 gpr_read_mask (const struct mips_cl_insn *ip)
3071 unsigned long pinfo, pinfo2;
3074 mask = gpr_mod_mask (ip);
3075 pinfo = ip->insn_mo->pinfo;
3076 pinfo2 = ip->insn_mo->pinfo2;
3077 if (mips_opts.mips16)
3079 if (pinfo & MIPS16_INSN_READ_X)
3080 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3081 if (pinfo & MIPS16_INSN_READ_Y)
3082 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3083 if (pinfo & MIPS16_INSN_READ_T)
3085 if (pinfo & MIPS16_INSN_READ_SP)
3087 if (pinfo & MIPS16_INSN_READ_31)
3089 if (pinfo & MIPS16_INSN_READ_Z)
3090 mask |= 1 << (mips16_to_32_reg_map
3091 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3092 if (pinfo & MIPS16_INSN_READ_GPR_X)
3093 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3097 if (pinfo2 & INSN2_READ_GPR_D)
3098 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3099 if (pinfo & INSN_READ_GPR_T)
3100 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3101 if (pinfo & INSN_READ_GPR_S)
3102 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3103 if (pinfo2 & INSN2_READ_GP)
3105 if (pinfo2 & INSN2_READ_GPR_31)
3107 if (pinfo2 & INSN2_READ_GPR_Z)
3108 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3110 if (mips_opts.micromips)
3112 if (pinfo2 & INSN2_READ_GPR_MC)
3113 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3114 if (pinfo2 & INSN2_READ_GPR_ME)
3115 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3116 if (pinfo2 & INSN2_READ_GPR_MG)
3117 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3118 if (pinfo2 & INSN2_READ_GPR_MJ)
3119 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3120 if (pinfo2 & INSN2_READ_GPR_MMN)
3122 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3123 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3125 if (pinfo2 & INSN2_READ_GPR_MP)
3126 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3127 if (pinfo2 & INSN2_READ_GPR_MQ)
3128 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3130 /* Don't include register 0. */
3134 /* Return the mask of core registers that IP writes. */
3137 gpr_write_mask (const struct mips_cl_insn *ip)
3139 unsigned long pinfo, pinfo2;
3142 mask = gpr_mod_mask (ip);
3143 pinfo = ip->insn_mo->pinfo;
3144 pinfo2 = ip->insn_mo->pinfo2;
3145 if (mips_opts.mips16)
3147 if (pinfo & MIPS16_INSN_WRITE_X)
3148 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3149 if (pinfo & MIPS16_INSN_WRITE_Y)
3150 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3151 if (pinfo & MIPS16_INSN_WRITE_Z)
3152 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3153 if (pinfo & MIPS16_INSN_WRITE_T)
3155 if (pinfo & MIPS16_INSN_WRITE_SP)
3157 if (pinfo & MIPS16_INSN_WRITE_31)
3159 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3160 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3164 if (pinfo & INSN_WRITE_GPR_D)
3165 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3166 if (pinfo & INSN_WRITE_GPR_T)
3167 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3168 if (pinfo & INSN_WRITE_GPR_S)
3169 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3170 if (pinfo & INSN_WRITE_GPR_31)
3172 if (pinfo2 & INSN2_WRITE_GPR_Z)
3173 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3175 if (mips_opts.micromips)
3177 if (pinfo2 & INSN2_WRITE_GPR_MB)
3178 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3179 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3181 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3182 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3184 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3185 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3186 if (pinfo2 & INSN2_WRITE_GPR_MP)
3187 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3189 /* Don't include register 0. */
3193 /* Return the mask of floating-point registers that IP reads. */
3196 fpr_read_mask (const struct mips_cl_insn *ip)
3198 unsigned long pinfo, pinfo2;
3202 pinfo = ip->insn_mo->pinfo;
3203 pinfo2 = ip->insn_mo->pinfo2;
3204 if (!mips_opts.mips16)
3206 if (pinfo2 & INSN2_READ_FPR_D)
3207 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3208 if (pinfo & INSN_READ_FPR_S)
3209 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3210 if (pinfo & INSN_READ_FPR_T)
3211 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3212 if (pinfo & INSN_READ_FPR_R)
3213 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3214 if (pinfo2 & INSN2_READ_FPR_Z)
3215 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3217 /* Conservatively treat all operands to an FP_D instruction are doubles.
3218 (This is overly pessimistic for things like cvt.d.s.) */
3219 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3224 /* Return the mask of floating-point registers that IP writes. */
3227 fpr_write_mask (const struct mips_cl_insn *ip)
3229 unsigned long pinfo, pinfo2;
3233 pinfo = ip->insn_mo->pinfo;
3234 pinfo2 = ip->insn_mo->pinfo2;
3235 if (!mips_opts.mips16)
3237 if (pinfo & INSN_WRITE_FPR_D)
3238 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3239 if (pinfo & INSN_WRITE_FPR_S)
3240 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3241 if (pinfo & INSN_WRITE_FPR_T)
3242 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3243 if (pinfo2 & INSN2_WRITE_FPR_Z)
3244 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3246 /* Conservatively treat all operands to an FP_D instruction are doubles.
3247 (This is overly pessimistic for things like cvt.s.d.) */
3248 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3253 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3254 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3255 by VR4120 errata. */
3258 classify_vr4120_insn (const char *name)
3260 if (strncmp (name, "macc", 4) == 0)
3261 return FIX_VR4120_MACC;
3262 if (strncmp (name, "dmacc", 5) == 0)
3263 return FIX_VR4120_DMACC;
3264 if (strncmp (name, "mult", 4) == 0)
3265 return FIX_VR4120_MULT;
3266 if (strncmp (name, "dmult", 5) == 0)
3267 return FIX_VR4120_DMULT;
3268 if (strstr (name, "div"))
3269 return FIX_VR4120_DIV;
3270 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3271 return FIX_VR4120_MTHILO;
3272 return NUM_FIX_VR4120_CLASSES;
3275 #define INSN_ERET 0x42000018
3276 #define INSN_DERET 0x4200001f
3278 /* Return the number of instructions that must separate INSN1 and INSN2,
3279 where INSN1 is the earlier instruction. Return the worst-case value
3280 for any INSN2 if INSN2 is null. */
3283 insns_between (const struct mips_cl_insn *insn1,
3284 const struct mips_cl_insn *insn2)
3286 unsigned long pinfo1, pinfo2;
3289 /* This function needs to know which pinfo flags are set for INSN2
3290 and which registers INSN2 uses. The former is stored in PINFO2 and
3291 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3292 will have every flag set and INSN2_USES_GPR will always return true. */
3293 pinfo1 = insn1->insn_mo->pinfo;
3294 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3296 #define INSN2_USES_GPR(REG) \
3297 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3299 /* For most targets, write-after-read dependencies on the HI and LO
3300 registers must be separated by at least two instructions. */
3301 if (!hilo_interlocks)
3303 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3305 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3309 /* If we're working around r7000 errata, there must be two instructions
3310 between an mfhi or mflo and any instruction that uses the result. */
3311 if (mips_7000_hilo_fix
3312 && !mips_opts.micromips
3313 && MF_HILO_INSN (pinfo1)
3314 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3317 /* If we're working around 24K errata, one instruction is required
3318 if an ERET or DERET is followed by a branch instruction. */
3319 if (mips_fix_24k && !mips_opts.micromips)
3321 if (insn1->insn_opcode == INSN_ERET
3322 || insn1->insn_opcode == INSN_DERET)
3325 || insn2->insn_opcode == INSN_ERET
3326 || insn2->insn_opcode == INSN_DERET
3327 || delayed_branch_p (insn2))
3332 /* If working around VR4120 errata, check for combinations that need
3333 a single intervening instruction. */
3334 if (mips_fix_vr4120 && !mips_opts.micromips)
3336 unsigned int class1, class2;
3338 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3339 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3343 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3344 if (vr4120_conflicts[class1] & (1 << class2))
3349 if (!HAVE_CODE_COMPRESSION)
3351 /* Check for GPR or coprocessor load delays. All such delays
3352 are on the RT register. */
3353 /* Itbl support may require additional care here. */
3354 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3355 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3357 know (pinfo1 & INSN_WRITE_GPR_T);
3358 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3362 /* Check for generic coprocessor hazards.
3364 This case is not handled very well. There is no special
3365 knowledge of CP0 handling, and the coprocessors other than
3366 the floating point unit are not distinguished at all. */
3367 /* Itbl support may require additional care here. FIXME!
3368 Need to modify this to include knowledge about
3369 user specified delays! */
3370 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3371 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3373 /* Handle cases where INSN1 writes to a known general coprocessor
3374 register. There must be a one instruction delay before INSN2
3375 if INSN2 reads that register, otherwise no delay is needed. */
3376 mask = fpr_write_mask (insn1);
3379 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3384 /* Read-after-write dependencies on the control registers
3385 require a two-instruction gap. */
3386 if ((pinfo1 & INSN_WRITE_COND_CODE)
3387 && (pinfo2 & INSN_READ_COND_CODE))
3390 /* We don't know exactly what INSN1 does. If INSN2 is
3391 also a coprocessor instruction, assume there must be
3392 a one instruction gap. */
3393 if (pinfo2 & INSN_COP)
3398 /* Check for read-after-write dependencies on the coprocessor
3399 control registers in cases where INSN1 does not need a general
3400 coprocessor delay. This means that INSN1 is a floating point
3401 comparison instruction. */
3402 /* Itbl support may require additional care here. */
3403 else if (!cop_interlocks
3404 && (pinfo1 & INSN_WRITE_COND_CODE)
3405 && (pinfo2 & INSN_READ_COND_CODE))
3409 #undef INSN2_USES_GPR
3414 /* Return the number of nops that would be needed to work around the
3415 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3416 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3417 that are contained within the first IGNORE instructions of HIST. */
3420 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3421 const struct mips_cl_insn *insn)
3426 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3427 are not affected by the errata. */
3429 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3430 || strcmp (insn->insn_mo->name, "mtlo") == 0
3431 || strcmp (insn->insn_mo->name, "mthi") == 0))
3434 /* Search for the first MFLO or MFHI. */
3435 for (i = 0; i < MAX_VR4130_NOPS; i++)
3436 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3438 /* Extract the destination register. */
3439 mask = gpr_write_mask (&hist[i]);
3441 /* No nops are needed if INSN reads that register. */
3442 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3445 /* ...or if any of the intervening instructions do. */
3446 for (j = 0; j < i; j++)
3447 if (gpr_read_mask (&hist[j]) & mask)
3451 return MAX_VR4130_NOPS - i;
3456 #define BASE_REG_EQ(INSN1, INSN2) \
3457 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3458 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3460 /* Return the minimum alignment for this store instruction. */
3463 fix_24k_align_to (const struct mips_opcode *mo)
3465 if (strcmp (mo->name, "sh") == 0)
3468 if (strcmp (mo->name, "swc1") == 0
3469 || strcmp (mo->name, "swc2") == 0
3470 || strcmp (mo->name, "sw") == 0
3471 || strcmp (mo->name, "sc") == 0
3472 || strcmp (mo->name, "s.s") == 0)
3475 if (strcmp (mo->name, "sdc1") == 0
3476 || strcmp (mo->name, "sdc2") == 0
3477 || strcmp (mo->name, "s.d") == 0)
3484 struct fix_24k_store_info
3486 /* Immediate offset, if any, for this store instruction. */
3488 /* Alignment required by this store instruction. */
3490 /* True for register offsets. */
3491 int register_offset;
3494 /* Comparison function used by qsort. */
3497 fix_24k_sort (const void *a, const void *b)
3499 const struct fix_24k_store_info *pos1 = a;
3500 const struct fix_24k_store_info *pos2 = b;
3502 return (pos1->off - pos2->off);
3505 /* INSN is a store instruction. Try to record the store information
3506 in STINFO. Return false if the information isn't known. */
3509 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3510 const struct mips_cl_insn *insn)
3512 /* The instruction must have a known offset. */
3513 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3516 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3517 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3521 /* Return the number of nops that would be needed to work around the 24k
3522 "lost data on stores during refill" errata if instruction INSN
3523 immediately followed the 2 instructions described by HIST.
3524 Ignore hazards that are contained within the first IGNORE
3525 instructions of HIST.
3527 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3528 for the data cache refills and store data. The following describes
3529 the scenario where the store data could be lost.
3531 * A data cache miss, due to either a load or a store, causing fill
3532 data to be supplied by the memory subsystem
3533 * The first three doublewords of fill data are returned and written
3535 * A sequence of four stores occurs in consecutive cycles around the
3536 final doubleword of the fill:
3540 * Zero, One or more instructions
3543 The four stores A-D must be to different doublewords of the line that
3544 is being filled. The fourth instruction in the sequence above permits
3545 the fill of the final doubleword to be transferred from the FSB into
3546 the cache. In the sequence above, the stores may be either integer
3547 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3548 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3549 different doublewords on the line. If the floating point unit is
3550 running in 1:2 mode, it is not possible to create the sequence above
3551 using only floating point store instructions.
3553 In this case, the cache line being filled is incorrectly marked
3554 invalid, thereby losing the data from any store to the line that
3555 occurs between the original miss and the completion of the five
3556 cycle sequence shown above.
3558 The workarounds are:
3560 * Run the data cache in write-through mode.
3561 * Insert a non-store instruction between
3562 Store A and Store B or Store B and Store C. */
3565 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3566 const struct mips_cl_insn *insn)
3568 struct fix_24k_store_info pos[3];
3569 int align, i, base_offset;
3574 /* If the previous instruction wasn't a store, there's nothing to
3576 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3579 /* If the instructions after the previous one are unknown, we have
3580 to assume the worst. */
3584 /* Check whether we are dealing with three consecutive stores. */
3585 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3586 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3589 /* If we don't know the relationship between the store addresses,
3590 assume the worst. */
3591 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3592 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3595 if (!fix_24k_record_store_info (&pos[0], insn)
3596 || !fix_24k_record_store_info (&pos[1], &hist[0])
3597 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3600 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3602 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3603 X bytes and such that the base register + X is known to be aligned
3606 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3610 align = pos[0].align_to;
3611 base_offset = pos[0].off;
3612 for (i = 1; i < 3; i++)
3613 if (align < pos[i].align_to)
3615 align = pos[i].align_to;
3616 base_offset = pos[i].off;
3618 for (i = 0; i < 3; i++)
3619 pos[i].off -= base_offset;
3622 pos[0].off &= ~align + 1;
3623 pos[1].off &= ~align + 1;
3624 pos[2].off &= ~align + 1;
3626 /* If any two stores write to the same chunk, they also write to the
3627 same doubleword. The offsets are still sorted at this point. */
3628 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3631 /* A range of at least 9 bytes is needed for the stores to be in
3632 non-overlapping doublewords. */
3633 if (pos[2].off - pos[0].off <= 8)
3636 if (pos[2].off - pos[1].off >= 24
3637 || pos[1].off - pos[0].off >= 24
3638 || pos[2].off - pos[0].off >= 32)
3644 /* Return the number of nops that would be needed if instruction INSN
3645 immediately followed the MAX_NOPS instructions given by HIST,
3646 where HIST[0] is the most recent instruction. Ignore hazards
3647 between INSN and the first IGNORE instructions in HIST.
3649 If INSN is null, return the worse-case number of nops for any
3653 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3654 const struct mips_cl_insn *insn)
3656 int i, nops, tmp_nops;
3659 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3661 tmp_nops = insns_between (hist + i, insn) - i;
3662 if (tmp_nops > nops)
3666 if (mips_fix_vr4130 && !mips_opts.micromips)
3668 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3669 if (tmp_nops > nops)
3673 if (mips_fix_24k && !mips_opts.micromips)
3675 tmp_nops = nops_for_24k (ignore, hist, insn);
3676 if (tmp_nops > nops)
3683 /* The variable arguments provide NUM_INSNS extra instructions that
3684 might be added to HIST. Return the largest number of nops that
3685 would be needed after the extended sequence, ignoring hazards
3686 in the first IGNORE instructions. */
3689 nops_for_sequence (int num_insns, int ignore,
3690 const struct mips_cl_insn *hist, ...)
3693 struct mips_cl_insn buffer[MAX_NOPS];
3694 struct mips_cl_insn *cursor;
3697 va_start (args, hist);
3698 cursor = buffer + num_insns;
3699 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3700 while (cursor > buffer)
3701 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3703 nops = nops_for_insn (ignore, buffer, NULL);
3708 /* Like nops_for_insn, but if INSN is a branch, take into account the
3709 worst-case delay for the branch target. */
3712 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3713 const struct mips_cl_insn *insn)
3717 nops = nops_for_insn (ignore, hist, insn);
3718 if (delayed_branch_p (insn))
3720 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3721 hist, insn, get_delay_slot_nop (insn));
3722 if (tmp_nops > nops)
3725 else if (compact_branch_p (insn))
3727 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3728 if (tmp_nops > nops)
3734 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3737 fix_loongson2f_nop (struct mips_cl_insn * ip)
3739 gas_assert (!HAVE_CODE_COMPRESSION);
3740 if (strcmp (ip->insn_mo->name, "nop") == 0)
3741 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3744 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3745 jr target pc &= 'hffff_ffff_cfff_ffff. */
3748 fix_loongson2f_jump (struct mips_cl_insn * ip)
3750 gas_assert (!HAVE_CODE_COMPRESSION);
3751 if (strcmp (ip->insn_mo->name, "j") == 0
3752 || strcmp (ip->insn_mo->name, "jr") == 0
3753 || strcmp (ip->insn_mo->name, "jalr") == 0)
3761 sreg = EXTRACT_OPERAND (0, RS, *ip);
3762 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3765 ep.X_op = O_constant;
3766 ep.X_add_number = 0xcfff0000;
3767 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3768 ep.X_add_number = 0xffff;
3769 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3770 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3775 fix_loongson2f (struct mips_cl_insn * ip)
3777 if (mips_fix_loongson2f_nop)
3778 fix_loongson2f_nop (ip);
3780 if (mips_fix_loongson2f_jump)
3781 fix_loongson2f_jump (ip);
3784 /* IP is a branch that has a delay slot, and we need to fill it
3785 automatically. Return true if we can do that by swapping IP
3786 with the previous instruction.
3787 ADDRESS_EXPR is an operand of the instruction to be used with
3791 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3792 bfd_reloc_code_real_type *reloc_type)
3794 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3795 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3797 /* -O2 and above is required for this optimization. */
3798 if (mips_optimize < 2)
3801 /* If we have seen .set volatile or .set nomove, don't optimize. */
3802 if (mips_opts.nomove)
3805 /* We can't swap if the previous instruction's position is fixed. */
3806 if (history[0].fixed_p)
3809 /* If the previous previous insn was in a .set noreorder, we can't
3810 swap. Actually, the MIPS assembler will swap in this situation.
3811 However, gcc configured -with-gnu-as will generate code like
3819 in which we can not swap the bne and INSN. If gcc is not configured
3820 -with-gnu-as, it does not output the .set pseudo-ops. */
3821 if (history[1].noreorder_p)
3824 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3825 This means that the previous instruction was a 4-byte one anyhow. */
3826 if (mips_opts.mips16 && history[0].fixp[0])
3829 /* If the branch is itself the target of a branch, we can not swap.
3830 We cheat on this; all we check for is whether there is a label on
3831 this instruction. If there are any branches to anything other than
3832 a label, users must use .set noreorder. */
3833 if (seg_info (now_seg)->label_list)
3836 /* If the previous instruction is in a variant frag other than this
3837 branch's one, we cannot do the swap. This does not apply to
3838 MIPS16 code, which uses variant frags for different purposes. */
3839 if (!mips_opts.mips16
3841 && history[0].frag->fr_type == rs_machine_dependent)
3844 /* We do not swap with instructions that cannot architecturally
3845 be placed in a branch delay slot, such as SYNC or ERET. We
3846 also refrain from swapping with a trap instruction, since it
3847 complicates trap handlers to have the trap instruction be in
3849 prev_pinfo = history[0].insn_mo->pinfo;
3850 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3853 /* Check for conflicts between the branch and the instructions
3854 before the candidate delay slot. */
3855 if (nops_for_insn (0, history + 1, ip) > 0)
3858 /* Check for conflicts between the swapped sequence and the
3859 target of the branch. */
3860 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3863 /* If the branch reads a register that the previous
3864 instruction sets, we can not swap. */
3865 gpr_read = gpr_read_mask (ip);
3866 prev_gpr_write = gpr_write_mask (&history[0]);
3867 if (gpr_read & prev_gpr_write)
3870 /* If the branch writes a register that the previous
3871 instruction sets, we can not swap. */
3872 gpr_write = gpr_write_mask (ip);
3873 if (gpr_write & prev_gpr_write)
3876 /* If the branch writes a register that the previous
3877 instruction reads, we can not swap. */
3878 prev_gpr_read = gpr_read_mask (&history[0]);
3879 if (gpr_write & prev_gpr_read)
3882 /* If one instruction sets a condition code and the
3883 other one uses a condition code, we can not swap. */
3884 pinfo = ip->insn_mo->pinfo;
3885 if ((pinfo & INSN_READ_COND_CODE)
3886 && (prev_pinfo & INSN_WRITE_COND_CODE))
3888 if ((pinfo & INSN_WRITE_COND_CODE)
3889 && (prev_pinfo & INSN_READ_COND_CODE))
3892 /* If the previous instruction uses the PC, we can not swap. */
3893 prev_pinfo2 = history[0].insn_mo->pinfo2;
3894 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3896 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3899 /* If the previous instruction has an incorrect size for a fixed
3900 branch delay slot in microMIPS mode, we cannot swap. */
3901 pinfo2 = ip->insn_mo->pinfo2;
3902 if (mips_opts.micromips
3903 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3904 && insn_length (history) != 2)
3906 if (mips_opts.micromips
3907 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3908 && insn_length (history) != 4)
3911 /* On R5900 short loops need to be fixed by inserting a nop in
3912 the branch delay slots.
3913 A short loop can be terminated too early. */
3914 if (mips_opts.arch == CPU_R5900
3915 /* Check if instruction has a parameter, ignore "j $31". */
3916 && (address_expr != NULL)
3917 /* Parameter must be 16 bit. */
3918 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3919 /* Branch to same segment. */
3920 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3921 /* Branch to same code fragment. */
3922 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3923 /* Can only calculate branch offset if value is known. */
3924 && symbol_constant_p(address_expr->X_add_symbol)
3925 /* Check if branch is really conditional. */
3926 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3927 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3928 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3931 /* Check if loop is shorter than 6 instructions including
3932 branch and delay slot. */
3933 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3940 /* When the loop includes branches or jumps,
3941 it is not a short loop. */
3942 for (i = 0; i < (distance / 4); i++)
3944 if ((history[i].cleared_p)
3945 || delayed_branch_p(&history[i]))
3953 /* Insert nop after branch to fix short loop. */
3962 /* Decide how we should add IP to the instruction stream.
3963 ADDRESS_EXPR is an operand of the instruction to be used with
3966 static enum append_method
3967 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3968 bfd_reloc_code_real_type *reloc_type)
3970 unsigned long pinfo;
3972 /* The relaxed version of a macro sequence must be inherently
3974 if (mips_relax.sequence == 2)
3977 /* We must not dabble with instructions in a ".set norerorder" block. */
3978 if (mips_opts.noreorder)
3981 /* Otherwise, it's our responsibility to fill branch delay slots. */
3982 if (delayed_branch_p (ip))
3984 if (!branch_likely_p (ip)
3985 && can_swap_branch_p (ip, address_expr, reloc_type))
3988 pinfo = ip->insn_mo->pinfo;
3989 if (mips_opts.mips16
3990 && ISA_SUPPORTS_MIPS16E
3991 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3992 return APPEND_ADD_COMPACT;
3994 return APPEND_ADD_WITH_NOP;
4000 /* IP is a MIPS16 instruction whose opcode we have just changed.
4001 Point IP->insn_mo to the new opcode's definition. */
4004 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4006 const struct mips_opcode *mo, *end;
4008 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4009 for (mo = ip->insn_mo; mo < end; mo++)
4010 if ((ip->insn_opcode & mo->mask) == mo->match)
4018 /* For microMIPS macros, we need to generate a local number label
4019 as the target of branches. */
4020 #define MICROMIPS_LABEL_CHAR '\037'
4021 static unsigned long micromips_target_label;
4022 static char micromips_target_name[32];
4025 micromips_label_name (void)
4027 char *p = micromips_target_name;
4028 char symbol_name_temporary[24];
4036 l = micromips_target_label;
4037 #ifdef LOCAL_LABEL_PREFIX
4038 *p++ = LOCAL_LABEL_PREFIX;
4041 *p++ = MICROMIPS_LABEL_CHAR;
4044 symbol_name_temporary[i++] = l % 10 + '0';
4049 *p++ = symbol_name_temporary[--i];
4052 return micromips_target_name;
4056 micromips_label_expr (expressionS *label_expr)
4058 label_expr->X_op = O_symbol;
4059 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4060 label_expr->X_add_number = 0;
4064 micromips_label_inc (void)
4066 micromips_target_label++;
4067 *micromips_target_name = '\0';
4071 micromips_add_label (void)
4075 s = colon (micromips_label_name ());
4076 micromips_label_inc ();
4077 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4079 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4085 /* If assembling microMIPS code, then return the microMIPS reloc
4086 corresponding to the requested one if any. Otherwise return
4087 the reloc unchanged. */
4089 static bfd_reloc_code_real_type
4090 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4092 static const bfd_reloc_code_real_type relocs[][2] =
4094 /* Keep sorted incrementally by the left-hand key. */
4095 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4096 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4097 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4098 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4099 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4100 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4101 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4102 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4103 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4104 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4105 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4106 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4107 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4108 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4109 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4110 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4111 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4112 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4113 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4114 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4115 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4116 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4117 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4118 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4119 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4120 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4121 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4123 bfd_reloc_code_real_type r;
4126 if (!mips_opts.micromips)
4128 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4134 return relocs[i][1];
4139 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4140 Return true on success, storing the resolved value in RESULT. */
4143 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4148 case BFD_RELOC_MIPS_HIGHEST:
4149 case BFD_RELOC_MICROMIPS_HIGHEST:
4150 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4153 case BFD_RELOC_MIPS_HIGHER:
4154 case BFD_RELOC_MICROMIPS_HIGHER:
4155 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4158 case BFD_RELOC_HI16_S:
4159 case BFD_RELOC_MICROMIPS_HI16_S:
4160 case BFD_RELOC_MIPS16_HI16_S:
4161 *result = ((operand + 0x8000) >> 16) & 0xffff;
4164 case BFD_RELOC_HI16:
4165 case BFD_RELOC_MICROMIPS_HI16:
4166 case BFD_RELOC_MIPS16_HI16:
4167 *result = (operand >> 16) & 0xffff;
4170 case BFD_RELOC_LO16:
4171 case BFD_RELOC_MICROMIPS_LO16:
4172 case BFD_RELOC_MIPS16_LO16:
4173 *result = operand & 0xffff;
4176 case BFD_RELOC_UNUSED:
4185 /* Output an instruction. IP is the instruction information.
4186 ADDRESS_EXPR is an operand of the instruction to be used with
4187 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4188 a macro expansion. */
4191 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4192 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4194 unsigned long prev_pinfo2, pinfo;
4195 bfd_boolean relaxed_branch = FALSE;
4196 enum append_method method;
4197 bfd_boolean relax32;
4200 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4201 fix_loongson2f (ip);
4203 file_ase_mips16 |= mips_opts.mips16;
4204 file_ase_micromips |= mips_opts.micromips;
4206 prev_pinfo2 = history[0].insn_mo->pinfo2;
4207 pinfo = ip->insn_mo->pinfo;
4209 if (mips_opts.micromips
4211 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4212 && micromips_insn_length (ip->insn_mo) != 2)
4213 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4214 && micromips_insn_length (ip->insn_mo) != 4)))
4215 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4216 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4218 if (address_expr == NULL)
4220 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4221 && reloc_type[1] == BFD_RELOC_UNUSED
4222 && reloc_type[2] == BFD_RELOC_UNUSED
4223 && address_expr->X_op == O_constant)
4225 switch (*reloc_type)
4227 case BFD_RELOC_MIPS_JMP:
4231 shift = mips_opts.micromips ? 1 : 2;
4232 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4233 as_bad (_("jump to misaligned address (0x%lx)"),
4234 (unsigned long) address_expr->X_add_number);
4235 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4241 case BFD_RELOC_MIPS16_JMP:
4242 if ((address_expr->X_add_number & 3) != 0)
4243 as_bad (_("jump to misaligned address (0x%lx)"),
4244 (unsigned long) address_expr->X_add_number);
4246 (((address_expr->X_add_number & 0x7c0000) << 3)
4247 | ((address_expr->X_add_number & 0xf800000) >> 7)
4248 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4252 case BFD_RELOC_16_PCREL_S2:
4256 shift = mips_opts.micromips ? 1 : 2;
4257 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4258 as_bad (_("branch to misaligned address (0x%lx)"),
4259 (unsigned long) address_expr->X_add_number);
4260 if (!mips_relax_branch)
4262 if ((address_expr->X_add_number + (1 << (shift + 15)))
4263 & ~((1 << (shift + 16)) - 1))
4264 as_bad (_("branch address range overflow (0x%lx)"),
4265 (unsigned long) address_expr->X_add_number);
4266 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4276 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4279 ip->insn_opcode |= value & 0xffff;
4287 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4289 /* There are a lot of optimizations we could do that we don't.
4290 In particular, we do not, in general, reorder instructions.
4291 If you use gcc with optimization, it will reorder
4292 instructions and generally do much more optimization then we
4293 do here; repeating all that work in the assembler would only
4294 benefit hand written assembly code, and does not seem worth
4296 int nops = (mips_optimize == 0
4297 ? nops_for_insn (0, history, NULL)
4298 : nops_for_insn_or_target (0, history, ip));
4302 unsigned long old_frag_offset;
4305 old_frag = frag_now;
4306 old_frag_offset = frag_now_fix ();
4308 for (i = 0; i < nops; i++)
4309 add_fixed_insn (NOP_INSN);
4310 insert_into_history (0, nops, NOP_INSN);
4314 listing_prev_line ();
4315 /* We may be at the start of a variant frag. In case we
4316 are, make sure there is enough space for the frag
4317 after the frags created by listing_prev_line. The
4318 argument to frag_grow here must be at least as large
4319 as the argument to all other calls to frag_grow in
4320 this file. We don't have to worry about being in the
4321 middle of a variant frag, because the variants insert
4322 all needed nop instructions themselves. */
4326 mips_move_text_labels ();
4328 #ifndef NO_ECOFF_DEBUGGING
4329 if (ECOFF_DEBUGGING)
4330 ecoff_fix_loc (old_frag, old_frag_offset);
4334 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4338 /* Work out how many nops in prev_nop_frag are needed by IP,
4339 ignoring hazards generated by the first prev_nop_frag_since
4341 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4342 gas_assert (nops <= prev_nop_frag_holds);
4344 /* Enforce NOPS as a minimum. */
4345 if (nops > prev_nop_frag_required)
4346 prev_nop_frag_required = nops;
4348 if (prev_nop_frag_holds == prev_nop_frag_required)
4350 /* Settle for the current number of nops. Update the history
4351 accordingly (for the benefit of any future .set reorder code). */
4352 prev_nop_frag = NULL;
4353 insert_into_history (prev_nop_frag_since,
4354 prev_nop_frag_holds, NOP_INSN);
4358 /* Allow this instruction to replace one of the nops that was
4359 tentatively added to prev_nop_frag. */
4360 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4361 prev_nop_frag_holds--;
4362 prev_nop_frag_since++;
4366 method = get_append_method (ip, address_expr, reloc_type);
4367 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4370 /* The value passed to dwarf2_emit_insn is the distance between
4371 the beginning of the current instruction and the address that
4372 should be recorded in the debug tables. This is normally the
4375 For MIPS16/microMIPS debug info we want to use ISA-encoded
4376 addresses, so we use -1 for an address higher by one than the
4379 If the instruction produced is a branch that we will swap with
4380 the preceding instruction, then we add the displacement by which
4381 the branch will be moved backwards. This is more appropriate
4382 and for MIPS16/microMIPS code also prevents a debugger from
4383 placing a breakpoint in the middle of the branch (and corrupting
4384 code if software breakpoints are used). */
4385 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4388 relax32 = (mips_relax_branch
4389 /* Don't try branch relaxation within .set nomacro, or within
4390 .set noat if we use $at for PIC computations. If it turns
4391 out that the branch was out-of-range, we'll get an error. */
4392 && !mips_opts.warn_about_macros
4393 && (mips_opts.at || mips_pic == NO_PIC)
4394 /* Don't relax BPOSGE32/64 as they have no complementing
4396 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4398 if (!HAVE_CODE_COMPRESSION
4401 && *reloc_type == BFD_RELOC_16_PCREL_S2
4402 && delayed_branch_p (ip))
4404 relaxed_branch = TRUE;
4405 add_relaxed_insn (ip, (relaxed_branch_length
4407 uncond_branch_p (ip) ? -1
4408 : branch_likely_p (ip) ? 1
4412 uncond_branch_p (ip),
4413 branch_likely_p (ip),
4414 pinfo & INSN_WRITE_GPR_31,
4416 address_expr->X_add_symbol,
4417 address_expr->X_add_number);
4418 *reloc_type = BFD_RELOC_UNUSED;
4420 else if (mips_opts.micromips
4422 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4423 || *reloc_type > BFD_RELOC_UNUSED)
4424 && (delayed_branch_p (ip) || compact_branch_p (ip))
4425 /* Don't try branch relaxation when users specify
4426 16-bit/32-bit instructions. */
4427 && !forced_insn_length)
4429 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4430 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4431 int uncond = uncond_branch_p (ip) ? -1 : 0;
4432 int compact = compact_branch_p (ip);
4433 int al = pinfo & INSN_WRITE_GPR_31;
4436 gas_assert (address_expr != NULL);
4437 gas_assert (!mips_relax.sequence);
4439 relaxed_branch = TRUE;
4440 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4441 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4442 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4444 address_expr->X_add_symbol,
4445 address_expr->X_add_number);
4446 *reloc_type = BFD_RELOC_UNUSED;
4448 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4450 /* We need to set up a variant frag. */
4451 gas_assert (address_expr != NULL);
4452 add_relaxed_insn (ip, 4, 0,
4454 (*reloc_type - BFD_RELOC_UNUSED,
4455 forced_insn_length == 2, forced_insn_length == 4,
4456 delayed_branch_p (&history[0]),
4457 history[0].mips16_absolute_jump_p),
4458 make_expr_symbol (address_expr), 0);
4460 else if (mips_opts.mips16 && insn_length (ip) == 2)
4462 if (!delayed_branch_p (ip))
4463 /* Make sure there is enough room to swap this instruction with
4464 a following jump instruction. */
4466 add_fixed_insn (ip);
4470 if (mips_opts.mips16
4471 && mips_opts.noreorder
4472 && delayed_branch_p (&history[0]))
4473 as_warn (_("extended instruction in delay slot"));
4475 if (mips_relax.sequence)
4477 /* If we've reached the end of this frag, turn it into a variant
4478 frag and record the information for the instructions we've
4480 if (frag_room () < 4)
4481 relax_close_frag ();
4482 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4485 if (mips_relax.sequence != 2)
4487 if (mips_macro_warning.first_insn_sizes[0] == 0)
4488 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4489 mips_macro_warning.sizes[0] += insn_length (ip);
4490 mips_macro_warning.insns[0]++;
4492 if (mips_relax.sequence != 1)
4494 if (mips_macro_warning.first_insn_sizes[1] == 0)
4495 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4496 mips_macro_warning.sizes[1] += insn_length (ip);
4497 mips_macro_warning.insns[1]++;
4500 if (mips_opts.mips16)
4503 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4505 add_fixed_insn (ip);
4508 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4510 bfd_reloc_code_real_type final_type[3];
4511 reloc_howto_type *howto0;
4512 reloc_howto_type *howto;
4515 /* Perform any necessary conversion to microMIPS relocations
4516 and find out how many relocations there actually are. */
4517 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4518 final_type[i] = micromips_map_reloc (reloc_type[i]);
4520 /* In a compound relocation, it is the final (outermost)
4521 operator that determines the relocated field. */
4522 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4526 /* To reproduce this failure try assembling gas/testsuites/
4527 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4529 as_bad (_("Unsupported MIPS relocation number %d"),
4531 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4535 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4536 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4537 bfd_get_reloc_size (howto),
4539 howto0 && howto0->pc_relative,
4542 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4543 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4544 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4546 /* These relocations can have an addend that won't fit in
4547 4 octets for 64bit assembly. */
4549 && ! howto->partial_inplace
4550 && (reloc_type[0] == BFD_RELOC_16
4551 || reloc_type[0] == BFD_RELOC_32
4552 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4553 || reloc_type[0] == BFD_RELOC_GPREL16
4554 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4555 || reloc_type[0] == BFD_RELOC_GPREL32
4556 || reloc_type[0] == BFD_RELOC_64
4557 || reloc_type[0] == BFD_RELOC_CTOR
4558 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4559 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4560 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4561 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4562 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4563 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4564 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4565 || hi16_reloc_p (reloc_type[0])
4566 || lo16_reloc_p (reloc_type[0])))
4567 ip->fixp[0]->fx_no_overflow = 1;
4569 /* These relocations can have an addend that won't fit in 2 octets. */
4570 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4571 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4572 ip->fixp[0]->fx_no_overflow = 1;
4574 if (mips_relax.sequence)
4576 if (mips_relax.first_fixup == 0)
4577 mips_relax.first_fixup = ip->fixp[0];
4579 else if (reloc_needs_lo_p (*reloc_type))
4581 struct mips_hi_fixup *hi_fixup;
4583 /* Reuse the last entry if it already has a matching %lo. */
4584 hi_fixup = mips_hi_fixup_list;
4586 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4588 hi_fixup = ((struct mips_hi_fixup *)
4589 xmalloc (sizeof (struct mips_hi_fixup)));
4590 hi_fixup->next = mips_hi_fixup_list;
4591 mips_hi_fixup_list = hi_fixup;
4593 hi_fixup->fixp = ip->fixp[0];
4594 hi_fixup->seg = now_seg;
4597 /* Add fixups for the second and third relocations, if given.
4598 Note that the ABI allows the second relocation to be
4599 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4600 moment we only use RSS_UNDEF, but we could add support
4601 for the others if it ever becomes necessary. */
4602 for (i = 1; i < 3; i++)
4603 if (reloc_type[i] != BFD_RELOC_UNUSED)
4605 ip->fixp[i] = fix_new (ip->frag, ip->where,
4606 ip->fixp[0]->fx_size, NULL, 0,
4607 FALSE, final_type[i]);
4609 /* Use fx_tcbit to mark compound relocs. */
4610 ip->fixp[0]->fx_tcbit = 1;
4611 ip->fixp[i]->fx_tcbit = 1;
4616 /* Update the register mask information. */
4617 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4618 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4623 insert_into_history (0, 1, ip);
4626 case APPEND_ADD_WITH_NOP:
4628 struct mips_cl_insn *nop;
4630 insert_into_history (0, 1, ip);
4631 nop = get_delay_slot_nop (ip);
4632 add_fixed_insn (nop);
4633 insert_into_history (0, 1, nop);
4634 if (mips_relax.sequence)
4635 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4639 case APPEND_ADD_COMPACT:
4640 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4641 gas_assert (mips_opts.mips16);
4642 ip->insn_opcode |= 0x0080;
4643 find_altered_mips16_opcode (ip);
4645 insert_into_history (0, 1, ip);
4650 struct mips_cl_insn delay = history[0];
4651 if (mips_opts.mips16)
4653 know (delay.frag == ip->frag);
4654 move_insn (ip, delay.frag, delay.where);
4655 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4657 else if (relaxed_branch || delay.frag != ip->frag)
4659 /* Add the delay slot instruction to the end of the
4660 current frag and shrink the fixed part of the
4661 original frag. If the branch occupies the tail of
4662 the latter, move it backwards to cover the gap. */
4663 delay.frag->fr_fix -= branch_disp;
4664 if (delay.frag == ip->frag)
4665 move_insn (ip, ip->frag, ip->where - branch_disp);
4666 add_fixed_insn (&delay);
4670 move_insn (&delay, ip->frag,
4671 ip->where - branch_disp + insn_length (ip));
4672 move_insn (ip, history[0].frag, history[0].where);
4676 insert_into_history (0, 1, &delay);
4681 /* If we have just completed an unconditional branch, clear the history. */
4682 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4683 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4687 mips_no_prev_insn ();
4689 for (i = 0; i < ARRAY_SIZE (history); i++)
4690 history[i].cleared_p = 1;
4693 /* We need to emit a label at the end of branch-likely macros. */
4694 if (emit_branch_likely_macro)
4696 emit_branch_likely_macro = FALSE;
4697 micromips_add_label ();
4700 /* We just output an insn, so the next one doesn't have a label. */
4701 mips_clear_insn_labels ();
4704 /* Forget that there was any previous instruction or label.
4705 When BRANCH is true, the branch history is also flushed. */
4708 mips_no_prev_insn (void)
4710 prev_nop_frag = NULL;
4711 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4712 mips_clear_insn_labels ();
4715 /* This function must be called before we emit something other than
4716 instructions. It is like mips_no_prev_insn except that it inserts
4717 any NOPS that might be needed by previous instructions. */
4720 mips_emit_delays (void)
4722 if (! mips_opts.noreorder)
4724 int nops = nops_for_insn (0, history, NULL);
4728 add_fixed_insn (NOP_INSN);
4729 mips_move_text_labels ();
4732 mips_no_prev_insn ();
4735 /* Start a (possibly nested) noreorder block. */
4738 start_noreorder (void)
4740 if (mips_opts.noreorder == 0)
4745 /* None of the instructions before the .set noreorder can be moved. */
4746 for (i = 0; i < ARRAY_SIZE (history); i++)
4747 history[i].fixed_p = 1;
4749 /* Insert any nops that might be needed between the .set noreorder
4750 block and the previous instructions. We will later remove any
4751 nops that turn out not to be needed. */
4752 nops = nops_for_insn (0, history, NULL);
4755 if (mips_optimize != 0)
4757 /* Record the frag which holds the nop instructions, so
4758 that we can remove them if we don't need them. */
4759 frag_grow (nops * NOP_INSN_SIZE);
4760 prev_nop_frag = frag_now;
4761 prev_nop_frag_holds = nops;
4762 prev_nop_frag_required = 0;
4763 prev_nop_frag_since = 0;
4766 for (; nops > 0; --nops)
4767 add_fixed_insn (NOP_INSN);
4769 /* Move on to a new frag, so that it is safe to simply
4770 decrease the size of prev_nop_frag. */
4771 frag_wane (frag_now);
4773 mips_move_text_labels ();
4775 mips_mark_labels ();
4776 mips_clear_insn_labels ();
4778 mips_opts.noreorder++;
4779 mips_any_noreorder = 1;
4782 /* End a nested noreorder block. */
4785 end_noreorder (void)
4787 mips_opts.noreorder--;
4788 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4790 /* Commit to inserting prev_nop_frag_required nops and go back to
4791 handling nop insertion the .set reorder way. */
4792 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4794 insert_into_history (prev_nop_frag_since,
4795 prev_nop_frag_required, NOP_INSN);
4796 prev_nop_frag = NULL;
4800 /* Set up global variables for the start of a new macro. */
4805 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4806 memset (&mips_macro_warning.first_insn_sizes, 0,
4807 sizeof (mips_macro_warning.first_insn_sizes));
4808 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4809 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4810 && delayed_branch_p (&history[0]));
4811 switch (history[0].insn_mo->pinfo2
4812 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4814 case INSN2_BRANCH_DELAY_32BIT:
4815 mips_macro_warning.delay_slot_length = 4;
4817 case INSN2_BRANCH_DELAY_16BIT:
4818 mips_macro_warning.delay_slot_length = 2;
4821 mips_macro_warning.delay_slot_length = 0;
4824 mips_macro_warning.first_frag = NULL;
4827 /* Given that a macro is longer than one instruction or of the wrong size,
4828 return the appropriate warning for it. Return null if no warning is
4829 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4830 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4831 and RELAX_NOMACRO. */
4834 macro_warning (relax_substateT subtype)
4836 if (subtype & RELAX_DELAY_SLOT)
4837 return _("Macro instruction expanded into multiple instructions"
4838 " in a branch delay slot");
4839 else if (subtype & RELAX_NOMACRO)
4840 return _("Macro instruction expanded into multiple instructions");
4841 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4842 | RELAX_DELAY_SLOT_SIZE_SECOND))
4843 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4844 ? _("Macro instruction expanded into a wrong size instruction"
4845 " in a 16-bit branch delay slot")
4846 : _("Macro instruction expanded into a wrong size instruction"
4847 " in a 32-bit branch delay slot"));
4852 /* Finish up a macro. Emit warnings as appropriate. */
4857 /* Relaxation warning flags. */
4858 relax_substateT subtype = 0;
4860 /* Check delay slot size requirements. */
4861 if (mips_macro_warning.delay_slot_length == 2)
4862 subtype |= RELAX_DELAY_SLOT_16BIT;
4863 if (mips_macro_warning.delay_slot_length != 0)
4865 if (mips_macro_warning.delay_slot_length
4866 != mips_macro_warning.first_insn_sizes[0])
4867 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4868 if (mips_macro_warning.delay_slot_length
4869 != mips_macro_warning.first_insn_sizes[1])
4870 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4873 /* Check instruction count requirements. */
4874 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4876 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4877 subtype |= RELAX_SECOND_LONGER;
4878 if (mips_opts.warn_about_macros)
4879 subtype |= RELAX_NOMACRO;
4880 if (mips_macro_warning.delay_slot_p)
4881 subtype |= RELAX_DELAY_SLOT;
4884 /* If both alternatives fail to fill a delay slot correctly,
4885 emit the warning now. */
4886 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4887 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4892 s = subtype & (RELAX_DELAY_SLOT_16BIT
4893 | RELAX_DELAY_SLOT_SIZE_FIRST
4894 | RELAX_DELAY_SLOT_SIZE_SECOND);
4895 msg = macro_warning (s);
4897 as_warn ("%s", msg);
4901 /* If both implementations are longer than 1 instruction, then emit the
4903 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4908 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4909 msg = macro_warning (s);
4911 as_warn ("%s", msg);
4915 /* If any flags still set, then one implementation might need a warning
4916 and the other either will need one of a different kind or none at all.
4917 Pass any remaining flags over to relaxation. */
4918 if (mips_macro_warning.first_frag != NULL)
4919 mips_macro_warning.first_frag->fr_subtype |= subtype;
4922 /* Instruction operand formats used in macros that vary between
4923 standard MIPS and microMIPS code. */
4925 static const char * const brk_fmt[2] = { "c", "mF" };
4926 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4927 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4928 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4929 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4930 static const char * const mfhl_fmt[2] = { "d", "mj" };
4931 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4932 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4934 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4935 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4936 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4937 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4938 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4939 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4940 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4941 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4943 /* Read a macro's relocation codes from *ARGS and store them in *R.
4944 The first argument in *ARGS will be either the code for a single
4945 relocation or -1 followed by the three codes that make up a
4946 composite relocation. */
4949 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4953 next = va_arg (*args, int);
4955 r[0] = (bfd_reloc_code_real_type) next;
4957 for (i = 0; i < 3; i++)
4958 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4961 /* Build an instruction created by a macro expansion. This is passed
4962 a pointer to the count of instructions created so far, an
4963 expression, the name of the instruction to build, an operand format
4964 string, and corresponding arguments. */
4967 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4969 const struct mips_opcode *mo = NULL;
4970 bfd_reloc_code_real_type r[3];
4971 const struct mips_opcode *amo;
4972 struct hash_control *hash;
4973 struct mips_cl_insn insn;
4976 va_start (args, fmt);
4978 if (mips_opts.mips16)
4980 mips16_macro_build (ep, name, fmt, &args);
4985 r[0] = BFD_RELOC_UNUSED;
4986 r[1] = BFD_RELOC_UNUSED;
4987 r[2] = BFD_RELOC_UNUSED;
4988 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4989 amo = (struct mips_opcode *) hash_find (hash, name);
4991 gas_assert (strcmp (name, amo->name) == 0);
4995 /* Search until we get a match for NAME. It is assumed here that
4996 macros will never generate MDMX, MIPS-3D, or MT instructions.
4997 We try to match an instruction that fulfils the branch delay
4998 slot instruction length requirement (if any) of the previous
4999 instruction. While doing this we record the first instruction
5000 seen that matches all the other conditions and use it anyway
5001 if the requirement cannot be met; we will issue an appropriate
5002 warning later on. */
5003 if (strcmp (fmt, amo->args) == 0
5004 && amo->pinfo != INSN_MACRO
5005 && is_opcode_valid (amo)
5006 && is_size_valid (amo))
5008 if (is_delay_slot_valid (amo))
5018 gas_assert (amo->name);
5020 while (strcmp (name, amo->name) == 0);
5023 create_insn (&insn, mo);
5041 INSERT_OPERAND (mips_opts.micromips,
5042 EXTLSB, insn, va_arg (args, int));
5047 /* Note that in the macro case, these arguments are already
5048 in MSB form. (When handling the instruction in the
5049 non-macro case, these arguments are sizes from which
5050 MSB values must be calculated.) */
5051 INSERT_OPERAND (mips_opts.micromips,
5052 INSMSB, insn, va_arg (args, int));
5056 gas_assert (!mips_opts.micromips);
5057 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5063 /* Note that in the macro case, these arguments are already
5064 in MSBD form. (When handling the instruction in the
5065 non-macro case, these arguments are sizes from which
5066 MSBD values must be calculated.) */
5067 INSERT_OPERAND (mips_opts.micromips,
5068 EXTMSBD, insn, va_arg (args, int));
5072 gas_assert (!mips_opts.micromips);
5073 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5082 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5086 gas_assert (mips_opts.micromips);
5090 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5094 gas_assert (!mips_opts.micromips);
5095 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5099 gas_assert (!mips_opts.micromips);
5101 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5105 if (mips_opts.micromips)
5106 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5108 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5112 gas_assert (!mips_opts.micromips);
5114 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5118 gas_assert (!mips_opts.micromips);
5120 int tmp = va_arg (args, int);
5122 INSERT_OPERAND (0, RT, insn, tmp);
5123 INSERT_OPERAND (0, RD, insn, tmp);
5129 gas_assert (!mips_opts.micromips);
5130 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5137 INSERT_OPERAND (mips_opts.micromips,
5138 SHAMT, insn, va_arg (args, int));
5142 gas_assert (!mips_opts.micromips);
5143 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5147 gas_assert (!mips_opts.micromips);
5148 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5152 gas_assert (!mips_opts.micromips);
5153 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5157 gas_assert (!mips_opts.micromips);
5158 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5165 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5170 macro_read_relocs (&args, r);
5171 gas_assert (*r == BFD_RELOC_GPREL16
5172 || *r == BFD_RELOC_MIPS_HIGHER
5173 || *r == BFD_RELOC_HI16_S
5174 || *r == BFD_RELOC_LO16
5175 || *r == BFD_RELOC_MIPS_GOT_OFST);
5179 macro_read_relocs (&args, r);
5183 macro_read_relocs (&args, r);
5184 gas_assert (ep != NULL
5185 && (ep->X_op == O_constant
5186 || (ep->X_op == O_symbol
5187 && (*r == BFD_RELOC_MIPS_HIGHEST
5188 || *r == BFD_RELOC_HI16_S
5189 || *r == BFD_RELOC_HI16
5190 || *r == BFD_RELOC_GPREL16
5191 || *r == BFD_RELOC_MIPS_GOT_HI16
5192 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5196 gas_assert (ep != NULL);
5199 * This allows macro() to pass an immediate expression for
5200 * creating short branches without creating a symbol.
5202 * We don't allow branch relaxation for these branches, as
5203 * they should only appear in ".set nomacro" anyway.
5205 if (ep->X_op == O_constant)
5207 /* For microMIPS we always use relocations for branches.
5208 So we should not resolve immediate values. */
5209 gas_assert (!mips_opts.micromips);
5211 if ((ep->X_add_number & 3) != 0)
5212 as_bad (_("branch to misaligned address (0x%lx)"),
5213 (unsigned long) ep->X_add_number);
5214 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5215 as_bad (_("branch address range overflow (0x%lx)"),
5216 (unsigned long) ep->X_add_number);
5217 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5221 *r = BFD_RELOC_16_PCREL_S2;
5225 gas_assert (ep != NULL);
5226 *r = BFD_RELOC_MIPS_JMP;
5230 gas_assert (!mips_opts.micromips);
5231 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5235 INSERT_OPERAND (mips_opts.micromips,
5236 CACHE, insn, va_arg (args, unsigned long));
5240 gas_assert (mips_opts.micromips);
5241 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5245 gas_assert (mips_opts.micromips);
5246 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5250 INSERT_OPERAND (mips_opts.micromips,
5251 3BITPOS, insn, va_arg (args, unsigned int));
5255 INSERT_OPERAND (mips_opts.micromips,
5256 OFFSET12, insn, va_arg (args, unsigned long));
5260 gas_assert (mips_opts.micromips);
5261 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5264 case 'm': /* Opcode extension character. */
5265 gas_assert (mips_opts.micromips);
5269 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5273 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5277 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5291 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5293 append_insn (&insn, ep, r, TRUE);
5297 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5300 struct mips_opcode *mo;
5301 struct mips_cl_insn insn;
5302 bfd_reloc_code_real_type r[3]
5303 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5305 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5307 gas_assert (strcmp (name, mo->name) == 0);
5309 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5312 gas_assert (mo->name);
5313 gas_assert (strcmp (name, mo->name) == 0);
5316 create_insn (&insn, mo);
5334 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5339 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5343 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5347 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5357 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5364 regno = va_arg (*args, int);
5365 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5366 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5389 gas_assert (ep != NULL);
5391 if (ep->X_op != O_constant)
5392 *r = (int) BFD_RELOC_UNUSED + c;
5393 else if (calculate_reloc (*r, ep->X_add_number, &value))
5395 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5397 *r = BFD_RELOC_UNUSED;
5403 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5410 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5412 append_insn (&insn, ep, r, TRUE);
5416 * Sign-extend 32-bit mode constants that have bit 31 set and all
5417 * higher bits unset.
5420 normalize_constant_expr (expressionS *ex)
5422 if (ex->X_op == O_constant
5423 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5424 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5429 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5430 * all higher bits unset.
5433 normalize_address_expr (expressionS *ex)
5435 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5436 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5437 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5438 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5443 * Generate a "jalr" instruction with a relocation hint to the called
5444 * function. This occurs in NewABI PIC code.
5447 macro_build_jalr (expressionS *ep, int cprestore)
5449 static const bfd_reloc_code_real_type jalr_relocs[2]
5450 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5451 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5455 if (MIPS_JALR_HINT_P (ep))
5460 if (mips_opts.micromips)
5462 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5463 if (MIPS_JALR_HINT_P (ep)
5464 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5465 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5467 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5470 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5471 if (MIPS_JALR_HINT_P (ep))
5472 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5476 * Generate a "lui" instruction.
5479 macro_build_lui (expressionS *ep, int regnum)
5481 gas_assert (! mips_opts.mips16);
5483 if (ep->X_op != O_constant)
5485 gas_assert (ep->X_op == O_symbol);
5486 /* _gp_disp is a special case, used from s_cpload.
5487 __gnu_local_gp is used if mips_no_shared. */
5488 gas_assert (mips_pic == NO_PIC
5490 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5491 || (! mips_in_shared
5492 && strcmp (S_GET_NAME (ep->X_add_symbol),
5493 "__gnu_local_gp") == 0));
5496 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5499 /* Generate a sequence of instructions to do a load or store from a constant
5500 offset off of a base register (breg) into/from a target register (treg),
5501 using AT if necessary. */
5503 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5504 int treg, int breg, int dbl)
5506 gas_assert (ep->X_op == O_constant);
5508 /* Sign-extending 32-bit constants makes their handling easier. */
5510 normalize_constant_expr (ep);
5512 /* Right now, this routine can only handle signed 32-bit constants. */
5513 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5514 as_warn (_("operand overflow"));
5516 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5518 /* Signed 16-bit offset will fit in the op. Easy! */
5519 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5523 /* 32-bit offset, need multiple instructions and AT, like:
5524 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5525 addu $tempreg,$tempreg,$breg
5526 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5527 to handle the complete offset. */
5528 macro_build_lui (ep, AT);
5529 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5530 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5533 as_bad (_("Macro used $at after \".set noat\""));
5538 * Generates code to set the $at register to true (one)
5539 * if reg is less than the immediate expression.
5542 set_at (int reg, int unsignedp)
5544 if (imm_expr.X_op == O_constant
5545 && imm_expr.X_add_number >= -0x8000
5546 && imm_expr.X_add_number < 0x8000)
5547 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5548 AT, reg, BFD_RELOC_LO16);
5551 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5552 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5556 /* Warn if an expression is not a constant. */
5559 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5561 if (ex->X_op == O_big)
5562 as_bad (_("unsupported large constant"));
5563 else if (ex->X_op != O_constant)
5564 as_bad (_("Instruction %s requires absolute expression"),
5567 if (HAVE_32BIT_GPRS)
5568 normalize_constant_expr (ex);
5571 /* Count the leading zeroes by performing a binary chop. This is a
5572 bulky bit of source, but performance is a LOT better for the
5573 majority of values than a simple loop to count the bits:
5574 for (lcnt = 0; (lcnt < 32); lcnt++)
5575 if ((v) & (1 << (31 - lcnt)))
5577 However it is not code size friendly, and the gain will drop a bit
5578 on certain cached systems.
5580 #define COUNT_TOP_ZEROES(v) \
5581 (((v) & ~0xffff) == 0 \
5582 ? ((v) & ~0xff) == 0 \
5583 ? ((v) & ~0xf) == 0 \
5584 ? ((v) & ~0x3) == 0 \
5585 ? ((v) & ~0x1) == 0 \
5590 : ((v) & ~0x7) == 0 \
5593 : ((v) & ~0x3f) == 0 \
5594 ? ((v) & ~0x1f) == 0 \
5597 : ((v) & ~0x7f) == 0 \
5600 : ((v) & ~0xfff) == 0 \
5601 ? ((v) & ~0x3ff) == 0 \
5602 ? ((v) & ~0x1ff) == 0 \
5605 : ((v) & ~0x7ff) == 0 \
5608 : ((v) & ~0x3fff) == 0 \
5609 ? ((v) & ~0x1fff) == 0 \
5612 : ((v) & ~0x7fff) == 0 \
5615 : ((v) & ~0xffffff) == 0 \
5616 ? ((v) & ~0xfffff) == 0 \
5617 ? ((v) & ~0x3ffff) == 0 \
5618 ? ((v) & ~0x1ffff) == 0 \
5621 : ((v) & ~0x7ffff) == 0 \
5624 : ((v) & ~0x3fffff) == 0 \
5625 ? ((v) & ~0x1fffff) == 0 \
5628 : ((v) & ~0x7fffff) == 0 \
5631 : ((v) & ~0xfffffff) == 0 \
5632 ? ((v) & ~0x3ffffff) == 0 \
5633 ? ((v) & ~0x1ffffff) == 0 \
5636 : ((v) & ~0x7ffffff) == 0 \
5639 : ((v) & ~0x3fffffff) == 0 \
5640 ? ((v) & ~0x1fffffff) == 0 \
5643 : ((v) & ~0x7fffffff) == 0 \
5648 * This routine generates the least number of instructions necessary to load
5649 * an absolute expression value into a register.
5652 load_register (int reg, expressionS *ep, int dbl)
5655 expressionS hi32, lo32;
5657 if (ep->X_op != O_big)
5659 gas_assert (ep->X_op == O_constant);
5661 /* Sign-extending 32-bit constants makes their handling easier. */
5663 normalize_constant_expr (ep);
5665 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5667 /* We can handle 16 bit signed values with an addiu to
5668 $zero. No need to ever use daddiu here, since $zero and
5669 the result are always correct in 32 bit mode. */
5670 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5673 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5675 /* We can handle 16 bit unsigned values with an ori to
5677 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5680 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5682 /* 32 bit values require an lui. */
5683 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5684 if ((ep->X_add_number & 0xffff) != 0)
5685 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5690 /* The value is larger than 32 bits. */
5692 if (!dbl || HAVE_32BIT_GPRS)
5696 sprintf_vma (value, ep->X_add_number);
5697 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5698 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5702 if (ep->X_op != O_big)
5705 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5706 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5707 hi32.X_add_number &= 0xffffffff;
5709 lo32.X_add_number &= 0xffffffff;
5713 gas_assert (ep->X_add_number > 2);
5714 if (ep->X_add_number == 3)
5715 generic_bignum[3] = 0;
5716 else if (ep->X_add_number > 4)
5717 as_bad (_("Number larger than 64 bits"));
5718 lo32.X_op = O_constant;
5719 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5720 hi32.X_op = O_constant;
5721 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5724 if (hi32.X_add_number == 0)
5729 unsigned long hi, lo;
5731 if (hi32.X_add_number == (offsetT) 0xffffffff)
5733 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5735 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5738 if (lo32.X_add_number & 0x80000000)
5740 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5741 if (lo32.X_add_number & 0xffff)
5742 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5747 /* Check for 16bit shifted constant. We know that hi32 is
5748 non-zero, so start the mask on the first bit of the hi32
5753 unsigned long himask, lomask;
5757 himask = 0xffff >> (32 - shift);
5758 lomask = (0xffff << shift) & 0xffffffff;
5762 himask = 0xffff << (shift - 32);
5765 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5766 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5770 tmp.X_op = O_constant;
5772 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5773 | (lo32.X_add_number >> shift));
5775 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5776 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5777 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5778 reg, reg, (shift >= 32) ? shift - 32 : shift);
5783 while (shift <= (64 - 16));
5785 /* Find the bit number of the lowest one bit, and store the
5786 shifted value in hi/lo. */
5787 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5788 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5792 while ((lo & 1) == 0)
5797 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5803 while ((hi & 1) == 0)
5812 /* Optimize if the shifted value is a (power of 2) - 1. */
5813 if ((hi == 0 && ((lo + 1) & lo) == 0)
5814 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5816 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5821 /* This instruction will set the register to be all
5823 tmp.X_op = O_constant;
5824 tmp.X_add_number = (offsetT) -1;
5825 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5829 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5830 reg, reg, (bit >= 32) ? bit - 32 : bit);
5832 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5833 reg, reg, (shift >= 32) ? shift - 32 : shift);
5838 /* Sign extend hi32 before calling load_register, because we can
5839 generally get better code when we load a sign extended value. */
5840 if ((hi32.X_add_number & 0x80000000) != 0)
5841 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5842 load_register (reg, &hi32, 0);
5845 if ((lo32.X_add_number & 0xffff0000) == 0)
5849 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5857 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5859 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5860 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5866 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5870 mid16.X_add_number >>= 16;
5871 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5872 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5875 if ((lo32.X_add_number & 0xffff) != 0)
5876 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5880 load_delay_nop (void)
5882 if (!gpr_interlocks)
5883 macro_build (NULL, "nop", "");
5886 /* Load an address into a register. */
5889 load_address (int reg, expressionS *ep, int *used_at)
5891 if (ep->X_op != O_constant
5892 && ep->X_op != O_symbol)
5894 as_bad (_("expression too complex"));
5895 ep->X_op = O_constant;
5898 if (ep->X_op == O_constant)
5900 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5904 if (mips_pic == NO_PIC)
5906 /* If this is a reference to a GP relative symbol, we want
5907 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5909 lui $reg,<sym> (BFD_RELOC_HI16_S)
5910 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5911 If we have an addend, we always use the latter form.
5913 With 64bit address space and a usable $at we want
5914 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5915 lui $at,<sym> (BFD_RELOC_HI16_S)
5916 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5917 daddiu $at,<sym> (BFD_RELOC_LO16)
5921 If $at is already in use, we use a path which is suboptimal
5922 on superscalar processors.
5923 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5924 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5926 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5928 daddiu $reg,<sym> (BFD_RELOC_LO16)
5930 For GP relative symbols in 64bit address space we can use
5931 the same sequence as in 32bit address space. */
5932 if (HAVE_64BIT_SYMBOLS)
5934 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5935 && !nopic_need_relax (ep->X_add_symbol, 1))
5937 relax_start (ep->X_add_symbol);
5938 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5939 mips_gp_register, BFD_RELOC_GPREL16);
5943 if (*used_at == 0 && mips_opts.at)
5945 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5946 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5947 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5948 BFD_RELOC_MIPS_HIGHER);
5949 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5950 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5951 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5956 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5957 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5958 BFD_RELOC_MIPS_HIGHER);
5959 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5960 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5961 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5962 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5965 if (mips_relax.sequence)
5970 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5971 && !nopic_need_relax (ep->X_add_symbol, 1))
5973 relax_start (ep->X_add_symbol);
5974 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5975 mips_gp_register, BFD_RELOC_GPREL16);
5978 macro_build_lui (ep, reg);
5979 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5980 reg, reg, BFD_RELOC_LO16);
5981 if (mips_relax.sequence)
5985 else if (!mips_big_got)
5989 /* If this is a reference to an external symbol, we want
5990 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5992 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5994 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5995 If there is a constant, it must be added in after.
5997 If we have NewABI, we want
5998 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5999 unless we're referencing a global symbol with a non-zero
6000 offset, in which case cst must be added separately. */
6003 if (ep->X_add_number)
6005 ex.X_add_number = ep->X_add_number;
6006 ep->X_add_number = 0;
6007 relax_start (ep->X_add_symbol);
6008 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6009 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6010 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6012 ex.X_op = O_constant;
6013 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6014 reg, reg, BFD_RELOC_LO16);
6015 ep->X_add_number = ex.X_add_number;
6018 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6019 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6020 if (mips_relax.sequence)
6025 ex.X_add_number = ep->X_add_number;
6026 ep->X_add_number = 0;
6027 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6028 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6030 relax_start (ep->X_add_symbol);
6032 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6036 if (ex.X_add_number != 0)
6038 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6039 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6040 ex.X_op = O_constant;
6041 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6042 reg, reg, BFD_RELOC_LO16);
6046 else if (mips_big_got)
6050 /* This is the large GOT case. If this is a reference to an
6051 external symbol, we want
6052 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6054 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6056 Otherwise, for a reference to a local symbol in old ABI, we want
6057 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6059 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6060 If there is a constant, it must be added in after.
6062 In the NewABI, for local symbols, with or without offsets, we want:
6063 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6064 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6068 ex.X_add_number = ep->X_add_number;
6069 ep->X_add_number = 0;
6070 relax_start (ep->X_add_symbol);
6071 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6072 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6073 reg, reg, mips_gp_register);
6074 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6075 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6076 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6077 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6078 else if (ex.X_add_number)
6080 ex.X_op = O_constant;
6081 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6085 ep->X_add_number = ex.X_add_number;
6087 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6088 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6089 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6090 BFD_RELOC_MIPS_GOT_OFST);
6095 ex.X_add_number = ep->X_add_number;
6096 ep->X_add_number = 0;
6097 relax_start (ep->X_add_symbol);
6098 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6099 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6100 reg, reg, mips_gp_register);
6101 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6102 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6104 if (reg_needs_delay (mips_gp_register))
6106 /* We need a nop before loading from $gp. This special
6107 check is required because the lui which starts the main
6108 instruction stream does not refer to $gp, and so will not
6109 insert the nop which may be required. */
6110 macro_build (NULL, "nop", "");
6112 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6113 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6115 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6119 if (ex.X_add_number != 0)
6121 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6122 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6123 ex.X_op = O_constant;
6124 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6132 if (!mips_opts.at && *used_at == 1)
6133 as_bad (_("Macro used $at after \".set noat\""));
6136 /* Move the contents of register SOURCE into register DEST. */
6139 move_register (int dest, int source)
6141 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6142 instruction specifically requires a 32-bit one. */
6143 if (mips_opts.micromips
6144 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6145 macro_build (NULL, "move", "mp,mj", dest, source);
6147 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6151 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6152 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6153 The two alternatives are:
6155 Global symbol Local sybmol
6156 ------------- ------------
6157 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6159 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6161 load_got_offset emits the first instruction and add_got_offset
6162 emits the second for a 16-bit offset or add_got_offset_hilo emits
6163 a sequence to add a 32-bit offset using a scratch register. */
6166 load_got_offset (int dest, expressionS *local)
6171 global.X_add_number = 0;
6173 relax_start (local->X_add_symbol);
6174 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6175 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6177 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6178 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6183 add_got_offset (int dest, expressionS *local)
6187 global.X_op = O_constant;
6188 global.X_op_symbol = NULL;
6189 global.X_add_symbol = NULL;
6190 global.X_add_number = local->X_add_number;
6192 relax_start (local->X_add_symbol);
6193 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6194 dest, dest, BFD_RELOC_LO16);
6196 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6201 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6204 int hold_mips_optimize;
6206 global.X_op = O_constant;
6207 global.X_op_symbol = NULL;
6208 global.X_add_symbol = NULL;
6209 global.X_add_number = local->X_add_number;
6211 relax_start (local->X_add_symbol);
6212 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6214 /* Set mips_optimize around the lui instruction to avoid
6215 inserting an unnecessary nop after the lw. */
6216 hold_mips_optimize = mips_optimize;
6218 macro_build_lui (&global, tmp);
6219 mips_optimize = hold_mips_optimize;
6220 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6223 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6226 /* Emit a sequence of instructions to emulate a branch likely operation.
6227 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6228 is its complementing branch with the original condition negated.
6229 CALL is set if the original branch specified the link operation.
6230 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6232 Code like this is produced in the noreorder mode:
6237 delay slot (executed only if branch taken)
6245 delay slot (executed only if branch taken)
6248 In the reorder mode the delay slot would be filled with a nop anyway,
6249 so code produced is simply:
6254 This function is used when producing code for the microMIPS ASE that
6255 does not implement branch likely instructions in hardware. */
6258 macro_build_branch_likely (const char *br, const char *brneg,
6259 int call, expressionS *ep, const char *fmt,
6260 unsigned int sreg, unsigned int treg)
6262 int noreorder = mips_opts.noreorder;
6265 gas_assert (mips_opts.micromips);
6269 micromips_label_expr (&expr1);
6270 macro_build (&expr1, brneg, fmt, sreg, treg);
6271 macro_build (NULL, "nop", "");
6272 macro_build (ep, call ? "bal" : "b", "p");
6274 /* Set to true so that append_insn adds a label. */
6275 emit_branch_likely_macro = TRUE;
6279 macro_build (ep, br, fmt, sreg, treg);
6280 macro_build (NULL, "nop", "");
6285 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6286 the condition code tested. EP specifies the branch target. */
6289 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6316 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6319 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6320 the register tested. EP specifies the branch target. */
6323 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6325 const char *brneg = NULL;
6335 br = mips_opts.micromips ? "bgez" : "bgezl";
6339 gas_assert (mips_opts.micromips);
6348 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6355 br = mips_opts.micromips ? "blez" : "blezl";
6362 br = mips_opts.micromips ? "bltz" : "bltzl";
6366 gas_assert (mips_opts.micromips);
6374 if (mips_opts.micromips && brneg)
6375 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6377 macro_build (ep, br, "s,p", sreg);
6380 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6381 TREG as the registers tested. EP specifies the branch target. */
6384 macro_build_branch_rsrt (int type, expressionS *ep,
6385 unsigned int sreg, unsigned int treg)
6387 const char *brneg = NULL;
6399 br = mips_opts.micromips ? "beq" : "beql";
6408 br = mips_opts.micromips ? "bne" : "bnel";
6414 if (mips_opts.micromips && brneg)
6415 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6417 macro_build (ep, br, "s,t,p", sreg, treg);
6422 * This routine implements the seemingly endless macro or synthesized
6423 * instructions and addressing modes in the mips assembly language. Many
6424 * of these macros are simple and are similar to each other. These could
6425 * probably be handled by some kind of table or grammar approach instead of
6426 * this verbose method. Others are not simple macros but are more like
6427 * optimizing code generation.
6428 * One interesting optimization is when several store macros appear
6429 * consecutively that would load AT with the upper half of the same address.
6430 * The ensuing load upper instructions are ommited. This implies some kind
6431 * of global optimization. We currently only optimize within a single macro.
6432 * For many of the load and store macros if the address is specified as a
6433 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6434 * first load register 'at' with zero and use it as the base register. The
6435 * mips assembler simply uses register $zero. Just one tiny optimization
6439 macro (struct mips_cl_insn *ip)
6441 unsigned int treg, sreg, dreg, breg;
6442 unsigned int tempreg;
6445 expressionS label_expr;
6464 bfd_reloc_code_real_type r;
6465 int hold_mips_optimize;
6467 gas_assert (! mips_opts.mips16);
6469 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6470 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6471 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6472 mask = ip->insn_mo->mask;
6474 label_expr.X_op = O_constant;
6475 label_expr.X_op_symbol = NULL;
6476 label_expr.X_add_symbol = NULL;
6477 label_expr.X_add_number = 0;
6479 expr1.X_op = O_constant;
6480 expr1.X_op_symbol = NULL;
6481 expr1.X_add_symbol = NULL;
6482 expr1.X_add_number = 1;
6497 if (mips_opts.micromips)
6498 micromips_label_expr (&label_expr);
6500 label_expr.X_add_number = 8;
6501 macro_build (&label_expr, "bgez", "s,p", sreg);
6503 macro_build (NULL, "nop", "");
6505 move_register (dreg, sreg);
6506 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6507 if (mips_opts.micromips)
6508 micromips_add_label ();
6525 if (!mips_opts.micromips)
6527 if (imm_expr.X_op == O_constant
6528 && imm_expr.X_add_number >= -0x200
6529 && imm_expr.X_add_number < 0x200)
6531 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6540 if (imm_expr.X_op == O_constant
6541 && imm_expr.X_add_number >= -0x8000
6542 && imm_expr.X_add_number < 0x8000)
6544 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6549 load_register (AT, &imm_expr, dbl);
6550 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6569 if (imm_expr.X_op == O_constant
6570 && imm_expr.X_add_number >= 0
6571 && imm_expr.X_add_number < 0x10000)
6573 if (mask != M_NOR_I)
6574 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6577 macro_build (&imm_expr, "ori", "t,r,i",
6578 treg, sreg, BFD_RELOC_LO16);
6579 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6585 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6586 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6590 switch (imm_expr.X_add_number)
6593 macro_build (NULL, "nop", "");
6596 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6600 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6601 (int) imm_expr.X_add_number);
6604 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6605 (unsigned long) imm_expr.X_add_number);
6614 gas_assert (mips_opts.micromips);
6615 macro_build_branch_ccl (mask, &offset_expr,
6616 EXTRACT_OPERAND (1, BCC, *ip));
6623 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6629 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6634 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6641 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6643 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6647 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6648 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6649 &offset_expr, AT, ZERO);
6659 macro_build_branch_rs (mask, &offset_expr, sreg);
6665 /* Check for > max integer. */
6666 maxnum = 0x7fffffff;
6667 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6674 if (imm_expr.X_op == O_constant
6675 && imm_expr.X_add_number >= maxnum
6676 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6679 /* Result is always false. */
6681 macro_build (NULL, "nop", "");
6683 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6686 if (imm_expr.X_op != O_constant)
6687 as_bad (_("Unsupported large constant"));
6688 ++imm_expr.X_add_number;
6692 if (mask == M_BGEL_I)
6694 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6696 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6697 &offset_expr, sreg);
6700 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6702 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6703 &offset_expr, sreg);
6706 maxnum = 0x7fffffff;
6707 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6714 maxnum = - maxnum - 1;
6715 if (imm_expr.X_op == O_constant
6716 && imm_expr.X_add_number <= maxnum
6717 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6720 /* result is always true */
6721 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6722 macro_build (&offset_expr, "b", "p");
6727 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6728 &offset_expr, AT, ZERO);
6737 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6738 &offset_expr, ZERO, treg);
6742 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6743 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6744 &offset_expr, AT, ZERO);
6753 && imm_expr.X_op == O_constant
6754 && imm_expr.X_add_number == -1))
6756 if (imm_expr.X_op != O_constant)
6757 as_bad (_("Unsupported large constant"));
6758 ++imm_expr.X_add_number;
6762 if (mask == M_BGEUL_I)
6764 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6766 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6767 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6768 &offset_expr, sreg, ZERO);
6773 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6774 &offset_expr, AT, ZERO);
6782 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6784 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6788 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6789 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6790 &offset_expr, AT, ZERO);
6798 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6799 &offset_expr, sreg, ZERO);
6805 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6806 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6807 &offset_expr, AT, ZERO);
6815 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6817 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6821 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6822 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6823 &offset_expr, AT, ZERO);
6830 maxnum = 0x7fffffff;
6831 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6838 if (imm_expr.X_op == O_constant
6839 && imm_expr.X_add_number >= maxnum
6840 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6842 if (imm_expr.X_op != O_constant)
6843 as_bad (_("Unsupported large constant"));
6844 ++imm_expr.X_add_number;
6848 if (mask == M_BLTL_I)
6850 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6851 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6852 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6853 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6858 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6859 &offset_expr, AT, ZERO);
6867 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6868 &offset_expr, sreg, ZERO);
6874 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6875 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6876 &offset_expr, AT, ZERO);
6885 && imm_expr.X_op == O_constant
6886 && imm_expr.X_add_number == -1))
6888 if (imm_expr.X_op != O_constant)
6889 as_bad (_("Unsupported large constant"));
6890 ++imm_expr.X_add_number;
6894 if (mask == M_BLTUL_I)
6896 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6898 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6899 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6900 &offset_expr, sreg, ZERO);
6905 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6906 &offset_expr, AT, ZERO);
6914 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6916 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6920 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6921 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6922 &offset_expr, AT, ZERO);
6932 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6933 &offset_expr, ZERO, treg);
6937 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6938 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6939 &offset_expr, AT, ZERO);
6945 /* Use unsigned arithmetic. */
6949 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6951 as_bad (_("Unsupported large constant"));
6956 pos = imm_expr.X_add_number;
6957 size = imm2_expr.X_add_number;
6962 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6965 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6967 as_bad (_("Improper extract size (%lu, position %lu)"),
6968 (unsigned long) size, (unsigned long) pos);
6972 if (size <= 32 && pos < 32)
6977 else if (size <= 32)
6987 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6994 /* Use unsigned arithmetic. */
6998 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7000 as_bad (_("Unsupported large constant"));
7005 pos = imm_expr.X_add_number;
7006 size = imm2_expr.X_add_number;
7011 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7014 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7016 as_bad (_("Improper insert size (%lu, position %lu)"),
7017 (unsigned long) size, (unsigned long) pos);
7021 if (pos < 32 && (pos + size - 1) < 32)
7036 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7037 (int) (pos + size - 1));
7053 as_warn (_("Divide by zero."));
7055 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7057 macro_build (NULL, "break", BRK_FMT, 7);
7064 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7065 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7069 if (mips_opts.micromips)
7070 micromips_label_expr (&label_expr);
7072 label_expr.X_add_number = 8;
7073 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7074 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7075 macro_build (NULL, "break", BRK_FMT, 7);
7076 if (mips_opts.micromips)
7077 micromips_add_label ();
7079 expr1.X_add_number = -1;
7081 load_register (AT, &expr1, dbl);
7082 if (mips_opts.micromips)
7083 micromips_label_expr (&label_expr);
7085 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7086 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7089 expr1.X_add_number = 1;
7090 load_register (AT, &expr1, dbl);
7091 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7095 expr1.X_add_number = 0x80000000;
7096 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7100 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7101 /* We want to close the noreorder block as soon as possible, so
7102 that later insns are available for delay slot filling. */
7107 if (mips_opts.micromips)
7108 micromips_label_expr (&label_expr);
7110 label_expr.X_add_number = 8;
7111 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7112 macro_build (NULL, "nop", "");
7114 /* We want to close the noreorder block as soon as possible, so
7115 that later insns are available for delay slot filling. */
7118 macro_build (NULL, "break", BRK_FMT, 6);
7120 if (mips_opts.micromips)
7121 micromips_add_label ();
7122 macro_build (NULL, s, MFHL_FMT, dreg);
7161 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7163 as_warn (_("Divide by zero."));
7165 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7167 macro_build (NULL, "break", BRK_FMT, 7);
7170 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7172 if (strcmp (s2, "mflo") == 0)
7173 move_register (dreg, sreg);
7175 move_register (dreg, ZERO);
7178 if (imm_expr.X_op == O_constant
7179 && imm_expr.X_add_number == -1
7180 && s[strlen (s) - 1] != 'u')
7182 if (strcmp (s2, "mflo") == 0)
7184 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7187 move_register (dreg, ZERO);
7192 load_register (AT, &imm_expr, dbl);
7193 macro_build (NULL, s, "z,s,t", sreg, AT);
7194 macro_build (NULL, s2, MFHL_FMT, dreg);
7216 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7217 macro_build (NULL, s, "z,s,t", sreg, treg);
7218 /* We want to close the noreorder block as soon as possible, so
7219 that later insns are available for delay slot filling. */
7224 if (mips_opts.micromips)
7225 micromips_label_expr (&label_expr);
7227 label_expr.X_add_number = 8;
7228 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7229 macro_build (NULL, s, "z,s,t", sreg, treg);
7231 /* We want to close the noreorder block as soon as possible, so
7232 that later insns are available for delay slot filling. */
7234 macro_build (NULL, "break", BRK_FMT, 7);
7235 if (mips_opts.micromips)
7236 micromips_add_label ();
7238 macro_build (NULL, s2, MFHL_FMT, dreg);
7250 /* Load the address of a symbol into a register. If breg is not
7251 zero, we then add a base register to it. */
7253 if (dbl && HAVE_32BIT_GPRS)
7254 as_warn (_("dla used to load 32-bit register"));
7256 if (!dbl && HAVE_64BIT_OBJECTS)
7257 as_warn (_("la used to load 64-bit address"));
7259 if (offset_expr.X_op == O_constant
7260 && offset_expr.X_add_number >= -0x8000
7261 && offset_expr.X_add_number < 0x8000)
7263 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7264 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7268 if (mips_opts.at && (treg == breg))
7278 if (offset_expr.X_op != O_symbol
7279 && offset_expr.X_op != O_constant)
7281 as_bad (_("Expression too complex"));
7282 offset_expr.X_op = O_constant;
7285 if (offset_expr.X_op == O_constant)
7286 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7287 else if (mips_pic == NO_PIC)
7289 /* If this is a reference to a GP relative symbol, we want
7290 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7292 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7293 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7294 If we have a constant, we need two instructions anyhow,
7295 so we may as well always use the latter form.
7297 With 64bit address space and a usable $at we want
7298 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7299 lui $at,<sym> (BFD_RELOC_HI16_S)
7300 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7301 daddiu $at,<sym> (BFD_RELOC_LO16)
7303 daddu $tempreg,$tempreg,$at
7305 If $at is already in use, we use a path which is suboptimal
7306 on superscalar processors.
7307 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7308 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7310 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7312 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7314 For GP relative symbols in 64bit address space we can use
7315 the same sequence as in 32bit address space. */
7316 if (HAVE_64BIT_SYMBOLS)
7318 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7319 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7321 relax_start (offset_expr.X_add_symbol);
7322 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7323 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7327 if (used_at == 0 && mips_opts.at)
7329 macro_build (&offset_expr, "lui", LUI_FMT,
7330 tempreg, BFD_RELOC_MIPS_HIGHEST);
7331 macro_build (&offset_expr, "lui", LUI_FMT,
7332 AT, BFD_RELOC_HI16_S);
7333 macro_build (&offset_expr, "daddiu", "t,r,j",
7334 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7335 macro_build (&offset_expr, "daddiu", "t,r,j",
7336 AT, AT, BFD_RELOC_LO16);
7337 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7338 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7343 macro_build (&offset_expr, "lui", LUI_FMT,
7344 tempreg, BFD_RELOC_MIPS_HIGHEST);
7345 macro_build (&offset_expr, "daddiu", "t,r,j",
7346 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7347 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7348 macro_build (&offset_expr, "daddiu", "t,r,j",
7349 tempreg, tempreg, BFD_RELOC_HI16_S);
7350 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7351 macro_build (&offset_expr, "daddiu", "t,r,j",
7352 tempreg, tempreg, BFD_RELOC_LO16);
7355 if (mips_relax.sequence)
7360 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7361 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7363 relax_start (offset_expr.X_add_symbol);
7364 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7365 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7368 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7369 as_bad (_("Offset too large"));
7370 macro_build_lui (&offset_expr, tempreg);
7371 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7372 tempreg, tempreg, BFD_RELOC_LO16);
7373 if (mips_relax.sequence)
7377 else if (!mips_big_got && !HAVE_NEWABI)
7379 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7381 /* If this is a reference to an external symbol, and there
7382 is no constant, we want
7383 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7384 or for lca or if tempreg is PIC_CALL_REG
7385 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7386 For a local symbol, we want
7387 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7389 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7391 If we have a small constant, and this is a reference to
7392 an external symbol, we want
7393 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7395 addiu $tempreg,$tempreg,<constant>
7396 For a local symbol, we want the same instruction
7397 sequence, but we output a BFD_RELOC_LO16 reloc on the
7400 If we have a large constant, and this is a reference to
7401 an external symbol, we want
7402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7403 lui $at,<hiconstant>
7404 addiu $at,$at,<loconstant>
7405 addu $tempreg,$tempreg,$at
7406 For a local symbol, we want the same instruction
7407 sequence, but we output a BFD_RELOC_LO16 reloc on the
7411 if (offset_expr.X_add_number == 0)
7413 if (mips_pic == SVR4_PIC
7415 && (call || tempreg == PIC_CALL_REG))
7416 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7418 relax_start (offset_expr.X_add_symbol);
7419 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7420 lw_reloc_type, mips_gp_register);
7423 /* We're going to put in an addu instruction using
7424 tempreg, so we may as well insert the nop right
7429 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7430 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7432 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7433 tempreg, tempreg, BFD_RELOC_LO16);
7435 /* FIXME: If breg == 0, and the next instruction uses
7436 $tempreg, then if this variant case is used an extra
7437 nop will be generated. */
7439 else if (offset_expr.X_add_number >= -0x8000
7440 && offset_expr.X_add_number < 0x8000)
7442 load_got_offset (tempreg, &offset_expr);
7444 add_got_offset (tempreg, &offset_expr);
7448 expr1.X_add_number = offset_expr.X_add_number;
7449 offset_expr.X_add_number =
7450 SEXT_16BIT (offset_expr.X_add_number);
7451 load_got_offset (tempreg, &offset_expr);
7452 offset_expr.X_add_number = expr1.X_add_number;
7453 /* If we are going to add in a base register, and the
7454 target register and the base register are the same,
7455 then we are using AT as a temporary register. Since
7456 we want to load the constant into AT, we add our
7457 current AT (from the global offset table) and the
7458 register into the register now, and pretend we were
7459 not using a base register. */
7463 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7468 add_got_offset_hilo (tempreg, &offset_expr, AT);
7472 else if (!mips_big_got && HAVE_NEWABI)
7474 int add_breg_early = 0;
7476 /* If this is a reference to an external, and there is no
7477 constant, or local symbol (*), with or without a
7479 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7480 or for lca or if tempreg is PIC_CALL_REG
7481 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7483 If we have a small constant, and this is a reference to
7484 an external symbol, we want
7485 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7486 addiu $tempreg,$tempreg,<constant>
7488 If we have a large constant, and this is a reference to
7489 an external symbol, we want
7490 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7491 lui $at,<hiconstant>
7492 addiu $at,$at,<loconstant>
7493 addu $tempreg,$tempreg,$at
7495 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7496 local symbols, even though it introduces an additional
7499 if (offset_expr.X_add_number)
7501 expr1.X_add_number = offset_expr.X_add_number;
7502 offset_expr.X_add_number = 0;
7504 relax_start (offset_expr.X_add_symbol);
7505 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7506 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7508 if (expr1.X_add_number >= -0x8000
7509 && expr1.X_add_number < 0x8000)
7511 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7512 tempreg, tempreg, BFD_RELOC_LO16);
7514 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7516 /* If we are going to add in a base register, and the
7517 target register and the base register are the same,
7518 then we are using AT as a temporary register. Since
7519 we want to load the constant into AT, we add our
7520 current AT (from the global offset table) and the
7521 register into the register now, and pretend we were
7522 not using a base register. */
7527 gas_assert (tempreg == AT);
7528 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7534 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7535 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7541 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7544 offset_expr.X_add_number = expr1.X_add_number;
7546 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7547 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7550 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7551 treg, tempreg, breg);
7557 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7559 relax_start (offset_expr.X_add_symbol);
7560 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7561 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7563 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7564 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7569 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7570 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7573 else if (mips_big_got && !HAVE_NEWABI)
7576 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7577 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7578 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7580 /* This is the large GOT case. If this is a reference to an
7581 external symbol, and there is no constant, we want
7582 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7583 addu $tempreg,$tempreg,$gp
7584 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7585 or for lca or if tempreg is PIC_CALL_REG
7586 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7587 addu $tempreg,$tempreg,$gp
7588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7589 For a local symbol, we want
7590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7594 If we have a small constant, and this is a reference to
7595 an external symbol, we want
7596 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7597 addu $tempreg,$tempreg,$gp
7598 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7600 addiu $tempreg,$tempreg,<constant>
7601 For a local symbol, we want
7602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7604 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7606 If we have a large constant, and this is a reference to
7607 an external symbol, we want
7608 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7609 addu $tempreg,$tempreg,$gp
7610 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7611 lui $at,<hiconstant>
7612 addiu $at,$at,<loconstant>
7613 addu $tempreg,$tempreg,$at
7614 For a local symbol, we want
7615 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7616 lui $at,<hiconstant>
7617 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7618 addu $tempreg,$tempreg,$at
7621 expr1.X_add_number = offset_expr.X_add_number;
7622 offset_expr.X_add_number = 0;
7623 relax_start (offset_expr.X_add_symbol);
7624 gpdelay = reg_needs_delay (mips_gp_register);
7625 if (expr1.X_add_number == 0 && breg == 0
7626 && (call || tempreg == PIC_CALL_REG))
7628 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7629 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7631 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7632 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7633 tempreg, tempreg, mips_gp_register);
7634 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7635 tempreg, lw_reloc_type, tempreg);
7636 if (expr1.X_add_number == 0)
7640 /* We're going to put in an addu instruction using
7641 tempreg, so we may as well insert the nop right
7646 else if (expr1.X_add_number >= -0x8000
7647 && expr1.X_add_number < 0x8000)
7650 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7651 tempreg, tempreg, BFD_RELOC_LO16);
7655 /* If we are going to add in a base register, and the
7656 target register and the base register are the same,
7657 then we are using AT as a temporary register. Since
7658 we want to load the constant into AT, we add our
7659 current AT (from the global offset table) and the
7660 register into the register now, and pretend we were
7661 not using a base register. */
7666 gas_assert (tempreg == AT);
7668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7673 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7674 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7678 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7683 /* This is needed because this instruction uses $gp, but
7684 the first instruction on the main stream does not. */
7685 macro_build (NULL, "nop", "");
7688 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7689 local_reloc_type, mips_gp_register);
7690 if (expr1.X_add_number >= -0x8000
7691 && expr1.X_add_number < 0x8000)
7694 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7695 tempreg, tempreg, BFD_RELOC_LO16);
7696 /* FIXME: If add_number is 0, and there was no base
7697 register, the external symbol case ended with a load,
7698 so if the symbol turns out to not be external, and
7699 the next instruction uses tempreg, an unnecessary nop
7700 will be inserted. */
7706 /* We must add in the base register now, as in the
7707 external symbol case. */
7708 gas_assert (tempreg == AT);
7710 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7713 /* We set breg to 0 because we have arranged to add
7714 it in in both cases. */
7718 macro_build_lui (&expr1, AT);
7719 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7720 AT, AT, BFD_RELOC_LO16);
7721 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7722 tempreg, tempreg, AT);
7727 else if (mips_big_got && HAVE_NEWABI)
7729 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7730 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7731 int add_breg_early = 0;
7733 /* This is the large GOT case. If this is a reference to an
7734 external symbol, and there is no constant, we want
7735 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7736 add $tempreg,$tempreg,$gp
7737 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7738 or for lca or if tempreg is PIC_CALL_REG
7739 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7740 add $tempreg,$tempreg,$gp
7741 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7743 If we have a small constant, and this is a reference to
7744 an external symbol, we want
7745 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7746 add $tempreg,$tempreg,$gp
7747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7748 addi $tempreg,$tempreg,<constant>
7750 If we have a large constant, and this is a reference to
7751 an external symbol, we want
7752 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7753 addu $tempreg,$tempreg,$gp
7754 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7755 lui $at,<hiconstant>
7756 addi $at,$at,<loconstant>
7757 add $tempreg,$tempreg,$at
7759 If we have NewABI, and we know it's a local symbol, we want
7760 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7761 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7762 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7764 relax_start (offset_expr.X_add_symbol);
7766 expr1.X_add_number = offset_expr.X_add_number;
7767 offset_expr.X_add_number = 0;
7769 if (expr1.X_add_number == 0 && breg == 0
7770 && (call || tempreg == PIC_CALL_REG))
7772 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7773 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7775 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7776 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7777 tempreg, tempreg, mips_gp_register);
7778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7779 tempreg, lw_reloc_type, tempreg);
7781 if (expr1.X_add_number == 0)
7783 else if (expr1.X_add_number >= -0x8000
7784 && expr1.X_add_number < 0x8000)
7786 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7787 tempreg, tempreg, BFD_RELOC_LO16);
7789 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7791 /* If we are going to add in a base register, and the
7792 target register and the base register are the same,
7793 then we are using AT as a temporary register. Since
7794 we want to load the constant into AT, we add our
7795 current AT (from the global offset table) and the
7796 register into the register now, and pretend we were
7797 not using a base register. */
7802 gas_assert (tempreg == AT);
7803 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7809 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7810 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7815 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7818 offset_expr.X_add_number = expr1.X_add_number;
7819 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7820 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7821 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7822 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7825 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7826 treg, tempreg, breg);
7836 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7840 gas_assert (!mips_opts.micromips);
7842 unsigned long temp = (treg << 16) | (0x01);
7843 macro_build (NULL, "c2", "C", temp);
7848 gas_assert (!mips_opts.micromips);
7850 unsigned long temp = (0x02);
7851 macro_build (NULL, "c2", "C", temp);
7856 gas_assert (!mips_opts.micromips);
7858 unsigned long temp = (treg << 16) | (0x02);
7859 macro_build (NULL, "c2", "C", temp);
7864 gas_assert (!mips_opts.micromips);
7865 macro_build (NULL, "c2", "C", 3);
7869 gas_assert (!mips_opts.micromips);
7871 unsigned long temp = (treg << 16) | 0x03;
7872 macro_build (NULL, "c2", "C", temp);
7877 /* The j instruction may not be used in PIC code, since it
7878 requires an absolute address. We convert it to a b
7880 if (mips_pic == NO_PIC)
7881 macro_build (&offset_expr, "j", "a");
7883 macro_build (&offset_expr, "b", "p");
7886 /* The jal instructions must be handled as macros because when
7887 generating PIC code they expand to multi-instruction
7888 sequences. Normally they are simple instructions. */
7893 gas_assert (mips_opts.micromips);
7901 if (mips_pic == NO_PIC)
7903 s = jals ? "jalrs" : "jalr";
7904 if (mips_opts.micromips
7906 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7907 macro_build (NULL, s, "mj", sreg);
7909 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7913 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7914 && mips_cprestore_offset >= 0);
7916 if (sreg != PIC_CALL_REG)
7917 as_warn (_("MIPS PIC call to register other than $25"));
7919 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7920 ? "jalrs" : "jalr");
7921 if (mips_opts.micromips
7923 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7924 macro_build (NULL, s, "mj", sreg);
7926 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7927 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7929 if (mips_cprestore_offset < 0)
7930 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7933 if (!mips_frame_reg_valid)
7935 as_warn (_("No .frame pseudo-op used in PIC code"));
7936 /* Quiet this warning. */
7937 mips_frame_reg_valid = 1;
7939 if (!mips_cprestore_valid)
7941 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7942 /* Quiet this warning. */
7943 mips_cprestore_valid = 1;
7945 if (mips_opts.noreorder)
7946 macro_build (NULL, "nop", "");
7947 expr1.X_add_number = mips_cprestore_offset;
7948 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7951 HAVE_64BIT_ADDRESSES);
7959 gas_assert (mips_opts.micromips);
7963 if (mips_pic == NO_PIC)
7964 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7965 else if (mips_pic == SVR4_PIC)
7967 /* If this is a reference to an external symbol, and we are
7968 using a small GOT, we want
7969 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7973 lw $gp,cprestore($sp)
7974 The cprestore value is set using the .cprestore
7975 pseudo-op. If we are using a big GOT, we want
7976 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7978 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7982 lw $gp,cprestore($sp)
7983 If the symbol is not external, we want
7984 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7986 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7989 lw $gp,cprestore($sp)
7991 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7992 sequences above, minus nops, unless the symbol is local,
7993 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7999 relax_start (offset_expr.X_add_symbol);
8000 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8001 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8004 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8005 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8011 relax_start (offset_expr.X_add_symbol);
8012 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8013 BFD_RELOC_MIPS_CALL_HI16);
8014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8015 PIC_CALL_REG, mips_gp_register);
8016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8017 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8021 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8023 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8024 PIC_CALL_REG, PIC_CALL_REG,
8025 BFD_RELOC_MIPS_GOT_OFST);
8029 macro_build_jalr (&offset_expr, 0);
8033 relax_start (offset_expr.X_add_symbol);
8036 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8037 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8046 gpdelay = reg_needs_delay (mips_gp_register);
8047 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8048 BFD_RELOC_MIPS_CALL_HI16);
8049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8050 PIC_CALL_REG, mips_gp_register);
8051 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8052 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8057 macro_build (NULL, "nop", "");
8059 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8060 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8063 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8064 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8066 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8068 if (mips_cprestore_offset < 0)
8069 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8072 if (!mips_frame_reg_valid)
8074 as_warn (_("No .frame pseudo-op used in PIC code"));
8075 /* Quiet this warning. */
8076 mips_frame_reg_valid = 1;
8078 if (!mips_cprestore_valid)
8080 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8081 /* Quiet this warning. */
8082 mips_cprestore_valid = 1;
8084 if (mips_opts.noreorder)
8085 macro_build (NULL, "nop", "");
8086 expr1.X_add_number = mips_cprestore_offset;
8087 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8090 HAVE_64BIT_ADDRESSES);
8094 else if (mips_pic == VXWORKS_PIC)
8095 as_bad (_("Non-PIC jump used in PIC library"));
8105 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8113 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8144 gas_assert (!mips_opts.micromips);
8147 /* Itbl support may require additional care here. */
8154 /* Itbl support may require additional care here. */
8162 off12 = mips_opts.micromips;
8163 /* Itbl support may require additional care here. */
8168 gas_assert (!mips_opts.micromips);
8171 /* Itbl support may require additional care here. */
8179 off12 = mips_opts.micromips;
8186 off12 = mips_opts.micromips;
8192 /* Itbl support may require additional care here. */
8200 off12 = mips_opts.micromips;
8201 /* Itbl support may require additional care here. */
8208 /* Itbl support may require additional care here. */
8215 /* Itbl support may require additional care here. */
8223 off12 = mips_opts.micromips;
8230 off12 = mips_opts.micromips;
8237 off12 = mips_opts.micromips;
8244 off12 = mips_opts.micromips;
8251 off12 = mips_opts.micromips;
8256 gas_assert (mips_opts.micromips);
8265 gas_assert (mips_opts.micromips);
8274 gas_assert (mips_opts.micromips);
8282 gas_assert (mips_opts.micromips);
8289 if (breg == treg + lp)
8292 tempreg = treg + lp;
8312 gas_assert (!mips_opts.micromips);
8315 /* Itbl support may require additional care here. */
8322 /* Itbl support may require additional care here. */
8330 off12 = mips_opts.micromips;
8331 /* Itbl support may require additional care here. */
8336 gas_assert (!mips_opts.micromips);
8339 /* Itbl support may require additional care here. */
8347 off12 = mips_opts.micromips;
8354 off12 = mips_opts.micromips;
8361 off12 = mips_opts.micromips;
8368 off12 = mips_opts.micromips;
8374 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8375 off12 = mips_opts.micromips;
8381 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8382 off12 = mips_opts.micromips;
8389 /* Itbl support may require additional care here. */
8396 off12 = mips_opts.micromips;
8397 /* Itbl support may require additional care here. */
8404 /* Itbl support may require additional care here. */
8409 gas_assert (!mips_opts.micromips);
8412 /* Itbl support may require additional care here. */
8420 off12 = mips_opts.micromips;
8427 off12 = mips_opts.micromips;
8432 gas_assert (mips_opts.micromips);
8440 gas_assert (mips_opts.micromips);
8448 gas_assert (mips_opts.micromips);
8456 gas_assert (mips_opts.micromips);
8465 if (offset_expr.X_op != O_constant
8466 && offset_expr.X_op != O_symbol)
8468 as_bad (_("Expression too complex"));
8469 offset_expr.X_op = O_constant;
8472 if (HAVE_32BIT_ADDRESSES
8473 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8477 sprintf_vma (value, offset_expr.X_add_number);
8478 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8481 /* A constant expression in PIC code can be handled just as it
8482 is in non PIC code. */
8483 if (offset_expr.X_op == O_constant)
8487 expr1.X_add_number = offset_expr.X_add_number;
8488 normalize_address_expr (&expr1);
8489 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8491 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8492 & ~(bfd_vma) 0xffff);
8495 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8497 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8498 & ~(bfd_vma) 0xfff);
8503 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8505 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8506 tempreg, tempreg, breg);
8511 if (offset_expr.X_add_number == 0)
8514 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8515 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8516 macro_build (NULL, s, fmt, treg, tempreg);
8519 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8521 macro_build (NULL, s, fmt,
8522 treg, (unsigned long) offset_expr.X_add_number, breg);
8524 else if (off12 || off0)
8526 /* A 12-bit or 0-bit offset field is too narrow to be used
8527 for a low-part relocation, so load the whole address into
8528 the auxillary register. In the case of "A(b)" addresses,
8529 we first load absolute address "A" into the register and
8530 then add base register "b". In the case of "o(b)" addresses,
8531 we simply need to add 16-bit offset "o" to base register "b", and
8532 offset_reloc already contains the relocations associated
8536 load_address (tempreg, &offset_expr, &used_at);
8538 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8539 tempreg, tempreg, breg);
8542 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8544 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8545 expr1.X_add_number = 0;
8547 macro_build (NULL, s, fmt, treg, tempreg);
8549 macro_build (NULL, s, fmt,
8550 treg, (unsigned long) expr1.X_add_number, tempreg);
8552 else if (mips_pic == NO_PIC)
8554 /* If this is a reference to a GP relative symbol, and there
8555 is no base register, we want
8556 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8557 Otherwise, if there is no base register, we want
8558 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8559 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8560 If we have a constant, we need two instructions anyhow,
8561 so we always use the latter form.
8563 If we have a base register, and this is a reference to a
8564 GP relative symbol, we want
8565 addu $tempreg,$breg,$gp
8566 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8568 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8569 addu $tempreg,$tempreg,$breg
8570 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8571 With a constant we always use the latter case.
8573 With 64bit address space and no base register and $at usable,
8575 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8576 lui $at,<sym> (BFD_RELOC_HI16_S)
8577 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8580 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8581 If we have a base register, we want
8582 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8583 lui $at,<sym> (BFD_RELOC_HI16_S)
8584 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8588 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8590 Without $at we can't generate the optimal path for superscalar
8591 processors here since this would require two temporary registers.
8592 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8593 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8595 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8597 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8598 If we have a base register, we want
8599 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8600 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8602 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8604 daddu $tempreg,$tempreg,$breg
8605 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8607 For GP relative symbols in 64bit address space we can use
8608 the same sequence as in 32bit address space. */
8609 if (HAVE_64BIT_SYMBOLS)
8611 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8612 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8614 relax_start (offset_expr.X_add_symbol);
8617 macro_build (&offset_expr, s, fmt, treg,
8618 BFD_RELOC_GPREL16, mips_gp_register);
8622 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8623 tempreg, breg, mips_gp_register);
8624 macro_build (&offset_expr, s, fmt, treg,
8625 BFD_RELOC_GPREL16, tempreg);
8630 if (used_at == 0 && mips_opts.at)
8632 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8633 BFD_RELOC_MIPS_HIGHEST);
8634 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8636 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8637 tempreg, BFD_RELOC_MIPS_HIGHER);
8639 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8640 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8641 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8642 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8648 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8649 BFD_RELOC_MIPS_HIGHEST);
8650 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8651 tempreg, BFD_RELOC_MIPS_HIGHER);
8652 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8653 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8654 tempreg, BFD_RELOC_HI16_S);
8655 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8657 macro_build (NULL, "daddu", "d,v,t",
8658 tempreg, tempreg, breg);
8659 macro_build (&offset_expr, s, fmt, treg,
8660 BFD_RELOC_LO16, tempreg);
8663 if (mips_relax.sequence)
8670 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8671 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8673 relax_start (offset_expr.X_add_symbol);
8674 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8678 macro_build_lui (&offset_expr, tempreg);
8679 macro_build (&offset_expr, s, fmt, treg,
8680 BFD_RELOC_LO16, tempreg);
8681 if (mips_relax.sequence)
8686 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8687 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8689 relax_start (offset_expr.X_add_symbol);
8690 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8691 tempreg, breg, mips_gp_register);
8692 macro_build (&offset_expr, s, fmt, treg,
8693 BFD_RELOC_GPREL16, tempreg);
8696 macro_build_lui (&offset_expr, tempreg);
8697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8698 tempreg, tempreg, breg);
8699 macro_build (&offset_expr, s, fmt, treg,
8700 BFD_RELOC_LO16, tempreg);
8701 if (mips_relax.sequence)
8705 else if (!mips_big_got)
8707 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8709 /* If this is a reference to an external symbol, we want
8710 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8712 <op> $treg,0($tempreg)
8714 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8716 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8717 <op> $treg,0($tempreg)
8720 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8721 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8723 If there is a base register, we add it to $tempreg before
8724 the <op>. If there is a constant, we stick it in the
8725 <op> instruction. We don't handle constants larger than
8726 16 bits, because we have no way to load the upper 16 bits
8727 (actually, we could handle them for the subset of cases
8728 in which we are not using $at). */
8729 gas_assert (offset_expr.X_op == O_symbol);
8732 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8733 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8735 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8736 tempreg, tempreg, breg);
8737 macro_build (&offset_expr, s, fmt, treg,
8738 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8741 expr1.X_add_number = offset_expr.X_add_number;
8742 offset_expr.X_add_number = 0;
8743 if (expr1.X_add_number < -0x8000
8744 || expr1.X_add_number >= 0x8000)
8745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8746 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8747 lw_reloc_type, mips_gp_register);
8749 relax_start (offset_expr.X_add_symbol);
8751 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8752 tempreg, BFD_RELOC_LO16);
8755 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8756 tempreg, tempreg, breg);
8757 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8759 else if (mips_big_got && !HAVE_NEWABI)
8763 /* If this is a reference to an external symbol, we want
8764 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8765 addu $tempreg,$tempreg,$gp
8766 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8767 <op> $treg,0($tempreg)
8769 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8771 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8772 <op> $treg,0($tempreg)
8773 If there is a base register, we add it to $tempreg before
8774 the <op>. If there is a constant, we stick it in the
8775 <op> instruction. We don't handle constants larger than
8776 16 bits, because we have no way to load the upper 16 bits
8777 (actually, we could handle them for the subset of cases
8778 in which we are not using $at). */
8779 gas_assert (offset_expr.X_op == O_symbol);
8780 expr1.X_add_number = offset_expr.X_add_number;
8781 offset_expr.X_add_number = 0;
8782 if (expr1.X_add_number < -0x8000
8783 || expr1.X_add_number >= 0x8000)
8784 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8785 gpdelay = reg_needs_delay (mips_gp_register);
8786 relax_start (offset_expr.X_add_symbol);
8787 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8788 BFD_RELOC_MIPS_GOT_HI16);
8789 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8791 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8792 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8795 macro_build (NULL, "nop", "");
8796 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8797 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8799 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8800 tempreg, BFD_RELOC_LO16);
8804 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8805 tempreg, tempreg, breg);
8806 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8808 else if (mips_big_got && HAVE_NEWABI)
8810 /* If this is a reference to an external symbol, we want
8811 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8812 add $tempreg,$tempreg,$gp
8813 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8814 <op> $treg,<ofst>($tempreg)
8815 Otherwise, for local symbols, we want:
8816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8817 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8818 gas_assert (offset_expr.X_op == O_symbol);
8819 expr1.X_add_number = offset_expr.X_add_number;
8820 offset_expr.X_add_number = 0;
8821 if (expr1.X_add_number < -0x8000
8822 || expr1.X_add_number >= 0x8000)
8823 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8824 relax_start (offset_expr.X_add_symbol);
8825 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8826 BFD_RELOC_MIPS_GOT_HI16);
8827 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8829 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8830 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8832 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8833 tempreg, tempreg, breg);
8834 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8837 offset_expr.X_add_number = expr1.X_add_number;
8838 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8839 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8841 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8842 tempreg, tempreg, breg);
8843 macro_build (&offset_expr, s, fmt, treg,
8844 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8854 load_register (treg, &imm_expr, 0);
8858 load_register (treg, &imm_expr, 1);
8862 if (imm_expr.X_op == O_constant)
8865 load_register (AT, &imm_expr, 0);
8866 macro_build (NULL, "mtc1", "t,G", AT, treg);
8871 gas_assert (offset_expr.X_op == O_symbol
8872 && strcmp (segment_name (S_GET_SEGMENT
8873 (offset_expr.X_add_symbol)),
8875 && offset_expr.X_add_number == 0);
8876 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8877 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8882 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8883 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8884 order 32 bits of the value and the low order 32 bits are either
8885 zero or in OFFSET_EXPR. */
8886 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8888 if (HAVE_64BIT_GPRS)
8889 load_register (treg, &imm_expr, 1);
8894 if (target_big_endian)
8906 load_register (hreg, &imm_expr, 0);
8909 if (offset_expr.X_op == O_absent)
8910 move_register (lreg, 0);
8913 gas_assert (offset_expr.X_op == O_constant);
8914 load_register (lreg, &offset_expr, 0);
8921 /* We know that sym is in the .rdata section. First we get the
8922 upper 16 bits of the address. */
8923 if (mips_pic == NO_PIC)
8925 macro_build_lui (&offset_expr, AT);
8930 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8931 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8935 /* Now we load the register(s). */
8936 if (HAVE_64BIT_GPRS)
8939 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8944 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8947 /* FIXME: How in the world do we deal with the possible
8949 offset_expr.X_add_number += 4;
8950 macro_build (&offset_expr, "lw", "t,o(b)",
8951 treg + 1, BFD_RELOC_LO16, AT);
8957 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8958 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8959 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8960 the value and the low order 32 bits are either zero or in
8962 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8965 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8966 if (HAVE_64BIT_FPRS)
8968 gas_assert (HAVE_64BIT_GPRS);
8969 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8973 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8974 if (offset_expr.X_op == O_absent)
8975 macro_build (NULL, "mtc1", "t,G", 0, treg);
8978 gas_assert (offset_expr.X_op == O_constant);
8979 load_register (AT, &offset_expr, 0);
8980 macro_build (NULL, "mtc1", "t,G", AT, treg);
8986 gas_assert (offset_expr.X_op == O_symbol
8987 && offset_expr.X_add_number == 0);
8988 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8989 if (strcmp (s, ".lit8") == 0)
8991 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
8993 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8994 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8997 breg = mips_gp_register;
8998 r = BFD_RELOC_MIPS_LITERAL;
9003 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9005 if (mips_pic != NO_PIC)
9006 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9007 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9010 /* FIXME: This won't work for a 64 bit address. */
9011 macro_build_lui (&offset_expr, AT);
9014 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9016 macro_build (&offset_expr, "ldc1", "T,o(b)",
9017 treg, BFD_RELOC_LO16, AT);
9026 /* Even on a big endian machine $fn comes before $fn+1. We have
9027 to adjust when loading from memory. */
9030 gas_assert (!mips_opts.micromips);
9031 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9032 macro_build (&offset_expr, "lwc1", "T,o(b)",
9033 target_big_endian ? treg + 1 : treg, r, breg);
9034 /* FIXME: A possible overflow which I don't know how to deal
9036 offset_expr.X_add_number += 4;
9037 macro_build (&offset_expr, "lwc1", "T,o(b)",
9038 target_big_endian ? treg : treg + 1, r, breg);
9042 gas_assert (!mips_opts.micromips);
9043 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9044 /* Even on a big endian machine $fn comes before $fn+1. We have
9045 to adjust when storing to memory. */
9046 macro_build (&offset_expr, "swc1", "T,o(b)",
9047 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
9048 offset_expr.X_add_number += 4;
9049 macro_build (&offset_expr, "swc1", "T,o(b)",
9050 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
9054 gas_assert (!mips_opts.micromips);
9056 * The MIPS assembler seems to check for X_add_number not
9057 * being double aligned and generating:
9060 * addiu at,at,%lo(foo+1)
9063 * But, the resulting address is the same after relocation so why
9064 * generate the extra instruction?
9066 /* Itbl support may require additional care here. */
9069 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9078 gas_assert (!mips_opts.micromips);
9079 /* Itbl support may require additional care here. */
9082 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9102 if (HAVE_64BIT_GPRS)
9112 if (HAVE_64BIT_GPRS)
9120 if (offset_expr.X_op != O_symbol
9121 && offset_expr.X_op != O_constant)
9123 as_bad (_("Expression too complex"));
9124 offset_expr.X_op = O_constant;
9127 if (HAVE_32BIT_ADDRESSES
9128 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9132 sprintf_vma (value, offset_expr.X_add_number);
9133 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9136 /* Even on a big endian machine $fn comes before $fn+1. We have
9137 to adjust when loading from memory. We set coproc if we must
9138 load $fn+1 first. */
9139 /* Itbl support may require additional care here. */
9140 if (!target_big_endian)
9143 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9145 /* If this is a reference to a GP relative symbol, we want
9146 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9147 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9148 If we have a base register, we use this
9150 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9151 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9152 If this is not a GP relative symbol, we want
9153 lui $at,<sym> (BFD_RELOC_HI16_S)
9154 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9156 If there is a base register, we add it to $at after the
9157 lui instruction. If there is a constant, we always use
9159 if (offset_expr.X_op == O_symbol
9160 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9161 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9163 relax_start (offset_expr.X_add_symbol);
9166 tempreg = mips_gp_register;
9170 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9171 AT, breg, mips_gp_register);
9176 /* Itbl support may require additional care here. */
9177 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9178 BFD_RELOC_GPREL16, tempreg);
9179 offset_expr.X_add_number += 4;
9181 /* Set mips_optimize to 2 to avoid inserting an
9183 hold_mips_optimize = mips_optimize;
9185 /* Itbl support may require additional care here. */
9186 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9187 BFD_RELOC_GPREL16, tempreg);
9188 mips_optimize = hold_mips_optimize;
9192 offset_expr.X_add_number -= 4;
9195 macro_build_lui (&offset_expr, AT);
9197 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9198 /* Itbl support may require additional care here. */
9199 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9200 BFD_RELOC_LO16, AT);
9201 /* FIXME: How do we handle overflow here? */
9202 offset_expr.X_add_number += 4;
9203 /* Itbl support may require additional care here. */
9204 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9205 BFD_RELOC_LO16, AT);
9206 if (mips_relax.sequence)
9209 else if (!mips_big_got)
9211 /* If this is a reference to an external symbol, we want
9212 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9217 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9219 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9220 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9221 If there is a base register we add it to $at before the
9222 lwc1 instructions. If there is a constant we include it
9223 in the lwc1 instructions. */
9225 expr1.X_add_number = offset_expr.X_add_number;
9226 if (expr1.X_add_number < -0x8000
9227 || expr1.X_add_number >= 0x8000 - 4)
9228 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9229 load_got_offset (AT, &offset_expr);
9232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9234 /* Set mips_optimize to 2 to avoid inserting an undesired
9236 hold_mips_optimize = mips_optimize;
9239 /* Itbl support may require additional care here. */
9240 relax_start (offset_expr.X_add_symbol);
9241 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9242 BFD_RELOC_LO16, AT);
9243 expr1.X_add_number += 4;
9244 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9245 BFD_RELOC_LO16, AT);
9247 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9248 BFD_RELOC_LO16, AT);
9249 offset_expr.X_add_number += 4;
9250 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9251 BFD_RELOC_LO16, AT);
9254 mips_optimize = hold_mips_optimize;
9256 else if (mips_big_got)
9260 /* If this is a reference to an external symbol, we want
9261 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9263 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9268 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9270 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9271 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9272 If there is a base register we add it to $at before the
9273 lwc1 instructions. If there is a constant we include it
9274 in the lwc1 instructions. */
9276 expr1.X_add_number = offset_expr.X_add_number;
9277 offset_expr.X_add_number = 0;
9278 if (expr1.X_add_number < -0x8000
9279 || expr1.X_add_number >= 0x8000 - 4)
9280 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9281 gpdelay = reg_needs_delay (mips_gp_register);
9282 relax_start (offset_expr.X_add_symbol);
9283 macro_build (&offset_expr, "lui", LUI_FMT,
9284 AT, BFD_RELOC_MIPS_GOT_HI16);
9285 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9286 AT, AT, mips_gp_register);
9287 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9288 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9291 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9292 /* Itbl support may require additional care here. */
9293 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9294 BFD_RELOC_LO16, AT);
9295 expr1.X_add_number += 4;
9297 /* Set mips_optimize to 2 to avoid inserting an undesired
9299 hold_mips_optimize = mips_optimize;
9301 /* Itbl support may require additional care here. */
9302 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9303 BFD_RELOC_LO16, AT);
9304 mips_optimize = hold_mips_optimize;
9305 expr1.X_add_number -= 4;
9308 offset_expr.X_add_number = expr1.X_add_number;
9310 macro_build (NULL, "nop", "");
9311 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9312 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9315 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9316 /* Itbl support may require additional care here. */
9317 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9318 BFD_RELOC_LO16, AT);
9319 offset_expr.X_add_number += 4;
9321 /* Set mips_optimize to 2 to avoid inserting an undesired
9323 hold_mips_optimize = mips_optimize;
9325 /* Itbl support may require additional care here. */
9326 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9327 BFD_RELOC_LO16, AT);
9328 mips_optimize = hold_mips_optimize;
9337 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9340 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9342 macro_build (&offset_expr, s, "t,o(b)", treg,
9343 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9345 if (!HAVE_64BIT_GPRS)
9347 offset_expr.X_add_number += 4;
9348 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9349 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9370 /* New code added to support COPZ instructions.
9371 This code builds table entries out of the macros in mip_opcodes.
9372 R4000 uses interlocks to handle coproc delays.
9373 Other chips (like the R3000) require nops to be inserted for delays.
9375 FIXME: Currently, we require that the user handle delays.
9376 In order to fill delay slots for non-interlocked chips,
9377 we must have a way to specify delays based on the coprocessor.
9378 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9379 What are the side-effects of the cop instruction?
9380 What cache support might we have and what are its effects?
9381 Both coprocessor & memory require delays. how long???
9382 What registers are read/set/modified?
9384 If an itbl is provided to interpret cop instructions,
9385 this knowledge can be encoded in the itbl spec. */
9399 gas_assert (!mips_opts.micromips);
9400 /* For now we just do C (same as Cz). The parameter will be
9401 stored in insn_opcode by mips_ip. */
9402 macro_build (NULL, s, "C", ip->insn_opcode);
9406 move_register (dreg, sreg);
9412 if (mips_opts.arch == CPU_R5900)
9414 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9418 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9419 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9426 /* The MIPS assembler some times generates shifts and adds. I'm
9427 not trying to be that fancy. GCC should do this for us
9430 load_register (AT, &imm_expr, dbl);
9431 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9432 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9448 load_register (AT, &imm_expr, dbl);
9449 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9450 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9451 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9452 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9454 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9457 if (mips_opts.micromips)
9458 micromips_label_expr (&label_expr);
9460 label_expr.X_add_number = 8;
9461 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9462 macro_build (NULL, "nop", "");
9463 macro_build (NULL, "break", BRK_FMT, 6);
9464 if (mips_opts.micromips)
9465 micromips_add_label ();
9468 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9484 load_register (AT, &imm_expr, dbl);
9485 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9486 sreg, imm ? AT : treg);
9487 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9488 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9490 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9493 if (mips_opts.micromips)
9494 micromips_label_expr (&label_expr);
9496 label_expr.X_add_number = 8;
9497 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9498 macro_build (NULL, "nop", "");
9499 macro_build (NULL, "break", BRK_FMT, 6);
9500 if (mips_opts.micromips)
9501 micromips_add_label ();
9507 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9518 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9519 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9523 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9524 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9525 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9526 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9530 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9541 macro_build (NULL, "negu", "d,w", tempreg, treg);
9542 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9546 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9547 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9548 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9549 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9558 if (imm_expr.X_op != O_constant)
9559 as_bad (_("Improper rotate count"));
9560 rot = imm_expr.X_add_number & 0x3f;
9561 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9563 rot = (64 - rot) & 0x3f;
9565 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9567 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9572 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9575 l = (rot < 0x20) ? "dsll" : "dsll32";
9576 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9579 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9580 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9581 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9589 if (imm_expr.X_op != O_constant)
9590 as_bad (_("Improper rotate count"));
9591 rot = imm_expr.X_add_number & 0x1f;
9592 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9594 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9599 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9603 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9604 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9605 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9610 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9612 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9616 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9617 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9618 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9619 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9623 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9625 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9629 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9630 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9631 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9632 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9641 if (imm_expr.X_op != O_constant)
9642 as_bad (_("Improper rotate count"));
9643 rot = imm_expr.X_add_number & 0x3f;
9644 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9647 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9649 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9654 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9657 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9658 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9661 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9662 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9663 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9671 if (imm_expr.X_op != O_constant)
9672 as_bad (_("Improper rotate count"));
9673 rot = imm_expr.X_add_number & 0x1f;
9674 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9676 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9681 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9685 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9686 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9687 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9693 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9695 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9698 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9699 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9704 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9706 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9711 as_warn (_("Instruction %s: result is always false"),
9713 move_register (dreg, 0);
9716 if (CPU_HAS_SEQ (mips_opts.arch)
9717 && -512 <= imm_expr.X_add_number
9718 && imm_expr.X_add_number < 512)
9720 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9721 (int) imm_expr.X_add_number);
9724 if (imm_expr.X_op == O_constant
9725 && imm_expr.X_add_number >= 0
9726 && imm_expr.X_add_number < 0x10000)
9728 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9730 else if (imm_expr.X_op == O_constant
9731 && imm_expr.X_add_number > -0x8000
9732 && imm_expr.X_add_number < 0)
9734 imm_expr.X_add_number = -imm_expr.X_add_number;
9735 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9736 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9738 else if (CPU_HAS_SEQ (mips_opts.arch))
9741 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9742 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9747 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9748 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9751 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9754 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9760 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9761 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9764 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9766 if (imm_expr.X_op == O_constant
9767 && imm_expr.X_add_number >= -0x8000
9768 && imm_expr.X_add_number < 0x8000)
9770 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9771 dreg, sreg, BFD_RELOC_LO16);
9775 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9776 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9780 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9783 case M_SGT: /* sreg > treg <==> treg < sreg */
9789 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9792 case M_SGT_I: /* sreg > I <==> I < sreg */
9799 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9800 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9803 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9809 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9810 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9813 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9820 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9821 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9822 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9826 if (imm_expr.X_op == O_constant
9827 && imm_expr.X_add_number >= -0x8000
9828 && imm_expr.X_add_number < 0x8000)
9830 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9834 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9835 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9839 if (imm_expr.X_op == O_constant
9840 && imm_expr.X_add_number >= -0x8000
9841 && imm_expr.X_add_number < 0x8000)
9843 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9848 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9849 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9854 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9856 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9859 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9860 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9865 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9867 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9872 as_warn (_("Instruction %s: result is always true"),
9874 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9875 dreg, 0, BFD_RELOC_LO16);
9878 if (CPU_HAS_SEQ (mips_opts.arch)
9879 && -512 <= imm_expr.X_add_number
9880 && imm_expr.X_add_number < 512)
9882 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9883 (int) imm_expr.X_add_number);
9886 if (imm_expr.X_op == O_constant
9887 && imm_expr.X_add_number >= 0
9888 && imm_expr.X_add_number < 0x10000)
9890 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9892 else if (imm_expr.X_op == O_constant
9893 && imm_expr.X_add_number > -0x8000
9894 && imm_expr.X_add_number < 0)
9896 imm_expr.X_add_number = -imm_expr.X_add_number;
9897 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9898 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9900 else if (CPU_HAS_SEQ (mips_opts.arch))
9903 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9904 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9909 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9910 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9913 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9928 if (!mips_opts.micromips)
9930 if (imm_expr.X_op == O_constant
9931 && imm_expr.X_add_number > -0x200
9932 && imm_expr.X_add_number <= 0x200)
9934 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9943 if (imm_expr.X_op == O_constant
9944 && imm_expr.X_add_number > -0x8000
9945 && imm_expr.X_add_number <= 0x8000)
9947 imm_expr.X_add_number = -imm_expr.X_add_number;
9948 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9953 load_register (AT, &imm_expr, dbl);
9954 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9976 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9977 macro_build (NULL, s, "s,t", sreg, AT);
9982 gas_assert (!mips_opts.micromips);
9983 gas_assert (mips_opts.isa == ISA_MIPS1);
9985 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9986 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9989 * Is the double cfc1 instruction a bug in the mips assembler;
9990 * or is there a reason for it?
9993 macro_build (NULL, "cfc1", "t,G", treg, RA);
9994 macro_build (NULL, "cfc1", "t,G", treg, RA);
9995 macro_build (NULL, "nop", "");
9996 expr1.X_add_number = 3;
9997 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9998 expr1.X_add_number = 2;
9999 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10000 macro_build (NULL, "ctc1", "t,G", AT, RA);
10001 macro_build (NULL, "nop", "");
10002 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10004 macro_build (NULL, "ctc1", "t,G", treg, RA);
10005 macro_build (NULL, "nop", "");
10028 off12 = mips_opts.micromips;
10036 off12 = mips_opts.micromips;
10052 off12 = mips_opts.micromips;
10061 off12 = mips_opts.micromips;
10066 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10067 as_bad (_("Operand overflow"));
10070 expr1.X_add_number = 0;
10075 load_address (tempreg, ep, &used_at);
10077 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10078 tempreg, tempreg, breg);
10084 && (offset_expr.X_op != O_constant
10085 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10086 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10090 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10091 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10096 else if (!ust && treg == breg)
10107 if (!target_big_endian)
10108 ep->X_add_number += off;
10110 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10112 macro_build (NULL, s, "t,~(b)",
10113 tempreg, (unsigned long) ep->X_add_number, breg);
10115 if (!target_big_endian)
10116 ep->X_add_number -= off;
10118 ep->X_add_number += off;
10120 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10122 macro_build (NULL, s2, "t,~(b)",
10123 tempreg, (unsigned long) ep->X_add_number, breg);
10125 /* If necessary, move the result in tempreg to the final destination. */
10126 if (!ust && treg != tempreg)
10128 /* Protect second load's delay slot. */
10130 move_register (treg, tempreg);
10136 if (target_big_endian == ust)
10137 ep->X_add_number += off;
10138 tempreg = ust || ab ? treg : AT;
10139 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10141 /* For halfword transfers we need a temporary register to shuffle
10142 bytes. Unfortunately for M_USH_A we have none available before
10143 the next store as AT holds the base address. We deal with this
10144 case by clobbering TREG and then restoring it as with ULH. */
10145 tempreg = ust == ab ? treg : AT;
10147 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10149 if (target_big_endian == ust)
10150 ep->X_add_number -= off;
10152 ep->X_add_number += off;
10153 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10155 /* For M_USH_A re-retrieve the LSB. */
10158 if (target_big_endian)
10159 ep->X_add_number += off;
10161 ep->X_add_number -= off;
10162 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10164 /* For ULH and M_USH_A OR the LSB in. */
10167 tempreg = !ab ? AT : treg;
10168 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10169 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10174 /* FIXME: Check if this is one of the itbl macros, since they
10175 are added dynamically. */
10176 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10179 if (!mips_opts.at && used_at)
10180 as_bad (_("Macro used $at after \".set noat\""));
10183 /* Implement macros in mips16 mode. */
10186 mips16_macro (struct mips_cl_insn *ip)
10189 int xreg, yreg, zreg, tmp;
10192 const char *s, *s2, *s3;
10194 mask = ip->insn_mo->mask;
10196 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10197 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10198 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10200 expr1.X_op = O_constant;
10201 expr1.X_op_symbol = NULL;
10202 expr1.X_add_symbol = NULL;
10203 expr1.X_add_number = 1;
10222 start_noreorder ();
10223 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10224 expr1.X_add_number = 2;
10225 macro_build (&expr1, "bnez", "x,p", yreg);
10226 macro_build (NULL, "break", "6", 7);
10228 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10229 since that causes an overflow. We should do that as well,
10230 but I don't see how to do the comparisons without a temporary
10233 macro_build (NULL, s, "x", zreg);
10252 start_noreorder ();
10253 macro_build (NULL, s, "0,x,y", xreg, yreg);
10254 expr1.X_add_number = 2;
10255 macro_build (&expr1, "bnez", "x,p", yreg);
10256 macro_build (NULL, "break", "6", 7);
10258 macro_build (NULL, s2, "x", zreg);
10264 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10265 macro_build (NULL, "mflo", "x", zreg);
10273 if (imm_expr.X_op != O_constant)
10274 as_bad (_("Unsupported large constant"));
10275 imm_expr.X_add_number = -imm_expr.X_add_number;
10276 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10280 if (imm_expr.X_op != O_constant)
10281 as_bad (_("Unsupported large constant"));
10282 imm_expr.X_add_number = -imm_expr.X_add_number;
10283 macro_build (&imm_expr, "addiu", "x,k", xreg);
10287 if (imm_expr.X_op != O_constant)
10288 as_bad (_("Unsupported large constant"));
10289 imm_expr.X_add_number = -imm_expr.X_add_number;
10290 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10312 goto do_reverse_branch;
10316 goto do_reverse_branch;
10328 goto do_reverse_branch;
10339 macro_build (NULL, s, "x,y", xreg, yreg);
10340 macro_build (&offset_expr, s2, "p");
10367 goto do_addone_branch_i;
10372 goto do_addone_branch_i;
10387 goto do_addone_branch_i;
10393 do_addone_branch_i:
10394 if (imm_expr.X_op != O_constant)
10395 as_bad (_("Unsupported large constant"));
10396 ++imm_expr.X_add_number;
10399 macro_build (&imm_expr, s, s3, xreg);
10400 macro_build (&offset_expr, s2, "p");
10404 expr1.X_add_number = 0;
10405 macro_build (&expr1, "slti", "x,8", yreg);
10407 move_register (xreg, yreg);
10408 expr1.X_add_number = 2;
10409 macro_build (&expr1, "bteqz", "p");
10410 macro_build (NULL, "neg", "x,w", xreg, xreg);
10414 /* For consistency checking, verify that all bits are specified either
10415 by the match/mask part of the instruction definition, or by the
10418 validate_mips_insn (const struct mips_opcode *opc)
10420 const char *p = opc->args;
10422 unsigned long used_bits = opc->mask;
10424 if ((used_bits & opc->match) != opc->match)
10426 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10427 opc->name, opc->args);
10430 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10440 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10441 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10442 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10443 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10444 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10445 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10446 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10447 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10448 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10449 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10450 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10451 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10452 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10454 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10455 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10456 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10457 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10458 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10459 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10460 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10461 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10462 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10463 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10464 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10465 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10466 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10467 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10468 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10469 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10472 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10473 c, opc->name, opc->args);
10477 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10478 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10480 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10481 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10482 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10483 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10485 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10486 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10488 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10489 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10491 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10492 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10493 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10494 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10495 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10496 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10497 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10498 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10499 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10500 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10501 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10502 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10503 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10504 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10505 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10506 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10507 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10509 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10510 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10511 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10512 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10514 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10515 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10516 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10517 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10518 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10519 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10520 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10521 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10522 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10525 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10526 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10527 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10528 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10529 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10532 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10533 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10534 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10535 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10536 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10537 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10538 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10539 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10540 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10541 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10542 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10543 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10544 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10545 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10546 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10547 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10548 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10549 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10550 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10551 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10553 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10554 c, opc->name, opc->args);
10558 if (used_bits != 0xffffffff)
10560 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10561 ~used_bits & 0xffffffff, opc->name, opc->args);
10567 /* For consistency checking, verify that the length implied matches the
10568 major opcode and that all bits are specified either by the match/mask
10569 part of the instruction definition, or by the operand list. */
10572 validate_micromips_insn (const struct mips_opcode *opc)
10574 unsigned long match = opc->match;
10575 unsigned long mask = opc->mask;
10576 const char *p = opc->args;
10577 unsigned long insn_bits;
10578 unsigned long used_bits;
10579 unsigned long major;
10580 unsigned int length;
10584 if ((mask & match) != match)
10586 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10587 opc->name, opc->args);
10590 length = micromips_insn_length (opc);
10591 if (length != 2 && length != 4)
10593 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10594 "%s %s"), length, opc->name, opc->args);
10597 major = match >> (10 + 8 * (length - 2));
10598 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10599 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10601 as_bad (_("Internal error: bad microMIPS opcode "
10602 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10606 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10607 insn_bits = 1 << 4 * length;
10608 insn_bits <<= 4 * length;
10611 #define USE_BITS(field) \
10612 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10623 case 'A': USE_BITS (EXTLSB); break;
10624 case 'B': USE_BITS (INSMSB); break;
10625 case 'C': USE_BITS (EXTMSBD); break;
10626 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10627 case 'E': USE_BITS (EXTLSB); break;
10628 case 'F': USE_BITS (INSMSB); break;
10629 case 'G': USE_BITS (EXTMSBD); break;
10630 case 'H': USE_BITS (EXTMSBD); break;
10632 as_bad (_("Internal error: bad mips opcode "
10633 "(unknown extension operand type `%c%c'): %s %s"),
10634 e, c, opc->name, opc->args);
10642 case 'A': USE_BITS (IMMA); break;
10643 case 'B': USE_BITS (IMMB); break;
10644 case 'C': USE_BITS (IMMC); break;
10645 case 'D': USE_BITS (IMMD); break;
10646 case 'E': USE_BITS (IMME); break;
10647 case 'F': USE_BITS (IMMF); break;
10648 case 'G': USE_BITS (IMMG); break;
10649 case 'H': USE_BITS (IMMH); break;
10650 case 'I': USE_BITS (IMMI); break;
10651 case 'J': USE_BITS (IMMJ); break;
10652 case 'L': USE_BITS (IMML); break;
10653 case 'M': USE_BITS (IMMM); break;
10654 case 'N': USE_BITS (IMMN); break;
10655 case 'O': USE_BITS (IMMO); break;
10656 case 'P': USE_BITS (IMMP); break;
10657 case 'Q': USE_BITS (IMMQ); break;
10658 case 'U': USE_BITS (IMMU); break;
10659 case 'W': USE_BITS (IMMW); break;
10660 case 'X': USE_BITS (IMMX); break;
10661 case 'Y': USE_BITS (IMMY); break;
10664 case 'b': USE_BITS (MB); break;
10665 case 'c': USE_BITS (MC); break;
10666 case 'd': USE_BITS (MD); break;
10667 case 'e': USE_BITS (ME); break;
10668 case 'f': USE_BITS (MF); break;
10669 case 'g': USE_BITS (MG); break;
10670 case 'h': USE_BITS (MH); break;
10671 case 'i': USE_BITS (MI); break;
10672 case 'j': USE_BITS (MJ); break;
10673 case 'l': USE_BITS (ML); break;
10674 case 'm': USE_BITS (MM); break;
10675 case 'n': USE_BITS (MN); break;
10676 case 'p': USE_BITS (MP); break;
10677 case 'q': USE_BITS (MQ); break;
10685 as_bad (_("Internal error: bad mips opcode "
10686 "(unknown extension operand type `%c%c'): %s %s"),
10687 e, c, opc->name, opc->args);
10691 case '.': USE_BITS (OFFSET10); break;
10692 case '1': USE_BITS (STYPE); break;
10693 case '2': USE_BITS (BP); break;
10694 case '3': USE_BITS (SA3); break;
10695 case '4': USE_BITS (SA4); break;
10696 case '5': USE_BITS (IMM8); break;
10697 case '6': USE_BITS (RS); break;
10698 case '7': USE_BITS (DSPACC); break;
10699 case '8': USE_BITS (WRDSP); break;
10700 case '0': USE_BITS (DSPSFT); break;
10701 case '<': USE_BITS (SHAMT); break;
10702 case '>': USE_BITS (SHAMT); break;
10703 case '@': USE_BITS (IMM10); break;
10704 case 'B': USE_BITS (CODE10); break;
10705 case 'C': USE_BITS (COPZ); break;
10706 case 'D': USE_BITS (FD); break;
10707 case 'E': USE_BITS (RT); break;
10708 case 'G': USE_BITS (RS); break;
10709 case 'H': USE_BITS (SEL); break;
10710 case 'K': USE_BITS (RS); break;
10711 case 'M': USE_BITS (CCC); break;
10712 case 'N': USE_BITS (BCC); break;
10713 case 'R': USE_BITS (FR); break;
10714 case 'S': USE_BITS (FS); break;
10715 case 'T': USE_BITS (FT); break;
10716 case 'V': USE_BITS (FS); break;
10717 case '\\': USE_BITS (3BITPOS); break;
10718 case '^': USE_BITS (RD); break;
10719 case 'a': USE_BITS (TARGET); break;
10720 case 'b': USE_BITS (RS); break;
10721 case 'c': USE_BITS (CODE); break;
10722 case 'd': USE_BITS (RD); break;
10723 case 'h': USE_BITS (PREFX); break;
10724 case 'i': USE_BITS (IMMEDIATE); break;
10725 case 'j': USE_BITS (DELTA); break;
10726 case 'k': USE_BITS (CACHE); break;
10727 case 'n': USE_BITS (RT); break;
10728 case 'o': USE_BITS (DELTA); break;
10729 case 'p': USE_BITS (DELTA); break;
10730 case 'q': USE_BITS (CODE2); break;
10731 case 'r': USE_BITS (RS); break;
10732 case 's': USE_BITS (RS); break;
10733 case 't': USE_BITS (RT); break;
10734 case 'u': USE_BITS (IMMEDIATE); break;
10735 case 'v': USE_BITS (RS); break;
10736 case 'w': USE_BITS (RT); break;
10737 case 'y': USE_BITS (RS3); break;
10739 case '|': USE_BITS (TRAP); break;
10740 case '~': USE_BITS (OFFSET12); break;
10742 as_bad (_("Internal error: bad microMIPS opcode "
10743 "(unknown operand type `%c'): %s %s"),
10744 c, opc->name, opc->args);
10748 if (used_bits != insn_bits)
10750 if (~used_bits & insn_bits)
10751 as_bad (_("Internal error: bad microMIPS opcode "
10752 "(bits 0x%lx undefined): %s %s"),
10753 ~used_bits & insn_bits, opc->name, opc->args);
10754 if (used_bits & ~insn_bits)
10755 as_bad (_("Internal error: bad microMIPS opcode "
10756 "(bits 0x%lx defined): %s %s"),
10757 used_bits & ~insn_bits, opc->name, opc->args);
10763 /* UDI immediates. */
10764 struct mips_immed {
10766 unsigned int shift;
10767 unsigned long mask;
10771 static const struct mips_immed mips_immed[] = {
10772 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10773 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10774 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10775 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10779 /* Check whether an odd floating-point register is allowed. */
10781 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10783 const char *s = insn->name;
10785 if (insn->pinfo == INSN_MACRO)
10786 /* Let a macro pass, we'll catch it later when it is expanded. */
10789 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10791 /* Allow odd registers for single-precision ops. */
10792 switch (insn->pinfo & (FP_S | FP_D))
10796 return 1; /* both single precision - ok */
10798 return 0; /* both double precision - fail */
10803 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10804 s = strchr (insn->name, '.');
10806 s = s != NULL ? strchr (s + 1, '.') : NULL;
10807 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10810 /* Single-precision coprocessor loads and moves are OK too. */
10811 if ((insn->pinfo & FP_S)
10812 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10813 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10819 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10820 taking bits from BIT up. */
10822 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10824 return (ep->X_op == O_constant
10825 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10826 && ep->X_add_number >= min << bit
10827 && ep->X_add_number < max << bit);
10830 /* This routine assembles an instruction into its binary format. As a
10831 side effect, it sets one of the global variables imm_reloc or
10832 offset_reloc to the type of relocation to do if one of the operands
10833 is an address expression. */
10836 mips_ip (char *str, struct mips_cl_insn *ip)
10838 bfd_boolean wrong_delay_slot_insns = FALSE;
10839 bfd_boolean need_delay_slot_ok = TRUE;
10840 struct mips_opcode *firstinsn = NULL;
10841 const struct mips_opcode *past;
10842 struct hash_control *hash;
10846 struct mips_opcode *insn;
10848 unsigned int regno;
10849 unsigned int lastregno;
10850 unsigned int destregno = 0;
10851 unsigned int lastpos = 0;
10852 unsigned int limlo, limhi;
10855 offsetT min_range, max_range;
10859 unsigned int rtype;
10865 if (mips_opts.micromips)
10867 hash = micromips_op_hash;
10868 past = µmips_opcodes[bfd_micromips_num_opcodes];
10873 past = &mips_opcodes[NUMOPCODES];
10875 forced_insn_length = 0;
10878 /* We first try to match an instruction up to a space or to the end. */
10879 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10882 /* Make a copy of the instruction so that we can fiddle with it. */
10883 name = alloca (end + 1);
10884 memcpy (name, str, end);
10889 insn = (struct mips_opcode *) hash_find (hash, name);
10891 if (insn != NULL || !mips_opts.micromips)
10893 if (forced_insn_length)
10896 /* See if there's an instruction size override suffix,
10897 either `16' or `32', at the end of the mnemonic proper,
10898 that defines the operation, i.e. before the first `.'
10899 character if any. Strip it and retry. */
10900 dot = strchr (name, '.');
10901 opend = dot != NULL ? dot - name : end;
10904 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10905 forced_insn_length = 2;
10906 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10907 forced_insn_length = 4;
10910 memcpy (name + opend - 2, name + opend, end - opend + 1);
10914 insn_error = _("Unrecognized opcode");
10918 /* For microMIPS instructions placed in a fixed-length branch delay slot
10919 we make up to two passes over the relevant fragment of the opcode
10920 table. First we try instructions that meet the delay slot's length
10921 requirement. If none matched, then we retry with the remaining ones
10922 and if one matches, then we use it and then issue an appropriate
10923 warning later on. */
10924 argsStart = s = str + end;
10927 bfd_boolean delay_slot_ok;
10928 bfd_boolean size_ok;
10931 gas_assert (strcmp (insn->name, name) == 0);
10933 ok = is_opcode_valid (insn);
10934 size_ok = is_size_valid (insn);
10935 delay_slot_ok = is_delay_slot_valid (insn);
10936 if (!delay_slot_ok && !wrong_delay_slot_insns)
10939 wrong_delay_slot_insns = TRUE;
10941 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10943 static char buf[256];
10945 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10950 if (wrong_delay_slot_insns && need_delay_slot_ok)
10952 gas_assert (firstinsn);
10953 need_delay_slot_ok = FALSE;
10963 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10964 mips_cpu_info_from_arch (mips_opts.arch)->name,
10965 mips_cpu_info_from_isa (mips_opts.isa)->name);
10967 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10968 8 * forced_insn_length);
10974 create_insn (ip, insn);
10977 lastregno = 0xffffffff;
10978 for (args = insn->args;; ++args)
10982 s += strspn (s, " \t");
10986 case '\0': /* end of args */
10992 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10993 code) or 14 (for microMIPS code). */
10994 my_getExpression (&imm_expr, s);
10995 check_absolute_expr (ip, &imm_expr);
10996 if ((unsigned long) imm_expr.X_add_number != 1
10997 && (unsigned long) imm_expr.X_add_number != 3)
10999 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11000 (unsigned long) imm_expr.X_add_number);
11002 INSERT_OPERAND (mips_opts.micromips,
11003 BP, *ip, imm_expr.X_add_number);
11004 imm_expr.X_op = O_absent;
11009 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11010 code) or 21 (for microMIPS code). */
11012 unsigned long mask = (mips_opts.micromips
11013 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11015 my_getExpression (&imm_expr, s);
11016 check_absolute_expr (ip, &imm_expr);
11017 if ((unsigned long) imm_expr.X_add_number > mask)
11018 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11019 mask, (unsigned long) imm_expr.X_add_number);
11020 INSERT_OPERAND (mips_opts.micromips,
11021 SA3, *ip, imm_expr.X_add_number);
11022 imm_expr.X_op = O_absent;
11028 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11029 code) or 21 (for microMIPS code). */
11031 unsigned long mask = (mips_opts.micromips
11032 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11034 my_getExpression (&imm_expr, s);
11035 check_absolute_expr (ip, &imm_expr);
11036 if ((unsigned long) imm_expr.X_add_number > mask)
11037 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11038 mask, (unsigned long) imm_expr.X_add_number);
11039 INSERT_OPERAND (mips_opts.micromips,
11040 SA4, *ip, imm_expr.X_add_number);
11041 imm_expr.X_op = O_absent;
11047 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11048 code) or 16 (for microMIPS code). */
11050 unsigned long mask = (mips_opts.micromips
11051 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11053 my_getExpression (&imm_expr, s);
11054 check_absolute_expr (ip, &imm_expr);
11055 if ((unsigned long) imm_expr.X_add_number > mask)
11056 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11057 mask, (unsigned long) imm_expr.X_add_number);
11058 INSERT_OPERAND (mips_opts.micromips,
11059 IMM8, *ip, imm_expr.X_add_number);
11060 imm_expr.X_op = O_absent;
11066 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11067 code) or 21 (for microMIPS code). */
11069 unsigned long mask = (mips_opts.micromips
11070 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11072 my_getExpression (&imm_expr, s);
11073 check_absolute_expr (ip, &imm_expr);
11074 if ((unsigned long) imm_expr.X_add_number > mask)
11075 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11076 mask, (unsigned long) imm_expr.X_add_number);
11077 INSERT_OPERAND (mips_opts.micromips,
11078 RS, *ip, imm_expr.X_add_number);
11079 imm_expr.X_op = O_absent;
11084 case '7': /* Four DSP accumulators in bits 11,12. */
11085 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11086 && s[3] >= '0' && s[3] <= '3')
11088 regno = s[3] - '0';
11090 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11094 as_bad (_("Invalid dsp acc register"));
11098 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11099 code) or 14 (for microMIPS code). */
11101 unsigned long mask = (mips_opts.micromips
11102 ? MICROMIPSOP_MASK_WRDSP
11105 my_getExpression (&imm_expr, s);
11106 check_absolute_expr (ip, &imm_expr);
11107 if ((unsigned long) imm_expr.X_add_number > mask)
11108 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11109 mask, (unsigned long) imm_expr.X_add_number);
11110 INSERT_OPERAND (mips_opts.micromips,
11111 WRDSP, *ip, imm_expr.X_add_number);
11112 imm_expr.X_op = O_absent;
11117 case '9': /* Four DSP accumulators in bits 21,22. */
11118 gas_assert (!mips_opts.micromips);
11119 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11120 && s[3] >= '0' && s[3] <= '3')
11122 regno = s[3] - '0';
11124 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11128 as_bad (_("Invalid dsp acc register"));
11132 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11133 code) or 20 (for microMIPS code). */
11135 long mask = (mips_opts.micromips
11136 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11138 my_getExpression (&imm_expr, s);
11139 check_absolute_expr (ip, &imm_expr);
11140 min_range = -((mask + 1) >> 1);
11141 max_range = ((mask + 1) >> 1) - 1;
11142 if (imm_expr.X_add_number < min_range
11143 || imm_expr.X_add_number > max_range)
11144 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11145 (long) min_range, (long) max_range,
11146 (long) imm_expr.X_add_number);
11147 INSERT_OPERAND (mips_opts.micromips,
11148 DSPSFT, *ip, imm_expr.X_add_number);
11149 imm_expr.X_op = O_absent;
11154 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11155 gas_assert (!mips_opts.micromips);
11156 my_getExpression (&imm_expr, s);
11157 check_absolute_expr (ip, &imm_expr);
11158 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11160 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11162 (unsigned long) imm_expr.X_add_number);
11164 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11165 imm_expr.X_op = O_absent;
11169 case ':': /* DSP 7-bit signed immediate in bit 19. */
11170 gas_assert (!mips_opts.micromips);
11171 my_getExpression (&imm_expr, s);
11172 check_absolute_expr (ip, &imm_expr);
11173 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11174 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11175 if (imm_expr.X_add_number < min_range ||
11176 imm_expr.X_add_number > max_range)
11178 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11179 (long) min_range, (long) max_range,
11180 (long) imm_expr.X_add_number);
11182 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11183 imm_expr.X_op = O_absent;
11187 case '@': /* DSP 10-bit signed immediate in bit 16. */
11189 long mask = (mips_opts.micromips
11190 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11192 my_getExpression (&imm_expr, s);
11193 check_absolute_expr (ip, &imm_expr);
11194 min_range = -((mask + 1) >> 1);
11195 max_range = ((mask + 1) >> 1) - 1;
11196 if (imm_expr.X_add_number < min_range
11197 || imm_expr.X_add_number > max_range)
11198 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11199 (long) min_range, (long) max_range,
11200 (long) imm_expr.X_add_number);
11201 INSERT_OPERAND (mips_opts.micromips,
11202 IMM10, *ip, imm_expr.X_add_number);
11203 imm_expr.X_op = O_absent;
11208 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11209 gas_assert (mips_opts.micromips);
11210 my_getExpression (&imm_expr, s);
11211 check_absolute_expr (ip, &imm_expr);
11212 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11213 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11214 MICROMIPSOP_MASK_RD,
11215 (unsigned long) imm_expr.X_add_number);
11216 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11217 imm_expr.X_op = O_absent;
11221 case '!': /* MT usermode flag bit. */
11222 gas_assert (!mips_opts.micromips);
11223 my_getExpression (&imm_expr, s);
11224 check_absolute_expr (ip, &imm_expr);
11225 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11226 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11227 (unsigned long) imm_expr.X_add_number);
11228 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11229 imm_expr.X_op = O_absent;
11233 case '$': /* MT load high flag bit. */
11234 gas_assert (!mips_opts.micromips);
11235 my_getExpression (&imm_expr, s);
11236 check_absolute_expr (ip, &imm_expr);
11237 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11238 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11239 (unsigned long) imm_expr.X_add_number);
11240 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11241 imm_expr.X_op = O_absent;
11245 case '*': /* Four DSP accumulators in bits 18,19. */
11246 gas_assert (!mips_opts.micromips);
11247 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11248 s[3] >= '0' && s[3] <= '3')
11250 regno = s[3] - '0';
11252 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11256 as_bad (_("Invalid dsp/smartmips acc register"));
11259 case '&': /* Four DSP accumulators in bits 13,14. */
11260 gas_assert (!mips_opts.micromips);
11261 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11262 s[3] >= '0' && s[3] <= '3')
11264 regno = s[3] - '0';
11266 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11270 as_bad (_("Invalid dsp/smartmips acc register"));
11273 case '\\': /* 3-bit bit position. */
11275 unsigned long mask = (mips_opts.micromips
11276 ? MICROMIPSOP_MASK_3BITPOS
11277 : OP_MASK_3BITPOS);
11279 my_getExpression (&imm_expr, s);
11280 check_absolute_expr (ip, &imm_expr);
11281 if ((unsigned long) imm_expr.X_add_number > mask)
11282 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11284 mask, (unsigned long) imm_expr.X_add_number);
11285 INSERT_OPERAND (mips_opts.micromips,
11286 3BITPOS, *ip, imm_expr.X_add_number);
11287 imm_expr.X_op = O_absent;
11301 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11305 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11309 gas_assert (!mips_opts.micromips);
11310 INSERT_OPERAND (0, FT, *ip, lastregno);
11314 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11320 /* Handle optional base register.
11321 Either the base register is omitted or
11322 we must have a left paren. */
11323 /* This is dependent on the next operand specifier
11324 is a base register specification. */
11325 gas_assert (args[1] == 'b'
11326 || (mips_opts.micromips
11328 && (args[2] == 'l' || args[2] == 'n'
11329 || args[2] == 's' || args[2] == 'a')));
11330 if (*s == '\0' && args[1] == 'b')
11332 /* Fall through. */
11334 case ')': /* These must match exactly. */
11339 case '[': /* These must match exactly. */
11341 gas_assert (!mips_opts.micromips);
11346 case '+': /* Opcode extension character. */
11349 case '1': /* UDI immediates. */
11353 gas_assert (!mips_opts.micromips);
11355 const struct mips_immed *imm = mips_immed;
11357 while (imm->type && imm->type != *args)
11361 my_getExpression (&imm_expr, s);
11362 check_absolute_expr (ip, &imm_expr);
11363 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11365 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11366 imm->desc ? imm->desc : ip->insn_mo->name,
11367 (unsigned long) imm_expr.X_add_number,
11368 (unsigned long) imm_expr.X_add_number);
11369 imm_expr.X_add_number &= imm->mask;
11371 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11373 imm_expr.X_op = O_absent;
11378 case 'J': /* 10-bit hypcall code. */
11379 gas_assert (!mips_opts.micromips);
11381 unsigned long mask = OP_MASK_CODE10;
11383 my_getExpression (&imm_expr, s);
11384 check_absolute_expr (ip, &imm_expr);
11385 if ((unsigned long) imm_expr.X_add_number > mask)
11386 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11388 mask, (unsigned long) imm_expr.X_add_number);
11389 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11390 imm_expr.X_op = O_absent;
11395 case 'A': /* ins/ext position, becomes LSB. */
11404 my_getExpression (&imm_expr, s);
11405 check_absolute_expr (ip, &imm_expr);
11406 if ((unsigned long) imm_expr.X_add_number < limlo
11407 || (unsigned long) imm_expr.X_add_number > limhi)
11409 as_bad (_("Improper position (%lu)"),
11410 (unsigned long) imm_expr.X_add_number);
11411 imm_expr.X_add_number = limlo;
11413 lastpos = imm_expr.X_add_number;
11414 INSERT_OPERAND (mips_opts.micromips,
11415 EXTLSB, *ip, imm_expr.X_add_number);
11416 imm_expr.X_op = O_absent;
11420 case 'B': /* ins size, becomes MSB. */
11429 my_getExpression (&imm_expr, s);
11430 check_absolute_expr (ip, &imm_expr);
11431 /* Check for negative input so that small negative numbers
11432 will not succeed incorrectly. The checks against
11433 (pos+size) transitively check "size" itself,
11434 assuming that "pos" is reasonable. */
11435 if ((long) imm_expr.X_add_number < 0
11436 || ((unsigned long) imm_expr.X_add_number
11438 || ((unsigned long) imm_expr.X_add_number
11439 + lastpos) > limhi)
11441 as_bad (_("Improper insert size (%lu, position %lu)"),
11442 (unsigned long) imm_expr.X_add_number,
11443 (unsigned long) lastpos);
11444 imm_expr.X_add_number = limlo - lastpos;
11446 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11447 lastpos + imm_expr.X_add_number - 1);
11448 imm_expr.X_op = O_absent;
11452 case 'C': /* ext size, becomes MSBD. */
11468 my_getExpression (&imm_expr, s);
11469 check_absolute_expr (ip, &imm_expr);
11470 /* The checks against (pos+size) don't transitively check
11471 "size" itself, assuming that "pos" is reasonable.
11472 We also need to check the lower bound of "size". */
11473 if ((long) imm_expr.X_add_number < sizelo
11474 || ((unsigned long) imm_expr.X_add_number
11476 || ((unsigned long) imm_expr.X_add_number
11477 + lastpos) > limhi)
11479 as_bad (_("Improper extract size (%lu, position %lu)"),
11480 (unsigned long) imm_expr.X_add_number,
11481 (unsigned long) lastpos);
11482 imm_expr.X_add_number = limlo - lastpos;
11484 INSERT_OPERAND (mips_opts.micromips,
11485 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11486 imm_expr.X_op = O_absent;
11491 /* +D is for disassembly only; never match. */
11495 /* "+I" is like "I", except that imm2_expr is used. */
11496 my_getExpression (&imm2_expr, s);
11497 if (imm2_expr.X_op != O_big
11498 && imm2_expr.X_op != O_constant)
11499 insn_error = _("absolute expression required");
11500 if (HAVE_32BIT_GPRS)
11501 normalize_constant_expr (&imm2_expr);
11505 case 'T': /* Coprocessor register. */
11506 gas_assert (!mips_opts.micromips);
11507 /* +T is for disassembly only; never match. */
11510 case 't': /* Coprocessor register number. */
11511 gas_assert (!mips_opts.micromips);
11512 if (s[0] == '$' && ISDIGIT (s[1]))
11522 while (ISDIGIT (*s));
11524 as_bad (_("Invalid register number (%d)"), regno);
11527 INSERT_OPERAND (0, RT, *ip, regno);
11532 as_bad (_("Invalid coprocessor 0 register number"));
11536 /* bbit[01] and bbit[01]32 bit index. Give error if index
11537 is not in the valid range. */
11538 gas_assert (!mips_opts.micromips);
11539 my_getExpression (&imm_expr, s);
11540 check_absolute_expr (ip, &imm_expr);
11541 if ((unsigned) imm_expr.X_add_number > 31)
11543 as_bad (_("Improper bit index (%lu)"),
11544 (unsigned long) imm_expr.X_add_number);
11545 imm_expr.X_add_number = 0;
11547 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11548 imm_expr.X_op = O_absent;
11553 /* bbit[01] bit index when bbit is used but we generate
11554 bbit[01]32 because the index is over 32. Move to the
11555 next candidate if index is not in the valid range. */
11556 gas_assert (!mips_opts.micromips);
11557 my_getExpression (&imm_expr, s);
11558 check_absolute_expr (ip, &imm_expr);
11559 if ((unsigned) imm_expr.X_add_number < 32
11560 || (unsigned) imm_expr.X_add_number > 63)
11562 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11563 imm_expr.X_op = O_absent;
11568 /* cins, cins32, exts and exts32 position field. Give error
11569 if it's not in the valid range. */
11570 gas_assert (!mips_opts.micromips);
11571 my_getExpression (&imm_expr, s);
11572 check_absolute_expr (ip, &imm_expr);
11573 if ((unsigned) imm_expr.X_add_number > 31)
11575 as_bad (_("Improper position (%lu)"),
11576 (unsigned long) imm_expr.X_add_number);
11577 imm_expr.X_add_number = 0;
11579 /* Make the pos explicit to simplify +S. */
11580 lastpos = imm_expr.X_add_number + 32;
11581 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11582 imm_expr.X_op = O_absent;
11587 /* cins, cins32, exts and exts32 position field. Move to
11588 the next candidate if it's not in the valid range. */
11589 gas_assert (!mips_opts.micromips);
11590 my_getExpression (&imm_expr, s);
11591 check_absolute_expr (ip, &imm_expr);
11592 if ((unsigned) imm_expr.X_add_number < 32
11593 || (unsigned) imm_expr.X_add_number > 63)
11595 lastpos = imm_expr.X_add_number;
11596 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11597 imm_expr.X_op = O_absent;
11602 /* cins and exts length-minus-one field. */
11603 gas_assert (!mips_opts.micromips);
11604 my_getExpression (&imm_expr, s);
11605 check_absolute_expr (ip, &imm_expr);
11606 if ((unsigned long) imm_expr.X_add_number > 31)
11608 as_bad (_("Improper size (%lu)"),
11609 (unsigned long) imm_expr.X_add_number);
11610 imm_expr.X_add_number = 0;
11612 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11613 imm_expr.X_op = O_absent;
11618 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11619 length-minus-one field. */
11620 gas_assert (!mips_opts.micromips);
11621 my_getExpression (&imm_expr, s);
11622 check_absolute_expr (ip, &imm_expr);
11623 if ((long) imm_expr.X_add_number < 0
11624 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11626 as_bad (_("Improper size (%lu)"),
11627 (unsigned long) imm_expr.X_add_number);
11628 imm_expr.X_add_number = 0;
11630 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11631 imm_expr.X_op = O_absent;
11636 /* seqi/snei immediate field. */
11637 gas_assert (!mips_opts.micromips);
11638 my_getExpression (&imm_expr, s);
11639 check_absolute_expr (ip, &imm_expr);
11640 if ((long) imm_expr.X_add_number < -512
11641 || (long) imm_expr.X_add_number >= 512)
11643 as_bad (_("Improper immediate (%ld)"),
11644 (long) imm_expr.X_add_number);
11645 imm_expr.X_add_number = 0;
11647 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11648 imm_expr.X_op = O_absent;
11652 case 'a': /* 8-bit signed offset in bit 6 */
11653 gas_assert (!mips_opts.micromips);
11654 my_getExpression (&imm_expr, s);
11655 check_absolute_expr (ip, &imm_expr);
11656 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11657 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11658 if (imm_expr.X_add_number < min_range
11659 || imm_expr.X_add_number > max_range)
11661 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11662 (long) min_range, (long) max_range,
11663 (long) imm_expr.X_add_number);
11665 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11666 imm_expr.X_op = O_absent;
11670 case 'b': /* 8-bit signed offset in bit 3 */
11671 gas_assert (!mips_opts.micromips);
11672 my_getExpression (&imm_expr, s);
11673 check_absolute_expr (ip, &imm_expr);
11674 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11675 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11676 if (imm_expr.X_add_number < min_range
11677 || imm_expr.X_add_number > max_range)
11679 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11680 (long) min_range, (long) max_range,
11681 (long) imm_expr.X_add_number);
11683 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11684 imm_expr.X_op = O_absent;
11688 case 'c': /* 9-bit signed offset in bit 6 */
11689 gas_assert (!mips_opts.micromips);
11690 my_getExpression (&imm_expr, s);
11691 check_absolute_expr (ip, &imm_expr);
11692 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11693 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11694 /* We check the offset range before adjusted. */
11697 if (imm_expr.X_add_number < min_range
11698 || imm_expr.X_add_number > max_range)
11700 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11701 (long) min_range, (long) max_range,
11702 (long) imm_expr.X_add_number);
11704 if (imm_expr.X_add_number & 0xf)
11706 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11707 (long) imm_expr.X_add_number);
11709 /* Right shift 4 bits to adjust the offset operand. */
11710 INSERT_OPERAND (0, OFFSET_C, *ip,
11711 imm_expr.X_add_number >> 4);
11712 imm_expr.X_op = O_absent;
11717 gas_assert (!mips_opts.micromips);
11718 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11720 if (regno == AT && mips_opts.at)
11722 if (mips_opts.at == ATREG)
11723 as_warn (_("used $at without \".set noat\""));
11725 as_warn (_("used $%u with \".set at=$%u\""),
11726 regno, mips_opts.at);
11728 INSERT_OPERAND (0, RZ, *ip, regno);
11732 gas_assert (!mips_opts.micromips);
11733 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11735 INSERT_OPERAND (0, FZ, *ip, regno);
11739 as_bad (_("Internal error: bad %s opcode "
11740 "(unknown extension operand type `+%c'): %s %s"),
11741 mips_opts.micromips ? "microMIPS" : "MIPS",
11742 *args, insn->name, insn->args);
11743 /* Further processing is fruitless. */
11748 case '.': /* 10-bit offset. */
11749 gas_assert (mips_opts.micromips);
11750 case '~': /* 12-bit offset. */
11752 int shift = *args == '.' ? 9 : 11;
11755 /* Check whether there is only a single bracketed expression
11756 left. If so, it must be the base register and the
11757 constant must be zero. */
11758 if (*s == '(' && strchr (s + 1, '(') == 0)
11761 /* If this value won't fit into the offset, then go find
11762 a macro that will generate a 16- or 32-bit offset code
11764 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11765 if ((i == 0 && (imm_expr.X_op != O_constant
11766 || imm_expr.X_add_number >= 1 << shift
11767 || imm_expr.X_add_number < -1 << shift))
11770 imm_expr.X_op = O_absent;
11774 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11776 INSERT_OPERAND (mips_opts.micromips,
11777 OFFSET12, *ip, imm_expr.X_add_number);
11778 imm_expr.X_op = O_absent;
11783 case '<': /* must be at least one digit */
11785 * According to the manual, if the shift amount is greater
11786 * than 31 or less than 0, then the shift amount should be
11787 * mod 32. In reality the mips assembler issues an error.
11788 * We issue a warning and mask out all but the low 5 bits.
11790 my_getExpression (&imm_expr, s);
11791 check_absolute_expr (ip, &imm_expr);
11792 if ((unsigned long) imm_expr.X_add_number > 31)
11793 as_warn (_("Improper shift amount (%lu)"),
11794 (unsigned long) imm_expr.X_add_number);
11795 INSERT_OPERAND (mips_opts.micromips,
11796 SHAMT, *ip, imm_expr.X_add_number);
11797 imm_expr.X_op = O_absent;
11801 case '>': /* shift amount minus 32 */
11802 my_getExpression (&imm_expr, s);
11803 check_absolute_expr (ip, &imm_expr);
11804 if ((unsigned long) imm_expr.X_add_number < 32
11805 || (unsigned long) imm_expr.X_add_number > 63)
11807 INSERT_OPERAND (mips_opts.micromips,
11808 SHAMT, *ip, imm_expr.X_add_number - 32);
11809 imm_expr.X_op = O_absent;
11813 case 'k': /* CACHE code. */
11814 case 'h': /* PREFX code. */
11815 case '1': /* SYNC type. */
11816 my_getExpression (&imm_expr, s);
11817 check_absolute_expr (ip, &imm_expr);
11818 if ((unsigned long) imm_expr.X_add_number > 31)
11819 as_warn (_("Invalid value for `%s' (%lu)"),
11821 (unsigned long) imm_expr.X_add_number);
11825 if (mips_fix_cn63xxp1
11826 && !mips_opts.micromips
11827 && strcmp ("pref", insn->name) == 0)
11828 switch (imm_expr.X_add_number)
11837 case 31: /* These are ok. */
11840 default: /* The rest must be changed to 28. */
11841 imm_expr.X_add_number = 28;
11844 INSERT_OPERAND (mips_opts.micromips,
11845 CACHE, *ip, imm_expr.X_add_number);
11848 INSERT_OPERAND (mips_opts.micromips,
11849 PREFX, *ip, imm_expr.X_add_number);
11852 INSERT_OPERAND (mips_opts.micromips,
11853 STYPE, *ip, imm_expr.X_add_number);
11856 imm_expr.X_op = O_absent;
11860 case 'c': /* BREAK code. */
11862 unsigned long mask = (mips_opts.micromips
11863 ? MICROMIPSOP_MASK_CODE
11866 my_getExpression (&imm_expr, s);
11867 check_absolute_expr (ip, &imm_expr);
11868 if ((unsigned long) imm_expr.X_add_number > mask)
11869 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11871 mask, (unsigned long) imm_expr.X_add_number);
11872 INSERT_OPERAND (mips_opts.micromips,
11873 CODE, *ip, imm_expr.X_add_number);
11874 imm_expr.X_op = O_absent;
11879 case 'q': /* Lower BREAK code. */
11881 unsigned long mask = (mips_opts.micromips
11882 ? MICROMIPSOP_MASK_CODE2
11885 my_getExpression (&imm_expr, s);
11886 check_absolute_expr (ip, &imm_expr);
11887 if ((unsigned long) imm_expr.X_add_number > mask)
11888 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11890 mask, (unsigned long) imm_expr.X_add_number);
11891 INSERT_OPERAND (mips_opts.micromips,
11892 CODE2, *ip, imm_expr.X_add_number);
11893 imm_expr.X_op = O_absent;
11898 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11900 unsigned long mask = (mips_opts.micromips
11901 ? MICROMIPSOP_MASK_CODE10
11904 my_getExpression (&imm_expr, s);
11905 check_absolute_expr (ip, &imm_expr);
11906 if ((unsigned long) imm_expr.X_add_number > mask)
11907 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11909 mask, (unsigned long) imm_expr.X_add_number);
11910 if (mips_opts.micromips)
11911 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11913 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11914 imm_expr.X_op = O_absent;
11919 case 'C': /* 25- or 23-bit coprocessor code. */
11921 unsigned long mask = (mips_opts.micromips
11922 ? MICROMIPSOP_MASK_COPZ
11925 my_getExpression (&imm_expr, s);
11926 check_absolute_expr (ip, &imm_expr);
11927 if ((unsigned long) imm_expr.X_add_number > mask)
11928 as_warn (_("Coproccesor code > %u bits (%lu)"),
11929 mips_opts.micromips ? 23U : 25U,
11930 (unsigned long) imm_expr.X_add_number);
11931 INSERT_OPERAND (mips_opts.micromips,
11932 COPZ, *ip, imm_expr.X_add_number);
11933 imm_expr.X_op = O_absent;
11938 case 'J': /* 19-bit WAIT code. */
11939 gas_assert (!mips_opts.micromips);
11940 my_getExpression (&imm_expr, s);
11941 check_absolute_expr (ip, &imm_expr);
11942 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11944 as_warn (_("Illegal 19-bit code (%lu)"),
11945 (unsigned long) imm_expr.X_add_number);
11946 imm_expr.X_add_number &= OP_MASK_CODE19;
11948 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11949 imm_expr.X_op = O_absent;
11953 case 'P': /* Performance register. */
11954 gas_assert (!mips_opts.micromips);
11955 my_getExpression (&imm_expr, s);
11956 check_absolute_expr (ip, &imm_expr);
11957 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11958 as_warn (_("Invalid performance register (%lu)"),
11959 (unsigned long) imm_expr.X_add_number);
11960 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
11961 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
11962 as_warn (_("Invalid performance register (%lu)"),
11963 (unsigned long) imm_expr.X_add_number);
11964 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11965 imm_expr.X_op = O_absent;
11969 case 'G': /* Coprocessor destination register. */
11971 unsigned long opcode = ip->insn_opcode;
11972 unsigned long mask;
11973 unsigned int types;
11976 if (mips_opts.micromips)
11978 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11979 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11980 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11984 case 0x000000fc: /* mfc0 */
11985 case 0x000002fc: /* mtc0 */
11986 case 0x580000fc: /* dmfc0 */
11987 case 0x580002fc: /* dmtc0 */
11997 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11998 cop0 = opcode == OP_OP_COP0;
12000 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12001 ok = reg_lookup (&s, types, ®no);
12002 if (mips_opts.micromips)
12003 INSERT_OPERAND (1, RS, *ip, regno);
12005 INSERT_OPERAND (0, RD, *ip, regno);
12014 case 'y': /* ALNV.PS source register. */
12015 gas_assert (mips_opts.micromips);
12017 case 'x': /* Ignore register name. */
12018 case 'U': /* Destination register (CLO/CLZ). */
12019 case 'g': /* Coprocessor destination register. */
12020 gas_assert (!mips_opts.micromips);
12021 case 'b': /* Base register. */
12022 case 'd': /* Destination register. */
12023 case 's': /* Source register. */
12024 case 't': /* Target register. */
12025 case 'r': /* Both target and source. */
12026 case 'v': /* Both dest and source. */
12027 case 'w': /* Both dest and target. */
12028 case 'E': /* Coprocessor target register. */
12029 case 'K': /* RDHWR destination register. */
12030 case 'z': /* Must be zero register. */
12033 if (*args == 'E' || *args == 'K')
12034 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12037 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12038 if (regno == AT && mips_opts.at)
12040 if (mips_opts.at == ATREG)
12041 as_warn (_("Used $at without \".set noat\""));
12043 as_warn (_("Used $%u with \".set at=$%u\""),
12044 regno, mips_opts.at);
12054 if (c == 'r' || c == 'v' || c == 'w')
12061 /* 'z' only matches $0. */
12062 if (c == 'z' && regno != 0)
12065 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12067 if (regno == lastregno)
12070 = _("Source and destination must be different");
12073 if (regno == 31 && lastregno == 0xffffffff)
12076 = _("A destination register must be supplied");
12080 /* Now that we have assembled one operand, we use the args
12081 string to figure out where it goes in the instruction. */
12088 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12092 if (mips_opts.micromips)
12093 INSERT_OPERAND (1, RS, *ip, regno);
12095 INSERT_OPERAND (0, RD, *ip, regno);
12100 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12104 gas_assert (!mips_opts.micromips);
12105 INSERT_OPERAND (0, RD, *ip, regno);
12106 INSERT_OPERAND (0, RT, *ip, regno);
12112 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12116 gas_assert (mips_opts.micromips);
12117 INSERT_OPERAND (1, RS3, *ip, regno);
12121 /* This case exists because on the r3000 trunc
12122 expands into a macro which requires a gp
12123 register. On the r6000 or r4000 it is
12124 assembled into a single instruction which
12125 ignores the register. Thus the insn version
12126 is MIPS_ISA2 and uses 'x', and the macro
12127 version is MIPS_ISA1 and uses 't'. */
12131 /* This case is for the div instruction, which
12132 acts differently if the destination argument
12133 is $0. This only matches $0, and is checked
12134 outside the switch. */
12144 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12148 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12153 case 'O': /* MDMX alignment immediate constant. */
12154 gas_assert (!mips_opts.micromips);
12155 my_getExpression (&imm_expr, s);
12156 check_absolute_expr (ip, &imm_expr);
12157 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12158 as_warn (_("Improper align amount (%ld), using low bits"),
12159 (long) imm_expr.X_add_number);
12160 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12161 imm_expr.X_op = O_absent;
12165 case 'Q': /* MDMX vector, element sel, or const. */
12168 /* MDMX Immediate. */
12169 gas_assert (!mips_opts.micromips);
12170 my_getExpression (&imm_expr, s);
12171 check_absolute_expr (ip, &imm_expr);
12172 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12173 as_warn (_("Invalid MDMX Immediate (%ld)"),
12174 (long) imm_expr.X_add_number);
12175 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12176 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12177 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12179 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12180 imm_expr.X_op = O_absent;
12184 /* Not MDMX Immediate. Fall through. */
12185 case 'X': /* MDMX destination register. */
12186 case 'Y': /* MDMX source register. */
12187 case 'Z': /* MDMX target register. */
12190 gas_assert (!mips_opts.micromips);
12191 case 'D': /* Floating point destination register. */
12192 case 'S': /* Floating point source register. */
12193 case 'T': /* Floating point target register. */
12194 case 'R': /* Floating point source register. */
12198 || (mips_opts.ase_mdmx
12199 && (ip->insn_mo->pinfo & FP_D)
12200 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12201 | INSN_COPROC_MEMORY_DELAY
12202 | INSN_LOAD_COPROC_DELAY
12203 | INSN_LOAD_MEMORY_DELAY
12204 | INSN_STORE_MEMORY))))
12205 rtype |= RTYPE_VEC;
12207 if (reg_lookup (&s, rtype, ®no))
12209 if ((regno & 1) != 0
12211 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12212 as_warn (_("Float register should be even, was %d"),
12220 if (c == 'V' || c == 'W')
12231 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12237 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12241 /* This is like 'Z', but also needs to fix the MDMX
12242 vector/scalar select bits. Note that the
12243 scalar immediate case is handled above. */
12246 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12247 int max_el = (is_qh ? 3 : 7);
12249 my_getExpression(&imm_expr, s);
12250 check_absolute_expr (ip, &imm_expr);
12252 if (imm_expr.X_add_number > max_el)
12253 as_bad (_("Bad element selector %ld"),
12254 (long) imm_expr.X_add_number);
12255 imm_expr.X_add_number &= max_el;
12256 ip->insn_opcode |= (imm_expr.X_add_number
12259 imm_expr.X_op = O_absent;
12261 as_warn (_("Expecting ']' found '%s'"), s);
12267 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12268 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12271 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12274 /* Fall through. */
12278 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12282 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12292 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12296 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12302 my_getExpression (&imm_expr, s);
12303 if (imm_expr.X_op != O_big
12304 && imm_expr.X_op != O_constant)
12305 insn_error = _("absolute expression required");
12306 if (HAVE_32BIT_GPRS)
12307 normalize_constant_expr (&imm_expr);
12312 my_getExpression (&offset_expr, s);
12313 normalize_address_expr (&offset_expr);
12314 *imm_reloc = BFD_RELOC_32;
12327 unsigned char temp[8];
12329 unsigned int length;
12334 /* These only appear as the last operand in an
12335 instruction, and every instruction that accepts
12336 them in any variant accepts them in all variants.
12337 This means we don't have to worry about backing out
12338 any changes if the instruction does not match.
12340 The difference between them is the size of the
12341 floating point constant and where it goes. For 'F'
12342 and 'L' the constant is 64 bits; for 'f' and 'l' it
12343 is 32 bits. Where the constant is placed is based
12344 on how the MIPS assembler does things:
12347 f -- immediate value
12350 The .lit4 and .lit8 sections are only used if
12351 permitted by the -G argument.
12353 The code below needs to know whether the target register
12354 is 32 or 64 bits wide. It relies on the fact 'f' and
12355 'F' are used with GPR-based instructions and 'l' and
12356 'L' are used with FPR-based instructions. */
12358 f64 = *args == 'F' || *args == 'L';
12359 using_gprs = *args == 'F' || *args == 'f';
12361 save_in = input_line_pointer;
12362 input_line_pointer = s;
12363 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12365 s = input_line_pointer;
12366 input_line_pointer = save_in;
12367 if (err != NULL && *err != '\0')
12369 as_bad (_("Bad floating point constant: %s"), err);
12370 memset (temp, '\0', sizeof temp);
12371 length = f64 ? 8 : 4;
12374 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12378 && (g_switch_value < 4
12379 || (temp[0] == 0 && temp[1] == 0)
12380 || (temp[2] == 0 && temp[3] == 0))))
12382 imm_expr.X_op = O_constant;
12383 if (!target_big_endian)
12384 imm_expr.X_add_number = bfd_getl32 (temp);
12386 imm_expr.X_add_number = bfd_getb32 (temp);
12388 else if (length > 4
12389 && !mips_disable_float_construction
12390 /* Constants can only be constructed in GPRs and
12391 copied to FPRs if the GPRs are at least as wide
12392 as the FPRs. Force the constant into memory if
12393 we are using 64-bit FPRs but the GPRs are only
12396 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12397 && ((temp[0] == 0 && temp[1] == 0)
12398 || (temp[2] == 0 && temp[3] == 0))
12399 && ((temp[4] == 0 && temp[5] == 0)
12400 || (temp[6] == 0 && temp[7] == 0)))
12402 /* The value is simple enough to load with a couple of
12403 instructions. If using 32-bit registers, set
12404 imm_expr to the high order 32 bits and offset_expr to
12405 the low order 32 bits. Otherwise, set imm_expr to
12406 the entire 64 bit constant. */
12407 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12409 imm_expr.X_op = O_constant;
12410 offset_expr.X_op = O_constant;
12411 if (!target_big_endian)
12413 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12414 offset_expr.X_add_number = bfd_getl32 (temp);
12418 imm_expr.X_add_number = bfd_getb32 (temp);
12419 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12421 if (offset_expr.X_add_number == 0)
12422 offset_expr.X_op = O_absent;
12424 else if (sizeof (imm_expr.X_add_number) > 4)
12426 imm_expr.X_op = O_constant;
12427 if (!target_big_endian)
12428 imm_expr.X_add_number = bfd_getl64 (temp);
12430 imm_expr.X_add_number = bfd_getb64 (temp);
12434 imm_expr.X_op = O_big;
12435 imm_expr.X_add_number = 4;
12436 if (!target_big_endian)
12438 generic_bignum[0] = bfd_getl16 (temp);
12439 generic_bignum[1] = bfd_getl16 (temp + 2);
12440 generic_bignum[2] = bfd_getl16 (temp + 4);
12441 generic_bignum[3] = bfd_getl16 (temp + 6);
12445 generic_bignum[0] = bfd_getb16 (temp + 6);
12446 generic_bignum[1] = bfd_getb16 (temp + 4);
12447 generic_bignum[2] = bfd_getb16 (temp + 2);
12448 generic_bignum[3] = bfd_getb16 (temp);
12454 const char *newname;
12457 /* Switch to the right section. */
12459 subseg = now_subseg;
12462 default: /* unused default case avoids warnings. */
12464 newname = RDATA_SECTION_NAME;
12465 if (g_switch_value >= 8)
12469 newname = RDATA_SECTION_NAME;
12472 gas_assert (g_switch_value >= 4);
12476 new_seg = subseg_new (newname, (subsegT) 0);
12478 bfd_set_section_flags (stdoutput, new_seg,
12483 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12484 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12485 record_alignment (new_seg, 4);
12487 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12488 if (seg == now_seg)
12489 as_bad (_("Can't use floating point insn in this section"));
12491 /* Set the argument to the current address in the
12493 offset_expr.X_op = O_symbol;
12494 offset_expr.X_add_symbol = symbol_temp_new_now ();
12495 offset_expr.X_add_number = 0;
12497 /* Put the floating point number into the section. */
12498 p = frag_more ((int) length);
12499 memcpy (p, temp, length);
12501 /* Switch back to the original section. */
12502 subseg_set (seg, subseg);
12507 case 'i': /* 16-bit unsigned immediate. */
12508 case 'j': /* 16-bit signed immediate. */
12509 *imm_reloc = BFD_RELOC_LO16;
12510 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12513 offsetT minval, maxval;
12515 more = (insn + 1 < past
12516 && strcmp (insn->name, insn[1].name) == 0);
12518 /* If the expression was written as an unsigned number,
12519 only treat it as signed if there are no more
12523 && sizeof (imm_expr.X_add_number) <= 4
12524 && imm_expr.X_op == O_constant
12525 && imm_expr.X_add_number < 0
12526 && imm_expr.X_unsigned
12527 && HAVE_64BIT_GPRS)
12530 /* For compatibility with older assemblers, we accept
12531 0x8000-0xffff as signed 16-bit numbers when only
12532 signed numbers are allowed. */
12534 minval = 0, maxval = 0xffff;
12536 minval = -0x8000, maxval = 0x7fff;
12538 minval = -0x8000, maxval = 0xffff;
12540 if (imm_expr.X_op != O_constant
12541 || imm_expr.X_add_number < minval
12542 || imm_expr.X_add_number > maxval)
12546 if (imm_expr.X_op == O_constant
12547 || imm_expr.X_op == O_big)
12548 as_bad (_("Expression out of range"));
12554 case 'o': /* 16-bit offset. */
12555 offset_reloc[0] = BFD_RELOC_LO16;
12556 offset_reloc[1] = BFD_RELOC_UNUSED;
12557 offset_reloc[2] = BFD_RELOC_UNUSED;
12559 /* Check whether there is only a single bracketed expression
12560 left. If so, it must be the base register and the
12561 constant must be zero. */
12562 if (*s == '(' && strchr (s + 1, '(') == 0)
12564 offset_expr.X_op = O_constant;
12565 offset_expr.X_add_number = 0;
12569 /* If this value won't fit into a 16 bit offset, then go
12570 find a macro that will generate the 32 bit offset
12572 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12573 && (offset_expr.X_op != O_constant
12574 || offset_expr.X_add_number >= 0x8000
12575 || offset_expr.X_add_number < -0x8000))
12581 case 'p': /* PC-relative offset. */
12582 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12583 my_getExpression (&offset_expr, s);
12587 case 'u': /* Upper 16 bits. */
12588 *imm_reloc = BFD_RELOC_LO16;
12589 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12590 && imm_expr.X_op == O_constant
12591 && (imm_expr.X_add_number < 0
12592 || imm_expr.X_add_number >= 0x10000))
12593 as_bad (_("lui expression (%lu) not in range 0..65535"),
12594 (unsigned long) imm_expr.X_add_number);
12598 case 'a': /* 26-bit address. */
12599 *offset_reloc = BFD_RELOC_MIPS_JMP;
12600 my_getExpression (&offset_expr, s);
12604 case 'N': /* 3-bit branch condition code. */
12605 case 'M': /* 3-bit compare condition code. */
12607 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12608 rtype |= RTYPE_FCC;
12609 if (!reg_lookup (&s, rtype, ®no))
12611 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12612 || strcmp (str + strlen (str) - 5, "any2f") == 0
12613 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12614 && (regno & 1) != 0)
12615 as_warn (_("Condition code register should be even for %s, "
12618 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12619 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12620 && (regno & 3) != 0)
12621 as_warn (_("Condition code register should be 0 or 4 for %s, "
12625 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12627 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12631 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12642 while (ISDIGIT (*s));
12645 c = 8; /* Invalid sel value. */
12648 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12649 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12653 gas_assert (!mips_opts.micromips);
12654 /* Must be at least one digit. */
12655 my_getExpression (&imm_expr, s);
12656 check_absolute_expr (ip, &imm_expr);
12658 if ((unsigned long) imm_expr.X_add_number
12659 > (unsigned long) OP_MASK_VECBYTE)
12661 as_bad (_("bad byte vector index (%ld)"),
12662 (long) imm_expr.X_add_number);
12663 imm_expr.X_add_number = 0;
12666 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12667 imm_expr.X_op = O_absent;
12672 gas_assert (!mips_opts.micromips);
12673 my_getExpression (&imm_expr, s);
12674 check_absolute_expr (ip, &imm_expr);
12676 if ((unsigned long) imm_expr.X_add_number
12677 > (unsigned long) OP_MASK_VECALIGN)
12679 as_bad (_("bad byte vector index (%ld)"),
12680 (long) imm_expr.X_add_number);
12681 imm_expr.X_add_number = 0;
12684 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12685 imm_expr.X_op = O_absent;
12689 case 'm': /* Opcode extension character. */
12690 gas_assert (mips_opts.micromips);
12695 if (strncmp (s, "$pc", 3) == 0)
12723 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12724 if (regno == AT && mips_opts.at)
12726 if (mips_opts.at == ATREG)
12727 as_warn (_("Used $at without \".set noat\""));
12729 as_warn (_("Used $%u with \".set at=$%u\""),
12730 regno, mips_opts.at);
12736 gas_assert (args[1] == ',');
12742 gas_assert (args[1] == ',');
12744 continue; /* Nothing to do. */
12750 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12752 if (regno == lastregno)
12755 = _("Source and destination must be different");
12758 if (regno == 31 && lastregno == 0xffffffff)
12761 = _("A destination register must be supplied");
12772 gas_assert (args[1] == ',');
12779 gas_assert (args[1] == ',');
12782 continue; /* Nothing to do. */
12786 /* Make sure regno is the same as lastregno. */
12787 if (c == 't' && regno != lastregno)
12790 /* Make sure regno is the same as destregno. */
12791 if (c == 'x' && regno != destregno)
12794 /* We need to save regno, before regno maps to the
12795 microMIPS register encoding. */
12805 regno = ILLEGAL_REG;
12809 regno = mips32_to_micromips_reg_b_map[regno];
12813 regno = mips32_to_micromips_reg_c_map[regno];
12817 regno = mips32_to_micromips_reg_d_map[regno];
12821 regno = mips32_to_micromips_reg_e_map[regno];
12825 regno = mips32_to_micromips_reg_f_map[regno];
12829 regno = mips32_to_micromips_reg_g_map[regno];
12833 regno = mips32_to_micromips_reg_h_map[regno];
12837 switch (EXTRACT_OPERAND (1, MI, *ip))
12842 else if (regno == 22)
12844 else if (regno == 5)
12846 else if (regno == 6)
12848 else if (regno == 7)
12851 regno = ILLEGAL_REG;
12857 else if (regno == 7)
12860 regno = ILLEGAL_REG;
12867 regno = ILLEGAL_REG;
12871 regno = ILLEGAL_REG;
12877 regno = mips32_to_micromips_reg_l_map[regno];
12881 regno = mips32_to_micromips_reg_m_map[regno];
12885 regno = mips32_to_micromips_reg_n_map[regno];
12889 regno = mips32_to_micromips_reg_q_map[regno];
12894 regno = ILLEGAL_REG;
12899 regno = ILLEGAL_REG;
12904 regno = ILLEGAL_REG;
12907 case 'j': /* Do nothing. */
12917 if (regno == ILLEGAL_REG)
12923 INSERT_OPERAND (1, MB, *ip, regno);
12927 INSERT_OPERAND (1, MC, *ip, regno);
12931 INSERT_OPERAND (1, MD, *ip, regno);
12935 INSERT_OPERAND (1, ME, *ip, regno);
12939 INSERT_OPERAND (1, MF, *ip, regno);
12943 INSERT_OPERAND (1, MG, *ip, regno);
12947 INSERT_OPERAND (1, MH, *ip, regno);
12951 INSERT_OPERAND (1, MI, *ip, regno);
12955 INSERT_OPERAND (1, MJ, *ip, regno);
12959 INSERT_OPERAND (1, ML, *ip, regno);
12963 INSERT_OPERAND (1, MM, *ip, regno);
12967 INSERT_OPERAND (1, MN, *ip, regno);
12971 INSERT_OPERAND (1, MP, *ip, regno);
12975 INSERT_OPERAND (1, MQ, *ip, regno);
12978 case 'a': /* Do nothing. */
12979 case 's': /* Do nothing. */
12980 case 't': /* Do nothing. */
12981 case 'x': /* Do nothing. */
12982 case 'y': /* Do nothing. */
12983 case 'z': /* Do nothing. */
12993 bfd_reloc_code_real_type r[3];
12997 /* Check whether there is only a single bracketed
12998 expression left. If so, it must be the base register
12999 and the constant must be zero. */
13000 if (*s == '(' && strchr (s + 1, '(') == 0)
13002 INSERT_OPERAND (1, IMMA, *ip, 0);
13006 if (my_getSmallExpression (&ep, r, s) > 0
13007 || !expr_const_in_range (&ep, -64, 64, 2))
13010 imm = ep.X_add_number >> 2;
13011 INSERT_OPERAND (1, IMMA, *ip, imm);
13018 bfd_reloc_code_real_type r[3];
13022 if (my_getSmallExpression (&ep, r, s) > 0
13023 || ep.X_op != O_constant)
13026 for (imm = 0; imm < 8; imm++)
13027 if (micromips_imm_b_map[imm] == ep.X_add_number)
13032 INSERT_OPERAND (1, IMMB, *ip, imm);
13039 bfd_reloc_code_real_type r[3];
13043 if (my_getSmallExpression (&ep, r, s) > 0
13044 || ep.X_op != O_constant)
13047 for (imm = 0; imm < 16; imm++)
13048 if (micromips_imm_c_map[imm] == ep.X_add_number)
13053 INSERT_OPERAND (1, IMMC, *ip, imm);
13058 case 'D': /* pc relative offset */
13059 case 'E': /* pc relative offset */
13060 my_getExpression (&offset_expr, s);
13061 if (offset_expr.X_op == O_register)
13064 if (!forced_insn_length)
13065 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13067 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13069 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13075 bfd_reloc_code_real_type r[3];
13079 if (my_getSmallExpression (&ep, r, s) > 0
13080 || !expr_const_in_range (&ep, 0, 16, 0))
13083 imm = ep.X_add_number;
13084 INSERT_OPERAND (1, IMMF, *ip, imm);
13091 bfd_reloc_code_real_type r[3];
13095 /* Check whether there is only a single bracketed
13096 expression left. If so, it must be the base register
13097 and the constant must be zero. */
13098 if (*s == '(' && strchr (s + 1, '(') == 0)
13100 INSERT_OPERAND (1, IMMG, *ip, 0);
13104 if (my_getSmallExpression (&ep, r, s) > 0
13105 || !expr_const_in_range (&ep, -1, 15, 0))
13108 imm = ep.X_add_number & 15;
13109 INSERT_OPERAND (1, IMMG, *ip, imm);
13116 bfd_reloc_code_real_type r[3];
13120 /* Check whether there is only a single bracketed
13121 expression left. If so, it must be the base register
13122 and the constant must be zero. */
13123 if (*s == '(' && strchr (s + 1, '(') == 0)
13125 INSERT_OPERAND (1, IMMH, *ip, 0);
13129 if (my_getSmallExpression (&ep, r, s) > 0
13130 || !expr_const_in_range (&ep, 0, 16, 1))
13133 imm = ep.X_add_number >> 1;
13134 INSERT_OPERAND (1, IMMH, *ip, imm);
13141 bfd_reloc_code_real_type r[3];
13145 if (my_getSmallExpression (&ep, r, s) > 0
13146 || !expr_const_in_range (&ep, -1, 127, 0))
13149 imm = ep.X_add_number & 127;
13150 INSERT_OPERAND (1, IMMI, *ip, imm);
13157 bfd_reloc_code_real_type r[3];
13161 /* Check whether there is only a single bracketed
13162 expression left. If so, it must be the base register
13163 and the constant must be zero. */
13164 if (*s == '(' && strchr (s + 1, '(') == 0)
13166 INSERT_OPERAND (1, IMMJ, *ip, 0);
13170 if (my_getSmallExpression (&ep, r, s) > 0
13171 || !expr_const_in_range (&ep, 0, 16, 2))
13174 imm = ep.X_add_number >> 2;
13175 INSERT_OPERAND (1, IMMJ, *ip, imm);
13182 bfd_reloc_code_real_type r[3];
13186 /* Check whether there is only a single bracketed
13187 expression left. If so, it must be the base register
13188 and the constant must be zero. */
13189 if (*s == '(' && strchr (s + 1, '(') == 0)
13191 INSERT_OPERAND (1, IMML, *ip, 0);
13195 if (my_getSmallExpression (&ep, r, s) > 0
13196 || !expr_const_in_range (&ep, 0, 16, 0))
13199 imm = ep.X_add_number;
13200 INSERT_OPERAND (1, IMML, *ip, imm);
13207 bfd_reloc_code_real_type r[3];
13211 if (my_getSmallExpression (&ep, r, s) > 0
13212 || !expr_const_in_range (&ep, 1, 9, 0))
13215 imm = ep.X_add_number & 7;
13216 INSERT_OPERAND (1, IMMM, *ip, imm);
13221 case 'N': /* Register list for lwm and swm. */
13223 /* A comma-separated list of registers and/or
13224 dash-separated contiguous ranges including
13225 both ra and a set of one or more registers
13226 starting at s0 up to s3 which have to be
13233 and any permutations of these. */
13234 unsigned int reglist;
13237 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13240 if ((reglist & 0xfff1ffff) != 0x80010000)
13243 reglist = (reglist >> 17) & 7;
13245 if ((reglist & -reglist) != reglist)
13248 imm = ffs (reglist) - 1;
13249 INSERT_OPERAND (1, IMMN, *ip, imm);
13253 case 'O': /* sdbbp 4-bit code. */
13255 bfd_reloc_code_real_type r[3];
13259 if (my_getSmallExpression (&ep, r, s) > 0
13260 || !expr_const_in_range (&ep, 0, 16, 0))
13263 imm = ep.X_add_number;
13264 INSERT_OPERAND (1, IMMO, *ip, imm);
13271 bfd_reloc_code_real_type r[3];
13275 if (my_getSmallExpression (&ep, r, s) > 0
13276 || !expr_const_in_range (&ep, 0, 32, 2))
13279 imm = ep.X_add_number >> 2;
13280 INSERT_OPERAND (1, IMMP, *ip, imm);
13287 bfd_reloc_code_real_type r[3];
13291 if (my_getSmallExpression (&ep, r, s) > 0
13292 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13295 imm = ep.X_add_number >> 2;
13296 INSERT_OPERAND (1, IMMQ, *ip, imm);
13303 bfd_reloc_code_real_type r[3];
13307 /* Check whether there is only a single bracketed
13308 expression left. If so, it must be the base register
13309 and the constant must be zero. */
13310 if (*s == '(' && strchr (s + 1, '(') == 0)
13312 INSERT_OPERAND (1, IMMU, *ip, 0);
13316 if (my_getSmallExpression (&ep, r, s) > 0
13317 || !expr_const_in_range (&ep, 0, 32, 2))
13320 imm = ep.X_add_number >> 2;
13321 INSERT_OPERAND (1, IMMU, *ip, imm);
13328 bfd_reloc_code_real_type r[3];
13332 if (my_getSmallExpression (&ep, r, s) > 0
13333 || !expr_const_in_range (&ep, 0, 64, 2))
13336 imm = ep.X_add_number >> 2;
13337 INSERT_OPERAND (1, IMMW, *ip, imm);
13344 bfd_reloc_code_real_type r[3];
13348 if (my_getSmallExpression (&ep, r, s) > 0
13349 || !expr_const_in_range (&ep, -8, 8, 0))
13352 imm = ep.X_add_number;
13353 INSERT_OPERAND (1, IMMX, *ip, imm);
13360 bfd_reloc_code_real_type r[3];
13364 if (my_getSmallExpression (&ep, r, s) > 0
13365 || expr_const_in_range (&ep, -2, 2, 2)
13366 || !expr_const_in_range (&ep, -258, 258, 2))
13369 imm = ep.X_add_number >> 2;
13370 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13371 INSERT_OPERAND (1, IMMY, *ip, imm);
13378 bfd_reloc_code_real_type r[3];
13381 if (my_getSmallExpression (&ep, r, s) > 0
13382 || !expr_const_in_range (&ep, 0, 1, 0))
13389 as_bad (_("Internal error: bad microMIPS opcode "
13390 "(unknown extension operand type `m%c'): %s %s"),
13391 *args, insn->name, insn->args);
13392 /* Further processing is fruitless. */
13397 case 'n': /* Register list for 32-bit lwm and swm. */
13398 gas_assert (mips_opts.micromips);
13400 /* A comma-separated list of registers and/or
13401 dash-separated contiguous ranges including
13402 at least one of ra and a set of one or more
13403 registers starting at s0 up to s7 and then
13404 s8 which have to be consecutive, e.g.:
13412 and any permutations of these. */
13413 unsigned int reglist;
13417 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13420 if ((reglist & 0x3f00ffff) != 0)
13423 ra = (reglist >> 27) & 0x10;
13424 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13426 if ((reglist & -reglist) != reglist)
13429 imm = (ffs (reglist) - 1) | ra;
13430 INSERT_OPERAND (1, RT, *ip, imm);
13431 imm_expr.X_op = O_absent;
13435 case '|': /* 4-bit trap code. */
13436 gas_assert (mips_opts.micromips);
13437 my_getExpression (&imm_expr, s);
13438 check_absolute_expr (ip, &imm_expr);
13439 if ((unsigned long) imm_expr.X_add_number
13440 > MICROMIPSOP_MASK_TRAP)
13441 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13442 (unsigned long) imm_expr.X_add_number,
13443 ip->insn_mo->name);
13444 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13445 imm_expr.X_op = O_absent;
13450 as_bad (_("Bad char = '%c'\n"), *args);
13455 /* Args don't match. */
13457 insn_error = _("Illegal operands");
13458 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13463 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13465 gas_assert (firstinsn);
13466 need_delay_slot_ok = FALSE;
13475 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13477 /* This routine assembles an instruction into its binary format when
13478 assembling for the mips16. As a side effect, it sets one of the
13479 global variables imm_reloc or offset_reloc to the type of relocation
13480 to do if one of the operands is an address expression. It also sets
13481 forced_insn_length to the resulting instruction size in bytes if the
13482 user explicitly requested a small or extended instruction. */
13485 mips16_ip (char *str, struct mips_cl_insn *ip)
13489 struct mips_opcode *insn;
13491 unsigned int regno;
13492 unsigned int lastregno = 0;
13498 forced_insn_length = 0;
13500 for (s = str; ISLOWER (*s); ++s)
13512 if (s[1] == 't' && s[2] == ' ')
13515 forced_insn_length = 2;
13519 else if (s[1] == 'e' && s[2] == ' ')
13522 forced_insn_length = 4;
13526 /* Fall through. */
13528 insn_error = _("unknown opcode");
13532 if (mips_opts.noautoextend && !forced_insn_length)
13533 forced_insn_length = 2;
13535 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13537 insn_error = _("unrecognized opcode");
13546 gas_assert (strcmp (insn->name, str) == 0);
13548 ok = is_opcode_valid_16 (insn);
13551 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13552 && strcmp (insn->name, insn[1].name) == 0)
13561 static char buf[100];
13563 _("Opcode not supported on this processor: %s (%s)"),
13564 mips_cpu_info_from_arch (mips_opts.arch)->name,
13565 mips_cpu_info_from_isa (mips_opts.isa)->name);
13572 create_insn (ip, insn);
13573 imm_expr.X_op = O_absent;
13574 imm_reloc[0] = BFD_RELOC_UNUSED;
13575 imm_reloc[1] = BFD_RELOC_UNUSED;
13576 imm_reloc[2] = BFD_RELOC_UNUSED;
13577 imm2_expr.X_op = O_absent;
13578 offset_expr.X_op = O_absent;
13579 offset_reloc[0] = BFD_RELOC_UNUSED;
13580 offset_reloc[1] = BFD_RELOC_UNUSED;
13581 offset_reloc[2] = BFD_RELOC_UNUSED;
13582 for (args = insn->args; 1; ++args)
13589 /* In this switch statement we call break if we did not find
13590 a match, continue if we did find a match, or return if we
13601 /* Stuff the immediate value in now, if we can. */
13602 if (imm_expr.X_op == O_constant
13603 && *imm_reloc > BFD_RELOC_UNUSED
13604 && insn->pinfo != INSN_MACRO
13605 && calculate_reloc (*offset_reloc,
13606 imm_expr.X_add_number, &value))
13608 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13609 *offset_reloc, value, forced_insn_length,
13611 imm_expr.X_op = O_absent;
13612 *imm_reloc = BFD_RELOC_UNUSED;
13613 *offset_reloc = BFD_RELOC_UNUSED;
13627 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13630 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13646 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13648 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13652 /* Fall through. */
13663 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13665 if (c == 'v' || c == 'w')
13668 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13670 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13681 if (c == 'v' || c == 'w')
13683 regno = mips16_to_32_reg_map[lastregno];
13697 regno = mips32_to_16_reg_map[regno];
13702 regno = ILLEGAL_REG;
13707 regno = ILLEGAL_REG;
13712 regno = ILLEGAL_REG;
13717 if (regno == AT && mips_opts.at)
13719 if (mips_opts.at == ATREG)
13720 as_warn (_("used $at without \".set noat\""));
13722 as_warn (_("used $%u with \".set at=$%u\""),
13723 regno, mips_opts.at);
13731 if (regno == ILLEGAL_REG)
13738 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13742 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13745 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13748 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13754 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13757 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13758 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13768 if (strncmp (s, "$pc", 3) == 0)
13785 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13788 if (imm_expr.X_op != O_constant)
13790 forced_insn_length = 4;
13791 ip->insn_opcode |= MIPS16_EXTEND;
13795 /* We need to relax this instruction. */
13796 *offset_reloc = *imm_reloc;
13797 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13802 *imm_reloc = BFD_RELOC_UNUSED;
13803 /* Fall through. */
13810 my_getExpression (&imm_expr, s);
13811 if (imm_expr.X_op == O_register)
13813 /* What we thought was an expression turned out to
13816 if (s[0] == '(' && args[1] == '(')
13818 /* It looks like the expression was omitted
13819 before a register indirection, which means
13820 that the expression is implicitly zero. We
13821 still set up imm_expr, so that we handle
13822 explicit extensions correctly. */
13823 imm_expr.X_op = O_constant;
13824 imm_expr.X_add_number = 0;
13825 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13832 /* We need to relax this instruction. */
13833 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13842 /* We use offset_reloc rather than imm_reloc for the PC
13843 relative operands. This lets macros with both
13844 immediate and address operands work correctly. */
13845 my_getExpression (&offset_expr, s);
13847 if (offset_expr.X_op == O_register)
13850 /* We need to relax this instruction. */
13851 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13855 case '6': /* break code */
13856 my_getExpression (&imm_expr, s);
13857 check_absolute_expr (ip, &imm_expr);
13858 if ((unsigned long) imm_expr.X_add_number > 63)
13859 as_warn (_("Invalid value for `%s' (%lu)"),
13861 (unsigned long) imm_expr.X_add_number);
13862 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13863 imm_expr.X_op = O_absent;
13867 case 'a': /* 26 bit address */
13868 my_getExpression (&offset_expr, s);
13870 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13871 ip->insn_opcode <<= 16;
13874 case 'l': /* register list for entry macro */
13875 case 'L': /* register list for exit macro */
13885 unsigned int freg, reg1, reg2;
13887 while (*s == ' ' || *s == ',')
13889 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13891 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13895 as_bad (_("can't parse register list"));
13905 if (!reg_lookup (&s, freg ? RTYPE_FPU
13906 : (RTYPE_GP | RTYPE_NUM), ®2))
13908 as_bad (_("invalid register list"));
13912 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13914 mask &= ~ (7 << 3);
13917 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13919 mask &= ~ (7 << 3);
13922 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13923 mask |= (reg2 - 3) << 3;
13924 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13925 mask |= (reg2 - 15) << 1;
13926 else if (reg1 == RA && reg2 == RA)
13930 as_bad (_("invalid register list"));
13934 /* The mask is filled in in the opcode table for the
13935 benefit of the disassembler. We remove it before
13936 applying the actual mask. */
13937 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13938 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13942 case 'm': /* Register list for save insn. */
13943 case 'M': /* Register list for restore insn. */
13945 int opcode = ip->insn_opcode;
13946 int framesz = 0, seen_framesz = 0;
13947 int nargs = 0, statics = 0, sregs = 0;
13951 unsigned int reg1, reg2;
13953 SKIP_SPACE_TABS (s);
13956 SKIP_SPACE_TABS (s);
13958 my_getExpression (&imm_expr, s);
13959 if (imm_expr.X_op == O_constant)
13961 /* Handle the frame size. */
13964 as_bad (_("more than one frame size in list"));
13968 framesz = imm_expr.X_add_number;
13969 imm_expr.X_op = O_absent;
13974 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13976 as_bad (_("can't parse register list"));
13988 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13991 as_bad (_("can't parse register list"));
13996 while (reg1 <= reg2)
13998 if (reg1 >= 4 && reg1 <= 7)
14002 nargs |= 1 << (reg1 - 4);
14004 /* statics $a0-$a3 */
14005 statics |= 1 << (reg1 - 4);
14007 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14010 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14012 else if (reg1 == 31)
14014 /* Add $ra to insn. */
14019 as_bad (_("unexpected register in list"));
14027 /* Encode args/statics combination. */
14028 if (nargs & statics)
14029 as_bad (_("arg/static registers overlap"));
14030 else if (nargs == 0xf)
14031 /* All $a0-$a3 are args. */
14032 opcode |= MIPS16_ALL_ARGS << 16;
14033 else if (statics == 0xf)
14034 /* All $a0-$a3 are statics. */
14035 opcode |= MIPS16_ALL_STATICS << 16;
14038 int narg = 0, nstat = 0;
14040 /* Count arg registers. */
14041 while (nargs & 0x1)
14047 as_bad (_("invalid arg register list"));
14049 /* Count static registers. */
14050 while (statics & 0x8)
14052 statics = (statics << 1) & 0xf;
14056 as_bad (_("invalid static register list"));
14058 /* Encode args/statics. */
14059 opcode |= ((narg << 2) | nstat) << 16;
14062 /* Encode $s0/$s1. */
14063 if (sregs & (1 << 0)) /* $s0 */
14065 if (sregs & (1 << 1)) /* $s1 */
14071 /* Count regs $s2-$s8. */
14079 as_bad (_("invalid static register list"));
14080 /* Encode $s2-$s8. */
14081 opcode |= nsreg << 24;
14084 /* Encode frame size. */
14086 as_bad (_("missing frame size"));
14087 else if ((framesz & 7) != 0 || framesz < 0
14088 || framesz > 0xff * 8)
14089 as_bad (_("invalid frame size"));
14090 else if (framesz != 128 || (opcode >> 16) != 0)
14093 opcode |= (((framesz & 0xf0) << 16)
14094 | (framesz & 0x0f));
14097 /* Finally build the instruction. */
14098 if ((opcode >> 16) != 0 || framesz == 0)
14099 opcode |= MIPS16_EXTEND;
14100 ip->insn_opcode = opcode;
14104 case 'e': /* extend code */
14105 my_getExpression (&imm_expr, s);
14106 check_absolute_expr (ip, &imm_expr);
14107 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14109 as_warn (_("Invalid value for `%s' (%lu)"),
14111 (unsigned long) imm_expr.X_add_number);
14112 imm_expr.X_add_number &= 0x7ff;
14114 ip->insn_opcode |= imm_expr.X_add_number;
14115 imm_expr.X_op = O_absent;
14125 /* Args don't match. */
14126 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14127 strcmp (insn->name, insn[1].name) == 0)
14134 insn_error = _("illegal operands");
14140 /* This structure holds information we know about a mips16 immediate
14143 struct mips16_immed_operand
14145 /* The type code used in the argument string in the opcode table. */
14147 /* The number of bits in the short form of the opcode. */
14149 /* The number of bits in the extended form of the opcode. */
14151 /* The amount by which the short form is shifted when it is used;
14152 for example, the sw instruction has a shift count of 2. */
14154 /* The amount by which the short form is shifted when it is stored
14155 into the instruction code. */
14157 /* Non-zero if the short form is unsigned. */
14159 /* Non-zero if the extended form is unsigned. */
14161 /* Non-zero if the value is PC relative. */
14165 /* The mips16 immediate operand types. */
14167 static const struct mips16_immed_operand mips16_immed_operands[] =
14169 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14170 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14171 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14172 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14173 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14174 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14175 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14176 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14177 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14178 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14179 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14180 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14181 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14182 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14183 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14184 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14185 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14186 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14187 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14188 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14189 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14192 #define MIPS16_NUM_IMMED \
14193 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14195 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14196 NBITS is the number of significant bits in VAL. */
14198 static unsigned long
14199 mips16_immed_extend (offsetT val, unsigned int nbits)
14204 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14207 else if (nbits == 15)
14209 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14214 extval = ((val & 0x1f) << 6) | (val & 0x20);
14217 return (extval << 16) | val;
14220 /* Install immediate value VAL into MIPS16 instruction *INSN,
14221 extending it if necessary. The instruction in *INSN may
14222 already be extended.
14224 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14225 if none. In the former case, VAL is a 16-bit number with no
14226 defined signedness.
14228 TYPE is the type of the immediate field. USER_INSN_LENGTH
14229 is the length that the user requested, or 0 if none. */
14232 mips16_immed (char *file, unsigned int line, int type,
14233 bfd_reloc_code_real_type reloc, offsetT val,
14234 unsigned int user_insn_length, unsigned long *insn)
14236 const struct mips16_immed_operand *op;
14237 int mintiny, maxtiny;
14239 op = mips16_immed_operands;
14240 while (op->type != type)
14243 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14248 if (type == '<' || type == '>' || type == '[' || type == ']')
14251 maxtiny = 1 << op->nbits;
14256 maxtiny = (1 << op->nbits) - 1;
14258 if (reloc != BFD_RELOC_UNUSED)
14263 mintiny = - (1 << (op->nbits - 1));
14264 maxtiny = (1 << (op->nbits - 1)) - 1;
14265 if (reloc != BFD_RELOC_UNUSED)
14266 val = SEXT_16BIT (val);
14269 /* Branch offsets have an implicit 0 in the lowest bit. */
14270 if (type == 'p' || type == 'q')
14273 if ((val & ((1 << op->shift) - 1)) != 0
14274 || val < (mintiny << op->shift)
14275 || val > (maxtiny << op->shift))
14277 /* We need an extended instruction. */
14278 if (user_insn_length == 2)
14279 as_bad_where (file, line, _("invalid unextended operand value"));
14281 *insn |= MIPS16_EXTEND;
14283 else if (user_insn_length == 4)
14285 /* The operand doesn't force an unextended instruction to be extended.
14286 Warn if the user wanted an extended instruction anyway. */
14287 *insn |= MIPS16_EXTEND;
14288 as_warn_where (file, line,
14289 _("extended operand requested but not required"));
14292 if (mips16_opcode_length (*insn) == 2)
14296 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14297 insnval <<= op->op_shift;
14302 long minext, maxext;
14304 if (reloc == BFD_RELOC_UNUSED)
14309 maxext = (1 << op->extbits) - 1;
14313 minext = - (1 << (op->extbits - 1));
14314 maxext = (1 << (op->extbits - 1)) - 1;
14316 if (val < minext || val > maxext)
14317 as_bad_where (file, line,
14318 _("operand value out of range for instruction"));
14321 *insn |= mips16_immed_extend (val, op->extbits);
14325 struct percent_op_match
14328 bfd_reloc_code_real_type reloc;
14331 static const struct percent_op_match mips_percent_op[] =
14333 {"%lo", BFD_RELOC_LO16},
14335 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14336 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14337 {"%call16", BFD_RELOC_MIPS_CALL16},
14338 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14339 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14340 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14341 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14342 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14343 {"%got", BFD_RELOC_MIPS_GOT16},
14344 {"%gp_rel", BFD_RELOC_GPREL16},
14345 {"%half", BFD_RELOC_16},
14346 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14347 {"%higher", BFD_RELOC_MIPS_HIGHER},
14348 {"%neg", BFD_RELOC_MIPS_SUB},
14349 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14350 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14351 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14352 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14353 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14354 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14355 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14357 {"%hi", BFD_RELOC_HI16_S}
14360 static const struct percent_op_match mips16_percent_op[] =
14362 {"%lo", BFD_RELOC_MIPS16_LO16},
14363 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14364 {"%got", BFD_RELOC_MIPS16_GOT16},
14365 {"%call16", BFD_RELOC_MIPS16_CALL16},
14366 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14367 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14368 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14369 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14370 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14371 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14372 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14373 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14377 /* Return true if *STR points to a relocation operator. When returning true,
14378 move *STR over the operator and store its relocation code in *RELOC.
14379 Leave both *STR and *RELOC alone when returning false. */
14382 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14384 const struct percent_op_match *percent_op;
14387 if (mips_opts.mips16)
14389 percent_op = mips16_percent_op;
14390 limit = ARRAY_SIZE (mips16_percent_op);
14394 percent_op = mips_percent_op;
14395 limit = ARRAY_SIZE (mips_percent_op);
14398 for (i = 0; i < limit; i++)
14399 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14401 int len = strlen (percent_op[i].str);
14403 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14406 *str += strlen (percent_op[i].str);
14407 *reloc = percent_op[i].reloc;
14409 /* Check whether the output BFD supports this relocation.
14410 If not, issue an error and fall back on something safe. */
14411 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14413 as_bad (_("relocation %s isn't supported by the current ABI"),
14414 percent_op[i].str);
14415 *reloc = BFD_RELOC_UNUSED;
14423 /* Parse string STR as a 16-bit relocatable operand. Store the
14424 expression in *EP and the relocations in the array starting
14425 at RELOC. Return the number of relocation operators used.
14427 On exit, EXPR_END points to the first character after the expression. */
14430 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14433 bfd_reloc_code_real_type reversed_reloc[3];
14434 size_t reloc_index, i;
14435 int crux_depth, str_depth;
14438 /* Search for the start of the main expression, recoding relocations
14439 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14440 of the main expression and with CRUX_DEPTH containing the number
14441 of open brackets at that point. */
14448 crux_depth = str_depth;
14450 /* Skip over whitespace and brackets, keeping count of the number
14452 while (*str == ' ' || *str == '\t' || *str == '(')
14457 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14458 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14460 my_getExpression (ep, crux);
14463 /* Match every open bracket. */
14464 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14468 if (crux_depth > 0)
14469 as_bad (_("unclosed '('"));
14473 if (reloc_index != 0)
14475 prev_reloc_op_frag = frag_now;
14476 for (i = 0; i < reloc_index; i++)
14477 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14480 return reloc_index;
14484 my_getExpression (expressionS *ep, char *str)
14488 save_in = input_line_pointer;
14489 input_line_pointer = str;
14491 expr_end = input_line_pointer;
14492 input_line_pointer = save_in;
14496 md_atof (int type, char *litP, int *sizeP)
14498 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14502 md_number_to_chars (char *buf, valueT val, int n)
14504 if (target_big_endian)
14505 number_to_chars_bigendian (buf, val, n);
14507 number_to_chars_littleendian (buf, val, n);
14511 static int support_64bit_objects(void)
14513 const char **list, **l;
14516 list = bfd_target_list ();
14517 for (l = list; *l != NULL; l++)
14518 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14519 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14521 yes = (*l != NULL);
14525 #endif /* OBJ_ELF */
14527 const char *md_shortopts = "O::g::G:";
14531 OPTION_MARCH = OPTION_MD_BASE,
14555 OPTION_NO_SMARTMIPS,
14559 OPTION_NO_MICROMIPS,
14562 OPTION_COMPAT_ARCH_BASE,
14571 OPTION_M7000_HILO_FIX,
14572 OPTION_MNO_7000_HILO_FIX,
14575 OPTION_FIX_LOONGSON2F_JUMP,
14576 OPTION_NO_FIX_LOONGSON2F_JUMP,
14577 OPTION_FIX_LOONGSON2F_NOP,
14578 OPTION_NO_FIX_LOONGSON2F_NOP,
14580 OPTION_NO_FIX_VR4120,
14582 OPTION_NO_FIX_VR4130,
14583 OPTION_FIX_CN63XXP1,
14584 OPTION_NO_FIX_CN63XXP1,
14591 OPTION_CONSTRUCT_FLOATS,
14592 OPTION_NO_CONSTRUCT_FLOATS,
14595 OPTION_RELAX_BRANCH,
14596 OPTION_NO_RELAX_BRANCH,
14603 OPTION_SINGLE_FLOAT,
14604 OPTION_DOUBLE_FLOAT,
14607 OPTION_CALL_SHARED,
14608 OPTION_CALL_NONPIC,
14618 OPTION_MVXWORKS_PIC,
14619 #endif /* OBJ_ELF */
14623 struct option md_longopts[] =
14625 /* Options which specify architecture. */
14626 {"march", required_argument, NULL, OPTION_MARCH},
14627 {"mtune", required_argument, NULL, OPTION_MTUNE},
14628 {"mips0", no_argument, NULL, OPTION_MIPS1},
14629 {"mips1", no_argument, NULL, OPTION_MIPS1},
14630 {"mips2", no_argument, NULL, OPTION_MIPS2},
14631 {"mips3", no_argument, NULL, OPTION_MIPS3},
14632 {"mips4", no_argument, NULL, OPTION_MIPS4},
14633 {"mips5", no_argument, NULL, OPTION_MIPS5},
14634 {"mips32", no_argument, NULL, OPTION_MIPS32},
14635 {"mips64", no_argument, NULL, OPTION_MIPS64},
14636 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14637 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14639 /* Options which specify Application Specific Extensions (ASEs). */
14640 {"mips16", no_argument, NULL, OPTION_MIPS16},
14641 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14642 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14643 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14644 {"mdmx", no_argument, NULL, OPTION_MDMX},
14645 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14646 {"mdsp", no_argument, NULL, OPTION_DSP},
14647 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14648 {"mmt", no_argument, NULL, OPTION_MT},
14649 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14650 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14651 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14652 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14653 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14654 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14655 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14656 {"mmcu", no_argument, NULL, OPTION_MCU},
14657 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14658 {"mvirt", no_argument, NULL, OPTION_VIRT},
14659 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
14661 /* Old-style architecture options. Don't add more of these. */
14662 {"m4650", no_argument, NULL, OPTION_M4650},
14663 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14664 {"m4010", no_argument, NULL, OPTION_M4010},
14665 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14666 {"m4100", no_argument, NULL, OPTION_M4100},
14667 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14668 {"m3900", no_argument, NULL, OPTION_M3900},
14669 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14671 /* Options which enable bug fixes. */
14672 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14673 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14674 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14675 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14676 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14677 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14678 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14679 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14680 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14681 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14682 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14683 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14684 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14685 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14686 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14688 /* Miscellaneous options. */
14689 {"trap", no_argument, NULL, OPTION_TRAP},
14690 {"no-break", no_argument, NULL, OPTION_TRAP},
14691 {"break", no_argument, NULL, OPTION_BREAK},
14692 {"no-trap", no_argument, NULL, OPTION_BREAK},
14693 {"EB", no_argument, NULL, OPTION_EB},
14694 {"EL", no_argument, NULL, OPTION_EL},
14695 {"mfp32", no_argument, NULL, OPTION_FP32},
14696 {"mgp32", no_argument, NULL, OPTION_GP32},
14697 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14698 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14699 {"mfp64", no_argument, NULL, OPTION_FP64},
14700 {"mgp64", no_argument, NULL, OPTION_GP64},
14701 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14702 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14703 {"mshared", no_argument, NULL, OPTION_MSHARED},
14704 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14705 {"msym32", no_argument, NULL, OPTION_MSYM32},
14706 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14707 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14708 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14709 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14710 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14712 /* Strictly speaking this next option is ELF specific,
14713 but we allow it for other ports as well in order to
14714 make testing easier. */
14715 {"32", no_argument, NULL, OPTION_32},
14717 /* ELF-specific options. */
14719 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14720 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14721 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14722 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14723 {"xgot", no_argument, NULL, OPTION_XGOT},
14724 {"mabi", required_argument, NULL, OPTION_MABI},
14725 {"n32", no_argument, NULL, OPTION_N32},
14726 {"64", no_argument, NULL, OPTION_64},
14727 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14728 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14729 {"mpdr", no_argument, NULL, OPTION_PDR},
14730 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14731 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14732 #endif /* OBJ_ELF */
14734 {NULL, no_argument, NULL, 0}
14736 size_t md_longopts_size = sizeof (md_longopts);
14738 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14739 NEW_VALUE. Warn if another value was already specified. Note:
14740 we have to defer parsing the -march and -mtune arguments in order
14741 to handle 'from-abi' correctly, since the ABI might be specified
14742 in a later argument. */
14745 mips_set_option_string (const char **string_ptr, const char *new_value)
14747 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14748 as_warn (_("A different %s was already specified, is now %s"),
14749 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14752 *string_ptr = new_value;
14756 md_parse_option (int c, char *arg)
14760 case OPTION_CONSTRUCT_FLOATS:
14761 mips_disable_float_construction = 0;
14764 case OPTION_NO_CONSTRUCT_FLOATS:
14765 mips_disable_float_construction = 1;
14777 target_big_endian = 1;
14781 target_big_endian = 0;
14787 else if (arg[0] == '0')
14789 else if (arg[0] == '1')
14799 mips_debug = atoi (arg);
14803 file_mips_isa = ISA_MIPS1;
14807 file_mips_isa = ISA_MIPS2;
14811 file_mips_isa = ISA_MIPS3;
14815 file_mips_isa = ISA_MIPS4;
14819 file_mips_isa = ISA_MIPS5;
14822 case OPTION_MIPS32:
14823 file_mips_isa = ISA_MIPS32;
14826 case OPTION_MIPS32R2:
14827 file_mips_isa = ISA_MIPS32R2;
14830 case OPTION_MIPS64R2:
14831 file_mips_isa = ISA_MIPS64R2;
14834 case OPTION_MIPS64:
14835 file_mips_isa = ISA_MIPS64;
14839 mips_set_option_string (&mips_tune_string, arg);
14843 mips_set_option_string (&mips_arch_string, arg);
14847 mips_set_option_string (&mips_arch_string, "4650");
14848 mips_set_option_string (&mips_tune_string, "4650");
14851 case OPTION_NO_M4650:
14855 mips_set_option_string (&mips_arch_string, "4010");
14856 mips_set_option_string (&mips_tune_string, "4010");
14859 case OPTION_NO_M4010:
14863 mips_set_option_string (&mips_arch_string, "4100");
14864 mips_set_option_string (&mips_tune_string, "4100");
14867 case OPTION_NO_M4100:
14871 mips_set_option_string (&mips_arch_string, "3900");
14872 mips_set_option_string (&mips_tune_string, "3900");
14875 case OPTION_NO_M3900:
14879 mips_opts.ase_mdmx = 1;
14882 case OPTION_NO_MDMX:
14883 mips_opts.ase_mdmx = 0;
14887 mips_opts.ase_dsp = 1;
14888 mips_opts.ase_dspr2 = 0;
14891 case OPTION_NO_DSP:
14892 mips_opts.ase_dsp = 0;
14893 mips_opts.ase_dspr2 = 0;
14897 mips_opts.ase_dspr2 = 1;
14898 mips_opts.ase_dsp = 1;
14901 case OPTION_NO_DSPR2:
14902 mips_opts.ase_dspr2 = 0;
14903 mips_opts.ase_dsp = 0;
14907 mips_opts.ase_mt = 1;
14911 mips_opts.ase_mt = 0;
14915 mips_opts.ase_mcu = 1;
14918 case OPTION_NO_MCU:
14919 mips_opts.ase_mcu = 0;
14922 case OPTION_MICROMIPS:
14923 if (mips_opts.mips16 == 1)
14925 as_bad (_("-mmicromips cannot be used with -mips16"));
14928 mips_opts.micromips = 1;
14929 mips_no_prev_insn ();
14932 case OPTION_NO_MICROMIPS:
14933 mips_opts.micromips = 0;
14934 mips_no_prev_insn ();
14938 mips_opts.ase_virt = 1;
14941 case OPTION_NO_VIRT:
14942 mips_opts.ase_virt = 0;
14945 case OPTION_MIPS16:
14946 if (mips_opts.micromips == 1)
14948 as_bad (_("-mips16 cannot be used with -micromips"));
14951 mips_opts.mips16 = 1;
14952 mips_no_prev_insn ();
14955 case OPTION_NO_MIPS16:
14956 mips_opts.mips16 = 0;
14957 mips_no_prev_insn ();
14960 case OPTION_MIPS3D:
14961 mips_opts.ase_mips3d = 1;
14964 case OPTION_NO_MIPS3D:
14965 mips_opts.ase_mips3d = 0;
14968 case OPTION_SMARTMIPS:
14969 mips_opts.ase_smartmips = 1;
14972 case OPTION_NO_SMARTMIPS:
14973 mips_opts.ase_smartmips = 0;
14976 case OPTION_FIX_24K:
14980 case OPTION_NO_FIX_24K:
14984 case OPTION_FIX_LOONGSON2F_JUMP:
14985 mips_fix_loongson2f_jump = TRUE;
14988 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14989 mips_fix_loongson2f_jump = FALSE;
14992 case OPTION_FIX_LOONGSON2F_NOP:
14993 mips_fix_loongson2f_nop = TRUE;
14996 case OPTION_NO_FIX_LOONGSON2F_NOP:
14997 mips_fix_loongson2f_nop = FALSE;
15000 case OPTION_FIX_VR4120:
15001 mips_fix_vr4120 = 1;
15004 case OPTION_NO_FIX_VR4120:
15005 mips_fix_vr4120 = 0;
15008 case OPTION_FIX_VR4130:
15009 mips_fix_vr4130 = 1;
15012 case OPTION_NO_FIX_VR4130:
15013 mips_fix_vr4130 = 0;
15016 case OPTION_FIX_CN63XXP1:
15017 mips_fix_cn63xxp1 = TRUE;
15020 case OPTION_NO_FIX_CN63XXP1:
15021 mips_fix_cn63xxp1 = FALSE;
15024 case OPTION_RELAX_BRANCH:
15025 mips_relax_branch = 1;
15028 case OPTION_NO_RELAX_BRANCH:
15029 mips_relax_branch = 0;
15032 case OPTION_MSHARED:
15033 mips_in_shared = TRUE;
15036 case OPTION_MNO_SHARED:
15037 mips_in_shared = FALSE;
15040 case OPTION_MSYM32:
15041 mips_opts.sym32 = TRUE;
15044 case OPTION_MNO_SYM32:
15045 mips_opts.sym32 = FALSE;
15049 /* When generating ELF code, we permit -KPIC and -call_shared to
15050 select SVR4_PIC, and -non_shared to select no PIC. This is
15051 intended to be compatible with Irix 5. */
15052 case OPTION_CALL_SHARED:
15055 as_bad (_("-call_shared is supported only for ELF format"));
15058 mips_pic = SVR4_PIC;
15059 mips_abicalls = TRUE;
15062 case OPTION_CALL_NONPIC:
15065 as_bad (_("-call_nonpic is supported only for ELF format"));
15069 mips_abicalls = TRUE;
15072 case OPTION_NON_SHARED:
15075 as_bad (_("-non_shared is supported only for ELF format"));
15079 mips_abicalls = FALSE;
15082 /* The -xgot option tells the assembler to use 32 bit offsets
15083 when accessing the got in SVR4_PIC mode. It is for Irix
15088 #endif /* OBJ_ELF */
15091 g_switch_value = atoi (arg);
15095 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15099 mips_abi = O32_ABI;
15100 /* We silently ignore -32 for non-ELF targets. This greatly
15101 simplifies the construction of the MIPS GAS test cases. */
15108 as_bad (_("-n32 is supported for ELF format only"));
15111 mips_abi = N32_ABI;
15117 as_bad (_("-64 is supported for ELF format only"));
15120 mips_abi = N64_ABI;
15121 if (!support_64bit_objects())
15122 as_fatal (_("No compiled in support for 64 bit object file format"));
15124 #endif /* OBJ_ELF */
15127 file_mips_gp32 = 1;
15131 file_mips_gp32 = 0;
15135 file_mips_fp32 = 1;
15139 file_mips_fp32 = 0;
15142 case OPTION_SINGLE_FLOAT:
15143 file_mips_single_float = 1;
15146 case OPTION_DOUBLE_FLOAT:
15147 file_mips_single_float = 0;
15150 case OPTION_SOFT_FLOAT:
15151 file_mips_soft_float = 1;
15154 case OPTION_HARD_FLOAT:
15155 file_mips_soft_float = 0;
15162 as_bad (_("-mabi is supported for ELF format only"));
15165 if (strcmp (arg, "32") == 0)
15166 mips_abi = O32_ABI;
15167 else if (strcmp (arg, "o64") == 0)
15168 mips_abi = O64_ABI;
15169 else if (strcmp (arg, "n32") == 0)
15170 mips_abi = N32_ABI;
15171 else if (strcmp (arg, "64") == 0)
15173 mips_abi = N64_ABI;
15174 if (! support_64bit_objects())
15175 as_fatal (_("No compiled in support for 64 bit object file "
15178 else if (strcmp (arg, "eabi") == 0)
15179 mips_abi = EABI_ABI;
15182 as_fatal (_("invalid abi -mabi=%s"), arg);
15186 #endif /* OBJ_ELF */
15188 case OPTION_M7000_HILO_FIX:
15189 mips_7000_hilo_fix = TRUE;
15192 case OPTION_MNO_7000_HILO_FIX:
15193 mips_7000_hilo_fix = FALSE;
15197 case OPTION_MDEBUG:
15198 mips_flag_mdebug = TRUE;
15201 case OPTION_NO_MDEBUG:
15202 mips_flag_mdebug = FALSE;
15206 mips_flag_pdr = TRUE;
15209 case OPTION_NO_PDR:
15210 mips_flag_pdr = FALSE;
15213 case OPTION_MVXWORKS_PIC:
15214 mips_pic = VXWORKS_PIC;
15216 #endif /* OBJ_ELF */
15222 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15227 /* Set up globals to generate code for the ISA or processor
15228 described by INFO. */
15231 mips_set_architecture (const struct mips_cpu_info *info)
15235 file_mips_arch = info->cpu;
15236 mips_opts.arch = info->cpu;
15237 mips_opts.isa = info->isa;
15242 /* Likewise for tuning. */
15245 mips_set_tune (const struct mips_cpu_info *info)
15248 mips_tune = info->cpu;
15253 mips_after_parse_args (void)
15255 const struct mips_cpu_info *arch_info = 0;
15256 const struct mips_cpu_info *tune_info = 0;
15258 /* GP relative stuff not working for PE */
15259 if (strncmp (TARGET_OS, "pe", 2) == 0)
15261 if (g_switch_seen && g_switch_value != 0)
15262 as_bad (_("-G not supported in this configuration."));
15263 g_switch_value = 0;
15266 if (mips_abi == NO_ABI)
15267 mips_abi = MIPS_DEFAULT_ABI;
15269 /* The following code determines the architecture and register size.
15270 Similar code was added to GCC 3.3 (see override_options() in
15271 config/mips/mips.c). The GAS and GCC code should be kept in sync
15272 as much as possible. */
15274 if (mips_arch_string != 0)
15275 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15277 if (file_mips_isa != ISA_UNKNOWN)
15279 /* Handle -mipsN. At this point, file_mips_isa contains the
15280 ISA level specified by -mipsN, while arch_info->isa contains
15281 the -march selection (if any). */
15282 if (arch_info != 0)
15284 /* -march takes precedence over -mipsN, since it is more descriptive.
15285 There's no harm in specifying both as long as the ISA levels
15287 if (file_mips_isa != arch_info->isa)
15288 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15289 mips_cpu_info_from_isa (file_mips_isa)->name,
15290 mips_cpu_info_from_isa (arch_info->isa)->name);
15293 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15296 if (arch_info == 0)
15298 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15299 gas_assert (arch_info);
15302 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15303 as_bad (_("-march=%s is not compatible with the selected ABI"),
15306 mips_set_architecture (arch_info);
15308 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15309 if (mips_tune_string != 0)
15310 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15312 if (tune_info == 0)
15313 mips_set_tune (arch_info);
15315 mips_set_tune (tune_info);
15317 if (file_mips_gp32 >= 0)
15319 /* The user specified the size of the integer registers. Make sure
15320 it agrees with the ABI and ISA. */
15321 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15322 as_bad (_("-mgp64 used with a 32-bit processor"));
15323 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15324 as_bad (_("-mgp32 used with a 64-bit ABI"));
15325 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15326 as_bad (_("-mgp64 used with a 32-bit ABI"));
15330 /* Infer the integer register size from the ABI and processor.
15331 Restrict ourselves to 32-bit registers if that's all the
15332 processor has, or if the ABI cannot handle 64-bit registers. */
15333 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15334 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15337 switch (file_mips_fp32)
15341 /* No user specified float register size.
15342 ??? GAS treats single-float processors as though they had 64-bit
15343 float registers (although it complains when double-precision
15344 instructions are used). As things stand, saying they have 32-bit
15345 registers would lead to spurious "register must be even" messages.
15346 So here we assume float registers are never smaller than the
15348 if (file_mips_gp32 == 0)
15349 /* 64-bit integer registers implies 64-bit float registers. */
15350 file_mips_fp32 = 0;
15351 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15352 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15353 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15354 file_mips_fp32 = 0;
15356 /* 32-bit float registers. */
15357 file_mips_fp32 = 1;
15360 /* The user specified the size of the float registers. Check if it
15361 agrees with the ABI and ISA. */
15363 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15364 as_bad (_("-mfp64 used with a 32-bit fpu"));
15365 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15366 && !ISA_HAS_MXHC1 (mips_opts.isa))
15367 as_warn (_("-mfp64 used with a 32-bit ABI"));
15370 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15371 as_warn (_("-mfp32 used with a 64-bit ABI"));
15375 /* End of GCC-shared inference code. */
15377 /* This flag is set when we have a 64-bit capable CPU but use only
15378 32-bit wide registers. Note that EABI does not use it. */
15379 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15380 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15381 || mips_abi == O32_ABI))
15382 mips_32bitmode = 1;
15384 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15385 as_bad (_("trap exception not supported at ISA 1"));
15387 /* If the selected architecture includes support for ASEs, enable
15388 generation of code for them. */
15389 if (mips_opts.mips16 == -1)
15390 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15391 if (mips_opts.micromips == -1)
15392 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15393 if (mips_opts.ase_mips3d == -1)
15394 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15395 && file_mips_fp32 == 0) ? 1 : 0;
15396 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15397 as_bad (_("-mfp32 used with -mips3d"));
15399 if (mips_opts.ase_mdmx == -1)
15400 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15401 && file_mips_fp32 == 0) ? 1 : 0;
15402 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15403 as_bad (_("-mfp32 used with -mdmx"));
15405 if (mips_opts.ase_smartmips == -1)
15406 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15407 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15408 as_warn (_("%s ISA does not support SmartMIPS"),
15409 mips_cpu_info_from_isa (mips_opts.isa)->name);
15411 if (mips_opts.ase_dsp == -1)
15412 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15413 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15414 as_warn (_("%s ISA does not support DSP ASE"),
15415 mips_cpu_info_from_isa (mips_opts.isa)->name);
15417 if (mips_opts.ase_dspr2 == -1)
15419 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15420 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15422 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15423 as_warn (_("%s ISA does not support DSP R2 ASE"),
15424 mips_cpu_info_from_isa (mips_opts.isa)->name);
15426 if (mips_opts.ase_mt == -1)
15427 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15428 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15429 as_warn (_("%s ISA does not support MT ASE"),
15430 mips_cpu_info_from_isa (mips_opts.isa)->name);
15432 if (mips_opts.ase_mcu == -1)
15433 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15434 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15435 as_warn (_("%s ISA does not support MCU ASE"),
15436 mips_cpu_info_from_isa (mips_opts.isa)->name);
15438 if (mips_opts.ase_virt == -1)
15439 mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0;
15440 if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE)
15441 as_warn (_("%s ISA does not support Virtualization ASE"),
15442 mips_cpu_info_from_isa (mips_opts.isa)->name);
15444 file_mips_isa = mips_opts.isa;
15445 file_ase_mips3d = mips_opts.ase_mips3d;
15446 file_ase_mdmx = mips_opts.ase_mdmx;
15447 file_ase_smartmips = mips_opts.ase_smartmips;
15448 file_ase_dsp = mips_opts.ase_dsp;
15449 file_ase_dspr2 = mips_opts.ase_dspr2;
15450 file_ase_mt = mips_opts.ase_mt;
15451 file_ase_virt = mips_opts.ase_virt;
15452 mips_opts.gp32 = file_mips_gp32;
15453 mips_opts.fp32 = file_mips_fp32;
15454 mips_opts.soft_float = file_mips_soft_float;
15455 mips_opts.single_float = file_mips_single_float;
15457 if (mips_flag_mdebug < 0)
15459 #ifdef OBJ_MAYBE_ECOFF
15460 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15461 mips_flag_mdebug = 1;
15463 #endif /* OBJ_MAYBE_ECOFF */
15464 mips_flag_mdebug = 0;
15469 mips_init_after_args (void)
15471 /* initialize opcodes */
15472 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15473 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15477 md_pcrel_from (fixS *fixP)
15479 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15480 switch (fixP->fx_r_type)
15482 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15483 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15484 /* Return the address of the delay slot. */
15487 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15488 case BFD_RELOC_MICROMIPS_JMP:
15489 case BFD_RELOC_16_PCREL_S2:
15490 case BFD_RELOC_MIPS_JMP:
15491 /* Return the address of the delay slot. */
15494 case BFD_RELOC_32_PCREL:
15498 /* We have no relocation type for PC relative MIPS16 instructions. */
15499 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15500 as_bad_where (fixP->fx_file, fixP->fx_line,
15501 _("PC relative MIPS16 instruction references a different section"));
15506 /* This is called before the symbol table is processed. In order to
15507 work with gcc when using mips-tfile, we must keep all local labels.
15508 However, in other cases, we want to discard them. If we were
15509 called with -g, but we didn't see any debugging information, it may
15510 mean that gcc is smuggling debugging information through to
15511 mips-tfile, in which case we must generate all local labels. */
15514 mips_frob_file_before_adjust (void)
15516 #ifndef NO_ECOFF_DEBUGGING
15517 if (ECOFF_DEBUGGING
15519 && ! ecoff_debugging_seen)
15520 flag_keep_locals = 1;
15524 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15525 the corresponding LO16 reloc. This is called before md_apply_fix and
15526 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15527 relocation operators.
15529 For our purposes, a %lo() expression matches a %got() or %hi()
15532 (a) it refers to the same symbol; and
15533 (b) the offset applied in the %lo() expression is no lower than
15534 the offset applied in the %got() or %hi().
15536 (b) allows us to cope with code like:
15539 lh $4,%lo(foo+2)($4)
15541 ...which is legal on RELA targets, and has a well-defined behaviour
15542 if the user knows that adding 2 to "foo" will not induce a carry to
15545 When several %lo()s match a particular %got() or %hi(), we use the
15546 following rules to distinguish them:
15548 (1) %lo()s with smaller offsets are a better match than %lo()s with
15551 (2) %lo()s with no matching %got() or %hi() are better than those
15552 that already have a matching %got() or %hi().
15554 (3) later %lo()s are better than earlier %lo()s.
15556 These rules are applied in order.
15558 (1) means, among other things, that %lo()s with identical offsets are
15559 chosen if they exist.
15561 (2) means that we won't associate several high-part relocations with
15562 the same low-part relocation unless there's no alternative. Having
15563 several high parts for the same low part is a GNU extension; this rule
15564 allows careful users to avoid it.
15566 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15567 with the last high-part relocation being at the front of the list.
15568 It therefore makes sense to choose the last matching low-part
15569 relocation, all other things being equal. It's also easier
15570 to code that way. */
15573 mips_frob_file (void)
15575 struct mips_hi_fixup *l;
15576 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15578 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15580 segment_info_type *seginfo;
15581 bfd_boolean matched_lo_p;
15582 fixS **hi_pos, **lo_pos, **pos;
15584 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15586 /* If a GOT16 relocation turns out to be against a global symbol,
15587 there isn't supposed to be a matching LO. Ignore %gots against
15588 constants; we'll report an error for those later. */
15589 if (got16_reloc_p (l->fixp->fx_r_type)
15590 && !(l->fixp->fx_addsy
15591 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15594 /* Check quickly whether the next fixup happens to be a matching %lo. */
15595 if (fixup_has_matching_lo_p (l->fixp))
15598 seginfo = seg_info (l->seg);
15600 /* Set HI_POS to the position of this relocation in the chain.
15601 Set LO_POS to the position of the chosen low-part relocation.
15602 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15603 relocation that matches an immediately-preceding high-part
15607 matched_lo_p = FALSE;
15608 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15610 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15612 if (*pos == l->fixp)
15615 if ((*pos)->fx_r_type == looking_for_rtype
15616 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15617 && (*pos)->fx_offset >= l->fixp->fx_offset
15619 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15621 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15624 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15625 && fixup_has_matching_lo_p (*pos));
15628 /* If we found a match, remove the high-part relocation from its
15629 current position and insert it before the low-part relocation.
15630 Make the offsets match so that fixup_has_matching_lo_p()
15633 We don't warn about unmatched high-part relocations since some
15634 versions of gcc have been known to emit dead "lui ...%hi(...)"
15636 if (lo_pos != NULL)
15638 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15639 if (l->fixp->fx_next != *lo_pos)
15641 *hi_pos = l->fixp->fx_next;
15642 l->fixp->fx_next = *lo_pos;
15650 mips_force_relocation (fixS *fixp)
15652 if (generic_force_reloc (fixp))
15655 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15656 so that the linker relaxation can update targets. */
15657 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15658 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15659 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15665 /* Read the instruction associated with RELOC from BUF. */
15667 static unsigned int
15668 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15670 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15671 return read_compressed_insn (buf, 4);
15673 return read_insn (buf);
15676 /* Write instruction INSN to BUF, given that it has been relocated
15680 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15681 unsigned long insn)
15683 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15684 write_compressed_insn (buf, insn, 4);
15686 write_insn (buf, insn);
15689 /* Apply a fixup to the object file. */
15692 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15695 unsigned long insn;
15696 reloc_howto_type *howto;
15698 /* We ignore generic BFD relocations we don't know about. */
15699 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15703 gas_assert (fixP->fx_size == 2
15704 || fixP->fx_size == 4
15705 || fixP->fx_r_type == BFD_RELOC_16
15706 || fixP->fx_r_type == BFD_RELOC_64
15707 || fixP->fx_r_type == BFD_RELOC_CTOR
15708 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15709 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15710 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15711 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15712 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15714 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15716 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15717 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15718 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15719 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15720 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15722 /* Don't treat parts of a composite relocation as done. There are two
15725 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15726 should nevertheless be emitted if the first part is.
15728 (2) In normal usage, composite relocations are never assembly-time
15729 constants. The easiest way of dealing with the pathological
15730 exceptions is to generate a relocation against STN_UNDEF and
15731 leave everything up to the linker. */
15732 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15735 switch (fixP->fx_r_type)
15737 case BFD_RELOC_MIPS_TLS_GD:
15738 case BFD_RELOC_MIPS_TLS_LDM:
15739 case BFD_RELOC_MIPS_TLS_DTPREL32:
15740 case BFD_RELOC_MIPS_TLS_DTPREL64:
15741 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15742 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15743 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15744 case BFD_RELOC_MIPS_TLS_TPREL32:
15745 case BFD_RELOC_MIPS_TLS_TPREL64:
15746 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15747 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15748 case BFD_RELOC_MICROMIPS_TLS_GD:
15749 case BFD_RELOC_MICROMIPS_TLS_LDM:
15750 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15751 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15752 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15753 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15754 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15755 case BFD_RELOC_MIPS16_TLS_GD:
15756 case BFD_RELOC_MIPS16_TLS_LDM:
15757 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15758 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15759 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15760 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15761 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15762 if (!fixP->fx_addsy)
15764 as_bad_where (fixP->fx_file, fixP->fx_line,
15765 _("TLS relocation against a constant"));
15768 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15771 case BFD_RELOC_MIPS_JMP:
15772 case BFD_RELOC_MIPS_SHIFT5:
15773 case BFD_RELOC_MIPS_SHIFT6:
15774 case BFD_RELOC_MIPS_GOT_DISP:
15775 case BFD_RELOC_MIPS_GOT_PAGE:
15776 case BFD_RELOC_MIPS_GOT_OFST:
15777 case BFD_RELOC_MIPS_SUB:
15778 case BFD_RELOC_MIPS_INSERT_A:
15779 case BFD_RELOC_MIPS_INSERT_B:
15780 case BFD_RELOC_MIPS_DELETE:
15781 case BFD_RELOC_MIPS_HIGHEST:
15782 case BFD_RELOC_MIPS_HIGHER:
15783 case BFD_RELOC_MIPS_SCN_DISP:
15784 case BFD_RELOC_MIPS_REL16:
15785 case BFD_RELOC_MIPS_RELGOT:
15786 case BFD_RELOC_MIPS_JALR:
15787 case BFD_RELOC_HI16:
15788 case BFD_RELOC_HI16_S:
15789 case BFD_RELOC_LO16:
15790 case BFD_RELOC_GPREL16:
15791 case BFD_RELOC_MIPS_LITERAL:
15792 case BFD_RELOC_MIPS_CALL16:
15793 case BFD_RELOC_MIPS_GOT16:
15794 case BFD_RELOC_GPREL32:
15795 case BFD_RELOC_MIPS_GOT_HI16:
15796 case BFD_RELOC_MIPS_GOT_LO16:
15797 case BFD_RELOC_MIPS_CALL_HI16:
15798 case BFD_RELOC_MIPS_CALL_LO16:
15799 case BFD_RELOC_MIPS16_GPREL:
15800 case BFD_RELOC_MIPS16_GOT16:
15801 case BFD_RELOC_MIPS16_CALL16:
15802 case BFD_RELOC_MIPS16_HI16:
15803 case BFD_RELOC_MIPS16_HI16_S:
15804 case BFD_RELOC_MIPS16_LO16:
15805 case BFD_RELOC_MIPS16_JMP:
15806 case BFD_RELOC_MICROMIPS_JMP:
15807 case BFD_RELOC_MICROMIPS_GOT_DISP:
15808 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15809 case BFD_RELOC_MICROMIPS_GOT_OFST:
15810 case BFD_RELOC_MICROMIPS_SUB:
15811 case BFD_RELOC_MICROMIPS_HIGHEST:
15812 case BFD_RELOC_MICROMIPS_HIGHER:
15813 case BFD_RELOC_MICROMIPS_SCN_DISP:
15814 case BFD_RELOC_MICROMIPS_JALR:
15815 case BFD_RELOC_MICROMIPS_HI16:
15816 case BFD_RELOC_MICROMIPS_HI16_S:
15817 case BFD_RELOC_MICROMIPS_LO16:
15818 case BFD_RELOC_MICROMIPS_GPREL16:
15819 case BFD_RELOC_MICROMIPS_LITERAL:
15820 case BFD_RELOC_MICROMIPS_CALL16:
15821 case BFD_RELOC_MICROMIPS_GOT16:
15822 case BFD_RELOC_MICROMIPS_GOT_HI16:
15823 case BFD_RELOC_MICROMIPS_GOT_LO16:
15824 case BFD_RELOC_MICROMIPS_CALL_HI16:
15825 case BFD_RELOC_MICROMIPS_CALL_LO16:
15830 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15832 insn = read_reloc_insn (buf, fixP->fx_r_type);
15833 if (mips16_reloc_p (fixP->fx_r_type))
15834 insn |= mips16_immed_extend (value, 16);
15836 insn |= (value & 0xffff);
15837 write_reloc_insn (buf, fixP->fx_r_type, insn);
15840 as_bad_where (fixP->fx_file, fixP->fx_line,
15841 _("Unsupported constant in relocation"));
15846 /* This is handled like BFD_RELOC_32, but we output a sign
15847 extended value if we are only 32 bits. */
15850 if (8 <= sizeof (valueT))
15851 md_number_to_chars (buf, *valP, 8);
15856 if ((*valP & 0x80000000) != 0)
15860 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15861 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15866 case BFD_RELOC_RVA:
15868 case BFD_RELOC_32_PCREL:
15870 /* If we are deleting this reloc entry, we must fill in the
15871 value now. This can happen if we have a .word which is not
15872 resolved when it appears but is later defined. */
15874 md_number_to_chars (buf, *valP, fixP->fx_size);
15877 case BFD_RELOC_16_PCREL_S2:
15878 if ((*valP & 0x3) != 0)
15879 as_bad_where (fixP->fx_file, fixP->fx_line,
15880 _("Branch to misaligned address (%lx)"), (long) *valP);
15882 /* We need to save the bits in the instruction since fixup_segment()
15883 might be deleting the relocation entry (i.e., a branch within
15884 the current segment). */
15885 if (! fixP->fx_done)
15888 /* Update old instruction data. */
15889 insn = read_insn (buf);
15891 if (*valP + 0x20000 <= 0x3ffff)
15893 insn |= (*valP >> 2) & 0xffff;
15894 write_insn (buf, insn);
15896 else if (mips_pic == NO_PIC
15898 && fixP->fx_frag->fr_address >= text_section->vma
15899 && (fixP->fx_frag->fr_address
15900 < text_section->vma + bfd_get_section_size (text_section))
15901 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15902 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15903 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15905 /* The branch offset is too large. If this is an
15906 unconditional branch, and we are not generating PIC code,
15907 we can convert it to an absolute jump instruction. */
15908 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15909 insn = 0x0c000000; /* jal */
15911 insn = 0x08000000; /* j */
15912 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15914 fixP->fx_addsy = section_symbol (text_section);
15915 *valP += md_pcrel_from (fixP);
15916 write_insn (buf, insn);
15920 /* If we got here, we have branch-relaxation disabled,
15921 and there's nothing we can do to fix this instruction
15922 without turning it into a longer sequence. */
15923 as_bad_where (fixP->fx_file, fixP->fx_line,
15924 _("Branch out of range"));
15928 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15929 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15930 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15931 /* We adjust the offset back to even. */
15932 if ((*valP & 0x1) != 0)
15935 if (! fixP->fx_done)
15938 /* Should never visit here, because we keep the relocation. */
15942 case BFD_RELOC_VTABLE_INHERIT:
15945 && !S_IS_DEFINED (fixP->fx_addsy)
15946 && !S_IS_WEAK (fixP->fx_addsy))
15947 S_SET_WEAK (fixP->fx_addsy);
15950 case BFD_RELOC_VTABLE_ENTRY:
15958 /* Remember value for tc_gen_reloc. */
15959 fixP->fx_addnumber = *valP;
15969 name = input_line_pointer;
15970 c = get_symbol_end ();
15971 p = (symbolS *) symbol_find_or_make (name);
15972 *input_line_pointer = c;
15976 /* Align the current frag to a given power of two. If a particular
15977 fill byte should be used, FILL points to an integer that contains
15978 that byte, otherwise FILL is null.
15980 This function used to have the comment:
15982 The MIPS assembler also automatically adjusts any preceding label.
15984 The implementation therefore applied the adjustment to a maximum of
15985 one label. However, other label adjustments are applied to batches
15986 of labels, and adjusting just one caused problems when new labels
15987 were added for the sake of debugging or unwind information.
15988 We therefore adjust all preceding labels (given as LABELS) instead. */
15991 mips_align (int to, int *fill, struct insn_label_list *labels)
15993 mips_emit_delays ();
15994 mips_record_compressed_mode ();
15995 if (fill == NULL && subseg_text_p (now_seg))
15996 frag_align_code (to, 0);
15998 frag_align (to, fill ? *fill : 0, 0);
15999 record_alignment (now_seg, to);
16000 mips_move_labels (labels, FALSE);
16003 /* Align to a given power of two. .align 0 turns off the automatic
16004 alignment used by the data creating pseudo-ops. */
16007 s_align (int x ATTRIBUTE_UNUSED)
16009 int temp, fill_value, *fill_ptr;
16010 long max_alignment = 28;
16012 /* o Note that the assembler pulls down any immediately preceding label
16013 to the aligned address.
16014 o It's not documented but auto alignment is reinstated by
16015 a .align pseudo instruction.
16016 o Note also that after auto alignment is turned off the mips assembler
16017 issues an error on attempt to assemble an improperly aligned data item.
16020 temp = get_absolute_expression ();
16021 if (temp > max_alignment)
16022 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16025 as_warn (_("Alignment negative: 0 assumed."));
16028 if (*input_line_pointer == ',')
16030 ++input_line_pointer;
16031 fill_value = get_absolute_expression ();
16032 fill_ptr = &fill_value;
16038 segment_info_type *si = seg_info (now_seg);
16039 struct insn_label_list *l = si->label_list;
16040 /* Auto alignment should be switched on by next section change. */
16042 mips_align (temp, fill_ptr, l);
16049 demand_empty_rest_of_line ();
16053 s_change_sec (int sec)
16058 /* The ELF backend needs to know that we are changing sections, so
16059 that .previous works correctly. We could do something like check
16060 for an obj_section_change_hook macro, but that might be confusing
16061 as it would not be appropriate to use it in the section changing
16062 functions in read.c, since obj-elf.c intercepts those. FIXME:
16063 This should be cleaner, somehow. */
16065 obj_elf_section_change_hook ();
16068 mips_emit_delays ();
16079 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16080 demand_empty_rest_of_line ();
16084 seg = subseg_new (RDATA_SECTION_NAME,
16085 (subsegT) get_absolute_expression ());
16088 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16089 | SEC_READONLY | SEC_RELOC
16091 if (strncmp (TARGET_OS, "elf", 3) != 0)
16092 record_alignment (seg, 4);
16094 demand_empty_rest_of_line ();
16098 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16101 bfd_set_section_flags (stdoutput, seg,
16102 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16103 if (strncmp (TARGET_OS, "elf", 3) != 0)
16104 record_alignment (seg, 4);
16106 demand_empty_rest_of_line ();
16110 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16113 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16114 if (strncmp (TARGET_OS, "elf", 3) != 0)
16115 record_alignment (seg, 4);
16117 demand_empty_rest_of_line ();
16125 s_change_section (int ignore ATTRIBUTE_UNUSED)
16128 char *section_name;
16133 int section_entry_size;
16134 int section_alignment;
16139 section_name = input_line_pointer;
16140 c = get_symbol_end ();
16142 next_c = *(input_line_pointer + 1);
16144 /* Do we have .section Name<,"flags">? */
16145 if (c != ',' || (c == ',' && next_c == '"'))
16147 /* just after name is now '\0'. */
16148 *input_line_pointer = c;
16149 input_line_pointer = section_name;
16150 obj_elf_section (ignore);
16153 input_line_pointer++;
16155 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16157 section_type = get_absolute_expression ();
16160 if (*input_line_pointer++ == ',')
16161 section_flag = get_absolute_expression ();
16164 if (*input_line_pointer++ == ',')
16165 section_entry_size = get_absolute_expression ();
16167 section_entry_size = 0;
16168 if (*input_line_pointer++ == ',')
16169 section_alignment = get_absolute_expression ();
16171 section_alignment = 0;
16172 /* FIXME: really ignore? */
16173 (void) section_alignment;
16175 section_name = xstrdup (section_name);
16177 /* When using the generic form of .section (as implemented by obj-elf.c),
16178 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16179 traditionally had to fall back on the more common @progbits instead.
16181 There's nothing really harmful in this, since bfd will correct
16182 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16183 means that, for backwards compatibility, the special_section entries
16184 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16186 Even so, we shouldn't force users of the MIPS .section syntax to
16187 incorrectly label the sections as SHT_PROGBITS. The best compromise
16188 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16189 generic type-checking code. */
16190 if (section_type == SHT_MIPS_DWARF)
16191 section_type = SHT_PROGBITS;
16193 obj_elf_change_section (section_name, section_type, section_flag,
16194 section_entry_size, 0, 0, 0);
16196 if (now_seg->name != section_name)
16197 free (section_name);
16198 #endif /* OBJ_ELF */
16202 mips_enable_auto_align (void)
16208 s_cons (int log_size)
16210 segment_info_type *si = seg_info (now_seg);
16211 struct insn_label_list *l = si->label_list;
16213 mips_emit_delays ();
16214 if (log_size > 0 && auto_align)
16215 mips_align (log_size, 0, l);
16216 cons (1 << log_size);
16217 mips_clear_insn_labels ();
16221 s_float_cons (int type)
16223 segment_info_type *si = seg_info (now_seg);
16224 struct insn_label_list *l = si->label_list;
16226 mips_emit_delays ();
16231 mips_align (3, 0, l);
16233 mips_align (2, 0, l);
16237 mips_clear_insn_labels ();
16240 /* Handle .globl. We need to override it because on Irix 5 you are
16243 where foo is an undefined symbol, to mean that foo should be
16244 considered to be the address of a function. */
16247 s_mips_globl (int x ATTRIBUTE_UNUSED)
16256 name = input_line_pointer;
16257 c = get_symbol_end ();
16258 symbolP = symbol_find_or_make (name);
16259 S_SET_EXTERNAL (symbolP);
16261 *input_line_pointer = c;
16262 SKIP_WHITESPACE ();
16264 /* On Irix 5, every global symbol that is not explicitly labelled as
16265 being a function is apparently labelled as being an object. */
16268 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16269 && (*input_line_pointer != ','))
16274 secname = input_line_pointer;
16275 c = get_symbol_end ();
16276 sec = bfd_get_section_by_name (stdoutput, secname);
16278 as_bad (_("%s: no such section"), secname);
16279 *input_line_pointer = c;
16281 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16282 flag = BSF_FUNCTION;
16285 symbol_get_bfdsym (symbolP)->flags |= flag;
16287 c = *input_line_pointer;
16290 input_line_pointer++;
16291 SKIP_WHITESPACE ();
16292 if (is_end_of_line[(unsigned char) *input_line_pointer])
16298 demand_empty_rest_of_line ();
16302 s_option (int x ATTRIBUTE_UNUSED)
16307 opt = input_line_pointer;
16308 c = get_symbol_end ();
16312 /* FIXME: What does this mean? */
16314 else if (strncmp (opt, "pic", 3) == 0)
16318 i = atoi (opt + 3);
16323 mips_pic = SVR4_PIC;
16324 mips_abicalls = TRUE;
16327 as_bad (_(".option pic%d not supported"), i);
16329 if (mips_pic == SVR4_PIC)
16331 if (g_switch_seen && g_switch_value != 0)
16332 as_warn (_("-G may not be used with SVR4 PIC code"));
16333 g_switch_value = 0;
16334 bfd_set_gp_size (stdoutput, 0);
16338 as_warn (_("Unrecognized option \"%s\""), opt);
16340 *input_line_pointer = c;
16341 demand_empty_rest_of_line ();
16344 /* This structure is used to hold a stack of .set values. */
16346 struct mips_option_stack
16348 struct mips_option_stack *next;
16349 struct mips_set_options options;
16352 static struct mips_option_stack *mips_opts_stack;
16354 /* Handle the .set pseudo-op. */
16357 s_mipsset (int x ATTRIBUTE_UNUSED)
16359 char *name = input_line_pointer, ch;
16361 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16362 ++input_line_pointer;
16363 ch = *input_line_pointer;
16364 *input_line_pointer = '\0';
16366 if (strcmp (name, "reorder") == 0)
16368 if (mips_opts.noreorder)
16371 else if (strcmp (name, "noreorder") == 0)
16373 if (!mips_opts.noreorder)
16374 start_noreorder ();
16376 else if (strncmp (name, "at=", 3) == 0)
16378 char *s = name + 3;
16380 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16381 as_bad (_("Unrecognized register name `%s'"), s);
16383 else if (strcmp (name, "at") == 0)
16385 mips_opts.at = ATREG;
16387 else if (strcmp (name, "noat") == 0)
16389 mips_opts.at = ZERO;
16391 else if (strcmp (name, "macro") == 0)
16393 mips_opts.warn_about_macros = 0;
16395 else if (strcmp (name, "nomacro") == 0)
16397 if (mips_opts.noreorder == 0)
16398 as_bad (_("`noreorder' must be set before `nomacro'"));
16399 mips_opts.warn_about_macros = 1;
16401 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16403 mips_opts.nomove = 0;
16405 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16407 mips_opts.nomove = 1;
16409 else if (strcmp (name, "bopt") == 0)
16411 mips_opts.nobopt = 0;
16413 else if (strcmp (name, "nobopt") == 0)
16415 mips_opts.nobopt = 1;
16417 else if (strcmp (name, "gp=default") == 0)
16418 mips_opts.gp32 = file_mips_gp32;
16419 else if (strcmp (name, "gp=32") == 0)
16420 mips_opts.gp32 = 1;
16421 else if (strcmp (name, "gp=64") == 0)
16423 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16424 as_warn (_("%s isa does not support 64-bit registers"),
16425 mips_cpu_info_from_isa (mips_opts.isa)->name);
16426 mips_opts.gp32 = 0;
16428 else if (strcmp (name, "fp=default") == 0)
16429 mips_opts.fp32 = file_mips_fp32;
16430 else if (strcmp (name, "fp=32") == 0)
16431 mips_opts.fp32 = 1;
16432 else if (strcmp (name, "fp=64") == 0)
16434 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16435 as_warn (_("%s isa does not support 64-bit floating point registers"),
16436 mips_cpu_info_from_isa (mips_opts.isa)->name);
16437 mips_opts.fp32 = 0;
16439 else if (strcmp (name, "softfloat") == 0)
16440 mips_opts.soft_float = 1;
16441 else if (strcmp (name, "hardfloat") == 0)
16442 mips_opts.soft_float = 0;
16443 else if (strcmp (name, "singlefloat") == 0)
16444 mips_opts.single_float = 1;
16445 else if (strcmp (name, "doublefloat") == 0)
16446 mips_opts.single_float = 0;
16447 else if (strcmp (name, "mips16") == 0
16448 || strcmp (name, "MIPS-16") == 0)
16450 if (mips_opts.micromips == 1)
16451 as_fatal (_("`mips16' cannot be used with `micromips'"));
16452 mips_opts.mips16 = 1;
16454 else if (strcmp (name, "nomips16") == 0
16455 || strcmp (name, "noMIPS-16") == 0)
16456 mips_opts.mips16 = 0;
16457 else if (strcmp (name, "micromips") == 0)
16459 if (mips_opts.mips16 == 1)
16460 as_fatal (_("`micromips' cannot be used with `mips16'"));
16461 mips_opts.micromips = 1;
16463 else if (strcmp (name, "nomicromips") == 0)
16464 mips_opts.micromips = 0;
16465 else if (strcmp (name, "smartmips") == 0)
16467 if (!ISA_SUPPORTS_SMARTMIPS)
16468 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16469 mips_cpu_info_from_isa (mips_opts.isa)->name);
16470 mips_opts.ase_smartmips = 1;
16472 else if (strcmp (name, "nosmartmips") == 0)
16473 mips_opts.ase_smartmips = 0;
16474 else if (strcmp (name, "mips3d") == 0)
16475 mips_opts.ase_mips3d = 1;
16476 else if (strcmp (name, "nomips3d") == 0)
16477 mips_opts.ase_mips3d = 0;
16478 else if (strcmp (name, "mdmx") == 0)
16479 mips_opts.ase_mdmx = 1;
16480 else if (strcmp (name, "nomdmx") == 0)
16481 mips_opts.ase_mdmx = 0;
16482 else if (strcmp (name, "dsp") == 0)
16484 if (!ISA_SUPPORTS_DSP_ASE)
16485 as_warn (_("%s ISA does not support DSP ASE"),
16486 mips_cpu_info_from_isa (mips_opts.isa)->name);
16487 mips_opts.ase_dsp = 1;
16488 mips_opts.ase_dspr2 = 0;
16490 else if (strcmp (name, "nodsp") == 0)
16492 mips_opts.ase_dsp = 0;
16493 mips_opts.ase_dspr2 = 0;
16495 else if (strcmp (name, "dspr2") == 0)
16497 if (!ISA_SUPPORTS_DSPR2_ASE)
16498 as_warn (_("%s ISA does not support DSP R2 ASE"),
16499 mips_cpu_info_from_isa (mips_opts.isa)->name);
16500 mips_opts.ase_dspr2 = 1;
16501 mips_opts.ase_dsp = 1;
16503 else if (strcmp (name, "nodspr2") == 0)
16505 mips_opts.ase_dspr2 = 0;
16506 mips_opts.ase_dsp = 0;
16508 else if (strcmp (name, "mt") == 0)
16510 if (!ISA_SUPPORTS_MT_ASE)
16511 as_warn (_("%s ISA does not support MT ASE"),
16512 mips_cpu_info_from_isa (mips_opts.isa)->name);
16513 mips_opts.ase_mt = 1;
16515 else if (strcmp (name, "nomt") == 0)
16516 mips_opts.ase_mt = 0;
16517 else if (strcmp (name, "mcu") == 0)
16518 mips_opts.ase_mcu = 1;
16519 else if (strcmp (name, "nomcu") == 0)
16520 mips_opts.ase_mcu = 0;
16521 else if (strcmp (name, "virt") == 0)
16523 if (!ISA_SUPPORTS_VIRT_ASE)
16524 as_warn (_("%s ISA does not support Virtualization ASE"),
16525 mips_cpu_info_from_isa (mips_opts.isa)->name);
16526 mips_opts.ase_virt = 1;
16528 else if (strcmp (name, "novirt") == 0)
16529 mips_opts.ase_virt = 0;
16530 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16534 /* Permit the user to change the ISA and architecture on the fly.
16535 Needless to say, misuse can cause serious problems. */
16536 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16539 mips_opts.isa = file_mips_isa;
16540 mips_opts.arch = file_mips_arch;
16542 else if (strncmp (name, "arch=", 5) == 0)
16544 const struct mips_cpu_info *p;
16546 p = mips_parse_cpu("internal use", name + 5);
16548 as_bad (_("unknown architecture %s"), name + 5);
16551 mips_opts.arch = p->cpu;
16552 mips_opts.isa = p->isa;
16555 else if (strncmp (name, "mips", 4) == 0)
16557 const struct mips_cpu_info *p;
16559 p = mips_parse_cpu("internal use", name);
16561 as_bad (_("unknown ISA level %s"), name + 4);
16564 mips_opts.arch = p->cpu;
16565 mips_opts.isa = p->isa;
16569 as_bad (_("unknown ISA or architecture %s"), name);
16571 switch (mips_opts.isa)
16579 mips_opts.gp32 = 1;
16580 mips_opts.fp32 = 1;
16587 mips_opts.gp32 = 0;
16588 if (mips_opts.arch == CPU_R5900)
16590 mips_opts.fp32 = 1;
16594 mips_opts.fp32 = 0;
16598 as_bad (_("unknown ISA level %s"), name + 4);
16603 mips_opts.gp32 = file_mips_gp32;
16604 mips_opts.fp32 = file_mips_fp32;
16607 else if (strcmp (name, "autoextend") == 0)
16608 mips_opts.noautoextend = 0;
16609 else if (strcmp (name, "noautoextend") == 0)
16610 mips_opts.noautoextend = 1;
16611 else if (strcmp (name, "push") == 0)
16613 struct mips_option_stack *s;
16615 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16616 s->next = mips_opts_stack;
16617 s->options = mips_opts;
16618 mips_opts_stack = s;
16620 else if (strcmp (name, "pop") == 0)
16622 struct mips_option_stack *s;
16624 s = mips_opts_stack;
16626 as_bad (_(".set pop with no .set push"));
16629 /* If we're changing the reorder mode we need to handle
16630 delay slots correctly. */
16631 if (s->options.noreorder && ! mips_opts.noreorder)
16632 start_noreorder ();
16633 else if (! s->options.noreorder && mips_opts.noreorder)
16636 mips_opts = s->options;
16637 mips_opts_stack = s->next;
16641 else if (strcmp (name, "sym32") == 0)
16642 mips_opts.sym32 = TRUE;
16643 else if (strcmp (name, "nosym32") == 0)
16644 mips_opts.sym32 = FALSE;
16645 else if (strchr (name, ','))
16647 /* Generic ".set" directive; use the generic handler. */
16648 *input_line_pointer = ch;
16649 input_line_pointer = name;
16655 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16657 *input_line_pointer = ch;
16658 demand_empty_rest_of_line ();
16661 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16662 .option pic2. It means to generate SVR4 PIC calls. */
16665 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16667 mips_pic = SVR4_PIC;
16668 mips_abicalls = TRUE;
16670 if (g_switch_seen && g_switch_value != 0)
16671 as_warn (_("-G may not be used with SVR4 PIC code"));
16672 g_switch_value = 0;
16674 bfd_set_gp_size (stdoutput, 0);
16675 demand_empty_rest_of_line ();
16678 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16679 PIC code. It sets the $gp register for the function based on the
16680 function address, which is in the register named in the argument.
16681 This uses a relocation against _gp_disp, which is handled specially
16682 by the linker. The result is:
16683 lui $gp,%hi(_gp_disp)
16684 addiu $gp,$gp,%lo(_gp_disp)
16685 addu $gp,$gp,.cpload argument
16686 The .cpload argument is normally $25 == $t9.
16688 The -mno-shared option changes this to:
16689 lui $gp,%hi(__gnu_local_gp)
16690 addiu $gp,$gp,%lo(__gnu_local_gp)
16691 and the argument is ignored. This saves an instruction, but the
16692 resulting code is not position independent; it uses an absolute
16693 address for __gnu_local_gp. Thus code assembled with -mno-shared
16694 can go into an ordinary executable, but not into a shared library. */
16697 s_cpload (int ignore ATTRIBUTE_UNUSED)
16703 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16704 .cpload is ignored. */
16705 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16711 if (mips_opts.mips16)
16713 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16714 ignore_rest_of_line ();
16718 /* .cpload should be in a .set noreorder section. */
16719 if (mips_opts.noreorder == 0)
16720 as_warn (_(".cpload not in noreorder section"));
16722 reg = tc_get_register (0);
16724 /* If we need to produce a 64-bit address, we are better off using
16725 the default instruction sequence. */
16726 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16728 ex.X_op = O_symbol;
16729 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16731 ex.X_op_symbol = NULL;
16732 ex.X_add_number = 0;
16734 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16735 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16737 mips_mark_labels ();
16738 mips_assembling_insn = TRUE;
16741 macro_build_lui (&ex, mips_gp_register);
16742 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16743 mips_gp_register, BFD_RELOC_LO16);
16745 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16746 mips_gp_register, reg);
16749 mips_assembling_insn = FALSE;
16750 demand_empty_rest_of_line ();
16753 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16754 .cpsetup $reg1, offset|$reg2, label
16756 If offset is given, this results in:
16757 sd $gp, offset($sp)
16758 lui $gp, %hi(%neg(%gp_rel(label)))
16759 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16760 daddu $gp, $gp, $reg1
16762 If $reg2 is given, this results in:
16763 daddu $reg2, $gp, $0
16764 lui $gp, %hi(%neg(%gp_rel(label)))
16765 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16766 daddu $gp, $gp, $reg1
16767 $reg1 is normally $25 == $t9.
16769 The -mno-shared option replaces the last three instructions with
16771 addiu $gp,$gp,%lo(_gp) */
16774 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16776 expressionS ex_off;
16777 expressionS ex_sym;
16780 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16781 We also need NewABI support. */
16782 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16788 if (mips_opts.mips16)
16790 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16791 ignore_rest_of_line ();
16795 reg1 = tc_get_register (0);
16796 SKIP_WHITESPACE ();
16797 if (*input_line_pointer != ',')
16799 as_bad (_("missing argument separator ',' for .cpsetup"));
16803 ++input_line_pointer;
16804 SKIP_WHITESPACE ();
16805 if (*input_line_pointer == '$')
16807 mips_cpreturn_register = tc_get_register (0);
16808 mips_cpreturn_offset = -1;
16812 mips_cpreturn_offset = get_absolute_expression ();
16813 mips_cpreturn_register = -1;
16815 SKIP_WHITESPACE ();
16816 if (*input_line_pointer != ',')
16818 as_bad (_("missing argument separator ',' for .cpsetup"));
16822 ++input_line_pointer;
16823 SKIP_WHITESPACE ();
16824 expression (&ex_sym);
16826 mips_mark_labels ();
16827 mips_assembling_insn = TRUE;
16830 if (mips_cpreturn_register == -1)
16832 ex_off.X_op = O_constant;
16833 ex_off.X_add_symbol = NULL;
16834 ex_off.X_op_symbol = NULL;
16835 ex_off.X_add_number = mips_cpreturn_offset;
16837 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16838 BFD_RELOC_LO16, SP);
16841 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16842 mips_gp_register, 0);
16844 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16846 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16847 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16850 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16851 mips_gp_register, -1, BFD_RELOC_GPREL16,
16852 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16854 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16855 mips_gp_register, reg1);
16861 ex.X_op = O_symbol;
16862 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16863 ex.X_op_symbol = NULL;
16864 ex.X_add_number = 0;
16866 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16867 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16869 macro_build_lui (&ex, mips_gp_register);
16870 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16871 mips_gp_register, BFD_RELOC_LO16);
16876 mips_assembling_insn = FALSE;
16877 demand_empty_rest_of_line ();
16881 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16883 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16884 .cplocal is ignored. */
16885 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16891 if (mips_opts.mips16)
16893 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16894 ignore_rest_of_line ();
16898 mips_gp_register = tc_get_register (0);
16899 demand_empty_rest_of_line ();
16902 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16903 offset from $sp. The offset is remembered, and after making a PIC
16904 call $gp is restored from that location. */
16907 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16911 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16912 .cprestore is ignored. */
16913 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16919 if (mips_opts.mips16)
16921 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16922 ignore_rest_of_line ();
16926 mips_cprestore_offset = get_absolute_expression ();
16927 mips_cprestore_valid = 1;
16929 ex.X_op = O_constant;
16930 ex.X_add_symbol = NULL;
16931 ex.X_op_symbol = NULL;
16932 ex.X_add_number = mips_cprestore_offset;
16934 mips_mark_labels ();
16935 mips_assembling_insn = TRUE;
16938 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16939 SP, HAVE_64BIT_ADDRESSES);
16942 mips_assembling_insn = FALSE;
16943 demand_empty_rest_of_line ();
16946 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16947 was given in the preceding .cpsetup, it results in:
16948 ld $gp, offset($sp)
16950 If a register $reg2 was given there, it results in:
16951 daddu $gp, $reg2, $0 */
16954 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16958 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16959 We also need NewABI support. */
16960 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16966 if (mips_opts.mips16)
16968 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16969 ignore_rest_of_line ();
16973 mips_mark_labels ();
16974 mips_assembling_insn = TRUE;
16977 if (mips_cpreturn_register == -1)
16979 ex.X_op = O_constant;
16980 ex.X_add_symbol = NULL;
16981 ex.X_op_symbol = NULL;
16982 ex.X_add_number = mips_cpreturn_offset;
16984 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16987 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16988 mips_cpreturn_register, 0);
16991 mips_assembling_insn = FALSE;
16992 demand_empty_rest_of_line ();
16995 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16996 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16997 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16998 debug information or MIPS16 TLS. */
17001 s_tls_rel_directive (const size_t bytes, const char *dirstr,
17002 bfd_reloc_code_real_type rtype)
17009 if (ex.X_op != O_symbol)
17011 as_bad (_("Unsupported use of %s"), dirstr);
17012 ignore_rest_of_line ();
17015 p = frag_more (bytes);
17016 md_number_to_chars (p, 0, bytes);
17017 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
17018 demand_empty_rest_of_line ();
17019 mips_clear_insn_labels ();
17022 /* Handle .dtprelword. */
17025 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
17027 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
17030 /* Handle .dtpreldword. */
17033 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
17035 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
17038 /* Handle .tprelword. */
17041 s_tprelword (int ignore ATTRIBUTE_UNUSED)
17043 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
17046 /* Handle .tpreldword. */
17049 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17051 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17054 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17055 code. It sets the offset to use in gp_rel relocations. */
17058 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17060 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17061 We also need NewABI support. */
17062 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17068 mips_gprel_offset = get_absolute_expression ();
17070 demand_empty_rest_of_line ();
17073 /* Handle the .gpword pseudo-op. This is used when generating PIC
17074 code. It generates a 32 bit GP relative reloc. */
17077 s_gpword (int ignore ATTRIBUTE_UNUSED)
17079 segment_info_type *si;
17080 struct insn_label_list *l;
17084 /* When not generating PIC code, this is treated as .word. */
17085 if (mips_pic != SVR4_PIC)
17091 si = seg_info (now_seg);
17092 l = si->label_list;
17093 mips_emit_delays ();
17095 mips_align (2, 0, l);
17098 mips_clear_insn_labels ();
17100 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17102 as_bad (_("Unsupported use of .gpword"));
17103 ignore_rest_of_line ();
17107 md_number_to_chars (p, 0, 4);
17108 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17109 BFD_RELOC_GPREL32);
17111 demand_empty_rest_of_line ();
17115 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17117 segment_info_type *si;
17118 struct insn_label_list *l;
17122 /* When not generating PIC code, this is treated as .dword. */
17123 if (mips_pic != SVR4_PIC)
17129 si = seg_info (now_seg);
17130 l = si->label_list;
17131 mips_emit_delays ();
17133 mips_align (3, 0, l);
17136 mips_clear_insn_labels ();
17138 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17140 as_bad (_("Unsupported use of .gpdword"));
17141 ignore_rest_of_line ();
17145 md_number_to_chars (p, 0, 8);
17146 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17147 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17149 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17150 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17151 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17153 demand_empty_rest_of_line ();
17156 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17157 tables in SVR4 PIC code. */
17160 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17164 /* This is ignored when not generating SVR4 PIC code. */
17165 if (mips_pic != SVR4_PIC)
17171 mips_mark_labels ();
17172 mips_assembling_insn = TRUE;
17174 /* Add $gp to the register named as an argument. */
17176 reg = tc_get_register (0);
17177 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17180 mips_assembling_insn = FALSE;
17181 demand_empty_rest_of_line ();
17184 /* Handle the .insn pseudo-op. This marks instruction labels in
17185 mips16/micromips mode. This permits the linker to handle them specially,
17186 such as generating jalx instructions when needed. We also make
17187 them odd for the duration of the assembly, in order to generate the
17188 right sort of code. We will make them even in the adjust_symtab
17189 routine, while leaving them marked. This is convenient for the
17190 debugger and the disassembler. The linker knows to make them odd
17194 s_insn (int ignore ATTRIBUTE_UNUSED)
17196 mips_mark_labels ();
17198 demand_empty_rest_of_line ();
17201 /* Handle a .stab[snd] directive. Ideally these directives would be
17202 implemented in a transparent way, so that removing them would not
17203 have any effect on the generated instructions. However, s_stab
17204 internally changes the section, so in practice we need to decide
17205 now whether the preceding label marks compressed code. We do not
17206 support changing the compression mode of a label after a .stab*
17207 directive, such as in:
17213 so the current mode wins. */
17216 s_mips_stab (int type)
17218 mips_mark_labels ();
17222 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17225 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17232 name = input_line_pointer;
17233 c = get_symbol_end ();
17234 symbolP = symbol_find_or_make (name);
17235 S_SET_WEAK (symbolP);
17236 *input_line_pointer = c;
17238 SKIP_WHITESPACE ();
17240 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17242 if (S_IS_DEFINED (symbolP))
17244 as_bad (_("ignoring attempt to redefine symbol %s"),
17245 S_GET_NAME (symbolP));
17246 ignore_rest_of_line ();
17250 if (*input_line_pointer == ',')
17252 ++input_line_pointer;
17253 SKIP_WHITESPACE ();
17257 if (exp.X_op != O_symbol)
17259 as_bad (_("bad .weakext directive"));
17260 ignore_rest_of_line ();
17263 symbol_set_value_expression (symbolP, &exp);
17266 demand_empty_rest_of_line ();
17269 /* Parse a register string into a number. Called from the ECOFF code
17270 to parse .frame. The argument is non-zero if this is the frame
17271 register, so that we can record it in mips_frame_reg. */
17274 tc_get_register (int frame)
17278 SKIP_WHITESPACE ();
17279 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17283 mips_frame_reg = reg != 0 ? reg : SP;
17284 mips_frame_reg_valid = 1;
17285 mips_cprestore_valid = 0;
17291 md_section_align (asection *seg, valueT addr)
17293 int align = bfd_get_section_alignment (stdoutput, seg);
17297 /* We don't need to align ELF sections to the full alignment.
17298 However, Irix 5 may prefer that we align them at least to a 16
17299 byte boundary. We don't bother to align the sections if we
17300 are targeted for an embedded system. */
17301 if (strncmp (TARGET_OS, "elf", 3) == 0)
17307 return ((addr + (1 << align) - 1) & (-1 << align));
17310 /* Utility routine, called from above as well. If called while the
17311 input file is still being read, it's only an approximation. (For
17312 example, a symbol may later become defined which appeared to be
17313 undefined earlier.) */
17316 nopic_need_relax (symbolS *sym, int before_relaxing)
17321 if (g_switch_value > 0)
17323 const char *symname;
17326 /* Find out whether this symbol can be referenced off the $gp
17327 register. It can be if it is smaller than the -G size or if
17328 it is in the .sdata or .sbss section. Certain symbols can
17329 not be referenced off the $gp, although it appears as though
17331 symname = S_GET_NAME (sym);
17332 if (symname != (const char *) NULL
17333 && (strcmp (symname, "eprol") == 0
17334 || strcmp (symname, "etext") == 0
17335 || strcmp (symname, "_gp") == 0
17336 || strcmp (symname, "edata") == 0
17337 || strcmp (symname, "_fbss") == 0
17338 || strcmp (symname, "_fdata") == 0
17339 || strcmp (symname, "_ftext") == 0
17340 || strcmp (symname, "end") == 0
17341 || strcmp (symname, "_gp_disp") == 0))
17343 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17345 #ifndef NO_ECOFF_DEBUGGING
17346 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17347 && (symbol_get_obj (sym)->ecoff_extern_size
17348 <= g_switch_value))
17350 /* We must defer this decision until after the whole
17351 file has been read, since there might be a .extern
17352 after the first use of this symbol. */
17353 || (before_relaxing
17354 #ifndef NO_ECOFF_DEBUGGING
17355 && symbol_get_obj (sym)->ecoff_extern_size == 0
17357 && S_GET_VALUE (sym) == 0)
17358 || (S_GET_VALUE (sym) != 0
17359 && S_GET_VALUE (sym) <= g_switch_value)))
17363 const char *segname;
17365 segname = segment_name (S_GET_SEGMENT (sym));
17366 gas_assert (strcmp (segname, ".lit8") != 0
17367 && strcmp (segname, ".lit4") != 0);
17368 change = (strcmp (segname, ".sdata") != 0
17369 && strcmp (segname, ".sbss") != 0
17370 && strncmp (segname, ".sdata.", 7) != 0
17371 && strncmp (segname, ".sbss.", 6) != 0
17372 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17373 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17378 /* We are not optimizing for the $gp register. */
17383 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17386 pic_need_relax (symbolS *sym, asection *segtype)
17390 /* Handle the case of a symbol equated to another symbol. */
17391 while (symbol_equated_reloc_p (sym))
17395 /* It's possible to get a loop here in a badly written program. */
17396 n = symbol_get_value_expression (sym)->X_add_symbol;
17402 if (symbol_section_p (sym))
17405 symsec = S_GET_SEGMENT (sym);
17407 /* This must duplicate the test in adjust_reloc_syms. */
17408 return (!bfd_is_und_section (symsec)
17409 && !bfd_is_abs_section (symsec)
17410 && !bfd_is_com_section (symsec)
17411 && !s_is_linkonce (sym, segtype)
17413 /* A global or weak symbol is treated as external. */
17414 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17420 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17421 extended opcode. SEC is the section the frag is in. */
17424 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17427 const struct mips16_immed_operand *op;
17429 int mintiny, maxtiny;
17433 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17435 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17438 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17439 op = mips16_immed_operands;
17440 while (op->type != type)
17443 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17448 if (type == '<' || type == '>' || type == '[' || type == ']')
17451 maxtiny = 1 << op->nbits;
17456 maxtiny = (1 << op->nbits) - 1;
17461 mintiny = - (1 << (op->nbits - 1));
17462 maxtiny = (1 << (op->nbits - 1)) - 1;
17465 sym_frag = symbol_get_frag (fragp->fr_symbol);
17466 val = S_GET_VALUE (fragp->fr_symbol);
17467 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17473 /* We won't have the section when we are called from
17474 mips_relax_frag. However, we will always have been called
17475 from md_estimate_size_before_relax first. If this is a
17476 branch to a different section, we mark it as such. If SEC is
17477 NULL, and the frag is not marked, then it must be a branch to
17478 the same section. */
17481 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17486 /* Must have been called from md_estimate_size_before_relax. */
17489 fragp->fr_subtype =
17490 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17492 /* FIXME: We should support this, and let the linker
17493 catch branches and loads that are out of range. */
17494 as_bad_where (fragp->fr_file, fragp->fr_line,
17495 _("unsupported PC relative reference to different section"));
17499 if (fragp != sym_frag && sym_frag->fr_address == 0)
17500 /* Assume non-extended on the first relaxation pass.
17501 The address we have calculated will be bogus if this is
17502 a forward branch to another frag, as the forward frag
17503 will have fr_address == 0. */
17507 /* In this case, we know for sure that the symbol fragment is in
17508 the same section. If the relax_marker of the symbol fragment
17509 differs from the relax_marker of this fragment, we have not
17510 yet adjusted the symbol fragment fr_address. We want to add
17511 in STRETCH in order to get a better estimate of the address.
17512 This particularly matters because of the shift bits. */
17514 && sym_frag->relax_marker != fragp->relax_marker)
17518 /* Adjust stretch for any alignment frag. Note that if have
17519 been expanding the earlier code, the symbol may be
17520 defined in what appears to be an earlier frag. FIXME:
17521 This doesn't handle the fr_subtype field, which specifies
17522 a maximum number of bytes to skip when doing an
17524 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17526 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17529 stretch = - ((- stretch)
17530 & ~ ((1 << (int) f->fr_offset) - 1));
17532 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17541 addr = fragp->fr_address + fragp->fr_fix;
17543 /* The base address rules are complicated. The base address of
17544 a branch is the following instruction. The base address of a
17545 PC relative load or add is the instruction itself, but if it
17546 is in a delay slot (in which case it can not be extended) use
17547 the address of the instruction whose delay slot it is in. */
17548 if (type == 'p' || type == 'q')
17552 /* If we are currently assuming that this frag should be
17553 extended, then, the current address is two bytes
17555 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17558 /* Ignore the low bit in the target, since it will be set
17559 for a text label. */
17560 if ((val & 1) != 0)
17563 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17565 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17568 val -= addr & ~ ((1 << op->shift) - 1);
17570 /* Branch offsets have an implicit 0 in the lowest bit. */
17571 if (type == 'p' || type == 'q')
17574 /* If any of the shifted bits are set, we must use an extended
17575 opcode. If the address depends on the size of this
17576 instruction, this can lead to a loop, so we arrange to always
17577 use an extended opcode. We only check this when we are in
17578 the main relaxation loop, when SEC is NULL. */
17579 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17581 fragp->fr_subtype =
17582 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17586 /* If we are about to mark a frag as extended because the value
17587 is precisely maxtiny + 1, then there is a chance of an
17588 infinite loop as in the following code:
17593 In this case when the la is extended, foo is 0x3fc bytes
17594 away, so the la can be shrunk, but then foo is 0x400 away, so
17595 the la must be extended. To avoid this loop, we mark the
17596 frag as extended if it was small, and is about to become
17597 extended with a value of maxtiny + 1. */
17598 if (val == ((maxtiny + 1) << op->shift)
17599 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17602 fragp->fr_subtype =
17603 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17607 else if (symsec != absolute_section && sec != NULL)
17608 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17610 if ((val & ((1 << op->shift) - 1)) != 0
17611 || val < (mintiny << op->shift)
17612 || val > (maxtiny << op->shift))
17618 /* Compute the length of a branch sequence, and adjust the
17619 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17620 worst-case length is computed, with UPDATE being used to indicate
17621 whether an unconditional (-1), branch-likely (+1) or regular (0)
17622 branch is to be computed. */
17624 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17626 bfd_boolean toofar;
17630 && S_IS_DEFINED (fragp->fr_symbol)
17631 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17636 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17638 addr = fragp->fr_address + fragp->fr_fix + 4;
17642 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17645 /* If the symbol is not defined or it's in a different segment,
17646 assume the user knows what's going on and emit a short
17652 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17654 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17655 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17656 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17657 RELAX_BRANCH_LINK (fragp->fr_subtype),
17663 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17666 if (mips_pic != NO_PIC)
17668 /* Additional space for PIC loading of target address. */
17670 if (mips_opts.isa == ISA_MIPS1)
17671 /* Additional space for $at-stabilizing nop. */
17675 /* If branch is conditional. */
17676 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17683 /* Compute the length of a branch sequence, and adjust the
17684 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17685 worst-case length is computed, with UPDATE being used to indicate
17686 whether an unconditional (-1), or regular (0) branch is to be
17690 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17692 bfd_boolean toofar;
17696 && S_IS_DEFINED (fragp->fr_symbol)
17697 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17702 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17703 /* Ignore the low bit in the target, since it will be set
17704 for a text label. */
17705 if ((val & 1) != 0)
17708 addr = fragp->fr_address + fragp->fr_fix + 4;
17712 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17715 /* If the symbol is not defined or it's in a different segment,
17716 assume the user knows what's going on and emit a short
17722 if (fragp && update
17723 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17724 fragp->fr_subtype = (toofar
17725 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17726 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17731 bfd_boolean compact_known = fragp != NULL;
17732 bfd_boolean compact = FALSE;
17733 bfd_boolean uncond;
17736 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17738 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17740 uncond = update < 0;
17742 /* If label is out of range, we turn branch <br>:
17744 <br> label # 4 bytes
17750 nop # 2 bytes if compact && !PIC
17753 if (mips_pic == NO_PIC && (!compact_known || compact))
17756 /* If assembling PIC code, we further turn:
17762 lw/ld at, %got(label)(gp) # 4 bytes
17763 d/addiu at, %lo(label) # 4 bytes
17766 if (mips_pic != NO_PIC)
17769 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17771 <brneg> 0f # 4 bytes
17772 nop # 2 bytes if !compact
17775 length += (compact_known && compact) ? 4 : 6;
17781 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17782 bit accordingly. */
17785 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17787 bfd_boolean toofar;
17790 && S_IS_DEFINED (fragp->fr_symbol)
17791 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17797 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17798 /* Ignore the low bit in the target, since it will be set
17799 for a text label. */
17800 if ((val & 1) != 0)
17803 /* Assume this is a 2-byte branch. */
17804 addr = fragp->fr_address + fragp->fr_fix + 2;
17806 /* We try to avoid the infinite loop by not adding 2 more bytes for
17811 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17813 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17814 else if (type == 'E')
17815 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17820 /* If the symbol is not defined or it's in a different segment,
17821 we emit a normal 32-bit branch. */
17824 if (fragp && update
17825 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17827 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17828 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17836 /* Estimate the size of a frag before relaxing. Unless this is the
17837 mips16, we are not really relaxing here, and the final size is
17838 encoded in the subtype information. For the mips16, we have to
17839 decide whether we are using an extended opcode or not. */
17842 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17846 if (RELAX_BRANCH_P (fragp->fr_subtype))
17849 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17851 return fragp->fr_var;
17854 if (RELAX_MIPS16_P (fragp->fr_subtype))
17855 /* We don't want to modify the EXTENDED bit here; it might get us
17856 into infinite loops. We change it only in mips_relax_frag(). */
17857 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17859 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17863 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17864 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17865 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17866 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17867 fragp->fr_var = length;
17872 if (mips_pic == NO_PIC)
17873 change = nopic_need_relax (fragp->fr_symbol, 0);
17874 else if (mips_pic == SVR4_PIC)
17875 change = pic_need_relax (fragp->fr_symbol, segtype);
17876 else if (mips_pic == VXWORKS_PIC)
17877 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17884 fragp->fr_subtype |= RELAX_USE_SECOND;
17885 return -RELAX_FIRST (fragp->fr_subtype);
17888 return -RELAX_SECOND (fragp->fr_subtype);
17891 /* This is called to see whether a reloc against a defined symbol
17892 should be converted into a reloc against a section. */
17895 mips_fix_adjustable (fixS *fixp)
17897 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17898 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17901 if (fixp->fx_addsy == NULL)
17904 /* If symbol SYM is in a mergeable section, relocations of the form
17905 SYM + 0 can usually be made section-relative. The mergeable data
17906 is then identified by the section offset rather than by the symbol.
17908 However, if we're generating REL LO16 relocations, the offset is split
17909 between the LO16 and parterning high part relocation. The linker will
17910 need to recalculate the complete offset in order to correctly identify
17913 The linker has traditionally not looked for the parterning high part
17914 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17915 placed anywhere. Rather than break backwards compatibility by changing
17916 this, it seems better not to force the issue, and instead keep the
17917 original symbol. This will work with either linker behavior. */
17918 if ((lo16_reloc_p (fixp->fx_r_type)
17919 || reloc_needs_lo_p (fixp->fx_r_type))
17920 && HAVE_IN_PLACE_ADDENDS
17921 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17924 /* There is no place to store an in-place offset for JALR relocations.
17925 Likewise an in-range offset of limited PC-relative relocations may
17926 overflow the in-place relocatable field if recalculated against the
17927 start address of the symbol's containing section. */
17928 if (HAVE_IN_PLACE_ADDENDS
17929 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17930 || jalr_reloc_p (fixp->fx_r_type)))
17934 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17935 to a floating-point stub. The same is true for non-R_MIPS16_26
17936 relocations against MIPS16 functions; in this case, the stub becomes
17937 the function's canonical address.
17939 Floating-point stubs are stored in unique .mips16.call.* or
17940 .mips16.fn.* sections. If a stub T for function F is in section S,
17941 the first relocation in section S must be against F; this is how the
17942 linker determines the target function. All relocations that might
17943 resolve to T must also be against F. We therefore have the following
17944 restrictions, which are given in an intentionally-redundant way:
17946 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17949 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17950 if that stub might be used.
17952 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17955 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17956 that stub might be used.
17958 There is a further restriction:
17960 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17961 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17962 targets with in-place addends; the relocation field cannot
17963 encode the low bit.
17965 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17966 against a MIPS16 symbol. We deal with (5) by by not reducing any
17967 such relocations on REL targets.
17969 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17970 relocation against some symbol R, no relocation against R may be
17971 reduced. (Note that this deals with (2) as well as (1) because
17972 relocations against global symbols will never be reduced on ELF
17973 targets.) This approach is a little simpler than trying to detect
17974 stub sections, and gives the "all or nothing" per-symbol consistency
17975 that we have for MIPS16 symbols. */
17977 && fixp->fx_subsy == NULL
17978 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17979 || *symbol_get_tc (fixp->fx_addsy)
17980 || (HAVE_IN_PLACE_ADDENDS
17981 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17982 && jmp_reloc_p (fixp->fx_r_type))))
17989 /* Translate internal representation of relocation info to BFD target
17993 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17995 static arelent *retval[4];
17997 bfd_reloc_code_real_type code;
17999 memset (retval, 0, sizeof(retval));
18000 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
18001 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
18002 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18003 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18005 if (fixp->fx_pcrel)
18007 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18008 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18009 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18010 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18011 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18013 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18014 Relocations want only the symbol offset. */
18015 reloc->addend = fixp->fx_addnumber + reloc->address;
18018 /* A gruesome hack which is a result of the gruesome gas
18019 reloc handling. What's worse, for COFF (as opposed to
18020 ECOFF), we might need yet another copy of reloc->address.
18021 See bfd_install_relocation. */
18022 reloc->addend += reloc->address;
18026 reloc->addend = fixp->fx_addnumber;
18028 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18029 entry to be used in the relocation's section offset. */
18030 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18032 reloc->address = reloc->addend;
18036 code = fixp->fx_r_type;
18038 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18039 if (reloc->howto == NULL)
18041 as_bad_where (fixp->fx_file, fixp->fx_line,
18042 _("Can not represent %s relocation in this object file format"),
18043 bfd_get_reloc_code_name (code));
18050 /* Relax a machine dependent frag. This returns the amount by which
18051 the current size of the frag should change. */
18054 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18056 if (RELAX_BRANCH_P (fragp->fr_subtype))
18058 offsetT old_var = fragp->fr_var;
18060 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18062 return fragp->fr_var - old_var;
18065 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18067 offsetT old_var = fragp->fr_var;
18068 offsetT new_var = 4;
18070 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18071 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18072 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18073 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18074 fragp->fr_var = new_var;
18076 return new_var - old_var;
18079 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18082 if (mips16_extended_frag (fragp, NULL, stretch))
18084 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18086 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18091 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18093 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18100 /* Convert a machine dependent frag. */
18103 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18105 if (RELAX_BRANCH_P (fragp->fr_subtype))
18108 unsigned long insn;
18112 buf = fragp->fr_literal + fragp->fr_fix;
18113 insn = read_insn (buf);
18115 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18117 /* We generate a fixup instead of applying it right now
18118 because, if there are linker relaxations, we're going to
18119 need the relocations. */
18120 exp.X_op = O_symbol;
18121 exp.X_add_symbol = fragp->fr_symbol;
18122 exp.X_add_number = fragp->fr_offset;
18124 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18125 BFD_RELOC_16_PCREL_S2);
18126 fixp->fx_file = fragp->fr_file;
18127 fixp->fx_line = fragp->fr_line;
18129 buf = write_insn (buf, insn);
18135 as_warn_where (fragp->fr_file, fragp->fr_line,
18136 _("Relaxed out-of-range branch into a jump"));
18138 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18141 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18143 /* Reverse the branch. */
18144 switch ((insn >> 28) & 0xf)
18147 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18148 have the condition reversed by tweaking a single
18149 bit, and their opcodes all have 0x4???????. */
18150 gas_assert ((insn & 0xf1000000) == 0x41000000);
18151 insn ^= 0x00010000;
18155 /* bltz 0x04000000 bgez 0x04010000
18156 bltzal 0x04100000 bgezal 0x04110000 */
18157 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18158 insn ^= 0x00010000;
18162 /* beq 0x10000000 bne 0x14000000
18163 blez 0x18000000 bgtz 0x1c000000 */
18164 insn ^= 0x04000000;
18172 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18174 /* Clear the and-link bit. */
18175 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18177 /* bltzal 0x04100000 bgezal 0x04110000
18178 bltzall 0x04120000 bgezall 0x04130000 */
18179 insn &= ~0x00100000;
18182 /* Branch over the branch (if the branch was likely) or the
18183 full jump (not likely case). Compute the offset from the
18184 current instruction to branch to. */
18185 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18189 /* How many bytes in instructions we've already emitted? */
18190 i = buf - fragp->fr_literal - fragp->fr_fix;
18191 /* How many bytes in instructions from here to the end? */
18192 i = fragp->fr_var - i;
18194 /* Convert to instruction count. */
18196 /* Branch counts from the next instruction. */
18199 /* Branch over the jump. */
18200 buf = write_insn (buf, insn);
18203 buf = write_insn (buf, 0);
18205 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18207 /* beql $0, $0, 2f */
18209 /* Compute the PC offset from the current instruction to
18210 the end of the variable frag. */
18211 /* How many bytes in instructions we've already emitted? */
18212 i = buf - fragp->fr_literal - fragp->fr_fix;
18213 /* How many bytes in instructions from here to the end? */
18214 i = fragp->fr_var - i;
18215 /* Convert to instruction count. */
18217 /* Don't decrement i, because we want to branch over the
18221 buf = write_insn (buf, insn);
18222 buf = write_insn (buf, 0);
18226 if (mips_pic == NO_PIC)
18229 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18230 ? 0x0c000000 : 0x08000000);
18231 exp.X_op = O_symbol;
18232 exp.X_add_symbol = fragp->fr_symbol;
18233 exp.X_add_number = fragp->fr_offset;
18235 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18236 FALSE, BFD_RELOC_MIPS_JMP);
18237 fixp->fx_file = fragp->fr_file;
18238 fixp->fx_line = fragp->fr_line;
18240 buf = write_insn (buf, insn);
18244 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18246 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18247 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18248 insn |= at << OP_SH_RT;
18249 exp.X_op = O_symbol;
18250 exp.X_add_symbol = fragp->fr_symbol;
18251 exp.X_add_number = fragp->fr_offset;
18253 if (fragp->fr_offset)
18255 exp.X_add_symbol = make_expr_symbol (&exp);
18256 exp.X_add_number = 0;
18259 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18260 FALSE, BFD_RELOC_MIPS_GOT16);
18261 fixp->fx_file = fragp->fr_file;
18262 fixp->fx_line = fragp->fr_line;
18264 buf = write_insn (buf, insn);
18266 if (mips_opts.isa == ISA_MIPS1)
18268 buf = write_insn (buf, 0);
18270 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18271 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18272 insn |= at << OP_SH_RS | at << OP_SH_RT;
18274 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18275 FALSE, BFD_RELOC_LO16);
18276 fixp->fx_file = fragp->fr_file;
18277 fixp->fx_line = fragp->fr_line;
18279 buf = write_insn (buf, insn);
18282 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18286 insn |= at << OP_SH_RS;
18288 buf = write_insn (buf, insn);
18292 fragp->fr_fix += fragp->fr_var;
18293 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18297 /* Relax microMIPS branches. */
18298 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18300 char *buf = fragp->fr_literal + fragp->fr_fix;
18301 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18302 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18303 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18304 bfd_boolean short_ds;
18305 unsigned long insn;
18309 exp.X_op = O_symbol;
18310 exp.X_add_symbol = fragp->fr_symbol;
18311 exp.X_add_number = fragp->fr_offset;
18313 fragp->fr_fix += fragp->fr_var;
18315 /* Handle 16-bit branches that fit or are forced to fit. */
18316 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18318 /* We generate a fixup instead of applying it right now,
18319 because if there is linker relaxation, we're going to
18320 need the relocations. */
18322 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18323 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18324 else if (type == 'E')
18325 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18326 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18330 fixp->fx_file = fragp->fr_file;
18331 fixp->fx_line = fragp->fr_line;
18333 /* These relocations can have an addend that won't fit in
18335 fixp->fx_no_overflow = 1;
18340 /* Handle 32-bit branches that fit or are forced to fit. */
18341 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18342 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18344 /* We generate a fixup instead of applying it right now,
18345 because if there is linker relaxation, we're going to
18346 need the relocations. */
18347 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18348 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18349 fixp->fx_file = fragp->fr_file;
18350 fixp->fx_line = fragp->fr_line;
18356 /* Relax 16-bit branches to 32-bit branches. */
18359 insn = read_compressed_insn (buf, 2);
18361 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18362 insn = 0x94000000; /* beq */
18363 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18365 unsigned long regno;
18367 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18368 regno = micromips_to_32_reg_d_map [regno];
18369 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18370 insn |= regno << MICROMIPSOP_SH_RS;
18375 /* Nothing else to do, just write it out. */
18376 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18377 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18379 buf = write_compressed_insn (buf, insn, 4);
18380 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18385 insn = read_compressed_insn (buf, 4);
18387 /* Relax 32-bit branches to a sequence of instructions. */
18388 as_warn_where (fragp->fr_file, fragp->fr_line,
18389 _("Relaxed out-of-range branch into a jump"));
18391 /* Set the short-delay-slot bit. */
18392 short_ds = al && (insn & 0x02000000) != 0;
18394 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18398 /* Reverse the branch. */
18399 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18400 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18401 insn ^= 0x20000000;
18402 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18403 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18404 || (insn & 0xffe00000) == 0x40800000 /* blez */
18405 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18406 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18407 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18408 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18409 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18410 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18411 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18412 insn ^= 0x00400000;
18413 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18414 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18415 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18416 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18417 insn ^= 0x00200000;
18423 /* Clear the and-link and short-delay-slot bits. */
18424 gas_assert ((insn & 0xfda00000) == 0x40200000);
18426 /* bltzal 0x40200000 bgezal 0x40600000 */
18427 /* bltzals 0x42200000 bgezals 0x42600000 */
18428 insn &= ~0x02200000;
18431 /* Make a label at the end for use with the branch. */
18432 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18433 micromips_label_inc ();
18434 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18436 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18440 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18441 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18442 fixp->fx_file = fragp->fr_file;
18443 fixp->fx_line = fragp->fr_line;
18445 /* Branch over the jump. */
18446 buf = write_compressed_insn (buf, insn, 4);
18449 buf = write_compressed_insn (buf, 0x0c00, 2);
18452 if (mips_pic == NO_PIC)
18454 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18456 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18457 insn = al ? jal : 0xd4000000;
18459 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18460 BFD_RELOC_MICROMIPS_JMP);
18461 fixp->fx_file = fragp->fr_file;
18462 fixp->fx_line = fragp->fr_line;
18464 buf = write_compressed_insn (buf, insn, 4);
18467 buf = write_compressed_insn (buf, 0x0c00, 2);
18471 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18472 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18473 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18475 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18476 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18477 insn |= at << MICROMIPSOP_SH_RT;
18479 if (exp.X_add_number)
18481 exp.X_add_symbol = make_expr_symbol (&exp);
18482 exp.X_add_number = 0;
18485 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18486 BFD_RELOC_MICROMIPS_GOT16);
18487 fixp->fx_file = fragp->fr_file;
18488 fixp->fx_line = fragp->fr_line;
18490 buf = write_compressed_insn (buf, insn, 4);
18492 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18493 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18494 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18496 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18497 BFD_RELOC_MICROMIPS_LO16);
18498 fixp->fx_file = fragp->fr_file;
18499 fixp->fx_line = fragp->fr_line;
18501 buf = write_compressed_insn (buf, insn, 4);
18503 /* jr/jrc/jalr/jalrs $at */
18504 insn = al ? jalr : jr;
18505 insn |= at << MICROMIPSOP_SH_MJ;
18507 buf = write_compressed_insn (buf, insn, 2);
18510 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18514 if (RELAX_MIPS16_P (fragp->fr_subtype))
18517 const struct mips16_immed_operand *op;
18520 unsigned int user_length, length;
18521 unsigned long insn;
18524 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18525 op = mips16_immed_operands;
18526 while (op->type != type)
18529 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18530 val = resolve_symbol_value (fragp->fr_symbol);
18535 addr = fragp->fr_address + fragp->fr_fix;
18537 /* The rules for the base address of a PC relative reloc are
18538 complicated; see mips16_extended_frag. */
18539 if (type == 'p' || type == 'q')
18544 /* Ignore the low bit in the target, since it will be
18545 set for a text label. */
18546 if ((val & 1) != 0)
18549 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18551 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18554 addr &= ~ (addressT) ((1 << op->shift) - 1);
18557 /* Make sure the section winds up with the alignment we have
18560 record_alignment (asec, op->shift);
18564 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18565 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18566 as_warn_where (fragp->fr_file, fragp->fr_line,
18567 _("extended instruction in delay slot"));
18569 buf = fragp->fr_literal + fragp->fr_fix;
18571 insn = read_compressed_insn (buf, 2);
18573 insn |= MIPS16_EXTEND;
18575 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18577 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18582 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18583 BFD_RELOC_UNUSED, val, user_length, &insn);
18585 length = (ext ? 4 : 2);
18586 gas_assert (mips16_opcode_length (insn) == length);
18587 write_compressed_insn (buf, insn, length);
18588 fragp->fr_fix += length;
18592 relax_substateT subtype = fragp->fr_subtype;
18593 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18594 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18598 first = RELAX_FIRST (subtype);
18599 second = RELAX_SECOND (subtype);
18600 fixp = (fixS *) fragp->fr_opcode;
18602 /* If the delay slot chosen does not match the size of the instruction,
18603 then emit a warning. */
18604 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18605 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18610 s = subtype & (RELAX_DELAY_SLOT_16BIT
18611 | RELAX_DELAY_SLOT_SIZE_FIRST
18612 | RELAX_DELAY_SLOT_SIZE_SECOND);
18613 msg = macro_warning (s);
18615 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18619 /* Possibly emit a warning if we've chosen the longer option. */
18620 if (use_second == second_longer)
18626 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18627 msg = macro_warning (s);
18629 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18633 /* Go through all the fixups for the first sequence. Disable them
18634 (by marking them as done) if we're going to use the second
18635 sequence instead. */
18637 && fixp->fx_frag == fragp
18638 && fixp->fx_where < fragp->fr_fix - second)
18640 if (subtype & RELAX_USE_SECOND)
18642 fixp = fixp->fx_next;
18645 /* Go through the fixups for the second sequence. Disable them if
18646 we're going to use the first sequence, otherwise adjust their
18647 addresses to account for the relaxation. */
18648 while (fixp && fixp->fx_frag == fragp)
18650 if (subtype & RELAX_USE_SECOND)
18651 fixp->fx_where -= first;
18654 fixp = fixp->fx_next;
18657 /* Now modify the frag contents. */
18658 if (subtype & RELAX_USE_SECOND)
18662 start = fragp->fr_literal + fragp->fr_fix - first - second;
18663 memmove (start, start + first, second);
18664 fragp->fr_fix -= first;
18667 fragp->fr_fix -= second;
18673 /* This function is called after the relocs have been generated.
18674 We've been storing mips16 text labels as odd. Here we convert them
18675 back to even for the convenience of the debugger. */
18678 mips_frob_file_after_relocs (void)
18681 unsigned int count, i;
18686 syms = bfd_get_outsymbols (stdoutput);
18687 count = bfd_get_symcount (stdoutput);
18688 for (i = 0; i < count; i++, syms++)
18689 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18690 && ((*syms)->value & 1) != 0)
18692 (*syms)->value &= ~1;
18693 /* If the symbol has an odd size, it was probably computed
18694 incorrectly, so adjust that as well. */
18695 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18696 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18702 /* This function is called whenever a label is defined, including fake
18703 labels instantiated off the dot special symbol. It is used when
18704 handling branch delays; if a branch has a label, we assume we cannot
18705 move it. This also bumps the value of the symbol by 1 in compressed
18709 mips_record_label (symbolS *sym)
18711 segment_info_type *si = seg_info (now_seg);
18712 struct insn_label_list *l;
18714 if (free_insn_labels == NULL)
18715 l = (struct insn_label_list *) xmalloc (sizeof *l);
18718 l = free_insn_labels;
18719 free_insn_labels = l->next;
18723 l->next = si->label_list;
18724 si->label_list = l;
18727 /* This function is called as tc_frob_label() whenever a label is defined
18728 and adds a DWARF-2 record we only want for true labels. */
18731 mips_define_label (symbolS *sym)
18733 mips_record_label (sym);
18735 dwarf2_emit_label (sym);
18739 /* This function is called by tc_new_dot_label whenever a new dot symbol
18743 mips_add_dot_label (symbolS *sym)
18745 mips_record_label (sym);
18746 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18747 mips_compressed_mark_label (sym);
18750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18752 /* Some special processing for a MIPS ELF file. */
18755 mips_elf_final_processing (void)
18757 /* Write out the register information. */
18758 if (mips_abi != N64_ABI)
18762 s.ri_gprmask = mips_gprmask;
18763 s.ri_cprmask[0] = mips_cprmask[0];
18764 s.ri_cprmask[1] = mips_cprmask[1];
18765 s.ri_cprmask[2] = mips_cprmask[2];
18766 s.ri_cprmask[3] = mips_cprmask[3];
18767 /* The gp_value field is set by the MIPS ELF backend. */
18769 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18770 ((Elf32_External_RegInfo *)
18771 mips_regmask_frag));
18775 Elf64_Internal_RegInfo s;
18777 s.ri_gprmask = mips_gprmask;
18779 s.ri_cprmask[0] = mips_cprmask[0];
18780 s.ri_cprmask[1] = mips_cprmask[1];
18781 s.ri_cprmask[2] = mips_cprmask[2];
18782 s.ri_cprmask[3] = mips_cprmask[3];
18783 /* The gp_value field is set by the MIPS ELF backend. */
18785 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18786 ((Elf64_External_RegInfo *)
18787 mips_regmask_frag));
18790 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18791 sort of BFD interface for this. */
18792 if (mips_any_noreorder)
18793 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18794 if (mips_pic != NO_PIC)
18796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18797 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18800 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18802 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18803 defined at present; this might need to change in future. */
18804 if (file_ase_mips16)
18805 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18806 if (file_ase_micromips)
18807 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18808 #if 0 /* XXX FIXME */
18809 if (file_ase_mips3d)
18810 elf_elfheader (stdoutput)->e_flags |= ???;
18813 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18815 /* Set the MIPS ELF ABI flags. */
18816 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18817 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18818 else if (mips_abi == O64_ABI)
18819 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18820 else if (mips_abi == EABI_ABI)
18822 if (!file_mips_gp32)
18823 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18825 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18827 else if (mips_abi == N32_ABI)
18828 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18830 /* Nothing to do for N64_ABI. */
18832 if (mips_32bitmode)
18833 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18835 #if 0 /* XXX FIXME */
18836 /* 32 bit code with 64 bit FP registers. */
18837 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18838 elf_elfheader (stdoutput)->e_flags |= ???;
18842 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18844 typedef struct proc {
18846 symbolS *func_end_sym;
18847 unsigned long reg_mask;
18848 unsigned long reg_offset;
18849 unsigned long fpreg_mask;
18850 unsigned long fpreg_offset;
18851 unsigned long frame_offset;
18852 unsigned long frame_reg;
18853 unsigned long pc_reg;
18856 static procS cur_proc;
18857 static procS *cur_proc_ptr;
18858 static int numprocs;
18860 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18861 as "2", and a normal nop as "0". */
18863 #define NOP_OPCODE_MIPS 0
18864 #define NOP_OPCODE_MIPS16 1
18865 #define NOP_OPCODE_MICROMIPS 2
18868 mips_nop_opcode (void)
18870 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18871 return NOP_OPCODE_MICROMIPS;
18872 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18873 return NOP_OPCODE_MIPS16;
18875 return NOP_OPCODE_MIPS;
18878 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18879 32-bit microMIPS NOPs here (if applicable). */
18882 mips_handle_align (fragS *fragp)
18886 int bytes, size, excess;
18889 if (fragp->fr_type != rs_align_code)
18892 p = fragp->fr_literal + fragp->fr_fix;
18894 switch (nop_opcode)
18896 case NOP_OPCODE_MICROMIPS:
18897 opcode = micromips_nop32_insn.insn_opcode;
18900 case NOP_OPCODE_MIPS16:
18901 opcode = mips16_nop_insn.insn_opcode;
18904 case NOP_OPCODE_MIPS:
18906 opcode = nop_insn.insn_opcode;
18911 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18912 excess = bytes % size;
18914 /* Handle the leading part if we're not inserting a whole number of
18915 instructions, and make it the end of the fixed part of the frag.
18916 Try to fit in a short microMIPS NOP if applicable and possible,
18917 and use zeroes otherwise. */
18918 gas_assert (excess < 4);
18919 fragp->fr_fix += excess;
18924 /* Fall through. */
18926 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18928 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18932 /* Fall through. */
18935 /* Fall through. */
18940 md_number_to_chars (p, opcode, size);
18941 fragp->fr_var = size;
18945 md_obj_begin (void)
18952 /* Check for premature end, nesting errors, etc. */
18954 as_warn (_("missing .end at end of assembly"));
18963 if (*input_line_pointer == '-')
18965 ++input_line_pointer;
18968 if (!ISDIGIT (*input_line_pointer))
18969 as_bad (_("expected simple number"));
18970 if (input_line_pointer[0] == '0')
18972 if (input_line_pointer[1] == 'x')
18974 input_line_pointer += 2;
18975 while (ISXDIGIT (*input_line_pointer))
18978 val |= hex_value (*input_line_pointer++);
18980 return negative ? -val : val;
18984 ++input_line_pointer;
18985 while (ISDIGIT (*input_line_pointer))
18988 val |= *input_line_pointer++ - '0';
18990 return negative ? -val : val;
18993 if (!ISDIGIT (*input_line_pointer))
18995 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18996 *input_line_pointer, *input_line_pointer);
18997 as_warn (_("invalid number"));
19000 while (ISDIGIT (*input_line_pointer))
19003 val += *input_line_pointer++ - '0';
19005 return negative ? -val : val;
19008 /* The .file directive; just like the usual .file directive, but there
19009 is an initial number which is the ECOFF file index. In the non-ECOFF
19010 case .file implies DWARF-2. */
19013 s_mips_file (int x ATTRIBUTE_UNUSED)
19015 static int first_file_directive = 0;
19017 if (ECOFF_DEBUGGING)
19026 filename = dwarf2_directive_file (0);
19028 /* Versions of GCC up to 3.1 start files with a ".file"
19029 directive even for stabs output. Make sure that this
19030 ".file" is handled. Note that you need a version of GCC
19031 after 3.1 in order to support DWARF-2 on MIPS. */
19032 if (filename != NULL && ! first_file_directive)
19034 (void) new_logical_line (filename, -1);
19035 s_app_file_string (filename, 0);
19037 first_file_directive = 1;
19041 /* The .loc directive, implying DWARF-2. */
19044 s_mips_loc (int x ATTRIBUTE_UNUSED)
19046 if (!ECOFF_DEBUGGING)
19047 dwarf2_directive_loc (0);
19050 /* The .end directive. */
19053 s_mips_end (int x ATTRIBUTE_UNUSED)
19057 /* Following functions need their own .frame and .cprestore directives. */
19058 mips_frame_reg_valid = 0;
19059 mips_cprestore_valid = 0;
19061 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19064 demand_empty_rest_of_line ();
19069 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19070 as_warn (_(".end not in text section"));
19074 as_warn (_(".end directive without a preceding .ent directive."));
19075 demand_empty_rest_of_line ();
19081 gas_assert (S_GET_NAME (p));
19082 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19083 as_warn (_(".end symbol does not match .ent symbol."));
19085 if (debug_type == DEBUG_STABS)
19086 stabs_generate_asm_endfunc (S_GET_NAME (p),
19090 as_warn (_(".end directive missing or unknown symbol"));
19093 /* Create an expression to calculate the size of the function. */
19094 if (p && cur_proc_ptr)
19096 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19097 expressionS *exp = xmalloc (sizeof (expressionS));
19100 exp->X_op = O_subtract;
19101 exp->X_add_symbol = symbol_temp_new_now ();
19102 exp->X_op_symbol = p;
19103 exp->X_add_number = 0;
19105 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19108 /* Generate a .pdr section. */
19109 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
19111 segT saved_seg = now_seg;
19112 subsegT saved_subseg = now_subseg;
19116 #ifdef md_flush_pending_output
19117 md_flush_pending_output ();
19120 gas_assert (pdr_seg);
19121 subseg_set (pdr_seg, 0);
19123 /* Write the symbol. */
19124 exp.X_op = O_symbol;
19125 exp.X_add_symbol = p;
19126 exp.X_add_number = 0;
19127 emit_expr (&exp, 4);
19129 fragp = frag_more (7 * 4);
19131 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19132 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19133 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19134 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19135 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19136 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19137 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19139 subseg_set (saved_seg, saved_subseg);
19141 #endif /* OBJ_ELF */
19143 cur_proc_ptr = NULL;
19146 /* The .aent and .ent directives. */
19149 s_mips_ent (int aent)
19153 symbolP = get_symbol ();
19154 if (*input_line_pointer == ',')
19155 ++input_line_pointer;
19156 SKIP_WHITESPACE ();
19157 if (ISDIGIT (*input_line_pointer)
19158 || *input_line_pointer == '-')
19161 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19162 as_warn (_(".ent or .aent not in text section."));
19164 if (!aent && cur_proc_ptr)
19165 as_warn (_("missing .end"));
19169 /* This function needs its own .frame and .cprestore directives. */
19170 mips_frame_reg_valid = 0;
19171 mips_cprestore_valid = 0;
19173 cur_proc_ptr = &cur_proc;
19174 memset (cur_proc_ptr, '\0', sizeof (procS));
19176 cur_proc_ptr->func_sym = symbolP;
19180 if (debug_type == DEBUG_STABS)
19181 stabs_generate_asm_func (S_GET_NAME (symbolP),
19182 S_GET_NAME (symbolP));
19185 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19187 demand_empty_rest_of_line ();
19190 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19191 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19192 s_mips_frame is used so that we can set the PDR information correctly.
19193 We can't use the ecoff routines because they make reference to the ecoff
19194 symbol table (in the mdebug section). */
19197 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19200 if (IS_ELF && !ECOFF_DEBUGGING)
19204 if (cur_proc_ptr == (procS *) NULL)
19206 as_warn (_(".frame outside of .ent"));
19207 demand_empty_rest_of_line ();
19211 cur_proc_ptr->frame_reg = tc_get_register (1);
19213 SKIP_WHITESPACE ();
19214 if (*input_line_pointer++ != ','
19215 || get_absolute_expression_and_terminator (&val) != ',')
19217 as_warn (_("Bad .frame directive"));
19218 --input_line_pointer;
19219 demand_empty_rest_of_line ();
19223 cur_proc_ptr->frame_offset = val;
19224 cur_proc_ptr->pc_reg = tc_get_register (0);
19226 demand_empty_rest_of_line ();
19229 #endif /* OBJ_ELF */
19233 /* The .fmask and .mask directives. If the mdebug section is present
19234 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19235 embedded targets, s_mips_mask is used so that we can set the PDR
19236 information correctly. We can't use the ecoff routines because they
19237 make reference to the ecoff symbol table (in the mdebug section). */
19240 s_mips_mask (int reg_type)
19243 if (IS_ELF && !ECOFF_DEBUGGING)
19247 if (cur_proc_ptr == (procS *) NULL)
19249 as_warn (_(".mask/.fmask outside of .ent"));
19250 demand_empty_rest_of_line ();
19254 if (get_absolute_expression_and_terminator (&mask) != ',')
19256 as_warn (_("Bad .mask/.fmask directive"));
19257 --input_line_pointer;
19258 demand_empty_rest_of_line ();
19262 off = get_absolute_expression ();
19264 if (reg_type == 'F')
19266 cur_proc_ptr->fpreg_mask = mask;
19267 cur_proc_ptr->fpreg_offset = off;
19271 cur_proc_ptr->reg_mask = mask;
19272 cur_proc_ptr->reg_offset = off;
19275 demand_empty_rest_of_line ();
19278 #endif /* OBJ_ELF */
19279 s_ignore (reg_type);
19282 /* A table describing all the processors gas knows about. Names are
19283 matched in the order listed.
19285 To ease comparison, please keep this table in the same order as
19286 gcc's mips_cpu_info_table[]. */
19287 static const struct mips_cpu_info mips_cpu_info_table[] =
19289 /* Entries for generic ISAs */
19290 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19291 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19292 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19293 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19294 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19295 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19296 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19298 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19301 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19302 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19303 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19306 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19309 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19310 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19311 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19312 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19313 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19314 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19315 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19316 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19317 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19318 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19319 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19320 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19321 { "r5900", 0, ISA_MIPS3, CPU_R5900 },
19322 /* ST Microelectronics Loongson 2E and 2F cores */
19323 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19324 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19327 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19328 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19329 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19330 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19331 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19332 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19333 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19334 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19335 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19336 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19337 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19338 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19339 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19340 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19341 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19344 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19345 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19346 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19347 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19349 /* MIPS 32 Release 2 */
19350 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19351 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19352 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19353 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19354 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19355 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19356 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19357 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19358 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19359 ISA_MIPS32R2, CPU_MIPS32R2 },
19360 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19361 ISA_MIPS32R2, CPU_MIPS32R2 },
19362 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19363 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19364 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19365 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19366 /* Deprecated forms of the above. */
19367 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19368 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19369 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19370 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19371 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19372 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19373 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19374 /* Deprecated forms of the above. */
19375 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19376 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19377 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19378 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19379 ISA_MIPS32R2, CPU_MIPS32R2 },
19380 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19381 ISA_MIPS32R2, CPU_MIPS32R2 },
19382 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19383 ISA_MIPS32R2, CPU_MIPS32R2 },
19384 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19385 ISA_MIPS32R2, CPU_MIPS32R2 },
19386 /* Deprecated forms of the above. */
19387 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19388 ISA_MIPS32R2, CPU_MIPS32R2 },
19389 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19390 ISA_MIPS32R2, CPU_MIPS32R2 },
19391 /* 34Kn is a 34kc without DSP. */
19392 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19393 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19394 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19395 ISA_MIPS32R2, CPU_MIPS32R2 },
19396 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19397 ISA_MIPS32R2, CPU_MIPS32R2 },
19398 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19399 ISA_MIPS32R2, CPU_MIPS32R2 },
19400 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19401 ISA_MIPS32R2, CPU_MIPS32R2 },
19402 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19403 ISA_MIPS32R2, CPU_MIPS32R2 },
19404 /* Deprecated forms of the above. */
19405 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19406 ISA_MIPS32R2, CPU_MIPS32R2 },
19407 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19408 ISA_MIPS32R2, CPU_MIPS32R2 },
19409 /* 1004K cores are multiprocessor versions of the 34K. */
19410 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19411 ISA_MIPS32R2, CPU_MIPS32R2 },
19412 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19413 ISA_MIPS32R2, CPU_MIPS32R2 },
19414 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19415 ISA_MIPS32R2, CPU_MIPS32R2 },
19416 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19417 ISA_MIPS32R2, CPU_MIPS32R2 },
19420 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19421 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19422 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19423 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19425 /* Broadcom SB-1 CPU core */
19426 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19427 ISA_MIPS64, CPU_SB1 },
19428 /* Broadcom SB-1A CPU core */
19429 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19430 ISA_MIPS64, CPU_SB1 },
19432 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19434 /* MIPS 64 Release 2 */
19436 /* Cavium Networks Octeon CPU core */
19437 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19438 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19439 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19442 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19445 XLP is mostly like XLR, with the prominent exception that it is
19446 MIPS64R2 rather than MIPS64. */
19447 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19454 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19455 with a final "000" replaced by "k". Ignore case.
19457 Note: this function is shared between GCC and GAS. */
19460 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19462 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19463 given++, canonical++;
19465 return ((*given == 0 && *canonical == 0)
19466 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19470 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19471 CPU name. We've traditionally allowed a lot of variation here.
19473 Note: this function is shared between GCC and GAS. */
19476 mips_matching_cpu_name_p (const char *canonical, const char *given)
19478 /* First see if the name matches exactly, or with a final "000"
19479 turned into "k". */
19480 if (mips_strict_matching_cpu_name_p (canonical, given))
19483 /* If not, try comparing based on numerical designation alone.
19484 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19485 if (TOLOWER (*given) == 'r')
19487 if (!ISDIGIT (*given))
19490 /* Skip over some well-known prefixes in the canonical name,
19491 hoping to find a number there too. */
19492 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19494 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19496 else if (TOLOWER (canonical[0]) == 'r')
19499 return mips_strict_matching_cpu_name_p (canonical, given);
19503 /* Parse an option that takes the name of a processor as its argument.
19504 OPTION is the name of the option and CPU_STRING is the argument.
19505 Return the corresponding processor enumeration if the CPU_STRING is
19506 recognized, otherwise report an error and return null.
19508 A similar function exists in GCC. */
19510 static const struct mips_cpu_info *
19511 mips_parse_cpu (const char *option, const char *cpu_string)
19513 const struct mips_cpu_info *p;
19515 /* 'from-abi' selects the most compatible architecture for the given
19516 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19517 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19518 version. Look first at the -mgp options, if given, otherwise base
19519 the choice on MIPS_DEFAULT_64BIT.
19521 Treat NO_ABI like the EABIs. One reason to do this is that the
19522 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19523 architecture. This code picks MIPS I for 'mips' and MIPS III for
19524 'mips64', just as we did in the days before 'from-abi'. */
19525 if (strcasecmp (cpu_string, "from-abi") == 0)
19527 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19528 return mips_cpu_info_from_isa (ISA_MIPS1);
19530 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19531 return mips_cpu_info_from_isa (ISA_MIPS3);
19533 if (file_mips_gp32 >= 0)
19534 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19536 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19541 /* 'default' has traditionally been a no-op. Probably not very useful. */
19542 if (strcasecmp (cpu_string, "default") == 0)
19545 for (p = mips_cpu_info_table; p->name != 0; p++)
19546 if (mips_matching_cpu_name_p (p->name, cpu_string))
19549 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19553 /* Return the canonical processor information for ISA (a member of the
19554 ISA_MIPS* enumeration). */
19556 static const struct mips_cpu_info *
19557 mips_cpu_info_from_isa (int isa)
19561 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19562 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19563 && isa == mips_cpu_info_table[i].isa)
19564 return (&mips_cpu_info_table[i]);
19569 static const struct mips_cpu_info *
19570 mips_cpu_info_from_arch (int arch)
19574 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19575 if (arch == mips_cpu_info_table[i].cpu)
19576 return (&mips_cpu_info_table[i]);
19582 show (FILE *stream, const char *string, int *col_p, int *first_p)
19586 fprintf (stream, "%24s", "");
19591 fprintf (stream, ", ");
19595 if (*col_p + strlen (string) > 72)
19597 fprintf (stream, "\n%24s", "");
19601 fprintf (stream, "%s", string);
19602 *col_p += strlen (string);
19608 md_show_usage (FILE *stream)
19613 fprintf (stream, _("\
19615 -EB generate big endian output\n\
19616 -EL generate little endian output\n\
19617 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19618 -G NUM allow referencing objects up to NUM bytes\n\
19619 implicitly with the gp register [default 8]\n"));
19620 fprintf (stream, _("\
19621 -mips1 generate MIPS ISA I instructions\n\
19622 -mips2 generate MIPS ISA II instructions\n\
19623 -mips3 generate MIPS ISA III instructions\n\
19624 -mips4 generate MIPS ISA IV instructions\n\
19625 -mips5 generate MIPS ISA V instructions\n\
19626 -mips32 generate MIPS32 ISA instructions\n\
19627 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19628 -mips64 generate MIPS64 ISA instructions\n\
19629 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19630 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19634 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19635 show (stream, mips_cpu_info_table[i].name, &column, &first);
19636 show (stream, "from-abi", &column, &first);
19637 fputc ('\n', stream);
19639 fprintf (stream, _("\
19640 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19641 -no-mCPU don't generate code specific to CPU.\n\
19642 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19646 show (stream, "3900", &column, &first);
19647 show (stream, "4010", &column, &first);
19648 show (stream, "4100", &column, &first);
19649 show (stream, "4650", &column, &first);
19650 fputc ('\n', stream);
19652 fprintf (stream, _("\
19653 -mips16 generate mips16 instructions\n\
19654 -no-mips16 do not generate mips16 instructions\n"));
19655 fprintf (stream, _("\
19656 -mmicromips generate microMIPS instructions\n\
19657 -mno-micromips do not generate microMIPS instructions\n"));
19658 fprintf (stream, _("\
19659 -msmartmips generate smartmips instructions\n\
19660 -mno-smartmips do not generate smartmips instructions\n"));
19661 fprintf (stream, _("\
19662 -mdsp generate DSP instructions\n\
19663 -mno-dsp do not generate DSP instructions\n"));
19664 fprintf (stream, _("\
19665 -mdspr2 generate DSP R2 instructions\n\
19666 -mno-dspr2 do not generate DSP R2 instructions\n"));
19667 fprintf (stream, _("\
19668 -mmt generate MT instructions\n\
19669 -mno-mt do not generate MT instructions\n"));
19670 fprintf (stream, _("\
19671 -mmcu generate MCU instructions\n\
19672 -mno-mcu do not generate MCU instructions\n"));
19673 fprintf (stream, _("\
19674 -mvirt generate Virtualization instructions\n\
19675 -mno-virt do not generate Virtualization instructions\n"));
19676 fprintf (stream, _("\
19677 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19678 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19679 -mfix-vr4120 work around certain VR4120 errata\n\
19680 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19681 -mfix-24k insert a nop after ERET and DERET instructions\n\
19682 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19683 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19684 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19685 -msym32 assume all symbols have 32-bit values\n\
19686 -O0 remove unneeded NOPs, do not swap branches\n\
19687 -O remove unneeded NOPs and swap branches\n\
19688 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19689 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19690 fprintf (stream, _("\
19691 -mhard-float allow floating-point instructions\n\
19692 -msoft-float do not allow floating-point instructions\n\
19693 -msingle-float only allow 32-bit floating-point operations\n\
19694 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19695 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19698 fprintf (stream, _("\
19699 -KPIC, -call_shared generate SVR4 position independent code\n\
19700 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19701 -mvxworks-pic generate VxWorks position independent code\n\
19702 -non_shared do not generate code that can operate with DSOs\n\
19703 -xgot assume a 32 bit GOT\n\
19704 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19705 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19706 position dependent (non shared) code\n\
19707 -mabi=ABI create ABI conformant object file for:\n"));
19711 show (stream, "32", &column, &first);
19712 show (stream, "o64", &column, &first);
19713 show (stream, "n32", &column, &first);
19714 show (stream, "64", &column, &first);
19715 show (stream, "eabi", &column, &first);
19717 fputc ('\n', stream);
19719 fprintf (stream, _("\
19720 -32 create o32 ABI object file (default)\n\
19721 -n32 create n32 ABI object file\n\
19722 -64 create 64 ABI object file\n"));
19728 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19730 if (HAVE_64BIT_SYMBOLS)
19731 return dwarf2_format_64bit_irix;
19733 return dwarf2_format_32bit;
19738 mips_dwarf2_addr_size (void)
19740 if (HAVE_64BIT_OBJECTS)
19746 /* Standard calling conventions leave the CFA at SP on entry. */
19748 mips_cfi_frame_initial_instructions (void)
19750 cfi_add_CFA_def_cfa_register (SP);
19754 tc_mips_regname_to_dw2regnum (char *regname)
19756 unsigned int regnum = -1;
19759 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))