1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error;
635 static int auto_align = 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset = -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset = -1;
647 static int mips_cpreturn_register = -1;
648 static int mips_gp_register = GP;
649 static int mips_gprel_offset = 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid = 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg = SP;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid = 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize = 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug = 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history[1 + MAX_NOPS];
692 /* Nop instructions used by emit_nop. */
693 static struct mips_cl_insn nop_insn;
694 static struct mips_cl_insn mips16_nop_insn;
695 static struct mips_cl_insn micromips_nop16_insn;
696 static struct mips_cl_insn micromips_nop32_insn;
698 /* The appropriate nop for the current mode. */
699 #define NOP_INSN (mips_opts.mips16 \
701 : (mips_opts.micromips \
702 ? (mips_opts.insn32 \
703 ? µmips_nop32_insn \
704 : µmips_nop16_insn) \
707 /* The size of NOP_INSN in bytes. */
708 #define NOP_INSN_SIZE ((mips_opts.mips16 \
709 || (mips_opts.micromips && !mips_opts.insn32)) \
712 /* If this is set, it points to a frag holding nop instructions which
713 were inserted before the start of a noreorder section. If those
714 nops turn out to be unnecessary, the size of the frag can be
716 static fragS *prev_nop_frag;
718 /* The number of nop instructions we created in prev_nop_frag. */
719 static int prev_nop_frag_holds;
721 /* The number of nop instructions that we know we need in
723 static int prev_nop_frag_required;
725 /* The number of instructions we've seen since prev_nop_frag. */
726 static int prev_nop_frag_since;
728 /* Relocations against symbols are sometimes done in two parts, with a HI
729 relocation and a LO relocation. Each relocation has only 16 bits of
730 space to store an addend. This means that in order for the linker to
731 handle carries correctly, it must be able to locate both the HI and
732 the LO relocation. This means that the relocations must appear in
733 order in the relocation table.
735 In order to implement this, we keep track of each unmatched HI
736 relocation. We then sort them so that they immediately precede the
737 corresponding LO relocation. */
742 struct mips_hi_fixup *next;
745 /* The section this fixup is in. */
749 /* The list of unmatched HI relocs. */
751 static struct mips_hi_fixup *mips_hi_fixup_list;
753 /* The frag containing the last explicit relocation operator.
754 Null if explicit relocations have not been used. */
756 static fragS *prev_reloc_op_frag;
758 /* Map mips16 register numbers to normal MIPS register numbers. */
760 static const unsigned int mips16_to_32_reg_map[] =
762 16, 17, 2, 3, 4, 5, 6, 7
765 /* Map microMIPS register numbers to normal MIPS register numbers. */
767 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
768 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
769 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
770 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
771 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
772 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
774 /* The microMIPS registers with type h. */
775 static const unsigned int micromips_to_32_reg_h_map1[] =
777 5, 5, 6, 4, 4, 4, 4, 4
779 static const unsigned int micromips_to_32_reg_h_map2[] =
781 6, 7, 7, 21, 22, 5, 6, 7
784 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
786 /* The microMIPS registers with type m. */
787 static const unsigned int micromips_to_32_reg_m_map[] =
789 0, 17, 2, 3, 16, 18, 19, 20
792 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
794 /* The microMIPS registers with type q. */
795 static const unsigned int micromips_to_32_reg_q_map[] =
797 0, 17, 2, 3, 4, 5, 6, 7
800 /* Classifies the kind of instructions we're interested in when
801 implementing -mfix-vr4120. */
802 enum fix_vr4120_class
810 NUM_FIX_VR4120_CLASSES
813 /* ...likewise -mfix-loongson2f-jump. */
814 static bfd_boolean mips_fix_loongson2f_jump;
816 /* ...likewise -mfix-loongson2f-nop. */
817 static bfd_boolean mips_fix_loongson2f_nop;
819 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
820 static bfd_boolean mips_fix_loongson2f;
822 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
823 there must be at least one other instruction between an instruction
824 of type X and an instruction of type Y. */
825 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
827 /* True if -mfix-vr4120 is in force. */
828 static int mips_fix_vr4120;
830 /* ...likewise -mfix-vr4130. */
831 static int mips_fix_vr4130;
833 /* ...likewise -mfix-24k. */
834 static int mips_fix_24k;
836 /* ...likewise -mfix-cn63xxp1 */
837 static bfd_boolean mips_fix_cn63xxp1;
839 /* We don't relax branches by default, since this causes us to expand
840 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
841 fail to compute the offset before expanding the macro to the most
842 efficient expansion. */
844 static int mips_relax_branch;
846 /* The expansion of many macros depends on the type of symbol that
847 they refer to. For example, when generating position-dependent code,
848 a macro that refers to a symbol may have two different expansions,
849 one which uses GP-relative addresses and one which uses absolute
850 addresses. When generating SVR4-style PIC, a macro may have
851 different expansions for local and global symbols.
853 We handle these situations by generating both sequences and putting
854 them in variant frags. In position-dependent code, the first sequence
855 will be the GP-relative one and the second sequence will be the
856 absolute one. In SVR4 PIC, the first sequence will be for global
857 symbols and the second will be for local symbols.
859 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
860 SECOND are the lengths of the two sequences in bytes. These fields
861 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
862 the subtype has the following flags:
865 Set if it has been decided that we should use the second
866 sequence instead of the first.
869 Set in the first variant frag if the macro's second implementation
870 is longer than its first. This refers to the macro as a whole,
871 not an individual relaxation.
874 Set in the first variant frag if the macro appeared in a .set nomacro
875 block and if one alternative requires a warning but the other does not.
878 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
881 RELAX_DELAY_SLOT_16BIT
882 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
885 RELAX_DELAY_SLOT_SIZE_FIRST
886 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
887 the macro is of the wrong size for the branch delay slot.
889 RELAX_DELAY_SLOT_SIZE_SECOND
890 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
891 the macro is of the wrong size for the branch delay slot.
893 The frag's "opcode" points to the first fixup for relaxable code.
895 Relaxable macros are generated using a sequence such as:
897 relax_start (SYMBOL);
898 ... generate first expansion ...
900 ... generate second expansion ...
903 The code and fixups for the unwanted alternative are discarded
904 by md_convert_frag. */
905 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
907 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
908 #define RELAX_SECOND(X) ((X) & 0xff)
909 #define RELAX_USE_SECOND 0x10000
910 #define RELAX_SECOND_LONGER 0x20000
911 #define RELAX_NOMACRO 0x40000
912 #define RELAX_DELAY_SLOT 0x80000
913 #define RELAX_DELAY_SLOT_16BIT 0x100000
914 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
915 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
917 /* Branch without likely bit. If label is out of range, we turn:
919 beq reg1, reg2, label
929 with the following opcode replacements:
936 bltzal <-> bgezal (with jal label instead of j label)
938 Even though keeping the delay slot instruction in the delay slot of
939 the branch would be more efficient, it would be very tricky to do
940 correctly, because we'd have to introduce a variable frag *after*
941 the delay slot instruction, and expand that instead. Let's do it
942 the easy way for now, even if the branch-not-taken case now costs
943 one additional instruction. Out-of-range branches are not supposed
944 to be common, anyway.
946 Branch likely. If label is out of range, we turn:
948 beql reg1, reg2, label
949 delay slot (annulled if branch not taken)
958 delay slot (executed only if branch taken)
961 It would be possible to generate a shorter sequence by losing the
962 likely bit, generating something like:
967 delay slot (executed only if branch taken)
979 bltzall -> bgezal (with jal label instead of j label)
980 bgezall -> bltzal (ditto)
983 but it's not clear that it would actually improve performance. */
984 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
988 | ((toofar) ? 0x20 : 0) \
989 | ((link) ? 0x40 : 0) \
990 | ((likely) ? 0x80 : 0) \
991 | ((uncond) ? 0x100 : 0)))
992 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
993 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
994 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
995 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
996 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
997 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
999 /* For mips16 code, we use an entirely different form of relaxation.
1000 mips16 supports two versions of most instructions which take
1001 immediate values: a small one which takes some small value, and a
1002 larger one which takes a 16 bit value. Since branches also follow
1003 this pattern, relaxing these values is required.
1005 We can assemble both mips16 and normal MIPS code in a single
1006 object. Therefore, we need to support this type of relaxation at
1007 the same time that we support the relaxation described above. We
1008 use the high bit of the subtype field to distinguish these cases.
1010 The information we store for this type of relaxation is the
1011 argument code found in the opcode file for this relocation, whether
1012 the user explicitly requested a small or extended form, and whether
1013 the relocation is in a jump or jal delay slot. That tells us the
1014 size of the value, and how it should be stored. We also store
1015 whether the fragment is considered to be extended or not. We also
1016 store whether this is known to be a branch to a different section,
1017 whether we have tried to relax this frag yet, and whether we have
1018 ever extended a PC relative fragment because of a shift count. */
1019 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1022 | ((small) ? 0x100 : 0) \
1023 | ((ext) ? 0x200 : 0) \
1024 | ((dslot) ? 0x400 : 0) \
1025 | ((jal_dslot) ? 0x800 : 0))
1026 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1027 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1028 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1029 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1030 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1031 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1032 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1033 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1034 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1035 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1036 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1037 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1039 /* For microMIPS code, we use relaxation similar to one we use for
1040 MIPS16 code. Some instructions that take immediate values support
1041 two encodings: a small one which takes some small value, and a
1042 larger one which takes a 16 bit value. As some branches also follow
1043 this pattern, relaxing these values is required.
1045 We can assemble both microMIPS and normal MIPS code in a single
1046 object. Therefore, we need to support this type of relaxation at
1047 the same time that we support the relaxation described above. We
1048 use one of the high bits of the subtype field to distinguish these
1051 The information we store for this type of relaxation is the argument
1052 code found in the opcode file for this relocation, the register
1053 selected as the assembler temporary, whether the branch is
1054 unconditional, whether it is compact, whether it stores the link
1055 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1056 branches to a sequence of instructions is enabled, and whether the
1057 displacement of a branch is too large to fit as an immediate argument
1058 of a 16-bit and a 32-bit branch, respectively. */
1059 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1060 relax32, toofar16, toofar32) \
1063 | (((at) & 0x1f) << 8) \
1064 | ((uncond) ? 0x2000 : 0) \
1065 | ((compact) ? 0x4000 : 0) \
1066 | ((link) ? 0x8000 : 0) \
1067 | ((relax32) ? 0x10000 : 0) \
1068 | ((toofar16) ? 0x20000 : 0) \
1069 | ((toofar32) ? 0x40000 : 0))
1070 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1071 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1072 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1073 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1074 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1075 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1076 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1078 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1079 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1080 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1081 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1082 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1083 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1085 /* Sign-extend 16-bit value X. */
1086 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1088 /* Is the given value a sign-extended 32-bit value? */
1089 #define IS_SEXT_32BIT_NUM(x) \
1090 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1091 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1093 /* Is the given value a sign-extended 16-bit value? */
1094 #define IS_SEXT_16BIT_NUM(x) \
1095 (((x) &~ (offsetT) 0x7fff) == 0 \
1096 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1098 /* Is the given value a sign-extended 12-bit value? */
1099 #define IS_SEXT_12BIT_NUM(x) \
1100 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1102 /* Is the given value a sign-extended 9-bit value? */
1103 #define IS_SEXT_9BIT_NUM(x) \
1104 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1106 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1107 #define IS_ZEXT_32BIT_NUM(x) \
1108 (((x) &~ (offsetT) 0xffffffff) == 0 \
1109 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1111 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1113 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1114 (((STRUCT) >> (SHIFT)) & (MASK))
1116 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1117 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1119 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1120 : EXTRACT_BITS ((INSN).insn_opcode, \
1121 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1122 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1123 EXTRACT_BITS ((INSN).insn_opcode, \
1124 MIPS16OP_MASK_##FIELD, \
1125 MIPS16OP_SH_##FIELD)
1127 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1128 #define MIPS16_EXTEND (0xf000U << 16)
1130 /* Whether or not we are emitting a branch-likely macro. */
1131 static bfd_boolean emit_branch_likely_macro = FALSE;
1133 /* Global variables used when generating relaxable macros. See the
1134 comment above RELAX_ENCODE for more details about how relaxation
1137 /* 0 if we're not emitting a relaxable macro.
1138 1 if we're emitting the first of the two relaxation alternatives.
1139 2 if we're emitting the second alternative. */
1142 /* The first relaxable fixup in the current frag. (In other words,
1143 the first fixup that refers to relaxable code.) */
1146 /* sizes[0] says how many bytes of the first alternative are stored in
1147 the current frag. Likewise sizes[1] for the second alternative. */
1148 unsigned int sizes[2];
1150 /* The symbol on which the choice of sequence depends. */
1154 /* Global variables used to decide whether a macro needs a warning. */
1156 /* True if the macro is in a branch delay slot. */
1157 bfd_boolean delay_slot_p;
1159 /* Set to the length in bytes required if the macro is in a delay slot
1160 that requires a specific length of instruction, otherwise zero. */
1161 unsigned int delay_slot_length;
1163 /* For relaxable macros, sizes[0] is the length of the first alternative
1164 in bytes and sizes[1] is the length of the second alternative.
1165 For non-relaxable macros, both elements give the length of the
1167 unsigned int sizes[2];
1169 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1170 instruction of the first alternative in bytes and first_insn_sizes[1]
1171 is the length of the first instruction of the second alternative.
1172 For non-relaxable macros, both elements give the length of the first
1173 instruction in bytes.
1175 Set to zero if we haven't yet seen the first instruction. */
1176 unsigned int first_insn_sizes[2];
1178 /* For relaxable macros, insns[0] is the number of instructions for the
1179 first alternative and insns[1] is the number of instructions for the
1182 For non-relaxable macros, both elements give the number of
1183 instructions for the macro. */
1184 unsigned int insns[2];
1186 /* The first variant frag for this macro. */
1188 } mips_macro_warning;
1190 /* Prototypes for static functions. */
1192 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1194 static void append_insn
1195 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1196 bfd_boolean expansionp);
1197 static void mips_no_prev_insn (void);
1198 static void macro_build (expressionS *, const char *, const char *, ...);
1199 static void mips16_macro_build
1200 (expressionS *, const char *, const char *, va_list *);
1201 static void load_register (int, expressionS *, int);
1202 static void macro_start (void);
1203 static void macro_end (void);
1204 static void macro (struct mips_cl_insn *ip, char *str);
1205 static void mips16_macro (struct mips_cl_insn * ip);
1206 static void mips_ip (char *str, struct mips_cl_insn * ip);
1207 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1208 static void mips16_immed
1209 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1210 unsigned int, unsigned long *);
1211 static size_t my_getSmallExpression
1212 (expressionS *, bfd_reloc_code_real_type *, char *);
1213 static void my_getExpression (expressionS *, char *);
1214 static void s_align (int);
1215 static void s_change_sec (int);
1216 static void s_change_section (int);
1217 static void s_cons (int);
1218 static void s_float_cons (int);
1219 static void s_mips_globl (int);
1220 static void s_option (int);
1221 static void s_mipsset (int);
1222 static void s_abicalls (int);
1223 static void s_cpload (int);
1224 static void s_cpsetup (int);
1225 static void s_cplocal (int);
1226 static void s_cprestore (int);
1227 static void s_cpreturn (int);
1228 static void s_dtprelword (int);
1229 static void s_dtpreldword (int);
1230 static void s_tprelword (int);
1231 static void s_tpreldword (int);
1232 static void s_gpvalue (int);
1233 static void s_gpword (int);
1234 static void s_gpdword (int);
1235 static void s_ehword (int);
1236 static void s_cpadd (int);
1237 static void s_insn (int);
1238 static void s_nan (int);
1239 static void md_obj_begin (void);
1240 static void md_obj_end (void);
1241 static void s_mips_ent (int);
1242 static void s_mips_end (int);
1243 static void s_mips_frame (int);
1244 static void s_mips_mask (int reg_type);
1245 static void s_mips_stab (int);
1246 static void s_mips_weakext (int);
1247 static void s_mips_file (int);
1248 static void s_mips_loc (int);
1249 static bfd_boolean pic_need_relax (symbolS *, asection *);
1250 static int relaxed_branch_length (fragS *, asection *, int);
1251 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1252 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1254 /* Table and functions used to map between CPU/ISA names, and
1255 ISA levels, and CPU numbers. */
1257 struct mips_cpu_info
1259 const char *name; /* CPU or ISA name. */
1260 int flags; /* MIPS_CPU_* flags. */
1261 int ase; /* Set of ASEs implemented by the CPU. */
1262 int isa; /* ISA level. */
1263 int cpu; /* CPU number (default CPU if ISA). */
1266 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1268 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1269 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1270 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1272 /* Command-line options. */
1273 const char *md_shortopts = "O::g::G:";
1277 OPTION_MARCH = OPTION_MD_BASE,
1301 OPTION_NO_SMARTMIPS,
1307 OPTION_NO_MICROMIPS,
1310 OPTION_COMPAT_ARCH_BASE,
1319 OPTION_M7000_HILO_FIX,
1320 OPTION_MNO_7000_HILO_FIX,
1323 OPTION_FIX_LOONGSON2F_JUMP,
1324 OPTION_NO_FIX_LOONGSON2F_JUMP,
1325 OPTION_FIX_LOONGSON2F_NOP,
1326 OPTION_NO_FIX_LOONGSON2F_NOP,
1328 OPTION_NO_FIX_VR4120,
1330 OPTION_NO_FIX_VR4130,
1331 OPTION_FIX_CN63XXP1,
1332 OPTION_NO_FIX_CN63XXP1,
1339 OPTION_CONSTRUCT_FLOATS,
1340 OPTION_NO_CONSTRUCT_FLOATS,
1343 OPTION_RELAX_BRANCH,
1344 OPTION_NO_RELAX_BRANCH,
1353 OPTION_SINGLE_FLOAT,
1354 OPTION_DOUBLE_FLOAT,
1367 OPTION_MVXWORKS_PIC,
1372 struct option md_longopts[] =
1374 /* Options which specify architecture. */
1375 {"march", required_argument, NULL, OPTION_MARCH},
1376 {"mtune", required_argument, NULL, OPTION_MTUNE},
1377 {"mips0", no_argument, NULL, OPTION_MIPS1},
1378 {"mips1", no_argument, NULL, OPTION_MIPS1},
1379 {"mips2", no_argument, NULL, OPTION_MIPS2},
1380 {"mips3", no_argument, NULL, OPTION_MIPS3},
1381 {"mips4", no_argument, NULL, OPTION_MIPS4},
1382 {"mips5", no_argument, NULL, OPTION_MIPS5},
1383 {"mips32", no_argument, NULL, OPTION_MIPS32},
1384 {"mips64", no_argument, NULL, OPTION_MIPS64},
1385 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1386 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1388 /* Options which specify Application Specific Extensions (ASEs). */
1389 {"mips16", no_argument, NULL, OPTION_MIPS16},
1390 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1391 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1392 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1393 {"mdmx", no_argument, NULL, OPTION_MDMX},
1394 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1395 {"mdsp", no_argument, NULL, OPTION_DSP},
1396 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1397 {"mmt", no_argument, NULL, OPTION_MT},
1398 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1399 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1400 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1401 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1402 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1403 {"meva", no_argument, NULL, OPTION_EVA},
1404 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1405 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1406 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1407 {"mmcu", no_argument, NULL, OPTION_MCU},
1408 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1409 {"mvirt", no_argument, NULL, OPTION_VIRT},
1410 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1412 /* Old-style architecture options. Don't add more of these. */
1413 {"m4650", no_argument, NULL, OPTION_M4650},
1414 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1415 {"m4010", no_argument, NULL, OPTION_M4010},
1416 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1417 {"m4100", no_argument, NULL, OPTION_M4100},
1418 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1419 {"m3900", no_argument, NULL, OPTION_M3900},
1420 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1422 /* Options which enable bug fixes. */
1423 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1424 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1425 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1426 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1427 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1428 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1429 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1430 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1431 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1432 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1433 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1434 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1435 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1436 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1437 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1439 /* Miscellaneous options. */
1440 {"trap", no_argument, NULL, OPTION_TRAP},
1441 {"no-break", no_argument, NULL, OPTION_TRAP},
1442 {"break", no_argument, NULL, OPTION_BREAK},
1443 {"no-trap", no_argument, NULL, OPTION_BREAK},
1444 {"EB", no_argument, NULL, OPTION_EB},
1445 {"EL", no_argument, NULL, OPTION_EL},
1446 {"mfp32", no_argument, NULL, OPTION_FP32},
1447 {"mgp32", no_argument, NULL, OPTION_GP32},
1448 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1449 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1450 {"mfp64", no_argument, NULL, OPTION_FP64},
1451 {"mgp64", no_argument, NULL, OPTION_GP64},
1452 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1453 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1454 {"minsn32", no_argument, NULL, OPTION_INSN32},
1455 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1456 {"mshared", no_argument, NULL, OPTION_MSHARED},
1457 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1458 {"msym32", no_argument, NULL, OPTION_MSYM32},
1459 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1460 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1461 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1462 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1463 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1465 /* Strictly speaking this next option is ELF specific,
1466 but we allow it for other ports as well in order to
1467 make testing easier. */
1468 {"32", no_argument, NULL, OPTION_32},
1470 /* ELF-specific options. */
1471 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1472 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1473 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1474 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1475 {"xgot", no_argument, NULL, OPTION_XGOT},
1476 {"mabi", required_argument, NULL, OPTION_MABI},
1477 {"n32", no_argument, NULL, OPTION_N32},
1478 {"64", no_argument, NULL, OPTION_64},
1479 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1480 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1481 {"mpdr", no_argument, NULL, OPTION_PDR},
1482 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1483 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1484 {"mnan", required_argument, NULL, OPTION_NAN},
1486 {NULL, no_argument, NULL, 0}
1488 size_t md_longopts_size = sizeof (md_longopts);
1490 /* Information about either an Application Specific Extension or an
1491 optional architecture feature that, for simplicity, we treat in the
1492 same way as an ASE. */
1495 /* The name of the ASE, used in both the command-line and .set options. */
1498 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1499 and 64-bit architectures, the flags here refer to the subset that
1500 is available on both. */
1503 /* The ASE_* flag used for instructions that are available on 64-bit
1504 architectures but that are not included in FLAGS. */
1505 unsigned int flags64;
1507 /* The command-line options that turn the ASE on and off. */
1511 /* The minimum required architecture revisions for MIPS32, MIPS64,
1512 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1515 int micromips32_rev;
1516 int micromips64_rev;
1519 /* A table of all supported ASEs. */
1520 static const struct mips_ase mips_ases[] = {
1521 { "dsp", ASE_DSP, ASE_DSP64,
1522 OPTION_DSP, OPTION_NO_DSP,
1525 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1526 OPTION_DSPR2, OPTION_NO_DSPR2,
1529 { "eva", ASE_EVA, 0,
1530 OPTION_EVA, OPTION_NO_EVA,
1533 { "mcu", ASE_MCU, 0,
1534 OPTION_MCU, OPTION_NO_MCU,
1537 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1538 { "mdmx", ASE_MDMX, 0,
1539 OPTION_MDMX, OPTION_NO_MDMX,
1542 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1543 { "mips3d", ASE_MIPS3D, 0,
1544 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1548 OPTION_MT, OPTION_NO_MT,
1551 { "smartmips", ASE_SMARTMIPS, 0,
1552 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1555 { "virt", ASE_VIRT, ASE_VIRT64,
1556 OPTION_VIRT, OPTION_NO_VIRT,
1560 /* The set of ASEs that require -mfp64. */
1561 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1563 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1564 static const unsigned int mips_ase_groups[] = {
1570 The following pseudo-ops from the Kane and Heinrich MIPS book
1571 should be defined here, but are currently unsupported: .alias,
1572 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1574 The following pseudo-ops from the Kane and Heinrich MIPS book are
1575 specific to the type of debugging information being generated, and
1576 should be defined by the object format: .aent, .begin, .bend,
1577 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1580 The following pseudo-ops from the Kane and Heinrich MIPS book are
1581 not MIPS CPU specific, but are also not specific to the object file
1582 format. This file is probably the best place to define them, but
1583 they are not currently supported: .asm0, .endr, .lab, .struct. */
1585 static const pseudo_typeS mips_pseudo_table[] =
1587 /* MIPS specific pseudo-ops. */
1588 {"option", s_option, 0},
1589 {"set", s_mipsset, 0},
1590 {"rdata", s_change_sec, 'r'},
1591 {"sdata", s_change_sec, 's'},
1592 {"livereg", s_ignore, 0},
1593 {"abicalls", s_abicalls, 0},
1594 {"cpload", s_cpload, 0},
1595 {"cpsetup", s_cpsetup, 0},
1596 {"cplocal", s_cplocal, 0},
1597 {"cprestore", s_cprestore, 0},
1598 {"cpreturn", s_cpreturn, 0},
1599 {"dtprelword", s_dtprelword, 0},
1600 {"dtpreldword", s_dtpreldword, 0},
1601 {"tprelword", s_tprelword, 0},
1602 {"tpreldword", s_tpreldword, 0},
1603 {"gpvalue", s_gpvalue, 0},
1604 {"gpword", s_gpword, 0},
1605 {"gpdword", s_gpdword, 0},
1606 {"ehword", s_ehword, 0},
1607 {"cpadd", s_cpadd, 0},
1608 {"insn", s_insn, 0},
1611 /* Relatively generic pseudo-ops that happen to be used on MIPS
1613 {"asciiz", stringer, 8 + 1},
1614 {"bss", s_change_sec, 'b'},
1616 {"half", s_cons, 1},
1617 {"dword", s_cons, 3},
1618 {"weakext", s_mips_weakext, 0},
1619 {"origin", s_org, 0},
1620 {"repeat", s_rept, 0},
1622 /* For MIPS this is non-standard, but we define it for consistency. */
1623 {"sbss", s_change_sec, 'B'},
1625 /* These pseudo-ops are defined in read.c, but must be overridden
1626 here for one reason or another. */
1627 {"align", s_align, 0},
1628 {"byte", s_cons, 0},
1629 {"data", s_change_sec, 'd'},
1630 {"double", s_float_cons, 'd'},
1631 {"float", s_float_cons, 'f'},
1632 {"globl", s_mips_globl, 0},
1633 {"global", s_mips_globl, 0},
1634 {"hword", s_cons, 1},
1636 {"long", s_cons, 2},
1637 {"octa", s_cons, 4},
1638 {"quad", s_cons, 3},
1639 {"section", s_change_section, 0},
1640 {"short", s_cons, 1},
1641 {"single", s_float_cons, 'f'},
1642 {"stabd", s_mips_stab, 'd'},
1643 {"stabn", s_mips_stab, 'n'},
1644 {"stabs", s_mips_stab, 's'},
1645 {"text", s_change_sec, 't'},
1646 {"word", s_cons, 2},
1648 { "extern", ecoff_directive_extern, 0},
1653 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1655 /* These pseudo-ops should be defined by the object file format.
1656 However, a.out doesn't support them, so we have versions here. */
1657 {"aent", s_mips_ent, 1},
1658 {"bgnb", s_ignore, 0},
1659 {"end", s_mips_end, 0},
1660 {"endb", s_ignore, 0},
1661 {"ent", s_mips_ent, 0},
1662 {"file", s_mips_file, 0},
1663 {"fmask", s_mips_mask, 'F'},
1664 {"frame", s_mips_frame, 0},
1665 {"loc", s_mips_loc, 0},
1666 {"mask", s_mips_mask, 'R'},
1667 {"verstamp", s_ignore, 0},
1671 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1672 purpose of the `.dc.a' internal pseudo-op. */
1675 mips_address_bytes (void)
1677 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1680 extern void pop_insert (const pseudo_typeS *);
1683 mips_pop_insert (void)
1685 pop_insert (mips_pseudo_table);
1686 if (! ECOFF_DEBUGGING)
1687 pop_insert (mips_nonecoff_pseudo_table);
1690 /* Symbols labelling the current insn. */
1692 struct insn_label_list
1694 struct insn_label_list *next;
1698 static struct insn_label_list *free_insn_labels;
1699 #define label_list tc_segment_info_data.labels
1701 static void mips_clear_insn_labels (void);
1702 static void mips_mark_labels (void);
1703 static void mips_compressed_mark_labels (void);
1706 mips_clear_insn_labels (void)
1708 register struct insn_label_list **pl;
1709 segment_info_type *si;
1713 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1716 si = seg_info (now_seg);
1717 *pl = si->label_list;
1718 si->label_list = NULL;
1722 /* Mark instruction labels in MIPS16/microMIPS mode. */
1725 mips_mark_labels (void)
1727 if (HAVE_CODE_COMPRESSION)
1728 mips_compressed_mark_labels ();
1731 static char *expr_end;
1733 /* Expressions which appear in macro instructions. These are set by
1734 mips_ip and read by macro. */
1736 static expressionS imm_expr;
1737 static expressionS imm2_expr;
1739 /* The relocatable field in an instruction and the relocs associated
1740 with it. These variables are used for instructions like LUI and
1741 JAL as well as true offsets. They are also used for address
1742 operands in macros. */
1744 static expressionS offset_expr;
1745 static bfd_reloc_code_real_type offset_reloc[3]
1746 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1748 /* This is set to the resulting size of the instruction to be produced
1749 by mips16_ip if an explicit extension is used or by mips_ip if an
1750 explicit size is supplied. */
1752 static unsigned int forced_insn_length;
1754 /* True if we are assembling an instruction. All dot symbols defined during
1755 this time should be treated as code labels. */
1757 static bfd_boolean mips_assembling_insn;
1759 /* The pdr segment for per procedure frame/regmask info. Not used for
1762 static segT pdr_seg;
1764 /* The default target format to use. */
1766 #if defined (TE_FreeBSD)
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1768 #elif defined (TE_TMIPS)
1769 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1771 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1775 mips_target_format (void)
1777 switch (OUTPUT_FLAVOR)
1779 case bfd_target_elf_flavour:
1781 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1782 return (target_big_endian
1783 ? "elf32-bigmips-vxworks"
1784 : "elf32-littlemips-vxworks");
1786 return (target_big_endian
1787 ? (HAVE_64BIT_OBJECTS
1788 ? ELF_TARGET ("elf64-", "big")
1790 ? ELF_TARGET ("elf32-n", "big")
1791 : ELF_TARGET ("elf32-", "big")))
1792 : (HAVE_64BIT_OBJECTS
1793 ? ELF_TARGET ("elf64-", "little")
1795 ? ELF_TARGET ("elf32-n", "little")
1796 : ELF_TARGET ("elf32-", "little"))));
1803 /* Return the ISA revision that is currently in use, or 0 if we are
1804 generating code for MIPS V or below. */
1809 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1812 /* microMIPS implies revision 2 or above. */
1813 if (mips_opts.micromips)
1816 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1822 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1825 mips_ase_mask (unsigned int flags)
1829 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1830 if (flags & mips_ase_groups[i])
1831 flags |= mips_ase_groups[i];
1835 /* Check whether the current ISA supports ASE. Issue a warning if
1839 mips_check_isa_supports_ase (const struct mips_ase *ase)
1843 static unsigned int warned_isa;
1844 static unsigned int warned_fp32;
1846 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1847 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1849 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1850 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1851 && (warned_isa & ase->flags) != ase->flags)
1853 warned_isa |= ase->flags;
1854 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1855 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1857 as_warn (_("The %d-bit %s architecture does not support the"
1858 " `%s' extension"), size, base, ase->name);
1860 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1861 ase->name, base, size, min_rev);
1863 if ((ase->flags & FP64_ASES)
1865 && (warned_fp32 & ase->flags) != ase->flags)
1867 warned_fp32 |= ase->flags;
1868 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1872 /* Check all enabled ASEs to see whether they are supported by the
1873 chosen architecture. */
1876 mips_check_isa_supports_ases (void)
1878 unsigned int i, mask;
1880 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1882 mask = mips_ase_mask (mips_ases[i].flags);
1883 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1884 mips_check_isa_supports_ase (&mips_ases[i]);
1888 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1889 that were affected. */
1892 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1896 mask = mips_ase_mask (ase->flags);
1897 mips_opts.ase &= ~mask;
1899 mips_opts.ase |= ase->flags;
1903 /* Return the ASE called NAME, or null if none. */
1905 static const struct mips_ase *
1906 mips_lookup_ase (const char *name)
1910 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1911 if (strcmp (name, mips_ases[i].name) == 0)
1912 return &mips_ases[i];
1916 /* Return the length of a microMIPS instruction in bytes. If bits of
1917 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1918 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1919 major opcode) will require further modifications to the opcode
1922 static inline unsigned int
1923 micromips_insn_length (const struct mips_opcode *mo)
1925 return (mo->mask >> 16) == 0 ? 2 : 4;
1928 /* Return the length of MIPS16 instruction OPCODE. */
1930 static inline unsigned int
1931 mips16_opcode_length (unsigned long opcode)
1933 return (opcode >> 16) == 0 ? 2 : 4;
1936 /* Return the length of instruction INSN. */
1938 static inline unsigned int
1939 insn_length (const struct mips_cl_insn *insn)
1941 if (mips_opts.micromips)
1942 return micromips_insn_length (insn->insn_mo);
1943 else if (mips_opts.mips16)
1944 return mips16_opcode_length (insn->insn_opcode);
1949 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1952 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1957 insn->insn_opcode = mo->match;
1960 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1961 insn->fixp[i] = NULL;
1962 insn->fixed_p = (mips_opts.noreorder > 0);
1963 insn->noreorder_p = (mips_opts.noreorder > 0);
1964 insn->mips16_absolute_jump_p = 0;
1965 insn->complete_p = 0;
1966 insn->cleared_p = 0;
1969 /* Install UVAL as the value of OPERAND in INSN. */
1972 insn_insert_operand (struct mips_cl_insn *insn,
1973 const struct mips_operand *operand, unsigned int uval)
1975 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
1978 /* Record the current MIPS16/microMIPS mode in now_seg. */
1981 mips_record_compressed_mode (void)
1983 segment_info_type *si;
1985 si = seg_info (now_seg);
1986 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1987 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1988 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1989 si->tc_segment_info_data.micromips = mips_opts.micromips;
1992 /* Read a standard MIPS instruction from BUF. */
1994 static unsigned long
1995 read_insn (char *buf)
1997 if (target_big_endian)
1998 return bfd_getb32 ((bfd_byte *) buf);
2000 return bfd_getl32 ((bfd_byte *) buf);
2003 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2007 write_insn (char *buf, unsigned int insn)
2009 md_number_to_chars (buf, insn, 4);
2013 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2014 has length LENGTH. */
2016 static unsigned long
2017 read_compressed_insn (char *buf, unsigned int length)
2023 for (i = 0; i < length; i += 2)
2026 if (target_big_endian)
2027 insn |= bfd_getb16 ((char *) buf);
2029 insn |= bfd_getl16 ((char *) buf);
2035 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2036 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2039 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2043 for (i = 0; i < length; i += 2)
2044 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2045 return buf + length;
2048 /* Install INSN at the location specified by its "frag" and "where" fields. */
2051 install_insn (const struct mips_cl_insn *insn)
2053 char *f = insn->frag->fr_literal + insn->where;
2054 if (HAVE_CODE_COMPRESSION)
2055 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2057 write_insn (f, insn->insn_opcode);
2058 mips_record_compressed_mode ();
2061 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2062 and install the opcode in the new location. */
2065 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2070 insn->where = where;
2071 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2072 if (insn->fixp[i] != NULL)
2074 insn->fixp[i]->fx_frag = frag;
2075 insn->fixp[i]->fx_where = where;
2077 install_insn (insn);
2080 /* Add INSN to the end of the output. */
2083 add_fixed_insn (struct mips_cl_insn *insn)
2085 char *f = frag_more (insn_length (insn));
2086 move_insn (insn, frag_now, f - frag_now->fr_literal);
2089 /* Start a variant frag and move INSN to the start of the variant part,
2090 marking it as fixed. The other arguments are as for frag_var. */
2093 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2094 relax_substateT subtype, symbolS *symbol, offsetT offset)
2096 frag_grow (max_chars);
2097 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2099 frag_var (rs_machine_dependent, max_chars, var,
2100 subtype, symbol, offset, NULL);
2103 /* Insert N copies of INSN into the history buffer, starting at
2104 position FIRST. Neither FIRST nor N need to be clipped. */
2107 insert_into_history (unsigned int first, unsigned int n,
2108 const struct mips_cl_insn *insn)
2110 if (mips_relax.sequence != 2)
2114 for (i = ARRAY_SIZE (history); i-- > first;)
2116 history[i] = history[i - n];
2122 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2123 the idea is to make it obvious at a glance that each errata is
2127 init_vr4120_conflicts (void)
2129 #define CONFLICT(FIRST, SECOND) \
2130 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2132 /* Errata 21 - [D]DIV[U] after [D]MACC */
2133 CONFLICT (MACC, DIV);
2134 CONFLICT (DMACC, DIV);
2136 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2137 CONFLICT (DMULT, DMULT);
2138 CONFLICT (DMULT, DMACC);
2139 CONFLICT (DMACC, DMULT);
2140 CONFLICT (DMACC, DMACC);
2142 /* Errata 24 - MT{LO,HI} after [D]MACC */
2143 CONFLICT (MACC, MTHILO);
2144 CONFLICT (DMACC, MTHILO);
2146 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2147 instruction is executed immediately after a MACC or DMACC
2148 instruction, the result of [either instruction] is incorrect." */
2149 CONFLICT (MACC, MULT);
2150 CONFLICT (MACC, DMULT);
2151 CONFLICT (DMACC, MULT);
2152 CONFLICT (DMACC, DMULT);
2154 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2155 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2156 DDIV or DDIVU instruction, the result of the MACC or
2157 DMACC instruction is incorrect.". */
2158 CONFLICT (DMULT, MACC);
2159 CONFLICT (DMULT, DMACC);
2160 CONFLICT (DIV, MACC);
2161 CONFLICT (DIV, DMACC);
2171 #define RTYPE_MASK 0x1ff00
2172 #define RTYPE_NUM 0x00100
2173 #define RTYPE_FPU 0x00200
2174 #define RTYPE_FCC 0x00400
2175 #define RTYPE_VEC 0x00800
2176 #define RTYPE_GP 0x01000
2177 #define RTYPE_CP0 0x02000
2178 #define RTYPE_PC 0x04000
2179 #define RTYPE_ACC 0x08000
2180 #define RTYPE_CCC 0x10000
2181 #define RNUM_MASK 0x000ff
2182 #define RWARN 0x80000
2184 #define GENERIC_REGISTER_NUMBERS \
2185 {"$0", RTYPE_NUM | 0}, \
2186 {"$1", RTYPE_NUM | 1}, \
2187 {"$2", RTYPE_NUM | 2}, \
2188 {"$3", RTYPE_NUM | 3}, \
2189 {"$4", RTYPE_NUM | 4}, \
2190 {"$5", RTYPE_NUM | 5}, \
2191 {"$6", RTYPE_NUM | 6}, \
2192 {"$7", RTYPE_NUM | 7}, \
2193 {"$8", RTYPE_NUM | 8}, \
2194 {"$9", RTYPE_NUM | 9}, \
2195 {"$10", RTYPE_NUM | 10}, \
2196 {"$11", RTYPE_NUM | 11}, \
2197 {"$12", RTYPE_NUM | 12}, \
2198 {"$13", RTYPE_NUM | 13}, \
2199 {"$14", RTYPE_NUM | 14}, \
2200 {"$15", RTYPE_NUM | 15}, \
2201 {"$16", RTYPE_NUM | 16}, \
2202 {"$17", RTYPE_NUM | 17}, \
2203 {"$18", RTYPE_NUM | 18}, \
2204 {"$19", RTYPE_NUM | 19}, \
2205 {"$20", RTYPE_NUM | 20}, \
2206 {"$21", RTYPE_NUM | 21}, \
2207 {"$22", RTYPE_NUM | 22}, \
2208 {"$23", RTYPE_NUM | 23}, \
2209 {"$24", RTYPE_NUM | 24}, \
2210 {"$25", RTYPE_NUM | 25}, \
2211 {"$26", RTYPE_NUM | 26}, \
2212 {"$27", RTYPE_NUM | 27}, \
2213 {"$28", RTYPE_NUM | 28}, \
2214 {"$29", RTYPE_NUM | 29}, \
2215 {"$30", RTYPE_NUM | 30}, \
2216 {"$31", RTYPE_NUM | 31}
2218 #define FPU_REGISTER_NAMES \
2219 {"$f0", RTYPE_FPU | 0}, \
2220 {"$f1", RTYPE_FPU | 1}, \
2221 {"$f2", RTYPE_FPU | 2}, \
2222 {"$f3", RTYPE_FPU | 3}, \
2223 {"$f4", RTYPE_FPU | 4}, \
2224 {"$f5", RTYPE_FPU | 5}, \
2225 {"$f6", RTYPE_FPU | 6}, \
2226 {"$f7", RTYPE_FPU | 7}, \
2227 {"$f8", RTYPE_FPU | 8}, \
2228 {"$f9", RTYPE_FPU | 9}, \
2229 {"$f10", RTYPE_FPU | 10}, \
2230 {"$f11", RTYPE_FPU | 11}, \
2231 {"$f12", RTYPE_FPU | 12}, \
2232 {"$f13", RTYPE_FPU | 13}, \
2233 {"$f14", RTYPE_FPU | 14}, \
2234 {"$f15", RTYPE_FPU | 15}, \
2235 {"$f16", RTYPE_FPU | 16}, \
2236 {"$f17", RTYPE_FPU | 17}, \
2237 {"$f18", RTYPE_FPU | 18}, \
2238 {"$f19", RTYPE_FPU | 19}, \
2239 {"$f20", RTYPE_FPU | 20}, \
2240 {"$f21", RTYPE_FPU | 21}, \
2241 {"$f22", RTYPE_FPU | 22}, \
2242 {"$f23", RTYPE_FPU | 23}, \
2243 {"$f24", RTYPE_FPU | 24}, \
2244 {"$f25", RTYPE_FPU | 25}, \
2245 {"$f26", RTYPE_FPU | 26}, \
2246 {"$f27", RTYPE_FPU | 27}, \
2247 {"$f28", RTYPE_FPU | 28}, \
2248 {"$f29", RTYPE_FPU | 29}, \
2249 {"$f30", RTYPE_FPU | 30}, \
2250 {"$f31", RTYPE_FPU | 31}
2252 #define FPU_CONDITION_CODE_NAMES \
2253 {"$fcc0", RTYPE_FCC | 0}, \
2254 {"$fcc1", RTYPE_FCC | 1}, \
2255 {"$fcc2", RTYPE_FCC | 2}, \
2256 {"$fcc3", RTYPE_FCC | 3}, \
2257 {"$fcc4", RTYPE_FCC | 4}, \
2258 {"$fcc5", RTYPE_FCC | 5}, \
2259 {"$fcc6", RTYPE_FCC | 6}, \
2260 {"$fcc7", RTYPE_FCC | 7}
2262 #define COPROC_CONDITION_CODE_NAMES \
2263 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2264 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2265 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2266 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2267 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2268 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2269 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2270 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2272 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2273 {"$a4", RTYPE_GP | 8}, \
2274 {"$a5", RTYPE_GP | 9}, \
2275 {"$a6", RTYPE_GP | 10}, \
2276 {"$a7", RTYPE_GP | 11}, \
2277 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2278 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2279 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2280 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2281 {"$t0", RTYPE_GP | 12}, \
2282 {"$t1", RTYPE_GP | 13}, \
2283 {"$t2", RTYPE_GP | 14}, \
2284 {"$t3", RTYPE_GP | 15}
2286 #define O32_SYMBOLIC_REGISTER_NAMES \
2287 {"$t0", RTYPE_GP | 8}, \
2288 {"$t1", RTYPE_GP | 9}, \
2289 {"$t2", RTYPE_GP | 10}, \
2290 {"$t3", RTYPE_GP | 11}, \
2291 {"$t4", RTYPE_GP | 12}, \
2292 {"$t5", RTYPE_GP | 13}, \
2293 {"$t6", RTYPE_GP | 14}, \
2294 {"$t7", RTYPE_GP | 15}, \
2295 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2296 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2297 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2298 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2300 /* Remaining symbolic register names */
2301 #define SYMBOLIC_REGISTER_NAMES \
2302 {"$zero", RTYPE_GP | 0}, \
2303 {"$at", RTYPE_GP | 1}, \
2304 {"$AT", RTYPE_GP | 1}, \
2305 {"$v0", RTYPE_GP | 2}, \
2306 {"$v1", RTYPE_GP | 3}, \
2307 {"$a0", RTYPE_GP | 4}, \
2308 {"$a1", RTYPE_GP | 5}, \
2309 {"$a2", RTYPE_GP | 6}, \
2310 {"$a3", RTYPE_GP | 7}, \
2311 {"$s0", RTYPE_GP | 16}, \
2312 {"$s1", RTYPE_GP | 17}, \
2313 {"$s2", RTYPE_GP | 18}, \
2314 {"$s3", RTYPE_GP | 19}, \
2315 {"$s4", RTYPE_GP | 20}, \
2316 {"$s5", RTYPE_GP | 21}, \
2317 {"$s6", RTYPE_GP | 22}, \
2318 {"$s7", RTYPE_GP | 23}, \
2319 {"$t8", RTYPE_GP | 24}, \
2320 {"$t9", RTYPE_GP | 25}, \
2321 {"$k0", RTYPE_GP | 26}, \
2322 {"$kt0", RTYPE_GP | 26}, \
2323 {"$k1", RTYPE_GP | 27}, \
2324 {"$kt1", RTYPE_GP | 27}, \
2325 {"$gp", RTYPE_GP | 28}, \
2326 {"$sp", RTYPE_GP | 29}, \
2327 {"$s8", RTYPE_GP | 30}, \
2328 {"$fp", RTYPE_GP | 30}, \
2329 {"$ra", RTYPE_GP | 31}
2331 #define MIPS16_SPECIAL_REGISTER_NAMES \
2332 {"$pc", RTYPE_PC | 0}
2334 #define MDMX_VECTOR_REGISTER_NAMES \
2335 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2336 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2337 {"$v2", RTYPE_VEC | 2}, \
2338 {"$v3", RTYPE_VEC | 3}, \
2339 {"$v4", RTYPE_VEC | 4}, \
2340 {"$v5", RTYPE_VEC | 5}, \
2341 {"$v6", RTYPE_VEC | 6}, \
2342 {"$v7", RTYPE_VEC | 7}, \
2343 {"$v8", RTYPE_VEC | 8}, \
2344 {"$v9", RTYPE_VEC | 9}, \
2345 {"$v10", RTYPE_VEC | 10}, \
2346 {"$v11", RTYPE_VEC | 11}, \
2347 {"$v12", RTYPE_VEC | 12}, \
2348 {"$v13", RTYPE_VEC | 13}, \
2349 {"$v14", RTYPE_VEC | 14}, \
2350 {"$v15", RTYPE_VEC | 15}, \
2351 {"$v16", RTYPE_VEC | 16}, \
2352 {"$v17", RTYPE_VEC | 17}, \
2353 {"$v18", RTYPE_VEC | 18}, \
2354 {"$v19", RTYPE_VEC | 19}, \
2355 {"$v20", RTYPE_VEC | 20}, \
2356 {"$v21", RTYPE_VEC | 21}, \
2357 {"$v22", RTYPE_VEC | 22}, \
2358 {"$v23", RTYPE_VEC | 23}, \
2359 {"$v24", RTYPE_VEC | 24}, \
2360 {"$v25", RTYPE_VEC | 25}, \
2361 {"$v26", RTYPE_VEC | 26}, \
2362 {"$v27", RTYPE_VEC | 27}, \
2363 {"$v28", RTYPE_VEC | 28}, \
2364 {"$v29", RTYPE_VEC | 29}, \
2365 {"$v30", RTYPE_VEC | 30}, \
2366 {"$v31", RTYPE_VEC | 31}
2368 #define MIPS_DSP_ACCUMULATOR_NAMES \
2369 {"$ac0", RTYPE_ACC | 0}, \
2370 {"$ac1", RTYPE_ACC | 1}, \
2371 {"$ac2", RTYPE_ACC | 2}, \
2372 {"$ac3", RTYPE_ACC | 3}
2374 static const struct regname reg_names[] = {
2375 GENERIC_REGISTER_NUMBERS,
2377 FPU_CONDITION_CODE_NAMES,
2378 COPROC_CONDITION_CODE_NAMES,
2380 /* The $txx registers depends on the abi,
2381 these will be added later into the symbol table from
2382 one of the tables below once mips_abi is set after
2383 parsing of arguments from the command line. */
2384 SYMBOLIC_REGISTER_NAMES,
2386 MIPS16_SPECIAL_REGISTER_NAMES,
2387 MDMX_VECTOR_REGISTER_NAMES,
2388 MIPS_DSP_ACCUMULATOR_NAMES,
2392 static const struct regname reg_names_o32[] = {
2393 O32_SYMBOLIC_REGISTER_NAMES,
2397 static const struct regname reg_names_n32n64[] = {
2398 N32N64_SYMBOLIC_REGISTER_NAMES,
2402 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2403 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2404 of these register symbols, return the associated vector register,
2405 otherwise return SYMVAL itself. */
2408 mips_prefer_vec_regno (unsigned int symval)
2410 if ((symval & -2) == (RTYPE_GP | 2))
2411 return RTYPE_VEC | (symval & 1);
2415 /* Return true if the string at *SPTR is a valid register name. If so,
2416 move *SPTR past the register and store the register's symbol value
2417 in *SYMVAL. This symbol value includes the register number
2418 (RNUM_MASK) and register type (RTYPE_MASK). */
2421 mips_parse_register (char **sptr, unsigned int *symval)
2427 /* Find end of name. */
2429 if (is_name_beginner (*e))
2431 while (is_part_of_name (*e))
2434 /* Terminate name. */
2438 /* Look up the name. */
2439 symbol = symbol_find (s);
2442 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2446 *symval = S_GET_VALUE (symbol);
2450 /* Check if SPTR points at a valid register specifier according to TYPES.
2451 If so, then return 1, advance S to consume the specifier and store
2452 the register's number in REGNOP, otherwise return 0. */
2455 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2459 if (mips_parse_register (s, ®no))
2461 if (types & RTYPE_VEC)
2462 regno = mips_prefer_vec_regno (regno);
2471 as_warn (_("Unrecognized register name `%s'"), *s);
2476 return regno <= RNUM_MASK;
2479 /* Token types for parsed operand lists. */
2480 enum mips_operand_token_type {
2481 /* A plain register, e.g. $f2. */
2484 /* An element of a vector, e.g. $v0[1]. */
2487 /* A continuous range of registers, e.g. $s0-$s4. */
2490 /* A (possibly relocated) expression. */
2493 /* A floating-point value. */
2496 /* A single character. This can be '(', ')' or ',', but '(' only appears
2500 /* The end of the operand list. */
2504 /* A parsed operand token. */
2505 struct mips_operand_token
2507 /* The type of token. */
2508 enum mips_operand_token_type type;
2511 /* The register symbol value for an OT_REG. */
2514 /* The register symbol value and index for an OT_REG_ELEMENT. */
2520 /* The two register symbol values involved in an OT_REG_RANGE. */
2522 unsigned int regno1;
2523 unsigned int regno2;
2526 /* The value of an OT_INTEGER. The value is represented as an
2527 expression and the relocation operators that were applied to
2528 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2529 relocation operators were used. */
2532 bfd_reloc_code_real_type relocs[3];
2535 /* The binary data for an OT_FLOAT constant, and the number of bytes
2538 unsigned char data[8];
2542 /* The character represented by an OT_CHAR. */
2547 /* An obstack used to construct lists of mips_operand_tokens. */
2548 static struct obstack mips_operand_tokens;
2550 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2553 mips_add_token (struct mips_operand_token *token,
2554 enum mips_operand_token_type type)
2557 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2560 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2561 and OT_REG tokens for them if so, and return a pointer to the first
2562 unconsumed character. Return null otherwise. */
2565 mips_parse_base_start (char *s)
2567 struct mips_operand_token token;
2574 SKIP_SPACE_TABS (s);
2575 if (!mips_parse_register (&s, ®no))
2579 mips_add_token (&token, OT_CHAR);
2581 token.u.regno = regno;
2582 mips_add_token (&token, OT_REG);
2587 /* Parse one or more tokens from S. Return a pointer to the first
2588 unconsumed character on success. Return null if an error was found
2589 and store the error text in insn_error. FLOAT_FORMAT is as for
2590 mips_parse_arguments. */
2593 mips_parse_argument_token (char *s, char float_format)
2595 char *end, *save_in, *err;
2596 unsigned int regno1, regno2;
2597 struct mips_operand_token token;
2599 /* First look for "($reg", since we want to treat that as an
2600 OT_CHAR and OT_REG rather than an expression. */
2601 end = mips_parse_base_start (s);
2605 /* Handle other characters that end up as OT_CHARs. */
2606 if (*s == ')' || *s == ',')
2609 mips_add_token (&token, OT_CHAR);
2614 /* Handle tokens that start with a register. */
2615 if (mips_parse_register (&s, ®no1))
2617 SKIP_SPACE_TABS (s);
2620 /* A register range. */
2622 SKIP_SPACE_TABS (s);
2623 if (!mips_parse_register (&s, ®no2))
2625 insn_error = _("Invalid register range");
2629 token.u.reg_range.regno1 = regno1;
2630 token.u.reg_range.regno2 = regno2;
2631 mips_add_token (&token, OT_REG_RANGE);
2636 /* A vector element. */
2637 expressionS element;
2640 SKIP_SPACE_TABS (s);
2641 my_getExpression (&element, s);
2642 if (element.X_op != O_constant)
2644 insn_error = _("Vector element must be constant");
2648 SKIP_SPACE_TABS (s);
2651 insn_error = _("Missing `]'");
2656 token.u.reg_element.regno = regno1;
2657 token.u.reg_element.index = element.X_add_number;
2658 mips_add_token (&token, OT_REG_ELEMENT);
2662 /* Looks like just a plain register. */
2663 token.u.regno = regno1;
2664 mips_add_token (&token, OT_REG);
2670 /* First try to treat expressions as floats. */
2671 save_in = input_line_pointer;
2672 input_line_pointer = s;
2673 err = md_atof (float_format, (char *) token.u.flt.data,
2674 &token.u.flt.length);
2675 end = input_line_pointer;
2676 input_line_pointer = save_in;
2684 mips_add_token (&token, OT_FLOAT);
2689 /* Treat everything else as an integer expression. */
2690 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
2691 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
2692 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
2693 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
2695 mips_add_token (&token, OT_INTEGER);
2699 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2700 if expressions should be treated as 32-bit floating-point constants,
2701 'd' if they should be treated as 64-bit floating-point constants,
2702 or 0 if they should be treated as integer expressions (the usual case).
2704 Return a list of tokens on success, otherwise return 0. The caller
2705 must obstack_free the list after use. */
2707 static struct mips_operand_token *
2708 mips_parse_arguments (char *s, char float_format)
2710 struct mips_operand_token token;
2712 SKIP_SPACE_TABS (s);
2715 s = mips_parse_argument_token (s, float_format);
2718 obstack_free (&mips_operand_tokens,
2719 obstack_finish (&mips_operand_tokens));
2722 SKIP_SPACE_TABS (s);
2724 mips_add_token (&token, OT_END);
2725 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
2728 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2729 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2732 is_opcode_valid (const struct mips_opcode *mo)
2734 int isa = mips_opts.isa;
2735 int ase = mips_opts.ase;
2739 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2740 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2741 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2742 ase |= mips_ases[i].flags64;
2744 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2747 /* Check whether the instruction or macro requires single-precision or
2748 double-precision floating-point support. Note that this information is
2749 stored differently in the opcode table for insns and macros. */
2750 if (mo->pinfo == INSN_MACRO)
2752 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2753 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2757 fp_s = mo->pinfo & FP_S;
2758 fp_d = mo->pinfo & FP_D;
2761 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2764 if (fp_s && mips_opts.soft_float)
2770 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2771 selected ISA and architecture. */
2774 is_opcode_valid_16 (const struct mips_opcode *mo)
2776 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2779 /* Return TRUE if the size of the microMIPS opcode MO matches one
2780 explicitly requested. Always TRUE in the standard MIPS mode. */
2783 is_size_valid (const struct mips_opcode *mo)
2785 if (!mips_opts.micromips)
2788 if (mips_opts.insn32)
2790 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2792 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2795 if (!forced_insn_length)
2797 if (mo->pinfo == INSN_MACRO)
2799 return forced_insn_length == micromips_insn_length (mo);
2802 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2803 of the preceding instruction. Always TRUE in the standard MIPS mode.
2805 We don't accept macros in 16-bit delay slots to avoid a case where
2806 a macro expansion fails because it relies on a preceding 32-bit real
2807 instruction to have matched and does not handle the operands correctly.
2808 The only macros that may expand to 16-bit instructions are JAL that
2809 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2810 and BGT (that likewise cannot be placed in a delay slot) that decay to
2811 a NOP. In all these cases the macros precede any corresponding real
2812 instruction definitions in the opcode table, so they will match in the
2813 second pass where the size of the delay slot is ignored and therefore
2814 produce correct code. */
2817 is_delay_slot_valid (const struct mips_opcode *mo)
2819 if (!mips_opts.micromips)
2822 if (mo->pinfo == INSN_MACRO)
2823 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2824 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2825 && micromips_insn_length (mo) != 4)
2827 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2828 && micromips_insn_length (mo) != 2)
2834 /* For consistency checking, verify that all bits of OPCODE are
2835 specified either by the match/mask part of the instruction
2836 definition, or by the operand list. INSN_BITS says which
2837 bits of the instruction are significant and DECODE_OPERAND
2838 provides the mips_operand description of each operand. */
2841 validate_mips_insn (const struct mips_opcode *opcode,
2842 unsigned long insn_bits,
2843 const struct mips_operand *(*decode_operand) (const char *))
2846 unsigned long used_bits, doubled, undefined;
2847 const struct mips_operand *operand;
2849 if ((opcode->mask & opcode->match) != opcode->match)
2851 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2852 opcode->name, opcode->args);
2856 for (s = opcode->args; *s; ++s)
2865 operand = decode_operand (s);
2868 as_bad (_("internal: unknown operand type: %s %s"),
2869 opcode->name, opcode->args);
2872 used_bits |= ((1 << operand->size) - 1) << operand->lsb;
2873 if (operand->type == OP_MDMX_IMM_REG)
2874 /* Bit 5 is the format selector (OB vs QH). The opcode table
2875 has separate entries for each format. */
2876 used_bits &= ~(1 << (operand->lsb + 5));
2877 /* Skip prefix characters. */
2878 if (*s == '+' || *s == 'm')
2882 doubled = used_bits & opcode->mask & insn_bits;
2885 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2886 " %s %s"), doubled, opcode->name, opcode->args);
2889 used_bits |= opcode->mask;
2890 undefined = ~used_bits & insn_bits;
2893 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2894 undefined, opcode->name, opcode->args);
2897 used_bits &= ~insn_bits;
2900 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2901 used_bits, opcode->name, opcode->args);
2907 /* The microMIPS version of validate_mips_insn. */
2910 validate_micromips_insn (const struct mips_opcode *opc)
2912 unsigned long insn_bits;
2913 unsigned long major;
2914 unsigned int length;
2916 length = micromips_insn_length (opc);
2917 if (length != 2 && length != 4)
2919 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2920 "%s %s"), length, opc->name, opc->args);
2923 major = opc->match >> (10 + 8 * (length - 2));
2924 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
2925 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
2927 as_bad (_("Internal error: bad microMIPS opcode "
2928 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
2932 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2933 insn_bits = 1 << 4 * length;
2934 insn_bits <<= 4 * length;
2936 return validate_mips_insn (opc, insn_bits, decode_micromips_operand);
2939 /* This function is called once, at assembler startup time. It should set up
2940 all the tables, etc. that the MD part of the assembler will need. */
2945 const char *retval = NULL;
2949 if (mips_pic != NO_PIC)
2951 if (g_switch_seen && g_switch_value != 0)
2952 as_bad (_("-G may not be used in position-independent code"));
2956 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2957 as_warn (_("Could not set architecture and machine"));
2959 op_hash = hash_new ();
2961 for (i = 0; i < NUMOPCODES;)
2963 const char *name = mips_opcodes[i].name;
2965 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2968 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2969 mips_opcodes[i].name, retval);
2970 /* Probably a memory allocation problem? Give up now. */
2971 as_fatal (_("Broken assembler. No assembly attempted."));
2975 if (mips_opcodes[i].pinfo != INSN_MACRO)
2977 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
2978 decode_mips_operand))
2980 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2982 create_insn (&nop_insn, mips_opcodes + i);
2983 if (mips_fix_loongson2f_nop)
2984 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2985 nop_insn.fixed_p = 1;
2990 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2993 mips16_op_hash = hash_new ();
2996 while (i < bfd_mips16_num_opcodes)
2998 const char *name = mips16_opcodes[i].name;
3000 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3002 as_fatal (_("internal: can't hash `%s': %s"),
3003 mips16_opcodes[i].name, retval);
3006 if (mips16_opcodes[i].pinfo != INSN_MACRO
3007 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
3008 != mips16_opcodes[i].match))
3010 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
3011 mips16_opcodes[i].name, mips16_opcodes[i].args);
3014 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3016 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3017 mips16_nop_insn.fixed_p = 1;
3021 while (i < bfd_mips16_num_opcodes
3022 && strcmp (mips16_opcodes[i].name, name) == 0);
3025 micromips_op_hash = hash_new ();
3028 while (i < bfd_micromips_num_opcodes)
3030 const char *name = micromips_opcodes[i].name;
3032 retval = hash_insert (micromips_op_hash, name,
3033 (void *) µmips_opcodes[i]);
3035 as_fatal (_("internal: can't hash `%s': %s"),
3036 micromips_opcodes[i].name, retval);
3038 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3040 struct mips_cl_insn *micromips_nop_insn;
3042 if (!validate_micromips_insn (µmips_opcodes[i]))
3045 if (micromips_insn_length (micromips_opcodes + i) == 2)
3046 micromips_nop_insn = µmips_nop16_insn;
3047 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3048 micromips_nop_insn = µmips_nop32_insn;
3052 if (micromips_nop_insn->insn_mo == NULL
3053 && strcmp (name, "nop") == 0)
3055 create_insn (micromips_nop_insn, micromips_opcodes + i);
3056 micromips_nop_insn->fixed_p = 1;
3059 while (++i < bfd_micromips_num_opcodes
3060 && strcmp (micromips_opcodes[i].name, name) == 0);
3064 as_fatal (_("Broken assembler. No assembly attempted."));
3066 /* We add all the general register names to the symbol table. This
3067 helps us detect invalid uses of them. */
3068 for (i = 0; reg_names[i].name; i++)
3069 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3070 reg_names[i].num, /* & RNUM_MASK, */
3071 &zero_address_frag));
3073 for (i = 0; reg_names_n32n64[i].name; i++)
3074 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3075 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3076 &zero_address_frag));
3078 for (i = 0; reg_names_o32[i].name; i++)
3079 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3080 reg_names_o32[i].num, /* & RNUM_MASK, */
3081 &zero_address_frag));
3083 obstack_init (&mips_operand_tokens);
3085 mips_no_prev_insn ();
3088 mips_cprmask[0] = 0;
3089 mips_cprmask[1] = 0;
3090 mips_cprmask[2] = 0;
3091 mips_cprmask[3] = 0;
3093 /* set the default alignment for the text section (2**2) */
3094 record_alignment (text_section, 2);
3096 bfd_set_gp_size (stdoutput, g_switch_value);
3098 /* On a native system other than VxWorks, sections must be aligned
3099 to 16 byte boundaries. When configured for an embedded ELF
3100 target, we don't bother. */
3101 if (strncmp (TARGET_OS, "elf", 3) != 0
3102 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3104 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3105 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3106 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3109 /* Create a .reginfo section for register masks and a .mdebug
3110 section for debugging information. */
3118 subseg = now_subseg;
3120 /* The ABI says this section should be loaded so that the
3121 running program can access it. However, we don't load it
3122 if we are configured for an embedded target */
3123 flags = SEC_READONLY | SEC_DATA;
3124 if (strncmp (TARGET_OS, "elf", 3) != 0)
3125 flags |= SEC_ALLOC | SEC_LOAD;
3127 if (mips_abi != N64_ABI)
3129 sec = subseg_new (".reginfo", (subsegT) 0);
3131 bfd_set_section_flags (stdoutput, sec, flags);
3132 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3134 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3138 /* The 64-bit ABI uses a .MIPS.options section rather than
3139 .reginfo section. */
3140 sec = subseg_new (".MIPS.options", (subsegT) 0);
3141 bfd_set_section_flags (stdoutput, sec, flags);
3142 bfd_set_section_alignment (stdoutput, sec, 3);
3144 /* Set up the option header. */
3146 Elf_Internal_Options opthdr;
3149 opthdr.kind = ODK_REGINFO;
3150 opthdr.size = (sizeof (Elf_External_Options)
3151 + sizeof (Elf64_External_RegInfo));
3154 f = frag_more (sizeof (Elf_External_Options));
3155 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3156 (Elf_External_Options *) f);
3158 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3162 if (ECOFF_DEBUGGING)
3164 sec = subseg_new (".mdebug", (subsegT) 0);
3165 (void) bfd_set_section_flags (stdoutput, sec,
3166 SEC_HAS_CONTENTS | SEC_READONLY);
3167 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3169 else if (mips_flag_pdr)
3171 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3172 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3173 SEC_READONLY | SEC_RELOC
3175 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3178 subseg_set (seg, subseg);
3181 if (! ECOFF_DEBUGGING)
3184 if (mips_fix_vr4120)
3185 init_vr4120_conflicts ();
3191 mips_emit_delays ();
3192 if (! ECOFF_DEBUGGING)
3197 md_assemble (char *str)
3199 struct mips_cl_insn insn;
3200 bfd_reloc_code_real_type unused_reloc[3]
3201 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3203 imm_expr.X_op = O_absent;
3204 imm2_expr.X_op = O_absent;
3205 offset_expr.X_op = O_absent;
3206 offset_reloc[0] = BFD_RELOC_UNUSED;
3207 offset_reloc[1] = BFD_RELOC_UNUSED;
3208 offset_reloc[2] = BFD_RELOC_UNUSED;
3210 mips_mark_labels ();
3211 mips_assembling_insn = TRUE;
3213 if (mips_opts.mips16)
3214 mips16_ip (str, &insn);
3217 mips_ip (str, &insn);
3218 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3219 str, insn.insn_opcode));
3223 as_bad ("%s `%s'", insn_error, str);
3224 else if (insn.insn_mo->pinfo == INSN_MACRO)
3227 if (mips_opts.mips16)
3228 mips16_macro (&insn);
3235 if (offset_expr.X_op != O_absent)
3236 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3238 append_insn (&insn, NULL, unused_reloc, FALSE);
3241 mips_assembling_insn = FALSE;
3244 /* Convenience functions for abstracting away the differences between
3245 MIPS16 and non-MIPS16 relocations. */
3247 static inline bfd_boolean
3248 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3252 case BFD_RELOC_MIPS16_JMP:
3253 case BFD_RELOC_MIPS16_GPREL:
3254 case BFD_RELOC_MIPS16_GOT16:
3255 case BFD_RELOC_MIPS16_CALL16:
3256 case BFD_RELOC_MIPS16_HI16_S:
3257 case BFD_RELOC_MIPS16_HI16:
3258 case BFD_RELOC_MIPS16_LO16:
3266 static inline bfd_boolean
3267 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3271 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3272 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3273 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3274 case BFD_RELOC_MICROMIPS_GPREL16:
3275 case BFD_RELOC_MICROMIPS_JMP:
3276 case BFD_RELOC_MICROMIPS_HI16:
3277 case BFD_RELOC_MICROMIPS_HI16_S:
3278 case BFD_RELOC_MICROMIPS_LO16:
3279 case BFD_RELOC_MICROMIPS_LITERAL:
3280 case BFD_RELOC_MICROMIPS_GOT16:
3281 case BFD_RELOC_MICROMIPS_CALL16:
3282 case BFD_RELOC_MICROMIPS_GOT_HI16:
3283 case BFD_RELOC_MICROMIPS_GOT_LO16:
3284 case BFD_RELOC_MICROMIPS_CALL_HI16:
3285 case BFD_RELOC_MICROMIPS_CALL_LO16:
3286 case BFD_RELOC_MICROMIPS_SUB:
3287 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3288 case BFD_RELOC_MICROMIPS_GOT_OFST:
3289 case BFD_RELOC_MICROMIPS_GOT_DISP:
3290 case BFD_RELOC_MICROMIPS_HIGHEST:
3291 case BFD_RELOC_MICROMIPS_HIGHER:
3292 case BFD_RELOC_MICROMIPS_SCN_DISP:
3293 case BFD_RELOC_MICROMIPS_JALR:
3301 static inline bfd_boolean
3302 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3304 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3307 static inline bfd_boolean
3308 got16_reloc_p (bfd_reloc_code_real_type reloc)
3310 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3311 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3314 static inline bfd_boolean
3315 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3317 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3318 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3321 static inline bfd_boolean
3322 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3324 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3325 || reloc == BFD_RELOC_MICROMIPS_LO16);
3328 static inline bfd_boolean
3329 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3331 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3334 static inline bfd_boolean
3335 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3337 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3338 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3341 /* Return true if RELOC is a PC-relative relocation that does not have
3342 full address range. */
3344 static inline bfd_boolean
3345 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3349 case BFD_RELOC_16_PCREL_S2:
3350 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3351 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3352 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3355 case BFD_RELOC_32_PCREL:
3356 return HAVE_64BIT_ADDRESSES;
3363 /* Return true if the given relocation might need a matching %lo().
3364 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3365 need a matching %lo() when applied to local symbols. */
3367 static inline bfd_boolean
3368 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3370 return (HAVE_IN_PLACE_ADDENDS
3371 && (hi16_reloc_p (reloc)
3372 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3373 all GOT16 relocations evaluate to "G". */
3374 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3377 /* Return the type of %lo() reloc needed by RELOC, given that
3378 reloc_needs_lo_p. */
3380 static inline bfd_reloc_code_real_type
3381 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3383 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3384 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3388 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3391 static inline bfd_boolean
3392 fixup_has_matching_lo_p (fixS *fixp)
3394 return (fixp->fx_next != NULL
3395 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3396 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3397 && fixp->fx_offset == fixp->fx_next->fx_offset);
3400 /* Move all labels in LABELS to the current insertion point. TEXT_P
3401 says whether the labels refer to text or data. */
3404 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3406 struct insn_label_list *l;
3409 for (l = labels; l != NULL; l = l->next)
3411 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3412 symbol_set_frag (l->label, frag_now);
3413 val = (valueT) frag_now_fix ();
3414 /* MIPS16/microMIPS text labels are stored as odd. */
3415 if (text_p && HAVE_CODE_COMPRESSION)
3417 S_SET_VALUE (l->label, val);
3421 /* Move all labels in insn_labels to the current insertion point
3422 and treat them as text labels. */
3425 mips_move_text_labels (void)
3427 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3431 s_is_linkonce (symbolS *sym, segT from_seg)
3433 bfd_boolean linkonce = FALSE;
3434 segT symseg = S_GET_SEGMENT (sym);
3436 if (symseg != from_seg && !S_IS_LOCAL (sym))
3438 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3440 /* The GNU toolchain uses an extension for ELF: a section
3441 beginning with the magic string .gnu.linkonce is a
3442 linkonce section. */
3443 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3444 sizeof ".gnu.linkonce" - 1) == 0)
3450 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3451 linker to handle them specially, such as generating jalx instructions
3452 when needed. We also make them odd for the duration of the assembly,
3453 in order to generate the right sort of code. We will make them even
3454 in the adjust_symtab routine, while leaving them marked. This is
3455 convenient for the debugger and the disassembler. The linker knows
3456 to make them odd again. */
3459 mips_compressed_mark_label (symbolS *label)
3461 gas_assert (HAVE_CODE_COMPRESSION);
3463 if (mips_opts.mips16)
3464 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3466 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3467 if ((S_GET_VALUE (label) & 1) == 0
3468 /* Don't adjust the address if the label is global or weak, or
3469 in a link-once section, since we'll be emitting symbol reloc
3470 references to it which will be patched up by the linker, and
3471 the final value of the symbol may or may not be MIPS16/microMIPS. */
3472 && !S_IS_WEAK (label)
3473 && !S_IS_EXTERNAL (label)
3474 && !s_is_linkonce (label, now_seg))
3475 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3478 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3481 mips_compressed_mark_labels (void)
3483 struct insn_label_list *l;
3485 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3486 mips_compressed_mark_label (l->label);
3489 /* End the current frag. Make it a variant frag and record the
3493 relax_close_frag (void)
3495 mips_macro_warning.first_frag = frag_now;
3496 frag_var (rs_machine_dependent, 0, 0,
3497 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3498 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3500 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3501 mips_relax.first_fixup = 0;
3504 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3505 See the comment above RELAX_ENCODE for more details. */
3508 relax_start (symbolS *symbol)
3510 gas_assert (mips_relax.sequence == 0);
3511 mips_relax.sequence = 1;
3512 mips_relax.symbol = symbol;
3515 /* Start generating the second version of a relaxable sequence.
3516 See the comment above RELAX_ENCODE for more details. */
3521 gas_assert (mips_relax.sequence == 1);
3522 mips_relax.sequence = 2;
3525 /* End the current relaxable sequence. */
3530 gas_assert (mips_relax.sequence == 2);
3531 relax_close_frag ();
3532 mips_relax.sequence = 0;
3535 /* Return true if IP is a delayed branch or jump. */
3537 static inline bfd_boolean
3538 delayed_branch_p (const struct mips_cl_insn *ip)
3540 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3541 | INSN_COND_BRANCH_DELAY
3542 | INSN_COND_BRANCH_LIKELY)) != 0;
3545 /* Return true if IP is a compact branch or jump. */
3547 static inline bfd_boolean
3548 compact_branch_p (const struct mips_cl_insn *ip)
3550 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3551 | INSN2_COND_BRANCH)) != 0;
3554 /* Return true if IP is an unconditional branch or jump. */
3556 static inline bfd_boolean
3557 uncond_branch_p (const struct mips_cl_insn *ip)
3559 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3560 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3563 /* Return true if IP is a branch-likely instruction. */
3565 static inline bfd_boolean
3566 branch_likely_p (const struct mips_cl_insn *ip)
3568 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3571 /* Return the type of nop that should be used to fill the delay slot
3572 of delayed branch IP. */
3574 static struct mips_cl_insn *
3575 get_delay_slot_nop (const struct mips_cl_insn *ip)
3577 if (mips_opts.micromips
3578 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3579 return µmips_nop32_insn;
3583 /* Return the mask of core registers that IP reads or writes. */
3586 gpr_mod_mask (const struct mips_cl_insn *ip)
3588 unsigned long pinfo2;
3592 pinfo2 = ip->insn_mo->pinfo2;
3593 if (mips_opts.micromips)
3595 if (pinfo2 & INSN2_MOD_GPR_MD)
3596 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3597 if (pinfo2 & INSN2_MOD_GPR_MF)
3598 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3600 if (pinfo2 & INSN2_MOD_SP)
3605 /* Return the mask of core registers that IP reads. */
3608 gpr_read_mask (const struct mips_cl_insn *ip)
3610 unsigned long pinfo, pinfo2;
3613 mask = gpr_mod_mask (ip);
3614 pinfo = ip->insn_mo->pinfo;
3615 pinfo2 = ip->insn_mo->pinfo2;
3616 if (mips_opts.mips16)
3618 if (pinfo & MIPS16_INSN_READ_X)
3619 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3620 if (pinfo & MIPS16_INSN_READ_Y)
3621 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3622 if (pinfo & MIPS16_INSN_READ_T)
3624 if (pinfo & MIPS16_INSN_READ_SP)
3626 if (pinfo & MIPS16_INSN_READ_Z)
3627 mask |= 1 << (mips16_to_32_reg_map
3628 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3629 if (pinfo & MIPS16_INSN_READ_GPR_X)
3630 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3634 if (pinfo2 & INSN2_READ_GPR_D)
3635 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3636 if (pinfo & INSN_READ_GPR_T)
3637 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3638 if (pinfo & INSN_READ_GPR_S)
3639 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3640 if (pinfo2 & INSN2_READ_GP)
3642 if (pinfo2 & INSN2_READ_GPR_Z)
3643 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3645 if (pinfo2 & INSN2_READ_GPR_31)
3647 if (mips_opts.micromips)
3649 if (pinfo2 & INSN2_READ_GPR_MC)
3650 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3651 if (pinfo2 & INSN2_READ_GPR_ME)
3652 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3653 if (pinfo2 & INSN2_READ_GPR_MG)
3654 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3655 if (pinfo2 & INSN2_READ_GPR_MJ)
3656 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3657 if (pinfo2 & INSN2_READ_GPR_MMN)
3659 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3660 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3662 if (pinfo2 & INSN2_READ_GPR_MP)
3663 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3664 if (pinfo2 & INSN2_READ_GPR_MQ)
3665 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3667 /* Don't include register 0. */
3671 /* Return the mask of core registers that IP writes. */
3674 gpr_write_mask (const struct mips_cl_insn *ip)
3676 unsigned long pinfo, pinfo2;
3679 mask = gpr_mod_mask (ip);
3680 pinfo = ip->insn_mo->pinfo;
3681 pinfo2 = ip->insn_mo->pinfo2;
3682 if (mips_opts.mips16)
3684 if (pinfo & MIPS16_INSN_WRITE_X)
3685 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3686 if (pinfo & MIPS16_INSN_WRITE_Y)
3687 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3688 if (pinfo & MIPS16_INSN_WRITE_Z)
3689 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3690 if (pinfo & MIPS16_INSN_WRITE_T)
3692 if (pinfo & MIPS16_INSN_WRITE_31)
3694 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3695 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3699 if (pinfo & INSN_WRITE_GPR_D)
3700 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3701 if (pinfo & INSN_WRITE_GPR_T)
3702 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3703 if (pinfo & INSN_WRITE_GPR_S)
3704 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3705 if (pinfo & INSN_WRITE_GPR_31)
3707 if (pinfo2 & INSN2_WRITE_GPR_Z)
3708 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3710 if (mips_opts.micromips)
3712 if (pinfo2 & INSN2_WRITE_GPR_MB)
3713 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3714 if (pinfo2 & INSN2_WRITE_GPR_MH)
3716 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3717 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3719 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3720 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3721 if (pinfo2 & INSN2_WRITE_GPR_MP)
3722 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3724 /* Don't include register 0. */
3728 /* Return the mask of floating-point registers that IP reads. */
3731 fpr_read_mask (const struct mips_cl_insn *ip)
3733 unsigned long pinfo, pinfo2;
3737 pinfo = ip->insn_mo->pinfo;
3738 pinfo2 = ip->insn_mo->pinfo2;
3739 if (!mips_opts.mips16)
3741 if (pinfo2 & INSN2_READ_FPR_D)
3742 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3743 if (pinfo & INSN_READ_FPR_S)
3744 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3745 if (pinfo & INSN_READ_FPR_T)
3746 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3747 if (pinfo & INSN_READ_FPR_R)
3748 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3749 if (pinfo2 & INSN2_READ_FPR_Z)
3750 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3752 /* Conservatively treat all operands to an FP_D instruction are doubles.
3753 (This is overly pessimistic for things like cvt.d.s.) */
3754 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3759 /* Return the mask of floating-point registers that IP writes. */
3762 fpr_write_mask (const struct mips_cl_insn *ip)
3764 unsigned long pinfo, pinfo2;
3768 pinfo = ip->insn_mo->pinfo;
3769 pinfo2 = ip->insn_mo->pinfo2;
3770 if (!mips_opts.mips16)
3772 if (pinfo & INSN_WRITE_FPR_D)
3773 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3774 if (pinfo & INSN_WRITE_FPR_S)
3775 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3776 if (pinfo & INSN_WRITE_FPR_T)
3777 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3778 if (pinfo2 & INSN2_WRITE_FPR_Z)
3779 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3781 /* Conservatively treat all operands to an FP_D instruction are doubles.
3782 (This is overly pessimistic for things like cvt.s.d.) */
3783 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3788 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3789 Check whether that is allowed. */
3792 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
3794 const char *s = insn->name;
3796 if (insn->pinfo == INSN_MACRO)
3797 /* Let a macro pass, we'll catch it later when it is expanded. */
3800 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
3802 /* Allow odd registers for single-precision ops. */
3803 switch (insn->pinfo & (FP_S | FP_D))
3814 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3815 s = strchr (insn->name, '.');
3816 if (s != NULL && opnum == 2)
3817 s = strchr (s + 1, '.');
3818 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
3821 /* Single-precision coprocessor loads and moves are OK too. */
3822 if ((insn->pinfo & FP_S)
3823 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
3824 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
3830 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3831 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3832 this operand is normally printed in hex or decimal. */
3835 report_bad_range (struct mips_cl_insn *insn, int argnum,
3836 offsetT val, int min_val, int max_val,
3837 bfd_boolean print_hex)
3839 if (print_hex && val >= 0)
3840 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3842 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3844 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3846 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3848 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3850 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3853 /* Report an invalid combination of position and size operands for a bitfield
3854 operation. POS and SIZE are the values that were given. */
3857 report_bad_field (offsetT pos, offsetT size)
3859 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3860 (unsigned long) pos, (unsigned long) size);
3863 /* Information about an instruction argument that we're trying to match. */
3864 struct mips_arg_info
3866 /* The instruction so far. */
3867 struct mips_cl_insn *insn;
3869 /* The first unconsumed operand token. */
3870 struct mips_operand_token *token;
3872 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3875 /* The 1-based argument number, for error reporting. This does not
3876 count elided optional registers, etc.. */
3879 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3880 unsigned int last_regno;
3882 /* If the first operand was an OP_REG, this is the register that it
3883 specified, otherwise it is ILLEGAL_REG. */
3884 unsigned int dest_regno;
3886 /* The value of the last OP_INT operand. Only used for OP_MSB,
3887 where it gives the lsb position. */
3888 unsigned int last_op_int;
3890 /* If true, match routines should silently reject invalid arguments.
3891 If false, match routines can accept invalid arguments as long as
3892 they report an appropriate error. They still have the option of
3893 silently rejecting arguments, in which case a generic "Invalid operands"
3894 style of error will be used instead. */
3895 bfd_boolean soft_match;
3897 /* If true, the OP_INT match routine should treat plain symbolic operands
3898 as if a relocation operator like %lo(...) had been used. This is only
3899 ever true if the operand can be relocated. */
3900 bfd_boolean allow_nonconst;
3902 /* When true, the OP_INT match routine should allow unsigned N-bit
3903 arguments to be used where a signed N-bit operand is expected. */
3904 bfd_boolean lax_max;
3906 /* True if a reference to the current AT register was seen. */
3907 bfd_boolean seen_at;
3910 /* Try to match an OT_CHAR token for character CH. Consume the token
3911 and return true on success, otherwise return false. */
3914 match_char (struct mips_arg_info *arg, char ch)
3916 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
3926 /* Try to get an expression from the next tokens in ARG. Consume the
3927 tokens and return true on success, storing the expression value in
3928 VALUE and relocation types in R. */
3931 match_expression (struct mips_arg_info *arg, expressionS *value,
3932 bfd_reloc_code_real_type *r)
3934 if (arg->token->type == OT_INTEGER)
3936 *value = arg->token->u.integer.value;
3937 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
3942 /* Error-reporting is more consistent if we treat registers as O_register
3943 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
3944 then handled in the same way. */
3945 if (arg->token->type == OT_REG)
3947 value->X_add_number = arg->token->u.regno;
3950 else if (arg->token[0].type == OT_CHAR
3951 && arg->token[0].u.ch == '('
3952 && arg->token[1].type == OT_REG
3953 && arg->token[2].type == OT_CHAR
3954 && arg->token[2].u.ch == ')')
3956 value->X_add_number = arg->token[1].u.regno;
3962 value->X_op = O_register;
3963 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
3967 /* Try to get a constant expression from the next tokens in ARG. Consume
3968 the tokens and return return true on success, storing the constant value
3969 in *VALUE. Use FALLBACK as the value if the match succeeded with an
3973 match_const_int (struct mips_arg_info *arg, offsetT *value, offsetT fallback)
3976 bfd_reloc_code_real_type r[3];
3978 if (!match_expression (arg, &ex, r))
3981 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
3982 *value = ex.X_add_number;
3985 if (arg->soft_match)
3987 as_bad (_("Operand %d of `%s' must be constant"),
3988 arg->argnum, arg->insn->insn_mo->name);
3994 /* Return the RTYPE_* flags for a register operand of type TYPE that
3995 appears in instruction OPCODE. */
3998 convert_reg_type (const struct mips_opcode *opcode,
3999 enum mips_reg_operand_type type)
4004 return RTYPE_NUM | RTYPE_GP;
4007 /* Allow vector register names for MDMX if the instruction is a 64-bit
4008 FPR load, store or move (including moves to and from GPRs). */
4009 if ((mips_opts.ase & ASE_MDMX)
4010 && (opcode->pinfo & FP_D)
4011 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4012 | INSN_COPROC_MEMORY_DELAY
4013 | INSN_LOAD_COPROC_DELAY
4014 | INSN_LOAD_MEMORY_DELAY
4015 | INSN_STORE_MEMORY)))
4016 return RTYPE_FPU | RTYPE_VEC;
4020 if (opcode->pinfo & (FP_D | FP_S))
4021 return RTYPE_CCC | RTYPE_FCC;
4025 if (opcode->membership & INSN_5400)
4027 return RTYPE_FPU | RTYPE_VEC;
4033 if (opcode->name[strlen (opcode->name) - 1] == '0')
4034 return RTYPE_NUM | RTYPE_CP0;
4043 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4046 check_regno (struct mips_arg_info *arg,
4047 enum mips_reg_operand_type type, unsigned int regno)
4049 if (AT && type == OP_REG_GP && regno == AT)
4050 arg->seen_at = TRUE;
4052 if (type == OP_REG_FP
4055 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4056 as_warn (_("Float register should be even, was %d"), regno);
4058 if (type == OP_REG_CCC)
4063 name = arg->insn->insn_mo->name;
4064 length = strlen (name);
4065 if ((regno & 1) != 0
4066 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4067 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4068 as_warn (_("Condition code register should be even for %s, was %d"),
4071 if ((regno & 3) != 0
4072 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4073 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4078 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4079 a register of type TYPE. Return true on success, storing the register
4080 number in *REGNO and warning about any dubious uses. */
4083 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4084 unsigned int symval, unsigned int *regno)
4086 if (type == OP_REG_VEC)
4087 symval = mips_prefer_vec_regno (symval);
4088 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4091 *regno = symval & RNUM_MASK;
4092 check_regno (arg, type, *regno);
4096 /* Try to interpret the next token in ARG as a register of type TYPE.
4097 Consume the token and return true on success, storing the register
4098 number in *REGNO. Return false on failure. */
4101 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4102 unsigned int *regno)
4104 if (arg->token->type == OT_REG
4105 && match_regno (arg, type, arg->token->u.regno, regno))
4113 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4114 Consume the token and return true on success, storing the register numbers
4115 in *REGNO1 and *REGNO2. Return false on failure. */
4118 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4119 unsigned int *regno1, unsigned int *regno2)
4121 if (match_reg (arg, type, regno1))
4126 if (arg->token->type == OT_REG_RANGE
4127 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4128 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4129 && *regno1 <= *regno2)
4137 /* OP_INT matcher. */
4140 match_int_operand (struct mips_arg_info *arg,
4141 const struct mips_operand *operand_base)
4143 const struct mips_int_operand *operand;
4144 unsigned int uval, mask;
4145 int min_val, max_val, factor;
4147 bfd_boolean print_hex;
4149 operand = (const struct mips_int_operand *) operand_base;
4150 factor = 1 << operand->shift;
4151 mask = (1 << operand_base->size) - 1;
4152 max_val = (operand->max_val + operand->bias) << operand->shift;
4153 min_val = max_val - (mask << operand->shift);
4155 max_val = mask << operand->shift;
4157 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4158 /* Assume we have an elided offset. The later match will fail
4159 if this turns out to be wrong. */
4161 else if (operand_base->lsb == 0
4162 && operand_base->size == 16
4163 && operand->shift == 0
4164 && operand->bias == 0
4165 && (operand->max_val == 32767 || operand->max_val == 65535))
4167 /* The operand can be relocated. */
4168 if (!match_expression (arg, &offset_expr, offset_reloc))
4171 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4172 /* Relocation operators were used. Accept the arguent and
4173 leave the relocation value in offset_expr and offset_relocs
4174 for the caller to process. */
4177 if (offset_expr.X_op != O_constant)
4179 /* If non-constant operands are allowed then leave them for
4180 the caller to process, otherwise fail the match. */
4181 if (!arg->allow_nonconst)
4183 offset_reloc[0] = BFD_RELOC_LO16;
4187 /* Clear the global state; we're going to install the operand
4189 sval = offset_expr.X_add_number;
4190 offset_expr.X_op = O_absent;
4194 if (!match_const_int (arg, &sval, min_val))
4198 arg->last_op_int = sval;
4200 /* Check the range. If there's a problem, record the lowest acceptable
4201 value in arg->last_op_int in order to prevent an unhelpful error
4204 Bit counts have traditionally been printed in hex by the disassembler
4205 but printed as decimal in error messages. Only resort to hex if
4206 the operand is bigger than 6 bits. */
4207 print_hex = operand->print_hex && operand_base->size > 6;
4208 if (sval < min_val || sval > max_val)
4210 if (arg->soft_match)
4212 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
4214 arg->last_op_int = min_val;
4216 else if (sval % factor)
4218 if (arg->soft_match)
4220 as_bad (print_hex && sval >= 0
4221 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4222 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4223 arg->argnum, arg->insn->insn_mo->name, factor,
4224 (unsigned long) sval);
4225 arg->last_op_int = min_val;
4228 uval = (unsigned int) sval >> operand->shift;
4229 uval -= operand->bias;
4231 /* Handle -mfix-cn63xxp1. */
4233 && mips_fix_cn63xxp1
4234 && !mips_opts.micromips
4235 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4250 /* The rest must be changed to 28. */
4255 insn_insert_operand (arg->insn, operand_base, uval);
4259 /* OP_MAPPED_INT matcher. */
4262 match_mapped_int_operand (struct mips_arg_info *arg,
4263 const struct mips_operand *operand_base)
4265 const struct mips_mapped_int_operand *operand;
4266 unsigned int uval, num_vals;
4269 operand = (const struct mips_mapped_int_operand *) operand_base;
4270 if (!match_const_int (arg, &sval, operand->int_map[0]))
4273 num_vals = 1 << operand_base->size;
4274 for (uval = 0; uval < num_vals; uval++)
4275 if (operand->int_map[uval] == sval)
4277 if (uval == num_vals)
4280 insn_insert_operand (arg->insn, operand_base, uval);
4284 /* OP_MSB matcher. */
4287 match_msb_operand (struct mips_arg_info *arg,
4288 const struct mips_operand *operand_base)
4290 const struct mips_msb_operand *operand;
4291 int min_val, max_val, max_high;
4292 offsetT size, sval, high;
4294 operand = (const struct mips_msb_operand *) operand_base;
4295 min_val = operand->bias;
4296 max_val = min_val + (1 << operand_base->size) - 1;
4297 max_high = operand->opsize;
4299 if (!match_const_int (arg, &size, 1))
4302 high = size + arg->last_op_int;
4303 sval = operand->add_lsb ? high : size;
4305 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4307 if (arg->soft_match)
4309 report_bad_field (arg->last_op_int, size);
4312 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4316 /* OP_REG matcher. */
4319 match_reg_operand (struct mips_arg_info *arg,
4320 const struct mips_operand *operand_base)
4322 const struct mips_reg_operand *operand;
4323 unsigned int regno, uval, num_vals;
4325 operand = (const struct mips_reg_operand *) operand_base;
4326 if (!match_reg (arg, operand->reg_type, ®no))
4329 if (operand->reg_map)
4331 num_vals = 1 << operand->root.size;
4332 for (uval = 0; uval < num_vals; uval++)
4333 if (operand->reg_map[uval] == regno)
4335 if (num_vals == uval)
4341 arg->last_regno = regno;
4342 if (arg->opnum == 1)
4343 arg->dest_regno = regno;
4344 insn_insert_operand (arg->insn, operand_base, uval);
4348 /* OP_REG_PAIR matcher. */
4351 match_reg_pair_operand (struct mips_arg_info *arg,
4352 const struct mips_operand *operand_base)
4354 const struct mips_reg_pair_operand *operand;
4355 unsigned int regno1, regno2, uval, num_vals;
4357 operand = (const struct mips_reg_pair_operand *) operand_base;
4358 if (!match_reg (arg, operand->reg_type, ®no1)
4359 || !match_char (arg, ',')
4360 || !match_reg (arg, operand->reg_type, ®no2))
4363 num_vals = 1 << operand_base->size;
4364 for (uval = 0; uval < num_vals; uval++)
4365 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4367 if (uval == num_vals)
4370 insn_insert_operand (arg->insn, operand_base, uval);
4374 /* OP_PCREL matcher. The caller chooses the relocation type. */
4377 match_pcrel_operand (struct mips_arg_info *arg)
4379 bfd_reloc_code_real_type r[3];
4381 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4384 /* OP_PERF_REG matcher. */
4387 match_perf_reg_operand (struct mips_arg_info *arg,
4388 const struct mips_operand *operand)
4392 if (!match_const_int (arg, &sval, 0))
4397 || (mips_opts.arch == CPU_R5900
4398 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4399 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4401 if (arg->soft_match)
4403 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4406 insn_insert_operand (arg->insn, operand, sval);
4410 /* OP_ADDIUSP matcher. */
4413 match_addiusp_operand (struct mips_arg_info *arg,
4414 const struct mips_operand *operand)
4419 if (!match_const_int (arg, &sval, -256))
4426 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4429 uval = (unsigned int) sval;
4430 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4431 insn_insert_operand (arg->insn, operand, uval);
4435 /* OP_CLO_CLZ_DEST matcher. */
4438 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4439 const struct mips_operand *operand)
4443 if (!match_reg (arg, OP_REG_GP, ®no))
4446 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4450 /* OP_LWM_SWM_LIST matcher. */
4453 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4454 const struct mips_operand *operand)
4456 unsigned int reglist, sregs, ra, regno1, regno2;
4457 struct mips_arg_info reset;
4460 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4464 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4469 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4472 while (match_char (arg, ',')
4473 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4476 if (operand->size == 2)
4478 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4484 and any permutations of these. */
4485 if ((reglist & 0xfff1ffff) != 0x80010000)
4488 sregs = (reglist >> 17) & 7;
4493 /* The list must include at least one of ra and s0-sN,
4494 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4495 which are $23 and $30 respectively.) E.g.:
4503 and any permutations of these. */
4504 if ((reglist & 0x3f00ffff) != 0)
4507 ra = (reglist >> 27) & 0x10;
4508 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4511 if ((sregs & -sregs) != sregs)
4514 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4518 /* OP_ENTRY_EXIT_LIST matcher. */
4521 match_entry_exit_operand (struct mips_arg_info *arg,
4522 const struct mips_operand *operand)
4525 bfd_boolean is_exit;
4527 /* The format is the same for both ENTRY and EXIT, but the constraints
4529 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4530 mask = (is_exit ? 7 << 3 : 0);
4533 unsigned int regno1, regno2;
4534 bfd_boolean is_freg;
4536 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4538 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4543 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4546 mask |= (5 + regno2) << 3;
4548 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4549 mask |= (regno2 - 3) << 3;
4550 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4551 mask |= (regno2 - 15) << 1;
4552 else if (regno1 == RA && regno2 == RA)
4557 while (match_char (arg, ','));
4559 insn_insert_operand (arg->insn, operand, mask);
4563 /* OP_SAVE_RESTORE_LIST matcher. */
4566 match_save_restore_list_operand (struct mips_arg_info *arg)
4568 unsigned int opcode, args, statics, sregs;
4569 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4574 opcode = arg->insn->insn_opcode;
4576 num_frame_sizes = 0;
4582 unsigned int regno1, regno2;
4584 if (arg->token->type == OT_INTEGER)
4586 /* Handle the frame size. */
4587 if (!match_const_int (arg, &frame_size, 0))
4589 num_frame_sizes += 1;
4593 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4596 while (regno1 <= regno2)
4598 if (regno1 >= 4 && regno1 <= 7)
4600 if (num_frame_sizes == 0)
4602 args |= 1 << (regno1 - 4);
4604 /* statics $a0-$a3 */
4605 statics |= 1 << (regno1 - 4);
4607 else if (regno1 >= 16 && regno1 <= 23)
4609 sregs |= 1 << (regno1 - 16);
4610 else if (regno1 == 30)
4613 else if (regno1 == 31)
4614 /* Add $ra to insn. */
4624 while (match_char (arg, ','));
4626 /* Encode args/statics combination. */
4629 else if (args == 0xf)
4630 /* All $a0-$a3 are args. */
4631 opcode |= MIPS16_ALL_ARGS << 16;
4632 else if (statics == 0xf)
4633 /* All $a0-$a3 are statics. */
4634 opcode |= MIPS16_ALL_STATICS << 16;
4637 /* Count arg registers. */
4647 /* Count static registers. */
4649 while (statics & 0x8)
4651 statics = (statics << 1) & 0xf;
4657 /* Encode args/statics. */
4658 opcode |= ((num_args << 2) | num_statics) << 16;
4661 /* Encode $s0/$s1. */
4662 if (sregs & (1 << 0)) /* $s0 */
4664 if (sregs & (1 << 1)) /* $s1 */
4668 /* Encode $s2-$s8. */
4677 opcode |= num_sregs << 24;
4679 /* Encode frame size. */
4680 if (num_frame_sizes == 0)
4681 error = _("Missing frame size");
4682 else if (num_frame_sizes > 1)
4683 error = _("Frame size specified twice");
4684 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4685 error = _("Invalid frame size");
4686 else if (frame_size != 128 || (opcode >> 16) != 0)
4689 opcode |= (((frame_size & 0xf0) << 16)
4690 | (frame_size & 0x0f));
4695 if (arg->soft_match)
4697 as_bad ("%s", error);
4700 /* Finally build the instruction. */
4701 if ((opcode >> 16) != 0 || frame_size == 0)
4702 opcode |= MIPS16_EXTEND;
4703 arg->insn->insn_opcode = opcode;
4707 /* OP_MDMX_IMM_REG matcher. */
4710 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
4711 const struct mips_operand *operand)
4713 unsigned int regno, uval;
4715 const struct mips_opcode *opcode;
4717 /* The mips_opcode records whether this is an octobyte or quadhalf
4718 instruction. Start out with that bit in place. */
4719 opcode = arg->insn->insn_mo;
4720 uval = mips_extract_operand (operand, opcode->match);
4721 is_qh = (uval != 0);
4723 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
4725 if ((opcode->membership & INSN_5400)
4726 && strcmp (opcode->name, "rzu.ob") == 0)
4728 if (arg->soft_match)
4730 as_bad (_("Operand %d of `%s' must be an immediate"),
4731 arg->argnum, opcode->name);
4734 /* Check whether this is a vector register or a broadcast of
4735 a single element. */
4736 if (arg->token->type == OT_REG_ELEMENT)
4738 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
4741 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
4743 if (arg->soft_match)
4745 as_bad (_("Invalid element selector"));
4748 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
4752 /* A full vector. */
4753 if ((opcode->membership & INSN_5400)
4754 && (strcmp (opcode->name, "sll.ob") == 0
4755 || strcmp (opcode->name, "srl.ob") == 0))
4757 if (arg->soft_match)
4759 as_bad (_("Operand %d of `%s' must be scalar"),
4760 arg->argnum, opcode->name);
4763 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
4766 uval |= MDMX_FMTSEL_VEC_QH << 5;
4768 uval |= MDMX_FMTSEL_VEC_OB << 5;
4777 if (!match_const_int (arg, &sval, 0))
4779 if (sval < 0 || sval > 31)
4781 if (arg->soft_match)
4783 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
4785 uval |= (sval & 31);
4787 uval |= MDMX_FMTSEL_IMM_QH << 5;
4789 uval |= MDMX_FMTSEL_IMM_OB << 5;
4791 insn_insert_operand (arg->insn, operand, uval);
4795 /* OP_PC matcher. */
4798 match_pc_operand (struct mips_arg_info *arg)
4800 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
4808 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4809 register that we need to match. */
4812 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
4816 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
4819 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4820 the length of the value in bytes (4 for float, 8 for double) and
4821 USING_GPRS says whether the destination is a GPR rather than an FPR.
4823 Return the constant in IMM and OFFSET as follows:
4825 - If the constant should be loaded via memory, set IMM to O_absent and
4826 OFFSET to the memory address.
4828 - Otherwise, if the constant should be loaded into two 32-bit registers,
4829 set IMM to the O_constant to load into the high register and OFFSET
4830 to the corresponding value for the low register.
4832 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4834 These constants only appear as the last operand in an instruction,
4835 and every instruction that accepts them in any variant accepts them
4836 in all variants. This means we don't have to worry about backing out
4837 any changes if the instruction does not match. We just match
4838 unconditionally and report an error if the constant is invalid. */
4841 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
4842 expressionS *offset, int length, bfd_boolean using_gprs)
4847 const char *newname;
4848 unsigned char *data;
4850 /* Where the constant is placed is based on how the MIPS assembler
4853 length == 4 && using_gprs -- immediate value only
4854 length == 8 && using_gprs -- .rdata or immediate value
4855 length == 4 && !using_gprs -- .lit4 or immediate value
4856 length == 8 && !using_gprs -- .lit8 or immediate value
4858 The .lit4 and .lit8 sections are only used if permitted by the
4860 if (arg->token->type != OT_FLOAT)
4863 gas_assert (arg->token->u.flt.length == length);
4864 data = arg->token->u.flt.data;
4867 /* Handle 32-bit constants for which an immediate value is best. */
4870 || g_switch_value < 4
4871 || (data[0] == 0 && data[1] == 0)
4872 || (data[2] == 0 && data[3] == 0)))
4874 imm->X_op = O_constant;
4875 if (!target_big_endian)
4876 imm->X_add_number = bfd_getl32 (data);
4878 imm->X_add_number = bfd_getb32 (data);
4879 offset->X_op = O_absent;
4883 /* Handle 64-bit constants for which an immediate value is best. */
4885 && !mips_disable_float_construction
4886 /* Constants can only be constructed in GPRs and copied
4887 to FPRs if the GPRs are at least as wide as the FPRs.
4888 Force the constant into memory if we are using 64-bit FPRs
4889 but the GPRs are only 32 bits wide. */
4890 /* ??? No longer true with the addition of MTHC1, but this
4891 is legacy code... */
4892 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
4893 && ((data[0] == 0 && data[1] == 0)
4894 || (data[2] == 0 && data[3] == 0))
4895 && ((data[4] == 0 && data[5] == 0)
4896 || (data[6] == 0 && data[7] == 0)))
4898 /* The value is simple enough to load with a couple of instructions.
4899 If using 32-bit registers, set IMM to the high order 32 bits and
4900 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4902 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
4904 imm->X_op = O_constant;
4905 offset->X_op = O_constant;
4906 if (!target_big_endian)
4908 imm->X_add_number = bfd_getl32 (data + 4);
4909 offset->X_add_number = bfd_getl32 (data);
4913 imm->X_add_number = bfd_getb32 (data);
4914 offset->X_add_number = bfd_getb32 (data + 4);
4916 if (offset->X_add_number == 0)
4917 offset->X_op = O_absent;
4921 imm->X_op = O_constant;
4922 if (!target_big_endian)
4923 imm->X_add_number = bfd_getl64 (data);
4925 imm->X_add_number = bfd_getb64 (data);
4926 offset->X_op = O_absent;
4931 /* Switch to the right section. */
4933 subseg = now_subseg;
4936 gas_assert (!using_gprs && g_switch_value >= 4);
4941 if (using_gprs || g_switch_value < 8)
4942 newname = RDATA_SECTION_NAME;
4947 new_seg = subseg_new (newname, (subsegT) 0);
4948 bfd_set_section_flags (stdoutput, new_seg,
4949 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
4950 frag_align (length == 4 ? 2 : 3, 0, 0);
4951 if (strncmp (TARGET_OS, "elf", 3) != 0)
4952 record_alignment (new_seg, 4);
4954 record_alignment (new_seg, length == 4 ? 2 : 3);
4956 as_bad (_("Can't use floating point insn in this section"));
4958 /* Set the argument to the current address in the section. */
4959 imm->X_op = O_absent;
4960 offset->X_op = O_symbol;
4961 offset->X_add_symbol = symbol_temp_new_now ();
4962 offset->X_add_number = 0;
4964 /* Put the floating point number into the section. */
4965 p = frag_more (length);
4966 memcpy (p, data, length);
4968 /* Switch back to the original section. */
4969 subseg_set (seg, subseg);
4973 /* S is the text seen for ARG. Match it against OPERAND. Return the end
4974 of the argument text if the match is successful, otherwise return null. */
4977 match_operand (struct mips_arg_info *arg,
4978 const struct mips_operand *operand)
4980 switch (operand->type)
4983 return match_int_operand (arg, operand);
4986 return match_mapped_int_operand (arg, operand);
4989 return match_msb_operand (arg, operand);
4992 return match_reg_operand (arg, operand);
4995 return match_reg_pair_operand (arg, operand);
4998 return match_pcrel_operand (arg);
5001 return match_perf_reg_operand (arg, operand);
5003 case OP_ADDIUSP_INT:
5004 return match_addiusp_operand (arg, operand);
5006 case OP_CLO_CLZ_DEST:
5007 return match_clo_clz_dest_operand (arg, operand);
5009 case OP_LWM_SWM_LIST:
5010 return match_lwm_swm_list_operand (arg, operand);
5012 case OP_ENTRY_EXIT_LIST:
5013 return match_entry_exit_operand (arg, operand);
5015 case OP_SAVE_RESTORE_LIST:
5016 return match_save_restore_list_operand (arg);
5018 case OP_MDMX_IMM_REG:
5019 return match_mdmx_imm_reg_operand (arg, operand);
5021 case OP_REPEAT_DEST_REG:
5022 return match_tied_reg_operand (arg, arg->dest_regno);
5024 case OP_REPEAT_PREV_REG:
5025 return match_tied_reg_operand (arg, arg->last_regno);
5028 return match_pc_operand (arg);
5033 /* ARG is the state after successfully matching an instruction.
5034 Issue any queued-up warnings. */
5037 check_completed_insn (struct mips_arg_info *arg)
5042 as_warn (_("Used $at without \".set noat\""));
5044 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5048 /* Return true if modifying general-purpose register REG needs a delay. */
5051 reg_needs_delay (unsigned int reg)
5053 unsigned long prev_pinfo;
5055 prev_pinfo = history[0].insn_mo->pinfo;
5056 if (!mips_opts.noreorder
5057 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5058 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5059 && (gpr_write_mask (&history[0]) & (1 << reg)))
5065 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5066 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5067 by VR4120 errata. */
5070 classify_vr4120_insn (const char *name)
5072 if (strncmp (name, "macc", 4) == 0)
5073 return FIX_VR4120_MACC;
5074 if (strncmp (name, "dmacc", 5) == 0)
5075 return FIX_VR4120_DMACC;
5076 if (strncmp (name, "mult", 4) == 0)
5077 return FIX_VR4120_MULT;
5078 if (strncmp (name, "dmult", 5) == 0)
5079 return FIX_VR4120_DMULT;
5080 if (strstr (name, "div"))
5081 return FIX_VR4120_DIV;
5082 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5083 return FIX_VR4120_MTHILO;
5084 return NUM_FIX_VR4120_CLASSES;
5087 #define INSN_ERET 0x42000018
5088 #define INSN_DERET 0x4200001f
5090 /* Return the number of instructions that must separate INSN1 and INSN2,
5091 where INSN1 is the earlier instruction. Return the worst-case value
5092 for any INSN2 if INSN2 is null. */
5095 insns_between (const struct mips_cl_insn *insn1,
5096 const struct mips_cl_insn *insn2)
5098 unsigned long pinfo1, pinfo2;
5101 /* If INFO2 is null, pessimistically assume that all flags are set for
5102 the second instruction. */
5103 pinfo1 = insn1->insn_mo->pinfo;
5104 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5106 /* For most targets, write-after-read dependencies on the HI and LO
5107 registers must be separated by at least two instructions. */
5108 if (!hilo_interlocks)
5110 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5112 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5116 /* If we're working around r7000 errata, there must be two instructions
5117 between an mfhi or mflo and any instruction that uses the result. */
5118 if (mips_7000_hilo_fix
5119 && !mips_opts.micromips
5120 && MF_HILO_INSN (pinfo1)
5121 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5124 /* If we're working around 24K errata, one instruction is required
5125 if an ERET or DERET is followed by a branch instruction. */
5126 if (mips_fix_24k && !mips_opts.micromips)
5128 if (insn1->insn_opcode == INSN_ERET
5129 || insn1->insn_opcode == INSN_DERET)
5132 || insn2->insn_opcode == INSN_ERET
5133 || insn2->insn_opcode == INSN_DERET
5134 || delayed_branch_p (insn2))
5139 /* If working around VR4120 errata, check for combinations that need
5140 a single intervening instruction. */
5141 if (mips_fix_vr4120 && !mips_opts.micromips)
5143 unsigned int class1, class2;
5145 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5146 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5150 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5151 if (vr4120_conflicts[class1] & (1 << class2))
5156 if (!HAVE_CODE_COMPRESSION)
5158 /* Check for GPR or coprocessor load delays. All such delays
5159 are on the RT register. */
5160 /* Itbl support may require additional care here. */
5161 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5162 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5164 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5168 /* Check for generic coprocessor hazards.
5170 This case is not handled very well. There is no special
5171 knowledge of CP0 handling, and the coprocessors other than
5172 the floating point unit are not distinguished at all. */
5173 /* Itbl support may require additional care here. FIXME!
5174 Need to modify this to include knowledge about
5175 user specified delays! */
5176 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5177 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5179 /* Handle cases where INSN1 writes to a known general coprocessor
5180 register. There must be a one instruction delay before INSN2
5181 if INSN2 reads that register, otherwise no delay is needed. */
5182 mask = fpr_write_mask (insn1);
5185 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5190 /* Read-after-write dependencies on the control registers
5191 require a two-instruction gap. */
5192 if ((pinfo1 & INSN_WRITE_COND_CODE)
5193 && (pinfo2 & INSN_READ_COND_CODE))
5196 /* We don't know exactly what INSN1 does. If INSN2 is
5197 also a coprocessor instruction, assume there must be
5198 a one instruction gap. */
5199 if (pinfo2 & INSN_COP)
5204 /* Check for read-after-write dependencies on the coprocessor
5205 control registers in cases where INSN1 does not need a general
5206 coprocessor delay. This means that INSN1 is a floating point
5207 comparison instruction. */
5208 /* Itbl support may require additional care here. */
5209 else if (!cop_interlocks
5210 && (pinfo1 & INSN_WRITE_COND_CODE)
5211 && (pinfo2 & INSN_READ_COND_CODE))
5218 /* Return the number of nops that would be needed to work around the
5219 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5220 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5221 that are contained within the first IGNORE instructions of HIST. */
5224 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5225 const struct mips_cl_insn *insn)
5230 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5231 are not affected by the errata. */
5233 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5234 || strcmp (insn->insn_mo->name, "mtlo") == 0
5235 || strcmp (insn->insn_mo->name, "mthi") == 0))
5238 /* Search for the first MFLO or MFHI. */
5239 for (i = 0; i < MAX_VR4130_NOPS; i++)
5240 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5242 /* Extract the destination register. */
5243 mask = gpr_write_mask (&hist[i]);
5245 /* No nops are needed if INSN reads that register. */
5246 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5249 /* ...or if any of the intervening instructions do. */
5250 for (j = 0; j < i; j++)
5251 if (gpr_read_mask (&hist[j]) & mask)
5255 return MAX_VR4130_NOPS - i;
5260 #define BASE_REG_EQ(INSN1, INSN2) \
5261 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5262 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5264 /* Return the minimum alignment for this store instruction. */
5267 fix_24k_align_to (const struct mips_opcode *mo)
5269 if (strcmp (mo->name, "sh") == 0)
5272 if (strcmp (mo->name, "swc1") == 0
5273 || strcmp (mo->name, "swc2") == 0
5274 || strcmp (mo->name, "sw") == 0
5275 || strcmp (mo->name, "sc") == 0
5276 || strcmp (mo->name, "s.s") == 0)
5279 if (strcmp (mo->name, "sdc1") == 0
5280 || strcmp (mo->name, "sdc2") == 0
5281 || strcmp (mo->name, "s.d") == 0)
5288 struct fix_24k_store_info
5290 /* Immediate offset, if any, for this store instruction. */
5292 /* Alignment required by this store instruction. */
5294 /* True for register offsets. */
5295 int register_offset;
5298 /* Comparison function used by qsort. */
5301 fix_24k_sort (const void *a, const void *b)
5303 const struct fix_24k_store_info *pos1 = a;
5304 const struct fix_24k_store_info *pos2 = b;
5306 return (pos1->off - pos2->off);
5309 /* INSN is a store instruction. Try to record the store information
5310 in STINFO. Return false if the information isn't known. */
5313 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5314 const struct mips_cl_insn *insn)
5316 /* The instruction must have a known offset. */
5317 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5320 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5321 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5325 /* Return the number of nops that would be needed to work around the 24k
5326 "lost data on stores during refill" errata if instruction INSN
5327 immediately followed the 2 instructions described by HIST.
5328 Ignore hazards that are contained within the first IGNORE
5329 instructions of HIST.
5331 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5332 for the data cache refills and store data. The following describes
5333 the scenario where the store data could be lost.
5335 * A data cache miss, due to either a load or a store, causing fill
5336 data to be supplied by the memory subsystem
5337 * The first three doublewords of fill data are returned and written
5339 * A sequence of four stores occurs in consecutive cycles around the
5340 final doubleword of the fill:
5344 * Zero, One or more instructions
5347 The four stores A-D must be to different doublewords of the line that
5348 is being filled. The fourth instruction in the sequence above permits
5349 the fill of the final doubleword to be transferred from the FSB into
5350 the cache. In the sequence above, the stores may be either integer
5351 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5352 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5353 different doublewords on the line. If the floating point unit is
5354 running in 1:2 mode, it is not possible to create the sequence above
5355 using only floating point store instructions.
5357 In this case, the cache line being filled is incorrectly marked
5358 invalid, thereby losing the data from any store to the line that
5359 occurs between the original miss and the completion of the five
5360 cycle sequence shown above.
5362 The workarounds are:
5364 * Run the data cache in write-through mode.
5365 * Insert a non-store instruction between
5366 Store A and Store B or Store B and Store C. */
5369 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5370 const struct mips_cl_insn *insn)
5372 struct fix_24k_store_info pos[3];
5373 int align, i, base_offset;
5378 /* If the previous instruction wasn't a store, there's nothing to
5380 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5383 /* If the instructions after the previous one are unknown, we have
5384 to assume the worst. */
5388 /* Check whether we are dealing with three consecutive stores. */
5389 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5390 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5393 /* If we don't know the relationship between the store addresses,
5394 assume the worst. */
5395 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5396 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5399 if (!fix_24k_record_store_info (&pos[0], insn)
5400 || !fix_24k_record_store_info (&pos[1], &hist[0])
5401 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5404 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5406 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5407 X bytes and such that the base register + X is known to be aligned
5410 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5414 align = pos[0].align_to;
5415 base_offset = pos[0].off;
5416 for (i = 1; i < 3; i++)
5417 if (align < pos[i].align_to)
5419 align = pos[i].align_to;
5420 base_offset = pos[i].off;
5422 for (i = 0; i < 3; i++)
5423 pos[i].off -= base_offset;
5426 pos[0].off &= ~align + 1;
5427 pos[1].off &= ~align + 1;
5428 pos[2].off &= ~align + 1;
5430 /* If any two stores write to the same chunk, they also write to the
5431 same doubleword. The offsets are still sorted at this point. */
5432 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5435 /* A range of at least 9 bytes is needed for the stores to be in
5436 non-overlapping doublewords. */
5437 if (pos[2].off - pos[0].off <= 8)
5440 if (pos[2].off - pos[1].off >= 24
5441 || pos[1].off - pos[0].off >= 24
5442 || pos[2].off - pos[0].off >= 32)
5448 /* Return the number of nops that would be needed if instruction INSN
5449 immediately followed the MAX_NOPS instructions given by HIST,
5450 where HIST[0] is the most recent instruction. Ignore hazards
5451 between INSN and the first IGNORE instructions in HIST.
5453 If INSN is null, return the worse-case number of nops for any
5457 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5458 const struct mips_cl_insn *insn)
5460 int i, nops, tmp_nops;
5463 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5465 tmp_nops = insns_between (hist + i, insn) - i;
5466 if (tmp_nops > nops)
5470 if (mips_fix_vr4130 && !mips_opts.micromips)
5472 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5473 if (tmp_nops > nops)
5477 if (mips_fix_24k && !mips_opts.micromips)
5479 tmp_nops = nops_for_24k (ignore, hist, insn);
5480 if (tmp_nops > nops)
5487 /* The variable arguments provide NUM_INSNS extra instructions that
5488 might be added to HIST. Return the largest number of nops that
5489 would be needed after the extended sequence, ignoring hazards
5490 in the first IGNORE instructions. */
5493 nops_for_sequence (int num_insns, int ignore,
5494 const struct mips_cl_insn *hist, ...)
5497 struct mips_cl_insn buffer[MAX_NOPS];
5498 struct mips_cl_insn *cursor;
5501 va_start (args, hist);
5502 cursor = buffer + num_insns;
5503 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5504 while (cursor > buffer)
5505 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5507 nops = nops_for_insn (ignore, buffer, NULL);
5512 /* Like nops_for_insn, but if INSN is a branch, take into account the
5513 worst-case delay for the branch target. */
5516 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5517 const struct mips_cl_insn *insn)
5521 nops = nops_for_insn (ignore, hist, insn);
5522 if (delayed_branch_p (insn))
5524 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5525 hist, insn, get_delay_slot_nop (insn));
5526 if (tmp_nops > nops)
5529 else if (compact_branch_p (insn))
5531 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5532 if (tmp_nops > nops)
5538 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5541 fix_loongson2f_nop (struct mips_cl_insn * ip)
5543 gas_assert (!HAVE_CODE_COMPRESSION);
5544 if (strcmp (ip->insn_mo->name, "nop") == 0)
5545 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5548 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5549 jr target pc &= 'hffff_ffff_cfff_ffff. */
5552 fix_loongson2f_jump (struct mips_cl_insn * ip)
5554 gas_assert (!HAVE_CODE_COMPRESSION);
5555 if (strcmp (ip->insn_mo->name, "j") == 0
5556 || strcmp (ip->insn_mo->name, "jr") == 0
5557 || strcmp (ip->insn_mo->name, "jalr") == 0)
5565 sreg = EXTRACT_OPERAND (0, RS, *ip);
5566 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5569 ep.X_op = O_constant;
5570 ep.X_add_number = 0xcfff0000;
5571 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5572 ep.X_add_number = 0xffff;
5573 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5574 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5579 fix_loongson2f (struct mips_cl_insn * ip)
5581 if (mips_fix_loongson2f_nop)
5582 fix_loongson2f_nop (ip);
5584 if (mips_fix_loongson2f_jump)
5585 fix_loongson2f_jump (ip);
5588 /* IP is a branch that has a delay slot, and we need to fill it
5589 automatically. Return true if we can do that by swapping IP
5590 with the previous instruction.
5591 ADDRESS_EXPR is an operand of the instruction to be used with
5595 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5596 bfd_reloc_code_real_type *reloc_type)
5598 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
5599 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5601 /* -O2 and above is required for this optimization. */
5602 if (mips_optimize < 2)
5605 /* If we have seen .set volatile or .set nomove, don't optimize. */
5606 if (mips_opts.nomove)
5609 /* We can't swap if the previous instruction's position is fixed. */
5610 if (history[0].fixed_p)
5613 /* If the previous previous insn was in a .set noreorder, we can't
5614 swap. Actually, the MIPS assembler will swap in this situation.
5615 However, gcc configured -with-gnu-as will generate code like
5623 in which we can not swap the bne and INSN. If gcc is not configured
5624 -with-gnu-as, it does not output the .set pseudo-ops. */
5625 if (history[1].noreorder_p)
5628 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5629 This means that the previous instruction was a 4-byte one anyhow. */
5630 if (mips_opts.mips16 && history[0].fixp[0])
5633 /* If the branch is itself the target of a branch, we can not swap.
5634 We cheat on this; all we check for is whether there is a label on
5635 this instruction. If there are any branches to anything other than
5636 a label, users must use .set noreorder. */
5637 if (seg_info (now_seg)->label_list)
5640 /* If the previous instruction is in a variant frag other than this
5641 branch's one, we cannot do the swap. This does not apply to
5642 MIPS16 code, which uses variant frags for different purposes. */
5643 if (!mips_opts.mips16
5645 && history[0].frag->fr_type == rs_machine_dependent)
5648 /* We do not swap with instructions that cannot architecturally
5649 be placed in a branch delay slot, such as SYNC or ERET. We
5650 also refrain from swapping with a trap instruction, since it
5651 complicates trap handlers to have the trap instruction be in
5653 prev_pinfo = history[0].insn_mo->pinfo;
5654 if (prev_pinfo & INSN_NO_DELAY_SLOT)
5657 /* Check for conflicts between the branch and the instructions
5658 before the candidate delay slot. */
5659 if (nops_for_insn (0, history + 1, ip) > 0)
5662 /* Check for conflicts between the swapped sequence and the
5663 target of the branch. */
5664 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5667 /* If the branch reads a register that the previous
5668 instruction sets, we can not swap. */
5669 gpr_read = gpr_read_mask (ip);
5670 prev_gpr_write = gpr_write_mask (&history[0]);
5671 if (gpr_read & prev_gpr_write)
5674 /* If the branch writes a register that the previous
5675 instruction sets, we can not swap. */
5676 gpr_write = gpr_write_mask (ip);
5677 if (gpr_write & prev_gpr_write)
5680 /* If the branch writes a register that the previous
5681 instruction reads, we can not swap. */
5682 prev_gpr_read = gpr_read_mask (&history[0]);
5683 if (gpr_write & prev_gpr_read)
5686 /* If one instruction sets a condition code and the
5687 other one uses a condition code, we can not swap. */
5688 pinfo = ip->insn_mo->pinfo;
5689 if ((pinfo & INSN_READ_COND_CODE)
5690 && (prev_pinfo & INSN_WRITE_COND_CODE))
5692 if ((pinfo & INSN_WRITE_COND_CODE)
5693 && (prev_pinfo & INSN_READ_COND_CODE))
5696 /* If the previous instruction uses the PC, we can not swap. */
5697 prev_pinfo2 = history[0].insn_mo->pinfo2;
5698 if (prev_pinfo2 & INSN2_READ_PC)
5701 /* If the previous instruction has an incorrect size for a fixed
5702 branch delay slot in microMIPS mode, we cannot swap. */
5703 pinfo2 = ip->insn_mo->pinfo2;
5704 if (mips_opts.micromips
5705 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
5706 && insn_length (history) != 2)
5708 if (mips_opts.micromips
5709 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
5710 && insn_length (history) != 4)
5713 /* On R5900 short loops need to be fixed by inserting a nop in
5714 the branch delay slots.
5715 A short loop can be terminated too early. */
5716 if (mips_opts.arch == CPU_R5900
5717 /* Check if instruction has a parameter, ignore "j $31". */
5718 && (address_expr != NULL)
5719 /* Parameter must be 16 bit. */
5720 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
5721 /* Branch to same segment. */
5722 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
5723 /* Branch to same code fragment. */
5724 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
5725 /* Can only calculate branch offset if value is known. */
5726 && symbol_constant_p(address_expr->X_add_symbol)
5727 /* Check if branch is really conditional. */
5728 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5729 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
5730 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5733 /* Check if loop is shorter than 6 instructions including
5734 branch and delay slot. */
5735 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
5742 /* When the loop includes branches or jumps,
5743 it is not a short loop. */
5744 for (i = 0; i < (distance / 4); i++)
5746 if ((history[i].cleared_p)
5747 || delayed_branch_p(&history[i]))
5755 /* Insert nop after branch to fix short loop. */
5764 /* Decide how we should add IP to the instruction stream.
5765 ADDRESS_EXPR is an operand of the instruction to be used with
5768 static enum append_method
5769 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
5770 bfd_reloc_code_real_type *reloc_type)
5772 unsigned long pinfo, pinfo2;
5774 /* The relaxed version of a macro sequence must be inherently
5776 if (mips_relax.sequence == 2)
5779 /* We must not dabble with instructions in a ".set norerorder" block. */
5780 if (mips_opts.noreorder)
5783 /* Otherwise, it's our responsibility to fill branch delay slots. */
5784 if (delayed_branch_p (ip))
5786 if (!branch_likely_p (ip)
5787 && can_swap_branch_p (ip, address_expr, reloc_type))
5790 pinfo = ip->insn_mo->pinfo;
5791 pinfo2 = ip->insn_mo->pinfo2;
5792 if (mips_opts.mips16
5793 && ISA_SUPPORTS_MIPS16E
5794 && ((pinfo & MIPS16_INSN_READ_X) != 0
5795 || (pinfo2 & INSN2_READ_GPR_31) != 0))
5796 return APPEND_ADD_COMPACT;
5798 return APPEND_ADD_WITH_NOP;
5804 /* IP is a MIPS16 instruction whose opcode we have just changed.
5805 Point IP->insn_mo to the new opcode's definition. */
5808 find_altered_mips16_opcode (struct mips_cl_insn *ip)
5810 const struct mips_opcode *mo, *end;
5812 end = &mips16_opcodes[bfd_mips16_num_opcodes];
5813 for (mo = ip->insn_mo; mo < end; mo++)
5814 if ((ip->insn_opcode & mo->mask) == mo->match)
5822 /* For microMIPS macros, we need to generate a local number label
5823 as the target of branches. */
5824 #define MICROMIPS_LABEL_CHAR '\037'
5825 static unsigned long micromips_target_label;
5826 static char micromips_target_name[32];
5829 micromips_label_name (void)
5831 char *p = micromips_target_name;
5832 char symbol_name_temporary[24];
5840 l = micromips_target_label;
5841 #ifdef LOCAL_LABEL_PREFIX
5842 *p++ = LOCAL_LABEL_PREFIX;
5845 *p++ = MICROMIPS_LABEL_CHAR;
5848 symbol_name_temporary[i++] = l % 10 + '0';
5853 *p++ = symbol_name_temporary[--i];
5856 return micromips_target_name;
5860 micromips_label_expr (expressionS *label_expr)
5862 label_expr->X_op = O_symbol;
5863 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
5864 label_expr->X_add_number = 0;
5868 micromips_label_inc (void)
5870 micromips_target_label++;
5871 *micromips_target_name = '\0';
5875 micromips_add_label (void)
5879 s = colon (micromips_label_name ());
5880 micromips_label_inc ();
5881 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
5884 /* If assembling microMIPS code, then return the microMIPS reloc
5885 corresponding to the requested one if any. Otherwise return
5886 the reloc unchanged. */
5888 static bfd_reloc_code_real_type
5889 micromips_map_reloc (bfd_reloc_code_real_type reloc)
5891 static const bfd_reloc_code_real_type relocs[][2] =
5893 /* Keep sorted incrementally by the left-hand key. */
5894 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
5895 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
5896 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
5897 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
5898 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
5899 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
5900 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
5901 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
5902 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
5903 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
5904 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
5905 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
5906 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
5907 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
5908 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
5909 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
5910 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
5911 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
5912 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
5913 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
5914 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
5915 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
5916 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
5917 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
5918 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
5919 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
5920 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
5922 bfd_reloc_code_real_type r;
5925 if (!mips_opts.micromips)
5927 for (i = 0; i < ARRAY_SIZE (relocs); i++)
5933 return relocs[i][1];
5938 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5939 Return true on success, storing the resolved value in RESULT. */
5942 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
5947 case BFD_RELOC_MIPS_HIGHEST:
5948 case BFD_RELOC_MICROMIPS_HIGHEST:
5949 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
5952 case BFD_RELOC_MIPS_HIGHER:
5953 case BFD_RELOC_MICROMIPS_HIGHER:
5954 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
5957 case BFD_RELOC_HI16_S:
5958 case BFD_RELOC_MICROMIPS_HI16_S:
5959 case BFD_RELOC_MIPS16_HI16_S:
5960 *result = ((operand + 0x8000) >> 16) & 0xffff;
5963 case BFD_RELOC_HI16:
5964 case BFD_RELOC_MICROMIPS_HI16:
5965 case BFD_RELOC_MIPS16_HI16:
5966 *result = (operand >> 16) & 0xffff;
5969 case BFD_RELOC_LO16:
5970 case BFD_RELOC_MICROMIPS_LO16:
5971 case BFD_RELOC_MIPS16_LO16:
5972 *result = operand & 0xffff;
5975 case BFD_RELOC_UNUSED:
5984 /* Output an instruction. IP is the instruction information.
5985 ADDRESS_EXPR is an operand of the instruction to be used with
5986 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5987 a macro expansion. */
5990 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
5991 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
5993 unsigned long prev_pinfo2, pinfo;
5994 bfd_boolean relaxed_branch = FALSE;
5995 enum append_method method;
5996 bfd_boolean relax32;
5999 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6000 fix_loongson2f (ip);
6002 file_ase_mips16 |= mips_opts.mips16;
6003 file_ase_micromips |= mips_opts.micromips;
6005 prev_pinfo2 = history[0].insn_mo->pinfo2;
6006 pinfo = ip->insn_mo->pinfo;
6008 if (mips_opts.micromips
6010 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6011 && micromips_insn_length (ip->insn_mo) != 2)
6012 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6013 && micromips_insn_length (ip->insn_mo) != 4)))
6014 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6015 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6017 if (address_expr == NULL)
6019 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6020 && reloc_type[1] == BFD_RELOC_UNUSED
6021 && reloc_type[2] == BFD_RELOC_UNUSED
6022 && address_expr->X_op == O_constant)
6024 switch (*reloc_type)
6026 case BFD_RELOC_MIPS_JMP:
6030 shift = mips_opts.micromips ? 1 : 2;
6031 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6032 as_bad (_("jump to misaligned address (0x%lx)"),
6033 (unsigned long) address_expr->X_add_number);
6034 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6040 case BFD_RELOC_MIPS16_JMP:
6041 if ((address_expr->X_add_number & 3) != 0)
6042 as_bad (_("jump to misaligned address (0x%lx)"),
6043 (unsigned long) address_expr->X_add_number);
6045 (((address_expr->X_add_number & 0x7c0000) << 3)
6046 | ((address_expr->X_add_number & 0xf800000) >> 7)
6047 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6051 case BFD_RELOC_16_PCREL_S2:
6055 shift = mips_opts.micromips ? 1 : 2;
6056 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6057 as_bad (_("branch to misaligned address (0x%lx)"),
6058 (unsigned long) address_expr->X_add_number);
6059 if (!mips_relax_branch)
6061 if ((address_expr->X_add_number + (1 << (shift + 15)))
6062 & ~((1 << (shift + 16)) - 1))
6063 as_bad (_("branch address range overflow (0x%lx)"),
6064 (unsigned long) address_expr->X_add_number);
6065 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6075 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6078 ip->insn_opcode |= value & 0xffff;
6086 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6088 /* There are a lot of optimizations we could do that we don't.
6089 In particular, we do not, in general, reorder instructions.
6090 If you use gcc with optimization, it will reorder
6091 instructions and generally do much more optimization then we
6092 do here; repeating all that work in the assembler would only
6093 benefit hand written assembly code, and does not seem worth
6095 int nops = (mips_optimize == 0
6096 ? nops_for_insn (0, history, NULL)
6097 : nops_for_insn_or_target (0, history, ip));
6101 unsigned long old_frag_offset;
6104 old_frag = frag_now;
6105 old_frag_offset = frag_now_fix ();
6107 for (i = 0; i < nops; i++)
6108 add_fixed_insn (NOP_INSN);
6109 insert_into_history (0, nops, NOP_INSN);
6113 listing_prev_line ();
6114 /* We may be at the start of a variant frag. In case we
6115 are, make sure there is enough space for the frag
6116 after the frags created by listing_prev_line. The
6117 argument to frag_grow here must be at least as large
6118 as the argument to all other calls to frag_grow in
6119 this file. We don't have to worry about being in the
6120 middle of a variant frag, because the variants insert
6121 all needed nop instructions themselves. */
6125 mips_move_text_labels ();
6127 #ifndef NO_ECOFF_DEBUGGING
6128 if (ECOFF_DEBUGGING)
6129 ecoff_fix_loc (old_frag, old_frag_offset);
6133 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6137 /* Work out how many nops in prev_nop_frag are needed by IP,
6138 ignoring hazards generated by the first prev_nop_frag_since
6140 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6141 gas_assert (nops <= prev_nop_frag_holds);
6143 /* Enforce NOPS as a minimum. */
6144 if (nops > prev_nop_frag_required)
6145 prev_nop_frag_required = nops;
6147 if (prev_nop_frag_holds == prev_nop_frag_required)
6149 /* Settle for the current number of nops. Update the history
6150 accordingly (for the benefit of any future .set reorder code). */
6151 prev_nop_frag = NULL;
6152 insert_into_history (prev_nop_frag_since,
6153 prev_nop_frag_holds, NOP_INSN);
6157 /* Allow this instruction to replace one of the nops that was
6158 tentatively added to prev_nop_frag. */
6159 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6160 prev_nop_frag_holds--;
6161 prev_nop_frag_since++;
6165 method = get_append_method (ip, address_expr, reloc_type);
6166 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6168 dwarf2_emit_insn (0);
6169 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6170 so "move" the instruction address accordingly.
6172 Also, it doesn't seem appropriate for the assembler to reorder .loc
6173 entries. If this instruction is a branch that we are going to swap
6174 with the previous instruction, the two instructions should be
6175 treated as a unit, and the debug information for both instructions
6176 should refer to the start of the branch sequence. Using the
6177 current position is certainly wrong when swapping a 32-bit branch
6178 and a 16-bit delay slot, since the current position would then be
6179 in the middle of a branch. */
6180 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6182 relax32 = (mips_relax_branch
6183 /* Don't try branch relaxation within .set nomacro, or within
6184 .set noat if we use $at for PIC computations. If it turns
6185 out that the branch was out-of-range, we'll get an error. */
6186 && !mips_opts.warn_about_macros
6187 && (mips_opts.at || mips_pic == NO_PIC)
6188 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6189 as they have no complementing branches. */
6190 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6192 if (!HAVE_CODE_COMPRESSION
6195 && *reloc_type == BFD_RELOC_16_PCREL_S2
6196 && delayed_branch_p (ip))
6198 relaxed_branch = TRUE;
6199 add_relaxed_insn (ip, (relaxed_branch_length
6201 uncond_branch_p (ip) ? -1
6202 : branch_likely_p (ip) ? 1
6206 uncond_branch_p (ip),
6207 branch_likely_p (ip),
6208 pinfo & INSN_WRITE_GPR_31,
6210 address_expr->X_add_symbol,
6211 address_expr->X_add_number);
6212 *reloc_type = BFD_RELOC_UNUSED;
6214 else if (mips_opts.micromips
6216 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6217 || *reloc_type > BFD_RELOC_UNUSED)
6218 && (delayed_branch_p (ip) || compact_branch_p (ip))
6219 /* Don't try branch relaxation when users specify
6220 16-bit/32-bit instructions. */
6221 && !forced_insn_length)
6223 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6224 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6225 int uncond = uncond_branch_p (ip) ? -1 : 0;
6226 int compact = compact_branch_p (ip);
6227 int al = pinfo & INSN_WRITE_GPR_31;
6230 gas_assert (address_expr != NULL);
6231 gas_assert (!mips_relax.sequence);
6233 relaxed_branch = TRUE;
6234 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6235 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6236 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6238 address_expr->X_add_symbol,
6239 address_expr->X_add_number);
6240 *reloc_type = BFD_RELOC_UNUSED;
6242 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6244 /* We need to set up a variant frag. */
6245 gas_assert (address_expr != NULL);
6246 add_relaxed_insn (ip, 4, 0,
6248 (*reloc_type - BFD_RELOC_UNUSED,
6249 forced_insn_length == 2, forced_insn_length == 4,
6250 delayed_branch_p (&history[0]),
6251 history[0].mips16_absolute_jump_p),
6252 make_expr_symbol (address_expr), 0);
6254 else if (mips_opts.mips16 && insn_length (ip) == 2)
6256 if (!delayed_branch_p (ip))
6257 /* Make sure there is enough room to swap this instruction with
6258 a following jump instruction. */
6260 add_fixed_insn (ip);
6264 if (mips_opts.mips16
6265 && mips_opts.noreorder
6266 && delayed_branch_p (&history[0]))
6267 as_warn (_("extended instruction in delay slot"));
6269 if (mips_relax.sequence)
6271 /* If we've reached the end of this frag, turn it into a variant
6272 frag and record the information for the instructions we've
6274 if (frag_room () < 4)
6275 relax_close_frag ();
6276 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6279 if (mips_relax.sequence != 2)
6281 if (mips_macro_warning.first_insn_sizes[0] == 0)
6282 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6283 mips_macro_warning.sizes[0] += insn_length (ip);
6284 mips_macro_warning.insns[0]++;
6286 if (mips_relax.sequence != 1)
6288 if (mips_macro_warning.first_insn_sizes[1] == 0)
6289 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6290 mips_macro_warning.sizes[1] += insn_length (ip);
6291 mips_macro_warning.insns[1]++;
6294 if (mips_opts.mips16)
6297 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6299 add_fixed_insn (ip);
6302 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6304 bfd_reloc_code_real_type final_type[3];
6305 reloc_howto_type *howto0;
6306 reloc_howto_type *howto;
6309 /* Perform any necessary conversion to microMIPS relocations
6310 and find out how many relocations there actually are. */
6311 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6312 final_type[i] = micromips_map_reloc (reloc_type[i]);
6314 /* In a compound relocation, it is the final (outermost)
6315 operator that determines the relocated field. */
6316 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6321 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6322 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6323 bfd_get_reloc_size (howto),
6325 howto0 && howto0->pc_relative,
6328 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6329 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6330 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6332 /* These relocations can have an addend that won't fit in
6333 4 octets for 64bit assembly. */
6335 && ! howto->partial_inplace
6336 && (reloc_type[0] == BFD_RELOC_16
6337 || reloc_type[0] == BFD_RELOC_32
6338 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6339 || reloc_type[0] == BFD_RELOC_GPREL16
6340 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6341 || reloc_type[0] == BFD_RELOC_GPREL32
6342 || reloc_type[0] == BFD_RELOC_64
6343 || reloc_type[0] == BFD_RELOC_CTOR
6344 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6345 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6346 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6347 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6348 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6349 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6350 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6351 || hi16_reloc_p (reloc_type[0])
6352 || lo16_reloc_p (reloc_type[0])))
6353 ip->fixp[0]->fx_no_overflow = 1;
6355 /* These relocations can have an addend that won't fit in 2 octets. */
6356 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6357 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6358 ip->fixp[0]->fx_no_overflow = 1;
6360 if (mips_relax.sequence)
6362 if (mips_relax.first_fixup == 0)
6363 mips_relax.first_fixup = ip->fixp[0];
6365 else if (reloc_needs_lo_p (*reloc_type))
6367 struct mips_hi_fixup *hi_fixup;
6369 /* Reuse the last entry if it already has a matching %lo. */
6370 hi_fixup = mips_hi_fixup_list;
6372 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6374 hi_fixup = ((struct mips_hi_fixup *)
6375 xmalloc (sizeof (struct mips_hi_fixup)));
6376 hi_fixup->next = mips_hi_fixup_list;
6377 mips_hi_fixup_list = hi_fixup;
6379 hi_fixup->fixp = ip->fixp[0];
6380 hi_fixup->seg = now_seg;
6383 /* Add fixups for the second and third relocations, if given.
6384 Note that the ABI allows the second relocation to be
6385 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6386 moment we only use RSS_UNDEF, but we could add support
6387 for the others if it ever becomes necessary. */
6388 for (i = 1; i < 3; i++)
6389 if (reloc_type[i] != BFD_RELOC_UNUSED)
6391 ip->fixp[i] = fix_new (ip->frag, ip->where,
6392 ip->fixp[0]->fx_size, NULL, 0,
6393 FALSE, final_type[i]);
6395 /* Use fx_tcbit to mark compound relocs. */
6396 ip->fixp[0]->fx_tcbit = 1;
6397 ip->fixp[i]->fx_tcbit = 1;
6402 /* Update the register mask information. */
6403 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6404 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6409 insert_into_history (0, 1, ip);
6412 case APPEND_ADD_WITH_NOP:
6414 struct mips_cl_insn *nop;
6416 insert_into_history (0, 1, ip);
6417 nop = get_delay_slot_nop (ip);
6418 add_fixed_insn (nop);
6419 insert_into_history (0, 1, nop);
6420 if (mips_relax.sequence)
6421 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6425 case APPEND_ADD_COMPACT:
6426 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6427 gas_assert (mips_opts.mips16);
6428 ip->insn_opcode |= 0x0080;
6429 find_altered_mips16_opcode (ip);
6431 insert_into_history (0, 1, ip);
6436 struct mips_cl_insn delay = history[0];
6437 if (mips_opts.mips16)
6439 know (delay.frag == ip->frag);
6440 move_insn (ip, delay.frag, delay.where);
6441 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6443 else if (relaxed_branch || delay.frag != ip->frag)
6445 /* Add the delay slot instruction to the end of the
6446 current frag and shrink the fixed part of the
6447 original frag. If the branch occupies the tail of
6448 the latter, move it backwards to cover the gap. */
6449 delay.frag->fr_fix -= branch_disp;
6450 if (delay.frag == ip->frag)
6451 move_insn (ip, ip->frag, ip->where - branch_disp);
6452 add_fixed_insn (&delay);
6456 move_insn (&delay, ip->frag,
6457 ip->where - branch_disp + insn_length (ip));
6458 move_insn (ip, history[0].frag, history[0].where);
6462 insert_into_history (0, 1, &delay);
6467 /* If we have just completed an unconditional branch, clear the history. */
6468 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6469 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6473 mips_no_prev_insn ();
6475 for (i = 0; i < ARRAY_SIZE (history); i++)
6476 history[i].cleared_p = 1;
6479 /* We need to emit a label at the end of branch-likely macros. */
6480 if (emit_branch_likely_macro)
6482 emit_branch_likely_macro = FALSE;
6483 micromips_add_label ();
6486 /* We just output an insn, so the next one doesn't have a label. */
6487 mips_clear_insn_labels ();
6490 /* Forget that there was any previous instruction or label.
6491 When BRANCH is true, the branch history is also flushed. */
6494 mips_no_prev_insn (void)
6496 prev_nop_frag = NULL;
6497 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6498 mips_clear_insn_labels ();
6501 /* This function must be called before we emit something other than
6502 instructions. It is like mips_no_prev_insn except that it inserts
6503 any NOPS that might be needed by previous instructions. */
6506 mips_emit_delays (void)
6508 if (! mips_opts.noreorder)
6510 int nops = nops_for_insn (0, history, NULL);
6514 add_fixed_insn (NOP_INSN);
6515 mips_move_text_labels ();
6518 mips_no_prev_insn ();
6521 /* Start a (possibly nested) noreorder block. */
6524 start_noreorder (void)
6526 if (mips_opts.noreorder == 0)
6531 /* None of the instructions before the .set noreorder can be moved. */
6532 for (i = 0; i < ARRAY_SIZE (history); i++)
6533 history[i].fixed_p = 1;
6535 /* Insert any nops that might be needed between the .set noreorder
6536 block and the previous instructions. We will later remove any
6537 nops that turn out not to be needed. */
6538 nops = nops_for_insn (0, history, NULL);
6541 if (mips_optimize != 0)
6543 /* Record the frag which holds the nop instructions, so
6544 that we can remove them if we don't need them. */
6545 frag_grow (nops * NOP_INSN_SIZE);
6546 prev_nop_frag = frag_now;
6547 prev_nop_frag_holds = nops;
6548 prev_nop_frag_required = 0;
6549 prev_nop_frag_since = 0;
6552 for (; nops > 0; --nops)
6553 add_fixed_insn (NOP_INSN);
6555 /* Move on to a new frag, so that it is safe to simply
6556 decrease the size of prev_nop_frag. */
6557 frag_wane (frag_now);
6559 mips_move_text_labels ();
6561 mips_mark_labels ();
6562 mips_clear_insn_labels ();
6564 mips_opts.noreorder++;
6565 mips_any_noreorder = 1;
6568 /* End a nested noreorder block. */
6571 end_noreorder (void)
6573 mips_opts.noreorder--;
6574 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6576 /* Commit to inserting prev_nop_frag_required nops and go back to
6577 handling nop insertion the .set reorder way. */
6578 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
6580 insert_into_history (prev_nop_frag_since,
6581 prev_nop_frag_required, NOP_INSN);
6582 prev_nop_frag = NULL;
6586 /* Set up global variables for the start of a new macro. */
6591 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
6592 memset (&mips_macro_warning.first_insn_sizes, 0,
6593 sizeof (mips_macro_warning.first_insn_sizes));
6594 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
6595 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
6596 && delayed_branch_p (&history[0]));
6597 switch (history[0].insn_mo->pinfo2
6598 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
6600 case INSN2_BRANCH_DELAY_32BIT:
6601 mips_macro_warning.delay_slot_length = 4;
6603 case INSN2_BRANCH_DELAY_16BIT:
6604 mips_macro_warning.delay_slot_length = 2;
6607 mips_macro_warning.delay_slot_length = 0;
6610 mips_macro_warning.first_frag = NULL;
6613 /* Given that a macro is longer than one instruction or of the wrong size,
6614 return the appropriate warning for it. Return null if no warning is
6615 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6616 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6617 and RELAX_NOMACRO. */
6620 macro_warning (relax_substateT subtype)
6622 if (subtype & RELAX_DELAY_SLOT)
6623 return _("Macro instruction expanded into multiple instructions"
6624 " in a branch delay slot");
6625 else if (subtype & RELAX_NOMACRO)
6626 return _("Macro instruction expanded into multiple instructions");
6627 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
6628 | RELAX_DELAY_SLOT_SIZE_SECOND))
6629 return ((subtype & RELAX_DELAY_SLOT_16BIT)
6630 ? _("Macro instruction expanded into a wrong size instruction"
6631 " in a 16-bit branch delay slot")
6632 : _("Macro instruction expanded into a wrong size instruction"
6633 " in a 32-bit branch delay slot"));
6638 /* Finish up a macro. Emit warnings as appropriate. */
6643 /* Relaxation warning flags. */
6644 relax_substateT subtype = 0;
6646 /* Check delay slot size requirements. */
6647 if (mips_macro_warning.delay_slot_length == 2)
6648 subtype |= RELAX_DELAY_SLOT_16BIT;
6649 if (mips_macro_warning.delay_slot_length != 0)
6651 if (mips_macro_warning.delay_slot_length
6652 != mips_macro_warning.first_insn_sizes[0])
6653 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
6654 if (mips_macro_warning.delay_slot_length
6655 != mips_macro_warning.first_insn_sizes[1])
6656 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
6659 /* Check instruction count requirements. */
6660 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
6662 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
6663 subtype |= RELAX_SECOND_LONGER;
6664 if (mips_opts.warn_about_macros)
6665 subtype |= RELAX_NOMACRO;
6666 if (mips_macro_warning.delay_slot_p)
6667 subtype |= RELAX_DELAY_SLOT;
6670 /* If both alternatives fail to fill a delay slot correctly,
6671 emit the warning now. */
6672 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
6673 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
6678 s = subtype & (RELAX_DELAY_SLOT_16BIT
6679 | RELAX_DELAY_SLOT_SIZE_FIRST
6680 | RELAX_DELAY_SLOT_SIZE_SECOND);
6681 msg = macro_warning (s);
6683 as_warn ("%s", msg);
6687 /* If both implementations are longer than 1 instruction, then emit the
6689 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
6694 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
6695 msg = macro_warning (s);
6697 as_warn ("%s", msg);
6701 /* If any flags still set, then one implementation might need a warning
6702 and the other either will need one of a different kind or none at all.
6703 Pass any remaining flags over to relaxation. */
6704 if (mips_macro_warning.first_frag != NULL)
6705 mips_macro_warning.first_frag->fr_subtype |= subtype;
6708 /* Instruction operand formats used in macros that vary between
6709 standard MIPS and microMIPS code. */
6711 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
6712 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
6713 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
6714 static const char * const lui_fmt[2] = { "t,u", "s,u" };
6715 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
6716 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
6717 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
6718 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
6720 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6721 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6722 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6723 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6724 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6725 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6726 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6727 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6729 /* Read a macro's relocation codes from *ARGS and store them in *R.
6730 The first argument in *ARGS will be either the code for a single
6731 relocation or -1 followed by the three codes that make up a
6732 composite relocation. */
6735 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
6739 next = va_arg (*args, int);
6741 r[0] = (bfd_reloc_code_real_type) next;
6744 for (i = 0; i < 3; i++)
6745 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
6746 /* This function is only used for 16-bit relocation fields.
6747 To make the macro code simpler, treat an unrelocated value
6748 in the same way as BFD_RELOC_LO16. */
6749 if (r[0] == BFD_RELOC_UNUSED)
6750 r[0] = BFD_RELOC_LO16;
6754 /* Build an instruction created by a macro expansion. This is passed
6755 a pointer to the count of instructions created so far, an
6756 expression, the name of the instruction to build, an operand format
6757 string, and corresponding arguments. */
6760 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
6762 const struct mips_opcode *mo = NULL;
6763 bfd_reloc_code_real_type r[3];
6764 const struct mips_opcode *amo;
6765 const struct mips_operand *operand;
6766 struct hash_control *hash;
6767 struct mips_cl_insn insn;
6771 va_start (args, fmt);
6773 if (mips_opts.mips16)
6775 mips16_macro_build (ep, name, fmt, &args);
6780 r[0] = BFD_RELOC_UNUSED;
6781 r[1] = BFD_RELOC_UNUSED;
6782 r[2] = BFD_RELOC_UNUSED;
6783 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
6784 amo = (struct mips_opcode *) hash_find (hash, name);
6786 gas_assert (strcmp (name, amo->name) == 0);
6790 /* Search until we get a match for NAME. It is assumed here that
6791 macros will never generate MDMX, MIPS-3D, or MT instructions.
6792 We try to match an instruction that fulfils the branch delay
6793 slot instruction length requirement (if any) of the previous
6794 instruction. While doing this we record the first instruction
6795 seen that matches all the other conditions and use it anyway
6796 if the requirement cannot be met; we will issue an appropriate
6797 warning later on. */
6798 if (strcmp (fmt, amo->args) == 0
6799 && amo->pinfo != INSN_MACRO
6800 && is_opcode_valid (amo)
6801 && is_size_valid (amo))
6803 if (is_delay_slot_valid (amo))
6813 gas_assert (amo->name);
6815 while (strcmp (name, amo->name) == 0);
6818 create_insn (&insn, mo);
6831 macro_read_relocs (&args, r);
6832 gas_assert (*r == BFD_RELOC_GPREL16
6833 || *r == BFD_RELOC_MIPS_HIGHER
6834 || *r == BFD_RELOC_HI16_S
6835 || *r == BFD_RELOC_LO16
6836 || *r == BFD_RELOC_MIPS_GOT_OFST);
6840 macro_read_relocs (&args, r);
6844 macro_read_relocs (&args, r);
6845 gas_assert (ep != NULL
6846 && (ep->X_op == O_constant
6847 || (ep->X_op == O_symbol
6848 && (*r == BFD_RELOC_MIPS_HIGHEST
6849 || *r == BFD_RELOC_HI16_S
6850 || *r == BFD_RELOC_HI16
6851 || *r == BFD_RELOC_GPREL16
6852 || *r == BFD_RELOC_MIPS_GOT_HI16
6853 || *r == BFD_RELOC_MIPS_CALL_HI16))));
6857 gas_assert (ep != NULL);
6860 * This allows macro() to pass an immediate expression for
6861 * creating short branches without creating a symbol.
6863 * We don't allow branch relaxation for these branches, as
6864 * they should only appear in ".set nomacro" anyway.
6866 if (ep->X_op == O_constant)
6868 /* For microMIPS we always use relocations for branches.
6869 So we should not resolve immediate values. */
6870 gas_assert (!mips_opts.micromips);
6872 if ((ep->X_add_number & 3) != 0)
6873 as_bad (_("branch to misaligned address (0x%lx)"),
6874 (unsigned long) ep->X_add_number);
6875 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
6876 as_bad (_("branch address range overflow (0x%lx)"),
6877 (unsigned long) ep->X_add_number);
6878 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
6882 *r = BFD_RELOC_16_PCREL_S2;
6886 gas_assert (ep != NULL);
6887 *r = BFD_RELOC_MIPS_JMP;
6891 operand = (mips_opts.micromips
6892 ? decode_micromips_operand (fmt)
6893 : decode_mips_operand (fmt));
6897 uval = va_arg (args, int);
6898 if (operand->type == OP_CLO_CLZ_DEST)
6899 uval |= (uval << 5);
6900 insn_insert_operand (&insn, operand, uval);
6902 if (*fmt == '+' || *fmt == 'm')
6908 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6910 append_insn (&insn, ep, r, TRUE);
6914 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
6917 struct mips_opcode *mo;
6918 struct mips_cl_insn insn;
6919 const struct mips_operand *operand;
6920 bfd_reloc_code_real_type r[3]
6921 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
6923 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
6925 gas_assert (strcmp (name, mo->name) == 0);
6927 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
6930 gas_assert (mo->name);
6931 gas_assert (strcmp (name, mo->name) == 0);
6934 create_insn (&insn, mo);
6972 gas_assert (ep != NULL);
6974 if (ep->X_op != O_constant)
6975 *r = (int) BFD_RELOC_UNUSED + c;
6976 else if (calculate_reloc (*r, ep->X_add_number, &value))
6978 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
6980 *r = BFD_RELOC_UNUSED;
6986 operand = decode_mips16_operand (c, FALSE);
6990 insn_insert_operand (&insn, operand, va_arg (*args, int));
6995 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6997 append_insn (&insn, ep, r, TRUE);
7001 * Sign-extend 32-bit mode constants that have bit 31 set and all
7002 * higher bits unset.
7005 normalize_constant_expr (expressionS *ex)
7007 if (ex->X_op == O_constant
7008 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7009 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7014 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7015 * all higher bits unset.
7018 normalize_address_expr (expressionS *ex)
7020 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7021 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7022 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7023 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7028 * Generate a "jalr" instruction with a relocation hint to the called
7029 * function. This occurs in NewABI PIC code.
7032 macro_build_jalr (expressionS *ep, int cprestore)
7034 static const bfd_reloc_code_real_type jalr_relocs[2]
7035 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7036 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7040 if (MIPS_JALR_HINT_P (ep))
7045 if (mips_opts.micromips)
7047 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7048 ? "jalr" : "jalrs");
7049 if (MIPS_JALR_HINT_P (ep)
7051 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7052 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7054 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7057 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7058 if (MIPS_JALR_HINT_P (ep))
7059 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7063 * Generate a "lui" instruction.
7066 macro_build_lui (expressionS *ep, int regnum)
7068 gas_assert (! mips_opts.mips16);
7070 if (ep->X_op != O_constant)
7072 gas_assert (ep->X_op == O_symbol);
7073 /* _gp_disp is a special case, used from s_cpload.
7074 __gnu_local_gp is used if mips_no_shared. */
7075 gas_assert (mips_pic == NO_PIC
7077 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7078 || (! mips_in_shared
7079 && strcmp (S_GET_NAME (ep->X_add_symbol),
7080 "__gnu_local_gp") == 0));
7083 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7086 /* Generate a sequence of instructions to do a load or store from a constant
7087 offset off of a base register (breg) into/from a target register (treg),
7088 using AT if necessary. */
7090 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7091 int treg, int breg, int dbl)
7093 gas_assert (ep->X_op == O_constant);
7095 /* Sign-extending 32-bit constants makes their handling easier. */
7097 normalize_constant_expr (ep);
7099 /* Right now, this routine can only handle signed 32-bit constants. */
7100 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7101 as_warn (_("operand overflow"));
7103 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7105 /* Signed 16-bit offset will fit in the op. Easy! */
7106 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7110 /* 32-bit offset, need multiple instructions and AT, like:
7111 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7112 addu $tempreg,$tempreg,$breg
7113 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7114 to handle the complete offset. */
7115 macro_build_lui (ep, AT);
7116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7117 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7120 as_bad (_("Macro used $at after \".set noat\""));
7125 * Generates code to set the $at register to true (one)
7126 * if reg is less than the immediate expression.
7129 set_at (int reg, int unsignedp)
7131 if (imm_expr.X_op == O_constant
7132 && imm_expr.X_add_number >= -0x8000
7133 && imm_expr.X_add_number < 0x8000)
7134 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
7135 AT, reg, BFD_RELOC_LO16);
7138 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7139 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
7143 /* Count the leading zeroes by performing a binary chop. This is a
7144 bulky bit of source, but performance is a LOT better for the
7145 majority of values than a simple loop to count the bits:
7146 for (lcnt = 0; (lcnt < 32); lcnt++)
7147 if ((v) & (1 << (31 - lcnt)))
7149 However it is not code size friendly, and the gain will drop a bit
7150 on certain cached systems.
7152 #define COUNT_TOP_ZEROES(v) \
7153 (((v) & ~0xffff) == 0 \
7154 ? ((v) & ~0xff) == 0 \
7155 ? ((v) & ~0xf) == 0 \
7156 ? ((v) & ~0x3) == 0 \
7157 ? ((v) & ~0x1) == 0 \
7162 : ((v) & ~0x7) == 0 \
7165 : ((v) & ~0x3f) == 0 \
7166 ? ((v) & ~0x1f) == 0 \
7169 : ((v) & ~0x7f) == 0 \
7172 : ((v) & ~0xfff) == 0 \
7173 ? ((v) & ~0x3ff) == 0 \
7174 ? ((v) & ~0x1ff) == 0 \
7177 : ((v) & ~0x7ff) == 0 \
7180 : ((v) & ~0x3fff) == 0 \
7181 ? ((v) & ~0x1fff) == 0 \
7184 : ((v) & ~0x7fff) == 0 \
7187 : ((v) & ~0xffffff) == 0 \
7188 ? ((v) & ~0xfffff) == 0 \
7189 ? ((v) & ~0x3ffff) == 0 \
7190 ? ((v) & ~0x1ffff) == 0 \
7193 : ((v) & ~0x7ffff) == 0 \
7196 : ((v) & ~0x3fffff) == 0 \
7197 ? ((v) & ~0x1fffff) == 0 \
7200 : ((v) & ~0x7fffff) == 0 \
7203 : ((v) & ~0xfffffff) == 0 \
7204 ? ((v) & ~0x3ffffff) == 0 \
7205 ? ((v) & ~0x1ffffff) == 0 \
7208 : ((v) & ~0x7ffffff) == 0 \
7211 : ((v) & ~0x3fffffff) == 0 \
7212 ? ((v) & ~0x1fffffff) == 0 \
7215 : ((v) & ~0x7fffffff) == 0 \
7220 * This routine generates the least number of instructions necessary to load
7221 * an absolute expression value into a register.
7224 load_register (int reg, expressionS *ep, int dbl)
7227 expressionS hi32, lo32;
7229 if (ep->X_op != O_big)
7231 gas_assert (ep->X_op == O_constant);
7233 /* Sign-extending 32-bit constants makes their handling easier. */
7235 normalize_constant_expr (ep);
7237 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
7239 /* We can handle 16 bit signed values with an addiu to
7240 $zero. No need to ever use daddiu here, since $zero and
7241 the result are always correct in 32 bit mode. */
7242 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7245 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
7247 /* We can handle 16 bit unsigned values with an ori to
7249 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7252 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
7254 /* 32 bit values require an lui. */
7255 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7256 if ((ep->X_add_number & 0xffff) != 0)
7257 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7262 /* The value is larger than 32 bits. */
7264 if (!dbl || HAVE_32BIT_GPRS)
7268 sprintf_vma (value, ep->X_add_number);
7269 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7270 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7274 if (ep->X_op != O_big)
7277 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7278 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7279 hi32.X_add_number &= 0xffffffff;
7281 lo32.X_add_number &= 0xffffffff;
7285 gas_assert (ep->X_add_number > 2);
7286 if (ep->X_add_number == 3)
7287 generic_bignum[3] = 0;
7288 else if (ep->X_add_number > 4)
7289 as_bad (_("Number larger than 64 bits"));
7290 lo32.X_op = O_constant;
7291 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
7292 hi32.X_op = O_constant;
7293 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
7296 if (hi32.X_add_number == 0)
7301 unsigned long hi, lo;
7303 if (hi32.X_add_number == (offsetT) 0xffffffff)
7305 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
7307 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7310 if (lo32.X_add_number & 0x80000000)
7312 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7313 if (lo32.X_add_number & 0xffff)
7314 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7319 /* Check for 16bit shifted constant. We know that hi32 is
7320 non-zero, so start the mask on the first bit of the hi32
7325 unsigned long himask, lomask;
7329 himask = 0xffff >> (32 - shift);
7330 lomask = (0xffff << shift) & 0xffffffff;
7334 himask = 0xffff << (shift - 32);
7337 if ((hi32.X_add_number & ~(offsetT) himask) == 0
7338 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
7342 tmp.X_op = O_constant;
7344 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
7345 | (lo32.X_add_number >> shift));
7347 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
7348 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7349 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7350 reg, reg, (shift >= 32) ? shift - 32 : shift);
7355 while (shift <= (64 - 16));
7357 /* Find the bit number of the lowest one bit, and store the
7358 shifted value in hi/lo. */
7359 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
7360 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
7364 while ((lo & 1) == 0)
7369 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
7375 while ((hi & 1) == 0)
7384 /* Optimize if the shifted value is a (power of 2) - 1. */
7385 if ((hi == 0 && ((lo + 1) & lo) == 0)
7386 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
7388 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
7393 /* This instruction will set the register to be all
7395 tmp.X_op = O_constant;
7396 tmp.X_add_number = (offsetT) -1;
7397 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7401 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7402 reg, reg, (bit >= 32) ? bit - 32 : bit);
7404 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
7405 reg, reg, (shift >= 32) ? shift - 32 : shift);
7410 /* Sign extend hi32 before calling load_register, because we can
7411 generally get better code when we load a sign extended value. */
7412 if ((hi32.X_add_number & 0x80000000) != 0)
7413 hi32.X_add_number |= ~(offsetT) 0xffffffff;
7414 load_register (reg, &hi32, 0);
7417 if ((lo32.X_add_number & 0xffff0000) == 0)
7421 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
7429 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
7431 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7432 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
7438 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
7442 mid16.X_add_number >>= 16;
7443 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7444 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7447 if ((lo32.X_add_number & 0xffff) != 0)
7448 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7452 load_delay_nop (void)
7454 if (!gpr_interlocks)
7455 macro_build (NULL, "nop", "");
7458 /* Load an address into a register. */
7461 load_address (int reg, expressionS *ep, int *used_at)
7463 if (ep->X_op != O_constant
7464 && ep->X_op != O_symbol)
7466 as_bad (_("expression too complex"));
7467 ep->X_op = O_constant;
7470 if (ep->X_op == O_constant)
7472 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
7476 if (mips_pic == NO_PIC)
7478 /* If this is a reference to a GP relative symbol, we want
7479 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7481 lui $reg,<sym> (BFD_RELOC_HI16_S)
7482 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7483 If we have an addend, we always use the latter form.
7485 With 64bit address space and a usable $at we want
7486 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7487 lui $at,<sym> (BFD_RELOC_HI16_S)
7488 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7489 daddiu $at,<sym> (BFD_RELOC_LO16)
7493 If $at is already in use, we use a path which is suboptimal
7494 on superscalar processors.
7495 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7496 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7498 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7500 daddiu $reg,<sym> (BFD_RELOC_LO16)
7502 For GP relative symbols in 64bit address space we can use
7503 the same sequence as in 32bit address space. */
7504 if (HAVE_64BIT_SYMBOLS)
7506 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7507 && !nopic_need_relax (ep->X_add_symbol, 1))
7509 relax_start (ep->X_add_symbol);
7510 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7511 mips_gp_register, BFD_RELOC_GPREL16);
7515 if (*used_at == 0 && mips_opts.at)
7517 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7518 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
7519 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7520 BFD_RELOC_MIPS_HIGHER);
7521 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
7522 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
7523 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
7528 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7529 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7530 BFD_RELOC_MIPS_HIGHER);
7531 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7532 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
7533 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7534 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
7537 if (mips_relax.sequence)
7542 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7543 && !nopic_need_relax (ep->X_add_symbol, 1))
7545 relax_start (ep->X_add_symbol);
7546 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7547 mips_gp_register, BFD_RELOC_GPREL16);
7550 macro_build_lui (ep, reg);
7551 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
7552 reg, reg, BFD_RELOC_LO16);
7553 if (mips_relax.sequence)
7557 else if (!mips_big_got)
7561 /* If this is a reference to an external symbol, we want
7562 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7564 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7566 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7567 If there is a constant, it must be added in after.
7569 If we have NewABI, we want
7570 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7571 unless we're referencing a global symbol with a non-zero
7572 offset, in which case cst must be added separately. */
7575 if (ep->X_add_number)
7577 ex.X_add_number = ep->X_add_number;
7578 ep->X_add_number = 0;
7579 relax_start (ep->X_add_symbol);
7580 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7581 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7582 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7583 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7584 ex.X_op = O_constant;
7585 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7586 reg, reg, BFD_RELOC_LO16);
7587 ep->X_add_number = ex.X_add_number;
7590 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7591 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7592 if (mips_relax.sequence)
7597 ex.X_add_number = ep->X_add_number;
7598 ep->X_add_number = 0;
7599 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7600 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7602 relax_start (ep->X_add_symbol);
7604 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7608 if (ex.X_add_number != 0)
7610 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7611 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7612 ex.X_op = O_constant;
7613 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7614 reg, reg, BFD_RELOC_LO16);
7618 else if (mips_big_got)
7622 /* This is the large GOT case. If this is a reference to an
7623 external symbol, we want
7624 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7626 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7628 Otherwise, for a reference to a local symbol in old ABI, we want
7629 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7631 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7632 If there is a constant, it must be added in after.
7634 In the NewABI, for local symbols, with or without offsets, we want:
7635 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7636 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7640 ex.X_add_number = ep->X_add_number;
7641 ep->X_add_number = 0;
7642 relax_start (ep->X_add_symbol);
7643 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7644 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7645 reg, reg, mips_gp_register);
7646 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7647 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7648 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7649 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7650 else if (ex.X_add_number)
7652 ex.X_op = O_constant;
7653 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7657 ep->X_add_number = ex.X_add_number;
7659 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7660 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7661 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7662 BFD_RELOC_MIPS_GOT_OFST);
7667 ex.X_add_number = ep->X_add_number;
7668 ep->X_add_number = 0;
7669 relax_start (ep->X_add_symbol);
7670 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7671 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7672 reg, reg, mips_gp_register);
7673 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7674 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7676 if (reg_needs_delay (mips_gp_register))
7678 /* We need a nop before loading from $gp. This special
7679 check is required because the lui which starts the main
7680 instruction stream does not refer to $gp, and so will not
7681 insert the nop which may be required. */
7682 macro_build (NULL, "nop", "");
7684 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7685 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7687 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7691 if (ex.X_add_number != 0)
7693 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7694 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7695 ex.X_op = O_constant;
7696 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7704 if (!mips_opts.at && *used_at == 1)
7705 as_bad (_("Macro used $at after \".set noat\""));
7708 /* Move the contents of register SOURCE into register DEST. */
7711 move_register (int dest, int source)
7713 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7714 instruction specifically requires a 32-bit one. */
7715 if (mips_opts.micromips
7716 && !mips_opts.insn32
7717 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7718 macro_build (NULL, "move", "mp,mj", dest, source);
7720 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
7724 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7725 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7726 The two alternatives are:
7728 Global symbol Local sybmol
7729 ------------- ------------
7730 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7732 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7734 load_got_offset emits the first instruction and add_got_offset
7735 emits the second for a 16-bit offset or add_got_offset_hilo emits
7736 a sequence to add a 32-bit offset using a scratch register. */
7739 load_got_offset (int dest, expressionS *local)
7744 global.X_add_number = 0;
7746 relax_start (local->X_add_symbol);
7747 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7748 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7750 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7751 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7756 add_got_offset (int dest, expressionS *local)
7760 global.X_op = O_constant;
7761 global.X_op_symbol = NULL;
7762 global.X_add_symbol = NULL;
7763 global.X_add_number = local->X_add_number;
7765 relax_start (local->X_add_symbol);
7766 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
7767 dest, dest, BFD_RELOC_LO16);
7769 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
7774 add_got_offset_hilo (int dest, expressionS *local, int tmp)
7777 int hold_mips_optimize;
7779 global.X_op = O_constant;
7780 global.X_op_symbol = NULL;
7781 global.X_add_symbol = NULL;
7782 global.X_add_number = local->X_add_number;
7784 relax_start (local->X_add_symbol);
7785 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
7787 /* Set mips_optimize around the lui instruction to avoid
7788 inserting an unnecessary nop after the lw. */
7789 hold_mips_optimize = mips_optimize;
7791 macro_build_lui (&global, tmp);
7792 mips_optimize = hold_mips_optimize;
7793 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
7796 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
7799 /* Emit a sequence of instructions to emulate a branch likely operation.
7800 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7801 is its complementing branch with the original condition negated.
7802 CALL is set if the original branch specified the link operation.
7803 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7805 Code like this is produced in the noreorder mode:
7810 delay slot (executed only if branch taken)
7818 delay slot (executed only if branch taken)
7821 In the reorder mode the delay slot would be filled with a nop anyway,
7822 so code produced is simply:
7827 This function is used when producing code for the microMIPS ASE that
7828 does not implement branch likely instructions in hardware. */
7831 macro_build_branch_likely (const char *br, const char *brneg,
7832 int call, expressionS *ep, const char *fmt,
7833 unsigned int sreg, unsigned int treg)
7835 int noreorder = mips_opts.noreorder;
7838 gas_assert (mips_opts.micromips);
7842 micromips_label_expr (&expr1);
7843 macro_build (&expr1, brneg, fmt, sreg, treg);
7844 macro_build (NULL, "nop", "");
7845 macro_build (ep, call ? "bal" : "b", "p");
7847 /* Set to true so that append_insn adds a label. */
7848 emit_branch_likely_macro = TRUE;
7852 macro_build (ep, br, fmt, sreg, treg);
7853 macro_build (NULL, "nop", "");
7858 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7859 the condition code tested. EP specifies the branch target. */
7862 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
7889 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
7892 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7893 the register tested. EP specifies the branch target. */
7896 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
7898 const char *brneg = NULL;
7908 br = mips_opts.micromips ? "bgez" : "bgezl";
7912 gas_assert (mips_opts.micromips);
7913 br = mips_opts.insn32 ? "bgezal" : "bgezals";
7921 br = mips_opts.micromips ? "bgtz" : "bgtzl";
7928 br = mips_opts.micromips ? "blez" : "blezl";
7935 br = mips_opts.micromips ? "bltz" : "bltzl";
7939 gas_assert (mips_opts.micromips);
7940 br = mips_opts.insn32 ? "bltzal" : "bltzals";
7947 if (mips_opts.micromips && brneg)
7948 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
7950 macro_build (ep, br, "s,p", sreg);
7953 /* Emit a three-argument branch macro specified by TYPE, using SREG and
7954 TREG as the registers tested. EP specifies the branch target. */
7957 macro_build_branch_rsrt (int type, expressionS *ep,
7958 unsigned int sreg, unsigned int treg)
7960 const char *brneg = NULL;
7972 br = mips_opts.micromips ? "beq" : "beql";
7981 br = mips_opts.micromips ? "bne" : "bnel";
7987 if (mips_opts.micromips && brneg)
7988 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
7990 macro_build (ep, br, "s,t,p", sreg, treg);
7993 /* Return the high part that should be loaded in order to make the low
7994 part of VALUE accessible using an offset of OFFBITS bits. */
7997 offset_high_part (offsetT value, unsigned int offbits)
8004 bias = 1 << (offbits - 1);
8005 low_mask = bias * 2 - 1;
8006 return (value + bias) & ~low_mask;
8009 /* Return true if the value stored in offset_expr and offset_reloc
8010 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8011 amount that the caller wants to add without inducing overflow
8012 and ALIGN is the known alignment of the value in bytes. */
8015 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8019 /* Accept any relocation operator if overflow isn't a concern. */
8020 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8023 /* These relocations are guaranteed not to overflow in correct links. */
8024 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8025 || gprel16_reloc_p (*offset_reloc))
8028 if (offset_expr.X_op == O_constant
8029 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8030 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8037 * This routine implements the seemingly endless macro or synthesized
8038 * instructions and addressing modes in the mips assembly language. Many
8039 * of these macros are simple and are similar to each other. These could
8040 * probably be handled by some kind of table or grammar approach instead of
8041 * this verbose method. Others are not simple macros but are more like
8042 * optimizing code generation.
8043 * One interesting optimization is when several store macros appear
8044 * consecutively that would load AT with the upper half of the same address.
8045 * The ensuing load upper instructions are ommited. This implies some kind
8046 * of global optimization. We currently only optimize within a single macro.
8047 * For many of the load and store macros if the address is specified as a
8048 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8049 * first load register 'at' with zero and use it as the base register. The
8050 * mips assembler simply uses register $zero. Just one tiny optimization
8054 macro (struct mips_cl_insn *ip, char *str)
8056 unsigned int treg, sreg, dreg, breg;
8057 unsigned int tempreg;
8060 expressionS label_expr;
8075 bfd_boolean large_offset;
8077 int hold_mips_optimize;
8080 gas_assert (! mips_opts.mips16);
8082 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
8083 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
8084 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
8085 mask = ip->insn_mo->mask;
8087 label_expr.X_op = O_constant;
8088 label_expr.X_op_symbol = NULL;
8089 label_expr.X_add_symbol = NULL;
8090 label_expr.X_add_number = 0;
8092 expr1.X_op = O_constant;
8093 expr1.X_op_symbol = NULL;
8094 expr1.X_add_symbol = NULL;
8095 expr1.X_add_number = 1;
8111 if (mips_opts.micromips)
8112 micromips_label_expr (&label_expr);
8114 label_expr.X_add_number = 8;
8115 macro_build (&label_expr, "bgez", "s,p", sreg);
8117 macro_build (NULL, "nop", "");
8119 move_register (dreg, sreg);
8120 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
8121 if (mips_opts.micromips)
8122 micromips_add_label ();
8139 if (!mips_opts.micromips)
8141 if (imm_expr.X_op == O_constant
8142 && imm_expr.X_add_number >= -0x200
8143 && imm_expr.X_add_number < 0x200)
8145 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
8154 if (imm_expr.X_op == O_constant
8155 && imm_expr.X_add_number >= -0x8000
8156 && imm_expr.X_add_number < 0x8000)
8158 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
8163 load_register (AT, &imm_expr, dbl);
8164 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
8183 if (imm_expr.X_op == O_constant
8184 && imm_expr.X_add_number >= 0
8185 && imm_expr.X_add_number < 0x10000)
8187 if (mask != M_NOR_I)
8188 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
8191 macro_build (&imm_expr, "ori", "t,r,i",
8192 treg, sreg, BFD_RELOC_LO16);
8193 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
8199 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8200 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
8204 switch (imm_expr.X_add_number)
8207 macro_build (NULL, "nop", "");
8210 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
8214 macro_build (NULL, "balign", "t,s,2", treg, sreg,
8215 (int) imm_expr.X_add_number);
8218 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8219 (unsigned long) imm_expr.X_add_number);
8228 gas_assert (mips_opts.micromips);
8229 macro_build_branch_ccl (mask, &offset_expr,
8230 EXTRACT_OPERAND (1, BCC, *ip));
8237 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8243 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
8248 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
8255 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
8257 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
8261 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8262 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8263 &offset_expr, AT, ZERO);
8273 macro_build_branch_rs (mask, &offset_expr, sreg);
8279 /* Check for > max integer. */
8280 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8283 /* Result is always false. */
8285 macro_build (NULL, "nop", "");
8287 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8290 if (imm_expr.X_op != O_constant)
8291 as_bad (_("Unsupported large constant"));
8292 ++imm_expr.X_add_number;
8296 if (mask == M_BGEL_I)
8298 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8300 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
8301 &offset_expr, sreg);
8304 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8306 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
8307 &offset_expr, sreg);
8310 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
8313 /* result is always true */
8314 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
8315 macro_build (&offset_expr, "b", "p");
8320 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8321 &offset_expr, AT, ZERO);
8330 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8331 &offset_expr, ZERO, treg);
8335 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8336 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8337 &offset_expr, AT, ZERO);
8346 && imm_expr.X_op == O_constant
8347 && imm_expr.X_add_number == -1))
8349 if (imm_expr.X_op != O_constant)
8350 as_bad (_("Unsupported large constant"));
8351 ++imm_expr.X_add_number;
8355 if (mask == M_BGEUL_I)
8357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8359 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8360 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8361 &offset_expr, sreg, ZERO);
8366 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8367 &offset_expr, AT, ZERO);
8375 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
8377 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
8381 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8382 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8383 &offset_expr, AT, ZERO);
8391 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8392 &offset_expr, sreg, ZERO);
8398 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8399 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8400 &offset_expr, AT, ZERO);
8408 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8410 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
8414 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8415 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8416 &offset_expr, AT, ZERO);
8423 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8425 if (imm_expr.X_op != O_constant)
8426 as_bad (_("Unsupported large constant"));
8427 ++imm_expr.X_add_number;
8431 if (mask == M_BLTL_I)
8433 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8434 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8435 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8436 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8441 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8442 &offset_expr, AT, ZERO);
8450 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8451 &offset_expr, sreg, ZERO);
8457 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8458 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8459 &offset_expr, AT, ZERO);
8468 && imm_expr.X_op == O_constant
8469 && imm_expr.X_add_number == -1))
8471 if (imm_expr.X_op != O_constant)
8472 as_bad (_("Unsupported large constant"));
8473 ++imm_expr.X_add_number;
8477 if (mask == M_BLTUL_I)
8479 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8481 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8482 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8483 &offset_expr, sreg, ZERO);
8488 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8489 &offset_expr, AT, ZERO);
8497 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8499 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
8503 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8504 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8505 &offset_expr, AT, ZERO);
8515 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8516 &offset_expr, ZERO, treg);
8520 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8521 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8522 &offset_expr, AT, ZERO);
8528 /* Use unsigned arithmetic. */
8532 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8534 as_bad (_("Unsupported large constant"));
8539 pos = imm_expr.X_add_number;
8540 size = imm2_expr.X_add_number;
8545 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8548 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8550 report_bad_field (pos, size);
8554 if (size <= 32 && pos < 32)
8559 else if (size <= 32)
8569 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8576 /* Use unsigned arithmetic. */
8580 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8582 as_bad (_("Unsupported large constant"));
8587 pos = imm_expr.X_add_number;
8588 size = imm2_expr.X_add_number;
8593 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8596 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8598 report_bad_field (pos, size);
8602 if (pos < 32 && (pos + size - 1) < 32)
8617 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8618 (int) (pos + size - 1));
8634 as_warn (_("Divide by zero."));
8636 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8638 macro_build (NULL, "break", BRK_FMT, 7);
8645 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8646 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8650 if (mips_opts.micromips)
8651 micromips_label_expr (&label_expr);
8653 label_expr.X_add_number = 8;
8654 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8655 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8656 macro_build (NULL, "break", BRK_FMT, 7);
8657 if (mips_opts.micromips)
8658 micromips_add_label ();
8660 expr1.X_add_number = -1;
8662 load_register (AT, &expr1, dbl);
8663 if (mips_opts.micromips)
8664 micromips_label_expr (&label_expr);
8666 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
8667 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
8670 expr1.X_add_number = 1;
8671 load_register (AT, &expr1, dbl);
8672 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
8676 expr1.X_add_number = 0x80000000;
8677 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
8681 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
8682 /* We want to close the noreorder block as soon as possible, so
8683 that later insns are available for delay slot filling. */
8688 if (mips_opts.micromips)
8689 micromips_label_expr (&label_expr);
8691 label_expr.X_add_number = 8;
8692 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
8693 macro_build (NULL, "nop", "");
8695 /* We want to close the noreorder block as soon as possible, so
8696 that later insns are available for delay slot filling. */
8699 macro_build (NULL, "break", BRK_FMT, 6);
8701 if (mips_opts.micromips)
8702 micromips_add_label ();
8703 macro_build (NULL, s, MFHL_FMT, dreg);
8742 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8744 as_warn (_("Divide by zero."));
8746 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8748 macro_build (NULL, "break", BRK_FMT, 7);
8751 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8753 if (strcmp (s2, "mflo") == 0)
8754 move_register (dreg, sreg);
8756 move_register (dreg, ZERO);
8759 if (imm_expr.X_op == O_constant
8760 && imm_expr.X_add_number == -1
8761 && s[strlen (s) - 1] != 'u')
8763 if (strcmp (s2, "mflo") == 0)
8765 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
8768 move_register (dreg, ZERO);
8773 load_register (AT, &imm_expr, dbl);
8774 macro_build (NULL, s, "z,s,t", sreg, AT);
8775 macro_build (NULL, s2, MFHL_FMT, dreg);
8797 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8798 macro_build (NULL, s, "z,s,t", sreg, treg);
8799 /* We want to close the noreorder block as soon as possible, so
8800 that later insns are available for delay slot filling. */
8805 if (mips_opts.micromips)
8806 micromips_label_expr (&label_expr);
8808 label_expr.X_add_number = 8;
8809 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8810 macro_build (NULL, s, "z,s,t", sreg, treg);
8812 /* We want to close the noreorder block as soon as possible, so
8813 that later insns are available for delay slot filling. */
8815 macro_build (NULL, "break", BRK_FMT, 7);
8816 if (mips_opts.micromips)
8817 micromips_add_label ();
8819 macro_build (NULL, s2, MFHL_FMT, dreg);
8831 /* Load the address of a symbol into a register. If breg is not
8832 zero, we then add a base register to it. */
8834 if (dbl && HAVE_32BIT_GPRS)
8835 as_warn (_("dla used to load 32-bit register"));
8837 if (!dbl && HAVE_64BIT_OBJECTS)
8838 as_warn (_("la used to load 64-bit address"));
8840 if (small_offset_p (0, align, 16))
8842 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
8843 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8847 if (mips_opts.at && (treg == breg))
8857 if (offset_expr.X_op != O_symbol
8858 && offset_expr.X_op != O_constant)
8860 as_bad (_("Expression too complex"));
8861 offset_expr.X_op = O_constant;
8864 if (offset_expr.X_op == O_constant)
8865 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
8866 else if (mips_pic == NO_PIC)
8868 /* If this is a reference to a GP relative symbol, we want
8869 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8871 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8872 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8873 If we have a constant, we need two instructions anyhow,
8874 so we may as well always use the latter form.
8876 With 64bit address space and a usable $at we want
8877 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8878 lui $at,<sym> (BFD_RELOC_HI16_S)
8879 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8880 daddiu $at,<sym> (BFD_RELOC_LO16)
8882 daddu $tempreg,$tempreg,$at
8884 If $at is already in use, we use a path which is suboptimal
8885 on superscalar processors.
8886 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8887 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8889 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8891 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8893 For GP relative symbols in 64bit address space we can use
8894 the same sequence as in 32bit address space. */
8895 if (HAVE_64BIT_SYMBOLS)
8897 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8898 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8900 relax_start (offset_expr.X_add_symbol);
8901 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8902 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8906 if (used_at == 0 && mips_opts.at)
8908 macro_build (&offset_expr, "lui", LUI_FMT,
8909 tempreg, BFD_RELOC_MIPS_HIGHEST);
8910 macro_build (&offset_expr, "lui", LUI_FMT,
8911 AT, BFD_RELOC_HI16_S);
8912 macro_build (&offset_expr, "daddiu", "t,r,j",
8913 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8914 macro_build (&offset_expr, "daddiu", "t,r,j",
8915 AT, AT, BFD_RELOC_LO16);
8916 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8917 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8922 macro_build (&offset_expr, "lui", LUI_FMT,
8923 tempreg, BFD_RELOC_MIPS_HIGHEST);
8924 macro_build (&offset_expr, "daddiu", "t,r,j",
8925 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8926 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8927 macro_build (&offset_expr, "daddiu", "t,r,j",
8928 tempreg, tempreg, BFD_RELOC_HI16_S);
8929 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8930 macro_build (&offset_expr, "daddiu", "t,r,j",
8931 tempreg, tempreg, BFD_RELOC_LO16);
8934 if (mips_relax.sequence)
8939 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8940 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8942 relax_start (offset_expr.X_add_symbol);
8943 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8944 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8947 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8948 as_bad (_("Offset too large"));
8949 macro_build_lui (&offset_expr, tempreg);
8950 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8951 tempreg, tempreg, BFD_RELOC_LO16);
8952 if (mips_relax.sequence)
8956 else if (!mips_big_got && !HAVE_NEWABI)
8958 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8960 /* If this is a reference to an external symbol, and there
8961 is no constant, we want
8962 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8963 or for lca or if tempreg is PIC_CALL_REG
8964 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8965 For a local symbol, we want
8966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8968 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8970 If we have a small constant, and this is a reference to
8971 an external symbol, we want
8972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8974 addiu $tempreg,$tempreg,<constant>
8975 For a local symbol, we want the same instruction
8976 sequence, but we output a BFD_RELOC_LO16 reloc on the
8979 If we have a large constant, and this is a reference to
8980 an external symbol, we want
8981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8982 lui $at,<hiconstant>
8983 addiu $at,$at,<loconstant>
8984 addu $tempreg,$tempreg,$at
8985 For a local symbol, we want the same instruction
8986 sequence, but we output a BFD_RELOC_LO16 reloc on the
8990 if (offset_expr.X_add_number == 0)
8992 if (mips_pic == SVR4_PIC
8994 && (call || tempreg == PIC_CALL_REG))
8995 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
8997 relax_start (offset_expr.X_add_symbol);
8998 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8999 lw_reloc_type, mips_gp_register);
9002 /* We're going to put in an addu instruction using
9003 tempreg, so we may as well insert the nop right
9008 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9009 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9011 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9012 tempreg, tempreg, BFD_RELOC_LO16);
9014 /* FIXME: If breg == 0, and the next instruction uses
9015 $tempreg, then if this variant case is used an extra
9016 nop will be generated. */
9018 else if (offset_expr.X_add_number >= -0x8000
9019 && offset_expr.X_add_number < 0x8000)
9021 load_got_offset (tempreg, &offset_expr);
9023 add_got_offset (tempreg, &offset_expr);
9027 expr1.X_add_number = offset_expr.X_add_number;
9028 offset_expr.X_add_number =
9029 SEXT_16BIT (offset_expr.X_add_number);
9030 load_got_offset (tempreg, &offset_expr);
9031 offset_expr.X_add_number = expr1.X_add_number;
9032 /* If we are going to add in a base register, and the
9033 target register and the base register are the same,
9034 then we are using AT as a temporary register. Since
9035 we want to load the constant into AT, we add our
9036 current AT (from the global offset table) and the
9037 register into the register now, and pretend we were
9038 not using a base register. */
9042 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9047 add_got_offset_hilo (tempreg, &offset_expr, AT);
9051 else if (!mips_big_got && HAVE_NEWABI)
9053 int add_breg_early = 0;
9055 /* If this is a reference to an external, and there is no
9056 constant, or local symbol (*), with or without a
9058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9059 or for lca or if tempreg is PIC_CALL_REG
9060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9062 If we have a small constant, and this is a reference to
9063 an external symbol, we want
9064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9065 addiu $tempreg,$tempreg,<constant>
9067 If we have a large constant, and this is a reference to
9068 an external symbol, we want
9069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9070 lui $at,<hiconstant>
9071 addiu $at,$at,<loconstant>
9072 addu $tempreg,$tempreg,$at
9074 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9075 local symbols, even though it introduces an additional
9078 if (offset_expr.X_add_number)
9080 expr1.X_add_number = offset_expr.X_add_number;
9081 offset_expr.X_add_number = 0;
9083 relax_start (offset_expr.X_add_symbol);
9084 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9085 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9087 if (expr1.X_add_number >= -0x8000
9088 && expr1.X_add_number < 0x8000)
9090 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9091 tempreg, tempreg, BFD_RELOC_LO16);
9093 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9095 /* If we are going to add in a base register, and the
9096 target register and the base register are the same,
9097 then we are using AT as a temporary register. Since
9098 we want to load the constant into AT, we add our
9099 current AT (from the global offset table) and the
9100 register into the register now, and pretend we were
9101 not using a base register. */
9106 gas_assert (tempreg == AT);
9107 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9113 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9114 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9120 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9123 offset_expr.X_add_number = expr1.X_add_number;
9125 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9126 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9130 treg, tempreg, breg);
9136 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
9138 relax_start (offset_expr.X_add_symbol);
9139 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9140 BFD_RELOC_MIPS_CALL16, mips_gp_register);
9142 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9143 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9148 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9149 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9152 else if (mips_big_got && !HAVE_NEWABI)
9155 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9156 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9157 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9159 /* This is the large GOT case. If this is a reference to an
9160 external symbol, and there is no constant, we want
9161 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9162 addu $tempreg,$tempreg,$gp
9163 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9164 or for lca or if tempreg is PIC_CALL_REG
9165 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9166 addu $tempreg,$tempreg,$gp
9167 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9168 For a local symbol, we want
9169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9171 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9173 If we have a small constant, and this is a reference to
9174 an external symbol, we want
9175 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9176 addu $tempreg,$tempreg,$gp
9177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9179 addiu $tempreg,$tempreg,<constant>
9180 For a local symbol, we want
9181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9183 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9185 If we have a large constant, and this is a reference to
9186 an external symbol, we want
9187 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9188 addu $tempreg,$tempreg,$gp
9189 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9190 lui $at,<hiconstant>
9191 addiu $at,$at,<loconstant>
9192 addu $tempreg,$tempreg,$at
9193 For a local symbol, we want
9194 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9195 lui $at,<hiconstant>
9196 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9197 addu $tempreg,$tempreg,$at
9200 expr1.X_add_number = offset_expr.X_add_number;
9201 offset_expr.X_add_number = 0;
9202 relax_start (offset_expr.X_add_symbol);
9203 gpdelay = reg_needs_delay (mips_gp_register);
9204 if (expr1.X_add_number == 0 && breg == 0
9205 && (call || tempreg == PIC_CALL_REG))
9207 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9208 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9210 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9211 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9212 tempreg, tempreg, mips_gp_register);
9213 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9214 tempreg, lw_reloc_type, tempreg);
9215 if (expr1.X_add_number == 0)
9219 /* We're going to put in an addu instruction using
9220 tempreg, so we may as well insert the nop right
9225 else if (expr1.X_add_number >= -0x8000
9226 && expr1.X_add_number < 0x8000)
9229 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9230 tempreg, tempreg, BFD_RELOC_LO16);
9234 /* If we are going to add in a base register, and the
9235 target register and the base register are the same,
9236 then we are using AT as a temporary register. Since
9237 we want to load the constant into AT, we add our
9238 current AT (from the global offset table) and the
9239 register into the register now, and pretend we were
9240 not using a base register. */
9245 gas_assert (tempreg == AT);
9247 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9252 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9253 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9257 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
9262 /* This is needed because this instruction uses $gp, but
9263 the first instruction on the main stream does not. */
9264 macro_build (NULL, "nop", "");
9267 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9268 local_reloc_type, mips_gp_register);
9269 if (expr1.X_add_number >= -0x8000
9270 && expr1.X_add_number < 0x8000)
9273 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9274 tempreg, tempreg, BFD_RELOC_LO16);
9275 /* FIXME: If add_number is 0, and there was no base
9276 register, the external symbol case ended with a load,
9277 so if the symbol turns out to not be external, and
9278 the next instruction uses tempreg, an unnecessary nop
9279 will be inserted. */
9285 /* We must add in the base register now, as in the
9286 external symbol case. */
9287 gas_assert (tempreg == AT);
9289 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9292 /* We set breg to 0 because we have arranged to add
9293 it in in both cases. */
9297 macro_build_lui (&expr1, AT);
9298 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9299 AT, AT, BFD_RELOC_LO16);
9300 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9301 tempreg, tempreg, AT);
9306 else if (mips_big_got && HAVE_NEWABI)
9308 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9309 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9310 int add_breg_early = 0;
9312 /* This is the large GOT case. If this is a reference to an
9313 external symbol, and there is no constant, we want
9314 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9315 add $tempreg,$tempreg,$gp
9316 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9317 or for lca or if tempreg is PIC_CALL_REG
9318 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9319 add $tempreg,$tempreg,$gp
9320 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9322 If we have a small constant, and this is a reference to
9323 an external symbol, we want
9324 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9325 add $tempreg,$tempreg,$gp
9326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9327 addi $tempreg,$tempreg,<constant>
9329 If we have a large constant, and this is a reference to
9330 an external symbol, we want
9331 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9332 addu $tempreg,$tempreg,$gp
9333 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9334 lui $at,<hiconstant>
9335 addi $at,$at,<loconstant>
9336 add $tempreg,$tempreg,$at
9338 If we have NewABI, and we know it's a local symbol, we want
9339 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9340 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9341 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9343 relax_start (offset_expr.X_add_symbol);
9345 expr1.X_add_number = offset_expr.X_add_number;
9346 offset_expr.X_add_number = 0;
9348 if (expr1.X_add_number == 0 && breg == 0
9349 && (call || tempreg == PIC_CALL_REG))
9351 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9352 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9354 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9355 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9356 tempreg, tempreg, mips_gp_register);
9357 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9358 tempreg, lw_reloc_type, tempreg);
9360 if (expr1.X_add_number == 0)
9362 else if (expr1.X_add_number >= -0x8000
9363 && expr1.X_add_number < 0x8000)
9365 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9366 tempreg, tempreg, BFD_RELOC_LO16);
9368 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9370 /* If we are going to add in a base register, and the
9371 target register and the base register are the same,
9372 then we are using AT as a temporary register. Since
9373 we want to load the constant into AT, we add our
9374 current AT (from the global offset table) and the
9375 register into the register now, and pretend we were
9376 not using a base register. */
9381 gas_assert (tempreg == AT);
9382 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9388 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9389 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9394 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9397 offset_expr.X_add_number = expr1.X_add_number;
9398 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9399 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9400 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9401 tempreg, BFD_RELOC_MIPS_GOT_OFST);
9404 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9405 treg, tempreg, breg);
9415 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
9419 gas_assert (!mips_opts.micromips);
9420 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
9424 gas_assert (!mips_opts.micromips);
9425 macro_build (NULL, "c2", "C", 0x02);
9429 gas_assert (!mips_opts.micromips);
9430 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
9434 gas_assert (!mips_opts.micromips);
9435 macro_build (NULL, "c2", "C", 3);
9439 gas_assert (!mips_opts.micromips);
9440 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
9444 /* The j instruction may not be used in PIC code, since it
9445 requires an absolute address. We convert it to a b
9447 if (mips_pic == NO_PIC)
9448 macro_build (&offset_expr, "j", "a");
9450 macro_build (&offset_expr, "b", "p");
9453 /* The jal instructions must be handled as macros because when
9454 generating PIC code they expand to multi-instruction
9455 sequences. Normally they are simple instructions. */
9460 gas_assert (mips_opts.micromips);
9461 if (mips_opts.insn32)
9463 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9473 if (mips_pic == NO_PIC)
9475 s = jals ? "jalrs" : "jalr";
9476 if (mips_opts.micromips
9477 && !mips_opts.insn32
9479 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9480 macro_build (NULL, s, "mj", sreg);
9482 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9486 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
9487 && mips_cprestore_offset >= 0);
9489 if (sreg != PIC_CALL_REG)
9490 as_warn (_("MIPS PIC call to register other than $25"));
9492 s = ((mips_opts.micromips
9493 && !mips_opts.insn32
9494 && (!mips_opts.noreorder || cprestore))
9495 ? "jalrs" : "jalr");
9496 if (mips_opts.micromips
9497 && !mips_opts.insn32
9499 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9500 macro_build (NULL, s, "mj", sreg);
9502 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9503 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
9505 if (mips_cprestore_offset < 0)
9506 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9509 if (!mips_frame_reg_valid)
9511 as_warn (_("No .frame pseudo-op used in PIC code"));
9512 /* Quiet this warning. */
9513 mips_frame_reg_valid = 1;
9515 if (!mips_cprestore_valid)
9517 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9518 /* Quiet this warning. */
9519 mips_cprestore_valid = 1;
9521 if (mips_opts.noreorder)
9522 macro_build (NULL, "nop", "");
9523 expr1.X_add_number = mips_cprestore_offset;
9524 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9527 HAVE_64BIT_ADDRESSES);
9535 gas_assert (mips_opts.micromips);
9536 if (mips_opts.insn32)
9538 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9544 if (mips_pic == NO_PIC)
9545 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
9546 else if (mips_pic == SVR4_PIC)
9548 /* If this is a reference to an external symbol, and we are
9549 using a small GOT, we want
9550 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9554 lw $gp,cprestore($sp)
9555 The cprestore value is set using the .cprestore
9556 pseudo-op. If we are using a big GOT, we want
9557 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9559 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9563 lw $gp,cprestore($sp)
9564 If the symbol is not external, we want
9565 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9567 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9570 lw $gp,cprestore($sp)
9572 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9573 sequences above, minus nops, unless the symbol is local,
9574 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9580 relax_start (offset_expr.X_add_symbol);
9581 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9582 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9585 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9586 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
9592 relax_start (offset_expr.X_add_symbol);
9593 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9594 BFD_RELOC_MIPS_CALL_HI16);
9595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9596 PIC_CALL_REG, mips_gp_register);
9597 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9598 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9601 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9602 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
9604 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9605 PIC_CALL_REG, PIC_CALL_REG,
9606 BFD_RELOC_MIPS_GOT_OFST);
9610 macro_build_jalr (&offset_expr, 0);
9614 relax_start (offset_expr.X_add_symbol);
9617 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9618 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9627 gpdelay = reg_needs_delay (mips_gp_register);
9628 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9629 BFD_RELOC_MIPS_CALL_HI16);
9630 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9631 PIC_CALL_REG, mips_gp_register);
9632 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9633 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9638 macro_build (NULL, "nop", "");
9640 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9641 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
9644 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9645 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
9647 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
9649 if (mips_cprestore_offset < 0)
9650 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9653 if (!mips_frame_reg_valid)
9655 as_warn (_("No .frame pseudo-op used in PIC code"));
9656 /* Quiet this warning. */
9657 mips_frame_reg_valid = 1;
9659 if (!mips_cprestore_valid)
9661 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9662 /* Quiet this warning. */
9663 mips_cprestore_valid = 1;
9665 if (mips_opts.noreorder)
9666 macro_build (NULL, "nop", "");
9667 expr1.X_add_number = mips_cprestore_offset;
9668 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9671 HAVE_64BIT_ADDRESSES);
9675 else if (mips_pic == VXWORKS_PIC)
9676 as_bad (_("Non-PIC jump used in PIC library"));
9754 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9760 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9785 gas_assert (!mips_opts.micromips);
9788 /* Itbl support may require additional care here. */
9794 /* Itbl support may require additional care here. */
9800 offbits = (mips_opts.micromips ? 12 : 16);
9801 /* Itbl support may require additional care here. */
9805 gas_assert (!mips_opts.micromips);
9808 /* Itbl support may require additional care here. */
9814 offbits = (mips_opts.micromips ? 12 : 16);
9819 offbits = (mips_opts.micromips ? 12 : 16);
9824 /* Itbl support may require additional care here. */
9830 offbits = (mips_opts.micromips ? 12 : 16);
9831 /* Itbl support may require additional care here. */
9837 /* Itbl support may require additional care here. */
9843 /* Itbl support may require additional care here. */
9849 offbits = (mips_opts.micromips ? 12 : 16);
9854 offbits = (mips_opts.micromips ? 12 : 16);
9859 offbits = (mips_opts.micromips ? 12 : 16);
9864 offbits = (mips_opts.micromips ? 12 : 16);
9869 offbits = (mips_opts.micromips ? 12 : 16);
9872 gas_assert (mips_opts.micromips);
9879 gas_assert (mips_opts.micromips);
9886 gas_assert (mips_opts.micromips);
9892 gas_assert (mips_opts.micromips);
9899 /* We don't want to use $0 as tempreg. */
9900 if (breg == treg + lp || treg + lp == ZERO)
9903 tempreg = treg + lp;
9919 gas_assert (!mips_opts.micromips);
9922 /* Itbl support may require additional care here. */
9928 /* Itbl support may require additional care here. */
9934 offbits = (mips_opts.micromips ? 12 : 16);
9935 /* Itbl support may require additional care here. */
9939 gas_assert (!mips_opts.micromips);
9942 /* Itbl support may require additional care here. */
9948 offbits = (mips_opts.micromips ? 12 : 16);
9953 offbits = (mips_opts.micromips ? 12 : 16);
9958 offbits = (mips_opts.micromips ? 12 : 16);
9963 offbits = (mips_opts.micromips ? 12 : 16);
9967 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
9968 offbits = (mips_opts.micromips ? 12 : 16);
9977 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
9978 offbits = (mips_opts.micromips ? 12 : 16);
9989 /* Itbl support may require additional care here. */
9994 offbits = (mips_opts.micromips ? 12 : 16);
9995 /* Itbl support may require additional care here. */
10001 /* Itbl support may require additional care here. */
10005 gas_assert (!mips_opts.micromips);
10008 /* Itbl support may require additional care here. */
10014 offbits = (mips_opts.micromips ? 12 : 16);
10019 offbits = (mips_opts.micromips ? 12 : 16);
10022 gas_assert (mips_opts.micromips);
10028 gas_assert (mips_opts.micromips);
10034 gas_assert (mips_opts.micromips);
10040 gas_assert (mips_opts.micromips);
10048 if (small_offset_p (0, align, 16))
10050 /* The first case exists for M_LD_AB and M_SD_AB, which are
10051 macros for o32 but which should act like normal instructions
10054 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
10055 offset_reloc[1], offset_reloc[2], breg);
10056 else if (small_offset_p (0, align, offbits))
10059 macro_build (NULL, s, fmt, treg, breg);
10061 macro_build (NULL, s, fmt, treg,
10062 (int) offset_expr.X_add_number, breg);
10068 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10069 tempreg, breg, -1, offset_reloc[0],
10070 offset_reloc[1], offset_reloc[2]);
10072 macro_build (NULL, s, fmt, treg, tempreg);
10074 macro_build (NULL, s, fmt, treg, 0, tempreg);
10082 if (offset_expr.X_op != O_constant
10083 && offset_expr.X_op != O_symbol)
10085 as_bad (_("Expression too complex"));
10086 offset_expr.X_op = O_constant;
10089 if (HAVE_32BIT_ADDRESSES
10090 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10094 sprintf_vma (value, offset_expr.X_add_number);
10095 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10098 /* A constant expression in PIC code can be handled just as it
10099 is in non PIC code. */
10100 if (offset_expr.X_op == O_constant)
10102 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10103 offbits == 0 ? 16 : offbits);
10104 offset_expr.X_add_number -= expr1.X_add_number;
10106 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10108 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10109 tempreg, tempreg, breg);
10112 if (offset_expr.X_add_number != 0)
10113 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10114 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10115 macro_build (NULL, s, fmt, treg, tempreg);
10117 else if (offbits == 16)
10118 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10120 macro_build (NULL, s, fmt, treg,
10121 (int) offset_expr.X_add_number, tempreg);
10123 else if (offbits != 16)
10125 /* The offset field is too narrow to be used for a low-part
10126 relocation, so load the whole address into the auxillary
10128 load_address (tempreg, &offset_expr, &used_at);
10130 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10131 tempreg, tempreg, breg);
10133 macro_build (NULL, s, fmt, treg, tempreg);
10135 macro_build (NULL, s, fmt, treg, 0, tempreg);
10137 else if (mips_pic == NO_PIC)
10139 /* If this is a reference to a GP relative symbol, and there
10140 is no base register, we want
10141 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10142 Otherwise, if there is no base register, we want
10143 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10144 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10145 If we have a constant, we need two instructions anyhow,
10146 so we always use the latter form.
10148 If we have a base register, and this is a reference to a
10149 GP relative symbol, we want
10150 addu $tempreg,$breg,$gp
10151 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
10153 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10154 addu $tempreg,$tempreg,$breg
10155 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10156 With a constant we always use the latter case.
10158 With 64bit address space and no base register and $at usable,
10160 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10161 lui $at,<sym> (BFD_RELOC_HI16_S)
10162 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10165 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10166 If we have a base register, we want
10167 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10168 lui $at,<sym> (BFD_RELOC_HI16_S)
10169 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10173 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10175 Without $at we can't generate the optimal path for superscalar
10176 processors here since this would require two temporary registers.
10177 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10178 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10180 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10182 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10183 If we have a base register, we want
10184 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10185 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10187 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10189 daddu $tempreg,$tempreg,$breg
10190 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10192 For GP relative symbols in 64bit address space we can use
10193 the same sequence as in 32bit address space. */
10194 if (HAVE_64BIT_SYMBOLS)
10196 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10197 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10199 relax_start (offset_expr.X_add_symbol);
10202 macro_build (&offset_expr, s, fmt, treg,
10203 BFD_RELOC_GPREL16, mips_gp_register);
10207 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10208 tempreg, breg, mips_gp_register);
10209 macro_build (&offset_expr, s, fmt, treg,
10210 BFD_RELOC_GPREL16, tempreg);
10215 if (used_at == 0 && mips_opts.at)
10217 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10218 BFD_RELOC_MIPS_HIGHEST);
10219 macro_build (&offset_expr, "lui", LUI_FMT, AT,
10221 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10222 tempreg, BFD_RELOC_MIPS_HIGHER);
10224 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
10225 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10226 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10227 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
10233 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10234 BFD_RELOC_MIPS_HIGHEST);
10235 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10236 tempreg, BFD_RELOC_MIPS_HIGHER);
10237 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10238 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10239 tempreg, BFD_RELOC_HI16_S);
10240 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10242 macro_build (NULL, "daddu", "d,v,t",
10243 tempreg, tempreg, breg);
10244 macro_build (&offset_expr, s, fmt, treg,
10245 BFD_RELOC_LO16, tempreg);
10248 if (mips_relax.sequence)
10255 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10256 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10258 relax_start (offset_expr.X_add_symbol);
10259 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
10263 macro_build_lui (&offset_expr, tempreg);
10264 macro_build (&offset_expr, s, fmt, treg,
10265 BFD_RELOC_LO16, tempreg);
10266 if (mips_relax.sequence)
10271 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10272 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10274 relax_start (offset_expr.X_add_symbol);
10275 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10276 tempreg, breg, mips_gp_register);
10277 macro_build (&offset_expr, s, fmt, treg,
10278 BFD_RELOC_GPREL16, tempreg);
10281 macro_build_lui (&offset_expr, tempreg);
10282 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10283 tempreg, tempreg, breg);
10284 macro_build (&offset_expr, s, fmt, treg,
10285 BFD_RELOC_LO16, tempreg);
10286 if (mips_relax.sequence)
10290 else if (!mips_big_got)
10292 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10294 /* If this is a reference to an external symbol, we want
10295 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10297 <op> $treg,0($tempreg)
10299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10301 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10302 <op> $treg,0($tempreg)
10304 For NewABI, we want
10305 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10306 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10308 If there is a base register, we add it to $tempreg before
10309 the <op>. If there is a constant, we stick it in the
10310 <op> instruction. We don't handle constants larger than
10311 16 bits, because we have no way to load the upper 16 bits
10312 (actually, we could handle them for the subset of cases
10313 in which we are not using $at). */
10314 gas_assert (offset_expr.X_op == O_symbol);
10317 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10318 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10320 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10321 tempreg, tempreg, breg);
10322 macro_build (&offset_expr, s, fmt, treg,
10323 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10326 expr1.X_add_number = offset_expr.X_add_number;
10327 offset_expr.X_add_number = 0;
10328 if (expr1.X_add_number < -0x8000
10329 || expr1.X_add_number >= 0x8000)
10330 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10331 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10332 lw_reloc_type, mips_gp_register);
10334 relax_start (offset_expr.X_add_symbol);
10336 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10337 tempreg, BFD_RELOC_LO16);
10340 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10341 tempreg, tempreg, breg);
10342 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10344 else if (mips_big_got && !HAVE_NEWABI)
10348 /* If this is a reference to an external symbol, we want
10349 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10350 addu $tempreg,$tempreg,$gp
10351 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10352 <op> $treg,0($tempreg)
10354 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10356 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10357 <op> $treg,0($tempreg)
10358 If there is a base register, we add it to $tempreg before
10359 the <op>. If there is a constant, we stick it in the
10360 <op> instruction. We don't handle constants larger than
10361 16 bits, because we have no way to load the upper 16 bits
10362 (actually, we could handle them for the subset of cases
10363 in which we are not using $at). */
10364 gas_assert (offset_expr.X_op == O_symbol);
10365 expr1.X_add_number = offset_expr.X_add_number;
10366 offset_expr.X_add_number = 0;
10367 if (expr1.X_add_number < -0x8000
10368 || expr1.X_add_number >= 0x8000)
10369 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10370 gpdelay = reg_needs_delay (mips_gp_register);
10371 relax_start (offset_expr.X_add_symbol);
10372 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10373 BFD_RELOC_MIPS_GOT_HI16);
10374 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10376 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10377 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10380 macro_build (NULL, "nop", "");
10381 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10382 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10384 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10385 tempreg, BFD_RELOC_LO16);
10389 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10390 tempreg, tempreg, breg);
10391 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10393 else if (mips_big_got && HAVE_NEWABI)
10395 /* If this is a reference to an external symbol, we want
10396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10397 add $tempreg,$tempreg,$gp
10398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10399 <op> $treg,<ofst>($tempreg)
10400 Otherwise, for local symbols, we want:
10401 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10402 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10403 gas_assert (offset_expr.X_op == O_symbol);
10404 expr1.X_add_number = offset_expr.X_add_number;
10405 offset_expr.X_add_number = 0;
10406 if (expr1.X_add_number < -0x8000
10407 || expr1.X_add_number >= 0x8000)
10408 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10409 relax_start (offset_expr.X_add_symbol);
10410 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10411 BFD_RELOC_MIPS_GOT_HI16);
10412 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10414 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10415 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10417 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10418 tempreg, tempreg, breg);
10419 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10422 offset_expr.X_add_number = expr1.X_add_number;
10423 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10424 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10426 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10427 tempreg, tempreg, breg);
10428 macro_build (&offset_expr, s, fmt, treg,
10429 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10438 gas_assert (mips_opts.micromips);
10439 gas_assert (mips_opts.insn32);
10440 start_noreorder ();
10441 macro_build (NULL, "jr", "s", RA);
10442 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
10443 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
10448 gas_assert (mips_opts.micromips);
10449 gas_assert (mips_opts.insn32);
10450 macro_build (NULL, "jr", "s", sreg);
10451 if (mips_opts.noreorder)
10452 macro_build (NULL, "nop", "");
10457 load_register (treg, &imm_expr, 0);
10461 load_register (treg, &imm_expr, 1);
10465 if (imm_expr.X_op == O_constant)
10468 load_register (AT, &imm_expr, 0);
10469 macro_build (NULL, "mtc1", "t,G", AT, treg);
10474 gas_assert (offset_expr.X_op == O_symbol
10475 && strcmp (segment_name (S_GET_SEGMENT
10476 (offset_expr.X_add_symbol)),
10478 && offset_expr.X_add_number == 0);
10479 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
10480 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
10485 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10486 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10487 order 32 bits of the value and the low order 32 bits are either
10488 zero or in OFFSET_EXPR. */
10489 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10491 if (HAVE_64BIT_GPRS)
10492 load_register (treg, &imm_expr, 1);
10497 if (target_big_endian)
10509 load_register (hreg, &imm_expr, 0);
10512 if (offset_expr.X_op == O_absent)
10513 move_register (lreg, 0);
10516 gas_assert (offset_expr.X_op == O_constant);
10517 load_register (lreg, &offset_expr, 0);
10524 /* We know that sym is in the .rdata section. First we get the
10525 upper 16 bits of the address. */
10526 if (mips_pic == NO_PIC)
10528 macro_build_lui (&offset_expr, AT);
10533 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10534 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10538 /* Now we load the register(s). */
10539 if (HAVE_64BIT_GPRS)
10542 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10547 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10550 /* FIXME: How in the world do we deal with the possible
10552 offset_expr.X_add_number += 4;
10553 macro_build (&offset_expr, "lw", "t,o(b)",
10554 treg + 1, BFD_RELOC_LO16, AT);
10560 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10561 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10562 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10563 the value and the low order 32 bits are either zero or in
10565 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10568 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
10569 if (HAVE_64BIT_FPRS)
10571 gas_assert (HAVE_64BIT_GPRS);
10572 macro_build (NULL, "dmtc1", "t,S", AT, treg);
10576 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
10577 if (offset_expr.X_op == O_absent)
10578 macro_build (NULL, "mtc1", "t,G", 0, treg);
10581 gas_assert (offset_expr.X_op == O_constant);
10582 load_register (AT, &offset_expr, 0);
10583 macro_build (NULL, "mtc1", "t,G", AT, treg);
10589 gas_assert (offset_expr.X_op == O_symbol
10590 && offset_expr.X_add_number == 0);
10591 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
10592 if (strcmp (s, ".lit8") == 0)
10594 breg = mips_gp_register;
10595 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
10596 offset_reloc[1] = BFD_RELOC_UNUSED;
10597 offset_reloc[2] = BFD_RELOC_UNUSED;
10601 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
10603 if (mips_pic != NO_PIC)
10604 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10605 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10608 /* FIXME: This won't work for a 64 bit address. */
10609 macro_build_lui (&offset_expr, AT);
10613 offset_reloc[0] = BFD_RELOC_LO16;
10614 offset_reloc[1] = BFD_RELOC_UNUSED;
10615 offset_reloc[2] = BFD_RELOC_UNUSED;
10622 * The MIPS assembler seems to check for X_add_number not
10623 * being double aligned and generating:
10624 * lui at,%hi(foo+1)
10626 * addiu at,at,%lo(foo+1)
10629 * But, the resulting address is the same after relocation so why
10630 * generate the extra instruction?
10632 /* Itbl support may require additional care here. */
10635 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10644 gas_assert (!mips_opts.micromips);
10645 /* Itbl support may require additional care here. */
10648 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10668 if (HAVE_64BIT_GPRS)
10678 if (HAVE_64BIT_GPRS)
10686 /* Even on a big endian machine $fn comes before $fn+1. We have
10687 to adjust when loading from memory. We set coproc if we must
10688 load $fn+1 first. */
10689 /* Itbl support may require additional care here. */
10690 if (!target_big_endian)
10693 if (small_offset_p (0, align, 16))
10696 if (!small_offset_p (4, align, 16))
10698 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
10699 -1, offset_reloc[0], offset_reloc[1],
10701 expr1.X_add_number = 0;
10705 offset_reloc[0] = BFD_RELOC_LO16;
10706 offset_reloc[1] = BFD_RELOC_UNUSED;
10707 offset_reloc[2] = BFD_RELOC_UNUSED;
10709 if (strcmp (s, "lw") == 0 && treg == breg)
10711 ep->X_add_number += 4;
10712 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
10713 offset_reloc[1], offset_reloc[2], breg);
10714 ep->X_add_number -= 4;
10715 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
10716 offset_reloc[1], offset_reloc[2], breg);
10720 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
10721 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10723 ep->X_add_number += 4;
10724 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
10725 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10731 if (offset_expr.X_op != O_symbol
10732 && offset_expr.X_op != O_constant)
10734 as_bad (_("Expression too complex"));
10735 offset_expr.X_op = O_constant;
10738 if (HAVE_32BIT_ADDRESSES
10739 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10743 sprintf_vma (value, offset_expr.X_add_number);
10744 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10747 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
10749 /* If this is a reference to a GP relative symbol, we want
10750 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10751 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10752 If we have a base register, we use this
10754 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10755 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10756 If this is not a GP relative symbol, we want
10757 lui $at,<sym> (BFD_RELOC_HI16_S)
10758 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10759 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10760 If there is a base register, we add it to $at after the
10761 lui instruction. If there is a constant, we always use
10763 if (offset_expr.X_op == O_symbol
10764 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10765 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10767 relax_start (offset_expr.X_add_symbol);
10770 tempreg = mips_gp_register;
10774 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10775 AT, breg, mips_gp_register);
10780 /* Itbl support may require additional care here. */
10781 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10782 BFD_RELOC_GPREL16, tempreg);
10783 offset_expr.X_add_number += 4;
10785 /* Set mips_optimize to 2 to avoid inserting an
10787 hold_mips_optimize = mips_optimize;
10789 /* Itbl support may require additional care here. */
10790 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10791 BFD_RELOC_GPREL16, tempreg);
10792 mips_optimize = hold_mips_optimize;
10796 offset_expr.X_add_number -= 4;
10799 if (offset_high_part (offset_expr.X_add_number, 16)
10800 != offset_high_part (offset_expr.X_add_number + 4, 16))
10802 load_address (AT, &offset_expr, &used_at);
10803 offset_expr.X_op = O_constant;
10804 offset_expr.X_add_number = 0;
10807 macro_build_lui (&offset_expr, AT);
10809 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10810 /* Itbl support may require additional care here. */
10811 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10812 BFD_RELOC_LO16, AT);
10813 /* FIXME: How do we handle overflow here? */
10814 offset_expr.X_add_number += 4;
10815 /* Itbl support may require additional care here. */
10816 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10817 BFD_RELOC_LO16, AT);
10818 if (mips_relax.sequence)
10821 else if (!mips_big_got)
10823 /* If this is a reference to an external symbol, we want
10824 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10827 <op> $treg+1,4($at)
10829 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10831 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10832 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10833 If there is a base register we add it to $at before the
10834 lwc1 instructions. If there is a constant we include it
10835 in the lwc1 instructions. */
10837 expr1.X_add_number = offset_expr.X_add_number;
10838 if (expr1.X_add_number < -0x8000
10839 || expr1.X_add_number >= 0x8000 - 4)
10840 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10841 load_got_offset (AT, &offset_expr);
10844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10846 /* Set mips_optimize to 2 to avoid inserting an undesired
10848 hold_mips_optimize = mips_optimize;
10851 /* Itbl support may require additional care here. */
10852 relax_start (offset_expr.X_add_symbol);
10853 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10854 BFD_RELOC_LO16, AT);
10855 expr1.X_add_number += 4;
10856 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10857 BFD_RELOC_LO16, AT);
10859 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10860 BFD_RELOC_LO16, AT);
10861 offset_expr.X_add_number += 4;
10862 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10863 BFD_RELOC_LO16, AT);
10866 mips_optimize = hold_mips_optimize;
10868 else if (mips_big_got)
10872 /* If this is a reference to an external symbol, we want
10873 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10875 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10878 <op> $treg+1,4($at)
10880 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10882 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10883 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10884 If there is a base register we add it to $at before the
10885 lwc1 instructions. If there is a constant we include it
10886 in the lwc1 instructions. */
10888 expr1.X_add_number = offset_expr.X_add_number;
10889 offset_expr.X_add_number = 0;
10890 if (expr1.X_add_number < -0x8000
10891 || expr1.X_add_number >= 0x8000 - 4)
10892 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10893 gpdelay = reg_needs_delay (mips_gp_register);
10894 relax_start (offset_expr.X_add_symbol);
10895 macro_build (&offset_expr, "lui", LUI_FMT,
10896 AT, BFD_RELOC_MIPS_GOT_HI16);
10897 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10898 AT, AT, mips_gp_register);
10899 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10900 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
10903 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10904 /* Itbl support may require additional care here. */
10905 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10906 BFD_RELOC_LO16, AT);
10907 expr1.X_add_number += 4;
10909 /* Set mips_optimize to 2 to avoid inserting an undesired
10911 hold_mips_optimize = mips_optimize;
10913 /* Itbl support may require additional care here. */
10914 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10915 BFD_RELOC_LO16, AT);
10916 mips_optimize = hold_mips_optimize;
10917 expr1.X_add_number -= 4;
10920 offset_expr.X_add_number = expr1.X_add_number;
10922 macro_build (NULL, "nop", "");
10923 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10924 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10927 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10928 /* Itbl support may require additional care here. */
10929 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10930 BFD_RELOC_LO16, AT);
10931 offset_expr.X_add_number += 4;
10933 /* Set mips_optimize to 2 to avoid inserting an undesired
10935 hold_mips_optimize = mips_optimize;
10937 /* Itbl support may require additional care here. */
10938 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10939 BFD_RELOC_LO16, AT);
10940 mips_optimize = hold_mips_optimize;
10959 /* New code added to support COPZ instructions.
10960 This code builds table entries out of the macros in mip_opcodes.
10961 R4000 uses interlocks to handle coproc delays.
10962 Other chips (like the R3000) require nops to be inserted for delays.
10964 FIXME: Currently, we require that the user handle delays.
10965 In order to fill delay slots for non-interlocked chips,
10966 we must have a way to specify delays based on the coprocessor.
10967 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10968 What are the side-effects of the cop instruction?
10969 What cache support might we have and what are its effects?
10970 Both coprocessor & memory require delays. how long???
10971 What registers are read/set/modified?
10973 If an itbl is provided to interpret cop instructions,
10974 this knowledge can be encoded in the itbl spec. */
10988 gas_assert (!mips_opts.micromips);
10989 /* For now we just do C (same as Cz). The parameter will be
10990 stored in insn_opcode by mips_ip. */
10991 macro_build (NULL, s, "C", (int) ip->insn_opcode);
10995 move_register (dreg, sreg);
10999 gas_assert (mips_opts.micromips);
11000 gas_assert (mips_opts.insn32);
11001 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
11002 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
11003 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
11004 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
11005 move_register (dreg, sreg);
11006 move_register (breg, treg);
11012 if (mips_opts.arch == CPU_R5900)
11014 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
11018 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
11019 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11026 /* The MIPS assembler some times generates shifts and adds. I'm
11027 not trying to be that fancy. GCC should do this for us
11030 load_register (AT, &imm_expr, dbl);
11031 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
11032 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11045 start_noreorder ();
11048 load_register (AT, &imm_expr, dbl);
11049 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
11050 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11051 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
11052 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11054 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
11057 if (mips_opts.micromips)
11058 micromips_label_expr (&label_expr);
11060 label_expr.X_add_number = 8;
11061 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
11062 macro_build (NULL, "nop", "");
11063 macro_build (NULL, "break", BRK_FMT, 6);
11064 if (mips_opts.micromips)
11065 micromips_add_label ();
11068 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11081 start_noreorder ();
11084 load_register (AT, &imm_expr, dbl);
11085 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11086 sreg, imm ? AT : treg);
11087 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11088 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11090 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11093 if (mips_opts.micromips)
11094 micromips_label_expr (&label_expr);
11096 label_expr.X_add_number = 8;
11097 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11098 macro_build (NULL, "nop", "");
11099 macro_build (NULL, "break", BRK_FMT, 6);
11100 if (mips_opts.micromips)
11101 micromips_add_label ();
11107 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11118 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
11119 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
11123 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
11124 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
11125 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
11126 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11130 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11141 macro_build (NULL, "negu", "d,w", tempreg, treg);
11142 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
11146 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
11147 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
11148 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
11149 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11158 if (imm_expr.X_op != O_constant)
11159 as_bad (_("Improper rotate count"));
11160 rot = imm_expr.X_add_number & 0x3f;
11161 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11163 rot = (64 - rot) & 0x3f;
11165 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
11167 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
11172 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
11175 l = (rot < 0x20) ? "dsll" : "dsll32";
11176 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
11179 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
11180 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11181 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11189 if (imm_expr.X_op != O_constant)
11190 as_bad (_("Improper rotate count"));
11191 rot = imm_expr.X_add_number & 0x1f;
11192 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11194 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
11199 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
11203 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
11204 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11205 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11210 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11212 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
11216 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
11217 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
11218 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
11219 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11223 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11225 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
11229 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
11230 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
11231 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
11232 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11241 if (imm_expr.X_op != O_constant)
11242 as_bad (_("Improper rotate count"));
11243 rot = imm_expr.X_add_number & 0x3f;
11244 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11247 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
11249 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
11254 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
11257 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
11258 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
11261 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
11262 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11263 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11271 if (imm_expr.X_op != O_constant)
11272 as_bad (_("Improper rotate count"));
11273 rot = imm_expr.X_add_number & 0x1f;
11274 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11276 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
11281 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
11285 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
11286 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11287 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11293 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
11294 else if (treg == 0)
11295 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11298 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11299 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11304 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11306 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11311 as_warn (_("Instruction %s: result is always false"),
11312 ip->insn_mo->name);
11313 move_register (dreg, 0);
11316 if (CPU_HAS_SEQ (mips_opts.arch)
11317 && -512 <= imm_expr.X_add_number
11318 && imm_expr.X_add_number < 512)
11320 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
11321 (int) imm_expr.X_add_number);
11324 if (imm_expr.X_op == O_constant
11325 && imm_expr.X_add_number >= 0
11326 && imm_expr.X_add_number < 0x10000)
11328 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11330 else if (imm_expr.X_op == O_constant
11331 && imm_expr.X_add_number > -0x8000
11332 && imm_expr.X_add_number < 0)
11334 imm_expr.X_add_number = -imm_expr.X_add_number;
11335 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11336 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11338 else if (CPU_HAS_SEQ (mips_opts.arch))
11341 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11342 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
11347 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11348 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11351 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11354 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
11360 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
11361 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11364 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
11366 if (imm_expr.X_op == O_constant
11367 && imm_expr.X_add_number >= -0x8000
11368 && imm_expr.X_add_number < 0x8000)
11370 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
11371 dreg, sreg, BFD_RELOC_LO16);
11375 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11376 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
11380 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11383 case M_SGT: /* sreg > treg <==> treg < sreg */
11389 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11392 case M_SGT_I: /* sreg > I <==> I < sreg */
11399 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11400 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11403 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11409 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11410 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11413 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11420 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11421 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11422 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11426 if (imm_expr.X_op == O_constant
11427 && imm_expr.X_add_number >= -0x8000
11428 && imm_expr.X_add_number < 0x8000)
11430 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11434 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11435 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
11439 if (imm_expr.X_op == O_constant
11440 && imm_expr.X_add_number >= -0x8000
11441 && imm_expr.X_add_number < 0x8000)
11443 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
11448 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11449 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
11454 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
11455 else if (treg == 0)
11456 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11459 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11460 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11465 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11467 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11472 as_warn (_("Instruction %s: result is always true"),
11473 ip->insn_mo->name);
11474 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
11475 dreg, 0, BFD_RELOC_LO16);
11478 if (CPU_HAS_SEQ (mips_opts.arch)
11479 && -512 <= imm_expr.X_add_number
11480 && imm_expr.X_add_number < 512)
11482 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
11483 (int) imm_expr.X_add_number);
11486 if (imm_expr.X_op == O_constant
11487 && imm_expr.X_add_number >= 0
11488 && imm_expr.X_add_number < 0x10000)
11490 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11492 else if (imm_expr.X_op == O_constant
11493 && imm_expr.X_add_number > -0x8000
11494 && imm_expr.X_add_number < 0)
11496 imm_expr.X_add_number = -imm_expr.X_add_number;
11497 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11498 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11500 else if (CPU_HAS_SEQ (mips_opts.arch))
11503 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11504 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
11509 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11510 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11513 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11528 if (!mips_opts.micromips)
11530 if (imm_expr.X_op == O_constant
11531 && imm_expr.X_add_number > -0x200
11532 && imm_expr.X_add_number <= 0x200)
11534 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
11543 if (imm_expr.X_op == O_constant
11544 && imm_expr.X_add_number > -0x8000
11545 && imm_expr.X_add_number <= 0x8000)
11547 imm_expr.X_add_number = -imm_expr.X_add_number;
11548 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11553 load_register (AT, &imm_expr, dbl);
11554 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
11576 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11577 macro_build (NULL, s, "s,t", sreg, AT);
11582 gas_assert (!mips_opts.micromips);
11583 gas_assert (mips_opts.isa == ISA_MIPS1);
11585 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
11586 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
11589 * Is the double cfc1 instruction a bug in the mips assembler;
11590 * or is there a reason for it?
11592 start_noreorder ();
11593 macro_build (NULL, "cfc1", "t,G", treg, RA);
11594 macro_build (NULL, "cfc1", "t,G", treg, RA);
11595 macro_build (NULL, "nop", "");
11596 expr1.X_add_number = 3;
11597 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
11598 expr1.X_add_number = 2;
11599 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
11600 macro_build (NULL, "ctc1", "t,G", AT, RA);
11601 macro_build (NULL, "nop", "");
11602 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
11604 macro_build (NULL, "ctc1", "t,G", treg, RA);
11605 macro_build (NULL, "nop", "");
11622 offbits = (mips_opts.micromips ? 12 : 16);
11628 offbits = (mips_opts.micromips ? 12 : 16);
11640 offbits = (mips_opts.micromips ? 12 : 16);
11647 offbits = (mips_opts.micromips ? 12 : 16);
11652 large_offset = !small_offset_p (off, align, offbits);
11654 expr1.X_add_number = 0;
11659 if (small_offset_p (0, align, 16))
11660 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
11661 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11664 load_address (tempreg, ep, &used_at);
11666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11667 tempreg, tempreg, breg);
11669 offset_reloc[0] = BFD_RELOC_LO16;
11670 offset_reloc[1] = BFD_RELOC_UNUSED;
11671 offset_reloc[2] = BFD_RELOC_UNUSED;
11676 else if (!ust && treg == breg)
11687 if (!target_big_endian)
11688 ep->X_add_number += off;
11690 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
11692 macro_build (ep, s, "t,o(b)", tempreg, -1,
11693 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11695 if (!target_big_endian)
11696 ep->X_add_number -= off;
11698 ep->X_add_number += off;
11700 macro_build (NULL, s2, "t,~(b)",
11701 tempreg, (int) ep->X_add_number, breg);
11703 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11704 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11706 /* If necessary, move the result in tempreg to the final destination. */
11707 if (!ust && treg != tempreg)
11709 /* Protect second load's delay slot. */
11711 move_register (treg, tempreg);
11717 if (target_big_endian == ust)
11718 ep->X_add_number += off;
11719 tempreg = ust || large_offset ? treg : AT;
11720 macro_build (ep, s, "t,o(b)", tempreg, -1,
11721 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11723 /* For halfword transfers we need a temporary register to shuffle
11724 bytes. Unfortunately for M_USH_A we have none available before
11725 the next store as AT holds the base address. We deal with this
11726 case by clobbering TREG and then restoring it as with ULH. */
11727 tempreg = ust == large_offset ? treg : AT;
11729 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
11731 if (target_big_endian == ust)
11732 ep->X_add_number -= off;
11734 ep->X_add_number += off;
11735 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11736 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11738 /* For M_USH_A re-retrieve the LSB. */
11739 if (ust && large_offset)
11741 if (target_big_endian)
11742 ep->X_add_number += off;
11744 ep->X_add_number -= off;
11745 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
11746 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
11748 /* For ULH and M_USH_A OR the LSB in. */
11749 if (!ust || large_offset)
11751 tempreg = !large_offset ? AT : treg;
11752 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
11753 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
11758 /* FIXME: Check if this is one of the itbl macros, since they
11759 are added dynamically. */
11760 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
11763 if (!mips_opts.at && used_at)
11764 as_bad (_("Macro used $at after \".set noat\""));
11767 /* Implement macros in mips16 mode. */
11770 mips16_macro (struct mips_cl_insn *ip)
11773 int xreg, yreg, zreg, tmp;
11776 const char *s, *s2, *s3;
11778 mask = ip->insn_mo->mask;
11780 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
11781 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
11782 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
11784 expr1.X_op = O_constant;
11785 expr1.X_op_symbol = NULL;
11786 expr1.X_add_symbol = NULL;
11787 expr1.X_add_number = 1;
11806 start_noreorder ();
11807 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
11808 expr1.X_add_number = 2;
11809 macro_build (&expr1, "bnez", "x,p", yreg);
11810 macro_build (NULL, "break", "6", 7);
11812 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11813 since that causes an overflow. We should do that as well,
11814 but I don't see how to do the comparisons without a temporary
11817 macro_build (NULL, s, "x", zreg);
11836 start_noreorder ();
11837 macro_build (NULL, s, "0,x,y", xreg, yreg);
11838 expr1.X_add_number = 2;
11839 macro_build (&expr1, "bnez", "x,p", yreg);
11840 macro_build (NULL, "break", "6", 7);
11842 macro_build (NULL, s2, "x", zreg);
11848 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
11849 macro_build (NULL, "mflo", "x", zreg);
11857 if (imm_expr.X_op != O_constant)
11858 as_bad (_("Unsupported large constant"));
11859 imm_expr.X_add_number = -imm_expr.X_add_number;
11860 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
11864 if (imm_expr.X_op != O_constant)
11865 as_bad (_("Unsupported large constant"));
11866 imm_expr.X_add_number = -imm_expr.X_add_number;
11867 macro_build (&imm_expr, "addiu", "x,k", xreg);
11871 if (imm_expr.X_op != O_constant)
11872 as_bad (_("Unsupported large constant"));
11873 imm_expr.X_add_number = -imm_expr.X_add_number;
11874 macro_build (&imm_expr, "daddiu", "y,j", yreg);
11896 goto do_reverse_branch;
11900 goto do_reverse_branch;
11912 goto do_reverse_branch;
11923 macro_build (NULL, s, "x,y", xreg, yreg);
11924 macro_build (&offset_expr, s2, "p");
11951 goto do_addone_branch_i;
11956 goto do_addone_branch_i;
11971 goto do_addone_branch_i;
11977 do_addone_branch_i:
11978 if (imm_expr.X_op != O_constant)
11979 as_bad (_("Unsupported large constant"));
11980 ++imm_expr.X_add_number;
11983 macro_build (&imm_expr, s, s3, xreg);
11984 macro_build (&offset_expr, s2, "p");
11988 expr1.X_add_number = 0;
11989 macro_build (&expr1, "slti", "x,8", yreg);
11991 move_register (xreg, yreg);
11992 expr1.X_add_number = 2;
11993 macro_build (&expr1, "bteqz", "p");
11994 macro_build (NULL, "neg", "x,w", xreg, xreg);
11998 /* Assemble an instruction into its binary format. If the instruction
11999 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12000 associated with "I", "+I" and "A" operands respectively. Otherwise
12001 store the value of the relocatable field (if any) in offset_expr.
12002 In both cases set offset_reloc to the relocation operators applied
12006 mips_ip (char *str, struct mips_cl_insn *ip)
12008 bfd_boolean wrong_delay_slot_insns = FALSE;
12009 bfd_boolean need_delay_slot_ok = TRUE;
12010 struct mips_opcode *firstinsn = NULL;
12011 const struct mips_opcode *past;
12012 struct hash_control *hash;
12015 struct mips_opcode *insn;
12021 const struct mips_operand *operand;
12022 struct mips_arg_info arg;
12023 struct mips_operand_token *tokens;
12024 bfd_boolean optional_reg;
12028 if (mips_opts.micromips)
12030 hash = micromips_op_hash;
12031 past = µmips_opcodes[bfd_micromips_num_opcodes];
12036 past = &mips_opcodes[NUMOPCODES];
12038 forced_insn_length = 0;
12041 /* We first try to match an instruction up to a space or to the end. */
12042 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12045 /* Make a copy of the instruction so that we can fiddle with it. */
12046 name = alloca (end + 1);
12047 memcpy (name, str, end);
12052 insn = (struct mips_opcode *) hash_find (hash, name);
12054 if (insn != NULL || !mips_opts.micromips)
12056 if (forced_insn_length)
12059 /* See if there's an instruction size override suffix,
12060 either `16' or `32', at the end of the mnemonic proper,
12061 that defines the operation, i.e. before the first `.'
12062 character if any. Strip it and retry. */
12063 dot = strchr (name, '.');
12064 opend = dot != NULL ? dot - name : end;
12067 if (name[opend - 2] == '1' && name[opend - 1] == '6')
12068 forced_insn_length = 2;
12069 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12070 forced_insn_length = 4;
12073 memcpy (name + opend - 2, name + opend, end - opend + 1);
12077 insn_error = _("Unrecognized opcode");
12081 if (strcmp (name, "li.s") == 0)
12083 else if (strcmp (name, "li.d") == 0)
12087 tokens = mips_parse_arguments (str + end, format);
12091 /* For microMIPS instructions placed in a fixed-length branch delay slot
12092 we make up to two passes over the relevant fragment of the opcode
12093 table. First we try instructions that meet the delay slot's length
12094 requirement. If none matched, then we retry with the remaining ones
12095 and if one matches, then we use it and then issue an appropriate
12096 warning later on. */
12099 bfd_boolean delay_slot_ok;
12100 bfd_boolean size_ok;
12102 bfd_boolean more_alts;
12104 gas_assert (strcmp (insn->name, name) == 0);
12106 ok = is_opcode_valid (insn);
12107 size_ok = is_size_valid (insn);
12108 delay_slot_ok = is_delay_slot_valid (insn);
12109 if (!delay_slot_ok && !wrong_delay_slot_insns)
12112 wrong_delay_slot_insns = TRUE;
12114 more_alts = (insn + 1 < past
12115 && strcmp (insn[0].name, insn[1].name) == 0);
12116 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
12118 static char buf[256];
12125 if (wrong_delay_slot_insns && need_delay_slot_ok)
12127 gas_assert (firstinsn);
12128 need_delay_slot_ok = FALSE;
12134 obstack_free (&mips_operand_tokens, tokens);
12139 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
12140 mips_cpu_info_from_arch (mips_opts.arch)->name,
12141 mips_cpu_info_from_isa (mips_opts.isa)->name);
12142 else if (mips_opts.insn32)
12143 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
12145 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
12146 8 * forced_insn_length);
12152 imm_expr.X_op = O_absent;
12153 imm2_expr.X_op = O_absent;
12154 offset_expr.X_op = O_absent;
12155 offset_reloc[0] = BFD_RELOC_UNUSED;
12156 offset_reloc[1] = BFD_RELOC_UNUSED;
12157 offset_reloc[2] = BFD_RELOC_UNUSED;
12159 create_insn (ip, insn);
12161 memset (&arg, 0, sizeof (arg));
12163 arg.token = tokens;
12165 arg.last_regno = ILLEGAL_REG;
12166 arg.dest_regno = ILLEGAL_REG;
12167 arg.soft_match = (more_alts
12168 || (wrong_delay_slot_insns && need_delay_slot_ok));
12169 for (args = insn->args;; ++args)
12171 if (arg.token->type == OT_END)
12173 /* Handle unary instructions in which only one operand is given.
12174 The source is then the same as the destination. */
12175 if (arg.opnum == 1 && *args == ',')
12183 arg.token = tokens;
12188 /* Treat elided base registers as $0. */
12189 if (strcmp (args, "(b)") == 0)
12192 /* Fail the match if there were too few operands. */
12196 /* Successful match. */
12197 if (arg.dest_regno == arg.last_regno
12198 && strncmp (ip->insn_mo->name, "jalr", 4) == 0)
12200 if (arg.opnum == 2)
12201 as_bad (_("Source and destination must be different"));
12202 else if (arg.last_regno == 31)
12203 as_bad (_("A destination register must be supplied"));
12205 check_completed_insn (&arg);
12206 obstack_free (&mips_operand_tokens, tokens);
12210 /* Fail the match if the line has too many operands. */
12214 /* Handle characters that need to match exactly. */
12215 if (*args == '(' || *args == ')' || *args == ',')
12217 if (match_char (&arg, *args))
12222 /* Handle special macro operands. Work out the properties of
12225 arg.lax_max = FALSE;
12226 optional_reg = FALSE;
12245 /* If these integer forms come last, there is no other
12246 form of the instruction that could match. Prefer to
12247 give detailed error messages where possible. */
12249 arg.soft_match = FALSE;
12253 /* "+I" is like "I", except that imm2_expr is used. */
12254 if (match_const_int (&arg, &imm2_expr.X_add_number, 0))
12255 imm2_expr.X_op = O_constant;
12257 insn_error = _("absolute expression required");
12258 if (HAVE_32BIT_GPRS)
12259 normalize_constant_expr (&imm2_expr);
12264 *offset_reloc = BFD_RELOC_MIPS_JMP;
12294 /* If these integer forms come last, there is no other
12295 form of the instruction that could match. Prefer to
12296 give detailed error messages where possible. */
12298 arg.soft_match = FALSE;
12306 /* We have already matched a comma by this point, so the register
12307 is only optional if there is another operand to come. */
12308 gas_assert (arg.opnum == 2);
12309 optional_reg = (args[1] == ',');
12313 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12314 imm_expr.X_op = O_constant;
12316 insn_error = _("absolute expression required");
12317 if (HAVE_32BIT_GPRS)
12318 normalize_constant_expr (&imm_expr);
12322 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12324 /* Assume that the offset has been elided and that what
12325 we saw was a base register. The match will fail later
12326 if that assumption turns out to be wrong. */
12327 offset_expr.X_op = O_constant;
12328 offset_expr.X_add_number = 0;
12330 else if (match_expression (&arg, &offset_expr, offset_reloc))
12331 normalize_address_expr (&offset_expr);
12333 insn_error = _("absolute expression required");
12337 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12339 insn_error = _("floating-point expression required");
12343 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12345 insn_error = _("floating-point expression required");
12349 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12351 insn_error = _("floating-point expression required");
12355 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12357 insn_error = _("floating-point expression required");
12360 /* ??? This is the traditional behavior, but is flaky if
12361 there are alternative versions of the same instruction
12362 for different subarchitectures. The next alternative
12363 might not be suitable. */
12365 /* For compatibility with older assemblers, we accept
12366 0x8000-0xffff as signed 16-bit numbers when only
12367 signed numbers are allowed. */
12368 arg.lax_max = !more_alts;
12370 /* Only accept non-constant operands if this is the
12371 final alternative. Later alternatives might include
12372 a macro implementation. */
12373 arg.allow_nonconst = !more_alts;
12377 /* There are no macro implementations for out-of-range values. */
12378 arg.allow_nonconst = TRUE;
12382 /* There should always be a macro implementation. */
12383 arg.allow_nonconst = FALSE;
12387 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12391 *offset_reloc = BFD_RELOC_MIPS_JMP;
12395 gas_assert (mips_opts.micromips);
12402 /* We have already matched a comma by this point,
12403 so the register is only optional if there is another
12404 operand to come. */
12405 gas_assert (arg.opnum == 2);
12406 optional_reg = (args[2] == ',');
12411 if (!forced_insn_length)
12412 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12414 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12416 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12422 operand = (mips_opts.micromips
12423 ? decode_micromips_operand (args)
12424 : decode_mips_operand (args));
12429 && (arg.token[0].type != OT_REG
12430 || arg.token[1].type == OT_END))
12432 /* Assume that the register has been elided and is the
12433 same as the first operand. */
12434 arg.token = tokens;
12438 if (!match_operand (&arg, operand))
12441 /* Skip prefixes. */
12442 if (*args == '+' || *args == 'm')
12447 /* Args don't match. */
12448 insn_error = _("Illegal operands");
12454 if (wrong_delay_slot_insns && need_delay_slot_ok)
12456 gas_assert (firstinsn);
12457 need_delay_slot_ok = FALSE;
12462 obstack_free (&mips_operand_tokens, tokens);
12467 /* As for mips_ip, but used when assembling MIPS16 code.
12468 Also set forced_insn_length to the resulting instruction size in
12469 bytes if the user explicitly requested a small or extended instruction. */
12472 mips16_ip (char *str, struct mips_cl_insn *ip)
12476 struct mips_opcode *insn;
12477 const struct mips_operand *operand;
12478 const struct mips_operand *ext_operand;
12479 struct mips_arg_info arg;
12480 struct mips_operand_token *tokens;
12481 bfd_boolean optional_reg;
12485 forced_insn_length = 0;
12487 for (s = str; ISLOWER (*s); ++s)
12499 if (s[1] == 't' && s[2] == ' ')
12502 forced_insn_length = 2;
12506 else if (s[1] == 'e' && s[2] == ' ')
12509 forced_insn_length = 4;
12513 /* Fall through. */
12515 insn_error = _("unknown opcode");
12519 if (mips_opts.noautoextend && !forced_insn_length)
12520 forced_insn_length = 2;
12522 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
12524 insn_error = _("unrecognized opcode");
12528 tokens = mips_parse_arguments (s, 0);
12535 bfd_boolean more_alts;
12538 gas_assert (strcmp (insn->name, str) == 0);
12540 ok = is_opcode_valid_16 (insn);
12541 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
12542 && strcmp (insn[0].name, insn[1].name) == 0);
12554 static char buf[100];
12556 _("Opcode not supported on this processor: %s (%s)"),
12557 mips_cpu_info_from_arch (mips_opts.arch)->name,
12558 mips_cpu_info_from_isa (mips_opts.isa)->name);
12561 obstack_free (&mips_operand_tokens, tokens);
12566 create_insn (ip, insn);
12567 imm_expr.X_op = O_absent;
12568 imm2_expr.X_op = O_absent;
12569 offset_expr.X_op = O_absent;
12570 offset_reloc[0] = BFD_RELOC_UNUSED;
12571 offset_reloc[1] = BFD_RELOC_UNUSED;
12572 offset_reloc[2] = BFD_RELOC_UNUSED;
12575 memset (&arg, 0, sizeof (arg));
12577 arg.token = tokens;
12579 arg.last_regno = ILLEGAL_REG;
12580 arg.dest_regno = ILLEGAL_REG;
12581 arg.soft_match = more_alts;
12583 for (args = insn->args; 1; ++args)
12587 if (arg.token->type == OT_END)
12591 /* Handle unary instructions in which only one operand is given.
12592 The source is then the same as the destination. */
12593 if (arg.opnum == 1 && *args == ',')
12598 arg.token = tokens;
12603 /* Fail the match if there were too few operands. */
12607 /* Successful match. Stuff the immediate value in now, if
12609 if (insn->pinfo == INSN_MACRO)
12611 gas_assert (relax_char == 0);
12612 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
12614 else if (relax_char
12615 && offset_expr.X_op == O_constant
12616 && calculate_reloc (*offset_reloc,
12617 offset_expr.X_add_number,
12620 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
12621 forced_insn_length, &ip->insn_opcode);
12622 offset_expr.X_op = O_absent;
12623 *offset_reloc = BFD_RELOC_UNUSED;
12625 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
12627 if (forced_insn_length == 2)
12628 as_bad (_("invalid unextended operand value"));
12629 forced_insn_length = 4;
12630 ip->insn_opcode |= MIPS16_EXTEND;
12632 else if (relax_char)
12633 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
12635 check_completed_insn (&arg);
12636 obstack_free (&mips_operand_tokens, tokens);
12640 /* Fail the match if the line has too many operands. */
12644 /* Handle characters that need to match exactly. */
12645 if (*args == '(' || *args == ')' || *args == ',')
12647 if (match_char (&arg, *args))
12653 optional_reg = FALSE;
12659 optional_reg = (args[1] == ',');
12671 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12672 imm_expr.X_op = O_constant;
12674 insn_error = _("absolute expression required");
12675 if (HAVE_32BIT_GPRS)
12676 normalize_constant_expr (&imm_expr);
12681 *offset_reloc = BFD_RELOC_MIPS16_JMP;
12682 ip->insn_opcode <<= 16;
12686 operand = decode_mips16_operand (c, FALSE);
12690 /* '6' is a special case. It is used for BREAK and SDBBP,
12691 whose operands are only meaningful to the software that decodes
12692 them. This means that there is no architectural reason why
12693 they cannot be prefixed by EXTEND, but in practice,
12694 exception handlers will only look at the instruction
12695 itself. We therefore allow '6' to be extended when
12696 disassembling but not when assembling. */
12697 if (operand->type != OP_PCREL && c != '6')
12699 ext_operand = decode_mips16_operand (c, TRUE);
12700 if (operand != ext_operand)
12702 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12704 offset_expr.X_op = O_constant;
12705 offset_expr.X_add_number = 0;
12710 /* We need the OT_INTEGER check because some MIPS16
12711 immediate variants are listed before the register ones. */
12712 if (arg.token->type != OT_INTEGER
12713 || !match_expression (&arg, &offset_expr, offset_reloc))
12716 /* '8' is used for SLTI(U) and has traditionally not
12717 been allowed to take relocation operators. */
12718 if (offset_reloc[0] != BFD_RELOC_UNUSED
12719 && (ext_operand->size != 16 || c == '8'))
12728 && (arg.token[0].type != OT_REG
12729 || arg.token[1].type == OT_END))
12731 /* Assume that the register has been elided and is the
12732 same as the first operand. */
12733 arg.token = tokens;
12737 if (!match_operand (&arg, operand))
12742 /* Args don't match. */
12749 insn_error = _("illegal operands");
12751 obstack_free (&mips_operand_tokens, tokens);
12756 /* This structure holds information we know about a mips16 immediate
12759 struct mips16_immed_operand
12761 /* The type code used in the argument string in the opcode table. */
12763 /* The number of bits in the short form of the opcode. */
12765 /* The number of bits in the extended form of the opcode. */
12767 /* The amount by which the short form is shifted when it is used;
12768 for example, the sw instruction has a shift count of 2. */
12770 /* The amount by which the short form is shifted when it is stored
12771 into the instruction code. */
12773 /* Non-zero if the short form is unsigned. */
12775 /* Non-zero if the extended form is unsigned. */
12777 /* Non-zero if the value is PC relative. */
12781 /* The mips16 immediate operand types. */
12783 static const struct mips16_immed_operand mips16_immed_operands[] =
12785 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12786 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12787 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12788 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12789 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
12790 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
12791 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
12792 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
12793 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
12794 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
12795 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
12796 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
12797 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
12798 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
12799 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
12800 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
12801 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12802 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12803 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
12804 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
12805 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
12808 #define MIPS16_NUM_IMMED \
12809 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12811 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12812 NBITS is the number of significant bits in VAL. */
12814 static unsigned long
12815 mips16_immed_extend (offsetT val, unsigned int nbits)
12820 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
12823 else if (nbits == 15)
12825 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
12830 extval = ((val & 0x1f) << 6) | (val & 0x20);
12833 return (extval << 16) | val;
12836 /* Install immediate value VAL into MIPS16 instruction *INSN,
12837 extending it if necessary. The instruction in *INSN may
12838 already be extended.
12840 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12841 if none. In the former case, VAL is a 16-bit number with no
12842 defined signedness.
12844 TYPE is the type of the immediate field. USER_INSN_LENGTH
12845 is the length that the user requested, or 0 if none. */
12848 mips16_immed (char *file, unsigned int line, int type,
12849 bfd_reloc_code_real_type reloc, offsetT val,
12850 unsigned int user_insn_length, unsigned long *insn)
12852 const struct mips16_immed_operand *op;
12853 int mintiny, maxtiny;
12855 op = mips16_immed_operands;
12856 while (op->type != type)
12859 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12864 if (type == '<' || type == '>' || type == '[' || type == ']')
12867 maxtiny = 1 << op->nbits;
12872 maxtiny = (1 << op->nbits) - 1;
12874 if (reloc != BFD_RELOC_UNUSED)
12879 mintiny = - (1 << (op->nbits - 1));
12880 maxtiny = (1 << (op->nbits - 1)) - 1;
12881 if (reloc != BFD_RELOC_UNUSED)
12882 val = SEXT_16BIT (val);
12885 /* Branch offsets have an implicit 0 in the lowest bit. */
12886 if (type == 'p' || type == 'q')
12889 if ((val & ((1 << op->shift) - 1)) != 0
12890 || val < (mintiny << op->shift)
12891 || val > (maxtiny << op->shift))
12893 /* We need an extended instruction. */
12894 if (user_insn_length == 2)
12895 as_bad_where (file, line, _("invalid unextended operand value"));
12897 *insn |= MIPS16_EXTEND;
12899 else if (user_insn_length == 4)
12901 /* The operand doesn't force an unextended instruction to be extended.
12902 Warn if the user wanted an extended instruction anyway. */
12903 *insn |= MIPS16_EXTEND;
12904 as_warn_where (file, line,
12905 _("extended operand requested but not required"));
12908 if (mips16_opcode_length (*insn) == 2)
12912 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
12913 insnval <<= op->op_shift;
12918 long minext, maxext;
12920 if (reloc == BFD_RELOC_UNUSED)
12925 maxext = (1 << op->extbits) - 1;
12929 minext = - (1 << (op->extbits - 1));
12930 maxext = (1 << (op->extbits - 1)) - 1;
12932 if (val < minext || val > maxext)
12933 as_bad_where (file, line,
12934 _("operand value out of range for instruction"));
12937 *insn |= mips16_immed_extend (val, op->extbits);
12941 struct percent_op_match
12944 bfd_reloc_code_real_type reloc;
12947 static const struct percent_op_match mips_percent_op[] =
12949 {"%lo", BFD_RELOC_LO16},
12950 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
12951 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
12952 {"%call16", BFD_RELOC_MIPS_CALL16},
12953 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
12954 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
12955 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
12956 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
12957 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
12958 {"%got", BFD_RELOC_MIPS_GOT16},
12959 {"%gp_rel", BFD_RELOC_GPREL16},
12960 {"%half", BFD_RELOC_16},
12961 {"%highest", BFD_RELOC_MIPS_HIGHEST},
12962 {"%higher", BFD_RELOC_MIPS_HIGHER},
12963 {"%neg", BFD_RELOC_MIPS_SUB},
12964 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
12965 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
12966 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
12967 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
12968 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
12969 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
12970 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
12971 {"%hi", BFD_RELOC_HI16_S}
12974 static const struct percent_op_match mips16_percent_op[] =
12976 {"%lo", BFD_RELOC_MIPS16_LO16},
12977 {"%gprel", BFD_RELOC_MIPS16_GPREL},
12978 {"%got", BFD_RELOC_MIPS16_GOT16},
12979 {"%call16", BFD_RELOC_MIPS16_CALL16},
12980 {"%hi", BFD_RELOC_MIPS16_HI16_S},
12981 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
12982 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
12983 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
12984 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
12985 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
12986 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
12987 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
12991 /* Return true if *STR points to a relocation operator. When returning true,
12992 move *STR over the operator and store its relocation code in *RELOC.
12993 Leave both *STR and *RELOC alone when returning false. */
12996 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
12998 const struct percent_op_match *percent_op;
13001 if (mips_opts.mips16)
13003 percent_op = mips16_percent_op;
13004 limit = ARRAY_SIZE (mips16_percent_op);
13008 percent_op = mips_percent_op;
13009 limit = ARRAY_SIZE (mips_percent_op);
13012 for (i = 0; i < limit; i++)
13013 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13015 int len = strlen (percent_op[i].str);
13017 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13020 *str += strlen (percent_op[i].str);
13021 *reloc = percent_op[i].reloc;
13023 /* Check whether the output BFD supports this relocation.
13024 If not, issue an error and fall back on something safe. */
13025 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13027 as_bad (_("relocation %s isn't supported by the current ABI"),
13028 percent_op[i].str);
13029 *reloc = BFD_RELOC_UNUSED;
13037 /* Parse string STR as a 16-bit relocatable operand. Store the
13038 expression in *EP and the relocations in the array starting
13039 at RELOC. Return the number of relocation operators used.
13041 On exit, EXPR_END points to the first character after the expression. */
13044 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13047 bfd_reloc_code_real_type reversed_reloc[3];
13048 size_t reloc_index, i;
13049 int crux_depth, str_depth;
13052 /* Search for the start of the main expression, recoding relocations
13053 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13054 of the main expression and with CRUX_DEPTH containing the number
13055 of open brackets at that point. */
13062 crux_depth = str_depth;
13064 /* Skip over whitespace and brackets, keeping count of the number
13066 while (*str == ' ' || *str == '\t' || *str == '(')
13071 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13072 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13074 my_getExpression (ep, crux);
13077 /* Match every open bracket. */
13078 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13082 if (crux_depth > 0)
13083 as_bad (_("unclosed '('"));
13087 if (reloc_index != 0)
13089 prev_reloc_op_frag = frag_now;
13090 for (i = 0; i < reloc_index; i++)
13091 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13094 return reloc_index;
13098 my_getExpression (expressionS *ep, char *str)
13102 save_in = input_line_pointer;
13103 input_line_pointer = str;
13105 expr_end = input_line_pointer;
13106 input_line_pointer = save_in;
13110 md_atof (int type, char *litP, int *sizeP)
13112 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13116 md_number_to_chars (char *buf, valueT val, int n)
13118 if (target_big_endian)
13119 number_to_chars_bigendian (buf, val, n);
13121 number_to_chars_littleendian (buf, val, n);
13124 static int support_64bit_objects(void)
13126 const char **list, **l;
13129 list = bfd_target_list ();
13130 for (l = list; *l != NULL; l++)
13131 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13132 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13134 yes = (*l != NULL);
13139 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13140 NEW_VALUE. Warn if another value was already specified. Note:
13141 we have to defer parsing the -march and -mtune arguments in order
13142 to handle 'from-abi' correctly, since the ABI might be specified
13143 in a later argument. */
13146 mips_set_option_string (const char **string_ptr, const char *new_value)
13148 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13149 as_warn (_("A different %s was already specified, is now %s"),
13150 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13153 *string_ptr = new_value;
13157 md_parse_option (int c, char *arg)
13161 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13162 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13164 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13165 c == mips_ases[i].option_on);
13171 case OPTION_CONSTRUCT_FLOATS:
13172 mips_disable_float_construction = 0;
13175 case OPTION_NO_CONSTRUCT_FLOATS:
13176 mips_disable_float_construction = 1;
13188 target_big_endian = 1;
13192 target_big_endian = 0;
13198 else if (arg[0] == '0')
13200 else if (arg[0] == '1')
13210 mips_debug = atoi (arg);
13214 file_mips_isa = ISA_MIPS1;
13218 file_mips_isa = ISA_MIPS2;
13222 file_mips_isa = ISA_MIPS3;
13226 file_mips_isa = ISA_MIPS4;
13230 file_mips_isa = ISA_MIPS5;
13233 case OPTION_MIPS32:
13234 file_mips_isa = ISA_MIPS32;
13237 case OPTION_MIPS32R2:
13238 file_mips_isa = ISA_MIPS32R2;
13241 case OPTION_MIPS64R2:
13242 file_mips_isa = ISA_MIPS64R2;
13245 case OPTION_MIPS64:
13246 file_mips_isa = ISA_MIPS64;
13250 mips_set_option_string (&mips_tune_string, arg);
13254 mips_set_option_string (&mips_arch_string, arg);
13258 mips_set_option_string (&mips_arch_string, "4650");
13259 mips_set_option_string (&mips_tune_string, "4650");
13262 case OPTION_NO_M4650:
13266 mips_set_option_string (&mips_arch_string, "4010");
13267 mips_set_option_string (&mips_tune_string, "4010");
13270 case OPTION_NO_M4010:
13274 mips_set_option_string (&mips_arch_string, "4100");
13275 mips_set_option_string (&mips_tune_string, "4100");
13278 case OPTION_NO_M4100:
13282 mips_set_option_string (&mips_arch_string, "3900");
13283 mips_set_option_string (&mips_tune_string, "3900");
13286 case OPTION_NO_M3900:
13289 case OPTION_MICROMIPS:
13290 if (mips_opts.mips16 == 1)
13292 as_bad (_("-mmicromips cannot be used with -mips16"));
13295 mips_opts.micromips = 1;
13296 mips_no_prev_insn ();
13299 case OPTION_NO_MICROMIPS:
13300 mips_opts.micromips = 0;
13301 mips_no_prev_insn ();
13304 case OPTION_MIPS16:
13305 if (mips_opts.micromips == 1)
13307 as_bad (_("-mips16 cannot be used with -micromips"));
13310 mips_opts.mips16 = 1;
13311 mips_no_prev_insn ();
13314 case OPTION_NO_MIPS16:
13315 mips_opts.mips16 = 0;
13316 mips_no_prev_insn ();
13319 case OPTION_FIX_24K:
13323 case OPTION_NO_FIX_24K:
13327 case OPTION_FIX_LOONGSON2F_JUMP:
13328 mips_fix_loongson2f_jump = TRUE;
13331 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13332 mips_fix_loongson2f_jump = FALSE;
13335 case OPTION_FIX_LOONGSON2F_NOP:
13336 mips_fix_loongson2f_nop = TRUE;
13339 case OPTION_NO_FIX_LOONGSON2F_NOP:
13340 mips_fix_loongson2f_nop = FALSE;
13343 case OPTION_FIX_VR4120:
13344 mips_fix_vr4120 = 1;
13347 case OPTION_NO_FIX_VR4120:
13348 mips_fix_vr4120 = 0;
13351 case OPTION_FIX_VR4130:
13352 mips_fix_vr4130 = 1;
13355 case OPTION_NO_FIX_VR4130:
13356 mips_fix_vr4130 = 0;
13359 case OPTION_FIX_CN63XXP1:
13360 mips_fix_cn63xxp1 = TRUE;
13363 case OPTION_NO_FIX_CN63XXP1:
13364 mips_fix_cn63xxp1 = FALSE;
13367 case OPTION_RELAX_BRANCH:
13368 mips_relax_branch = 1;
13371 case OPTION_NO_RELAX_BRANCH:
13372 mips_relax_branch = 0;
13375 case OPTION_INSN32:
13376 mips_opts.insn32 = TRUE;
13379 case OPTION_NO_INSN32:
13380 mips_opts.insn32 = FALSE;
13383 case OPTION_MSHARED:
13384 mips_in_shared = TRUE;
13387 case OPTION_MNO_SHARED:
13388 mips_in_shared = FALSE;
13391 case OPTION_MSYM32:
13392 mips_opts.sym32 = TRUE;
13395 case OPTION_MNO_SYM32:
13396 mips_opts.sym32 = FALSE;
13399 /* When generating ELF code, we permit -KPIC and -call_shared to
13400 select SVR4_PIC, and -non_shared to select no PIC. This is
13401 intended to be compatible with Irix 5. */
13402 case OPTION_CALL_SHARED:
13403 mips_pic = SVR4_PIC;
13404 mips_abicalls = TRUE;
13407 case OPTION_CALL_NONPIC:
13409 mips_abicalls = TRUE;
13412 case OPTION_NON_SHARED:
13414 mips_abicalls = FALSE;
13417 /* The -xgot option tells the assembler to use 32 bit offsets
13418 when accessing the got in SVR4_PIC mode. It is for Irix
13425 g_switch_value = atoi (arg);
13429 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13432 mips_abi = O32_ABI;
13436 mips_abi = N32_ABI;
13440 mips_abi = N64_ABI;
13441 if (!support_64bit_objects())
13442 as_fatal (_("No compiled in support for 64 bit object file format"));
13446 file_mips_gp32 = 1;
13450 file_mips_gp32 = 0;
13454 file_mips_fp32 = 1;
13458 file_mips_fp32 = 0;
13461 case OPTION_SINGLE_FLOAT:
13462 file_mips_single_float = 1;
13465 case OPTION_DOUBLE_FLOAT:
13466 file_mips_single_float = 0;
13469 case OPTION_SOFT_FLOAT:
13470 file_mips_soft_float = 1;
13473 case OPTION_HARD_FLOAT:
13474 file_mips_soft_float = 0;
13478 if (strcmp (arg, "32") == 0)
13479 mips_abi = O32_ABI;
13480 else if (strcmp (arg, "o64") == 0)
13481 mips_abi = O64_ABI;
13482 else if (strcmp (arg, "n32") == 0)
13483 mips_abi = N32_ABI;
13484 else if (strcmp (arg, "64") == 0)
13486 mips_abi = N64_ABI;
13487 if (! support_64bit_objects())
13488 as_fatal (_("No compiled in support for 64 bit object file "
13491 else if (strcmp (arg, "eabi") == 0)
13492 mips_abi = EABI_ABI;
13495 as_fatal (_("invalid abi -mabi=%s"), arg);
13500 case OPTION_M7000_HILO_FIX:
13501 mips_7000_hilo_fix = TRUE;
13504 case OPTION_MNO_7000_HILO_FIX:
13505 mips_7000_hilo_fix = FALSE;
13508 case OPTION_MDEBUG:
13509 mips_flag_mdebug = TRUE;
13512 case OPTION_NO_MDEBUG:
13513 mips_flag_mdebug = FALSE;
13517 mips_flag_pdr = TRUE;
13520 case OPTION_NO_PDR:
13521 mips_flag_pdr = FALSE;
13524 case OPTION_MVXWORKS_PIC:
13525 mips_pic = VXWORKS_PIC;
13529 if (strcmp (arg, "2008") == 0)
13530 mips_flag_nan2008 = TRUE;
13531 else if (strcmp (arg, "legacy") == 0)
13532 mips_flag_nan2008 = FALSE;
13535 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13544 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13549 /* Set up globals to generate code for the ISA or processor
13550 described by INFO. */
13553 mips_set_architecture (const struct mips_cpu_info *info)
13557 file_mips_arch = info->cpu;
13558 mips_opts.arch = info->cpu;
13559 mips_opts.isa = info->isa;
13564 /* Likewise for tuning. */
13567 mips_set_tune (const struct mips_cpu_info *info)
13570 mips_tune = info->cpu;
13575 mips_after_parse_args (void)
13577 const struct mips_cpu_info *arch_info = 0;
13578 const struct mips_cpu_info *tune_info = 0;
13580 /* GP relative stuff not working for PE */
13581 if (strncmp (TARGET_OS, "pe", 2) == 0)
13583 if (g_switch_seen && g_switch_value != 0)
13584 as_bad (_("-G not supported in this configuration."));
13585 g_switch_value = 0;
13588 if (mips_abi == NO_ABI)
13589 mips_abi = MIPS_DEFAULT_ABI;
13591 /* The following code determines the architecture and register size.
13592 Similar code was added to GCC 3.3 (see override_options() in
13593 config/mips/mips.c). The GAS and GCC code should be kept in sync
13594 as much as possible. */
13596 if (mips_arch_string != 0)
13597 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13599 if (file_mips_isa != ISA_UNKNOWN)
13601 /* Handle -mipsN. At this point, file_mips_isa contains the
13602 ISA level specified by -mipsN, while arch_info->isa contains
13603 the -march selection (if any). */
13604 if (arch_info != 0)
13606 /* -march takes precedence over -mipsN, since it is more descriptive.
13607 There's no harm in specifying both as long as the ISA levels
13609 if (file_mips_isa != arch_info->isa)
13610 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13611 mips_cpu_info_from_isa (file_mips_isa)->name,
13612 mips_cpu_info_from_isa (arch_info->isa)->name);
13615 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13618 if (arch_info == 0)
13620 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13621 gas_assert (arch_info);
13624 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13625 as_bad (_("-march=%s is not compatible with the selected ABI"),
13628 mips_set_architecture (arch_info);
13630 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13631 if (mips_tune_string != 0)
13632 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13634 if (tune_info == 0)
13635 mips_set_tune (arch_info);
13637 mips_set_tune (tune_info);
13639 if (file_mips_gp32 >= 0)
13641 /* The user specified the size of the integer registers. Make sure
13642 it agrees with the ABI and ISA. */
13643 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13644 as_bad (_("-mgp64 used with a 32-bit processor"));
13645 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13646 as_bad (_("-mgp32 used with a 64-bit ABI"));
13647 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13648 as_bad (_("-mgp64 used with a 32-bit ABI"));
13652 /* Infer the integer register size from the ABI and processor.
13653 Restrict ourselves to 32-bit registers if that's all the
13654 processor has, or if the ABI cannot handle 64-bit registers. */
13655 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13656 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13659 switch (file_mips_fp32)
13663 /* No user specified float register size.
13664 ??? GAS treats single-float processors as though they had 64-bit
13665 float registers (although it complains when double-precision
13666 instructions are used). As things stand, saying they have 32-bit
13667 registers would lead to spurious "register must be even" messages.
13668 So here we assume float registers are never smaller than the
13670 if (file_mips_gp32 == 0)
13671 /* 64-bit integer registers implies 64-bit float registers. */
13672 file_mips_fp32 = 0;
13673 else if ((mips_opts.ase & FP64_ASES)
13674 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13675 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13676 file_mips_fp32 = 0;
13678 /* 32-bit float registers. */
13679 file_mips_fp32 = 1;
13682 /* The user specified the size of the float registers. Check if it
13683 agrees with the ABI and ISA. */
13685 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13686 as_bad (_("-mfp64 used with a 32-bit fpu"));
13687 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13688 && !ISA_HAS_MXHC1 (mips_opts.isa))
13689 as_warn (_("-mfp64 used with a 32-bit ABI"));
13692 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13693 as_warn (_("-mfp32 used with a 64-bit ABI"));
13697 /* End of GCC-shared inference code. */
13699 /* This flag is set when we have a 64-bit capable CPU but use only
13700 32-bit wide registers. Note that EABI does not use it. */
13701 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13702 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13703 || mips_abi == O32_ABI))
13704 mips_32bitmode = 1;
13706 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13707 as_bad (_("trap exception not supported at ISA 1"));
13709 /* If the selected architecture includes support for ASEs, enable
13710 generation of code for them. */
13711 if (mips_opts.mips16 == -1)
13712 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
13713 if (mips_opts.micromips == -1)
13714 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
13716 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13717 ASEs from being selected implicitly. */
13718 if (file_mips_fp32 == 1)
13719 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13721 /* If the user didn't explicitly select or deselect a particular ASE,
13722 use the default setting for the CPU. */
13723 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13725 file_mips_isa = mips_opts.isa;
13726 file_ase = mips_opts.ase;
13727 mips_opts.gp32 = file_mips_gp32;
13728 mips_opts.fp32 = file_mips_fp32;
13729 mips_opts.soft_float = file_mips_soft_float;
13730 mips_opts.single_float = file_mips_single_float;
13732 mips_check_isa_supports_ases ();
13734 if (mips_flag_mdebug < 0)
13735 mips_flag_mdebug = 0;
13739 mips_init_after_args (void)
13741 /* initialize opcodes */
13742 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
13743 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
13747 md_pcrel_from (fixS *fixP)
13749 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
13750 switch (fixP->fx_r_type)
13752 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13753 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13754 /* Return the address of the delay slot. */
13757 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13758 case BFD_RELOC_MICROMIPS_JMP:
13759 case BFD_RELOC_16_PCREL_S2:
13760 case BFD_RELOC_MIPS_JMP:
13761 /* Return the address of the delay slot. */
13764 case BFD_RELOC_32_PCREL:
13768 /* We have no relocation type for PC relative MIPS16 instructions. */
13769 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
13770 as_bad_where (fixP->fx_file, fixP->fx_line,
13771 _("PC relative MIPS16 instruction references a different section"));
13776 /* This is called before the symbol table is processed. In order to
13777 work with gcc when using mips-tfile, we must keep all local labels.
13778 However, in other cases, we want to discard them. If we were
13779 called with -g, but we didn't see any debugging information, it may
13780 mean that gcc is smuggling debugging information through to
13781 mips-tfile, in which case we must generate all local labels. */
13784 mips_frob_file_before_adjust (void)
13786 #ifndef NO_ECOFF_DEBUGGING
13787 if (ECOFF_DEBUGGING
13789 && ! ecoff_debugging_seen)
13790 flag_keep_locals = 1;
13794 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13795 the corresponding LO16 reloc. This is called before md_apply_fix and
13796 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13797 relocation operators.
13799 For our purposes, a %lo() expression matches a %got() or %hi()
13802 (a) it refers to the same symbol; and
13803 (b) the offset applied in the %lo() expression is no lower than
13804 the offset applied in the %got() or %hi().
13806 (b) allows us to cope with code like:
13809 lh $4,%lo(foo+2)($4)
13811 ...which is legal on RELA targets, and has a well-defined behaviour
13812 if the user knows that adding 2 to "foo" will not induce a carry to
13815 When several %lo()s match a particular %got() or %hi(), we use the
13816 following rules to distinguish them:
13818 (1) %lo()s with smaller offsets are a better match than %lo()s with
13821 (2) %lo()s with no matching %got() or %hi() are better than those
13822 that already have a matching %got() or %hi().
13824 (3) later %lo()s are better than earlier %lo()s.
13826 These rules are applied in order.
13828 (1) means, among other things, that %lo()s with identical offsets are
13829 chosen if they exist.
13831 (2) means that we won't associate several high-part relocations with
13832 the same low-part relocation unless there's no alternative. Having
13833 several high parts for the same low part is a GNU extension; this rule
13834 allows careful users to avoid it.
13836 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13837 with the last high-part relocation being at the front of the list.
13838 It therefore makes sense to choose the last matching low-part
13839 relocation, all other things being equal. It's also easier
13840 to code that way. */
13843 mips_frob_file (void)
13845 struct mips_hi_fixup *l;
13846 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
13848 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
13850 segment_info_type *seginfo;
13851 bfd_boolean matched_lo_p;
13852 fixS **hi_pos, **lo_pos, **pos;
13854 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
13856 /* If a GOT16 relocation turns out to be against a global symbol,
13857 there isn't supposed to be a matching LO. Ignore %gots against
13858 constants; we'll report an error for those later. */
13859 if (got16_reloc_p (l->fixp->fx_r_type)
13860 && !(l->fixp->fx_addsy
13861 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
13864 /* Check quickly whether the next fixup happens to be a matching %lo. */
13865 if (fixup_has_matching_lo_p (l->fixp))
13868 seginfo = seg_info (l->seg);
13870 /* Set HI_POS to the position of this relocation in the chain.
13871 Set LO_POS to the position of the chosen low-part relocation.
13872 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13873 relocation that matches an immediately-preceding high-part
13877 matched_lo_p = FALSE;
13878 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
13880 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
13882 if (*pos == l->fixp)
13885 if ((*pos)->fx_r_type == looking_for_rtype
13886 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
13887 && (*pos)->fx_offset >= l->fixp->fx_offset
13889 || (*pos)->fx_offset < (*lo_pos)->fx_offset
13891 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
13894 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
13895 && fixup_has_matching_lo_p (*pos));
13898 /* If we found a match, remove the high-part relocation from its
13899 current position and insert it before the low-part relocation.
13900 Make the offsets match so that fixup_has_matching_lo_p()
13903 We don't warn about unmatched high-part relocations since some
13904 versions of gcc have been known to emit dead "lui ...%hi(...)"
13906 if (lo_pos != NULL)
13908 l->fixp->fx_offset = (*lo_pos)->fx_offset;
13909 if (l->fixp->fx_next != *lo_pos)
13911 *hi_pos = l->fixp->fx_next;
13912 l->fixp->fx_next = *lo_pos;
13920 mips_force_relocation (fixS *fixp)
13922 if (generic_force_reloc (fixp))
13925 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13926 so that the linker relaxation can update targets. */
13927 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13928 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13929 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
13935 /* Read the instruction associated with RELOC from BUF. */
13937 static unsigned int
13938 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
13940 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13941 return read_compressed_insn (buf, 4);
13943 return read_insn (buf);
13946 /* Write instruction INSN to BUF, given that it has been relocated
13950 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
13951 unsigned long insn)
13953 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13954 write_compressed_insn (buf, insn, 4);
13956 write_insn (buf, insn);
13959 /* Apply a fixup to the object file. */
13962 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
13965 unsigned long insn;
13966 reloc_howto_type *howto;
13968 /* We ignore generic BFD relocations we don't know about. */
13969 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
13973 gas_assert (fixP->fx_size == 2
13974 || fixP->fx_size == 4
13975 || fixP->fx_r_type == BFD_RELOC_16
13976 || fixP->fx_r_type == BFD_RELOC_64
13977 || fixP->fx_r_type == BFD_RELOC_CTOR
13978 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
13979 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
13980 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13981 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
13982 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
13984 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
13986 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
13987 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13988 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13989 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
13990 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
13992 /* Don't treat parts of a composite relocation as done. There are two
13995 (1) The second and third parts will be against 0 (RSS_UNDEF) but
13996 should nevertheless be emitted if the first part is.
13998 (2) In normal usage, composite relocations are never assembly-time
13999 constants. The easiest way of dealing with the pathological
14000 exceptions is to generate a relocation against STN_UNDEF and
14001 leave everything up to the linker. */
14002 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14005 switch (fixP->fx_r_type)
14007 case BFD_RELOC_MIPS_TLS_GD:
14008 case BFD_RELOC_MIPS_TLS_LDM:
14009 case BFD_RELOC_MIPS_TLS_DTPREL32:
14010 case BFD_RELOC_MIPS_TLS_DTPREL64:
14011 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14012 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14013 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14014 case BFD_RELOC_MIPS_TLS_TPREL32:
14015 case BFD_RELOC_MIPS_TLS_TPREL64:
14016 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14017 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14018 case BFD_RELOC_MICROMIPS_TLS_GD:
14019 case BFD_RELOC_MICROMIPS_TLS_LDM:
14020 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14021 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14022 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14023 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14024 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14025 case BFD_RELOC_MIPS16_TLS_GD:
14026 case BFD_RELOC_MIPS16_TLS_LDM:
14027 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14028 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14029 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14030 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14031 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14032 if (!fixP->fx_addsy)
14034 as_bad_where (fixP->fx_file, fixP->fx_line,
14035 _("TLS relocation against a constant"));
14038 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14041 case BFD_RELOC_MIPS_JMP:
14042 case BFD_RELOC_MIPS_SHIFT5:
14043 case BFD_RELOC_MIPS_SHIFT6:
14044 case BFD_RELOC_MIPS_GOT_DISP:
14045 case BFD_RELOC_MIPS_GOT_PAGE:
14046 case BFD_RELOC_MIPS_GOT_OFST:
14047 case BFD_RELOC_MIPS_SUB:
14048 case BFD_RELOC_MIPS_INSERT_A:
14049 case BFD_RELOC_MIPS_INSERT_B:
14050 case BFD_RELOC_MIPS_DELETE:
14051 case BFD_RELOC_MIPS_HIGHEST:
14052 case BFD_RELOC_MIPS_HIGHER:
14053 case BFD_RELOC_MIPS_SCN_DISP:
14054 case BFD_RELOC_MIPS_REL16:
14055 case BFD_RELOC_MIPS_RELGOT:
14056 case BFD_RELOC_MIPS_JALR:
14057 case BFD_RELOC_HI16:
14058 case BFD_RELOC_HI16_S:
14059 case BFD_RELOC_LO16:
14060 case BFD_RELOC_GPREL16:
14061 case BFD_RELOC_MIPS_LITERAL:
14062 case BFD_RELOC_MIPS_CALL16:
14063 case BFD_RELOC_MIPS_GOT16:
14064 case BFD_RELOC_GPREL32:
14065 case BFD_RELOC_MIPS_GOT_HI16:
14066 case BFD_RELOC_MIPS_GOT_LO16:
14067 case BFD_RELOC_MIPS_CALL_HI16:
14068 case BFD_RELOC_MIPS_CALL_LO16:
14069 case BFD_RELOC_MIPS16_GPREL:
14070 case BFD_RELOC_MIPS16_GOT16:
14071 case BFD_RELOC_MIPS16_CALL16:
14072 case BFD_RELOC_MIPS16_HI16:
14073 case BFD_RELOC_MIPS16_HI16_S:
14074 case BFD_RELOC_MIPS16_LO16:
14075 case BFD_RELOC_MIPS16_JMP:
14076 case BFD_RELOC_MICROMIPS_JMP:
14077 case BFD_RELOC_MICROMIPS_GOT_DISP:
14078 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14079 case BFD_RELOC_MICROMIPS_GOT_OFST:
14080 case BFD_RELOC_MICROMIPS_SUB:
14081 case BFD_RELOC_MICROMIPS_HIGHEST:
14082 case BFD_RELOC_MICROMIPS_HIGHER:
14083 case BFD_RELOC_MICROMIPS_SCN_DISP:
14084 case BFD_RELOC_MICROMIPS_JALR:
14085 case BFD_RELOC_MICROMIPS_HI16:
14086 case BFD_RELOC_MICROMIPS_HI16_S:
14087 case BFD_RELOC_MICROMIPS_LO16:
14088 case BFD_RELOC_MICROMIPS_GPREL16:
14089 case BFD_RELOC_MICROMIPS_LITERAL:
14090 case BFD_RELOC_MICROMIPS_CALL16:
14091 case BFD_RELOC_MICROMIPS_GOT16:
14092 case BFD_RELOC_MICROMIPS_GOT_HI16:
14093 case BFD_RELOC_MICROMIPS_GOT_LO16:
14094 case BFD_RELOC_MICROMIPS_CALL_HI16:
14095 case BFD_RELOC_MICROMIPS_CALL_LO16:
14096 case BFD_RELOC_MIPS_EH:
14101 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14103 insn = read_reloc_insn (buf, fixP->fx_r_type);
14104 if (mips16_reloc_p (fixP->fx_r_type))
14105 insn |= mips16_immed_extend (value, 16);
14107 insn |= (value & 0xffff);
14108 write_reloc_insn (buf, fixP->fx_r_type, insn);
14111 as_bad_where (fixP->fx_file, fixP->fx_line,
14112 _("Unsupported constant in relocation"));
14117 /* This is handled like BFD_RELOC_32, but we output a sign
14118 extended value if we are only 32 bits. */
14121 if (8 <= sizeof (valueT))
14122 md_number_to_chars (buf, *valP, 8);
14127 if ((*valP & 0x80000000) != 0)
14131 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14132 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14137 case BFD_RELOC_RVA:
14139 case BFD_RELOC_32_PCREL:
14141 /* If we are deleting this reloc entry, we must fill in the
14142 value now. This can happen if we have a .word which is not
14143 resolved when it appears but is later defined. */
14145 md_number_to_chars (buf, *valP, fixP->fx_size);
14148 case BFD_RELOC_16_PCREL_S2:
14149 if ((*valP & 0x3) != 0)
14150 as_bad_where (fixP->fx_file, fixP->fx_line,
14151 _("Branch to misaligned address (%lx)"), (long) *valP);
14153 /* We need to save the bits in the instruction since fixup_segment()
14154 might be deleting the relocation entry (i.e., a branch within
14155 the current segment). */
14156 if (! fixP->fx_done)
14159 /* Update old instruction data. */
14160 insn = read_insn (buf);
14162 if (*valP + 0x20000 <= 0x3ffff)
14164 insn |= (*valP >> 2) & 0xffff;
14165 write_insn (buf, insn);
14167 else if (mips_pic == NO_PIC
14169 && fixP->fx_frag->fr_address >= text_section->vma
14170 && (fixP->fx_frag->fr_address
14171 < text_section->vma + bfd_get_section_size (text_section))
14172 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14173 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14174 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14176 /* The branch offset is too large. If this is an
14177 unconditional branch, and we are not generating PIC code,
14178 we can convert it to an absolute jump instruction. */
14179 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14180 insn = 0x0c000000; /* jal */
14182 insn = 0x08000000; /* j */
14183 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14185 fixP->fx_addsy = section_symbol (text_section);
14186 *valP += md_pcrel_from (fixP);
14187 write_insn (buf, insn);
14191 /* If we got here, we have branch-relaxation disabled,
14192 and there's nothing we can do to fix this instruction
14193 without turning it into a longer sequence. */
14194 as_bad_where (fixP->fx_file, fixP->fx_line,
14195 _("Branch out of range"));
14199 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14200 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14201 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14202 /* We adjust the offset back to even. */
14203 if ((*valP & 0x1) != 0)
14206 if (! fixP->fx_done)
14209 /* Should never visit here, because we keep the relocation. */
14213 case BFD_RELOC_VTABLE_INHERIT:
14216 && !S_IS_DEFINED (fixP->fx_addsy)
14217 && !S_IS_WEAK (fixP->fx_addsy))
14218 S_SET_WEAK (fixP->fx_addsy);
14221 case BFD_RELOC_VTABLE_ENTRY:
14229 /* Remember value for tc_gen_reloc. */
14230 fixP->fx_addnumber = *valP;
14240 name = input_line_pointer;
14241 c = get_symbol_end ();
14242 p = (symbolS *) symbol_find_or_make (name);
14243 *input_line_pointer = c;
14247 /* Align the current frag to a given power of two. If a particular
14248 fill byte should be used, FILL points to an integer that contains
14249 that byte, otherwise FILL is null.
14251 This function used to have the comment:
14253 The MIPS assembler also automatically adjusts any preceding label.
14255 The implementation therefore applied the adjustment to a maximum of
14256 one label. However, other label adjustments are applied to batches
14257 of labels, and adjusting just one caused problems when new labels
14258 were added for the sake of debugging or unwind information.
14259 We therefore adjust all preceding labels (given as LABELS) instead. */
14262 mips_align (int to, int *fill, struct insn_label_list *labels)
14264 mips_emit_delays ();
14265 mips_record_compressed_mode ();
14266 if (fill == NULL && subseg_text_p (now_seg))
14267 frag_align_code (to, 0);
14269 frag_align (to, fill ? *fill : 0, 0);
14270 record_alignment (now_seg, to);
14271 mips_move_labels (labels, FALSE);
14274 /* Align to a given power of two. .align 0 turns off the automatic
14275 alignment used by the data creating pseudo-ops. */
14278 s_align (int x ATTRIBUTE_UNUSED)
14280 int temp, fill_value, *fill_ptr;
14281 long max_alignment = 28;
14283 /* o Note that the assembler pulls down any immediately preceding label
14284 to the aligned address.
14285 o It's not documented but auto alignment is reinstated by
14286 a .align pseudo instruction.
14287 o Note also that after auto alignment is turned off the mips assembler
14288 issues an error on attempt to assemble an improperly aligned data item.
14291 temp = get_absolute_expression ();
14292 if (temp > max_alignment)
14293 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14296 as_warn (_("Alignment negative: 0 assumed."));
14299 if (*input_line_pointer == ',')
14301 ++input_line_pointer;
14302 fill_value = get_absolute_expression ();
14303 fill_ptr = &fill_value;
14309 segment_info_type *si = seg_info (now_seg);
14310 struct insn_label_list *l = si->label_list;
14311 /* Auto alignment should be switched on by next section change. */
14313 mips_align (temp, fill_ptr, l);
14320 demand_empty_rest_of_line ();
14324 s_change_sec (int sec)
14328 /* The ELF backend needs to know that we are changing sections, so
14329 that .previous works correctly. We could do something like check
14330 for an obj_section_change_hook macro, but that might be confusing
14331 as it would not be appropriate to use it in the section changing
14332 functions in read.c, since obj-elf.c intercepts those. FIXME:
14333 This should be cleaner, somehow. */
14334 obj_elf_section_change_hook ();
14336 mips_emit_delays ();
14347 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14348 demand_empty_rest_of_line ();
14352 seg = subseg_new (RDATA_SECTION_NAME,
14353 (subsegT) get_absolute_expression ());
14354 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14355 | SEC_READONLY | SEC_RELOC
14357 if (strncmp (TARGET_OS, "elf", 3) != 0)
14358 record_alignment (seg, 4);
14359 demand_empty_rest_of_line ();
14363 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14364 bfd_set_section_flags (stdoutput, seg,
14365 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14366 if (strncmp (TARGET_OS, "elf", 3) != 0)
14367 record_alignment (seg, 4);
14368 demand_empty_rest_of_line ();
14372 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14373 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14374 if (strncmp (TARGET_OS, "elf", 3) != 0)
14375 record_alignment (seg, 4);
14376 demand_empty_rest_of_line ();
14384 s_change_section (int ignore ATTRIBUTE_UNUSED)
14386 char *section_name;
14391 int section_entry_size;
14392 int section_alignment;
14394 section_name = input_line_pointer;
14395 c = get_symbol_end ();
14397 next_c = *(input_line_pointer + 1);
14399 /* Do we have .section Name<,"flags">? */
14400 if (c != ',' || (c == ',' && next_c == '"'))
14402 /* just after name is now '\0'. */
14403 *input_line_pointer = c;
14404 input_line_pointer = section_name;
14405 obj_elf_section (ignore);
14408 input_line_pointer++;
14410 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14412 section_type = get_absolute_expression ();
14415 if (*input_line_pointer++ == ',')
14416 section_flag = get_absolute_expression ();
14419 if (*input_line_pointer++ == ',')
14420 section_entry_size = get_absolute_expression ();
14422 section_entry_size = 0;
14423 if (*input_line_pointer++ == ',')
14424 section_alignment = get_absolute_expression ();
14426 section_alignment = 0;
14427 /* FIXME: really ignore? */
14428 (void) section_alignment;
14430 section_name = xstrdup (section_name);
14432 /* When using the generic form of .section (as implemented by obj-elf.c),
14433 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14434 traditionally had to fall back on the more common @progbits instead.
14436 There's nothing really harmful in this, since bfd will correct
14437 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14438 means that, for backwards compatibility, the special_section entries
14439 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14441 Even so, we shouldn't force users of the MIPS .section syntax to
14442 incorrectly label the sections as SHT_PROGBITS. The best compromise
14443 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14444 generic type-checking code. */
14445 if (section_type == SHT_MIPS_DWARF)
14446 section_type = SHT_PROGBITS;
14448 obj_elf_change_section (section_name, section_type, section_flag,
14449 section_entry_size, 0, 0, 0);
14451 if (now_seg->name != section_name)
14452 free (section_name);
14456 mips_enable_auto_align (void)
14462 s_cons (int log_size)
14464 segment_info_type *si = seg_info (now_seg);
14465 struct insn_label_list *l = si->label_list;
14467 mips_emit_delays ();
14468 if (log_size > 0 && auto_align)
14469 mips_align (log_size, 0, l);
14470 cons (1 << log_size);
14471 mips_clear_insn_labels ();
14475 s_float_cons (int type)
14477 segment_info_type *si = seg_info (now_seg);
14478 struct insn_label_list *l = si->label_list;
14480 mips_emit_delays ();
14485 mips_align (3, 0, l);
14487 mips_align (2, 0, l);
14491 mips_clear_insn_labels ();
14494 /* Handle .globl. We need to override it because on Irix 5 you are
14497 where foo is an undefined symbol, to mean that foo should be
14498 considered to be the address of a function. */
14501 s_mips_globl (int x ATTRIBUTE_UNUSED)
14510 name = input_line_pointer;
14511 c = get_symbol_end ();
14512 symbolP = symbol_find_or_make (name);
14513 S_SET_EXTERNAL (symbolP);
14515 *input_line_pointer = c;
14516 SKIP_WHITESPACE ();
14518 /* On Irix 5, every global symbol that is not explicitly labelled as
14519 being a function is apparently labelled as being an object. */
14522 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14523 && (*input_line_pointer != ','))
14528 secname = input_line_pointer;
14529 c = get_symbol_end ();
14530 sec = bfd_get_section_by_name (stdoutput, secname);
14532 as_bad (_("%s: no such section"), secname);
14533 *input_line_pointer = c;
14535 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14536 flag = BSF_FUNCTION;
14539 symbol_get_bfdsym (symbolP)->flags |= flag;
14541 c = *input_line_pointer;
14544 input_line_pointer++;
14545 SKIP_WHITESPACE ();
14546 if (is_end_of_line[(unsigned char) *input_line_pointer])
14552 demand_empty_rest_of_line ();
14556 s_option (int x ATTRIBUTE_UNUSED)
14561 opt = input_line_pointer;
14562 c = get_symbol_end ();
14566 /* FIXME: What does this mean? */
14568 else if (strncmp (opt, "pic", 3) == 0)
14572 i = atoi (opt + 3);
14577 mips_pic = SVR4_PIC;
14578 mips_abicalls = TRUE;
14581 as_bad (_(".option pic%d not supported"), i);
14583 if (mips_pic == SVR4_PIC)
14585 if (g_switch_seen && g_switch_value != 0)
14586 as_warn (_("-G may not be used with SVR4 PIC code"));
14587 g_switch_value = 0;
14588 bfd_set_gp_size (stdoutput, 0);
14592 as_warn (_("Unrecognized option \"%s\""), opt);
14594 *input_line_pointer = c;
14595 demand_empty_rest_of_line ();
14598 /* This structure is used to hold a stack of .set values. */
14600 struct mips_option_stack
14602 struct mips_option_stack *next;
14603 struct mips_set_options options;
14606 static struct mips_option_stack *mips_opts_stack;
14608 /* Handle the .set pseudo-op. */
14611 s_mipsset (int x ATTRIBUTE_UNUSED)
14613 char *name = input_line_pointer, ch;
14614 const struct mips_ase *ase;
14616 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14617 ++input_line_pointer;
14618 ch = *input_line_pointer;
14619 *input_line_pointer = '\0';
14621 if (strcmp (name, "reorder") == 0)
14623 if (mips_opts.noreorder)
14626 else if (strcmp (name, "noreorder") == 0)
14628 if (!mips_opts.noreorder)
14629 start_noreorder ();
14631 else if (strncmp (name, "at=", 3) == 0)
14633 char *s = name + 3;
14635 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14636 as_bad (_("Unrecognized register name `%s'"), s);
14638 else if (strcmp (name, "at") == 0)
14640 mips_opts.at = ATREG;
14642 else if (strcmp (name, "noat") == 0)
14644 mips_opts.at = ZERO;
14646 else if (strcmp (name, "macro") == 0)
14648 mips_opts.warn_about_macros = 0;
14650 else if (strcmp (name, "nomacro") == 0)
14652 if (mips_opts.noreorder == 0)
14653 as_bad (_("`noreorder' must be set before `nomacro'"));
14654 mips_opts.warn_about_macros = 1;
14656 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14658 mips_opts.nomove = 0;
14660 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14662 mips_opts.nomove = 1;
14664 else if (strcmp (name, "bopt") == 0)
14666 mips_opts.nobopt = 0;
14668 else if (strcmp (name, "nobopt") == 0)
14670 mips_opts.nobopt = 1;
14672 else if (strcmp (name, "gp=default") == 0)
14673 mips_opts.gp32 = file_mips_gp32;
14674 else if (strcmp (name, "gp=32") == 0)
14675 mips_opts.gp32 = 1;
14676 else if (strcmp (name, "gp=64") == 0)
14678 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14679 as_warn (_("%s isa does not support 64-bit registers"),
14680 mips_cpu_info_from_isa (mips_opts.isa)->name);
14681 mips_opts.gp32 = 0;
14683 else if (strcmp (name, "fp=default") == 0)
14684 mips_opts.fp32 = file_mips_fp32;
14685 else if (strcmp (name, "fp=32") == 0)
14686 mips_opts.fp32 = 1;
14687 else if (strcmp (name, "fp=64") == 0)
14689 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14690 as_warn (_("%s isa does not support 64-bit floating point registers"),
14691 mips_cpu_info_from_isa (mips_opts.isa)->name);
14692 mips_opts.fp32 = 0;
14694 else if (strcmp (name, "softfloat") == 0)
14695 mips_opts.soft_float = 1;
14696 else if (strcmp (name, "hardfloat") == 0)
14697 mips_opts.soft_float = 0;
14698 else if (strcmp (name, "singlefloat") == 0)
14699 mips_opts.single_float = 1;
14700 else if (strcmp (name, "doublefloat") == 0)
14701 mips_opts.single_float = 0;
14702 else if (strcmp (name, "mips16") == 0
14703 || strcmp (name, "MIPS-16") == 0)
14705 if (mips_opts.micromips == 1)
14706 as_fatal (_("`mips16' cannot be used with `micromips'"));
14707 mips_opts.mips16 = 1;
14709 else if (strcmp (name, "nomips16") == 0
14710 || strcmp (name, "noMIPS-16") == 0)
14711 mips_opts.mips16 = 0;
14712 else if (strcmp (name, "micromips") == 0)
14714 if (mips_opts.mips16 == 1)
14715 as_fatal (_("`micromips' cannot be used with `mips16'"));
14716 mips_opts.micromips = 1;
14718 else if (strcmp (name, "nomicromips") == 0)
14719 mips_opts.micromips = 0;
14720 else if (name[0] == 'n'
14722 && (ase = mips_lookup_ase (name + 2)))
14723 mips_set_ase (ase, FALSE);
14724 else if ((ase = mips_lookup_ase (name)))
14725 mips_set_ase (ase, TRUE);
14726 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
14730 /* Permit the user to change the ISA and architecture on the fly.
14731 Needless to say, misuse can cause serious problems. */
14732 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
14735 mips_opts.isa = file_mips_isa;
14736 mips_opts.arch = file_mips_arch;
14738 else if (strncmp (name, "arch=", 5) == 0)
14740 const struct mips_cpu_info *p;
14742 p = mips_parse_cpu("internal use", name + 5);
14744 as_bad (_("unknown architecture %s"), name + 5);
14747 mips_opts.arch = p->cpu;
14748 mips_opts.isa = p->isa;
14751 else if (strncmp (name, "mips", 4) == 0)
14753 const struct mips_cpu_info *p;
14755 p = mips_parse_cpu("internal use", name);
14757 as_bad (_("unknown ISA level %s"), name + 4);
14760 mips_opts.arch = p->cpu;
14761 mips_opts.isa = p->isa;
14765 as_bad (_("unknown ISA or architecture %s"), name);
14767 switch (mips_opts.isa)
14775 mips_opts.gp32 = 1;
14776 mips_opts.fp32 = 1;
14783 mips_opts.gp32 = 0;
14784 if (mips_opts.arch == CPU_R5900)
14786 mips_opts.fp32 = 1;
14790 mips_opts.fp32 = 0;
14794 as_bad (_("unknown ISA level %s"), name + 4);
14799 mips_opts.gp32 = file_mips_gp32;
14800 mips_opts.fp32 = file_mips_fp32;
14803 else if (strcmp (name, "autoextend") == 0)
14804 mips_opts.noautoextend = 0;
14805 else if (strcmp (name, "noautoextend") == 0)
14806 mips_opts.noautoextend = 1;
14807 else if (strcmp (name, "insn32") == 0)
14808 mips_opts.insn32 = TRUE;
14809 else if (strcmp (name, "noinsn32") == 0)
14810 mips_opts.insn32 = FALSE;
14811 else if (strcmp (name, "push") == 0)
14813 struct mips_option_stack *s;
14815 s = (struct mips_option_stack *) xmalloc (sizeof *s);
14816 s->next = mips_opts_stack;
14817 s->options = mips_opts;
14818 mips_opts_stack = s;
14820 else if (strcmp (name, "pop") == 0)
14822 struct mips_option_stack *s;
14824 s = mips_opts_stack;
14826 as_bad (_(".set pop with no .set push"));
14829 /* If we're changing the reorder mode we need to handle
14830 delay slots correctly. */
14831 if (s->options.noreorder && ! mips_opts.noreorder)
14832 start_noreorder ();
14833 else if (! s->options.noreorder && mips_opts.noreorder)
14836 mips_opts = s->options;
14837 mips_opts_stack = s->next;
14841 else if (strcmp (name, "sym32") == 0)
14842 mips_opts.sym32 = TRUE;
14843 else if (strcmp (name, "nosym32") == 0)
14844 mips_opts.sym32 = FALSE;
14845 else if (strchr (name, ','))
14847 /* Generic ".set" directive; use the generic handler. */
14848 *input_line_pointer = ch;
14849 input_line_pointer = name;
14855 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
14857 mips_check_isa_supports_ases ();
14858 *input_line_pointer = ch;
14859 demand_empty_rest_of_line ();
14862 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14863 .option pic2. It means to generate SVR4 PIC calls. */
14866 s_abicalls (int ignore ATTRIBUTE_UNUSED)
14868 mips_pic = SVR4_PIC;
14869 mips_abicalls = TRUE;
14871 if (g_switch_seen && g_switch_value != 0)
14872 as_warn (_("-G may not be used with SVR4 PIC code"));
14873 g_switch_value = 0;
14875 bfd_set_gp_size (stdoutput, 0);
14876 demand_empty_rest_of_line ();
14879 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14880 PIC code. It sets the $gp register for the function based on the
14881 function address, which is in the register named in the argument.
14882 This uses a relocation against _gp_disp, which is handled specially
14883 by the linker. The result is:
14884 lui $gp,%hi(_gp_disp)
14885 addiu $gp,$gp,%lo(_gp_disp)
14886 addu $gp,$gp,.cpload argument
14887 The .cpload argument is normally $25 == $t9.
14889 The -mno-shared option changes this to:
14890 lui $gp,%hi(__gnu_local_gp)
14891 addiu $gp,$gp,%lo(__gnu_local_gp)
14892 and the argument is ignored. This saves an instruction, but the
14893 resulting code is not position independent; it uses an absolute
14894 address for __gnu_local_gp. Thus code assembled with -mno-shared
14895 can go into an ordinary executable, but not into a shared library. */
14898 s_cpload (int ignore ATTRIBUTE_UNUSED)
14904 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14905 .cpload is ignored. */
14906 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
14912 if (mips_opts.mips16)
14914 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14915 ignore_rest_of_line ();
14919 /* .cpload should be in a .set noreorder section. */
14920 if (mips_opts.noreorder == 0)
14921 as_warn (_(".cpload not in noreorder section"));
14923 reg = tc_get_register (0);
14925 /* If we need to produce a 64-bit address, we are better off using
14926 the default instruction sequence. */
14927 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
14929 ex.X_op = O_symbol;
14930 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
14932 ex.X_op_symbol = NULL;
14933 ex.X_add_number = 0;
14935 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14936 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
14938 mips_mark_labels ();
14939 mips_assembling_insn = TRUE;
14942 macro_build_lui (&ex, mips_gp_register);
14943 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
14944 mips_gp_register, BFD_RELOC_LO16);
14946 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
14947 mips_gp_register, reg);
14950 mips_assembling_insn = FALSE;
14951 demand_empty_rest_of_line ();
14954 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14955 .cpsetup $reg1, offset|$reg2, label
14957 If offset is given, this results in:
14958 sd $gp, offset($sp)
14959 lui $gp, %hi(%neg(%gp_rel(label)))
14960 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14961 daddu $gp, $gp, $reg1
14963 If $reg2 is given, this results in:
14964 daddu $reg2, $gp, $0
14965 lui $gp, %hi(%neg(%gp_rel(label)))
14966 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14967 daddu $gp, $gp, $reg1
14968 $reg1 is normally $25 == $t9.
14970 The -mno-shared option replaces the last three instructions with
14972 addiu $gp,$gp,%lo(_gp) */
14975 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
14977 expressionS ex_off;
14978 expressionS ex_sym;
14981 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14982 We also need NewABI support. */
14983 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14989 if (mips_opts.mips16)
14991 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
14992 ignore_rest_of_line ();
14996 reg1 = tc_get_register (0);
14997 SKIP_WHITESPACE ();
14998 if (*input_line_pointer != ',')
15000 as_bad (_("missing argument separator ',' for .cpsetup"));
15004 ++input_line_pointer;
15005 SKIP_WHITESPACE ();
15006 if (*input_line_pointer == '$')
15008 mips_cpreturn_register = tc_get_register (0);
15009 mips_cpreturn_offset = -1;
15013 mips_cpreturn_offset = get_absolute_expression ();
15014 mips_cpreturn_register = -1;
15016 SKIP_WHITESPACE ();
15017 if (*input_line_pointer != ',')
15019 as_bad (_("missing argument separator ',' for .cpsetup"));
15023 ++input_line_pointer;
15024 SKIP_WHITESPACE ();
15025 expression (&ex_sym);
15027 mips_mark_labels ();
15028 mips_assembling_insn = TRUE;
15031 if (mips_cpreturn_register == -1)
15033 ex_off.X_op = O_constant;
15034 ex_off.X_add_symbol = NULL;
15035 ex_off.X_op_symbol = NULL;
15036 ex_off.X_add_number = mips_cpreturn_offset;
15038 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15039 BFD_RELOC_LO16, SP);
15042 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15043 mips_gp_register, 0);
15045 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15047 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15048 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15051 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15052 mips_gp_register, -1, BFD_RELOC_GPREL16,
15053 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15055 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15056 mips_gp_register, reg1);
15062 ex.X_op = O_symbol;
15063 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15064 ex.X_op_symbol = NULL;
15065 ex.X_add_number = 0;
15067 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15068 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15070 macro_build_lui (&ex, mips_gp_register);
15071 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15072 mips_gp_register, BFD_RELOC_LO16);
15077 mips_assembling_insn = FALSE;
15078 demand_empty_rest_of_line ();
15082 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15084 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15085 .cplocal is ignored. */
15086 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15092 if (mips_opts.mips16)
15094 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15095 ignore_rest_of_line ();
15099 mips_gp_register = tc_get_register (0);
15100 demand_empty_rest_of_line ();
15103 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15104 offset from $sp. The offset is remembered, and after making a PIC
15105 call $gp is restored from that location. */
15108 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15112 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15113 .cprestore is ignored. */
15114 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15120 if (mips_opts.mips16)
15122 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15123 ignore_rest_of_line ();
15127 mips_cprestore_offset = get_absolute_expression ();
15128 mips_cprestore_valid = 1;
15130 ex.X_op = O_constant;
15131 ex.X_add_symbol = NULL;
15132 ex.X_op_symbol = NULL;
15133 ex.X_add_number = mips_cprestore_offset;
15135 mips_mark_labels ();
15136 mips_assembling_insn = TRUE;
15139 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15140 SP, HAVE_64BIT_ADDRESSES);
15143 mips_assembling_insn = FALSE;
15144 demand_empty_rest_of_line ();
15147 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15148 was given in the preceding .cpsetup, it results in:
15149 ld $gp, offset($sp)
15151 If a register $reg2 was given there, it results in:
15152 daddu $gp, $reg2, $0 */
15155 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15159 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15160 We also need NewABI support. */
15161 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15167 if (mips_opts.mips16)
15169 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15170 ignore_rest_of_line ();
15174 mips_mark_labels ();
15175 mips_assembling_insn = TRUE;
15178 if (mips_cpreturn_register == -1)
15180 ex.X_op = O_constant;
15181 ex.X_add_symbol = NULL;
15182 ex.X_op_symbol = NULL;
15183 ex.X_add_number = mips_cpreturn_offset;
15185 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15188 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15189 mips_cpreturn_register, 0);
15192 mips_assembling_insn = FALSE;
15193 demand_empty_rest_of_line ();
15196 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15197 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15198 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15199 debug information or MIPS16 TLS. */
15202 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15203 bfd_reloc_code_real_type rtype)
15210 if (ex.X_op != O_symbol)
15212 as_bad (_("Unsupported use of %s"), dirstr);
15213 ignore_rest_of_line ();
15216 p = frag_more (bytes);
15217 md_number_to_chars (p, 0, bytes);
15218 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15219 demand_empty_rest_of_line ();
15220 mips_clear_insn_labels ();
15223 /* Handle .dtprelword. */
15226 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15228 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15231 /* Handle .dtpreldword. */
15234 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15236 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15239 /* Handle .tprelword. */
15242 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15244 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15247 /* Handle .tpreldword. */
15250 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15252 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15255 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15256 code. It sets the offset to use in gp_rel relocations. */
15259 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15261 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15262 We also need NewABI support. */
15263 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15269 mips_gprel_offset = get_absolute_expression ();
15271 demand_empty_rest_of_line ();
15274 /* Handle the .gpword pseudo-op. This is used when generating PIC
15275 code. It generates a 32 bit GP relative reloc. */
15278 s_gpword (int ignore ATTRIBUTE_UNUSED)
15280 segment_info_type *si;
15281 struct insn_label_list *l;
15285 /* When not generating PIC code, this is treated as .word. */
15286 if (mips_pic != SVR4_PIC)
15292 si = seg_info (now_seg);
15293 l = si->label_list;
15294 mips_emit_delays ();
15296 mips_align (2, 0, l);
15299 mips_clear_insn_labels ();
15301 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15303 as_bad (_("Unsupported use of .gpword"));
15304 ignore_rest_of_line ();
15308 md_number_to_chars (p, 0, 4);
15309 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15310 BFD_RELOC_GPREL32);
15312 demand_empty_rest_of_line ();
15316 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15318 segment_info_type *si;
15319 struct insn_label_list *l;
15323 /* When not generating PIC code, this is treated as .dword. */
15324 if (mips_pic != SVR4_PIC)
15330 si = seg_info (now_seg);
15331 l = si->label_list;
15332 mips_emit_delays ();
15334 mips_align (3, 0, l);
15337 mips_clear_insn_labels ();
15339 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15341 as_bad (_("Unsupported use of .gpdword"));
15342 ignore_rest_of_line ();
15346 md_number_to_chars (p, 0, 8);
15347 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15348 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15350 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15351 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15352 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15354 demand_empty_rest_of_line ();
15357 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15358 tables. It generates a R_MIPS_EH reloc. */
15361 s_ehword (int ignore ATTRIBUTE_UNUSED)
15366 mips_emit_delays ();
15369 mips_clear_insn_labels ();
15371 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15373 as_bad (_("Unsupported use of .ehword"));
15374 ignore_rest_of_line ();
15378 md_number_to_chars (p, 0, 4);
15379 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15380 BFD_RELOC_MIPS_EH);
15382 demand_empty_rest_of_line ();
15385 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15386 tables in SVR4 PIC code. */
15389 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15393 /* This is ignored when not generating SVR4 PIC code. */
15394 if (mips_pic != SVR4_PIC)
15400 mips_mark_labels ();
15401 mips_assembling_insn = TRUE;
15403 /* Add $gp to the register named as an argument. */
15405 reg = tc_get_register (0);
15406 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15409 mips_assembling_insn = FALSE;
15410 demand_empty_rest_of_line ();
15413 /* Handle the .insn pseudo-op. This marks instruction labels in
15414 mips16/micromips mode. This permits the linker to handle them specially,
15415 such as generating jalx instructions when needed. We also make
15416 them odd for the duration of the assembly, in order to generate the
15417 right sort of code. We will make them even in the adjust_symtab
15418 routine, while leaving them marked. This is convenient for the
15419 debugger and the disassembler. The linker knows to make them odd
15423 s_insn (int ignore ATTRIBUTE_UNUSED)
15425 mips_mark_labels ();
15427 demand_empty_rest_of_line ();
15430 /* Handle the .nan pseudo-op. */
15433 s_nan (int ignore ATTRIBUTE_UNUSED)
15435 static const char str_legacy[] = "legacy";
15436 static const char str_2008[] = "2008";
15439 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15441 if (i == sizeof (str_2008) - 1
15442 && memcmp (input_line_pointer, str_2008, i) == 0)
15443 mips_flag_nan2008 = TRUE;
15444 else if (i == sizeof (str_legacy) - 1
15445 && memcmp (input_line_pointer, str_legacy, i) == 0)
15446 mips_flag_nan2008 = FALSE;
15448 as_bad (_("Bad .nan directive"));
15450 input_line_pointer += i;
15451 demand_empty_rest_of_line ();
15454 /* Handle a .stab[snd] directive. Ideally these directives would be
15455 implemented in a transparent way, so that removing them would not
15456 have any effect on the generated instructions. However, s_stab
15457 internally changes the section, so in practice we need to decide
15458 now whether the preceding label marks compressed code. We do not
15459 support changing the compression mode of a label after a .stab*
15460 directive, such as in:
15466 so the current mode wins. */
15469 s_mips_stab (int type)
15471 mips_mark_labels ();
15475 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15478 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15485 name = input_line_pointer;
15486 c = get_symbol_end ();
15487 symbolP = symbol_find_or_make (name);
15488 S_SET_WEAK (symbolP);
15489 *input_line_pointer = c;
15491 SKIP_WHITESPACE ();
15493 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15495 if (S_IS_DEFINED (symbolP))
15497 as_bad (_("ignoring attempt to redefine symbol %s"),
15498 S_GET_NAME (symbolP));
15499 ignore_rest_of_line ();
15503 if (*input_line_pointer == ',')
15505 ++input_line_pointer;
15506 SKIP_WHITESPACE ();
15510 if (exp.X_op != O_symbol)
15512 as_bad (_("bad .weakext directive"));
15513 ignore_rest_of_line ();
15516 symbol_set_value_expression (symbolP, &exp);
15519 demand_empty_rest_of_line ();
15522 /* Parse a register string into a number. Called from the ECOFF code
15523 to parse .frame. The argument is non-zero if this is the frame
15524 register, so that we can record it in mips_frame_reg. */
15527 tc_get_register (int frame)
15531 SKIP_WHITESPACE ();
15532 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15536 mips_frame_reg = reg != 0 ? reg : SP;
15537 mips_frame_reg_valid = 1;
15538 mips_cprestore_valid = 0;
15544 md_section_align (asection *seg, valueT addr)
15546 int align = bfd_get_section_alignment (stdoutput, seg);
15548 /* We don't need to align ELF sections to the full alignment.
15549 However, Irix 5 may prefer that we align them at least to a 16
15550 byte boundary. We don't bother to align the sections if we
15551 are targeted for an embedded system. */
15552 if (strncmp (TARGET_OS, "elf", 3) == 0)
15557 return ((addr + (1 << align) - 1) & (-1 << align));
15560 /* Utility routine, called from above as well. If called while the
15561 input file is still being read, it's only an approximation. (For
15562 example, a symbol may later become defined which appeared to be
15563 undefined earlier.) */
15566 nopic_need_relax (symbolS *sym, int before_relaxing)
15571 if (g_switch_value > 0)
15573 const char *symname;
15576 /* Find out whether this symbol can be referenced off the $gp
15577 register. It can be if it is smaller than the -G size or if
15578 it is in the .sdata or .sbss section. Certain symbols can
15579 not be referenced off the $gp, although it appears as though
15581 symname = S_GET_NAME (sym);
15582 if (symname != (const char *) NULL
15583 && (strcmp (symname, "eprol") == 0
15584 || strcmp (symname, "etext") == 0
15585 || strcmp (symname, "_gp") == 0
15586 || strcmp (symname, "edata") == 0
15587 || strcmp (symname, "_fbss") == 0
15588 || strcmp (symname, "_fdata") == 0
15589 || strcmp (symname, "_ftext") == 0
15590 || strcmp (symname, "end") == 0
15591 || strcmp (symname, "_gp_disp") == 0))
15593 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15595 #ifndef NO_ECOFF_DEBUGGING
15596 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15597 && (symbol_get_obj (sym)->ecoff_extern_size
15598 <= g_switch_value))
15600 /* We must defer this decision until after the whole
15601 file has been read, since there might be a .extern
15602 after the first use of this symbol. */
15603 || (before_relaxing
15604 #ifndef NO_ECOFF_DEBUGGING
15605 && symbol_get_obj (sym)->ecoff_extern_size == 0
15607 && S_GET_VALUE (sym) == 0)
15608 || (S_GET_VALUE (sym) != 0
15609 && S_GET_VALUE (sym) <= g_switch_value)))
15613 const char *segname;
15615 segname = segment_name (S_GET_SEGMENT (sym));
15616 gas_assert (strcmp (segname, ".lit8") != 0
15617 && strcmp (segname, ".lit4") != 0);
15618 change = (strcmp (segname, ".sdata") != 0
15619 && strcmp (segname, ".sbss") != 0
15620 && strncmp (segname, ".sdata.", 7) != 0
15621 && strncmp (segname, ".sbss.", 6) != 0
15622 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15623 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15628 /* We are not optimizing for the $gp register. */
15633 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15636 pic_need_relax (symbolS *sym, asection *segtype)
15640 /* Handle the case of a symbol equated to another symbol. */
15641 while (symbol_equated_reloc_p (sym))
15645 /* It's possible to get a loop here in a badly written program. */
15646 n = symbol_get_value_expression (sym)->X_add_symbol;
15652 if (symbol_section_p (sym))
15655 symsec = S_GET_SEGMENT (sym);
15657 /* This must duplicate the test in adjust_reloc_syms. */
15658 return (!bfd_is_und_section (symsec)
15659 && !bfd_is_abs_section (symsec)
15660 && !bfd_is_com_section (symsec)
15661 && !s_is_linkonce (sym, segtype)
15662 /* A global or weak symbol is treated as external. */
15663 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15667 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15668 extended opcode. SEC is the section the frag is in. */
15671 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15674 const struct mips16_immed_operand *op;
15676 int mintiny, maxtiny;
15680 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15682 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15685 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15686 op = mips16_immed_operands;
15687 while (op->type != type)
15690 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
15695 if (type == '<' || type == '>' || type == '[' || type == ']')
15698 maxtiny = 1 << op->nbits;
15703 maxtiny = (1 << op->nbits) - 1;
15708 mintiny = - (1 << (op->nbits - 1));
15709 maxtiny = (1 << (op->nbits - 1)) - 1;
15712 sym_frag = symbol_get_frag (fragp->fr_symbol);
15713 val = S_GET_VALUE (fragp->fr_symbol);
15714 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15720 /* We won't have the section when we are called from
15721 mips_relax_frag. However, we will always have been called
15722 from md_estimate_size_before_relax first. If this is a
15723 branch to a different section, we mark it as such. If SEC is
15724 NULL, and the frag is not marked, then it must be a branch to
15725 the same section. */
15728 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15733 /* Must have been called from md_estimate_size_before_relax. */
15736 fragp->fr_subtype =
15737 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15739 /* FIXME: We should support this, and let the linker
15740 catch branches and loads that are out of range. */
15741 as_bad_where (fragp->fr_file, fragp->fr_line,
15742 _("unsupported PC relative reference to different section"));
15746 if (fragp != sym_frag && sym_frag->fr_address == 0)
15747 /* Assume non-extended on the first relaxation pass.
15748 The address we have calculated will be bogus if this is
15749 a forward branch to another frag, as the forward frag
15750 will have fr_address == 0. */
15754 /* In this case, we know for sure that the symbol fragment is in
15755 the same section. If the relax_marker of the symbol fragment
15756 differs from the relax_marker of this fragment, we have not
15757 yet adjusted the symbol fragment fr_address. We want to add
15758 in STRETCH in order to get a better estimate of the address.
15759 This particularly matters because of the shift bits. */
15761 && sym_frag->relax_marker != fragp->relax_marker)
15765 /* Adjust stretch for any alignment frag. Note that if have
15766 been expanding the earlier code, the symbol may be
15767 defined in what appears to be an earlier frag. FIXME:
15768 This doesn't handle the fr_subtype field, which specifies
15769 a maximum number of bytes to skip when doing an
15771 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
15773 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
15776 stretch = - ((- stretch)
15777 & ~ ((1 << (int) f->fr_offset) - 1));
15779 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
15788 addr = fragp->fr_address + fragp->fr_fix;
15790 /* The base address rules are complicated. The base address of
15791 a branch is the following instruction. The base address of a
15792 PC relative load or add is the instruction itself, but if it
15793 is in a delay slot (in which case it can not be extended) use
15794 the address of the instruction whose delay slot it is in. */
15795 if (type == 'p' || type == 'q')
15799 /* If we are currently assuming that this frag should be
15800 extended, then, the current address is two bytes
15802 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
15805 /* Ignore the low bit in the target, since it will be set
15806 for a text label. */
15807 if ((val & 1) != 0)
15810 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
15812 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
15815 val -= addr & ~ ((1 << op->shift) - 1);
15817 /* Branch offsets have an implicit 0 in the lowest bit. */
15818 if (type == 'p' || type == 'q')
15821 /* If any of the shifted bits are set, we must use an extended
15822 opcode. If the address depends on the size of this
15823 instruction, this can lead to a loop, so we arrange to always
15824 use an extended opcode. We only check this when we are in
15825 the main relaxation loop, when SEC is NULL. */
15826 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
15828 fragp->fr_subtype =
15829 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15833 /* If we are about to mark a frag as extended because the value
15834 is precisely maxtiny + 1, then there is a chance of an
15835 infinite loop as in the following code:
15840 In this case when the la is extended, foo is 0x3fc bytes
15841 away, so the la can be shrunk, but then foo is 0x400 away, so
15842 the la must be extended. To avoid this loop, we mark the
15843 frag as extended if it was small, and is about to become
15844 extended with a value of maxtiny + 1. */
15845 if (val == ((maxtiny + 1) << op->shift)
15846 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
15849 fragp->fr_subtype =
15850 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15854 else if (symsec != absolute_section && sec != NULL)
15855 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
15857 if ((val & ((1 << op->shift) - 1)) != 0
15858 || val < (mintiny << op->shift)
15859 || val > (maxtiny << op->shift))
15865 /* Compute the length of a branch sequence, and adjust the
15866 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15867 worst-case length is computed, with UPDATE being used to indicate
15868 whether an unconditional (-1), branch-likely (+1) or regular (0)
15869 branch is to be computed. */
15871 relaxed_branch_length (fragS *fragp, asection *sec, int update)
15873 bfd_boolean toofar;
15877 && S_IS_DEFINED (fragp->fr_symbol)
15878 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15883 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15885 addr = fragp->fr_address + fragp->fr_fix + 4;
15889 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
15892 /* If the symbol is not defined or it's in a different segment,
15893 assume the user knows what's going on and emit a short
15899 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
15901 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
15902 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
15903 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
15904 RELAX_BRANCH_LINK (fragp->fr_subtype),
15910 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
15913 if (mips_pic != NO_PIC)
15915 /* Additional space for PIC loading of target address. */
15917 if (mips_opts.isa == ISA_MIPS1)
15918 /* Additional space for $at-stabilizing nop. */
15922 /* If branch is conditional. */
15923 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
15930 /* Compute the length of a branch sequence, and adjust the
15931 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15932 worst-case length is computed, with UPDATE being used to indicate
15933 whether an unconditional (-1), or regular (0) branch is to be
15937 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
15939 bfd_boolean toofar;
15943 && S_IS_DEFINED (fragp->fr_symbol)
15944 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15949 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15950 /* Ignore the low bit in the target, since it will be set
15951 for a text label. */
15952 if ((val & 1) != 0)
15955 addr = fragp->fr_address + fragp->fr_fix + 4;
15959 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
15962 /* If the symbol is not defined or it's in a different segment,
15963 assume the user knows what's going on and emit a short
15969 if (fragp && update
15970 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
15971 fragp->fr_subtype = (toofar
15972 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
15973 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
15978 bfd_boolean compact_known = fragp != NULL;
15979 bfd_boolean compact = FALSE;
15980 bfd_boolean uncond;
15983 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
15985 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
15987 uncond = update < 0;
15989 /* If label is out of range, we turn branch <br>:
15991 <br> label # 4 bytes
15997 nop # 2 bytes if compact && !PIC
16000 if (mips_pic == NO_PIC && (!compact_known || compact))
16003 /* If assembling PIC code, we further turn:
16009 lw/ld at, %got(label)(gp) # 4 bytes
16010 d/addiu at, %lo(label) # 4 bytes
16013 if (mips_pic != NO_PIC)
16016 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16018 <brneg> 0f # 4 bytes
16019 nop # 2 bytes if !compact
16022 length += (compact_known && compact) ? 4 : 6;
16028 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16029 bit accordingly. */
16032 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16034 bfd_boolean toofar;
16037 && S_IS_DEFINED (fragp->fr_symbol)
16038 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16044 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16045 /* Ignore the low bit in the target, since it will be set
16046 for a text label. */
16047 if ((val & 1) != 0)
16050 /* Assume this is a 2-byte branch. */
16051 addr = fragp->fr_address + fragp->fr_fix + 2;
16053 /* We try to avoid the infinite loop by not adding 2 more bytes for
16058 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16060 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16061 else if (type == 'E')
16062 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16067 /* If the symbol is not defined or it's in a different segment,
16068 we emit a normal 32-bit branch. */
16071 if (fragp && update
16072 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16074 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16075 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16083 /* Estimate the size of a frag before relaxing. Unless this is the
16084 mips16, we are not really relaxing here, and the final size is
16085 encoded in the subtype information. For the mips16, we have to
16086 decide whether we are using an extended opcode or not. */
16089 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16093 if (RELAX_BRANCH_P (fragp->fr_subtype))
16096 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16098 return fragp->fr_var;
16101 if (RELAX_MIPS16_P (fragp->fr_subtype))
16102 /* We don't want to modify the EXTENDED bit here; it might get us
16103 into infinite loops. We change it only in mips_relax_frag(). */
16104 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16106 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16110 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16111 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16112 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16113 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16114 fragp->fr_var = length;
16119 if (mips_pic == NO_PIC)
16120 change = nopic_need_relax (fragp->fr_symbol, 0);
16121 else if (mips_pic == SVR4_PIC)
16122 change = pic_need_relax (fragp->fr_symbol, segtype);
16123 else if (mips_pic == VXWORKS_PIC)
16124 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16131 fragp->fr_subtype |= RELAX_USE_SECOND;
16132 return -RELAX_FIRST (fragp->fr_subtype);
16135 return -RELAX_SECOND (fragp->fr_subtype);
16138 /* This is called to see whether a reloc against a defined symbol
16139 should be converted into a reloc against a section. */
16142 mips_fix_adjustable (fixS *fixp)
16144 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16145 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16148 if (fixp->fx_addsy == NULL)
16151 /* If symbol SYM is in a mergeable section, relocations of the form
16152 SYM + 0 can usually be made section-relative. The mergeable data
16153 is then identified by the section offset rather than by the symbol.
16155 However, if we're generating REL LO16 relocations, the offset is split
16156 between the LO16 and parterning high part relocation. The linker will
16157 need to recalculate the complete offset in order to correctly identify
16160 The linker has traditionally not looked for the parterning high part
16161 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16162 placed anywhere. Rather than break backwards compatibility by changing
16163 this, it seems better not to force the issue, and instead keep the
16164 original symbol. This will work with either linker behavior. */
16165 if ((lo16_reloc_p (fixp->fx_r_type)
16166 || reloc_needs_lo_p (fixp->fx_r_type))
16167 && HAVE_IN_PLACE_ADDENDS
16168 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16171 /* There is no place to store an in-place offset for JALR relocations.
16172 Likewise an in-range offset of limited PC-relative relocations may
16173 overflow the in-place relocatable field if recalculated against the
16174 start address of the symbol's containing section. */
16175 if (HAVE_IN_PLACE_ADDENDS
16176 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16177 || jalr_reloc_p (fixp->fx_r_type)))
16180 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16181 to a floating-point stub. The same is true for non-R_MIPS16_26
16182 relocations against MIPS16 functions; in this case, the stub becomes
16183 the function's canonical address.
16185 Floating-point stubs are stored in unique .mips16.call.* or
16186 .mips16.fn.* sections. If a stub T for function F is in section S,
16187 the first relocation in section S must be against F; this is how the
16188 linker determines the target function. All relocations that might
16189 resolve to T must also be against F. We therefore have the following
16190 restrictions, which are given in an intentionally-redundant way:
16192 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16195 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16196 if that stub might be used.
16198 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16201 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16202 that stub might be used.
16204 There is a further restriction:
16206 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16207 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16208 targets with in-place addends; the relocation field cannot
16209 encode the low bit.
16211 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16212 against a MIPS16 symbol. We deal with (5) by by not reducing any
16213 such relocations on REL targets.
16215 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16216 relocation against some symbol R, no relocation against R may be
16217 reduced. (Note that this deals with (2) as well as (1) because
16218 relocations against global symbols will never be reduced on ELF
16219 targets.) This approach is a little simpler than trying to detect
16220 stub sections, and gives the "all or nothing" per-symbol consistency
16221 that we have for MIPS16 symbols. */
16222 if (fixp->fx_subsy == NULL
16223 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16224 || *symbol_get_tc (fixp->fx_addsy)
16225 || (HAVE_IN_PLACE_ADDENDS
16226 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16227 && jmp_reloc_p (fixp->fx_r_type))))
16233 /* Translate internal representation of relocation info to BFD target
16237 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16239 static arelent *retval[4];
16241 bfd_reloc_code_real_type code;
16243 memset (retval, 0, sizeof(retval));
16244 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16245 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16246 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16247 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16249 if (fixp->fx_pcrel)
16251 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16252 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16253 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16254 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16255 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16257 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16258 Relocations want only the symbol offset. */
16259 reloc->addend = fixp->fx_addnumber + reloc->address;
16262 reloc->addend = fixp->fx_addnumber;
16264 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16265 entry to be used in the relocation's section offset. */
16266 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16268 reloc->address = reloc->addend;
16272 code = fixp->fx_r_type;
16274 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16275 if (reloc->howto == NULL)
16277 as_bad_where (fixp->fx_file, fixp->fx_line,
16278 _("Can not represent %s relocation in this object file format"),
16279 bfd_get_reloc_code_name (code));
16286 /* Relax a machine dependent frag. This returns the amount by which
16287 the current size of the frag should change. */
16290 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16292 if (RELAX_BRANCH_P (fragp->fr_subtype))
16294 offsetT old_var = fragp->fr_var;
16296 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16298 return fragp->fr_var - old_var;
16301 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16303 offsetT old_var = fragp->fr_var;
16304 offsetT new_var = 4;
16306 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16307 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16308 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16309 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16310 fragp->fr_var = new_var;
16312 return new_var - old_var;
16315 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16318 if (mips16_extended_frag (fragp, NULL, stretch))
16320 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16322 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16327 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16329 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16336 /* Convert a machine dependent frag. */
16339 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16341 if (RELAX_BRANCH_P (fragp->fr_subtype))
16344 unsigned long insn;
16348 buf = fragp->fr_literal + fragp->fr_fix;
16349 insn = read_insn (buf);
16351 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16353 /* We generate a fixup instead of applying it right now
16354 because, if there are linker relaxations, we're going to
16355 need the relocations. */
16356 exp.X_op = O_symbol;
16357 exp.X_add_symbol = fragp->fr_symbol;
16358 exp.X_add_number = fragp->fr_offset;
16360 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16361 BFD_RELOC_16_PCREL_S2);
16362 fixp->fx_file = fragp->fr_file;
16363 fixp->fx_line = fragp->fr_line;
16365 buf = write_insn (buf, insn);
16371 as_warn_where (fragp->fr_file, fragp->fr_line,
16372 _("Relaxed out-of-range branch into a jump"));
16374 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16377 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16379 /* Reverse the branch. */
16380 switch ((insn >> 28) & 0xf)
16383 /* bc[0-3][tf]l? instructions can have the condition
16384 reversed by tweaking a single TF bit, and their
16385 opcodes all have 0x4???????. */
16386 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16387 insn ^= 0x00010000;
16391 /* bltz 0x04000000 bgez 0x04010000
16392 bltzal 0x04100000 bgezal 0x04110000 */
16393 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16394 insn ^= 0x00010000;
16398 /* beq 0x10000000 bne 0x14000000
16399 blez 0x18000000 bgtz 0x1c000000 */
16400 insn ^= 0x04000000;
16408 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16410 /* Clear the and-link bit. */
16411 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16413 /* bltzal 0x04100000 bgezal 0x04110000
16414 bltzall 0x04120000 bgezall 0x04130000 */
16415 insn &= ~0x00100000;
16418 /* Branch over the branch (if the branch was likely) or the
16419 full jump (not likely case). Compute the offset from the
16420 current instruction to branch to. */
16421 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16425 /* How many bytes in instructions we've already emitted? */
16426 i = buf - fragp->fr_literal - fragp->fr_fix;
16427 /* How many bytes in instructions from here to the end? */
16428 i = fragp->fr_var - i;
16430 /* Convert to instruction count. */
16432 /* Branch counts from the next instruction. */
16435 /* Branch over the jump. */
16436 buf = write_insn (buf, insn);
16439 buf = write_insn (buf, 0);
16441 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16443 /* beql $0, $0, 2f */
16445 /* Compute the PC offset from the current instruction to
16446 the end of the variable frag. */
16447 /* How many bytes in instructions we've already emitted? */
16448 i = buf - fragp->fr_literal - fragp->fr_fix;
16449 /* How many bytes in instructions from here to the end? */
16450 i = fragp->fr_var - i;
16451 /* Convert to instruction count. */
16453 /* Don't decrement i, because we want to branch over the
16457 buf = write_insn (buf, insn);
16458 buf = write_insn (buf, 0);
16462 if (mips_pic == NO_PIC)
16465 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16466 ? 0x0c000000 : 0x08000000);
16467 exp.X_op = O_symbol;
16468 exp.X_add_symbol = fragp->fr_symbol;
16469 exp.X_add_number = fragp->fr_offset;
16471 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16472 FALSE, BFD_RELOC_MIPS_JMP);
16473 fixp->fx_file = fragp->fr_file;
16474 fixp->fx_line = fragp->fr_line;
16476 buf = write_insn (buf, insn);
16480 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16482 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16483 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16484 insn |= at << OP_SH_RT;
16485 exp.X_op = O_symbol;
16486 exp.X_add_symbol = fragp->fr_symbol;
16487 exp.X_add_number = fragp->fr_offset;
16489 if (fragp->fr_offset)
16491 exp.X_add_symbol = make_expr_symbol (&exp);
16492 exp.X_add_number = 0;
16495 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16496 FALSE, BFD_RELOC_MIPS_GOT16);
16497 fixp->fx_file = fragp->fr_file;
16498 fixp->fx_line = fragp->fr_line;
16500 buf = write_insn (buf, insn);
16502 if (mips_opts.isa == ISA_MIPS1)
16504 buf = write_insn (buf, 0);
16506 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16507 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16508 insn |= at << OP_SH_RS | at << OP_SH_RT;
16510 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16511 FALSE, BFD_RELOC_LO16);
16512 fixp->fx_file = fragp->fr_file;
16513 fixp->fx_line = fragp->fr_line;
16515 buf = write_insn (buf, insn);
16518 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16522 insn |= at << OP_SH_RS;
16524 buf = write_insn (buf, insn);
16528 fragp->fr_fix += fragp->fr_var;
16529 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16533 /* Relax microMIPS branches. */
16534 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16536 char *buf = fragp->fr_literal + fragp->fr_fix;
16537 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16538 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16539 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16540 bfd_boolean short_ds;
16541 unsigned long insn;
16545 exp.X_op = O_symbol;
16546 exp.X_add_symbol = fragp->fr_symbol;
16547 exp.X_add_number = fragp->fr_offset;
16549 fragp->fr_fix += fragp->fr_var;
16551 /* Handle 16-bit branches that fit or are forced to fit. */
16552 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16554 /* We generate a fixup instead of applying it right now,
16555 because if there is linker relaxation, we're going to
16556 need the relocations. */
16558 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16559 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16560 else if (type == 'E')
16561 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16562 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16566 fixp->fx_file = fragp->fr_file;
16567 fixp->fx_line = fragp->fr_line;
16569 /* These relocations can have an addend that won't fit in
16571 fixp->fx_no_overflow = 1;
16576 /* Handle 32-bit branches that fit or are forced to fit. */
16577 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16578 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16580 /* We generate a fixup instead of applying it right now,
16581 because if there is linker relaxation, we're going to
16582 need the relocations. */
16583 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16584 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16585 fixp->fx_file = fragp->fr_file;
16586 fixp->fx_line = fragp->fr_line;
16592 /* Relax 16-bit branches to 32-bit branches. */
16595 insn = read_compressed_insn (buf, 2);
16597 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16598 insn = 0x94000000; /* beq */
16599 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16601 unsigned long regno;
16603 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16604 regno = micromips_to_32_reg_d_map [regno];
16605 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16606 insn |= regno << MICROMIPSOP_SH_RS;
16611 /* Nothing else to do, just write it out. */
16612 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16613 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16615 buf = write_compressed_insn (buf, insn, 4);
16616 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16621 insn = read_compressed_insn (buf, 4);
16623 /* Relax 32-bit branches to a sequence of instructions. */
16624 as_warn_where (fragp->fr_file, fragp->fr_line,
16625 _("Relaxed out-of-range branch into a jump"));
16627 /* Set the short-delay-slot bit. */
16628 short_ds = al && (insn & 0x02000000) != 0;
16630 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16634 /* Reverse the branch. */
16635 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16636 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16637 insn ^= 0x20000000;
16638 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16639 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16640 || (insn & 0xffe00000) == 0x40800000 /* blez */
16641 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16642 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16643 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16644 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16645 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16646 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16647 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16648 insn ^= 0x00400000;
16649 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16650 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16651 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16652 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16653 insn ^= 0x00200000;
16659 /* Clear the and-link and short-delay-slot bits. */
16660 gas_assert ((insn & 0xfda00000) == 0x40200000);
16662 /* bltzal 0x40200000 bgezal 0x40600000 */
16663 /* bltzals 0x42200000 bgezals 0x42600000 */
16664 insn &= ~0x02200000;
16667 /* Make a label at the end for use with the branch. */
16668 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16669 micromips_label_inc ();
16670 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16673 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16674 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16675 fixp->fx_file = fragp->fr_file;
16676 fixp->fx_line = fragp->fr_line;
16678 /* Branch over the jump. */
16679 buf = write_compressed_insn (buf, insn, 4);
16682 buf = write_compressed_insn (buf, 0x0c00, 2);
16685 if (mips_pic == NO_PIC)
16687 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16689 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16690 insn = al ? jal : 0xd4000000;
16692 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16693 BFD_RELOC_MICROMIPS_JMP);
16694 fixp->fx_file = fragp->fr_file;
16695 fixp->fx_line = fragp->fr_line;
16697 buf = write_compressed_insn (buf, insn, 4);
16700 buf = write_compressed_insn (buf, 0x0c00, 2);
16704 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16705 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16706 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16708 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16709 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16710 insn |= at << MICROMIPSOP_SH_RT;
16712 if (exp.X_add_number)
16714 exp.X_add_symbol = make_expr_symbol (&exp);
16715 exp.X_add_number = 0;
16718 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16719 BFD_RELOC_MICROMIPS_GOT16);
16720 fixp->fx_file = fragp->fr_file;
16721 fixp->fx_line = fragp->fr_line;
16723 buf = write_compressed_insn (buf, insn, 4);
16725 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16726 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16727 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16729 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16730 BFD_RELOC_MICROMIPS_LO16);
16731 fixp->fx_file = fragp->fr_file;
16732 fixp->fx_line = fragp->fr_line;
16734 buf = write_compressed_insn (buf, insn, 4);
16736 /* jr/jrc/jalr/jalrs $at */
16737 insn = al ? jalr : jr;
16738 insn |= at << MICROMIPSOP_SH_MJ;
16740 buf = write_compressed_insn (buf, insn, 2);
16743 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16747 if (RELAX_MIPS16_P (fragp->fr_subtype))
16750 const struct mips16_immed_operand *op;
16753 unsigned int user_length, length;
16754 unsigned long insn;
16757 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16758 op = mips16_immed_operands;
16759 while (op->type != type)
16762 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
16763 val = resolve_symbol_value (fragp->fr_symbol);
16768 addr = fragp->fr_address + fragp->fr_fix;
16770 /* The rules for the base address of a PC relative reloc are
16771 complicated; see mips16_extended_frag. */
16772 if (type == 'p' || type == 'q')
16777 /* Ignore the low bit in the target, since it will be
16778 set for a text label. */
16779 if ((val & 1) != 0)
16782 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16784 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16787 addr &= ~ (addressT) ((1 << op->shift) - 1);
16790 /* Make sure the section winds up with the alignment we have
16793 record_alignment (asec, op->shift);
16797 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
16798 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
16799 as_warn_where (fragp->fr_file, fragp->fr_line,
16800 _("extended instruction in delay slot"));
16802 buf = fragp->fr_literal + fragp->fr_fix;
16804 insn = read_compressed_insn (buf, 2);
16806 insn |= MIPS16_EXTEND;
16808 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16810 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16815 mips16_immed (fragp->fr_file, fragp->fr_line, type,
16816 BFD_RELOC_UNUSED, val, user_length, &insn);
16818 length = (ext ? 4 : 2);
16819 gas_assert (mips16_opcode_length (insn) == length);
16820 write_compressed_insn (buf, insn, length);
16821 fragp->fr_fix += length;
16825 relax_substateT subtype = fragp->fr_subtype;
16826 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
16827 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
16831 first = RELAX_FIRST (subtype);
16832 second = RELAX_SECOND (subtype);
16833 fixp = (fixS *) fragp->fr_opcode;
16835 /* If the delay slot chosen does not match the size of the instruction,
16836 then emit a warning. */
16837 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
16838 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
16843 s = subtype & (RELAX_DELAY_SLOT_16BIT
16844 | RELAX_DELAY_SLOT_SIZE_FIRST
16845 | RELAX_DELAY_SLOT_SIZE_SECOND);
16846 msg = macro_warning (s);
16848 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16852 /* Possibly emit a warning if we've chosen the longer option. */
16853 if (use_second == second_longer)
16859 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
16860 msg = macro_warning (s);
16862 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16866 /* Go through all the fixups for the first sequence. Disable them
16867 (by marking them as done) if we're going to use the second
16868 sequence instead. */
16870 && fixp->fx_frag == fragp
16871 && fixp->fx_where < fragp->fr_fix - second)
16873 if (subtype & RELAX_USE_SECOND)
16875 fixp = fixp->fx_next;
16878 /* Go through the fixups for the second sequence. Disable them if
16879 we're going to use the first sequence, otherwise adjust their
16880 addresses to account for the relaxation. */
16881 while (fixp && fixp->fx_frag == fragp)
16883 if (subtype & RELAX_USE_SECOND)
16884 fixp->fx_where -= first;
16887 fixp = fixp->fx_next;
16890 /* Now modify the frag contents. */
16891 if (subtype & RELAX_USE_SECOND)
16895 start = fragp->fr_literal + fragp->fr_fix - first - second;
16896 memmove (start, start + first, second);
16897 fragp->fr_fix -= first;
16900 fragp->fr_fix -= second;
16904 /* This function is called after the relocs have been generated.
16905 We've been storing mips16 text labels as odd. Here we convert them
16906 back to even for the convenience of the debugger. */
16909 mips_frob_file_after_relocs (void)
16912 unsigned int count, i;
16914 syms = bfd_get_outsymbols (stdoutput);
16915 count = bfd_get_symcount (stdoutput);
16916 for (i = 0; i < count; i++, syms++)
16917 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
16918 && ((*syms)->value & 1) != 0)
16920 (*syms)->value &= ~1;
16921 /* If the symbol has an odd size, it was probably computed
16922 incorrectly, so adjust that as well. */
16923 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
16924 ++elf_symbol (*syms)->internal_elf_sym.st_size;
16928 /* This function is called whenever a label is defined, including fake
16929 labels instantiated off the dot special symbol. It is used when
16930 handling branch delays; if a branch has a label, we assume we cannot
16931 move it. This also bumps the value of the symbol by 1 in compressed
16935 mips_record_label (symbolS *sym)
16937 segment_info_type *si = seg_info (now_seg);
16938 struct insn_label_list *l;
16940 if (free_insn_labels == NULL)
16941 l = (struct insn_label_list *) xmalloc (sizeof *l);
16944 l = free_insn_labels;
16945 free_insn_labels = l->next;
16949 l->next = si->label_list;
16950 si->label_list = l;
16953 /* This function is called as tc_frob_label() whenever a label is defined
16954 and adds a DWARF-2 record we only want for true labels. */
16957 mips_define_label (symbolS *sym)
16959 mips_record_label (sym);
16960 dwarf2_emit_label (sym);
16963 /* This function is called by tc_new_dot_label whenever a new dot symbol
16967 mips_add_dot_label (symbolS *sym)
16969 mips_record_label (sym);
16970 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
16971 mips_compressed_mark_label (sym);
16974 /* Some special processing for a MIPS ELF file. */
16977 mips_elf_final_processing (void)
16979 /* Write out the register information. */
16980 if (mips_abi != N64_ABI)
16984 s.ri_gprmask = mips_gprmask;
16985 s.ri_cprmask[0] = mips_cprmask[0];
16986 s.ri_cprmask[1] = mips_cprmask[1];
16987 s.ri_cprmask[2] = mips_cprmask[2];
16988 s.ri_cprmask[3] = mips_cprmask[3];
16989 /* The gp_value field is set by the MIPS ELF backend. */
16991 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
16992 ((Elf32_External_RegInfo *)
16993 mips_regmask_frag));
16997 Elf64_Internal_RegInfo s;
16999 s.ri_gprmask = mips_gprmask;
17001 s.ri_cprmask[0] = mips_cprmask[0];
17002 s.ri_cprmask[1] = mips_cprmask[1];
17003 s.ri_cprmask[2] = mips_cprmask[2];
17004 s.ri_cprmask[3] = mips_cprmask[3];
17005 /* The gp_value field is set by the MIPS ELF backend. */
17007 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17008 ((Elf64_External_RegInfo *)
17009 mips_regmask_frag));
17012 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17013 sort of BFD interface for this. */
17014 if (mips_any_noreorder)
17015 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17016 if (mips_pic != NO_PIC)
17018 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
17019 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17022 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17024 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17025 defined at present; this might need to change in future. */
17026 if (file_ase_mips16)
17027 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17028 if (file_ase_micromips)
17029 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17030 if (file_ase & ASE_MDMX)
17031 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17033 /* Set the MIPS ELF ABI flags. */
17034 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17035 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17036 else if (mips_abi == O64_ABI)
17037 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17038 else if (mips_abi == EABI_ABI)
17040 if (!file_mips_gp32)
17041 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17043 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17045 else if (mips_abi == N32_ABI)
17046 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17048 /* Nothing to do for N64_ABI. */
17050 if (mips_32bitmode)
17051 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17053 if (mips_flag_nan2008)
17054 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17056 #if 0 /* XXX FIXME */
17057 /* 32 bit code with 64 bit FP registers. */
17058 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17059 elf_elfheader (stdoutput)->e_flags |= ???;
17063 typedef struct proc {
17065 symbolS *func_end_sym;
17066 unsigned long reg_mask;
17067 unsigned long reg_offset;
17068 unsigned long fpreg_mask;
17069 unsigned long fpreg_offset;
17070 unsigned long frame_offset;
17071 unsigned long frame_reg;
17072 unsigned long pc_reg;
17075 static procS cur_proc;
17076 static procS *cur_proc_ptr;
17077 static int numprocs;
17079 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17080 as "2", and a normal nop as "0". */
17082 #define NOP_OPCODE_MIPS 0
17083 #define NOP_OPCODE_MIPS16 1
17084 #define NOP_OPCODE_MICROMIPS 2
17087 mips_nop_opcode (void)
17089 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17090 return NOP_OPCODE_MICROMIPS;
17091 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17092 return NOP_OPCODE_MIPS16;
17094 return NOP_OPCODE_MIPS;
17097 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17098 32-bit microMIPS NOPs here (if applicable). */
17101 mips_handle_align (fragS *fragp)
17105 int bytes, size, excess;
17108 if (fragp->fr_type != rs_align_code)
17111 p = fragp->fr_literal + fragp->fr_fix;
17113 switch (nop_opcode)
17115 case NOP_OPCODE_MICROMIPS:
17116 opcode = micromips_nop32_insn.insn_opcode;
17119 case NOP_OPCODE_MIPS16:
17120 opcode = mips16_nop_insn.insn_opcode;
17123 case NOP_OPCODE_MIPS:
17125 opcode = nop_insn.insn_opcode;
17130 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17131 excess = bytes % size;
17133 /* Handle the leading part if we're not inserting a whole number of
17134 instructions, and make it the end of the fixed part of the frag.
17135 Try to fit in a short microMIPS NOP if applicable and possible,
17136 and use zeroes otherwise. */
17137 gas_assert (excess < 4);
17138 fragp->fr_fix += excess;
17143 /* Fall through. */
17145 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17147 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17151 /* Fall through. */
17154 /* Fall through. */
17159 md_number_to_chars (p, opcode, size);
17160 fragp->fr_var = size;
17164 md_obj_begin (void)
17171 /* Check for premature end, nesting errors, etc. */
17173 as_warn (_("missing .end at end of assembly"));
17182 if (*input_line_pointer == '-')
17184 ++input_line_pointer;
17187 if (!ISDIGIT (*input_line_pointer))
17188 as_bad (_("expected simple number"));
17189 if (input_line_pointer[0] == '0')
17191 if (input_line_pointer[1] == 'x')
17193 input_line_pointer += 2;
17194 while (ISXDIGIT (*input_line_pointer))
17197 val |= hex_value (*input_line_pointer++);
17199 return negative ? -val : val;
17203 ++input_line_pointer;
17204 while (ISDIGIT (*input_line_pointer))
17207 val |= *input_line_pointer++ - '0';
17209 return negative ? -val : val;
17212 if (!ISDIGIT (*input_line_pointer))
17214 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17215 *input_line_pointer, *input_line_pointer);
17216 as_warn (_("invalid number"));
17219 while (ISDIGIT (*input_line_pointer))
17222 val += *input_line_pointer++ - '0';
17224 return negative ? -val : val;
17227 /* The .file directive; just like the usual .file directive, but there
17228 is an initial number which is the ECOFF file index. In the non-ECOFF
17229 case .file implies DWARF-2. */
17232 s_mips_file (int x ATTRIBUTE_UNUSED)
17234 static int first_file_directive = 0;
17236 if (ECOFF_DEBUGGING)
17245 filename = dwarf2_directive_file (0);
17247 /* Versions of GCC up to 3.1 start files with a ".file"
17248 directive even for stabs output. Make sure that this
17249 ".file" is handled. Note that you need a version of GCC
17250 after 3.1 in order to support DWARF-2 on MIPS. */
17251 if (filename != NULL && ! first_file_directive)
17253 (void) new_logical_line (filename, -1);
17254 s_app_file_string (filename, 0);
17256 first_file_directive = 1;
17260 /* The .loc directive, implying DWARF-2. */
17263 s_mips_loc (int x ATTRIBUTE_UNUSED)
17265 if (!ECOFF_DEBUGGING)
17266 dwarf2_directive_loc (0);
17269 /* The .end directive. */
17272 s_mips_end (int x ATTRIBUTE_UNUSED)
17276 /* Following functions need their own .frame and .cprestore directives. */
17277 mips_frame_reg_valid = 0;
17278 mips_cprestore_valid = 0;
17280 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17283 demand_empty_rest_of_line ();
17288 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17289 as_warn (_(".end not in text section"));
17293 as_warn (_(".end directive without a preceding .ent directive."));
17294 demand_empty_rest_of_line ();
17300 gas_assert (S_GET_NAME (p));
17301 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17302 as_warn (_(".end symbol does not match .ent symbol."));
17304 if (debug_type == DEBUG_STABS)
17305 stabs_generate_asm_endfunc (S_GET_NAME (p),
17309 as_warn (_(".end directive missing or unknown symbol"));
17311 /* Create an expression to calculate the size of the function. */
17312 if (p && cur_proc_ptr)
17314 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17315 expressionS *exp = xmalloc (sizeof (expressionS));
17318 exp->X_op = O_subtract;
17319 exp->X_add_symbol = symbol_temp_new_now ();
17320 exp->X_op_symbol = p;
17321 exp->X_add_number = 0;
17323 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17326 /* Generate a .pdr section. */
17327 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17329 segT saved_seg = now_seg;
17330 subsegT saved_subseg = now_subseg;
17334 #ifdef md_flush_pending_output
17335 md_flush_pending_output ();
17338 gas_assert (pdr_seg);
17339 subseg_set (pdr_seg, 0);
17341 /* Write the symbol. */
17342 exp.X_op = O_symbol;
17343 exp.X_add_symbol = p;
17344 exp.X_add_number = 0;
17345 emit_expr (&exp, 4);
17347 fragp = frag_more (7 * 4);
17349 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17350 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17351 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17352 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17353 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17354 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17355 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17357 subseg_set (saved_seg, saved_subseg);
17360 cur_proc_ptr = NULL;
17363 /* The .aent and .ent directives. */
17366 s_mips_ent (int aent)
17370 symbolP = get_symbol ();
17371 if (*input_line_pointer == ',')
17372 ++input_line_pointer;
17373 SKIP_WHITESPACE ();
17374 if (ISDIGIT (*input_line_pointer)
17375 || *input_line_pointer == '-')
17378 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17379 as_warn (_(".ent or .aent not in text section."));
17381 if (!aent && cur_proc_ptr)
17382 as_warn (_("missing .end"));
17386 /* This function needs its own .frame and .cprestore directives. */
17387 mips_frame_reg_valid = 0;
17388 mips_cprestore_valid = 0;
17390 cur_proc_ptr = &cur_proc;
17391 memset (cur_proc_ptr, '\0', sizeof (procS));
17393 cur_proc_ptr->func_sym = symbolP;
17397 if (debug_type == DEBUG_STABS)
17398 stabs_generate_asm_func (S_GET_NAME (symbolP),
17399 S_GET_NAME (symbolP));
17402 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17404 demand_empty_rest_of_line ();
17407 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17408 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17409 s_mips_frame is used so that we can set the PDR information correctly.
17410 We can't use the ecoff routines because they make reference to the ecoff
17411 symbol table (in the mdebug section). */
17414 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17416 if (ECOFF_DEBUGGING)
17422 if (cur_proc_ptr == (procS *) NULL)
17424 as_warn (_(".frame outside of .ent"));
17425 demand_empty_rest_of_line ();
17429 cur_proc_ptr->frame_reg = tc_get_register (1);
17431 SKIP_WHITESPACE ();
17432 if (*input_line_pointer++ != ','
17433 || get_absolute_expression_and_terminator (&val) != ',')
17435 as_warn (_("Bad .frame directive"));
17436 --input_line_pointer;
17437 demand_empty_rest_of_line ();
17441 cur_proc_ptr->frame_offset = val;
17442 cur_proc_ptr->pc_reg = tc_get_register (0);
17444 demand_empty_rest_of_line ();
17448 /* The .fmask and .mask directives. If the mdebug section is present
17449 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17450 embedded targets, s_mips_mask is used so that we can set the PDR
17451 information correctly. We can't use the ecoff routines because they
17452 make reference to the ecoff symbol table (in the mdebug section). */
17455 s_mips_mask (int reg_type)
17457 if (ECOFF_DEBUGGING)
17458 s_ignore (reg_type);
17463 if (cur_proc_ptr == (procS *) NULL)
17465 as_warn (_(".mask/.fmask outside of .ent"));
17466 demand_empty_rest_of_line ();
17470 if (get_absolute_expression_and_terminator (&mask) != ',')
17472 as_warn (_("Bad .mask/.fmask directive"));
17473 --input_line_pointer;
17474 demand_empty_rest_of_line ();
17478 off = get_absolute_expression ();
17480 if (reg_type == 'F')
17482 cur_proc_ptr->fpreg_mask = mask;
17483 cur_proc_ptr->fpreg_offset = off;
17487 cur_proc_ptr->reg_mask = mask;
17488 cur_proc_ptr->reg_offset = off;
17491 demand_empty_rest_of_line ();
17495 /* A table describing all the processors gas knows about. Names are
17496 matched in the order listed.
17498 To ease comparison, please keep this table in the same order as
17499 gcc's mips_cpu_info_table[]. */
17500 static const struct mips_cpu_info mips_cpu_info_table[] =
17502 /* Entries for generic ISAs */
17503 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17504 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17505 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17506 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17507 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17508 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17509 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17510 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17511 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17514 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17515 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17516 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17519 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17522 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17523 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17524 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17525 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17526 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17527 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17528 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17529 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17530 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17531 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17532 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17533 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17534 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17535 /* ST Microelectronics Loongson 2E and 2F cores */
17536 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17537 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17540 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17541 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17542 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17543 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17544 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17545 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17546 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17547 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17548 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17549 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17550 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17551 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17552 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17553 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17554 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17557 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17558 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17559 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17560 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17562 /* MIPS 32 Release 2 */
17563 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17564 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17565 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17566 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17567 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17568 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17569 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17570 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17571 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17572 ISA_MIPS32R2, CPU_MIPS32R2 },
17573 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17574 ISA_MIPS32R2, CPU_MIPS32R2 },
17575 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17576 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17577 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17578 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17579 /* Deprecated forms of the above. */
17580 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17581 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17582 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17583 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17584 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17585 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17586 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17587 /* Deprecated forms of the above. */
17588 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17589 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17590 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17591 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17592 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17593 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17594 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17595 /* Deprecated forms of the above. */
17596 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17597 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17598 /* 34Kn is a 34kc without DSP. */
17599 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17600 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17601 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17602 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17603 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17604 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17605 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17606 /* Deprecated forms of the above. */
17607 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17608 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17609 /* 1004K cores are multiprocessor versions of the 34K. */
17610 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17611 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17612 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17613 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17616 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17617 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17618 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17619 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17621 /* Broadcom SB-1 CPU core */
17622 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17623 /* Broadcom SB-1A CPU core */
17624 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17626 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17628 /* MIPS 64 Release 2 */
17630 /* Cavium Networks Octeon CPU core */
17631 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17632 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17633 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17636 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17639 XLP is mostly like XLR, with the prominent exception that it is
17640 MIPS64R2 rather than MIPS64. */
17641 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17644 { NULL, 0, 0, 0, 0 }
17648 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17649 with a final "000" replaced by "k". Ignore case.
17651 Note: this function is shared between GCC and GAS. */
17654 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17656 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17657 given++, canonical++;
17659 return ((*given == 0 && *canonical == 0)
17660 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17664 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17665 CPU name. We've traditionally allowed a lot of variation here.
17667 Note: this function is shared between GCC and GAS. */
17670 mips_matching_cpu_name_p (const char *canonical, const char *given)
17672 /* First see if the name matches exactly, or with a final "000"
17673 turned into "k". */
17674 if (mips_strict_matching_cpu_name_p (canonical, given))
17677 /* If not, try comparing based on numerical designation alone.
17678 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17679 if (TOLOWER (*given) == 'r')
17681 if (!ISDIGIT (*given))
17684 /* Skip over some well-known prefixes in the canonical name,
17685 hoping to find a number there too. */
17686 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17688 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17690 else if (TOLOWER (canonical[0]) == 'r')
17693 return mips_strict_matching_cpu_name_p (canonical, given);
17697 /* Parse an option that takes the name of a processor as its argument.
17698 OPTION is the name of the option and CPU_STRING is the argument.
17699 Return the corresponding processor enumeration if the CPU_STRING is
17700 recognized, otherwise report an error and return null.
17702 A similar function exists in GCC. */
17704 static const struct mips_cpu_info *
17705 mips_parse_cpu (const char *option, const char *cpu_string)
17707 const struct mips_cpu_info *p;
17709 /* 'from-abi' selects the most compatible architecture for the given
17710 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17711 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17712 version. Look first at the -mgp options, if given, otherwise base
17713 the choice on MIPS_DEFAULT_64BIT.
17715 Treat NO_ABI like the EABIs. One reason to do this is that the
17716 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17717 architecture. This code picks MIPS I for 'mips' and MIPS III for
17718 'mips64', just as we did in the days before 'from-abi'. */
17719 if (strcasecmp (cpu_string, "from-abi") == 0)
17721 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17722 return mips_cpu_info_from_isa (ISA_MIPS1);
17724 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17725 return mips_cpu_info_from_isa (ISA_MIPS3);
17727 if (file_mips_gp32 >= 0)
17728 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17730 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17735 /* 'default' has traditionally been a no-op. Probably not very useful. */
17736 if (strcasecmp (cpu_string, "default") == 0)
17739 for (p = mips_cpu_info_table; p->name != 0; p++)
17740 if (mips_matching_cpu_name_p (p->name, cpu_string))
17743 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
17747 /* Return the canonical processor information for ISA (a member of the
17748 ISA_MIPS* enumeration). */
17750 static const struct mips_cpu_info *
17751 mips_cpu_info_from_isa (int isa)
17755 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17756 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
17757 && isa == mips_cpu_info_table[i].isa)
17758 return (&mips_cpu_info_table[i]);
17763 static const struct mips_cpu_info *
17764 mips_cpu_info_from_arch (int arch)
17768 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17769 if (arch == mips_cpu_info_table[i].cpu)
17770 return (&mips_cpu_info_table[i]);
17776 show (FILE *stream, const char *string, int *col_p, int *first_p)
17780 fprintf (stream, "%24s", "");
17785 fprintf (stream, ", ");
17789 if (*col_p + strlen (string) > 72)
17791 fprintf (stream, "\n%24s", "");
17795 fprintf (stream, "%s", string);
17796 *col_p += strlen (string);
17802 md_show_usage (FILE *stream)
17807 fprintf (stream, _("\
17809 -EB generate big endian output\n\
17810 -EL generate little endian output\n\
17811 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17812 -G NUM allow referencing objects up to NUM bytes\n\
17813 implicitly with the gp register [default 8]\n"));
17814 fprintf (stream, _("\
17815 -mips1 generate MIPS ISA I instructions\n\
17816 -mips2 generate MIPS ISA II instructions\n\
17817 -mips3 generate MIPS ISA III instructions\n\
17818 -mips4 generate MIPS ISA IV instructions\n\
17819 -mips5 generate MIPS ISA V instructions\n\
17820 -mips32 generate MIPS32 ISA instructions\n\
17821 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17822 -mips64 generate MIPS64 ISA instructions\n\
17823 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17824 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17828 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17829 show (stream, mips_cpu_info_table[i].name, &column, &first);
17830 show (stream, "from-abi", &column, &first);
17831 fputc ('\n', stream);
17833 fprintf (stream, _("\
17834 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17835 -no-mCPU don't generate code specific to CPU.\n\
17836 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17840 show (stream, "3900", &column, &first);
17841 show (stream, "4010", &column, &first);
17842 show (stream, "4100", &column, &first);
17843 show (stream, "4650", &column, &first);
17844 fputc ('\n', stream);
17846 fprintf (stream, _("\
17847 -mips16 generate mips16 instructions\n\
17848 -no-mips16 do not generate mips16 instructions\n"));
17849 fprintf (stream, _("\
17850 -mmicromips generate microMIPS instructions\n\
17851 -mno-micromips do not generate microMIPS instructions\n"));
17852 fprintf (stream, _("\
17853 -msmartmips generate smartmips instructions\n\
17854 -mno-smartmips do not generate smartmips instructions\n"));
17855 fprintf (stream, _("\
17856 -mdsp generate DSP instructions\n\
17857 -mno-dsp do not generate DSP instructions\n"));
17858 fprintf (stream, _("\
17859 -mdspr2 generate DSP R2 instructions\n\
17860 -mno-dspr2 do not generate DSP R2 instructions\n"));
17861 fprintf (stream, _("\
17862 -mmt generate MT instructions\n\
17863 -mno-mt do not generate MT instructions\n"));
17864 fprintf (stream, _("\
17865 -mmcu generate MCU instructions\n\
17866 -mno-mcu do not generate MCU instructions\n"));
17867 fprintf (stream, _("\
17868 -mvirt generate Virtualization instructions\n\
17869 -mno-virt do not generate Virtualization instructions\n"));
17870 fprintf (stream, _("\
17871 -minsn32 only generate 32-bit microMIPS instructions\n\
17872 -mno-insn32 generate all microMIPS instructions\n"));
17873 fprintf (stream, _("\
17874 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17875 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17876 -mfix-vr4120 work around certain VR4120 errata\n\
17877 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17878 -mfix-24k insert a nop after ERET and DERET instructions\n\
17879 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17880 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17881 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17882 -msym32 assume all symbols have 32-bit values\n\
17883 -O0 remove unneeded NOPs, do not swap branches\n\
17884 -O remove unneeded NOPs and swap branches\n\
17885 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17886 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17887 fprintf (stream, _("\
17888 -mhard-float allow floating-point instructions\n\
17889 -msoft-float do not allow floating-point instructions\n\
17890 -msingle-float only allow 32-bit floating-point operations\n\
17891 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17892 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17893 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17894 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17898 show (stream, "legacy", &column, &first);
17899 show (stream, "2008", &column, &first);
17901 fputc ('\n', stream);
17903 fprintf (stream, _("\
17904 -KPIC, -call_shared generate SVR4 position independent code\n\
17905 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17906 -mvxworks-pic generate VxWorks position independent code\n\
17907 -non_shared do not generate code that can operate with DSOs\n\
17908 -xgot assume a 32 bit GOT\n\
17909 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17910 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17911 position dependent (non shared) code\n\
17912 -mabi=ABI create ABI conformant object file for:\n"));
17916 show (stream, "32", &column, &first);
17917 show (stream, "o64", &column, &first);
17918 show (stream, "n32", &column, &first);
17919 show (stream, "64", &column, &first);
17920 show (stream, "eabi", &column, &first);
17922 fputc ('\n', stream);
17924 fprintf (stream, _("\
17925 -32 create o32 ABI object file (default)\n\
17926 -n32 create n32 ABI object file\n\
17927 -64 create 64 ABI object file\n"));
17932 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
17934 if (HAVE_64BIT_SYMBOLS)
17935 return dwarf2_format_64bit_irix;
17937 return dwarf2_format_32bit;
17942 mips_dwarf2_addr_size (void)
17944 if (HAVE_64BIT_OBJECTS)
17950 /* Standard calling conventions leave the CFA at SP on entry. */
17952 mips_cfi_frame_initial_instructions (void)
17954 cfi_add_CFA_def_cfa_register (SP);
17958 tc_mips_regname_to_dw2regnum (char *regname)
17960 unsigned int regnum = -1;
17963 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))