1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro = FALSE;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1295 static void append_insn
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS *, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS *, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS *, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn *ip, char *str);
1306 static void mips16_macro (struct mips_cl_insn * ip);
1307 static void mips_ip (char *str, struct mips_cl_insn * ip);
1308 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314 static void my_getExpression (expressionS *, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean pic_need_relax (symbolS *, asection *);
1350 static int relaxed_branch_length (fragS *, asection *, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name; /* CPU or ISA name. */
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts = "O::g::G:";
1378 OPTION_MARCH = OPTION_MD_BASE,
1410 OPTION_NO_SMARTMIPS,
1418 OPTION_NO_MICROMIPS,
1421 OPTION_COMPAT_ARCH_BASE,
1430 OPTION_M7000_HILO_FIX,
1431 OPTION_MNO_7000_HILO_FIX,
1435 OPTION_NO_FIX_RM7000,
1436 OPTION_FIX_LOONGSON2F_JUMP,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP,
1438 OPTION_FIX_LOONGSON2F_NOP,
1439 OPTION_NO_FIX_LOONGSON2F_NOP,
1441 OPTION_NO_FIX_VR4120,
1443 OPTION_NO_FIX_VR4130,
1444 OPTION_FIX_CN63XXP1,
1445 OPTION_NO_FIX_CN63XXP1,
1452 OPTION_CONSTRUCT_FLOATS,
1453 OPTION_NO_CONSTRUCT_FLOATS,
1457 OPTION_RELAX_BRANCH,
1458 OPTION_NO_RELAX_BRANCH,
1467 OPTION_SINGLE_FLOAT,
1468 OPTION_DOUBLE_FLOAT,
1481 OPTION_MVXWORKS_PIC,
1484 OPTION_NO_ODD_SPREG,
1488 struct option md_longopts[] =
1490 /* Options which specify architecture. */
1491 {"march", required_argument, NULL, OPTION_MARCH},
1492 {"mtune", required_argument, NULL, OPTION_MTUNE},
1493 {"mips0", no_argument, NULL, OPTION_MIPS1},
1494 {"mips1", no_argument, NULL, OPTION_MIPS1},
1495 {"mips2", no_argument, NULL, OPTION_MIPS2},
1496 {"mips3", no_argument, NULL, OPTION_MIPS3},
1497 {"mips4", no_argument, NULL, OPTION_MIPS4},
1498 {"mips5", no_argument, NULL, OPTION_MIPS5},
1499 {"mips32", no_argument, NULL, OPTION_MIPS32},
1500 {"mips64", no_argument, NULL, OPTION_MIPS64},
1501 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1502 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1503 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1504 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1505 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1506 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1507 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1508 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument, NULL, OPTION_MIPS16},
1512 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1513 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1514 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1515 {"mdmx", no_argument, NULL, OPTION_MDMX},
1516 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1517 {"mdsp", no_argument, NULL, OPTION_DSP},
1518 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1519 {"mmt", no_argument, NULL, OPTION_MT},
1520 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1521 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1522 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1523 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1524 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1525 {"meva", no_argument, NULL, OPTION_EVA},
1526 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1527 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1528 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1529 {"mmcu", no_argument, NULL, OPTION_MCU},
1530 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1531 {"mvirt", no_argument, NULL, OPTION_VIRT},
1532 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1533 {"mmsa", no_argument, NULL, OPTION_MSA},
1534 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1535 {"mxpa", no_argument, NULL, OPTION_XPA},
1536 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument, NULL, OPTION_M4650},
1540 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1541 {"m4010", no_argument, NULL, OPTION_M4010},
1542 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1543 {"m4100", no_argument, NULL, OPTION_M4100},
1544 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1545 {"m3900", no_argument, NULL, OPTION_M3900},
1546 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1550 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1551 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1552 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1553 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1554 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1555 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1556 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1557 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1558 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1559 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1560 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1561 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1562 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1563 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1564 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1565 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1567 /* Miscellaneous options. */
1568 {"trap", no_argument, NULL, OPTION_TRAP},
1569 {"no-break", no_argument, NULL, OPTION_TRAP},
1570 {"break", no_argument, NULL, OPTION_BREAK},
1571 {"no-trap", no_argument, NULL, OPTION_BREAK},
1572 {"EB", no_argument, NULL, OPTION_EB},
1573 {"EL", no_argument, NULL, OPTION_EL},
1574 {"mfp32", no_argument, NULL, OPTION_FP32},
1575 {"mgp32", no_argument, NULL, OPTION_GP32},
1576 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1577 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1578 {"mfp64", no_argument, NULL, OPTION_FP64},
1579 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1580 {"mgp64", no_argument, NULL, OPTION_GP64},
1581 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1582 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1583 {"minsn32", no_argument, NULL, OPTION_INSN32},
1584 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1585 {"mshared", no_argument, NULL, OPTION_MSHARED},
1586 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1587 {"msym32", no_argument, NULL, OPTION_MSYM32},
1588 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1589 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1590 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1591 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1592 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1593 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1594 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument, NULL, OPTION_32},
1601 /* ELF-specific options. */
1602 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1603 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1604 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1605 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1606 {"xgot", no_argument, NULL, OPTION_XGOT},
1607 {"mabi", required_argument, NULL, OPTION_MABI},
1608 {"n32", no_argument, NULL, OPTION_N32},
1609 {"64", no_argument, NULL, OPTION_64},
1610 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1611 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1612 {"mpdr", no_argument, NULL, OPTION_PDR},
1613 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1614 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1615 {"mnan", required_argument, NULL, OPTION_NAN},
1617 {NULL, no_argument, NULL, 0}
1619 size_t md_longopts_size = sizeof (md_longopts);
1621 /* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1626 /* The name of the ASE, used in both the command-line and .set options. */
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64;
1638 /* The command-line options that turn the ASE on and off. */
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1646 int micromips32_rev;
1647 int micromips64_rev;
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1654 /* A table of all supported ASEs. */
1655 static const struct mips_ase mips_ases[] = {
1656 { "dsp", ASE_DSP, ASE_DSP64,
1657 OPTION_DSP, OPTION_NO_DSP,
1661 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1662 OPTION_DSPR2, OPTION_NO_DSPR2,
1666 { "eva", ASE_EVA, 0,
1667 OPTION_EVA, OPTION_NO_EVA,
1671 { "mcu", ASE_MCU, 0,
1672 OPTION_MCU, OPTION_NO_MCU,
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX, 0,
1678 OPTION_MDMX, OPTION_NO_MDMX,
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D, 0,
1684 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1689 OPTION_MT, OPTION_NO_MT,
1693 { "smartmips", ASE_SMARTMIPS, 0,
1694 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1698 { "virt", ASE_VIRT, ASE_VIRT64,
1699 OPTION_VIRT, OPTION_NO_VIRT,
1703 { "msa", ASE_MSA, ASE_MSA64,
1704 OPTION_MSA, OPTION_NO_MSA,
1708 { "xpa", ASE_XPA, 0,
1709 OPTION_XPA, OPTION_NO_XPA,
1714 /* The set of ASEs that require -mfp64. */
1715 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1717 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1718 static const unsigned int mips_ase_groups[] = {
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
1739 static const pseudo_typeS mips_pseudo_table[] =
1741 /* MIPS specific pseudo-ops. */
1742 {"option", s_option, 0},
1743 {"set", s_mipsset, 0},
1744 {"rdata", s_change_sec, 'r'},
1745 {"sdata", s_change_sec, 's'},
1746 {"livereg", s_ignore, 0},
1747 {"abicalls", s_abicalls, 0},
1748 {"cpload", s_cpload, 0},
1749 {"cpsetup", s_cpsetup, 0},
1750 {"cplocal", s_cplocal, 0},
1751 {"cprestore", s_cprestore, 0},
1752 {"cpreturn", s_cpreturn, 0},
1753 {"dtprelword", s_dtprelword, 0},
1754 {"dtpreldword", s_dtpreldword, 0},
1755 {"tprelword", s_tprelword, 0},
1756 {"tpreldword", s_tpreldword, 0},
1757 {"gpvalue", s_gpvalue, 0},
1758 {"gpword", s_gpword, 0},
1759 {"gpdword", s_gpdword, 0},
1760 {"ehword", s_ehword, 0},
1761 {"cpadd", s_cpadd, 0},
1762 {"insn", s_insn, 0},
1764 {"module", s_module, 0},
1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
1768 {"asciiz", stringer, 8 + 1},
1769 {"bss", s_change_sec, 'b'},
1771 {"half", s_cons, 1},
1772 {"dword", s_cons, 3},
1773 {"weakext", s_mips_weakext, 0},
1774 {"origin", s_org, 0},
1775 {"repeat", s_rept, 0},
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec, 'B'},
1780 /* These pseudo-ops are defined in read.c, but must be overridden
1781 here for one reason or another. */
1782 {"align", s_align, 0},
1783 {"byte", s_cons, 0},
1784 {"data", s_change_sec, 'd'},
1785 {"double", s_float_cons, 'd'},
1786 {"float", s_float_cons, 'f'},
1787 {"globl", s_mips_globl, 0},
1788 {"global", s_mips_globl, 0},
1789 {"hword", s_cons, 1},
1791 {"long", s_cons, 2},
1792 {"octa", s_cons, 4},
1793 {"quad", s_cons, 3},
1794 {"section", s_change_section, 0},
1795 {"short", s_cons, 1},
1796 {"single", s_float_cons, 'f'},
1797 {"stabd", s_mips_stab, 'd'},
1798 {"stabn", s_mips_stab, 'n'},
1799 {"stabs", s_mips_stab, 's'},
1800 {"text", s_change_sec, 't'},
1801 {"word", s_cons, 2},
1803 { "extern", ecoff_directive_extern, 0},
1808 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
1812 {"aent", s_mips_ent, 1},
1813 {"bgnb", s_ignore, 0},
1814 {"end", s_mips_end, 0},
1815 {"endb", s_ignore, 0},
1816 {"ent", s_mips_ent, 0},
1817 {"file", s_mips_file, 0},
1818 {"fmask", s_mips_mask, 'F'},
1819 {"frame", s_mips_frame, 0},
1820 {"loc", s_mips_loc, 0},
1821 {"mask", s_mips_mask, 'R'},
1822 {"verstamp", s_ignore, 0},
1826 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1830 mips_address_bytes (void)
1832 file_mips_check_options ();
1833 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1836 extern void pop_insert (const pseudo_typeS *);
1839 mips_pop_insert (void)
1841 pop_insert (mips_pseudo_table);
1842 if (! ECOFF_DEBUGGING)
1843 pop_insert (mips_nonecoff_pseudo_table);
1846 /* Symbols labelling the current insn. */
1848 struct insn_label_list
1850 struct insn_label_list *next;
1854 static struct insn_label_list *free_insn_labels;
1855 #define label_list tc_segment_info_data.labels
1857 static void mips_clear_insn_labels (void);
1858 static void mips_mark_labels (void);
1859 static void mips_compressed_mark_labels (void);
1862 mips_clear_insn_labels (void)
1864 struct insn_label_list **pl;
1865 segment_info_type *si;
1869 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1872 si = seg_info (now_seg);
1873 *pl = si->label_list;
1874 si->label_list = NULL;
1878 /* Mark instruction labels in MIPS16/microMIPS mode. */
1881 mips_mark_labels (void)
1883 if (HAVE_CODE_COMPRESSION)
1884 mips_compressed_mark_labels ();
1887 static char *expr_end;
1889 /* An expression in a macro instruction. This is set by mips_ip and
1890 mips16_ip and when populated is always an O_constant. */
1892 static expressionS imm_expr;
1894 /* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
1899 static expressionS offset_expr;
1900 static bfd_reloc_code_real_type offset_reloc[3]
1901 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1903 /* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
1907 static unsigned int forced_insn_length;
1909 /* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1912 static bfd_boolean mips_assembling_insn;
1914 /* The pdr segment for per procedure frame/regmask info. Not used for
1917 static segT pdr_seg;
1919 /* The default target format to use. */
1921 #if defined (TE_FreeBSD)
1922 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923 #elif defined (TE_TMIPS)
1924 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1926 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1930 mips_target_format (void)
1932 switch (OUTPUT_FLAVOR)
1934 case bfd_target_elf_flavour:
1936 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1941 return (target_big_endian
1942 ? (HAVE_64BIT_OBJECTS
1943 ? ELF_TARGET ("elf64-", "big")
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
1947 : (HAVE_64BIT_OBJECTS
1948 ? ELF_TARGET ("elf64-", "little")
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
1958 /* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1964 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1967 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1970 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1973 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts.micromips)
1980 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1986 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1989 mips_ase_mask (unsigned int flags)
1993 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1994 if (flags & mips_ase_groups[i])
1995 flags |= mips_ase_groups[i];
1999 /* Check whether the current ISA supports ASE. Issue a warning if
2003 mips_check_isa_supports_ase (const struct mips_ase *ase)
2007 static unsigned int warned_isa;
2008 static unsigned int warned_fp32;
2010 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2011 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2013 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2014 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2015 && (warned_isa & ase->flags) != ase->flags)
2017 warned_isa |= ase->flags;
2018 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2019 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2021 as_warn (_("the %d-bit %s architecture does not support the"
2022 " `%s' extension"), size, base, ase->name);
2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2025 ase->name, base, size, min_rev);
2027 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2028 && (warned_isa & ase->flags) != ase->flags)
2030 warned_isa |= ase->flags;
2031 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2032 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase->name, base, size, ase->rem_rev);
2037 if ((ase->flags & FP64_ASES)
2038 && mips_opts.fp != 64
2039 && (warned_fp32 & ase->flags) != ase->flags)
2041 warned_fp32 |= ase->flags;
2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2046 /* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2050 mips_check_isa_supports_ases (void)
2052 unsigned int i, mask;
2054 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2056 mask = mips_ase_mask (mips_ases[i].flags);
2057 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2058 mips_check_isa_supports_ase (&mips_ases[i]);
2062 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2066 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2067 bfd_boolean enabled_p)
2071 mask = mips_ase_mask (ase->flags);
2074 opts->ase |= ase->flags;
2078 /* Return the ASE called NAME, or null if none. */
2080 static const struct mips_ase *
2081 mips_lookup_ase (const char *name)
2085 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2086 if (strcmp (name, mips_ases[i].name) == 0)
2087 return &mips_ases[i];
2091 /* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2093 otherwise it is a 32-bit instruction. */
2095 static inline unsigned int
2096 micromips_insn_length (const struct mips_opcode *mo)
2098 return (mo->mask >> 16) == 0 ? 2 : 4;
2101 /* Return the length of MIPS16 instruction OPCODE. */
2103 static inline unsigned int
2104 mips16_opcode_length (unsigned long opcode)
2106 return (opcode >> 16) == 0 ? 2 : 4;
2109 /* Return the length of instruction INSN. */
2111 static inline unsigned int
2112 insn_length (const struct mips_cl_insn *insn)
2114 if (mips_opts.micromips)
2115 return micromips_insn_length (insn->insn_mo);
2116 else if (mips_opts.mips16)
2117 return mips16_opcode_length (insn->insn_opcode);
2122 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2125 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2130 insn->insn_opcode = mo->match;
2133 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2134 insn->fixp[i] = NULL;
2135 insn->fixed_p = (mips_opts.noreorder > 0);
2136 insn->noreorder_p = (mips_opts.noreorder > 0);
2137 insn->mips16_absolute_jump_p = 0;
2138 insn->complete_p = 0;
2139 insn->cleared_p = 0;
2142 /* Get a list of all the operands in INSN. */
2144 static const struct mips_operand_array *
2145 insn_operands (const struct mips_cl_insn *insn)
2147 if (insn->insn_mo >= &mips_opcodes[0]
2148 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2149 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2151 if (insn->insn_mo >= &mips16_opcodes[0]
2152 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2153 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2155 if (insn->insn_mo >= µmips_opcodes[0]
2156 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2157 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2162 /* Get a description of operand OPNO of INSN. */
2164 static const struct mips_operand *
2165 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2167 const struct mips_operand_array *operands;
2169 operands = insn_operands (insn);
2170 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2172 return operands->operand[opno];
2175 /* Install UVAL as the value of OPERAND in INSN. */
2178 insn_insert_operand (struct mips_cl_insn *insn,
2179 const struct mips_operand *operand, unsigned int uval)
2181 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2184 /* Extract the value of OPERAND from INSN. */
2186 static inline unsigned
2187 insn_extract_operand (const struct mips_cl_insn *insn,
2188 const struct mips_operand *operand)
2190 return mips_extract_operand (operand, insn->insn_opcode);
2193 /* Record the current MIPS16/microMIPS mode in now_seg. */
2196 mips_record_compressed_mode (void)
2198 segment_info_type *si;
2200 si = seg_info (now_seg);
2201 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2202 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2203 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2204 si->tc_segment_info_data.micromips = mips_opts.micromips;
2207 /* Read a standard MIPS instruction from BUF. */
2209 static unsigned long
2210 read_insn (char *buf)
2212 if (target_big_endian)
2213 return bfd_getb32 ((bfd_byte *) buf);
2215 return bfd_getl32 ((bfd_byte *) buf);
2218 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2222 write_insn (char *buf, unsigned int insn)
2224 md_number_to_chars (buf, insn, 4);
2228 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2229 has length LENGTH. */
2231 static unsigned long
2232 read_compressed_insn (char *buf, unsigned int length)
2238 for (i = 0; i < length; i += 2)
2241 if (target_big_endian)
2242 insn |= bfd_getb16 ((char *) buf);
2244 insn |= bfd_getl16 ((char *) buf);
2250 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2251 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2254 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2258 for (i = 0; i < length; i += 2)
2259 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2260 return buf + length;
2263 /* Install INSN at the location specified by its "frag" and "where" fields. */
2266 install_insn (const struct mips_cl_insn *insn)
2268 char *f = insn->frag->fr_literal + insn->where;
2269 if (HAVE_CODE_COMPRESSION)
2270 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2272 write_insn (f, insn->insn_opcode);
2273 mips_record_compressed_mode ();
2276 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2277 and install the opcode in the new location. */
2280 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2285 insn->where = where;
2286 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2287 if (insn->fixp[i] != NULL)
2289 insn->fixp[i]->fx_frag = frag;
2290 insn->fixp[i]->fx_where = where;
2292 install_insn (insn);
2295 /* Add INSN to the end of the output. */
2298 add_fixed_insn (struct mips_cl_insn *insn)
2300 char *f = frag_more (insn_length (insn));
2301 move_insn (insn, frag_now, f - frag_now->fr_literal);
2304 /* Start a variant frag and move INSN to the start of the variant part,
2305 marking it as fixed. The other arguments are as for frag_var. */
2308 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2309 relax_substateT subtype, symbolS *symbol, offsetT offset)
2311 frag_grow (max_chars);
2312 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2314 frag_var (rs_machine_dependent, max_chars, var,
2315 subtype, symbol, offset, NULL);
2318 /* Insert N copies of INSN into the history buffer, starting at
2319 position FIRST. Neither FIRST nor N need to be clipped. */
2322 insert_into_history (unsigned int first, unsigned int n,
2323 const struct mips_cl_insn *insn)
2325 if (mips_relax.sequence != 2)
2329 for (i = ARRAY_SIZE (history); i-- > first;)
2331 history[i] = history[i - n];
2337 /* Clear the error in insn_error. */
2340 clear_insn_error (void)
2342 memset (&insn_error, 0, sizeof (insn_error));
2345 /* Possibly record error message MSG for the current instruction.
2346 If the error is about a particular argument, ARGNUM is the 1-based
2347 number of that argument, otherwise it is 0. FORMAT is the format
2348 of MSG. Return true if MSG was used, false if the current message
2352 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2357 /* Give priority to errors against specific arguments, and to
2358 the first whole-instruction message. */
2364 /* Keep insn_error if it is against a later argument. */
2365 if (argnum < insn_error.min_argnum)
2368 /* If both errors are against the same argument but are different,
2369 give up on reporting a specific error for this argument.
2370 See the comment about mips_insn_error for details. */
2371 if (argnum == insn_error.min_argnum
2373 && strcmp (insn_error.msg, msg) != 0)
2376 insn_error.min_argnum += 1;
2380 insn_error.min_argnum = argnum;
2381 insn_error.format = format;
2382 insn_error.msg = msg;
2386 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2387 as for set_insn_error_format. */
2390 set_insn_error (int argnum, const char *msg)
2392 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2395 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error_i (int argnum, const char *msg, int i)
2401 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2405 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2406 are as for set_insn_error_format. */
2409 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2411 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2413 insn_error.u.ss[0] = s1;
2414 insn_error.u.ss[1] = s2;
2418 /* Report the error in insn_error, which is against assembly code STR. */
2421 report_insn_error (const char *str)
2425 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2426 switch (insn_error.format)
2433 as_bad (msg, insn_error.u.i, str);
2437 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2442 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2443 the idea is to make it obvious at a glance that each errata is
2447 init_vr4120_conflicts (void)
2449 #define CONFLICT(FIRST, SECOND) \
2450 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2452 /* Errata 21 - [D]DIV[U] after [D]MACC */
2453 CONFLICT (MACC, DIV);
2454 CONFLICT (DMACC, DIV);
2456 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2457 CONFLICT (DMULT, DMULT);
2458 CONFLICT (DMULT, DMACC);
2459 CONFLICT (DMACC, DMULT);
2460 CONFLICT (DMACC, DMACC);
2462 /* Errata 24 - MT{LO,HI} after [D]MACC */
2463 CONFLICT (MACC, MTHILO);
2464 CONFLICT (DMACC, MTHILO);
2466 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2467 instruction is executed immediately after a MACC or DMACC
2468 instruction, the result of [either instruction] is incorrect." */
2469 CONFLICT (MACC, MULT);
2470 CONFLICT (MACC, DMULT);
2471 CONFLICT (DMACC, MULT);
2472 CONFLICT (DMACC, DMULT);
2474 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2475 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2476 DDIV or DDIVU instruction, the result of the MACC or
2477 DMACC instruction is incorrect.". */
2478 CONFLICT (DMULT, MACC);
2479 CONFLICT (DMULT, DMACC);
2480 CONFLICT (DIV, MACC);
2481 CONFLICT (DIV, DMACC);
2491 #define RNUM_MASK 0x00000ff
2492 #define RTYPE_MASK 0x0ffff00
2493 #define RTYPE_NUM 0x0000100
2494 #define RTYPE_FPU 0x0000200
2495 #define RTYPE_FCC 0x0000400
2496 #define RTYPE_VEC 0x0000800
2497 #define RTYPE_GP 0x0001000
2498 #define RTYPE_CP0 0x0002000
2499 #define RTYPE_PC 0x0004000
2500 #define RTYPE_ACC 0x0008000
2501 #define RTYPE_CCC 0x0010000
2502 #define RTYPE_VI 0x0020000
2503 #define RTYPE_VF 0x0040000
2504 #define RTYPE_R5900_I 0x0080000
2505 #define RTYPE_R5900_Q 0x0100000
2506 #define RTYPE_R5900_R 0x0200000
2507 #define RTYPE_R5900_ACC 0x0400000
2508 #define RTYPE_MSA 0x0800000
2509 #define RWARN 0x8000000
2511 #define GENERIC_REGISTER_NUMBERS \
2512 {"$0", RTYPE_NUM | 0}, \
2513 {"$1", RTYPE_NUM | 1}, \
2514 {"$2", RTYPE_NUM | 2}, \
2515 {"$3", RTYPE_NUM | 3}, \
2516 {"$4", RTYPE_NUM | 4}, \
2517 {"$5", RTYPE_NUM | 5}, \
2518 {"$6", RTYPE_NUM | 6}, \
2519 {"$7", RTYPE_NUM | 7}, \
2520 {"$8", RTYPE_NUM | 8}, \
2521 {"$9", RTYPE_NUM | 9}, \
2522 {"$10", RTYPE_NUM | 10}, \
2523 {"$11", RTYPE_NUM | 11}, \
2524 {"$12", RTYPE_NUM | 12}, \
2525 {"$13", RTYPE_NUM | 13}, \
2526 {"$14", RTYPE_NUM | 14}, \
2527 {"$15", RTYPE_NUM | 15}, \
2528 {"$16", RTYPE_NUM | 16}, \
2529 {"$17", RTYPE_NUM | 17}, \
2530 {"$18", RTYPE_NUM | 18}, \
2531 {"$19", RTYPE_NUM | 19}, \
2532 {"$20", RTYPE_NUM | 20}, \
2533 {"$21", RTYPE_NUM | 21}, \
2534 {"$22", RTYPE_NUM | 22}, \
2535 {"$23", RTYPE_NUM | 23}, \
2536 {"$24", RTYPE_NUM | 24}, \
2537 {"$25", RTYPE_NUM | 25}, \
2538 {"$26", RTYPE_NUM | 26}, \
2539 {"$27", RTYPE_NUM | 27}, \
2540 {"$28", RTYPE_NUM | 28}, \
2541 {"$29", RTYPE_NUM | 29}, \
2542 {"$30", RTYPE_NUM | 30}, \
2543 {"$31", RTYPE_NUM | 31}
2545 #define FPU_REGISTER_NAMES \
2546 {"$f0", RTYPE_FPU | 0}, \
2547 {"$f1", RTYPE_FPU | 1}, \
2548 {"$f2", RTYPE_FPU | 2}, \
2549 {"$f3", RTYPE_FPU | 3}, \
2550 {"$f4", RTYPE_FPU | 4}, \
2551 {"$f5", RTYPE_FPU | 5}, \
2552 {"$f6", RTYPE_FPU | 6}, \
2553 {"$f7", RTYPE_FPU | 7}, \
2554 {"$f8", RTYPE_FPU | 8}, \
2555 {"$f9", RTYPE_FPU | 9}, \
2556 {"$f10", RTYPE_FPU | 10}, \
2557 {"$f11", RTYPE_FPU | 11}, \
2558 {"$f12", RTYPE_FPU | 12}, \
2559 {"$f13", RTYPE_FPU | 13}, \
2560 {"$f14", RTYPE_FPU | 14}, \
2561 {"$f15", RTYPE_FPU | 15}, \
2562 {"$f16", RTYPE_FPU | 16}, \
2563 {"$f17", RTYPE_FPU | 17}, \
2564 {"$f18", RTYPE_FPU | 18}, \
2565 {"$f19", RTYPE_FPU | 19}, \
2566 {"$f20", RTYPE_FPU | 20}, \
2567 {"$f21", RTYPE_FPU | 21}, \
2568 {"$f22", RTYPE_FPU | 22}, \
2569 {"$f23", RTYPE_FPU | 23}, \
2570 {"$f24", RTYPE_FPU | 24}, \
2571 {"$f25", RTYPE_FPU | 25}, \
2572 {"$f26", RTYPE_FPU | 26}, \
2573 {"$f27", RTYPE_FPU | 27}, \
2574 {"$f28", RTYPE_FPU | 28}, \
2575 {"$f29", RTYPE_FPU | 29}, \
2576 {"$f30", RTYPE_FPU | 30}, \
2577 {"$f31", RTYPE_FPU | 31}
2579 #define FPU_CONDITION_CODE_NAMES \
2580 {"$fcc0", RTYPE_FCC | 0}, \
2581 {"$fcc1", RTYPE_FCC | 1}, \
2582 {"$fcc2", RTYPE_FCC | 2}, \
2583 {"$fcc3", RTYPE_FCC | 3}, \
2584 {"$fcc4", RTYPE_FCC | 4}, \
2585 {"$fcc5", RTYPE_FCC | 5}, \
2586 {"$fcc6", RTYPE_FCC | 6}, \
2587 {"$fcc7", RTYPE_FCC | 7}
2589 #define COPROC_CONDITION_CODE_NAMES \
2590 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2591 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2592 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2593 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2594 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2595 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2596 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2597 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2599 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2600 {"$a4", RTYPE_GP | 8}, \
2601 {"$a5", RTYPE_GP | 9}, \
2602 {"$a6", RTYPE_GP | 10}, \
2603 {"$a7", RTYPE_GP | 11}, \
2604 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2605 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2606 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2607 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2608 {"$t0", RTYPE_GP | 12}, \
2609 {"$t1", RTYPE_GP | 13}, \
2610 {"$t2", RTYPE_GP | 14}, \
2611 {"$t3", RTYPE_GP | 15}
2613 #define O32_SYMBOLIC_REGISTER_NAMES \
2614 {"$t0", RTYPE_GP | 8}, \
2615 {"$t1", RTYPE_GP | 9}, \
2616 {"$t2", RTYPE_GP | 10}, \
2617 {"$t3", RTYPE_GP | 11}, \
2618 {"$t4", RTYPE_GP | 12}, \
2619 {"$t5", RTYPE_GP | 13}, \
2620 {"$t6", RTYPE_GP | 14}, \
2621 {"$t7", RTYPE_GP | 15}, \
2622 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2623 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2624 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2625 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2627 /* Remaining symbolic register names */
2628 #define SYMBOLIC_REGISTER_NAMES \
2629 {"$zero", RTYPE_GP | 0}, \
2630 {"$at", RTYPE_GP | 1}, \
2631 {"$AT", RTYPE_GP | 1}, \
2632 {"$v0", RTYPE_GP | 2}, \
2633 {"$v1", RTYPE_GP | 3}, \
2634 {"$a0", RTYPE_GP | 4}, \
2635 {"$a1", RTYPE_GP | 5}, \
2636 {"$a2", RTYPE_GP | 6}, \
2637 {"$a3", RTYPE_GP | 7}, \
2638 {"$s0", RTYPE_GP | 16}, \
2639 {"$s1", RTYPE_GP | 17}, \
2640 {"$s2", RTYPE_GP | 18}, \
2641 {"$s3", RTYPE_GP | 19}, \
2642 {"$s4", RTYPE_GP | 20}, \
2643 {"$s5", RTYPE_GP | 21}, \
2644 {"$s6", RTYPE_GP | 22}, \
2645 {"$s7", RTYPE_GP | 23}, \
2646 {"$t8", RTYPE_GP | 24}, \
2647 {"$t9", RTYPE_GP | 25}, \
2648 {"$k0", RTYPE_GP | 26}, \
2649 {"$kt0", RTYPE_GP | 26}, \
2650 {"$k1", RTYPE_GP | 27}, \
2651 {"$kt1", RTYPE_GP | 27}, \
2652 {"$gp", RTYPE_GP | 28}, \
2653 {"$sp", RTYPE_GP | 29}, \
2654 {"$s8", RTYPE_GP | 30}, \
2655 {"$fp", RTYPE_GP | 30}, \
2656 {"$ra", RTYPE_GP | 31}
2658 #define MIPS16_SPECIAL_REGISTER_NAMES \
2659 {"$pc", RTYPE_PC | 0}
2661 #define MDMX_VECTOR_REGISTER_NAMES \
2662 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2663 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2664 {"$v2", RTYPE_VEC | 2}, \
2665 {"$v3", RTYPE_VEC | 3}, \
2666 {"$v4", RTYPE_VEC | 4}, \
2667 {"$v5", RTYPE_VEC | 5}, \
2668 {"$v6", RTYPE_VEC | 6}, \
2669 {"$v7", RTYPE_VEC | 7}, \
2670 {"$v8", RTYPE_VEC | 8}, \
2671 {"$v9", RTYPE_VEC | 9}, \
2672 {"$v10", RTYPE_VEC | 10}, \
2673 {"$v11", RTYPE_VEC | 11}, \
2674 {"$v12", RTYPE_VEC | 12}, \
2675 {"$v13", RTYPE_VEC | 13}, \
2676 {"$v14", RTYPE_VEC | 14}, \
2677 {"$v15", RTYPE_VEC | 15}, \
2678 {"$v16", RTYPE_VEC | 16}, \
2679 {"$v17", RTYPE_VEC | 17}, \
2680 {"$v18", RTYPE_VEC | 18}, \
2681 {"$v19", RTYPE_VEC | 19}, \
2682 {"$v20", RTYPE_VEC | 20}, \
2683 {"$v21", RTYPE_VEC | 21}, \
2684 {"$v22", RTYPE_VEC | 22}, \
2685 {"$v23", RTYPE_VEC | 23}, \
2686 {"$v24", RTYPE_VEC | 24}, \
2687 {"$v25", RTYPE_VEC | 25}, \
2688 {"$v26", RTYPE_VEC | 26}, \
2689 {"$v27", RTYPE_VEC | 27}, \
2690 {"$v28", RTYPE_VEC | 28}, \
2691 {"$v29", RTYPE_VEC | 29}, \
2692 {"$v30", RTYPE_VEC | 30}, \
2693 {"$v31", RTYPE_VEC | 31}
2695 #define R5900_I_NAMES \
2696 {"$I", RTYPE_R5900_I | 0}
2698 #define R5900_Q_NAMES \
2699 {"$Q", RTYPE_R5900_Q | 0}
2701 #define R5900_R_NAMES \
2702 {"$R", RTYPE_R5900_R | 0}
2704 #define R5900_ACC_NAMES \
2705 {"$ACC", RTYPE_R5900_ACC | 0 }
2707 #define MIPS_DSP_ACCUMULATOR_NAMES \
2708 {"$ac0", RTYPE_ACC | 0}, \
2709 {"$ac1", RTYPE_ACC | 1}, \
2710 {"$ac2", RTYPE_ACC | 2}, \
2711 {"$ac3", RTYPE_ACC | 3}
2713 static const struct regname reg_names[] = {
2714 GENERIC_REGISTER_NUMBERS,
2716 FPU_CONDITION_CODE_NAMES,
2717 COPROC_CONDITION_CODE_NAMES,
2719 /* The $txx registers depends on the abi,
2720 these will be added later into the symbol table from
2721 one of the tables below once mips_abi is set after
2722 parsing of arguments from the command line. */
2723 SYMBOLIC_REGISTER_NAMES,
2725 MIPS16_SPECIAL_REGISTER_NAMES,
2726 MDMX_VECTOR_REGISTER_NAMES,
2731 MIPS_DSP_ACCUMULATOR_NAMES,
2735 static const struct regname reg_names_o32[] = {
2736 O32_SYMBOLIC_REGISTER_NAMES,
2740 static const struct regname reg_names_n32n64[] = {
2741 N32N64_SYMBOLIC_REGISTER_NAMES,
2745 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2746 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2747 of these register symbols, return the associated vector register,
2748 otherwise return SYMVAL itself. */
2751 mips_prefer_vec_regno (unsigned int symval)
2753 if ((symval & -2) == (RTYPE_GP | 2))
2754 return RTYPE_VEC | (symval & 1);
2758 /* Return true if string [S, E) is a valid register name, storing its
2759 symbol value in *SYMVAL_PTR if so. */
2762 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2767 /* Terminate name. */
2771 /* Look up the name. */
2772 symbol = symbol_find (s);
2775 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2778 *symval_ptr = S_GET_VALUE (symbol);
2782 /* Return true if the string at *SPTR is a valid register name. Allow it
2783 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2786 When returning true, move *SPTR past the register, store the
2787 register's symbol value in *SYMVAL_PTR and the channel mask in
2788 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2789 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2790 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2793 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2794 unsigned int *channels_ptr)
2798 unsigned int channels, symval, bit;
2800 /* Find end of name. */
2802 if (is_name_beginner (*e))
2804 while (is_part_of_name (*e))
2808 if (!mips_parse_register_1 (s, e, &symval))
2813 /* Eat characters from the end of the string that are valid
2814 channel suffixes. The preceding register must be $ACC or
2815 end with a digit, so there is no ambiguity. */
2818 for (q = "wzyx"; *q; q++, bit <<= 1)
2819 if (m > s && m[-1] == *q)
2826 || !mips_parse_register_1 (s, m, &symval)
2827 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2832 *symval_ptr = symval;
2834 *channels_ptr = channels;
2838 /* Check if SPTR points at a valid register specifier according to TYPES.
2839 If so, then return 1, advance S to consume the specifier and store
2840 the register's number in REGNOP, otherwise return 0. */
2843 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2847 if (mips_parse_register (s, ®no, NULL))
2849 if (types & RTYPE_VEC)
2850 regno = mips_prefer_vec_regno (regno);
2859 as_warn (_("unrecognized register name `%s'"), *s);
2864 return regno <= RNUM_MASK;
2867 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2868 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2871 mips_parse_vu0_channels (char *s, unsigned int *channels)
2876 for (i = 0; i < 4; i++)
2877 if (*s == "xyzw"[i])
2879 *channels |= 1 << (3 - i);
2885 /* Token types for parsed operand lists. */
2886 enum mips_operand_token_type {
2887 /* A plain register, e.g. $f2. */
2890 /* A 4-bit XYZW channel mask. */
2893 /* A constant vector index, e.g. [1]. */
2896 /* A register vector index, e.g. [$2]. */
2899 /* A continuous range of registers, e.g. $s0-$s4. */
2902 /* A (possibly relocated) expression. */
2905 /* A floating-point value. */
2908 /* A single character. This can be '(', ')' or ',', but '(' only appears
2912 /* A doubled character, either "--" or "++". */
2915 /* The end of the operand list. */
2919 /* A parsed operand token. */
2920 struct mips_operand_token
2922 /* The type of token. */
2923 enum mips_operand_token_type type;
2926 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2929 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2930 unsigned int channels;
2932 /* The integer value of an OT_INTEGER_INDEX. */
2935 /* The two register symbol values involved in an OT_REG_RANGE. */
2937 unsigned int regno1;
2938 unsigned int regno2;
2941 /* The value of an OT_INTEGER. The value is represented as an
2942 expression and the relocation operators that were applied to
2943 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2944 relocation operators were used. */
2947 bfd_reloc_code_real_type relocs[3];
2950 /* The binary data for an OT_FLOAT constant, and the number of bytes
2953 unsigned char data[8];
2957 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2962 /* An obstack used to construct lists of mips_operand_tokens. */
2963 static struct obstack mips_operand_tokens;
2965 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2968 mips_add_token (struct mips_operand_token *token,
2969 enum mips_operand_token_type type)
2972 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2975 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2976 and OT_REG tokens for them if so, and return a pointer to the first
2977 unconsumed character. Return null otherwise. */
2980 mips_parse_base_start (char *s)
2982 struct mips_operand_token token;
2983 unsigned int regno, channels;
2984 bfd_boolean decrement_p;
2990 SKIP_SPACE_TABS (s);
2992 /* Only match "--" as part of a base expression. In other contexts "--X"
2993 is a double negative. */
2994 decrement_p = (s[0] == '-' && s[1] == '-');
2998 SKIP_SPACE_TABS (s);
3001 /* Allow a channel specifier because that leads to better error messages
3002 than treating something like "$vf0x++" as an expression. */
3003 if (!mips_parse_register (&s, ®no, &channels))
3007 mips_add_token (&token, OT_CHAR);
3012 mips_add_token (&token, OT_DOUBLE_CHAR);
3015 token.u.regno = regno;
3016 mips_add_token (&token, OT_REG);
3020 token.u.channels = channels;
3021 mips_add_token (&token, OT_CHANNELS);
3024 /* For consistency, only match "++" as part of base expressions too. */
3025 SKIP_SPACE_TABS (s);
3026 if (s[0] == '+' && s[1] == '+')
3030 mips_add_token (&token, OT_DOUBLE_CHAR);
3036 /* Parse one or more tokens from S. Return a pointer to the first
3037 unconsumed character on success. Return null if an error was found
3038 and store the error text in insn_error. FLOAT_FORMAT is as for
3039 mips_parse_arguments. */
3042 mips_parse_argument_token (char *s, char float_format)
3044 char *end, *save_in, *err;
3045 unsigned int regno1, regno2, channels;
3046 struct mips_operand_token token;
3048 /* First look for "($reg", since we want to treat that as an
3049 OT_CHAR and OT_REG rather than an expression. */
3050 end = mips_parse_base_start (s);
3054 /* Handle other characters that end up as OT_CHARs. */
3055 if (*s == ')' || *s == ',')
3058 mips_add_token (&token, OT_CHAR);
3063 /* Handle tokens that start with a register. */
3064 if (mips_parse_register (&s, ®no1, &channels))
3068 /* A register and a VU0 channel suffix. */
3069 token.u.regno = regno1;
3070 mips_add_token (&token, OT_REG);
3072 token.u.channels = channels;
3073 mips_add_token (&token, OT_CHANNELS);
3077 SKIP_SPACE_TABS (s);
3080 /* A register range. */
3082 SKIP_SPACE_TABS (s);
3083 if (!mips_parse_register (&s, ®no2, NULL))
3085 set_insn_error (0, _("invalid register range"));
3089 token.u.reg_range.regno1 = regno1;
3090 token.u.reg_range.regno2 = regno2;
3091 mips_add_token (&token, OT_REG_RANGE);
3095 /* Add the register itself. */
3096 token.u.regno = regno1;
3097 mips_add_token (&token, OT_REG);
3099 /* Check for a vector index. */
3103 SKIP_SPACE_TABS (s);
3104 if (mips_parse_register (&s, &token.u.regno, NULL))
3105 mips_add_token (&token, OT_REG_INDEX);
3108 expressionS element;
3110 my_getExpression (&element, s);
3111 if (element.X_op != O_constant)
3113 set_insn_error (0, _("vector element must be constant"));
3117 token.u.index = element.X_add_number;
3118 mips_add_token (&token, OT_INTEGER_INDEX);
3120 SKIP_SPACE_TABS (s);
3123 set_insn_error (0, _("missing `]'"));
3133 /* First try to treat expressions as floats. */
3134 save_in = input_line_pointer;
3135 input_line_pointer = s;
3136 err = md_atof (float_format, (char *) token.u.flt.data,
3137 &token.u.flt.length);
3138 end = input_line_pointer;
3139 input_line_pointer = save_in;
3142 set_insn_error (0, err);
3147 mips_add_token (&token, OT_FLOAT);
3152 /* Treat everything else as an integer expression. */
3153 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3154 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3155 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3156 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3158 mips_add_token (&token, OT_INTEGER);
3162 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3163 if expressions should be treated as 32-bit floating-point constants,
3164 'd' if they should be treated as 64-bit floating-point constants,
3165 or 0 if they should be treated as integer expressions (the usual case).
3167 Return a list of tokens on success, otherwise return 0. The caller
3168 must obstack_free the list after use. */
3170 static struct mips_operand_token *
3171 mips_parse_arguments (char *s, char float_format)
3173 struct mips_operand_token token;
3175 SKIP_SPACE_TABS (s);
3178 s = mips_parse_argument_token (s, float_format);
3181 obstack_free (&mips_operand_tokens,
3182 obstack_finish (&mips_operand_tokens));
3185 SKIP_SPACE_TABS (s);
3187 mips_add_token (&token, OT_END);
3188 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3191 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3192 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3195 is_opcode_valid (const struct mips_opcode *mo)
3197 int isa = mips_opts.isa;
3198 int ase = mips_opts.ase;
3202 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3203 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3204 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3205 ase |= mips_ases[i].flags64;
3207 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3210 /* Check whether the instruction or macro requires single-precision or
3211 double-precision floating-point support. Note that this information is
3212 stored differently in the opcode table for insns and macros. */
3213 if (mo->pinfo == INSN_MACRO)
3215 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3216 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3220 fp_s = mo->pinfo & FP_S;
3221 fp_d = mo->pinfo & FP_D;
3224 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3227 if (fp_s && mips_opts.soft_float)
3233 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3234 selected ISA and architecture. */
3237 is_opcode_valid_16 (const struct mips_opcode *mo)
3239 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3242 /* Return TRUE if the size of the microMIPS opcode MO matches one
3243 explicitly requested. Always TRUE in the standard MIPS mode. */
3246 is_size_valid (const struct mips_opcode *mo)
3248 if (!mips_opts.micromips)
3251 if (mips_opts.insn32)
3253 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3255 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3258 if (!forced_insn_length)
3260 if (mo->pinfo == INSN_MACRO)
3262 return forced_insn_length == micromips_insn_length (mo);
3265 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3266 of the preceding instruction. Always TRUE in the standard MIPS mode.
3268 We don't accept macros in 16-bit delay slots to avoid a case where
3269 a macro expansion fails because it relies on a preceding 32-bit real
3270 instruction to have matched and does not handle the operands correctly.
3271 The only macros that may expand to 16-bit instructions are JAL that
3272 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3273 and BGT (that likewise cannot be placed in a delay slot) that decay to
3274 a NOP. In all these cases the macros precede any corresponding real
3275 instruction definitions in the opcode table, so they will match in the
3276 second pass where the size of the delay slot is ignored and therefore
3277 produce correct code. */
3280 is_delay_slot_valid (const struct mips_opcode *mo)
3282 if (!mips_opts.micromips)
3285 if (mo->pinfo == INSN_MACRO)
3286 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3287 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3288 && micromips_insn_length (mo) != 4)
3290 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3291 && micromips_insn_length (mo) != 2)
3297 /* For consistency checking, verify that all bits of OPCODE are specified
3298 either by the match/mask part of the instruction definition, or by the
3299 operand list. Also build up a list of operands in OPERANDS.
3301 INSN_BITS says which bits of the instruction are significant.
3302 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3303 provides the mips_operand description of each operand. DECODE_OPERAND
3304 is null for MIPS16 instructions. */
3307 validate_mips_insn (const struct mips_opcode *opcode,
3308 unsigned long insn_bits,
3309 const struct mips_operand *(*decode_operand) (const char *),
3310 struct mips_operand_array *operands)
3313 unsigned long used_bits, doubled, undefined, opno, mask;
3314 const struct mips_operand *operand;
3316 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3317 if ((mask & opcode->match) != opcode->match)
3319 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3320 opcode->name, opcode->args);
3325 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3326 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3327 for (s = opcode->args; *s; ++s)
3340 if (!decode_operand)
3341 operand = decode_mips16_operand (*s, FALSE);
3343 operand = decode_operand (s);
3344 if (!operand && opcode->pinfo != INSN_MACRO)
3346 as_bad (_("internal: unknown operand type: %s %s"),
3347 opcode->name, opcode->args);
3350 gas_assert (opno < MAX_OPERANDS);
3351 operands->operand[opno] = operand;
3352 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3354 used_bits = mips_insert_operand (operand, used_bits, -1);
3355 if (operand->type == OP_MDMX_IMM_REG)
3356 /* Bit 5 is the format selector (OB vs QH). The opcode table
3357 has separate entries for each format. */
3358 used_bits &= ~(1 << (operand->lsb + 5));
3359 if (operand->type == OP_ENTRY_EXIT_LIST)
3360 used_bits &= ~(mask & 0x700);
3362 /* Skip prefix characters. */
3363 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3368 doubled = used_bits & mask & insn_bits;
3371 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3372 " %s %s"), doubled, opcode->name, opcode->args);
3376 undefined = ~used_bits & insn_bits;
3377 if (opcode->pinfo != INSN_MACRO && undefined)
3379 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3380 undefined, opcode->name, opcode->args);
3383 used_bits &= ~insn_bits;
3386 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3387 used_bits, opcode->name, opcode->args);
3393 /* The MIPS16 version of validate_mips_insn. */
3396 validate_mips16_insn (const struct mips_opcode *opcode,
3397 struct mips_operand_array *operands)
3399 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3401 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3402 instruction. Use TMP to describe the full instruction. */
3403 struct mips_opcode tmp;
3408 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3410 return validate_mips_insn (opcode, 0xffff, 0, operands);
3413 /* The microMIPS version of validate_mips_insn. */
3416 validate_micromips_insn (const struct mips_opcode *opc,
3417 struct mips_operand_array *operands)
3419 unsigned long insn_bits;
3420 unsigned long major;
3421 unsigned int length;
3423 if (opc->pinfo == INSN_MACRO)
3424 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3427 length = micromips_insn_length (opc);
3428 if (length != 2 && length != 4)
3430 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3431 "%s %s"), length, opc->name, opc->args);
3434 major = opc->match >> (10 + 8 * (length - 2));
3435 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3436 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3438 as_bad (_("internal error: bad microMIPS opcode "
3439 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3443 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3444 insn_bits = 1 << 4 * length;
3445 insn_bits <<= 4 * length;
3447 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3451 /* This function is called once, at assembler startup time. It should set up
3452 all the tables, etc. that the MD part of the assembler will need. */
3457 const char *retval = NULL;
3461 if (mips_pic != NO_PIC)
3463 if (g_switch_seen && g_switch_value != 0)
3464 as_bad (_("-G may not be used in position-independent code"));
3467 else if (mips_abicalls)
3469 if (g_switch_seen && g_switch_value != 0)
3470 as_bad (_("-G may not be used with abicalls"));
3474 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3475 as_warn (_("could not set architecture and machine"));
3477 op_hash = hash_new ();
3479 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3480 for (i = 0; i < NUMOPCODES;)
3482 const char *name = mips_opcodes[i].name;
3484 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3487 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3488 mips_opcodes[i].name, retval);
3489 /* Probably a memory allocation problem? Give up now. */
3490 as_fatal (_("broken assembler, no assembly attempted"));
3494 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3495 decode_mips_operand, &mips_operands[i]))
3497 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3499 create_insn (&nop_insn, mips_opcodes + i);
3500 if (mips_fix_loongson2f_nop)
3501 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3502 nop_insn.fixed_p = 1;
3506 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3509 mips16_op_hash = hash_new ();
3510 mips16_operands = XCNEWVEC (struct mips_operand_array,
3511 bfd_mips16_num_opcodes);
3514 while (i < bfd_mips16_num_opcodes)
3516 const char *name = mips16_opcodes[i].name;
3518 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3520 as_fatal (_("internal: can't hash `%s': %s"),
3521 mips16_opcodes[i].name, retval);
3524 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3526 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3528 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3529 mips16_nop_insn.fixed_p = 1;
3533 while (i < bfd_mips16_num_opcodes
3534 && strcmp (mips16_opcodes[i].name, name) == 0);
3537 micromips_op_hash = hash_new ();
3538 micromips_operands = XCNEWVEC (struct mips_operand_array,
3539 bfd_micromips_num_opcodes);
3542 while (i < bfd_micromips_num_opcodes)
3544 const char *name = micromips_opcodes[i].name;
3546 retval = hash_insert (micromips_op_hash, name,
3547 (void *) µmips_opcodes[i]);
3549 as_fatal (_("internal: can't hash `%s': %s"),
3550 micromips_opcodes[i].name, retval);
3553 struct mips_cl_insn *micromips_nop_insn;
3555 if (!validate_micromips_insn (µmips_opcodes[i],
3556 µmips_operands[i]))
3559 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3561 if (micromips_insn_length (micromips_opcodes + i) == 2)
3562 micromips_nop_insn = µmips_nop16_insn;
3563 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3564 micromips_nop_insn = µmips_nop32_insn;
3568 if (micromips_nop_insn->insn_mo == NULL
3569 && strcmp (name, "nop") == 0)
3571 create_insn (micromips_nop_insn, micromips_opcodes + i);
3572 micromips_nop_insn->fixed_p = 1;
3576 while (++i < bfd_micromips_num_opcodes
3577 && strcmp (micromips_opcodes[i].name, name) == 0);
3581 as_fatal (_("broken assembler, no assembly attempted"));
3583 /* We add all the general register names to the symbol table. This
3584 helps us detect invalid uses of them. */
3585 for (i = 0; reg_names[i].name; i++)
3586 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3587 reg_names[i].num, /* & RNUM_MASK, */
3588 &zero_address_frag));
3590 for (i = 0; reg_names_n32n64[i].name; i++)
3591 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3592 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3593 &zero_address_frag));
3595 for (i = 0; reg_names_o32[i].name; i++)
3596 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3597 reg_names_o32[i].num, /* & RNUM_MASK, */
3598 &zero_address_frag));
3600 for (i = 0; i < 32; i++)
3604 /* R5900 VU0 floating-point register. */
3605 regname[sizeof (rename) - 1] = 0;
3606 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3607 symbol_table_insert (symbol_new (regname, reg_section,
3608 RTYPE_VF | i, &zero_address_frag));
3610 /* R5900 VU0 integer register. */
3611 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3612 symbol_table_insert (symbol_new (regname, reg_section,
3613 RTYPE_VI | i, &zero_address_frag));
3616 snprintf (regname, sizeof (regname) - 1, "$w%d", i);
3617 symbol_table_insert (symbol_new (regname, reg_section,
3618 RTYPE_MSA | i, &zero_address_frag));
3621 obstack_init (&mips_operand_tokens);
3623 mips_no_prev_insn ();
3626 mips_cprmask[0] = 0;
3627 mips_cprmask[1] = 0;
3628 mips_cprmask[2] = 0;
3629 mips_cprmask[3] = 0;
3631 /* set the default alignment for the text section (2**2) */
3632 record_alignment (text_section, 2);
3634 bfd_set_gp_size (stdoutput, g_switch_value);
3636 /* On a native system other than VxWorks, sections must be aligned
3637 to 16 byte boundaries. When configured for an embedded ELF
3638 target, we don't bother. */
3639 if (strncmp (TARGET_OS, "elf", 3) != 0
3640 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3642 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3643 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3644 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3647 /* Create a .reginfo section for register masks and a .mdebug
3648 section for debugging information. */
3656 subseg = now_subseg;
3658 /* The ABI says this section should be loaded so that the
3659 running program can access it. However, we don't load it
3660 if we are configured for an embedded target */
3661 flags = SEC_READONLY | SEC_DATA;
3662 if (strncmp (TARGET_OS, "elf", 3) != 0)
3663 flags |= SEC_ALLOC | SEC_LOAD;
3665 if (mips_abi != N64_ABI)
3667 sec = subseg_new (".reginfo", (subsegT) 0);
3669 bfd_set_section_flags (stdoutput, sec, flags);
3670 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3672 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3676 /* The 64-bit ABI uses a .MIPS.options section rather than
3677 .reginfo section. */
3678 sec = subseg_new (".MIPS.options", (subsegT) 0);
3679 bfd_set_section_flags (stdoutput, sec, flags);
3680 bfd_set_section_alignment (stdoutput, sec, 3);
3682 /* Set up the option header. */
3684 Elf_Internal_Options opthdr;
3687 opthdr.kind = ODK_REGINFO;
3688 opthdr.size = (sizeof (Elf_External_Options)
3689 + sizeof (Elf64_External_RegInfo));
3692 f = frag_more (sizeof (Elf_External_Options));
3693 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3694 (Elf_External_Options *) f);
3696 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3700 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3701 bfd_set_section_flags (stdoutput, sec,
3702 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3703 bfd_set_section_alignment (stdoutput, sec, 3);
3704 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3706 if (ECOFF_DEBUGGING)
3708 sec = subseg_new (".mdebug", (subsegT) 0);
3709 (void) bfd_set_section_flags (stdoutput, sec,
3710 SEC_HAS_CONTENTS | SEC_READONLY);
3711 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3713 else if (mips_flag_pdr)
3715 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3716 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3717 SEC_READONLY | SEC_RELOC
3719 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3722 subseg_set (seg, subseg);
3725 if (mips_fix_vr4120)
3726 init_vr4120_conflicts ();
3730 fpabi_incompatible_with (int fpabi, const char *what)
3732 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3733 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3737 fpabi_requires (int fpabi, const char *what)
3739 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3740 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3743 /* Check -mabi and register sizes against the specified FP ABI. */
3745 check_fpabi (int fpabi)
3749 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3750 if (file_mips_opts.soft_float)
3751 fpabi_incompatible_with (fpabi, "softfloat");
3752 else if (file_mips_opts.single_float)
3753 fpabi_incompatible_with (fpabi, "singlefloat");
3754 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3755 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3756 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3757 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3760 case Val_GNU_MIPS_ABI_FP_XX:
3761 if (mips_abi != O32_ABI)
3762 fpabi_requires (fpabi, "-mabi=32");
3763 else if (file_mips_opts.soft_float)
3764 fpabi_incompatible_with (fpabi, "softfloat");
3765 else if (file_mips_opts.single_float)
3766 fpabi_incompatible_with (fpabi, "singlefloat");
3767 else if (file_mips_opts.fp != 0)
3768 fpabi_requires (fpabi, "fp=xx");
3771 case Val_GNU_MIPS_ABI_FP_64A:
3772 case Val_GNU_MIPS_ABI_FP_64:
3773 if (mips_abi != O32_ABI)
3774 fpabi_requires (fpabi, "-mabi=32");
3775 else if (file_mips_opts.soft_float)
3776 fpabi_incompatible_with (fpabi, "softfloat");
3777 else if (file_mips_opts.single_float)
3778 fpabi_incompatible_with (fpabi, "singlefloat");
3779 else if (file_mips_opts.fp != 64)
3780 fpabi_requires (fpabi, "fp=64");
3781 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3782 fpabi_incompatible_with (fpabi, "nooddspreg");
3783 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3784 fpabi_requires (fpabi, "nooddspreg");
3787 case Val_GNU_MIPS_ABI_FP_SINGLE:
3788 if (file_mips_opts.soft_float)
3789 fpabi_incompatible_with (fpabi, "softfloat");
3790 else if (!file_mips_opts.single_float)
3791 fpabi_requires (fpabi, "singlefloat");
3794 case Val_GNU_MIPS_ABI_FP_SOFT:
3795 if (!file_mips_opts.soft_float)
3796 fpabi_requires (fpabi, "softfloat");
3799 case Val_GNU_MIPS_ABI_FP_OLD_64:
3800 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3801 Tag_GNU_MIPS_ABI_FP, fpabi);
3804 case Val_GNU_MIPS_ABI_FP_NAN2008:
3805 /* Silently ignore compatibility value. */
3809 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3810 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3815 /* Perform consistency checks on the current options. */
3818 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3820 /* Check the size of integer registers agrees with the ABI and ISA. */
3821 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3822 as_bad (_("`gp=64' used with a 32-bit processor"));
3824 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3825 as_bad (_("`gp=32' used with a 64-bit ABI"));
3827 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3828 as_bad (_("`gp=64' used with a 32-bit ABI"));
3830 /* Check the size of the float registers agrees with the ABI and ISA. */
3834 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3835 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3836 else if (opts->single_float == 1)
3837 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3840 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3841 as_bad (_("`fp=64' used with a 32-bit fpu"));
3843 && ABI_NEEDS_32BIT_REGS (mips_abi)
3844 && !ISA_HAS_MXHC1 (opts->isa))
3845 as_warn (_("`fp=64' used with a 32-bit ABI"));
3849 && ABI_NEEDS_64BIT_REGS (mips_abi))
3850 as_warn (_("`fp=32' used with a 64-bit ABI"));
3851 if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0)
3852 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3855 as_bad (_("Unknown size of floating point registers"));
3859 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3860 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3862 if (opts->micromips == 1 && opts->mips16 == 1)
3863 as_bad (_("`mips16' cannot be used with `micromips'"));
3864 else if (ISA_IS_R6 (mips_opts.isa)
3865 && (opts->micromips == 1
3866 || opts->mips16 == 1))
3867 as_fatal (_("`%s' can not be used with `%s'"),
3868 opts->micromips ? "micromips" : "mips16",
3869 mips_cpu_info_from_isa (mips_opts.isa)->name);
3871 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3872 as_fatal (_("branch relaxation is not supported in `%s'"),
3873 mips_cpu_info_from_isa (opts->isa)->name);
3876 /* Perform consistency checks on the module level options exactly once.
3877 This is a deferred check that happens:
3878 at the first .set directive
3879 or, at the first pseudo op that generates code (inc .dc.a)
3880 or, at the first instruction
3884 file_mips_check_options (void)
3886 const struct mips_cpu_info *arch_info = 0;
3888 if (file_mips_opts_checked)
3891 /* The following code determines the register size.
3892 Similar code was added to GCC 3.3 (see override_options() in
3893 config/mips/mips.c). The GAS and GCC code should be kept in sync
3894 as much as possible. */
3896 if (file_mips_opts.gp < 0)
3898 /* Infer the integer register size from the ABI and processor.
3899 Restrict ourselves to 32-bit registers if that's all the
3900 processor has, or if the ABI cannot handle 64-bit registers. */
3901 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3902 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3906 if (file_mips_opts.fp < 0)
3908 /* No user specified float register size.
3909 ??? GAS treats single-float processors as though they had 64-bit
3910 float registers (although it complains when double-precision
3911 instructions are used). As things stand, saying they have 32-bit
3912 registers would lead to spurious "register must be even" messages.
3913 So here we assume float registers are never smaller than the
3915 if (file_mips_opts.gp == 64)
3916 /* 64-bit integer registers implies 64-bit float registers. */
3917 file_mips_opts.fp = 64;
3918 else if ((file_mips_opts.ase & FP64_ASES)
3919 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3920 /* Handle ASEs that require 64-bit float registers, if possible. */
3921 file_mips_opts.fp = 64;
3922 else if (ISA_IS_R6 (mips_opts.isa))
3923 /* R6 implies 64-bit float registers. */
3924 file_mips_opts.fp = 64;
3926 /* 32-bit float registers. */
3927 file_mips_opts.fp = 32;
3930 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3932 /* Disable operations on odd-numbered floating-point registers by default
3933 when using the FPXX ABI. */
3934 if (file_mips_opts.oddspreg < 0)
3936 if (file_mips_opts.fp == 0)
3937 file_mips_opts.oddspreg = 0;
3939 file_mips_opts.oddspreg = 1;
3942 /* End of GCC-shared inference code. */
3944 /* This flag is set when we have a 64-bit capable CPU but use only
3945 32-bit wide registers. Note that EABI does not use it. */
3946 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3947 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3948 || mips_abi == O32_ABI))
3951 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3952 as_bad (_("trap exception not supported at ISA 1"));
3954 /* If the selected architecture includes support for ASEs, enable
3955 generation of code for them. */
3956 if (file_mips_opts.mips16 == -1)
3957 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3958 if (file_mips_opts.micromips == -1)
3959 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3962 if (mips_nan2008 == -1)
3963 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3964 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3965 as_fatal (_("`%s' does not support legacy NaN"),
3966 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3968 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3969 being selected implicitly. */
3970 if (file_mips_opts.fp != 64)
3971 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3973 /* If the user didn't explicitly select or deselect a particular ASE,
3974 use the default setting for the CPU. */
3975 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3977 /* Set up the current options. These may change throughout assembly. */
3978 mips_opts = file_mips_opts;
3980 mips_check_isa_supports_ases ();
3981 mips_check_options (&file_mips_opts, TRUE);
3982 file_mips_opts_checked = TRUE;
3984 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3985 as_warn (_("could not set architecture and machine"));
3989 md_assemble (char *str)
3991 struct mips_cl_insn insn;
3992 bfd_reloc_code_real_type unused_reloc[3]
3993 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3995 file_mips_check_options ();
3997 imm_expr.X_op = O_absent;
3998 offset_expr.X_op = O_absent;
3999 offset_reloc[0] = BFD_RELOC_UNUSED;
4000 offset_reloc[1] = BFD_RELOC_UNUSED;
4001 offset_reloc[2] = BFD_RELOC_UNUSED;
4003 mips_mark_labels ();
4004 mips_assembling_insn = TRUE;
4005 clear_insn_error ();
4007 if (mips_opts.mips16)
4008 mips16_ip (str, &insn);
4011 mips_ip (str, &insn);
4012 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4013 str, insn.insn_opcode));
4017 report_insn_error (str);
4018 else if (insn.insn_mo->pinfo == INSN_MACRO)
4021 if (mips_opts.mips16)
4022 mips16_macro (&insn);
4029 if (offset_expr.X_op != O_absent)
4030 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4032 append_insn (&insn, NULL, unused_reloc, FALSE);
4035 mips_assembling_insn = FALSE;
4038 /* Convenience functions for abstracting away the differences between
4039 MIPS16 and non-MIPS16 relocations. */
4041 static inline bfd_boolean
4042 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4046 case BFD_RELOC_MIPS16_JMP:
4047 case BFD_RELOC_MIPS16_GPREL:
4048 case BFD_RELOC_MIPS16_GOT16:
4049 case BFD_RELOC_MIPS16_CALL16:
4050 case BFD_RELOC_MIPS16_HI16_S:
4051 case BFD_RELOC_MIPS16_HI16:
4052 case BFD_RELOC_MIPS16_LO16:
4060 static inline bfd_boolean
4061 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4065 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4066 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4067 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4068 case BFD_RELOC_MICROMIPS_GPREL16:
4069 case BFD_RELOC_MICROMIPS_JMP:
4070 case BFD_RELOC_MICROMIPS_HI16:
4071 case BFD_RELOC_MICROMIPS_HI16_S:
4072 case BFD_RELOC_MICROMIPS_LO16:
4073 case BFD_RELOC_MICROMIPS_LITERAL:
4074 case BFD_RELOC_MICROMIPS_GOT16:
4075 case BFD_RELOC_MICROMIPS_CALL16:
4076 case BFD_RELOC_MICROMIPS_GOT_HI16:
4077 case BFD_RELOC_MICROMIPS_GOT_LO16:
4078 case BFD_RELOC_MICROMIPS_CALL_HI16:
4079 case BFD_RELOC_MICROMIPS_CALL_LO16:
4080 case BFD_RELOC_MICROMIPS_SUB:
4081 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4082 case BFD_RELOC_MICROMIPS_GOT_OFST:
4083 case BFD_RELOC_MICROMIPS_GOT_DISP:
4084 case BFD_RELOC_MICROMIPS_HIGHEST:
4085 case BFD_RELOC_MICROMIPS_HIGHER:
4086 case BFD_RELOC_MICROMIPS_SCN_DISP:
4087 case BFD_RELOC_MICROMIPS_JALR:
4095 static inline bfd_boolean
4096 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4098 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4101 static inline bfd_boolean
4102 got16_reloc_p (bfd_reloc_code_real_type reloc)
4104 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4105 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4108 static inline bfd_boolean
4109 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4111 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4112 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4115 static inline bfd_boolean
4116 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4118 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4119 || reloc == BFD_RELOC_MICROMIPS_LO16);
4122 static inline bfd_boolean
4123 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4125 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4128 static inline bfd_boolean
4129 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4131 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4132 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4135 /* Return true if RELOC is a PC-relative relocation that does not have
4136 full address range. */
4138 static inline bfd_boolean
4139 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4143 case BFD_RELOC_16_PCREL_S2:
4144 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4145 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4146 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4147 case BFD_RELOC_MIPS_21_PCREL_S2:
4148 case BFD_RELOC_MIPS_26_PCREL_S2:
4149 case BFD_RELOC_MIPS_18_PCREL_S3:
4150 case BFD_RELOC_MIPS_19_PCREL_S2:
4153 case BFD_RELOC_32_PCREL:
4154 case BFD_RELOC_HI16_S_PCREL:
4155 case BFD_RELOC_LO16_PCREL:
4156 return HAVE_64BIT_ADDRESSES;
4163 /* Return true if the given relocation might need a matching %lo().
4164 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4165 need a matching %lo() when applied to local symbols. */
4167 static inline bfd_boolean
4168 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4170 return (HAVE_IN_PLACE_ADDENDS
4171 && (hi16_reloc_p (reloc)
4172 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4173 all GOT16 relocations evaluate to "G". */
4174 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4177 /* Return the type of %lo() reloc needed by RELOC, given that
4178 reloc_needs_lo_p. */
4180 static inline bfd_reloc_code_real_type
4181 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4183 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4184 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4188 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4191 static inline bfd_boolean
4192 fixup_has_matching_lo_p (fixS *fixp)
4194 return (fixp->fx_next != NULL
4195 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4196 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4197 && fixp->fx_offset == fixp->fx_next->fx_offset);
4200 /* Move all labels in LABELS to the current insertion point. TEXT_P
4201 says whether the labels refer to text or data. */
4204 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4206 struct insn_label_list *l;
4209 for (l = labels; l != NULL; l = l->next)
4211 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4212 symbol_set_frag (l->label, frag_now);
4213 val = (valueT) frag_now_fix ();
4214 /* MIPS16/microMIPS text labels are stored as odd. */
4215 if (text_p && HAVE_CODE_COMPRESSION)
4217 S_SET_VALUE (l->label, val);
4221 /* Move all labels in insn_labels to the current insertion point
4222 and treat them as text labels. */
4225 mips_move_text_labels (void)
4227 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4231 s_is_linkonce (symbolS *sym, segT from_seg)
4233 bfd_boolean linkonce = FALSE;
4234 segT symseg = S_GET_SEGMENT (sym);
4236 if (symseg != from_seg && !S_IS_LOCAL (sym))
4238 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4240 /* The GNU toolchain uses an extension for ELF: a section
4241 beginning with the magic string .gnu.linkonce is a
4242 linkonce section. */
4243 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4244 sizeof ".gnu.linkonce" - 1) == 0)
4250 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4251 linker to handle them specially, such as generating jalx instructions
4252 when needed. We also make them odd for the duration of the assembly,
4253 in order to generate the right sort of code. We will make them even
4254 in the adjust_symtab routine, while leaving them marked. This is
4255 convenient for the debugger and the disassembler. The linker knows
4256 to make them odd again. */
4259 mips_compressed_mark_label (symbolS *label)
4261 gas_assert (HAVE_CODE_COMPRESSION);
4263 if (mips_opts.mips16)
4264 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4266 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4267 if ((S_GET_VALUE (label) & 1) == 0
4268 /* Don't adjust the address if the label is global or weak, or
4269 in a link-once section, since we'll be emitting symbol reloc
4270 references to it which will be patched up by the linker, and
4271 the final value of the symbol may or may not be MIPS16/microMIPS. */
4272 && !S_IS_WEAK (label)
4273 && !S_IS_EXTERNAL (label)
4274 && !s_is_linkonce (label, now_seg))
4275 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4278 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4281 mips_compressed_mark_labels (void)
4283 struct insn_label_list *l;
4285 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4286 mips_compressed_mark_label (l->label);
4289 /* End the current frag. Make it a variant frag and record the
4293 relax_close_frag (void)
4295 mips_macro_warning.first_frag = frag_now;
4296 frag_var (rs_machine_dependent, 0, 0,
4297 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4298 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4300 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4301 mips_relax.first_fixup = 0;
4304 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4305 See the comment above RELAX_ENCODE for more details. */
4308 relax_start (symbolS *symbol)
4310 gas_assert (mips_relax.sequence == 0);
4311 mips_relax.sequence = 1;
4312 mips_relax.symbol = symbol;
4315 /* Start generating the second version of a relaxable sequence.
4316 See the comment above RELAX_ENCODE for more details. */
4321 gas_assert (mips_relax.sequence == 1);
4322 mips_relax.sequence = 2;
4325 /* End the current relaxable sequence. */
4330 gas_assert (mips_relax.sequence == 2);
4331 relax_close_frag ();
4332 mips_relax.sequence = 0;
4335 /* Return true if IP is a delayed branch or jump. */
4337 static inline bfd_boolean
4338 delayed_branch_p (const struct mips_cl_insn *ip)
4340 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4341 | INSN_COND_BRANCH_DELAY
4342 | INSN_COND_BRANCH_LIKELY)) != 0;
4345 /* Return true if IP is a compact branch or jump. */
4347 static inline bfd_boolean
4348 compact_branch_p (const struct mips_cl_insn *ip)
4350 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4351 | INSN2_COND_BRANCH)) != 0;
4354 /* Return true if IP is an unconditional branch or jump. */
4356 static inline bfd_boolean
4357 uncond_branch_p (const struct mips_cl_insn *ip)
4359 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4360 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4363 /* Return true if IP is a branch-likely instruction. */
4365 static inline bfd_boolean
4366 branch_likely_p (const struct mips_cl_insn *ip)
4368 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4371 /* Return the type of nop that should be used to fill the delay slot
4372 of delayed branch IP. */
4374 static struct mips_cl_insn *
4375 get_delay_slot_nop (const struct mips_cl_insn *ip)
4377 if (mips_opts.micromips
4378 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4379 return µmips_nop32_insn;
4383 /* Return a mask that has bit N set if OPCODE reads the register(s)
4387 insn_read_mask (const struct mips_opcode *opcode)
4389 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4392 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4396 insn_write_mask (const struct mips_opcode *opcode)
4398 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4401 /* Return a mask of the registers specified by operand OPERAND of INSN.
4402 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4406 operand_reg_mask (const struct mips_cl_insn *insn,
4407 const struct mips_operand *operand,
4408 unsigned int type_mask)
4410 unsigned int uval, vsel;
4412 switch (operand->type)
4419 case OP_ADDIUSP_INT:
4420 case OP_ENTRY_EXIT_LIST:
4421 case OP_REPEAT_DEST_REG:
4422 case OP_REPEAT_PREV_REG:
4425 case OP_VU0_MATCH_SUFFIX:
4430 case OP_OPTIONAL_REG:
4432 const struct mips_reg_operand *reg_op;
4434 reg_op = (const struct mips_reg_operand *) operand;
4435 if (!(type_mask & (1 << reg_op->reg_type)))
4437 uval = insn_extract_operand (insn, operand);
4438 return 1 << mips_decode_reg_operand (reg_op, uval);
4443 const struct mips_reg_pair_operand *pair_op;
4445 pair_op = (const struct mips_reg_pair_operand *) operand;
4446 if (!(type_mask & (1 << pair_op->reg_type)))
4448 uval = insn_extract_operand (insn, operand);
4449 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4452 case OP_CLO_CLZ_DEST:
4453 if (!(type_mask & (1 << OP_REG_GP)))
4455 uval = insn_extract_operand (insn, operand);
4456 return (1 << (uval & 31)) | (1 << (uval >> 5));
4459 if (!(type_mask & (1 << OP_REG_GP)))
4461 uval = insn_extract_operand (insn, operand);
4462 gas_assert ((uval & 31) == (uval >> 5));
4463 return 1 << (uval & 31);
4466 case OP_NON_ZERO_REG:
4467 if (!(type_mask & (1 << OP_REG_GP)))
4469 uval = insn_extract_operand (insn, operand);
4470 return 1 << (uval & 31);
4472 case OP_LWM_SWM_LIST:
4475 case OP_SAVE_RESTORE_LIST:
4478 case OP_MDMX_IMM_REG:
4479 if (!(type_mask & (1 << OP_REG_VEC)))
4481 uval = insn_extract_operand (insn, operand);
4483 if ((vsel & 0x18) == 0x18)
4485 return 1 << (uval & 31);
4488 if (!(type_mask & (1 << OP_REG_GP)))
4490 return 1 << insn_extract_operand (insn, operand);
4495 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4496 where bit N of OPNO_MASK is set if operand N should be included.
4497 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4501 insn_reg_mask (const struct mips_cl_insn *insn,
4502 unsigned int type_mask, unsigned int opno_mask)
4504 unsigned int opno, reg_mask;
4508 while (opno_mask != 0)
4511 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4518 /* Return the mask of core registers that IP reads. */
4521 gpr_read_mask (const struct mips_cl_insn *ip)
4523 unsigned long pinfo, pinfo2;
4526 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4527 pinfo = ip->insn_mo->pinfo;
4528 pinfo2 = ip->insn_mo->pinfo2;
4529 if (pinfo & INSN_UDI)
4531 /* UDI instructions have traditionally been assumed to read RS
4533 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4534 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4536 if (pinfo & INSN_READ_GPR_24)
4538 if (pinfo2 & INSN2_READ_GPR_16)
4540 if (pinfo2 & INSN2_READ_SP)
4542 if (pinfo2 & INSN2_READ_GPR_31)
4544 /* Don't include register 0. */
4548 /* Return the mask of core registers that IP writes. */
4551 gpr_write_mask (const struct mips_cl_insn *ip)
4553 unsigned long pinfo, pinfo2;
4556 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4557 pinfo = ip->insn_mo->pinfo;
4558 pinfo2 = ip->insn_mo->pinfo2;
4559 if (pinfo & INSN_WRITE_GPR_24)
4561 if (pinfo & INSN_WRITE_GPR_31)
4563 if (pinfo & INSN_UDI)
4564 /* UDI instructions have traditionally been assumed to write to RD. */
4565 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4566 if (pinfo2 & INSN2_WRITE_SP)
4568 /* Don't include register 0. */
4572 /* Return the mask of floating-point registers that IP reads. */
4575 fpr_read_mask (const struct mips_cl_insn *ip)
4577 unsigned long pinfo;
4580 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4581 | (1 << OP_REG_MSA)),
4582 insn_read_mask (ip->insn_mo));
4583 pinfo = ip->insn_mo->pinfo;
4584 /* Conservatively treat all operands to an FP_D instruction are doubles.
4585 (This is overly pessimistic for things like cvt.d.s.) */
4586 if (FPR_SIZE != 64 && (pinfo & FP_D))
4591 /* Return the mask of floating-point registers that IP writes. */
4594 fpr_write_mask (const struct mips_cl_insn *ip)
4596 unsigned long pinfo;
4599 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4600 | (1 << OP_REG_MSA)),
4601 insn_write_mask (ip->insn_mo));
4602 pinfo = ip->insn_mo->pinfo;
4603 /* Conservatively treat all operands to an FP_D instruction are doubles.
4604 (This is overly pessimistic for things like cvt.s.d.) */
4605 if (FPR_SIZE != 64 && (pinfo & FP_D))
4610 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4611 Check whether that is allowed. */
4614 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4616 const char *s = insn->name;
4617 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4619 && mips_opts.oddspreg;
4621 if (insn->pinfo == INSN_MACRO)
4622 /* Let a macro pass, we'll catch it later when it is expanded. */
4625 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4626 otherwise it depends on oddspreg. */
4627 if ((insn->pinfo & FP_S)
4628 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4629 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4630 return FPR_SIZE == 32 || oddspreg;
4632 /* Allow odd registers for single-precision ops and double-precision if the
4633 floating-point registers are 64-bit wide. */
4634 switch (insn->pinfo & (FP_S | FP_D))
4640 return FPR_SIZE == 64;
4645 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4646 s = strchr (insn->name, '.');
4647 if (s != NULL && opnum == 2)
4648 s = strchr (s + 1, '.');
4649 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4652 return FPR_SIZE == 64;
4655 /* Information about an instruction argument that we're trying to match. */
4656 struct mips_arg_info
4658 /* The instruction so far. */
4659 struct mips_cl_insn *insn;
4661 /* The first unconsumed operand token. */
4662 struct mips_operand_token *token;
4664 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4667 /* The 1-based argument number, for error reporting. This does not
4668 count elided optional registers, etc.. */
4671 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4672 unsigned int last_regno;
4674 /* If the first operand was an OP_REG, this is the register that it
4675 specified, otherwise it is ILLEGAL_REG. */
4676 unsigned int dest_regno;
4678 /* The value of the last OP_INT operand. Only used for OP_MSB,
4679 where it gives the lsb position. */
4680 unsigned int last_op_int;
4682 /* If true, match routines should assume that no later instruction
4683 alternative matches and should therefore be as accomodating as
4684 possible. Match routines should not report errors if something
4685 is only invalid for !LAX_MATCH. */
4686 bfd_boolean lax_match;
4688 /* True if a reference to the current AT register was seen. */
4689 bfd_boolean seen_at;
4692 /* Record that the argument is out of range. */
4695 match_out_of_range (struct mips_arg_info *arg)
4697 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4700 /* Record that the argument isn't constant but needs to be. */
4703 match_not_constant (struct mips_arg_info *arg)
4705 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4709 /* Try to match an OT_CHAR token for character CH. Consume the token
4710 and return true on success, otherwise return false. */
4713 match_char (struct mips_arg_info *arg, char ch)
4715 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4725 /* Try to get an expression from the next tokens in ARG. Consume the
4726 tokens and return true on success, storing the expression value in
4727 VALUE and relocation types in R. */
4730 match_expression (struct mips_arg_info *arg, expressionS *value,
4731 bfd_reloc_code_real_type *r)
4733 /* If the next token is a '(' that was parsed as being part of a base
4734 expression, assume we have an elided offset. The later match will fail
4735 if this turns out to be wrong. */
4736 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4738 value->X_op = O_constant;
4739 value->X_add_number = 0;
4740 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4744 /* Reject register-based expressions such as "0+$2" and "(($2))".
4745 For plain registers the default error seems more appropriate. */
4746 if (arg->token->type == OT_INTEGER
4747 && arg->token->u.integer.value.X_op == O_register)
4749 set_insn_error (arg->argnum, _("register value used as expression"));
4753 if (arg->token->type == OT_INTEGER)
4755 *value = arg->token->u.integer.value;
4756 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4762 (arg->argnum, _("operand %d must be an immediate expression"),
4767 /* Try to get a constant expression from the next tokens in ARG. Consume
4768 the tokens and return return true on success, storing the constant value
4769 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4773 match_const_int (struct mips_arg_info *arg, offsetT *value)
4776 bfd_reloc_code_real_type r[3];
4778 if (!match_expression (arg, &ex, r))
4781 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4782 *value = ex.X_add_number;
4785 match_not_constant (arg);
4791 /* Return the RTYPE_* flags for a register operand of type TYPE that
4792 appears in instruction OPCODE. */
4795 convert_reg_type (const struct mips_opcode *opcode,
4796 enum mips_reg_operand_type type)
4801 return RTYPE_NUM | RTYPE_GP;
4804 /* Allow vector register names for MDMX if the instruction is a 64-bit
4805 FPR load, store or move (including moves to and from GPRs). */
4806 if ((mips_opts.ase & ASE_MDMX)
4807 && (opcode->pinfo & FP_D)
4808 && (opcode->pinfo & (INSN_COPROC_MOVE
4809 | INSN_COPROC_MEMORY_DELAY
4812 | INSN_STORE_MEMORY)))
4813 return RTYPE_FPU | RTYPE_VEC;
4817 if (opcode->pinfo & (FP_D | FP_S))
4818 return RTYPE_CCC | RTYPE_FCC;
4822 if (opcode->membership & INSN_5400)
4824 return RTYPE_FPU | RTYPE_VEC;
4830 if (opcode->name[strlen (opcode->name) - 1] == '0')
4831 return RTYPE_NUM | RTYPE_CP0;
4838 return RTYPE_NUM | RTYPE_VI;
4841 return RTYPE_NUM | RTYPE_VF;
4843 case OP_REG_R5900_I:
4844 return RTYPE_R5900_I;
4846 case OP_REG_R5900_Q:
4847 return RTYPE_R5900_Q;
4849 case OP_REG_R5900_R:
4850 return RTYPE_R5900_R;
4852 case OP_REG_R5900_ACC:
4853 return RTYPE_R5900_ACC;
4858 case OP_REG_MSA_CTRL:
4864 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4867 check_regno (struct mips_arg_info *arg,
4868 enum mips_reg_operand_type type, unsigned int regno)
4870 if (AT && type == OP_REG_GP && regno == AT)
4871 arg->seen_at = TRUE;
4873 if (type == OP_REG_FP
4875 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4877 /* This was a warning prior to introducing O32 FPXX and FP64 support
4878 so maintain a warning for FP32 but raise an error for the new
4881 as_warn (_("float register should be even, was %d"), regno);
4883 as_bad (_("float register should be even, was %d"), regno);
4886 if (type == OP_REG_CCC)
4891 name = arg->insn->insn_mo->name;
4892 length = strlen (name);
4893 if ((regno & 1) != 0
4894 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4895 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4896 as_warn (_("condition code register should be even for %s, was %d"),
4899 if ((regno & 3) != 0
4900 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4901 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4906 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4907 a register of type TYPE. Return true on success, storing the register
4908 number in *REGNO and warning about any dubious uses. */
4911 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4912 unsigned int symval, unsigned int *regno)
4914 if (type == OP_REG_VEC)
4915 symval = mips_prefer_vec_regno (symval);
4916 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4919 *regno = symval & RNUM_MASK;
4920 check_regno (arg, type, *regno);
4924 /* Try to interpret the next token in ARG as a register of type TYPE.
4925 Consume the token and return true on success, storing the register
4926 number in *REGNO. Return false on failure. */
4929 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4930 unsigned int *regno)
4932 if (arg->token->type == OT_REG
4933 && match_regno (arg, type, arg->token->u.regno, regno))
4941 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4942 Consume the token and return true on success, storing the register numbers
4943 in *REGNO1 and *REGNO2. Return false on failure. */
4946 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4947 unsigned int *regno1, unsigned int *regno2)
4949 if (match_reg (arg, type, regno1))
4954 if (arg->token->type == OT_REG_RANGE
4955 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4956 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4957 && *regno1 <= *regno2)
4965 /* OP_INT matcher. */
4968 match_int_operand (struct mips_arg_info *arg,
4969 const struct mips_operand *operand_base)
4971 const struct mips_int_operand *operand;
4973 int min_val, max_val, factor;
4976 operand = (const struct mips_int_operand *) operand_base;
4977 factor = 1 << operand->shift;
4978 min_val = mips_int_operand_min (operand);
4979 max_val = mips_int_operand_max (operand);
4981 if (operand_base->lsb == 0
4982 && operand_base->size == 16
4983 && operand->shift == 0
4984 && operand->bias == 0
4985 && (operand->max_val == 32767 || operand->max_val == 65535))
4987 /* The operand can be relocated. */
4988 if (!match_expression (arg, &offset_expr, offset_reloc))
4991 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4992 /* Relocation operators were used. Accept the arguent and
4993 leave the relocation value in offset_expr and offset_relocs
4994 for the caller to process. */
4997 if (offset_expr.X_op != O_constant)
4999 /* Accept non-constant operands if no later alternative matches,
5000 leaving it for the caller to process. */
5001 if (!arg->lax_match)
5003 offset_reloc[0] = BFD_RELOC_LO16;
5007 /* Clear the global state; we're going to install the operand
5009 sval = offset_expr.X_add_number;
5010 offset_expr.X_op = O_absent;
5012 /* For compatibility with older assemblers, we accept
5013 0x8000-0xffff as signed 16-bit numbers when only
5014 signed numbers are allowed. */
5017 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5018 if (!arg->lax_match && sval <= max_val)
5024 if (!match_const_int (arg, &sval))
5028 arg->last_op_int = sval;
5030 if (sval < min_val || sval > max_val || sval % factor)
5032 match_out_of_range (arg);
5036 uval = (unsigned int) sval >> operand->shift;
5037 uval -= operand->bias;
5039 /* Handle -mfix-cn63xxp1. */
5041 && mips_fix_cn63xxp1
5042 && !mips_opts.micromips
5043 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5058 /* The rest must be changed to 28. */
5063 insn_insert_operand (arg->insn, operand_base, uval);
5067 /* OP_MAPPED_INT matcher. */
5070 match_mapped_int_operand (struct mips_arg_info *arg,
5071 const struct mips_operand *operand_base)
5073 const struct mips_mapped_int_operand *operand;
5074 unsigned int uval, num_vals;
5077 operand = (const struct mips_mapped_int_operand *) operand_base;
5078 if (!match_const_int (arg, &sval))
5081 num_vals = 1 << operand_base->size;
5082 for (uval = 0; uval < num_vals; uval++)
5083 if (operand->int_map[uval] == sval)
5085 if (uval == num_vals)
5087 match_out_of_range (arg);
5091 insn_insert_operand (arg->insn, operand_base, uval);
5095 /* OP_MSB matcher. */
5098 match_msb_operand (struct mips_arg_info *arg,
5099 const struct mips_operand *operand_base)
5101 const struct mips_msb_operand *operand;
5102 int min_val, max_val, max_high;
5103 offsetT size, sval, high;
5105 operand = (const struct mips_msb_operand *) operand_base;
5106 min_val = operand->bias;
5107 max_val = min_val + (1 << operand_base->size) - 1;
5108 max_high = operand->opsize;
5110 if (!match_const_int (arg, &size))
5113 high = size + arg->last_op_int;
5114 sval = operand->add_lsb ? high : size;
5116 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5118 match_out_of_range (arg);
5121 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5125 /* OP_REG matcher. */
5128 match_reg_operand (struct mips_arg_info *arg,
5129 const struct mips_operand *operand_base)
5131 const struct mips_reg_operand *operand;
5132 unsigned int regno, uval, num_vals;
5134 operand = (const struct mips_reg_operand *) operand_base;
5135 if (!match_reg (arg, operand->reg_type, ®no))
5138 if (operand->reg_map)
5140 num_vals = 1 << operand->root.size;
5141 for (uval = 0; uval < num_vals; uval++)
5142 if (operand->reg_map[uval] == regno)
5144 if (num_vals == uval)
5150 arg->last_regno = regno;
5151 if (arg->opnum == 1)
5152 arg->dest_regno = regno;
5153 insn_insert_operand (arg->insn, operand_base, uval);
5157 /* OP_REG_PAIR matcher. */
5160 match_reg_pair_operand (struct mips_arg_info *arg,
5161 const struct mips_operand *operand_base)
5163 const struct mips_reg_pair_operand *operand;
5164 unsigned int regno1, regno2, uval, num_vals;
5166 operand = (const struct mips_reg_pair_operand *) operand_base;
5167 if (!match_reg (arg, operand->reg_type, ®no1)
5168 || !match_char (arg, ',')
5169 || !match_reg (arg, operand->reg_type, ®no2))
5172 num_vals = 1 << operand_base->size;
5173 for (uval = 0; uval < num_vals; uval++)
5174 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5176 if (uval == num_vals)
5179 insn_insert_operand (arg->insn, operand_base, uval);
5183 /* OP_PCREL matcher. The caller chooses the relocation type. */
5186 match_pcrel_operand (struct mips_arg_info *arg)
5188 bfd_reloc_code_real_type r[3];
5190 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5193 /* OP_PERF_REG matcher. */
5196 match_perf_reg_operand (struct mips_arg_info *arg,
5197 const struct mips_operand *operand)
5201 if (!match_const_int (arg, &sval))
5206 || (mips_opts.arch == CPU_R5900
5207 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5208 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5210 set_insn_error (arg->argnum, _("invalid performance register"));
5214 insn_insert_operand (arg->insn, operand, sval);
5218 /* OP_ADDIUSP matcher. */
5221 match_addiusp_operand (struct mips_arg_info *arg,
5222 const struct mips_operand *operand)
5227 if (!match_const_int (arg, &sval))
5232 match_out_of_range (arg);
5237 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5239 match_out_of_range (arg);
5243 uval = (unsigned int) sval;
5244 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5245 insn_insert_operand (arg->insn, operand, uval);
5249 /* OP_CLO_CLZ_DEST matcher. */
5252 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5253 const struct mips_operand *operand)
5257 if (!match_reg (arg, OP_REG_GP, ®no))
5260 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5264 /* OP_CHECK_PREV matcher. */
5267 match_check_prev_operand (struct mips_arg_info *arg,
5268 const struct mips_operand *operand_base)
5270 const struct mips_check_prev_operand *operand;
5273 operand = (const struct mips_check_prev_operand *) operand_base;
5275 if (!match_reg (arg, OP_REG_GP, ®no))
5278 if (!operand->zero_ok && regno == 0)
5281 if ((operand->less_than_ok && regno < arg->last_regno)
5282 || (operand->greater_than_ok && regno > arg->last_regno)
5283 || (operand->equal_ok && regno == arg->last_regno))
5285 arg->last_regno = regno;
5286 insn_insert_operand (arg->insn, operand_base, regno);
5293 /* OP_SAME_RS_RT matcher. */
5296 match_same_rs_rt_operand (struct mips_arg_info *arg,
5297 const struct mips_operand *operand)
5301 if (!match_reg (arg, OP_REG_GP, ®no))
5306 set_insn_error (arg->argnum, _("the source register must not be $0"));
5310 arg->last_regno = regno;
5312 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5316 /* OP_LWM_SWM_LIST matcher. */
5319 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5320 const struct mips_operand *operand)
5322 unsigned int reglist, sregs, ra, regno1, regno2;
5323 struct mips_arg_info reset;
5326 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5330 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5335 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5338 while (match_char (arg, ',')
5339 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5342 if (operand->size == 2)
5344 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5350 and any permutations of these. */
5351 if ((reglist & 0xfff1ffff) != 0x80010000)
5354 sregs = (reglist >> 17) & 7;
5359 /* The list must include at least one of ra and s0-sN,
5360 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5361 which are $23 and $30 respectively.) E.g.:
5369 and any permutations of these. */
5370 if ((reglist & 0x3f00ffff) != 0)
5373 ra = (reglist >> 27) & 0x10;
5374 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5377 if ((sregs & -sregs) != sregs)
5380 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5384 /* OP_ENTRY_EXIT_LIST matcher. */
5387 match_entry_exit_operand (struct mips_arg_info *arg,
5388 const struct mips_operand *operand)
5391 bfd_boolean is_exit;
5393 /* The format is the same for both ENTRY and EXIT, but the constraints
5395 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5396 mask = (is_exit ? 7 << 3 : 0);
5399 unsigned int regno1, regno2;
5400 bfd_boolean is_freg;
5402 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5404 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5409 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5412 mask |= (5 + regno2) << 3;
5414 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5415 mask |= (regno2 - 3) << 3;
5416 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5417 mask |= (regno2 - 15) << 1;
5418 else if (regno1 == RA && regno2 == RA)
5423 while (match_char (arg, ','));
5425 insn_insert_operand (arg->insn, operand, mask);
5429 /* OP_SAVE_RESTORE_LIST matcher. */
5432 match_save_restore_list_operand (struct mips_arg_info *arg)
5434 unsigned int opcode, args, statics, sregs;
5435 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5438 opcode = arg->insn->insn_opcode;
5440 num_frame_sizes = 0;
5446 unsigned int regno1, regno2;
5448 if (arg->token->type == OT_INTEGER)
5450 /* Handle the frame size. */
5451 if (!match_const_int (arg, &frame_size))
5453 num_frame_sizes += 1;
5457 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5460 while (regno1 <= regno2)
5462 if (regno1 >= 4 && regno1 <= 7)
5464 if (num_frame_sizes == 0)
5466 args |= 1 << (regno1 - 4);
5468 /* statics $a0-$a3 */
5469 statics |= 1 << (regno1 - 4);
5471 else if (regno1 >= 16 && regno1 <= 23)
5473 sregs |= 1 << (regno1 - 16);
5474 else if (regno1 == 30)
5477 else if (regno1 == 31)
5478 /* Add $ra to insn. */
5488 while (match_char (arg, ','));
5490 /* Encode args/statics combination. */
5493 else if (args == 0xf)
5494 /* All $a0-$a3 are args. */
5495 opcode |= MIPS16_ALL_ARGS << 16;
5496 else if (statics == 0xf)
5497 /* All $a0-$a3 are statics. */
5498 opcode |= MIPS16_ALL_STATICS << 16;
5501 /* Count arg registers. */
5511 /* Count static registers. */
5513 while (statics & 0x8)
5515 statics = (statics << 1) & 0xf;
5521 /* Encode args/statics. */
5522 opcode |= ((num_args << 2) | num_statics) << 16;
5525 /* Encode $s0/$s1. */
5526 if (sregs & (1 << 0)) /* $s0 */
5528 if (sregs & (1 << 1)) /* $s1 */
5532 /* Encode $s2-$s8. */
5541 opcode |= num_sregs << 24;
5543 /* Encode frame size. */
5544 if (num_frame_sizes == 0)
5546 set_insn_error (arg->argnum, _("missing frame size"));
5549 if (num_frame_sizes > 1)
5551 set_insn_error (arg->argnum, _("frame size specified twice"));
5554 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5556 set_insn_error (arg->argnum, _("invalid frame size"));
5559 if (frame_size != 128 || (opcode >> 16) != 0)
5562 opcode |= (((frame_size & 0xf0) << 16)
5563 | (frame_size & 0x0f));
5566 /* Finally build the instruction. */
5567 if ((opcode >> 16) != 0 || frame_size == 0)
5568 opcode |= MIPS16_EXTEND;
5569 arg->insn->insn_opcode = opcode;
5573 /* OP_MDMX_IMM_REG matcher. */
5576 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5577 const struct mips_operand *operand)
5579 unsigned int regno, uval;
5581 const struct mips_opcode *opcode;
5583 /* The mips_opcode records whether this is an octobyte or quadhalf
5584 instruction. Start out with that bit in place. */
5585 opcode = arg->insn->insn_mo;
5586 uval = mips_extract_operand (operand, opcode->match);
5587 is_qh = (uval != 0);
5589 if (arg->token->type == OT_REG)
5591 if ((opcode->membership & INSN_5400)
5592 && strcmp (opcode->name, "rzu.ob") == 0)
5594 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5599 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5603 /* Check whether this is a vector register or a broadcast of
5604 a single element. */
5605 if (arg->token->type == OT_INTEGER_INDEX)
5607 if (arg->token->u.index > (is_qh ? 3 : 7))
5609 set_insn_error (arg->argnum, _("invalid element selector"));
5612 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5617 /* A full vector. */
5618 if ((opcode->membership & INSN_5400)
5619 && (strcmp (opcode->name, "sll.ob") == 0
5620 || strcmp (opcode->name, "srl.ob") == 0))
5622 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5628 uval |= MDMX_FMTSEL_VEC_QH << 5;
5630 uval |= MDMX_FMTSEL_VEC_OB << 5;
5638 if (!match_const_int (arg, &sval))
5640 if (sval < 0 || sval > 31)
5642 match_out_of_range (arg);
5645 uval |= (sval & 31);
5647 uval |= MDMX_FMTSEL_IMM_QH << 5;
5649 uval |= MDMX_FMTSEL_IMM_OB << 5;
5651 insn_insert_operand (arg->insn, operand, uval);
5655 /* OP_IMM_INDEX matcher. */
5658 match_imm_index_operand (struct mips_arg_info *arg,
5659 const struct mips_operand *operand)
5661 unsigned int max_val;
5663 if (arg->token->type != OT_INTEGER_INDEX)
5666 max_val = (1 << operand->size) - 1;
5667 if (arg->token->u.index > max_val)
5669 match_out_of_range (arg);
5672 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5677 /* OP_REG_INDEX matcher. */
5680 match_reg_index_operand (struct mips_arg_info *arg,
5681 const struct mips_operand *operand)
5685 if (arg->token->type != OT_REG_INDEX)
5688 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5691 insn_insert_operand (arg->insn, operand, regno);
5696 /* OP_PC matcher. */
5699 match_pc_operand (struct mips_arg_info *arg)
5701 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5709 /* OP_NON_ZERO_REG matcher. */
5712 match_non_zero_reg_operand (struct mips_arg_info *arg,
5713 const struct mips_operand *operand)
5717 if (!match_reg (arg, OP_REG_GP, ®no))
5723 arg->last_regno = regno;
5724 insn_insert_operand (arg->insn, operand, regno);
5728 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5729 register that we need to match. */
5732 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5736 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5739 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5740 the length of the value in bytes (4 for float, 8 for double) and
5741 USING_GPRS says whether the destination is a GPR rather than an FPR.
5743 Return the constant in IMM and OFFSET as follows:
5745 - If the constant should be loaded via memory, set IMM to O_absent and
5746 OFFSET to the memory address.
5748 - Otherwise, if the constant should be loaded into two 32-bit registers,
5749 set IMM to the O_constant to load into the high register and OFFSET
5750 to the corresponding value for the low register.
5752 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5754 These constants only appear as the last operand in an instruction,
5755 and every instruction that accepts them in any variant accepts them
5756 in all variants. This means we don't have to worry about backing out
5757 any changes if the instruction does not match. We just match
5758 unconditionally and report an error if the constant is invalid. */
5761 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5762 expressionS *offset, int length, bfd_boolean using_gprs)
5767 const char *newname;
5768 unsigned char *data;
5770 /* Where the constant is placed is based on how the MIPS assembler
5773 length == 4 && using_gprs -- immediate value only
5774 length == 8 && using_gprs -- .rdata or immediate value
5775 length == 4 && !using_gprs -- .lit4 or immediate value
5776 length == 8 && !using_gprs -- .lit8 or immediate value
5778 The .lit4 and .lit8 sections are only used if permitted by the
5780 if (arg->token->type != OT_FLOAT)
5782 set_insn_error (arg->argnum, _("floating-point expression required"));
5786 gas_assert (arg->token->u.flt.length == length);
5787 data = arg->token->u.flt.data;
5790 /* Handle 32-bit constants for which an immediate value is best. */
5793 || g_switch_value < 4
5794 || (data[0] == 0 && data[1] == 0)
5795 || (data[2] == 0 && data[3] == 0)))
5797 imm->X_op = O_constant;
5798 if (!target_big_endian)
5799 imm->X_add_number = bfd_getl32 (data);
5801 imm->X_add_number = bfd_getb32 (data);
5802 offset->X_op = O_absent;
5806 /* Handle 64-bit constants for which an immediate value is best. */
5808 && !mips_disable_float_construction
5809 /* Constants can only be constructed in GPRs and copied to FPRs if the
5810 GPRs are at least as wide as the FPRs or MTHC1 is available.
5811 Unlike most tests for 32-bit floating-point registers this check
5812 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5813 permit 64-bit moves without MXHC1.
5814 Force the constant into memory otherwise. */
5817 || ISA_HAS_MXHC1 (mips_opts.isa)
5819 && ((data[0] == 0 && data[1] == 0)
5820 || (data[2] == 0 && data[3] == 0))
5821 && ((data[4] == 0 && data[5] == 0)
5822 || (data[6] == 0 && data[7] == 0)))
5824 /* The value is simple enough to load with a couple of instructions.
5825 If using 32-bit registers, set IMM to the high order 32 bits and
5826 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5828 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5830 imm->X_op = O_constant;
5831 offset->X_op = O_constant;
5832 if (!target_big_endian)
5834 imm->X_add_number = bfd_getl32 (data + 4);
5835 offset->X_add_number = bfd_getl32 (data);
5839 imm->X_add_number = bfd_getb32 (data);
5840 offset->X_add_number = bfd_getb32 (data + 4);
5842 if (offset->X_add_number == 0)
5843 offset->X_op = O_absent;
5847 imm->X_op = O_constant;
5848 if (!target_big_endian)
5849 imm->X_add_number = bfd_getl64 (data);
5851 imm->X_add_number = bfd_getb64 (data);
5852 offset->X_op = O_absent;
5857 /* Switch to the right section. */
5859 subseg = now_subseg;
5862 gas_assert (!using_gprs && g_switch_value >= 4);
5867 if (using_gprs || g_switch_value < 8)
5868 newname = RDATA_SECTION_NAME;
5873 new_seg = subseg_new (newname, (subsegT) 0);
5874 bfd_set_section_flags (stdoutput, new_seg,
5875 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5876 frag_align (length == 4 ? 2 : 3, 0, 0);
5877 if (strncmp (TARGET_OS, "elf", 3) != 0)
5878 record_alignment (new_seg, 4);
5880 record_alignment (new_seg, length == 4 ? 2 : 3);
5882 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5884 /* Set the argument to the current address in the section. */
5885 imm->X_op = O_absent;
5886 offset->X_op = O_symbol;
5887 offset->X_add_symbol = symbol_temp_new_now ();
5888 offset->X_add_number = 0;
5890 /* Put the floating point number into the section. */
5891 p = frag_more (length);
5892 memcpy (p, data, length);
5894 /* Switch back to the original section. */
5895 subseg_set (seg, subseg);
5899 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5903 match_vu0_suffix_operand (struct mips_arg_info *arg,
5904 const struct mips_operand *operand,
5905 bfd_boolean match_p)
5909 /* The operand can be an XYZW mask or a single 2-bit channel index
5910 (with X being 0). */
5911 gas_assert (operand->size == 2 || operand->size == 4);
5913 /* The suffix can be omitted when it is already part of the opcode. */
5914 if (arg->token->type != OT_CHANNELS)
5917 uval = arg->token->u.channels;
5918 if (operand->size == 2)
5920 /* Check that a single bit is set and convert it into a 2-bit index. */
5921 if ((uval & -uval) != uval)
5923 uval = 4 - ffs (uval);
5926 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5931 insn_insert_operand (arg->insn, operand, uval);
5935 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5936 of the argument text if the match is successful, otherwise return null. */
5939 match_operand (struct mips_arg_info *arg,
5940 const struct mips_operand *operand)
5942 switch (operand->type)
5945 return match_int_operand (arg, operand);
5948 return match_mapped_int_operand (arg, operand);
5951 return match_msb_operand (arg, operand);
5954 case OP_OPTIONAL_REG:
5955 return match_reg_operand (arg, operand);
5958 return match_reg_pair_operand (arg, operand);
5961 return match_pcrel_operand (arg);
5964 return match_perf_reg_operand (arg, operand);
5966 case OP_ADDIUSP_INT:
5967 return match_addiusp_operand (arg, operand);
5969 case OP_CLO_CLZ_DEST:
5970 return match_clo_clz_dest_operand (arg, operand);
5972 case OP_LWM_SWM_LIST:
5973 return match_lwm_swm_list_operand (arg, operand);
5975 case OP_ENTRY_EXIT_LIST:
5976 return match_entry_exit_operand (arg, operand);
5978 case OP_SAVE_RESTORE_LIST:
5979 return match_save_restore_list_operand (arg);
5981 case OP_MDMX_IMM_REG:
5982 return match_mdmx_imm_reg_operand (arg, operand);
5984 case OP_REPEAT_DEST_REG:
5985 return match_tied_reg_operand (arg, arg->dest_regno);
5987 case OP_REPEAT_PREV_REG:
5988 return match_tied_reg_operand (arg, arg->last_regno);
5991 return match_pc_operand (arg);
5994 return match_vu0_suffix_operand (arg, operand, FALSE);
5996 case OP_VU0_MATCH_SUFFIX:
5997 return match_vu0_suffix_operand (arg, operand, TRUE);
6000 return match_imm_index_operand (arg, operand);
6003 return match_reg_index_operand (arg, operand);
6006 return match_same_rs_rt_operand (arg, operand);
6009 return match_check_prev_operand (arg, operand);
6011 case OP_NON_ZERO_REG:
6012 return match_non_zero_reg_operand (arg, operand);
6017 /* ARG is the state after successfully matching an instruction.
6018 Issue any queued-up warnings. */
6021 check_completed_insn (struct mips_arg_info *arg)
6026 as_warn (_("used $at without \".set noat\""));
6028 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6032 /* Return true if modifying general-purpose register REG needs a delay. */
6035 reg_needs_delay (unsigned int reg)
6037 unsigned long prev_pinfo;
6039 prev_pinfo = history[0].insn_mo->pinfo;
6040 if (!mips_opts.noreorder
6041 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6042 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6043 && (gpr_write_mask (&history[0]) & (1 << reg)))
6049 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6050 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6051 by VR4120 errata. */
6054 classify_vr4120_insn (const char *name)
6056 if (strncmp (name, "macc", 4) == 0)
6057 return FIX_VR4120_MACC;
6058 if (strncmp (name, "dmacc", 5) == 0)
6059 return FIX_VR4120_DMACC;
6060 if (strncmp (name, "mult", 4) == 0)
6061 return FIX_VR4120_MULT;
6062 if (strncmp (name, "dmult", 5) == 0)
6063 return FIX_VR4120_DMULT;
6064 if (strstr (name, "div"))
6065 return FIX_VR4120_DIV;
6066 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6067 return FIX_VR4120_MTHILO;
6068 return NUM_FIX_VR4120_CLASSES;
6071 #define INSN_ERET 0x42000018
6072 #define INSN_DERET 0x4200001f
6073 #define INSN_DMULT 0x1c
6074 #define INSN_DMULTU 0x1d
6076 /* Return the number of instructions that must separate INSN1 and INSN2,
6077 where INSN1 is the earlier instruction. Return the worst-case value
6078 for any INSN2 if INSN2 is null. */
6081 insns_between (const struct mips_cl_insn *insn1,
6082 const struct mips_cl_insn *insn2)
6084 unsigned long pinfo1, pinfo2;
6087 /* If INFO2 is null, pessimistically assume that all flags are set for
6088 the second instruction. */
6089 pinfo1 = insn1->insn_mo->pinfo;
6090 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6092 /* For most targets, write-after-read dependencies on the HI and LO
6093 registers must be separated by at least two instructions. */
6094 if (!hilo_interlocks)
6096 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6098 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6102 /* If we're working around r7000 errata, there must be two instructions
6103 between an mfhi or mflo and any instruction that uses the result. */
6104 if (mips_7000_hilo_fix
6105 && !mips_opts.micromips
6106 && MF_HILO_INSN (pinfo1)
6107 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6110 /* If we're working around 24K errata, one instruction is required
6111 if an ERET or DERET is followed by a branch instruction. */
6112 if (mips_fix_24k && !mips_opts.micromips)
6114 if (insn1->insn_opcode == INSN_ERET
6115 || insn1->insn_opcode == INSN_DERET)
6118 || insn2->insn_opcode == INSN_ERET
6119 || insn2->insn_opcode == INSN_DERET
6120 || delayed_branch_p (insn2))
6125 /* If we're working around PMC RM7000 errata, there must be three
6126 nops between a dmult and a load instruction. */
6127 if (mips_fix_rm7000 && !mips_opts.micromips)
6129 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6130 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6132 if (pinfo2 & INSN_LOAD_MEMORY)
6137 /* If working around VR4120 errata, check for combinations that need
6138 a single intervening instruction. */
6139 if (mips_fix_vr4120 && !mips_opts.micromips)
6141 unsigned int class1, class2;
6143 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6144 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6148 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6149 if (vr4120_conflicts[class1] & (1 << class2))
6154 if (!HAVE_CODE_COMPRESSION)
6156 /* Check for GPR or coprocessor load delays. All such delays
6157 are on the RT register. */
6158 /* Itbl support may require additional care here. */
6159 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6160 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6162 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6166 /* Check for generic coprocessor hazards.
6168 This case is not handled very well. There is no special
6169 knowledge of CP0 handling, and the coprocessors other than
6170 the floating point unit are not distinguished at all. */
6171 /* Itbl support may require additional care here. FIXME!
6172 Need to modify this to include knowledge about
6173 user specified delays! */
6174 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6175 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6177 /* Handle cases where INSN1 writes to a known general coprocessor
6178 register. There must be a one instruction delay before INSN2
6179 if INSN2 reads that register, otherwise no delay is needed. */
6180 mask = fpr_write_mask (insn1);
6183 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6188 /* Read-after-write dependencies on the control registers
6189 require a two-instruction gap. */
6190 if ((pinfo1 & INSN_WRITE_COND_CODE)
6191 && (pinfo2 & INSN_READ_COND_CODE))
6194 /* We don't know exactly what INSN1 does. If INSN2 is
6195 also a coprocessor instruction, assume there must be
6196 a one instruction gap. */
6197 if (pinfo2 & INSN_COP)
6202 /* Check for read-after-write dependencies on the coprocessor
6203 control registers in cases where INSN1 does not need a general
6204 coprocessor delay. This means that INSN1 is a floating point
6205 comparison instruction. */
6206 /* Itbl support may require additional care here. */
6207 else if (!cop_interlocks
6208 && (pinfo1 & INSN_WRITE_COND_CODE)
6209 && (pinfo2 & INSN_READ_COND_CODE))
6213 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6214 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6216 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6217 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6218 || (insn2 && delayed_branch_p (insn2))))
6224 /* Return the number of nops that would be needed to work around the
6225 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6226 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6227 that are contained within the first IGNORE instructions of HIST. */
6230 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6231 const struct mips_cl_insn *insn)
6236 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6237 are not affected by the errata. */
6239 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6240 || strcmp (insn->insn_mo->name, "mtlo") == 0
6241 || strcmp (insn->insn_mo->name, "mthi") == 0))
6244 /* Search for the first MFLO or MFHI. */
6245 for (i = 0; i < MAX_VR4130_NOPS; i++)
6246 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6248 /* Extract the destination register. */
6249 mask = gpr_write_mask (&hist[i]);
6251 /* No nops are needed if INSN reads that register. */
6252 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6255 /* ...or if any of the intervening instructions do. */
6256 for (j = 0; j < i; j++)
6257 if (gpr_read_mask (&hist[j]) & mask)
6261 return MAX_VR4130_NOPS - i;
6266 #define BASE_REG_EQ(INSN1, INSN2) \
6267 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6268 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6270 /* Return the minimum alignment for this store instruction. */
6273 fix_24k_align_to (const struct mips_opcode *mo)
6275 if (strcmp (mo->name, "sh") == 0)
6278 if (strcmp (mo->name, "swc1") == 0
6279 || strcmp (mo->name, "swc2") == 0
6280 || strcmp (mo->name, "sw") == 0
6281 || strcmp (mo->name, "sc") == 0
6282 || strcmp (mo->name, "s.s") == 0)
6285 if (strcmp (mo->name, "sdc1") == 0
6286 || strcmp (mo->name, "sdc2") == 0
6287 || strcmp (mo->name, "s.d") == 0)
6294 struct fix_24k_store_info
6296 /* Immediate offset, if any, for this store instruction. */
6298 /* Alignment required by this store instruction. */
6300 /* True for register offsets. */
6301 int register_offset;
6304 /* Comparison function used by qsort. */
6307 fix_24k_sort (const void *a, const void *b)
6309 const struct fix_24k_store_info *pos1 = a;
6310 const struct fix_24k_store_info *pos2 = b;
6312 return (pos1->off - pos2->off);
6315 /* INSN is a store instruction. Try to record the store information
6316 in STINFO. Return false if the information isn't known. */
6319 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6320 const struct mips_cl_insn *insn)
6322 /* The instruction must have a known offset. */
6323 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6326 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6327 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6331 /* Return the number of nops that would be needed to work around the 24k
6332 "lost data on stores during refill" errata if instruction INSN
6333 immediately followed the 2 instructions described by HIST.
6334 Ignore hazards that are contained within the first IGNORE
6335 instructions of HIST.
6337 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6338 for the data cache refills and store data. The following describes
6339 the scenario where the store data could be lost.
6341 * A data cache miss, due to either a load or a store, causing fill
6342 data to be supplied by the memory subsystem
6343 * The first three doublewords of fill data are returned and written
6345 * A sequence of four stores occurs in consecutive cycles around the
6346 final doubleword of the fill:
6350 * Zero, One or more instructions
6353 The four stores A-D must be to different doublewords of the line that
6354 is being filled. The fourth instruction in the sequence above permits
6355 the fill of the final doubleword to be transferred from the FSB into
6356 the cache. In the sequence above, the stores may be either integer
6357 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6358 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6359 different doublewords on the line. If the floating point unit is
6360 running in 1:2 mode, it is not possible to create the sequence above
6361 using only floating point store instructions.
6363 In this case, the cache line being filled is incorrectly marked
6364 invalid, thereby losing the data from any store to the line that
6365 occurs between the original miss and the completion of the five
6366 cycle sequence shown above.
6368 The workarounds are:
6370 * Run the data cache in write-through mode.
6371 * Insert a non-store instruction between
6372 Store A and Store B or Store B and Store C. */
6375 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6376 const struct mips_cl_insn *insn)
6378 struct fix_24k_store_info pos[3];
6379 int align, i, base_offset;
6384 /* If the previous instruction wasn't a store, there's nothing to
6386 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6389 /* If the instructions after the previous one are unknown, we have
6390 to assume the worst. */
6394 /* Check whether we are dealing with three consecutive stores. */
6395 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6396 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6399 /* If we don't know the relationship between the store addresses,
6400 assume the worst. */
6401 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6402 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6405 if (!fix_24k_record_store_info (&pos[0], insn)
6406 || !fix_24k_record_store_info (&pos[1], &hist[0])
6407 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6410 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6412 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6413 X bytes and such that the base register + X is known to be aligned
6416 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6420 align = pos[0].align_to;
6421 base_offset = pos[0].off;
6422 for (i = 1; i < 3; i++)
6423 if (align < pos[i].align_to)
6425 align = pos[i].align_to;
6426 base_offset = pos[i].off;
6428 for (i = 0; i < 3; i++)
6429 pos[i].off -= base_offset;
6432 pos[0].off &= ~align + 1;
6433 pos[1].off &= ~align + 1;
6434 pos[2].off &= ~align + 1;
6436 /* If any two stores write to the same chunk, they also write to the
6437 same doubleword. The offsets are still sorted at this point. */
6438 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6441 /* A range of at least 9 bytes is needed for the stores to be in
6442 non-overlapping doublewords. */
6443 if (pos[2].off - pos[0].off <= 8)
6446 if (pos[2].off - pos[1].off >= 24
6447 || pos[1].off - pos[0].off >= 24
6448 || pos[2].off - pos[0].off >= 32)
6454 /* Return the number of nops that would be needed if instruction INSN
6455 immediately followed the MAX_NOPS instructions given by HIST,
6456 where HIST[0] is the most recent instruction. Ignore hazards
6457 between INSN and the first IGNORE instructions in HIST.
6459 If INSN is null, return the worse-case number of nops for any
6463 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6464 const struct mips_cl_insn *insn)
6466 int i, nops, tmp_nops;
6469 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6471 tmp_nops = insns_between (hist + i, insn) - i;
6472 if (tmp_nops > nops)
6476 if (mips_fix_vr4130 && !mips_opts.micromips)
6478 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6479 if (tmp_nops > nops)
6483 if (mips_fix_24k && !mips_opts.micromips)
6485 tmp_nops = nops_for_24k (ignore, hist, insn);
6486 if (tmp_nops > nops)
6493 /* The variable arguments provide NUM_INSNS extra instructions that
6494 might be added to HIST. Return the largest number of nops that
6495 would be needed after the extended sequence, ignoring hazards
6496 in the first IGNORE instructions. */
6499 nops_for_sequence (int num_insns, int ignore,
6500 const struct mips_cl_insn *hist, ...)
6503 struct mips_cl_insn buffer[MAX_NOPS];
6504 struct mips_cl_insn *cursor;
6507 va_start (args, hist);
6508 cursor = buffer + num_insns;
6509 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6510 while (cursor > buffer)
6511 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6513 nops = nops_for_insn (ignore, buffer, NULL);
6518 /* Like nops_for_insn, but if INSN is a branch, take into account the
6519 worst-case delay for the branch target. */
6522 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6523 const struct mips_cl_insn *insn)
6527 nops = nops_for_insn (ignore, hist, insn);
6528 if (delayed_branch_p (insn))
6530 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6531 hist, insn, get_delay_slot_nop (insn));
6532 if (tmp_nops > nops)
6535 else if (compact_branch_p (insn))
6537 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6538 if (tmp_nops > nops)
6544 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6547 fix_loongson2f_nop (struct mips_cl_insn * ip)
6549 gas_assert (!HAVE_CODE_COMPRESSION);
6550 if (strcmp (ip->insn_mo->name, "nop") == 0)
6551 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6554 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6555 jr target pc &= 'hffff_ffff_cfff_ffff. */
6558 fix_loongson2f_jump (struct mips_cl_insn * ip)
6560 gas_assert (!HAVE_CODE_COMPRESSION);
6561 if (strcmp (ip->insn_mo->name, "j") == 0
6562 || strcmp (ip->insn_mo->name, "jr") == 0
6563 || strcmp (ip->insn_mo->name, "jalr") == 0)
6571 sreg = EXTRACT_OPERAND (0, RS, *ip);
6572 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6575 ep.X_op = O_constant;
6576 ep.X_add_number = 0xcfff0000;
6577 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6578 ep.X_add_number = 0xffff;
6579 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6580 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6585 fix_loongson2f (struct mips_cl_insn * ip)
6587 if (mips_fix_loongson2f_nop)
6588 fix_loongson2f_nop (ip);
6590 if (mips_fix_loongson2f_jump)
6591 fix_loongson2f_jump (ip);
6594 /* IP is a branch that has a delay slot, and we need to fill it
6595 automatically. Return true if we can do that by swapping IP
6596 with the previous instruction.
6597 ADDRESS_EXPR is an operand of the instruction to be used with
6601 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6602 bfd_reloc_code_real_type *reloc_type)
6604 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6605 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6606 unsigned int fpr_read, prev_fpr_write;
6608 /* -O2 and above is required for this optimization. */
6609 if (mips_optimize < 2)
6612 /* If we have seen .set volatile or .set nomove, don't optimize. */
6613 if (mips_opts.nomove)
6616 /* We can't swap if the previous instruction's position is fixed. */
6617 if (history[0].fixed_p)
6620 /* If the previous previous insn was in a .set noreorder, we can't
6621 swap. Actually, the MIPS assembler will swap in this situation.
6622 However, gcc configured -with-gnu-as will generate code like
6630 in which we can not swap the bne and INSN. If gcc is not configured
6631 -with-gnu-as, it does not output the .set pseudo-ops. */
6632 if (history[1].noreorder_p)
6635 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6636 This means that the previous instruction was a 4-byte one anyhow. */
6637 if (mips_opts.mips16 && history[0].fixp[0])
6640 /* If the branch is itself the target of a branch, we can not swap.
6641 We cheat on this; all we check for is whether there is a label on
6642 this instruction. If there are any branches to anything other than
6643 a label, users must use .set noreorder. */
6644 if (seg_info (now_seg)->label_list)
6647 /* If the previous instruction is in a variant frag other than this
6648 branch's one, we cannot do the swap. This does not apply to
6649 MIPS16 code, which uses variant frags for different purposes. */
6650 if (!mips_opts.mips16
6652 && history[0].frag->fr_type == rs_machine_dependent)
6655 /* We do not swap with instructions that cannot architecturally
6656 be placed in a branch delay slot, such as SYNC or ERET. We
6657 also refrain from swapping with a trap instruction, since it
6658 complicates trap handlers to have the trap instruction be in
6660 prev_pinfo = history[0].insn_mo->pinfo;
6661 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6664 /* Check for conflicts between the branch and the instructions
6665 before the candidate delay slot. */
6666 if (nops_for_insn (0, history + 1, ip) > 0)
6669 /* Check for conflicts between the swapped sequence and the
6670 target of the branch. */
6671 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6674 /* If the branch reads a register that the previous
6675 instruction sets, we can not swap. */
6676 gpr_read = gpr_read_mask (ip);
6677 prev_gpr_write = gpr_write_mask (&history[0]);
6678 if (gpr_read & prev_gpr_write)
6681 fpr_read = fpr_read_mask (ip);
6682 prev_fpr_write = fpr_write_mask (&history[0]);
6683 if (fpr_read & prev_fpr_write)
6686 /* If the branch writes a register that the previous
6687 instruction sets, we can not swap. */
6688 gpr_write = gpr_write_mask (ip);
6689 if (gpr_write & prev_gpr_write)
6692 /* If the branch writes a register that the previous
6693 instruction reads, we can not swap. */
6694 prev_gpr_read = gpr_read_mask (&history[0]);
6695 if (gpr_write & prev_gpr_read)
6698 /* If one instruction sets a condition code and the
6699 other one uses a condition code, we can not swap. */
6700 pinfo = ip->insn_mo->pinfo;
6701 if ((pinfo & INSN_READ_COND_CODE)
6702 && (prev_pinfo & INSN_WRITE_COND_CODE))
6704 if ((pinfo & INSN_WRITE_COND_CODE)
6705 && (prev_pinfo & INSN_READ_COND_CODE))
6708 /* If the previous instruction uses the PC, we can not swap. */
6709 prev_pinfo2 = history[0].insn_mo->pinfo2;
6710 if (prev_pinfo2 & INSN2_READ_PC)
6713 /* If the previous instruction has an incorrect size for a fixed
6714 branch delay slot in microMIPS mode, we cannot swap. */
6715 pinfo2 = ip->insn_mo->pinfo2;
6716 if (mips_opts.micromips
6717 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6718 && insn_length (history) != 2)
6720 if (mips_opts.micromips
6721 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6722 && insn_length (history) != 4)
6725 /* On R5900 short loops need to be fixed by inserting a nop in
6726 the branch delay slots.
6727 A short loop can be terminated too early. */
6728 if (mips_opts.arch == CPU_R5900
6729 /* Check if instruction has a parameter, ignore "j $31". */
6730 && (address_expr != NULL)
6731 /* Parameter must be 16 bit. */
6732 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6733 /* Branch to same segment. */
6734 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6735 /* Branch to same code fragment. */
6736 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6737 /* Can only calculate branch offset if value is known. */
6738 && symbol_constant_p(address_expr->X_add_symbol)
6739 /* Check if branch is really conditional. */
6740 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6741 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6742 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6745 /* Check if loop is shorter than 6 instructions including
6746 branch and delay slot. */
6747 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6754 /* When the loop includes branches or jumps,
6755 it is not a short loop. */
6756 for (i = 0; i < (distance / 4); i++)
6758 if ((history[i].cleared_p)
6759 || delayed_branch_p(&history[i]))
6767 /* Insert nop after branch to fix short loop. */
6776 /* Decide how we should add IP to the instruction stream.
6777 ADDRESS_EXPR is an operand of the instruction to be used with
6780 static enum append_method
6781 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6782 bfd_reloc_code_real_type *reloc_type)
6784 /* The relaxed version of a macro sequence must be inherently
6786 if (mips_relax.sequence == 2)
6789 /* We must not dabble with instructions in a ".set norerorder" block. */
6790 if (mips_opts.noreorder)
6793 /* Otherwise, it's our responsibility to fill branch delay slots. */
6794 if (delayed_branch_p (ip))
6796 if (!branch_likely_p (ip)
6797 && can_swap_branch_p (ip, address_expr, reloc_type))
6800 if (mips_opts.mips16
6801 && ISA_SUPPORTS_MIPS16E
6802 && gpr_read_mask (ip) != 0)
6803 return APPEND_ADD_COMPACT;
6805 return APPEND_ADD_WITH_NOP;
6811 /* IP is a MIPS16 instruction whose opcode we have just changed.
6812 Point IP->insn_mo to the new opcode's definition. */
6815 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6817 const struct mips_opcode *mo, *end;
6819 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6820 for (mo = ip->insn_mo; mo < end; mo++)
6821 if ((ip->insn_opcode & mo->mask) == mo->match)
6829 /* For microMIPS macros, we need to generate a local number label
6830 as the target of branches. */
6831 #define MICROMIPS_LABEL_CHAR '\037'
6832 static unsigned long micromips_target_label;
6833 static char micromips_target_name[32];
6836 micromips_label_name (void)
6838 char *p = micromips_target_name;
6839 char symbol_name_temporary[24];
6847 l = micromips_target_label;
6848 #ifdef LOCAL_LABEL_PREFIX
6849 *p++ = LOCAL_LABEL_PREFIX;
6852 *p++ = MICROMIPS_LABEL_CHAR;
6855 symbol_name_temporary[i++] = l % 10 + '0';
6860 *p++ = symbol_name_temporary[--i];
6863 return micromips_target_name;
6867 micromips_label_expr (expressionS *label_expr)
6869 label_expr->X_op = O_symbol;
6870 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6871 label_expr->X_add_number = 0;
6875 micromips_label_inc (void)
6877 micromips_target_label++;
6878 *micromips_target_name = '\0';
6882 micromips_add_label (void)
6886 s = colon (micromips_label_name ());
6887 micromips_label_inc ();
6888 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6891 /* If assembling microMIPS code, then return the microMIPS reloc
6892 corresponding to the requested one if any. Otherwise return
6893 the reloc unchanged. */
6895 static bfd_reloc_code_real_type
6896 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6898 static const bfd_reloc_code_real_type relocs[][2] =
6900 /* Keep sorted incrementally by the left-hand key. */
6901 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6902 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6903 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6904 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6905 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6906 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6907 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6908 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6909 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6910 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6911 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6912 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6913 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6914 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6915 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6916 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6917 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6918 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6919 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6920 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6921 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6922 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6923 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6924 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6925 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6926 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6927 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6929 bfd_reloc_code_real_type r;
6932 if (!mips_opts.micromips)
6934 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6940 return relocs[i][1];
6945 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6946 Return true on success, storing the resolved value in RESULT. */
6949 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6954 case BFD_RELOC_MIPS_HIGHEST:
6955 case BFD_RELOC_MICROMIPS_HIGHEST:
6956 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6959 case BFD_RELOC_MIPS_HIGHER:
6960 case BFD_RELOC_MICROMIPS_HIGHER:
6961 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6964 case BFD_RELOC_HI16_S:
6965 case BFD_RELOC_MICROMIPS_HI16_S:
6966 case BFD_RELOC_MIPS16_HI16_S:
6967 *result = ((operand + 0x8000) >> 16) & 0xffff;
6970 case BFD_RELOC_HI16:
6971 case BFD_RELOC_MICROMIPS_HI16:
6972 case BFD_RELOC_MIPS16_HI16:
6973 *result = (operand >> 16) & 0xffff;
6976 case BFD_RELOC_LO16:
6977 case BFD_RELOC_MICROMIPS_LO16:
6978 case BFD_RELOC_MIPS16_LO16:
6979 *result = operand & 0xffff;
6982 case BFD_RELOC_UNUSED:
6991 /* Output an instruction. IP is the instruction information.
6992 ADDRESS_EXPR is an operand of the instruction to be used with
6993 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6994 a macro expansion. */
6997 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6998 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7000 unsigned long prev_pinfo2, pinfo;
7001 bfd_boolean relaxed_branch = FALSE;
7002 enum append_method method;
7003 bfd_boolean relax32;
7006 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7007 fix_loongson2f (ip);
7009 file_ase_mips16 |= mips_opts.mips16;
7010 file_ase_micromips |= mips_opts.micromips;
7012 prev_pinfo2 = history[0].insn_mo->pinfo2;
7013 pinfo = ip->insn_mo->pinfo;
7015 if (mips_opts.micromips
7017 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7018 && micromips_insn_length (ip->insn_mo) != 2)
7019 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7020 && micromips_insn_length (ip->insn_mo) != 4)))
7021 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7022 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7024 if (address_expr == NULL)
7026 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7027 && reloc_type[1] == BFD_RELOC_UNUSED
7028 && reloc_type[2] == BFD_RELOC_UNUSED
7029 && address_expr->X_op == O_constant)
7031 switch (*reloc_type)
7033 case BFD_RELOC_MIPS_JMP:
7037 shift = mips_opts.micromips ? 1 : 2;
7038 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7039 as_bad (_("jump to misaligned address (0x%lx)"),
7040 (unsigned long) address_expr->X_add_number);
7041 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7047 case BFD_RELOC_MIPS16_JMP:
7048 if ((address_expr->X_add_number & 3) != 0)
7049 as_bad (_("jump to misaligned address (0x%lx)"),
7050 (unsigned long) address_expr->X_add_number);
7052 (((address_expr->X_add_number & 0x7c0000) << 3)
7053 | ((address_expr->X_add_number & 0xf800000) >> 7)
7054 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7058 case BFD_RELOC_16_PCREL_S2:
7062 shift = mips_opts.micromips ? 1 : 2;
7063 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7064 as_bad (_("branch to misaligned address (0x%lx)"),
7065 (unsigned long) address_expr->X_add_number);
7066 if (!mips_relax_branch)
7068 if ((address_expr->X_add_number + (1 << (shift + 15)))
7069 & ~((1 << (shift + 16)) - 1))
7070 as_bad (_("branch address range overflow (0x%lx)"),
7071 (unsigned long) address_expr->X_add_number);
7072 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7078 case BFD_RELOC_MIPS_21_PCREL_S2:
7083 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7084 as_bad (_("branch to misaligned address (0x%lx)"),
7085 (unsigned long) address_expr->X_add_number);
7086 if ((address_expr->X_add_number + (1 << (shift + 20)))
7087 & ~((1 << (shift + 21)) - 1))
7088 as_bad (_("branch address range overflow (0x%lx)"),
7089 (unsigned long) address_expr->X_add_number);
7090 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7095 case BFD_RELOC_MIPS_26_PCREL_S2:
7100 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7101 as_bad (_("branch to misaligned address (0x%lx)"),
7102 (unsigned long) address_expr->X_add_number);
7103 if ((address_expr->X_add_number + (1 << (shift + 25)))
7104 & ~((1 << (shift + 26)) - 1))
7105 as_bad (_("branch address range overflow (0x%lx)"),
7106 (unsigned long) address_expr->X_add_number);
7107 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7116 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7119 ip->insn_opcode |= value & 0xffff;
7127 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7129 /* There are a lot of optimizations we could do that we don't.
7130 In particular, we do not, in general, reorder instructions.
7131 If you use gcc with optimization, it will reorder
7132 instructions and generally do much more optimization then we
7133 do here; repeating all that work in the assembler would only
7134 benefit hand written assembly code, and does not seem worth
7136 int nops = (mips_optimize == 0
7137 ? nops_for_insn (0, history, NULL)
7138 : nops_for_insn_or_target (0, history, ip));
7142 unsigned long old_frag_offset;
7145 old_frag = frag_now;
7146 old_frag_offset = frag_now_fix ();
7148 for (i = 0; i < nops; i++)
7149 add_fixed_insn (NOP_INSN);
7150 insert_into_history (0, nops, NOP_INSN);
7154 listing_prev_line ();
7155 /* We may be at the start of a variant frag. In case we
7156 are, make sure there is enough space for the frag
7157 after the frags created by listing_prev_line. The
7158 argument to frag_grow here must be at least as large
7159 as the argument to all other calls to frag_grow in
7160 this file. We don't have to worry about being in the
7161 middle of a variant frag, because the variants insert
7162 all needed nop instructions themselves. */
7166 mips_move_text_labels ();
7168 #ifndef NO_ECOFF_DEBUGGING
7169 if (ECOFF_DEBUGGING)
7170 ecoff_fix_loc (old_frag, old_frag_offset);
7174 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7178 /* Work out how many nops in prev_nop_frag are needed by IP,
7179 ignoring hazards generated by the first prev_nop_frag_since
7181 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7182 gas_assert (nops <= prev_nop_frag_holds);
7184 /* Enforce NOPS as a minimum. */
7185 if (nops > prev_nop_frag_required)
7186 prev_nop_frag_required = nops;
7188 if (prev_nop_frag_holds == prev_nop_frag_required)
7190 /* Settle for the current number of nops. Update the history
7191 accordingly (for the benefit of any future .set reorder code). */
7192 prev_nop_frag = NULL;
7193 insert_into_history (prev_nop_frag_since,
7194 prev_nop_frag_holds, NOP_INSN);
7198 /* Allow this instruction to replace one of the nops that was
7199 tentatively added to prev_nop_frag. */
7200 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7201 prev_nop_frag_holds--;
7202 prev_nop_frag_since++;
7206 method = get_append_method (ip, address_expr, reloc_type);
7207 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7209 dwarf2_emit_insn (0);
7210 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7211 so "move" the instruction address accordingly.
7213 Also, it doesn't seem appropriate for the assembler to reorder .loc
7214 entries. If this instruction is a branch that we are going to swap
7215 with the previous instruction, the two instructions should be
7216 treated as a unit, and the debug information for both instructions
7217 should refer to the start of the branch sequence. Using the
7218 current position is certainly wrong when swapping a 32-bit branch
7219 and a 16-bit delay slot, since the current position would then be
7220 in the middle of a branch. */
7221 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7223 relax32 = (mips_relax_branch
7224 /* Don't try branch relaxation within .set nomacro, or within
7225 .set noat if we use $at for PIC computations. If it turns
7226 out that the branch was out-of-range, we'll get an error. */
7227 && !mips_opts.warn_about_macros
7228 && (mips_opts.at || mips_pic == NO_PIC)
7229 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7230 as they have no complementing branches. */
7231 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7233 if (!HAVE_CODE_COMPRESSION
7236 && *reloc_type == BFD_RELOC_16_PCREL_S2
7237 && delayed_branch_p (ip))
7239 relaxed_branch = TRUE;
7240 add_relaxed_insn (ip, (relaxed_branch_length
7242 uncond_branch_p (ip) ? -1
7243 : branch_likely_p (ip) ? 1
7247 uncond_branch_p (ip),
7248 branch_likely_p (ip),
7249 pinfo & INSN_WRITE_GPR_31,
7251 address_expr->X_add_symbol,
7252 address_expr->X_add_number);
7253 *reloc_type = BFD_RELOC_UNUSED;
7255 else if (mips_opts.micromips
7257 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7258 || *reloc_type > BFD_RELOC_UNUSED)
7259 && (delayed_branch_p (ip) || compact_branch_p (ip))
7260 /* Don't try branch relaxation when users specify
7261 16-bit/32-bit instructions. */
7262 && !forced_insn_length)
7264 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7265 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7266 int uncond = uncond_branch_p (ip) ? -1 : 0;
7267 int compact = compact_branch_p (ip);
7268 int al = pinfo & INSN_WRITE_GPR_31;
7271 gas_assert (address_expr != NULL);
7272 gas_assert (!mips_relax.sequence);
7274 relaxed_branch = TRUE;
7275 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7276 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
7277 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7279 address_expr->X_add_symbol,
7280 address_expr->X_add_number);
7281 *reloc_type = BFD_RELOC_UNUSED;
7283 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7285 /* We need to set up a variant frag. */
7286 gas_assert (address_expr != NULL);
7287 add_relaxed_insn (ip, 4, 0,
7289 (*reloc_type - BFD_RELOC_UNUSED,
7290 forced_insn_length == 2, forced_insn_length == 4,
7291 delayed_branch_p (&history[0]),
7292 history[0].mips16_absolute_jump_p),
7293 make_expr_symbol (address_expr), 0);
7295 else if (mips_opts.mips16 && insn_length (ip) == 2)
7297 if (!delayed_branch_p (ip))
7298 /* Make sure there is enough room to swap this instruction with
7299 a following jump instruction. */
7301 add_fixed_insn (ip);
7305 if (mips_opts.mips16
7306 && mips_opts.noreorder
7307 && delayed_branch_p (&history[0]))
7308 as_warn (_("extended instruction in delay slot"));
7310 if (mips_relax.sequence)
7312 /* If we've reached the end of this frag, turn it into a variant
7313 frag and record the information for the instructions we've
7315 if (frag_room () < 4)
7316 relax_close_frag ();
7317 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7320 if (mips_relax.sequence != 2)
7322 if (mips_macro_warning.first_insn_sizes[0] == 0)
7323 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7324 mips_macro_warning.sizes[0] += insn_length (ip);
7325 mips_macro_warning.insns[0]++;
7327 if (mips_relax.sequence != 1)
7329 if (mips_macro_warning.first_insn_sizes[1] == 0)
7330 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7331 mips_macro_warning.sizes[1] += insn_length (ip);
7332 mips_macro_warning.insns[1]++;
7335 if (mips_opts.mips16)
7338 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7340 add_fixed_insn (ip);
7343 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7345 bfd_reloc_code_real_type final_type[3];
7346 reloc_howto_type *howto0;
7347 reloc_howto_type *howto;
7350 /* Perform any necessary conversion to microMIPS relocations
7351 and find out how many relocations there actually are. */
7352 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7353 final_type[i] = micromips_map_reloc (reloc_type[i]);
7355 /* In a compound relocation, it is the final (outermost)
7356 operator that determines the relocated field. */
7357 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7362 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7363 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7364 bfd_get_reloc_size (howto),
7366 howto0 && howto0->pc_relative,
7369 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7370 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7371 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7373 /* These relocations can have an addend that won't fit in
7374 4 octets for 64bit assembly. */
7376 && ! howto->partial_inplace
7377 && (reloc_type[0] == BFD_RELOC_16
7378 || reloc_type[0] == BFD_RELOC_32
7379 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7380 || reloc_type[0] == BFD_RELOC_GPREL16
7381 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7382 || reloc_type[0] == BFD_RELOC_GPREL32
7383 || reloc_type[0] == BFD_RELOC_64
7384 || reloc_type[0] == BFD_RELOC_CTOR
7385 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7386 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7387 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7388 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7389 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7390 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7391 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7392 || hi16_reloc_p (reloc_type[0])
7393 || lo16_reloc_p (reloc_type[0])))
7394 ip->fixp[0]->fx_no_overflow = 1;
7396 /* These relocations can have an addend that won't fit in 2 octets. */
7397 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7398 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7399 ip->fixp[0]->fx_no_overflow = 1;
7401 if (mips_relax.sequence)
7403 if (mips_relax.first_fixup == 0)
7404 mips_relax.first_fixup = ip->fixp[0];
7406 else if (reloc_needs_lo_p (*reloc_type))
7408 struct mips_hi_fixup *hi_fixup;
7410 /* Reuse the last entry if it already has a matching %lo. */
7411 hi_fixup = mips_hi_fixup_list;
7413 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7415 hi_fixup = ((struct mips_hi_fixup *)
7416 xmalloc (sizeof (struct mips_hi_fixup)));
7417 hi_fixup->next = mips_hi_fixup_list;
7418 mips_hi_fixup_list = hi_fixup;
7420 hi_fixup->fixp = ip->fixp[0];
7421 hi_fixup->seg = now_seg;
7424 /* Add fixups for the second and third relocations, if given.
7425 Note that the ABI allows the second relocation to be
7426 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7427 moment we only use RSS_UNDEF, but we could add support
7428 for the others if it ever becomes necessary. */
7429 for (i = 1; i < 3; i++)
7430 if (reloc_type[i] != BFD_RELOC_UNUSED)
7432 ip->fixp[i] = fix_new (ip->frag, ip->where,
7433 ip->fixp[0]->fx_size, NULL, 0,
7434 FALSE, final_type[i]);
7436 /* Use fx_tcbit to mark compound relocs. */
7437 ip->fixp[0]->fx_tcbit = 1;
7438 ip->fixp[i]->fx_tcbit = 1;
7443 /* Update the register mask information. */
7444 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7445 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7450 insert_into_history (0, 1, ip);
7453 case APPEND_ADD_WITH_NOP:
7455 struct mips_cl_insn *nop;
7457 insert_into_history (0, 1, ip);
7458 nop = get_delay_slot_nop (ip);
7459 add_fixed_insn (nop);
7460 insert_into_history (0, 1, nop);
7461 if (mips_relax.sequence)
7462 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7466 case APPEND_ADD_COMPACT:
7467 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7468 gas_assert (mips_opts.mips16);
7469 ip->insn_opcode |= 0x0080;
7470 find_altered_mips16_opcode (ip);
7472 insert_into_history (0, 1, ip);
7477 struct mips_cl_insn delay = history[0];
7478 if (mips_opts.mips16)
7480 know (delay.frag == ip->frag);
7481 move_insn (ip, delay.frag, delay.where);
7482 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7484 else if (relaxed_branch || delay.frag != ip->frag)
7486 /* Add the delay slot instruction to the end of the
7487 current frag and shrink the fixed part of the
7488 original frag. If the branch occupies the tail of
7489 the latter, move it backwards to cover the gap. */
7490 delay.frag->fr_fix -= branch_disp;
7491 if (delay.frag == ip->frag)
7492 move_insn (ip, ip->frag, ip->where - branch_disp);
7493 add_fixed_insn (&delay);
7497 move_insn (&delay, ip->frag,
7498 ip->where - branch_disp + insn_length (ip));
7499 move_insn (ip, history[0].frag, history[0].where);
7503 insert_into_history (0, 1, &delay);
7508 /* If we have just completed an unconditional branch, clear the history. */
7509 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7510 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7514 mips_no_prev_insn ();
7516 for (i = 0; i < ARRAY_SIZE (history); i++)
7517 history[i].cleared_p = 1;
7520 /* We need to emit a label at the end of branch-likely macros. */
7521 if (emit_branch_likely_macro)
7523 emit_branch_likely_macro = FALSE;
7524 micromips_add_label ();
7527 /* We just output an insn, so the next one doesn't have a label. */
7528 mips_clear_insn_labels ();
7531 /* Forget that there was any previous instruction or label.
7532 When BRANCH is true, the branch history is also flushed. */
7535 mips_no_prev_insn (void)
7537 prev_nop_frag = NULL;
7538 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7539 mips_clear_insn_labels ();
7542 /* This function must be called before we emit something other than
7543 instructions. It is like mips_no_prev_insn except that it inserts
7544 any NOPS that might be needed by previous instructions. */
7547 mips_emit_delays (void)
7549 if (! mips_opts.noreorder)
7551 int nops = nops_for_insn (0, history, NULL);
7555 add_fixed_insn (NOP_INSN);
7556 mips_move_text_labels ();
7559 mips_no_prev_insn ();
7562 /* Start a (possibly nested) noreorder block. */
7565 start_noreorder (void)
7567 if (mips_opts.noreorder == 0)
7572 /* None of the instructions before the .set noreorder can be moved. */
7573 for (i = 0; i < ARRAY_SIZE (history); i++)
7574 history[i].fixed_p = 1;
7576 /* Insert any nops that might be needed between the .set noreorder
7577 block and the previous instructions. We will later remove any
7578 nops that turn out not to be needed. */
7579 nops = nops_for_insn (0, history, NULL);
7582 if (mips_optimize != 0)
7584 /* Record the frag which holds the nop instructions, so
7585 that we can remove them if we don't need them. */
7586 frag_grow (nops * NOP_INSN_SIZE);
7587 prev_nop_frag = frag_now;
7588 prev_nop_frag_holds = nops;
7589 prev_nop_frag_required = 0;
7590 prev_nop_frag_since = 0;
7593 for (; nops > 0; --nops)
7594 add_fixed_insn (NOP_INSN);
7596 /* Move on to a new frag, so that it is safe to simply
7597 decrease the size of prev_nop_frag. */
7598 frag_wane (frag_now);
7600 mips_move_text_labels ();
7602 mips_mark_labels ();
7603 mips_clear_insn_labels ();
7605 mips_opts.noreorder++;
7606 mips_any_noreorder = 1;
7609 /* End a nested noreorder block. */
7612 end_noreorder (void)
7614 mips_opts.noreorder--;
7615 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7617 /* Commit to inserting prev_nop_frag_required nops and go back to
7618 handling nop insertion the .set reorder way. */
7619 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7621 insert_into_history (prev_nop_frag_since,
7622 prev_nop_frag_required, NOP_INSN);
7623 prev_nop_frag = NULL;
7627 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7628 higher bits unset. */
7631 normalize_constant_expr (expressionS *ex)
7633 if (ex->X_op == O_constant
7634 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7635 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7639 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7640 all higher bits unset. */
7643 normalize_address_expr (expressionS *ex)
7645 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7646 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7647 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7648 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7652 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7653 Return true if the match was successful.
7655 OPCODE_EXTRA is a value that should be ORed into the opcode
7656 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7657 there are more alternatives after OPCODE and SOFT_MATCH is
7658 as for mips_arg_info. */
7661 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7662 struct mips_operand_token *tokens, unsigned int opcode_extra,
7663 bfd_boolean lax_match, bfd_boolean complete_p)
7666 struct mips_arg_info arg;
7667 const struct mips_operand *operand;
7670 imm_expr.X_op = O_absent;
7671 offset_expr.X_op = O_absent;
7672 offset_reloc[0] = BFD_RELOC_UNUSED;
7673 offset_reloc[1] = BFD_RELOC_UNUSED;
7674 offset_reloc[2] = BFD_RELOC_UNUSED;
7676 create_insn (insn, opcode);
7677 /* When no opcode suffix is specified, assume ".xyzw". */
7678 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7679 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7681 insn->insn_opcode |= opcode_extra;
7682 memset (&arg, 0, sizeof (arg));
7686 arg.last_regno = ILLEGAL_REG;
7687 arg.dest_regno = ILLEGAL_REG;
7688 arg.lax_match = lax_match;
7689 for (args = opcode->args;; ++args)
7691 if (arg.token->type == OT_END)
7693 /* Handle unary instructions in which only one operand is given.
7694 The source is then the same as the destination. */
7695 if (arg.opnum == 1 && *args == ',')
7697 operand = (mips_opts.micromips
7698 ? decode_micromips_operand (args + 1)
7699 : decode_mips_operand (args + 1));
7700 if (operand && mips_optional_operand_p (operand))
7708 /* Treat elided base registers as $0. */
7709 if (strcmp (args, "(b)") == 0)
7717 /* The register suffix is optional. */
7722 /* Fail the match if there were too few operands. */
7726 /* Successful match. */
7729 clear_insn_error ();
7730 if (arg.dest_regno == arg.last_regno
7731 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7735 (0, _("source and destination must be different"));
7736 else if (arg.last_regno == 31)
7738 (0, _("a destination register must be supplied"));
7740 else if (arg.last_regno == 31
7741 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7742 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7743 set_insn_error (0, _("the source register must not be $31"));
7744 check_completed_insn (&arg);
7748 /* Fail the match if the line has too many operands. */
7752 /* Handle characters that need to match exactly. */
7753 if (*args == '(' || *args == ')' || *args == ',')
7755 if (match_char (&arg, *args))
7762 if (arg.token->type == OT_DOUBLE_CHAR
7763 && arg.token->u.ch == *args)
7771 /* Handle special macro operands. Work out the properties of
7780 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7784 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7793 *offset_reloc = BFD_RELOC_MIPS_JMP;
7797 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7801 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7807 if (!match_const_int (&arg, &imm_expr.X_add_number))
7809 imm_expr.X_op = O_constant;
7811 normalize_constant_expr (&imm_expr);
7815 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7817 /* Assume that the offset has been elided and that what
7818 we saw was a base register. The match will fail later
7819 if that assumption turns out to be wrong. */
7820 offset_expr.X_op = O_constant;
7821 offset_expr.X_add_number = 0;
7825 if (!match_expression (&arg, &offset_expr, offset_reloc))
7827 normalize_address_expr (&offset_expr);
7832 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7838 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7844 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7850 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7856 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7860 *offset_reloc = BFD_RELOC_MIPS_JMP;
7864 gas_assert (mips_opts.micromips);
7870 if (!forced_insn_length)
7871 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7873 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7875 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7881 operand = (mips_opts.micromips
7882 ? decode_micromips_operand (args)
7883 : decode_mips_operand (args));
7887 /* Skip prefixes. */
7888 if (*args == '+' || *args == 'm' || *args == '-')
7891 if (mips_optional_operand_p (operand)
7893 && (arg.token[0].type != OT_REG
7894 || arg.token[1].type == OT_END))
7896 /* Assume that the register has been elided and is the
7897 same as the first operand. */
7902 if (!match_operand (&arg, operand))
7907 /* Like match_insn, but for MIPS16. */
7910 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7911 struct mips_operand_token *tokens)
7914 const struct mips_operand *operand;
7915 const struct mips_operand *ext_operand;
7916 struct mips_arg_info arg;
7919 create_insn (insn, opcode);
7920 imm_expr.X_op = O_absent;
7921 offset_expr.X_op = O_absent;
7922 offset_reloc[0] = BFD_RELOC_UNUSED;
7923 offset_reloc[1] = BFD_RELOC_UNUSED;
7924 offset_reloc[2] = BFD_RELOC_UNUSED;
7927 memset (&arg, 0, sizeof (arg));
7931 arg.last_regno = ILLEGAL_REG;
7932 arg.dest_regno = ILLEGAL_REG;
7934 for (args = opcode->args;; ++args)
7938 if (arg.token->type == OT_END)
7942 /* Handle unary instructions in which only one operand is given.
7943 The source is then the same as the destination. */
7944 if (arg.opnum == 1 && *args == ',')
7946 operand = decode_mips16_operand (args[1], FALSE);
7947 if (operand && mips_optional_operand_p (operand))
7955 /* Fail the match if there were too few operands. */
7959 /* Successful match. Stuff the immediate value in now, if
7961 clear_insn_error ();
7962 if (opcode->pinfo == INSN_MACRO)
7964 gas_assert (relax_char == 0 || relax_char == 'p');
7965 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7968 && offset_expr.X_op == O_constant
7969 && calculate_reloc (*offset_reloc,
7970 offset_expr.X_add_number,
7973 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7974 forced_insn_length, &insn->insn_opcode);
7975 offset_expr.X_op = O_absent;
7976 *offset_reloc = BFD_RELOC_UNUSED;
7978 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7980 if (forced_insn_length == 2)
7981 set_insn_error (0, _("invalid unextended operand value"));
7982 forced_insn_length = 4;
7983 insn->insn_opcode |= MIPS16_EXTEND;
7985 else if (relax_char)
7986 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7988 check_completed_insn (&arg);
7992 /* Fail the match if the line has too many operands. */
7996 /* Handle characters that need to match exactly. */
7997 if (*args == '(' || *args == ')' || *args == ',')
7999 if (match_char (&arg, *args))
8017 if (!match_const_int (&arg, &imm_expr.X_add_number))
8019 imm_expr.X_op = O_constant;
8021 normalize_constant_expr (&imm_expr);
8026 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8027 insn->insn_opcode <<= 16;
8031 operand = decode_mips16_operand (c, FALSE);
8035 /* '6' is a special case. It is used for BREAK and SDBBP,
8036 whose operands are only meaningful to the software that decodes
8037 them. This means that there is no architectural reason why
8038 they cannot be prefixed by EXTEND, but in practice,
8039 exception handlers will only look at the instruction
8040 itself. We therefore allow '6' to be extended when
8041 disassembling but not when assembling. */
8042 if (operand->type != OP_PCREL && c != '6')
8044 ext_operand = decode_mips16_operand (c, TRUE);
8045 if (operand != ext_operand)
8047 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8049 offset_expr.X_op = O_constant;
8050 offset_expr.X_add_number = 0;
8055 /* We need the OT_INTEGER check because some MIPS16
8056 immediate variants are listed before the register ones. */
8057 if (arg.token->type != OT_INTEGER
8058 || !match_expression (&arg, &offset_expr, offset_reloc))
8061 /* '8' is used for SLTI(U) and has traditionally not
8062 been allowed to take relocation operators. */
8063 if (offset_reloc[0] != BFD_RELOC_UNUSED
8064 && (ext_operand->size != 16 || c == '8'))
8072 if (mips_optional_operand_p (operand)
8074 && (arg.token[0].type != OT_REG
8075 || arg.token[1].type == OT_END))
8077 /* Assume that the register has been elided and is the
8078 same as the first operand. */
8083 if (!match_operand (&arg, operand))
8088 /* Record that the current instruction is invalid for the current ISA. */
8091 match_invalid_for_isa (void)
8094 (0, _("opcode not supported on this processor: %s (%s)"),
8095 mips_cpu_info_from_arch (mips_opts.arch)->name,
8096 mips_cpu_info_from_isa (mips_opts.isa)->name);
8099 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8100 Return true if a definite match or failure was found, storing any match
8101 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8102 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8103 tried and failed to match under normal conditions and now want to try a
8104 more relaxed match. */
8107 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8108 const struct mips_opcode *past, struct mips_operand_token *tokens,
8109 int opcode_extra, bfd_boolean lax_match)
8111 const struct mips_opcode *opcode;
8112 const struct mips_opcode *invalid_delay_slot;
8113 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8115 /* Search for a match, ignoring alternatives that don't satisfy the
8116 current ISA or forced_length. */
8117 invalid_delay_slot = 0;
8118 seen_valid_for_isa = FALSE;
8119 seen_valid_for_size = FALSE;
8123 gas_assert (strcmp (opcode->name, first->name) == 0);
8124 if (is_opcode_valid (opcode))
8126 seen_valid_for_isa = TRUE;
8127 if (is_size_valid (opcode))
8129 bfd_boolean delay_slot_ok;
8131 seen_valid_for_size = TRUE;
8132 delay_slot_ok = is_delay_slot_valid (opcode);
8133 if (match_insn (insn, opcode, tokens, opcode_extra,
8134 lax_match, delay_slot_ok))
8138 if (!invalid_delay_slot)
8139 invalid_delay_slot = opcode;
8148 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8150 /* If the only matches we found had the wrong length for the delay slot,
8151 pick the first such match. We'll issue an appropriate warning later. */
8152 if (invalid_delay_slot)
8154 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8160 /* Handle the case where we didn't try to match an instruction because
8161 all the alternatives were incompatible with the current ISA. */
8162 if (!seen_valid_for_isa)
8164 match_invalid_for_isa ();
8168 /* Handle the case where we didn't try to match an instruction because
8169 all the alternatives were of the wrong size. */
8170 if (!seen_valid_for_size)
8172 if (mips_opts.insn32)
8173 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8176 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8177 8 * forced_insn_length);
8184 /* Like match_insns, but for MIPS16. */
8187 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8188 struct mips_operand_token *tokens)
8190 const struct mips_opcode *opcode;
8191 bfd_boolean seen_valid_for_isa;
8193 /* Search for a match, ignoring alternatives that don't satisfy the
8194 current ISA. There are no separate entries for extended forms so
8195 we deal with forced_length later. */
8196 seen_valid_for_isa = FALSE;
8200 gas_assert (strcmp (opcode->name, first->name) == 0);
8201 if (is_opcode_valid_16 (opcode))
8203 seen_valid_for_isa = TRUE;
8204 if (match_mips16_insn (insn, opcode, tokens))
8209 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8210 && strcmp (opcode->name, first->name) == 0);
8212 /* Handle the case where we didn't try to match an instruction because
8213 all the alternatives were incompatible with the current ISA. */
8214 if (!seen_valid_for_isa)
8216 match_invalid_for_isa ();
8223 /* Set up global variables for the start of a new macro. */
8228 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8229 memset (&mips_macro_warning.first_insn_sizes, 0,
8230 sizeof (mips_macro_warning.first_insn_sizes));
8231 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8232 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8233 && delayed_branch_p (&history[0]));
8234 switch (history[0].insn_mo->pinfo2
8235 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8237 case INSN2_BRANCH_DELAY_32BIT:
8238 mips_macro_warning.delay_slot_length = 4;
8240 case INSN2_BRANCH_DELAY_16BIT:
8241 mips_macro_warning.delay_slot_length = 2;
8244 mips_macro_warning.delay_slot_length = 0;
8247 mips_macro_warning.first_frag = NULL;
8250 /* Given that a macro is longer than one instruction or of the wrong size,
8251 return the appropriate warning for it. Return null if no warning is
8252 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8253 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8254 and RELAX_NOMACRO. */
8257 macro_warning (relax_substateT subtype)
8259 if (subtype & RELAX_DELAY_SLOT)
8260 return _("macro instruction expanded into multiple instructions"
8261 " in a branch delay slot");
8262 else if (subtype & RELAX_NOMACRO)
8263 return _("macro instruction expanded into multiple instructions");
8264 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8265 | RELAX_DELAY_SLOT_SIZE_SECOND))
8266 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8267 ? _("macro instruction expanded into a wrong size instruction"
8268 " in a 16-bit branch delay slot")
8269 : _("macro instruction expanded into a wrong size instruction"
8270 " in a 32-bit branch delay slot"));
8275 /* Finish up a macro. Emit warnings as appropriate. */
8280 /* Relaxation warning flags. */
8281 relax_substateT subtype = 0;
8283 /* Check delay slot size requirements. */
8284 if (mips_macro_warning.delay_slot_length == 2)
8285 subtype |= RELAX_DELAY_SLOT_16BIT;
8286 if (mips_macro_warning.delay_slot_length != 0)
8288 if (mips_macro_warning.delay_slot_length
8289 != mips_macro_warning.first_insn_sizes[0])
8290 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8291 if (mips_macro_warning.delay_slot_length
8292 != mips_macro_warning.first_insn_sizes[1])
8293 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8296 /* Check instruction count requirements. */
8297 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8299 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8300 subtype |= RELAX_SECOND_LONGER;
8301 if (mips_opts.warn_about_macros)
8302 subtype |= RELAX_NOMACRO;
8303 if (mips_macro_warning.delay_slot_p)
8304 subtype |= RELAX_DELAY_SLOT;
8307 /* If both alternatives fail to fill a delay slot correctly,
8308 emit the warning now. */
8309 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8310 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8315 s = subtype & (RELAX_DELAY_SLOT_16BIT
8316 | RELAX_DELAY_SLOT_SIZE_FIRST
8317 | RELAX_DELAY_SLOT_SIZE_SECOND);
8318 msg = macro_warning (s);
8320 as_warn ("%s", msg);
8324 /* If both implementations are longer than 1 instruction, then emit the
8326 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8331 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8332 msg = macro_warning (s);
8334 as_warn ("%s", msg);
8338 /* If any flags still set, then one implementation might need a warning
8339 and the other either will need one of a different kind or none at all.
8340 Pass any remaining flags over to relaxation. */
8341 if (mips_macro_warning.first_frag != NULL)
8342 mips_macro_warning.first_frag->fr_subtype |= subtype;
8345 /* Instruction operand formats used in macros that vary between
8346 standard MIPS and microMIPS code. */
8348 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8349 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8350 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8351 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8352 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8353 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8354 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8355 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8357 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8358 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8359 : cop12_fmt[mips_opts.micromips])
8360 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8361 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8362 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8363 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8364 : mem12_fmt[mips_opts.micromips])
8365 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8366 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8367 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8369 /* Read a macro's relocation codes from *ARGS and store them in *R.
8370 The first argument in *ARGS will be either the code for a single
8371 relocation or -1 followed by the three codes that make up a
8372 composite relocation. */
8375 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8379 next = va_arg (*args, int);
8381 r[0] = (bfd_reloc_code_real_type) next;
8384 for (i = 0; i < 3; i++)
8385 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8386 /* This function is only used for 16-bit relocation fields.
8387 To make the macro code simpler, treat an unrelocated value
8388 in the same way as BFD_RELOC_LO16. */
8389 if (r[0] == BFD_RELOC_UNUSED)
8390 r[0] = BFD_RELOC_LO16;
8394 /* Build an instruction created by a macro expansion. This is passed
8395 a pointer to the count of instructions created so far, an
8396 expression, the name of the instruction to build, an operand format
8397 string, and corresponding arguments. */
8400 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8402 const struct mips_opcode *mo = NULL;
8403 bfd_reloc_code_real_type r[3];
8404 const struct mips_opcode *amo;
8405 const struct mips_operand *operand;
8406 struct hash_control *hash;
8407 struct mips_cl_insn insn;
8411 va_start (args, fmt);
8413 if (mips_opts.mips16)
8415 mips16_macro_build (ep, name, fmt, &args);
8420 r[0] = BFD_RELOC_UNUSED;
8421 r[1] = BFD_RELOC_UNUSED;
8422 r[2] = BFD_RELOC_UNUSED;
8423 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8424 amo = (struct mips_opcode *) hash_find (hash, name);
8426 gas_assert (strcmp (name, amo->name) == 0);
8430 /* Search until we get a match for NAME. It is assumed here that
8431 macros will never generate MDMX, MIPS-3D, or MT instructions.
8432 We try to match an instruction that fulfils the branch delay
8433 slot instruction length requirement (if any) of the previous
8434 instruction. While doing this we record the first instruction
8435 seen that matches all the other conditions and use it anyway
8436 if the requirement cannot be met; we will issue an appropriate
8437 warning later on. */
8438 if (strcmp (fmt, amo->args) == 0
8439 && amo->pinfo != INSN_MACRO
8440 && is_opcode_valid (amo)
8441 && is_size_valid (amo))
8443 if (is_delay_slot_valid (amo))
8453 gas_assert (amo->name);
8455 while (strcmp (name, amo->name) == 0);
8458 create_insn (&insn, mo);
8471 macro_read_relocs (&args, r);
8472 gas_assert (*r == BFD_RELOC_GPREL16
8473 || *r == BFD_RELOC_MIPS_HIGHER
8474 || *r == BFD_RELOC_HI16_S
8475 || *r == BFD_RELOC_LO16
8476 || *r == BFD_RELOC_MIPS_GOT_OFST);
8480 macro_read_relocs (&args, r);
8484 macro_read_relocs (&args, r);
8485 gas_assert (ep != NULL
8486 && (ep->X_op == O_constant
8487 || (ep->X_op == O_symbol
8488 && (*r == BFD_RELOC_MIPS_HIGHEST
8489 || *r == BFD_RELOC_HI16_S
8490 || *r == BFD_RELOC_HI16
8491 || *r == BFD_RELOC_GPREL16
8492 || *r == BFD_RELOC_MIPS_GOT_HI16
8493 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8497 gas_assert (ep != NULL);
8500 * This allows macro() to pass an immediate expression for
8501 * creating short branches without creating a symbol.
8503 * We don't allow branch relaxation for these branches, as
8504 * they should only appear in ".set nomacro" anyway.
8506 if (ep->X_op == O_constant)
8508 /* For microMIPS we always use relocations for branches.
8509 So we should not resolve immediate values. */
8510 gas_assert (!mips_opts.micromips);
8512 if ((ep->X_add_number & 3) != 0)
8513 as_bad (_("branch to misaligned address (0x%lx)"),
8514 (unsigned long) ep->X_add_number);
8515 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8516 as_bad (_("branch address range overflow (0x%lx)"),
8517 (unsigned long) ep->X_add_number);
8518 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8522 *r = BFD_RELOC_16_PCREL_S2;
8526 gas_assert (ep != NULL);
8527 *r = BFD_RELOC_MIPS_JMP;
8531 operand = (mips_opts.micromips
8532 ? decode_micromips_operand (fmt)
8533 : decode_mips_operand (fmt));
8537 uval = va_arg (args, int);
8538 if (operand->type == OP_CLO_CLZ_DEST)
8539 uval |= (uval << 5);
8540 insn_insert_operand (&insn, operand, uval);
8542 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8548 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8550 append_insn (&insn, ep, r, TRUE);
8554 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8557 struct mips_opcode *mo;
8558 struct mips_cl_insn insn;
8559 const struct mips_operand *operand;
8560 bfd_reloc_code_real_type r[3]
8561 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8563 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8565 gas_assert (strcmp (name, mo->name) == 0);
8567 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8570 gas_assert (mo->name);
8571 gas_assert (strcmp (name, mo->name) == 0);
8574 create_insn (&insn, mo);
8612 gas_assert (ep != NULL);
8614 if (ep->X_op != O_constant)
8615 *r = (int) BFD_RELOC_UNUSED + c;
8616 else if (calculate_reloc (*r, ep->X_add_number, &value))
8618 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8620 *r = BFD_RELOC_UNUSED;
8626 operand = decode_mips16_operand (c, FALSE);
8630 insn_insert_operand (&insn, operand, va_arg (*args, int));
8635 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8637 append_insn (&insn, ep, r, TRUE);
8641 * Generate a "jalr" instruction with a relocation hint to the called
8642 * function. This occurs in NewABI PIC code.
8645 macro_build_jalr (expressionS *ep, int cprestore)
8647 static const bfd_reloc_code_real_type jalr_relocs[2]
8648 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8649 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8653 if (MIPS_JALR_HINT_P (ep))
8658 if (mips_opts.micromips)
8660 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8661 ? "jalr" : "jalrs");
8662 if (MIPS_JALR_HINT_P (ep)
8664 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8665 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8667 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8670 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8671 if (MIPS_JALR_HINT_P (ep))
8672 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8676 * Generate a "lui" instruction.
8679 macro_build_lui (expressionS *ep, int regnum)
8681 gas_assert (! mips_opts.mips16);
8683 if (ep->X_op != O_constant)
8685 gas_assert (ep->X_op == O_symbol);
8686 /* _gp_disp is a special case, used from s_cpload.
8687 __gnu_local_gp is used if mips_no_shared. */
8688 gas_assert (mips_pic == NO_PIC
8690 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8691 || (! mips_in_shared
8692 && strcmp (S_GET_NAME (ep->X_add_symbol),
8693 "__gnu_local_gp") == 0));
8696 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8699 /* Generate a sequence of instructions to do a load or store from a constant
8700 offset off of a base register (breg) into/from a target register (treg),
8701 using AT if necessary. */
8703 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8704 int treg, int breg, int dbl)
8706 gas_assert (ep->X_op == O_constant);
8708 /* Sign-extending 32-bit constants makes their handling easier. */
8710 normalize_constant_expr (ep);
8712 /* Right now, this routine can only handle signed 32-bit constants. */
8713 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8714 as_warn (_("operand overflow"));
8716 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8718 /* Signed 16-bit offset will fit in the op. Easy! */
8719 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8723 /* 32-bit offset, need multiple instructions and AT, like:
8724 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8725 addu $tempreg,$tempreg,$breg
8726 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8727 to handle the complete offset. */
8728 macro_build_lui (ep, AT);
8729 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8730 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8733 as_bad (_("macro used $at after \".set noat\""));
8738 * Generates code to set the $at register to true (one)
8739 * if reg is less than the immediate expression.
8742 set_at (int reg, int unsignedp)
8744 if (imm_expr.X_add_number >= -0x8000
8745 && imm_expr.X_add_number < 0x8000)
8746 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8747 AT, reg, BFD_RELOC_LO16);
8750 load_register (AT, &imm_expr, GPR_SIZE == 64);
8751 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8755 /* Count the leading zeroes by performing a binary chop. This is a
8756 bulky bit of source, but performance is a LOT better for the
8757 majority of values than a simple loop to count the bits:
8758 for (lcnt = 0; (lcnt < 32); lcnt++)
8759 if ((v) & (1 << (31 - lcnt)))
8761 However it is not code size friendly, and the gain will drop a bit
8762 on certain cached systems.
8764 #define COUNT_TOP_ZEROES(v) \
8765 (((v) & ~0xffff) == 0 \
8766 ? ((v) & ~0xff) == 0 \
8767 ? ((v) & ~0xf) == 0 \
8768 ? ((v) & ~0x3) == 0 \
8769 ? ((v) & ~0x1) == 0 \
8774 : ((v) & ~0x7) == 0 \
8777 : ((v) & ~0x3f) == 0 \
8778 ? ((v) & ~0x1f) == 0 \
8781 : ((v) & ~0x7f) == 0 \
8784 : ((v) & ~0xfff) == 0 \
8785 ? ((v) & ~0x3ff) == 0 \
8786 ? ((v) & ~0x1ff) == 0 \
8789 : ((v) & ~0x7ff) == 0 \
8792 : ((v) & ~0x3fff) == 0 \
8793 ? ((v) & ~0x1fff) == 0 \
8796 : ((v) & ~0x7fff) == 0 \
8799 : ((v) & ~0xffffff) == 0 \
8800 ? ((v) & ~0xfffff) == 0 \
8801 ? ((v) & ~0x3ffff) == 0 \
8802 ? ((v) & ~0x1ffff) == 0 \
8805 : ((v) & ~0x7ffff) == 0 \
8808 : ((v) & ~0x3fffff) == 0 \
8809 ? ((v) & ~0x1fffff) == 0 \
8812 : ((v) & ~0x7fffff) == 0 \
8815 : ((v) & ~0xfffffff) == 0 \
8816 ? ((v) & ~0x3ffffff) == 0 \
8817 ? ((v) & ~0x1ffffff) == 0 \
8820 : ((v) & ~0x7ffffff) == 0 \
8823 : ((v) & ~0x3fffffff) == 0 \
8824 ? ((v) & ~0x1fffffff) == 0 \
8827 : ((v) & ~0x7fffffff) == 0 \
8832 * This routine generates the least number of instructions necessary to load
8833 * an absolute expression value into a register.
8836 load_register (int reg, expressionS *ep, int dbl)
8839 expressionS hi32, lo32;
8841 if (ep->X_op != O_big)
8843 gas_assert (ep->X_op == O_constant);
8845 /* Sign-extending 32-bit constants makes their handling easier. */
8847 normalize_constant_expr (ep);
8849 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8851 /* We can handle 16 bit signed values with an addiu to
8852 $zero. No need to ever use daddiu here, since $zero and
8853 the result are always correct in 32 bit mode. */
8854 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8857 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8859 /* We can handle 16 bit unsigned values with an ori to
8861 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8864 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8866 /* 32 bit values require an lui. */
8867 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8868 if ((ep->X_add_number & 0xffff) != 0)
8869 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8874 /* The value is larger than 32 bits. */
8876 if (!dbl || GPR_SIZE == 32)
8880 sprintf_vma (value, ep->X_add_number);
8881 as_bad (_("number (0x%s) larger than 32 bits"), value);
8882 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8886 if (ep->X_op != O_big)
8889 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8890 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8891 hi32.X_add_number &= 0xffffffff;
8893 lo32.X_add_number &= 0xffffffff;
8897 gas_assert (ep->X_add_number > 2);
8898 if (ep->X_add_number == 3)
8899 generic_bignum[3] = 0;
8900 else if (ep->X_add_number > 4)
8901 as_bad (_("number larger than 64 bits"));
8902 lo32.X_op = O_constant;
8903 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8904 hi32.X_op = O_constant;
8905 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8908 if (hi32.X_add_number == 0)
8913 unsigned long hi, lo;
8915 if (hi32.X_add_number == (offsetT) 0xffffffff)
8917 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8919 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8922 if (lo32.X_add_number & 0x80000000)
8924 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8925 if (lo32.X_add_number & 0xffff)
8926 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8931 /* Check for 16bit shifted constant. We know that hi32 is
8932 non-zero, so start the mask on the first bit of the hi32
8937 unsigned long himask, lomask;
8941 himask = 0xffff >> (32 - shift);
8942 lomask = (0xffff << shift) & 0xffffffff;
8946 himask = 0xffff << (shift - 32);
8949 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8950 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8954 tmp.X_op = O_constant;
8956 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8957 | (lo32.X_add_number >> shift));
8959 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8960 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8961 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8962 reg, reg, (shift >= 32) ? shift - 32 : shift);
8967 while (shift <= (64 - 16));
8969 /* Find the bit number of the lowest one bit, and store the
8970 shifted value in hi/lo. */
8971 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8972 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8976 while ((lo & 1) == 0)
8981 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8987 while ((hi & 1) == 0)
8996 /* Optimize if the shifted value is a (power of 2) - 1. */
8997 if ((hi == 0 && ((lo + 1) & lo) == 0)
8998 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9000 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9005 /* This instruction will set the register to be all
9007 tmp.X_op = O_constant;
9008 tmp.X_add_number = (offsetT) -1;
9009 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9013 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9014 reg, reg, (bit >= 32) ? bit - 32 : bit);
9016 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9017 reg, reg, (shift >= 32) ? shift - 32 : shift);
9022 /* Sign extend hi32 before calling load_register, because we can
9023 generally get better code when we load a sign extended value. */
9024 if ((hi32.X_add_number & 0x80000000) != 0)
9025 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9026 load_register (reg, &hi32, 0);
9029 if ((lo32.X_add_number & 0xffff0000) == 0)
9033 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9041 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9043 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9044 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9050 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9054 mid16.X_add_number >>= 16;
9055 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9056 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9059 if ((lo32.X_add_number & 0xffff) != 0)
9060 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9064 load_delay_nop (void)
9066 if (!gpr_interlocks)
9067 macro_build (NULL, "nop", "");
9070 /* Load an address into a register. */
9073 load_address (int reg, expressionS *ep, int *used_at)
9075 if (ep->X_op != O_constant
9076 && ep->X_op != O_symbol)
9078 as_bad (_("expression too complex"));
9079 ep->X_op = O_constant;
9082 if (ep->X_op == O_constant)
9084 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9088 if (mips_pic == NO_PIC)
9090 /* If this is a reference to a GP relative symbol, we want
9091 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9093 lui $reg,<sym> (BFD_RELOC_HI16_S)
9094 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9095 If we have an addend, we always use the latter form.
9097 With 64bit address space and a usable $at we want
9098 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9099 lui $at,<sym> (BFD_RELOC_HI16_S)
9100 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9101 daddiu $at,<sym> (BFD_RELOC_LO16)
9105 If $at is already in use, we use a path which is suboptimal
9106 on superscalar processors.
9107 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9108 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9110 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9112 daddiu $reg,<sym> (BFD_RELOC_LO16)
9114 For GP relative symbols in 64bit address space we can use
9115 the same sequence as in 32bit address space. */
9116 if (HAVE_64BIT_SYMBOLS)
9118 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9119 && !nopic_need_relax (ep->X_add_symbol, 1))
9121 relax_start (ep->X_add_symbol);
9122 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9123 mips_gp_register, BFD_RELOC_GPREL16);
9127 if (*used_at == 0 && mips_opts.at)
9129 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9130 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9131 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9132 BFD_RELOC_MIPS_HIGHER);
9133 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9134 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9135 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9140 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9141 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9142 BFD_RELOC_MIPS_HIGHER);
9143 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9144 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9145 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9146 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9149 if (mips_relax.sequence)
9154 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9155 && !nopic_need_relax (ep->X_add_symbol, 1))
9157 relax_start (ep->X_add_symbol);
9158 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9159 mips_gp_register, BFD_RELOC_GPREL16);
9162 macro_build_lui (ep, reg);
9163 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9164 reg, reg, BFD_RELOC_LO16);
9165 if (mips_relax.sequence)
9169 else if (!mips_big_got)
9173 /* If this is a reference to an external symbol, we want
9174 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9176 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9178 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9179 If there is a constant, it must be added in after.
9181 If we have NewABI, we want
9182 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9183 unless we're referencing a global symbol with a non-zero
9184 offset, in which case cst must be added separately. */
9187 if (ep->X_add_number)
9189 ex.X_add_number = ep->X_add_number;
9190 ep->X_add_number = 0;
9191 relax_start (ep->X_add_symbol);
9192 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9193 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9194 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9195 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9196 ex.X_op = O_constant;
9197 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9198 reg, reg, BFD_RELOC_LO16);
9199 ep->X_add_number = ex.X_add_number;
9202 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9203 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9204 if (mips_relax.sequence)
9209 ex.X_add_number = ep->X_add_number;
9210 ep->X_add_number = 0;
9211 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9212 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9214 relax_start (ep->X_add_symbol);
9216 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9220 if (ex.X_add_number != 0)
9222 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9223 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9224 ex.X_op = O_constant;
9225 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9226 reg, reg, BFD_RELOC_LO16);
9230 else if (mips_big_got)
9234 /* This is the large GOT case. If this is a reference to an
9235 external symbol, we want
9236 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9238 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9240 Otherwise, for a reference to a local symbol in old ABI, we want
9241 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9243 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9244 If there is a constant, it must be added in after.
9246 In the NewABI, for local symbols, with or without offsets, we want:
9247 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9248 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9252 ex.X_add_number = ep->X_add_number;
9253 ep->X_add_number = 0;
9254 relax_start (ep->X_add_symbol);
9255 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9257 reg, reg, mips_gp_register);
9258 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9259 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9260 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9261 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9262 else if (ex.X_add_number)
9264 ex.X_op = O_constant;
9265 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9269 ep->X_add_number = ex.X_add_number;
9271 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9272 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9273 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9274 BFD_RELOC_MIPS_GOT_OFST);
9279 ex.X_add_number = ep->X_add_number;
9280 ep->X_add_number = 0;
9281 relax_start (ep->X_add_symbol);
9282 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9283 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9284 reg, reg, mips_gp_register);
9285 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9286 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9288 if (reg_needs_delay (mips_gp_register))
9290 /* We need a nop before loading from $gp. This special
9291 check is required because the lui which starts the main
9292 instruction stream does not refer to $gp, and so will not
9293 insert the nop which may be required. */
9294 macro_build (NULL, "nop", "");
9296 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9297 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9299 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9303 if (ex.X_add_number != 0)
9305 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9306 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9307 ex.X_op = O_constant;
9308 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9316 if (!mips_opts.at && *used_at == 1)
9317 as_bad (_("macro used $at after \".set noat\""));
9320 /* Move the contents of register SOURCE into register DEST. */
9323 move_register (int dest, int source)
9325 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9326 instruction specifically requires a 32-bit one. */
9327 if (mips_opts.micromips
9328 && !mips_opts.insn32
9329 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9330 macro_build (NULL, "move", "mp,mj", dest, source);
9332 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9335 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9336 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9337 The two alternatives are:
9339 Global symbol Local sybmol
9340 ------------- ------------
9341 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9343 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9345 load_got_offset emits the first instruction and add_got_offset
9346 emits the second for a 16-bit offset or add_got_offset_hilo emits
9347 a sequence to add a 32-bit offset using a scratch register. */
9350 load_got_offset (int dest, expressionS *local)
9355 global.X_add_number = 0;
9357 relax_start (local->X_add_symbol);
9358 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9359 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9361 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9362 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9367 add_got_offset (int dest, expressionS *local)
9371 global.X_op = O_constant;
9372 global.X_op_symbol = NULL;
9373 global.X_add_symbol = NULL;
9374 global.X_add_number = local->X_add_number;
9376 relax_start (local->X_add_symbol);
9377 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9378 dest, dest, BFD_RELOC_LO16);
9380 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9385 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9388 int hold_mips_optimize;
9390 global.X_op = O_constant;
9391 global.X_op_symbol = NULL;
9392 global.X_add_symbol = NULL;
9393 global.X_add_number = local->X_add_number;
9395 relax_start (local->X_add_symbol);
9396 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9398 /* Set mips_optimize around the lui instruction to avoid
9399 inserting an unnecessary nop after the lw. */
9400 hold_mips_optimize = mips_optimize;
9402 macro_build_lui (&global, tmp);
9403 mips_optimize = hold_mips_optimize;
9404 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9407 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9410 /* Emit a sequence of instructions to emulate a branch likely operation.
9411 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9412 is its complementing branch with the original condition negated.
9413 CALL is set if the original branch specified the link operation.
9414 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9416 Code like this is produced in the noreorder mode:
9421 delay slot (executed only if branch taken)
9429 delay slot (executed only if branch taken)
9432 In the reorder mode the delay slot would be filled with a nop anyway,
9433 so code produced is simply:
9438 This function is used when producing code for the microMIPS ASE that
9439 does not implement branch likely instructions in hardware. */
9442 macro_build_branch_likely (const char *br, const char *brneg,
9443 int call, expressionS *ep, const char *fmt,
9444 unsigned int sreg, unsigned int treg)
9446 int noreorder = mips_opts.noreorder;
9449 gas_assert (mips_opts.micromips);
9453 micromips_label_expr (&expr1);
9454 macro_build (&expr1, brneg, fmt, sreg, treg);
9455 macro_build (NULL, "nop", "");
9456 macro_build (ep, call ? "bal" : "b", "p");
9458 /* Set to true so that append_insn adds a label. */
9459 emit_branch_likely_macro = TRUE;
9463 macro_build (ep, br, fmt, sreg, treg);
9464 macro_build (NULL, "nop", "");
9469 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9470 the condition code tested. EP specifies the branch target. */
9473 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9500 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9503 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9504 the register tested. EP specifies the branch target. */
9507 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9509 const char *brneg = NULL;
9519 br = mips_opts.micromips ? "bgez" : "bgezl";
9523 gas_assert (mips_opts.micromips);
9524 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9532 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9539 br = mips_opts.micromips ? "blez" : "blezl";
9546 br = mips_opts.micromips ? "bltz" : "bltzl";
9550 gas_assert (mips_opts.micromips);
9551 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9558 if (mips_opts.micromips && brneg)
9559 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9561 macro_build (ep, br, "s,p", sreg);
9564 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9565 TREG as the registers tested. EP specifies the branch target. */
9568 macro_build_branch_rsrt (int type, expressionS *ep,
9569 unsigned int sreg, unsigned int treg)
9571 const char *brneg = NULL;
9583 br = mips_opts.micromips ? "beq" : "beql";
9592 br = mips_opts.micromips ? "bne" : "bnel";
9598 if (mips_opts.micromips && brneg)
9599 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9601 macro_build (ep, br, "s,t,p", sreg, treg);
9604 /* Return the high part that should be loaded in order to make the low
9605 part of VALUE accessible using an offset of OFFBITS bits. */
9608 offset_high_part (offsetT value, unsigned int offbits)
9615 bias = 1 << (offbits - 1);
9616 low_mask = bias * 2 - 1;
9617 return (value + bias) & ~low_mask;
9620 /* Return true if the value stored in offset_expr and offset_reloc
9621 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9622 amount that the caller wants to add without inducing overflow
9623 and ALIGN is the known alignment of the value in bytes. */
9626 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9630 /* Accept any relocation operator if overflow isn't a concern. */
9631 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9634 /* These relocations are guaranteed not to overflow in correct links. */
9635 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9636 || gprel16_reloc_p (*offset_reloc))
9639 if (offset_expr.X_op == O_constant
9640 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9641 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9648 * This routine implements the seemingly endless macro or synthesized
9649 * instructions and addressing modes in the mips assembly language. Many
9650 * of these macros are simple and are similar to each other. These could
9651 * probably be handled by some kind of table or grammar approach instead of
9652 * this verbose method. Others are not simple macros but are more like
9653 * optimizing code generation.
9654 * One interesting optimization is when several store macros appear
9655 * consecutively that would load AT with the upper half of the same address.
9656 * The ensuing load upper instructions are ommited. This implies some kind
9657 * of global optimization. We currently only optimize within a single macro.
9658 * For many of the load and store macros if the address is specified as a
9659 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9660 * first load register 'at' with zero and use it as the base register. The
9661 * mips assembler simply uses register $zero. Just one tiny optimization
9665 macro (struct mips_cl_insn *ip, char *str)
9667 const struct mips_operand_array *operands;
9668 unsigned int breg, i;
9669 unsigned int tempreg;
9672 expressionS label_expr;
9687 bfd_boolean large_offset;
9689 int hold_mips_optimize;
9691 unsigned int op[MAX_OPERANDS];
9693 gas_assert (! mips_opts.mips16);
9695 operands = insn_operands (ip);
9696 for (i = 0; i < MAX_OPERANDS; i++)
9697 if (operands->operand[i])
9698 op[i] = insn_extract_operand (ip, operands->operand[i]);
9702 mask = ip->insn_mo->mask;
9704 label_expr.X_op = O_constant;
9705 label_expr.X_op_symbol = NULL;
9706 label_expr.X_add_symbol = NULL;
9707 label_expr.X_add_number = 0;
9709 expr1.X_op = O_constant;
9710 expr1.X_op_symbol = NULL;
9711 expr1.X_add_symbol = NULL;
9712 expr1.X_add_number = 1;
9728 if (mips_opts.micromips)
9729 micromips_label_expr (&label_expr);
9731 label_expr.X_add_number = 8;
9732 macro_build (&label_expr, "bgez", "s,p", op[1]);
9734 macro_build (NULL, "nop", "");
9736 move_register (op[0], op[1]);
9737 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9738 if (mips_opts.micromips)
9739 micromips_add_label ();
9756 if (!mips_opts.micromips)
9758 if (imm_expr.X_add_number >= -0x200
9759 && imm_expr.X_add_number < 0x200)
9761 macro_build (NULL, s, "t,r,.", op[0], op[1],
9762 (int) imm_expr.X_add_number);
9771 if (imm_expr.X_add_number >= -0x8000
9772 && imm_expr.X_add_number < 0x8000)
9774 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9779 load_register (AT, &imm_expr, dbl);
9780 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9799 if (imm_expr.X_add_number >= 0
9800 && imm_expr.X_add_number < 0x10000)
9802 if (mask != M_NOR_I)
9803 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9806 macro_build (&imm_expr, "ori", "t,r,i",
9807 op[0], op[1], BFD_RELOC_LO16);
9808 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9814 load_register (AT, &imm_expr, GPR_SIZE == 64);
9815 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9819 switch (imm_expr.X_add_number)
9822 macro_build (NULL, "nop", "");
9825 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9829 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9830 (int) imm_expr.X_add_number);
9833 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9834 (unsigned long) imm_expr.X_add_number);
9843 gas_assert (mips_opts.micromips);
9844 macro_build_branch_ccl (mask, &offset_expr,
9845 EXTRACT_OPERAND (1, BCC, *ip));
9852 if (imm_expr.X_add_number == 0)
9858 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9863 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9870 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9871 else if (op[0] == 0)
9872 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9876 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9877 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9878 &offset_expr, AT, ZERO);
9888 macro_build_branch_rs (mask, &offset_expr, op[0]);
9894 /* Check for > max integer. */
9895 if (imm_expr.X_add_number >= GPR_SMAX)
9898 /* Result is always false. */
9900 macro_build (NULL, "nop", "");
9902 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9905 ++imm_expr.X_add_number;
9909 if (mask == M_BGEL_I)
9911 if (imm_expr.X_add_number == 0)
9913 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9914 &offset_expr, op[0]);
9917 if (imm_expr.X_add_number == 1)
9919 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9920 &offset_expr, op[0]);
9923 if (imm_expr.X_add_number <= GPR_SMIN)
9926 /* result is always true */
9927 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9928 macro_build (&offset_expr, "b", "p");
9933 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9934 &offset_expr, AT, ZERO);
9942 else if (op[0] == 0)
9943 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9944 &offset_expr, ZERO, op[1]);
9948 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9949 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9950 &offset_expr, AT, ZERO);
9959 && imm_expr.X_add_number == -1))
9961 ++imm_expr.X_add_number;
9965 if (mask == M_BGEUL_I)
9967 if (imm_expr.X_add_number == 0)
9969 else if (imm_expr.X_add_number == 1)
9970 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9971 &offset_expr, op[0], ZERO);
9976 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9977 &offset_expr, AT, ZERO);
9985 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9986 else if (op[0] == 0)
9987 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9991 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9992 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9993 &offset_expr, AT, ZERO);
10001 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10002 &offset_expr, op[0], ZERO);
10003 else if (op[0] == 0)
10008 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10009 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10010 &offset_expr, AT, ZERO);
10018 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10019 else if (op[0] == 0)
10020 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10024 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10025 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10026 &offset_expr, AT, ZERO);
10033 if (imm_expr.X_add_number >= GPR_SMAX)
10035 ++imm_expr.X_add_number;
10039 if (mask == M_BLTL_I)
10041 if (imm_expr.X_add_number == 0)
10042 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10043 else if (imm_expr.X_add_number == 1)
10044 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10049 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10050 &offset_expr, AT, ZERO);
10058 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10059 &offset_expr, op[0], ZERO);
10060 else if (op[0] == 0)
10065 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10066 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10067 &offset_expr, AT, ZERO);
10076 && imm_expr.X_add_number == -1))
10078 ++imm_expr.X_add_number;
10082 if (mask == M_BLTUL_I)
10084 if (imm_expr.X_add_number == 0)
10086 else if (imm_expr.X_add_number == 1)
10087 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10088 &offset_expr, op[0], ZERO);
10093 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10094 &offset_expr, AT, ZERO);
10102 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10103 else if (op[0] == 0)
10104 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10108 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10109 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10110 &offset_expr, AT, ZERO);
10119 else if (op[0] == 0)
10120 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10121 &offset_expr, ZERO, op[1]);
10125 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10126 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10127 &offset_expr, AT, ZERO);
10143 as_warn (_("divide by zero"));
10145 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10147 macro_build (NULL, "break", BRK_FMT, 7);
10151 start_noreorder ();
10154 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10155 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10159 if (mips_opts.micromips)
10160 micromips_label_expr (&label_expr);
10162 label_expr.X_add_number = 8;
10163 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10164 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10165 macro_build (NULL, "break", BRK_FMT, 7);
10166 if (mips_opts.micromips)
10167 micromips_add_label ();
10169 expr1.X_add_number = -1;
10171 load_register (AT, &expr1, dbl);
10172 if (mips_opts.micromips)
10173 micromips_label_expr (&label_expr);
10175 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10176 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10179 expr1.X_add_number = 1;
10180 load_register (AT, &expr1, dbl);
10181 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10185 expr1.X_add_number = 0x80000000;
10186 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10190 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10191 /* We want to close the noreorder block as soon as possible, so
10192 that later insns are available for delay slot filling. */
10197 if (mips_opts.micromips)
10198 micromips_label_expr (&label_expr);
10200 label_expr.X_add_number = 8;
10201 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10202 macro_build (NULL, "nop", "");
10204 /* We want to close the noreorder block as soon as possible, so
10205 that later insns are available for delay slot filling. */
10208 macro_build (NULL, "break", BRK_FMT, 6);
10210 if (mips_opts.micromips)
10211 micromips_add_label ();
10212 macro_build (NULL, s, MFHL_FMT, op[0]);
10251 if (imm_expr.X_add_number == 0)
10253 as_warn (_("divide by zero"));
10255 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10257 macro_build (NULL, "break", BRK_FMT, 7);
10260 if (imm_expr.X_add_number == 1)
10262 if (strcmp (s2, "mflo") == 0)
10263 move_register (op[0], op[1]);
10265 move_register (op[0], ZERO);
10268 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10270 if (strcmp (s2, "mflo") == 0)
10271 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10273 move_register (op[0], ZERO);
10278 load_register (AT, &imm_expr, dbl);
10279 macro_build (NULL, s, "z,s,t", op[1], AT);
10280 macro_build (NULL, s2, MFHL_FMT, op[0]);
10299 start_noreorder ();
10302 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10303 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10304 /* We want to close the noreorder block as soon as possible, so
10305 that later insns are available for delay slot filling. */
10310 if (mips_opts.micromips)
10311 micromips_label_expr (&label_expr);
10313 label_expr.X_add_number = 8;
10314 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10315 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10317 /* We want to close the noreorder block as soon as possible, so
10318 that later insns are available for delay slot filling. */
10320 macro_build (NULL, "break", BRK_FMT, 7);
10321 if (mips_opts.micromips)
10322 micromips_add_label ();
10324 macro_build (NULL, s2, MFHL_FMT, op[0]);
10336 /* Load the address of a symbol into a register. If breg is not
10337 zero, we then add a base register to it. */
10340 if (dbl && GPR_SIZE == 32)
10341 as_warn (_("dla used to load 32-bit register; recommend using la "
10344 if (!dbl && HAVE_64BIT_OBJECTS)
10345 as_warn (_("la used to load 64-bit address; recommend using dla "
10348 if (small_offset_p (0, align, 16))
10350 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10351 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10355 if (mips_opts.at && (op[0] == breg))
10363 if (offset_expr.X_op != O_symbol
10364 && offset_expr.X_op != O_constant)
10366 as_bad (_("expression too complex"));
10367 offset_expr.X_op = O_constant;
10370 if (offset_expr.X_op == O_constant)
10371 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10372 else if (mips_pic == NO_PIC)
10374 /* If this is a reference to a GP relative symbol, we want
10375 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10377 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10378 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10379 If we have a constant, we need two instructions anyhow,
10380 so we may as well always use the latter form.
10382 With 64bit address space and a usable $at we want
10383 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10384 lui $at,<sym> (BFD_RELOC_HI16_S)
10385 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10386 daddiu $at,<sym> (BFD_RELOC_LO16)
10388 daddu $tempreg,$tempreg,$at
10390 If $at is already in use, we use a path which is suboptimal
10391 on superscalar processors.
10392 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10393 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10395 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10397 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10399 For GP relative symbols in 64bit address space we can use
10400 the same sequence as in 32bit address space. */
10401 if (HAVE_64BIT_SYMBOLS)
10403 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10404 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10406 relax_start (offset_expr.X_add_symbol);
10407 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10408 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10412 if (used_at == 0 && mips_opts.at)
10414 macro_build (&offset_expr, "lui", LUI_FMT,
10415 tempreg, BFD_RELOC_MIPS_HIGHEST);
10416 macro_build (&offset_expr, "lui", LUI_FMT,
10417 AT, BFD_RELOC_HI16_S);
10418 macro_build (&offset_expr, "daddiu", "t,r,j",
10419 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10420 macro_build (&offset_expr, "daddiu", "t,r,j",
10421 AT, AT, BFD_RELOC_LO16);
10422 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10423 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10428 macro_build (&offset_expr, "lui", LUI_FMT,
10429 tempreg, BFD_RELOC_MIPS_HIGHEST);
10430 macro_build (&offset_expr, "daddiu", "t,r,j",
10431 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10432 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10433 macro_build (&offset_expr, "daddiu", "t,r,j",
10434 tempreg, tempreg, BFD_RELOC_HI16_S);
10435 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10436 macro_build (&offset_expr, "daddiu", "t,r,j",
10437 tempreg, tempreg, BFD_RELOC_LO16);
10440 if (mips_relax.sequence)
10445 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10446 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10448 relax_start (offset_expr.X_add_symbol);
10449 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10450 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10453 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10454 as_bad (_("offset too large"));
10455 macro_build_lui (&offset_expr, tempreg);
10456 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10457 tempreg, tempreg, BFD_RELOC_LO16);
10458 if (mips_relax.sequence)
10462 else if (!mips_big_got && !HAVE_NEWABI)
10464 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10466 /* If this is a reference to an external symbol, and there
10467 is no constant, we want
10468 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10469 or for lca or if tempreg is PIC_CALL_REG
10470 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10471 For a local symbol, we want
10472 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10474 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10476 If we have a small constant, and this is a reference to
10477 an external symbol, we want
10478 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10480 addiu $tempreg,$tempreg,<constant>
10481 For a local symbol, we want the same instruction
10482 sequence, but we output a BFD_RELOC_LO16 reloc on the
10485 If we have a large constant, and this is a reference to
10486 an external symbol, we want
10487 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10488 lui $at,<hiconstant>
10489 addiu $at,$at,<loconstant>
10490 addu $tempreg,$tempreg,$at
10491 For a local symbol, we want the same instruction
10492 sequence, but we output a BFD_RELOC_LO16 reloc on the
10496 if (offset_expr.X_add_number == 0)
10498 if (mips_pic == SVR4_PIC
10500 && (call || tempreg == PIC_CALL_REG))
10501 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10503 relax_start (offset_expr.X_add_symbol);
10504 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10505 lw_reloc_type, mips_gp_register);
10508 /* We're going to put in an addu instruction using
10509 tempreg, so we may as well insert the nop right
10514 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10515 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10517 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10518 tempreg, tempreg, BFD_RELOC_LO16);
10520 /* FIXME: If breg == 0, and the next instruction uses
10521 $tempreg, then if this variant case is used an extra
10522 nop will be generated. */
10524 else if (offset_expr.X_add_number >= -0x8000
10525 && offset_expr.X_add_number < 0x8000)
10527 load_got_offset (tempreg, &offset_expr);
10529 add_got_offset (tempreg, &offset_expr);
10533 expr1.X_add_number = offset_expr.X_add_number;
10534 offset_expr.X_add_number =
10535 SEXT_16BIT (offset_expr.X_add_number);
10536 load_got_offset (tempreg, &offset_expr);
10537 offset_expr.X_add_number = expr1.X_add_number;
10538 /* If we are going to add in a base register, and the
10539 target register and the base register are the same,
10540 then we are using AT as a temporary register. Since
10541 we want to load the constant into AT, we add our
10542 current AT (from the global offset table) and the
10543 register into the register now, and pretend we were
10544 not using a base register. */
10548 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10553 add_got_offset_hilo (tempreg, &offset_expr, AT);
10557 else if (!mips_big_got && HAVE_NEWABI)
10559 int add_breg_early = 0;
10561 /* If this is a reference to an external, and there is no
10562 constant, or local symbol (*), with or without a
10564 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10565 or for lca or if tempreg is PIC_CALL_REG
10566 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10568 If we have a small constant, and this is a reference to
10569 an external symbol, we want
10570 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10571 addiu $tempreg,$tempreg,<constant>
10573 If we have a large constant, and this is a reference to
10574 an external symbol, we want
10575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10576 lui $at,<hiconstant>
10577 addiu $at,$at,<loconstant>
10578 addu $tempreg,$tempreg,$at
10580 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10581 local symbols, even though it introduces an additional
10584 if (offset_expr.X_add_number)
10586 expr1.X_add_number = offset_expr.X_add_number;
10587 offset_expr.X_add_number = 0;
10589 relax_start (offset_expr.X_add_symbol);
10590 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10591 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10593 if (expr1.X_add_number >= -0x8000
10594 && expr1.X_add_number < 0x8000)
10596 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10597 tempreg, tempreg, BFD_RELOC_LO16);
10599 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10603 /* If we are going to add in a base register, and the
10604 target register and the base register are the same,
10605 then we are using AT as a temporary register. Since
10606 we want to load the constant into AT, we add our
10607 current AT (from the global offset table) and the
10608 register into the register now, and pretend we were
10609 not using a base register. */
10614 gas_assert (tempreg == AT);
10615 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10618 add_breg_early = 1;
10621 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10622 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10628 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10631 offset_expr.X_add_number = expr1.X_add_number;
10633 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10634 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10635 if (add_breg_early)
10637 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10638 op[0], tempreg, breg);
10644 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10646 relax_start (offset_expr.X_add_symbol);
10647 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10648 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10650 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10651 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10656 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10657 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10660 else if (mips_big_got && !HAVE_NEWABI)
10663 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10664 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10665 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10667 /* This is the large GOT case. If this is a reference to an
10668 external symbol, and there is no constant, we want
10669 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10670 addu $tempreg,$tempreg,$gp
10671 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10672 or for lca or if tempreg is PIC_CALL_REG
10673 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10674 addu $tempreg,$tempreg,$gp
10675 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10676 For a local symbol, we want
10677 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10679 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10681 If we have a small constant, and this is a reference to
10682 an external symbol, we want
10683 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10684 addu $tempreg,$tempreg,$gp
10685 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10687 addiu $tempreg,$tempreg,<constant>
10688 For a local symbol, we want
10689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10691 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10693 If we have a large constant, and this is a reference to
10694 an external symbol, we want
10695 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10696 addu $tempreg,$tempreg,$gp
10697 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10698 lui $at,<hiconstant>
10699 addiu $at,$at,<loconstant>
10700 addu $tempreg,$tempreg,$at
10701 For a local symbol, we want
10702 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10703 lui $at,<hiconstant>
10704 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10705 addu $tempreg,$tempreg,$at
10708 expr1.X_add_number = offset_expr.X_add_number;
10709 offset_expr.X_add_number = 0;
10710 relax_start (offset_expr.X_add_symbol);
10711 gpdelay = reg_needs_delay (mips_gp_register);
10712 if (expr1.X_add_number == 0 && breg == 0
10713 && (call || tempreg == PIC_CALL_REG))
10715 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10716 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10718 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10719 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10720 tempreg, tempreg, mips_gp_register);
10721 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10722 tempreg, lw_reloc_type, tempreg);
10723 if (expr1.X_add_number == 0)
10727 /* We're going to put in an addu instruction using
10728 tempreg, so we may as well insert the nop right
10733 else if (expr1.X_add_number >= -0x8000
10734 && expr1.X_add_number < 0x8000)
10737 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10738 tempreg, tempreg, BFD_RELOC_LO16);
10744 /* If we are going to add in a base register, and the
10745 target register and the base register are the same,
10746 then we are using AT as a temporary register. Since
10747 we want to load the constant into AT, we add our
10748 current AT (from the global offset table) and the
10749 register into the register now, and pretend we were
10750 not using a base register. */
10755 gas_assert (tempreg == AT);
10757 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10762 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10767 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10772 /* This is needed because this instruction uses $gp, but
10773 the first instruction on the main stream does not. */
10774 macro_build (NULL, "nop", "");
10777 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10778 local_reloc_type, mips_gp_register);
10779 if (expr1.X_add_number >= -0x8000
10780 && expr1.X_add_number < 0x8000)
10783 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10784 tempreg, tempreg, BFD_RELOC_LO16);
10785 /* FIXME: If add_number is 0, and there was no base
10786 register, the external symbol case ended with a load,
10787 so if the symbol turns out to not be external, and
10788 the next instruction uses tempreg, an unnecessary nop
10789 will be inserted. */
10795 /* We must add in the base register now, as in the
10796 external symbol case. */
10797 gas_assert (tempreg == AT);
10799 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10802 /* We set breg to 0 because we have arranged to add
10803 it in in both cases. */
10807 macro_build_lui (&expr1, AT);
10808 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10809 AT, AT, BFD_RELOC_LO16);
10810 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10811 tempreg, tempreg, AT);
10816 else if (mips_big_got && HAVE_NEWABI)
10818 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10819 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10820 int add_breg_early = 0;
10822 /* This is the large GOT case. If this is a reference to an
10823 external symbol, and there is no constant, we want
10824 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10825 add $tempreg,$tempreg,$gp
10826 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10827 or for lca or if tempreg is PIC_CALL_REG
10828 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10829 add $tempreg,$tempreg,$gp
10830 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10832 If we have a small constant, and this is a reference to
10833 an external symbol, we want
10834 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10835 add $tempreg,$tempreg,$gp
10836 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10837 addi $tempreg,$tempreg,<constant>
10839 If we have a large constant, and this is a reference to
10840 an external symbol, we want
10841 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10842 addu $tempreg,$tempreg,$gp
10843 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10844 lui $at,<hiconstant>
10845 addi $at,$at,<loconstant>
10846 add $tempreg,$tempreg,$at
10848 If we have NewABI, and we know it's a local symbol, we want
10849 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10850 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10851 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10853 relax_start (offset_expr.X_add_symbol);
10855 expr1.X_add_number = offset_expr.X_add_number;
10856 offset_expr.X_add_number = 0;
10858 if (expr1.X_add_number == 0 && breg == 0
10859 && (call || tempreg == PIC_CALL_REG))
10861 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10862 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10864 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10865 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10866 tempreg, tempreg, mips_gp_register);
10867 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10868 tempreg, lw_reloc_type, tempreg);
10870 if (expr1.X_add_number == 0)
10872 else if (expr1.X_add_number >= -0x8000
10873 && expr1.X_add_number < 0x8000)
10875 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10876 tempreg, tempreg, BFD_RELOC_LO16);
10878 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10882 /* If we are going to add in a base register, and the
10883 target register and the base register are the same,
10884 then we are using AT as a temporary register. Since
10885 we want to load the constant into AT, we add our
10886 current AT (from the global offset table) and the
10887 register into the register now, and pretend we were
10888 not using a base register. */
10893 gas_assert (tempreg == AT);
10894 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10897 add_breg_early = 1;
10900 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10906 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10909 offset_expr.X_add_number = expr1.X_add_number;
10910 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10911 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10912 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10913 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10914 if (add_breg_early)
10916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10917 op[0], tempreg, breg);
10927 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10931 gas_assert (!mips_opts.micromips);
10932 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10936 gas_assert (!mips_opts.micromips);
10937 macro_build (NULL, "c2", "C", 0x02);
10941 gas_assert (!mips_opts.micromips);
10942 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10946 gas_assert (!mips_opts.micromips);
10947 macro_build (NULL, "c2", "C", 3);
10951 gas_assert (!mips_opts.micromips);
10952 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10956 /* The j instruction may not be used in PIC code, since it
10957 requires an absolute address. We convert it to a b
10959 if (mips_pic == NO_PIC)
10960 macro_build (&offset_expr, "j", "a");
10962 macro_build (&offset_expr, "b", "p");
10965 /* The jal instructions must be handled as macros because when
10966 generating PIC code they expand to multi-instruction
10967 sequences. Normally they are simple instructions. */
10971 /* Fall through. */
10973 gas_assert (mips_opts.micromips);
10974 if (mips_opts.insn32)
10976 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
10984 /* Fall through. */
10987 if (mips_pic == NO_PIC)
10989 s = jals ? "jalrs" : "jalr";
10990 if (mips_opts.micromips
10991 && !mips_opts.insn32
10993 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10994 macro_build (NULL, s, "mj", op[1]);
10996 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11000 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11001 && mips_cprestore_offset >= 0);
11003 if (op[1] != PIC_CALL_REG)
11004 as_warn (_("MIPS PIC call to register other than $25"));
11006 s = ((mips_opts.micromips
11007 && !mips_opts.insn32
11008 && (!mips_opts.noreorder || cprestore))
11009 ? "jalrs" : "jalr");
11010 if (mips_opts.micromips
11011 && !mips_opts.insn32
11013 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11014 macro_build (NULL, s, "mj", op[1]);
11016 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11017 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11019 if (mips_cprestore_offset < 0)
11020 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11023 if (!mips_frame_reg_valid)
11025 as_warn (_("no .frame pseudo-op used in PIC code"));
11026 /* Quiet this warning. */
11027 mips_frame_reg_valid = 1;
11029 if (!mips_cprestore_valid)
11031 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11032 /* Quiet this warning. */
11033 mips_cprestore_valid = 1;
11035 if (mips_opts.noreorder)
11036 macro_build (NULL, "nop", "");
11037 expr1.X_add_number = mips_cprestore_offset;
11038 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11041 HAVE_64BIT_ADDRESSES);
11049 gas_assert (mips_opts.micromips);
11050 if (mips_opts.insn32)
11052 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11056 /* Fall through. */
11058 if (mips_pic == NO_PIC)
11059 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11060 else if (mips_pic == SVR4_PIC)
11062 /* If this is a reference to an external symbol, and we are
11063 using a small GOT, we want
11064 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11068 lw $gp,cprestore($sp)
11069 The cprestore value is set using the .cprestore
11070 pseudo-op. If we are using a big GOT, we want
11071 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11073 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11077 lw $gp,cprestore($sp)
11078 If the symbol is not external, we want
11079 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11081 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11084 lw $gp,cprestore($sp)
11086 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11087 sequences above, minus nops, unless the symbol is local,
11088 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11094 relax_start (offset_expr.X_add_symbol);
11095 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11096 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11099 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11100 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11106 relax_start (offset_expr.X_add_symbol);
11107 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11108 BFD_RELOC_MIPS_CALL_HI16);
11109 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11110 PIC_CALL_REG, mips_gp_register);
11111 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11112 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11115 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11116 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11118 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11119 PIC_CALL_REG, PIC_CALL_REG,
11120 BFD_RELOC_MIPS_GOT_OFST);
11124 macro_build_jalr (&offset_expr, 0);
11128 relax_start (offset_expr.X_add_symbol);
11131 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11132 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11141 gpdelay = reg_needs_delay (mips_gp_register);
11142 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11143 BFD_RELOC_MIPS_CALL_HI16);
11144 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11145 PIC_CALL_REG, mips_gp_register);
11146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11147 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11152 macro_build (NULL, "nop", "");
11154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11155 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11158 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11159 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11161 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11163 if (mips_cprestore_offset < 0)
11164 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11167 if (!mips_frame_reg_valid)
11169 as_warn (_("no .frame pseudo-op used in PIC code"));
11170 /* Quiet this warning. */
11171 mips_frame_reg_valid = 1;
11173 if (!mips_cprestore_valid)
11175 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11176 /* Quiet this warning. */
11177 mips_cprestore_valid = 1;
11179 if (mips_opts.noreorder)
11180 macro_build (NULL, "nop", "");
11181 expr1.X_add_number = mips_cprestore_offset;
11182 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11185 HAVE_64BIT_ADDRESSES);
11189 else if (mips_pic == VXWORKS_PIC)
11190 as_bad (_("non-PIC jump used in PIC library"));
11297 gas_assert (!mips_opts.micromips);
11300 /* Itbl support may require additional care here. */
11306 /* Itbl support may require additional care here. */
11312 offbits = (mips_opts.micromips ? 12
11313 : ISA_IS_R6 (mips_opts.isa) ? 11
11315 /* Itbl support may require additional care here. */
11319 gas_assert (!mips_opts.micromips);
11322 /* Itbl support may require additional care here. */
11328 offbits = (mips_opts.micromips ? 12 : 16);
11333 offbits = (mips_opts.micromips ? 12 : 16);
11338 /* Itbl support may require additional care here. */
11344 offbits = (mips_opts.micromips ? 12
11345 : ISA_IS_R6 (mips_opts.isa) ? 11
11347 /* Itbl support may require additional care here. */
11353 /* Itbl support may require additional care here. */
11359 /* Itbl support may require additional care here. */
11365 offbits = (mips_opts.micromips ? 12 : 16);
11370 offbits = (mips_opts.micromips ? 12 : 16);
11375 offbits = (mips_opts.micromips ? 12
11376 : ISA_IS_R6 (mips_opts.isa) ? 9
11382 offbits = (mips_opts.micromips ? 12
11383 : ISA_IS_R6 (mips_opts.isa) ? 9
11389 offbits = (mips_opts.micromips ? 12 : 16);
11392 gas_assert (mips_opts.micromips);
11399 gas_assert (mips_opts.micromips);
11406 gas_assert (mips_opts.micromips);
11412 gas_assert (mips_opts.micromips);
11419 /* We don't want to use $0 as tempreg. */
11420 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11423 tempreg = op[0] + lp;
11439 gas_assert (!mips_opts.micromips);
11442 /* Itbl support may require additional care here. */
11448 /* Itbl support may require additional care here. */
11454 offbits = (mips_opts.micromips ? 12
11455 : ISA_IS_R6 (mips_opts.isa) ? 11
11457 /* Itbl support may require additional care here. */
11461 gas_assert (!mips_opts.micromips);
11464 /* Itbl support may require additional care here. */
11470 offbits = (mips_opts.micromips ? 12 : 16);
11475 offbits = (mips_opts.micromips ? 12 : 16);
11480 offbits = (mips_opts.micromips ? 12
11481 : ISA_IS_R6 (mips_opts.isa) ? 9
11487 offbits = (mips_opts.micromips ? 12
11488 : ISA_IS_R6 (mips_opts.isa) ? 9
11493 fmt = (mips_opts.micromips ? "k,~(b)"
11494 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11496 offbits = (mips_opts.micromips ? 12
11497 : ISA_IS_R6 (mips_opts.isa) ? 9
11507 fmt = (mips_opts.micromips ? "k,~(b)"
11508 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11510 offbits = (mips_opts.micromips ? 12
11511 : ISA_IS_R6 (mips_opts.isa) ? 9
11523 /* Itbl support may require additional care here. */
11528 offbits = (mips_opts.micromips ? 12
11529 : ISA_IS_R6 (mips_opts.isa) ? 11
11531 /* Itbl support may require additional care here. */
11537 /* Itbl support may require additional care here. */
11541 gas_assert (!mips_opts.micromips);
11544 /* Itbl support may require additional care here. */
11550 offbits = (mips_opts.micromips ? 12 : 16);
11555 offbits = (mips_opts.micromips ? 12 : 16);
11558 gas_assert (mips_opts.micromips);
11564 gas_assert (mips_opts.micromips);
11570 gas_assert (mips_opts.micromips);
11576 gas_assert (mips_opts.micromips);
11585 if (small_offset_p (0, align, 16))
11587 /* The first case exists for M_LD_AB and M_SD_AB, which are
11588 macros for o32 but which should act like normal instructions
11591 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11592 offset_reloc[1], offset_reloc[2], breg);
11593 else if (small_offset_p (0, align, offbits))
11596 macro_build (NULL, s, fmt, op[0], breg);
11598 macro_build (NULL, s, fmt, op[0],
11599 (int) offset_expr.X_add_number, breg);
11605 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11606 tempreg, breg, -1, offset_reloc[0],
11607 offset_reloc[1], offset_reloc[2]);
11609 macro_build (NULL, s, fmt, op[0], tempreg);
11611 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11619 if (offset_expr.X_op != O_constant
11620 && offset_expr.X_op != O_symbol)
11622 as_bad (_("expression too complex"));
11623 offset_expr.X_op = O_constant;
11626 if (HAVE_32BIT_ADDRESSES
11627 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11631 sprintf_vma (value, offset_expr.X_add_number);
11632 as_bad (_("number (0x%s) larger than 32 bits"), value);
11635 /* A constant expression in PIC code can be handled just as it
11636 is in non PIC code. */
11637 if (offset_expr.X_op == O_constant)
11639 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11640 offbits == 0 ? 16 : offbits);
11641 offset_expr.X_add_number -= expr1.X_add_number;
11643 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11645 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11646 tempreg, tempreg, breg);
11649 if (offset_expr.X_add_number != 0)
11650 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11651 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11652 macro_build (NULL, s, fmt, op[0], tempreg);
11654 else if (offbits == 16)
11655 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11657 macro_build (NULL, s, fmt, op[0],
11658 (int) offset_expr.X_add_number, tempreg);
11660 else if (offbits != 16)
11662 /* The offset field is too narrow to be used for a low-part
11663 relocation, so load the whole address into the auxillary
11665 load_address (tempreg, &offset_expr, &used_at);
11667 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11668 tempreg, tempreg, breg);
11670 macro_build (NULL, s, fmt, op[0], tempreg);
11672 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11674 else if (mips_pic == NO_PIC)
11676 /* If this is a reference to a GP relative symbol, and there
11677 is no base register, we want
11678 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11679 Otherwise, if there is no base register, we want
11680 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11681 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11682 If we have a constant, we need two instructions anyhow,
11683 so we always use the latter form.
11685 If we have a base register, and this is a reference to a
11686 GP relative symbol, we want
11687 addu $tempreg,$breg,$gp
11688 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11690 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11691 addu $tempreg,$tempreg,$breg
11692 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11693 With a constant we always use the latter case.
11695 With 64bit address space and no base register and $at usable,
11697 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11698 lui $at,<sym> (BFD_RELOC_HI16_S)
11699 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11702 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11703 If we have a base register, we want
11704 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11705 lui $at,<sym> (BFD_RELOC_HI16_S)
11706 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11710 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11712 Without $at we can't generate the optimal path for superscalar
11713 processors here since this would require two temporary registers.
11714 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11715 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11717 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11719 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11720 If we have a base register, we want
11721 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11722 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11724 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11726 daddu $tempreg,$tempreg,$breg
11727 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11729 For GP relative symbols in 64bit address space we can use
11730 the same sequence as in 32bit address space. */
11731 if (HAVE_64BIT_SYMBOLS)
11733 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11734 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11736 relax_start (offset_expr.X_add_symbol);
11739 macro_build (&offset_expr, s, fmt, op[0],
11740 BFD_RELOC_GPREL16, mips_gp_register);
11744 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11745 tempreg, breg, mips_gp_register);
11746 macro_build (&offset_expr, s, fmt, op[0],
11747 BFD_RELOC_GPREL16, tempreg);
11752 if (used_at == 0 && mips_opts.at)
11754 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11755 BFD_RELOC_MIPS_HIGHEST);
11756 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11758 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11759 tempreg, BFD_RELOC_MIPS_HIGHER);
11761 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11762 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11763 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11764 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11770 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11771 BFD_RELOC_MIPS_HIGHEST);
11772 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11773 tempreg, BFD_RELOC_MIPS_HIGHER);
11774 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11775 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11776 tempreg, BFD_RELOC_HI16_S);
11777 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11779 macro_build (NULL, "daddu", "d,v,t",
11780 tempreg, tempreg, breg);
11781 macro_build (&offset_expr, s, fmt, op[0],
11782 BFD_RELOC_LO16, tempreg);
11785 if (mips_relax.sequence)
11792 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11793 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11795 relax_start (offset_expr.X_add_symbol);
11796 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11800 macro_build_lui (&offset_expr, tempreg);
11801 macro_build (&offset_expr, s, fmt, op[0],
11802 BFD_RELOC_LO16, tempreg);
11803 if (mips_relax.sequence)
11808 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11809 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11811 relax_start (offset_expr.X_add_symbol);
11812 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11813 tempreg, breg, mips_gp_register);
11814 macro_build (&offset_expr, s, fmt, op[0],
11815 BFD_RELOC_GPREL16, tempreg);
11818 macro_build_lui (&offset_expr, tempreg);
11819 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11820 tempreg, tempreg, breg);
11821 macro_build (&offset_expr, s, fmt, op[0],
11822 BFD_RELOC_LO16, tempreg);
11823 if (mips_relax.sequence)
11827 else if (!mips_big_got)
11829 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11831 /* If this is a reference to an external symbol, we want
11832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11834 <op> op[0],0($tempreg)
11836 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11838 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11839 <op> op[0],0($tempreg)
11841 For NewABI, we want
11842 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11843 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11845 If there is a base register, we add it to $tempreg before
11846 the <op>. If there is a constant, we stick it in the
11847 <op> instruction. We don't handle constants larger than
11848 16 bits, because we have no way to load the upper 16 bits
11849 (actually, we could handle them for the subset of cases
11850 in which we are not using $at). */
11851 gas_assert (offset_expr.X_op == O_symbol);
11854 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11855 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11857 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11858 tempreg, tempreg, breg);
11859 macro_build (&offset_expr, s, fmt, op[0],
11860 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11863 expr1.X_add_number = offset_expr.X_add_number;
11864 offset_expr.X_add_number = 0;
11865 if (expr1.X_add_number < -0x8000
11866 || expr1.X_add_number >= 0x8000)
11867 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11869 lw_reloc_type, mips_gp_register);
11871 relax_start (offset_expr.X_add_symbol);
11873 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11874 tempreg, BFD_RELOC_LO16);
11877 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11878 tempreg, tempreg, breg);
11879 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11881 else if (mips_big_got && !HAVE_NEWABI)
11885 /* If this is a reference to an external symbol, we want
11886 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11887 addu $tempreg,$tempreg,$gp
11888 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11889 <op> op[0],0($tempreg)
11891 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11893 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11894 <op> op[0],0($tempreg)
11895 If there is a base register, we add it to $tempreg before
11896 the <op>. If there is a constant, we stick it in the
11897 <op> instruction. We don't handle constants larger than
11898 16 bits, because we have no way to load the upper 16 bits
11899 (actually, we could handle them for the subset of cases
11900 in which we are not using $at). */
11901 gas_assert (offset_expr.X_op == O_symbol);
11902 expr1.X_add_number = offset_expr.X_add_number;
11903 offset_expr.X_add_number = 0;
11904 if (expr1.X_add_number < -0x8000
11905 || expr1.X_add_number >= 0x8000)
11906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11907 gpdelay = reg_needs_delay (mips_gp_register);
11908 relax_start (offset_expr.X_add_symbol);
11909 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11910 BFD_RELOC_MIPS_GOT_HI16);
11911 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11913 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11914 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11917 macro_build (NULL, "nop", "");
11918 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11919 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11921 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11922 tempreg, BFD_RELOC_LO16);
11926 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11927 tempreg, tempreg, breg);
11928 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11930 else if (mips_big_got && HAVE_NEWABI)
11932 /* If this is a reference to an external symbol, we want
11933 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11934 add $tempreg,$tempreg,$gp
11935 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11936 <op> op[0],<ofst>($tempreg)
11937 Otherwise, for local symbols, we want:
11938 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11939 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11940 gas_assert (offset_expr.X_op == O_symbol);
11941 expr1.X_add_number = offset_expr.X_add_number;
11942 offset_expr.X_add_number = 0;
11943 if (expr1.X_add_number < -0x8000
11944 || expr1.X_add_number >= 0x8000)
11945 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11946 relax_start (offset_expr.X_add_symbol);
11947 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11948 BFD_RELOC_MIPS_GOT_HI16);
11949 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11951 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11952 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11954 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11955 tempreg, tempreg, breg);
11956 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11959 offset_expr.X_add_number = expr1.X_add_number;
11960 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11961 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11963 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11964 tempreg, tempreg, breg);
11965 macro_build (&offset_expr, s, fmt, op[0],
11966 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11975 gas_assert (mips_opts.micromips);
11976 gas_assert (mips_opts.insn32);
11977 start_noreorder ();
11978 macro_build (NULL, "jr", "s", RA);
11979 expr1.X_add_number = op[0] << 2;
11980 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11985 gas_assert (mips_opts.micromips);
11986 gas_assert (mips_opts.insn32);
11987 macro_build (NULL, "jr", "s", op[0]);
11988 if (mips_opts.noreorder)
11989 macro_build (NULL, "nop", "");
11994 load_register (op[0], &imm_expr, 0);
11998 load_register (op[0], &imm_expr, 1);
12002 if (imm_expr.X_op == O_constant)
12005 load_register (AT, &imm_expr, 0);
12006 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12011 gas_assert (imm_expr.X_op == O_absent
12012 && offset_expr.X_op == O_symbol
12013 && strcmp (segment_name (S_GET_SEGMENT
12014 (offset_expr.X_add_symbol)),
12016 && offset_expr.X_add_number == 0);
12017 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12018 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12023 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12024 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12025 order 32 bits of the value and the low order 32 bits are either
12026 zero or in OFFSET_EXPR. */
12027 if (imm_expr.X_op == O_constant)
12029 if (GPR_SIZE == 64)
12030 load_register (op[0], &imm_expr, 1);
12035 if (target_big_endian)
12047 load_register (hreg, &imm_expr, 0);
12050 if (offset_expr.X_op == O_absent)
12051 move_register (lreg, 0);
12054 gas_assert (offset_expr.X_op == O_constant);
12055 load_register (lreg, &offset_expr, 0);
12061 gas_assert (imm_expr.X_op == O_absent);
12063 /* We know that sym is in the .rdata section. First we get the
12064 upper 16 bits of the address. */
12065 if (mips_pic == NO_PIC)
12067 macro_build_lui (&offset_expr, AT);
12072 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12073 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12077 /* Now we load the register(s). */
12078 if (GPR_SIZE == 64)
12081 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12082 BFD_RELOC_LO16, AT);
12087 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12088 BFD_RELOC_LO16, AT);
12091 /* FIXME: How in the world do we deal with the possible
12093 offset_expr.X_add_number += 4;
12094 macro_build (&offset_expr, "lw", "t,o(b)",
12095 op[0] + 1, BFD_RELOC_LO16, AT);
12101 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12102 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12103 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12104 the value and the low order 32 bits are either zero or in
12106 if (imm_expr.X_op == O_constant)
12109 load_register (AT, &imm_expr, FPR_SIZE == 64);
12110 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12111 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12114 if (ISA_HAS_MXHC1 (mips_opts.isa))
12115 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12116 else if (FPR_SIZE != 32)
12117 as_bad (_("Unable to generate `%s' compliant code "
12119 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12121 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12122 if (offset_expr.X_op == O_absent)
12123 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12126 gas_assert (offset_expr.X_op == O_constant);
12127 load_register (AT, &offset_expr, 0);
12128 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12134 gas_assert (imm_expr.X_op == O_absent
12135 && offset_expr.X_op == O_symbol
12136 && offset_expr.X_add_number == 0);
12137 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12138 if (strcmp (s, ".lit8") == 0)
12140 op[2] = mips_gp_register;
12141 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12142 offset_reloc[1] = BFD_RELOC_UNUSED;
12143 offset_reloc[2] = BFD_RELOC_UNUSED;
12147 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12149 if (mips_pic != NO_PIC)
12150 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12151 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12154 /* FIXME: This won't work for a 64 bit address. */
12155 macro_build_lui (&offset_expr, AT);
12159 offset_reloc[0] = BFD_RELOC_LO16;
12160 offset_reloc[1] = BFD_RELOC_UNUSED;
12161 offset_reloc[2] = BFD_RELOC_UNUSED;
12168 * The MIPS assembler seems to check for X_add_number not
12169 * being double aligned and generating:
12170 * lui at,%hi(foo+1)
12172 * addiu at,at,%lo(foo+1)
12175 * But, the resulting address is the same after relocation so why
12176 * generate the extra instruction?
12178 /* Itbl support may require additional care here. */
12181 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12190 gas_assert (!mips_opts.micromips);
12191 /* Itbl support may require additional care here. */
12194 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12214 if (GPR_SIZE == 64)
12224 if (GPR_SIZE == 64)
12232 /* Even on a big endian machine $fn comes before $fn+1. We have
12233 to adjust when loading from memory. We set coproc if we must
12234 load $fn+1 first. */
12235 /* Itbl support may require additional care here. */
12236 if (!target_big_endian)
12240 if (small_offset_p (0, align, 16))
12243 if (!small_offset_p (4, align, 16))
12245 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12246 -1, offset_reloc[0], offset_reloc[1],
12248 expr1.X_add_number = 0;
12252 offset_reloc[0] = BFD_RELOC_LO16;
12253 offset_reloc[1] = BFD_RELOC_UNUSED;
12254 offset_reloc[2] = BFD_RELOC_UNUSED;
12256 if (strcmp (s, "lw") == 0 && op[0] == breg)
12258 ep->X_add_number += 4;
12259 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12260 offset_reloc[1], offset_reloc[2], breg);
12261 ep->X_add_number -= 4;
12262 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12263 offset_reloc[1], offset_reloc[2], breg);
12267 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12268 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12270 ep->X_add_number += 4;
12271 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12272 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12278 if (offset_expr.X_op != O_symbol
12279 && offset_expr.X_op != O_constant)
12281 as_bad (_("expression too complex"));
12282 offset_expr.X_op = O_constant;
12285 if (HAVE_32BIT_ADDRESSES
12286 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12290 sprintf_vma (value, offset_expr.X_add_number);
12291 as_bad (_("number (0x%s) larger than 32 bits"), value);
12294 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12296 /* If this is a reference to a GP relative symbol, we want
12297 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12298 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12299 If we have a base register, we use this
12301 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12302 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12303 If this is not a GP relative symbol, we want
12304 lui $at,<sym> (BFD_RELOC_HI16_S)
12305 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12306 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12307 If there is a base register, we add it to $at after the
12308 lui instruction. If there is a constant, we always use
12310 if (offset_expr.X_op == O_symbol
12311 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12312 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12314 relax_start (offset_expr.X_add_symbol);
12317 tempreg = mips_gp_register;
12321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12322 AT, breg, mips_gp_register);
12327 /* Itbl support may require additional care here. */
12328 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12329 BFD_RELOC_GPREL16, tempreg);
12330 offset_expr.X_add_number += 4;
12332 /* Set mips_optimize to 2 to avoid inserting an
12334 hold_mips_optimize = mips_optimize;
12336 /* Itbl support may require additional care here. */
12337 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12338 BFD_RELOC_GPREL16, tempreg);
12339 mips_optimize = hold_mips_optimize;
12343 offset_expr.X_add_number -= 4;
12346 if (offset_high_part (offset_expr.X_add_number, 16)
12347 != offset_high_part (offset_expr.X_add_number + 4, 16))
12349 load_address (AT, &offset_expr, &used_at);
12350 offset_expr.X_op = O_constant;
12351 offset_expr.X_add_number = 0;
12354 macro_build_lui (&offset_expr, AT);
12356 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12357 /* Itbl support may require additional care here. */
12358 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12359 BFD_RELOC_LO16, AT);
12360 /* FIXME: How do we handle overflow here? */
12361 offset_expr.X_add_number += 4;
12362 /* Itbl support may require additional care here. */
12363 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12364 BFD_RELOC_LO16, AT);
12365 if (mips_relax.sequence)
12368 else if (!mips_big_got)
12370 /* If this is a reference to an external symbol, we want
12371 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12374 <op> op[0]+1,4($at)
12376 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12378 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12379 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12380 If there is a base register we add it to $at before the
12381 lwc1 instructions. If there is a constant we include it
12382 in the lwc1 instructions. */
12384 expr1.X_add_number = offset_expr.X_add_number;
12385 if (expr1.X_add_number < -0x8000
12386 || expr1.X_add_number >= 0x8000 - 4)
12387 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12388 load_got_offset (AT, &offset_expr);
12391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12393 /* Set mips_optimize to 2 to avoid inserting an undesired
12395 hold_mips_optimize = mips_optimize;
12398 /* Itbl support may require additional care here. */
12399 relax_start (offset_expr.X_add_symbol);
12400 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12401 BFD_RELOC_LO16, AT);
12402 expr1.X_add_number += 4;
12403 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12404 BFD_RELOC_LO16, AT);
12406 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12407 BFD_RELOC_LO16, AT);
12408 offset_expr.X_add_number += 4;
12409 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12410 BFD_RELOC_LO16, AT);
12413 mips_optimize = hold_mips_optimize;
12415 else if (mips_big_got)
12419 /* If this is a reference to an external symbol, we want
12420 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12422 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12425 <op> op[0]+1,4($at)
12427 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12429 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12430 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12431 If there is a base register we add it to $at before the
12432 lwc1 instructions. If there is a constant we include it
12433 in the lwc1 instructions. */
12435 expr1.X_add_number = offset_expr.X_add_number;
12436 offset_expr.X_add_number = 0;
12437 if (expr1.X_add_number < -0x8000
12438 || expr1.X_add_number >= 0x8000 - 4)
12439 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12440 gpdelay = reg_needs_delay (mips_gp_register);
12441 relax_start (offset_expr.X_add_symbol);
12442 macro_build (&offset_expr, "lui", LUI_FMT,
12443 AT, BFD_RELOC_MIPS_GOT_HI16);
12444 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12445 AT, AT, mips_gp_register);
12446 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12447 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12451 /* Itbl support may require additional care here. */
12452 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12453 BFD_RELOC_LO16, AT);
12454 expr1.X_add_number += 4;
12456 /* Set mips_optimize to 2 to avoid inserting an undesired
12458 hold_mips_optimize = mips_optimize;
12460 /* Itbl support may require additional care here. */
12461 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12462 BFD_RELOC_LO16, AT);
12463 mips_optimize = hold_mips_optimize;
12464 expr1.X_add_number -= 4;
12467 offset_expr.X_add_number = expr1.X_add_number;
12469 macro_build (NULL, "nop", "");
12470 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12471 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12474 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12475 /* Itbl support may require additional care here. */
12476 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12477 BFD_RELOC_LO16, AT);
12478 offset_expr.X_add_number += 4;
12480 /* Set mips_optimize to 2 to avoid inserting an undesired
12482 hold_mips_optimize = mips_optimize;
12484 /* Itbl support may require additional care here. */
12485 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12486 BFD_RELOC_LO16, AT);
12487 mips_optimize = hold_mips_optimize;
12501 gas_assert (!mips_opts.micromips);
12506 /* New code added to support COPZ instructions.
12507 This code builds table entries out of the macros in mip_opcodes.
12508 R4000 uses interlocks to handle coproc delays.
12509 Other chips (like the R3000) require nops to be inserted for delays.
12511 FIXME: Currently, we require that the user handle delays.
12512 In order to fill delay slots for non-interlocked chips,
12513 we must have a way to specify delays based on the coprocessor.
12514 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12515 What are the side-effects of the cop instruction?
12516 What cache support might we have and what are its effects?
12517 Both coprocessor & memory require delays. how long???
12518 What registers are read/set/modified?
12520 If an itbl is provided to interpret cop instructions,
12521 this knowledge can be encoded in the itbl spec. */
12535 gas_assert (!mips_opts.micromips);
12536 /* For now we just do C (same as Cz). The parameter will be
12537 stored in insn_opcode by mips_ip. */
12538 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12542 move_register (op[0], op[1]);
12546 gas_assert (mips_opts.micromips);
12547 gas_assert (mips_opts.insn32);
12548 move_register (micromips_to_32_reg_h_map1[op[0]],
12549 micromips_to_32_reg_m_map[op[1]]);
12550 move_register (micromips_to_32_reg_h_map2[op[0]],
12551 micromips_to_32_reg_n_map[op[2]]);
12557 if (mips_opts.arch == CPU_R5900)
12558 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12562 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12563 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12570 /* The MIPS assembler some times generates shifts and adds. I'm
12571 not trying to be that fancy. GCC should do this for us
12574 load_register (AT, &imm_expr, dbl);
12575 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12576 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12589 start_noreorder ();
12592 load_register (AT, &imm_expr, dbl);
12593 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12594 op[1], imm ? AT : op[2]);
12595 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12596 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12597 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12599 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12602 if (mips_opts.micromips)
12603 micromips_label_expr (&label_expr);
12605 label_expr.X_add_number = 8;
12606 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12607 macro_build (NULL, "nop", "");
12608 macro_build (NULL, "break", BRK_FMT, 6);
12609 if (mips_opts.micromips)
12610 micromips_add_label ();
12613 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12626 start_noreorder ();
12629 load_register (AT, &imm_expr, dbl);
12630 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12631 op[1], imm ? AT : op[2]);
12632 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12633 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12635 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12638 if (mips_opts.micromips)
12639 micromips_label_expr (&label_expr);
12641 label_expr.X_add_number = 8;
12642 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12643 macro_build (NULL, "nop", "");
12644 macro_build (NULL, "break", BRK_FMT, 6);
12645 if (mips_opts.micromips)
12646 micromips_add_label ();
12652 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12654 if (op[0] == op[1])
12661 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12662 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12666 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12667 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12668 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12669 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12673 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12675 if (op[0] == op[1])
12682 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12683 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12687 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12688 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12689 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12690 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12699 rot = imm_expr.X_add_number & 0x3f;
12700 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12702 rot = (64 - rot) & 0x3f;
12704 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12706 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12711 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12714 l = (rot < 0x20) ? "dsll" : "dsll32";
12715 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12718 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12719 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12720 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12728 rot = imm_expr.X_add_number & 0x1f;
12729 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12731 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12732 (32 - rot) & 0x1f);
12737 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12741 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12742 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12743 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12748 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12750 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12754 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12755 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12756 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12757 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12761 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12763 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12767 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12768 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12769 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12770 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12779 rot = imm_expr.X_add_number & 0x3f;
12780 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12783 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12785 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12790 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12793 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12794 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12797 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12798 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12799 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12807 rot = imm_expr.X_add_number & 0x1f;
12808 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12810 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12815 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12819 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12820 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12821 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12827 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12828 else if (op[2] == 0)
12829 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12832 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12833 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12838 if (imm_expr.X_add_number == 0)
12840 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12845 as_warn (_("instruction %s: result is always false"),
12846 ip->insn_mo->name);
12847 move_register (op[0], 0);
12850 if (CPU_HAS_SEQ (mips_opts.arch)
12851 && -512 <= imm_expr.X_add_number
12852 && imm_expr.X_add_number < 512)
12854 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12855 (int) imm_expr.X_add_number);
12858 if (imm_expr.X_add_number >= 0
12859 && imm_expr.X_add_number < 0x10000)
12860 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12861 else if (imm_expr.X_add_number > -0x8000
12862 && imm_expr.X_add_number < 0)
12864 imm_expr.X_add_number = -imm_expr.X_add_number;
12865 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
12866 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12868 else if (CPU_HAS_SEQ (mips_opts.arch))
12871 load_register (AT, &imm_expr, GPR_SIZE == 64);
12872 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12877 load_register (AT, &imm_expr, GPR_SIZE == 64);
12878 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12881 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12884 case M_SGE: /* X >= Y <==> not (X < Y) */
12890 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12891 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12894 case M_SGE_I: /* X >= I <==> not (X < I) */
12896 if (imm_expr.X_add_number >= -0x8000
12897 && imm_expr.X_add_number < 0x8000)
12898 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12899 op[0], op[1], BFD_RELOC_LO16);
12902 load_register (AT, &imm_expr, GPR_SIZE == 64);
12903 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12907 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12910 case M_SGT: /* X > Y <==> Y < X */
12916 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12919 case M_SGT_I: /* X > I <==> I < X */
12926 load_register (AT, &imm_expr, GPR_SIZE == 64);
12927 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12930 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12936 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12937 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12940 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12947 load_register (AT, &imm_expr, GPR_SIZE == 64);
12948 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12949 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12953 if (imm_expr.X_add_number >= -0x8000
12954 && imm_expr.X_add_number < 0x8000)
12956 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12961 load_register (AT, &imm_expr, GPR_SIZE == 64);
12962 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12966 if (imm_expr.X_add_number >= -0x8000
12967 && imm_expr.X_add_number < 0x8000)
12969 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12974 load_register (AT, &imm_expr, GPR_SIZE == 64);
12975 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12980 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12981 else if (op[2] == 0)
12982 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12985 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12986 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12991 if (imm_expr.X_add_number == 0)
12993 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12998 as_warn (_("instruction %s: result is always true"),
12999 ip->insn_mo->name);
13000 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13001 op[0], 0, BFD_RELOC_LO16);
13004 if (CPU_HAS_SEQ (mips_opts.arch)
13005 && -512 <= imm_expr.X_add_number
13006 && imm_expr.X_add_number < 512)
13008 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13009 (int) imm_expr.X_add_number);
13012 if (imm_expr.X_add_number >= 0
13013 && imm_expr.X_add_number < 0x10000)
13015 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13018 else if (imm_expr.X_add_number > -0x8000
13019 && imm_expr.X_add_number < 0)
13021 imm_expr.X_add_number = -imm_expr.X_add_number;
13022 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13023 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13025 else if (CPU_HAS_SEQ (mips_opts.arch))
13028 load_register (AT, &imm_expr, GPR_SIZE == 64);
13029 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13034 load_register (AT, &imm_expr, GPR_SIZE == 64);
13035 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13038 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13053 if (!mips_opts.micromips)
13055 if (imm_expr.X_add_number > -0x200
13056 && imm_expr.X_add_number <= 0x200)
13058 macro_build (NULL, s, "t,r,.", op[0], op[1],
13059 (int) -imm_expr.X_add_number);
13068 if (imm_expr.X_add_number > -0x8000
13069 && imm_expr.X_add_number <= 0x8000)
13071 imm_expr.X_add_number = -imm_expr.X_add_number;
13072 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13077 load_register (AT, &imm_expr, dbl);
13078 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13100 load_register (AT, &imm_expr, GPR_SIZE == 64);
13101 macro_build (NULL, s, "s,t", op[0], AT);
13106 gas_assert (!mips_opts.micromips);
13107 gas_assert (mips_opts.isa == ISA_MIPS1);
13111 * Is the double cfc1 instruction a bug in the mips assembler;
13112 * or is there a reason for it?
13114 start_noreorder ();
13115 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13116 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13117 macro_build (NULL, "nop", "");
13118 expr1.X_add_number = 3;
13119 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13120 expr1.X_add_number = 2;
13121 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13122 macro_build (NULL, "ctc1", "t,G", AT, RA);
13123 macro_build (NULL, "nop", "");
13124 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13126 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13127 macro_build (NULL, "nop", "");
13144 offbits = (mips_opts.micromips ? 12 : 16);
13150 offbits = (mips_opts.micromips ? 12 : 16);
13162 offbits = (mips_opts.micromips ? 12 : 16);
13169 offbits = (mips_opts.micromips ? 12 : 16);
13175 large_offset = !small_offset_p (off, align, offbits);
13177 expr1.X_add_number = 0;
13182 if (small_offset_p (0, align, 16))
13183 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13184 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13187 load_address (tempreg, ep, &used_at);
13189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13190 tempreg, tempreg, breg);
13192 offset_reloc[0] = BFD_RELOC_LO16;
13193 offset_reloc[1] = BFD_RELOC_UNUSED;
13194 offset_reloc[2] = BFD_RELOC_UNUSED;
13199 else if (!ust && op[0] == breg)
13210 if (!target_big_endian)
13211 ep->X_add_number += off;
13213 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13215 macro_build (ep, s, "t,o(b)", tempreg, -1,
13216 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13218 if (!target_big_endian)
13219 ep->X_add_number -= off;
13221 ep->X_add_number += off;
13223 macro_build (NULL, s2, "t,~(b)",
13224 tempreg, (int) ep->X_add_number, breg);
13226 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13227 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13229 /* If necessary, move the result in tempreg to the final destination. */
13230 if (!ust && op[0] != tempreg)
13232 /* Protect second load's delay slot. */
13234 move_register (op[0], tempreg);
13240 if (target_big_endian == ust)
13241 ep->X_add_number += off;
13242 tempreg = ust || large_offset ? op[0] : AT;
13243 macro_build (ep, s, "t,o(b)", tempreg, -1,
13244 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13246 /* For halfword transfers we need a temporary register to shuffle
13247 bytes. Unfortunately for M_USH_A we have none available before
13248 the next store as AT holds the base address. We deal with this
13249 case by clobbering TREG and then restoring it as with ULH. */
13250 tempreg = ust == large_offset ? op[0] : AT;
13252 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13254 if (target_big_endian == ust)
13255 ep->X_add_number -= off;
13257 ep->X_add_number += off;
13258 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13259 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13261 /* For M_USH_A re-retrieve the LSB. */
13262 if (ust && large_offset)
13264 if (target_big_endian)
13265 ep->X_add_number += off;
13267 ep->X_add_number -= off;
13268 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13269 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13271 /* For ULH and M_USH_A OR the LSB in. */
13272 if (!ust || large_offset)
13274 tempreg = !large_offset ? AT : op[0];
13275 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13276 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13281 /* FIXME: Check if this is one of the itbl macros, since they
13282 are added dynamically. */
13283 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13286 if (!mips_opts.at && used_at)
13287 as_bad (_("macro used $at after \".set noat\""));
13290 /* Implement macros in mips16 mode. */
13293 mips16_macro (struct mips_cl_insn *ip)
13295 const struct mips_operand_array *operands;
13300 const char *s, *s2, *s3;
13301 unsigned int op[MAX_OPERANDS];
13304 mask = ip->insn_mo->mask;
13306 operands = insn_operands (ip);
13307 for (i = 0; i < MAX_OPERANDS; i++)
13308 if (operands->operand[i])
13309 op[i] = insn_extract_operand (ip, operands->operand[i]);
13313 expr1.X_op = O_constant;
13314 expr1.X_op_symbol = NULL;
13315 expr1.X_add_symbol = NULL;
13316 expr1.X_add_number = 1;
13335 start_noreorder ();
13336 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13337 expr1.X_add_number = 2;
13338 macro_build (&expr1, "bnez", "x,p", op[2]);
13339 macro_build (NULL, "break", "6", 7);
13341 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13342 since that causes an overflow. We should do that as well,
13343 but I don't see how to do the comparisons without a temporary
13346 macro_build (NULL, s, "x", op[0]);
13365 start_noreorder ();
13366 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13367 expr1.X_add_number = 2;
13368 macro_build (&expr1, "bnez", "x,p", op[2]);
13369 macro_build (NULL, "break", "6", 7);
13371 macro_build (NULL, s2, "x", op[0]);
13377 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13378 macro_build (NULL, "mflo", "x", op[0]);
13386 imm_expr.X_add_number = -imm_expr.X_add_number;
13387 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13391 imm_expr.X_add_number = -imm_expr.X_add_number;
13392 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13396 imm_expr.X_add_number = -imm_expr.X_add_number;
13397 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13419 goto do_reverse_branch;
13423 goto do_reverse_branch;
13435 goto do_reverse_branch;
13446 macro_build (NULL, s, "x,y", op[0], op[1]);
13447 macro_build (&offset_expr, s2, "p");
13474 goto do_addone_branch_i;
13479 goto do_addone_branch_i;
13494 goto do_addone_branch_i;
13500 do_addone_branch_i:
13501 ++imm_expr.X_add_number;
13504 macro_build (&imm_expr, s, s3, op[0]);
13505 macro_build (&offset_expr, s2, "p");
13509 expr1.X_add_number = 0;
13510 macro_build (&expr1, "slti", "x,8", op[1]);
13511 if (op[0] != op[1])
13512 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13513 expr1.X_add_number = 2;
13514 macro_build (&expr1, "bteqz", "p");
13515 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13520 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13521 opcode bits in *OPCODE_EXTRA. */
13523 static struct mips_opcode *
13524 mips_lookup_insn (struct hash_control *hash, const char *start,
13525 ssize_t length, unsigned int *opcode_extra)
13527 char *name, *dot, *p;
13528 unsigned int mask, suffix;
13530 struct mips_opcode *insn;
13532 /* Make a copy of the instruction so that we can fiddle with it. */
13533 name = alloca (length + 1);
13534 memcpy (name, start, length);
13535 name[length] = '\0';
13537 /* Look up the instruction as-is. */
13538 insn = (struct mips_opcode *) hash_find (hash, name);
13542 dot = strchr (name, '.');
13545 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13546 p = mips_parse_vu0_channels (dot + 1, &mask);
13547 if (*p == 0 && mask != 0)
13550 insn = (struct mips_opcode *) hash_find (hash, name);
13552 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13554 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13560 if (mips_opts.micromips)
13562 /* See if there's an instruction size override suffix,
13563 either `16' or `32', at the end of the mnemonic proper,
13564 that defines the operation, i.e. before the first `.'
13565 character if any. Strip it and retry. */
13566 opend = dot != NULL ? dot - name : length;
13567 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13569 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13575 memcpy (name + opend - 2, name + opend, length - opend + 1);
13576 insn = (struct mips_opcode *) hash_find (hash, name);
13579 forced_insn_length = suffix;
13588 /* Assemble an instruction into its binary format. If the instruction
13589 is a macro, set imm_expr and offset_expr to the values associated
13590 with "I" and "A" operands respectively. Otherwise store the value
13591 of the relocatable field (if any) in offset_expr. In both cases
13592 set offset_reloc to the relocation operators applied to offset_expr. */
13595 mips_ip (char *str, struct mips_cl_insn *insn)
13597 const struct mips_opcode *first, *past;
13598 struct hash_control *hash;
13601 struct mips_operand_token *tokens;
13602 unsigned int opcode_extra;
13604 if (mips_opts.micromips)
13606 hash = micromips_op_hash;
13607 past = µmips_opcodes[bfd_micromips_num_opcodes];
13612 past = &mips_opcodes[NUMOPCODES];
13614 forced_insn_length = 0;
13617 /* We first try to match an instruction up to a space or to the end. */
13618 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13621 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13624 set_insn_error (0, _("unrecognized opcode"));
13628 if (strcmp (first->name, "li.s") == 0)
13630 else if (strcmp (first->name, "li.d") == 0)
13634 tokens = mips_parse_arguments (str + end, format);
13638 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13639 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13640 set_insn_error (0, _("invalid operands"));
13642 obstack_free (&mips_operand_tokens, tokens);
13645 /* As for mips_ip, but used when assembling MIPS16 code.
13646 Also set forced_insn_length to the resulting instruction size in
13647 bytes if the user explicitly requested a small or extended instruction. */
13650 mips16_ip (char *str, struct mips_cl_insn *insn)
13653 struct mips_opcode *first;
13654 struct mips_operand_token *tokens;
13656 forced_insn_length = 0;
13658 for (s = str; ISLOWER (*s); ++s)
13672 if (s[1] == 't' && s[2] == ' ')
13674 forced_insn_length = 2;
13678 else if (s[1] == 'e' && s[2] == ' ')
13680 forced_insn_length = 4;
13684 /* Fall through. */
13686 set_insn_error (0, _("unrecognized opcode"));
13690 if (mips_opts.noautoextend && !forced_insn_length)
13691 forced_insn_length = 2;
13694 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13699 set_insn_error (0, _("unrecognized opcode"));
13703 tokens = mips_parse_arguments (s, 0);
13707 if (!match_mips16_insns (insn, first, tokens))
13708 set_insn_error (0, _("invalid operands"));
13710 obstack_free (&mips_operand_tokens, tokens);
13713 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13714 NBITS is the number of significant bits in VAL. */
13716 static unsigned long
13717 mips16_immed_extend (offsetT val, unsigned int nbits)
13722 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13725 else if (nbits == 15)
13727 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13732 extval = ((val & 0x1f) << 6) | (val & 0x20);
13735 return (extval << 16) | val;
13738 /* Like decode_mips16_operand, but require the operand to be defined and
13739 require it to be an integer. */
13741 static const struct mips_int_operand *
13742 mips16_immed_operand (int type, bfd_boolean extended_p)
13744 const struct mips_operand *operand;
13746 operand = decode_mips16_operand (type, extended_p);
13747 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13749 return (const struct mips_int_operand *) operand;
13752 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13755 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13756 bfd_reloc_code_real_type reloc, offsetT sval)
13758 int min_val, max_val;
13760 min_val = mips_int_operand_min (operand);
13761 max_val = mips_int_operand_max (operand);
13762 if (reloc != BFD_RELOC_UNUSED)
13765 sval = SEXT_16BIT (sval);
13770 return (sval >= min_val
13772 && (sval & ((1 << operand->shift) - 1)) == 0);
13775 /* Install immediate value VAL into MIPS16 instruction *INSN,
13776 extending it if necessary. The instruction in *INSN may
13777 already be extended.
13779 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13780 if none. In the former case, VAL is a 16-bit number with no
13781 defined signedness.
13783 TYPE is the type of the immediate field. USER_INSN_LENGTH
13784 is the length that the user requested, or 0 if none. */
13787 mips16_immed (const char *file, unsigned int line, int type,
13788 bfd_reloc_code_real_type reloc, offsetT val,
13789 unsigned int user_insn_length, unsigned long *insn)
13791 const struct mips_int_operand *operand;
13792 unsigned int uval, length;
13794 operand = mips16_immed_operand (type, FALSE);
13795 if (!mips16_immed_in_range_p (operand, reloc, val))
13797 /* We need an extended instruction. */
13798 if (user_insn_length == 2)
13799 as_bad_where (file, line, _("invalid unextended operand value"));
13801 *insn |= MIPS16_EXTEND;
13803 else if (user_insn_length == 4)
13805 /* The operand doesn't force an unextended instruction to be extended.
13806 Warn if the user wanted an extended instruction anyway. */
13807 *insn |= MIPS16_EXTEND;
13808 as_warn_where (file, line,
13809 _("extended operand requested but not required"));
13812 length = mips16_opcode_length (*insn);
13815 operand = mips16_immed_operand (type, TRUE);
13816 if (!mips16_immed_in_range_p (operand, reloc, val))
13817 as_bad_where (file, line,
13818 _("operand value out of range for instruction"));
13820 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13822 *insn = mips_insert_operand (&operand->root, *insn, uval);
13824 *insn |= mips16_immed_extend (uval, operand->root.size);
13827 struct percent_op_match
13830 bfd_reloc_code_real_type reloc;
13833 static const struct percent_op_match mips_percent_op[] =
13835 {"%lo", BFD_RELOC_LO16},
13836 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13837 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13838 {"%call16", BFD_RELOC_MIPS_CALL16},
13839 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13840 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13841 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13842 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13843 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13844 {"%got", BFD_RELOC_MIPS_GOT16},
13845 {"%gp_rel", BFD_RELOC_GPREL16},
13846 {"%half", BFD_RELOC_16},
13847 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13848 {"%higher", BFD_RELOC_MIPS_HIGHER},
13849 {"%neg", BFD_RELOC_MIPS_SUB},
13850 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13851 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13852 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13853 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13854 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13855 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13856 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13857 {"%hi", BFD_RELOC_HI16_S},
13858 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13859 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
13862 static const struct percent_op_match mips16_percent_op[] =
13864 {"%lo", BFD_RELOC_MIPS16_LO16},
13865 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13866 {"%got", BFD_RELOC_MIPS16_GOT16},
13867 {"%call16", BFD_RELOC_MIPS16_CALL16},
13868 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13869 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13870 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13871 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13872 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13873 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13874 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13875 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13879 /* Return true if *STR points to a relocation operator. When returning true,
13880 move *STR over the operator and store its relocation code in *RELOC.
13881 Leave both *STR and *RELOC alone when returning false. */
13884 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13886 const struct percent_op_match *percent_op;
13889 if (mips_opts.mips16)
13891 percent_op = mips16_percent_op;
13892 limit = ARRAY_SIZE (mips16_percent_op);
13896 percent_op = mips_percent_op;
13897 limit = ARRAY_SIZE (mips_percent_op);
13900 for (i = 0; i < limit; i++)
13901 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13903 int len = strlen (percent_op[i].str);
13905 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13908 *str += strlen (percent_op[i].str);
13909 *reloc = percent_op[i].reloc;
13911 /* Check whether the output BFD supports this relocation.
13912 If not, issue an error and fall back on something safe. */
13913 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13915 as_bad (_("relocation %s isn't supported by the current ABI"),
13916 percent_op[i].str);
13917 *reloc = BFD_RELOC_UNUSED;
13925 /* Parse string STR as a 16-bit relocatable operand. Store the
13926 expression in *EP and the relocations in the array starting
13927 at RELOC. Return the number of relocation operators used.
13929 On exit, EXPR_END points to the first character after the expression. */
13932 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13935 bfd_reloc_code_real_type reversed_reloc[3];
13936 size_t reloc_index, i;
13937 int crux_depth, str_depth;
13940 /* Search for the start of the main expression, recoding relocations
13941 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13942 of the main expression and with CRUX_DEPTH containing the number
13943 of open brackets at that point. */
13950 crux_depth = str_depth;
13952 /* Skip over whitespace and brackets, keeping count of the number
13954 while (*str == ' ' || *str == '\t' || *str == '(')
13959 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13960 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13962 my_getExpression (ep, crux);
13965 /* Match every open bracket. */
13966 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13970 if (crux_depth > 0)
13971 as_bad (_("unclosed '('"));
13975 if (reloc_index != 0)
13977 prev_reloc_op_frag = frag_now;
13978 for (i = 0; i < reloc_index; i++)
13979 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13982 return reloc_index;
13986 my_getExpression (expressionS *ep, char *str)
13990 save_in = input_line_pointer;
13991 input_line_pointer = str;
13993 expr_end = input_line_pointer;
13994 input_line_pointer = save_in;
13998 md_atof (int type, char *litP, int *sizeP)
14000 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14004 md_number_to_chars (char *buf, valueT val, int n)
14006 if (target_big_endian)
14007 number_to_chars_bigendian (buf, val, n);
14009 number_to_chars_littleendian (buf, val, n);
14012 static int support_64bit_objects(void)
14014 const char **list, **l;
14017 list = bfd_target_list ();
14018 for (l = list; *l != NULL; l++)
14019 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14020 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14022 yes = (*l != NULL);
14027 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14028 NEW_VALUE. Warn if another value was already specified. Note:
14029 we have to defer parsing the -march and -mtune arguments in order
14030 to handle 'from-abi' correctly, since the ABI might be specified
14031 in a later argument. */
14034 mips_set_option_string (const char **string_ptr, const char *new_value)
14036 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14037 as_warn (_("a different %s was already specified, is now %s"),
14038 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14041 *string_ptr = new_value;
14045 md_parse_option (int c, char *arg)
14049 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14050 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14052 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14053 c == mips_ases[i].option_on);
14059 case OPTION_CONSTRUCT_FLOATS:
14060 mips_disable_float_construction = 0;
14063 case OPTION_NO_CONSTRUCT_FLOATS:
14064 mips_disable_float_construction = 1;
14076 target_big_endian = 1;
14080 target_big_endian = 0;
14086 else if (arg[0] == '0')
14088 else if (arg[0] == '1')
14098 mips_debug = atoi (arg);
14102 file_mips_opts.isa = ISA_MIPS1;
14106 file_mips_opts.isa = ISA_MIPS2;
14110 file_mips_opts.isa = ISA_MIPS3;
14114 file_mips_opts.isa = ISA_MIPS4;
14118 file_mips_opts.isa = ISA_MIPS5;
14121 case OPTION_MIPS32:
14122 file_mips_opts.isa = ISA_MIPS32;
14125 case OPTION_MIPS32R2:
14126 file_mips_opts.isa = ISA_MIPS32R2;
14129 case OPTION_MIPS32R3:
14130 file_mips_opts.isa = ISA_MIPS32R3;
14133 case OPTION_MIPS32R5:
14134 file_mips_opts.isa = ISA_MIPS32R5;
14137 case OPTION_MIPS32R6:
14138 file_mips_opts.isa = ISA_MIPS32R6;
14141 case OPTION_MIPS64R2:
14142 file_mips_opts.isa = ISA_MIPS64R2;
14145 case OPTION_MIPS64R3:
14146 file_mips_opts.isa = ISA_MIPS64R3;
14149 case OPTION_MIPS64R5:
14150 file_mips_opts.isa = ISA_MIPS64R5;
14153 case OPTION_MIPS64R6:
14154 file_mips_opts.isa = ISA_MIPS64R6;
14157 case OPTION_MIPS64:
14158 file_mips_opts.isa = ISA_MIPS64;
14162 mips_set_option_string (&mips_tune_string, arg);
14166 mips_set_option_string (&mips_arch_string, arg);
14170 mips_set_option_string (&mips_arch_string, "4650");
14171 mips_set_option_string (&mips_tune_string, "4650");
14174 case OPTION_NO_M4650:
14178 mips_set_option_string (&mips_arch_string, "4010");
14179 mips_set_option_string (&mips_tune_string, "4010");
14182 case OPTION_NO_M4010:
14186 mips_set_option_string (&mips_arch_string, "4100");
14187 mips_set_option_string (&mips_tune_string, "4100");
14190 case OPTION_NO_M4100:
14194 mips_set_option_string (&mips_arch_string, "3900");
14195 mips_set_option_string (&mips_tune_string, "3900");
14198 case OPTION_NO_M3900:
14201 case OPTION_MICROMIPS:
14202 if (file_mips_opts.mips16 == 1)
14204 as_bad (_("-mmicromips cannot be used with -mips16"));
14207 file_mips_opts.micromips = 1;
14208 mips_no_prev_insn ();
14211 case OPTION_NO_MICROMIPS:
14212 file_mips_opts.micromips = 0;
14213 mips_no_prev_insn ();
14216 case OPTION_MIPS16:
14217 if (file_mips_opts.micromips == 1)
14219 as_bad (_("-mips16 cannot be used with -micromips"));
14222 file_mips_opts.mips16 = 1;
14223 mips_no_prev_insn ();
14226 case OPTION_NO_MIPS16:
14227 file_mips_opts.mips16 = 0;
14228 mips_no_prev_insn ();
14231 case OPTION_FIX_24K:
14235 case OPTION_NO_FIX_24K:
14239 case OPTION_FIX_RM7000:
14240 mips_fix_rm7000 = 1;
14243 case OPTION_NO_FIX_RM7000:
14244 mips_fix_rm7000 = 0;
14247 case OPTION_FIX_LOONGSON2F_JUMP:
14248 mips_fix_loongson2f_jump = TRUE;
14251 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14252 mips_fix_loongson2f_jump = FALSE;
14255 case OPTION_FIX_LOONGSON2F_NOP:
14256 mips_fix_loongson2f_nop = TRUE;
14259 case OPTION_NO_FIX_LOONGSON2F_NOP:
14260 mips_fix_loongson2f_nop = FALSE;
14263 case OPTION_FIX_VR4120:
14264 mips_fix_vr4120 = 1;
14267 case OPTION_NO_FIX_VR4120:
14268 mips_fix_vr4120 = 0;
14271 case OPTION_FIX_VR4130:
14272 mips_fix_vr4130 = 1;
14275 case OPTION_NO_FIX_VR4130:
14276 mips_fix_vr4130 = 0;
14279 case OPTION_FIX_CN63XXP1:
14280 mips_fix_cn63xxp1 = TRUE;
14283 case OPTION_NO_FIX_CN63XXP1:
14284 mips_fix_cn63xxp1 = FALSE;
14287 case OPTION_RELAX_BRANCH:
14288 mips_relax_branch = 1;
14291 case OPTION_NO_RELAX_BRANCH:
14292 mips_relax_branch = 0;
14295 case OPTION_INSN32:
14296 file_mips_opts.insn32 = TRUE;
14299 case OPTION_NO_INSN32:
14300 file_mips_opts.insn32 = FALSE;
14303 case OPTION_MSHARED:
14304 mips_in_shared = TRUE;
14307 case OPTION_MNO_SHARED:
14308 mips_in_shared = FALSE;
14311 case OPTION_MSYM32:
14312 file_mips_opts.sym32 = TRUE;
14315 case OPTION_MNO_SYM32:
14316 file_mips_opts.sym32 = FALSE;
14319 /* When generating ELF code, we permit -KPIC and -call_shared to
14320 select SVR4_PIC, and -non_shared to select no PIC. This is
14321 intended to be compatible with Irix 5. */
14322 case OPTION_CALL_SHARED:
14323 mips_pic = SVR4_PIC;
14324 mips_abicalls = TRUE;
14327 case OPTION_CALL_NONPIC:
14329 mips_abicalls = TRUE;
14332 case OPTION_NON_SHARED:
14334 mips_abicalls = FALSE;
14337 /* The -xgot option tells the assembler to use 32 bit offsets
14338 when accessing the got in SVR4_PIC mode. It is for Irix
14345 g_switch_value = atoi (arg);
14349 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14352 mips_abi = O32_ABI;
14356 mips_abi = N32_ABI;
14360 mips_abi = N64_ABI;
14361 if (!support_64bit_objects())
14362 as_fatal (_("no compiled in support for 64 bit object file format"));
14366 file_mips_opts.gp = 32;
14370 file_mips_opts.gp = 64;
14374 file_mips_opts.fp = 32;
14378 file_mips_opts.fp = 0;
14382 file_mips_opts.fp = 64;
14385 case OPTION_ODD_SPREG:
14386 file_mips_opts.oddspreg = 1;
14389 case OPTION_NO_ODD_SPREG:
14390 file_mips_opts.oddspreg = 0;
14393 case OPTION_SINGLE_FLOAT:
14394 file_mips_opts.single_float = 1;
14397 case OPTION_DOUBLE_FLOAT:
14398 file_mips_opts.single_float = 0;
14401 case OPTION_SOFT_FLOAT:
14402 file_mips_opts.soft_float = 1;
14405 case OPTION_HARD_FLOAT:
14406 file_mips_opts.soft_float = 0;
14410 if (strcmp (arg, "32") == 0)
14411 mips_abi = O32_ABI;
14412 else if (strcmp (arg, "o64") == 0)
14413 mips_abi = O64_ABI;
14414 else if (strcmp (arg, "n32") == 0)
14415 mips_abi = N32_ABI;
14416 else if (strcmp (arg, "64") == 0)
14418 mips_abi = N64_ABI;
14419 if (! support_64bit_objects())
14420 as_fatal (_("no compiled in support for 64 bit object file "
14423 else if (strcmp (arg, "eabi") == 0)
14424 mips_abi = EABI_ABI;
14427 as_fatal (_("invalid abi -mabi=%s"), arg);
14432 case OPTION_M7000_HILO_FIX:
14433 mips_7000_hilo_fix = TRUE;
14436 case OPTION_MNO_7000_HILO_FIX:
14437 mips_7000_hilo_fix = FALSE;
14440 case OPTION_MDEBUG:
14441 mips_flag_mdebug = TRUE;
14444 case OPTION_NO_MDEBUG:
14445 mips_flag_mdebug = FALSE;
14449 mips_flag_pdr = TRUE;
14452 case OPTION_NO_PDR:
14453 mips_flag_pdr = FALSE;
14456 case OPTION_MVXWORKS_PIC:
14457 mips_pic = VXWORKS_PIC;
14461 if (strcmp (arg, "2008") == 0)
14463 else if (strcmp (arg, "legacy") == 0)
14467 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14476 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14481 /* Set up globals to tune for the ISA or processor described by INFO. */
14484 mips_set_tune (const struct mips_cpu_info *info)
14487 mips_tune = info->cpu;
14492 mips_after_parse_args (void)
14494 const struct mips_cpu_info *arch_info = 0;
14495 const struct mips_cpu_info *tune_info = 0;
14497 /* GP relative stuff not working for PE */
14498 if (strncmp (TARGET_OS, "pe", 2) == 0)
14500 if (g_switch_seen && g_switch_value != 0)
14501 as_bad (_("-G not supported in this configuration"));
14502 g_switch_value = 0;
14505 if (mips_abi == NO_ABI)
14506 mips_abi = MIPS_DEFAULT_ABI;
14508 /* The following code determines the architecture.
14509 Similar code was added to GCC 3.3 (see override_options() in
14510 config/mips/mips.c). The GAS and GCC code should be kept in sync
14511 as much as possible. */
14513 if (mips_arch_string != 0)
14514 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14516 if (file_mips_opts.isa != ISA_UNKNOWN)
14518 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14519 ISA level specified by -mipsN, while arch_info->isa contains
14520 the -march selection (if any). */
14521 if (arch_info != 0)
14523 /* -march takes precedence over -mipsN, since it is more descriptive.
14524 There's no harm in specifying both as long as the ISA levels
14526 if (file_mips_opts.isa != arch_info->isa)
14527 as_bad (_("-%s conflicts with the other architecture options,"
14528 " which imply -%s"),
14529 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14530 mips_cpu_info_from_isa (arch_info->isa)->name);
14533 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14536 if (arch_info == 0)
14538 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14539 gas_assert (arch_info);
14542 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14543 as_bad (_("-march=%s is not compatible with the selected ABI"),
14546 file_mips_opts.arch = arch_info->cpu;
14547 file_mips_opts.isa = arch_info->isa;
14549 /* Set up initial mips_opts state. */
14550 mips_opts = file_mips_opts;
14552 /* The register size inference code is now placed in
14553 file_mips_check_options. */
14555 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14557 if (mips_tune_string != 0)
14558 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14560 if (tune_info == 0)
14561 mips_set_tune (arch_info);
14563 mips_set_tune (tune_info);
14565 if (mips_flag_mdebug < 0)
14566 mips_flag_mdebug = 0;
14570 mips_init_after_args (void)
14572 /* initialize opcodes */
14573 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14574 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14578 md_pcrel_from (fixS *fixP)
14580 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14581 switch (fixP->fx_r_type)
14583 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14584 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14585 /* Return the address of the delay slot. */
14588 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14589 case BFD_RELOC_MICROMIPS_JMP:
14590 case BFD_RELOC_16_PCREL_S2:
14591 case BFD_RELOC_MIPS_21_PCREL_S2:
14592 case BFD_RELOC_MIPS_26_PCREL_S2:
14593 case BFD_RELOC_MIPS_JMP:
14594 /* Return the address of the delay slot. */
14602 /* This is called before the symbol table is processed. In order to
14603 work with gcc when using mips-tfile, we must keep all local labels.
14604 However, in other cases, we want to discard them. If we were
14605 called with -g, but we didn't see any debugging information, it may
14606 mean that gcc is smuggling debugging information through to
14607 mips-tfile, in which case we must generate all local labels. */
14610 mips_frob_file_before_adjust (void)
14612 #ifndef NO_ECOFF_DEBUGGING
14613 if (ECOFF_DEBUGGING
14615 && ! ecoff_debugging_seen)
14616 flag_keep_locals = 1;
14620 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14621 the corresponding LO16 reloc. This is called before md_apply_fix and
14622 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14623 relocation operators.
14625 For our purposes, a %lo() expression matches a %got() or %hi()
14628 (a) it refers to the same symbol; and
14629 (b) the offset applied in the %lo() expression is no lower than
14630 the offset applied in the %got() or %hi().
14632 (b) allows us to cope with code like:
14635 lh $4,%lo(foo+2)($4)
14637 ...which is legal on RELA targets, and has a well-defined behaviour
14638 if the user knows that adding 2 to "foo" will not induce a carry to
14641 When several %lo()s match a particular %got() or %hi(), we use the
14642 following rules to distinguish them:
14644 (1) %lo()s with smaller offsets are a better match than %lo()s with
14647 (2) %lo()s with no matching %got() or %hi() are better than those
14648 that already have a matching %got() or %hi().
14650 (3) later %lo()s are better than earlier %lo()s.
14652 These rules are applied in order.
14654 (1) means, among other things, that %lo()s with identical offsets are
14655 chosen if they exist.
14657 (2) means that we won't associate several high-part relocations with
14658 the same low-part relocation unless there's no alternative. Having
14659 several high parts for the same low part is a GNU extension; this rule
14660 allows careful users to avoid it.
14662 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14663 with the last high-part relocation being at the front of the list.
14664 It therefore makes sense to choose the last matching low-part
14665 relocation, all other things being equal. It's also easier
14666 to code that way. */
14669 mips_frob_file (void)
14671 struct mips_hi_fixup *l;
14672 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14674 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14676 segment_info_type *seginfo;
14677 bfd_boolean matched_lo_p;
14678 fixS **hi_pos, **lo_pos, **pos;
14680 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14682 /* If a GOT16 relocation turns out to be against a global symbol,
14683 there isn't supposed to be a matching LO. Ignore %gots against
14684 constants; we'll report an error for those later. */
14685 if (got16_reloc_p (l->fixp->fx_r_type)
14686 && !(l->fixp->fx_addsy
14687 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14690 /* Check quickly whether the next fixup happens to be a matching %lo. */
14691 if (fixup_has_matching_lo_p (l->fixp))
14694 seginfo = seg_info (l->seg);
14696 /* Set HI_POS to the position of this relocation in the chain.
14697 Set LO_POS to the position of the chosen low-part relocation.
14698 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14699 relocation that matches an immediately-preceding high-part
14703 matched_lo_p = FALSE;
14704 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14706 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14708 if (*pos == l->fixp)
14711 if ((*pos)->fx_r_type == looking_for_rtype
14712 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14713 && (*pos)->fx_offset >= l->fixp->fx_offset
14715 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14717 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14720 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14721 && fixup_has_matching_lo_p (*pos));
14724 /* If we found a match, remove the high-part relocation from its
14725 current position and insert it before the low-part relocation.
14726 Make the offsets match so that fixup_has_matching_lo_p()
14729 We don't warn about unmatched high-part relocations since some
14730 versions of gcc have been known to emit dead "lui ...%hi(...)"
14732 if (lo_pos != NULL)
14734 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14735 if (l->fixp->fx_next != *lo_pos)
14737 *hi_pos = l->fixp->fx_next;
14738 l->fixp->fx_next = *lo_pos;
14746 mips_force_relocation (fixS *fixp)
14748 if (generic_force_reloc (fixp))
14751 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14752 so that the linker relaxation can update targets. */
14753 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14754 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14755 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14758 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14759 if (ISA_IS_R6 (mips_opts.isa)
14760 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14761 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14762 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14763 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14764 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14765 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14766 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14772 /* Read the instruction associated with RELOC from BUF. */
14774 static unsigned int
14775 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14777 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14778 return read_compressed_insn (buf, 4);
14780 return read_insn (buf);
14783 /* Write instruction INSN to BUF, given that it has been relocated
14787 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14788 unsigned long insn)
14790 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14791 write_compressed_insn (buf, insn, 4);
14793 write_insn (buf, insn);
14796 /* Apply a fixup to the object file. */
14799 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14802 unsigned long insn;
14803 reloc_howto_type *howto;
14805 if (fixP->fx_pcrel)
14806 switch (fixP->fx_r_type)
14808 case BFD_RELOC_16_PCREL_S2:
14809 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14810 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14811 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14812 case BFD_RELOC_32_PCREL:
14813 case BFD_RELOC_MIPS_21_PCREL_S2:
14814 case BFD_RELOC_MIPS_26_PCREL_S2:
14815 case BFD_RELOC_MIPS_18_PCREL_S3:
14816 case BFD_RELOC_MIPS_19_PCREL_S2:
14817 case BFD_RELOC_HI16_S_PCREL:
14818 case BFD_RELOC_LO16_PCREL:
14822 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14826 as_bad_where (fixP->fx_file, fixP->fx_line,
14827 _("PC-relative reference to a different section"));
14831 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14832 that have no MIPS ELF equivalent. */
14833 if (fixP->fx_r_type != BFD_RELOC_8)
14835 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14840 gas_assert (fixP->fx_size == 2
14841 || fixP->fx_size == 4
14842 || fixP->fx_r_type == BFD_RELOC_8
14843 || fixP->fx_r_type == BFD_RELOC_16
14844 || fixP->fx_r_type == BFD_RELOC_64
14845 || fixP->fx_r_type == BFD_RELOC_CTOR
14846 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14847 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14848 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14849 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14850 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
14851 || fixP->fx_r_type == BFD_RELOC_NONE);
14853 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14855 /* Don't treat parts of a composite relocation as done. There are two
14858 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14859 should nevertheless be emitted if the first part is.
14861 (2) In normal usage, composite relocations are never assembly-time
14862 constants. The easiest way of dealing with the pathological
14863 exceptions is to generate a relocation against STN_UNDEF and
14864 leave everything up to the linker. */
14865 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14868 switch (fixP->fx_r_type)
14870 case BFD_RELOC_MIPS_TLS_GD:
14871 case BFD_RELOC_MIPS_TLS_LDM:
14872 case BFD_RELOC_MIPS_TLS_DTPREL32:
14873 case BFD_RELOC_MIPS_TLS_DTPREL64:
14874 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14875 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14876 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14877 case BFD_RELOC_MIPS_TLS_TPREL32:
14878 case BFD_RELOC_MIPS_TLS_TPREL64:
14879 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14880 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14881 case BFD_RELOC_MICROMIPS_TLS_GD:
14882 case BFD_RELOC_MICROMIPS_TLS_LDM:
14883 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14884 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14885 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14886 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14887 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14888 case BFD_RELOC_MIPS16_TLS_GD:
14889 case BFD_RELOC_MIPS16_TLS_LDM:
14890 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14891 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14892 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14893 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14894 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14895 if (!fixP->fx_addsy)
14897 as_bad_where (fixP->fx_file, fixP->fx_line,
14898 _("TLS relocation against a constant"));
14901 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14904 case BFD_RELOC_MIPS_JMP:
14905 case BFD_RELOC_MIPS_SHIFT5:
14906 case BFD_RELOC_MIPS_SHIFT6:
14907 case BFD_RELOC_MIPS_GOT_DISP:
14908 case BFD_RELOC_MIPS_GOT_PAGE:
14909 case BFD_RELOC_MIPS_GOT_OFST:
14910 case BFD_RELOC_MIPS_SUB:
14911 case BFD_RELOC_MIPS_INSERT_A:
14912 case BFD_RELOC_MIPS_INSERT_B:
14913 case BFD_RELOC_MIPS_DELETE:
14914 case BFD_RELOC_MIPS_HIGHEST:
14915 case BFD_RELOC_MIPS_HIGHER:
14916 case BFD_RELOC_MIPS_SCN_DISP:
14917 case BFD_RELOC_MIPS_REL16:
14918 case BFD_RELOC_MIPS_RELGOT:
14919 case BFD_RELOC_MIPS_JALR:
14920 case BFD_RELOC_HI16:
14921 case BFD_RELOC_HI16_S:
14922 case BFD_RELOC_LO16:
14923 case BFD_RELOC_GPREL16:
14924 case BFD_RELOC_MIPS_LITERAL:
14925 case BFD_RELOC_MIPS_CALL16:
14926 case BFD_RELOC_MIPS_GOT16:
14927 case BFD_RELOC_GPREL32:
14928 case BFD_RELOC_MIPS_GOT_HI16:
14929 case BFD_RELOC_MIPS_GOT_LO16:
14930 case BFD_RELOC_MIPS_CALL_HI16:
14931 case BFD_RELOC_MIPS_CALL_LO16:
14932 case BFD_RELOC_MIPS16_GPREL:
14933 case BFD_RELOC_MIPS16_GOT16:
14934 case BFD_RELOC_MIPS16_CALL16:
14935 case BFD_RELOC_MIPS16_HI16:
14936 case BFD_RELOC_MIPS16_HI16_S:
14937 case BFD_RELOC_MIPS16_LO16:
14938 case BFD_RELOC_MIPS16_JMP:
14939 case BFD_RELOC_MICROMIPS_JMP:
14940 case BFD_RELOC_MICROMIPS_GOT_DISP:
14941 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14942 case BFD_RELOC_MICROMIPS_GOT_OFST:
14943 case BFD_RELOC_MICROMIPS_SUB:
14944 case BFD_RELOC_MICROMIPS_HIGHEST:
14945 case BFD_RELOC_MICROMIPS_HIGHER:
14946 case BFD_RELOC_MICROMIPS_SCN_DISP:
14947 case BFD_RELOC_MICROMIPS_JALR:
14948 case BFD_RELOC_MICROMIPS_HI16:
14949 case BFD_RELOC_MICROMIPS_HI16_S:
14950 case BFD_RELOC_MICROMIPS_LO16:
14951 case BFD_RELOC_MICROMIPS_GPREL16:
14952 case BFD_RELOC_MICROMIPS_LITERAL:
14953 case BFD_RELOC_MICROMIPS_CALL16:
14954 case BFD_RELOC_MICROMIPS_GOT16:
14955 case BFD_RELOC_MICROMIPS_GOT_HI16:
14956 case BFD_RELOC_MICROMIPS_GOT_LO16:
14957 case BFD_RELOC_MICROMIPS_CALL_HI16:
14958 case BFD_RELOC_MICROMIPS_CALL_LO16:
14959 case BFD_RELOC_MIPS_EH:
14964 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14966 insn = read_reloc_insn (buf, fixP->fx_r_type);
14967 if (mips16_reloc_p (fixP->fx_r_type))
14968 insn |= mips16_immed_extend (value, 16);
14970 insn |= (value & 0xffff);
14971 write_reloc_insn (buf, fixP->fx_r_type, insn);
14974 as_bad_where (fixP->fx_file, fixP->fx_line,
14975 _("unsupported constant in relocation"));
14980 /* This is handled like BFD_RELOC_32, but we output a sign
14981 extended value if we are only 32 bits. */
14984 if (8 <= sizeof (valueT))
14985 md_number_to_chars (buf, *valP, 8);
14990 if ((*valP & 0x80000000) != 0)
14994 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14995 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15000 case BFD_RELOC_RVA:
15002 case BFD_RELOC_32_PCREL:
15005 /* If we are deleting this reloc entry, we must fill in the
15006 value now. This can happen if we have a .word which is not
15007 resolved when it appears but is later defined. */
15009 md_number_to_chars (buf, *valP, fixP->fx_size);
15012 case BFD_RELOC_MIPS_21_PCREL_S2:
15013 case BFD_RELOC_MIPS_26_PCREL_S2:
15014 if ((*valP & 0x3) != 0)
15015 as_bad_where (fixP->fx_file, fixP->fx_line,
15016 _("branch to misaligned address (%lx)"), (long) *valP);
15018 gas_assert (!fixP->fx_done);
15021 case BFD_RELOC_MIPS_18_PCREL_S3:
15022 if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15023 as_bad_where (fixP->fx_file, fixP->fx_line,
15024 _("PC-relative access using misaligned symbol (%lx)"),
15025 (long) S_GET_VALUE (fixP->fx_addsy));
15026 if ((fixP->fx_offset & 0x7) != 0)
15027 as_bad_where (fixP->fx_file, fixP->fx_line,
15028 _("PC-relative access using misaligned offset (%lx)"),
15029 (long) fixP->fx_offset);
15031 gas_assert (!fixP->fx_done);
15034 case BFD_RELOC_MIPS_19_PCREL_S2:
15035 if ((*valP & 0x3) != 0)
15036 as_bad_where (fixP->fx_file, fixP->fx_line,
15037 _("PC-relative access to misaligned address (%lx)"),
15038 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15040 gas_assert (!fixP->fx_done);
15043 case BFD_RELOC_HI16_S_PCREL:
15044 case BFD_RELOC_LO16_PCREL:
15045 gas_assert (!fixP->fx_done);
15048 case BFD_RELOC_16_PCREL_S2:
15049 if ((*valP & 0x3) != 0)
15050 as_bad_where (fixP->fx_file, fixP->fx_line,
15051 _("branch to misaligned address (%lx)"), (long) *valP);
15053 /* We need to save the bits in the instruction since fixup_segment()
15054 might be deleting the relocation entry (i.e., a branch within
15055 the current segment). */
15056 if (! fixP->fx_done)
15059 /* Update old instruction data. */
15060 insn = read_insn (buf);
15062 if (*valP + 0x20000 <= 0x3ffff)
15064 insn |= (*valP >> 2) & 0xffff;
15065 write_insn (buf, insn);
15067 else if (mips_pic == NO_PIC
15069 && fixP->fx_frag->fr_address >= text_section->vma
15070 && (fixP->fx_frag->fr_address
15071 < text_section->vma + bfd_get_section_size (text_section))
15072 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15073 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15074 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15076 /* The branch offset is too large. If this is an
15077 unconditional branch, and we are not generating PIC code,
15078 we can convert it to an absolute jump instruction. */
15079 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15080 insn = 0x0c000000; /* jal */
15082 insn = 0x08000000; /* j */
15083 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15085 fixP->fx_addsy = section_symbol (text_section);
15086 *valP += md_pcrel_from (fixP);
15087 write_insn (buf, insn);
15091 /* If we got here, we have branch-relaxation disabled,
15092 and there's nothing we can do to fix this instruction
15093 without turning it into a longer sequence. */
15094 as_bad_where (fixP->fx_file, fixP->fx_line,
15095 _("branch out of range"));
15099 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15100 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15101 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15102 /* We adjust the offset back to even. */
15103 if ((*valP & 0x1) != 0)
15106 if (! fixP->fx_done)
15109 /* Should never visit here, because we keep the relocation. */
15113 case BFD_RELOC_VTABLE_INHERIT:
15116 && !S_IS_DEFINED (fixP->fx_addsy)
15117 && !S_IS_WEAK (fixP->fx_addsy))
15118 S_SET_WEAK (fixP->fx_addsy);
15121 case BFD_RELOC_NONE:
15122 case BFD_RELOC_VTABLE_ENTRY:
15130 /* Remember value for tc_gen_reloc. */
15131 fixP->fx_addnumber = *valP;
15141 c = get_symbol_name (&name);
15142 p = (symbolS *) symbol_find_or_make (name);
15143 (void) restore_line_pointer (c);
15147 /* Align the current frag to a given power of two. If a particular
15148 fill byte should be used, FILL points to an integer that contains
15149 that byte, otherwise FILL is null.
15151 This function used to have the comment:
15153 The MIPS assembler also automatically adjusts any preceding label.
15155 The implementation therefore applied the adjustment to a maximum of
15156 one label. However, other label adjustments are applied to batches
15157 of labels, and adjusting just one caused problems when new labels
15158 were added for the sake of debugging or unwind information.
15159 We therefore adjust all preceding labels (given as LABELS) instead. */
15162 mips_align (int to, int *fill, struct insn_label_list *labels)
15164 mips_emit_delays ();
15165 mips_record_compressed_mode ();
15166 if (fill == NULL && subseg_text_p (now_seg))
15167 frag_align_code (to, 0);
15169 frag_align (to, fill ? *fill : 0, 0);
15170 record_alignment (now_seg, to);
15171 mips_move_labels (labels, FALSE);
15174 /* Align to a given power of two. .align 0 turns off the automatic
15175 alignment used by the data creating pseudo-ops. */
15178 s_align (int x ATTRIBUTE_UNUSED)
15180 int temp, fill_value, *fill_ptr;
15181 long max_alignment = 28;
15183 /* o Note that the assembler pulls down any immediately preceding label
15184 to the aligned address.
15185 o It's not documented but auto alignment is reinstated by
15186 a .align pseudo instruction.
15187 o Note also that after auto alignment is turned off the mips assembler
15188 issues an error on attempt to assemble an improperly aligned data item.
15191 temp = get_absolute_expression ();
15192 if (temp > max_alignment)
15193 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15196 as_warn (_("alignment negative, 0 assumed"));
15199 if (*input_line_pointer == ',')
15201 ++input_line_pointer;
15202 fill_value = get_absolute_expression ();
15203 fill_ptr = &fill_value;
15209 segment_info_type *si = seg_info (now_seg);
15210 struct insn_label_list *l = si->label_list;
15211 /* Auto alignment should be switched on by next section change. */
15213 mips_align (temp, fill_ptr, l);
15220 demand_empty_rest_of_line ();
15224 s_change_sec (int sec)
15228 /* The ELF backend needs to know that we are changing sections, so
15229 that .previous works correctly. We could do something like check
15230 for an obj_section_change_hook macro, but that might be confusing
15231 as it would not be appropriate to use it in the section changing
15232 functions in read.c, since obj-elf.c intercepts those. FIXME:
15233 This should be cleaner, somehow. */
15234 obj_elf_section_change_hook ();
15236 mips_emit_delays ();
15247 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15248 demand_empty_rest_of_line ();
15252 seg = subseg_new (RDATA_SECTION_NAME,
15253 (subsegT) get_absolute_expression ());
15254 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15255 | SEC_READONLY | SEC_RELOC
15257 if (strncmp (TARGET_OS, "elf", 3) != 0)
15258 record_alignment (seg, 4);
15259 demand_empty_rest_of_line ();
15263 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15264 bfd_set_section_flags (stdoutput, seg,
15265 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15266 if (strncmp (TARGET_OS, "elf", 3) != 0)
15267 record_alignment (seg, 4);
15268 demand_empty_rest_of_line ();
15272 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15273 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15274 if (strncmp (TARGET_OS, "elf", 3) != 0)
15275 record_alignment (seg, 4);
15276 demand_empty_rest_of_line ();
15284 s_change_section (int ignore ATTRIBUTE_UNUSED)
15287 char *section_name;
15292 int section_entry_size;
15293 int section_alignment;
15295 saved_ilp = input_line_pointer;
15296 endc = get_symbol_name (§ion_name);
15297 c = (endc == '"' ? input_line_pointer[1] : endc);
15299 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15301 /* Do we have .section Name<,"flags">? */
15302 if (c != ',' || (c == ',' && next_c == '"'))
15304 /* Just after name is now '\0'. */
15305 (void) restore_line_pointer (endc);
15306 input_line_pointer = saved_ilp;
15307 obj_elf_section (ignore);
15311 section_name = xstrdup (section_name);
15312 c = restore_line_pointer (endc);
15314 input_line_pointer++;
15316 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15318 section_type = get_absolute_expression ();
15322 if (*input_line_pointer++ == ',')
15323 section_flag = get_absolute_expression ();
15327 if (*input_line_pointer++ == ',')
15328 section_entry_size = get_absolute_expression ();
15330 section_entry_size = 0;
15332 if (*input_line_pointer++ == ',')
15333 section_alignment = get_absolute_expression ();
15335 section_alignment = 0;
15337 /* FIXME: really ignore? */
15338 (void) section_alignment;
15340 /* When using the generic form of .section (as implemented by obj-elf.c),
15341 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15342 traditionally had to fall back on the more common @progbits instead.
15344 There's nothing really harmful in this, since bfd will correct
15345 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15346 means that, for backwards compatibility, the special_section entries
15347 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15349 Even so, we shouldn't force users of the MIPS .section syntax to
15350 incorrectly label the sections as SHT_PROGBITS. The best compromise
15351 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15352 generic type-checking code. */
15353 if (section_type == SHT_MIPS_DWARF)
15354 section_type = SHT_PROGBITS;
15356 obj_elf_change_section (section_name, section_type, section_flag,
15357 section_entry_size, 0, 0, 0);
15359 if (now_seg->name != section_name)
15360 free (section_name);
15364 mips_enable_auto_align (void)
15370 s_cons (int log_size)
15372 segment_info_type *si = seg_info (now_seg);
15373 struct insn_label_list *l = si->label_list;
15375 mips_emit_delays ();
15376 if (log_size > 0 && auto_align)
15377 mips_align (log_size, 0, l);
15378 cons (1 << log_size);
15379 mips_clear_insn_labels ();
15383 s_float_cons (int type)
15385 segment_info_type *si = seg_info (now_seg);
15386 struct insn_label_list *l = si->label_list;
15388 mips_emit_delays ();
15393 mips_align (3, 0, l);
15395 mips_align (2, 0, l);
15399 mips_clear_insn_labels ();
15402 /* Handle .globl. We need to override it because on Irix 5 you are
15405 where foo is an undefined symbol, to mean that foo should be
15406 considered to be the address of a function. */
15409 s_mips_globl (int x ATTRIBUTE_UNUSED)
15418 c = get_symbol_name (&name);
15419 symbolP = symbol_find_or_make (name);
15420 S_SET_EXTERNAL (symbolP);
15422 *input_line_pointer = c;
15423 SKIP_WHITESPACE_AFTER_NAME ();
15425 /* On Irix 5, every global symbol that is not explicitly labelled as
15426 being a function is apparently labelled as being an object. */
15429 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15430 && (*input_line_pointer != ','))
15435 c = get_symbol_name (&secname);
15436 sec = bfd_get_section_by_name (stdoutput, secname);
15438 as_bad (_("%s: no such section"), secname);
15439 (void) restore_line_pointer (c);
15441 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15442 flag = BSF_FUNCTION;
15445 symbol_get_bfdsym (symbolP)->flags |= flag;
15447 c = *input_line_pointer;
15450 input_line_pointer++;
15451 SKIP_WHITESPACE ();
15452 if (is_end_of_line[(unsigned char) *input_line_pointer])
15458 demand_empty_rest_of_line ();
15462 s_option (int x ATTRIBUTE_UNUSED)
15467 c = get_symbol_name (&opt);
15471 /* FIXME: What does this mean? */
15473 else if (strncmp (opt, "pic", 3) == 0)
15477 i = atoi (opt + 3);
15482 mips_pic = SVR4_PIC;
15483 mips_abicalls = TRUE;
15486 as_bad (_(".option pic%d not supported"), i);
15488 if (mips_pic == SVR4_PIC)
15490 if (g_switch_seen && g_switch_value != 0)
15491 as_warn (_("-G may not be used with SVR4 PIC code"));
15492 g_switch_value = 0;
15493 bfd_set_gp_size (stdoutput, 0);
15497 as_warn (_("unrecognized option \"%s\""), opt);
15499 (void) restore_line_pointer (c);
15500 demand_empty_rest_of_line ();
15503 /* This structure is used to hold a stack of .set values. */
15505 struct mips_option_stack
15507 struct mips_option_stack *next;
15508 struct mips_set_options options;
15511 static struct mips_option_stack *mips_opts_stack;
15514 parse_code_option (char * name)
15516 const struct mips_ase *ase;
15517 if (strncmp (name, "at=", 3) == 0)
15519 char *s = name + 3;
15521 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15522 as_bad (_("unrecognized register name `%s'"), s);
15524 else if (strcmp (name, "at") == 0)
15525 mips_opts.at = ATREG;
15526 else if (strcmp (name, "noat") == 0)
15527 mips_opts.at = ZERO;
15528 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15529 mips_opts.nomove = 0;
15530 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15531 mips_opts.nomove = 1;
15532 else if (strcmp (name, "bopt") == 0)
15533 mips_opts.nobopt = 0;
15534 else if (strcmp (name, "nobopt") == 0)
15535 mips_opts.nobopt = 1;
15536 else if (strcmp (name, "gp=32") == 0)
15538 else if (strcmp (name, "gp=64") == 0)
15540 else if (strcmp (name, "fp=32") == 0)
15542 else if (strcmp (name, "fp=xx") == 0)
15544 else if (strcmp (name, "fp=64") == 0)
15546 else if (strcmp (name, "softfloat") == 0)
15547 mips_opts.soft_float = 1;
15548 else if (strcmp (name, "hardfloat") == 0)
15549 mips_opts.soft_float = 0;
15550 else if (strcmp (name, "singlefloat") == 0)
15551 mips_opts.single_float = 1;
15552 else if (strcmp (name, "doublefloat") == 0)
15553 mips_opts.single_float = 0;
15554 else if (strcmp (name, "nooddspreg") == 0)
15555 mips_opts.oddspreg = 0;
15556 else if (strcmp (name, "oddspreg") == 0)
15557 mips_opts.oddspreg = 1;
15558 else if (strcmp (name, "mips16") == 0
15559 || strcmp (name, "MIPS-16") == 0)
15560 mips_opts.mips16 = 1;
15561 else if (strcmp (name, "nomips16") == 0
15562 || strcmp (name, "noMIPS-16") == 0)
15563 mips_opts.mips16 = 0;
15564 else if (strcmp (name, "micromips") == 0)
15565 mips_opts.micromips = 1;
15566 else if (strcmp (name, "nomicromips") == 0)
15567 mips_opts.micromips = 0;
15568 else if (name[0] == 'n'
15570 && (ase = mips_lookup_ase (name + 2)))
15571 mips_set_ase (ase, &mips_opts, FALSE);
15572 else if ((ase = mips_lookup_ase (name)))
15573 mips_set_ase (ase, &mips_opts, TRUE);
15574 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15576 /* Permit the user to change the ISA and architecture on the fly.
15577 Needless to say, misuse can cause serious problems. */
15578 if (strncmp (name, "arch=", 5) == 0)
15580 const struct mips_cpu_info *p;
15582 p = mips_parse_cpu ("internal use", name + 5);
15584 as_bad (_("unknown architecture %s"), name + 5);
15587 mips_opts.arch = p->cpu;
15588 mips_opts.isa = p->isa;
15591 else if (strncmp (name, "mips", 4) == 0)
15593 const struct mips_cpu_info *p;
15595 p = mips_parse_cpu ("internal use", name);
15597 as_bad (_("unknown ISA level %s"), name + 4);
15600 mips_opts.arch = p->cpu;
15601 mips_opts.isa = p->isa;
15605 as_bad (_("unknown ISA or architecture %s"), name);
15607 else if (strcmp (name, "autoextend") == 0)
15608 mips_opts.noautoextend = 0;
15609 else if (strcmp (name, "noautoextend") == 0)
15610 mips_opts.noautoextend = 1;
15611 else if (strcmp (name, "insn32") == 0)
15612 mips_opts.insn32 = TRUE;
15613 else if (strcmp (name, "noinsn32") == 0)
15614 mips_opts.insn32 = FALSE;
15615 else if (strcmp (name, "sym32") == 0)
15616 mips_opts.sym32 = TRUE;
15617 else if (strcmp (name, "nosym32") == 0)
15618 mips_opts.sym32 = FALSE;
15624 /* Handle the .set pseudo-op. */
15627 s_mipsset (int x ATTRIBUTE_UNUSED)
15629 char *name = input_line_pointer, ch;
15630 int prev_isa = mips_opts.isa;
15632 file_mips_check_options ();
15634 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15635 ++input_line_pointer;
15636 ch = *input_line_pointer;
15637 *input_line_pointer = '\0';
15639 if (strchr (name, ','))
15641 /* Generic ".set" directive; use the generic handler. */
15642 *input_line_pointer = ch;
15643 input_line_pointer = name;
15648 if (strcmp (name, "reorder") == 0)
15650 if (mips_opts.noreorder)
15653 else if (strcmp (name, "noreorder") == 0)
15655 if (!mips_opts.noreorder)
15656 start_noreorder ();
15658 else if (strcmp (name, "macro") == 0)
15659 mips_opts.warn_about_macros = 0;
15660 else if (strcmp (name, "nomacro") == 0)
15662 if (mips_opts.noreorder == 0)
15663 as_bad (_("`noreorder' must be set before `nomacro'"));
15664 mips_opts.warn_about_macros = 1;
15666 else if (strcmp (name, "gp=default") == 0)
15667 mips_opts.gp = file_mips_opts.gp;
15668 else if (strcmp (name, "fp=default") == 0)
15669 mips_opts.fp = file_mips_opts.fp;
15670 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15672 mips_opts.isa = file_mips_opts.isa;
15673 mips_opts.arch = file_mips_opts.arch;
15674 mips_opts.gp = file_mips_opts.gp;
15675 mips_opts.fp = file_mips_opts.fp;
15677 else if (strcmp (name, "push") == 0)
15679 struct mips_option_stack *s;
15681 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15682 s->next = mips_opts_stack;
15683 s->options = mips_opts;
15684 mips_opts_stack = s;
15686 else if (strcmp (name, "pop") == 0)
15688 struct mips_option_stack *s;
15690 s = mips_opts_stack;
15692 as_bad (_(".set pop with no .set push"));
15695 /* If we're changing the reorder mode we need to handle
15696 delay slots correctly. */
15697 if (s->options.noreorder && ! mips_opts.noreorder)
15698 start_noreorder ();
15699 else if (! s->options.noreorder && mips_opts.noreorder)
15702 mips_opts = s->options;
15703 mips_opts_stack = s->next;
15707 else if (!parse_code_option (name))
15708 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15710 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15711 registers based on what is supported by the arch/cpu. */
15712 if (mips_opts.isa != prev_isa)
15714 switch (mips_opts.isa)
15719 /* MIPS I cannot support FPXX. */
15721 /* fall-through. */
15728 if (mips_opts.fp != 0)
15744 if (mips_opts.fp != 0)
15746 if (mips_opts.arch == CPU_R5900)
15753 as_bad (_("unknown ISA level %s"), name + 4);
15758 mips_check_options (&mips_opts, FALSE);
15760 mips_check_isa_supports_ases ();
15761 *input_line_pointer = ch;
15762 demand_empty_rest_of_line ();
15765 /* Handle the .module pseudo-op. */
15768 s_module (int ignore ATTRIBUTE_UNUSED)
15770 char *name = input_line_pointer, ch;
15772 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15773 ++input_line_pointer;
15774 ch = *input_line_pointer;
15775 *input_line_pointer = '\0';
15777 if (!file_mips_opts_checked)
15779 if (!parse_code_option (name))
15780 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15782 /* Update module level settings from mips_opts. */
15783 file_mips_opts = mips_opts;
15786 as_bad (_(".module is not permitted after generating code"));
15788 *input_line_pointer = ch;
15789 demand_empty_rest_of_line ();
15792 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15793 .option pic2. It means to generate SVR4 PIC calls. */
15796 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15798 mips_pic = SVR4_PIC;
15799 mips_abicalls = TRUE;
15801 if (g_switch_seen && g_switch_value != 0)
15802 as_warn (_("-G may not be used with SVR4 PIC code"));
15803 g_switch_value = 0;
15805 bfd_set_gp_size (stdoutput, 0);
15806 demand_empty_rest_of_line ();
15809 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15810 PIC code. It sets the $gp register for the function based on the
15811 function address, which is in the register named in the argument.
15812 This uses a relocation against _gp_disp, which is handled specially
15813 by the linker. The result is:
15814 lui $gp,%hi(_gp_disp)
15815 addiu $gp,$gp,%lo(_gp_disp)
15816 addu $gp,$gp,.cpload argument
15817 The .cpload argument is normally $25 == $t9.
15819 The -mno-shared option changes this to:
15820 lui $gp,%hi(__gnu_local_gp)
15821 addiu $gp,$gp,%lo(__gnu_local_gp)
15822 and the argument is ignored. This saves an instruction, but the
15823 resulting code is not position independent; it uses an absolute
15824 address for __gnu_local_gp. Thus code assembled with -mno-shared
15825 can go into an ordinary executable, but not into a shared library. */
15828 s_cpload (int ignore ATTRIBUTE_UNUSED)
15834 file_mips_check_options ();
15836 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15837 .cpload is ignored. */
15838 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15844 if (mips_opts.mips16)
15846 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15847 ignore_rest_of_line ();
15851 /* .cpload should be in a .set noreorder section. */
15852 if (mips_opts.noreorder == 0)
15853 as_warn (_(".cpload not in noreorder section"));
15855 reg = tc_get_register (0);
15857 /* If we need to produce a 64-bit address, we are better off using
15858 the default instruction sequence. */
15859 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15861 ex.X_op = O_symbol;
15862 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15864 ex.X_op_symbol = NULL;
15865 ex.X_add_number = 0;
15867 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15868 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15870 mips_mark_labels ();
15871 mips_assembling_insn = TRUE;
15874 macro_build_lui (&ex, mips_gp_register);
15875 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15876 mips_gp_register, BFD_RELOC_LO16);
15878 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15879 mips_gp_register, reg);
15882 mips_assembling_insn = FALSE;
15883 demand_empty_rest_of_line ();
15886 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15887 .cpsetup $reg1, offset|$reg2, label
15889 If offset is given, this results in:
15890 sd $gp, offset($sp)
15891 lui $gp, %hi(%neg(%gp_rel(label)))
15892 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15893 daddu $gp, $gp, $reg1
15895 If $reg2 is given, this results in:
15897 lui $gp, %hi(%neg(%gp_rel(label)))
15898 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15899 daddu $gp, $gp, $reg1
15900 $reg1 is normally $25 == $t9.
15902 The -mno-shared option replaces the last three instructions with
15904 addiu $gp,$gp,%lo(_gp) */
15907 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15909 expressionS ex_off;
15910 expressionS ex_sym;
15913 file_mips_check_options ();
15915 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15916 We also need NewABI support. */
15917 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15923 if (mips_opts.mips16)
15925 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15926 ignore_rest_of_line ();
15930 reg1 = tc_get_register (0);
15931 SKIP_WHITESPACE ();
15932 if (*input_line_pointer != ',')
15934 as_bad (_("missing argument separator ',' for .cpsetup"));
15938 ++input_line_pointer;
15939 SKIP_WHITESPACE ();
15940 if (*input_line_pointer == '$')
15942 mips_cpreturn_register = tc_get_register (0);
15943 mips_cpreturn_offset = -1;
15947 mips_cpreturn_offset = get_absolute_expression ();
15948 mips_cpreturn_register = -1;
15950 SKIP_WHITESPACE ();
15951 if (*input_line_pointer != ',')
15953 as_bad (_("missing argument separator ',' for .cpsetup"));
15957 ++input_line_pointer;
15958 SKIP_WHITESPACE ();
15959 expression (&ex_sym);
15961 mips_mark_labels ();
15962 mips_assembling_insn = TRUE;
15965 if (mips_cpreturn_register == -1)
15967 ex_off.X_op = O_constant;
15968 ex_off.X_add_symbol = NULL;
15969 ex_off.X_op_symbol = NULL;
15970 ex_off.X_add_number = mips_cpreturn_offset;
15972 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15973 BFD_RELOC_LO16, SP);
15976 move_register (mips_cpreturn_register, mips_gp_register);
15978 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15980 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15981 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15984 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15985 mips_gp_register, -1, BFD_RELOC_GPREL16,
15986 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15988 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15989 mips_gp_register, reg1);
15995 ex.X_op = O_symbol;
15996 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15997 ex.X_op_symbol = NULL;
15998 ex.X_add_number = 0;
16000 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16001 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16003 macro_build_lui (&ex, mips_gp_register);
16004 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16005 mips_gp_register, BFD_RELOC_LO16);
16010 mips_assembling_insn = FALSE;
16011 demand_empty_rest_of_line ();
16015 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16017 file_mips_check_options ();
16019 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16020 .cplocal is ignored. */
16021 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16027 if (mips_opts.mips16)
16029 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16030 ignore_rest_of_line ();
16034 mips_gp_register = tc_get_register (0);
16035 demand_empty_rest_of_line ();
16038 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16039 offset from $sp. The offset is remembered, and after making a PIC
16040 call $gp is restored from that location. */
16043 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16047 file_mips_check_options ();
16049 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16050 .cprestore is ignored. */
16051 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16057 if (mips_opts.mips16)
16059 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16060 ignore_rest_of_line ();
16064 mips_cprestore_offset = get_absolute_expression ();
16065 mips_cprestore_valid = 1;
16067 ex.X_op = O_constant;
16068 ex.X_add_symbol = NULL;
16069 ex.X_op_symbol = NULL;
16070 ex.X_add_number = mips_cprestore_offset;
16072 mips_mark_labels ();
16073 mips_assembling_insn = TRUE;
16076 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16077 SP, HAVE_64BIT_ADDRESSES);
16080 mips_assembling_insn = FALSE;
16081 demand_empty_rest_of_line ();
16084 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16085 was given in the preceding .cpsetup, it results in:
16086 ld $gp, offset($sp)
16088 If a register $reg2 was given there, it results in:
16089 or $gp, $reg2, $0 */
16092 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16096 file_mips_check_options ();
16098 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16099 We also need NewABI support. */
16100 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16106 if (mips_opts.mips16)
16108 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16109 ignore_rest_of_line ();
16113 mips_mark_labels ();
16114 mips_assembling_insn = TRUE;
16117 if (mips_cpreturn_register == -1)
16119 ex.X_op = O_constant;
16120 ex.X_add_symbol = NULL;
16121 ex.X_op_symbol = NULL;
16122 ex.X_add_number = mips_cpreturn_offset;
16124 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16127 move_register (mips_gp_register, mips_cpreturn_register);
16131 mips_assembling_insn = FALSE;
16132 demand_empty_rest_of_line ();
16135 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16136 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16137 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16138 debug information or MIPS16 TLS. */
16141 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16142 bfd_reloc_code_real_type rtype)
16149 if (ex.X_op != O_symbol)
16151 as_bad (_("unsupported use of %s"), dirstr);
16152 ignore_rest_of_line ();
16155 p = frag_more (bytes);
16156 md_number_to_chars (p, 0, bytes);
16157 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16158 demand_empty_rest_of_line ();
16159 mips_clear_insn_labels ();
16162 /* Handle .dtprelword. */
16165 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16167 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16170 /* Handle .dtpreldword. */
16173 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16175 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16178 /* Handle .tprelword. */
16181 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16183 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16186 /* Handle .tpreldword. */
16189 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16191 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16194 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16195 code. It sets the offset to use in gp_rel relocations. */
16198 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16200 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16201 We also need NewABI support. */
16202 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16208 mips_gprel_offset = get_absolute_expression ();
16210 demand_empty_rest_of_line ();
16213 /* Handle the .gpword pseudo-op. This is used when generating PIC
16214 code. It generates a 32 bit GP relative reloc. */
16217 s_gpword (int ignore ATTRIBUTE_UNUSED)
16219 segment_info_type *si;
16220 struct insn_label_list *l;
16224 /* When not generating PIC code, this is treated as .word. */
16225 if (mips_pic != SVR4_PIC)
16231 si = seg_info (now_seg);
16232 l = si->label_list;
16233 mips_emit_delays ();
16235 mips_align (2, 0, l);
16238 mips_clear_insn_labels ();
16240 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16242 as_bad (_("unsupported use of .gpword"));
16243 ignore_rest_of_line ();
16247 md_number_to_chars (p, 0, 4);
16248 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16249 BFD_RELOC_GPREL32);
16251 demand_empty_rest_of_line ();
16255 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16257 segment_info_type *si;
16258 struct insn_label_list *l;
16262 /* When not generating PIC code, this is treated as .dword. */
16263 if (mips_pic != SVR4_PIC)
16269 si = seg_info (now_seg);
16270 l = si->label_list;
16271 mips_emit_delays ();
16273 mips_align (3, 0, l);
16276 mips_clear_insn_labels ();
16278 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16280 as_bad (_("unsupported use of .gpdword"));
16281 ignore_rest_of_line ();
16285 md_number_to_chars (p, 0, 8);
16286 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16287 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16289 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16290 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16291 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16293 demand_empty_rest_of_line ();
16296 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16297 tables. It generates a R_MIPS_EH reloc. */
16300 s_ehword (int ignore ATTRIBUTE_UNUSED)
16305 mips_emit_delays ();
16308 mips_clear_insn_labels ();
16310 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16312 as_bad (_("unsupported use of .ehword"));
16313 ignore_rest_of_line ();
16317 md_number_to_chars (p, 0, 4);
16318 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16319 BFD_RELOC_32_PCREL);
16321 demand_empty_rest_of_line ();
16324 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16325 tables in SVR4 PIC code. */
16328 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16332 file_mips_check_options ();
16334 /* This is ignored when not generating SVR4 PIC code. */
16335 if (mips_pic != SVR4_PIC)
16341 mips_mark_labels ();
16342 mips_assembling_insn = TRUE;
16344 /* Add $gp to the register named as an argument. */
16346 reg = tc_get_register (0);
16347 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16350 mips_assembling_insn = FALSE;
16351 demand_empty_rest_of_line ();
16354 /* Handle the .insn pseudo-op. This marks instruction labels in
16355 mips16/micromips mode. This permits the linker to handle them specially,
16356 such as generating jalx instructions when needed. We also make
16357 them odd for the duration of the assembly, in order to generate the
16358 right sort of code. We will make them even in the adjust_symtab
16359 routine, while leaving them marked. This is convenient for the
16360 debugger and the disassembler. The linker knows to make them odd
16364 s_insn (int ignore ATTRIBUTE_UNUSED)
16366 file_mips_check_options ();
16367 file_ase_mips16 |= mips_opts.mips16;
16368 file_ase_micromips |= mips_opts.micromips;
16370 mips_mark_labels ();
16372 demand_empty_rest_of_line ();
16375 /* Handle the .nan pseudo-op. */
16378 s_nan (int ignore ATTRIBUTE_UNUSED)
16380 static const char str_legacy[] = "legacy";
16381 static const char str_2008[] = "2008";
16384 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16386 if (i == sizeof (str_2008) - 1
16387 && memcmp (input_line_pointer, str_2008, i) == 0)
16389 else if (i == sizeof (str_legacy) - 1
16390 && memcmp (input_line_pointer, str_legacy, i) == 0)
16392 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16395 as_bad (_("`%s' does not support legacy NaN"),
16396 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16399 as_bad (_("bad .nan directive"));
16401 input_line_pointer += i;
16402 demand_empty_rest_of_line ();
16405 /* Handle a .stab[snd] directive. Ideally these directives would be
16406 implemented in a transparent way, so that removing them would not
16407 have any effect on the generated instructions. However, s_stab
16408 internally changes the section, so in practice we need to decide
16409 now whether the preceding label marks compressed code. We do not
16410 support changing the compression mode of a label after a .stab*
16411 directive, such as in:
16417 so the current mode wins. */
16420 s_mips_stab (int type)
16422 mips_mark_labels ();
16426 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16429 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16436 c = get_symbol_name (&name);
16437 symbolP = symbol_find_or_make (name);
16438 S_SET_WEAK (symbolP);
16439 *input_line_pointer = c;
16441 SKIP_WHITESPACE_AFTER_NAME ();
16443 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16445 if (S_IS_DEFINED (symbolP))
16447 as_bad (_("ignoring attempt to redefine symbol %s"),
16448 S_GET_NAME (symbolP));
16449 ignore_rest_of_line ();
16453 if (*input_line_pointer == ',')
16455 ++input_line_pointer;
16456 SKIP_WHITESPACE ();
16460 if (exp.X_op != O_symbol)
16462 as_bad (_("bad .weakext directive"));
16463 ignore_rest_of_line ();
16466 symbol_set_value_expression (symbolP, &exp);
16469 demand_empty_rest_of_line ();
16472 /* Parse a register string into a number. Called from the ECOFF code
16473 to parse .frame. The argument is non-zero if this is the frame
16474 register, so that we can record it in mips_frame_reg. */
16477 tc_get_register (int frame)
16481 SKIP_WHITESPACE ();
16482 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16486 mips_frame_reg = reg != 0 ? reg : SP;
16487 mips_frame_reg_valid = 1;
16488 mips_cprestore_valid = 0;
16494 md_section_align (asection *seg, valueT addr)
16496 int align = bfd_get_section_alignment (stdoutput, seg);
16498 /* We don't need to align ELF sections to the full alignment.
16499 However, Irix 5 may prefer that we align them at least to a 16
16500 byte boundary. We don't bother to align the sections if we
16501 are targeted for an embedded system. */
16502 if (strncmp (TARGET_OS, "elf", 3) == 0)
16507 return ((addr + (1 << align) - 1) & -(1 << align));
16510 /* Utility routine, called from above as well. If called while the
16511 input file is still being read, it's only an approximation. (For
16512 example, a symbol may later become defined which appeared to be
16513 undefined earlier.) */
16516 nopic_need_relax (symbolS *sym, int before_relaxing)
16521 if (g_switch_value > 0)
16523 const char *symname;
16526 /* Find out whether this symbol can be referenced off the $gp
16527 register. It can be if it is smaller than the -G size or if
16528 it is in the .sdata or .sbss section. Certain symbols can
16529 not be referenced off the $gp, although it appears as though
16531 symname = S_GET_NAME (sym);
16532 if (symname != (const char *) NULL
16533 && (strcmp (symname, "eprol") == 0
16534 || strcmp (symname, "etext") == 0
16535 || strcmp (symname, "_gp") == 0
16536 || strcmp (symname, "edata") == 0
16537 || strcmp (symname, "_fbss") == 0
16538 || strcmp (symname, "_fdata") == 0
16539 || strcmp (symname, "_ftext") == 0
16540 || strcmp (symname, "end") == 0
16541 || strcmp (symname, "_gp_disp") == 0))
16543 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16545 #ifndef NO_ECOFF_DEBUGGING
16546 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16547 && (symbol_get_obj (sym)->ecoff_extern_size
16548 <= g_switch_value))
16550 /* We must defer this decision until after the whole
16551 file has been read, since there might be a .extern
16552 after the first use of this symbol. */
16553 || (before_relaxing
16554 #ifndef NO_ECOFF_DEBUGGING
16555 && symbol_get_obj (sym)->ecoff_extern_size == 0
16557 && S_GET_VALUE (sym) == 0)
16558 || (S_GET_VALUE (sym) != 0
16559 && S_GET_VALUE (sym) <= g_switch_value)))
16563 const char *segname;
16565 segname = segment_name (S_GET_SEGMENT (sym));
16566 gas_assert (strcmp (segname, ".lit8") != 0
16567 && strcmp (segname, ".lit4") != 0);
16568 change = (strcmp (segname, ".sdata") != 0
16569 && strcmp (segname, ".sbss") != 0
16570 && strncmp (segname, ".sdata.", 7) != 0
16571 && strncmp (segname, ".sbss.", 6) != 0
16572 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16573 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16578 /* We are not optimizing for the $gp register. */
16583 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16586 pic_need_relax (symbolS *sym, asection *segtype)
16590 /* Handle the case of a symbol equated to another symbol. */
16591 while (symbol_equated_reloc_p (sym))
16595 /* It's possible to get a loop here in a badly written program. */
16596 n = symbol_get_value_expression (sym)->X_add_symbol;
16602 if (symbol_section_p (sym))
16605 symsec = S_GET_SEGMENT (sym);
16607 /* This must duplicate the test in adjust_reloc_syms. */
16608 return (!bfd_is_und_section (symsec)
16609 && !bfd_is_abs_section (symsec)
16610 && !bfd_is_com_section (symsec)
16611 && !s_is_linkonce (sym, segtype)
16612 /* A global or weak symbol is treated as external. */
16613 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16617 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16618 extended opcode. SEC is the section the frag is in. */
16621 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16624 const struct mips_int_operand *operand;
16629 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16631 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16634 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16635 operand = mips16_immed_operand (type, FALSE);
16637 sym_frag = symbol_get_frag (fragp->fr_symbol);
16638 val = S_GET_VALUE (fragp->fr_symbol);
16639 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16641 if (operand->root.type == OP_PCREL)
16643 const struct mips_pcrel_operand *pcrel_op;
16647 /* We won't have the section when we are called from
16648 mips_relax_frag. However, we will always have been called
16649 from md_estimate_size_before_relax first. If this is a
16650 branch to a different section, we mark it as such. If SEC is
16651 NULL, and the frag is not marked, then it must be a branch to
16652 the same section. */
16653 pcrel_op = (const struct mips_pcrel_operand *) operand;
16656 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16661 /* Must have been called from md_estimate_size_before_relax. */
16664 fragp->fr_subtype =
16665 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16667 /* FIXME: We should support this, and let the linker
16668 catch branches and loads that are out of range. */
16669 as_bad_where (fragp->fr_file, fragp->fr_line,
16670 _("unsupported PC relative reference to different section"));
16674 if (fragp != sym_frag && sym_frag->fr_address == 0)
16675 /* Assume non-extended on the first relaxation pass.
16676 The address we have calculated will be bogus if this is
16677 a forward branch to another frag, as the forward frag
16678 will have fr_address == 0. */
16682 /* In this case, we know for sure that the symbol fragment is in
16683 the same section. If the relax_marker of the symbol fragment
16684 differs from the relax_marker of this fragment, we have not
16685 yet adjusted the symbol fragment fr_address. We want to add
16686 in STRETCH in order to get a better estimate of the address.
16687 This particularly matters because of the shift bits. */
16689 && sym_frag->relax_marker != fragp->relax_marker)
16693 /* Adjust stretch for any alignment frag. Note that if have
16694 been expanding the earlier code, the symbol may be
16695 defined in what appears to be an earlier frag. FIXME:
16696 This doesn't handle the fr_subtype field, which specifies
16697 a maximum number of bytes to skip when doing an
16699 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16701 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16704 stretch = - ((- stretch)
16705 & ~ ((1 << (int) f->fr_offset) - 1));
16707 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16716 addr = fragp->fr_address + fragp->fr_fix;
16718 /* The base address rules are complicated. The base address of
16719 a branch is the following instruction. The base address of a
16720 PC relative load or add is the instruction itself, but if it
16721 is in a delay slot (in which case it can not be extended) use
16722 the address of the instruction whose delay slot it is in. */
16723 if (pcrel_op->include_isa_bit)
16727 /* If we are currently assuming that this frag should be
16728 extended, then, the current address is two bytes
16730 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16733 /* Ignore the low bit in the target, since it will be set
16734 for a text label. */
16737 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16739 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16742 val -= addr & -(1 << pcrel_op->align_log2);
16744 /* If any of the shifted bits are set, we must use an extended
16745 opcode. If the address depends on the size of this
16746 instruction, this can lead to a loop, so we arrange to always
16747 use an extended opcode. We only check this when we are in
16748 the main relaxation loop, when SEC is NULL. */
16749 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16751 fragp->fr_subtype =
16752 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16756 /* If we are about to mark a frag as extended because the value
16757 is precisely the next value above maxtiny, then there is a
16758 chance of an infinite loop as in the following code:
16763 In this case when the la is extended, foo is 0x3fc bytes
16764 away, so the la can be shrunk, but then foo is 0x400 away, so
16765 the la must be extended. To avoid this loop, we mark the
16766 frag as extended if it was small, and is about to become
16767 extended with the next value above maxtiny. */
16768 maxtiny = mips_int_operand_max (operand);
16769 if (val == maxtiny + (1 << operand->shift)
16770 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16773 fragp->fr_subtype =
16774 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16778 else if (symsec != absolute_section && sec != NULL)
16779 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16781 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16784 /* Compute the length of a branch sequence, and adjust the
16785 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16786 worst-case length is computed, with UPDATE being used to indicate
16787 whether an unconditional (-1), branch-likely (+1) or regular (0)
16788 branch is to be computed. */
16790 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16792 bfd_boolean toofar;
16796 && S_IS_DEFINED (fragp->fr_symbol)
16797 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16802 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16804 addr = fragp->fr_address + fragp->fr_fix + 4;
16808 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16811 /* If the symbol is not defined or it's in a different segment,
16812 assume the user knows what's going on and emit a short
16818 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16820 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16821 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16822 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16823 RELAX_BRANCH_LINK (fragp->fr_subtype),
16829 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16832 if (mips_pic != NO_PIC)
16834 /* Additional space for PIC loading of target address. */
16836 if (mips_opts.isa == ISA_MIPS1)
16837 /* Additional space for $at-stabilizing nop. */
16841 /* If branch is conditional. */
16842 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16849 /* Compute the length of a branch sequence, and adjust the
16850 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16851 worst-case length is computed, with UPDATE being used to indicate
16852 whether an unconditional (-1), or regular (0) branch is to be
16856 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16858 bfd_boolean toofar;
16862 && S_IS_DEFINED (fragp->fr_symbol)
16863 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16868 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16869 /* Ignore the low bit in the target, since it will be set
16870 for a text label. */
16871 if ((val & 1) != 0)
16874 addr = fragp->fr_address + fragp->fr_fix + 4;
16878 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16881 /* If the symbol is not defined or it's in a different segment,
16882 assume the user knows what's going on and emit a short
16888 if (fragp && update
16889 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16890 fragp->fr_subtype = (toofar
16891 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16892 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16897 bfd_boolean compact_known = fragp != NULL;
16898 bfd_boolean compact = FALSE;
16899 bfd_boolean uncond;
16902 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16904 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16906 uncond = update < 0;
16908 /* If label is out of range, we turn branch <br>:
16910 <br> label # 4 bytes
16916 nop # 2 bytes if compact && !PIC
16919 if (mips_pic == NO_PIC && (!compact_known || compact))
16922 /* If assembling PIC code, we further turn:
16928 lw/ld at, %got(label)(gp) # 4 bytes
16929 d/addiu at, %lo(label) # 4 bytes
16932 if (mips_pic != NO_PIC)
16935 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16937 <brneg> 0f # 4 bytes
16938 nop # 2 bytes if !compact
16941 length += (compact_known && compact) ? 4 : 6;
16947 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16948 bit accordingly. */
16951 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16953 bfd_boolean toofar;
16956 && S_IS_DEFINED (fragp->fr_symbol)
16957 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16963 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16964 /* Ignore the low bit in the target, since it will be set
16965 for a text label. */
16966 if ((val & 1) != 0)
16969 /* Assume this is a 2-byte branch. */
16970 addr = fragp->fr_address + fragp->fr_fix + 2;
16972 /* We try to avoid the infinite loop by not adding 2 more bytes for
16977 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16979 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16980 else if (type == 'E')
16981 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16986 /* If the symbol is not defined or it's in a different segment,
16987 we emit a normal 32-bit branch. */
16990 if (fragp && update
16991 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16993 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16994 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17002 /* Estimate the size of a frag before relaxing. Unless this is the
17003 mips16, we are not really relaxing here, and the final size is
17004 encoded in the subtype information. For the mips16, we have to
17005 decide whether we are using an extended opcode or not. */
17008 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17012 if (RELAX_BRANCH_P (fragp->fr_subtype))
17015 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17017 return fragp->fr_var;
17020 if (RELAX_MIPS16_P (fragp->fr_subtype))
17021 /* We don't want to modify the EXTENDED bit here; it might get us
17022 into infinite loops. We change it only in mips_relax_frag(). */
17023 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17025 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17029 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17030 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17031 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17032 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17033 fragp->fr_var = length;
17038 if (mips_pic == NO_PIC)
17039 change = nopic_need_relax (fragp->fr_symbol, 0);
17040 else if (mips_pic == SVR4_PIC)
17041 change = pic_need_relax (fragp->fr_symbol, segtype);
17042 else if (mips_pic == VXWORKS_PIC)
17043 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17050 fragp->fr_subtype |= RELAX_USE_SECOND;
17051 return -RELAX_FIRST (fragp->fr_subtype);
17054 return -RELAX_SECOND (fragp->fr_subtype);
17057 /* This is called to see whether a reloc against a defined symbol
17058 should be converted into a reloc against a section. */
17061 mips_fix_adjustable (fixS *fixp)
17063 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17064 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17067 if (fixp->fx_addsy == NULL)
17070 /* Allow relocs used for EH tables. */
17071 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17074 /* If symbol SYM is in a mergeable section, relocations of the form
17075 SYM + 0 can usually be made section-relative. The mergeable data
17076 is then identified by the section offset rather than by the symbol.
17078 However, if we're generating REL LO16 relocations, the offset is split
17079 between the LO16 and parterning high part relocation. The linker will
17080 need to recalculate the complete offset in order to correctly identify
17083 The linker has traditionally not looked for the parterning high part
17084 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17085 placed anywhere. Rather than break backwards compatibility by changing
17086 this, it seems better not to force the issue, and instead keep the
17087 original symbol. This will work with either linker behavior. */
17088 if ((lo16_reloc_p (fixp->fx_r_type)
17089 || reloc_needs_lo_p (fixp->fx_r_type))
17090 && HAVE_IN_PLACE_ADDENDS
17091 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17094 /* There is no place to store an in-place offset for JALR relocations.
17095 Likewise an in-range offset of limited PC-relative relocations may
17096 overflow the in-place relocatable field if recalculated against the
17097 start address of the symbol's containing section.
17099 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17100 section relative to allow linker relaxations to be performed later on. */
17101 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
17102 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17103 || jalr_reloc_p (fixp->fx_r_type)))
17106 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17107 to a floating-point stub. The same is true for non-R_MIPS16_26
17108 relocations against MIPS16 functions; in this case, the stub becomes
17109 the function's canonical address.
17111 Floating-point stubs are stored in unique .mips16.call.* or
17112 .mips16.fn.* sections. If a stub T for function F is in section S,
17113 the first relocation in section S must be against F; this is how the
17114 linker determines the target function. All relocations that might
17115 resolve to T must also be against F. We therefore have the following
17116 restrictions, which are given in an intentionally-redundant way:
17118 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17121 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17122 if that stub might be used.
17124 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17127 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17128 that stub might be used.
17130 There is a further restriction:
17132 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17133 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17134 targets with in-place addends; the relocation field cannot
17135 encode the low bit.
17137 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17138 against a MIPS16 symbol. We deal with (5) by by not reducing any
17139 such relocations on REL targets.
17141 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17142 relocation against some symbol R, no relocation against R may be
17143 reduced. (Note that this deals with (2) as well as (1) because
17144 relocations against global symbols will never be reduced on ELF
17145 targets.) This approach is a little simpler than trying to detect
17146 stub sections, and gives the "all or nothing" per-symbol consistency
17147 that we have for MIPS16 symbols. */
17148 if (fixp->fx_subsy == NULL
17149 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17150 || *symbol_get_tc (fixp->fx_addsy)
17151 || (HAVE_IN_PLACE_ADDENDS
17152 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17153 && jmp_reloc_p (fixp->fx_r_type))))
17159 /* Translate internal representation of relocation info to BFD target
17163 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17165 static arelent *retval[4];
17167 bfd_reloc_code_real_type code;
17169 memset (retval, 0, sizeof(retval));
17170 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17171 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17172 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17173 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17175 if (fixp->fx_pcrel)
17177 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17178 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17179 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17180 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17181 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17182 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17183 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17184 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17185 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17186 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17187 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17189 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17190 Relocations want only the symbol offset. */
17191 reloc->addend = fixp->fx_addnumber + reloc->address;
17194 reloc->addend = fixp->fx_addnumber;
17196 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17197 entry to be used in the relocation's section offset. */
17198 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17200 reloc->address = reloc->addend;
17204 code = fixp->fx_r_type;
17206 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17207 if (reloc->howto == NULL)
17209 as_bad_where (fixp->fx_file, fixp->fx_line,
17210 _("cannot represent %s relocation in this object file"
17212 bfd_get_reloc_code_name (code));
17219 /* Relax a machine dependent frag. This returns the amount by which
17220 the current size of the frag should change. */
17223 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17225 if (RELAX_BRANCH_P (fragp->fr_subtype))
17227 offsetT old_var = fragp->fr_var;
17229 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17231 return fragp->fr_var - old_var;
17234 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17236 offsetT old_var = fragp->fr_var;
17237 offsetT new_var = 4;
17239 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17240 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17241 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17242 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17243 fragp->fr_var = new_var;
17245 return new_var - old_var;
17248 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17251 if (mips16_extended_frag (fragp, NULL, stretch))
17253 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17255 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17260 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17262 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17269 /* Convert a machine dependent frag. */
17272 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17274 if (RELAX_BRANCH_P (fragp->fr_subtype))
17277 unsigned long insn;
17281 buf = fragp->fr_literal + fragp->fr_fix;
17282 insn = read_insn (buf);
17284 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17286 /* We generate a fixup instead of applying it right now
17287 because, if there are linker relaxations, we're going to
17288 need the relocations. */
17289 exp.X_op = O_symbol;
17290 exp.X_add_symbol = fragp->fr_symbol;
17291 exp.X_add_number = fragp->fr_offset;
17293 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17294 BFD_RELOC_16_PCREL_S2);
17295 fixp->fx_file = fragp->fr_file;
17296 fixp->fx_line = fragp->fr_line;
17298 buf = write_insn (buf, insn);
17304 as_warn_where (fragp->fr_file, fragp->fr_line,
17305 _("relaxed out-of-range branch into a jump"));
17307 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17310 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17312 /* Reverse the branch. */
17313 switch ((insn >> 28) & 0xf)
17316 if ((insn & 0xff000000) == 0x47000000
17317 || (insn & 0xff600000) == 0x45600000)
17319 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17320 reversed by tweaking bit 23. */
17321 insn ^= 0x00800000;
17325 /* bc[0-3][tf]l? instructions can have the condition
17326 reversed by tweaking a single TF bit, and their
17327 opcodes all have 0x4???????. */
17328 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17329 insn ^= 0x00010000;
17334 /* bltz 0x04000000 bgez 0x04010000
17335 bltzal 0x04100000 bgezal 0x04110000 */
17336 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17337 insn ^= 0x00010000;
17341 /* beq 0x10000000 bne 0x14000000
17342 blez 0x18000000 bgtz 0x1c000000 */
17343 insn ^= 0x04000000;
17351 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17353 /* Clear the and-link bit. */
17354 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17356 /* bltzal 0x04100000 bgezal 0x04110000
17357 bltzall 0x04120000 bgezall 0x04130000 */
17358 insn &= ~0x00100000;
17361 /* Branch over the branch (if the branch was likely) or the
17362 full jump (not likely case). Compute the offset from the
17363 current instruction to branch to. */
17364 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17368 /* How many bytes in instructions we've already emitted? */
17369 i = buf - fragp->fr_literal - fragp->fr_fix;
17370 /* How many bytes in instructions from here to the end? */
17371 i = fragp->fr_var - i;
17373 /* Convert to instruction count. */
17375 /* Branch counts from the next instruction. */
17378 /* Branch over the jump. */
17379 buf = write_insn (buf, insn);
17382 buf = write_insn (buf, 0);
17384 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17386 /* beql $0, $0, 2f */
17388 /* Compute the PC offset from the current instruction to
17389 the end of the variable frag. */
17390 /* How many bytes in instructions we've already emitted? */
17391 i = buf - fragp->fr_literal - fragp->fr_fix;
17392 /* How many bytes in instructions from here to the end? */
17393 i = fragp->fr_var - i;
17394 /* Convert to instruction count. */
17396 /* Don't decrement i, because we want to branch over the
17400 buf = write_insn (buf, insn);
17401 buf = write_insn (buf, 0);
17405 if (mips_pic == NO_PIC)
17408 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17409 ? 0x0c000000 : 0x08000000);
17410 exp.X_op = O_symbol;
17411 exp.X_add_symbol = fragp->fr_symbol;
17412 exp.X_add_number = fragp->fr_offset;
17414 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17415 FALSE, BFD_RELOC_MIPS_JMP);
17416 fixp->fx_file = fragp->fr_file;
17417 fixp->fx_line = fragp->fr_line;
17419 buf = write_insn (buf, insn);
17423 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17425 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17426 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17427 insn |= at << OP_SH_RT;
17428 exp.X_op = O_symbol;
17429 exp.X_add_symbol = fragp->fr_symbol;
17430 exp.X_add_number = fragp->fr_offset;
17432 if (fragp->fr_offset)
17434 exp.X_add_symbol = make_expr_symbol (&exp);
17435 exp.X_add_number = 0;
17438 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17439 FALSE, BFD_RELOC_MIPS_GOT16);
17440 fixp->fx_file = fragp->fr_file;
17441 fixp->fx_line = fragp->fr_line;
17443 buf = write_insn (buf, insn);
17445 if (mips_opts.isa == ISA_MIPS1)
17447 buf = write_insn (buf, 0);
17449 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17450 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17451 insn |= at << OP_SH_RS | at << OP_SH_RT;
17453 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17454 FALSE, BFD_RELOC_LO16);
17455 fixp->fx_file = fragp->fr_file;
17456 fixp->fx_line = fragp->fr_line;
17458 buf = write_insn (buf, insn);
17461 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17465 insn |= at << OP_SH_RS;
17467 buf = write_insn (buf, insn);
17471 fragp->fr_fix += fragp->fr_var;
17472 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17476 /* Relax microMIPS branches. */
17477 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17479 char *buf = fragp->fr_literal + fragp->fr_fix;
17480 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17481 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17482 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17483 bfd_boolean short_ds;
17484 unsigned long insn;
17488 exp.X_op = O_symbol;
17489 exp.X_add_symbol = fragp->fr_symbol;
17490 exp.X_add_number = fragp->fr_offset;
17492 fragp->fr_fix += fragp->fr_var;
17494 /* Handle 16-bit branches that fit or are forced to fit. */
17495 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17497 /* We generate a fixup instead of applying it right now,
17498 because if there is linker relaxation, we're going to
17499 need the relocations. */
17501 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17502 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17503 else if (type == 'E')
17504 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17505 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17509 fixp->fx_file = fragp->fr_file;
17510 fixp->fx_line = fragp->fr_line;
17512 /* These relocations can have an addend that won't fit in
17514 fixp->fx_no_overflow = 1;
17519 /* Handle 32-bit branches that fit or are forced to fit. */
17520 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17521 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17523 /* We generate a fixup instead of applying it right now,
17524 because if there is linker relaxation, we're going to
17525 need the relocations. */
17526 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17527 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17528 fixp->fx_file = fragp->fr_file;
17529 fixp->fx_line = fragp->fr_line;
17535 /* Relax 16-bit branches to 32-bit branches. */
17538 insn = read_compressed_insn (buf, 2);
17540 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17541 insn = 0x94000000; /* beq */
17542 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17544 unsigned long regno;
17546 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17547 regno = micromips_to_32_reg_d_map [regno];
17548 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17549 insn |= regno << MICROMIPSOP_SH_RS;
17554 /* Nothing else to do, just write it out. */
17555 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17556 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17558 buf = write_compressed_insn (buf, insn, 4);
17559 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17564 insn = read_compressed_insn (buf, 4);
17566 /* Relax 32-bit branches to a sequence of instructions. */
17567 as_warn_where (fragp->fr_file, fragp->fr_line,
17568 _("relaxed out-of-range branch into a jump"));
17570 /* Set the short-delay-slot bit. */
17571 short_ds = al && (insn & 0x02000000) != 0;
17573 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17577 /* Reverse the branch. */
17578 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17579 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17580 insn ^= 0x20000000;
17581 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17582 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17583 || (insn & 0xffe00000) == 0x40800000 /* blez */
17584 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17585 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17586 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17587 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17588 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17589 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17590 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17591 insn ^= 0x00400000;
17592 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17593 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17594 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17595 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17596 insn ^= 0x00200000;
17597 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17599 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17601 insn ^= 0x00800000;
17607 /* Clear the and-link and short-delay-slot bits. */
17608 gas_assert ((insn & 0xfda00000) == 0x40200000);
17610 /* bltzal 0x40200000 bgezal 0x40600000 */
17611 /* bltzals 0x42200000 bgezals 0x42600000 */
17612 insn &= ~0x02200000;
17615 /* Make a label at the end for use with the branch. */
17616 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17617 micromips_label_inc ();
17618 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17621 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17622 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17623 fixp->fx_file = fragp->fr_file;
17624 fixp->fx_line = fragp->fr_line;
17626 /* Branch over the jump. */
17627 buf = write_compressed_insn (buf, insn, 4);
17630 buf = write_compressed_insn (buf, 0x0c00, 2);
17633 if (mips_pic == NO_PIC)
17635 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17637 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17638 insn = al ? jal : 0xd4000000;
17640 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17641 BFD_RELOC_MICROMIPS_JMP);
17642 fixp->fx_file = fragp->fr_file;
17643 fixp->fx_line = fragp->fr_line;
17645 buf = write_compressed_insn (buf, insn, 4);
17648 buf = write_compressed_insn (buf, 0x0c00, 2);
17652 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17653 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17654 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17656 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17657 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17658 insn |= at << MICROMIPSOP_SH_RT;
17660 if (exp.X_add_number)
17662 exp.X_add_symbol = make_expr_symbol (&exp);
17663 exp.X_add_number = 0;
17666 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17667 BFD_RELOC_MICROMIPS_GOT16);
17668 fixp->fx_file = fragp->fr_file;
17669 fixp->fx_line = fragp->fr_line;
17671 buf = write_compressed_insn (buf, insn, 4);
17673 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17674 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17675 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17677 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17678 BFD_RELOC_MICROMIPS_LO16);
17679 fixp->fx_file = fragp->fr_file;
17680 fixp->fx_line = fragp->fr_line;
17682 buf = write_compressed_insn (buf, insn, 4);
17684 /* jr/jrc/jalr/jalrs $at */
17685 insn = al ? jalr : jr;
17686 insn |= at << MICROMIPSOP_SH_MJ;
17688 buf = write_compressed_insn (buf, insn, 2);
17691 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17695 if (RELAX_MIPS16_P (fragp->fr_subtype))
17698 const struct mips_int_operand *operand;
17701 unsigned int user_length, length;
17702 unsigned long insn;
17705 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17706 operand = mips16_immed_operand (type, FALSE);
17708 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17709 val = resolve_symbol_value (fragp->fr_symbol);
17710 if (operand->root.type == OP_PCREL)
17712 const struct mips_pcrel_operand *pcrel_op;
17715 pcrel_op = (const struct mips_pcrel_operand *) operand;
17716 addr = fragp->fr_address + fragp->fr_fix;
17718 /* The rules for the base address of a PC relative reloc are
17719 complicated; see mips16_extended_frag. */
17720 if (pcrel_op->include_isa_bit)
17725 /* Ignore the low bit in the target, since it will be
17726 set for a text label. */
17729 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17731 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17734 addr &= -(1 << pcrel_op->align_log2);
17737 /* Make sure the section winds up with the alignment we have
17739 if (operand->shift > 0)
17740 record_alignment (asec, operand->shift);
17744 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17745 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17746 as_warn_where (fragp->fr_file, fragp->fr_line,
17747 _("extended instruction in delay slot"));
17749 buf = fragp->fr_literal + fragp->fr_fix;
17751 insn = read_compressed_insn (buf, 2);
17753 insn |= MIPS16_EXTEND;
17755 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17757 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17762 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17763 BFD_RELOC_UNUSED, val, user_length, &insn);
17765 length = (ext ? 4 : 2);
17766 gas_assert (mips16_opcode_length (insn) == length);
17767 write_compressed_insn (buf, insn, length);
17768 fragp->fr_fix += length;
17772 relax_substateT subtype = fragp->fr_subtype;
17773 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17774 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17778 first = RELAX_FIRST (subtype);
17779 second = RELAX_SECOND (subtype);
17780 fixp = (fixS *) fragp->fr_opcode;
17782 /* If the delay slot chosen does not match the size of the instruction,
17783 then emit a warning. */
17784 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17785 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17790 s = subtype & (RELAX_DELAY_SLOT_16BIT
17791 | RELAX_DELAY_SLOT_SIZE_FIRST
17792 | RELAX_DELAY_SLOT_SIZE_SECOND);
17793 msg = macro_warning (s);
17795 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17799 /* Possibly emit a warning if we've chosen the longer option. */
17800 if (use_second == second_longer)
17806 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17807 msg = macro_warning (s);
17809 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17813 /* Go through all the fixups for the first sequence. Disable them
17814 (by marking them as done) if we're going to use the second
17815 sequence instead. */
17817 && fixp->fx_frag == fragp
17818 && fixp->fx_where < fragp->fr_fix - second)
17820 if (subtype & RELAX_USE_SECOND)
17822 fixp = fixp->fx_next;
17825 /* Go through the fixups for the second sequence. Disable them if
17826 we're going to use the first sequence, otherwise adjust their
17827 addresses to account for the relaxation. */
17828 while (fixp && fixp->fx_frag == fragp)
17830 if (subtype & RELAX_USE_SECOND)
17831 fixp->fx_where -= first;
17834 fixp = fixp->fx_next;
17837 /* Now modify the frag contents. */
17838 if (subtype & RELAX_USE_SECOND)
17842 start = fragp->fr_literal + fragp->fr_fix - first - second;
17843 memmove (start, start + first, second);
17844 fragp->fr_fix -= first;
17847 fragp->fr_fix -= second;
17851 /* This function is called after the relocs have been generated.
17852 We've been storing mips16 text labels as odd. Here we convert them
17853 back to even for the convenience of the debugger. */
17856 mips_frob_file_after_relocs (void)
17859 unsigned int count, i;
17861 syms = bfd_get_outsymbols (stdoutput);
17862 count = bfd_get_symcount (stdoutput);
17863 for (i = 0; i < count; i++, syms++)
17864 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17865 && ((*syms)->value & 1) != 0)
17867 (*syms)->value &= ~1;
17868 /* If the symbol has an odd size, it was probably computed
17869 incorrectly, so adjust that as well. */
17870 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17871 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17875 /* This function is called whenever a label is defined, including fake
17876 labels instantiated off the dot special symbol. It is used when
17877 handling branch delays; if a branch has a label, we assume we cannot
17878 move it. This also bumps the value of the symbol by 1 in compressed
17882 mips_record_label (symbolS *sym)
17884 segment_info_type *si = seg_info (now_seg);
17885 struct insn_label_list *l;
17887 if (free_insn_labels == NULL)
17888 l = (struct insn_label_list *) xmalloc (sizeof *l);
17891 l = free_insn_labels;
17892 free_insn_labels = l->next;
17896 l->next = si->label_list;
17897 si->label_list = l;
17900 /* This function is called as tc_frob_label() whenever a label is defined
17901 and adds a DWARF-2 record we only want for true labels. */
17904 mips_define_label (symbolS *sym)
17906 mips_record_label (sym);
17907 dwarf2_emit_label (sym);
17910 /* This function is called by tc_new_dot_label whenever a new dot symbol
17914 mips_add_dot_label (symbolS *sym)
17916 mips_record_label (sym);
17917 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17918 mips_compressed_mark_label (sym);
17921 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17922 static unsigned int
17923 mips_convert_ase_flags (int ase)
17925 unsigned int ext_ases = 0;
17928 ext_ases |= AFL_ASE_DSP;
17929 if (ase & ASE_DSPR2)
17930 ext_ases |= AFL_ASE_DSPR2;
17932 ext_ases |= AFL_ASE_EVA;
17934 ext_ases |= AFL_ASE_MCU;
17935 if (ase & ASE_MDMX)
17936 ext_ases |= AFL_ASE_MDMX;
17937 if (ase & ASE_MIPS3D)
17938 ext_ases |= AFL_ASE_MIPS3D;
17940 ext_ases |= AFL_ASE_MT;
17941 if (ase & ASE_SMARTMIPS)
17942 ext_ases |= AFL_ASE_SMARTMIPS;
17943 if (ase & ASE_VIRT)
17944 ext_ases |= AFL_ASE_VIRT;
17946 ext_ases |= AFL_ASE_MSA;
17948 ext_ases |= AFL_ASE_XPA;
17952 /* Some special processing for a MIPS ELF file. */
17955 mips_elf_final_processing (void)
17958 Elf_Internal_ABIFlags_v0 flags;
17962 switch (file_mips_opts.isa)
17965 flags.isa_level = 1;
17968 flags.isa_level = 2;
17971 flags.isa_level = 3;
17974 flags.isa_level = 4;
17977 flags.isa_level = 5;
17980 flags.isa_level = 32;
17984 flags.isa_level = 32;
17988 flags.isa_level = 32;
17992 flags.isa_level = 32;
17996 flags.isa_level = 32;
18000 flags.isa_level = 64;
18004 flags.isa_level = 64;
18008 flags.isa_level = 64;
18012 flags.isa_level = 64;
18016 flags.isa_level = 64;
18021 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18022 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18023 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18024 : (file_mips_opts.fp == 64) ? AFL_REG_64
18026 flags.cpr2_size = AFL_REG_NONE;
18027 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18028 Tag_GNU_MIPS_ABI_FP);
18029 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18030 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18031 if (file_ase_mips16)
18032 flags.ases |= AFL_ASE_MIPS16;
18033 if (file_ase_micromips)
18034 flags.ases |= AFL_ASE_MICROMIPS;
18036 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18037 || file_mips_opts.fp == 64)
18038 && file_mips_opts.oddspreg)
18039 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18042 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18043 ((Elf_External_ABIFlags_v0 *)
18046 /* Write out the register information. */
18047 if (mips_abi != N64_ABI)
18051 s.ri_gprmask = mips_gprmask;
18052 s.ri_cprmask[0] = mips_cprmask[0];
18053 s.ri_cprmask[1] = mips_cprmask[1];
18054 s.ri_cprmask[2] = mips_cprmask[2];
18055 s.ri_cprmask[3] = mips_cprmask[3];
18056 /* The gp_value field is set by the MIPS ELF backend. */
18058 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18059 ((Elf32_External_RegInfo *)
18060 mips_regmask_frag));
18064 Elf64_Internal_RegInfo s;
18066 s.ri_gprmask = mips_gprmask;
18068 s.ri_cprmask[0] = mips_cprmask[0];
18069 s.ri_cprmask[1] = mips_cprmask[1];
18070 s.ri_cprmask[2] = mips_cprmask[2];
18071 s.ri_cprmask[3] = mips_cprmask[3];
18072 /* The gp_value field is set by the MIPS ELF backend. */
18074 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18075 ((Elf64_External_RegInfo *)
18076 mips_regmask_frag));
18079 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18080 sort of BFD interface for this. */
18081 if (mips_any_noreorder)
18082 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18083 if (mips_pic != NO_PIC)
18085 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18086 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18089 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18091 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18092 defined at present; this might need to change in future. */
18093 if (file_ase_mips16)
18094 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18095 if (file_ase_micromips)
18096 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18097 if (file_mips_opts.ase & ASE_MDMX)
18098 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18100 /* Set the MIPS ELF ABI flags. */
18101 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18102 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18103 else if (mips_abi == O64_ABI)
18104 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18105 else if (mips_abi == EABI_ABI)
18107 if (file_mips_opts.gp == 64)
18108 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18110 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18112 else if (mips_abi == N32_ABI)
18113 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18115 /* Nothing to do for N64_ABI. */
18117 if (mips_32bitmode)
18118 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18120 if (mips_nan2008 == 1)
18121 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18123 /* 32 bit code with 64 bit FP registers. */
18124 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18125 Tag_GNU_MIPS_ABI_FP);
18126 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18127 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18130 typedef struct proc {
18132 symbolS *func_end_sym;
18133 unsigned long reg_mask;
18134 unsigned long reg_offset;
18135 unsigned long fpreg_mask;
18136 unsigned long fpreg_offset;
18137 unsigned long frame_offset;
18138 unsigned long frame_reg;
18139 unsigned long pc_reg;
18142 static procS cur_proc;
18143 static procS *cur_proc_ptr;
18144 static int numprocs;
18146 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18147 as "2", and a normal nop as "0". */
18149 #define NOP_OPCODE_MIPS 0
18150 #define NOP_OPCODE_MIPS16 1
18151 #define NOP_OPCODE_MICROMIPS 2
18154 mips_nop_opcode (void)
18156 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18157 return NOP_OPCODE_MICROMIPS;
18158 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18159 return NOP_OPCODE_MIPS16;
18161 return NOP_OPCODE_MIPS;
18164 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18165 32-bit microMIPS NOPs here (if applicable). */
18168 mips_handle_align (fragS *fragp)
18172 int bytes, size, excess;
18175 if (fragp->fr_type != rs_align_code)
18178 p = fragp->fr_literal + fragp->fr_fix;
18180 switch (nop_opcode)
18182 case NOP_OPCODE_MICROMIPS:
18183 opcode = micromips_nop32_insn.insn_opcode;
18186 case NOP_OPCODE_MIPS16:
18187 opcode = mips16_nop_insn.insn_opcode;
18190 case NOP_OPCODE_MIPS:
18192 opcode = nop_insn.insn_opcode;
18197 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18198 excess = bytes % size;
18200 /* Handle the leading part if we're not inserting a whole number of
18201 instructions, and make it the end of the fixed part of the frag.
18202 Try to fit in a short microMIPS NOP if applicable and possible,
18203 and use zeroes otherwise. */
18204 gas_assert (excess < 4);
18205 fragp->fr_fix += excess;
18210 /* Fall through. */
18212 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18214 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18218 /* Fall through. */
18221 /* Fall through. */
18226 md_number_to_chars (p, opcode, size);
18227 fragp->fr_var = size;
18236 if (*input_line_pointer == '-')
18238 ++input_line_pointer;
18241 if (!ISDIGIT (*input_line_pointer))
18242 as_bad (_("expected simple number"));
18243 if (input_line_pointer[0] == '0')
18245 if (input_line_pointer[1] == 'x')
18247 input_line_pointer += 2;
18248 while (ISXDIGIT (*input_line_pointer))
18251 val |= hex_value (*input_line_pointer++);
18253 return negative ? -val : val;
18257 ++input_line_pointer;
18258 while (ISDIGIT (*input_line_pointer))
18261 val |= *input_line_pointer++ - '0';
18263 return negative ? -val : val;
18266 if (!ISDIGIT (*input_line_pointer))
18268 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18269 *input_line_pointer, *input_line_pointer);
18270 as_warn (_("invalid number"));
18273 while (ISDIGIT (*input_line_pointer))
18276 val += *input_line_pointer++ - '0';
18278 return negative ? -val : val;
18281 /* The .file directive; just like the usual .file directive, but there
18282 is an initial number which is the ECOFF file index. In the non-ECOFF
18283 case .file implies DWARF-2. */
18286 s_mips_file (int x ATTRIBUTE_UNUSED)
18288 static int first_file_directive = 0;
18290 if (ECOFF_DEBUGGING)
18299 filename = dwarf2_directive_file (0);
18301 /* Versions of GCC up to 3.1 start files with a ".file"
18302 directive even for stabs output. Make sure that this
18303 ".file" is handled. Note that you need a version of GCC
18304 after 3.1 in order to support DWARF-2 on MIPS. */
18305 if (filename != NULL && ! first_file_directive)
18307 (void) new_logical_line (filename, -1);
18308 s_app_file_string (filename, 0);
18310 first_file_directive = 1;
18314 /* The .loc directive, implying DWARF-2. */
18317 s_mips_loc (int x ATTRIBUTE_UNUSED)
18319 if (!ECOFF_DEBUGGING)
18320 dwarf2_directive_loc (0);
18323 /* The .end directive. */
18326 s_mips_end (int x ATTRIBUTE_UNUSED)
18330 /* Following functions need their own .frame and .cprestore directives. */
18331 mips_frame_reg_valid = 0;
18332 mips_cprestore_valid = 0;
18334 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18337 demand_empty_rest_of_line ();
18342 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18343 as_warn (_(".end not in text section"));
18347 as_warn (_(".end directive without a preceding .ent directive"));
18348 demand_empty_rest_of_line ();
18354 gas_assert (S_GET_NAME (p));
18355 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18356 as_warn (_(".end symbol does not match .ent symbol"));
18358 if (debug_type == DEBUG_STABS)
18359 stabs_generate_asm_endfunc (S_GET_NAME (p),
18363 as_warn (_(".end directive missing or unknown symbol"));
18365 /* Create an expression to calculate the size of the function. */
18366 if (p && cur_proc_ptr)
18368 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18369 expressionS *exp = xmalloc (sizeof (expressionS));
18372 exp->X_op = O_subtract;
18373 exp->X_add_symbol = symbol_temp_new_now ();
18374 exp->X_op_symbol = p;
18375 exp->X_add_number = 0;
18377 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18380 /* Generate a .pdr section. */
18381 if (!ECOFF_DEBUGGING && mips_flag_pdr)
18383 segT saved_seg = now_seg;
18384 subsegT saved_subseg = now_subseg;
18388 #ifdef md_flush_pending_output
18389 md_flush_pending_output ();
18392 gas_assert (pdr_seg);
18393 subseg_set (pdr_seg, 0);
18395 /* Write the symbol. */
18396 exp.X_op = O_symbol;
18397 exp.X_add_symbol = p;
18398 exp.X_add_number = 0;
18399 emit_expr (&exp, 4);
18401 fragp = frag_more (7 * 4);
18403 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18404 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18405 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18406 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18407 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18408 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18409 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18411 subseg_set (saved_seg, saved_subseg);
18414 cur_proc_ptr = NULL;
18417 /* The .aent and .ent directives. */
18420 s_mips_ent (int aent)
18424 symbolP = get_symbol ();
18425 if (*input_line_pointer == ',')
18426 ++input_line_pointer;
18427 SKIP_WHITESPACE ();
18428 if (ISDIGIT (*input_line_pointer)
18429 || *input_line_pointer == '-')
18432 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18433 as_warn (_(".ent or .aent not in text section"));
18435 if (!aent && cur_proc_ptr)
18436 as_warn (_("missing .end"));
18440 /* This function needs its own .frame and .cprestore directives. */
18441 mips_frame_reg_valid = 0;
18442 mips_cprestore_valid = 0;
18444 cur_proc_ptr = &cur_proc;
18445 memset (cur_proc_ptr, '\0', sizeof (procS));
18447 cur_proc_ptr->func_sym = symbolP;
18451 if (debug_type == DEBUG_STABS)
18452 stabs_generate_asm_func (S_GET_NAME (symbolP),
18453 S_GET_NAME (symbolP));
18456 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18458 demand_empty_rest_of_line ();
18461 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18462 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18463 s_mips_frame is used so that we can set the PDR information correctly.
18464 We can't use the ecoff routines because they make reference to the ecoff
18465 symbol table (in the mdebug section). */
18468 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18470 if (ECOFF_DEBUGGING)
18476 if (cur_proc_ptr == (procS *) NULL)
18478 as_warn (_(".frame outside of .ent"));
18479 demand_empty_rest_of_line ();
18483 cur_proc_ptr->frame_reg = tc_get_register (1);
18485 SKIP_WHITESPACE ();
18486 if (*input_line_pointer++ != ','
18487 || get_absolute_expression_and_terminator (&val) != ',')
18489 as_warn (_("bad .frame directive"));
18490 --input_line_pointer;
18491 demand_empty_rest_of_line ();
18495 cur_proc_ptr->frame_offset = val;
18496 cur_proc_ptr->pc_reg = tc_get_register (0);
18498 demand_empty_rest_of_line ();
18502 /* The .fmask and .mask directives. If the mdebug section is present
18503 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18504 embedded targets, s_mips_mask is used so that we can set the PDR
18505 information correctly. We can't use the ecoff routines because they
18506 make reference to the ecoff symbol table (in the mdebug section). */
18509 s_mips_mask (int reg_type)
18511 if (ECOFF_DEBUGGING)
18512 s_ignore (reg_type);
18517 if (cur_proc_ptr == (procS *) NULL)
18519 as_warn (_(".mask/.fmask outside of .ent"));
18520 demand_empty_rest_of_line ();
18524 if (get_absolute_expression_and_terminator (&mask) != ',')
18526 as_warn (_("bad .mask/.fmask directive"));
18527 --input_line_pointer;
18528 demand_empty_rest_of_line ();
18532 off = get_absolute_expression ();
18534 if (reg_type == 'F')
18536 cur_proc_ptr->fpreg_mask = mask;
18537 cur_proc_ptr->fpreg_offset = off;
18541 cur_proc_ptr->reg_mask = mask;
18542 cur_proc_ptr->reg_offset = off;
18545 demand_empty_rest_of_line ();
18549 /* A table describing all the processors gas knows about. Names are
18550 matched in the order listed.
18552 To ease comparison, please keep this table in the same order as
18553 gcc's mips_cpu_info_table[]. */
18554 static const struct mips_cpu_info mips_cpu_info_table[] =
18556 /* Entries for generic ISAs */
18557 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18558 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18559 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18560 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18561 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18562 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18563 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18564 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18565 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
18566 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
18567 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18568 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
18569 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18570 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
18571 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
18574 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18575 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18576 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
18579 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
18582 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18583 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18584 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18585 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18586 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18587 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18588 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18589 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18590 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18591 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18592 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18593 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18594 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
18595 /* ST Microelectronics Loongson 2E and 2F cores */
18596 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18597 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
18600 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18601 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18602 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18603 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18604 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18605 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18606 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18607 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18608 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18609 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18610 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18611 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18612 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18613 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18614 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
18617 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18618 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18619 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18620 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18622 /* MIPS 32 Release 2 */
18623 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18624 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18625 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18626 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18627 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18628 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18629 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18630 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18631 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18632 ISA_MIPS32R2, CPU_MIPS32R2 },
18633 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18634 ISA_MIPS32R2, CPU_MIPS32R2 },
18635 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18636 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18637 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18638 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18639 /* Deprecated forms of the above. */
18640 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18641 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18642 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18643 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18644 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18645 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18646 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18647 /* Deprecated forms of the above. */
18648 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18649 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18650 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18651 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18652 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18653 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18654 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18655 /* Deprecated forms of the above. */
18656 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18657 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18658 /* 34Kn is a 34kc without DSP. */
18659 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18660 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18661 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18662 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18663 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18664 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18665 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18666 /* Deprecated forms of the above. */
18667 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18668 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18669 /* 1004K cores are multiprocessor versions of the 34K. */
18670 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18671 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18672 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18673 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18674 /* interaptiv is the new name for 1004kf */
18675 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18677 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18678 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18679 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18680 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
18683 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18684 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18685 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18686 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18688 /* Broadcom SB-1 CPU core */
18689 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18690 /* Broadcom SB-1A CPU core */
18691 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18693 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
18695 /* MIPS 64 Release 2 */
18697 /* Cavium Networks Octeon CPU core */
18698 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18699 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18700 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
18701 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
18704 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
18707 XLP is mostly like XLR, with the prominent exception that it is
18708 MIPS64R2 rather than MIPS64. */
18709 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
18712 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18715 { NULL, 0, 0, 0, 0 }
18719 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18720 with a final "000" replaced by "k". Ignore case.
18722 Note: this function is shared between GCC and GAS. */
18725 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18727 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18728 given++, canonical++;
18730 return ((*given == 0 && *canonical == 0)
18731 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18735 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18736 CPU name. We've traditionally allowed a lot of variation here.
18738 Note: this function is shared between GCC and GAS. */
18741 mips_matching_cpu_name_p (const char *canonical, const char *given)
18743 /* First see if the name matches exactly, or with a final "000"
18744 turned into "k". */
18745 if (mips_strict_matching_cpu_name_p (canonical, given))
18748 /* If not, try comparing based on numerical designation alone.
18749 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18750 if (TOLOWER (*given) == 'r')
18752 if (!ISDIGIT (*given))
18755 /* Skip over some well-known prefixes in the canonical name,
18756 hoping to find a number there too. */
18757 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18759 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18761 else if (TOLOWER (canonical[0]) == 'r')
18764 return mips_strict_matching_cpu_name_p (canonical, given);
18768 /* Parse an option that takes the name of a processor as its argument.
18769 OPTION is the name of the option and CPU_STRING is the argument.
18770 Return the corresponding processor enumeration if the CPU_STRING is
18771 recognized, otherwise report an error and return null.
18773 A similar function exists in GCC. */
18775 static const struct mips_cpu_info *
18776 mips_parse_cpu (const char *option, const char *cpu_string)
18778 const struct mips_cpu_info *p;
18780 /* 'from-abi' selects the most compatible architecture for the given
18781 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18782 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18783 version. Look first at the -mgp options, if given, otherwise base
18784 the choice on MIPS_DEFAULT_64BIT.
18786 Treat NO_ABI like the EABIs. One reason to do this is that the
18787 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18788 architecture. This code picks MIPS I for 'mips' and MIPS III for
18789 'mips64', just as we did in the days before 'from-abi'. */
18790 if (strcasecmp (cpu_string, "from-abi") == 0)
18792 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18793 return mips_cpu_info_from_isa (ISA_MIPS1);
18795 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18796 return mips_cpu_info_from_isa (ISA_MIPS3);
18798 if (file_mips_opts.gp >= 0)
18799 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
18800 ? ISA_MIPS1 : ISA_MIPS3);
18802 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18807 /* 'default' has traditionally been a no-op. Probably not very useful. */
18808 if (strcasecmp (cpu_string, "default") == 0)
18811 for (p = mips_cpu_info_table; p->name != 0; p++)
18812 if (mips_matching_cpu_name_p (p->name, cpu_string))
18815 as_bad (_("bad value (%s) for %s"), cpu_string, option);
18819 /* Return the canonical processor information for ISA (a member of the
18820 ISA_MIPS* enumeration). */
18822 static const struct mips_cpu_info *
18823 mips_cpu_info_from_isa (int isa)
18827 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18828 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18829 && isa == mips_cpu_info_table[i].isa)
18830 return (&mips_cpu_info_table[i]);
18835 static const struct mips_cpu_info *
18836 mips_cpu_info_from_arch (int arch)
18840 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18841 if (arch == mips_cpu_info_table[i].cpu)
18842 return (&mips_cpu_info_table[i]);
18848 show (FILE *stream, const char *string, int *col_p, int *first_p)
18852 fprintf (stream, "%24s", "");
18857 fprintf (stream, ", ");
18861 if (*col_p + strlen (string) > 72)
18863 fprintf (stream, "\n%24s", "");
18867 fprintf (stream, "%s", string);
18868 *col_p += strlen (string);
18874 md_show_usage (FILE *stream)
18879 fprintf (stream, _("\
18881 -EB generate big endian output\n\
18882 -EL generate little endian output\n\
18883 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18884 -G NUM allow referencing objects up to NUM bytes\n\
18885 implicitly with the gp register [default 8]\n"));
18886 fprintf (stream, _("\
18887 -mips1 generate MIPS ISA I instructions\n\
18888 -mips2 generate MIPS ISA II instructions\n\
18889 -mips3 generate MIPS ISA III instructions\n\
18890 -mips4 generate MIPS ISA IV instructions\n\
18891 -mips5 generate MIPS ISA V instructions\n\
18892 -mips32 generate MIPS32 ISA instructions\n\
18893 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18894 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18895 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18896 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18897 -mips64 generate MIPS64 ISA instructions\n\
18898 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18899 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18900 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18901 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18902 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18906 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18907 show (stream, mips_cpu_info_table[i].name, &column, &first);
18908 show (stream, "from-abi", &column, &first);
18909 fputc ('\n', stream);
18911 fprintf (stream, _("\
18912 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18913 -no-mCPU don't generate code specific to CPU.\n\
18914 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18918 show (stream, "3900", &column, &first);
18919 show (stream, "4010", &column, &first);
18920 show (stream, "4100", &column, &first);
18921 show (stream, "4650", &column, &first);
18922 fputc ('\n', stream);
18924 fprintf (stream, _("\
18925 -mips16 generate mips16 instructions\n\
18926 -no-mips16 do not generate mips16 instructions\n"));
18927 fprintf (stream, _("\
18928 -mmicromips generate microMIPS instructions\n\
18929 -mno-micromips do not generate microMIPS instructions\n"));
18930 fprintf (stream, _("\
18931 -msmartmips generate smartmips instructions\n\
18932 -mno-smartmips do not generate smartmips instructions\n"));
18933 fprintf (stream, _("\
18934 -mdsp generate DSP instructions\n\
18935 -mno-dsp do not generate DSP instructions\n"));
18936 fprintf (stream, _("\
18937 -mdspr2 generate DSP R2 instructions\n\
18938 -mno-dspr2 do not generate DSP R2 instructions\n"));
18939 fprintf (stream, _("\
18940 -mmt generate MT instructions\n\
18941 -mno-mt do not generate MT instructions\n"));
18942 fprintf (stream, _("\
18943 -mmcu generate MCU instructions\n\
18944 -mno-mcu do not generate MCU instructions\n"));
18945 fprintf (stream, _("\
18946 -mmsa generate MSA instructions\n\
18947 -mno-msa do not generate MSA instructions\n"));
18948 fprintf (stream, _("\
18949 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18950 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18951 fprintf (stream, _("\
18952 -mvirt generate Virtualization instructions\n\
18953 -mno-virt do not generate Virtualization instructions\n"));
18954 fprintf (stream, _("\
18955 -minsn32 only generate 32-bit microMIPS instructions\n\
18956 -mno-insn32 generate all microMIPS instructions\n"));
18957 fprintf (stream, _("\
18958 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18959 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18960 -mfix-vr4120 work around certain VR4120 errata\n\
18961 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18962 -mfix-24k insert a nop after ERET and DERET instructions\n\
18963 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18964 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18965 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18966 -msym32 assume all symbols have 32-bit values\n\
18967 -O0 remove unneeded NOPs, do not swap branches\n\
18968 -O remove unneeded NOPs and swap branches\n\
18969 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18970 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18971 fprintf (stream, _("\
18972 -mhard-float allow floating-point instructions\n\
18973 -msoft-float do not allow floating-point instructions\n\
18974 -msingle-float only allow 32-bit floating-point operations\n\
18975 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18976 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18977 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18978 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18982 show (stream, "legacy", &column, &first);
18983 show (stream, "2008", &column, &first);
18985 fputc ('\n', stream);
18987 fprintf (stream, _("\
18988 -KPIC, -call_shared generate SVR4 position independent code\n\
18989 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18990 -mvxworks-pic generate VxWorks position independent code\n\
18991 -non_shared do not generate code that can operate with DSOs\n\
18992 -xgot assume a 32 bit GOT\n\
18993 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18994 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18995 position dependent (non shared) code\n\
18996 -mabi=ABI create ABI conformant object file for:\n"));
19000 show (stream, "32", &column, &first);
19001 show (stream, "o64", &column, &first);
19002 show (stream, "n32", &column, &first);
19003 show (stream, "64", &column, &first);
19004 show (stream, "eabi", &column, &first);
19006 fputc ('\n', stream);
19008 fprintf (stream, _("\
19009 -32 create o32 ABI object file (default)\n\
19010 -n32 create n32 ABI object file\n\
19011 -64 create 64 ABI object file\n"));
19016 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19018 if (HAVE_64BIT_SYMBOLS)
19019 return dwarf2_format_64bit_irix;
19021 return dwarf2_format_32bit;
19026 mips_dwarf2_addr_size (void)
19028 if (HAVE_64BIT_OBJECTS)
19034 /* Standard calling conventions leave the CFA at SP on entry. */
19036 mips_cfi_frame_initial_instructions (void)
19038 cfi_add_CFA_def_cfa_register (SP);
19042 tc_mips_regname_to_dw2regnum (char *regname)
19044 unsigned int regnum = -1;
19047 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19053 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19054 Given a symbolic attribute NAME, return the proper integer value.
19055 Returns -1 if the attribute is not known. */
19058 mips_convert_symbolic_attribute (const char *name)
19060 static const struct
19065 attribute_table[] =
19067 #define T(tag) {#tag, tag}
19068 T (Tag_GNU_MIPS_ABI_FP),
19069 T (Tag_GNU_MIPS_ABI_MSA),
19077 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19078 if (streq (name, attribute_table[i].name))
19079 return attribute_table[i].tag;
19087 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19089 mips_emit_delays ();
19091 as_warn (_("missing .end at end of assembly"));
19093 /* Just in case no code was emitted, do the consistency check. */
19094 file_mips_check_options ();
19096 /* Set a floating-point ABI if the user did not. */
19097 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19099 /* Perform consistency checks on the floating-point ABI. */
19100 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19101 Tag_GNU_MIPS_ABI_FP);
19102 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19103 check_fpabi (fpabi);
19107 /* Soft-float gets precedence over single-float, the two options should
19108 not be used together so this should not matter. */
19109 if (file_mips_opts.soft_float == 1)
19110 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19111 /* Single-float gets precedence over all double_float cases. */
19112 else if (file_mips_opts.single_float == 1)
19113 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19116 switch (file_mips_opts.fp)
19119 if (file_mips_opts.gp == 32)
19120 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19123 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19126 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19127 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19128 else if (file_mips_opts.gp == 32)
19129 fpabi = Val_GNU_MIPS_ABI_FP_64;
19131 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19136 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19137 Tag_GNU_MIPS_ABI_FP, fpabi);
19141 /* Returns the relocation type required for a particular CFI encoding. */
19143 bfd_reloc_code_real_type
19144 mips_cfi_reloc_for_encoding (int encoding)
19146 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19147 return BFD_RELOC_32_PCREL;
19148 else return BFD_RELOC_NONE;