1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi = NO_ABI;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls = FALSE;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32 = -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32 = -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts =
202 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask;
209 unsigned long mips_cprmask[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa = ISA_UNKNOWN;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch = CPU_UNKNOWN;
228 static const char *mips_arch_string;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune = CPU_UNKNOWN;
233 static const char *mips_tune_string;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode = 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* True if relocations are stored in-place. */
283 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
285 /* We can only have 64bit addresses if the object file format supports it. */
286 #define HAVE_32BIT_ADDRESSES \
288 || (bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS)) \
291 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
293 /* Addresses are loaded in different ways, depending on the address size
294 in use. The n32 ABI Documentation also mandates the use of additions
295 with overflow checking, but existing implementations don't follow it. */
296 #define ADDRESS_ADD_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
299 #define ADDRESS_ADDI_INSN \
300 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
302 #define ADDRESS_LOAD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
305 #define ADDRESS_STORE_INSN \
306 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
308 /* Return true if the given CPU supports the MIPS16 ASE. */
309 #define CPU_HAS_MIPS16(cpu) \
310 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
311 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
313 /* Return true if the given CPU supports the MIPS3D ASE. */
314 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
317 /* Return true if the given CPU supports the MDMX ASE. */
318 #define CPU_HAS_MDMX(cpu) (FALSE \
321 /* True if CPU has a dror instruction. */
322 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
324 /* True if CPU has a ror instruction. */
325 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
327 /* True if mflo and mfhi can be immediately followed by instructions
328 which write to the HI and LO registers.
330 According to MIPS specifications, MIPS ISAs I, II, and III need
331 (at least) two instructions between the reads of HI/LO and
332 instructions which write them, and later ISAs do not. Contradicting
333 the MIPS specifications, some MIPS IV processor user manuals (e.g.
334 the UM for the NEC Vr5000) document needing the instructions between
335 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
336 MIPS64 and later ISAs to have the interlocks, plus any specific
337 earlier-ISA CPUs for which CPU documentation declares that the
338 instructions are really interlocked. */
339 #define hilo_interlocks \
340 (mips_opts.isa == ISA_MIPS32 \
341 || mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_R10000 \
346 || mips_opts.arch == CPU_R12000 \
347 || mips_opts.arch == CPU_RM7000 \
348 || mips_opts.arch == CPU_VR5500 \
351 /* Whether the processor uses hardware interlocks to protect reads
352 from the GPRs after they are loaded from memory, and thus does not
353 require nops to be inserted. This applies to instructions marked
354 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
356 #define gpr_interlocks \
357 (mips_opts.isa != ISA_MIPS1 \
358 || mips_opts.arch == CPU_R3900)
360 /* Whether the processor uses hardware interlocks to avoid delays
361 required by coprocessor instructions, and thus does not require
362 nops to be inserted. This applies to instructions marked
363 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
364 between instructions marked INSN_WRITE_COND_CODE and ones marked
365 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
366 levels I, II, and III. */
367 /* Itbl support may require additional care here. */
368 #define cop_interlocks \
369 ((mips_opts.isa != ISA_MIPS1 \
370 && mips_opts.isa != ISA_MIPS2 \
371 && mips_opts.isa != ISA_MIPS3) \
372 || mips_opts.arch == CPU_R4300 \
375 /* Whether the processor uses hardware interlocks to protect reads
376 from coprocessor registers after they are loaded from memory, and
377 thus does not require nops to be inserted. This applies to
378 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
379 requires at MIPS ISA level I. */
380 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
382 /* Is this a mfhi or mflo instruction? */
383 #define MF_HILO_INSN(PINFO) \
384 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
386 /* MIPS PIC level. */
388 enum mips_pic_level mips_pic;
390 /* 1 if we should generate 32 bit offsets from the $gp register in
391 SVR4_PIC mode. Currently has no meaning in other modes. */
392 static int mips_big_got = 0;
394 /* 1 if trap instructions should used for overflow rather than break
396 static int mips_trap = 0;
398 /* 1 if double width floating point constants should not be constructed
399 by assembling two single width halves into two single width floating
400 point registers which just happen to alias the double width destination
401 register. On some architectures this aliasing can be disabled by a bit
402 in the status register, and the setting of this bit cannot be determined
403 automatically at assemble time. */
404 static int mips_disable_float_construction;
406 /* Non-zero if any .set noreorder directives were used. */
408 static int mips_any_noreorder;
410 /* Non-zero if nops should be inserted when the register referenced in
411 an mfhi/mflo instruction is read in the next two instructions. */
412 static int mips_7000_hilo_fix;
414 /* The size of the small data section. */
415 static unsigned int g_switch_value = 8;
416 /* Whether the -G option was used. */
417 static int g_switch_seen = 0;
422 /* If we can determine in advance that GP optimization won't be
423 possible, we can skip the relaxation stuff that tries to produce
424 GP-relative references. This makes delay slot optimization work
427 This function can only provide a guess, but it seems to work for
428 gcc output. It needs to guess right for gcc, otherwise gcc
429 will put what it thinks is a GP-relative instruction in a branch
432 I don't know if a fix is needed for the SVR4_PIC mode. I've only
433 fixed it for the non-PIC mode. KR 95/04/07 */
434 static int nopic_need_relax (symbolS *, int);
436 /* handle of the OPCODE hash table */
437 static struct hash_control *op_hash = NULL;
439 /* The opcode hash table we use for the mips16. */
440 static struct hash_control *mips16_op_hash = NULL;
442 /* This array holds the chars that always start a comment. If the
443 pre-processor is disabled, these aren't very useful */
444 const char comment_chars[] = "#";
446 /* This array holds the chars that only start a comment at the beginning of
447 a line. If the line seems to have the form '# 123 filename'
448 .line and .file directives will appear in the pre-processed output */
449 /* Note that input_file.c hand checks for '#' at the beginning of the
450 first line of the input file. This is because the compiler outputs
451 #NO_APP at the beginning of its output. */
452 /* Also note that C style comments are always supported. */
453 const char line_comment_chars[] = "#";
455 /* This array holds machine specific line separator characters. */
456 const char line_separator_chars[] = ";";
458 /* Chars that can be used to separate mant from exp in floating point nums */
459 const char EXP_CHARS[] = "eE";
461 /* Chars that mean this number is a floating point constant */
464 const char FLT_CHARS[] = "rRsSfFdDxXpP";
466 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
467 changed in read.c . Ideally it shouldn't have to know about it at all,
468 but nothing is ideal around here.
471 static char *insn_error;
473 static int auto_align = 1;
475 /* When outputting SVR4 PIC code, the assembler needs to know the
476 offset in the stack frame from which to restore the $gp register.
477 This is set by the .cprestore pseudo-op, and saved in this
479 static offsetT mips_cprestore_offset = -1;
481 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
482 more optimizations, it can use a register value instead of a memory-saved
483 offset and even an other register than $gp as global pointer. */
484 static offsetT mips_cpreturn_offset = -1;
485 static int mips_cpreturn_register = -1;
486 static int mips_gp_register = GP;
487 static int mips_gprel_offset = 0;
489 /* Whether mips_cprestore_offset has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_cprestore_valid = 0;
493 /* This is the register which holds the stack frame, as set by the
494 .frame pseudo-op. This is needed to implement .cprestore. */
495 static int mips_frame_reg = SP;
497 /* Whether mips_frame_reg has been set in the current function
498 (or whether it has already been warned about, if not). */
499 static int mips_frame_reg_valid = 0;
501 /* To output NOP instructions correctly, we need to keep information
502 about the previous two instructions. */
504 /* Whether we are optimizing. The default value of 2 means to remove
505 unneeded NOPs and swap branch instructions when possible. A value
506 of 1 means to not swap branches. A value of 0 means to always
508 static int mips_optimize = 2;
510 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
511 equivalent to seeing no -g option at all. */
512 static int mips_debug = 0;
514 /* The previous instruction. */
515 static struct mips_cl_insn prev_insn;
517 /* The instruction before prev_insn. */
518 static struct mips_cl_insn prev_prev_insn;
520 /* If we don't want information for prev_insn or prev_prev_insn, we
521 point the insn_mo field at this dummy integer. */
522 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
524 /* Non-zero if prev_insn is valid. */
525 static int prev_insn_valid;
527 /* The frag for the previous instruction. */
528 static struct frag *prev_insn_frag;
530 /* The offset into prev_insn_frag for the previous instruction. */
531 static long prev_insn_where;
533 /* The reloc type for the previous instruction, if any. */
534 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
536 /* The reloc for the previous instruction, if any. */
537 static fixS *prev_insn_fixp[3];
539 /* Non-zero if the previous instruction was in a delay slot. */
540 static int prev_insn_is_delay_slot;
542 /* Non-zero if the previous instruction was in a .set noreorder. */
543 static int prev_insn_unreordered;
545 /* Non-zero if the previous instruction uses an extend opcode (if
547 static int prev_insn_extended;
549 /* Non-zero if the previous previous instruction was in a .set
551 static int prev_prev_insn_unreordered;
553 /* If this is set, it points to a frag holding nop instructions which
554 were inserted before the start of a noreorder section. If those
555 nops turn out to be unnecessary, the size of the frag can be
557 static fragS *prev_nop_frag;
559 /* The number of nop instructions we created in prev_nop_frag. */
560 static int prev_nop_frag_holds;
562 /* The number of nop instructions that we know we need in
564 static int prev_nop_frag_required;
566 /* The number of instructions we've seen since prev_nop_frag. */
567 static int prev_nop_frag_since;
569 /* For ECOFF and ELF, relocations against symbols are done in two
570 parts, with a HI relocation and a LO relocation. Each relocation
571 has only 16 bits of space to store an addend. This means that in
572 order for the linker to handle carries correctly, it must be able
573 to locate both the HI and the LO relocation. This means that the
574 relocations must appear in order in the relocation table.
576 In order to implement this, we keep track of each unmatched HI
577 relocation. We then sort them so that they immediately precede the
578 corresponding LO relocation. */
583 struct mips_hi_fixup *next;
586 /* The section this fixup is in. */
590 /* The list of unmatched HI relocs. */
592 static struct mips_hi_fixup *mips_hi_fixup_list;
594 /* The frag containing the last explicit relocation operator.
595 Null if explicit relocations have not been used. */
597 static fragS *prev_reloc_op_frag;
599 /* Map normal MIPS register numbers to mips16 register numbers. */
601 #define X ILLEGAL_REG
602 static const int mips32_to_16_reg_map[] =
604 X, X, 2, 3, 4, 5, 6, 7,
605 X, X, X, X, X, X, X, X,
606 0, 1, X, X, X, X, X, X,
607 X, X, X, X, X, X, X, X
611 /* Map mips16 register numbers to normal MIPS register numbers. */
613 static const unsigned int mips16_to_32_reg_map[] =
615 16, 17, 2, 3, 4, 5, 6, 7
618 static int mips_fix_vr4120;
620 /* We don't relax branches by default, since this causes us to expand
621 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
622 fail to compute the offset before expanding the macro to the most
623 efficient expansion. */
625 static int mips_relax_branch;
627 /* The expansion of many macros depends on the type of symbol that
628 they refer to. For example, when generating position-dependent code,
629 a macro that refers to a symbol may have two different expansions,
630 one which uses GP-relative addresses and one which uses absolute
631 addresses. When generating SVR4-style PIC, a macro may have
632 different expansions for local and global symbols.
634 We handle these situations by generating both sequences and putting
635 them in variant frags. In position-dependent code, the first sequence
636 will be the GP-relative one and the second sequence will be the
637 absolute one. In SVR4 PIC, the first sequence will be for global
638 symbols and the second will be for local symbols.
640 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
641 SECOND are the lengths of the two sequences in bytes. These fields
642 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
643 the subtype has the following flags:
646 Set if it has been decided that we should use the second
647 sequence instead of the first.
650 Set in the first variant frag if the macro's second implementation
651 is longer than its first. This refers to the macro as a whole,
652 not an individual relaxation.
655 Set in the first variant frag if the macro appeared in a .set nomacro
656 block and if one alternative requires a warning but the other does not.
659 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
662 The frag's "opcode" points to the first fixup for relaxable code.
664 Relaxable macros are generated using a sequence such as:
666 relax_start (SYMBOL);
667 ... generate first expansion ...
669 ... generate second expansion ...
672 The code and fixups for the unwanted alternative are discarded
673 by md_convert_frag. */
674 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
676 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
677 #define RELAX_SECOND(X) ((X) & 0xff)
678 #define RELAX_USE_SECOND 0x10000
679 #define RELAX_SECOND_LONGER 0x20000
680 #define RELAX_NOMACRO 0x40000
681 #define RELAX_DELAY_SLOT 0x80000
683 /* Branch without likely bit. If label is out of range, we turn:
685 beq reg1, reg2, label
695 with the following opcode replacements:
702 bltzal <-> bgezal (with jal label instead of j label)
704 Even though keeping the delay slot instruction in the delay slot of
705 the branch would be more efficient, it would be very tricky to do
706 correctly, because we'd have to introduce a variable frag *after*
707 the delay slot instruction, and expand that instead. Let's do it
708 the easy way for now, even if the branch-not-taken case now costs
709 one additional instruction. Out-of-range branches are not supposed
710 to be common, anyway.
712 Branch likely. If label is out of range, we turn:
714 beql reg1, reg2, label
715 delay slot (annulled if branch not taken)
724 delay slot (executed only if branch taken)
727 It would be possible to generate a shorter sequence by losing the
728 likely bit, generating something like:
733 delay slot (executed only if branch taken)
745 bltzall -> bgezal (with jal label instead of j label)
746 bgezall -> bltzal (ditto)
749 but it's not clear that it would actually improve performance. */
750 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
753 | ((toofar) ? 1 : 0) \
755 | ((likely) ? 4 : 0) \
756 | ((uncond) ? 8 : 0)))
757 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
758 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
759 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
760 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
761 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
763 /* For mips16 code, we use an entirely different form of relaxation.
764 mips16 supports two versions of most instructions which take
765 immediate values: a small one which takes some small value, and a
766 larger one which takes a 16 bit value. Since branches also follow
767 this pattern, relaxing these values is required.
769 We can assemble both mips16 and normal MIPS code in a single
770 object. Therefore, we need to support this type of relaxation at
771 the same time that we support the relaxation described above. We
772 use the high bit of the subtype field to distinguish these cases.
774 The information we store for this type of relaxation is the
775 argument code found in the opcode file for this relocation, whether
776 the user explicitly requested a small or extended form, and whether
777 the relocation is in a jump or jal delay slot. That tells us the
778 size of the value, and how it should be stored. We also store
779 whether the fragment is considered to be extended or not. We also
780 store whether this is known to be a branch to a different section,
781 whether we have tried to relax this frag yet, and whether we have
782 ever extended a PC relative fragment because of a shift count. */
783 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
786 | ((small) ? 0x100 : 0) \
787 | ((ext) ? 0x200 : 0) \
788 | ((dslot) ? 0x400 : 0) \
789 | ((jal_dslot) ? 0x800 : 0))
790 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
791 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
792 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
793 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
794 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
795 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
796 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
797 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
798 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
799 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
800 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
801 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
803 /* Is the given value a sign-extended 32-bit value? */
804 #define IS_SEXT_32BIT_NUM(x) \
805 (((x) &~ (offsetT) 0x7fffffff) == 0 \
806 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
808 /* Is the given value a sign-extended 16-bit value? */
809 #define IS_SEXT_16BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fff) == 0 \
811 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
814 /* Global variables used when generating relaxable macros. See the
815 comment above RELAX_ENCODE for more details about how relaxation
818 /* 0 if we're not emitting a relaxable macro.
819 1 if we're emitting the first of the two relaxation alternatives.
820 2 if we're emitting the second alternative. */
823 /* The first relaxable fixup in the current frag. (In other words,
824 the first fixup that refers to relaxable code.) */
827 /* sizes[0] says how many bytes of the first alternative are stored in
828 the current frag. Likewise sizes[1] for the second alternative. */
829 unsigned int sizes[2];
831 /* The symbol on which the choice of sequence depends. */
835 /* Global variables used to decide whether a macro needs a warning. */
837 /* True if the macro is in a branch delay slot. */
838 bfd_boolean delay_slot_p;
840 /* For relaxable macros, sizes[0] is the length of the first alternative
841 in bytes and sizes[1] is the length of the second alternative.
842 For non-relaxable macros, both elements give the length of the
844 unsigned int sizes[2];
846 /* The first variant frag for this macro. */
848 } mips_macro_warning;
850 /* Prototypes for static functions. */
852 #define internalError() \
853 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
855 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
857 static void append_insn
858 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
859 static void mips_no_prev_insn (int);
860 static void mips16_macro_build
861 (expressionS *, const char *, const char *, va_list);
862 static void load_register (int, expressionS *, int);
863 static void macro_start (void);
864 static void macro_end (void);
865 static void macro (struct mips_cl_insn * ip);
866 static void mips16_macro (struct mips_cl_insn * ip);
867 #ifdef LOSING_COMPILER
868 static void macro2 (struct mips_cl_insn * ip);
870 static void mips_ip (char *str, struct mips_cl_insn * ip);
871 static void mips16_ip (char *str, struct mips_cl_insn * ip);
872 static void mips16_immed
873 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
874 unsigned long *, bfd_boolean *, unsigned short *);
875 static size_t my_getSmallExpression
876 (expressionS *, bfd_reloc_code_real_type *, char *);
877 static void my_getExpression (expressionS *, char *);
878 static void s_align (int);
879 static void s_change_sec (int);
880 static void s_change_section (int);
881 static void s_cons (int);
882 static void s_float_cons (int);
883 static void s_mips_globl (int);
884 static void s_option (int);
885 static void s_mipsset (int);
886 static void s_abicalls (int);
887 static void s_cpload (int);
888 static void s_cpsetup (int);
889 static void s_cplocal (int);
890 static void s_cprestore (int);
891 static void s_cpreturn (int);
892 static void s_gpvalue (int);
893 static void s_gpword (int);
894 static void s_gpdword (int);
895 static void s_cpadd (int);
896 static void s_insn (int);
897 static void md_obj_begin (void);
898 static void md_obj_end (void);
899 static void s_mips_ent (int);
900 static void s_mips_end (int);
901 static void s_mips_frame (int);
902 static void s_mips_mask (int reg_type);
903 static void s_mips_stab (int);
904 static void s_mips_weakext (int);
905 static void s_mips_file (int);
906 static void s_mips_loc (int);
907 static bfd_boolean pic_need_relax (symbolS *, asection *);
908 static int relaxed_branch_length (fragS *, asection *, int);
909 static int validate_mips_insn (const struct mips_opcode *);
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name; /* CPU or ISA name. */
917 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
918 int isa; /* ISA level. */
919 int cpu; /* CPU number (default CPU if ISA). */
922 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
923 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
924 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
928 The following pseudo-ops from the Kane and Heinrich MIPS book
929 should be defined here, but are currently unsupported: .alias,
930 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
932 The following pseudo-ops from the Kane and Heinrich MIPS book are
933 specific to the type of debugging information being generated, and
934 should be defined by the object format: .aent, .begin, .bend,
935 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
938 The following pseudo-ops from the Kane and Heinrich MIPS book are
939 not MIPS CPU specific, but are also not specific to the object file
940 format. This file is probably the best place to define them, but
941 they are not currently supported: .asm0, .endr, .lab, .repeat,
944 static const pseudo_typeS mips_pseudo_table[] =
946 /* MIPS specific pseudo-ops. */
947 {"option", s_option, 0},
948 {"set", s_mipsset, 0},
949 {"rdata", s_change_sec, 'r'},
950 {"sdata", s_change_sec, 's'},
951 {"livereg", s_ignore, 0},
952 {"abicalls", s_abicalls, 0},
953 {"cpload", s_cpload, 0},
954 {"cpsetup", s_cpsetup, 0},
955 {"cplocal", s_cplocal, 0},
956 {"cprestore", s_cprestore, 0},
957 {"cpreturn", s_cpreturn, 0},
958 {"gpvalue", s_gpvalue, 0},
959 {"gpword", s_gpword, 0},
960 {"gpdword", s_gpdword, 0},
961 {"cpadd", s_cpadd, 0},
964 /* Relatively generic pseudo-ops that happen to be used on MIPS
966 {"asciiz", stringer, 1},
967 {"bss", s_change_sec, 'b'},
970 {"dword", s_cons, 3},
971 {"weakext", s_mips_weakext, 0},
973 /* These pseudo-ops are defined in read.c, but must be overridden
974 here for one reason or another. */
975 {"align", s_align, 0},
977 {"data", s_change_sec, 'd'},
978 {"double", s_float_cons, 'd'},
979 {"float", s_float_cons, 'f'},
980 {"globl", s_mips_globl, 0},
981 {"global", s_mips_globl, 0},
982 {"hword", s_cons, 1},
987 {"section", s_change_section, 0},
988 {"short", s_cons, 1},
989 {"single", s_float_cons, 'f'},
990 {"stabn", s_mips_stab, 'n'},
991 {"text", s_change_sec, 't'},
994 { "extern", ecoff_directive_extern, 0},
999 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1001 /* These pseudo-ops should be defined by the object file format.
1002 However, a.out doesn't support them, so we have versions here. */
1003 {"aent", s_mips_ent, 1},
1004 {"bgnb", s_ignore, 0},
1005 {"end", s_mips_end, 0},
1006 {"endb", s_ignore, 0},
1007 {"ent", s_mips_ent, 0},
1008 {"file", s_mips_file, 0},
1009 {"fmask", s_mips_mask, 'F'},
1010 {"frame", s_mips_frame, 0},
1011 {"loc", s_mips_loc, 0},
1012 {"mask", s_mips_mask, 'R'},
1013 {"verstamp", s_ignore, 0},
1017 extern void pop_insert (const pseudo_typeS *);
1020 mips_pop_insert (void)
1022 pop_insert (mips_pseudo_table);
1023 if (! ECOFF_DEBUGGING)
1024 pop_insert (mips_nonecoff_pseudo_table);
1027 /* Symbols labelling the current insn. */
1029 struct insn_label_list
1031 struct insn_label_list *next;
1035 static struct insn_label_list *insn_labels;
1036 static struct insn_label_list *free_insn_labels;
1038 static void mips_clear_insn_labels (void);
1041 mips_clear_insn_labels (void)
1043 register struct insn_label_list **pl;
1045 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1051 static char *expr_end;
1053 /* Expressions which appear in instructions. These are set by
1056 static expressionS imm_expr;
1057 static expressionS imm2_expr;
1058 static expressionS offset_expr;
1060 /* Relocs associated with imm_expr and offset_expr. */
1062 static bfd_reloc_code_real_type imm_reloc[3]
1063 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1064 static bfd_reloc_code_real_type offset_reloc[3]
1065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1067 /* These are set by mips16_ip if an explicit extension is used. */
1069 static bfd_boolean mips16_small, mips16_ext;
1072 /* The pdr segment for per procedure frame/regmask info. Not used for
1075 static segT pdr_seg;
1078 /* The default target format to use. */
1081 mips_target_format (void)
1083 switch (OUTPUT_FLAVOR)
1085 case bfd_target_ecoff_flavour:
1086 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1087 case bfd_target_coff_flavour:
1089 case bfd_target_elf_flavour:
1091 /* This is traditional mips. */
1092 return (target_big_endian
1093 ? (HAVE_64BIT_OBJECTS
1094 ? "elf64-tradbigmips"
1096 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1097 : (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradlittlemips"
1100 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1106 ? "elf32-nbigmips" : "elf32-bigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-littlemips"
1110 ? "elf32-nlittlemips" : "elf32-littlemips")));
1118 /* This function is called once, at assembler startup time. It should
1119 set up all the tables, etc. that the MD part of the assembler will need. */
1124 register const char *retval = NULL;
1128 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1129 as_warn (_("Could not set architecture and machine"));
1131 op_hash = hash_new ();
1133 for (i = 0; i < NUMOPCODES;)
1135 const char *name = mips_opcodes[i].name;
1137 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1140 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1141 mips_opcodes[i].name, retval);
1142 /* Probably a memory allocation problem? Give up now. */
1143 as_fatal (_("Broken assembler. No assembly attempted."));
1147 if (mips_opcodes[i].pinfo != INSN_MACRO)
1149 if (!validate_mips_insn (&mips_opcodes[i]))
1154 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1157 mips16_op_hash = hash_new ();
1160 while (i < bfd_mips16_num_opcodes)
1162 const char *name = mips16_opcodes[i].name;
1164 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1166 as_fatal (_("internal: can't hash `%s': %s"),
1167 mips16_opcodes[i].name, retval);
1170 if (mips16_opcodes[i].pinfo != INSN_MACRO
1171 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1172 != mips16_opcodes[i].match))
1174 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1175 mips16_opcodes[i].name, mips16_opcodes[i].args);
1180 while (i < bfd_mips16_num_opcodes
1181 && strcmp (mips16_opcodes[i].name, name) == 0);
1185 as_fatal (_("Broken assembler. No assembly attempted."));
1187 /* We add all the general register names to the symbol table. This
1188 helps us detect invalid uses of them. */
1189 for (i = 0; i < 32; i++)
1193 sprintf (buf, "$%d", i);
1194 symbol_table_insert (symbol_new (buf, reg_section, i,
1195 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1208 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1214 &zero_address_frag));
1216 /* If we don't add these register names to the symbol table, they
1217 may end up being added as regular symbols by operand(), and then
1218 make it to the object file as undefined in case they're not
1219 regarded as local symbols. They're local in o32, since `$' is a
1220 local symbol prefix, but not in n32 or n64. */
1221 for (i = 0; i < 8; i++)
1225 sprintf (buf, "$fcc%i", i);
1226 symbol_table_insert (symbol_new (buf, reg_section, -1,
1227 &zero_address_frag));
1230 mips_no_prev_insn (FALSE);
1233 mips_cprmask[0] = 0;
1234 mips_cprmask[1] = 0;
1235 mips_cprmask[2] = 0;
1236 mips_cprmask[3] = 0;
1238 /* set the default alignment for the text section (2**2) */
1239 record_alignment (text_section, 2);
1241 bfd_set_gp_size (stdoutput, g_switch_value);
1243 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1245 /* On a native system, sections must be aligned to 16 byte
1246 boundaries. When configured for an embedded ELF target, we
1248 if (strcmp (TARGET_OS, "elf") != 0)
1250 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1251 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1252 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1255 /* Create a .reginfo section for register masks and a .mdebug
1256 section for debugging information. */
1264 subseg = now_subseg;
1266 /* The ABI says this section should be loaded so that the
1267 running program can access it. However, we don't load it
1268 if we are configured for an embedded target */
1269 flags = SEC_READONLY | SEC_DATA;
1270 if (strcmp (TARGET_OS, "elf") != 0)
1271 flags |= SEC_ALLOC | SEC_LOAD;
1273 if (mips_abi != N64_ABI)
1275 sec = subseg_new (".reginfo", (subsegT) 0);
1277 bfd_set_section_flags (stdoutput, sec, flags);
1278 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1281 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1286 /* The 64-bit ABI uses a .MIPS.options section rather than
1287 .reginfo section. */
1288 sec = subseg_new (".MIPS.options", (subsegT) 0);
1289 bfd_set_section_flags (stdoutput, sec, flags);
1290 bfd_set_section_alignment (stdoutput, sec, 3);
1293 /* Set up the option header. */
1295 Elf_Internal_Options opthdr;
1298 opthdr.kind = ODK_REGINFO;
1299 opthdr.size = (sizeof (Elf_External_Options)
1300 + sizeof (Elf64_External_RegInfo));
1303 f = frag_more (sizeof (Elf_External_Options));
1304 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1305 (Elf_External_Options *) f);
1307 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1312 if (ECOFF_DEBUGGING)
1314 sec = subseg_new (".mdebug", (subsegT) 0);
1315 (void) bfd_set_section_flags (stdoutput, sec,
1316 SEC_HAS_CONTENTS | SEC_READONLY);
1317 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1320 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1322 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1323 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1324 SEC_READONLY | SEC_RELOC
1326 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1330 subseg_set (seg, subseg);
1334 if (! ECOFF_DEBUGGING)
1341 if (! ECOFF_DEBUGGING)
1346 md_assemble (char *str)
1348 struct mips_cl_insn insn;
1349 bfd_reloc_code_real_type unused_reloc[3]
1350 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1352 imm_expr.X_op = O_absent;
1353 imm2_expr.X_op = O_absent;
1354 offset_expr.X_op = O_absent;
1355 imm_reloc[0] = BFD_RELOC_UNUSED;
1356 imm_reloc[1] = BFD_RELOC_UNUSED;
1357 imm_reloc[2] = BFD_RELOC_UNUSED;
1358 offset_reloc[0] = BFD_RELOC_UNUSED;
1359 offset_reloc[1] = BFD_RELOC_UNUSED;
1360 offset_reloc[2] = BFD_RELOC_UNUSED;
1362 if (mips_opts.mips16)
1363 mips16_ip (str, &insn);
1366 mips_ip (str, &insn);
1367 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1368 str, insn.insn_opcode));
1373 as_bad ("%s `%s'", insn_error, str);
1377 if (insn.insn_mo->pinfo == INSN_MACRO)
1380 if (mips_opts.mips16)
1381 mips16_macro (&insn);
1388 if (imm_expr.X_op != O_absent)
1389 append_insn (&insn, &imm_expr, imm_reloc);
1390 else if (offset_expr.X_op != O_absent)
1391 append_insn (&insn, &offset_expr, offset_reloc);
1393 append_insn (&insn, NULL, unused_reloc);
1397 /* Return true if the given relocation might need a matching %lo().
1398 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1399 applied to local symbols. */
1401 static inline bfd_boolean
1402 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1404 return (HAVE_IN_PLACE_ADDENDS
1405 && (reloc == BFD_RELOC_HI16_S
1406 || reloc == BFD_RELOC_MIPS_GOT16));
1409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1412 static inline bfd_boolean
1413 fixup_has_matching_lo_p (fixS *fixp)
1415 return (fixp->fx_next != NULL
1416 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1417 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1418 && fixp->fx_offset == fixp->fx_next->fx_offset);
1421 /* See whether instruction IP reads register REG. CLASS is the type
1425 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1426 enum mips_regclass class)
1428 if (class == MIPS16_REG)
1430 assert (mips_opts.mips16);
1431 reg = mips16_to_32_reg_map[reg];
1432 class = MIPS_GR_REG;
1435 /* Don't report on general register ZERO, since it never changes. */
1436 if (class == MIPS_GR_REG && reg == ZERO)
1439 if (class == MIPS_FP_REG)
1441 assert (! mips_opts.mips16);
1442 /* If we are called with either $f0 or $f1, we must check $f0.
1443 This is not optimal, because it will introduce an unnecessary
1444 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1445 need to distinguish reading both $f0 and $f1 or just one of
1446 them. Note that we don't have to check the other way,
1447 because there is no instruction that sets both $f0 and $f1
1448 and requires a delay. */
1449 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1450 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1451 == (reg &~ (unsigned) 1)))
1453 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1454 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1455 == (reg &~ (unsigned) 1)))
1458 else if (! mips_opts.mips16)
1460 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1461 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1463 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1464 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1469 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1470 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1471 & MIPS16OP_MASK_RX)]
1474 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1475 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1476 & MIPS16OP_MASK_RY)]
1479 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1480 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1481 & MIPS16OP_MASK_MOVE32Z)]
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1488 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1490 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1491 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1492 & MIPS16OP_MASK_REGR32) == reg)
1499 /* This function returns true if modifying a register requires a
1503 reg_needs_delay (unsigned int reg)
1505 unsigned long prev_pinfo;
1507 prev_pinfo = prev_insn.insn_mo->pinfo;
1508 if (! mips_opts.noreorder
1509 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1510 && ! gpr_interlocks)
1511 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1512 && ! cop_interlocks)))
1514 /* A load from a coprocessor or from memory. All load delays
1515 delay the use of general register rt for one instruction. */
1516 /* Itbl support may require additional care here. */
1517 know (prev_pinfo & INSN_WRITE_GPR_T);
1518 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1525 /* Mark instruction labels in mips16 mode. This permits the linker to
1526 handle them specially, such as generating jalx instructions when
1527 needed. We also make them odd for the duration of the assembly, in
1528 order to generate the right sort of code. We will make them even
1529 in the adjust_symtab routine, while leaving them marked. This is
1530 convenient for the debugger and the disassembler. The linker knows
1531 to make them odd again. */
1534 mips16_mark_labels (void)
1536 if (mips_opts.mips16)
1538 struct insn_label_list *l;
1541 for (l = insn_labels; l != NULL; l = l->next)
1544 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1545 S_SET_OTHER (l->label, STO_MIPS16);
1547 val = S_GET_VALUE (l->label);
1549 S_SET_VALUE (l->label, val + 1);
1554 /* End the current frag. Make it a variant frag and record the
1558 relax_close_frag (void)
1560 mips_macro_warning.first_frag = frag_now;
1561 frag_var (rs_machine_dependent, 0, 0,
1562 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1563 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1565 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1566 mips_relax.first_fixup = 0;
1569 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1570 See the comment above RELAX_ENCODE for more details. */
1573 relax_start (symbolS *symbol)
1575 assert (mips_relax.sequence == 0);
1576 mips_relax.sequence = 1;
1577 mips_relax.symbol = symbol;
1580 /* Start generating the second version of a relaxable sequence.
1581 See the comment above RELAX_ENCODE for more details. */
1586 assert (mips_relax.sequence == 1);
1587 mips_relax.sequence = 2;
1590 /* End the current relaxable sequence. */
1595 assert (mips_relax.sequence == 2);
1596 relax_close_frag ();
1597 mips_relax.sequence = 0;
1600 /* Output an instruction. IP is the instruction information.
1601 ADDRESS_EXPR is an operand of the instruction to be used with
1605 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1606 bfd_reloc_code_real_type *reloc_type)
1608 register unsigned long prev_pinfo, pinfo;
1612 relax_stateT prev_insn_frag_type = 0;
1613 bfd_boolean relaxed_branch = FALSE;
1614 bfd_boolean force_new_frag = FALSE;
1616 /* Mark instruction labels in mips16 mode. */
1617 mips16_mark_labels ();
1619 prev_pinfo = prev_insn.insn_mo->pinfo;
1620 pinfo = ip->insn_mo->pinfo;
1622 if (mips_relax.sequence != 2
1623 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1627 /* If the previous insn required any delay slots, see if we need
1628 to insert a NOP or two. There are eight kinds of possible
1629 hazards, of which an instruction can have at most one type.
1630 (1) a load from memory delay
1631 (2) a load from a coprocessor delay
1632 (3) an unconditional branch delay
1633 (4) a conditional branch delay
1634 (5) a move to coprocessor register delay
1635 (6) a load coprocessor register from memory delay
1636 (7) a coprocessor condition code delay
1637 (8) a HI/LO special register delay
1639 There are a lot of optimizations we could do that we don't.
1640 In particular, we do not, in general, reorder instructions.
1641 If you use gcc with optimization, it will reorder
1642 instructions and generally do much more optimization then we
1643 do here; repeating all that work in the assembler would only
1644 benefit hand written assembly code, and does not seem worth
1647 /* This is how a NOP is emitted. */
1648 #define emit_nop() \
1650 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1651 : md_number_to_chars (frag_more (4), 0, 4))
1653 /* The previous insn might require a delay slot, depending upon
1654 the contents of the current insn. */
1655 if (! mips_opts.mips16
1656 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1657 && ! gpr_interlocks)
1658 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1659 && ! cop_interlocks)))
1661 /* A load from a coprocessor or from memory. All load
1662 delays delay the use of general register rt for one
1664 /* Itbl support may require additional care here. */
1665 know (prev_pinfo & INSN_WRITE_GPR_T);
1666 if (mips_optimize == 0
1667 || insn_uses_reg (ip,
1668 ((prev_insn.insn_opcode >> OP_SH_RT)
1673 else if (! mips_opts.mips16
1674 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1675 && ! cop_interlocks)
1676 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1677 && ! cop_mem_interlocks)))
1679 /* A generic coprocessor delay. The previous instruction
1680 modified a coprocessor general or control register. If
1681 it modified a control register, we need to avoid any
1682 coprocessor instruction (this is probably not always
1683 required, but it sometimes is). If it modified a general
1684 register, we avoid using that register.
1686 This case is not handled very well. There is no special
1687 knowledge of CP0 handling, and the coprocessors other
1688 than the floating point unit are not distinguished at
1690 /* Itbl support may require additional care here. FIXME!
1691 Need to modify this to include knowledge about
1692 user specified delays! */
1693 if (prev_pinfo & INSN_WRITE_FPR_T)
1695 if (mips_optimize == 0
1696 || insn_uses_reg (ip,
1697 ((prev_insn.insn_opcode >> OP_SH_FT)
1702 else if (prev_pinfo & INSN_WRITE_FPR_S)
1704 if (mips_optimize == 0
1705 || insn_uses_reg (ip,
1706 ((prev_insn.insn_opcode >> OP_SH_FS)
1713 /* We don't know exactly what the previous instruction
1714 does. If the current instruction uses a coprocessor
1715 register, we must insert a NOP. If previous
1716 instruction may set the condition codes, and the
1717 current instruction uses them, we must insert two
1719 /* Itbl support may require additional care here. */
1720 if (mips_optimize == 0
1721 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1722 && (pinfo & INSN_READ_COND_CODE)))
1724 else if (pinfo & INSN_COP)
1728 else if (! mips_opts.mips16
1729 && (prev_pinfo & INSN_WRITE_COND_CODE)
1730 && ! cop_interlocks)
1732 /* The previous instruction sets the coprocessor condition
1733 codes, but does not require a general coprocessor delay
1734 (this means it is a floating point comparison
1735 instruction). If this instruction uses the condition
1736 codes, we need to insert a single NOP. */
1737 /* Itbl support may require additional care here. */
1738 if (mips_optimize == 0
1739 || (pinfo & INSN_READ_COND_CODE))
1743 /* If we're fixing up mfhi/mflo for the r7000 and the
1744 previous insn was an mfhi/mflo and the current insn
1745 reads the register that the mfhi/mflo wrote to, then
1748 else if (mips_7000_hilo_fix
1749 && MF_HILO_INSN (prev_pinfo)
1750 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1757 /* If we're fixing up mfhi/mflo for the r7000 and the
1758 2nd previous insn was an mfhi/mflo and the current insn
1759 reads the register that the mfhi/mflo wrote to, then
1762 else if (mips_7000_hilo_fix
1763 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1764 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1772 else if (prev_pinfo & INSN_READ_LO)
1774 /* The previous instruction reads the LO register; if the
1775 current instruction writes to the LO register, we must
1776 insert two NOPS. Some newer processors have interlocks.
1777 Also the tx39's multiply instructions can be executed
1778 immediately after a read from HI/LO (without the delay),
1779 though the tx39's divide insns still do require the
1781 if (! (hilo_interlocks
1782 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1783 && (mips_optimize == 0
1784 || (pinfo & INSN_WRITE_LO)))
1786 /* Most mips16 branch insns don't have a delay slot.
1787 If a read from LO is immediately followed by a branch
1788 to a write to LO we have a read followed by a write
1789 less than 2 insns away. We assume the target of
1790 a branch might be a write to LO, and insert a nop
1791 between a read and an immediately following branch. */
1792 else if (mips_opts.mips16
1793 && (mips_optimize == 0
1794 || (pinfo & MIPS16_INSN_BRANCH)))
1797 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1799 /* The previous instruction reads the HI register; if the
1800 current instruction writes to the HI register, we must
1801 insert a NOP. Some newer processors have interlocks.
1802 Also the note tx39's multiply above. */
1803 if (! (hilo_interlocks
1804 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1805 && (mips_optimize == 0
1806 || (pinfo & INSN_WRITE_HI)))
1808 /* Most mips16 branch insns don't have a delay slot.
1809 If a read from HI is immediately followed by a branch
1810 to a write to HI we have a read followed by a write
1811 less than 2 insns away. We assume the target of
1812 a branch might be a write to HI, and insert a nop
1813 between a read and an immediately following branch. */
1814 else if (mips_opts.mips16
1815 && (mips_optimize == 0
1816 || (pinfo & MIPS16_INSN_BRANCH)))
1820 /* If the previous instruction was in a noreorder section, then
1821 we don't want to insert the nop after all. */
1822 /* Itbl support may require additional care here. */
1823 if (prev_insn_unreordered)
1826 /* There are two cases which require two intervening
1827 instructions: 1) setting the condition codes using a move to
1828 coprocessor instruction which requires a general coprocessor
1829 delay and then reading the condition codes 2) reading the HI
1830 or LO register and then writing to it (except on processors
1831 which have interlocks). If we are not already emitting a NOP
1832 instruction, we must check for these cases compared to the
1833 instruction previous to the previous instruction. */
1834 if ((! mips_opts.mips16
1835 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1836 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1837 && (pinfo & INSN_READ_COND_CODE)
1838 && ! cop_interlocks)
1839 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1840 && (pinfo & INSN_WRITE_LO)
1841 && ! (hilo_interlocks
1842 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1843 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1844 && (pinfo & INSN_WRITE_HI)
1845 && ! (hilo_interlocks
1846 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1851 if (prev_prev_insn_unreordered)
1854 if (prev_prev_nop && nops == 0)
1857 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1859 /* We're out of bits in pinfo, so we must resort to string
1860 ops here. Shortcuts are selected based on opcodes being
1861 limited to the VR4120 instruction set. */
1863 const char *pn = prev_insn.insn_mo->name;
1864 const char *tn = ip->insn_mo->name;
1865 if (strncmp (pn, "macc", 4) == 0
1866 || strncmp (pn, "dmacc", 5) == 0)
1868 /* Errata 21 - [D]DIV[U] after [D]MACC */
1869 if (strstr (tn, "div"))
1872 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1873 instruction is executed immediately after a MACC or
1874 DMACC instruction, the result of [either instruction]
1876 if (strncmp (tn, "mult", 4) == 0
1877 || strncmp (tn, "dmult", 5) == 0)
1880 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1881 Applies on top of VR4181A MD(1) errata. */
1882 if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn, "mtlo") == 0
1887 || strcmp (tn, "mthi") == 0)
1890 else if (strncmp (pn, "dmult", 5) == 0
1891 && (strncmp (tn, "dmult", 5) == 0
1892 || strncmp (tn, "dmacc", 5) == 0))
1894 /* Here is the rest of errata 23. */
1897 else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
1898 && (strncmp (tn, "macc", 4) == 0
1899 || strncmp (tn, "dmacc", 5) == 0))
1901 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1902 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1903 DDIV or DDIVU instruction, the result of the MACC or
1904 DMACC instruction is incorrect.". This partly overlaps
1905 the workaround for errata 23. */
1908 if (nops < min_nops)
1912 /* If we are being given a nop instruction, don't bother with
1913 one of the nops we would otherwise output. This will only
1914 happen when a nop instruction is used with mips_optimize set
1917 && ! mips_opts.noreorder
1918 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1921 /* Now emit the right number of NOP instructions. */
1922 if (nops > 0 && ! mips_opts.noreorder)
1925 unsigned long old_frag_offset;
1927 struct insn_label_list *l;
1929 old_frag = frag_now;
1930 old_frag_offset = frag_now_fix ();
1932 for (i = 0; i < nops; i++)
1937 listing_prev_line ();
1938 /* We may be at the start of a variant frag. In case we
1939 are, make sure there is enough space for the frag
1940 after the frags created by listing_prev_line. The
1941 argument to frag_grow here must be at least as large
1942 as the argument to all other calls to frag_grow in
1943 this file. We don't have to worry about being in the
1944 middle of a variant frag, because the variants insert
1945 all needed nop instructions themselves. */
1949 for (l = insn_labels; l != NULL; l = l->next)
1953 assert (S_GET_SEGMENT (l->label) == now_seg);
1954 symbol_set_frag (l->label, frag_now);
1955 val = (valueT) frag_now_fix ();
1956 /* mips16 text labels are stored as odd. */
1957 if (mips_opts.mips16)
1959 S_SET_VALUE (l->label, val);
1962 #ifndef NO_ECOFF_DEBUGGING
1963 if (ECOFF_DEBUGGING)
1964 ecoff_fix_loc (old_frag, old_frag_offset);
1967 else if (prev_nop_frag != NULL)
1969 /* We have a frag holding nops we may be able to remove. If
1970 we don't need any nops, we can decrease the size of
1971 prev_nop_frag by the size of one instruction. If we do
1972 need some nops, we count them in prev_nops_required. */
1973 if (prev_nop_frag_since == 0)
1977 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1978 --prev_nop_frag_holds;
1981 prev_nop_frag_required += nops;
1985 if (prev_prev_nop == 0)
1987 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1988 --prev_nop_frag_holds;
1991 ++prev_nop_frag_required;
1994 if (prev_nop_frag_holds <= prev_nop_frag_required)
1995 prev_nop_frag = NULL;
1997 ++prev_nop_frag_since;
1999 /* Sanity check: by the time we reach the second instruction
2000 after prev_nop_frag, we should have used up all the nops
2001 one way or another. */
2002 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2006 /* Record the frag type before frag_var. */
2008 prev_insn_frag_type = prev_insn_frag->fr_type;
2011 && *reloc_type == BFD_RELOC_16_PCREL_S2
2012 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2013 || pinfo & INSN_COND_BRANCH_LIKELY)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts.warn_about_macros
2019 && !(mips_opts.noat && mips_pic != NO_PIC)
2020 && !mips_opts.mips16)
2022 relaxed_branch = TRUE;
2023 f = frag_var (rs_machine_dependent,
2024 relaxed_branch_length
2026 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2027 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2029 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2030 pinfo & INSN_COND_BRANCH_LIKELY,
2031 pinfo & INSN_WRITE_GPR_31,
2033 address_expr->X_add_symbol,
2034 address_expr->X_add_number,
2036 *reloc_type = BFD_RELOC_UNUSED;
2038 else if (*reloc_type > BFD_RELOC_UNUSED)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts.mips16 && address_expr != NULL);
2042 f = frag_var (rs_machine_dependent, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2044 mips16_small, mips16_ext,
2046 & INSN_UNCOND_BRANCH_DELAY),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP)),
2049 make_expr_symbol (address_expr), 0, NULL);
2051 else if (mips_opts.mips16
2053 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2055 /* Make sure there is enough room to swap this instruction with
2056 a following jump instruction. */
2062 if (mips_opts.mips16
2063 && mips_opts.noreorder
2064 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2065 as_warn (_("extended instruction in delay slot"));
2067 if (mips_relax.sequence)
2069 /* If we've reached the end of this frag, turn it into a variant
2070 frag and record the information for the instructions we've
2072 if (frag_room () < 4)
2073 relax_close_frag ();
2074 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2077 if (mips_relax.sequence != 2)
2078 mips_macro_warning.sizes[0] += 4;
2079 if (mips_relax.sequence != 1)
2080 mips_macro_warning.sizes[1] += 4;
2085 fixp[0] = fixp[1] = fixp[2] = NULL;
2086 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2088 if (address_expr->X_op == O_constant)
2092 switch (*reloc_type)
2095 ip->insn_opcode |= address_expr->X_add_number;
2098 case BFD_RELOC_MIPS_HIGHEST:
2099 tmp = (address_expr->X_add_number
2100 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2102 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2105 case BFD_RELOC_MIPS_HIGHER:
2106 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2107 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2110 case BFD_RELOC_HI16_S:
2111 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2115 case BFD_RELOC_HI16:
2116 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2119 case BFD_RELOC_UNUSED:
2120 case BFD_RELOC_LO16:
2121 case BFD_RELOC_MIPS_GOT_DISP:
2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2125 case BFD_RELOC_MIPS_JMP:
2126 if ((address_expr->X_add_number & 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr->X_add_number);
2129 if (address_expr->X_add_number & ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr->X_add_number);
2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP:
2136 if ((address_expr->X_add_number & 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr->X_add_number);
2139 if (address_expr->X_add_number & ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr->X_add_number);
2143 (((address_expr->X_add_number & 0x7c0000) << 3)
2144 | ((address_expr->X_add_number & 0xf800000) >> 7)
2145 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2:
2155 else if (*reloc_type < BFD_RELOC_UNUSED)
2158 reloc_howto_type *howto;
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i = 1; i < 3; i++)
2164 if (reloc_type[i] == BFD_RELOC_UNUSED)
2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2169 bfd_get_reloc_size(howto),
2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2177 && ! howto->partial_inplace
2178 && (reloc_type[0] == BFD_RELOC_16
2179 || reloc_type[0] == BFD_RELOC_32
2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2181 || reloc_type[0] == BFD_RELOC_HI16_S
2182 || reloc_type[0] == BFD_RELOC_LO16
2183 || reloc_type[0] == BFD_RELOC_GPREL16
2184 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2185 || reloc_type[0] == BFD_RELOC_GPREL32
2186 || reloc_type[0] == BFD_RELOC_64
2187 || reloc_type[0] == BFD_RELOC_CTOR
2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2194 fixp[0]->fx_no_overflow = 1;
2196 if (mips_relax.sequence)
2198 if (mips_relax.first_fixup == 0)
2199 mips_relax.first_fixup = fixp[0];
2201 else if (reloc_needs_lo_p (*reloc_type))
2203 struct mips_hi_fixup *hi_fixup;
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup = mips_hi_fixup_list;
2208 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2210 hi_fixup = ((struct mips_hi_fixup *)
2211 xmalloc (sizeof (struct mips_hi_fixup)));
2212 hi_fixup->next = mips_hi_fixup_list;
2213 mips_hi_fixup_list = hi_fixup;
2215 hi_fixup->fixp = fixp[0];
2216 hi_fixup->seg = now_seg;
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i = 1; i < 3; i++)
2225 if (reloc_type[i] != BFD_RELOC_UNUSED)
2227 address_expr->X_op = O_absent;
2228 address_expr->X_add_symbol = 0;
2229 address_expr->X_add_number = 0;
2231 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2232 fixp[0]->fx_size, address_expr,
2233 FALSE, reloc_type[i]);
2235 /* Use fx_tcbit to mark compound relocs. */
2236 fixp[0]->fx_tcbit = 1;
2237 fixp[i]->fx_tcbit = 1;
2242 if (! mips_opts.mips16)
2244 md_number_to_chars (f, ip->insn_opcode, 4);
2246 dwarf2_emit_insn (4);
2249 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2251 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2252 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2254 /* The value passed to dwarf2_emit_insn is the distance between
2255 the end of the current instruction and the address that should
2256 be recorded in the debug tables. Since we want to use ISA-encoded
2257 addresses in MIPS16 debug info, the value is one byte less than
2258 the real instruction length. */
2259 dwarf2_emit_insn (3);
2266 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2269 md_number_to_chars (f, ip->insn_opcode, 2);
2271 dwarf2_emit_insn (ip->use_extend ? 3 : 1);
2275 /* Update the register mask information. */
2276 if (! mips_opts.mips16)
2278 if (pinfo & INSN_WRITE_GPR_D)
2279 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2280 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2281 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2282 if (pinfo & INSN_READ_GPR_S)
2283 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2284 if (pinfo & INSN_WRITE_GPR_31)
2285 mips_gprmask |= 1 << RA;
2286 if (pinfo & INSN_WRITE_FPR_D)
2287 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2288 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2289 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2290 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2291 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2292 if ((pinfo & INSN_READ_FPR_R) != 0)
2293 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2294 if (pinfo & INSN_COP)
2296 /* We don't keep enough information to sort these cases out.
2297 The itbl support does keep this information however, although
2298 we currently don't support itbl fprmats as part of the cop
2299 instruction. May want to add this support in the future. */
2301 /* Never set the bit for $0, which is always zero. */
2302 mips_gprmask &= ~1 << 0;
2306 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2307 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2308 & MIPS16OP_MASK_RX);
2309 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2310 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2311 & MIPS16OP_MASK_RY);
2312 if (pinfo & MIPS16_INSN_WRITE_Z)
2313 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2314 & MIPS16OP_MASK_RZ);
2315 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2316 mips_gprmask |= 1 << TREG;
2317 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2318 mips_gprmask |= 1 << SP;
2319 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2320 mips_gprmask |= 1 << RA;
2321 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2322 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2323 if (pinfo & MIPS16_INSN_READ_Z)
2324 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2325 & MIPS16OP_MASK_MOVE32Z);
2326 if (pinfo & MIPS16_INSN_READ_GPR_X)
2327 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2328 & MIPS16OP_MASK_REGR32);
2331 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2333 /* Filling the branch delay slot is more complex. We try to
2334 switch the branch with the previous instruction, which we can
2335 do if the previous instruction does not set up a condition
2336 that the branch tests and if the branch is not itself the
2337 target of any branch. */
2338 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2339 || (pinfo & INSN_COND_BRANCH_DELAY))
2341 if (mips_optimize < 2
2342 /* If we have seen .set volatile or .set nomove, don't
2344 || mips_opts.nomove != 0
2345 /* If we had to emit any NOP instructions, then we
2346 already know we can not swap. */
2348 /* If we don't even know the previous insn, we can not
2350 || ! prev_insn_valid
2351 /* If the previous insn is already in a branch delay
2352 slot, then we can not swap. */
2353 || prev_insn_is_delay_slot
2354 /* If the previous previous insn was in a .set
2355 noreorder, we can't swap. Actually, the MIPS
2356 assembler will swap in this situation. However, gcc
2357 configured -with-gnu-as will generate code like
2363 in which we can not swap the bne and INSN. If gcc is
2364 not configured -with-gnu-as, it does not output the
2365 .set pseudo-ops. We don't have to check
2366 prev_insn_unreordered, because prev_insn_valid will
2367 be 0 in that case. We don't want to use
2368 prev_prev_insn_valid, because we do want to be able
2369 to swap at the start of a function. */
2370 || prev_prev_insn_unreordered
2371 /* If the branch is itself the target of a branch, we
2372 can not swap. We cheat on this; all we check for is
2373 whether there is a label on this instruction. If
2374 there are any branches to anything other than a
2375 label, users must use .set noreorder. */
2376 || insn_labels != NULL
2377 /* If the previous instruction is in a variant frag
2378 other than this branch's one, we cannot do the swap.
2379 This does not apply to the mips16, which uses variant
2380 frags for different purposes. */
2381 || (! mips_opts.mips16
2382 && prev_insn_frag_type == rs_machine_dependent)
2383 /* If the branch reads the condition codes, we don't
2384 even try to swap, because in the sequence
2389 we can not swap, and I don't feel like handling that
2391 || (! mips_opts.mips16
2392 && (pinfo & INSN_READ_COND_CODE)
2393 && ! cop_interlocks)
2394 /* We can not swap with an instruction that requires a
2395 delay slot, because the target of the branch might
2396 interfere with that instruction. */
2397 || (! mips_opts.mips16
2399 /* Itbl support may require additional care here. */
2400 & (INSN_LOAD_COPROC_DELAY
2401 | INSN_COPROC_MOVE_DELAY
2402 | INSN_WRITE_COND_CODE))
2403 && ! cop_interlocks)
2404 || (! (hilo_interlocks
2405 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2409 || (! mips_opts.mips16
2410 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2411 && ! gpr_interlocks)
2412 || (! mips_opts.mips16
2413 /* Itbl support may require additional care here. */
2414 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2415 && ! cop_mem_interlocks)
2416 /* We can not swap with a branch instruction. */
2418 & (INSN_UNCOND_BRANCH_DELAY
2419 | INSN_COND_BRANCH_DELAY
2420 | INSN_COND_BRANCH_LIKELY))
2421 /* We do not swap with a trap instruction, since it
2422 complicates trap handlers to have the trap
2423 instruction be in a delay slot. */
2424 || (prev_pinfo & INSN_TRAP)
2425 /* If the branch reads a register that the previous
2426 instruction sets, we can not swap. */
2427 || (! mips_opts.mips16
2428 && (prev_pinfo & INSN_WRITE_GPR_T)
2429 && insn_uses_reg (ip,
2430 ((prev_insn.insn_opcode >> OP_SH_RT)
2433 || (! mips_opts.mips16
2434 && (prev_pinfo & INSN_WRITE_GPR_D)
2435 && insn_uses_reg (ip,
2436 ((prev_insn.insn_opcode >> OP_SH_RD)
2439 || (mips_opts.mips16
2440 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2441 && insn_uses_reg (ip,
2442 ((prev_insn.insn_opcode
2444 & MIPS16OP_MASK_RX),
2446 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2447 && insn_uses_reg (ip,
2448 ((prev_insn.insn_opcode
2450 & MIPS16OP_MASK_RY),
2452 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2453 && insn_uses_reg (ip,
2454 ((prev_insn.insn_opcode
2456 & MIPS16OP_MASK_RZ),
2458 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2459 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2460 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2461 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2462 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2463 && insn_uses_reg (ip,
2464 MIPS16OP_EXTRACT_REG32R (prev_insn.
2467 /* If the branch writes a register that the previous
2468 instruction sets, we can not swap (we know that
2469 branches write only to RD or to $31). */
2470 || (! mips_opts.mips16
2471 && (prev_pinfo & INSN_WRITE_GPR_T)
2472 && (((pinfo & INSN_WRITE_GPR_D)
2473 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2474 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2475 || ((pinfo & INSN_WRITE_GPR_31)
2476 && (((prev_insn.insn_opcode >> OP_SH_RT)
2479 || (! mips_opts.mips16
2480 && (prev_pinfo & INSN_WRITE_GPR_D)
2481 && (((pinfo & INSN_WRITE_GPR_D)
2482 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2483 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2484 || ((pinfo & INSN_WRITE_GPR_31)
2485 && (((prev_insn.insn_opcode >> OP_SH_RD)
2488 || (mips_opts.mips16
2489 && (pinfo & MIPS16_INSN_WRITE_31)
2490 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2491 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2492 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2494 /* If the branch writes a register that the previous
2495 instruction reads, we can not swap (we know that
2496 branches only write to RD or to $31). */
2497 || (! mips_opts.mips16
2498 && (pinfo & INSN_WRITE_GPR_D)
2499 && insn_uses_reg (&prev_insn,
2500 ((ip->insn_opcode >> OP_SH_RD)
2503 || (! mips_opts.mips16
2504 && (pinfo & INSN_WRITE_GPR_31)
2505 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2506 || (mips_opts.mips16
2507 && (pinfo & MIPS16_INSN_WRITE_31)
2508 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2509 /* If the previous previous instruction has a load
2510 delay, and sets a register that the branch reads, we
2512 || (! mips_opts.mips16
2513 /* Itbl support may require additional care here. */
2514 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2515 && ! cop_interlocks)
2516 || ((prev_prev_insn.insn_mo->pinfo
2517 & INSN_LOAD_MEMORY_DELAY)
2518 && ! gpr_interlocks))
2519 && insn_uses_reg (ip,
2520 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2523 /* If one instruction sets a condition code and the
2524 other one uses a condition code, we can not swap. */
2525 || ((pinfo & INSN_READ_COND_CODE)
2526 && (prev_pinfo & INSN_WRITE_COND_CODE))
2527 || ((pinfo & INSN_WRITE_COND_CODE)
2528 && (prev_pinfo & INSN_READ_COND_CODE))
2529 /* If the previous instruction uses the PC, we can not
2531 || (mips_opts.mips16
2532 && (prev_pinfo & MIPS16_INSN_READ_PC))
2533 /* If the previous instruction was extended, we can not
2535 || (mips_opts.mips16 && prev_insn_extended)
2536 /* If the previous instruction had a fixup in mips16
2537 mode, we can not swap. This normally means that the
2538 previous instruction was a 4 byte branch anyhow. */
2539 || (mips_opts.mips16 && prev_insn_fixp[0])
2540 /* If the previous instruction is a sync, sync.l, or
2541 sync.p, we can not swap. */
2542 || (prev_pinfo & INSN_SYNC))
2544 /* We could do even better for unconditional branches to
2545 portions of this object file; we could pick up the
2546 instruction at the destination, put it in the delay
2547 slot, and bump the destination address. */
2549 /* Update the previous insn information. */
2550 prev_prev_insn = *ip;
2551 prev_insn.insn_mo = &dummy_opcode;
2555 /* It looks like we can actually do the swap. */
2556 if (! mips_opts.mips16)
2561 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2562 if (!relaxed_branch)
2564 /* If this is not a relaxed branch, then just
2565 swap the instructions. */
2566 memcpy (temp, prev_f, 4);
2567 memcpy (prev_f, f, 4);
2568 memcpy (f, temp, 4);
2572 /* If this is a relaxed branch, then we move the
2573 instruction to be placed in the delay slot to
2574 the current frag, shrinking the fixed part of
2575 the originating frag. If the branch occupies
2576 the tail of the latter, we move it backwards,
2577 into the space freed by the moved instruction. */
2579 memcpy (f, prev_f, 4);
2580 prev_insn_frag->fr_fix -= 4;
2581 if (prev_insn_frag->fr_type == rs_machine_dependent)
2582 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2585 if (prev_insn_fixp[0])
2587 prev_insn_fixp[0]->fx_frag = frag_now;
2588 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2590 if (prev_insn_fixp[1])
2592 prev_insn_fixp[1]->fx_frag = frag_now;
2593 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2595 if (prev_insn_fixp[2])
2597 prev_insn_fixp[2]->fx_frag = frag_now;
2598 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2600 if (prev_insn_fixp[0] && HAVE_NEWABI
2601 && prev_insn_frag != frag_now
2602 && (prev_insn_fixp[0]->fx_r_type
2603 == BFD_RELOC_MIPS_GOT_DISP
2604 || (prev_insn_fixp[0]->fx_r_type
2605 == BFD_RELOC_MIPS_CALL16)))
2607 /* To avoid confusion in tc_gen_reloc, we must
2608 ensure that this does not become a variant
2610 force_new_frag = TRUE;
2613 if (!relaxed_branch)
2617 fixp[0]->fx_frag = prev_insn_frag;
2618 fixp[0]->fx_where = prev_insn_where;
2622 fixp[1]->fx_frag = prev_insn_frag;
2623 fixp[1]->fx_where = prev_insn_where;
2627 fixp[2]->fx_frag = prev_insn_frag;
2628 fixp[2]->fx_where = prev_insn_where;
2631 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2634 fixp[0]->fx_where -= 4;
2636 fixp[1]->fx_where -= 4;
2638 fixp[2]->fx_where -= 4;
2646 assert (prev_insn_fixp[0] == NULL);
2647 assert (prev_insn_fixp[1] == NULL);
2648 assert (prev_insn_fixp[2] == NULL);
2649 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2650 memcpy (temp, prev_f, 2);
2651 memcpy (prev_f, f, 2);
2652 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2654 assert (*reloc_type == BFD_RELOC_UNUSED);
2655 memcpy (f, temp, 2);
2659 memcpy (f, f + 2, 2);
2660 memcpy (f + 2, temp, 2);
2664 fixp[0]->fx_frag = prev_insn_frag;
2665 fixp[0]->fx_where = prev_insn_where;
2669 fixp[1]->fx_frag = prev_insn_frag;
2670 fixp[1]->fx_where = prev_insn_where;
2674 fixp[2]->fx_frag = prev_insn_frag;
2675 fixp[2]->fx_where = prev_insn_where;
2679 /* Update the previous insn information; leave prev_insn
2681 prev_prev_insn = *ip;
2683 prev_insn_is_delay_slot = 1;
2685 /* If that was an unconditional branch, forget the previous
2686 insn information. */
2687 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2689 prev_prev_insn.insn_mo = &dummy_opcode;
2690 prev_insn.insn_mo = &dummy_opcode;
2693 prev_insn_fixp[0] = NULL;
2694 prev_insn_fixp[1] = NULL;
2695 prev_insn_fixp[2] = NULL;
2696 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2697 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2698 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2699 prev_insn_extended = 0;
2701 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2703 /* We don't yet optimize a branch likely. What we should do
2704 is look at the target, copy the instruction found there
2705 into the delay slot, and increment the branch to jump to
2706 the next instruction. */
2708 /* Update the previous insn information. */
2709 prev_prev_insn = *ip;
2710 prev_insn.insn_mo = &dummy_opcode;
2711 prev_insn_fixp[0] = NULL;
2712 prev_insn_fixp[1] = NULL;
2713 prev_insn_fixp[2] = NULL;
2714 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2715 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2716 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2717 prev_insn_extended = 0;
2718 prev_insn_is_delay_slot = 1;
2722 /* Update the previous insn information. */
2724 prev_prev_insn.insn_mo = &dummy_opcode;
2726 prev_prev_insn = prev_insn;
2729 /* Any time we see a branch, we always fill the delay slot
2730 immediately; since this insn is not a branch, we know it
2731 is not in a delay slot. */
2732 prev_insn_is_delay_slot = 0;
2734 prev_insn_fixp[0] = fixp[0];
2735 prev_insn_fixp[1] = fixp[1];
2736 prev_insn_fixp[2] = fixp[2];
2737 prev_insn_reloc_type[0] = reloc_type[0];
2738 prev_insn_reloc_type[1] = reloc_type[1];
2739 prev_insn_reloc_type[2] = reloc_type[2];
2740 if (mips_opts.mips16)
2741 prev_insn_extended = (ip->use_extend
2742 || *reloc_type > BFD_RELOC_UNUSED);
2745 prev_prev_insn_unreordered = prev_insn_unreordered;
2746 prev_insn_unreordered = 0;
2747 prev_insn_frag = frag_now;
2748 prev_insn_where = f - frag_now->fr_literal;
2749 prev_insn_valid = 1;
2751 else if (mips_relax.sequence != 2)
2753 /* We need to record a bit of information even when we are not
2754 reordering, in order to determine the base address for mips16
2755 PC relative relocs. */
2756 prev_prev_insn = prev_insn;
2758 prev_insn_reloc_type[0] = reloc_type[0];
2759 prev_insn_reloc_type[1] = reloc_type[1];
2760 prev_insn_reloc_type[2] = reloc_type[2];
2761 prev_prev_insn_unreordered = prev_insn_unreordered;
2762 prev_insn_unreordered = 1;
2765 /* We just output an insn, so the next one doesn't have a label. */
2766 mips_clear_insn_labels ();
2769 /* This function forgets that there was any previous instruction or
2770 label. If PRESERVE is non-zero, it remembers enough information to
2771 know whether nops are needed before a noreorder section. */
2774 mips_no_prev_insn (int preserve)
2778 prev_insn.insn_mo = &dummy_opcode;
2779 prev_prev_insn.insn_mo = &dummy_opcode;
2780 prev_nop_frag = NULL;
2781 prev_nop_frag_holds = 0;
2782 prev_nop_frag_required = 0;
2783 prev_nop_frag_since = 0;
2785 prev_insn_valid = 0;
2786 prev_insn_is_delay_slot = 0;
2787 prev_insn_unreordered = 0;
2788 prev_insn_extended = 0;
2789 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2790 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2791 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2792 prev_prev_insn_unreordered = 0;
2793 mips_clear_insn_labels ();
2796 /* This function must be called whenever we turn on noreorder or emit
2797 something other than instructions. It inserts any NOPS which might
2798 be needed by the previous instruction, and clears the information
2799 kept for the previous instructions. The INSNS parameter is true if
2800 instructions are to follow. */
2803 mips_emit_delays (bfd_boolean insns)
2805 if (! mips_opts.noreorder)
2810 if ((! mips_opts.mips16
2811 && ((prev_insn.insn_mo->pinfo
2812 & (INSN_LOAD_COPROC_DELAY
2813 | INSN_COPROC_MOVE_DELAY
2814 | INSN_WRITE_COND_CODE))
2815 && ! cop_interlocks))
2816 || (! hilo_interlocks
2817 && (prev_insn.insn_mo->pinfo
2820 || (! mips_opts.mips16
2821 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2822 && ! gpr_interlocks)
2823 || (! mips_opts.mips16
2824 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2825 && ! cop_mem_interlocks))
2827 /* Itbl support may require additional care here. */
2829 if ((! mips_opts.mips16
2830 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2831 && ! cop_interlocks))
2832 || (! hilo_interlocks
2833 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2834 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2837 if (prev_insn_unreordered)
2840 else if ((! mips_opts.mips16
2841 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2842 && ! cop_interlocks))
2843 || (! hilo_interlocks
2844 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2845 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2847 /* Itbl support may require additional care here. */
2848 if (! prev_prev_insn_unreordered)
2852 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2855 const char *pn = prev_insn.insn_mo->name;
2856 if (strncmp (pn, "macc", 4) == 0
2857 || strncmp (pn, "dmacc", 5) == 0
2858 || strncmp (pn, "dmult", 5) == 0
2859 || strstr (pn, "div"))
2861 if (nops < min_nops)
2867 struct insn_label_list *l;
2871 /* Record the frag which holds the nop instructions, so
2872 that we can remove them if we don't need them. */
2873 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2874 prev_nop_frag = frag_now;
2875 prev_nop_frag_holds = nops;
2876 prev_nop_frag_required = 0;
2877 prev_nop_frag_since = 0;
2880 for (; nops > 0; --nops)
2885 /* Move on to a new frag, so that it is safe to simply
2886 decrease the size of prev_nop_frag. */
2887 frag_wane (frag_now);
2891 for (l = insn_labels; l != NULL; l = l->next)
2895 assert (S_GET_SEGMENT (l->label) == now_seg);
2896 symbol_set_frag (l->label, frag_now);
2897 val = (valueT) frag_now_fix ();
2898 /* mips16 text labels are stored as odd. */
2899 if (mips_opts.mips16)
2901 S_SET_VALUE (l->label, val);
2906 /* Mark instruction labels in mips16 mode. */
2908 mips16_mark_labels ();
2910 mips_no_prev_insn (insns);
2913 /* Set up global variables for the start of a new macro. */
2918 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2919 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2920 && (prev_insn.insn_mo->pinfo
2921 & (INSN_UNCOND_BRANCH_DELAY
2922 | INSN_COND_BRANCH_DELAY
2923 | INSN_COND_BRANCH_LIKELY)) != 0);
2926 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2927 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2928 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2931 macro_warning (relax_substateT subtype)
2933 if (subtype & RELAX_DELAY_SLOT)
2934 return _("Macro instruction expanded into multiple instructions"
2935 " in a branch delay slot");
2936 else if (subtype & RELAX_NOMACRO)
2937 return _("Macro instruction expanded into multiple instructions");
2942 /* Finish up a macro. Emit warnings as appropriate. */
2947 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2949 relax_substateT subtype;
2951 /* Set up the relaxation warning flags. */
2953 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2954 subtype |= RELAX_SECOND_LONGER;
2955 if (mips_opts.warn_about_macros)
2956 subtype |= RELAX_NOMACRO;
2957 if (mips_macro_warning.delay_slot_p)
2958 subtype |= RELAX_DELAY_SLOT;
2960 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2962 /* Either the macro has a single implementation or both
2963 implementations are longer than 4 bytes. Emit the
2965 const char *msg = macro_warning (subtype);
2971 /* One implementation might need a warning but the other
2972 definitely doesn't. */
2973 mips_macro_warning.first_frag->fr_subtype |= subtype;
2978 /* Build an instruction created by a macro expansion. This is passed
2979 a pointer to the count of instructions created so far, an
2980 expression, the name of the instruction to build, an operand format
2981 string, and corresponding arguments. */
2984 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2986 struct mips_cl_insn insn;
2987 bfd_reloc_code_real_type r[3];
2990 va_start (args, fmt);
2992 if (mips_opts.mips16)
2994 mips16_macro_build (ep, name, fmt, args);
2999 r[0] = BFD_RELOC_UNUSED;
3000 r[1] = BFD_RELOC_UNUSED;
3001 r[2] = BFD_RELOC_UNUSED;
3002 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3003 assert (insn.insn_mo);
3004 assert (strcmp (name, insn.insn_mo->name) == 0);
3006 /* Search until we get a match for NAME. */
3009 /* It is assumed here that macros will never generate
3010 MDMX or MIPS-3D instructions. */
3011 if (strcmp (fmt, insn.insn_mo->args) == 0
3012 && insn.insn_mo->pinfo != INSN_MACRO
3013 && OPCODE_IS_MEMBER (insn.insn_mo,
3015 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3017 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3021 assert (insn.insn_mo->name);
3022 assert (strcmp (name, insn.insn_mo->name) == 0);
3025 insn.insn_opcode = insn.insn_mo->match;
3043 insn.insn_opcode |= (va_arg (args, int)
3044 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3049 /* Note that in the macro case, these arguments are already
3050 in MSB form. (When handling the instruction in the
3051 non-macro case, these arguments are sizes from which
3052 MSB values must be calculated.) */
3053 insn.insn_opcode |= (va_arg (args, int)
3054 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3060 /* Note that in the macro case, these arguments are already
3061 in MSBD form. (When handling the instruction in the
3062 non-macro case, these arguments are sizes from which
3063 MSBD values must be calculated.) */
3064 insn.insn_opcode |= (va_arg (args, int)
3065 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3076 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3080 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3085 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3091 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3096 int tmp = va_arg (args, int);
3098 insn.insn_opcode |= tmp << OP_SH_RT;
3099 insn.insn_opcode |= tmp << OP_SH_RD;
3105 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3112 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3116 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3120 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3124 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3128 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3135 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3141 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3142 assert (*r == BFD_RELOC_GPREL16
3143 || *r == BFD_RELOC_MIPS_LITERAL
3144 || *r == BFD_RELOC_MIPS_HIGHER
3145 || *r == BFD_RELOC_HI16_S
3146 || *r == BFD_RELOC_LO16
3147 || *r == BFD_RELOC_MIPS_GOT16
3148 || *r == BFD_RELOC_MIPS_CALL16
3149 || *r == BFD_RELOC_MIPS_GOT_DISP
3150 || *r == BFD_RELOC_MIPS_GOT_PAGE
3151 || *r == BFD_RELOC_MIPS_GOT_OFST
3152 || *r == BFD_RELOC_MIPS_GOT_LO16
3153 || *r == BFD_RELOC_MIPS_CALL_LO16);
3157 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3159 && (ep->X_op == O_constant
3160 || (ep->X_op == O_symbol
3161 && (*r == BFD_RELOC_MIPS_HIGHEST
3162 || *r == BFD_RELOC_HI16_S
3163 || *r == BFD_RELOC_HI16
3164 || *r == BFD_RELOC_GPREL16
3165 || *r == BFD_RELOC_MIPS_GOT_HI16
3166 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3170 assert (ep != NULL);
3172 * This allows macro() to pass an immediate expression for
3173 * creating short branches without creating a symbol.
3174 * Note that the expression still might come from the assembly
3175 * input, in which case the value is not checked for range nor
3176 * is a relocation entry generated (yuck).
3178 if (ep->X_op == O_constant)
3180 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3184 *r = BFD_RELOC_16_PCREL_S2;
3188 assert (ep != NULL);
3189 *r = BFD_RELOC_MIPS_JMP;
3193 insn.insn_opcode |= va_arg (args, unsigned long);
3202 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3204 append_insn (&insn, ep, r);
3208 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3211 struct mips_cl_insn insn;
3212 bfd_reloc_code_real_type r[3]
3213 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3215 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3216 assert (insn.insn_mo);
3217 assert (strcmp (name, insn.insn_mo->name) == 0);
3219 while (strcmp (fmt, insn.insn_mo->args) != 0
3220 || insn.insn_mo->pinfo == INSN_MACRO)
3223 assert (insn.insn_mo->name);
3224 assert (strcmp (name, insn.insn_mo->name) == 0);
3227 insn.insn_opcode = insn.insn_mo->match;
3228 insn.use_extend = FALSE;
3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3252 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3256 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3260 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3270 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3277 regno = va_arg (args, int);
3278 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3279 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3300 assert (ep != NULL);
3302 if (ep->X_op != O_constant)
3303 *r = (int) BFD_RELOC_UNUSED + c;
3306 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3307 FALSE, &insn.insn_opcode, &insn.use_extend,
3310 *r = BFD_RELOC_UNUSED;
3316 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3323 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3325 append_insn (&insn, ep, r);
3329 * Generate a "jalr" instruction with a relocation hint to the called
3330 * function. This occurs in NewABI PIC code.
3333 macro_build_jalr (expressionS *ep)
3342 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3344 fix_new_exp (frag_now, f - frag_now->fr_literal,
3345 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3349 * Generate a "lui" instruction.
3352 macro_build_lui (expressionS *ep, int regnum)
3354 expressionS high_expr;
3355 struct mips_cl_insn insn;
3356 bfd_reloc_code_real_type r[3]
3357 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3358 const char *name = "lui";
3359 const char *fmt = "t,u";
3361 assert (! mips_opts.mips16);
3365 if (high_expr.X_op == O_constant)
3367 /* we can compute the instruction now without a relocation entry */
3368 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3370 *r = BFD_RELOC_UNUSED;
3374 assert (ep->X_op == O_symbol);
3375 /* _gp_disp is a special case, used from s_cpload. */
3376 assert (mips_pic == NO_PIC
3378 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3379 *r = BFD_RELOC_HI16_S;
3382 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3383 assert (insn.insn_mo);
3384 assert (strcmp (name, insn.insn_mo->name) == 0);
3385 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3387 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3388 if (*r == BFD_RELOC_UNUSED)
3390 insn.insn_opcode |= high_expr.X_add_number;
3391 append_insn (&insn, NULL, r);
3394 append_insn (&insn, &high_expr, r);
3397 /* Generate a sequence of instructions to do a load or store from a constant
3398 offset off of a base register (breg) into/from a target register (treg),
3399 using AT if necessary. */
3401 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3402 int treg, int breg, int dbl)
3404 assert (ep->X_op == O_constant);
3406 /* Sign-extending 32-bit constants makes their handling easier. */
3407 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3408 == ~((bfd_vma) 0x7fffffff)))
3410 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3411 as_bad (_("constant too large"));
3413 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3417 /* Right now, this routine can only handle signed 32-bit constants. */
3418 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3419 as_warn (_("operand overflow"));
3421 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3423 /* Signed 16-bit offset will fit in the op. Easy! */
3424 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3428 /* 32-bit offset, need multiple instructions and AT, like:
3429 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3430 addu $tempreg,$tempreg,$breg
3431 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3432 to handle the complete offset. */
3433 macro_build_lui (ep, AT);
3434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3435 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3438 as_warn (_("Macro used $at after \".set noat\""));
3443 * Generates code to set the $at register to true (one)
3444 * if reg is less than the immediate expression.
3447 set_at (int reg, int unsignedp)
3449 if (imm_expr.X_op == O_constant
3450 && imm_expr.X_add_number >= -0x8000
3451 && imm_expr.X_add_number < 0x8000)
3452 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3453 AT, reg, BFD_RELOC_LO16);
3456 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3457 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3462 normalize_constant_expr (expressionS *ex)
3464 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3465 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3469 /* Warn if an expression is not a constant. */
3472 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3474 if (ex->X_op == O_big)
3475 as_bad (_("unsupported large constant"));
3476 else if (ex->X_op != O_constant)
3477 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3479 normalize_constant_expr (ex);
3482 /* Count the leading zeroes by performing a binary chop. This is a
3483 bulky bit of source, but performance is a LOT better for the
3484 majority of values than a simple loop to count the bits:
3485 for (lcnt = 0; (lcnt < 32); lcnt++)
3486 if ((v) & (1 << (31 - lcnt)))
3488 However it is not code size friendly, and the gain will drop a bit
3489 on certain cached systems.
3491 #define COUNT_TOP_ZEROES(v) \
3492 (((v) & ~0xffff) == 0 \
3493 ? ((v) & ~0xff) == 0 \
3494 ? ((v) & ~0xf) == 0 \
3495 ? ((v) & ~0x3) == 0 \
3496 ? ((v) & ~0x1) == 0 \
3501 : ((v) & ~0x7) == 0 \
3504 : ((v) & ~0x3f) == 0 \
3505 ? ((v) & ~0x1f) == 0 \
3508 : ((v) & ~0x7f) == 0 \
3511 : ((v) & ~0xfff) == 0 \
3512 ? ((v) & ~0x3ff) == 0 \
3513 ? ((v) & ~0x1ff) == 0 \
3516 : ((v) & ~0x7ff) == 0 \
3519 : ((v) & ~0x3fff) == 0 \
3520 ? ((v) & ~0x1fff) == 0 \
3523 : ((v) & ~0x7fff) == 0 \
3526 : ((v) & ~0xffffff) == 0 \
3527 ? ((v) & ~0xfffff) == 0 \
3528 ? ((v) & ~0x3ffff) == 0 \
3529 ? ((v) & ~0x1ffff) == 0 \
3532 : ((v) & ~0x7ffff) == 0 \
3535 : ((v) & ~0x3fffff) == 0 \
3536 ? ((v) & ~0x1fffff) == 0 \
3539 : ((v) & ~0x7fffff) == 0 \
3542 : ((v) & ~0xfffffff) == 0 \
3543 ? ((v) & ~0x3ffffff) == 0 \
3544 ? ((v) & ~0x1ffffff) == 0 \
3547 : ((v) & ~0x7ffffff) == 0 \
3550 : ((v) & ~0x3fffffff) == 0 \
3551 ? ((v) & ~0x1fffffff) == 0 \
3554 : ((v) & ~0x7fffffff) == 0 \
3559 * This routine generates the least number of instructions necessary to load
3560 * an absolute expression value into a register.
3563 load_register (int reg, expressionS *ep, int dbl)
3566 expressionS hi32, lo32;
3568 if (ep->X_op != O_big)
3570 assert (ep->X_op == O_constant);
3572 /* Sign-extending 32-bit constants makes their handling easier. */
3573 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3574 == ~((bfd_vma) 0x7fffffff)))
3576 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3577 as_bad (_("constant too large"));
3579 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3583 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3585 /* We can handle 16 bit signed values with an addiu to
3586 $zero. No need to ever use daddiu here, since $zero and
3587 the result are always correct in 32 bit mode. */
3588 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3591 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3593 /* We can handle 16 bit unsigned values with an ori to
3595 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3598 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3600 /* 32 bit values require an lui. */
3601 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3602 if ((ep->X_add_number & 0xffff) != 0)
3603 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3608 /* The value is larger than 32 bits. */
3610 if (HAVE_32BIT_GPRS)
3612 as_bad (_("Number (0x%lx) larger than 32 bits"),
3613 (unsigned long) ep->X_add_number);
3614 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3618 if (ep->X_op != O_big)
3621 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3622 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3623 hi32.X_add_number &= 0xffffffff;
3625 lo32.X_add_number &= 0xffffffff;
3629 assert (ep->X_add_number > 2);
3630 if (ep->X_add_number == 3)
3631 generic_bignum[3] = 0;
3632 else if (ep->X_add_number > 4)
3633 as_bad (_("Number larger than 64 bits"));
3634 lo32.X_op = O_constant;
3635 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3636 hi32.X_op = O_constant;
3637 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3640 if (hi32.X_add_number == 0)
3645 unsigned long hi, lo;
3647 if (hi32.X_add_number == (offsetT) 0xffffffff)
3649 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3651 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3654 if (lo32.X_add_number & 0x80000000)
3656 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3657 if (lo32.X_add_number & 0xffff)
3658 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3663 /* Check for 16bit shifted constant. We know that hi32 is
3664 non-zero, so start the mask on the first bit of the hi32
3669 unsigned long himask, lomask;
3673 himask = 0xffff >> (32 - shift);
3674 lomask = (0xffff << shift) & 0xffffffff;
3678 himask = 0xffff << (shift - 32);
3681 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3682 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3686 tmp.X_op = O_constant;
3688 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3689 | (lo32.X_add_number >> shift));
3691 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3692 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3693 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3694 reg, reg, (shift >= 32) ? shift - 32 : shift);
3699 while (shift <= (64 - 16));
3701 /* Find the bit number of the lowest one bit, and store the
3702 shifted value in hi/lo. */
3703 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3704 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3708 while ((lo & 1) == 0)
3713 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3719 while ((hi & 1) == 0)
3728 /* Optimize if the shifted value is a (power of 2) - 1. */
3729 if ((hi == 0 && ((lo + 1) & lo) == 0)
3730 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3732 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3737 /* This instruction will set the register to be all
3739 tmp.X_op = O_constant;
3740 tmp.X_add_number = (offsetT) -1;
3741 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3745 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3746 reg, reg, (bit >= 32) ? bit - 32 : bit);
3748 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3749 reg, reg, (shift >= 32) ? shift - 32 : shift);
3754 /* Sign extend hi32 before calling load_register, because we can
3755 generally get better code when we load a sign extended value. */
3756 if ((hi32.X_add_number & 0x80000000) != 0)
3757 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3758 load_register (reg, &hi32, 0);
3761 if ((lo32.X_add_number & 0xffff0000) == 0)
3765 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3773 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3775 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3776 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3782 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3786 mid16.X_add_number >>= 16;
3787 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3788 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3791 if ((lo32.X_add_number & 0xffff) != 0)
3792 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3796 load_delay_nop (void)
3798 if (!gpr_interlocks)
3799 macro_build (NULL, "nop", "");
3802 /* Load an address into a register. */
3805 load_address (int reg, expressionS *ep, int *used_at)
3807 if (ep->X_op != O_constant
3808 && ep->X_op != O_symbol)
3810 as_bad (_("expression too complex"));
3811 ep->X_op = O_constant;
3814 if (ep->X_op == O_constant)
3816 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3820 if (mips_pic == NO_PIC)
3822 /* If this is a reference to a GP relative symbol, we want
3823 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3825 lui $reg,<sym> (BFD_RELOC_HI16_S)
3826 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3827 If we have an addend, we always use the latter form.
3829 With 64bit address space and a usable $at we want
3830 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3831 lui $at,<sym> (BFD_RELOC_HI16_S)
3832 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3833 daddiu $at,<sym> (BFD_RELOC_LO16)
3837 If $at is already in use, we use a path which is suboptimal
3838 on superscalar processors.
3839 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3840 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3842 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3844 daddiu $reg,<sym> (BFD_RELOC_LO16)
3846 if (HAVE_64BIT_ADDRESSES)
3848 /* ??? We don't provide a GP-relative alternative for these macros.
3849 It used not to be possible with the original relaxation code,
3850 but it could be done now. */
3852 if (*used_at == 0 && ! mips_opts.noat)
3854 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3855 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3856 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3857 BFD_RELOC_MIPS_HIGHER);
3858 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3859 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3860 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3865 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3866 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3867 BFD_RELOC_MIPS_HIGHER);
3868 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3869 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3870 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3871 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3876 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3877 && ! nopic_need_relax (ep->X_add_symbol, 1))
3879 relax_start (ep->X_add_symbol);
3880 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3881 mips_gp_register, BFD_RELOC_GPREL16);
3884 macro_build_lui (ep, reg);
3885 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3886 reg, reg, BFD_RELOC_LO16);
3887 if (mips_relax.sequence)
3891 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3895 /* If this is a reference to an external symbol, we want
3896 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3898 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3900 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3901 If there is a constant, it must be added in after.
3903 If we have NewABI, we want
3904 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3905 unless we're referencing a global symbol with a non-zero
3906 offset, in which case cst must be added separately. */
3909 if (ep->X_add_number)
3911 ex.X_add_number = ep->X_add_number;
3912 ep->X_add_number = 0;
3913 relax_start (ep->X_add_symbol);
3914 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3915 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3916 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3917 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3918 ex.X_op = O_constant;
3919 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3920 reg, reg, BFD_RELOC_LO16);
3921 ep->X_add_number = ex.X_add_number;
3924 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3925 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3926 if (mips_relax.sequence)
3931 ex.X_add_number = ep->X_add_number;
3932 ep->X_add_number = 0;
3933 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3934 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3936 relax_start (ep->X_add_symbol);
3938 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3942 if (ex.X_add_number != 0)
3944 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3945 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3946 ex.X_op = O_constant;
3947 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3948 reg, reg, BFD_RELOC_LO16);
3952 else if (mips_pic == SVR4_PIC)
3956 /* This is the large GOT case. If this is a reference to an
3957 external symbol, we want
3958 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3960 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3962 Otherwise, for a reference to a local symbol in old ABI, we want
3963 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3965 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3966 If there is a constant, it must be added in after.
3968 In the NewABI, for local symbols, with or without offsets, we want:
3969 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3970 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3974 ex.X_add_number = ep->X_add_number;
3975 ep->X_add_number = 0;
3976 relax_start (ep->X_add_symbol);
3977 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3979 reg, reg, mips_gp_register);
3980 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3981 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3982 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3983 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3984 else if (ex.X_add_number)
3986 ex.X_op = O_constant;
3987 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3991 ep->X_add_number = ex.X_add_number;
3993 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3994 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3995 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3996 BFD_RELOC_MIPS_GOT_OFST);
4001 ex.X_add_number = ep->X_add_number;
4002 ep->X_add_number = 0;
4003 relax_start (ep->X_add_symbol);
4004 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4006 reg, reg, mips_gp_register);
4007 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4008 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4010 if (reg_needs_delay (mips_gp_register))
4012 /* We need a nop before loading from $gp. This special
4013 check is required because the lui which starts the main
4014 instruction stream does not refer to $gp, and so will not
4015 insert the nop which may be required. */
4016 macro_build (NULL, "nop", "");
4018 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4019 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4021 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4025 if (ex.X_add_number != 0)
4027 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4028 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4029 ex.X_op = O_constant;
4030 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4039 /* Move the contents of register SOURCE into register DEST. */
4042 move_register (int dest, int source)
4044 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4048 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4049 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4050 The two alternatives are:
4052 Global symbol Local sybmol
4053 ------------- ------------
4054 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4056 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4058 load_got_offset emits the first instruction and add_got_offset
4059 emits the second for a 16-bit offset or add_got_offset_hilo emits
4060 a sequence to add a 32-bit offset using a scratch register. */
4063 load_got_offset (int dest, expressionS *local)
4068 global.X_add_number = 0;
4070 relax_start (local->X_add_symbol);
4071 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4072 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4074 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4075 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4080 add_got_offset (int dest, expressionS *local)
4084 global.X_op = O_constant;
4085 global.X_op_symbol = NULL;
4086 global.X_add_symbol = NULL;
4087 global.X_add_number = local->X_add_number;
4089 relax_start (local->X_add_symbol);
4090 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4091 dest, dest, BFD_RELOC_LO16);
4093 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4098 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4101 int hold_mips_optimize;
4103 global.X_op = O_constant;
4104 global.X_op_symbol = NULL;
4105 global.X_add_symbol = NULL;
4106 global.X_add_number = local->X_add_number;
4108 relax_start (local->X_add_symbol);
4109 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4111 /* Set mips_optimize around the lui instruction to avoid
4112 inserting an unnecessary nop after the lw. */
4113 hold_mips_optimize = mips_optimize;
4115 macro_build_lui (&global, tmp);
4116 mips_optimize = hold_mips_optimize;
4117 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4125 * This routine implements the seemingly endless macro or synthesized
4126 * instructions and addressing modes in the mips assembly language. Many
4127 * of these macros are simple and are similar to each other. These could
4128 * probably be handled by some kind of table or grammar approach instead of
4129 * this verbose method. Others are not simple macros but are more like
4130 * optimizing code generation.
4131 * One interesting optimization is when several store macros appear
4132 * consecutively that would load AT with the upper half of the same address.
4133 * The ensuing load upper instructions are ommited. This implies some kind
4134 * of global optimization. We currently only optimize within a single macro.
4135 * For many of the load and store macros if the address is specified as a
4136 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4137 * first load register 'at' with zero and use it as the base register. The
4138 * mips assembler simply uses register $zero. Just one tiny optimization
4142 macro (struct mips_cl_insn *ip)
4144 register int treg, sreg, dreg, breg;
4160 bfd_reloc_code_real_type r;
4161 int hold_mips_optimize;
4163 assert (! mips_opts.mips16);
4165 treg = (ip->insn_opcode >> 16) & 0x1f;
4166 dreg = (ip->insn_opcode >> 11) & 0x1f;
4167 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4168 mask = ip->insn_mo->mask;
4170 expr1.X_op = O_constant;
4171 expr1.X_op_symbol = NULL;
4172 expr1.X_add_symbol = NULL;
4173 expr1.X_add_number = 1;
4185 mips_emit_delays (TRUE);
4186 ++mips_opts.noreorder;
4187 mips_any_noreorder = 1;
4189 expr1.X_add_number = 8;
4190 macro_build (&expr1, "bgez", "s,p", sreg);
4192 macro_build (NULL, "nop", "", 0);
4194 move_register (dreg, sreg);
4195 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4197 --mips_opts.noreorder;
4218 if (imm_expr.X_op == O_constant
4219 && imm_expr.X_add_number >= -0x8000
4220 && imm_expr.X_add_number < 0x8000)
4222 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4225 load_register (AT, &imm_expr, dbl);
4226 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4245 if (imm_expr.X_op == O_constant
4246 && imm_expr.X_add_number >= 0
4247 && imm_expr.X_add_number < 0x10000)
4249 if (mask != M_NOR_I)
4250 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4253 macro_build (&imm_expr, "ori", "t,r,i",
4254 treg, sreg, BFD_RELOC_LO16);
4255 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4260 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4261 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4278 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4280 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4283 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4284 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4292 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4297 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4300 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4301 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4307 /* check for > max integer */
4308 maxnum = 0x7fffffff;
4309 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4316 if (imm_expr.X_op == O_constant
4317 && imm_expr.X_add_number >= maxnum
4318 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4321 /* result is always false */
4323 macro_build (NULL, "nop", "", 0);
4325 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4328 if (imm_expr.X_op != O_constant)
4329 as_bad (_("Unsupported large constant"));
4330 ++imm_expr.X_add_number;
4334 if (mask == M_BGEL_I)
4336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4338 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4341 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4343 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4346 maxnum = 0x7fffffff;
4347 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4354 maxnum = - maxnum - 1;
4355 if (imm_expr.X_op == O_constant
4356 && imm_expr.X_add_number <= maxnum
4357 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4360 /* result is always true */
4361 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4362 macro_build (&offset_expr, "b", "p");
4366 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4376 macro_build (&offset_expr, likely ? "beql" : "beq",
4380 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4381 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4389 && imm_expr.X_op == O_constant
4390 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4392 if (imm_expr.X_op != O_constant)
4393 as_bad (_("Unsupported large constant"));
4394 ++imm_expr.X_add_number;
4398 if (mask == M_BGEUL_I)
4400 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4402 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4404 macro_build (&offset_expr, likely ? "bnel" : "bne",
4409 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4417 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4422 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4425 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4426 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4434 macro_build (&offset_expr, likely ? "bnel" : "bne",
4440 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4441 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4449 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4454 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4457 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4458 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4464 maxnum = 0x7fffffff;
4465 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4472 if (imm_expr.X_op == O_constant
4473 && imm_expr.X_add_number >= maxnum
4474 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4476 if (imm_expr.X_op != O_constant)
4477 as_bad (_("Unsupported large constant"));
4478 ++imm_expr.X_add_number;
4482 if (mask == M_BLTL_I)
4484 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4486 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4489 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4491 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4495 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4503 macro_build (&offset_expr, likely ? "beql" : "beq",
4509 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4510 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4518 && imm_expr.X_op == O_constant
4519 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4521 if (imm_expr.X_op != O_constant)
4522 as_bad (_("Unsupported large constant"));
4523 ++imm_expr.X_add_number;
4527 if (mask == M_BLTUL_I)
4529 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4531 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4533 macro_build (&offset_expr, likely ? "beql" : "beq",
4538 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4546 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4551 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4554 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4555 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4565 macro_build (&offset_expr, likely ? "bnel" : "bne",
4569 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4570 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4578 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4580 as_bad (_("Unsupported large constant"));
4585 pos = (unsigned long) imm_expr.X_add_number;
4586 size = (unsigned long) imm2_expr.X_add_number;
4591 as_bad (_("Improper position (%lu)"), pos);
4594 if (size == 0 || size > 64
4595 || (pos + size - 1) > 63)
4597 as_bad (_("Improper extract size (%lu, position %lu)"),
4602 if (size <= 32 && pos < 32)
4607 else if (size <= 32)
4617 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4626 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4628 as_bad (_("Unsupported large constant"));
4633 pos = (unsigned long) imm_expr.X_add_number;
4634 size = (unsigned long) imm2_expr.X_add_number;
4639 as_bad (_("Improper position (%lu)"), pos);
4642 if (size == 0 || size > 64
4643 || (pos + size - 1) > 63)
4645 as_bad (_("Improper insert size (%lu, position %lu)"),
4650 if (pos < 32 && (pos + size - 1) < 32)
4665 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4682 as_warn (_("Divide by zero."));
4684 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4686 macro_build (NULL, "break", "c", 7);
4690 mips_emit_delays (TRUE);
4691 ++mips_opts.noreorder;
4692 mips_any_noreorder = 1;
4695 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4696 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4700 expr1.X_add_number = 8;
4701 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4702 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4703 macro_build (NULL, "break", "c", 7);
4705 expr1.X_add_number = -1;
4706 load_register (AT, &expr1, dbl);
4707 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4708 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4711 expr1.X_add_number = 1;
4712 load_register (AT, &expr1, dbl);
4713 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4717 expr1.X_add_number = 0x80000000;
4718 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4722 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4723 /* We want to close the noreorder block as soon as possible, so
4724 that later insns are available for delay slot filling. */
4725 --mips_opts.noreorder;
4729 expr1.X_add_number = 8;
4730 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4731 macro_build (NULL, "nop", "", 0);
4733 /* We want to close the noreorder block as soon as possible, so
4734 that later insns are available for delay slot filling. */
4735 --mips_opts.noreorder;
4737 macro_build (NULL, "break", "c", 6);
4739 macro_build (NULL, s, "d", dreg);
4778 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4780 as_warn (_("Divide by zero."));
4782 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4784 macro_build (NULL, "break", "c", 7);
4787 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4789 if (strcmp (s2, "mflo") == 0)
4790 move_register (dreg, sreg);
4792 move_register (dreg, 0);
4795 if (imm_expr.X_op == O_constant
4796 && imm_expr.X_add_number == -1
4797 && s[strlen (s) - 1] != 'u')
4799 if (strcmp (s2, "mflo") == 0)
4801 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4804 move_register (dreg, 0);
4808 load_register (AT, &imm_expr, dbl);
4809 macro_build (NULL, s, "z,s,t", sreg, AT);
4810 macro_build (NULL, s2, "d", dreg);
4829 mips_emit_delays (TRUE);
4830 ++mips_opts.noreorder;
4831 mips_any_noreorder = 1;
4834 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4835 macro_build (NULL, s, "z,s,t", sreg, treg);
4836 /* We want to close the noreorder block as soon as possible, so
4837 that later insns are available for delay slot filling. */
4838 --mips_opts.noreorder;
4842 expr1.X_add_number = 8;
4843 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4844 macro_build (NULL, s, "z,s,t", sreg, treg);
4846 /* We want to close the noreorder block as soon as possible, so
4847 that later insns are available for delay slot filling. */
4848 --mips_opts.noreorder;
4849 macro_build (NULL, "break", "c", 7);
4851 macro_build (NULL, s2, "d", dreg);
4863 /* Load the address of a symbol into a register. If breg is not
4864 zero, we then add a base register to it. */
4866 if (dbl && HAVE_32BIT_GPRS)
4867 as_warn (_("dla used to load 32-bit register"));
4869 if (! dbl && HAVE_64BIT_OBJECTS)
4870 as_warn (_("la used to load 64-bit address"));
4872 if (offset_expr.X_op == O_constant
4873 && offset_expr.X_add_number >= -0x8000
4874 && offset_expr.X_add_number < 0x8000)
4876 macro_build (&offset_expr,
4877 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4878 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4893 if (offset_expr.X_op != O_symbol
4894 && offset_expr.X_op != O_constant)
4896 as_bad (_("expression too complex"));
4897 offset_expr.X_op = O_constant;
4900 if (offset_expr.X_op == O_constant)
4901 load_register (tempreg, &offset_expr,
4903 ? (dbl || HAVE_64BIT_ADDRESSES)
4904 : HAVE_64BIT_ADDRESSES));
4905 else if (mips_pic == NO_PIC)
4907 /* If this is a reference to a GP relative symbol, we want
4908 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4910 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4911 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4912 If we have a constant, we need two instructions anyhow,
4913 so we may as well always use the latter form.
4915 With 64bit address space and a usable $at we want
4916 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4917 lui $at,<sym> (BFD_RELOC_HI16_S)
4918 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4919 daddiu $at,<sym> (BFD_RELOC_LO16)
4921 daddu $tempreg,$tempreg,$at
4923 If $at is already in use, we use a path which is suboptimal
4924 on superscalar processors.
4925 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4926 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4928 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4930 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4932 if (HAVE_64BIT_ADDRESSES)
4934 /* ??? We don't provide a GP-relative alternative for
4935 these macros. It used not to be possible with the
4936 original relaxation code, but it could be done now. */
4938 if (used_at == 0 && ! mips_opts.noat)
4940 macro_build (&offset_expr, "lui", "t,u",
4941 tempreg, BFD_RELOC_MIPS_HIGHEST);
4942 macro_build (&offset_expr, "lui", "t,u",
4943 AT, BFD_RELOC_HI16_S);
4944 macro_build (&offset_expr, "daddiu", "t,r,j",
4945 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4946 macro_build (&offset_expr, "daddiu", "t,r,j",
4947 AT, AT, BFD_RELOC_LO16);
4948 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4949 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4954 macro_build (&offset_expr, "lui", "t,u",
4955 tempreg, BFD_RELOC_MIPS_HIGHEST);
4956 macro_build (&offset_expr, "daddiu", "t,r,j",
4957 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4958 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4959 macro_build (&offset_expr, "daddiu", "t,r,j",
4960 tempreg, tempreg, BFD_RELOC_HI16_S);
4961 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4962 macro_build (&offset_expr, "daddiu", "t,r,j",
4963 tempreg, tempreg, BFD_RELOC_LO16);
4968 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4969 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4971 relax_start (offset_expr.X_add_symbol);
4972 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4973 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4976 macro_build_lui (&offset_expr, tempreg);
4977 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4978 tempreg, tempreg, BFD_RELOC_LO16);
4979 if (mips_relax.sequence)
4983 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4985 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4987 /* If this is a reference to an external symbol, and there
4988 is no constant, we want
4989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4990 or for lca or if tempreg is PIC_CALL_REG
4991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4992 For a local symbol, we want
4993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4995 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4997 If we have a small constant, and this is a reference to
4998 an external symbol, we want
4999 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5001 addiu $tempreg,$tempreg,<constant>
5002 For a local symbol, we want the same instruction
5003 sequence, but we output a BFD_RELOC_LO16 reloc on the
5006 If we have a large constant, and this is a reference to
5007 an external symbol, we want
5008 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5009 lui $at,<hiconstant>
5010 addiu $at,$at,<loconstant>
5011 addu $tempreg,$tempreg,$at
5012 For a local symbol, we want the same instruction
5013 sequence, but we output a BFD_RELOC_LO16 reloc on the
5017 if (offset_expr.X_add_number == 0)
5019 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5020 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5022 relax_start (offset_expr.X_add_symbol);
5023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5024 lw_reloc_type, mips_gp_register);
5027 /* We're going to put in an addu instruction using
5028 tempreg, so we may as well insert the nop right
5033 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5034 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5036 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5037 tempreg, tempreg, BFD_RELOC_LO16);
5039 /* FIXME: If breg == 0, and the next instruction uses
5040 $tempreg, then if this variant case is used an extra
5041 nop will be generated. */
5043 else if (offset_expr.X_add_number >= -0x8000
5044 && offset_expr.X_add_number < 0x8000)
5046 load_got_offset (tempreg, &offset_expr);
5048 add_got_offset (tempreg, &offset_expr);
5052 expr1.X_add_number = offset_expr.X_add_number;
5053 offset_expr.X_add_number =
5054 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5055 load_got_offset (tempreg, &offset_expr);
5056 offset_expr.X_add_number = expr1.X_add_number;
5057 /* If we are going to add in a base register, and the
5058 target register and the base register are the same,
5059 then we are using AT as a temporary register. Since
5060 we want to load the constant into AT, we add our
5061 current AT (from the global offset table) and the
5062 register into the register now, and pretend we were
5063 not using a base register. */
5067 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5072 add_got_offset_hilo (tempreg, &offset_expr, AT);
5076 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5078 int add_breg_early = 0;
5080 /* If this is a reference to an external, and there is no
5081 constant, or local symbol (*), with or without a
5083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5084 or for lca or if tempreg is PIC_CALL_REG
5085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5087 If we have a small constant, and this is a reference to
5088 an external symbol, we want
5089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5090 addiu $tempreg,$tempreg,<constant>
5092 If we have a large constant, and this is a reference to
5093 an external symbol, we want
5094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5095 lui $at,<hiconstant>
5096 addiu $at,$at,<loconstant>
5097 addu $tempreg,$tempreg,$at
5099 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5100 local symbols, even though it introduces an additional
5103 if (offset_expr.X_add_number)
5105 expr1.X_add_number = offset_expr.X_add_number;
5106 offset_expr.X_add_number = 0;
5108 relax_start (offset_expr.X_add_symbol);
5109 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5110 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5112 if (expr1.X_add_number >= -0x8000
5113 && expr1.X_add_number < 0x8000)
5115 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5116 tempreg, tempreg, BFD_RELOC_LO16);
5118 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5122 /* If we are going to add in a base register, and the
5123 target register and the base register are the same,
5124 then we are using AT as a temporary register. Since
5125 we want to load the constant into AT, we add our
5126 current AT (from the global offset table) and the
5127 register into the register now, and pretend we were
5128 not using a base register. */
5133 assert (tempreg == AT);
5134 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5140 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5141 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5147 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5150 offset_expr.X_add_number = expr1.X_add_number;
5152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5153 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5157 treg, tempreg, breg);
5163 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5165 relax_start (offset_expr.X_add_symbol);
5166 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5167 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5169 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5170 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5175 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5176 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5179 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5182 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5183 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5184 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5186 /* This is the large GOT case. If this is a reference to an
5187 external symbol, and there is no constant, we want
5188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5189 addu $tempreg,$tempreg,$gp
5190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5191 or for lca or if tempreg is PIC_CALL_REG
5192 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5193 addu $tempreg,$tempreg,$gp
5194 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5195 For a local symbol, we want
5196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5198 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5200 If we have a small constant, and this is a reference to
5201 an external symbol, we want
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5206 addiu $tempreg,$tempreg,<constant>
5207 For a local symbol, we want
5208 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5210 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5212 If we have a large constant, and this is a reference to
5213 an external symbol, we want
5214 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5215 addu $tempreg,$tempreg,$gp
5216 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5217 lui $at,<hiconstant>
5218 addiu $at,$at,<loconstant>
5219 addu $tempreg,$tempreg,$at
5220 For a local symbol, we want
5221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5222 lui $at,<hiconstant>
5223 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5224 addu $tempreg,$tempreg,$at
5227 expr1.X_add_number = offset_expr.X_add_number;
5228 offset_expr.X_add_number = 0;
5229 relax_start (offset_expr.X_add_symbol);
5230 gpdelay = reg_needs_delay (mips_gp_register);
5231 if (expr1.X_add_number == 0 && breg == 0
5232 && (call || tempreg == PIC_CALL_REG))
5234 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5235 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5237 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5238 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5239 tempreg, tempreg, mips_gp_register);
5240 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5241 tempreg, lw_reloc_type, tempreg);
5242 if (expr1.X_add_number == 0)
5246 /* We're going to put in an addu instruction using
5247 tempreg, so we may as well insert the nop right
5252 else if (expr1.X_add_number >= -0x8000
5253 && expr1.X_add_number < 0x8000)
5256 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5257 tempreg, tempreg, BFD_RELOC_LO16);
5263 /* If we are going to add in a base register, and the
5264 target register and the base register are the same,
5265 then we are using AT as a temporary register. Since
5266 we want to load the constant into AT, we add our
5267 current AT (from the global offset table) and the
5268 register into the register now, and pretend we were
5269 not using a base register. */
5274 assert (tempreg == AT);
5276 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5281 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5282 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5286 offset_expr.X_add_number =
5287 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5292 /* This is needed because this instruction uses $gp, but
5293 the first instruction on the main stream does not. */
5294 macro_build (NULL, "nop", "");
5297 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5298 local_reloc_type, mips_gp_register);
5299 if (expr1.X_add_number >= -0x8000
5300 && expr1.X_add_number < 0x8000)
5303 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5304 tempreg, tempreg, BFD_RELOC_LO16);
5305 /* FIXME: If add_number is 0, and there was no base
5306 register, the external symbol case ended with a load,
5307 so if the symbol turns out to not be external, and
5308 the next instruction uses tempreg, an unnecessary nop
5309 will be inserted. */
5315 /* We must add in the base register now, as in the
5316 external symbol case. */
5317 assert (tempreg == AT);
5319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5322 /* We set breg to 0 because we have arranged to add
5323 it in in both cases. */
5327 macro_build_lui (&expr1, AT);
5328 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5329 AT, AT, BFD_RELOC_LO16);
5330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5331 tempreg, tempreg, AT);
5335 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5337 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5338 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5339 int add_breg_early = 0;
5341 /* This is the large GOT case. If this is a reference to an
5342 external symbol, and there is no constant, we want
5343 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5344 add $tempreg,$tempreg,$gp
5345 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5346 or for lca or if tempreg is PIC_CALL_REG
5347 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5348 add $tempreg,$tempreg,$gp
5349 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5351 If we have a small constant, and this is a reference to
5352 an external symbol, we want
5353 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5354 add $tempreg,$tempreg,$gp
5355 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5356 addi $tempreg,$tempreg,<constant>
5358 If we have a large constant, and this is a reference to
5359 an external symbol, we want
5360 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5361 addu $tempreg,$tempreg,$gp
5362 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5363 lui $at,<hiconstant>
5364 addi $at,$at,<loconstant>
5365 add $tempreg,$tempreg,$at
5367 If we have NewABI, and we know it's a local symbol, we want
5368 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5369 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5370 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5372 relax_start (offset_expr.X_add_symbol);
5374 expr1.X_add_number = offset_expr.X_add_number;
5375 offset_expr.X_add_number = 0;
5377 if (expr1.X_add_number == 0 && breg == 0
5378 && (call || tempreg == PIC_CALL_REG))
5380 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5381 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5383 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5384 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5385 tempreg, tempreg, mips_gp_register);
5386 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5387 tempreg, lw_reloc_type, tempreg);
5389 if (expr1.X_add_number == 0)
5391 else if (expr1.X_add_number >= -0x8000
5392 && expr1.X_add_number < 0x8000)
5394 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5395 tempreg, tempreg, BFD_RELOC_LO16);
5397 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5401 /* If we are going to add in a base register, and the
5402 target register and the base register are the same,
5403 then we are using AT as a temporary register. Since
5404 we want to load the constant into AT, we add our
5405 current AT (from the global offset table) and the
5406 register into the register now, and pretend we were
5407 not using a base register. */
5412 assert (tempreg == AT);
5413 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5419 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5420 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5425 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5428 offset_expr.X_add_number = expr1.X_add_number;
5429 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5430 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5431 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5432 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5436 treg, tempreg, breg);
5449 if (mips_pic == NO_PIC)
5450 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5452 s = ADDRESS_ADD_INSN;
5454 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5463 /* The j instruction may not be used in PIC code, since it
5464 requires an absolute address. We convert it to a b
5466 if (mips_pic == NO_PIC)
5467 macro_build (&offset_expr, "j", "a");
5469 macro_build (&offset_expr, "b", "p");
5472 /* The jal instructions must be handled as macros because when
5473 generating PIC code they expand to multi-instruction
5474 sequences. Normally they are simple instructions. */
5479 if (mips_pic == NO_PIC)
5480 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5481 else if (mips_pic == SVR4_PIC)
5483 if (sreg != PIC_CALL_REG)
5484 as_warn (_("MIPS PIC call to register other than $25"));
5486 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5489 if (mips_cprestore_offset < 0)
5490 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5493 if (! mips_frame_reg_valid)
5495 as_warn (_("No .frame pseudo-op used in PIC code"));
5496 /* Quiet this warning. */
5497 mips_frame_reg_valid = 1;
5499 if (! mips_cprestore_valid)
5501 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5502 /* Quiet this warning. */
5503 mips_cprestore_valid = 1;
5505 expr1.X_add_number = mips_cprestore_offset;
5506 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5509 HAVE_64BIT_ADDRESSES);
5519 if (mips_pic == NO_PIC)
5520 macro_build (&offset_expr, "jal", "a");
5521 else if (mips_pic == SVR4_PIC)
5523 /* If this is a reference to an external symbol, and we are
5524 using a small GOT, we want
5525 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5529 lw $gp,cprestore($sp)
5530 The cprestore value is set using the .cprestore
5531 pseudo-op. If we are using a big GOT, we want
5532 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5534 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5538 lw $gp,cprestore($sp)
5539 If the symbol is not external, we want
5540 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5542 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5545 lw $gp,cprestore($sp)
5547 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5548 sequences above, minus nops, unless the symbol is local,
5549 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5555 relax_start (offset_expr.X_add_symbol);
5556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5557 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5560 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5561 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5567 relax_start (offset_expr.X_add_symbol);
5568 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5569 BFD_RELOC_MIPS_CALL_HI16);
5570 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5571 PIC_CALL_REG, mips_gp_register);
5572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5573 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5576 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5577 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5579 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5580 PIC_CALL_REG, PIC_CALL_REG,
5581 BFD_RELOC_MIPS_GOT_OFST);
5585 macro_build_jalr (&offset_expr);
5589 relax_start (offset_expr.X_add_symbol);
5592 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5593 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5602 gpdelay = reg_needs_delay (mips_gp_register);
5603 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5604 BFD_RELOC_MIPS_CALL_HI16);
5605 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5606 PIC_CALL_REG, mips_gp_register);
5607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5608 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5613 macro_build (NULL, "nop", "");
5615 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5616 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5619 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5620 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5622 macro_build_jalr (&offset_expr);
5624 if (mips_cprestore_offset < 0)
5625 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5628 if (! mips_frame_reg_valid)
5630 as_warn (_("No .frame pseudo-op used in PIC code"));
5631 /* Quiet this warning. */
5632 mips_frame_reg_valid = 1;
5634 if (! mips_cprestore_valid)
5636 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5637 /* Quiet this warning. */
5638 mips_cprestore_valid = 1;
5640 if (mips_opts.noreorder)
5641 macro_build (NULL, "nop", "");
5642 expr1.X_add_number = mips_cprestore_offset;
5643 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5646 HAVE_64BIT_ADDRESSES);
5672 /* Itbl support may require additional care here. */
5677 /* Itbl support may require additional care here. */
5682 /* Itbl support may require additional care here. */
5687 /* Itbl support may require additional care here. */
5699 if (mips_opts.arch == CPU_R4650)
5701 as_bad (_("opcode not supported on this processor"));
5705 /* Itbl support may require additional care here. */
5710 /* Itbl support may require additional care here. */
5715 /* Itbl support may require additional care here. */
5735 if (breg == treg || coproc || lr)
5757 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5772 /* Itbl support may require additional care here. */
5788 if (mips_opts.arch == CPU_R4650)
5790 as_bad (_("opcode not supported on this processor"));
5795 /* Itbl support may require additional care here. */
5799 /* Itbl support may require additional care here. */
5804 /* Itbl support may require additional care here. */
5816 /* Itbl support may require additional care here. */
5817 if (mask == M_LWC1_AB
5818 || mask == M_SWC1_AB
5819 || mask == M_LDC1_AB
5820 || mask == M_SDC1_AB
5829 /* Sign-extending 32-bit constants makes their handling easier.
5830 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5832 if ((! HAVE_64BIT_ADDRESSES
5833 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5834 && (offset_expr.X_op == O_constant)
5835 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5836 == ~((bfd_vma) 0x7fffffff)))
5838 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5839 as_bad (_("constant too large"));
5841 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5842 ^ 0x80000000) - 0x80000000);
5845 if (offset_expr.X_op != O_constant
5846 && offset_expr.X_op != O_symbol)
5848 as_bad (_("expression too complex"));
5849 offset_expr.X_op = O_constant;
5852 /* A constant expression in PIC code can be handled just as it
5853 is in non PIC code. */
5854 if (mips_pic == NO_PIC
5855 || offset_expr.X_op == O_constant)
5857 /* If this is a reference to a GP relative symbol, and there
5858 is no base register, we want
5859 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5860 Otherwise, if there is no base register, we want
5861 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5862 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5863 If we have a constant, we need two instructions anyhow,
5864 so we always use the latter form.
5866 If we have a base register, and this is a reference to a
5867 GP relative symbol, we want
5868 addu $tempreg,$breg,$gp
5869 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5871 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5872 addu $tempreg,$tempreg,$breg
5873 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5874 With a constant we always use the latter case.
5876 With 64bit address space and no base register and $at usable,
5878 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5879 lui $at,<sym> (BFD_RELOC_HI16_S)
5880 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5884 If we have a base register, we want
5885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5886 lui $at,<sym> (BFD_RELOC_HI16_S)
5887 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5891 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5893 Without $at we can't generate the optimal path for superscalar
5894 processors here since this would require two temporary registers.
5895 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5896 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5898 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5900 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5901 If we have a base register, we want
5902 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5903 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5905 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5907 daddu $tempreg,$tempreg,$breg
5908 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5910 If we have 64-bit addresses, as an optimization, for
5911 addresses which are 32-bit constants (e.g. kseg0/kseg1
5912 addresses) we fall back to the 32-bit address generation
5913 mechanism since it is more efficient. Note that due to
5914 the signed offset used by memory operations, the 32-bit
5915 range is shifted down by 32768 here. This code should
5916 probably attempt to generate 64-bit constants more
5917 efficiently in general.
5919 As an extension for architectures with 64-bit registers,
5920 we don't truncate 64-bit addresses given as literal
5921 constants down to 32 bits, to support existing practice
5922 in the mips64 Linux (the kernel), that compiles source
5923 files with -mabi=64, assembling them as o32 or n32 (with
5924 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5925 the whole kernel is loaded into a memory region that is
5926 addressable with sign-extended 32-bit addresses, it is
5927 wasteful to compute the upper 32 bits of every
5928 non-literal address, that takes more space and time.
5929 Some day this should probably be implemented as an
5930 assembler option, such that the kernel doesn't have to
5931 use such ugly hacks, even though it will still have to
5932 end up converting the binary to ELF32 for a number of
5933 platforms whose boot loaders don't support ELF64
5935 if ((HAVE_64BIT_ADDRESSES
5936 && ! (offset_expr.X_op == O_constant
5937 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5939 && offset_expr.X_op == O_constant
5940 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5942 /* ??? We don't provide a GP-relative alternative for
5943 these macros. It used not to be possible with the
5944 original relaxation code, but it could be done now. */
5946 if (used_at == 0 && ! mips_opts.noat)
5948 macro_build (&offset_expr, "lui", "t,u", tempreg,
5949 BFD_RELOC_MIPS_HIGHEST);
5950 macro_build (&offset_expr, "lui", "t,u", AT,
5952 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5953 tempreg, BFD_RELOC_MIPS_HIGHER);
5955 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
5956 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5957 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5958 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
5964 macro_build (&offset_expr, "lui", "t,u", tempreg,
5965 BFD_RELOC_MIPS_HIGHEST);
5966 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5967 tempreg, BFD_RELOC_MIPS_HIGHER);
5968 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5969 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5970 tempreg, BFD_RELOC_HI16_S);
5971 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5973 macro_build (NULL, "daddu", "d,v,t",
5974 tempreg, tempreg, breg);
5975 macro_build (&offset_expr, s, fmt, treg,
5976 BFD_RELOC_LO16, tempreg);
5982 if (offset_expr.X_op == O_constant
5983 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
5984 as_bad (_("load/store address overflow (max 32 bits)"));
5988 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5989 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5991 relax_start (offset_expr.X_add_symbol);
5992 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
5997 macro_build_lui (&offset_expr, tempreg);
5998 macro_build (&offset_expr, s, fmt, treg,
5999 BFD_RELOC_LO16, tempreg);
6000 if (mips_relax.sequence)
6005 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6006 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6008 relax_start (offset_expr.X_add_symbol);
6009 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6010 tempreg, breg, mips_gp_register);
6011 macro_build (&offset_expr, s, fmt, treg,
6012 BFD_RELOC_GPREL16, tempreg);
6015 macro_build_lui (&offset_expr, tempreg);
6016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6017 tempreg, tempreg, breg);
6018 macro_build (&offset_expr, s, fmt, treg,
6019 BFD_RELOC_LO16, tempreg);
6020 if (mips_relax.sequence)
6024 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6026 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6028 /* If this is a reference to an external symbol, we want
6029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6031 <op> $treg,0($tempreg)
6033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6035 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6036 <op> $treg,0($tempreg)
6039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6040 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6042 If there is a base register, we add it to $tempreg before
6043 the <op>. If there is a constant, we stick it in the
6044 <op> instruction. We don't handle constants larger than
6045 16 bits, because we have no way to load the upper 16 bits
6046 (actually, we could handle them for the subset of cases
6047 in which we are not using $at). */
6048 assert (offset_expr.X_op == O_symbol);
6051 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6052 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6055 tempreg, tempreg, breg);
6056 macro_build (&offset_expr, s, fmt, treg,
6057 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6064 expr1.X_add_number = offset_expr.X_add_number;
6065 offset_expr.X_add_number = 0;
6066 if (expr1.X_add_number < -0x8000
6067 || expr1.X_add_number >= 0x8000)
6068 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6069 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6070 lw_reloc_type, mips_gp_register);
6072 relax_start (offset_expr.X_add_symbol);
6074 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6075 tempreg, BFD_RELOC_LO16);
6078 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6079 tempreg, tempreg, breg);
6080 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6082 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6086 /* If this is a reference to an external symbol, we want
6087 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6088 addu $tempreg,$tempreg,$gp
6089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6090 <op> $treg,0($tempreg)
6092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6094 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6095 <op> $treg,0($tempreg)
6096 If there is a base register, we add it to $tempreg before
6097 the <op>. If there is a constant, we stick it in the
6098 <op> instruction. We don't handle constants larger than
6099 16 bits, because we have no way to load the upper 16 bits
6100 (actually, we could handle them for the subset of cases
6101 in which we are not using $at). */
6102 assert (offset_expr.X_op == O_symbol);
6103 expr1.X_add_number = offset_expr.X_add_number;
6104 offset_expr.X_add_number = 0;
6105 if (expr1.X_add_number < -0x8000
6106 || expr1.X_add_number >= 0x8000)
6107 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6108 gpdelay = reg_needs_delay (mips_gp_register);
6109 relax_start (offset_expr.X_add_symbol);
6110 macro_build (&offset_expr, "lui", "t,u", tempreg,
6111 BFD_RELOC_MIPS_GOT_HI16);
6112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6114 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6115 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6118 macro_build (NULL, "nop", "");
6119 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6120 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6122 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6123 tempreg, BFD_RELOC_LO16);
6127 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6128 tempreg, tempreg, breg);
6129 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6131 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6133 /* If this is a reference to an external symbol, we want
6134 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6135 add $tempreg,$tempreg,$gp
6136 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6137 <op> $treg,<ofst>($tempreg)
6138 Otherwise, for local symbols, we want:
6139 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6140 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6141 assert (offset_expr.X_op == O_symbol);
6142 expr1.X_add_number = offset_expr.X_add_number;
6143 offset_expr.X_add_number = 0;
6144 if (expr1.X_add_number < -0x8000
6145 || expr1.X_add_number >= 0x8000)
6146 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6147 relax_start (offset_expr.X_add_symbol);
6148 macro_build (&offset_expr, "lui", "t,u", tempreg,
6149 BFD_RELOC_MIPS_GOT_HI16);
6150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6153 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6156 tempreg, tempreg, breg);
6157 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6160 offset_expr.X_add_number = expr1.X_add_number;
6161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6162 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6164 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6165 tempreg, tempreg, breg);
6166 macro_build (&offset_expr, s, fmt, treg,
6167 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6180 load_register (treg, &imm_expr, 0);
6184 load_register (treg, &imm_expr, 1);
6188 if (imm_expr.X_op == O_constant)
6190 load_register (AT, &imm_expr, 0);
6191 macro_build (NULL, "mtc1", "t,G", AT, treg);
6196 assert (offset_expr.X_op == O_symbol
6197 && strcmp (segment_name (S_GET_SEGMENT
6198 (offset_expr.X_add_symbol)),
6200 && offset_expr.X_add_number == 0);
6201 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6202 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6207 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6208 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6209 order 32 bits of the value and the low order 32 bits are either
6210 zero or in OFFSET_EXPR. */
6211 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6213 if (HAVE_64BIT_GPRS)
6214 load_register (treg, &imm_expr, 1);
6219 if (target_big_endian)
6231 load_register (hreg, &imm_expr, 0);
6234 if (offset_expr.X_op == O_absent)
6235 move_register (lreg, 0);
6238 assert (offset_expr.X_op == O_constant);
6239 load_register (lreg, &offset_expr, 0);
6246 /* We know that sym is in the .rdata section. First we get the
6247 upper 16 bits of the address. */
6248 if (mips_pic == NO_PIC)
6250 macro_build_lui (&offset_expr, AT);
6252 else if (mips_pic == SVR4_PIC)
6254 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6255 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6260 /* Now we load the register(s). */
6261 if (HAVE_64BIT_GPRS)
6262 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6265 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6268 /* FIXME: How in the world do we deal with the possible
6270 offset_expr.X_add_number += 4;
6271 macro_build (&offset_expr, "lw", "t,o(b)",
6272 treg + 1, BFD_RELOC_LO16, AT);
6278 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6279 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6280 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6281 the value and the low order 32 bits are either zero or in
6283 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6285 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6286 if (HAVE_64BIT_FPRS)
6288 assert (HAVE_64BIT_GPRS);
6289 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6293 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6294 if (offset_expr.X_op == O_absent)
6295 macro_build (NULL, "mtc1", "t,G", 0, treg);
6298 assert (offset_expr.X_op == O_constant);
6299 load_register (AT, &offset_expr, 0);
6300 macro_build (NULL, "mtc1", "t,G", AT, treg);
6306 assert (offset_expr.X_op == O_symbol
6307 && offset_expr.X_add_number == 0);
6308 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6309 if (strcmp (s, ".lit8") == 0)
6311 if (mips_opts.isa != ISA_MIPS1)
6313 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6314 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6317 breg = mips_gp_register;
6318 r = BFD_RELOC_MIPS_LITERAL;
6323 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6324 if (mips_pic == SVR4_PIC)
6325 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6326 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6329 /* FIXME: This won't work for a 64 bit address. */
6330 macro_build_lui (&offset_expr, AT);
6333 if (mips_opts.isa != ISA_MIPS1)
6335 macro_build (&offset_expr, "ldc1", "T,o(b)",
6336 treg, BFD_RELOC_LO16, AT);
6345 if (mips_opts.arch == CPU_R4650)
6347 as_bad (_("opcode not supported on this processor"));
6350 /* Even on a big endian machine $fn comes before $fn+1. We have
6351 to adjust when loading from memory. */
6354 assert (mips_opts.isa == ISA_MIPS1);
6355 macro_build (&offset_expr, "lwc1", "T,o(b)",
6356 target_big_endian ? treg + 1 : treg, r, breg);
6357 /* FIXME: A possible overflow which I don't know how to deal
6359 offset_expr.X_add_number += 4;
6360 macro_build (&offset_expr, "lwc1", "T,o(b)",
6361 target_big_endian ? treg : treg + 1, r, breg);
6369 * The MIPS assembler seems to check for X_add_number not
6370 * being double aligned and generating:
6373 * addiu at,at,%lo(foo+1)
6376 * But, the resulting address is the same after relocation so why
6377 * generate the extra instruction?
6379 if (mips_opts.arch == CPU_R4650)
6381 as_bad (_("opcode not supported on this processor"));
6384 /* Itbl support may require additional care here. */
6386 if (mips_opts.isa != ISA_MIPS1)
6397 if (mips_opts.arch == CPU_R4650)
6399 as_bad (_("opcode not supported on this processor"));
6403 if (mips_opts.isa != ISA_MIPS1)
6411 /* Itbl support may require additional care here. */
6416 if (HAVE_64BIT_GPRS)
6427 if (HAVE_64BIT_GPRS)
6437 if (offset_expr.X_op != O_symbol
6438 && offset_expr.X_op != O_constant)
6440 as_bad (_("expression too complex"));
6441 offset_expr.X_op = O_constant;
6444 /* Even on a big endian machine $fn comes before $fn+1. We have
6445 to adjust when loading from memory. We set coproc if we must
6446 load $fn+1 first. */
6447 /* Itbl support may require additional care here. */
6448 if (! target_big_endian)
6451 if (mips_pic == NO_PIC
6452 || offset_expr.X_op == O_constant)
6454 /* If this is a reference to a GP relative symbol, we want
6455 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6456 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6457 If we have a base register, we use this
6459 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6460 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6461 If this is not a GP relative symbol, we want
6462 lui $at,<sym> (BFD_RELOC_HI16_S)
6463 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6464 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6465 If there is a base register, we add it to $at after the
6466 lui instruction. If there is a constant, we always use
6468 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6469 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6473 relax_start (offset_expr.X_add_symbol);
6476 tempreg = mips_gp_register;
6481 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6482 AT, breg, mips_gp_register);
6487 /* Itbl support may require additional care here. */
6488 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6489 BFD_RELOC_GPREL16, tempreg);
6490 offset_expr.X_add_number += 4;
6492 /* Set mips_optimize to 2 to avoid inserting an
6494 hold_mips_optimize = mips_optimize;
6496 /* Itbl support may require additional care here. */
6497 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6498 BFD_RELOC_GPREL16, tempreg);
6499 mips_optimize = hold_mips_optimize;
6503 /* We just generated two relocs. When tc_gen_reloc
6504 handles this case, it will skip the first reloc and
6505 handle the second. The second reloc already has an
6506 extra addend of 4, which we added above. We must
6507 subtract it out, and then subtract another 4 to make
6508 the first reloc come out right. The second reloc
6509 will come out right because we are going to add 4 to
6510 offset_expr when we build its instruction below.
6512 If we have a symbol, then we don't want to include
6513 the offset, because it will wind up being included
6514 when we generate the reloc. */
6516 if (offset_expr.X_op == O_constant)
6517 offset_expr.X_add_number -= 8;
6520 offset_expr.X_add_number = -4;
6521 offset_expr.X_op = O_constant;
6524 macro_build_lui (&offset_expr, AT);
6526 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6527 /* Itbl support may require additional care here. */
6528 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6529 BFD_RELOC_LO16, AT);
6530 /* FIXME: How do we handle overflow here? */
6531 offset_expr.X_add_number += 4;
6532 /* Itbl support may require additional care here. */
6533 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6534 BFD_RELOC_LO16, AT);
6535 if (mips_relax.sequence)
6538 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6540 /* If this is a reference to an external symbol, we want
6541 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6546 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6548 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6549 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6550 If there is a base register we add it to $at before the
6551 lwc1 instructions. If there is a constant we include it
6552 in the lwc1 instructions. */
6554 expr1.X_add_number = offset_expr.X_add_number;
6555 if (expr1.X_add_number < -0x8000
6556 || expr1.X_add_number >= 0x8000 - 4)
6557 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6558 load_got_offset (AT, &offset_expr);
6561 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6563 /* Set mips_optimize to 2 to avoid inserting an undesired
6565 hold_mips_optimize = mips_optimize;
6568 /* Itbl support may require additional care here. */
6569 relax_start (offset_expr.X_add_symbol);
6570 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6571 BFD_RELOC_LO16, AT);
6572 expr1.X_add_number += 4;
6573 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6574 BFD_RELOC_LO16, AT);
6576 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6577 BFD_RELOC_LO16, AT);
6578 offset_expr.X_add_number += 4;
6579 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6580 BFD_RELOC_LO16, AT);
6583 mips_optimize = hold_mips_optimize;
6585 else if (mips_pic == SVR4_PIC)
6589 /* If this is a reference to an external symbol, we want
6590 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6592 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6597 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6599 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6600 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6601 If there is a base register we add it to $at before the
6602 lwc1 instructions. If there is a constant we include it
6603 in the lwc1 instructions. */
6605 expr1.X_add_number = offset_expr.X_add_number;
6606 offset_expr.X_add_number = 0;
6607 if (expr1.X_add_number < -0x8000
6608 || expr1.X_add_number >= 0x8000 - 4)
6609 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6610 gpdelay = reg_needs_delay (mips_gp_register);
6611 relax_start (offset_expr.X_add_symbol);
6612 macro_build (&offset_expr, "lui", "t,u",
6613 AT, BFD_RELOC_MIPS_GOT_HI16);
6614 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6615 AT, AT, mips_gp_register);
6616 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6617 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6620 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6621 /* Itbl support may require additional care here. */
6622 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6623 BFD_RELOC_LO16, AT);
6624 expr1.X_add_number += 4;
6626 /* Set mips_optimize to 2 to avoid inserting an undesired
6628 hold_mips_optimize = mips_optimize;
6630 /* Itbl support may require additional care here. */
6631 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6632 BFD_RELOC_LO16, AT);
6633 mips_optimize = hold_mips_optimize;
6634 expr1.X_add_number -= 4;
6637 offset_expr.X_add_number = expr1.X_add_number;
6639 macro_build (NULL, "nop", "");
6640 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6641 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6644 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6645 /* Itbl support may require additional care here. */
6646 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6647 BFD_RELOC_LO16, AT);
6648 offset_expr.X_add_number += 4;
6650 /* Set mips_optimize to 2 to avoid inserting an undesired
6652 hold_mips_optimize = mips_optimize;
6654 /* Itbl support may require additional care here. */
6655 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6656 BFD_RELOC_LO16, AT);
6657 mips_optimize = hold_mips_optimize;
6674 assert (HAVE_32BIT_ADDRESSES);
6675 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6676 offset_expr.X_add_number += 4;
6677 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6680 /* New code added to support COPZ instructions.
6681 This code builds table entries out of the macros in mip_opcodes.
6682 R4000 uses interlocks to handle coproc delays.
6683 Other chips (like the R3000) require nops to be inserted for delays.
6685 FIXME: Currently, we require that the user handle delays.
6686 In order to fill delay slots for non-interlocked chips,
6687 we must have a way to specify delays based on the coprocessor.
6688 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6689 What are the side-effects of the cop instruction?
6690 What cache support might we have and what are its effects?
6691 Both coprocessor & memory require delays. how long???
6692 What registers are read/set/modified?
6694 If an itbl is provided to interpret cop instructions,
6695 this knowledge can be encoded in the itbl spec. */
6709 /* For now we just do C (same as Cz). The parameter will be
6710 stored in insn_opcode by mips_ip. */
6711 macro_build (NULL, s, "C", ip->insn_opcode);
6715 move_register (dreg, sreg);
6718 #ifdef LOSING_COMPILER
6720 /* Try and see if this is a new itbl instruction.
6721 This code builds table entries out of the macros in mip_opcodes.
6722 FIXME: For now we just assemble the expression and pass it's
6723 value along as a 32-bit immediate.
6724 We may want to have the assembler assemble this value,
6725 so that we gain the assembler's knowledge of delay slots,
6727 Would it be more efficient to use mask (id) here? */
6728 if (itbl_have_entries
6729 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6731 s = ip->insn_mo->name;
6733 coproc = ITBL_DECODE_PNUM (immed_expr);;
6734 macro_build (&immed_expr, s, "C");
6741 as_warn (_("Macro used $at after \".set noat\""));
6745 macro2 (struct mips_cl_insn *ip)
6747 register int treg, sreg, dreg, breg;
6762 bfd_reloc_code_real_type r;
6764 treg = (ip->insn_opcode >> 16) & 0x1f;
6765 dreg = (ip->insn_opcode >> 11) & 0x1f;
6766 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6767 mask = ip->insn_mo->mask;
6769 expr1.X_op = O_constant;
6770 expr1.X_op_symbol = NULL;
6771 expr1.X_add_symbol = NULL;
6772 expr1.X_add_number = 1;
6776 #endif /* LOSING_COMPILER */
6781 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6782 macro_build (NULL, "mflo", "d", dreg);
6788 /* The MIPS assembler some times generates shifts and adds. I'm
6789 not trying to be that fancy. GCC should do this for us
6791 load_register (AT, &imm_expr, dbl);
6792 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6793 macro_build (NULL, "mflo", "d", dreg);
6806 mips_emit_delays (TRUE);
6807 ++mips_opts.noreorder;
6808 mips_any_noreorder = 1;
6810 load_register (AT, &imm_expr, dbl);
6811 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6812 macro_build (NULL, "mflo", "d", dreg);
6813 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6814 macro_build (NULL, "mfhi", "d", AT);
6816 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6819 expr1.X_add_number = 8;
6820 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6821 macro_build (NULL, "nop", "", 0);
6822 macro_build (NULL, "break", "c", 6);
6824 --mips_opts.noreorder;
6825 macro_build (NULL, "mflo", "d", dreg);
6838 mips_emit_delays (TRUE);
6839 ++mips_opts.noreorder;
6840 mips_any_noreorder = 1;
6842 load_register (AT, &imm_expr, dbl);
6843 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6844 sreg, imm ? AT : treg);
6845 macro_build (NULL, "mfhi", "d", AT);
6846 macro_build (NULL, "mflo", "d", dreg);
6848 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6851 expr1.X_add_number = 8;
6852 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6853 macro_build (NULL, "nop", "", 0);
6854 macro_build (NULL, "break", "c", 6);
6856 --mips_opts.noreorder;
6860 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6872 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6873 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6878 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6879 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6880 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6881 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6885 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6897 macro_build (NULL, "negu", "d,w", tempreg, treg);
6898 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6903 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6904 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6905 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6906 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6914 if (imm_expr.X_op != O_constant)
6915 as_bad (_("Improper rotate count"));
6916 rot = imm_expr.X_add_number & 0x3f;
6917 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6919 rot = (64 - rot) & 0x3f;
6921 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6923 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6928 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
6931 l = (rot < 0x20) ? "dsll" : "dsll32";
6932 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6934 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
6935 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6936 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6944 if (imm_expr.X_op != O_constant)
6945 as_bad (_("Improper rotate count"));
6946 rot = imm_expr.X_add_number & 0x1f;
6947 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6949 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6954 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
6957 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
6958 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6959 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6964 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6966 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
6969 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6970 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
6971 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
6972 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6976 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6978 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
6981 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6982 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
6983 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
6984 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6992 if (imm_expr.X_op != O_constant)
6993 as_bad (_("Improper rotate count"));
6994 rot = imm_expr.X_add_number & 0x3f;
6995 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6998 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7000 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7005 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7008 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7009 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7011 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7012 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7013 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7021 if (imm_expr.X_op != O_constant)
7022 as_bad (_("Improper rotate count"));
7023 rot = imm_expr.X_add_number & 0x1f;
7024 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7026 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7031 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7034 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7035 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7036 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7041 if (mips_opts.arch == CPU_R4650)
7043 as_bad (_("opcode not supported on this processor"));
7046 assert (mips_opts.isa == ISA_MIPS1);
7047 /* Even on a big endian machine $fn comes before $fn+1. We have
7048 to adjust when storing to memory. */
7049 macro_build (&offset_expr, "swc1", "T,o(b)",
7050 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7051 offset_expr.X_add_number += 4;
7052 macro_build (&offset_expr, "swc1", "T,o(b)",
7053 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7058 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7060 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7063 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7064 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7069 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7071 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7076 as_warn (_("Instruction %s: result is always false"),
7078 move_register (dreg, 0);
7081 if (imm_expr.X_op == O_constant
7082 && imm_expr.X_add_number >= 0
7083 && imm_expr.X_add_number < 0x10000)
7085 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7088 else if (imm_expr.X_op == O_constant
7089 && imm_expr.X_add_number > -0x8000
7090 && imm_expr.X_add_number < 0)
7092 imm_expr.X_add_number = -imm_expr.X_add_number;
7093 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7094 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7099 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7100 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7103 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7108 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7114 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7115 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7118 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7120 if (imm_expr.X_op == O_constant
7121 && imm_expr.X_add_number >= -0x8000
7122 && imm_expr.X_add_number < 0x8000)
7124 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7125 dreg, sreg, BFD_RELOC_LO16);
7130 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7131 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7135 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7140 case M_SGT: /* sreg > treg <==> treg < sreg */
7146 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7149 case M_SGT_I: /* sreg > I <==> I < sreg */
7155 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7156 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7159 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7165 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7166 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7169 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7175 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7176 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7177 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7181 if (imm_expr.X_op == O_constant
7182 && imm_expr.X_add_number >= -0x8000
7183 && imm_expr.X_add_number < 0x8000)
7185 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7188 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7189 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7193 if (imm_expr.X_op == O_constant
7194 && imm_expr.X_add_number >= -0x8000
7195 && imm_expr.X_add_number < 0x8000)
7197 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7201 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7202 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7207 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7209 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7212 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7213 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7218 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7220 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7225 as_warn (_("Instruction %s: result is always true"),
7227 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7228 dreg, 0, BFD_RELOC_LO16);
7231 if (imm_expr.X_op == O_constant
7232 && imm_expr.X_add_number >= 0
7233 && imm_expr.X_add_number < 0x10000)
7235 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7238 else if (imm_expr.X_op == O_constant
7239 && imm_expr.X_add_number > -0x8000
7240 && imm_expr.X_add_number < 0)
7242 imm_expr.X_add_number = -imm_expr.X_add_number;
7243 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7244 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7249 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7250 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7253 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7261 if (imm_expr.X_op == O_constant
7262 && imm_expr.X_add_number > -0x8000
7263 && imm_expr.X_add_number <= 0x8000)
7265 imm_expr.X_add_number = -imm_expr.X_add_number;
7266 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7267 dreg, sreg, BFD_RELOC_LO16);
7270 load_register (AT, &imm_expr, dbl);
7271 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7277 if (imm_expr.X_op == O_constant
7278 && imm_expr.X_add_number > -0x8000
7279 && imm_expr.X_add_number <= 0x8000)
7281 imm_expr.X_add_number = -imm_expr.X_add_number;
7282 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7283 dreg, sreg, BFD_RELOC_LO16);
7286 load_register (AT, &imm_expr, dbl);
7287 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7308 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7309 macro_build (NULL, s, "s,t", sreg, AT);
7314 assert (mips_opts.isa == ISA_MIPS1);
7315 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7316 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7319 * Is the double cfc1 instruction a bug in the mips assembler;
7320 * or is there a reason for it?
7322 mips_emit_delays (TRUE);
7323 ++mips_opts.noreorder;
7324 mips_any_noreorder = 1;
7325 macro_build (NULL, "cfc1", "t,G", treg, RA);
7326 macro_build (NULL, "cfc1", "t,G", treg, RA);
7327 macro_build (NULL, "nop", "");
7328 expr1.X_add_number = 3;
7329 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7330 expr1.X_add_number = 2;
7331 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7332 macro_build (NULL, "ctc1", "t,G", AT, RA);
7333 macro_build (NULL, "nop", "");
7334 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7336 macro_build (NULL, "ctc1", "t,G", treg, RA);
7337 macro_build (NULL, "nop", "");
7338 --mips_opts.noreorder;
7347 if (offset_expr.X_add_number >= 0x7fff)
7348 as_bad (_("operand overflow"));
7349 if (! target_big_endian)
7350 ++offset_expr.X_add_number;
7351 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7352 if (! target_big_endian)
7353 --offset_expr.X_add_number;
7355 ++offset_expr.X_add_number;
7356 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7357 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7358 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7371 if (offset_expr.X_add_number >= 0x8000 - off)
7372 as_bad (_("operand overflow"));
7377 if (! target_big_endian)
7378 offset_expr.X_add_number += off;
7379 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7380 if (! target_big_endian)
7381 offset_expr.X_add_number -= off;
7383 offset_expr.X_add_number += off;
7384 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7386 /* If necessary, move the result in tempreg the final destination. */
7387 if (treg == tempreg)
7389 /* Protect second load's delay slot. */
7391 move_register (treg, tempreg);
7405 load_address (AT, &offset_expr, &used_at);
7407 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7408 if (! target_big_endian)
7409 expr1.X_add_number = off;
7411 expr1.X_add_number = 0;
7412 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7413 if (! target_big_endian)
7414 expr1.X_add_number = 0;
7416 expr1.X_add_number = off;
7417 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7423 load_address (AT, &offset_expr, &used_at);
7425 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7426 if (target_big_endian)
7427 expr1.X_add_number = 0;
7428 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7429 treg, BFD_RELOC_LO16, AT);
7430 if (target_big_endian)
7431 expr1.X_add_number = 1;
7433 expr1.X_add_number = 0;
7434 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7435 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7436 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7440 if (offset_expr.X_add_number >= 0x7fff)
7441 as_bad (_("operand overflow"));
7442 if (target_big_endian)
7443 ++offset_expr.X_add_number;
7444 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7445 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7446 if (target_big_endian)
7447 --offset_expr.X_add_number;
7449 ++offset_expr.X_add_number;
7450 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7463 if (offset_expr.X_add_number >= 0x8000 - off)
7464 as_bad (_("operand overflow"));
7465 if (! target_big_endian)
7466 offset_expr.X_add_number += off;
7467 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7468 if (! target_big_endian)
7469 offset_expr.X_add_number -= off;
7471 offset_expr.X_add_number += off;
7472 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7486 load_address (AT, &offset_expr, &used_at);
7488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7489 if (! target_big_endian)
7490 expr1.X_add_number = off;
7492 expr1.X_add_number = 0;
7493 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7494 if (! target_big_endian)
7495 expr1.X_add_number = 0;
7497 expr1.X_add_number = off;
7498 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7503 load_address (AT, &offset_expr, &used_at);
7505 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7506 if (! target_big_endian)
7507 expr1.X_add_number = 0;
7508 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7509 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7510 if (! target_big_endian)
7511 expr1.X_add_number = 1;
7513 expr1.X_add_number = 0;
7514 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7515 if (! target_big_endian)
7516 expr1.X_add_number = 0;
7518 expr1.X_add_number = 1;
7519 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7520 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7521 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7525 /* FIXME: Check if this is one of the itbl macros, since they
7526 are added dynamically. */
7527 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7531 as_warn (_("Macro used $at after \".set noat\""));
7534 /* Implement macros in mips16 mode. */
7537 mips16_macro (struct mips_cl_insn *ip)
7540 int xreg, yreg, zreg, tmp;
7543 const char *s, *s2, *s3;
7545 mask = ip->insn_mo->mask;
7547 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7548 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7549 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7551 expr1.X_op = O_constant;
7552 expr1.X_op_symbol = NULL;
7553 expr1.X_add_symbol = NULL;
7554 expr1.X_add_number = 1;
7573 mips_emit_delays (TRUE);
7574 ++mips_opts.noreorder;
7575 mips_any_noreorder = 1;
7576 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7577 expr1.X_add_number = 2;
7578 macro_build (&expr1, "bnez", "x,p", yreg);
7579 macro_build (NULL, "break", "6", 7);
7581 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7582 since that causes an overflow. We should do that as well,
7583 but I don't see how to do the comparisons without a temporary
7585 --mips_opts.noreorder;
7586 macro_build (NULL, s, "x", zreg);
7605 mips_emit_delays (TRUE);
7606 ++mips_opts.noreorder;
7607 mips_any_noreorder = 1;
7608 macro_build (NULL, s, "0,x,y", xreg, yreg);
7609 expr1.X_add_number = 2;
7610 macro_build (&expr1, "bnez", "x,p", yreg);
7611 macro_build (NULL, "break", "6", 7);
7612 --mips_opts.noreorder;
7613 macro_build (NULL, s2, "x", zreg);
7619 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7620 macro_build (NULL, "mflo", "x", zreg);
7628 if (imm_expr.X_op != O_constant)
7629 as_bad (_("Unsupported large constant"));
7630 imm_expr.X_add_number = -imm_expr.X_add_number;
7631 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7635 if (imm_expr.X_op != O_constant)
7636 as_bad (_("Unsupported large constant"));
7637 imm_expr.X_add_number = -imm_expr.X_add_number;
7638 macro_build (&imm_expr, "addiu", "x,k", xreg);
7642 if (imm_expr.X_op != O_constant)
7643 as_bad (_("Unsupported large constant"));
7644 imm_expr.X_add_number = -imm_expr.X_add_number;
7645 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7667 goto do_reverse_branch;
7671 goto do_reverse_branch;
7683 goto do_reverse_branch;
7694 macro_build (NULL, s, "x,y", xreg, yreg);
7695 macro_build (&offset_expr, s2, "p");
7722 goto do_addone_branch_i;
7727 goto do_addone_branch_i;
7742 goto do_addone_branch_i;
7749 if (imm_expr.X_op != O_constant)
7750 as_bad (_("Unsupported large constant"));
7751 ++imm_expr.X_add_number;
7754 macro_build (&imm_expr, s, s3, xreg);
7755 macro_build (&offset_expr, s2, "p");
7759 expr1.X_add_number = 0;
7760 macro_build (&expr1, "slti", "x,8", yreg);
7762 move_register (xreg, yreg);
7763 expr1.X_add_number = 2;
7764 macro_build (&expr1, "bteqz", "p");
7765 macro_build (NULL, "neg", "x,w", xreg, xreg);
7769 /* For consistency checking, verify that all bits are specified either
7770 by the match/mask part of the instruction definition, or by the
7773 validate_mips_insn (const struct mips_opcode *opc)
7775 const char *p = opc->args;
7777 unsigned long used_bits = opc->mask;
7779 if ((used_bits & opc->match) != opc->match)
7781 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7782 opc->name, opc->args);
7785 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7795 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7796 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7797 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7798 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7799 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7800 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7801 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7802 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7803 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7806 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7807 c, opc->name, opc->args);
7811 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7812 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7814 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7815 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7816 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7817 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7819 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7820 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7822 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7823 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7825 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7826 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7827 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7828 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7829 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7830 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7831 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7832 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7833 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7834 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7835 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7836 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7837 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7838 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7839 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7840 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7841 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7843 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7844 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7845 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7846 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7848 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7849 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7850 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7851 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7852 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7853 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7854 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7855 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7856 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7859 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7860 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7861 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7862 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7863 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7867 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7868 c, opc->name, opc->args);
7872 if (used_bits != 0xffffffff)
7874 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7875 ~used_bits & 0xffffffff, opc->name, opc->args);
7881 /* This routine assembles an instruction into its binary format. As a
7882 side effect, it sets one of the global variables imm_reloc or
7883 offset_reloc to the type of relocation to do if one of the operands
7884 is an address expression. */
7887 mips_ip (char *str, struct mips_cl_insn *ip)
7892 struct mips_opcode *insn;
7895 unsigned int lastregno = 0;
7896 unsigned int lastpos = 0;
7897 unsigned int limlo, limhi;
7903 /* If the instruction contains a '.', we first try to match an instruction
7904 including the '.'. Then we try again without the '.'. */
7906 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7909 /* If we stopped on whitespace, then replace the whitespace with null for
7910 the call to hash_find. Save the character we replaced just in case we
7911 have to re-parse the instruction. */
7918 insn = (struct mips_opcode *) hash_find (op_hash, str);
7920 /* If we didn't find the instruction in the opcode table, try again, but
7921 this time with just the instruction up to, but not including the
7925 /* Restore the character we overwrite above (if any). */
7929 /* Scan up to the first '.' or whitespace. */
7931 *s != '\0' && *s != '.' && !ISSPACE (*s);
7935 /* If we did not find a '.', then we can quit now. */
7938 insn_error = "unrecognized opcode";
7942 /* Lookup the instruction in the hash table. */
7944 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7946 insn_error = "unrecognized opcode";
7956 assert (strcmp (insn->name, str) == 0);
7958 if (OPCODE_IS_MEMBER (insn,
7960 | (file_ase_mips16 ? INSN_MIPS16 : 0)
7961 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7962 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7968 if (insn->pinfo != INSN_MACRO)
7970 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7976 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7977 && strcmp (insn->name, insn[1].name) == 0)
7986 static char buf[100];
7988 _("opcode not supported on this processor: %s (%s)"),
7989 mips_cpu_info_from_arch (mips_opts.arch)->name,
7990 mips_cpu_info_from_isa (mips_opts.isa)->name);
8000 ip->insn_opcode = insn->match;
8002 for (args = insn->args;; ++args)
8006 s += strspn (s, " \t");
8010 case '\0': /* end of args */
8023 ip->insn_opcode |= lastregno << OP_SH_RS;
8027 ip->insn_opcode |= lastregno << OP_SH_RT;
8031 ip->insn_opcode |= lastregno << OP_SH_FT;
8035 ip->insn_opcode |= lastregno << OP_SH_FS;
8041 /* Handle optional base register.
8042 Either the base register is omitted or
8043 we must have a left paren. */
8044 /* This is dependent on the next operand specifier
8045 is a base register specification. */
8046 assert (args[1] == 'b' || args[1] == '5'
8047 || args[1] == '-' || args[1] == '4');
8051 case ')': /* these must match exactly */
8058 case '+': /* Opcode extension character. */
8061 case 'A': /* ins/ext position, becomes LSB. */
8070 my_getExpression (&imm_expr, s);
8071 check_absolute_expr (ip, &imm_expr);
8072 if ((unsigned long) imm_expr.X_add_number < limlo
8073 || (unsigned long) imm_expr.X_add_number > limhi)
8075 as_bad (_("Improper position (%lu)"),
8076 (unsigned long) imm_expr.X_add_number);
8077 imm_expr.X_add_number = limlo;
8079 lastpos = imm_expr.X_add_number;
8080 ip->insn_opcode |= (imm_expr.X_add_number
8081 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8082 imm_expr.X_op = O_absent;
8086 case 'B': /* ins size, becomes MSB. */
8095 my_getExpression (&imm_expr, s);
8096 check_absolute_expr (ip, &imm_expr);
8097 /* Check for negative input so that small negative numbers
8098 will not succeed incorrectly. The checks against
8099 (pos+size) transitively check "size" itself,
8100 assuming that "pos" is reasonable. */
8101 if ((long) imm_expr.X_add_number < 0
8102 || ((unsigned long) imm_expr.X_add_number
8104 || ((unsigned long) imm_expr.X_add_number
8107 as_bad (_("Improper insert size (%lu, position %lu)"),
8108 (unsigned long) imm_expr.X_add_number,
8109 (unsigned long) lastpos);
8110 imm_expr.X_add_number = limlo - lastpos;
8112 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8113 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8114 imm_expr.X_op = O_absent;
8118 case 'C': /* ext size, becomes MSBD. */
8131 my_getExpression (&imm_expr, s);
8132 check_absolute_expr (ip, &imm_expr);
8133 /* Check for negative input so that small negative numbers
8134 will not succeed incorrectly. The checks against
8135 (pos+size) transitively check "size" itself,
8136 assuming that "pos" is reasonable. */
8137 if ((long) imm_expr.X_add_number < 0
8138 || ((unsigned long) imm_expr.X_add_number
8140 || ((unsigned long) imm_expr.X_add_number
8143 as_bad (_("Improper extract size (%lu, position %lu)"),
8144 (unsigned long) imm_expr.X_add_number,
8145 (unsigned long) lastpos);
8146 imm_expr.X_add_number = limlo - lastpos;
8148 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8149 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8150 imm_expr.X_op = O_absent;
8155 /* +D is for disassembly only; never match. */
8159 /* "+I" is like "I", except that imm2_expr is used. */
8160 my_getExpression (&imm2_expr, s);
8161 if (imm2_expr.X_op != O_big
8162 && imm2_expr.X_op != O_constant)
8163 insn_error = _("absolute expression required");
8164 normalize_constant_expr (&imm2_expr);
8169 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8170 *args, insn->name, insn->args);
8171 /* Further processing is fruitless. */
8176 case '<': /* must be at least one digit */
8178 * According to the manual, if the shift amount is greater
8179 * than 31 or less than 0, then the shift amount should be
8180 * mod 32. In reality the mips assembler issues an error.
8181 * We issue a warning and mask out all but the low 5 bits.
8183 my_getExpression (&imm_expr, s);
8184 check_absolute_expr (ip, &imm_expr);
8185 if ((unsigned long) imm_expr.X_add_number > 31)
8187 as_warn (_("Improper shift amount (%lu)"),
8188 (unsigned long) imm_expr.X_add_number);
8189 imm_expr.X_add_number &= OP_MASK_SHAMT;
8191 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8192 imm_expr.X_op = O_absent;
8196 case '>': /* shift amount minus 32 */
8197 my_getExpression (&imm_expr, s);
8198 check_absolute_expr (ip, &imm_expr);
8199 if ((unsigned long) imm_expr.X_add_number < 32
8200 || (unsigned long) imm_expr.X_add_number > 63)
8202 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8203 imm_expr.X_op = O_absent;
8207 case 'k': /* cache code */
8208 case 'h': /* prefx code */
8209 my_getExpression (&imm_expr, s);
8210 check_absolute_expr (ip, &imm_expr);
8211 if ((unsigned long) imm_expr.X_add_number > 31)
8213 as_warn (_("Invalid value for `%s' (%lu)"),
8215 (unsigned long) imm_expr.X_add_number);
8216 imm_expr.X_add_number &= 0x1f;
8219 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8221 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8222 imm_expr.X_op = O_absent;
8226 case 'c': /* break code */
8227 my_getExpression (&imm_expr, s);
8228 check_absolute_expr (ip, &imm_expr);
8229 if ((unsigned long) imm_expr.X_add_number > 1023)
8231 as_warn (_("Illegal break code (%lu)"),
8232 (unsigned long) imm_expr.X_add_number);
8233 imm_expr.X_add_number &= OP_MASK_CODE;
8235 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8236 imm_expr.X_op = O_absent;
8240 case 'q': /* lower break code */
8241 my_getExpression (&imm_expr, s);
8242 check_absolute_expr (ip, &imm_expr);
8243 if ((unsigned long) imm_expr.X_add_number > 1023)
8245 as_warn (_("Illegal lower break code (%lu)"),
8246 (unsigned long) imm_expr.X_add_number);
8247 imm_expr.X_add_number &= OP_MASK_CODE2;
8249 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8250 imm_expr.X_op = O_absent;
8254 case 'B': /* 20-bit syscall/break code. */
8255 my_getExpression (&imm_expr, s);
8256 check_absolute_expr (ip, &imm_expr);
8257 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8258 as_warn (_("Illegal 20-bit code (%lu)"),
8259 (unsigned long) imm_expr.X_add_number);
8260 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8261 imm_expr.X_op = O_absent;
8265 case 'C': /* Coprocessor code */
8266 my_getExpression (&imm_expr, s);
8267 check_absolute_expr (ip, &imm_expr);
8268 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8270 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8271 (unsigned long) imm_expr.X_add_number);
8272 imm_expr.X_add_number &= ((1 << 25) - 1);
8274 ip->insn_opcode |= imm_expr.X_add_number;
8275 imm_expr.X_op = O_absent;
8279 case 'J': /* 19-bit wait code. */
8280 my_getExpression (&imm_expr, s);
8281 check_absolute_expr (ip, &imm_expr);
8282 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8283 as_warn (_("Illegal 19-bit code (%lu)"),
8284 (unsigned long) imm_expr.X_add_number);
8285 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8286 imm_expr.X_op = O_absent;
8290 case 'P': /* Performance register */
8291 my_getExpression (&imm_expr, s);
8292 check_absolute_expr (ip, &imm_expr);
8293 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8295 as_warn (_("Invalid performance register (%lu)"),
8296 (unsigned long) imm_expr.X_add_number);
8297 imm_expr.X_add_number &= OP_MASK_PERFREG;
8299 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8300 imm_expr.X_op = O_absent;
8304 case 'b': /* base register */
8305 case 'd': /* destination register */
8306 case 's': /* source register */
8307 case 't': /* target register */
8308 case 'r': /* both target and source */
8309 case 'v': /* both dest and source */
8310 case 'w': /* both dest and target */
8311 case 'E': /* coprocessor target register */
8312 case 'G': /* coprocessor destination register */
8313 case 'K': /* 'rdhwr' destination register */
8314 case 'x': /* ignore register name */
8315 case 'z': /* must be zero register */
8316 case 'U': /* destination register (clo/clz). */
8331 while (ISDIGIT (*s));
8333 as_bad (_("Invalid register number (%d)"), regno);
8335 else if (*args == 'E' || *args == 'G' || *args == 'K')
8339 if (s[1] == 'r' && s[2] == 'a')
8344 else if (s[1] == 'f' && s[2] == 'p')
8349 else if (s[1] == 's' && s[2] == 'p')
8354 else if (s[1] == 'g' && s[2] == 'p')
8359 else if (s[1] == 'a' && s[2] == 't')
8364 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8369 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8374 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8379 else if (itbl_have_entries)
8384 p = s + 1; /* advance past '$' */
8385 n = itbl_get_field (&p); /* n is name */
8387 /* See if this is a register defined in an
8389 if (itbl_get_reg_val (n, &r))
8391 /* Get_field advances to the start of
8392 the next field, so we need to back
8393 rack to the end of the last field. */
8397 s = strchr (s, '\0');
8411 as_warn (_("Used $at without \".set noat\""));
8417 if (c == 'r' || c == 'v' || c == 'w')
8424 /* 'z' only matches $0. */
8425 if (c == 'z' && regno != 0)
8428 /* Now that we have assembled one operand, we use the args string
8429 * to figure out where it goes in the instruction. */
8436 ip->insn_opcode |= regno << OP_SH_RS;
8441 ip->insn_opcode |= regno << OP_SH_RD;
8444 ip->insn_opcode |= regno << OP_SH_RD;
8445 ip->insn_opcode |= regno << OP_SH_RT;
8450 ip->insn_opcode |= regno << OP_SH_RT;
8453 /* This case exists because on the r3000 trunc
8454 expands into a macro which requires a gp
8455 register. On the r6000 or r4000 it is
8456 assembled into a single instruction which
8457 ignores the register. Thus the insn version
8458 is MIPS_ISA2 and uses 'x', and the macro
8459 version is MIPS_ISA1 and uses 't'. */
8462 /* This case is for the div instruction, which
8463 acts differently if the destination argument
8464 is $0. This only matches $0, and is checked
8465 outside the switch. */
8468 /* Itbl operand; not yet implemented. FIXME ?? */
8470 /* What about all other operands like 'i', which
8471 can be specified in the opcode table? */
8481 ip->insn_opcode |= lastregno << OP_SH_RS;
8484 ip->insn_opcode |= lastregno << OP_SH_RT;
8489 case 'O': /* MDMX alignment immediate constant. */
8490 my_getExpression (&imm_expr, s);
8491 check_absolute_expr (ip, &imm_expr);
8492 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8494 as_warn ("Improper align amount (%ld), using low bits",
8495 (long) imm_expr.X_add_number);
8496 imm_expr.X_add_number &= OP_MASK_ALN;
8498 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8499 imm_expr.X_op = O_absent;
8503 case 'Q': /* MDMX vector, element sel, or const. */
8506 /* MDMX Immediate. */
8507 my_getExpression (&imm_expr, s);
8508 check_absolute_expr (ip, &imm_expr);
8509 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8511 as_warn (_("Invalid MDMX Immediate (%ld)"),
8512 (long) imm_expr.X_add_number);
8513 imm_expr.X_add_number &= OP_MASK_FT;
8515 imm_expr.X_add_number &= OP_MASK_FT;
8516 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8517 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8519 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8520 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8521 imm_expr.X_op = O_absent;
8525 /* Not MDMX Immediate. Fall through. */
8526 case 'X': /* MDMX destination register. */
8527 case 'Y': /* MDMX source register. */
8528 case 'Z': /* MDMX target register. */
8530 case 'D': /* floating point destination register */
8531 case 'S': /* floating point source register */
8532 case 'T': /* floating point target register */
8533 case 'R': /* floating point source register */
8537 /* Accept $fN for FP and MDMX register numbers, and in
8538 addition accept $vN for MDMX register numbers. */
8539 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8540 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8551 while (ISDIGIT (*s));
8554 as_bad (_("Invalid float register number (%d)"), regno);
8556 if ((regno & 1) != 0
8558 && ! (strcmp (str, "mtc1") == 0
8559 || strcmp (str, "mfc1") == 0
8560 || strcmp (str, "lwc1") == 0
8561 || strcmp (str, "swc1") == 0
8562 || strcmp (str, "l.s") == 0
8563 || strcmp (str, "s.s") == 0))
8564 as_warn (_("Float register should be even, was %d"),
8572 if (c == 'V' || c == 'W')
8583 ip->insn_opcode |= regno << OP_SH_FD;
8588 ip->insn_opcode |= regno << OP_SH_FS;
8591 /* This is like 'Z', but also needs to fix the MDMX
8592 vector/scalar select bits. Note that the
8593 scalar immediate case is handled above. */
8596 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8597 int max_el = (is_qh ? 3 : 7);
8599 my_getExpression(&imm_expr, s);
8600 check_absolute_expr (ip, &imm_expr);
8602 if (imm_expr.X_add_number > max_el)
8603 as_bad(_("Bad element selector %ld"),
8604 (long) imm_expr.X_add_number);
8605 imm_expr.X_add_number &= max_el;
8606 ip->insn_opcode |= (imm_expr.X_add_number
8609 imm_expr.X_op = O_absent;
8611 as_warn(_("Expecting ']' found '%s'"), s);
8617 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8618 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8621 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8628 ip->insn_opcode |= regno << OP_SH_FT;
8631 ip->insn_opcode |= regno << OP_SH_FR;
8641 ip->insn_opcode |= lastregno << OP_SH_FS;
8644 ip->insn_opcode |= lastregno << OP_SH_FT;
8650 my_getExpression (&imm_expr, s);
8651 if (imm_expr.X_op != O_big
8652 && imm_expr.X_op != O_constant)
8653 insn_error = _("absolute expression required");
8654 normalize_constant_expr (&imm_expr);
8659 my_getExpression (&offset_expr, s);
8660 *imm_reloc = BFD_RELOC_32;
8673 unsigned char temp[8];
8675 unsigned int length;
8680 /* These only appear as the last operand in an
8681 instruction, and every instruction that accepts
8682 them in any variant accepts them in all variants.
8683 This means we don't have to worry about backing out
8684 any changes if the instruction does not match.
8686 The difference between them is the size of the
8687 floating point constant and where it goes. For 'F'
8688 and 'L' the constant is 64 bits; for 'f' and 'l' it
8689 is 32 bits. Where the constant is placed is based
8690 on how the MIPS assembler does things:
8693 f -- immediate value
8696 The .lit4 and .lit8 sections are only used if
8697 permitted by the -G argument.
8699 The code below needs to know whether the target register
8700 is 32 or 64 bits wide. It relies on the fact 'f' and
8701 'F' are used with GPR-based instructions and 'l' and
8702 'L' are used with FPR-based instructions. */
8704 f64 = *args == 'F' || *args == 'L';
8705 using_gprs = *args == 'F' || *args == 'f';
8707 save_in = input_line_pointer;
8708 input_line_pointer = s;
8709 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8711 s = input_line_pointer;
8712 input_line_pointer = save_in;
8713 if (err != NULL && *err != '\0')
8715 as_bad (_("Bad floating point constant: %s"), err);
8716 memset (temp, '\0', sizeof temp);
8717 length = f64 ? 8 : 4;
8720 assert (length == (unsigned) (f64 ? 8 : 4));
8724 && (g_switch_value < 4
8725 || (temp[0] == 0 && temp[1] == 0)
8726 || (temp[2] == 0 && temp[3] == 0))))
8728 imm_expr.X_op = O_constant;
8729 if (! target_big_endian)
8730 imm_expr.X_add_number = bfd_getl32 (temp);
8732 imm_expr.X_add_number = bfd_getb32 (temp);
8735 && ! mips_disable_float_construction
8736 /* Constants can only be constructed in GPRs and
8737 copied to FPRs if the GPRs are at least as wide
8738 as the FPRs. Force the constant into memory if
8739 we are using 64-bit FPRs but the GPRs are only
8742 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8743 && ((temp[0] == 0 && temp[1] == 0)
8744 || (temp[2] == 0 && temp[3] == 0))
8745 && ((temp[4] == 0 && temp[5] == 0)
8746 || (temp[6] == 0 && temp[7] == 0)))
8748 /* The value is simple enough to load with a couple of
8749 instructions. If using 32-bit registers, set
8750 imm_expr to the high order 32 bits and offset_expr to
8751 the low order 32 bits. Otherwise, set imm_expr to
8752 the entire 64 bit constant. */
8753 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8755 imm_expr.X_op = O_constant;
8756 offset_expr.X_op = O_constant;
8757 if (! target_big_endian)
8759 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8760 offset_expr.X_add_number = bfd_getl32 (temp);
8764 imm_expr.X_add_number = bfd_getb32 (temp);
8765 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8767 if (offset_expr.X_add_number == 0)
8768 offset_expr.X_op = O_absent;
8770 else if (sizeof (imm_expr.X_add_number) > 4)
8772 imm_expr.X_op = O_constant;
8773 if (! target_big_endian)
8774 imm_expr.X_add_number = bfd_getl64 (temp);
8776 imm_expr.X_add_number = bfd_getb64 (temp);
8780 imm_expr.X_op = O_big;
8781 imm_expr.X_add_number = 4;
8782 if (! target_big_endian)
8784 generic_bignum[0] = bfd_getl16 (temp);
8785 generic_bignum[1] = bfd_getl16 (temp + 2);
8786 generic_bignum[2] = bfd_getl16 (temp + 4);
8787 generic_bignum[3] = bfd_getl16 (temp + 6);
8791 generic_bignum[0] = bfd_getb16 (temp + 6);
8792 generic_bignum[1] = bfd_getb16 (temp + 4);
8793 generic_bignum[2] = bfd_getb16 (temp + 2);
8794 generic_bignum[3] = bfd_getb16 (temp);
8800 const char *newname;
8803 /* Switch to the right section. */
8805 subseg = now_subseg;
8808 default: /* unused default case avoids warnings. */
8810 newname = RDATA_SECTION_NAME;
8811 if (g_switch_value >= 8)
8815 newname = RDATA_SECTION_NAME;
8818 assert (g_switch_value >= 4);
8822 new_seg = subseg_new (newname, (subsegT) 0);
8823 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8824 bfd_set_section_flags (stdoutput, new_seg,
8829 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8830 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8831 && strcmp (TARGET_OS, "elf") != 0)
8832 record_alignment (new_seg, 4);
8834 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8836 as_bad (_("Can't use floating point insn in this section"));
8838 /* Set the argument to the current address in the
8840 offset_expr.X_op = O_symbol;
8841 offset_expr.X_add_symbol =
8842 symbol_new ("L0\001", now_seg,
8843 (valueT) frag_now_fix (), frag_now);
8844 offset_expr.X_add_number = 0;
8846 /* Put the floating point number into the section. */
8847 p = frag_more ((int) length);
8848 memcpy (p, temp, length);
8850 /* Switch back to the original section. */
8851 subseg_set (seg, subseg);
8856 case 'i': /* 16 bit unsigned immediate */
8857 case 'j': /* 16 bit signed immediate */
8858 *imm_reloc = BFD_RELOC_LO16;
8859 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
8862 offsetT minval, maxval;
8864 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
8865 && strcmp (insn->name, insn[1].name) == 0);
8867 /* If the expression was written as an unsigned number,
8868 only treat it as signed if there are no more
8872 && sizeof (imm_expr.X_add_number) <= 4
8873 && imm_expr.X_op == O_constant
8874 && imm_expr.X_add_number < 0
8875 && imm_expr.X_unsigned
8879 /* For compatibility with older assemblers, we accept
8880 0x8000-0xffff as signed 16-bit numbers when only
8881 signed numbers are allowed. */
8883 minval = 0, maxval = 0xffff;
8885 minval = -0x8000, maxval = 0x7fff;
8887 minval = -0x8000, maxval = 0xffff;
8889 if (imm_expr.X_op != O_constant
8890 || imm_expr.X_add_number < minval
8891 || imm_expr.X_add_number > maxval)
8895 if (imm_expr.X_op == O_constant
8896 || imm_expr.X_op == O_big)
8897 as_bad (_("expression out of range"));
8903 case 'o': /* 16 bit offset */
8904 /* Check whether there is only a single bracketed expression
8905 left. If so, it must be the base register and the
8906 constant must be zero. */
8907 if (*s == '(' && strchr (s + 1, '(') == 0)
8909 offset_expr.X_op = O_constant;
8910 offset_expr.X_add_number = 0;
8914 /* If this value won't fit into a 16 bit offset, then go
8915 find a macro that will generate the 32 bit offset
8917 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
8918 && (offset_expr.X_op != O_constant
8919 || offset_expr.X_add_number >= 0x8000
8920 || offset_expr.X_add_number < -0x8000))
8926 case 'p': /* pc relative offset */
8927 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8928 my_getExpression (&offset_expr, s);
8932 case 'u': /* upper 16 bits */
8933 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
8934 && imm_expr.X_op == O_constant
8935 && (imm_expr.X_add_number < 0
8936 || imm_expr.X_add_number >= 0x10000))
8937 as_bad (_("lui expression not in range 0..65535"));
8941 case 'a': /* 26 bit address */
8942 my_getExpression (&offset_expr, s);
8944 *offset_reloc = BFD_RELOC_MIPS_JMP;
8947 case 'N': /* 3 bit branch condition code */
8948 case 'M': /* 3 bit compare condition code */
8949 if (strncmp (s, "$fcc", 4) != 0)
8959 while (ISDIGIT (*s));
8961 as_bad (_("Invalid condition code register $fcc%d"), regno);
8962 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
8963 || strcmp(str + strlen(str) - 5, "any2f") == 0
8964 || strcmp(str + strlen(str) - 5, "any2t") == 0)
8965 && (regno & 1) != 0)
8966 as_warn(_("Condition code register should be even for %s, was %d"),
8968 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
8969 || strcmp(str + strlen(str) - 5, "any4t") == 0)
8970 && (regno & 3) != 0)
8971 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8974 ip->insn_opcode |= regno << OP_SH_BCC;
8976 ip->insn_opcode |= regno << OP_SH_CCC;
8980 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8991 while (ISDIGIT (*s));
8994 c = 8; /* Invalid sel value. */
8997 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8998 ip->insn_opcode |= c;
9002 /* Must be at least one digit. */
9003 my_getExpression (&imm_expr, s);
9004 check_absolute_expr (ip, &imm_expr);
9006 if ((unsigned long) imm_expr.X_add_number
9007 > (unsigned long) OP_MASK_VECBYTE)
9009 as_bad (_("bad byte vector index (%ld)"),
9010 (long) imm_expr.X_add_number);
9011 imm_expr.X_add_number = 0;
9014 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9015 imm_expr.X_op = O_absent;
9020 my_getExpression (&imm_expr, s);
9021 check_absolute_expr (ip, &imm_expr);
9023 if ((unsigned long) imm_expr.X_add_number
9024 > (unsigned long) OP_MASK_VECALIGN)
9026 as_bad (_("bad byte vector index (%ld)"),
9027 (long) imm_expr.X_add_number);
9028 imm_expr.X_add_number = 0;
9031 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9032 imm_expr.X_op = O_absent;
9037 as_bad (_("bad char = '%c'\n"), *args);
9042 /* Args don't match. */
9043 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9044 !strcmp (insn->name, insn[1].name))
9048 insn_error = _("illegal operands");
9053 insn_error = _("illegal operands");
9058 /* This routine assembles an instruction into its binary format when
9059 assembling for the mips16. As a side effect, it sets one of the
9060 global variables imm_reloc or offset_reloc to the type of
9061 relocation to do if one of the operands is an address expression.
9062 It also sets mips16_small and mips16_ext if the user explicitly
9063 requested a small or extended instruction. */
9066 mips16_ip (char *str, struct mips_cl_insn *ip)
9070 struct mips_opcode *insn;
9073 unsigned int lastregno = 0;
9078 mips16_small = FALSE;
9081 for (s = str; ISLOWER (*s); ++s)
9093 if (s[1] == 't' && s[2] == ' ')
9096 mips16_small = TRUE;
9100 else if (s[1] == 'e' && s[2] == ' ')
9109 insn_error = _("unknown opcode");
9113 if (mips_opts.noautoextend && ! mips16_ext)
9114 mips16_small = TRUE;
9116 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9118 insn_error = _("unrecognized opcode");
9125 assert (strcmp (insn->name, str) == 0);
9128 ip->insn_opcode = insn->match;
9129 ip->use_extend = FALSE;
9130 imm_expr.X_op = O_absent;
9131 imm_reloc[0] = BFD_RELOC_UNUSED;
9132 imm_reloc[1] = BFD_RELOC_UNUSED;
9133 imm_reloc[2] = BFD_RELOC_UNUSED;
9134 imm2_expr.X_op = O_absent;
9135 offset_expr.X_op = O_absent;
9136 offset_reloc[0] = BFD_RELOC_UNUSED;
9137 offset_reloc[1] = BFD_RELOC_UNUSED;
9138 offset_reloc[2] = BFD_RELOC_UNUSED;
9139 for (args = insn->args; 1; ++args)
9146 /* In this switch statement we call break if we did not find
9147 a match, continue if we did find a match, or return if we
9156 /* Stuff the immediate value in now, if we can. */
9157 if (imm_expr.X_op == O_constant
9158 && *imm_reloc > BFD_RELOC_UNUSED
9159 && insn->pinfo != INSN_MACRO)
9161 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9162 imm_expr.X_add_number, TRUE, mips16_small,
9163 mips16_ext, &ip->insn_opcode,
9164 &ip->use_extend, &ip->extend);
9165 imm_expr.X_op = O_absent;
9166 *imm_reloc = BFD_RELOC_UNUSED;
9180 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9183 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9199 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9201 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9228 while (ISDIGIT (*s));
9231 as_bad (_("invalid register number (%d)"), regno);
9237 if (s[1] == 'r' && s[2] == 'a')
9242 else if (s[1] == 'f' && s[2] == 'p')
9247 else if (s[1] == 's' && s[2] == 'p')
9252 else if (s[1] == 'g' && s[2] == 'p')
9257 else if (s[1] == 'a' && s[2] == 't')
9262 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9267 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9272 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9285 if (c == 'v' || c == 'w')
9287 regno = mips16_to_32_reg_map[lastregno];
9301 regno = mips32_to_16_reg_map[regno];
9306 regno = ILLEGAL_REG;
9311 regno = ILLEGAL_REG;
9316 regno = ILLEGAL_REG;
9321 if (regno == AT && ! mips_opts.noat)
9322 as_warn (_("used $at without \".set noat\""));
9329 if (regno == ILLEGAL_REG)
9336 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9340 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9343 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9346 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9352 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9355 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9356 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9366 if (strncmp (s, "$pc", 3) == 0)
9390 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9392 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9393 and generate the appropriate reloc. If the text
9394 inside %gprel is not a symbol name with an
9395 optional offset, then we generate a normal reloc
9396 and will probably fail later. */
9397 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9398 if (imm_expr.X_op == O_symbol)
9401 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9403 ip->use_extend = TRUE;
9410 /* Just pick up a normal expression. */
9411 my_getExpression (&imm_expr, s);
9414 if (imm_expr.X_op == O_register)
9416 /* What we thought was an expression turned out to
9419 if (s[0] == '(' && args[1] == '(')
9421 /* It looks like the expression was omitted
9422 before a register indirection, which means
9423 that the expression is implicitly zero. We
9424 still set up imm_expr, so that we handle
9425 explicit extensions correctly. */
9426 imm_expr.X_op = O_constant;
9427 imm_expr.X_add_number = 0;
9428 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9435 /* We need to relax this instruction. */
9436 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9445 /* We use offset_reloc rather than imm_reloc for the PC
9446 relative operands. This lets macros with both
9447 immediate and address operands work correctly. */
9448 my_getExpression (&offset_expr, s);
9450 if (offset_expr.X_op == O_register)
9453 /* We need to relax this instruction. */
9454 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9458 case '6': /* break code */
9459 my_getExpression (&imm_expr, s);
9460 check_absolute_expr (ip, &imm_expr);
9461 if ((unsigned long) imm_expr.X_add_number > 63)
9463 as_warn (_("Invalid value for `%s' (%lu)"),
9465 (unsigned long) imm_expr.X_add_number);
9466 imm_expr.X_add_number &= 0x3f;
9468 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9469 imm_expr.X_op = O_absent;
9473 case 'a': /* 26 bit address */
9474 my_getExpression (&offset_expr, s);
9476 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9477 ip->insn_opcode <<= 16;
9480 case 'l': /* register list for entry macro */
9481 case 'L': /* register list for exit macro */
9491 int freg, reg1, reg2;
9493 while (*s == ' ' || *s == ',')
9497 as_bad (_("can't parse register list"));
9509 while (ISDIGIT (*s))
9531 as_bad (_("invalid register list"));
9536 while (ISDIGIT (*s))
9543 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9548 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9553 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9554 mask |= (reg2 - 3) << 3;
9555 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9556 mask |= (reg2 - 15) << 1;
9557 else if (reg1 == RA && reg2 == RA)
9561 as_bad (_("invalid register list"));
9565 /* The mask is filled in in the opcode table for the
9566 benefit of the disassembler. We remove it before
9567 applying the actual mask. */
9568 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9569 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9573 case 'e': /* extend code */
9574 my_getExpression (&imm_expr, s);
9575 check_absolute_expr (ip, &imm_expr);
9576 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9578 as_warn (_("Invalid value for `%s' (%lu)"),
9580 (unsigned long) imm_expr.X_add_number);
9581 imm_expr.X_add_number &= 0x7ff;
9583 ip->insn_opcode |= imm_expr.X_add_number;
9584 imm_expr.X_op = O_absent;
9594 /* Args don't match. */
9595 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9596 strcmp (insn->name, insn[1].name) == 0)
9603 insn_error = _("illegal operands");
9609 /* This structure holds information we know about a mips16 immediate
9612 struct mips16_immed_operand
9614 /* The type code used in the argument string in the opcode table. */
9616 /* The number of bits in the short form of the opcode. */
9618 /* The number of bits in the extended form of the opcode. */
9620 /* The amount by which the short form is shifted when it is used;
9621 for example, the sw instruction has a shift count of 2. */
9623 /* The amount by which the short form is shifted when it is stored
9624 into the instruction code. */
9626 /* Non-zero if the short form is unsigned. */
9628 /* Non-zero if the extended form is unsigned. */
9630 /* Non-zero if the value is PC relative. */
9634 /* The mips16 immediate operand types. */
9636 static const struct mips16_immed_operand mips16_immed_operands[] =
9638 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9639 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9640 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9641 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9642 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9643 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9644 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9645 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9646 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9647 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9648 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9649 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9650 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9651 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9652 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9653 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9654 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9655 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9656 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9657 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9658 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9661 #define MIPS16_NUM_IMMED \
9662 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9664 /* Handle a mips16 instruction with an immediate value. This or's the
9665 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9666 whether an extended value is needed; if one is needed, it sets
9667 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9668 If SMALL is true, an unextended opcode was explicitly requested.
9669 If EXT is true, an extended opcode was explicitly requested. If
9670 WARN is true, warn if EXT does not match reality. */
9673 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9674 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9675 unsigned long *insn, bfd_boolean *use_extend,
9676 unsigned short *extend)
9678 register const struct mips16_immed_operand *op;
9679 int mintiny, maxtiny;
9680 bfd_boolean needext;
9682 op = mips16_immed_operands;
9683 while (op->type != type)
9686 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9691 if (type == '<' || type == '>' || type == '[' || type == ']')
9694 maxtiny = 1 << op->nbits;
9699 maxtiny = (1 << op->nbits) - 1;
9704 mintiny = - (1 << (op->nbits - 1));
9705 maxtiny = (1 << (op->nbits - 1)) - 1;
9708 /* Branch offsets have an implicit 0 in the lowest bit. */
9709 if (type == 'p' || type == 'q')
9712 if ((val & ((1 << op->shift) - 1)) != 0
9713 || val < (mintiny << op->shift)
9714 || val > (maxtiny << op->shift))
9719 if (warn && ext && ! needext)
9720 as_warn_where (file, line,
9721 _("extended operand requested but not required"));
9722 if (small && needext)
9723 as_bad_where (file, line, _("invalid unextended operand value"));
9725 if (small || (! ext && ! needext))
9729 *use_extend = FALSE;
9730 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9731 insnval <<= op->op_shift;
9736 long minext, maxext;
9742 maxext = (1 << op->extbits) - 1;
9746 minext = - (1 << (op->extbits - 1));
9747 maxext = (1 << (op->extbits - 1)) - 1;
9749 if (val < minext || val > maxext)
9750 as_bad_where (file, line,
9751 _("operand value out of range for instruction"));
9754 if (op->extbits == 16)
9756 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9759 else if (op->extbits == 15)
9761 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9766 extval = ((val & 0x1f) << 6) | (val & 0x20);
9770 *extend = (unsigned short) extval;
9775 static const struct percent_op_match
9778 bfd_reloc_code_real_type reloc;
9781 {"%lo", BFD_RELOC_LO16},
9783 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9784 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9785 {"%call16", BFD_RELOC_MIPS_CALL16},
9786 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9787 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9788 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9789 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9790 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9791 {"%got", BFD_RELOC_MIPS_GOT16},
9792 {"%gp_rel", BFD_RELOC_GPREL16},
9793 {"%half", BFD_RELOC_16},
9794 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9795 {"%higher", BFD_RELOC_MIPS_HIGHER},
9796 {"%neg", BFD_RELOC_MIPS_SUB},
9798 {"%hi", BFD_RELOC_HI16_S}
9802 /* Return true if *STR points to a relocation operator. When returning true,
9803 move *STR over the operator and store its relocation code in *RELOC.
9804 Leave both *STR and *RELOC alone when returning false. */
9807 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9811 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9812 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9814 *str += strlen (percent_op[i].str);
9815 *reloc = percent_op[i].reloc;
9817 /* Check whether the output BFD supports this relocation.
9818 If not, issue an error and fall back on something safe. */
9819 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9821 as_bad ("relocation %s isn't supported by the current ABI",
9823 *reloc = BFD_RELOC_UNUSED;
9831 /* Parse string STR as a 16-bit relocatable operand. Store the
9832 expression in *EP and the relocations in the array starting
9833 at RELOC. Return the number of relocation operators used.
9835 On exit, EXPR_END points to the first character after the expression. */
9838 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
9841 bfd_reloc_code_real_type reversed_reloc[3];
9842 size_t reloc_index, i;
9843 int crux_depth, str_depth;
9846 /* Search for the start of the main expression, recoding relocations
9847 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9848 of the main expression and with CRUX_DEPTH containing the number
9849 of open brackets at that point. */
9856 crux_depth = str_depth;
9858 /* Skip over whitespace and brackets, keeping count of the number
9860 while (*str == ' ' || *str == '\t' || *str == '(')
9865 && reloc_index < (HAVE_NEWABI ? 3 : 1)
9866 && parse_relocation (&str, &reversed_reloc[reloc_index]));
9868 my_getExpression (ep, crux);
9871 /* Match every open bracket. */
9872 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
9877 as_bad ("unclosed '('");
9881 if (reloc_index != 0)
9883 prev_reloc_op_frag = frag_now;
9884 for (i = 0; i < reloc_index; i++)
9885 reloc[i] = reversed_reloc[reloc_index - 1 - i];
9892 my_getExpression (expressionS *ep, char *str)
9897 save_in = input_line_pointer;
9898 input_line_pointer = str;
9900 expr_end = input_line_pointer;
9901 input_line_pointer = save_in;
9903 /* If we are in mips16 mode, and this is an expression based on `.',
9904 then we bump the value of the symbol by 1 since that is how other
9905 text symbols are handled. We don't bother to handle complex
9906 expressions, just `.' plus or minus a constant. */
9907 if (mips_opts.mips16
9908 && ep->X_op == O_symbol
9909 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9910 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9911 && symbol_get_frag (ep->X_add_symbol) == frag_now
9912 && symbol_constant_p (ep->X_add_symbol)
9913 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9914 S_SET_VALUE (ep->X_add_symbol, val + 1);
9917 /* Turn a string in input_line_pointer into a floating point constant
9918 of type TYPE, and store the appropriate bytes in *LITP. The number
9919 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9920 returned, or NULL on OK. */
9923 md_atof (int type, char *litP, int *sizeP)
9926 LITTLENUM_TYPE words[4];
9942 return _("bad call to md_atof");
9945 t = atof_ieee (input_line_pointer, type, words);
9947 input_line_pointer = t;
9951 if (! target_big_endian)
9953 for (i = prec - 1; i >= 0; i--)
9955 md_number_to_chars (litP, words[i], 2);
9961 for (i = 0; i < prec; i++)
9963 md_number_to_chars (litP, words[i], 2);
9972 md_number_to_chars (char *buf, valueT val, int n)
9974 if (target_big_endian)
9975 number_to_chars_bigendian (buf, val, n);
9977 number_to_chars_littleendian (buf, val, n);
9981 static int support_64bit_objects(void)
9983 const char **list, **l;
9986 list = bfd_target_list ();
9987 for (l = list; *l != NULL; l++)
9989 /* This is traditional mips */
9990 if (strcmp (*l, "elf64-tradbigmips") == 0
9991 || strcmp (*l, "elf64-tradlittlemips") == 0)
9993 if (strcmp (*l, "elf64-bigmips") == 0
9994 || strcmp (*l, "elf64-littlemips") == 0)
10001 #endif /* OBJ_ELF */
10003 const char *md_shortopts = "O::g::G:";
10005 struct option md_longopts[] =
10007 /* Options which specify architecture. */
10008 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10009 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10010 {"march", required_argument, NULL, OPTION_MARCH},
10011 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10012 {"mtune", required_argument, NULL, OPTION_MTUNE},
10013 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10014 {"mips0", no_argument, NULL, OPTION_MIPS1},
10015 {"mips1", no_argument, NULL, OPTION_MIPS1},
10016 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10017 {"mips2", no_argument, NULL, OPTION_MIPS2},
10018 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10019 {"mips3", no_argument, NULL, OPTION_MIPS3},
10020 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10021 {"mips4", no_argument, NULL, OPTION_MIPS4},
10022 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10023 {"mips5", no_argument, NULL, OPTION_MIPS5},
10024 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10025 {"mips32", no_argument, NULL, OPTION_MIPS32},
10026 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10027 {"mips64", no_argument, NULL, OPTION_MIPS64},
10028 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10029 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10030 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10031 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10033 /* Options which specify Application Specific Extensions (ASEs). */
10034 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10035 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10036 {"mips16", no_argument, NULL, OPTION_MIPS16},
10037 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10038 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10039 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10040 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10041 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10042 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10043 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10044 {"mdmx", no_argument, NULL, OPTION_MDMX},
10045 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10046 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10048 /* Old-style architecture options. Don't add more of these. */
10049 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10050 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10051 {"m4650", no_argument, NULL, OPTION_M4650},
10052 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10053 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10054 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10055 {"m4010", no_argument, NULL, OPTION_M4010},
10056 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10057 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10058 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10059 {"m4100", no_argument, NULL, OPTION_M4100},
10060 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10061 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10062 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10063 {"m3900", no_argument, NULL, OPTION_M3900},
10064 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10065 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10067 /* Options which enable bug fixes. */
10068 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10069 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10070 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10071 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10072 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10073 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10074 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10075 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10076 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10077 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10079 /* Miscellaneous options. */
10080 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10081 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10082 {"trap", no_argument, NULL, OPTION_TRAP},
10083 {"no-break", no_argument, NULL, OPTION_TRAP},
10084 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10085 {"break", no_argument, NULL, OPTION_BREAK},
10086 {"no-trap", no_argument, NULL, OPTION_BREAK},
10087 #define OPTION_EB (OPTION_MISC_BASE + 2)
10088 {"EB", no_argument, NULL, OPTION_EB},
10089 #define OPTION_EL (OPTION_MISC_BASE + 3)
10090 {"EL", no_argument, NULL, OPTION_EL},
10091 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10092 {"mfp32", no_argument, NULL, OPTION_FP32},
10093 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10094 {"mgp32", no_argument, NULL, OPTION_GP32},
10095 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10096 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10097 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10098 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10099 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10100 {"mfp64", no_argument, NULL, OPTION_FP64},
10101 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10102 {"mgp64", no_argument, NULL, OPTION_GP64},
10103 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10104 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10105 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10106 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10108 /* ELF-specific options. */
10110 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10111 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10112 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10113 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10114 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10115 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10116 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10117 {"xgot", no_argument, NULL, OPTION_XGOT},
10118 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10119 {"mabi", required_argument, NULL, OPTION_MABI},
10120 #define OPTION_32 (OPTION_ELF_BASE + 4)
10121 {"32", no_argument, NULL, OPTION_32},
10122 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10123 {"n32", no_argument, NULL, OPTION_N32},
10124 #define OPTION_64 (OPTION_ELF_BASE + 6)
10125 {"64", no_argument, NULL, OPTION_64},
10126 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10127 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10128 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10129 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10130 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10131 {"mpdr", no_argument, NULL, OPTION_PDR},
10132 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10133 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10134 #endif /* OBJ_ELF */
10136 {NULL, no_argument, NULL, 0}
10138 size_t md_longopts_size = sizeof (md_longopts);
10140 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10141 NEW_VALUE. Warn if another value was already specified. Note:
10142 we have to defer parsing the -march and -mtune arguments in order
10143 to handle 'from-abi' correctly, since the ABI might be specified
10144 in a later argument. */
10147 mips_set_option_string (const char **string_ptr, const char *new_value)
10149 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10150 as_warn (_("A different %s was already specified, is now %s"),
10151 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10154 *string_ptr = new_value;
10158 md_parse_option (int c, char *arg)
10162 case OPTION_CONSTRUCT_FLOATS:
10163 mips_disable_float_construction = 0;
10166 case OPTION_NO_CONSTRUCT_FLOATS:
10167 mips_disable_float_construction = 1;
10179 target_big_endian = 1;
10183 target_big_endian = 0;
10187 if (arg && arg[1] == '0')
10197 mips_debug = atoi (arg);
10198 /* When the MIPS assembler sees -g or -g2, it does not do
10199 optimizations which limit full symbolic debugging. We take
10200 that to be equivalent to -O0. */
10201 if (mips_debug == 2)
10206 file_mips_isa = ISA_MIPS1;
10210 file_mips_isa = ISA_MIPS2;
10214 file_mips_isa = ISA_MIPS3;
10218 file_mips_isa = ISA_MIPS4;
10222 file_mips_isa = ISA_MIPS5;
10225 case OPTION_MIPS32:
10226 file_mips_isa = ISA_MIPS32;
10229 case OPTION_MIPS32R2:
10230 file_mips_isa = ISA_MIPS32R2;
10233 case OPTION_MIPS64R2:
10234 file_mips_isa = ISA_MIPS64R2;
10237 case OPTION_MIPS64:
10238 file_mips_isa = ISA_MIPS64;
10242 mips_set_option_string (&mips_tune_string, arg);
10246 mips_set_option_string (&mips_arch_string, arg);
10250 mips_set_option_string (&mips_arch_string, "4650");
10251 mips_set_option_string (&mips_tune_string, "4650");
10254 case OPTION_NO_M4650:
10258 mips_set_option_string (&mips_arch_string, "4010");
10259 mips_set_option_string (&mips_tune_string, "4010");
10262 case OPTION_NO_M4010:
10266 mips_set_option_string (&mips_arch_string, "4100");
10267 mips_set_option_string (&mips_tune_string, "4100");
10270 case OPTION_NO_M4100:
10274 mips_set_option_string (&mips_arch_string, "3900");
10275 mips_set_option_string (&mips_tune_string, "3900");
10278 case OPTION_NO_M3900:
10282 mips_opts.ase_mdmx = 1;
10285 case OPTION_NO_MDMX:
10286 mips_opts.ase_mdmx = 0;
10289 case OPTION_MIPS16:
10290 mips_opts.mips16 = 1;
10291 mips_no_prev_insn (FALSE);
10294 case OPTION_NO_MIPS16:
10295 mips_opts.mips16 = 0;
10296 mips_no_prev_insn (FALSE);
10299 case OPTION_MIPS3D:
10300 mips_opts.ase_mips3d = 1;
10303 case OPTION_NO_MIPS3D:
10304 mips_opts.ase_mips3d = 0;
10307 case OPTION_FIX_VR4120:
10308 mips_fix_vr4120 = 1;
10311 case OPTION_NO_FIX_VR4120:
10312 mips_fix_vr4120 = 0;
10315 case OPTION_RELAX_BRANCH:
10316 mips_relax_branch = 1;
10319 case OPTION_NO_RELAX_BRANCH:
10320 mips_relax_branch = 0;
10324 /* When generating ELF code, we permit -KPIC and -call_shared to
10325 select SVR4_PIC, and -non_shared to select no PIC. This is
10326 intended to be compatible with Irix 5. */
10327 case OPTION_CALL_SHARED:
10328 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10330 as_bad (_("-call_shared is supported only for ELF format"));
10333 mips_pic = SVR4_PIC;
10334 mips_abicalls = TRUE;
10335 if (g_switch_seen && g_switch_value != 0)
10337 as_bad (_("-G may not be used with SVR4 PIC code"));
10340 g_switch_value = 0;
10343 case OPTION_NON_SHARED:
10344 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10346 as_bad (_("-non_shared is supported only for ELF format"));
10350 mips_abicalls = FALSE;
10353 /* The -xgot option tells the assembler to use 32 offsets when
10354 accessing the got in SVR4_PIC mode. It is for Irix
10359 #endif /* OBJ_ELF */
10362 if (mips_pic == SVR4_PIC)
10364 as_bad (_("-G may not be used with SVR4 PIC code"));
10368 g_switch_value = atoi (arg);
10373 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10376 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10378 as_bad (_("-32 is supported for ELF format only"));
10381 mips_abi = O32_ABI;
10385 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10387 as_bad (_("-n32 is supported for ELF format only"));
10390 mips_abi = N32_ABI;
10394 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10396 as_bad (_("-64 is supported for ELF format only"));
10399 mips_abi = N64_ABI;
10400 if (! support_64bit_objects())
10401 as_fatal (_("No compiled in support for 64 bit object file format"));
10403 #endif /* OBJ_ELF */
10406 file_mips_gp32 = 1;
10410 file_mips_gp32 = 0;
10414 file_mips_fp32 = 1;
10418 file_mips_fp32 = 0;
10423 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10425 as_bad (_("-mabi is supported for ELF format only"));
10428 if (strcmp (arg, "32") == 0)
10429 mips_abi = O32_ABI;
10430 else if (strcmp (arg, "o64") == 0)
10431 mips_abi = O64_ABI;
10432 else if (strcmp (arg, "n32") == 0)
10433 mips_abi = N32_ABI;
10434 else if (strcmp (arg, "64") == 0)
10436 mips_abi = N64_ABI;
10437 if (! support_64bit_objects())
10438 as_fatal (_("No compiled in support for 64 bit object file "
10441 else if (strcmp (arg, "eabi") == 0)
10442 mips_abi = EABI_ABI;
10445 as_fatal (_("invalid abi -mabi=%s"), arg);
10449 #endif /* OBJ_ELF */
10451 case OPTION_M7000_HILO_FIX:
10452 mips_7000_hilo_fix = TRUE;
10455 case OPTION_MNO_7000_HILO_FIX:
10456 mips_7000_hilo_fix = FALSE;
10460 case OPTION_MDEBUG:
10461 mips_flag_mdebug = TRUE;
10464 case OPTION_NO_MDEBUG:
10465 mips_flag_mdebug = FALSE;
10469 mips_flag_pdr = TRUE;
10472 case OPTION_NO_PDR:
10473 mips_flag_pdr = FALSE;
10475 #endif /* OBJ_ELF */
10484 /* Set up globals to generate code for the ISA or processor
10485 described by INFO. */
10488 mips_set_architecture (const struct mips_cpu_info *info)
10492 file_mips_arch = info->cpu;
10493 mips_opts.arch = info->cpu;
10494 mips_opts.isa = info->isa;
10499 /* Likewise for tuning. */
10502 mips_set_tune (const struct mips_cpu_info *info)
10505 mips_tune = info->cpu;
10510 mips_after_parse_args (void)
10512 const struct mips_cpu_info *arch_info = 0;
10513 const struct mips_cpu_info *tune_info = 0;
10515 /* GP relative stuff not working for PE */
10516 if (strncmp (TARGET_OS, "pe", 2) == 0
10517 && g_switch_value != 0)
10520 as_bad (_("-G not supported in this configuration."));
10521 g_switch_value = 0;
10524 if (mips_abi == NO_ABI)
10525 mips_abi = MIPS_DEFAULT_ABI;
10527 /* The following code determines the architecture and register size.
10528 Similar code was added to GCC 3.3 (see override_options() in
10529 config/mips/mips.c). The GAS and GCC code should be kept in sync
10530 as much as possible. */
10532 if (mips_arch_string != 0)
10533 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10535 if (file_mips_isa != ISA_UNKNOWN)
10537 /* Handle -mipsN. At this point, file_mips_isa contains the
10538 ISA level specified by -mipsN, while arch_info->isa contains
10539 the -march selection (if any). */
10540 if (arch_info != 0)
10542 /* -march takes precedence over -mipsN, since it is more descriptive.
10543 There's no harm in specifying both as long as the ISA levels
10545 if (file_mips_isa != arch_info->isa)
10546 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10547 mips_cpu_info_from_isa (file_mips_isa)->name,
10548 mips_cpu_info_from_isa (arch_info->isa)->name);
10551 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10554 if (arch_info == 0)
10555 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10557 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10558 as_bad ("-march=%s is not compatible with the selected ABI",
10561 mips_set_architecture (arch_info);
10563 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10564 if (mips_tune_string != 0)
10565 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10567 if (tune_info == 0)
10568 mips_set_tune (arch_info);
10570 mips_set_tune (tune_info);
10572 if (file_mips_gp32 >= 0)
10574 /* The user specified the size of the integer registers. Make sure
10575 it agrees with the ABI and ISA. */
10576 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10577 as_bad (_("-mgp64 used with a 32-bit processor"));
10578 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10579 as_bad (_("-mgp32 used with a 64-bit ABI"));
10580 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10581 as_bad (_("-mgp64 used with a 32-bit ABI"));
10585 /* Infer the integer register size from the ABI and processor.
10586 Restrict ourselves to 32-bit registers if that's all the
10587 processor has, or if the ABI cannot handle 64-bit registers. */
10588 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10589 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10592 /* ??? GAS treats single-float processors as though they had 64-bit
10593 float registers (although it complains when double-precision
10594 instructions are used). As things stand, saying they have 32-bit
10595 registers would lead to spurious "register must be even" messages.
10596 So here we assume float registers are always the same size as
10597 integer ones, unless the user says otherwise. */
10598 if (file_mips_fp32 < 0)
10599 file_mips_fp32 = file_mips_gp32;
10601 /* End of GCC-shared inference code. */
10603 /* This flag is set when we have a 64-bit capable CPU but use only
10604 32-bit wide registers. Note that EABI does not use it. */
10605 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10606 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10607 || mips_abi == O32_ABI))
10608 mips_32bitmode = 1;
10610 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10611 as_bad (_("trap exception not supported at ISA 1"));
10613 /* If the selected architecture includes support for ASEs, enable
10614 generation of code for them. */
10615 if (mips_opts.mips16 == -1)
10616 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10617 if (mips_opts.ase_mips3d == -1)
10618 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10619 if (mips_opts.ase_mdmx == -1)
10620 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10622 file_mips_isa = mips_opts.isa;
10623 file_ase_mips16 = mips_opts.mips16;
10624 file_ase_mips3d = mips_opts.ase_mips3d;
10625 file_ase_mdmx = mips_opts.ase_mdmx;
10626 mips_opts.gp32 = file_mips_gp32;
10627 mips_opts.fp32 = file_mips_fp32;
10629 if (mips_flag_mdebug < 0)
10631 #ifdef OBJ_MAYBE_ECOFF
10632 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10633 mips_flag_mdebug = 1;
10635 #endif /* OBJ_MAYBE_ECOFF */
10636 mips_flag_mdebug = 0;
10641 mips_init_after_args (void)
10643 /* initialize opcodes */
10644 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10645 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10649 md_pcrel_from (fixS *fixP)
10651 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10652 switch (fixP->fx_r_type)
10654 case BFD_RELOC_16_PCREL_S2:
10655 case BFD_RELOC_MIPS_JMP:
10656 /* Return the address of the delay slot. */
10663 /* This is called before the symbol table is processed. In order to
10664 work with gcc when using mips-tfile, we must keep all local labels.
10665 However, in other cases, we want to discard them. If we were
10666 called with -g, but we didn't see any debugging information, it may
10667 mean that gcc is smuggling debugging information through to
10668 mips-tfile, in which case we must generate all local labels. */
10671 mips_frob_file_before_adjust (void)
10673 #ifndef NO_ECOFF_DEBUGGING
10674 if (ECOFF_DEBUGGING
10676 && ! ecoff_debugging_seen)
10677 flag_keep_locals = 1;
10681 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10682 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10683 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10684 relocation operators.
10686 For our purposes, a %lo() expression matches a %got() or %hi()
10689 (a) it refers to the same symbol; and
10690 (b) the offset applied in the %lo() expression is no lower than
10691 the offset applied in the %got() or %hi().
10693 (b) allows us to cope with code like:
10696 lh $4,%lo(foo+2)($4)
10698 ...which is legal on RELA targets, and has a well-defined behaviour
10699 if the user knows that adding 2 to "foo" will not induce a carry to
10702 When several %lo()s match a particular %got() or %hi(), we use the
10703 following rules to distinguish them:
10705 (1) %lo()s with smaller offsets are a better match than %lo()s with
10708 (2) %lo()s with no matching %got() or %hi() are better than those
10709 that already have a matching %got() or %hi().
10711 (3) later %lo()s are better than earlier %lo()s.
10713 These rules are applied in order.
10715 (1) means, among other things, that %lo()s with identical offsets are
10716 chosen if they exist.
10718 (2) means that we won't associate several high-part relocations with
10719 the same low-part relocation unless there's no alternative. Having
10720 several high parts for the same low part is a GNU extension; this rule
10721 allows careful users to avoid it.
10723 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10724 with the last high-part relocation being at the front of the list.
10725 It therefore makes sense to choose the last matching low-part
10726 relocation, all other things being equal. It's also easier
10727 to code that way. */
10730 mips_frob_file (void)
10732 struct mips_hi_fixup *l;
10734 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10736 segment_info_type *seginfo;
10737 bfd_boolean matched_lo_p;
10738 fixS **hi_pos, **lo_pos, **pos;
10740 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10742 /* If a GOT16 relocation turns out to be against a global symbol,
10743 there isn't supposed to be a matching LO. */
10744 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10745 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10748 /* Check quickly whether the next fixup happens to be a matching %lo. */
10749 if (fixup_has_matching_lo_p (l->fixp))
10752 seginfo = seg_info (l->seg);
10754 /* Set HI_POS to the position of this relocation in the chain.
10755 Set LO_POS to the position of the chosen low-part relocation.
10756 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10757 relocation that matches an immediately-preceding high-part
10761 matched_lo_p = FALSE;
10762 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10764 if (*pos == l->fixp)
10767 if ((*pos)->fx_r_type == BFD_RELOC_LO16
10768 && (*pos)->fx_addsy == l->fixp->fx_addsy
10769 && (*pos)->fx_offset >= l->fixp->fx_offset
10771 || (*pos)->fx_offset < (*lo_pos)->fx_offset
10773 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
10776 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
10777 && fixup_has_matching_lo_p (*pos));
10780 /* If we found a match, remove the high-part relocation from its
10781 current position and insert it before the low-part relocation.
10782 Make the offsets match so that fixup_has_matching_lo_p()
10785 We don't warn about unmatched high-part relocations since some
10786 versions of gcc have been known to emit dead "lui ...%hi(...)"
10788 if (lo_pos != NULL)
10790 l->fixp->fx_offset = (*lo_pos)->fx_offset;
10791 if (l->fixp->fx_next != *lo_pos)
10793 *hi_pos = l->fixp->fx_next;
10794 l->fixp->fx_next = *lo_pos;
10801 /* We may have combined relocations without symbols in the N32/N64 ABI.
10802 We have to prevent gas from dropping them. */
10805 mips_force_relocation (fixS *fixp)
10807 if (generic_force_reloc (fixp))
10811 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10812 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10813 || fixp->fx_r_type == BFD_RELOC_HI16_S
10814 || fixp->fx_r_type == BFD_RELOC_LO16))
10820 /* This hook is called before a fix is simplified. We don't really
10821 decide whether to skip a fix here. Rather, we turn global symbols
10822 used as branch targets into local symbols, such that they undergo
10823 simplification. We can only do this if the symbol is defined and
10824 it is in the same section as the branch. If this doesn't hold, we
10825 emit a better error message than just saying the relocation is not
10826 valid for the selected object format.
10828 FIXP is the fix-up we're going to try to simplify, SEG is the
10829 segment in which the fix up occurs. The return value should be
10830 non-zero to indicate the fix-up is valid for further
10831 simplifications. */
10834 mips_validate_fix (struct fix *fixP, asection *seg)
10836 /* There's a lot of discussion on whether it should be possible to
10837 use R_MIPS_PC16 to represent branch relocations. The outcome
10838 seems to be that it can, but gas/bfd are very broken in creating
10839 RELA relocations for this, so for now we only accept branches to
10840 symbols in the same section. Anything else is of dubious value,
10841 since there's no guarantee that at link time the symbol would be
10842 in range. Even for branches to local symbols this is arguably
10843 wrong, since it we assume the symbol is not going to be
10844 overridden, which should be possible per ELF library semantics,
10845 but then, there isn't a dynamic relocation that could be used to
10846 this effect, and the target would likely be out of range as well.
10848 Unfortunately, it seems that there is too much code out there
10849 that relies on branches to symbols that are global to be resolved
10850 as if they were local, like the IRIX tools do, so we do it as
10851 well, but with a warning so that people are reminded to fix their
10852 code. If we ever get back to using R_MIPS_PC16 for branch
10853 targets, this entire block should go away (and probably the
10854 whole function). */
10856 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
10857 && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
10858 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
10859 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
10862 if (! S_IS_DEFINED (fixP->fx_addsy))
10864 as_bad_where (fixP->fx_file, fixP->fx_line,
10865 _("Cannot branch to undefined symbol."));
10866 /* Avoid any further errors about this fixup. */
10869 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
10871 as_bad_where (fixP->fx_file, fixP->fx_line,
10872 _("Cannot branch to symbol in another section."));
10875 else if (S_IS_EXTERNAL (fixP->fx_addsy))
10877 symbolS *sym = fixP->fx_addsy;
10879 if (mips_pic == SVR4_PIC)
10880 as_warn_where (fixP->fx_file, fixP->fx_line,
10881 _("Pretending global symbol used as branch target is local."));
10883 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
10884 S_GET_SEGMENT (sym),
10886 symbol_get_frag (sym));
10887 copy_symbol_attributes (fixP->fx_addsy, sym);
10888 S_CLEAR_EXTERNAL (fixP->fx_addsy);
10889 assert (symbol_resolved_p (sym));
10890 symbol_mark_resolved (fixP->fx_addsy);
10897 /* Apply a fixup to the object file. */
10900 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10904 reloc_howto_type *howto;
10906 /* We ignore generic BFD relocations we don't know about. */
10907 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10911 assert (fixP->fx_size == 4
10912 || fixP->fx_r_type == BFD_RELOC_16
10913 || fixP->fx_r_type == BFD_RELOC_64
10914 || fixP->fx_r_type == BFD_RELOC_CTOR
10915 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10916 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10917 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10919 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
10921 assert (! fixP->fx_pcrel);
10923 /* Don't treat parts of a composite relocation as done. There are two
10926 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10927 should nevertheless be emitted if the first part is.
10929 (2) In normal usage, composite relocations are never assembly-time
10930 constants. The easiest way of dealing with the pathological
10931 exceptions is to generate a relocation against STN_UNDEF and
10932 leave everything up to the linker. */
10933 if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0)
10936 switch (fixP->fx_r_type)
10938 case BFD_RELOC_MIPS_JMP:
10939 case BFD_RELOC_MIPS_SHIFT5:
10940 case BFD_RELOC_MIPS_SHIFT6:
10941 case BFD_RELOC_MIPS_GOT_DISP:
10942 case BFD_RELOC_MIPS_GOT_PAGE:
10943 case BFD_RELOC_MIPS_GOT_OFST:
10944 case BFD_RELOC_MIPS_SUB:
10945 case BFD_RELOC_MIPS_INSERT_A:
10946 case BFD_RELOC_MIPS_INSERT_B:
10947 case BFD_RELOC_MIPS_DELETE:
10948 case BFD_RELOC_MIPS_HIGHEST:
10949 case BFD_RELOC_MIPS_HIGHER:
10950 case BFD_RELOC_MIPS_SCN_DISP:
10951 case BFD_RELOC_MIPS_REL16:
10952 case BFD_RELOC_MIPS_RELGOT:
10953 case BFD_RELOC_MIPS_JALR:
10954 case BFD_RELOC_HI16:
10955 case BFD_RELOC_HI16_S:
10956 case BFD_RELOC_GPREL16:
10957 case BFD_RELOC_MIPS_LITERAL:
10958 case BFD_RELOC_MIPS_CALL16:
10959 case BFD_RELOC_MIPS_GOT16:
10960 case BFD_RELOC_GPREL32:
10961 case BFD_RELOC_MIPS_GOT_HI16:
10962 case BFD_RELOC_MIPS_GOT_LO16:
10963 case BFD_RELOC_MIPS_CALL_HI16:
10964 case BFD_RELOC_MIPS_CALL_LO16:
10965 case BFD_RELOC_MIPS16_GPREL:
10966 assert (! fixP->fx_pcrel);
10967 /* Nothing needed to do. The value comes from the reloc entry */
10970 case BFD_RELOC_MIPS16_JMP:
10971 /* We currently always generate a reloc against a symbol, which
10972 means that we don't want an addend even if the symbol is
10978 /* This is handled like BFD_RELOC_32, but we output a sign
10979 extended value if we are only 32 bits. */
10982 if (8 <= sizeof (valueT))
10983 md_number_to_chars (buf, *valP, 8);
10988 if ((*valP & 0x80000000) != 0)
10992 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
10994 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11000 case BFD_RELOC_RVA:
11002 /* If we are deleting this reloc entry, we must fill in the
11003 value now. This can happen if we have a .word which is not
11004 resolved when it appears but is later defined. */
11006 md_number_to_chars (buf, *valP, 4);
11010 /* If we are deleting this reloc entry, we must fill in the
11013 md_number_to_chars (buf, *valP, 2);
11016 case BFD_RELOC_LO16:
11017 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11018 may be safe to remove, but if so it's not obvious. */
11019 /* When handling an embedded PIC switch statement, we can wind
11020 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11023 if (*valP + 0x8000 > 0xffff)
11024 as_bad_where (fixP->fx_file, fixP->fx_line,
11025 _("relocation overflow"));
11026 if (target_big_endian)
11028 md_number_to_chars (buf, *valP, 2);
11032 case BFD_RELOC_16_PCREL_S2:
11033 if ((*valP & 0x3) != 0)
11034 as_bad_where (fixP->fx_file, fixP->fx_line,
11035 _("Branch to odd address (%lx)"), (long) *valP);
11038 * We need to save the bits in the instruction since fixup_segment()
11039 * might be deleting the relocation entry (i.e., a branch within
11040 * the current segment).
11042 if (! fixP->fx_done)
11045 /* update old instruction data */
11046 if (target_big_endian)
11047 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11049 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11051 if (*valP + 0x20000 <= 0x3ffff)
11053 insn |= (*valP >> 2) & 0xffff;
11054 md_number_to_chars (buf, insn, 4);
11056 else if (mips_pic == NO_PIC
11058 && fixP->fx_frag->fr_address >= text_section->vma
11059 && (fixP->fx_frag->fr_address
11060 < text_section->vma + bfd_get_section_size (text_section))
11061 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11062 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11063 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11065 /* The branch offset is too large. If this is an
11066 unconditional branch, and we are not generating PIC code,
11067 we can convert it to an absolute jump instruction. */
11068 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11069 insn = 0x0c000000; /* jal */
11071 insn = 0x08000000; /* j */
11072 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11074 fixP->fx_addsy = section_symbol (text_section);
11075 *valP += md_pcrel_from (fixP);
11076 md_number_to_chars (buf, insn, 4);
11080 /* If we got here, we have branch-relaxation disabled,
11081 and there's nothing we can do to fix this instruction
11082 without turning it into a longer sequence. */
11083 as_bad_where (fixP->fx_file, fixP->fx_line,
11084 _("Branch out of range"));
11088 case BFD_RELOC_VTABLE_INHERIT:
11091 && !S_IS_DEFINED (fixP->fx_addsy)
11092 && !S_IS_WEAK (fixP->fx_addsy))
11093 S_SET_WEAK (fixP->fx_addsy);
11096 case BFD_RELOC_VTABLE_ENTRY:
11104 /* Remember value for tc_gen_reloc. */
11105 fixP->fx_addnumber = *valP;
11110 printInsn (unsigned long oc)
11112 const struct mips_opcode *p;
11113 int treg, sreg, dreg, shamt;
11118 for (i = 0; i < NUMOPCODES; ++i)
11120 p = &mips_opcodes[i];
11121 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11123 printf ("%08lx %s\t", oc, p->name);
11124 treg = (oc >> 16) & 0x1f;
11125 sreg = (oc >> 21) & 0x1f;
11126 dreg = (oc >> 11) & 0x1f;
11127 shamt = (oc >> 6) & 0x1f;
11129 for (args = p->args;; ++args)
11140 printf ("%c", *args);
11144 assert (treg == sreg);
11145 printf ("$%d,$%d", treg, sreg);
11150 printf ("$%d", dreg);
11155 printf ("$%d", treg);
11159 printf ("0x%x", treg);
11164 printf ("$%d", sreg);
11168 printf ("0x%08lx", oc & 0x1ffffff);
11175 printf ("%d", imm);
11180 printf ("$%d", shamt);
11191 printf (_("%08lx UNDEFINED\n"), oc);
11202 name = input_line_pointer;
11203 c = get_symbol_end ();
11204 p = (symbolS *) symbol_find_or_make (name);
11205 *input_line_pointer = c;
11209 /* Align the current frag to a given power of two. The MIPS assembler
11210 also automatically adjusts any preceding label. */
11213 mips_align (int to, int fill, symbolS *label)
11215 mips_emit_delays (FALSE);
11216 frag_align (to, fill, 0);
11217 record_alignment (now_seg, to);
11220 assert (S_GET_SEGMENT (label) == now_seg);
11221 symbol_set_frag (label, frag_now);
11222 S_SET_VALUE (label, (valueT) frag_now_fix ());
11226 /* Align to a given power of two. .align 0 turns off the automatic
11227 alignment used by the data creating pseudo-ops. */
11230 s_align (int x ATTRIBUTE_UNUSED)
11233 register long temp_fill;
11234 long max_alignment = 15;
11238 o Note that the assembler pulls down any immediately preceding label
11239 to the aligned address.
11240 o It's not documented but auto alignment is reinstated by
11241 a .align pseudo instruction.
11242 o Note also that after auto alignment is turned off the mips assembler
11243 issues an error on attempt to assemble an improperly aligned data item.
11248 temp = get_absolute_expression ();
11249 if (temp > max_alignment)
11250 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11253 as_warn (_("Alignment negative: 0 assumed."));
11256 if (*input_line_pointer == ',')
11258 ++input_line_pointer;
11259 temp_fill = get_absolute_expression ();
11266 mips_align (temp, (int) temp_fill,
11267 insn_labels != NULL ? insn_labels->label : NULL);
11274 demand_empty_rest_of_line ();
11278 mips_flush_pending_output (void)
11280 mips_emit_delays (FALSE);
11281 mips_clear_insn_labels ();
11285 s_change_sec (int sec)
11290 /* The ELF backend needs to know that we are changing sections, so
11291 that .previous works correctly. We could do something like check
11292 for an obj_section_change_hook macro, but that might be confusing
11293 as it would not be appropriate to use it in the section changing
11294 functions in read.c, since obj-elf.c intercepts those. FIXME:
11295 This should be cleaner, somehow. */
11296 obj_elf_section_change_hook ();
11299 mips_emit_delays (FALSE);
11309 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11310 demand_empty_rest_of_line ();
11314 seg = subseg_new (RDATA_SECTION_NAME,
11315 (subsegT) get_absolute_expression ());
11316 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11318 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11319 | SEC_READONLY | SEC_RELOC
11321 if (strcmp (TARGET_OS, "elf") != 0)
11322 record_alignment (seg, 4);
11324 demand_empty_rest_of_line ();
11328 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11329 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11331 bfd_set_section_flags (stdoutput, seg,
11332 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11333 if (strcmp (TARGET_OS, "elf") != 0)
11334 record_alignment (seg, 4);
11336 demand_empty_rest_of_line ();
11344 s_change_section (int ignore ATTRIBUTE_UNUSED)
11347 char *section_name;
11352 int section_entry_size;
11353 int section_alignment;
11355 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11358 section_name = input_line_pointer;
11359 c = get_symbol_end ();
11361 next_c = *(input_line_pointer + 1);
11363 /* Do we have .section Name<,"flags">? */
11364 if (c != ',' || (c == ',' && next_c == '"'))
11366 /* just after name is now '\0'. */
11367 *input_line_pointer = c;
11368 input_line_pointer = section_name;
11369 obj_elf_section (ignore);
11372 input_line_pointer++;
11374 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11376 section_type = get_absolute_expression ();
11379 if (*input_line_pointer++ == ',')
11380 section_flag = get_absolute_expression ();
11383 if (*input_line_pointer++ == ',')
11384 section_entry_size = get_absolute_expression ();
11386 section_entry_size = 0;
11387 if (*input_line_pointer++ == ',')
11388 section_alignment = get_absolute_expression ();
11390 section_alignment = 0;
11392 section_name = xstrdup (section_name);
11394 /* When using the generic form of .section (as implemented by obj-elf.c),
11395 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11396 traditionally had to fall back on the more common @progbits instead.
11398 There's nothing really harmful in this, since bfd will correct
11399 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11400 means that, for backwards compatibiltiy, the special_section entries
11401 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11403 Even so, we shouldn't force users of the MIPS .section syntax to
11404 incorrectly label the sections as SHT_PROGBITS. The best compromise
11405 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11406 generic type-checking code. */
11407 if (section_type == SHT_MIPS_DWARF)
11408 section_type = SHT_PROGBITS;
11410 obj_elf_change_section (section_name, section_type, section_flag,
11411 section_entry_size, 0, 0, 0);
11413 if (now_seg->name != section_name)
11414 free (section_name);
11415 #endif /* OBJ_ELF */
11419 mips_enable_auto_align (void)
11425 s_cons (int log_size)
11429 label = insn_labels != NULL ? insn_labels->label : NULL;
11430 mips_emit_delays (FALSE);
11431 if (log_size > 0 && auto_align)
11432 mips_align (log_size, 0, label);
11433 mips_clear_insn_labels ();
11434 cons (1 << log_size);
11438 s_float_cons (int type)
11442 label = insn_labels != NULL ? insn_labels->label : NULL;
11444 mips_emit_delays (FALSE);
11449 mips_align (3, 0, label);
11451 mips_align (2, 0, label);
11454 mips_clear_insn_labels ();
11459 /* Handle .globl. We need to override it because on Irix 5 you are
11462 where foo is an undefined symbol, to mean that foo should be
11463 considered to be the address of a function. */
11466 s_mips_globl (int x ATTRIBUTE_UNUSED)
11473 name = input_line_pointer;
11474 c = get_symbol_end ();
11475 symbolP = symbol_find_or_make (name);
11476 *input_line_pointer = c;
11477 SKIP_WHITESPACE ();
11479 /* On Irix 5, every global symbol that is not explicitly labelled as
11480 being a function is apparently labelled as being an object. */
11483 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11488 secname = input_line_pointer;
11489 c = get_symbol_end ();
11490 sec = bfd_get_section_by_name (stdoutput, secname);
11492 as_bad (_("%s: no such section"), secname);
11493 *input_line_pointer = c;
11495 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11496 flag = BSF_FUNCTION;
11499 symbol_get_bfdsym (symbolP)->flags |= flag;
11501 S_SET_EXTERNAL (symbolP);
11502 demand_empty_rest_of_line ();
11506 s_option (int x ATTRIBUTE_UNUSED)
11511 opt = input_line_pointer;
11512 c = get_symbol_end ();
11516 /* FIXME: What does this mean? */
11518 else if (strncmp (opt, "pic", 3) == 0)
11522 i = atoi (opt + 3);
11527 mips_pic = SVR4_PIC;
11528 mips_abicalls = TRUE;
11531 as_bad (_(".option pic%d not supported"), i);
11533 if (mips_pic == SVR4_PIC)
11535 if (g_switch_seen && g_switch_value != 0)
11536 as_warn (_("-G may not be used with SVR4 PIC code"));
11537 g_switch_value = 0;
11538 bfd_set_gp_size (stdoutput, 0);
11542 as_warn (_("Unrecognized option \"%s\""), opt);
11544 *input_line_pointer = c;
11545 demand_empty_rest_of_line ();
11548 /* This structure is used to hold a stack of .set values. */
11550 struct mips_option_stack
11552 struct mips_option_stack *next;
11553 struct mips_set_options options;
11556 static struct mips_option_stack *mips_opts_stack;
11558 /* Handle the .set pseudo-op. */
11561 s_mipsset (int x ATTRIBUTE_UNUSED)
11563 char *name = input_line_pointer, ch;
11565 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11566 ++input_line_pointer;
11567 ch = *input_line_pointer;
11568 *input_line_pointer = '\0';
11570 if (strcmp (name, "reorder") == 0)
11572 if (mips_opts.noreorder && prev_nop_frag != NULL)
11574 /* If we still have pending nops, we can discard them. The
11575 usual nop handling will insert any that are still
11577 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11578 * (mips_opts.mips16 ? 2 : 4));
11579 prev_nop_frag = NULL;
11581 mips_opts.noreorder = 0;
11583 else if (strcmp (name, "noreorder") == 0)
11585 mips_emit_delays (TRUE);
11586 mips_opts.noreorder = 1;
11587 mips_any_noreorder = 1;
11589 else if (strcmp (name, "at") == 0)
11591 mips_opts.noat = 0;
11593 else if (strcmp (name, "noat") == 0)
11595 mips_opts.noat = 1;
11597 else if (strcmp (name, "macro") == 0)
11599 mips_opts.warn_about_macros = 0;
11601 else if (strcmp (name, "nomacro") == 0)
11603 if (mips_opts.noreorder == 0)
11604 as_bad (_("`noreorder' must be set before `nomacro'"));
11605 mips_opts.warn_about_macros = 1;
11607 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11609 mips_opts.nomove = 0;
11611 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11613 mips_opts.nomove = 1;
11615 else if (strcmp (name, "bopt") == 0)
11617 mips_opts.nobopt = 0;
11619 else if (strcmp (name, "nobopt") == 0)
11621 mips_opts.nobopt = 1;
11623 else if (strcmp (name, "mips16") == 0
11624 || strcmp (name, "MIPS-16") == 0)
11625 mips_opts.mips16 = 1;
11626 else if (strcmp (name, "nomips16") == 0
11627 || strcmp (name, "noMIPS-16") == 0)
11628 mips_opts.mips16 = 0;
11629 else if (strcmp (name, "mips3d") == 0)
11630 mips_opts.ase_mips3d = 1;
11631 else if (strcmp (name, "nomips3d") == 0)
11632 mips_opts.ase_mips3d = 0;
11633 else if (strcmp (name, "mdmx") == 0)
11634 mips_opts.ase_mdmx = 1;
11635 else if (strcmp (name, "nomdmx") == 0)
11636 mips_opts.ase_mdmx = 0;
11637 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11641 /* Permit the user to change the ISA and architecture on the fly.
11642 Needless to say, misuse can cause serious problems. */
11643 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11646 mips_opts.isa = file_mips_isa;
11647 mips_opts.arch = file_mips_arch;
11649 else if (strncmp (name, "arch=", 5) == 0)
11651 const struct mips_cpu_info *p;
11653 p = mips_parse_cpu("internal use", name + 5);
11655 as_bad (_("unknown architecture %s"), name + 5);
11658 mips_opts.arch = p->cpu;
11659 mips_opts.isa = p->isa;
11662 else if (strncmp (name, "mips", 4) == 0)
11664 const struct mips_cpu_info *p;
11666 p = mips_parse_cpu("internal use", name);
11668 as_bad (_("unknown ISA level %s"), name + 4);
11671 mips_opts.arch = p->cpu;
11672 mips_opts.isa = p->isa;
11676 as_bad (_("unknown ISA or architecture %s"), name);
11678 switch (mips_opts.isa)
11686 mips_opts.gp32 = 1;
11687 mips_opts.fp32 = 1;
11694 mips_opts.gp32 = 0;
11695 mips_opts.fp32 = 0;
11698 as_bad (_("unknown ISA level %s"), name + 4);
11703 mips_opts.gp32 = file_mips_gp32;
11704 mips_opts.fp32 = file_mips_fp32;
11707 else if (strcmp (name, "autoextend") == 0)
11708 mips_opts.noautoextend = 0;
11709 else if (strcmp (name, "noautoextend") == 0)
11710 mips_opts.noautoextend = 1;
11711 else if (strcmp (name, "push") == 0)
11713 struct mips_option_stack *s;
11715 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11716 s->next = mips_opts_stack;
11717 s->options = mips_opts;
11718 mips_opts_stack = s;
11720 else if (strcmp (name, "pop") == 0)
11722 struct mips_option_stack *s;
11724 s = mips_opts_stack;
11726 as_bad (_(".set pop with no .set push"));
11729 /* If we're changing the reorder mode we need to handle
11730 delay slots correctly. */
11731 if (s->options.noreorder && ! mips_opts.noreorder)
11732 mips_emit_delays (TRUE);
11733 else if (! s->options.noreorder && mips_opts.noreorder)
11735 if (prev_nop_frag != NULL)
11737 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11738 * (mips_opts.mips16 ? 2 : 4));
11739 prev_nop_frag = NULL;
11743 mips_opts = s->options;
11744 mips_opts_stack = s->next;
11750 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11752 *input_line_pointer = ch;
11753 demand_empty_rest_of_line ();
11756 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11757 .option pic2. It means to generate SVR4 PIC calls. */
11760 s_abicalls (int ignore ATTRIBUTE_UNUSED)
11762 mips_pic = SVR4_PIC;
11763 mips_abicalls = TRUE;
11765 if (g_switch_seen && g_switch_value != 0)
11766 as_warn (_("-G may not be used with SVR4 PIC code"));
11767 g_switch_value = 0;
11769 bfd_set_gp_size (stdoutput, 0);
11770 demand_empty_rest_of_line ();
11773 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11774 PIC code. It sets the $gp register for the function based on the
11775 function address, which is in the register named in the argument.
11776 This uses a relocation against _gp_disp, which is handled specially
11777 by the linker. The result is:
11778 lui $gp,%hi(_gp_disp)
11779 addiu $gp,$gp,%lo(_gp_disp)
11780 addu $gp,$gp,.cpload argument
11781 The .cpload argument is normally $25 == $t9. */
11784 s_cpload (int ignore ATTRIBUTE_UNUSED)
11788 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11789 .cpload is ignored. */
11790 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11796 /* .cpload should be in a .set noreorder section. */
11797 if (mips_opts.noreorder == 0)
11798 as_warn (_(".cpload not in noreorder section"));
11800 ex.X_op = O_symbol;
11801 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11802 ex.X_op_symbol = NULL;
11803 ex.X_add_number = 0;
11805 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11806 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11809 macro_build_lui (&ex, mips_gp_register);
11810 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11811 mips_gp_register, BFD_RELOC_LO16);
11812 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
11813 mips_gp_register, tc_get_register (0));
11816 demand_empty_rest_of_line ();
11819 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11820 .cpsetup $reg1, offset|$reg2, label
11822 If offset is given, this results in:
11823 sd $gp, offset($sp)
11824 lui $gp, %hi(%neg(%gp_rel(label)))
11825 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11826 daddu $gp, $gp, $reg1
11828 If $reg2 is given, this results in:
11829 daddu $reg2, $gp, $0
11830 lui $gp, %hi(%neg(%gp_rel(label)))
11831 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11832 daddu $gp, $gp, $reg1
11833 $reg1 is normally $25 == $t9. */
11835 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
11837 expressionS ex_off;
11838 expressionS ex_sym;
11842 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11843 We also need NewABI support. */
11844 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11850 reg1 = tc_get_register (0);
11851 SKIP_WHITESPACE ();
11852 if (*input_line_pointer != ',')
11854 as_bad (_("missing argument separator ',' for .cpsetup"));
11858 ++input_line_pointer;
11859 SKIP_WHITESPACE ();
11860 if (*input_line_pointer == '$')
11862 mips_cpreturn_register = tc_get_register (0);
11863 mips_cpreturn_offset = -1;
11867 mips_cpreturn_offset = get_absolute_expression ();
11868 mips_cpreturn_register = -1;
11870 SKIP_WHITESPACE ();
11871 if (*input_line_pointer != ',')
11873 as_bad (_("missing argument separator ',' for .cpsetup"));
11877 ++input_line_pointer;
11878 SKIP_WHITESPACE ();
11879 expression (&ex_sym);
11882 if (mips_cpreturn_register == -1)
11884 ex_off.X_op = O_constant;
11885 ex_off.X_add_symbol = NULL;
11886 ex_off.X_op_symbol = NULL;
11887 ex_off.X_add_number = mips_cpreturn_offset;
11889 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
11890 BFD_RELOC_LO16, SP);
11893 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
11894 mips_gp_register, 0);
11896 /* Ensure there's room for the next two instructions, so that `f'
11897 doesn't end up with an address in the wrong frag. */
11900 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
11901 fix_new (frag_now, f - frag_now->fr_literal,
11902 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11903 fix_new (frag_now, f - frag_now->fr_literal,
11904 4, NULL, 0, 0, BFD_RELOC_HI16_S);
11907 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
11908 mips_gp_register, BFD_RELOC_GPREL16);
11909 fix_new (frag_now, f - frag_now->fr_literal,
11910 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11911 fix_new (frag_now, f - frag_now->fr_literal,
11912 4, NULL, 0, 0, BFD_RELOC_LO16);
11914 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
11915 mips_gp_register, reg1);
11918 demand_empty_rest_of_line ();
11922 s_cplocal (int ignore ATTRIBUTE_UNUSED)
11924 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11925 .cplocal is ignored. */
11926 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11932 mips_gp_register = tc_get_register (0);
11933 demand_empty_rest_of_line ();
11936 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11937 offset from $sp. The offset is remembered, and after making a PIC
11938 call $gp is restored from that location. */
11941 s_cprestore (int ignore ATTRIBUTE_UNUSED)
11945 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11946 .cprestore is ignored. */
11947 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11953 mips_cprestore_offset = get_absolute_expression ();
11954 mips_cprestore_valid = 1;
11956 ex.X_op = O_constant;
11957 ex.X_add_symbol = NULL;
11958 ex.X_op_symbol = NULL;
11959 ex.X_add_number = mips_cprestore_offset;
11962 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
11963 SP, HAVE_64BIT_ADDRESSES);
11966 demand_empty_rest_of_line ();
11969 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11970 was given in the preceding .cpsetup, it results in:
11971 ld $gp, offset($sp)
11973 If a register $reg2 was given there, it results in:
11974 daddu $gp, $reg2, $0
11977 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
11981 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11982 We also need NewABI support. */
11983 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11990 if (mips_cpreturn_register == -1)
11992 ex.X_op = O_constant;
11993 ex.X_add_symbol = NULL;
11994 ex.X_op_symbol = NULL;
11995 ex.X_add_number = mips_cpreturn_offset;
11997 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12000 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12001 mips_cpreturn_register, 0);
12004 demand_empty_rest_of_line ();
12007 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12008 code. It sets the offset to use in gp_rel relocations. */
12011 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12013 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12014 We also need NewABI support. */
12015 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12021 mips_gprel_offset = get_absolute_expression ();
12023 demand_empty_rest_of_line ();
12026 /* Handle the .gpword pseudo-op. This is used when generating PIC
12027 code. It generates a 32 bit GP relative reloc. */
12030 s_gpword (int ignore ATTRIBUTE_UNUSED)
12036 /* When not generating PIC code, this is treated as .word. */
12037 if (mips_pic != SVR4_PIC)
12043 label = insn_labels != NULL ? insn_labels->label : NULL;
12044 mips_emit_delays (TRUE);
12046 mips_align (2, 0, label);
12047 mips_clear_insn_labels ();
12051 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12053 as_bad (_("Unsupported use of .gpword"));
12054 ignore_rest_of_line ();
12058 md_number_to_chars (p, 0, 4);
12059 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12060 BFD_RELOC_GPREL32);
12062 demand_empty_rest_of_line ();
12066 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12072 /* When not generating PIC code, this is treated as .dword. */
12073 if (mips_pic != SVR4_PIC)
12079 label = insn_labels != NULL ? insn_labels->label : NULL;
12080 mips_emit_delays (TRUE);
12082 mips_align (3, 0, label);
12083 mips_clear_insn_labels ();
12087 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12089 as_bad (_("Unsupported use of .gpdword"));
12090 ignore_rest_of_line ();
12094 md_number_to_chars (p, 0, 8);
12095 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12096 BFD_RELOC_GPREL32);
12098 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12099 ex.X_op = O_absent;
12100 ex.X_add_symbol = 0;
12101 ex.X_add_number = 0;
12102 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12105 demand_empty_rest_of_line ();
12108 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12109 tables in SVR4 PIC code. */
12112 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12116 /* This is ignored when not generating SVR4 PIC code. */
12117 if (mips_pic != SVR4_PIC)
12123 /* Add $gp to the register named as an argument. */
12125 reg = tc_get_register (0);
12126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12129 demand_empty_rest_of_line ();
12132 /* Handle the .insn pseudo-op. This marks instruction labels in
12133 mips16 mode. This permits the linker to handle them specially,
12134 such as generating jalx instructions when needed. We also make
12135 them odd for the duration of the assembly, in order to generate the
12136 right sort of code. We will make them even in the adjust_symtab
12137 routine, while leaving them marked. This is convenient for the
12138 debugger and the disassembler. The linker knows to make them odd
12142 s_insn (int ignore ATTRIBUTE_UNUSED)
12144 mips16_mark_labels ();
12146 demand_empty_rest_of_line ();
12149 /* Handle a .stabn directive. We need these in order to mark a label
12150 as being a mips16 text label correctly. Sometimes the compiler
12151 will emit a label, followed by a .stabn, and then switch sections.
12152 If the label and .stabn are in mips16 mode, then the label is
12153 really a mips16 text label. */
12156 s_mips_stab (int type)
12159 mips16_mark_labels ();
12164 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12168 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12175 name = input_line_pointer;
12176 c = get_symbol_end ();
12177 symbolP = symbol_find_or_make (name);
12178 S_SET_WEAK (symbolP);
12179 *input_line_pointer = c;
12181 SKIP_WHITESPACE ();
12183 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12185 if (S_IS_DEFINED (symbolP))
12187 as_bad ("ignoring attempt to redefine symbol %s",
12188 S_GET_NAME (symbolP));
12189 ignore_rest_of_line ();
12193 if (*input_line_pointer == ',')
12195 ++input_line_pointer;
12196 SKIP_WHITESPACE ();
12200 if (exp.X_op != O_symbol)
12202 as_bad ("bad .weakext directive");
12203 ignore_rest_of_line ();
12206 symbol_set_value_expression (symbolP, &exp);
12209 demand_empty_rest_of_line ();
12212 /* Parse a register string into a number. Called from the ECOFF code
12213 to parse .frame. The argument is non-zero if this is the frame
12214 register, so that we can record it in mips_frame_reg. */
12217 tc_get_register (int frame)
12221 SKIP_WHITESPACE ();
12222 if (*input_line_pointer++ != '$')
12224 as_warn (_("expected `$'"));
12227 else if (ISDIGIT (*input_line_pointer))
12229 reg = get_absolute_expression ();
12230 if (reg < 0 || reg >= 32)
12232 as_warn (_("Bad register number"));
12238 if (strncmp (input_line_pointer, "ra", 2) == 0)
12241 input_line_pointer += 2;
12243 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12246 input_line_pointer += 2;
12248 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12251 input_line_pointer += 2;
12253 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12256 input_line_pointer += 2;
12258 else if (strncmp (input_line_pointer, "at", 2) == 0)
12261 input_line_pointer += 2;
12263 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12266 input_line_pointer += 3;
12268 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12271 input_line_pointer += 3;
12273 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12276 input_line_pointer += 4;
12280 as_warn (_("Unrecognized register name"));
12282 while (ISALNUM(*input_line_pointer))
12283 input_line_pointer++;
12288 mips_frame_reg = reg != 0 ? reg : SP;
12289 mips_frame_reg_valid = 1;
12290 mips_cprestore_valid = 0;
12296 md_section_align (asection *seg, valueT addr)
12298 int align = bfd_get_section_alignment (stdoutput, seg);
12301 /* We don't need to align ELF sections to the full alignment.
12302 However, Irix 5 may prefer that we align them at least to a 16
12303 byte boundary. We don't bother to align the sections if we are
12304 targeted for an embedded system. */
12305 if (strcmp (TARGET_OS, "elf") == 0)
12311 return ((addr + (1 << align) - 1) & (-1 << align));
12314 /* Utility routine, called from above as well. If called while the
12315 input file is still being read, it's only an approximation. (For
12316 example, a symbol may later become defined which appeared to be
12317 undefined earlier.) */
12320 nopic_need_relax (symbolS *sym, int before_relaxing)
12325 if (g_switch_value > 0)
12327 const char *symname;
12330 /* Find out whether this symbol can be referenced off the $gp
12331 register. It can be if it is smaller than the -G size or if
12332 it is in the .sdata or .sbss section. Certain symbols can
12333 not be referenced off the $gp, although it appears as though
12335 symname = S_GET_NAME (sym);
12336 if (symname != (const char *) NULL
12337 && (strcmp (symname, "eprol") == 0
12338 || strcmp (symname, "etext") == 0
12339 || strcmp (symname, "_gp") == 0
12340 || strcmp (symname, "edata") == 0
12341 || strcmp (symname, "_fbss") == 0
12342 || strcmp (symname, "_fdata") == 0
12343 || strcmp (symname, "_ftext") == 0
12344 || strcmp (symname, "end") == 0
12345 || strcmp (symname, "_gp_disp") == 0))
12347 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12349 #ifndef NO_ECOFF_DEBUGGING
12350 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12351 && (symbol_get_obj (sym)->ecoff_extern_size
12352 <= g_switch_value))
12354 /* We must defer this decision until after the whole
12355 file has been read, since there might be a .extern
12356 after the first use of this symbol. */
12357 || (before_relaxing
12358 #ifndef NO_ECOFF_DEBUGGING
12359 && symbol_get_obj (sym)->ecoff_extern_size == 0
12361 && S_GET_VALUE (sym) == 0)
12362 || (S_GET_VALUE (sym) != 0
12363 && S_GET_VALUE (sym) <= g_switch_value)))
12367 const char *segname;
12369 segname = segment_name (S_GET_SEGMENT (sym));
12370 assert (strcmp (segname, ".lit8") != 0
12371 && strcmp (segname, ".lit4") != 0);
12372 change = (strcmp (segname, ".sdata") != 0
12373 && strcmp (segname, ".sbss") != 0
12374 && strncmp (segname, ".sdata.", 7) != 0
12375 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12380 /* We are not optimizing for the $gp register. */
12385 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12388 pic_need_relax (symbolS *sym, asection *segtype)
12391 bfd_boolean linkonce;
12393 /* Handle the case of a symbol equated to another symbol. */
12394 while (symbol_equated_reloc_p (sym))
12398 /* It's possible to get a loop here in a badly written
12400 n = symbol_get_value_expression (sym)->X_add_symbol;
12406 symsec = S_GET_SEGMENT (sym);
12408 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12410 if (symsec != segtype && ! S_IS_LOCAL (sym))
12412 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12416 /* The GNU toolchain uses an extension for ELF: a section
12417 beginning with the magic string .gnu.linkonce is a linkonce
12419 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12420 sizeof ".gnu.linkonce" - 1) == 0)
12424 /* This must duplicate the test in adjust_reloc_syms. */
12425 return (symsec != &bfd_und_section
12426 && symsec != &bfd_abs_section
12427 && ! bfd_is_com_section (symsec)
12430 /* A global or weak symbol is treated as external. */
12431 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12432 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12438 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12439 extended opcode. SEC is the section the frag is in. */
12442 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12445 register const struct mips16_immed_operand *op;
12447 int mintiny, maxtiny;
12451 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12453 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12456 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12457 op = mips16_immed_operands;
12458 while (op->type != type)
12461 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12466 if (type == '<' || type == '>' || type == '[' || type == ']')
12469 maxtiny = 1 << op->nbits;
12474 maxtiny = (1 << op->nbits) - 1;
12479 mintiny = - (1 << (op->nbits - 1));
12480 maxtiny = (1 << (op->nbits - 1)) - 1;
12483 sym_frag = symbol_get_frag (fragp->fr_symbol);
12484 val = S_GET_VALUE (fragp->fr_symbol);
12485 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12491 /* We won't have the section when we are called from
12492 mips_relax_frag. However, we will always have been called
12493 from md_estimate_size_before_relax first. If this is a
12494 branch to a different section, we mark it as such. If SEC is
12495 NULL, and the frag is not marked, then it must be a branch to
12496 the same section. */
12499 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12504 /* Must have been called from md_estimate_size_before_relax. */
12507 fragp->fr_subtype =
12508 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12510 /* FIXME: We should support this, and let the linker
12511 catch branches and loads that are out of range. */
12512 as_bad_where (fragp->fr_file, fragp->fr_line,
12513 _("unsupported PC relative reference to different section"));
12517 if (fragp != sym_frag && sym_frag->fr_address == 0)
12518 /* Assume non-extended on the first relaxation pass.
12519 The address we have calculated will be bogus if this is
12520 a forward branch to another frag, as the forward frag
12521 will have fr_address == 0. */
12525 /* In this case, we know for sure that the symbol fragment is in
12526 the same section. If the relax_marker of the symbol fragment
12527 differs from the relax_marker of this fragment, we have not
12528 yet adjusted the symbol fragment fr_address. We want to add
12529 in STRETCH in order to get a better estimate of the address.
12530 This particularly matters because of the shift bits. */
12532 && sym_frag->relax_marker != fragp->relax_marker)
12536 /* Adjust stretch for any alignment frag. Note that if have
12537 been expanding the earlier code, the symbol may be
12538 defined in what appears to be an earlier frag. FIXME:
12539 This doesn't handle the fr_subtype field, which specifies
12540 a maximum number of bytes to skip when doing an
12542 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12544 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12547 stretch = - ((- stretch)
12548 & ~ ((1 << (int) f->fr_offset) - 1));
12550 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12559 addr = fragp->fr_address + fragp->fr_fix;
12561 /* The base address rules are complicated. The base address of
12562 a branch is the following instruction. The base address of a
12563 PC relative load or add is the instruction itself, but if it
12564 is in a delay slot (in which case it can not be extended) use
12565 the address of the instruction whose delay slot it is in. */
12566 if (type == 'p' || type == 'q')
12570 /* If we are currently assuming that this frag should be
12571 extended, then, the current address is two bytes
12573 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12576 /* Ignore the low bit in the target, since it will be set
12577 for a text label. */
12578 if ((val & 1) != 0)
12581 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12583 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12586 val -= addr & ~ ((1 << op->shift) - 1);
12588 /* Branch offsets have an implicit 0 in the lowest bit. */
12589 if (type == 'p' || type == 'q')
12592 /* If any of the shifted bits are set, we must use an extended
12593 opcode. If the address depends on the size of this
12594 instruction, this can lead to a loop, so we arrange to always
12595 use an extended opcode. We only check this when we are in
12596 the main relaxation loop, when SEC is NULL. */
12597 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12599 fragp->fr_subtype =
12600 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12604 /* If we are about to mark a frag as extended because the value
12605 is precisely maxtiny + 1, then there is a chance of an
12606 infinite loop as in the following code:
12611 In this case when the la is extended, foo is 0x3fc bytes
12612 away, so the la can be shrunk, but then foo is 0x400 away, so
12613 the la must be extended. To avoid this loop, we mark the
12614 frag as extended if it was small, and is about to become
12615 extended with a value of maxtiny + 1. */
12616 if (val == ((maxtiny + 1) << op->shift)
12617 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12620 fragp->fr_subtype =
12621 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12625 else if (symsec != absolute_section && sec != NULL)
12626 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12628 if ((val & ((1 << op->shift) - 1)) != 0
12629 || val < (mintiny << op->shift)
12630 || val > (maxtiny << op->shift))
12636 /* Compute the length of a branch sequence, and adjust the
12637 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12638 worst-case length is computed, with UPDATE being used to indicate
12639 whether an unconditional (-1), branch-likely (+1) or regular (0)
12640 branch is to be computed. */
12642 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12644 bfd_boolean toofar;
12648 && S_IS_DEFINED (fragp->fr_symbol)
12649 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12654 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12656 addr = fragp->fr_address + fragp->fr_fix + 4;
12660 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12663 /* If the symbol is not defined or it's in a different segment,
12664 assume the user knows what's going on and emit a short
12670 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12672 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12673 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12674 RELAX_BRANCH_LINK (fragp->fr_subtype),
12680 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12683 if (mips_pic != NO_PIC)
12685 /* Additional space for PIC loading of target address. */
12687 if (mips_opts.isa == ISA_MIPS1)
12688 /* Additional space for $at-stabilizing nop. */
12692 /* If branch is conditional. */
12693 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12700 /* Estimate the size of a frag before relaxing. Unless this is the
12701 mips16, we are not really relaxing here, and the final size is
12702 encoded in the subtype information. For the mips16, we have to
12703 decide whether we are using an extended opcode or not. */
12706 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12710 if (RELAX_BRANCH_P (fragp->fr_subtype))
12713 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12715 return fragp->fr_var;
12718 if (RELAX_MIPS16_P (fragp->fr_subtype))
12719 /* We don't want to modify the EXTENDED bit here; it might get us
12720 into infinite loops. We change it only in mips_relax_frag(). */
12721 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12723 if (mips_pic == NO_PIC)
12724 change = nopic_need_relax (fragp->fr_symbol, 0);
12725 else if (mips_pic == SVR4_PIC)
12726 change = pic_need_relax (fragp->fr_symbol, segtype);
12732 fragp->fr_subtype |= RELAX_USE_SECOND;
12733 return -RELAX_FIRST (fragp->fr_subtype);
12736 return -RELAX_SECOND (fragp->fr_subtype);
12739 /* This is called to see whether a reloc against a defined symbol
12740 should be converted into a reloc against a section. */
12743 mips_fix_adjustable (fixS *fixp)
12745 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12746 about the format of the offset in the .o file. */
12747 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12750 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12751 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12754 if (fixp->fx_addsy == NULL)
12757 /* If symbol SYM is in a mergeable section, relocations of the form
12758 SYM + 0 can usually be made section-relative. The mergeable data
12759 is then identified by the section offset rather than by the symbol.
12761 However, if we're generating REL LO16 relocations, the offset is split
12762 between the LO16 and parterning high part relocation. The linker will
12763 need to recalculate the complete offset in order to correctly identify
12766 The linker has traditionally not looked for the parterning high part
12767 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12768 placed anywhere. Rather than break backwards compatibility by changing
12769 this, it seems better not to force the issue, and instead keep the
12770 original symbol. This will work with either linker behavior. */
12771 if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
12772 && HAVE_IN_PLACE_ADDENDS
12773 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
12777 /* Don't adjust relocations against mips16 symbols, so that the linker
12778 can find them if it needs to set up a stub. */
12779 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12780 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12781 && fixp->fx_subsy == NULL)
12788 /* Translate internal representation of relocation info to BFD target
12792 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12794 static arelent *retval[4];
12796 bfd_reloc_code_real_type code;
12798 memset (retval, 0, sizeof(retval));
12799 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
12800 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12801 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12802 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12804 assert (! fixp->fx_pcrel);
12805 reloc->addend = fixp->fx_addnumber;
12807 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12808 entry to be used in the relocation's section offset. */
12809 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12811 reloc->address = reloc->addend;
12815 code = fixp->fx_r_type;
12817 /* To support a PC relative reloc, we used a Cygnus extension.
12818 We check for that here to make sure that we don't let such a
12819 reloc escape normally. (FIXME: This was formerly used by
12820 embedded-PIC support, but is now used by branch handling in
12821 general. That probably should be fixed.) */
12822 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12823 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12824 && code == BFD_RELOC_16_PCREL_S2)
12825 reloc->howto = NULL;
12827 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12829 if (reloc->howto == NULL)
12831 as_bad_where (fixp->fx_file, fixp->fx_line,
12832 _("Can not represent %s relocation in this object file format"),
12833 bfd_get_reloc_code_name (code));
12840 /* Relax a machine dependent frag. This returns the amount by which
12841 the current size of the frag should change. */
12844 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
12846 if (RELAX_BRANCH_P (fragp->fr_subtype))
12848 offsetT old_var = fragp->fr_var;
12850 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
12852 return fragp->fr_var - old_var;
12855 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12858 if (mips16_extended_frag (fragp, NULL, stretch))
12860 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12862 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12867 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12869 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12876 /* Convert a machine dependent frag. */
12879 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
12881 if (RELAX_BRANCH_P (fragp->fr_subtype))
12884 unsigned long insn;
12888 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
12890 if (target_big_endian)
12891 insn = bfd_getb32 (buf);
12893 insn = bfd_getl32 (buf);
12895 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12897 /* We generate a fixup instead of applying it right now
12898 because, if there are linker relaxations, we're going to
12899 need the relocations. */
12900 exp.X_op = O_symbol;
12901 exp.X_add_symbol = fragp->fr_symbol;
12902 exp.X_add_number = fragp->fr_offset;
12904 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
12906 BFD_RELOC_16_PCREL_S2);
12907 fixp->fx_file = fragp->fr_file;
12908 fixp->fx_line = fragp->fr_line;
12910 md_number_to_chars (buf, insn, 4);
12917 as_warn_where (fragp->fr_file, fragp->fr_line,
12918 _("relaxed out-of-range branch into a jump"));
12920 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
12923 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12925 /* Reverse the branch. */
12926 switch ((insn >> 28) & 0xf)
12929 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12930 have the condition reversed by tweaking a single
12931 bit, and their opcodes all have 0x4???????. */
12932 assert ((insn & 0xf1000000) == 0x41000000);
12933 insn ^= 0x00010000;
12937 /* bltz 0x04000000 bgez 0x04010000
12938 bltzal 0x04100000 bgezal 0x04110000 */
12939 assert ((insn & 0xfc0e0000) == 0x04000000);
12940 insn ^= 0x00010000;
12944 /* beq 0x10000000 bne 0x14000000
12945 blez 0x18000000 bgtz 0x1c000000 */
12946 insn ^= 0x04000000;
12954 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
12956 /* Clear the and-link bit. */
12957 assert ((insn & 0xfc1c0000) == 0x04100000);
12959 /* bltzal 0x04100000 bgezal 0x04110000
12960 bltzall 0x04120000 bgezall 0x04130000 */
12961 insn &= ~0x00100000;
12964 /* Branch over the branch (if the branch was likely) or the
12965 full jump (not likely case). Compute the offset from the
12966 current instruction to branch to. */
12967 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12971 /* How many bytes in instructions we've already emitted? */
12972 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12973 /* How many bytes in instructions from here to the end? */
12974 i = fragp->fr_var - i;
12976 /* Convert to instruction count. */
12978 /* Branch counts from the next instruction. */
12981 /* Branch over the jump. */
12982 md_number_to_chars (buf, insn, 4);
12986 md_number_to_chars (buf, 0, 4);
12989 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12991 /* beql $0, $0, 2f */
12993 /* Compute the PC offset from the current instruction to
12994 the end of the variable frag. */
12995 /* How many bytes in instructions we've already emitted? */
12996 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12997 /* How many bytes in instructions from here to the end? */
12998 i = fragp->fr_var - i;
12999 /* Convert to instruction count. */
13001 /* Don't decrement i, because we want to branch over the
13005 md_number_to_chars (buf, insn, 4);
13008 md_number_to_chars (buf, 0, 4);
13013 if (mips_pic == NO_PIC)
13016 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13017 ? 0x0c000000 : 0x08000000);
13018 exp.X_op = O_symbol;
13019 exp.X_add_symbol = fragp->fr_symbol;
13020 exp.X_add_number = fragp->fr_offset;
13022 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13023 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13024 fixp->fx_file = fragp->fr_file;
13025 fixp->fx_line = fragp->fr_line;
13027 md_number_to_chars (buf, insn, 4);
13032 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13033 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13034 exp.X_op = O_symbol;
13035 exp.X_add_symbol = fragp->fr_symbol;
13036 exp.X_add_number = fragp->fr_offset;
13038 if (fragp->fr_offset)
13040 exp.X_add_symbol = make_expr_symbol (&exp);
13041 exp.X_add_number = 0;
13044 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13045 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13046 fixp->fx_file = fragp->fr_file;
13047 fixp->fx_line = fragp->fr_line;
13049 md_number_to_chars (buf, insn, 4);
13052 if (mips_opts.isa == ISA_MIPS1)
13055 md_number_to_chars (buf, 0, 4);
13059 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13060 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13062 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13063 4, &exp, 0, BFD_RELOC_LO16);
13064 fixp->fx_file = fragp->fr_file;
13065 fixp->fx_line = fragp->fr_line;
13067 md_number_to_chars (buf, insn, 4);
13071 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13076 md_number_to_chars (buf, insn, 4);
13081 assert (buf == (bfd_byte *)fragp->fr_literal
13082 + fragp->fr_fix + fragp->fr_var);
13084 fragp->fr_fix += fragp->fr_var;
13089 if (RELAX_MIPS16_P (fragp->fr_subtype))
13092 register const struct mips16_immed_operand *op;
13093 bfd_boolean small, ext;
13096 unsigned long insn;
13097 bfd_boolean use_extend;
13098 unsigned short extend;
13100 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13101 op = mips16_immed_operands;
13102 while (op->type != type)
13105 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13116 resolve_symbol_value (fragp->fr_symbol);
13117 val = S_GET_VALUE (fragp->fr_symbol);
13122 addr = fragp->fr_address + fragp->fr_fix;
13124 /* The rules for the base address of a PC relative reloc are
13125 complicated; see mips16_extended_frag. */
13126 if (type == 'p' || type == 'q')
13131 /* Ignore the low bit in the target, since it will be
13132 set for a text label. */
13133 if ((val & 1) != 0)
13136 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13138 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13141 addr &= ~ (addressT) ((1 << op->shift) - 1);
13144 /* Make sure the section winds up with the alignment we have
13147 record_alignment (asec, op->shift);
13151 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13152 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13153 as_warn_where (fragp->fr_file, fragp->fr_line,
13154 _("extended instruction in delay slot"));
13156 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13158 if (target_big_endian)
13159 insn = bfd_getb16 (buf);
13161 insn = bfd_getl16 (buf);
13163 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13164 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13165 small, ext, &insn, &use_extend, &extend);
13169 md_number_to_chars (buf, 0xf000 | extend, 2);
13170 fragp->fr_fix += 2;
13174 md_number_to_chars (buf, insn, 2);
13175 fragp->fr_fix += 2;
13183 first = RELAX_FIRST (fragp->fr_subtype);
13184 second = RELAX_SECOND (fragp->fr_subtype);
13185 fixp = (fixS *) fragp->fr_opcode;
13187 /* Possibly emit a warning if we've chosen the longer option. */
13188 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13189 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13191 const char *msg = macro_warning (fragp->fr_subtype);
13193 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13196 /* Go through all the fixups for the first sequence. Disable them
13197 (by marking them as done) if we're going to use the second
13198 sequence instead. */
13200 && fixp->fx_frag == fragp
13201 && fixp->fx_where < fragp->fr_fix - second)
13203 if (fragp->fr_subtype & RELAX_USE_SECOND)
13205 fixp = fixp->fx_next;
13208 /* Go through the fixups for the second sequence. Disable them if
13209 we're going to use the first sequence, otherwise adjust their
13210 addresses to account for the relaxation. */
13211 while (fixp && fixp->fx_frag == fragp)
13213 if (fragp->fr_subtype & RELAX_USE_SECOND)
13214 fixp->fx_where -= first;
13217 fixp = fixp->fx_next;
13220 /* Now modify the frag contents. */
13221 if (fragp->fr_subtype & RELAX_USE_SECOND)
13225 start = fragp->fr_literal + fragp->fr_fix - first - second;
13226 memmove (start, start + first, second);
13227 fragp->fr_fix -= first;
13230 fragp->fr_fix -= second;
13236 /* This function is called after the relocs have been generated.
13237 We've been storing mips16 text labels as odd. Here we convert them
13238 back to even for the convenience of the debugger. */
13241 mips_frob_file_after_relocs (void)
13244 unsigned int count, i;
13246 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13249 syms = bfd_get_outsymbols (stdoutput);
13250 count = bfd_get_symcount (stdoutput);
13251 for (i = 0; i < count; i++, syms++)
13253 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13254 && ((*syms)->value & 1) != 0)
13256 (*syms)->value &= ~1;
13257 /* If the symbol has an odd size, it was probably computed
13258 incorrectly, so adjust that as well. */
13259 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13260 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13267 /* This function is called whenever a label is defined. It is used
13268 when handling branch delays; if a branch has a label, we assume we
13269 can not move it. */
13272 mips_define_label (symbolS *sym)
13274 struct insn_label_list *l;
13276 if (free_insn_labels == NULL)
13277 l = (struct insn_label_list *) xmalloc (sizeof *l);
13280 l = free_insn_labels;
13281 free_insn_labels = l->next;
13285 l->next = insn_labels;
13289 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13291 /* Some special processing for a MIPS ELF file. */
13294 mips_elf_final_processing (void)
13296 /* Write out the register information. */
13297 if (mips_abi != N64_ABI)
13301 s.ri_gprmask = mips_gprmask;
13302 s.ri_cprmask[0] = mips_cprmask[0];
13303 s.ri_cprmask[1] = mips_cprmask[1];
13304 s.ri_cprmask[2] = mips_cprmask[2];
13305 s.ri_cprmask[3] = mips_cprmask[3];
13306 /* The gp_value field is set by the MIPS ELF backend. */
13308 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13309 ((Elf32_External_RegInfo *)
13310 mips_regmask_frag));
13314 Elf64_Internal_RegInfo s;
13316 s.ri_gprmask = mips_gprmask;
13318 s.ri_cprmask[0] = mips_cprmask[0];
13319 s.ri_cprmask[1] = mips_cprmask[1];
13320 s.ri_cprmask[2] = mips_cprmask[2];
13321 s.ri_cprmask[3] = mips_cprmask[3];
13322 /* The gp_value field is set by the MIPS ELF backend. */
13324 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13325 ((Elf64_External_RegInfo *)
13326 mips_regmask_frag));
13329 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13330 sort of BFD interface for this. */
13331 if (mips_any_noreorder)
13332 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13333 if (mips_pic != NO_PIC)
13335 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13336 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13339 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13341 /* Set MIPS ELF flags for ASEs. */
13342 if (file_ase_mips16)
13343 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13344 #if 0 /* XXX FIXME */
13345 if (file_ase_mips3d)
13346 elf_elfheader (stdoutput)->e_flags |= ???;
13349 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13351 /* Set the MIPS ELF ABI flags. */
13352 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13353 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13354 else if (mips_abi == O64_ABI)
13355 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13356 else if (mips_abi == EABI_ABI)
13358 if (!file_mips_gp32)
13359 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13361 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13363 else if (mips_abi == N32_ABI)
13364 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13366 /* Nothing to do for N64_ABI. */
13368 if (mips_32bitmode)
13369 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13372 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13374 typedef struct proc {
13376 unsigned long reg_mask;
13377 unsigned long reg_offset;
13378 unsigned long fpreg_mask;
13379 unsigned long fpreg_offset;
13380 unsigned long frame_offset;
13381 unsigned long frame_reg;
13382 unsigned long pc_reg;
13385 static procS cur_proc;
13386 static procS *cur_proc_ptr;
13387 static int numprocs;
13389 /* Fill in an rs_align_code fragment. */
13392 mips_handle_align (fragS *fragp)
13394 if (fragp->fr_type != rs_align_code)
13397 if (mips_opts.mips16)
13399 static const unsigned char be_nop[] = { 0x65, 0x00 };
13400 static const unsigned char le_nop[] = { 0x00, 0x65 };
13405 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13406 p = fragp->fr_literal + fragp->fr_fix;
13414 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13418 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13422 md_obj_begin (void)
13429 /* check for premature end, nesting errors, etc */
13431 as_warn (_("missing .end at end of assembly"));
13440 if (*input_line_pointer == '-')
13442 ++input_line_pointer;
13445 if (!ISDIGIT (*input_line_pointer))
13446 as_bad (_("expected simple number"));
13447 if (input_line_pointer[0] == '0')
13449 if (input_line_pointer[1] == 'x')
13451 input_line_pointer += 2;
13452 while (ISXDIGIT (*input_line_pointer))
13455 val |= hex_value (*input_line_pointer++);
13457 return negative ? -val : val;
13461 ++input_line_pointer;
13462 while (ISDIGIT (*input_line_pointer))
13465 val |= *input_line_pointer++ - '0';
13467 return negative ? -val : val;
13470 if (!ISDIGIT (*input_line_pointer))
13472 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13473 *input_line_pointer, *input_line_pointer);
13474 as_warn (_("invalid number"));
13477 while (ISDIGIT (*input_line_pointer))
13480 val += *input_line_pointer++ - '0';
13482 return negative ? -val : val;
13485 /* The .file directive; just like the usual .file directive, but there
13486 is an initial number which is the ECOFF file index. In the non-ECOFF
13487 case .file implies DWARF-2. */
13490 s_mips_file (int x ATTRIBUTE_UNUSED)
13492 static int first_file_directive = 0;
13494 if (ECOFF_DEBUGGING)
13503 filename = dwarf2_directive_file (0);
13505 /* Versions of GCC up to 3.1 start files with a ".file"
13506 directive even for stabs output. Make sure that this
13507 ".file" is handled. Note that you need a version of GCC
13508 after 3.1 in order to support DWARF-2 on MIPS. */
13509 if (filename != NULL && ! first_file_directive)
13511 (void) new_logical_line (filename, -1);
13512 s_app_file_string (filename);
13514 first_file_directive = 1;
13518 /* The .loc directive, implying DWARF-2. */
13521 s_mips_loc (int x ATTRIBUTE_UNUSED)
13523 if (!ECOFF_DEBUGGING)
13524 dwarf2_directive_loc (0);
13527 /* The .end directive. */
13530 s_mips_end (int x ATTRIBUTE_UNUSED)
13534 /* Following functions need their own .frame and .cprestore directives. */
13535 mips_frame_reg_valid = 0;
13536 mips_cprestore_valid = 0;
13538 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13541 demand_empty_rest_of_line ();
13546 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13547 as_warn (_(".end not in text section"));
13551 as_warn (_(".end directive without a preceding .ent directive."));
13552 demand_empty_rest_of_line ();
13558 assert (S_GET_NAME (p));
13559 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13560 as_warn (_(".end symbol does not match .ent symbol."));
13562 if (debug_type == DEBUG_STABS)
13563 stabs_generate_asm_endfunc (S_GET_NAME (p),
13567 as_warn (_(".end directive missing or unknown symbol"));
13570 /* Generate a .pdr section. */
13571 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13574 segT saved_seg = now_seg;
13575 subsegT saved_subseg = now_subseg;
13580 dot = frag_now_fix ();
13582 #ifdef md_flush_pending_output
13583 md_flush_pending_output ();
13587 subseg_set (pdr_seg, 0);
13589 /* Write the symbol. */
13590 exp.X_op = O_symbol;
13591 exp.X_add_symbol = p;
13592 exp.X_add_number = 0;
13593 emit_expr (&exp, 4);
13595 fragp = frag_more (7 * 4);
13597 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13598 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13599 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13600 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13601 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13602 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13603 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13605 subseg_set (saved_seg, saved_subseg);
13607 #endif /* OBJ_ELF */
13609 cur_proc_ptr = NULL;
13612 /* The .aent and .ent directives. */
13615 s_mips_ent (int aent)
13619 symbolP = get_symbol ();
13620 if (*input_line_pointer == ',')
13621 ++input_line_pointer;
13622 SKIP_WHITESPACE ();
13623 if (ISDIGIT (*input_line_pointer)
13624 || *input_line_pointer == '-')
13627 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13628 as_warn (_(".ent or .aent not in text section."));
13630 if (!aent && cur_proc_ptr)
13631 as_warn (_("missing .end"));
13635 /* This function needs its own .frame and .cprestore directives. */
13636 mips_frame_reg_valid = 0;
13637 mips_cprestore_valid = 0;
13639 cur_proc_ptr = &cur_proc;
13640 memset (cur_proc_ptr, '\0', sizeof (procS));
13642 cur_proc_ptr->isym = symbolP;
13644 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13648 if (debug_type == DEBUG_STABS)
13649 stabs_generate_asm_func (S_GET_NAME (symbolP),
13650 S_GET_NAME (symbolP));
13653 demand_empty_rest_of_line ();
13656 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13657 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13658 s_mips_frame is used so that we can set the PDR information correctly.
13659 We can't use the ecoff routines because they make reference to the ecoff
13660 symbol table (in the mdebug section). */
13663 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13666 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13670 if (cur_proc_ptr == (procS *) NULL)
13672 as_warn (_(".frame outside of .ent"));
13673 demand_empty_rest_of_line ();
13677 cur_proc_ptr->frame_reg = tc_get_register (1);
13679 SKIP_WHITESPACE ();
13680 if (*input_line_pointer++ != ','
13681 || get_absolute_expression_and_terminator (&val) != ',')
13683 as_warn (_("Bad .frame directive"));
13684 --input_line_pointer;
13685 demand_empty_rest_of_line ();
13689 cur_proc_ptr->frame_offset = val;
13690 cur_proc_ptr->pc_reg = tc_get_register (0);
13692 demand_empty_rest_of_line ();
13695 #endif /* OBJ_ELF */
13699 /* The .fmask and .mask directives. If the mdebug section is present
13700 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13701 embedded targets, s_mips_mask is used so that we can set the PDR
13702 information correctly. We can't use the ecoff routines because they
13703 make reference to the ecoff symbol table (in the mdebug section). */
13706 s_mips_mask (int reg_type)
13709 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13713 if (cur_proc_ptr == (procS *) NULL)
13715 as_warn (_(".mask/.fmask outside of .ent"));
13716 demand_empty_rest_of_line ();
13720 if (get_absolute_expression_and_terminator (&mask) != ',')
13722 as_warn (_("Bad .mask/.fmask directive"));
13723 --input_line_pointer;
13724 demand_empty_rest_of_line ();
13728 off = get_absolute_expression ();
13730 if (reg_type == 'F')
13732 cur_proc_ptr->fpreg_mask = mask;
13733 cur_proc_ptr->fpreg_offset = off;
13737 cur_proc_ptr->reg_mask = mask;
13738 cur_proc_ptr->reg_offset = off;
13741 demand_empty_rest_of_line ();
13744 #endif /* OBJ_ELF */
13745 s_ignore (reg_type);
13748 /* The .loc directive. */
13758 assert (now_seg == text_section);
13760 lineno = get_number ();
13761 addroff = frag_now_fix ();
13763 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13764 S_SET_TYPE (symbolP, N_SLINE);
13765 S_SET_OTHER (symbolP, 0);
13766 S_SET_DESC (symbolP, lineno);
13767 symbolP->sy_segment = now_seg;
13771 /* A table describing all the processors gas knows about. Names are
13772 matched in the order listed.
13774 To ease comparison, please keep this table in the same order as
13775 gcc's mips_cpu_info_table[]. */
13776 static const struct mips_cpu_info mips_cpu_info_table[] =
13778 /* Entries for generic ISAs */
13779 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13780 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13781 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13782 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13783 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13784 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13785 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
13786 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13787 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
13790 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13791 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13792 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13795 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13798 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13799 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13800 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13801 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13802 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
13803 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
13804 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
13805 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13806 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13807 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13808 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13809 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13812 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13813 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13814 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13815 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13816 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
13817 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
13818 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13819 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13820 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13821 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13822 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13823 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
13824 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
13827 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
13828 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13829 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13832 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13833 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13835 /* Broadcom SB-1 CPU core */
13836 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13843 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13844 with a final "000" replaced by "k". Ignore case.
13846 Note: this function is shared between GCC and GAS. */
13849 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13851 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13852 given++, canonical++;
13854 return ((*given == 0 && *canonical == 0)
13855 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13859 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13860 CPU name. We've traditionally allowed a lot of variation here.
13862 Note: this function is shared between GCC and GAS. */
13865 mips_matching_cpu_name_p (const char *canonical, const char *given)
13867 /* First see if the name matches exactly, or with a final "000"
13868 turned into "k". */
13869 if (mips_strict_matching_cpu_name_p (canonical, given))
13872 /* If not, try comparing based on numerical designation alone.
13873 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13874 if (TOLOWER (*given) == 'r')
13876 if (!ISDIGIT (*given))
13879 /* Skip over some well-known prefixes in the canonical name,
13880 hoping to find a number there too. */
13881 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13883 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13885 else if (TOLOWER (canonical[0]) == 'r')
13888 return mips_strict_matching_cpu_name_p (canonical, given);
13892 /* Parse an option that takes the name of a processor as its argument.
13893 OPTION is the name of the option and CPU_STRING is the argument.
13894 Return the corresponding processor enumeration if the CPU_STRING is
13895 recognized, otherwise report an error and return null.
13897 A similar function exists in GCC. */
13899 static const struct mips_cpu_info *
13900 mips_parse_cpu (const char *option, const char *cpu_string)
13902 const struct mips_cpu_info *p;
13904 /* 'from-abi' selects the most compatible architecture for the given
13905 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13906 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13907 version. Look first at the -mgp options, if given, otherwise base
13908 the choice on MIPS_DEFAULT_64BIT.
13910 Treat NO_ABI like the EABIs. One reason to do this is that the
13911 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13912 architecture. This code picks MIPS I for 'mips' and MIPS III for
13913 'mips64', just as we did in the days before 'from-abi'. */
13914 if (strcasecmp (cpu_string, "from-abi") == 0)
13916 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13917 return mips_cpu_info_from_isa (ISA_MIPS1);
13919 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13920 return mips_cpu_info_from_isa (ISA_MIPS3);
13922 if (file_mips_gp32 >= 0)
13923 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13925 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13930 /* 'default' has traditionally been a no-op. Probably not very useful. */
13931 if (strcasecmp (cpu_string, "default") == 0)
13934 for (p = mips_cpu_info_table; p->name != 0; p++)
13935 if (mips_matching_cpu_name_p (p->name, cpu_string))
13938 as_bad ("Bad value (%s) for %s", cpu_string, option);
13942 /* Return the canonical processor information for ISA (a member of the
13943 ISA_MIPS* enumeration). */
13945 static const struct mips_cpu_info *
13946 mips_cpu_info_from_isa (int isa)
13950 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13951 if (mips_cpu_info_table[i].is_isa
13952 && isa == mips_cpu_info_table[i].isa)
13953 return (&mips_cpu_info_table[i]);
13958 static const struct mips_cpu_info *
13959 mips_cpu_info_from_arch (int arch)
13963 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13964 if (arch == mips_cpu_info_table[i].cpu)
13965 return (&mips_cpu_info_table[i]);
13971 show (FILE *stream, const char *string, int *col_p, int *first_p)
13975 fprintf (stream, "%24s", "");
13980 fprintf (stream, ", ");
13984 if (*col_p + strlen (string) > 72)
13986 fprintf (stream, "\n%24s", "");
13990 fprintf (stream, "%s", string);
13991 *col_p += strlen (string);
13997 md_show_usage (FILE *stream)
14002 fprintf (stream, _("\
14004 -EB generate big endian output\n\
14005 -EL generate little endian output\n\
14006 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14007 -G NUM allow referencing objects up to NUM bytes\n\
14008 implicitly with the gp register [default 8]\n"));
14009 fprintf (stream, _("\
14010 -mips1 generate MIPS ISA I instructions\n\
14011 -mips2 generate MIPS ISA II instructions\n\
14012 -mips3 generate MIPS ISA III instructions\n\
14013 -mips4 generate MIPS ISA IV instructions\n\
14014 -mips5 generate MIPS ISA V instructions\n\
14015 -mips32 generate MIPS32 ISA instructions\n\
14016 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14017 -mips64 generate MIPS64 ISA instructions\n\
14018 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14019 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14023 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14024 show (stream, mips_cpu_info_table[i].name, &column, &first);
14025 show (stream, "from-abi", &column, &first);
14026 fputc ('\n', stream);
14028 fprintf (stream, _("\
14029 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14030 -no-mCPU don't generate code specific to CPU.\n\
14031 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14035 show (stream, "3900", &column, &first);
14036 show (stream, "4010", &column, &first);
14037 show (stream, "4100", &column, &first);
14038 show (stream, "4650", &column, &first);
14039 fputc ('\n', stream);
14041 fprintf (stream, _("\
14042 -mips16 generate mips16 instructions\n\
14043 -no-mips16 do not generate mips16 instructions\n"));
14044 fprintf (stream, _("\
14045 -mfix-vr4120 work around certain VR4120 errata\n\
14046 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14047 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14048 -O0 remove unneeded NOPs, do not swap branches\n\
14049 -O remove unneeded NOPs and swap branches\n\
14050 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14051 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14052 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14054 fprintf (stream, _("\
14055 -KPIC, -call_shared generate SVR4 position independent code\n\
14056 -non_shared do not generate position independent code\n\
14057 -xgot assume a 32 bit GOT\n\
14058 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14059 -mabi=ABI create ABI conformant object file for:\n"));
14063 show (stream, "32", &column, &first);
14064 show (stream, "o64", &column, &first);
14065 show (stream, "n32", &column, &first);
14066 show (stream, "64", &column, &first);
14067 show (stream, "eabi", &column, &first);
14069 fputc ('\n', stream);
14071 fprintf (stream, _("\
14072 -32 create o32 ABI object file (default)\n\
14073 -n32 create n32 ABI object file\n\
14074 -64 create 64 ABI object file\n"));
14079 mips_dwarf2_format (void)
14081 if (mips_abi == N64_ABI)
14084 return dwarf2_format_64bit_irix;
14086 return dwarf2_format_64bit;
14090 return dwarf2_format_32bit;
14094 mips_dwarf2_addr_size (void)
14096 if (mips_abi == N64_ABI)