1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
290 /* Return true if the given CPU supports the MIPS3D ASE. */
291 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
294 /* Return true if the given CPU supports the MDMX ASE. */
295 #define CPU_HAS_MDMX(cpu) (false \
298 /* Whether the processor uses hardware interlocks to protect
299 reads from the HI and LO registers, and thus does not
300 require nops to be inserted. */
302 #define hilo_interlocks (mips_arch == CPU_R4010 \
303 || mips_arch == CPU_SB1 \
306 /* Whether the processor uses hardware interlocks to protect reads
307 from the GPRs, and thus does not require nops to be inserted. */
308 #define gpr_interlocks \
309 (mips_opts.isa != ISA_MIPS1 \
310 || mips_arch == CPU_R3900)
312 /* As with other "interlocks" this is used by hardware that has FP
313 (co-processor) interlocks. */
314 /* Itbl support may require additional care here. */
315 #define cop_interlocks (mips_arch == CPU_R4300 \
316 || mips_arch == CPU_SB1 \
319 /* Is this a mfhi or mflo instruction? */
320 #define MF_HILO_INSN(PINFO) \
321 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
323 /* MIPS PIC level. */
327 /* Do not generate PIC code. */
330 /* Generate PIC code as in the SVR4 MIPS ABI. */
333 /* Generate PIC code without using a global offset table: the data
334 segment has a maximum size of 64K, all data references are off
335 the $gp register, and all text references are PC relative. This
336 is used on some embedded systems. */
340 static enum mips_pic_level mips_pic;
342 /* Warn about all NOPS that the assembler generates. */
343 static int warn_nops = 0;
345 /* 1 if we should generate 32 bit offsets from the $gp register in
346 SVR4_PIC mode. Currently has no meaning in other modes. */
347 static int mips_big_got = 0;
349 /* 1 if trap instructions should used for overflow rather than break
351 static int mips_trap = 0;
353 /* 1 if double width floating point constants should not be constructed
354 by assembling two single width halves into two single width floating
355 point registers which just happen to alias the double width destination
356 register. On some architectures this aliasing can be disabled by a bit
357 in the status register, and the setting of this bit cannot be determined
358 automatically at assemble time. */
359 static int mips_disable_float_construction;
361 /* Non-zero if any .set noreorder directives were used. */
363 static int mips_any_noreorder;
365 /* Non-zero if nops should be inserted when the register referenced in
366 an mfhi/mflo instruction is read in the next two instructions. */
367 static int mips_7000_hilo_fix;
369 /* The size of the small data section. */
370 static unsigned int g_switch_value = 8;
371 /* Whether the -G option was used. */
372 static int g_switch_seen = 0;
377 /* If we can determine in advance that GP optimization won't be
378 possible, we can skip the relaxation stuff that tries to produce
379 GP-relative references. This makes delay slot optimization work
382 This function can only provide a guess, but it seems to work for
383 gcc output. It needs to guess right for gcc, otherwise gcc
384 will put what it thinks is a GP-relative instruction in a branch
387 I don't know if a fix is needed for the SVR4_PIC mode. I've only
388 fixed it for the non-PIC mode. KR 95/04/07 */
389 static int nopic_need_relax PARAMS ((symbolS *, int));
391 /* handle of the OPCODE hash table */
392 static struct hash_control *op_hash = NULL;
394 /* The opcode hash table we use for the mips16. */
395 static struct hash_control *mips16_op_hash = NULL;
397 /* This array holds the chars that always start a comment. If the
398 pre-processor is disabled, these aren't very useful */
399 const char comment_chars[] = "#";
401 /* This array holds the chars that only start a comment at the beginning of
402 a line. If the line seems to have the form '# 123 filename'
403 .line and .file directives will appear in the pre-processed output */
404 /* Note that input_file.c hand checks for '#' at the beginning of the
405 first line of the input file. This is because the compiler outputs
406 #NO_APP at the beginning of its output. */
407 /* Also note that C style comments are always supported. */
408 const char line_comment_chars[] = "#";
410 /* This array holds machine specific line separator characters. */
411 const char line_separator_chars[] = ";";
413 /* Chars that can be used to separate mant from exp in floating point nums */
414 const char EXP_CHARS[] = "eE";
416 /* Chars that mean this number is a floating point constant */
419 const char FLT_CHARS[] = "rRsSfFdDxXpP";
421 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
422 changed in read.c . Ideally it shouldn't have to know about it at all,
423 but nothing is ideal around here.
426 static char *insn_error;
428 static int auto_align = 1;
430 /* When outputting SVR4 PIC code, the assembler needs to know the
431 offset in the stack frame from which to restore the $gp register.
432 This is set by the .cprestore pseudo-op, and saved in this
434 static offsetT mips_cprestore_offset = -1;
436 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
437 more optimizations, it can use a register value instead of a memory-saved
438 offset and even an other register than $gp as global pointer. */
439 static offsetT mips_cpreturn_offset = -1;
440 static int mips_cpreturn_register = -1;
441 static int mips_gp_register = GP;
442 static int mips_gprel_offset = 0;
444 /* Whether mips_cprestore_offset has been set in the current function
445 (or whether it has already been warned about, if not). */
446 static int mips_cprestore_valid = 0;
448 /* This is the register which holds the stack frame, as set by the
449 .frame pseudo-op. This is needed to implement .cprestore. */
450 static int mips_frame_reg = SP;
452 /* Whether mips_frame_reg has been set in the current function
453 (or whether it has already been warned about, if not). */
454 static int mips_frame_reg_valid = 0;
456 /* To output NOP instructions correctly, we need to keep information
457 about the previous two instructions. */
459 /* Whether we are optimizing. The default value of 2 means to remove
460 unneeded NOPs and swap branch instructions when possible. A value
461 of 1 means to not swap branches. A value of 0 means to always
463 static int mips_optimize = 2;
465 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
466 equivalent to seeing no -g option at all. */
467 static int mips_debug = 0;
469 /* The previous instruction. */
470 static struct mips_cl_insn prev_insn;
472 /* The instruction before prev_insn. */
473 static struct mips_cl_insn prev_prev_insn;
475 /* If we don't want information for prev_insn or prev_prev_insn, we
476 point the insn_mo field at this dummy integer. */
477 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
479 /* Non-zero if prev_insn is valid. */
480 static int prev_insn_valid;
482 /* The frag for the previous instruction. */
483 static struct frag *prev_insn_frag;
485 /* The offset into prev_insn_frag for the previous instruction. */
486 static long prev_insn_where;
488 /* The reloc type for the previous instruction, if any. */
489 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
491 /* The reloc for the previous instruction, if any. */
492 static fixS *prev_insn_fixp[3];
494 /* Non-zero if the previous instruction was in a delay slot. */
495 static int prev_insn_is_delay_slot;
497 /* Non-zero if the previous instruction was in a .set noreorder. */
498 static int prev_insn_unreordered;
500 /* Non-zero if the previous instruction uses an extend opcode (if
502 static int prev_insn_extended;
504 /* Non-zero if the previous previous instruction was in a .set
506 static int prev_prev_insn_unreordered;
508 /* If this is set, it points to a frag holding nop instructions which
509 were inserted before the start of a noreorder section. If those
510 nops turn out to be unnecessary, the size of the frag can be
512 static fragS *prev_nop_frag;
514 /* The number of nop instructions we created in prev_nop_frag. */
515 static int prev_nop_frag_holds;
517 /* The number of nop instructions that we know we need in
519 static int prev_nop_frag_required;
521 /* The number of instructions we've seen since prev_nop_frag. */
522 static int prev_nop_frag_since;
524 /* For ECOFF and ELF, relocations against symbols are done in two
525 parts, with a HI relocation and a LO relocation. Each relocation
526 has only 16 bits of space to store an addend. This means that in
527 order for the linker to handle carries correctly, it must be able
528 to locate both the HI and the LO relocation. This means that the
529 relocations must appear in order in the relocation table.
531 In order to implement this, we keep track of each unmatched HI
532 relocation. We then sort them so that they immediately precede the
533 corresponding LO relocation. */
538 struct mips_hi_fixup *next;
541 /* The section this fixup is in. */
545 /* The list of unmatched HI relocs. */
547 static struct mips_hi_fixup *mips_hi_fixup_list;
549 /* Map normal MIPS register numbers to mips16 register numbers. */
551 #define X ILLEGAL_REG
552 static const int mips32_to_16_reg_map[] =
554 X, X, 2, 3, 4, 5, 6, 7,
555 X, X, X, X, X, X, X, X,
556 0, 1, X, X, X, X, X, X,
557 X, X, X, X, X, X, X, X
561 /* Map mips16 register numbers to normal MIPS register numbers. */
563 static const unsigned int mips16_to_32_reg_map[] =
565 16, 17, 2, 3, 4, 5, 6, 7
568 /* Since the MIPS does not have multiple forms of PC relative
569 instructions, we do not have to do relaxing as is done on other
570 platforms. However, we do have to handle GP relative addressing
571 correctly, which turns out to be a similar problem.
573 Every macro that refers to a symbol can occur in (at least) two
574 forms, one with GP relative addressing and one without. For
575 example, loading a global variable into a register generally uses
576 a macro instruction like this:
578 If i can be addressed off the GP register (this is true if it is in
579 the .sbss or .sdata section, or if it is known to be smaller than
580 the -G argument) this will generate the following instruction:
582 This instruction will use a GPREL reloc. If i can not be addressed
583 off the GP register, the following instruction sequence will be used:
586 In this case the first instruction will have a HI16 reloc, and the
587 second reloc will have a LO16 reloc. Both relocs will be against
590 The issue here is that we may not know whether i is GP addressable
591 until after we see the instruction that uses it. Therefore, we
592 want to be able to choose the final instruction sequence only at
593 the end of the assembly. This is similar to the way other
594 platforms choose the size of a PC relative instruction only at the
597 When generating position independent code we do not use GP
598 addressing in quite the same way, but the issue still arises as
599 external symbols and local symbols must be handled differently.
601 We handle these issues by actually generating both possible
602 instruction sequences. The longer one is put in a frag_var with
603 type rs_machine_dependent. We encode what to do with the frag in
604 the subtype field. We encode (1) the number of existing bytes to
605 replace, (2) the number of new bytes to use, (3) the offset from
606 the start of the existing bytes to the first reloc we must generate
607 (that is, the offset is applied from the start of the existing
608 bytes after they are replaced by the new bytes, if any), (4) the
609 offset from the start of the existing bytes to the second reloc,
610 (5) whether a third reloc is needed (the third reloc is always four
611 bytes after the second reloc), and (6) whether to warn if this
612 variant is used (this is sometimes needed if .set nomacro or .set
613 noat is in effect). All these numbers are reasonably small.
615 Generating two instruction sequences must be handled carefully to
616 ensure that delay slots are handled correctly. Fortunately, there
617 are a limited number of cases. When the second instruction
618 sequence is generated, append_insn is directed to maintain the
619 existing delay slot information, so it continues to apply to any
620 code after the second instruction sequence. This means that the
621 second instruction sequence must not impose any requirements not
622 required by the first instruction sequence.
624 These variant frags are then handled in functions called by the
625 machine independent code. md_estimate_size_before_relax returns
626 the final size of the frag. md_convert_frag sets up the final form
627 of the frag. tc_gen_reloc adjust the first reloc and adds a second
629 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
633 | (((reloc1) + 64) << 9) \
634 | (((reloc2) + 64) << 2) \
635 | ((reloc3) ? (1 << 1) : 0) \
637 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
638 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
639 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
640 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
641 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
642 #define RELAX_WARN(i) ((i) & 1)
644 /* For mips16 code, we use an entirely different form of relaxation.
645 mips16 supports two versions of most instructions which take
646 immediate values: a small one which takes some small value, and a
647 larger one which takes a 16 bit value. Since branches also follow
648 this pattern, relaxing these values is required.
650 We can assemble both mips16 and normal MIPS code in a single
651 object. Therefore, we need to support this type of relaxation at
652 the same time that we support the relaxation described above. We
653 use the high bit of the subtype field to distinguish these cases.
655 The information we store for this type of relaxation is the
656 argument code found in the opcode file for this relocation, whether
657 the user explicitly requested a small or extended form, and whether
658 the relocation is in a jump or jal delay slot. That tells us the
659 size of the value, and how it should be stored. We also store
660 whether the fragment is considered to be extended or not. We also
661 store whether this is known to be a branch to a different section,
662 whether we have tried to relax this frag yet, and whether we have
663 ever extended a PC relative fragment because of a shift count. */
664 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
667 | ((small) ? 0x100 : 0) \
668 | ((ext) ? 0x200 : 0) \
669 | ((dslot) ? 0x400 : 0) \
670 | ((jal_dslot) ? 0x800 : 0))
671 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
672 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
673 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
674 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
675 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
676 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
677 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
678 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
679 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
680 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
681 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
682 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
684 /* Prototypes for static functions. */
687 #define internalError() \
688 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
690 #define internalError() as_fatal (_("MIPS internal Error"));
693 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
695 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
696 unsigned int reg, enum mips_regclass class));
697 static int reg_needs_delay PARAMS ((unsigned int));
698 static void mips16_mark_labels PARAMS ((void));
699 static void append_insn PARAMS ((char *place,
700 struct mips_cl_insn * ip,
702 bfd_reloc_code_real_type *r,
704 static void mips_no_prev_insn PARAMS ((int));
705 static void mips_emit_delays PARAMS ((boolean));
707 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
708 const char *name, const char *fmt,
711 static void macro_build ();
713 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
714 const char *, const char *,
716 static void macro_build_jalr PARAMS ((int, expressionS *));
717 static void macro_build_lui PARAMS ((char *place, int *counter,
718 expressionS * ep, int regnum));
719 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
720 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
722 static void load_register PARAMS ((int *, int, expressionS *, int));
723 static void load_address PARAMS ((int *, int, expressionS *, int *));
724 static void move_register PARAMS ((int *, int, int));
725 static void macro PARAMS ((struct mips_cl_insn * ip));
726 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
727 #ifdef LOSING_COMPILER
728 static void macro2 PARAMS ((struct mips_cl_insn * ip));
730 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
731 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
732 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
733 boolean, boolean, unsigned long *,
734 boolean *, unsigned short *));
735 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
737 static int my_getSmallExpression PARAMS ((expressionS *, char *));
738 static void my_getExpression PARAMS ((expressionS *, char *));
740 static int support_64bit_objects PARAMS((void));
742 static void mips_set_option_string PARAMS ((const char **, const char *));
743 static symbolS *get_symbol PARAMS ((void));
744 static void mips_align PARAMS ((int to, int fill, symbolS *label));
745 static void s_align PARAMS ((int));
746 static void s_change_sec PARAMS ((int));
747 static void s_cons PARAMS ((int));
748 static void s_float_cons PARAMS ((int));
749 static void s_mips_globl PARAMS ((int));
750 static void s_option PARAMS ((int));
751 static void s_mipsset PARAMS ((int));
752 static void s_abicalls PARAMS ((int));
753 static void s_cpload PARAMS ((int));
754 static void s_cpsetup PARAMS ((int));
755 static void s_cplocal PARAMS ((int));
756 static void s_cprestore PARAMS ((int));
757 static void s_cpreturn PARAMS ((int));
758 static void s_gpvalue PARAMS ((int));
759 static void s_gpword PARAMS ((int));
760 static void s_cpadd PARAMS ((int));
761 static void s_insn PARAMS ((int));
762 static void md_obj_begin PARAMS ((void));
763 static void md_obj_end PARAMS ((void));
764 static long get_number PARAMS ((void));
765 static void s_mips_ent PARAMS ((int));
766 static void s_mips_end PARAMS ((int));
767 static void s_mips_frame PARAMS ((int));
768 static void s_mips_mask PARAMS ((int));
769 static void s_mips_stab PARAMS ((int));
770 static void s_mips_weakext PARAMS ((int));
771 static void s_mips_file PARAMS ((int));
772 static void s_mips_loc PARAMS ((int));
773 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
774 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
775 static void show PARAMS ((FILE *, const char *, int *, int *));
777 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
780 /* Return values of my_getSmallExpression(). */
787 /* Direct relocation creation by %percent_op(). */
806 /* Table and functions used to map between CPU/ISA names, and
807 ISA levels, and CPU numbers. */
811 const char *name; /* CPU or ISA name. */
812 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
813 int isa; /* ISA level. */
814 int cpu; /* CPU number (default CPU if ISA). */
817 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
818 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
819 static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *,
821 static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *));
822 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
824 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
828 The following pseudo-ops from the Kane and Heinrich MIPS book
829 should be defined here, but are currently unsupported: .alias,
830 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
832 The following pseudo-ops from the Kane and Heinrich MIPS book are
833 specific to the type of debugging information being generated, and
834 should be defined by the object format: .aent, .begin, .bend,
835 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
838 The following pseudo-ops from the Kane and Heinrich MIPS book are
839 not MIPS CPU specific, but are also not specific to the object file
840 format. This file is probably the best place to define them, but
841 they are not currently supported: .asm0, .endr, .lab, .repeat,
844 static const pseudo_typeS mips_pseudo_table[] =
846 /* MIPS specific pseudo-ops. */
847 {"option", s_option, 0},
848 {"set", s_mipsset, 0},
849 {"rdata", s_change_sec, 'r'},
850 {"sdata", s_change_sec, 's'},
851 {"livereg", s_ignore, 0},
852 {"abicalls", s_abicalls, 0},
853 {"cpload", s_cpload, 0},
854 {"cpsetup", s_cpsetup, 0},
855 {"cplocal", s_cplocal, 0},
856 {"cprestore", s_cprestore, 0},
857 {"cpreturn", s_cpreturn, 0},
858 {"gpvalue", s_gpvalue, 0},
859 {"gpword", s_gpword, 0},
860 {"cpadd", s_cpadd, 0},
863 /* Relatively generic pseudo-ops that happen to be used on MIPS
865 {"asciiz", stringer, 1},
866 {"bss", s_change_sec, 'b'},
869 {"dword", s_cons, 3},
870 {"weakext", s_mips_weakext, 0},
872 /* These pseudo-ops are defined in read.c, but must be overridden
873 here for one reason or another. */
874 {"align", s_align, 0},
876 {"data", s_change_sec, 'd'},
877 {"double", s_float_cons, 'd'},
878 {"float", s_float_cons, 'f'},
879 {"globl", s_mips_globl, 0},
880 {"global", s_mips_globl, 0},
881 {"hword", s_cons, 1},
886 {"short", s_cons, 1},
887 {"single", s_float_cons, 'f'},
888 {"stabn", s_mips_stab, 'n'},
889 {"text", s_change_sec, 't'},
892 { "extern", ecoff_directive_extern, 0},
897 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
899 /* These pseudo-ops should be defined by the object file format.
900 However, a.out doesn't support them, so we have versions here. */
901 {"aent", s_mips_ent, 1},
902 {"bgnb", s_ignore, 0},
903 {"end", s_mips_end, 0},
904 {"endb", s_ignore, 0},
905 {"ent", s_mips_ent, 0},
906 {"file", s_mips_file, 0},
907 {"fmask", s_mips_mask, 'F'},
908 {"frame", s_mips_frame, 0},
909 {"loc", s_mips_loc, 0},
910 {"mask", s_mips_mask, 'R'},
911 {"verstamp", s_ignore, 0},
915 extern void pop_insert PARAMS ((const pseudo_typeS *));
920 pop_insert (mips_pseudo_table);
921 if (! ECOFF_DEBUGGING)
922 pop_insert (mips_nonecoff_pseudo_table);
925 /* Symbols labelling the current insn. */
927 struct insn_label_list
929 struct insn_label_list *next;
933 static struct insn_label_list *insn_labels;
934 static struct insn_label_list *free_insn_labels;
936 static void mips_clear_insn_labels PARAMS ((void));
939 mips_clear_insn_labels ()
941 register struct insn_label_list **pl;
943 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
949 static char *expr_end;
951 /* Expressions which appear in instructions. These are set by
954 static expressionS imm_expr;
955 static expressionS offset_expr;
957 /* Relocs associated with imm_expr and offset_expr. */
959 static bfd_reloc_code_real_type imm_reloc[3]
960 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
961 static bfd_reloc_code_real_type offset_reloc[3]
962 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
964 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
966 static boolean imm_unmatched_hi;
968 /* These are set by mips16_ip if an explicit extension is used. */
970 static boolean mips16_small, mips16_ext;
972 /* The pdr segment for per procedure frame/regmask info. Not used for
977 /* The default target format to use. */
980 mips_target_format ()
982 switch (OUTPUT_FLAVOR)
984 case bfd_target_aout_flavour:
985 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
986 case bfd_target_ecoff_flavour:
987 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
988 case bfd_target_coff_flavour:
990 case bfd_target_elf_flavour:
992 /* This is traditional mips. */
993 return (target_big_endian
994 ? (HAVE_64BIT_OBJECTS
995 ? "elf64-tradbigmips"
997 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
998 : (HAVE_64BIT_OBJECTS
999 ? "elf64-tradlittlemips"
1001 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1003 return (target_big_endian
1004 ? (HAVE_64BIT_OBJECTS
1007 ? "elf32-nbigmips" : "elf32-bigmips"))
1008 : (HAVE_64BIT_OBJECTS
1009 ? "elf64-littlemips"
1011 ? "elf32-nlittlemips" : "elf32-littlemips")));
1019 /* This function is called once, at assembler startup time. It should
1020 set up all the tables, etc. that the MD part of the assembler will need. */
1025 register const char *retval = NULL;
1029 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1030 as_warn (_("Could not set architecture and machine"));
1032 op_hash = hash_new ();
1034 for (i = 0; i < NUMOPCODES;)
1036 const char *name = mips_opcodes[i].name;
1038 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1041 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1042 mips_opcodes[i].name, retval);
1043 /* Probably a memory allocation problem? Give up now. */
1044 as_fatal (_("Broken assembler. No assembly attempted."));
1048 if (mips_opcodes[i].pinfo != INSN_MACRO)
1050 if (!validate_mips_insn (&mips_opcodes[i]))
1055 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1058 mips16_op_hash = hash_new ();
1061 while (i < bfd_mips16_num_opcodes)
1063 const char *name = mips16_opcodes[i].name;
1065 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1067 as_fatal (_("internal: can't hash `%s': %s"),
1068 mips16_opcodes[i].name, retval);
1071 if (mips16_opcodes[i].pinfo != INSN_MACRO
1072 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1073 != mips16_opcodes[i].match))
1075 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1076 mips16_opcodes[i].name, mips16_opcodes[i].args);
1081 while (i < bfd_mips16_num_opcodes
1082 && strcmp (mips16_opcodes[i].name, name) == 0);
1086 as_fatal (_("Broken assembler. No assembly attempted."));
1088 /* We add all the general register names to the symbol table. This
1089 helps us detect invalid uses of them. */
1090 for (i = 0; i < 32; i++)
1094 sprintf (buf, "$%d", i);
1095 symbol_table_insert (symbol_new (buf, reg_section, i,
1096 &zero_address_frag));
1098 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1099 &zero_address_frag));
1100 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1101 &zero_address_frag));
1102 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1103 &zero_address_frag));
1104 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1105 &zero_address_frag));
1106 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1107 &zero_address_frag));
1108 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1109 &zero_address_frag));
1110 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1111 &zero_address_frag));
1112 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1113 &zero_address_frag));
1114 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1115 &zero_address_frag));
1117 mips_no_prev_insn (false);
1120 mips_cprmask[0] = 0;
1121 mips_cprmask[1] = 0;
1122 mips_cprmask[2] = 0;
1123 mips_cprmask[3] = 0;
1125 /* set the default alignment for the text section (2**2) */
1126 record_alignment (text_section, 2);
1128 if (USE_GLOBAL_POINTER_OPT)
1129 bfd_set_gp_size (stdoutput, g_switch_value);
1131 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1133 /* On a native system, sections must be aligned to 16 byte
1134 boundaries. When configured for an embedded ELF target, we
1136 if (strcmp (TARGET_OS, "elf") != 0)
1138 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1139 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1140 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1143 /* Create a .reginfo section for register masks and a .mdebug
1144 section for debugging information. */
1152 subseg = now_subseg;
1154 /* The ABI says this section should be loaded so that the
1155 running program can access it. However, we don't load it
1156 if we are configured for an embedded target */
1157 flags = SEC_READONLY | SEC_DATA;
1158 if (strcmp (TARGET_OS, "elf") != 0)
1159 flags |= SEC_ALLOC | SEC_LOAD;
1161 if (mips_abi != N64_ABI)
1163 sec = subseg_new (".reginfo", (subsegT) 0);
1165 bfd_set_section_flags (stdoutput, sec, flags);
1166 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1169 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1174 /* The 64-bit ABI uses a .MIPS.options section rather than
1175 .reginfo section. */
1176 sec = subseg_new (".MIPS.options", (subsegT) 0);
1177 bfd_set_section_flags (stdoutput, sec, flags);
1178 bfd_set_section_alignment (stdoutput, sec, 3);
1181 /* Set up the option header. */
1183 Elf_Internal_Options opthdr;
1186 opthdr.kind = ODK_REGINFO;
1187 opthdr.size = (sizeof (Elf_External_Options)
1188 + sizeof (Elf64_External_RegInfo));
1191 f = frag_more (sizeof (Elf_External_Options));
1192 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1193 (Elf_External_Options *) f);
1195 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1200 if (ECOFF_DEBUGGING)
1202 sec = subseg_new (".mdebug", (subsegT) 0);
1203 (void) bfd_set_section_flags (stdoutput, sec,
1204 SEC_HAS_CONTENTS | SEC_READONLY);
1205 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1208 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1210 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1211 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1212 SEC_READONLY | SEC_RELOC
1214 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1218 subseg_set (seg, subseg);
1222 if (! ECOFF_DEBUGGING)
1229 if (! ECOFF_DEBUGGING)
1237 struct mips_cl_insn insn;
1238 bfd_reloc_code_real_type unused_reloc[3]
1239 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1241 imm_expr.X_op = O_absent;
1242 imm_unmatched_hi = false;
1243 offset_expr.X_op = O_absent;
1244 imm_reloc[0] = BFD_RELOC_UNUSED;
1245 imm_reloc[1] = BFD_RELOC_UNUSED;
1246 imm_reloc[2] = BFD_RELOC_UNUSED;
1247 offset_reloc[0] = BFD_RELOC_UNUSED;
1248 offset_reloc[1] = BFD_RELOC_UNUSED;
1249 offset_reloc[2] = BFD_RELOC_UNUSED;
1251 if (mips_opts.mips16)
1252 mips16_ip (str, &insn);
1255 mips_ip (str, &insn);
1256 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1257 str, insn.insn_opcode));
1262 as_bad ("%s `%s'", insn_error, str);
1266 if (insn.insn_mo->pinfo == INSN_MACRO)
1268 if (mips_opts.mips16)
1269 mips16_macro (&insn);
1275 if (imm_expr.X_op != O_absent)
1276 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1277 else if (offset_expr.X_op != O_absent)
1278 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1280 append_insn (NULL, &insn, NULL, unused_reloc, false);
1284 /* See whether instruction IP reads register REG. CLASS is the type
1288 insn_uses_reg (ip, reg, class)
1289 struct mips_cl_insn *ip;
1291 enum mips_regclass class;
1293 if (class == MIPS16_REG)
1295 assert (mips_opts.mips16);
1296 reg = mips16_to_32_reg_map[reg];
1297 class = MIPS_GR_REG;
1300 /* Don't report on general register ZERO, since it never changes. */
1301 if (class == MIPS_GR_REG && reg == ZERO)
1304 if (class == MIPS_FP_REG)
1306 assert (! mips_opts.mips16);
1307 /* If we are called with either $f0 or $f1, we must check $f0.
1308 This is not optimal, because it will introduce an unnecessary
1309 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1310 need to distinguish reading both $f0 and $f1 or just one of
1311 them. Note that we don't have to check the other way,
1312 because there is no instruction that sets both $f0 and $f1
1313 and requires a delay. */
1314 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1315 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1316 == (reg &~ (unsigned) 1)))
1318 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1319 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1320 == (reg &~ (unsigned) 1)))
1323 else if (! mips_opts.mips16)
1325 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1326 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1328 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1329 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1334 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1335 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1336 & MIPS16OP_MASK_RX)]
1339 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1340 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1341 & MIPS16OP_MASK_RY)]
1344 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1345 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1346 & MIPS16OP_MASK_MOVE32Z)]
1349 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1351 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1353 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1355 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1356 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1357 & MIPS16OP_MASK_REGR32) == reg)
1364 /* This function returns true if modifying a register requires a
1368 reg_needs_delay (reg)
1371 unsigned long prev_pinfo;
1373 prev_pinfo = prev_insn.insn_mo->pinfo;
1374 if (! mips_opts.noreorder
1375 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1376 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1377 || (! gpr_interlocks
1378 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1380 /* A load from a coprocessor or from memory. All load
1381 delays delay the use of general register rt for one
1382 instruction on the r3000. The r6000 and r4000 use
1384 /* Itbl support may require additional care here. */
1385 know (prev_pinfo & INSN_WRITE_GPR_T);
1386 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1393 /* Mark instruction labels in mips16 mode. This permits the linker to
1394 handle them specially, such as generating jalx instructions when
1395 needed. We also make them odd for the duration of the assembly, in
1396 order to generate the right sort of code. We will make them even
1397 in the adjust_symtab routine, while leaving them marked. This is
1398 convenient for the debugger and the disassembler. The linker knows
1399 to make them odd again. */
1402 mips16_mark_labels ()
1404 if (mips_opts.mips16)
1406 struct insn_label_list *l;
1409 for (l = insn_labels; l != NULL; l = l->next)
1412 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1413 S_SET_OTHER (l->label, STO_MIPS16);
1415 val = S_GET_VALUE (l->label);
1417 S_SET_VALUE (l->label, val + 1);
1422 /* Output an instruction. PLACE is where to put the instruction; if
1423 it is NULL, this uses frag_more to get room. IP is the instruction
1424 information. ADDRESS_EXPR is an operand of the instruction to be
1425 used with RELOC_TYPE. */
1428 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1430 struct mips_cl_insn *ip;
1431 expressionS *address_expr;
1432 bfd_reloc_code_real_type *reloc_type;
1433 boolean unmatched_hi;
1435 register unsigned long prev_pinfo, pinfo;
1440 /* Mark instruction labels in mips16 mode. */
1441 mips16_mark_labels ();
1443 prev_pinfo = prev_insn.insn_mo->pinfo;
1444 pinfo = ip->insn_mo->pinfo;
1446 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1450 /* If the previous insn required any delay slots, see if we need
1451 to insert a NOP or two. There are eight kinds of possible
1452 hazards, of which an instruction can have at most one type.
1453 (1) a load from memory delay
1454 (2) a load from a coprocessor delay
1455 (3) an unconditional branch delay
1456 (4) a conditional branch delay
1457 (5) a move to coprocessor register delay
1458 (6) a load coprocessor register from memory delay
1459 (7) a coprocessor condition code delay
1460 (8) a HI/LO special register delay
1462 There are a lot of optimizations we could do that we don't.
1463 In particular, we do not, in general, reorder instructions.
1464 If you use gcc with optimization, it will reorder
1465 instructions and generally do much more optimization then we
1466 do here; repeating all that work in the assembler would only
1467 benefit hand written assembly code, and does not seem worth
1470 /* This is how a NOP is emitted. */
1471 #define emit_nop() \
1473 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1474 : md_number_to_chars (frag_more (4), 0, 4))
1476 /* The previous insn might require a delay slot, depending upon
1477 the contents of the current insn. */
1478 if (! mips_opts.mips16
1479 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1480 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1481 && ! cop_interlocks)
1482 || (! gpr_interlocks
1483 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1485 /* A load from a coprocessor or from memory. All load
1486 delays delay the use of general register rt for one
1487 instruction on the r3000. The r6000 and r4000 use
1489 /* Itbl support may require additional care here. */
1490 know (prev_pinfo & INSN_WRITE_GPR_T);
1491 if (mips_optimize == 0
1492 || insn_uses_reg (ip,
1493 ((prev_insn.insn_opcode >> OP_SH_RT)
1498 else if (! mips_opts.mips16
1499 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1500 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1501 && ! cop_interlocks)
1502 || (mips_opts.isa == ISA_MIPS1
1503 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1505 /* A generic coprocessor delay. The previous instruction
1506 modified a coprocessor general or control register. If
1507 it modified a control register, we need to avoid any
1508 coprocessor instruction (this is probably not always
1509 required, but it sometimes is). If it modified a general
1510 register, we avoid using that register.
1512 On the r6000 and r4000 loading a coprocessor register
1513 from memory is interlocked, and does not require a delay.
1515 This case is not handled very well. There is no special
1516 knowledge of CP0 handling, and the coprocessors other
1517 than the floating point unit are not distinguished at
1519 /* Itbl support may require additional care here. FIXME!
1520 Need to modify this to include knowledge about
1521 user specified delays! */
1522 if (prev_pinfo & INSN_WRITE_FPR_T)
1524 if (mips_optimize == 0
1525 || insn_uses_reg (ip,
1526 ((prev_insn.insn_opcode >> OP_SH_FT)
1531 else if (prev_pinfo & INSN_WRITE_FPR_S)
1533 if (mips_optimize == 0
1534 || insn_uses_reg (ip,
1535 ((prev_insn.insn_opcode >> OP_SH_FS)
1542 /* We don't know exactly what the previous instruction
1543 does. If the current instruction uses a coprocessor
1544 register, we must insert a NOP. If previous
1545 instruction may set the condition codes, and the
1546 current instruction uses them, we must insert two
1548 /* Itbl support may require additional care here. */
1549 if (mips_optimize == 0
1550 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1551 && (pinfo & INSN_READ_COND_CODE)))
1553 else if (pinfo & INSN_COP)
1557 else if (! mips_opts.mips16
1558 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1559 && (prev_pinfo & INSN_WRITE_COND_CODE)
1560 && ! cop_interlocks)
1562 /* The previous instruction sets the coprocessor condition
1563 codes, but does not require a general coprocessor delay
1564 (this means it is a floating point comparison
1565 instruction). If this instruction uses the condition
1566 codes, we need to insert a single NOP. */
1567 /* Itbl support may require additional care here. */
1568 if (mips_optimize == 0
1569 || (pinfo & INSN_READ_COND_CODE))
1573 /* If we're fixing up mfhi/mflo for the r7000 and the
1574 previous insn was an mfhi/mflo and the current insn
1575 reads the register that the mfhi/mflo wrote to, then
1578 else if (mips_7000_hilo_fix
1579 && MF_HILO_INSN (prev_pinfo)
1580 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1587 /* If we're fixing up mfhi/mflo for the r7000 and the
1588 2nd previous insn was an mfhi/mflo and the current insn
1589 reads the register that the mfhi/mflo wrote to, then
1592 else if (mips_7000_hilo_fix
1593 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1594 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1602 else if (prev_pinfo & INSN_READ_LO)
1604 /* The previous instruction reads the LO register; if the
1605 current instruction writes to the LO register, we must
1606 insert two NOPS. Some newer processors have interlocks.
1607 Also the tx39's multiply instructions can be exectuted
1608 immediatly after a read from HI/LO (without the delay),
1609 though the tx39's divide insns still do require the
1611 if (! (hilo_interlocks
1612 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1613 && (mips_optimize == 0
1614 || (pinfo & INSN_WRITE_LO)))
1616 /* Most mips16 branch insns don't have a delay slot.
1617 If a read from LO is immediately followed by a branch
1618 to a write to LO we have a read followed by a write
1619 less than 2 insns away. We assume the target of
1620 a branch might be a write to LO, and insert a nop
1621 between a read and an immediately following branch. */
1622 else if (mips_opts.mips16
1623 && (mips_optimize == 0
1624 || (pinfo & MIPS16_INSN_BRANCH)))
1627 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1629 /* The previous instruction reads the HI register; if the
1630 current instruction writes to the HI register, we must
1631 insert a NOP. Some newer processors have interlocks.
1632 Also the note tx39's multiply above. */
1633 if (! (hilo_interlocks
1634 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1635 && (mips_optimize == 0
1636 || (pinfo & INSN_WRITE_HI)))
1638 /* Most mips16 branch insns don't have a delay slot.
1639 If a read from HI is immediately followed by a branch
1640 to a write to HI we have a read followed by a write
1641 less than 2 insns away. We assume the target of
1642 a branch might be a write to HI, and insert a nop
1643 between a read and an immediately following branch. */
1644 else if (mips_opts.mips16
1645 && (mips_optimize == 0
1646 || (pinfo & MIPS16_INSN_BRANCH)))
1650 /* If the previous instruction was in a noreorder section, then
1651 we don't want to insert the nop after all. */
1652 /* Itbl support may require additional care here. */
1653 if (prev_insn_unreordered)
1656 /* There are two cases which require two intervening
1657 instructions: 1) setting the condition codes using a move to
1658 coprocessor instruction which requires a general coprocessor
1659 delay and then reading the condition codes 2) reading the HI
1660 or LO register and then writing to it (except on processors
1661 which have interlocks). If we are not already emitting a NOP
1662 instruction, we must check for these cases compared to the
1663 instruction previous to the previous instruction. */
1664 if ((! mips_opts.mips16
1665 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1666 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1667 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1668 && (pinfo & INSN_READ_COND_CODE)
1669 && ! cop_interlocks)
1670 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1671 && (pinfo & INSN_WRITE_LO)
1672 && ! (hilo_interlocks
1673 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1674 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1675 && (pinfo & INSN_WRITE_HI)
1676 && ! (hilo_interlocks
1677 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1682 if (prev_prev_insn_unreordered)
1685 if (prev_prev_nop && nops == 0)
1688 /* If we are being given a nop instruction, don't bother with
1689 one of the nops we would otherwise output. This will only
1690 happen when a nop instruction is used with mips_optimize set
1693 && ! mips_opts.noreorder
1694 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1697 /* Now emit the right number of NOP instructions. */
1698 if (nops > 0 && ! mips_opts.noreorder)
1701 unsigned long old_frag_offset;
1703 struct insn_label_list *l;
1705 old_frag = frag_now;
1706 old_frag_offset = frag_now_fix ();
1708 for (i = 0; i < nops; i++)
1713 listing_prev_line ();
1714 /* We may be at the start of a variant frag. In case we
1715 are, make sure there is enough space for the frag
1716 after the frags created by listing_prev_line. The
1717 argument to frag_grow here must be at least as large
1718 as the argument to all other calls to frag_grow in
1719 this file. We don't have to worry about being in the
1720 middle of a variant frag, because the variants insert
1721 all needed nop instructions themselves. */
1725 for (l = insn_labels; l != NULL; l = l->next)
1729 assert (S_GET_SEGMENT (l->label) == now_seg);
1730 symbol_set_frag (l->label, frag_now);
1731 val = (valueT) frag_now_fix ();
1732 /* mips16 text labels are stored as odd. */
1733 if (mips_opts.mips16)
1735 S_SET_VALUE (l->label, val);
1738 #ifndef NO_ECOFF_DEBUGGING
1739 if (ECOFF_DEBUGGING)
1740 ecoff_fix_loc (old_frag, old_frag_offset);
1743 else if (prev_nop_frag != NULL)
1745 /* We have a frag holding nops we may be able to remove. If
1746 we don't need any nops, we can decrease the size of
1747 prev_nop_frag by the size of one instruction. If we do
1748 need some nops, we count them in prev_nops_required. */
1749 if (prev_nop_frag_since == 0)
1753 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1754 --prev_nop_frag_holds;
1757 prev_nop_frag_required += nops;
1761 if (prev_prev_nop == 0)
1763 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1764 --prev_nop_frag_holds;
1767 ++prev_nop_frag_required;
1770 if (prev_nop_frag_holds <= prev_nop_frag_required)
1771 prev_nop_frag = NULL;
1773 ++prev_nop_frag_since;
1775 /* Sanity check: by the time we reach the second instruction
1776 after prev_nop_frag, we should have used up all the nops
1777 one way or another. */
1778 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1782 if (*reloc_type > BFD_RELOC_UNUSED)
1784 /* We need to set up a variant frag. */
1785 assert (mips_opts.mips16 && address_expr != NULL);
1786 f = frag_var (rs_machine_dependent, 4, 0,
1787 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1788 mips16_small, mips16_ext,
1790 & INSN_UNCOND_BRANCH_DELAY),
1791 (*prev_insn_reloc_type
1792 == BFD_RELOC_MIPS16_JMP)),
1793 make_expr_symbol (address_expr), 0, NULL);
1795 else if (place != NULL)
1797 else if (mips_opts.mips16
1799 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1801 /* Make sure there is enough room to swap this instruction with
1802 a following jump instruction. */
1808 if (mips_opts.mips16
1809 && mips_opts.noreorder
1810 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1811 as_warn (_("extended instruction in delay slot"));
1816 fixp[0] = fixp[1] = fixp[2] = NULL;
1817 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1819 if (address_expr->X_op == O_constant)
1823 switch (*reloc_type)
1826 ip->insn_opcode |= address_expr->X_add_number;
1829 case BFD_RELOC_MIPS_HIGHEST:
1830 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1832 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1835 case BFD_RELOC_MIPS_HIGHER:
1836 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1837 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1840 case BFD_RELOC_HI16_S:
1841 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1845 case BFD_RELOC_HI16:
1846 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1849 case BFD_RELOC_LO16:
1850 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1853 case BFD_RELOC_MIPS_JMP:
1854 if ((address_expr->X_add_number & 3) != 0)
1855 as_bad (_("jump to misaligned address (0x%lx)"),
1856 (unsigned long) address_expr->X_add_number);
1857 if (address_expr->X_add_number & ~0xfffffff
1858 || address_expr->X_add_number > 0x7fffffc)
1859 as_bad (_("jump address range overflow (0x%lx)"),
1860 (unsigned long) address_expr->X_add_number);
1861 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1864 case BFD_RELOC_MIPS16_JMP:
1865 if ((address_expr->X_add_number & 3) != 0)
1866 as_bad (_("jump to misaligned address (0x%lx)"),
1867 (unsigned long) address_expr->X_add_number);
1868 if (address_expr->X_add_number & ~0xfffffff
1869 || address_expr->X_add_number > 0x7fffffc)
1870 as_bad (_("jump address range overflow (0x%lx)"),
1871 (unsigned long) address_expr->X_add_number);
1873 (((address_expr->X_add_number & 0x7c0000) << 3)
1874 | ((address_expr->X_add_number & 0xf800000) >> 7)
1875 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1878 case BFD_RELOC_16_PCREL:
1879 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1882 case BFD_RELOC_16_PCREL_S2:
1892 /* Don't generate a reloc if we are writing into a variant frag. */
1895 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1897 (*reloc_type == BFD_RELOC_16_PCREL
1898 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1901 /* These relocations can have an addend that won't fit in
1902 4 octets for 64bit assembly. */
1903 if (HAVE_64BIT_GPRS &&
1904 (*reloc_type == BFD_RELOC_16
1905 || *reloc_type == BFD_RELOC_32
1906 || *reloc_type == BFD_RELOC_MIPS_JMP
1907 || *reloc_type == BFD_RELOC_HI16_S
1908 || *reloc_type == BFD_RELOC_LO16
1909 || *reloc_type == BFD_RELOC_GPREL16
1910 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1911 || *reloc_type == BFD_RELOC_GPREL32
1912 || *reloc_type == BFD_RELOC_64
1913 || *reloc_type == BFD_RELOC_CTOR
1914 || *reloc_type == BFD_RELOC_MIPS_SUB
1915 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1916 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1917 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1918 || *reloc_type == BFD_RELOC_MIPS_REL16
1919 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1920 fixp[0]->fx_no_overflow = 1;
1924 struct mips_hi_fixup *hi_fixup;
1926 assert (*reloc_type == BFD_RELOC_HI16_S);
1927 hi_fixup = ((struct mips_hi_fixup *)
1928 xmalloc (sizeof (struct mips_hi_fixup)));
1929 hi_fixup->fixp = fixp[0];
1930 hi_fixup->seg = now_seg;
1931 hi_fixup->next = mips_hi_fixup_list;
1932 mips_hi_fixup_list = hi_fixup;
1935 if (reloc_type[1] != BFD_RELOC_UNUSED)
1937 /* FIXME: This symbol can be one of
1938 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1939 address_expr->X_op = O_absent;
1940 address_expr->X_add_symbol = 0;
1941 address_expr->X_add_number = 0;
1943 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1944 4, address_expr, false,
1947 /* These relocations can have an addend that won't fit in
1948 4 octets for 64bit assembly. */
1949 if (HAVE_64BIT_GPRS &&
1950 (*reloc_type == BFD_RELOC_16
1951 || *reloc_type == BFD_RELOC_32
1952 || *reloc_type == BFD_RELOC_MIPS_JMP
1953 || *reloc_type == BFD_RELOC_HI16_S
1954 || *reloc_type == BFD_RELOC_LO16
1955 || *reloc_type == BFD_RELOC_GPREL16
1956 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1957 || *reloc_type == BFD_RELOC_GPREL32
1958 || *reloc_type == BFD_RELOC_64
1959 || *reloc_type == BFD_RELOC_CTOR
1960 || *reloc_type == BFD_RELOC_MIPS_SUB
1961 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1962 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1963 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1964 || *reloc_type == BFD_RELOC_MIPS_REL16
1965 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1966 fixp[1]->fx_no_overflow = 1;
1968 if (reloc_type[2] != BFD_RELOC_UNUSED)
1970 address_expr->X_op = O_absent;
1971 address_expr->X_add_symbol = 0;
1972 address_expr->X_add_number = 0;
1974 fixp[2] = fix_new_exp (frag_now,
1975 f - frag_now->fr_literal, 4,
1976 address_expr, false,
1979 /* These relocations can have an addend that won't fit in
1980 4 octets for 64bit assembly. */
1981 if (HAVE_64BIT_GPRS &&
1982 (*reloc_type == BFD_RELOC_16
1983 || *reloc_type == BFD_RELOC_32
1984 || *reloc_type == BFD_RELOC_MIPS_JMP
1985 || *reloc_type == BFD_RELOC_HI16_S
1986 || *reloc_type == BFD_RELOC_LO16
1987 || *reloc_type == BFD_RELOC_GPREL16
1988 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1989 || *reloc_type == BFD_RELOC_GPREL32
1990 || *reloc_type == BFD_RELOC_64
1991 || *reloc_type == BFD_RELOC_CTOR
1992 || *reloc_type == BFD_RELOC_MIPS_SUB
1993 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1994 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1995 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1996 || *reloc_type == BFD_RELOC_MIPS_REL16
1997 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1998 fixp[2]->fx_no_overflow = 1;
2005 if (! mips_opts.mips16)
2007 md_number_to_chars (f, ip->insn_opcode, 4);
2009 dwarf2_emit_insn (4);
2012 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2014 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2015 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2017 dwarf2_emit_insn (4);
2024 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2027 md_number_to_chars (f, ip->insn_opcode, 2);
2029 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2033 /* Update the register mask information. */
2034 if (! mips_opts.mips16)
2036 if (pinfo & INSN_WRITE_GPR_D)
2037 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2038 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2039 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2040 if (pinfo & INSN_READ_GPR_S)
2041 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2042 if (pinfo & INSN_WRITE_GPR_31)
2043 mips_gprmask |= 1 << RA;
2044 if (pinfo & INSN_WRITE_FPR_D)
2045 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2046 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2047 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2048 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2049 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2050 if ((pinfo & INSN_READ_FPR_R) != 0)
2051 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2052 if (pinfo & INSN_COP)
2054 /* We don't keep enough information to sort these cases out.
2055 The itbl support does keep this information however, although
2056 we currently don't support itbl fprmats as part of the cop
2057 instruction. May want to add this support in the future. */
2059 /* Never set the bit for $0, which is always zero. */
2060 mips_gprmask &= ~1 << 0;
2064 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2065 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2066 & MIPS16OP_MASK_RX);
2067 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2068 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2069 & MIPS16OP_MASK_RY);
2070 if (pinfo & MIPS16_INSN_WRITE_Z)
2071 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2072 & MIPS16OP_MASK_RZ);
2073 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2074 mips_gprmask |= 1 << TREG;
2075 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2076 mips_gprmask |= 1 << SP;
2077 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2078 mips_gprmask |= 1 << RA;
2079 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2080 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2081 if (pinfo & MIPS16_INSN_READ_Z)
2082 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2083 & MIPS16OP_MASK_MOVE32Z);
2084 if (pinfo & MIPS16_INSN_READ_GPR_X)
2085 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2086 & MIPS16OP_MASK_REGR32);
2089 if (place == NULL && ! mips_opts.noreorder)
2091 /* Filling the branch delay slot is more complex. We try to
2092 switch the branch with the previous instruction, which we can
2093 do if the previous instruction does not set up a condition
2094 that the branch tests and if the branch is not itself the
2095 target of any branch. */
2096 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2097 || (pinfo & INSN_COND_BRANCH_DELAY))
2099 if (mips_optimize < 2
2100 /* If we have seen .set volatile or .set nomove, don't
2102 || mips_opts.nomove != 0
2103 /* If we had to emit any NOP instructions, then we
2104 already know we can not swap. */
2106 /* If we don't even know the previous insn, we can not
2108 || ! prev_insn_valid
2109 /* If the previous insn is already in a branch delay
2110 slot, then we can not swap. */
2111 || prev_insn_is_delay_slot
2112 /* If the previous previous insn was in a .set
2113 noreorder, we can't swap. Actually, the MIPS
2114 assembler will swap in this situation. However, gcc
2115 configured -with-gnu-as will generate code like
2121 in which we can not swap the bne and INSN. If gcc is
2122 not configured -with-gnu-as, it does not output the
2123 .set pseudo-ops. We don't have to check
2124 prev_insn_unreordered, because prev_insn_valid will
2125 be 0 in that case. We don't want to use
2126 prev_prev_insn_valid, because we do want to be able
2127 to swap at the start of a function. */
2128 || prev_prev_insn_unreordered
2129 /* If the branch is itself the target of a branch, we
2130 can not swap. We cheat on this; all we check for is
2131 whether there is a label on this instruction. If
2132 there are any branches to anything other than a
2133 label, users must use .set noreorder. */
2134 || insn_labels != NULL
2135 /* If the previous instruction is in a variant frag, we
2136 can not do the swap. This does not apply to the
2137 mips16, which uses variant frags for different
2139 || (! mips_opts.mips16
2140 && prev_insn_frag->fr_type == rs_machine_dependent)
2141 /* If the branch reads the condition codes, we don't
2142 even try to swap, because in the sequence
2147 we can not swap, and I don't feel like handling that
2149 || (! mips_opts.mips16
2150 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2151 && (pinfo & INSN_READ_COND_CODE))
2152 /* We can not swap with an instruction that requires a
2153 delay slot, becase the target of the branch might
2154 interfere with that instruction. */
2155 || (! mips_opts.mips16
2156 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2158 /* Itbl support may require additional care here. */
2159 & (INSN_LOAD_COPROC_DELAY
2160 | INSN_COPROC_MOVE_DELAY
2161 | INSN_WRITE_COND_CODE)))
2162 || (! (hilo_interlocks
2163 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2167 || (! mips_opts.mips16
2169 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2170 || (! mips_opts.mips16
2171 && mips_opts.isa == ISA_MIPS1
2172 /* Itbl support may require additional care here. */
2173 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2174 /* We can not swap with a branch instruction. */
2176 & (INSN_UNCOND_BRANCH_DELAY
2177 | INSN_COND_BRANCH_DELAY
2178 | INSN_COND_BRANCH_LIKELY))
2179 /* We do not swap with a trap instruction, since it
2180 complicates trap handlers to have the trap
2181 instruction be in a delay slot. */
2182 || (prev_pinfo & INSN_TRAP)
2183 /* If the branch reads a register that the previous
2184 instruction sets, we can not swap. */
2185 || (! mips_opts.mips16
2186 && (prev_pinfo & INSN_WRITE_GPR_T)
2187 && insn_uses_reg (ip,
2188 ((prev_insn.insn_opcode >> OP_SH_RT)
2191 || (! mips_opts.mips16
2192 && (prev_pinfo & INSN_WRITE_GPR_D)
2193 && insn_uses_reg (ip,
2194 ((prev_insn.insn_opcode >> OP_SH_RD)
2197 || (mips_opts.mips16
2198 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2199 && insn_uses_reg (ip,
2200 ((prev_insn.insn_opcode
2202 & MIPS16OP_MASK_RX),
2204 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2205 && insn_uses_reg (ip,
2206 ((prev_insn.insn_opcode
2208 & MIPS16OP_MASK_RY),
2210 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2211 && insn_uses_reg (ip,
2212 ((prev_insn.insn_opcode
2214 & MIPS16OP_MASK_RZ),
2216 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2217 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2218 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2219 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2220 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2221 && insn_uses_reg (ip,
2222 MIPS16OP_EXTRACT_REG32R (prev_insn.
2225 /* If the branch writes a register that the previous
2226 instruction sets, we can not swap (we know that
2227 branches write only to RD or to $31). */
2228 || (! mips_opts.mips16
2229 && (prev_pinfo & INSN_WRITE_GPR_T)
2230 && (((pinfo & INSN_WRITE_GPR_D)
2231 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2232 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2233 || ((pinfo & INSN_WRITE_GPR_31)
2234 && (((prev_insn.insn_opcode >> OP_SH_RT)
2237 || (! mips_opts.mips16
2238 && (prev_pinfo & INSN_WRITE_GPR_D)
2239 && (((pinfo & INSN_WRITE_GPR_D)
2240 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2241 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2242 || ((pinfo & INSN_WRITE_GPR_31)
2243 && (((prev_insn.insn_opcode >> OP_SH_RD)
2246 || (mips_opts.mips16
2247 && (pinfo & MIPS16_INSN_WRITE_31)
2248 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2249 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2250 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2252 /* If the branch writes a register that the previous
2253 instruction reads, we can not swap (we know that
2254 branches only write to RD or to $31). */
2255 || (! mips_opts.mips16
2256 && (pinfo & INSN_WRITE_GPR_D)
2257 && insn_uses_reg (&prev_insn,
2258 ((ip->insn_opcode >> OP_SH_RD)
2261 || (! mips_opts.mips16
2262 && (pinfo & INSN_WRITE_GPR_31)
2263 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2264 || (mips_opts.mips16
2265 && (pinfo & MIPS16_INSN_WRITE_31)
2266 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2267 /* If we are generating embedded PIC code, the branch
2268 might be expanded into a sequence which uses $at, so
2269 we can't swap with an instruction which reads it. */
2270 || (mips_pic == EMBEDDED_PIC
2271 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2272 /* If the previous previous instruction has a load
2273 delay, and sets a register that the branch reads, we
2275 || (! mips_opts.mips16
2276 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2277 /* Itbl support may require additional care here. */
2278 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2279 || (! gpr_interlocks
2280 && (prev_prev_insn.insn_mo->pinfo
2281 & INSN_LOAD_MEMORY_DELAY)))
2282 && insn_uses_reg (ip,
2283 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2286 /* If one instruction sets a condition code and the
2287 other one uses a condition code, we can not swap. */
2288 || ((pinfo & INSN_READ_COND_CODE)
2289 && (prev_pinfo & INSN_WRITE_COND_CODE))
2290 || ((pinfo & INSN_WRITE_COND_CODE)
2291 && (prev_pinfo & INSN_READ_COND_CODE))
2292 /* If the previous instruction uses the PC, we can not
2294 || (mips_opts.mips16
2295 && (prev_pinfo & MIPS16_INSN_READ_PC))
2296 /* If the previous instruction was extended, we can not
2298 || (mips_opts.mips16 && prev_insn_extended)
2299 /* If the previous instruction had a fixup in mips16
2300 mode, we can not swap. This normally means that the
2301 previous instruction was a 4 byte branch anyhow. */
2302 || (mips_opts.mips16 && prev_insn_fixp[0])
2303 /* If the previous instruction is a sync, sync.l, or
2304 sync.p, we can not swap. */
2305 || (prev_pinfo & INSN_SYNC))
2307 /* We could do even better for unconditional branches to
2308 portions of this object file; we could pick up the
2309 instruction at the destination, put it in the delay
2310 slot, and bump the destination address. */
2312 /* Update the previous insn information. */
2313 prev_prev_insn = *ip;
2314 prev_insn.insn_mo = &dummy_opcode;
2318 /* It looks like we can actually do the swap. */
2319 if (! mips_opts.mips16)
2324 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2325 memcpy (temp, prev_f, 4);
2326 memcpy (prev_f, f, 4);
2327 memcpy (f, temp, 4);
2328 if (prev_insn_fixp[0])
2330 prev_insn_fixp[0]->fx_frag = frag_now;
2331 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2333 if (prev_insn_fixp[1])
2335 prev_insn_fixp[1]->fx_frag = frag_now;
2336 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2338 if (prev_insn_fixp[2])
2340 prev_insn_fixp[2]->fx_frag = frag_now;
2341 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2345 fixp[0]->fx_frag = prev_insn_frag;
2346 fixp[0]->fx_where = prev_insn_where;
2350 fixp[1]->fx_frag = prev_insn_frag;
2351 fixp[1]->fx_where = prev_insn_where;
2355 fixp[2]->fx_frag = prev_insn_frag;
2356 fixp[2]->fx_where = prev_insn_where;
2364 assert (prev_insn_fixp[0] == NULL);
2365 assert (prev_insn_fixp[1] == NULL);
2366 assert (prev_insn_fixp[2] == NULL);
2367 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2368 memcpy (temp, prev_f, 2);
2369 memcpy (prev_f, f, 2);
2370 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2372 assert (*reloc_type == BFD_RELOC_UNUSED);
2373 memcpy (f, temp, 2);
2377 memcpy (f, f + 2, 2);
2378 memcpy (f + 2, temp, 2);
2382 fixp[0]->fx_frag = prev_insn_frag;
2383 fixp[0]->fx_where = prev_insn_where;
2387 fixp[1]->fx_frag = prev_insn_frag;
2388 fixp[1]->fx_where = prev_insn_where;
2392 fixp[2]->fx_frag = prev_insn_frag;
2393 fixp[2]->fx_where = prev_insn_where;
2397 /* Update the previous insn information; leave prev_insn
2399 prev_prev_insn = *ip;
2401 prev_insn_is_delay_slot = 1;
2403 /* If that was an unconditional branch, forget the previous
2404 insn information. */
2405 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2407 prev_prev_insn.insn_mo = &dummy_opcode;
2408 prev_insn.insn_mo = &dummy_opcode;
2411 prev_insn_fixp[0] = NULL;
2412 prev_insn_fixp[1] = NULL;
2413 prev_insn_fixp[2] = NULL;
2414 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2415 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2416 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2417 prev_insn_extended = 0;
2419 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2421 /* We don't yet optimize a branch likely. What we should do
2422 is look at the target, copy the instruction found there
2423 into the delay slot, and increment the branch to jump to
2424 the next instruction. */
2426 /* Update the previous insn information. */
2427 prev_prev_insn = *ip;
2428 prev_insn.insn_mo = &dummy_opcode;
2429 prev_insn_fixp[0] = NULL;
2430 prev_insn_fixp[1] = NULL;
2431 prev_insn_fixp[2] = NULL;
2432 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2433 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2434 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2435 prev_insn_extended = 0;
2439 /* Update the previous insn information. */
2441 prev_prev_insn.insn_mo = &dummy_opcode;
2443 prev_prev_insn = prev_insn;
2446 /* Any time we see a branch, we always fill the delay slot
2447 immediately; since this insn is not a branch, we know it
2448 is not in a delay slot. */
2449 prev_insn_is_delay_slot = 0;
2451 prev_insn_fixp[0] = fixp[0];
2452 prev_insn_fixp[1] = fixp[1];
2453 prev_insn_fixp[2] = fixp[2];
2454 prev_insn_reloc_type[0] = reloc_type[0];
2455 prev_insn_reloc_type[1] = reloc_type[1];
2456 prev_insn_reloc_type[2] = reloc_type[2];
2457 if (mips_opts.mips16)
2458 prev_insn_extended = (ip->use_extend
2459 || *reloc_type > BFD_RELOC_UNUSED);
2462 prev_prev_insn_unreordered = prev_insn_unreordered;
2463 prev_insn_unreordered = 0;
2464 prev_insn_frag = frag_now;
2465 prev_insn_where = f - frag_now->fr_literal;
2466 prev_insn_valid = 1;
2468 else if (place == NULL)
2470 /* We need to record a bit of information even when we are not
2471 reordering, in order to determine the base address for mips16
2472 PC relative relocs. */
2473 prev_prev_insn = prev_insn;
2475 prev_insn_reloc_type[0] = reloc_type[0];
2476 prev_insn_reloc_type[1] = reloc_type[1];
2477 prev_insn_reloc_type[2] = reloc_type[2];
2478 prev_prev_insn_unreordered = prev_insn_unreordered;
2479 prev_insn_unreordered = 1;
2482 /* We just output an insn, so the next one doesn't have a label. */
2483 mips_clear_insn_labels ();
2485 /* We must ensure that a fixup associated with an unmatched %hi
2486 reloc does not become a variant frag. Otherwise, the
2487 rearrangement of %hi relocs in frob_file may confuse
2491 frag_wane (frag_now);
2496 /* This function forgets that there was any previous instruction or
2497 label. If PRESERVE is non-zero, it remembers enough information to
2498 know whether nops are needed before a noreorder section. */
2501 mips_no_prev_insn (preserve)
2506 prev_insn.insn_mo = &dummy_opcode;
2507 prev_prev_insn.insn_mo = &dummy_opcode;
2508 prev_nop_frag = NULL;
2509 prev_nop_frag_holds = 0;
2510 prev_nop_frag_required = 0;
2511 prev_nop_frag_since = 0;
2513 prev_insn_valid = 0;
2514 prev_insn_is_delay_slot = 0;
2515 prev_insn_unreordered = 0;
2516 prev_insn_extended = 0;
2517 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2518 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2519 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2520 prev_prev_insn_unreordered = 0;
2521 mips_clear_insn_labels ();
2524 /* This function must be called whenever we turn on noreorder or emit
2525 something other than instructions. It inserts any NOPS which might
2526 be needed by the previous instruction, and clears the information
2527 kept for the previous instructions. The INSNS parameter is true if
2528 instructions are to follow. */
2531 mips_emit_delays (insns)
2534 if (! mips_opts.noreorder)
2539 if ((! mips_opts.mips16
2540 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2541 && (! cop_interlocks
2542 && (prev_insn.insn_mo->pinfo
2543 & (INSN_LOAD_COPROC_DELAY
2544 | INSN_COPROC_MOVE_DELAY
2545 | INSN_WRITE_COND_CODE))))
2546 || (! hilo_interlocks
2547 && (prev_insn.insn_mo->pinfo
2550 || (! mips_opts.mips16
2552 && (prev_insn.insn_mo->pinfo
2553 & INSN_LOAD_MEMORY_DELAY))
2554 || (! mips_opts.mips16
2555 && mips_opts.isa == ISA_MIPS1
2556 && (prev_insn.insn_mo->pinfo
2557 & INSN_COPROC_MEMORY_DELAY)))
2559 /* Itbl support may require additional care here. */
2561 if ((! mips_opts.mips16
2562 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2563 && (! cop_interlocks
2564 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2565 || (! hilo_interlocks
2566 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2567 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2570 if (prev_insn_unreordered)
2573 else if ((! mips_opts.mips16
2574 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2575 && (! cop_interlocks
2576 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2577 || (! hilo_interlocks
2578 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2579 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2581 /* Itbl support may require additional care here. */
2582 if (! prev_prev_insn_unreordered)
2588 struct insn_label_list *l;
2592 /* Record the frag which holds the nop instructions, so
2593 that we can remove them if we don't need them. */
2594 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2595 prev_nop_frag = frag_now;
2596 prev_nop_frag_holds = nops;
2597 prev_nop_frag_required = 0;
2598 prev_nop_frag_since = 0;
2601 for (; nops > 0; --nops)
2606 /* Move on to a new frag, so that it is safe to simply
2607 decrease the size of prev_nop_frag. */
2608 frag_wane (frag_now);
2612 for (l = insn_labels; l != NULL; l = l->next)
2616 assert (S_GET_SEGMENT (l->label) == now_seg);
2617 symbol_set_frag (l->label, frag_now);
2618 val = (valueT) frag_now_fix ();
2619 /* mips16 text labels are stored as odd. */
2620 if (mips_opts.mips16)
2622 S_SET_VALUE (l->label, val);
2627 /* Mark instruction labels in mips16 mode. */
2629 mips16_mark_labels ();
2631 mips_no_prev_insn (insns);
2634 /* Build an instruction created by a macro expansion. This is passed
2635 a pointer to the count of instructions created so far, an
2636 expression, the name of the instruction to build, an operand format
2637 string, and corresponding arguments. */
2641 macro_build (char *place,
2649 macro_build (place, counter, ep, name, fmt, va_alist)
2658 struct mips_cl_insn insn;
2659 bfd_reloc_code_real_type r[3];
2663 va_start (args, fmt);
2669 * If the macro is about to expand into a second instruction,
2670 * print a warning if needed. We need to pass ip as a parameter
2671 * to generate a better warning message here...
2673 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2674 as_warn (_("Macro instruction expanded into multiple instructions"));
2677 * If the macro is about to expand into a second instruction,
2678 * and it is in a delay slot, print a warning.
2682 && mips_opts.noreorder
2683 && (prev_prev_insn.insn_mo->pinfo
2684 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2685 | INSN_COND_BRANCH_LIKELY)) != 0)
2686 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2689 ++*counter; /* bump instruction counter */
2691 if (mips_opts.mips16)
2693 mips16_macro_build (place, counter, ep, name, fmt, args);
2698 r[0] = BFD_RELOC_UNUSED;
2699 r[1] = BFD_RELOC_UNUSED;
2700 r[2] = BFD_RELOC_UNUSED;
2701 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2702 assert (insn.insn_mo);
2703 assert (strcmp (name, insn.insn_mo->name) == 0);
2705 /* Search until we get a match for NAME. */
2708 /* It is assumed here that macros will never generate
2709 MDMX or MIPS-3D instructions. */
2710 if (strcmp (fmt, insn.insn_mo->args) == 0
2711 && insn.insn_mo->pinfo != INSN_MACRO
2712 && OPCODE_IS_MEMBER (insn.insn_mo,
2714 | (mips_opts.mips16 ? INSN_MIPS16 : 0)),
2716 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2720 assert (insn.insn_mo->name);
2721 assert (strcmp (name, insn.insn_mo->name) == 0);
2724 insn.insn_opcode = insn.insn_mo->match;
2740 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2744 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2749 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2754 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2759 int tmp = va_arg (args, int);
2761 insn.insn_opcode |= tmp << OP_SH_RT;
2762 insn.insn_opcode |= tmp << OP_SH_RD;
2768 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2775 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2779 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2783 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2787 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2791 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2798 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2804 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2805 assert (*r == BFD_RELOC_GPREL16
2806 || *r == BFD_RELOC_MIPS_LITERAL
2807 || *r == BFD_RELOC_MIPS_HIGHER
2808 || *r == BFD_RELOC_HI16_S
2809 || *r == BFD_RELOC_LO16
2810 || *r == BFD_RELOC_MIPS_GOT16
2811 || *r == BFD_RELOC_MIPS_CALL16
2812 || *r == BFD_RELOC_MIPS_GOT_DISP
2813 || *r == BFD_RELOC_MIPS_GOT_PAGE
2814 || *r == BFD_RELOC_MIPS_GOT_OFST
2815 || *r == BFD_RELOC_MIPS_GOT_LO16
2816 || *r == BFD_RELOC_MIPS_CALL_LO16
2817 || (ep->X_op == O_subtract
2818 && *r == BFD_RELOC_PCREL_LO16));
2822 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2824 && (ep->X_op == O_constant
2825 || (ep->X_op == O_symbol
2826 && (*r == BFD_RELOC_MIPS_HIGHEST
2827 || *r == BFD_RELOC_HI16_S
2828 || *r == BFD_RELOC_HI16
2829 || *r == BFD_RELOC_GPREL16
2830 || *r == BFD_RELOC_MIPS_GOT_HI16
2831 || *r == BFD_RELOC_MIPS_CALL_HI16))
2832 || (ep->X_op == O_subtract
2833 && *r == BFD_RELOC_PCREL_HI16_S)));
2837 assert (ep != NULL);
2839 * This allows macro() to pass an immediate expression for
2840 * creating short branches without creating a symbol.
2841 * Note that the expression still might come from the assembly
2842 * input, in which case the value is not checked for range nor
2843 * is a relocation entry generated (yuck).
2845 if (ep->X_op == O_constant)
2847 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2851 if (mips_pic == EMBEDDED_PIC)
2852 *r = BFD_RELOC_16_PCREL_S2;
2854 *r = BFD_RELOC_16_PCREL;
2858 assert (ep != NULL);
2859 *r = BFD_RELOC_MIPS_JMP;
2863 insn.insn_opcode |= va_arg (args, unsigned long);
2872 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2874 append_insn (place, &insn, ep, r, false);
2878 mips16_macro_build (place, counter, ep, name, fmt, args)
2880 int *counter ATTRIBUTE_UNUSED;
2886 struct mips_cl_insn insn;
2887 bfd_reloc_code_real_type r[3]
2888 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2890 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2891 assert (insn.insn_mo);
2892 assert (strcmp (name, insn.insn_mo->name) == 0);
2894 while (strcmp (fmt, insn.insn_mo->args) != 0
2895 || insn.insn_mo->pinfo == INSN_MACRO)
2898 assert (insn.insn_mo->name);
2899 assert (strcmp (name, insn.insn_mo->name) == 0);
2902 insn.insn_opcode = insn.insn_mo->match;
2903 insn.use_extend = false;
2922 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2927 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2931 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2935 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2945 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2952 regno = va_arg (args, int);
2953 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2954 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2975 assert (ep != NULL);
2977 if (ep->X_op != O_constant)
2978 *r = (int) BFD_RELOC_UNUSED + c;
2981 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2982 false, &insn.insn_opcode, &insn.use_extend,
2985 *r = BFD_RELOC_UNUSED;
2991 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2998 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3000 append_insn (place, &insn, ep, r, false);
3004 * Generate a "jalr" instruction with a relocation hint to the called
3005 * function. This occurs in NewABI PIC code.
3008 macro_build_jalr (icnt, ep)
3014 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3017 fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR);
3021 * Generate a "lui" instruction.
3024 macro_build_lui (place, counter, ep, regnum)
3030 expressionS high_expr;
3031 struct mips_cl_insn insn;
3032 bfd_reloc_code_real_type r[3]
3033 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3034 const char *name = "lui";
3035 const char *fmt = "t,u";
3037 assert (! mips_opts.mips16);
3043 high_expr.X_op = O_constant;
3044 high_expr.X_add_number = ep->X_add_number;
3047 if (high_expr.X_op == O_constant)
3049 /* we can compute the instruction now without a relocation entry */
3050 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3052 *r = BFD_RELOC_UNUSED;
3054 else if (! HAVE_NEWABI)
3056 assert (ep->X_op == O_symbol);
3057 /* _gp_disp is a special case, used from s_cpload. */
3058 assert (mips_pic == NO_PIC
3059 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3060 *r = BFD_RELOC_HI16_S;
3064 * If the macro is about to expand into a second instruction,
3065 * print a warning if needed. We need to pass ip as a parameter
3066 * to generate a better warning message here...
3068 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3069 as_warn (_("Macro instruction expanded into multiple instructions"));
3072 ++*counter; /* bump instruction counter */
3074 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3075 assert (insn.insn_mo);
3076 assert (strcmp (name, insn.insn_mo->name) == 0);
3077 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3079 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3080 if (*r == BFD_RELOC_UNUSED)
3082 insn.insn_opcode |= high_expr.X_add_number;
3083 append_insn (place, &insn, NULL, r, false);
3086 append_insn (place, &insn, &high_expr, r, false);
3090 * Generates code to set the $at register to true (one)
3091 * if reg is less than the immediate expression.
3094 set_at (counter, reg, unsignedp)
3099 if (imm_expr.X_op == O_constant
3100 && imm_expr.X_add_number >= -0x8000
3101 && imm_expr.X_add_number < 0x8000)
3102 macro_build ((char *) NULL, counter, &imm_expr,
3103 unsignedp ? "sltiu" : "slti",
3104 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3107 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3108 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3109 unsignedp ? "sltu" : "slt",
3110 "d,v,t", AT, reg, AT);
3114 /* Warn if an expression is not a constant. */
3117 check_absolute_expr (ip, ex)
3118 struct mips_cl_insn *ip;
3121 if (ex->X_op == O_big)
3122 as_bad (_("unsupported large constant"));
3123 else if (ex->X_op != O_constant)
3124 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3127 /* Count the leading zeroes by performing a binary chop. This is a
3128 bulky bit of source, but performance is a LOT better for the
3129 majority of values than a simple loop to count the bits:
3130 for (lcnt = 0; (lcnt < 32); lcnt++)
3131 if ((v) & (1 << (31 - lcnt)))
3133 However it is not code size friendly, and the gain will drop a bit
3134 on certain cached systems.
3136 #define COUNT_TOP_ZEROES(v) \
3137 (((v) & ~0xffff) == 0 \
3138 ? ((v) & ~0xff) == 0 \
3139 ? ((v) & ~0xf) == 0 \
3140 ? ((v) & ~0x3) == 0 \
3141 ? ((v) & ~0x1) == 0 \
3146 : ((v) & ~0x7) == 0 \
3149 : ((v) & ~0x3f) == 0 \
3150 ? ((v) & ~0x1f) == 0 \
3153 : ((v) & ~0x7f) == 0 \
3156 : ((v) & ~0xfff) == 0 \
3157 ? ((v) & ~0x3ff) == 0 \
3158 ? ((v) & ~0x1ff) == 0 \
3161 : ((v) & ~0x7ff) == 0 \
3164 : ((v) & ~0x3fff) == 0 \
3165 ? ((v) & ~0x1fff) == 0 \
3168 : ((v) & ~0x7fff) == 0 \
3171 : ((v) & ~0xffffff) == 0 \
3172 ? ((v) & ~0xfffff) == 0 \
3173 ? ((v) & ~0x3ffff) == 0 \
3174 ? ((v) & ~0x1ffff) == 0 \
3177 : ((v) & ~0x7ffff) == 0 \
3180 : ((v) & ~0x3fffff) == 0 \
3181 ? ((v) & ~0x1fffff) == 0 \
3184 : ((v) & ~0x7fffff) == 0 \
3187 : ((v) & ~0xfffffff) == 0 \
3188 ? ((v) & ~0x3ffffff) == 0 \
3189 ? ((v) & ~0x1ffffff) == 0 \
3192 : ((v) & ~0x7ffffff) == 0 \
3195 : ((v) & ~0x3fffffff) == 0 \
3196 ? ((v) & ~0x1fffffff) == 0 \
3199 : ((v) & ~0x7fffffff) == 0 \
3203 /* Is the given value a sign-extended 32-bit value? */
3204 #define IS_SEXT_32BIT_NUM(x) \
3205 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3206 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3209 * This routine generates the least number of instructions neccessary to load
3210 * an absolute expression value into a register.
3213 load_register (counter, reg, ep, dbl)
3220 expressionS hi32, lo32;
3222 if (ep->X_op != O_big)
3224 assert (ep->X_op == O_constant);
3225 if (ep->X_add_number < 0x8000
3226 && (ep->X_add_number >= 0
3227 || (ep->X_add_number >= -0x8000
3230 || sizeof (ep->X_add_number) > 4))))
3232 /* We can handle 16 bit signed values with an addiu to
3233 $zero. No need to ever use daddiu here, since $zero and
3234 the result are always correct in 32 bit mode. */
3235 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3236 (int) BFD_RELOC_LO16);
3239 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3241 /* We can handle 16 bit unsigned values with an ori to
3243 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3244 (int) BFD_RELOC_LO16);
3247 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3250 || sizeof (ep->X_add_number) > 4
3251 || (ep->X_add_number & 0x80000000) == 0))
3252 || ((HAVE_32BIT_GPRS || ! dbl)
3253 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3256 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3257 == ~ (offsetT) 0xffffffff)))
3259 /* 32 bit values require an lui. */
3260 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3261 (int) BFD_RELOC_HI16);
3262 if ((ep->X_add_number & 0xffff) != 0)
3263 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3264 (int) BFD_RELOC_LO16);
3269 /* The value is larger than 32 bits. */
3271 if (HAVE_32BIT_GPRS)
3273 as_bad (_("Number (0x%lx) larger than 32 bits"),
3274 (unsigned long) ep->X_add_number);
3275 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3276 (int) BFD_RELOC_LO16);
3280 if (ep->X_op != O_big)
3283 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3284 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3285 hi32.X_add_number &= 0xffffffff;
3287 lo32.X_add_number &= 0xffffffff;
3291 assert (ep->X_add_number > 2);
3292 if (ep->X_add_number == 3)
3293 generic_bignum[3] = 0;
3294 else if (ep->X_add_number > 4)
3295 as_bad (_("Number larger than 64 bits"));
3296 lo32.X_op = O_constant;
3297 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3298 hi32.X_op = O_constant;
3299 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3302 if (hi32.X_add_number == 0)
3307 unsigned long hi, lo;
3309 if (hi32.X_add_number == (offsetT) 0xffffffff)
3311 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3313 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3314 reg, 0, (int) BFD_RELOC_LO16);
3317 if (lo32.X_add_number & 0x80000000)
3319 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3320 (int) BFD_RELOC_HI16);
3321 if (lo32.X_add_number & 0xffff)
3322 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3323 reg, reg, (int) BFD_RELOC_LO16);
3328 /* Check for 16bit shifted constant. We know that hi32 is
3329 non-zero, so start the mask on the first bit of the hi32
3334 unsigned long himask, lomask;
3338 himask = 0xffff >> (32 - shift);
3339 lomask = (0xffff << shift) & 0xffffffff;
3343 himask = 0xffff << (shift - 32);
3346 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3347 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3351 tmp.X_op = O_constant;
3353 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3354 | (lo32.X_add_number >> shift));
3356 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3357 macro_build ((char *) NULL, counter, &tmp,
3358 "ori", "t,r,i", reg, 0,
3359 (int) BFD_RELOC_LO16);
3360 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3361 (shift >= 32) ? "dsll32" : "dsll",
3363 (shift >= 32) ? shift - 32 : shift);
3368 while (shift <= (64 - 16));
3370 /* Find the bit number of the lowest one bit, and store the
3371 shifted value in hi/lo. */
3372 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3373 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3377 while ((lo & 1) == 0)
3382 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3388 while ((hi & 1) == 0)
3397 /* Optimize if the shifted value is a (power of 2) - 1. */
3398 if ((hi == 0 && ((lo + 1) & lo) == 0)
3399 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3401 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3406 /* This instruction will set the register to be all
3408 tmp.X_op = O_constant;
3409 tmp.X_add_number = (offsetT) -1;
3410 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3411 reg, 0, (int) BFD_RELOC_LO16);
3415 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3416 (bit >= 32) ? "dsll32" : "dsll",
3418 (bit >= 32) ? bit - 32 : bit);
3420 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3421 (shift >= 32) ? "dsrl32" : "dsrl",
3423 (shift >= 32) ? shift - 32 : shift);
3428 /* Sign extend hi32 before calling load_register, because we can
3429 generally get better code when we load a sign extended value. */
3430 if ((hi32.X_add_number & 0x80000000) != 0)
3431 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3432 load_register (counter, reg, &hi32, 0);
3435 if ((lo32.X_add_number & 0xffff0000) == 0)
3439 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3440 "dsll32", "d,w,<", reg, freg, 0);
3448 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3450 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3451 (int) BFD_RELOC_HI16);
3452 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3453 "dsrl32", "d,w,<", reg, reg, 0);
3459 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3460 "d,w,<", reg, freg, 16);
3464 mid16.X_add_number >>= 16;
3465 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3466 freg, (int) BFD_RELOC_LO16);
3467 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3468 "d,w,<", reg, reg, 16);
3471 if ((lo32.X_add_number & 0xffff) != 0)
3472 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3473 (int) BFD_RELOC_LO16);
3476 /* Load an address into a register. */
3479 load_address (counter, reg, ep, used_at)
3487 if (ep->X_op != O_constant
3488 && ep->X_op != O_symbol)
3490 as_bad (_("expression too complex"));
3491 ep->X_op = O_constant;
3494 if (ep->X_op == O_constant)
3496 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3500 if (mips_pic == NO_PIC)
3502 /* If this is a reference to a GP relative symbol, we want
3503 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3505 lui $reg,<sym> (BFD_RELOC_HI16_S)
3506 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3507 If we have an addend, we always use the latter form.
3509 With 64bit address space and a usable $at we want
3510 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3511 lui $at,<sym> (BFD_RELOC_HI16_S)
3512 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3513 daddiu $at,<sym> (BFD_RELOC_LO16)
3517 If $at is already in use, we use an path which is suboptimal
3518 on superscalar processors.
3519 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3520 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3522 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3524 daddiu $reg,<sym> (BFD_RELOC_LO16)
3526 if (HAVE_64BIT_ADDRESSES)
3528 /* We don't do GP optimization for now because RELAX_ENCODE can't
3529 hold the data for such large chunks. */
3531 if (*used_at == 0 && ! mips_opts.noat)
3533 macro_build (p, counter, ep, "lui", "t,u",
3534 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3535 macro_build (p, counter, ep, "lui", "t,u",
3536 AT, (int) BFD_RELOC_HI16_S);
3537 macro_build (p, counter, ep, "daddiu", "t,r,j",
3538 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3539 macro_build (p, counter, ep, "daddiu", "t,r,j",
3540 AT, AT, (int) BFD_RELOC_LO16);
3541 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3542 "d,w,<", reg, reg, 0);
3543 macro_build (p, counter, (expressionS *) NULL, "daddu",
3544 "d,v,t", reg, reg, AT);
3549 macro_build (p, counter, ep, "lui", "t,u",
3550 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3551 macro_build (p, counter, ep, "daddiu", "t,r,j",
3552 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3553 macro_build (p, counter, (expressionS *) NULL, "dsll",
3554 "d,w,<", reg, reg, 16);
3555 macro_build (p, counter, ep, "daddiu", "t,r,j",
3556 reg, reg, (int) BFD_RELOC_HI16_S);
3557 macro_build (p, counter, (expressionS *) NULL, "dsll",
3558 "d,w,<", reg, reg, 16);
3559 macro_build (p, counter, ep, "daddiu", "t,r,j",
3560 reg, reg, (int) BFD_RELOC_LO16);
3565 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3566 && ! nopic_need_relax (ep->X_add_symbol, 1))
3569 macro_build ((char *) NULL, counter, ep,
3570 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3571 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3572 p = frag_var (rs_machine_dependent, 8, 0,
3573 RELAX_ENCODE (4, 8, 0, 4, 0,
3574 mips_opts.warn_about_macros),
3575 ep->X_add_symbol, 0, NULL);
3577 macro_build_lui (p, counter, ep, reg);
3580 macro_build (p, counter, ep,
3581 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3582 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3585 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3589 /* If this is a reference to an external symbol, we want
3590 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3592 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3594 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3595 If there is a constant, it must be added in after. */
3596 ex.X_add_number = ep->X_add_number;
3597 ep->X_add_number = 0;
3599 macro_build ((char *) NULL, counter, ep,
3600 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3601 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3602 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3603 p = frag_var (rs_machine_dependent, 4, 0,
3604 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3605 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3606 macro_build (p, counter, ep,
3607 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3608 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3609 if (ex.X_add_number != 0)
3611 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3612 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3613 ex.X_op = O_constant;
3614 macro_build ((char *) NULL, counter, &ex,
3615 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3616 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3619 else if (mips_pic == SVR4_PIC)
3624 /* This is the large GOT case. If this is a reference to an
3625 external symbol, we want
3626 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3628 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3629 Otherwise, for a reference to a local symbol, we want
3630 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3632 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3633 If we have NewABI, we want
3634 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3635 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3636 If there is a constant, it must be added in after. */
3637 ex.X_add_number = ep->X_add_number;
3638 ep->X_add_number = 0;
3641 macro_build ((char *) NULL, counter, ep,
3642 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3643 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3644 macro_build (p, counter, ep,
3645 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3646 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3650 if (reg_needs_delay (mips_gp_register))
3655 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3656 (int) BFD_RELOC_MIPS_GOT_HI16);
3657 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3658 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3659 reg, mips_gp_register);
3660 macro_build ((char *) NULL, counter, ep,
3661 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3662 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3663 p = frag_var (rs_machine_dependent, 12 + off, 0,
3664 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3665 mips_opts.warn_about_macros),
3666 ep->X_add_symbol, 0, NULL);
3669 /* We need a nop before loading from $gp. This special
3670 check is required because the lui which starts the main
3671 instruction stream does not refer to $gp, and so will not
3672 insert the nop which may be required. */
3673 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3676 macro_build (p, counter, ep,
3677 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3678 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3680 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3682 macro_build (p, counter, ep,
3683 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3684 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3687 if (ex.X_add_number != 0)
3689 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3690 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3691 ex.X_op = O_constant;
3692 macro_build ((char *) NULL, counter, &ex,
3693 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3694 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3697 else if (mips_pic == EMBEDDED_PIC)
3700 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3702 macro_build ((char *) NULL, counter, ep,
3703 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3704 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3710 /* Move the contents of register SOURCE into register DEST. */
3713 move_register (counter, dest, source)
3718 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3719 HAVE_32BIT_GPRS ? "addu" : "daddu",
3720 "d,v,t", dest, source, 0);
3725 * This routine implements the seemingly endless macro or synthesized
3726 * instructions and addressing modes in the mips assembly language. Many
3727 * of these macros are simple and are similar to each other. These could
3728 * probably be handled by some kind of table or grammer aproach instead of
3729 * this verbose method. Others are not simple macros but are more like
3730 * optimizing code generation.
3731 * One interesting optimization is when several store macros appear
3732 * consecutivly that would load AT with the upper half of the same address.
3733 * The ensuing load upper instructions are ommited. This implies some kind
3734 * of global optimization. We currently only optimize within a single macro.
3735 * For many of the load and store macros if the address is specified as a
3736 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3737 * first load register 'at' with zero and use it as the base register. The
3738 * mips assembler simply uses register $zero. Just one tiny optimization
3743 struct mips_cl_insn *ip;
3745 register int treg, sreg, dreg, breg;
3761 bfd_reloc_code_real_type r;
3762 int hold_mips_optimize;
3764 assert (! mips_opts.mips16);
3766 treg = (ip->insn_opcode >> 16) & 0x1f;
3767 dreg = (ip->insn_opcode >> 11) & 0x1f;
3768 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3769 mask = ip->insn_mo->mask;
3771 expr1.X_op = O_constant;
3772 expr1.X_op_symbol = NULL;
3773 expr1.X_add_symbol = NULL;
3774 expr1.X_add_number = 1;
3786 mips_emit_delays (true);
3787 ++mips_opts.noreorder;
3788 mips_any_noreorder = 1;
3790 expr1.X_add_number = 8;
3791 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3793 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3796 move_register (&icnt, dreg, sreg);
3797 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3798 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3800 --mips_opts.noreorder;
3821 if (imm_expr.X_op == O_constant
3822 && imm_expr.X_add_number >= -0x8000
3823 && imm_expr.X_add_number < 0x8000)
3825 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3826 (int) BFD_RELOC_LO16);
3829 load_register (&icnt, AT, &imm_expr, dbl);
3830 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3850 if (imm_expr.X_op == O_constant
3851 && imm_expr.X_add_number >= 0
3852 && imm_expr.X_add_number < 0x10000)
3854 if (mask != M_NOR_I)
3855 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3856 sreg, (int) BFD_RELOC_LO16);
3859 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3860 treg, sreg, (int) BFD_RELOC_LO16);
3861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3862 "d,v,t", treg, treg, 0);
3867 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3868 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3886 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3888 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3892 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3893 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3901 macro_build ((char *) NULL, &icnt, &offset_expr,
3902 likely ? "bgezl" : "bgez", "s,p", sreg);
3907 macro_build ((char *) NULL, &icnt, &offset_expr,
3908 likely ? "blezl" : "blez", "s,p", treg);
3911 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3913 macro_build ((char *) NULL, &icnt, &offset_expr,
3914 likely ? "beql" : "beq", "s,t,p", AT, 0);
3920 /* check for > max integer */
3921 maxnum = 0x7fffffff;
3922 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3929 if (imm_expr.X_op == O_constant
3930 && imm_expr.X_add_number >= maxnum
3931 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3934 /* result is always false */
3938 as_warn (_("Branch %s is always false (nop)"),
3940 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3946 as_warn (_("Branch likely %s is always false"),
3948 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3953 if (imm_expr.X_op != O_constant)
3954 as_bad (_("Unsupported large constant"));
3955 ++imm_expr.X_add_number;
3959 if (mask == M_BGEL_I)
3961 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3963 macro_build ((char *) NULL, &icnt, &offset_expr,
3964 likely ? "bgezl" : "bgez", "s,p", sreg);
3967 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3969 macro_build ((char *) NULL, &icnt, &offset_expr,
3970 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3973 maxnum = 0x7fffffff;
3974 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3981 maxnum = - maxnum - 1;
3982 if (imm_expr.X_op == O_constant
3983 && imm_expr.X_add_number <= maxnum
3984 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3987 /* result is always true */
3988 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3989 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
3992 set_at (&icnt, sreg, 0);
3993 macro_build ((char *) NULL, &icnt, &offset_expr,
3994 likely ? "beql" : "beq", "s,t,p", AT, 0);
4004 macro_build ((char *) NULL, &icnt, &offset_expr,
4005 likely ? "beql" : "beq", "s,t,p", 0, treg);
4008 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4009 "d,v,t", AT, sreg, treg);
4010 macro_build ((char *) NULL, &icnt, &offset_expr,
4011 likely ? "beql" : "beq", "s,t,p", AT, 0);
4019 && imm_expr.X_op == O_constant
4020 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4022 if (imm_expr.X_op != O_constant)
4023 as_bad (_("Unsupported large constant"));
4024 ++imm_expr.X_add_number;
4028 if (mask == M_BGEUL_I)
4030 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4032 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4034 macro_build ((char *) NULL, &icnt, &offset_expr,
4035 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4038 set_at (&icnt, sreg, 1);
4039 macro_build ((char *) NULL, &icnt, &offset_expr,
4040 likely ? "beql" : "beq", "s,t,p", AT, 0);
4048 macro_build ((char *) NULL, &icnt, &offset_expr,
4049 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4054 macro_build ((char *) NULL, &icnt, &offset_expr,
4055 likely ? "bltzl" : "bltz", "s,p", treg);
4058 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4060 macro_build ((char *) NULL, &icnt, &offset_expr,
4061 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4069 macro_build ((char *) NULL, &icnt, &offset_expr,
4070 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4075 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4076 "d,v,t", AT, treg, sreg);
4077 macro_build ((char *) NULL, &icnt, &offset_expr,
4078 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4086 macro_build ((char *) NULL, &icnt, &offset_expr,
4087 likely ? "blezl" : "blez", "s,p", sreg);
4092 macro_build ((char *) NULL, &icnt, &offset_expr,
4093 likely ? "bgezl" : "bgez", "s,p", treg);
4096 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4098 macro_build ((char *) NULL, &icnt, &offset_expr,
4099 likely ? "beql" : "beq", "s,t,p", AT, 0);
4105 maxnum = 0x7fffffff;
4106 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4113 if (imm_expr.X_op == O_constant
4114 && imm_expr.X_add_number >= maxnum
4115 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4117 if (imm_expr.X_op != O_constant)
4118 as_bad (_("Unsupported large constant"));
4119 ++imm_expr.X_add_number;
4123 if (mask == M_BLTL_I)
4125 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4127 macro_build ((char *) NULL, &icnt, &offset_expr,
4128 likely ? "bltzl" : "bltz", "s,p", sreg);
4131 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4133 macro_build ((char *) NULL, &icnt, &offset_expr,
4134 likely ? "blezl" : "blez", "s,p", sreg);
4137 set_at (&icnt, sreg, 0);
4138 macro_build ((char *) NULL, &icnt, &offset_expr,
4139 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4147 macro_build ((char *) NULL, &icnt, &offset_expr,
4148 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4153 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4154 "d,v,t", AT, treg, sreg);
4155 macro_build ((char *) NULL, &icnt, &offset_expr,
4156 likely ? "beql" : "beq", "s,t,p", AT, 0);
4164 && imm_expr.X_op == O_constant
4165 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4167 if (imm_expr.X_op != O_constant)
4168 as_bad (_("Unsupported large constant"));
4169 ++imm_expr.X_add_number;
4173 if (mask == M_BLTUL_I)
4175 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4177 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4179 macro_build ((char *) NULL, &icnt, &offset_expr,
4180 likely ? "beql" : "beq",
4184 set_at (&icnt, sreg, 1);
4185 macro_build ((char *) NULL, &icnt, &offset_expr,
4186 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4194 macro_build ((char *) NULL, &icnt, &offset_expr,
4195 likely ? "bltzl" : "bltz", "s,p", sreg);
4200 macro_build ((char *) NULL, &icnt, &offset_expr,
4201 likely ? "bgtzl" : "bgtz", "s,p", treg);
4204 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4206 macro_build ((char *) NULL, &icnt, &offset_expr,
4207 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4217 macro_build ((char *) NULL, &icnt, &offset_expr,
4218 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4221 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4224 macro_build ((char *) NULL, &icnt, &offset_expr,
4225 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4240 as_warn (_("Divide by zero."));
4242 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4245 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4250 mips_emit_delays (true);
4251 ++mips_opts.noreorder;
4252 mips_any_noreorder = 1;
4255 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4256 "s,t,q", treg, 0, 7);
4257 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4258 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4262 expr1.X_add_number = 8;
4263 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4264 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4265 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4266 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4269 expr1.X_add_number = -1;
4270 macro_build ((char *) NULL, &icnt, &expr1,
4271 dbl ? "daddiu" : "addiu",
4272 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4273 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4274 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4277 expr1.X_add_number = 1;
4278 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4279 (int) BFD_RELOC_LO16);
4280 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4281 "d,w,<", AT, AT, 31);
4285 expr1.X_add_number = 0x80000000;
4286 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4287 (int) BFD_RELOC_HI16);
4291 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4292 "s,t,q", sreg, AT, 6);
4293 /* We want to close the noreorder block as soon as possible, so
4294 that later insns are available for delay slot filling. */
4295 --mips_opts.noreorder;
4299 expr1.X_add_number = 8;
4300 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4301 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4304 /* We want to close the noreorder block as soon as possible, so
4305 that later insns are available for delay slot filling. */
4306 --mips_opts.noreorder;
4308 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4311 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4350 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4352 as_warn (_("Divide by zero."));
4354 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4357 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4361 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4363 if (strcmp (s2, "mflo") == 0)
4364 move_register (&icnt, dreg, sreg);
4366 move_register (&icnt, dreg, 0);
4369 if (imm_expr.X_op == O_constant
4370 && imm_expr.X_add_number == -1
4371 && s[strlen (s) - 1] != 'u')
4373 if (strcmp (s2, "mflo") == 0)
4375 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4376 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4379 move_register (&icnt, dreg, 0);
4383 load_register (&icnt, AT, &imm_expr, dbl);
4384 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4386 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4405 mips_emit_delays (true);
4406 ++mips_opts.noreorder;
4407 mips_any_noreorder = 1;
4410 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4411 "s,t,q", treg, 0, 7);
4412 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4414 /* We want to close the noreorder block as soon as possible, so
4415 that later insns are available for delay slot filling. */
4416 --mips_opts.noreorder;
4420 expr1.X_add_number = 8;
4421 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4422 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4425 /* We want to close the noreorder block as soon as possible, so
4426 that later insns are available for delay slot filling. */
4427 --mips_opts.noreorder;
4428 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4431 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4437 /* Load the address of a symbol into a register. If breg is not
4438 zero, we then add a base register to it. */
4440 if (dbl && HAVE_32BIT_GPRS)
4441 as_warn (_("dla used to load 32-bit register"));
4443 if (! dbl && HAVE_64BIT_OBJECTS)
4444 as_warn (_("la used to load 64-bit address"));
4446 if (offset_expr.X_op == O_constant
4447 && offset_expr.X_add_number >= -0x8000
4448 && offset_expr.X_add_number < 0x8000)
4450 macro_build ((char *) NULL, &icnt, &offset_expr,
4451 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4452 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4467 /* When generating embedded PIC code, we permit expressions of
4470 la $treg,foo-bar($breg)
4471 where bar is an address in the current section. These are used
4472 when getting the addresses of functions. We don't permit
4473 X_add_number to be non-zero, because if the symbol is
4474 external the relaxing code needs to know that any addend is
4475 purely the offset to X_op_symbol. */
4476 if (mips_pic == EMBEDDED_PIC
4477 && offset_expr.X_op == O_subtract
4478 && (symbol_constant_p (offset_expr.X_op_symbol)
4479 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4480 : (symbol_equated_p (offset_expr.X_op_symbol)
4482 (symbol_get_value_expression (offset_expr.X_op_symbol)
4485 && (offset_expr.X_add_number == 0
4486 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4492 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4493 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4497 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4498 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4499 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4500 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4501 "d,v,t", tempreg, tempreg, breg);
4503 macro_build ((char *) NULL, &icnt, &offset_expr,
4504 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4505 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4511 if (offset_expr.X_op != O_symbol
4512 && offset_expr.X_op != O_constant)
4514 as_bad (_("expression too complex"));
4515 offset_expr.X_op = O_constant;
4518 if (offset_expr.X_op == O_constant)
4519 load_register (&icnt, tempreg, &offset_expr,
4520 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4521 ? (dbl || HAVE_64BIT_ADDRESSES)
4522 : HAVE_64BIT_ADDRESSES));
4523 else if (mips_pic == NO_PIC)
4525 /* If this is a reference to a GP relative symbol, we want
4526 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4528 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4529 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4530 If we have a constant, we need two instructions anyhow,
4531 so we may as well always use the latter form.
4533 With 64bit address space and a usable $at we want
4534 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4535 lui $at,<sym> (BFD_RELOC_HI16_S)
4536 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4537 daddiu $at,<sym> (BFD_RELOC_LO16)
4539 daddu $tempreg,$tempreg,$at
4541 If $at is already in use, we use an path which is suboptimal
4542 on superscalar processors.
4543 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4544 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4546 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4548 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4551 if (HAVE_64BIT_ADDRESSES)
4553 /* We don't do GP optimization for now because RELAX_ENCODE can't
4554 hold the data for such large chunks. */
4556 if (used_at == 0 && ! mips_opts.noat)
4558 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4559 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4560 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4561 AT, (int) BFD_RELOC_HI16_S);
4562 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4563 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4564 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4565 AT, AT, (int) BFD_RELOC_LO16);
4566 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4567 "d,w,<", tempreg, tempreg, 0);
4568 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4569 "d,v,t", tempreg, tempreg, AT);
4574 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4575 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4576 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4577 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4578 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4579 tempreg, tempreg, 16);
4580 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4581 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4582 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4583 tempreg, tempreg, 16);
4584 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4585 tempreg, tempreg, (int) BFD_RELOC_LO16);
4590 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4591 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4594 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4595 "t,r,j", tempreg, mips_gp_register,
4596 (int) BFD_RELOC_GPREL16);
4597 p = frag_var (rs_machine_dependent, 8, 0,
4598 RELAX_ENCODE (4, 8, 0, 4, 0,
4599 mips_opts.warn_about_macros),
4600 offset_expr.X_add_symbol, 0, NULL);
4602 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4605 macro_build (p, &icnt, &offset_expr, "addiu",
4606 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4609 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4611 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4613 /* If this is a reference to an external symbol, and there
4614 is no constant, we want
4615 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4616 or if tempreg is PIC_CALL_REG
4617 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4618 For a local symbol, we want
4619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4621 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4623 If we have a small constant, and this is a reference to
4624 an external symbol, we want
4625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4627 addiu $tempreg,$tempreg,<constant>
4628 For a local symbol, we want the same instruction
4629 sequence, but we output a BFD_RELOC_LO16 reloc on the
4632 If we have a large constant, and this is a reference to
4633 an external symbol, we want
4634 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4635 lui $at,<hiconstant>
4636 addiu $at,$at,<loconstant>
4637 addu $tempreg,$tempreg,$at
4638 For a local symbol, we want the same instruction
4639 sequence, but we output a BFD_RELOC_LO16 reloc on the
4640 addiu instruction. */
4641 expr1.X_add_number = offset_expr.X_add_number;
4642 offset_expr.X_add_number = 0;
4644 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4645 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4646 macro_build ((char *) NULL, &icnt, &offset_expr,
4647 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4648 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4649 if (expr1.X_add_number == 0)
4658 /* We're going to put in an addu instruction using
4659 tempreg, so we may as well insert the nop right
4661 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4665 p = frag_var (rs_machine_dependent, 8 - off, 0,
4666 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4668 ? mips_opts.warn_about_macros
4670 offset_expr.X_add_symbol, 0, NULL);
4673 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4676 macro_build (p, &icnt, &expr1,
4677 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4678 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4679 /* FIXME: If breg == 0, and the next instruction uses
4680 $tempreg, then if this variant case is used an extra
4681 nop will be generated. */
4683 else if (expr1.X_add_number >= -0x8000
4684 && expr1.X_add_number < 0x8000)
4686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4688 macro_build ((char *) NULL, &icnt, &expr1,
4689 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4690 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4691 frag_var (rs_machine_dependent, 0, 0,
4692 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4693 offset_expr.X_add_symbol, 0, NULL);
4699 /* If we are going to add in a base register, and the
4700 target register and the base register are the same,
4701 then we are using AT as a temporary register. Since
4702 we want to load the constant into AT, we add our
4703 current AT (from the global offset table) and the
4704 register into the register now, and pretend we were
4705 not using a base register. */
4710 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4712 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4713 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4714 "d,v,t", treg, AT, breg);
4720 /* Set mips_optimize around the lui instruction to avoid
4721 inserting an unnecessary nop after the lw. */
4722 hold_mips_optimize = mips_optimize;
4724 macro_build_lui (NULL, &icnt, &expr1, AT);
4725 mips_optimize = hold_mips_optimize;
4727 macro_build ((char *) NULL, &icnt, &expr1,
4728 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4729 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4730 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4731 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4732 "d,v,t", tempreg, tempreg, AT);
4733 frag_var (rs_machine_dependent, 0, 0,
4734 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4735 offset_expr.X_add_symbol, 0, NULL);
4739 else if (mips_pic == SVR4_PIC)
4743 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4744 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4746 /* This is the large GOT case. If this is a reference to an
4747 external symbol, and there is no constant, we want
4748 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4749 addu $tempreg,$tempreg,$gp
4750 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4751 or if tempreg is PIC_CALL_REG
4752 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4753 addu $tempreg,$tempreg,$gp
4754 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4755 For a local symbol, we want
4756 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4758 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4760 If we have a small constant, and this is a reference to
4761 an external symbol, we want
4762 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4763 addu $tempreg,$tempreg,$gp
4764 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4766 addiu $tempreg,$tempreg,<constant>
4767 For a local symbol, we want
4768 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4770 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4772 If we have a large constant, and this is a reference to
4773 an external symbol, we want
4774 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4775 addu $tempreg,$tempreg,$gp
4776 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4777 lui $at,<hiconstant>
4778 addiu $at,$at,<loconstant>
4779 addu $tempreg,$tempreg,$at
4780 For a local symbol, we want
4781 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4782 lui $at,<hiconstant>
4783 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4784 addu $tempreg,$tempreg,$at
4786 For NewABI, we want for data addresses
4787 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4788 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4789 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4793 int reloc_type = (tempreg == PIC_CALL_REG
4794 ? BFD_RELOC_MIPS_CALL16
4795 : BFD_RELOC_MIPS_GOT_DISP);
4797 macro_build ((char *) NULL, &icnt, &offset_expr,
4798 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4799 "t,o(b)", tempreg, reloc_type, mips_gp_register);
4802 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4803 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4804 "d,v,t", treg, tempreg, breg);
4811 expr1.X_add_number = offset_expr.X_add_number;
4812 offset_expr.X_add_number = 0;
4814 if (reg_needs_delay (mips_gp_register))
4818 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4820 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4821 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4823 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4824 tempreg, lui_reloc_type);
4825 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4826 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4827 "d,v,t", tempreg, tempreg, mips_gp_register);
4828 macro_build ((char *) NULL, &icnt, &offset_expr,
4829 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4830 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4831 if (expr1.X_add_number == 0)
4839 /* We're going to put in an addu instruction using
4840 tempreg, so we may as well insert the nop right
4842 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4847 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4848 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4851 ? mips_opts.warn_about_macros
4853 offset_expr.X_add_symbol, 0, NULL);
4855 else if (expr1.X_add_number >= -0x8000
4856 && expr1.X_add_number < 0x8000)
4858 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4860 macro_build ((char *) NULL, &icnt, &expr1,
4861 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4862 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4864 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4865 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4867 ? mips_opts.warn_about_macros
4869 offset_expr.X_add_symbol, 0, NULL);
4875 /* If we are going to add in a base register, and the
4876 target register and the base register are the same,
4877 then we are using AT as a temporary register. Since
4878 we want to load the constant into AT, we add our
4879 current AT (from the global offset table) and the
4880 register into the register now, and pretend we were
4881 not using a base register. */
4889 assert (tempreg == AT);
4890 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4892 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4893 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4894 "d,v,t", treg, AT, breg);
4899 /* Set mips_optimize around the lui instruction to avoid
4900 inserting an unnecessary nop after the lw. */
4901 hold_mips_optimize = mips_optimize;
4903 macro_build_lui (NULL, &icnt, &expr1, AT);
4904 mips_optimize = hold_mips_optimize;
4906 macro_build ((char *) NULL, &icnt, &expr1,
4907 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4908 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4909 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4910 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4911 "d,v,t", dreg, dreg, AT);
4913 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4914 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4917 ? mips_opts.warn_about_macros
4919 offset_expr.X_add_symbol, 0, NULL);
4926 /* This is needed because this instruction uses $gp, but
4927 the first instruction on the main stream does not. */
4928 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4931 macro_build (p, &icnt, &offset_expr,
4932 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4933 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
4936 if (expr1.X_add_number >= -0x8000
4937 && expr1.X_add_number < 0x8000)
4939 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4941 macro_build (p, &icnt, &expr1,
4942 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4943 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4944 /* FIXME: If add_number is 0, and there was no base
4945 register, the external symbol case ended with a load,
4946 so if the symbol turns out to not be external, and
4947 the next instruction uses tempreg, an unnecessary nop
4948 will be inserted. */
4954 /* We must add in the base register now, as in the
4955 external symbol case. */
4956 assert (tempreg == AT);
4957 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4959 macro_build (p, &icnt, (expressionS *) NULL,
4960 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4961 "d,v,t", treg, AT, breg);
4964 /* We set breg to 0 because we have arranged to add
4965 it in in both cases. */
4969 macro_build_lui (p, &icnt, &expr1, AT);
4971 macro_build (p, &icnt, &expr1,
4972 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4973 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4975 macro_build (p, &icnt, (expressionS *) NULL,
4976 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4977 "d,v,t", tempreg, tempreg, AT);
4981 else if (mips_pic == EMBEDDED_PIC)
4984 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4986 macro_build ((char *) NULL, &icnt, &offset_expr,
4987 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4988 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4997 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4998 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5000 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5002 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5003 "d,v,t", treg, tempreg, breg);
5012 /* The j instruction may not be used in PIC code, since it
5013 requires an absolute address. We convert it to a b
5015 if (mips_pic == NO_PIC)
5016 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5018 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5021 /* The jal instructions must be handled as macros because when
5022 generating PIC code they expand to multi-instruction
5023 sequences. Normally they are simple instructions. */
5028 if (mips_pic == NO_PIC
5029 || mips_pic == EMBEDDED_PIC)
5030 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5032 else if (mips_pic == SVR4_PIC)
5034 if (sreg != PIC_CALL_REG)
5035 as_warn (_("MIPS PIC call to register other than $25"));
5037 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5041 if (mips_cprestore_offset < 0)
5042 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5045 if (! mips_frame_reg_valid)
5047 as_warn (_("No .frame pseudo-op used in PIC code"));
5048 /* Quiet this warning. */
5049 mips_frame_reg_valid = 1;
5051 if (! mips_cprestore_valid)
5053 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5054 /* Quiet this warning. */
5055 mips_cprestore_valid = 1;
5057 expr1.X_add_number = mips_cprestore_offset;
5058 macro_build ((char *) NULL, &icnt, &expr1,
5059 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5060 mips_gp_register, (int) BFD_RELOC_LO16,
5071 if (mips_pic == NO_PIC)
5072 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5073 else if (mips_pic == SVR4_PIC)
5077 /* If this is a reference to an external symbol, and we are
5078 using a small GOT, we want
5079 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5083 lw $gp,cprestore($sp)
5084 The cprestore value is set using the .cprestore
5085 pseudo-op. If we are using a big GOT, we want
5086 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5088 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5092 lw $gp,cprestore($sp)
5093 If the symbol is not external, we want
5094 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5096 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5099 lw $gp,cprestore($sp)
5101 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5102 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5106 macro_build ((char *) NULL, &icnt, &offset_expr,
5107 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5108 "t,o(b)", PIC_CALL_REG,
5109 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5110 macro_build_jalr (icnt, &offset_expr);
5117 macro_build ((char *) NULL, &icnt, &offset_expr,
5118 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5119 "t,o(b)", PIC_CALL_REG,
5120 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5121 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5123 p = frag_var (rs_machine_dependent, 4, 0,
5124 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5125 offset_expr.X_add_symbol, 0, NULL);
5131 if (reg_needs_delay (mips_gp_register))
5135 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5136 "t,u", PIC_CALL_REG,
5137 (int) BFD_RELOC_MIPS_CALL_HI16);
5138 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5139 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5140 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5142 macro_build ((char *) NULL, &icnt, &offset_expr,
5143 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5144 "t,o(b)", PIC_CALL_REG,
5145 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5146 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5148 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5149 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5151 offset_expr.X_add_symbol, 0, NULL);
5154 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5157 macro_build (p, &icnt, &offset_expr,
5158 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5159 "t,o(b)", PIC_CALL_REG,
5160 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5162 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5165 macro_build (p, &icnt, &offset_expr,
5166 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5167 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5168 (int) BFD_RELOC_LO16);
5169 macro_build_jalr (icnt, &offset_expr);
5171 if (mips_cprestore_offset < 0)
5172 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5175 if (! mips_frame_reg_valid)
5177 as_warn (_("No .frame pseudo-op used in PIC code"));
5178 /* Quiet this warning. */
5179 mips_frame_reg_valid = 1;
5181 if (! mips_cprestore_valid)
5183 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5184 /* Quiet this warning. */
5185 mips_cprestore_valid = 1;
5187 if (mips_opts.noreorder)
5188 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5190 expr1.X_add_number = mips_cprestore_offset;
5191 macro_build ((char *) NULL, &icnt, &expr1,
5192 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5193 mips_gp_register, (int) BFD_RELOC_LO16,
5198 else if (mips_pic == EMBEDDED_PIC)
5200 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5201 /* The linker may expand the call to a longer sequence which
5202 uses $at, so we must break rather than return. */
5227 /* Itbl support may require additional care here. */
5232 /* Itbl support may require additional care here. */
5237 /* Itbl support may require additional care here. */
5242 /* Itbl support may require additional care here. */
5254 if (mips_arch == CPU_R4650)
5256 as_bad (_("opcode not supported on this processor"));
5260 /* Itbl support may require additional care here. */
5265 /* Itbl support may require additional care here. */
5270 /* Itbl support may require additional care here. */
5290 if (breg == treg || coproc || lr)
5312 /* Itbl support may require additional care here. */
5317 /* Itbl support may require additional care here. */
5322 /* Itbl support may require additional care here. */
5327 /* Itbl support may require additional care here. */
5343 if (mips_arch == CPU_R4650)
5345 as_bad (_("opcode not supported on this processor"));
5350 /* Itbl support may require additional care here. */
5354 /* Itbl support may require additional care here. */
5359 /* Itbl support may require additional care here. */
5371 /* Itbl support may require additional care here. */
5372 if (mask == M_LWC1_AB
5373 || mask == M_SWC1_AB
5374 || mask == M_LDC1_AB
5375 || mask == M_SDC1_AB
5384 /* For embedded PIC, we allow loads where the offset is calculated
5385 by subtracting a symbol in the current segment from an unknown
5386 symbol, relative to a base register, e.g.:
5387 <op> $treg, <sym>-<localsym>($breg)
5388 This is used by the compiler for switch statements. */
5389 if (mips_pic == EMBEDDED_PIC
5390 && offset_expr.X_op == O_subtract
5391 && (symbol_constant_p (offset_expr.X_op_symbol)
5392 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5393 : (symbol_equated_p (offset_expr.X_op_symbol)
5395 (symbol_get_value_expression (offset_expr.X_op_symbol)
5399 && (offset_expr.X_add_number == 0
5400 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5402 /* For this case, we output the instructions:
5403 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5404 addiu $tempreg,$tempreg,$breg
5405 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5406 If the relocation would fit entirely in 16 bits, it would be
5408 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5409 instead, but that seems quite difficult. */
5410 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5411 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5412 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5413 ((bfd_arch_bits_per_address (stdoutput) == 32
5414 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5415 ? "addu" : "daddu"),
5416 "d,v,t", tempreg, tempreg, breg);
5417 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5418 (int) BFD_RELOC_PCREL_LO16, tempreg);
5424 if (offset_expr.X_op != O_constant
5425 && offset_expr.X_op != O_symbol)
5427 as_bad (_("expression too complex"));
5428 offset_expr.X_op = O_constant;
5431 /* A constant expression in PIC code can be handled just as it
5432 is in non PIC code. */
5433 if (mips_pic == NO_PIC
5434 || offset_expr.X_op == O_constant)
5438 /* If this is a reference to a GP relative symbol, and there
5439 is no base register, we want
5440 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5441 Otherwise, if there is no base register, we want
5442 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5443 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5444 If we have a constant, we need two instructions anyhow,
5445 so we always use the latter form.
5447 If we have a base register, and this is a reference to a
5448 GP relative symbol, we want
5449 addu $tempreg,$breg,$gp
5450 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5452 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5453 addu $tempreg,$tempreg,$breg
5454 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5455 With a constant we always use the latter case.
5457 With 64bit address space and no base register and $at usable,
5459 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5460 lui $at,<sym> (BFD_RELOC_HI16_S)
5461 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5464 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5465 If we have a base register, we want
5466 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5467 lui $at,<sym> (BFD_RELOC_HI16_S)
5468 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5472 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5474 Without $at we can't generate the optimal path for superscalar
5475 processors here since this would require two temporary registers.
5476 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5477 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5479 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5481 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5482 If we have a base register, we want
5483 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5484 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5486 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5488 daddu $tempreg,$tempreg,$breg
5489 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5491 If we have 64-bit addresses, as an optimization, for
5492 addresses which are 32-bit constants (e.g. kseg0/kseg1
5493 addresses) we fall back to the 32-bit address generation
5494 mechanism since it is more efficient. Note that due to
5495 the signed offset used by memory operations, the 32-bit
5496 range is shifted down by 32768 here. This code should
5497 probably attempt to generate 64-bit constants more
5498 efficiently in general.
5500 if (HAVE_64BIT_ADDRESSES
5501 && !(offset_expr.X_op == O_constant
5502 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5506 /* We don't do GP optimization for now because RELAX_ENCODE can't
5507 hold the data for such large chunks. */
5509 if (used_at == 0 && ! mips_opts.noat)
5511 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5512 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5513 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5514 AT, (int) BFD_RELOC_HI16_S);
5515 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5516 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5518 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5519 "d,v,t", AT, AT, breg);
5520 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5521 "d,w,<", tempreg, tempreg, 0);
5522 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5523 "d,v,t", tempreg, tempreg, AT);
5524 macro_build (p, &icnt, &offset_expr, s,
5525 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5530 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5531 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5532 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5533 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5534 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5535 "d,w,<", tempreg, tempreg, 16);
5536 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5537 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5538 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5539 "d,w,<", tempreg, tempreg, 16);
5541 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5542 "d,v,t", tempreg, tempreg, breg);
5543 macro_build (p, &icnt, &offset_expr, s,
5544 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5552 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5553 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5558 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5559 treg, (int) BFD_RELOC_GPREL16,
5561 p = frag_var (rs_machine_dependent, 8, 0,
5562 RELAX_ENCODE (4, 8, 0, 4, 0,
5563 (mips_opts.warn_about_macros
5565 && mips_opts.noat))),
5566 offset_expr.X_add_symbol, 0, NULL);
5569 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5572 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5573 (int) BFD_RELOC_LO16, tempreg);
5577 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5578 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5583 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5584 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5585 "d,v,t", tempreg, breg, mips_gp_register);
5586 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5587 treg, (int) BFD_RELOC_GPREL16, tempreg);
5588 p = frag_var (rs_machine_dependent, 12, 0,
5589 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5590 offset_expr.X_add_symbol, 0, NULL);
5592 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5595 macro_build (p, &icnt, (expressionS *) NULL,
5596 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5597 "d,v,t", tempreg, tempreg, breg);
5600 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5601 (int) BFD_RELOC_LO16, tempreg);
5604 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5608 /* If this is a reference to an external symbol, we want
5609 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5611 <op> $treg,0($tempreg)
5613 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5615 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5616 <op> $treg,0($tempreg)
5617 If there is a base register, we add it to $tempreg before
5618 the <op>. If there is a constant, we stick it in the
5619 <op> instruction. We don't handle constants larger than
5620 16 bits, because we have no way to load the upper 16 bits
5621 (actually, we could handle them for the subset of cases
5622 in which we are not using $at). */
5623 assert (offset_expr.X_op == O_symbol);
5624 expr1.X_add_number = offset_expr.X_add_number;
5625 offset_expr.X_add_number = 0;
5626 if (expr1.X_add_number < -0x8000
5627 || expr1.X_add_number >= 0x8000)
5628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5630 macro_build ((char *) NULL, &icnt, &offset_expr,
5631 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5632 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5633 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5634 p = frag_var (rs_machine_dependent, 4, 0,
5635 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5636 offset_expr.X_add_symbol, 0, NULL);
5637 macro_build (p, &icnt, &offset_expr,
5638 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5639 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5642 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5643 "d,v,t", tempreg, tempreg, breg);
5644 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5645 (int) BFD_RELOC_LO16, tempreg);
5647 else if (mips_pic == SVR4_PIC)
5652 /* If this is a reference to an external symbol, we want
5653 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5654 addu $tempreg,$tempreg,$gp
5655 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5656 <op> $treg,0($tempreg)
5658 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5660 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5661 <op> $treg,0($tempreg)
5662 If there is a base register, we add it to $tempreg before
5663 the <op>. If there is a constant, we stick it in the
5664 <op> instruction. We don't handle constants larger than
5665 16 bits, because we have no way to load the upper 16 bits
5666 (actually, we could handle them for the subset of cases
5667 in which we are not using $at).
5670 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5671 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5672 <op> $treg,0($tempreg)
5674 assert (offset_expr.X_op == O_symbol);
5675 expr1.X_add_number = offset_expr.X_add_number;
5676 offset_expr.X_add_number = 0;
5677 if (expr1.X_add_number < -0x8000
5678 || expr1.X_add_number >= 0x8000)
5679 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5682 macro_build ((char *) NULL, &icnt, &offset_expr,
5683 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5684 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5686 macro_build ((char *) NULL, &icnt, &offset_expr,
5687 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5688 "t,r,j", tempreg, tempreg,
5689 BFD_RELOC_MIPS_GOT_OFST);
5691 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5692 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5693 "d,v,t", tempreg, tempreg, breg);
5694 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5695 (int) BFD_RELOC_LO16, tempreg);
5702 if (reg_needs_delay (mips_gp_register))
5707 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5708 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5709 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5710 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5711 "d,v,t", tempreg, tempreg, mips_gp_register);
5712 macro_build ((char *) NULL, &icnt, &offset_expr,
5713 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5714 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5716 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5717 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5718 offset_expr.X_add_symbol, 0, NULL);
5721 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5724 macro_build (p, &icnt, &offset_expr,
5725 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5726 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5729 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5731 macro_build (p, &icnt, &offset_expr,
5732 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5733 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5735 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5736 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5737 "d,v,t", tempreg, tempreg, breg);
5738 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5739 (int) BFD_RELOC_LO16, tempreg);
5741 else if (mips_pic == EMBEDDED_PIC)
5743 /* If there is no base register, we want
5744 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5745 If there is a base register, we want
5746 addu $tempreg,$breg,$gp
5747 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5749 assert (offset_expr.X_op == O_symbol);
5752 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5753 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5758 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5759 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5760 "d,v,t", tempreg, breg, mips_gp_register);
5761 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5762 treg, (int) BFD_RELOC_GPREL16, tempreg);
5775 load_register (&icnt, treg, &imm_expr, 0);
5779 load_register (&icnt, treg, &imm_expr, 1);
5783 if (imm_expr.X_op == O_constant)
5785 load_register (&icnt, AT, &imm_expr, 0);
5786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5787 "mtc1", "t,G", AT, treg);
5792 assert (offset_expr.X_op == O_symbol
5793 && strcmp (segment_name (S_GET_SEGMENT
5794 (offset_expr.X_add_symbol)),
5796 && offset_expr.X_add_number == 0);
5797 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5798 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5803 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5804 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5805 order 32 bits of the value and the low order 32 bits are either
5806 zero or in OFFSET_EXPR. */
5807 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5809 if (HAVE_64BIT_GPRS)
5810 load_register (&icnt, treg, &imm_expr, 1);
5815 if (target_big_endian)
5827 load_register (&icnt, hreg, &imm_expr, 0);
5830 if (offset_expr.X_op == O_absent)
5831 move_register (&icnt, lreg, 0);
5834 assert (offset_expr.X_op == O_constant);
5835 load_register (&icnt, lreg, &offset_expr, 0);
5842 /* We know that sym is in the .rdata section. First we get the
5843 upper 16 bits of the address. */
5844 if (mips_pic == NO_PIC)
5846 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5848 else if (mips_pic == SVR4_PIC)
5850 macro_build ((char *) NULL, &icnt, &offset_expr,
5851 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5852 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5855 else if (mips_pic == EMBEDDED_PIC)
5857 /* For embedded PIC we pick up the entire address off $gp in
5858 a single instruction. */
5859 macro_build ((char *) NULL, &icnt, &offset_expr,
5860 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5861 mips_gp_register, (int) BFD_RELOC_GPREL16);
5862 offset_expr.X_op = O_constant;
5863 offset_expr.X_add_number = 0;
5868 /* Now we load the register(s). */
5869 if (HAVE_64BIT_GPRS)
5870 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5871 treg, (int) BFD_RELOC_LO16, AT);
5874 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5875 treg, (int) BFD_RELOC_LO16, AT);
5878 /* FIXME: How in the world do we deal with the possible
5880 offset_expr.X_add_number += 4;
5881 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5882 treg + 1, (int) BFD_RELOC_LO16, AT);
5886 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5887 does not become a variant frag. */
5888 frag_wane (frag_now);
5894 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5895 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5896 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5897 the value and the low order 32 bits are either zero or in
5899 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5901 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5902 if (HAVE_64BIT_FPRS)
5904 assert (HAVE_64BIT_GPRS);
5905 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5906 "dmtc1", "t,S", AT, treg);
5910 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5911 "mtc1", "t,G", AT, treg + 1);
5912 if (offset_expr.X_op == O_absent)
5913 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5914 "mtc1", "t,G", 0, treg);
5917 assert (offset_expr.X_op == O_constant);
5918 load_register (&icnt, AT, &offset_expr, 0);
5919 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5920 "mtc1", "t,G", AT, treg);
5926 assert (offset_expr.X_op == O_symbol
5927 && offset_expr.X_add_number == 0);
5928 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5929 if (strcmp (s, ".lit8") == 0)
5931 if (mips_opts.isa != ISA_MIPS1)
5933 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5934 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5938 breg = mips_gp_register;
5939 r = BFD_RELOC_MIPS_LITERAL;
5944 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5945 if (mips_pic == SVR4_PIC)
5946 macro_build ((char *) NULL, &icnt, &offset_expr,
5947 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5948 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5952 /* FIXME: This won't work for a 64 bit address. */
5953 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5956 if (mips_opts.isa != ISA_MIPS1)
5958 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5959 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5961 /* To avoid confusion in tc_gen_reloc, we must ensure
5962 that this does not become a variant frag. */
5963 frag_wane (frag_now);
5974 if (mips_arch == CPU_R4650)
5976 as_bad (_("opcode not supported on this processor"));
5979 /* Even on a big endian machine $fn comes before $fn+1. We have
5980 to adjust when loading from memory. */
5983 assert (mips_opts.isa == ISA_MIPS1);
5984 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5985 target_big_endian ? treg + 1 : treg,
5987 /* FIXME: A possible overflow which I don't know how to deal
5989 offset_expr.X_add_number += 4;
5990 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5991 target_big_endian ? treg : treg + 1,
5994 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5995 does not become a variant frag. */
5996 frag_wane (frag_now);
6005 * The MIPS assembler seems to check for X_add_number not
6006 * being double aligned and generating:
6009 * addiu at,at,%lo(foo+1)
6012 * But, the resulting address is the same after relocation so why
6013 * generate the extra instruction?
6015 if (mips_arch == CPU_R4650)
6017 as_bad (_("opcode not supported on this processor"));
6020 /* Itbl support may require additional care here. */
6022 if (mips_opts.isa != ISA_MIPS1)
6033 if (mips_arch == CPU_R4650)
6035 as_bad (_("opcode not supported on this processor"));
6039 if (mips_opts.isa != ISA_MIPS1)
6047 /* Itbl support may require additional care here. */
6052 if (HAVE_64BIT_GPRS)
6063 if (HAVE_64BIT_GPRS)
6073 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6074 loads for the case of doing a pair of loads to simulate an 'ld'.
6075 This is not currently done by the compiler, and assembly coders
6076 writing embedded-pic code can cope. */
6078 if (offset_expr.X_op != O_symbol
6079 && offset_expr.X_op != O_constant)
6081 as_bad (_("expression too complex"));
6082 offset_expr.X_op = O_constant;
6085 /* Even on a big endian machine $fn comes before $fn+1. We have
6086 to adjust when loading from memory. We set coproc if we must
6087 load $fn+1 first. */
6088 /* Itbl support may require additional care here. */
6089 if (! target_big_endian)
6092 if (mips_pic == NO_PIC
6093 || offset_expr.X_op == O_constant)
6097 /* If this is a reference to a GP relative symbol, we want
6098 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6099 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6100 If we have a base register, we use this
6102 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6103 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6104 If this is not a GP relative symbol, we want
6105 lui $at,<sym> (BFD_RELOC_HI16_S)
6106 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6107 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6108 If there is a base register, we add it to $at after the
6109 lui instruction. If there is a constant, we always use
6111 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6112 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6124 tempreg = mips_gp_register;
6131 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6132 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6133 "d,v,t", AT, breg, mips_gp_register);
6139 /* Itbl support may require additional care here. */
6140 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6141 coproc ? treg + 1 : treg,
6142 (int) BFD_RELOC_GPREL16, tempreg);
6143 offset_expr.X_add_number += 4;
6145 /* Set mips_optimize to 2 to avoid inserting an
6147 hold_mips_optimize = mips_optimize;
6149 /* Itbl support may require additional care here. */
6150 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6151 coproc ? treg : treg + 1,
6152 (int) BFD_RELOC_GPREL16, tempreg);
6153 mips_optimize = hold_mips_optimize;
6155 p = frag_var (rs_machine_dependent, 12 + off, 0,
6156 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6157 used_at && mips_opts.noat),
6158 offset_expr.X_add_symbol, 0, NULL);
6160 /* We just generated two relocs. When tc_gen_reloc
6161 handles this case, it will skip the first reloc and
6162 handle the second. The second reloc already has an
6163 extra addend of 4, which we added above. We must
6164 subtract it out, and then subtract another 4 to make
6165 the first reloc come out right. The second reloc
6166 will come out right because we are going to add 4 to
6167 offset_expr when we build its instruction below.
6169 If we have a symbol, then we don't want to include
6170 the offset, because it will wind up being included
6171 when we generate the reloc. */
6173 if (offset_expr.X_op == O_constant)
6174 offset_expr.X_add_number -= 8;
6177 offset_expr.X_add_number = -4;
6178 offset_expr.X_op = O_constant;
6181 macro_build_lui (p, &icnt, &offset_expr, AT);
6186 macro_build (p, &icnt, (expressionS *) NULL,
6187 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6188 "d,v,t", AT, breg, AT);
6192 /* Itbl support may require additional care here. */
6193 macro_build (p, &icnt, &offset_expr, s, fmt,
6194 coproc ? treg + 1 : treg,
6195 (int) BFD_RELOC_LO16, AT);
6198 /* FIXME: How do we handle overflow here? */
6199 offset_expr.X_add_number += 4;
6200 /* Itbl support may require additional care here. */
6201 macro_build (p, &icnt, &offset_expr, s, fmt,
6202 coproc ? treg : treg + 1,
6203 (int) BFD_RELOC_LO16, AT);
6205 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6209 /* If this is a reference to an external symbol, we want
6210 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6215 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6217 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6218 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6219 If there is a base register we add it to $at before the
6220 lwc1 instructions. If there is a constant we include it
6221 in the lwc1 instructions. */
6223 expr1.X_add_number = offset_expr.X_add_number;
6224 offset_expr.X_add_number = 0;
6225 if (expr1.X_add_number < -0x8000
6226 || expr1.X_add_number >= 0x8000 - 4)
6227 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6232 frag_grow (24 + off);
6233 macro_build ((char *) NULL, &icnt, &offset_expr,
6234 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6235 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6236 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6238 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6239 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6240 "d,v,t", AT, breg, AT);
6241 /* Itbl support may require additional care here. */
6242 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6243 coproc ? treg + 1 : treg,
6244 (int) BFD_RELOC_LO16, AT);
6245 expr1.X_add_number += 4;
6247 /* Set mips_optimize to 2 to avoid inserting an undesired
6249 hold_mips_optimize = mips_optimize;
6251 /* Itbl support may require additional care here. */
6252 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6253 coproc ? treg : treg + 1,
6254 (int) BFD_RELOC_LO16, AT);
6255 mips_optimize = hold_mips_optimize;
6257 (void) frag_var (rs_machine_dependent, 0, 0,
6258 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6259 offset_expr.X_add_symbol, 0, NULL);
6261 else if (mips_pic == SVR4_PIC)
6266 /* If this is a reference to an external symbol, we want
6267 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6269 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6274 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6276 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6277 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6278 If there is a base register we add it to $at before the
6279 lwc1 instructions. If there is a constant we include it
6280 in the lwc1 instructions. */
6282 expr1.X_add_number = offset_expr.X_add_number;
6283 offset_expr.X_add_number = 0;
6284 if (expr1.X_add_number < -0x8000
6285 || expr1.X_add_number >= 0x8000 - 4)
6286 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6287 if (reg_needs_delay (mips_gp_register))
6296 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6297 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6298 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6299 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6300 "d,v,t", AT, AT, mips_gp_register);
6301 macro_build ((char *) NULL, &icnt, &offset_expr,
6302 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6303 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6304 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6306 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6307 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6308 "d,v,t", AT, breg, AT);
6309 /* Itbl support may require additional care here. */
6310 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6311 coproc ? treg + 1 : treg,
6312 (int) BFD_RELOC_LO16, AT);
6313 expr1.X_add_number += 4;
6315 /* Set mips_optimize to 2 to avoid inserting an undesired
6317 hold_mips_optimize = mips_optimize;
6319 /* Itbl support may require additional care here. */
6320 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6321 coproc ? treg : treg + 1,
6322 (int) BFD_RELOC_LO16, AT);
6323 mips_optimize = hold_mips_optimize;
6324 expr1.X_add_number -= 4;
6326 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6327 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6328 8 + gpdel + off, 1, 0),
6329 offset_expr.X_add_symbol, 0, NULL);
6332 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6335 macro_build (p, &icnt, &offset_expr,
6336 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6337 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6340 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6344 macro_build (p, &icnt, (expressionS *) NULL,
6345 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6346 "d,v,t", AT, breg, AT);
6349 /* Itbl support may require additional care here. */
6350 macro_build (p, &icnt, &expr1, s, fmt,
6351 coproc ? treg + 1 : treg,
6352 (int) BFD_RELOC_LO16, AT);
6354 expr1.X_add_number += 4;
6356 /* Set mips_optimize to 2 to avoid inserting an undesired
6358 hold_mips_optimize = mips_optimize;
6360 /* Itbl support may require additional care here. */
6361 macro_build (p, &icnt, &expr1, s, fmt,
6362 coproc ? treg : treg + 1,
6363 (int) BFD_RELOC_LO16, AT);
6364 mips_optimize = hold_mips_optimize;
6366 else if (mips_pic == EMBEDDED_PIC)
6368 /* If there is no base register, we use
6369 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6370 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6371 If we have a base register, we use
6373 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6374 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6378 tempreg = mips_gp_register;
6383 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6384 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6385 "d,v,t", AT, breg, mips_gp_register);
6390 /* Itbl support may require additional care here. */
6391 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6392 coproc ? treg + 1 : treg,
6393 (int) BFD_RELOC_GPREL16, tempreg);
6394 offset_expr.X_add_number += 4;
6395 /* Itbl support may require additional care here. */
6396 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6397 coproc ? treg : treg + 1,
6398 (int) BFD_RELOC_GPREL16, tempreg);
6414 assert (HAVE_32BIT_ADDRESSES);
6415 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6416 (int) BFD_RELOC_LO16, breg);
6417 offset_expr.X_add_number += 4;
6418 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6419 (int) BFD_RELOC_LO16, breg);
6422 /* New code added to support COPZ instructions.
6423 This code builds table entries out of the macros in mip_opcodes.
6424 R4000 uses interlocks to handle coproc delays.
6425 Other chips (like the R3000) require nops to be inserted for delays.
6427 FIXME: Currently, we require that the user handle delays.
6428 In order to fill delay slots for non-interlocked chips,
6429 we must have a way to specify delays based on the coprocessor.
6430 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6431 What are the side-effects of the cop instruction?
6432 What cache support might we have and what are its effects?
6433 Both coprocessor & memory require delays. how long???
6434 What registers are read/set/modified?
6436 If an itbl is provided to interpret cop instructions,
6437 this knowledge can be encoded in the itbl spec. */
6451 /* For now we just do C (same as Cz). The parameter will be
6452 stored in insn_opcode by mips_ip. */
6453 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6458 move_register (&icnt, dreg, sreg);
6461 #ifdef LOSING_COMPILER
6463 /* Try and see if this is a new itbl instruction.
6464 This code builds table entries out of the macros in mip_opcodes.
6465 FIXME: For now we just assemble the expression and pass it's
6466 value along as a 32-bit immediate.
6467 We may want to have the assembler assemble this value,
6468 so that we gain the assembler's knowledge of delay slots,
6470 Would it be more efficient to use mask (id) here? */
6471 if (itbl_have_entries
6472 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6474 s = ip->insn_mo->name;
6476 coproc = ITBL_DECODE_PNUM (immed_expr);;
6477 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6484 as_warn (_("Macro used $at after \".set noat\""));
6489 struct mips_cl_insn *ip;
6491 register int treg, sreg, dreg, breg;
6507 bfd_reloc_code_real_type r;
6510 treg = (ip->insn_opcode >> 16) & 0x1f;
6511 dreg = (ip->insn_opcode >> 11) & 0x1f;
6512 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6513 mask = ip->insn_mo->mask;
6515 expr1.X_op = O_constant;
6516 expr1.X_op_symbol = NULL;
6517 expr1.X_add_symbol = NULL;
6518 expr1.X_add_number = 1;
6522 #endif /* LOSING_COMPILER */
6527 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6528 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6529 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6536 /* The MIPS assembler some times generates shifts and adds. I'm
6537 not trying to be that fancy. GCC should do this for us
6539 load_register (&icnt, AT, &imm_expr, dbl);
6540 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6541 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6556 mips_emit_delays (true);
6557 ++mips_opts.noreorder;
6558 mips_any_noreorder = 1;
6560 load_register (&icnt, AT, &imm_expr, dbl);
6561 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6562 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6565 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6566 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6570 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6571 "s,t,q", dreg, AT, 6);
6574 expr1.X_add_number = 8;
6575 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6577 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6579 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6582 --mips_opts.noreorder;
6583 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6596 mips_emit_delays (true);
6597 ++mips_opts.noreorder;
6598 mips_any_noreorder = 1;
6600 load_register (&icnt, AT, &imm_expr, dbl);
6601 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6602 dbl ? "dmultu" : "multu",
6603 "s,t", sreg, imm ? AT : treg);
6604 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6606 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6609 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6613 expr1.X_add_number = 8;
6614 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6615 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6620 --mips_opts.noreorder;
6624 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6625 "d,v,t", AT, 0, treg);
6626 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6627 "d,t,s", AT, sreg, AT);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6629 "d,t,s", dreg, sreg, treg);
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6631 "d,v,t", dreg, dreg, AT);
6635 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6636 "d,v,t", AT, 0, treg);
6637 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6638 "d,t,s", AT, sreg, AT);
6639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6640 "d,t,s", dreg, sreg, treg);
6641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6642 "d,v,t", dreg, dreg, AT);
6650 if (imm_expr.X_op != O_constant)
6651 as_bad (_("rotate count too large"));
6652 rot = imm_expr.X_add_number & 0x3f;
6655 l = (rot < 0x20) ? "dsll" : "dsll32";
6656 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6658 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6659 "d,w,<", AT, sreg, rot);
6660 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6661 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6662 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6663 "d,v,t", dreg, dreg, AT);
6671 if (imm_expr.X_op != O_constant)
6672 as_bad (_("rotate count too large"));
6673 rot = imm_expr.X_add_number & 0x1f;
6676 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6677 "d,w,<", AT, sreg, rot);
6678 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6679 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6680 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6681 "d,v,t", dreg, dreg, AT);
6686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6687 "d,v,t", AT, 0, treg);
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6689 "d,t,s", AT, sreg, AT);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6691 "d,t,s", dreg, sreg, treg);
6692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6693 "d,v,t", dreg, dreg, AT);
6697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6698 "d,v,t", AT, 0, treg);
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6700 "d,t,s", AT, sreg, AT);
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6702 "d,t,s", dreg, sreg, treg);
6703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6704 "d,v,t", dreg, dreg, AT);
6712 if (imm_expr.X_op != O_constant)
6713 as_bad (_("rotate count too large"));
6714 rot = imm_expr.X_add_number & 0x3f;
6717 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6718 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6720 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6721 "d,w,<", AT, sreg, rot);
6722 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6723 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6724 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6725 "d,v,t", dreg, dreg, AT);
6733 if (imm_expr.X_op != O_constant)
6734 as_bad (_("rotate count too large"));
6735 rot = imm_expr.X_add_number & 0x1f;
6738 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6739 "d,w,<", AT, sreg, rot);
6740 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6741 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6742 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6743 "d,v,t", dreg, dreg, AT);
6748 if (mips_arch == CPU_R4650)
6750 as_bad (_("opcode not supported on this processor"));
6753 assert (mips_opts.isa == ISA_MIPS1);
6754 /* Even on a big endian machine $fn comes before $fn+1. We have
6755 to adjust when storing to memory. */
6756 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6757 target_big_endian ? treg + 1 : treg,
6758 (int) BFD_RELOC_LO16, breg);
6759 offset_expr.X_add_number += 4;
6760 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6761 target_big_endian ? treg : treg + 1,
6762 (int) BFD_RELOC_LO16, breg);
6767 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6768 treg, (int) BFD_RELOC_LO16);
6770 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6771 sreg, (int) BFD_RELOC_LO16);
6774 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6775 "d,v,t", dreg, sreg, treg);
6776 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6777 dreg, (int) BFD_RELOC_LO16);
6782 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6784 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6785 sreg, (int) BFD_RELOC_LO16);
6790 as_warn (_("Instruction %s: result is always false"),
6792 move_register (&icnt, dreg, 0);
6795 if (imm_expr.X_op == O_constant
6796 && imm_expr.X_add_number >= 0
6797 && imm_expr.X_add_number < 0x10000)
6799 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6800 sreg, (int) BFD_RELOC_LO16);
6803 else if (imm_expr.X_op == O_constant
6804 && imm_expr.X_add_number > -0x8000
6805 && imm_expr.X_add_number < 0)
6807 imm_expr.X_add_number = -imm_expr.X_add_number;
6808 macro_build ((char *) NULL, &icnt, &imm_expr,
6809 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6810 "t,r,j", dreg, sreg,
6811 (int) BFD_RELOC_LO16);
6816 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6817 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6818 "d,v,t", dreg, sreg, AT);
6821 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6822 (int) BFD_RELOC_LO16);
6827 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6833 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6835 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6836 (int) BFD_RELOC_LO16);
6839 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6841 if (imm_expr.X_op == O_constant
6842 && imm_expr.X_add_number >= -0x8000
6843 && imm_expr.X_add_number < 0x8000)
6845 macro_build ((char *) NULL, &icnt, &imm_expr,
6846 mask == M_SGE_I ? "slti" : "sltiu",
6847 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6852 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6853 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6854 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6858 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6859 (int) BFD_RELOC_LO16);
6864 case M_SGT: /* sreg > treg <==> treg < sreg */
6870 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6874 case M_SGT_I: /* sreg > I <==> I < sreg */
6880 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6881 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6885 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6891 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6893 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6894 (int) BFD_RELOC_LO16);
6897 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6903 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6904 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6906 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6907 (int) BFD_RELOC_LO16);
6911 if (imm_expr.X_op == O_constant
6912 && imm_expr.X_add_number >= -0x8000
6913 && imm_expr.X_add_number < 0x8000)
6915 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6916 dreg, sreg, (int) BFD_RELOC_LO16);
6919 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6920 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6925 if (imm_expr.X_op == O_constant
6926 && imm_expr.X_add_number >= -0x8000
6927 && imm_expr.X_add_number < 0x8000)
6929 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6930 dreg, sreg, (int) BFD_RELOC_LO16);
6933 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6934 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6935 "d,v,t", dreg, sreg, AT);
6940 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6941 "d,v,t", dreg, 0, treg);
6943 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6944 "d,v,t", dreg, 0, sreg);
6947 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6948 "d,v,t", dreg, sreg, treg);
6949 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6950 "d,v,t", dreg, 0, dreg);
6955 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6957 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6958 "d,v,t", dreg, 0, sreg);
6963 as_warn (_("Instruction %s: result is always true"),
6965 macro_build ((char *) NULL, &icnt, &expr1,
6966 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6967 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6970 if (imm_expr.X_op == O_constant
6971 && imm_expr.X_add_number >= 0
6972 && imm_expr.X_add_number < 0x10000)
6974 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6975 dreg, sreg, (int) BFD_RELOC_LO16);
6978 else if (imm_expr.X_op == O_constant
6979 && imm_expr.X_add_number > -0x8000
6980 && imm_expr.X_add_number < 0)
6982 imm_expr.X_add_number = -imm_expr.X_add_number;
6983 macro_build ((char *) NULL, &icnt, &imm_expr,
6984 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6985 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6990 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6991 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6992 "d,v,t", dreg, sreg, AT);
6995 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6996 "d,v,t", dreg, 0, dreg);
7004 if (imm_expr.X_op == O_constant
7005 && imm_expr.X_add_number > -0x8000
7006 && imm_expr.X_add_number <= 0x8000)
7008 imm_expr.X_add_number = -imm_expr.X_add_number;
7009 macro_build ((char *) NULL, &icnt, &imm_expr,
7010 dbl ? "daddi" : "addi",
7011 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7014 load_register (&icnt, AT, &imm_expr, dbl);
7015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7016 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7022 if (imm_expr.X_op == O_constant
7023 && imm_expr.X_add_number > -0x8000
7024 && imm_expr.X_add_number <= 0x8000)
7026 imm_expr.X_add_number = -imm_expr.X_add_number;
7027 macro_build ((char *) NULL, &icnt, &imm_expr,
7028 dbl ? "daddiu" : "addiu",
7029 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7032 load_register (&icnt, AT, &imm_expr, dbl);
7033 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7034 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7055 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7056 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7062 assert (mips_opts.isa == ISA_MIPS1);
7063 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7064 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7067 * Is the double cfc1 instruction a bug in the mips assembler;
7068 * or is there a reason for it?
7070 mips_emit_delays (true);
7071 ++mips_opts.noreorder;
7072 mips_any_noreorder = 1;
7073 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7075 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7077 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7078 expr1.X_add_number = 3;
7079 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7080 (int) BFD_RELOC_LO16);
7081 expr1.X_add_number = 2;
7082 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7083 (int) BFD_RELOC_LO16);
7084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7086 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7087 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7088 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7091 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7092 --mips_opts.noreorder;
7101 if (offset_expr.X_add_number >= 0x7fff)
7102 as_bad (_("operand overflow"));
7103 /* avoid load delay */
7104 if (! target_big_endian)
7105 ++offset_expr.X_add_number;
7106 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7107 (int) BFD_RELOC_LO16, breg);
7108 if (! target_big_endian)
7109 --offset_expr.X_add_number;
7111 ++offset_expr.X_add_number;
7112 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7113 (int) BFD_RELOC_LO16, breg);
7114 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7130 if (offset_expr.X_add_number >= 0x8000 - off)
7131 as_bad (_("operand overflow"));
7132 if (! target_big_endian)
7133 offset_expr.X_add_number += off;
7134 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7135 (int) BFD_RELOC_LO16, breg);
7136 if (! target_big_endian)
7137 offset_expr.X_add_number -= off;
7139 offset_expr.X_add_number += off;
7140 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7141 (int) BFD_RELOC_LO16, breg);
7155 load_address (&icnt, AT, &offset_expr, &used_at);
7157 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7158 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7159 "d,v,t", AT, AT, breg);
7160 if (! target_big_endian)
7161 expr1.X_add_number = off;
7163 expr1.X_add_number = 0;
7164 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7165 (int) BFD_RELOC_LO16, AT);
7166 if (! target_big_endian)
7167 expr1.X_add_number = 0;
7169 expr1.X_add_number = off;
7170 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7171 (int) BFD_RELOC_LO16, AT);
7177 load_address (&icnt, AT, &offset_expr, &used_at);
7179 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7180 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7181 "d,v,t", AT, AT, breg);
7182 if (target_big_endian)
7183 expr1.X_add_number = 0;
7184 macro_build ((char *) NULL, &icnt, &expr1,
7185 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7186 (int) BFD_RELOC_LO16, AT);
7187 if (target_big_endian)
7188 expr1.X_add_number = 1;
7190 expr1.X_add_number = 0;
7191 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7192 (int) BFD_RELOC_LO16, AT);
7193 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7195 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7200 if (offset_expr.X_add_number >= 0x7fff)
7201 as_bad (_("operand overflow"));
7202 if (target_big_endian)
7203 ++offset_expr.X_add_number;
7204 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7205 (int) BFD_RELOC_LO16, breg);
7206 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7208 if (target_big_endian)
7209 --offset_expr.X_add_number;
7211 ++offset_expr.X_add_number;
7212 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7213 (int) BFD_RELOC_LO16, breg);
7226 if (offset_expr.X_add_number >= 0x8000 - off)
7227 as_bad (_("operand overflow"));
7228 if (! target_big_endian)
7229 offset_expr.X_add_number += off;
7230 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7231 (int) BFD_RELOC_LO16, breg);
7232 if (! target_big_endian)
7233 offset_expr.X_add_number -= off;
7235 offset_expr.X_add_number += off;
7236 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7237 (int) BFD_RELOC_LO16, breg);
7251 load_address (&icnt, AT, &offset_expr, &used_at);
7253 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7254 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7255 "d,v,t", AT, AT, breg);
7256 if (! target_big_endian)
7257 expr1.X_add_number = off;
7259 expr1.X_add_number = 0;
7260 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7261 (int) BFD_RELOC_LO16, AT);
7262 if (! target_big_endian)
7263 expr1.X_add_number = 0;
7265 expr1.X_add_number = off;
7266 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7267 (int) BFD_RELOC_LO16, AT);
7272 load_address (&icnt, AT, &offset_expr, &used_at);
7274 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7275 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7276 "d,v,t", AT, AT, breg);
7277 if (! target_big_endian)
7278 expr1.X_add_number = 0;
7279 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7280 (int) BFD_RELOC_LO16, AT);
7281 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7283 if (! target_big_endian)
7284 expr1.X_add_number = 1;
7286 expr1.X_add_number = 0;
7287 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7288 (int) BFD_RELOC_LO16, AT);
7289 if (! target_big_endian)
7290 expr1.X_add_number = 0;
7292 expr1.X_add_number = 1;
7293 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7294 (int) BFD_RELOC_LO16, AT);
7295 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7297 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7302 /* FIXME: Check if this is one of the itbl macros, since they
7303 are added dynamically. */
7304 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7308 as_warn (_("Macro used $at after \".set noat\""));
7311 /* Implement macros in mips16 mode. */
7315 struct mips_cl_insn *ip;
7318 int xreg, yreg, zreg, tmp;
7322 const char *s, *s2, *s3;
7324 mask = ip->insn_mo->mask;
7326 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7327 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7328 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7332 expr1.X_op = O_constant;
7333 expr1.X_op_symbol = NULL;
7334 expr1.X_add_symbol = NULL;
7335 expr1.X_add_number = 1;
7354 mips_emit_delays (true);
7355 ++mips_opts.noreorder;
7356 mips_any_noreorder = 1;
7357 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7358 dbl ? "ddiv" : "div",
7359 "0,x,y", xreg, yreg);
7360 expr1.X_add_number = 2;
7361 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7362 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7365 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7366 since that causes an overflow. We should do that as well,
7367 but I don't see how to do the comparisons without a temporary
7369 --mips_opts.noreorder;
7370 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7389 mips_emit_delays (true);
7390 ++mips_opts.noreorder;
7391 mips_any_noreorder = 1;
7392 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7394 expr1.X_add_number = 2;
7395 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7396 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7398 --mips_opts.noreorder;
7399 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7405 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7406 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7407 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7416 if (imm_expr.X_op != O_constant)
7417 as_bad (_("Unsupported large constant"));
7418 imm_expr.X_add_number = -imm_expr.X_add_number;
7419 macro_build ((char *) NULL, &icnt, &imm_expr,
7420 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7424 if (imm_expr.X_op != O_constant)
7425 as_bad (_("Unsupported large constant"));
7426 imm_expr.X_add_number = -imm_expr.X_add_number;
7427 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7432 if (imm_expr.X_op != O_constant)
7433 as_bad (_("Unsupported large constant"));
7434 imm_expr.X_add_number = -imm_expr.X_add_number;
7435 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7458 goto do_reverse_branch;
7462 goto do_reverse_branch;
7474 goto do_reverse_branch;
7485 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7487 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7514 goto do_addone_branch_i;
7519 goto do_addone_branch_i;
7534 goto do_addone_branch_i;
7541 if (imm_expr.X_op != O_constant)
7542 as_bad (_("Unsupported large constant"));
7543 ++imm_expr.X_add_number;
7546 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7547 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7551 expr1.X_add_number = 0;
7552 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7554 move_register (&icnt, xreg, yreg);
7555 expr1.X_add_number = 2;
7556 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7557 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7558 "neg", "x,w", xreg, xreg);
7562 /* For consistency checking, verify that all bits are specified either
7563 by the match/mask part of the instruction definition, or by the
7566 validate_mips_insn (opc)
7567 const struct mips_opcode *opc;
7569 const char *p = opc->args;
7571 unsigned long used_bits = opc->mask;
7573 if ((used_bits & opc->match) != opc->match)
7575 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7576 opc->name, opc->args);
7579 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7586 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7587 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7589 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7590 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7591 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7592 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7594 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7595 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7597 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7599 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7600 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7601 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7602 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7603 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7604 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7605 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7606 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7607 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7608 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7609 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7610 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7611 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7612 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7613 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7614 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7615 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7617 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7618 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7619 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7620 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7622 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7623 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7624 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7625 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7626 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7627 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7628 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7629 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7630 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7633 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7634 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7635 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7637 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7638 c, opc->name, opc->args);
7642 if (used_bits != 0xffffffff)
7644 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7645 ~used_bits & 0xffffffff, opc->name, opc->args);
7651 /* This routine assembles an instruction into its binary format. As a
7652 side effect, it sets one of the global variables imm_reloc or
7653 offset_reloc to the type of relocation to do if one of the operands
7654 is an address expression. */
7659 struct mips_cl_insn *ip;
7664 struct mips_opcode *insn;
7667 unsigned int lastregno = 0;
7673 /* If the instruction contains a '.', we first try to match an instruction
7674 including the '.'. Then we try again without the '.'. */
7676 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7679 /* If we stopped on whitespace, then replace the whitespace with null for
7680 the call to hash_find. Save the character we replaced just in case we
7681 have to re-parse the instruction. */
7688 insn = (struct mips_opcode *) hash_find (op_hash, str);
7690 /* If we didn't find the instruction in the opcode table, try again, but
7691 this time with just the instruction up to, but not including the
7695 /* Restore the character we overwrite above (if any). */
7699 /* Scan up to the first '.' or whitespace. */
7701 *s != '\0' && *s != '.' && !ISSPACE (*s);
7705 /* If we did not find a '.', then we can quit now. */
7708 insn_error = "unrecognized opcode";
7712 /* Lookup the instruction in the hash table. */
7714 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7716 insn_error = "unrecognized opcode";
7726 assert (strcmp (insn->name, str) == 0);
7728 if (OPCODE_IS_MEMBER (insn,
7730 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
7731 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7732 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7738 if (insn->pinfo != INSN_MACRO)
7740 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7746 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7747 && strcmp (insn->name, insn[1].name) == 0)
7756 static char buf[100];
7757 if (mips_arch_info->is_isa)
7759 _("opcode not supported at this ISA level (%s)"),
7760 mips_cpu_info_from_isa (mips_opts.isa)->name);
7763 _("opcode not supported on this processor: %s (%s)"),
7764 mips_arch_info->name,
7765 mips_cpu_info_from_isa (mips_opts.isa)->name);
7775 ip->insn_opcode = insn->match;
7777 for (args = insn->args;; ++args)
7781 s += strspn (s, " \t");
7785 case '\0': /* end of args */
7798 ip->insn_opcode |= lastregno << OP_SH_RS;
7802 ip->insn_opcode |= lastregno << OP_SH_RT;
7806 ip->insn_opcode |= lastregno << OP_SH_FT;
7810 ip->insn_opcode |= lastregno << OP_SH_FS;
7816 /* Handle optional base register.
7817 Either the base register is omitted or
7818 we must have a left paren. */
7819 /* This is dependent on the next operand specifier
7820 is a base register specification. */
7821 assert (args[1] == 'b' || args[1] == '5'
7822 || args[1] == '-' || args[1] == '4');
7826 case ')': /* these must match exactly */
7831 case '<': /* must be at least one digit */
7833 * According to the manual, if the shift amount is greater
7834 * than 31 or less than 0, then the shift amount should be
7835 * mod 32. In reality the mips assembler issues an error.
7836 * We issue a warning and mask out all but the low 5 bits.
7838 my_getExpression (&imm_expr, s);
7839 check_absolute_expr (ip, &imm_expr);
7840 if ((unsigned long) imm_expr.X_add_number > 31)
7842 as_warn (_("Improper shift amount (%lu)"),
7843 (unsigned long) imm_expr.X_add_number);
7844 imm_expr.X_add_number &= OP_MASK_SHAMT;
7846 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7847 imm_expr.X_op = O_absent;
7851 case '>': /* shift amount minus 32 */
7852 my_getExpression (&imm_expr, s);
7853 check_absolute_expr (ip, &imm_expr);
7854 if ((unsigned long) imm_expr.X_add_number < 32
7855 || (unsigned long) imm_expr.X_add_number > 63)
7857 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7858 imm_expr.X_op = O_absent;
7862 case 'k': /* cache code */
7863 case 'h': /* prefx code */
7864 my_getExpression (&imm_expr, s);
7865 check_absolute_expr (ip, &imm_expr);
7866 if ((unsigned long) imm_expr.X_add_number > 31)
7868 as_warn (_("Invalid value for `%s' (%lu)"),
7870 (unsigned long) imm_expr.X_add_number);
7871 imm_expr.X_add_number &= 0x1f;
7874 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7876 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7877 imm_expr.X_op = O_absent;
7881 case 'c': /* break code */
7882 my_getExpression (&imm_expr, s);
7883 check_absolute_expr (ip, &imm_expr);
7884 if ((unsigned long) imm_expr.X_add_number > 1023)
7886 as_warn (_("Illegal break code (%lu)"),
7887 (unsigned long) imm_expr.X_add_number);
7888 imm_expr.X_add_number &= OP_MASK_CODE;
7890 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7891 imm_expr.X_op = O_absent;
7895 case 'q': /* lower break code */
7896 my_getExpression (&imm_expr, s);
7897 check_absolute_expr (ip, &imm_expr);
7898 if ((unsigned long) imm_expr.X_add_number > 1023)
7900 as_warn (_("Illegal lower break code (%lu)"),
7901 (unsigned long) imm_expr.X_add_number);
7902 imm_expr.X_add_number &= OP_MASK_CODE2;
7904 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7905 imm_expr.X_op = O_absent;
7909 case 'B': /* 20-bit syscall/break code. */
7910 my_getExpression (&imm_expr, s);
7911 check_absolute_expr (ip, &imm_expr);
7912 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7913 as_warn (_("Illegal 20-bit code (%lu)"),
7914 (unsigned long) imm_expr.X_add_number);
7915 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7916 imm_expr.X_op = O_absent;
7920 case 'C': /* Coprocessor code */
7921 my_getExpression (&imm_expr, s);
7922 check_absolute_expr (ip, &imm_expr);
7923 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7925 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7926 (unsigned long) imm_expr.X_add_number);
7927 imm_expr.X_add_number &= ((1 << 25) - 1);
7929 ip->insn_opcode |= imm_expr.X_add_number;
7930 imm_expr.X_op = O_absent;
7934 case 'J': /* 19-bit wait code. */
7935 my_getExpression (&imm_expr, s);
7936 check_absolute_expr (ip, &imm_expr);
7937 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7938 as_warn (_("Illegal 19-bit code (%lu)"),
7939 (unsigned long) imm_expr.X_add_number);
7940 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7941 imm_expr.X_op = O_absent;
7945 case 'P': /* Performance register */
7946 my_getExpression (&imm_expr, s);
7947 check_absolute_expr (ip, &imm_expr);
7948 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7950 as_warn (_("Invalid performance register (%lu)"),
7951 (unsigned long) imm_expr.X_add_number);
7952 imm_expr.X_add_number &= OP_MASK_PERFREG;
7954 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7955 imm_expr.X_op = O_absent;
7959 case 'b': /* base register */
7960 case 'd': /* destination register */
7961 case 's': /* source register */
7962 case 't': /* target register */
7963 case 'r': /* both target and source */
7964 case 'v': /* both dest and source */
7965 case 'w': /* both dest and target */
7966 case 'E': /* coprocessor target register */
7967 case 'G': /* coprocessor destination register */
7968 case 'x': /* ignore register name */
7969 case 'z': /* must be zero register */
7970 case 'U': /* destination register (clo/clz). */
7985 while (ISDIGIT (*s));
7987 as_bad (_("Invalid register number (%d)"), regno);
7989 else if (*args == 'E' || *args == 'G')
7993 if (s[1] == 'r' && s[2] == 'a')
7998 else if (s[1] == 'f' && s[2] == 'p')
8003 else if (s[1] == 's' && s[2] == 'p')
8008 else if (s[1] == 'g' && s[2] == 'p')
8013 else if (s[1] == 'a' && s[2] == 't')
8018 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8023 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8028 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8033 else if (itbl_have_entries)
8038 p = s + 1; /* advance past '$' */
8039 n = itbl_get_field (&p); /* n is name */
8041 /* See if this is a register defined in an
8043 if (itbl_get_reg_val (n, &r))
8045 /* Get_field advances to the start of
8046 the next field, so we need to back
8047 rack to the end of the last field. */
8051 s = strchr (s, '\0');
8064 as_warn (_("Used $at without \".set noat\""));
8070 if (c == 'r' || c == 'v' || c == 'w')
8077 /* 'z' only matches $0. */
8078 if (c == 'z' && regno != 0)
8081 /* Now that we have assembled one operand, we use the args string
8082 * to figure out where it goes in the instruction. */
8089 ip->insn_opcode |= regno << OP_SH_RS;
8093 ip->insn_opcode |= regno << OP_SH_RD;
8096 ip->insn_opcode |= regno << OP_SH_RD;
8097 ip->insn_opcode |= regno << OP_SH_RT;
8102 ip->insn_opcode |= regno << OP_SH_RT;
8105 /* This case exists because on the r3000 trunc
8106 expands into a macro which requires a gp
8107 register. On the r6000 or r4000 it is
8108 assembled into a single instruction which
8109 ignores the register. Thus the insn version
8110 is MIPS_ISA2 and uses 'x', and the macro
8111 version is MIPS_ISA1 and uses 't'. */
8114 /* This case is for the div instruction, which
8115 acts differently if the destination argument
8116 is $0. This only matches $0, and is checked
8117 outside the switch. */
8120 /* Itbl operand; not yet implemented. FIXME ?? */
8122 /* What about all other operands like 'i', which
8123 can be specified in the opcode table? */
8133 ip->insn_opcode |= lastregno << OP_SH_RS;
8136 ip->insn_opcode |= lastregno << OP_SH_RT;
8141 case 'O': /* MDMX alignment immediate constant. */
8142 my_getExpression (&imm_expr, s);
8143 check_absolute_expr (ip, &imm_expr);
8144 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8146 as_warn ("Improper align amount (%ld), using low bits",
8147 (long) imm_expr.X_add_number);
8148 imm_expr.X_add_number &= OP_MASK_ALN;
8150 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8151 imm_expr.X_op = O_absent;
8155 case 'Q': /* MDMX vector, element sel, or const. */
8158 /* MDMX Immediate. */
8159 my_getExpression (&imm_expr, s);
8160 check_absolute_expr (ip, &imm_expr);
8161 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8163 as_warn (_("Invalid MDMX Immediate (%ld)"),
8164 (long) imm_expr.X_add_number);
8165 imm_expr.X_add_number &= OP_MASK_FT;
8167 imm_expr.X_add_number &= OP_MASK_FT;
8168 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8169 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8171 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8172 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8173 imm_expr.X_op = O_absent;
8177 /* Not MDMX Immediate. Fall through. */
8178 case 'X': /* MDMX destination register. */
8179 case 'Y': /* MDMX source register. */
8180 case 'Z': /* MDMX target register. */
8182 case 'D': /* floating point destination register */
8183 case 'S': /* floating point source register */
8184 case 'T': /* floating point target register */
8185 case 'R': /* floating point source register */
8189 /* Accept $fN for FP and MDMX register numbers, and in
8190 addition accept $vN for MDMX register numbers. */
8191 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8192 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8203 while (ISDIGIT (*s));
8206 as_bad (_("Invalid float register number (%d)"), regno);
8208 if ((regno & 1) != 0
8210 && ! (strcmp (str, "mtc1") == 0
8211 || strcmp (str, "mfc1") == 0
8212 || strcmp (str, "lwc1") == 0
8213 || strcmp (str, "swc1") == 0
8214 || strcmp (str, "l.s") == 0
8215 || strcmp (str, "s.s") == 0))
8216 as_warn (_("Float register should be even, was %d"),
8224 if (c == 'V' || c == 'W')
8235 ip->insn_opcode |= regno << OP_SH_FD;
8240 ip->insn_opcode |= regno << OP_SH_FS;
8243 /* This is like 'Z', but also needs to fix the MDMX
8244 vector/scalar select bits. Note that the
8245 scalar immediate case is handled above. */
8248 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8249 int max_el = (is_qh ? 3 : 7);
8251 my_getExpression(&imm_expr, s);
8252 check_absolute_expr (ip, &imm_expr);
8254 if (imm_expr.X_add_number > max_el)
8255 as_bad(_("Bad element selector %ld"),
8256 (long) imm_expr.X_add_number);
8257 imm_expr.X_add_number &= max_el;
8258 ip->insn_opcode |= (imm_expr.X_add_number
8262 as_warn(_("Expecting ']' found '%s'"), s);
8268 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8269 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8272 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8279 ip->insn_opcode |= regno << OP_SH_FT;
8282 ip->insn_opcode |= regno << OP_SH_FR;
8292 ip->insn_opcode |= lastregno << OP_SH_FS;
8295 ip->insn_opcode |= lastregno << OP_SH_FT;
8301 my_getExpression (&imm_expr, s);
8302 if (imm_expr.X_op != O_big
8303 && imm_expr.X_op != O_constant)
8304 insn_error = _("absolute expression required");
8309 my_getExpression (&offset_expr, s);
8310 *imm_reloc = BFD_RELOC_32;
8323 unsigned char temp[8];
8325 unsigned int length;
8330 /* These only appear as the last operand in an
8331 instruction, and every instruction that accepts
8332 them in any variant accepts them in all variants.
8333 This means we don't have to worry about backing out
8334 any changes if the instruction does not match.
8336 The difference between them is the size of the
8337 floating point constant and where it goes. For 'F'
8338 and 'L' the constant is 64 bits; for 'f' and 'l' it
8339 is 32 bits. Where the constant is placed is based
8340 on how the MIPS assembler does things:
8343 f -- immediate value
8346 The .lit4 and .lit8 sections are only used if
8347 permitted by the -G argument.
8349 When generating embedded PIC code, we use the
8350 .lit8 section but not the .lit4 section (we can do
8351 .lit4 inline easily; we need to put .lit8
8352 somewhere in the data segment, and using .lit8
8353 permits the linker to eventually combine identical
8356 The code below needs to know whether the target register
8357 is 32 or 64 bits wide. It relies on the fact 'f' and
8358 'F' are used with GPR-based instructions and 'l' and
8359 'L' are used with FPR-based instructions. */
8361 f64 = *args == 'F' || *args == 'L';
8362 using_gprs = *args == 'F' || *args == 'f';
8364 save_in = input_line_pointer;
8365 input_line_pointer = s;
8366 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8368 s = input_line_pointer;
8369 input_line_pointer = save_in;
8370 if (err != NULL && *err != '\0')
8372 as_bad (_("Bad floating point constant: %s"), err);
8373 memset (temp, '\0', sizeof temp);
8374 length = f64 ? 8 : 4;
8377 assert (length == (unsigned) (f64 ? 8 : 4));
8381 && (! USE_GLOBAL_POINTER_OPT
8382 || mips_pic == EMBEDDED_PIC
8383 || g_switch_value < 4
8384 || (temp[0] == 0 && temp[1] == 0)
8385 || (temp[2] == 0 && temp[3] == 0))))
8387 imm_expr.X_op = O_constant;
8388 if (! target_big_endian)
8389 imm_expr.X_add_number = bfd_getl32 (temp);
8391 imm_expr.X_add_number = bfd_getb32 (temp);
8394 && ! mips_disable_float_construction
8395 /* Constants can only be constructed in GPRs and
8396 copied to FPRs if the GPRs are at least as wide
8397 as the FPRs. Force the constant into memory if
8398 we are using 64-bit FPRs but the GPRs are only
8401 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8402 && ((temp[0] == 0 && temp[1] == 0)
8403 || (temp[2] == 0 && temp[3] == 0))
8404 && ((temp[4] == 0 && temp[5] == 0)
8405 || (temp[6] == 0 && temp[7] == 0)))
8407 /* The value is simple enough to load with a couple of
8408 instructions. If using 32-bit registers, set
8409 imm_expr to the high order 32 bits and offset_expr to
8410 the low order 32 bits. Otherwise, set imm_expr to
8411 the entire 64 bit constant. */
8412 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8414 imm_expr.X_op = O_constant;
8415 offset_expr.X_op = O_constant;
8416 if (! target_big_endian)
8418 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8419 offset_expr.X_add_number = bfd_getl32 (temp);
8423 imm_expr.X_add_number = bfd_getb32 (temp);
8424 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8426 if (offset_expr.X_add_number == 0)
8427 offset_expr.X_op = O_absent;
8429 else if (sizeof (imm_expr.X_add_number) > 4)
8431 imm_expr.X_op = O_constant;
8432 if (! target_big_endian)
8433 imm_expr.X_add_number = bfd_getl64 (temp);
8435 imm_expr.X_add_number = bfd_getb64 (temp);
8439 imm_expr.X_op = O_big;
8440 imm_expr.X_add_number = 4;
8441 if (! target_big_endian)
8443 generic_bignum[0] = bfd_getl16 (temp);
8444 generic_bignum[1] = bfd_getl16 (temp + 2);
8445 generic_bignum[2] = bfd_getl16 (temp + 4);
8446 generic_bignum[3] = bfd_getl16 (temp + 6);
8450 generic_bignum[0] = bfd_getb16 (temp + 6);
8451 generic_bignum[1] = bfd_getb16 (temp + 4);
8452 generic_bignum[2] = bfd_getb16 (temp + 2);
8453 generic_bignum[3] = bfd_getb16 (temp);
8459 const char *newname;
8462 /* Switch to the right section. */
8464 subseg = now_subseg;
8467 default: /* unused default case avoids warnings. */
8469 newname = RDATA_SECTION_NAME;
8470 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8471 || mips_pic == EMBEDDED_PIC)
8475 if (mips_pic == EMBEDDED_PIC)
8478 newname = RDATA_SECTION_NAME;
8481 assert (!USE_GLOBAL_POINTER_OPT
8482 || g_switch_value >= 4);
8486 new_seg = subseg_new (newname, (subsegT) 0);
8487 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8488 bfd_set_section_flags (stdoutput, new_seg,
8493 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8494 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8495 && strcmp (TARGET_OS, "elf") != 0)
8496 record_alignment (new_seg, 4);
8498 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8500 as_bad (_("Can't use floating point insn in this section"));
8502 /* Set the argument to the current address in the
8504 offset_expr.X_op = O_symbol;
8505 offset_expr.X_add_symbol =
8506 symbol_new ("L0\001", now_seg,
8507 (valueT) frag_now_fix (), frag_now);
8508 offset_expr.X_add_number = 0;
8510 /* Put the floating point number into the section. */
8511 p = frag_more ((int) length);
8512 memcpy (p, temp, length);
8514 /* Switch back to the original section. */
8515 subseg_set (seg, subseg);
8520 case 'i': /* 16 bit unsigned immediate */
8521 case 'j': /* 16 bit signed immediate */
8522 *imm_reloc = BFD_RELOC_LO16;
8523 c = my_getSmallExpression (&imm_expr, s);
8528 if (imm_expr.X_op == O_constant)
8529 imm_expr.X_add_number =
8530 (imm_expr.X_add_number >> 16) & 0xffff;
8532 else if (c == S_EX_HIGHEST)
8533 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8534 else if (c == S_EX_HIGHER)
8535 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8536 else if (c == S_EX_GP_REL)
8538 /* This occurs in NewABI only. */
8539 c = my_getSmallExpression (&imm_expr, s);
8541 as_bad (_("bad composition of relocations"));
8544 c = my_getSmallExpression (&imm_expr, s);
8546 as_bad (_("bad composition of relocations"));
8549 imm_reloc[0] = BFD_RELOC_GPREL16;
8550 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8551 imm_reloc[2] = BFD_RELOC_LO16;
8556 else if (c == S_EX_HI)
8558 *imm_reloc = BFD_RELOC_HI16_S;
8559 imm_unmatched_hi = true;
8562 *imm_reloc = BFD_RELOC_HI16;
8564 else if (imm_expr.X_op == O_constant)
8565 imm_expr.X_add_number &= 0xffff;
8569 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8570 || ((imm_expr.X_add_number < 0
8571 || imm_expr.X_add_number >= 0x10000)
8572 && imm_expr.X_op == O_constant))
8574 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8575 !strcmp (insn->name, insn[1].name))
8577 if (imm_expr.X_op == O_constant
8578 || imm_expr.X_op == O_big)
8579 as_bad (_("16 bit expression not in range 0..65535"));
8587 /* The upper bound should be 0x8000, but
8588 unfortunately the MIPS assembler accepts numbers
8589 from 0x8000 to 0xffff and sign extends them, and
8590 we want to be compatible. We only permit this
8591 extended range for an instruction which does not
8592 provide any further alternates, since those
8593 alternates may handle other cases. People should
8594 use the numbers they mean, rather than relying on
8595 a mysterious sign extension. */
8596 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8597 strcmp (insn->name, insn[1].name) == 0);
8602 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8603 || ((imm_expr.X_add_number < -0x8000
8604 || imm_expr.X_add_number >= max)
8605 && imm_expr.X_op == O_constant)
8607 && imm_expr.X_add_number < 0
8609 && imm_expr.X_unsigned
8610 && sizeof (imm_expr.X_add_number) <= 4))
8614 if (imm_expr.X_op == O_constant
8615 || imm_expr.X_op == O_big)
8616 as_bad (_("16 bit expression not in range -32768..32767"));
8622 case 'o': /* 16 bit offset */
8623 c = my_getSmallExpression (&offset_expr, s);
8625 /* If this value won't fit into a 16 bit offset, then go
8626 find a macro that will generate the 32 bit offset
8629 && (offset_expr.X_op != O_constant
8630 || offset_expr.X_add_number >= 0x8000
8631 || offset_expr.X_add_number < -0x8000))
8636 if (offset_expr.X_op != O_constant)
8638 offset_expr.X_add_number =
8639 (offset_expr.X_add_number >> 16) & 0xffff;
8641 *offset_reloc = BFD_RELOC_LO16;
8645 case 'p': /* pc relative offset */
8646 if (mips_pic == EMBEDDED_PIC)
8647 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8649 *offset_reloc = BFD_RELOC_16_PCREL;
8650 my_getExpression (&offset_expr, s);
8654 case 'u': /* upper 16 bits */
8655 c = my_getSmallExpression (&imm_expr, s);
8656 *imm_reloc = BFD_RELOC_LO16;
8661 if (imm_expr.X_op == O_constant)
8662 imm_expr.X_add_number =
8663 (imm_expr.X_add_number >> 16) & 0xffff;
8664 else if (c == S_EX_HI)
8666 *imm_reloc = BFD_RELOC_HI16_S;
8667 imm_unmatched_hi = true;
8670 else if (c == S_EX_HIGHEST)
8671 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8672 else if (c == S_EX_GP_REL)
8674 /* This occurs in NewABI only. */
8675 c = my_getSmallExpression (&imm_expr, s);
8677 as_bad (_("bad composition of relocations"));
8680 c = my_getSmallExpression (&imm_expr, s);
8682 as_bad (_("bad composition of relocations"));
8685 imm_reloc[0] = BFD_RELOC_GPREL16;
8686 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8687 imm_reloc[2] = BFD_RELOC_HI16_S;
8693 *imm_reloc = BFD_RELOC_HI16;
8695 else if (imm_expr.X_op == O_constant)
8696 imm_expr.X_add_number &= 0xffff;
8698 if (imm_expr.X_op == O_constant
8699 && (imm_expr.X_add_number < 0
8700 || imm_expr.X_add_number >= 0x10000))
8701 as_bad (_("lui expression not in range 0..65535"));
8705 case 'a': /* 26 bit address */
8706 my_getExpression (&offset_expr, s);
8708 *offset_reloc = BFD_RELOC_MIPS_JMP;
8711 case 'N': /* 3 bit branch condition code */
8712 case 'M': /* 3 bit compare condition code */
8713 if (strncmp (s, "$fcc", 4) != 0)
8723 while (ISDIGIT (*s));
8725 as_bad (_("invalid condition code register $fcc%d"), regno);
8727 ip->insn_opcode |= regno << OP_SH_BCC;
8729 ip->insn_opcode |= regno << OP_SH_CCC;
8733 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8744 while (ISDIGIT (*s));
8747 c = 8; /* Invalid sel value. */
8750 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8751 ip->insn_opcode |= c;
8755 as_bad (_("bad char = '%c'\n"), *args);
8760 /* Args don't match. */
8761 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8762 !strcmp (insn->name, insn[1].name))
8766 insn_error = _("illegal operands");
8771 insn_error = _("illegal operands");
8776 /* This routine assembles an instruction into its binary format when
8777 assembling for the mips16. As a side effect, it sets one of the
8778 global variables imm_reloc or offset_reloc to the type of
8779 relocation to do if one of the operands is an address expression.
8780 It also sets mips16_small and mips16_ext if the user explicitly
8781 requested a small or extended instruction. */
8786 struct mips_cl_insn *ip;
8790 struct mips_opcode *insn;
8793 unsigned int lastregno = 0;
8798 mips16_small = false;
8801 for (s = str; ISLOWER (*s); ++s)
8813 if (s[1] == 't' && s[2] == ' ')
8816 mips16_small = true;
8820 else if (s[1] == 'e' && s[2] == ' ')
8829 insn_error = _("unknown opcode");
8833 if (mips_opts.noautoextend && ! mips16_ext)
8834 mips16_small = true;
8836 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8838 insn_error = _("unrecognized opcode");
8845 assert (strcmp (insn->name, str) == 0);
8848 ip->insn_opcode = insn->match;
8849 ip->use_extend = false;
8850 imm_expr.X_op = O_absent;
8851 imm_reloc[0] = BFD_RELOC_UNUSED;
8852 imm_reloc[1] = BFD_RELOC_UNUSED;
8853 imm_reloc[2] = BFD_RELOC_UNUSED;
8854 offset_expr.X_op = O_absent;
8855 offset_reloc[0] = BFD_RELOC_UNUSED;
8856 offset_reloc[1] = BFD_RELOC_UNUSED;
8857 offset_reloc[2] = BFD_RELOC_UNUSED;
8858 for (args = insn->args; 1; ++args)
8865 /* In this switch statement we call break if we did not find
8866 a match, continue if we did find a match, or return if we
8875 /* Stuff the immediate value in now, if we can. */
8876 if (imm_expr.X_op == O_constant
8877 && *imm_reloc > BFD_RELOC_UNUSED
8878 && insn->pinfo != INSN_MACRO)
8880 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8881 imm_expr.X_add_number, true, mips16_small,
8882 mips16_ext, &ip->insn_opcode,
8883 &ip->use_extend, &ip->extend);
8884 imm_expr.X_op = O_absent;
8885 *imm_reloc = BFD_RELOC_UNUSED;
8899 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8902 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8918 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8920 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8947 while (ISDIGIT (*s));
8950 as_bad (_("invalid register number (%d)"), regno);
8956 if (s[1] == 'r' && s[2] == 'a')
8961 else if (s[1] == 'f' && s[2] == 'p')
8966 else if (s[1] == 's' && s[2] == 'p')
8971 else if (s[1] == 'g' && s[2] == 'p')
8976 else if (s[1] == 'a' && s[2] == 't')
8981 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8986 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8991 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9004 if (c == 'v' || c == 'w')
9006 regno = mips16_to_32_reg_map[lastregno];
9020 regno = mips32_to_16_reg_map[regno];
9025 regno = ILLEGAL_REG;
9030 regno = ILLEGAL_REG;
9035 regno = ILLEGAL_REG;
9040 if (regno == AT && ! mips_opts.noat)
9041 as_warn (_("used $at without \".set noat\""));
9048 if (regno == ILLEGAL_REG)
9055 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9059 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9062 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9065 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9071 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9074 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9075 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9085 if (strncmp (s, "$pc", 3) == 0)
9109 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9111 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9112 and generate the appropriate reloc. If the text
9113 inside %gprel is not a symbol name with an
9114 optional offset, then we generate a normal reloc
9115 and will probably fail later. */
9116 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9117 if (imm_expr.X_op == O_symbol)
9120 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9122 ip->use_extend = true;
9129 /* Just pick up a normal expression. */
9130 my_getExpression (&imm_expr, s);
9133 if (imm_expr.X_op == O_register)
9135 /* What we thought was an expression turned out to
9138 if (s[0] == '(' && args[1] == '(')
9140 /* It looks like the expression was omitted
9141 before a register indirection, which means
9142 that the expression is implicitly zero. We
9143 still set up imm_expr, so that we handle
9144 explicit extensions correctly. */
9145 imm_expr.X_op = O_constant;
9146 imm_expr.X_add_number = 0;
9147 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9154 /* We need to relax this instruction. */
9155 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9164 /* We use offset_reloc rather than imm_reloc for the PC
9165 relative operands. This lets macros with both
9166 immediate and address operands work correctly. */
9167 my_getExpression (&offset_expr, s);
9169 if (offset_expr.X_op == O_register)
9172 /* We need to relax this instruction. */
9173 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9177 case '6': /* break code */
9178 my_getExpression (&imm_expr, s);
9179 check_absolute_expr (ip, &imm_expr);
9180 if ((unsigned long) imm_expr.X_add_number > 63)
9182 as_warn (_("Invalid value for `%s' (%lu)"),
9184 (unsigned long) imm_expr.X_add_number);
9185 imm_expr.X_add_number &= 0x3f;
9187 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9188 imm_expr.X_op = O_absent;
9192 case 'a': /* 26 bit address */
9193 my_getExpression (&offset_expr, s);
9195 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9196 ip->insn_opcode <<= 16;
9199 case 'l': /* register list for entry macro */
9200 case 'L': /* register list for exit macro */
9210 int freg, reg1, reg2;
9212 while (*s == ' ' || *s == ',')
9216 as_bad (_("can't parse register list"));
9228 while (ISDIGIT (*s))
9250 as_bad (_("invalid register list"));
9255 while (ISDIGIT (*s))
9262 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9267 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9272 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9273 mask |= (reg2 - 3) << 3;
9274 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9275 mask |= (reg2 - 15) << 1;
9276 else if (reg1 == RA && reg2 == RA)
9280 as_bad (_("invalid register list"));
9284 /* The mask is filled in in the opcode table for the
9285 benefit of the disassembler. We remove it before
9286 applying the actual mask. */
9287 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9288 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9292 case 'e': /* extend code */
9293 my_getExpression (&imm_expr, s);
9294 check_absolute_expr (ip, &imm_expr);
9295 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9297 as_warn (_("Invalid value for `%s' (%lu)"),
9299 (unsigned long) imm_expr.X_add_number);
9300 imm_expr.X_add_number &= 0x7ff;
9302 ip->insn_opcode |= imm_expr.X_add_number;
9303 imm_expr.X_op = O_absent;
9313 /* Args don't match. */
9314 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9315 strcmp (insn->name, insn[1].name) == 0)
9322 insn_error = _("illegal operands");
9328 /* This structure holds information we know about a mips16 immediate
9331 struct mips16_immed_operand
9333 /* The type code used in the argument string in the opcode table. */
9335 /* The number of bits in the short form of the opcode. */
9337 /* The number of bits in the extended form of the opcode. */
9339 /* The amount by which the short form is shifted when it is used;
9340 for example, the sw instruction has a shift count of 2. */
9342 /* The amount by which the short form is shifted when it is stored
9343 into the instruction code. */
9345 /* Non-zero if the short form is unsigned. */
9347 /* Non-zero if the extended form is unsigned. */
9349 /* Non-zero if the value is PC relative. */
9353 /* The mips16 immediate operand types. */
9355 static const struct mips16_immed_operand mips16_immed_operands[] =
9357 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9358 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9359 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9360 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9361 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9362 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9363 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9364 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9365 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9366 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9367 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9368 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9369 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9370 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9371 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9372 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9373 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9374 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9375 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9376 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9377 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9380 #define MIPS16_NUM_IMMED \
9381 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9383 /* Handle a mips16 instruction with an immediate value. This or's the
9384 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9385 whether an extended value is needed; if one is needed, it sets
9386 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9387 If SMALL is true, an unextended opcode was explicitly requested.
9388 If EXT is true, an extended opcode was explicitly requested. If
9389 WARN is true, warn if EXT does not match reality. */
9392 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9401 unsigned long *insn;
9402 boolean *use_extend;
9403 unsigned short *extend;
9405 register const struct mips16_immed_operand *op;
9406 int mintiny, maxtiny;
9409 op = mips16_immed_operands;
9410 while (op->type != type)
9413 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9418 if (type == '<' || type == '>' || type == '[' || type == ']')
9421 maxtiny = 1 << op->nbits;
9426 maxtiny = (1 << op->nbits) - 1;
9431 mintiny = - (1 << (op->nbits - 1));
9432 maxtiny = (1 << (op->nbits - 1)) - 1;
9435 /* Branch offsets have an implicit 0 in the lowest bit. */
9436 if (type == 'p' || type == 'q')
9439 if ((val & ((1 << op->shift) - 1)) != 0
9440 || val < (mintiny << op->shift)
9441 || val > (maxtiny << op->shift))
9446 if (warn && ext && ! needext)
9447 as_warn_where (file, line,
9448 _("extended operand requested but not required"));
9449 if (small && needext)
9450 as_bad_where (file, line, _("invalid unextended operand value"));
9452 if (small || (! ext && ! needext))
9456 *use_extend = false;
9457 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9458 insnval <<= op->op_shift;
9463 long minext, maxext;
9469 maxext = (1 << op->extbits) - 1;
9473 minext = - (1 << (op->extbits - 1));
9474 maxext = (1 << (op->extbits - 1)) - 1;
9476 if (val < minext || val > maxext)
9477 as_bad_where (file, line,
9478 _("operand value out of range for instruction"));
9481 if (op->extbits == 16)
9483 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9486 else if (op->extbits == 15)
9488 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9493 extval = ((val & 0x1f) << 6) | (val & 0x20);
9497 *extend = (unsigned short) extval;
9502 static struct percent_op_match
9505 const enum small_ex_type type;
9510 {"%call_hi", S_EX_CALL_HI},
9511 {"%call_lo", S_EX_CALL_LO},
9512 {"%call16", S_EX_CALL16},
9513 {"%got_disp", S_EX_GOT_DISP},
9514 {"%got_page", S_EX_GOT_PAGE},
9515 {"%got_ofst", S_EX_GOT_OFST},
9516 {"%got_hi", S_EX_GOT_HI},
9517 {"%got_lo", S_EX_GOT_LO},
9519 {"%gp_rel", S_EX_GP_REL},
9520 {"%half", S_EX_HALF},
9521 {"%highest", S_EX_HIGHEST},
9522 {"%higher", S_EX_HIGHER},
9528 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9529 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9530 can be nested, this is handled by blanking the innermost, parsing the
9531 rest by subsequent calls. */
9534 my_getSmallParser (str, len, nestlevel)
9540 *str += strspn (*str, " \t");
9541 /* Check for expression in parentheses. */
9544 char *b = *str + 1 + strspn (*str + 1, " \t");
9547 /* Check for base register. */
9551 && (e = b + strcspn (b, ") \t"))
9552 && e - b > 1 && e - b < 4)
9555 && ((b[1] == 'f' && b[2] == 'p')
9556 || (b[1] == 's' && b[2] == 'p')
9557 || (b[1] == 'g' && b[2] == 'p')
9558 || (b[1] == 'a' && b[2] == 't')
9560 && ISDIGIT (b[2]))))
9561 || (ISDIGIT (b[1])))
9563 *len = strcspn (*str, ")") + 1;
9564 return S_EX_REGISTER;
9568 /* Check for percent_op (in parentheses). */
9569 else if (b[0] == '%')
9572 return my_getPercentOp (str, len, nestlevel);
9575 /* Some other expression in the parentheses, which can contain
9576 parentheses itself. Attempt to find the matching one. */
9582 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9591 /* Check for percent_op (outside of parentheses). */
9592 else if (*str[0] == '%')
9593 return my_getPercentOp (str, len, nestlevel);
9595 /* Any other expression. */
9600 my_getPercentOp (str, len, nestlevel)
9605 char *tmp = *str + 1;
9608 while (ISALPHA (*tmp) || *tmp == '_')
9610 *tmp = TOLOWER (*tmp);
9613 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9615 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9619 int type = percent_op[i].type;
9621 /* Only %hi and %lo are allowed for OldABI. */
9622 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9625 *len = strlen (percent_op[i].str);
9634 my_getSmallExpression (ep, str)
9638 static char *oldstr = NULL;
9644 /* Don't update oldstr if the last call had nested percent_op's. We need
9645 it to parse the outer ones later. */
9652 c = my_getSmallParser (&str, &len, &nestlevel);
9653 if (c != S_EX_NONE && c != S_EX_REGISTER)
9656 while (c != S_EX_NONE && c != S_EX_REGISTER);
9660 /* A percent_op was encountered. Don't try to get an expression if
9661 it is already blanked out. */
9662 if (*(str + strspn (str + 1, " )")) != ')')
9666 /* Let my_getExpression() stop at the closing parenthesis. */
9667 save = *(str + len);
9668 *(str + len) = '\0';
9669 my_getExpression (ep, str);
9670 *(str + len) = save;
9674 /* Blank out including the % sign and the proper matching
9677 char *s = strrchr (oldstr, '%');
9680 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9684 else if (*end == ')')
9688 memset (s, ' ', end - s);
9692 expr_end = str + len;
9696 else if (c == S_EX_NONE)
9698 my_getExpression (ep, str);
9700 else if (c == S_EX_REGISTER)
9702 ep->X_op = O_constant;
9704 ep->X_add_symbol = NULL;
9705 ep->X_op_symbol = NULL;
9706 ep->X_add_number = 0;
9710 as_fatal (_("internal error"));
9714 /* All percent_op's have been handled. */
9721 my_getExpression (ep, str)
9728 save_in = input_line_pointer;
9729 input_line_pointer = str;
9731 expr_end = input_line_pointer;
9732 input_line_pointer = save_in;
9734 /* If we are in mips16 mode, and this is an expression based on `.',
9735 then we bump the value of the symbol by 1 since that is how other
9736 text symbols are handled. We don't bother to handle complex
9737 expressions, just `.' plus or minus a constant. */
9738 if (mips_opts.mips16
9739 && ep->X_op == O_symbol
9740 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9741 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9742 && symbol_get_frag (ep->X_add_symbol) == frag_now
9743 && symbol_constant_p (ep->X_add_symbol)
9744 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9745 S_SET_VALUE (ep->X_add_symbol, val + 1);
9748 /* Turn a string in input_line_pointer into a floating point constant
9749 of type TYPE, and store the appropriate bytes in *LITP. The number
9750 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9751 returned, or NULL on OK. */
9754 md_atof (type, litP, sizeP)
9760 LITTLENUM_TYPE words[4];
9776 return _("bad call to md_atof");
9779 t = atof_ieee (input_line_pointer, type, words);
9781 input_line_pointer = t;
9785 if (! target_big_endian)
9787 for (i = prec - 1; i >= 0; i--)
9789 md_number_to_chars (litP, (valueT) words[i], 2);
9795 for (i = 0; i < prec; i++)
9797 md_number_to_chars (litP, (valueT) words[i], 2);
9806 md_number_to_chars (buf, val, n)
9811 if (target_big_endian)
9812 number_to_chars_bigendian (buf, val, n);
9814 number_to_chars_littleendian (buf, val, n);
9818 static int support_64bit_objects(void)
9820 const char **list, **l;
9822 list = bfd_target_list ();
9823 for (l = list; *l != NULL; l++)
9825 /* This is traditional mips */
9826 if (strcmp (*l, "elf64-tradbigmips") == 0
9827 || strcmp (*l, "elf64-tradlittlemips") == 0)
9829 if (strcmp (*l, "elf64-bigmips") == 0
9830 || strcmp (*l, "elf64-littlemips") == 0)
9834 return (*l != NULL);
9836 #endif /* OBJ_ELF */
9838 const char *md_shortopts = "nO::g::G:";
9840 struct option md_longopts[] =
9842 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9843 {"mips0", no_argument, NULL, OPTION_MIPS1},
9844 {"mips1", no_argument, NULL, OPTION_MIPS1},
9845 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9846 {"mips2", no_argument, NULL, OPTION_MIPS2},
9847 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9848 {"mips3", no_argument, NULL, OPTION_MIPS3},
9849 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9850 {"mips4", no_argument, NULL, OPTION_MIPS4},
9851 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9852 {"mips5", no_argument, NULL, OPTION_MIPS5},
9853 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9854 {"mips32", no_argument, NULL, OPTION_MIPS32},
9855 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9856 {"mips64", no_argument, NULL, OPTION_MIPS64},
9857 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9858 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9859 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9860 {"trap", no_argument, NULL, OPTION_TRAP},
9861 {"no-break", no_argument, NULL, OPTION_TRAP},
9862 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9863 {"break", no_argument, NULL, OPTION_BREAK},
9864 {"no-trap", no_argument, NULL, OPTION_BREAK},
9865 #define OPTION_EB (OPTION_MD_BASE + 11)
9866 {"EB", no_argument, NULL, OPTION_EB},
9867 #define OPTION_EL (OPTION_MD_BASE + 12)
9868 {"EL", no_argument, NULL, OPTION_EL},
9869 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9870 {"mips16", no_argument, NULL, OPTION_MIPS16},
9871 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9872 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9873 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9874 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9875 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9876 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9877 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9878 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9879 {"mfp32", no_argument, NULL, OPTION_FP32},
9880 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9881 {"mgp32", no_argument, NULL, OPTION_GP32},
9882 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9883 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9884 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9885 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9886 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9887 {"march", required_argument, NULL, OPTION_MARCH},
9888 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9889 {"mtune", required_argument, NULL, OPTION_MTUNE},
9890 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9891 {"mfp64", no_argument, NULL, OPTION_FP64},
9892 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9893 {"m4650", no_argument, NULL, OPTION_M4650},
9894 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9895 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9896 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9897 {"m4010", no_argument, NULL, OPTION_M4010},
9898 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9899 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9900 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9901 {"m4100", no_argument, NULL, OPTION_M4100},
9902 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9903 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9904 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9905 {"m3900", no_argument, NULL, OPTION_M3900},
9906 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9907 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9908 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9909 {"mgp64", no_argument, NULL, OPTION_GP64},
9910 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9911 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9912 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9913 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9914 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9915 {"mdmx", no_argument, NULL, OPTION_MDMX},
9916 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9917 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9919 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9920 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9921 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9922 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9923 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9924 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9925 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9926 {"xgot", no_argument, NULL, OPTION_XGOT},
9927 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9928 {"mabi", required_argument, NULL, OPTION_MABI},
9929 #define OPTION_32 (OPTION_ELF_BASE + 4)
9930 {"32", no_argument, NULL, OPTION_32},
9931 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9932 {"n32", no_argument, NULL, OPTION_N32},
9933 #define OPTION_64 (OPTION_ELF_BASE + 6)
9934 {"64", no_argument, NULL, OPTION_64},
9935 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
9936 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
9937 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
9938 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
9939 #endif /* OBJ_ELF */
9940 {NULL, no_argument, NULL, 0}
9942 size_t md_longopts_size = sizeof (md_longopts);
9944 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
9945 NEW_VALUE. Warn if another value was already specified. Note:
9946 we have to defer parsing the -march and -mtune arguments in order
9947 to handle 'from-abi' correctly, since the ABI might be specified
9948 in a later argument. */
9951 mips_set_option_string (string_ptr, new_value)
9952 const char **string_ptr, *new_value;
9954 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
9955 as_warn (_("A different %s was already specified, is now %s"),
9956 string_ptr == &mips_arch_string ? "-march" : "-mtune",
9959 *string_ptr = new_value;
9963 md_parse_option (c, arg)
9969 case OPTION_CONSTRUCT_FLOATS:
9970 mips_disable_float_construction = 0;
9973 case OPTION_NO_CONSTRUCT_FLOATS:
9974 mips_disable_float_construction = 1;
9986 target_big_endian = 1;
9990 target_big_endian = 0;
9998 if (arg && arg[1] == '0')
10008 mips_debug = atoi (arg);
10009 /* When the MIPS assembler sees -g or -g2, it does not do
10010 optimizations which limit full symbolic debugging. We take
10011 that to be equivalent to -O0. */
10012 if (mips_debug == 2)
10017 file_mips_isa = ISA_MIPS1;
10021 file_mips_isa = ISA_MIPS2;
10025 file_mips_isa = ISA_MIPS3;
10029 file_mips_isa = ISA_MIPS4;
10033 file_mips_isa = ISA_MIPS5;
10036 case OPTION_MIPS32:
10037 file_mips_isa = ISA_MIPS32;
10040 case OPTION_MIPS64:
10041 file_mips_isa = ISA_MIPS64;
10045 mips_set_option_string (&mips_tune_string, arg);
10049 mips_set_option_string (&mips_arch_string, arg);
10053 mips_set_option_string (&mips_arch_string, "4650");
10054 mips_set_option_string (&mips_tune_string, "4650");
10057 case OPTION_NO_M4650:
10061 mips_set_option_string (&mips_arch_string, "4010");
10062 mips_set_option_string (&mips_tune_string, "4010");
10065 case OPTION_NO_M4010:
10069 mips_set_option_string (&mips_arch_string, "4100");
10070 mips_set_option_string (&mips_tune_string, "4100");
10073 case OPTION_NO_M4100:
10077 mips_set_option_string (&mips_arch_string, "3900");
10078 mips_set_option_string (&mips_tune_string, "3900");
10081 case OPTION_NO_M3900:
10085 mips_opts.ase_mdmx = 1;
10088 case OPTION_NO_MDMX:
10089 mips_opts.ase_mdmx = 0;
10092 case OPTION_MIPS16:
10093 mips_opts.mips16 = 1;
10094 mips_no_prev_insn (false);
10097 case OPTION_NO_MIPS16:
10098 mips_opts.mips16 = 0;
10099 mips_no_prev_insn (false);
10102 case OPTION_MIPS3D:
10103 mips_opts.ase_mips3d = 1;
10106 case OPTION_NO_MIPS3D:
10107 mips_opts.ase_mips3d = 0;
10110 case OPTION_MEMBEDDED_PIC:
10111 mips_pic = EMBEDDED_PIC;
10112 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10114 as_bad (_("-G may not be used with embedded PIC code"));
10117 g_switch_value = 0x7fffffff;
10121 /* When generating ELF code, we permit -KPIC and -call_shared to
10122 select SVR4_PIC, and -non_shared to select no PIC. This is
10123 intended to be compatible with Irix 5. */
10124 case OPTION_CALL_SHARED:
10125 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10127 as_bad (_("-call_shared is supported only for ELF format"));
10130 mips_pic = SVR4_PIC;
10131 if (g_switch_seen && g_switch_value != 0)
10133 as_bad (_("-G may not be used with SVR4 PIC code"));
10136 g_switch_value = 0;
10139 case OPTION_NON_SHARED:
10140 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10142 as_bad (_("-non_shared is supported only for ELF format"));
10148 /* The -xgot option tells the assembler to use 32 offsets when
10149 accessing the got in SVR4_PIC mode. It is for Irix
10154 #endif /* OBJ_ELF */
10157 if (! USE_GLOBAL_POINTER_OPT)
10159 as_bad (_("-G is not supported for this configuration"));
10162 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10164 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10168 g_switch_value = atoi (arg);
10173 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10176 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10178 as_bad (_("-32 is supported for ELF format only"));
10181 mips_abi = O32_ABI;
10185 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10187 as_bad (_("-n32 is supported for ELF format only"));
10190 mips_abi = N32_ABI;
10194 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10196 as_bad (_("-64 is supported for ELF format only"));
10199 mips_abi = N64_ABI;
10200 if (! support_64bit_objects())
10201 as_fatal (_("No compiled in support for 64 bit object file format"));
10203 #endif /* OBJ_ELF */
10206 file_mips_gp32 = 1;
10210 file_mips_gp32 = 0;
10214 file_mips_fp32 = 1;
10218 file_mips_fp32 = 0;
10223 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10225 as_bad (_("-mabi is supported for ELF format only"));
10228 if (strcmp (arg, "32") == 0)
10229 mips_abi = O32_ABI;
10230 else if (strcmp (arg, "o64") == 0)
10231 mips_abi = O64_ABI;
10232 else if (strcmp (arg, "n32") == 0)
10233 mips_abi = N32_ABI;
10234 else if (strcmp (arg, "64") == 0)
10236 mips_abi = N64_ABI;
10237 if (! support_64bit_objects())
10238 as_fatal (_("No compiled in support for 64 bit object file "
10241 else if (strcmp (arg, "eabi") == 0)
10242 mips_abi = EABI_ABI;
10245 as_fatal (_("invalid abi -mabi=%s"), arg);
10249 #endif /* OBJ_ELF */
10251 case OPTION_M7000_HILO_FIX:
10252 mips_7000_hilo_fix = true;
10255 case OPTION_MNO_7000_HILO_FIX:
10256 mips_7000_hilo_fix = false;
10260 case OPTION_MDEBUG:
10261 mips_flag_mdebug = true;
10264 case OPTION_NO_MDEBUG:
10265 mips_flag_mdebug = false;
10267 #endif /* OBJ_ELF */
10276 /* Set up globals to generate code for the ISA or processor
10277 described by INFO. */
10280 mips_set_architecture (info)
10281 const struct mips_cpu_info *info;
10285 mips_arch_info = info;
10286 mips_arch = info->cpu;
10287 mips_opts.isa = info->isa;
10292 /* Likewise for tuning. */
10295 mips_set_tune (info)
10296 const struct mips_cpu_info *info;
10300 mips_tune_info = info;
10301 mips_tune = info->cpu;
10307 mips_after_parse_args ()
10309 /* GP relative stuff not working for PE */
10310 if (strncmp (TARGET_OS, "pe", 2) == 0
10311 && g_switch_value != 0)
10314 as_bad (_("-G not supported in this configuration."));
10315 g_switch_value = 0;
10318 /* The following code determines the architecture and register size.
10319 Similar code was added to GCC 3.3 (see override_options() in
10320 config/mips/mips.c). The GAS and GCC code should be kept in sync
10321 as much as possible. */
10323 if (mips_arch_string != 0)
10324 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10326 if (mips_tune_string != 0)
10327 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10329 if (file_mips_isa != ISA_UNKNOWN)
10331 /* Handle -mipsN. At this point, file_mips_isa contains the
10332 ISA level specified by -mipsN, while mips_opts.isa contains
10333 the -march selection (if any). */
10334 if (mips_arch_info != 0)
10336 /* -march takes precedence over -mipsN, since it is more descriptive.
10337 There's no harm in specifying both as long as the ISA levels
10339 if (file_mips_isa != mips_opts.isa)
10340 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10341 mips_cpu_info_from_isa (file_mips_isa)->name,
10342 mips_cpu_info_from_isa (mips_opts.isa)->name);
10345 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10348 if (mips_arch_info == 0)
10349 mips_set_architecture (mips_parse_cpu ("default CPU",
10350 MIPS_CPU_STRING_DEFAULT));
10352 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10353 as_bad ("-march=%s is not compatible with the selected ABI",
10354 mips_arch_info->name);
10356 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10357 if (mips_tune_info == 0)
10358 mips_set_tune (mips_arch_info);
10360 if (file_mips_gp32 >= 0)
10362 /* The user specified the size of the integer registers. Make sure
10363 it agrees with the ABI and ISA. */
10364 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10365 as_bad (_("-mgp64 used with a 32-bit processor"));
10366 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10367 as_bad (_("-mgp32 used with a 64-bit ABI"));
10368 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10369 as_bad (_("-mgp64 used with a 32-bit ABI"));
10373 /* Infer the integer register size from the ABI and processor.
10374 Restrict ourselves to 32-bit registers if that's all the
10375 processor has, or if the ABI cannot handle 64-bit registers. */
10376 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10377 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10380 /* ??? GAS treats single-float processors as though they had 64-bit
10381 float registers (although it complains when double-precision
10382 instructions are used). As things stand, saying they have 32-bit
10383 registers would lead to spurious "register must be even" messages.
10384 So here we assume float registers are always the same size as
10385 integer ones, unless the user says otherwise. */
10386 if (file_mips_fp32 < 0)
10387 file_mips_fp32 = file_mips_gp32;
10389 /* End of GCC-shared inference code. */
10391 /* ??? When do we want this flag to be set? Who uses it? */
10392 if (file_mips_gp32 == 1
10393 && mips_abi == NO_ABI
10394 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10395 mips_32bitmode = 1;
10397 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10398 as_bad (_("trap exception not supported at ISA 1"));
10400 /* If the selected architecture includes support for ASEs, enable
10401 generation of code for them. */
10402 if (mips_opts.mips16 == -1)
10403 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10404 if (mips_opts.ase_mips3d == -1)
10405 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10406 if (mips_opts.ase_mdmx == -1)
10407 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10409 file_mips_isa = mips_opts.isa;
10410 file_ase_mips16 = mips_opts.mips16;
10411 file_ase_mips3d = mips_opts.ase_mips3d;
10412 file_ase_mdmx = mips_opts.ase_mdmx;
10413 mips_opts.gp32 = file_mips_gp32;
10414 mips_opts.fp32 = file_mips_fp32;
10419 if (mips_flag_mdebug < 0)
10421 #ifdef OBJ_MAYBE_ECOFF
10422 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10423 mips_flag_mdebug = 1;
10425 #endif /* OBJ_MAYBE_ECOFF */
10426 mips_flag_mdebug = 0;
10431 mips_init_after_args ()
10433 /* initialize opcodes */
10434 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10435 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10439 md_pcrel_from (fixP)
10442 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10443 && fixP->fx_addsy != (symbolS *) NULL
10444 && ! S_IS_DEFINED (fixP->fx_addsy))
10446 /* This makes a branch to an undefined symbol be a branch to the
10447 current location. */
10448 if (mips_pic == EMBEDDED_PIC)
10454 /* Return the address of the delay slot. */
10455 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10458 /* This is called before the symbol table is processed. In order to
10459 work with gcc when using mips-tfile, we must keep all local labels.
10460 However, in other cases, we want to discard them. If we were
10461 called with -g, but we didn't see any debugging information, it may
10462 mean that gcc is smuggling debugging information through to
10463 mips-tfile, in which case we must generate all local labels. */
10466 mips_frob_file_before_adjust ()
10468 #ifndef NO_ECOFF_DEBUGGING
10469 if (ECOFF_DEBUGGING
10471 && ! ecoff_debugging_seen)
10472 flag_keep_locals = 1;
10476 /* Sort any unmatched HI16_S relocs so that they immediately precede
10477 the corresponding LO reloc. This is called before md_apply_fix3 and
10478 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10479 explicit use of the %hi modifier. */
10484 struct mips_hi_fixup *l;
10486 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10488 segment_info_type *seginfo;
10491 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10493 /* Check quickly whether the next fixup happens to be a matching
10495 if (l->fixp->fx_next != NULL
10496 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10497 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10498 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10501 /* Look through the fixups for this segment for a matching %lo.
10502 When we find one, move the %hi just in front of it. We do
10503 this in two passes. In the first pass, we try to find a
10504 unique %lo. In the second pass, we permit multiple %hi
10505 relocs for a single %lo (this is a GNU extension). */
10506 seginfo = seg_info (l->seg);
10507 for (pass = 0; pass < 2; pass++)
10512 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10514 /* Check whether this is a %lo fixup which matches l->fixp. */
10515 if (f->fx_r_type == BFD_RELOC_LO16
10516 && f->fx_addsy == l->fixp->fx_addsy
10517 && f->fx_offset == l->fixp->fx_offset
10520 || prev->fx_r_type != BFD_RELOC_HI16_S
10521 || prev->fx_addsy != f->fx_addsy
10522 || prev->fx_offset != f->fx_offset))
10526 /* Move l->fixp before f. */
10527 for (pf = &seginfo->fix_root;
10529 pf = &(*pf)->fx_next)
10530 assert (*pf != NULL);
10532 *pf = l->fixp->fx_next;
10534 l->fixp->fx_next = f;
10536 seginfo->fix_root = l->fixp;
10538 prev->fx_next = l->fixp;
10549 #if 0 /* GCC code motion plus incomplete dead code elimination
10550 can leave a %hi without a %lo. */
10552 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10553 _("Unmatched %%hi reloc"));
10559 /* When generating embedded PIC code we need to use a special
10560 relocation to represent the difference of two symbols in the .text
10561 section (switch tables use a difference of this sort). See
10562 include/coff/mips.h for details. This macro checks whether this
10563 fixup requires the special reloc. */
10564 #define SWITCH_TABLE(fixp) \
10565 ((fixp)->fx_r_type == BFD_RELOC_32 \
10566 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10567 && (fixp)->fx_addsy != NULL \
10568 && (fixp)->fx_subsy != NULL \
10569 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10570 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10572 /* When generating embedded PIC code we must keep all PC relative
10573 relocations, in case the linker has to relax a call. We also need
10574 to keep relocations for switch table entries.
10576 We may have combined relocations without symbols in the N32/N64 ABI.
10577 We have to prevent gas from dropping them. */
10580 mips_force_relocation (fixp)
10583 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10584 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10588 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10589 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10590 || fixp->fx_r_type == BFD_RELOC_HI16_S
10591 || fixp->fx_r_type == BFD_RELOC_LO16))
10594 return (mips_pic == EMBEDDED_PIC
10596 || SWITCH_TABLE (fixp)
10597 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10598 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10603 mips_need_elf_addend_fixup (fixP)
10606 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10608 if (mips_pic == EMBEDDED_PIC
10609 && S_IS_WEAK (fixP->fx_addsy))
10611 if (mips_pic != EMBEDDED_PIC
10612 && (S_IS_WEAK (fixP->fx_addsy)
10613 || S_IS_EXTERNAL (fixP->fx_addsy))
10614 && !S_IS_COMMON (fixP->fx_addsy))
10616 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10617 && (((bfd_get_section_flags (stdoutput,
10618 S_GET_SEGMENT (fixP->fx_addsy))
10619 & SEC_LINK_ONCE) != 0)
10620 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10622 sizeof (".gnu.linkonce") - 1)))
10628 /* Apply a fixup to the object file. */
10631 md_apply_fix3 (fixP, valP, seg)
10634 segT seg ATTRIBUTE_UNUSED;
10640 assert (fixP->fx_size == 4
10641 || fixP->fx_r_type == BFD_RELOC_16
10642 || fixP->fx_r_type == BFD_RELOC_32
10643 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10644 || fixP->fx_r_type == BFD_RELOC_HI16_S
10645 || fixP->fx_r_type == BFD_RELOC_LO16
10646 || fixP->fx_r_type == BFD_RELOC_GPREL16
10647 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10648 || fixP->fx_r_type == BFD_RELOC_GPREL32
10649 || fixP->fx_r_type == BFD_RELOC_64
10650 || fixP->fx_r_type == BFD_RELOC_CTOR
10651 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10652 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10653 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10654 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10655 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10656 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10657 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10658 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10659 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10663 /* If we aren't adjusting this fixup to be against the section
10664 symbol, we need to adjust the value. */
10666 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10668 if (mips_need_elf_addend_fixup (fixP))
10670 reloc_howto_type *howto;
10671 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10675 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10676 if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel)
10678 /* In this case, the bfd_install_relocation routine will
10679 incorrectly add the symbol value back in. We just want
10680 the addend to appear in the object file. */
10683 /* Make sure the addend is still non-zero. If it became zero
10684 after the last operation, set it to a spurious value and
10685 subtract the same value from the object file's contents. */
10690 /* The in-place addends for LO16 relocations are signed;
10691 leave the matching HI16 in-place addends as zero. */
10692 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10694 bfd_vma contents, mask, field;
10696 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10699 target_big_endian);
10701 /* MASK has bits set where the relocation should go.
10702 FIELD is -value, shifted into the appropriate place
10703 for this relocation. */
10704 mask = 1 << (howto->bitsize - 1);
10705 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10706 field = (-value >> howto->rightshift) << howto->bitpos;
10708 bfd_put_bits ((field & mask) | (contents & ~mask),
10709 fixP->fx_frag->fr_literal + fixP->fx_where,
10711 target_big_endian);
10717 /* This code was generated using trial and error and so is
10718 fragile and not trustworthy. If you change it, you should
10719 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10720 they still pass. */
10721 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10723 value += fixP->fx_frag->fr_address + fixP->fx_where;
10725 /* BFD's REL handling, for MIPS, is _very_ weird.
10726 This gives the right results, but it can't possibly
10727 be the way things are supposed to work. */
10728 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10729 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10730 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10731 value += fixP->fx_frag->fr_address + fixP->fx_where;
10736 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10738 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10741 switch (fixP->fx_r_type)
10743 case BFD_RELOC_MIPS_JMP:
10744 case BFD_RELOC_MIPS_SHIFT5:
10745 case BFD_RELOC_MIPS_SHIFT6:
10746 case BFD_RELOC_MIPS_GOT_DISP:
10747 case BFD_RELOC_MIPS_GOT_PAGE:
10748 case BFD_RELOC_MIPS_GOT_OFST:
10749 case BFD_RELOC_MIPS_SUB:
10750 case BFD_RELOC_MIPS_INSERT_A:
10751 case BFD_RELOC_MIPS_INSERT_B:
10752 case BFD_RELOC_MIPS_DELETE:
10753 case BFD_RELOC_MIPS_HIGHEST:
10754 case BFD_RELOC_MIPS_HIGHER:
10755 case BFD_RELOC_MIPS_SCN_DISP:
10756 case BFD_RELOC_MIPS_REL16:
10757 case BFD_RELOC_MIPS_RELGOT:
10758 case BFD_RELOC_MIPS_JALR:
10759 case BFD_RELOC_HI16:
10760 case BFD_RELOC_HI16_S:
10761 case BFD_RELOC_GPREL16:
10762 case BFD_RELOC_MIPS_LITERAL:
10763 case BFD_RELOC_MIPS_CALL16:
10764 case BFD_RELOC_MIPS_GOT16:
10765 case BFD_RELOC_GPREL32:
10766 case BFD_RELOC_MIPS_GOT_HI16:
10767 case BFD_RELOC_MIPS_GOT_LO16:
10768 case BFD_RELOC_MIPS_CALL_HI16:
10769 case BFD_RELOC_MIPS_CALL_LO16:
10770 case BFD_RELOC_MIPS16_GPREL:
10771 if (fixP->fx_pcrel)
10772 as_bad_where (fixP->fx_file, fixP->fx_line,
10773 _("Invalid PC relative reloc"));
10774 /* Nothing needed to do. The value comes from the reloc entry */
10777 case BFD_RELOC_MIPS16_JMP:
10778 /* We currently always generate a reloc against a symbol, which
10779 means that we don't want an addend even if the symbol is
10781 fixP->fx_addnumber = 0;
10784 case BFD_RELOC_PCREL_HI16_S:
10785 /* The addend for this is tricky if it is internal, so we just
10786 do everything here rather than in bfd_install_relocation. */
10787 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10792 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10794 /* For an external symbol adjust by the address to make it
10795 pcrel_offset. We use the address of the RELLO reloc
10796 which follows this one. */
10797 value += (fixP->fx_next->fx_frag->fr_address
10798 + fixP->fx_next->fx_where);
10800 value = ((value + 0x8000) >> 16) & 0xffff;
10801 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10802 if (target_big_endian)
10804 md_number_to_chars ((char *) buf, value, 2);
10807 case BFD_RELOC_PCREL_LO16:
10808 /* The addend for this is tricky if it is internal, so we just
10809 do everything here rather than in bfd_install_relocation. */
10810 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10815 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10816 value += fixP->fx_frag->fr_address + fixP->fx_where;
10817 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10818 if (target_big_endian)
10820 md_number_to_chars ((char *) buf, value, 2);
10824 /* This is handled like BFD_RELOC_32, but we output a sign
10825 extended value if we are only 32 bits. */
10827 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10829 if (8 <= sizeof (valueT))
10830 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10837 w1 = w2 = fixP->fx_where;
10838 if (target_big_endian)
10842 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10843 if ((value & 0x80000000) != 0)
10847 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10852 case BFD_RELOC_RVA:
10854 /* If we are deleting this reloc entry, we must fill in the
10855 value now. This can happen if we have a .word which is not
10856 resolved when it appears but is later defined. We also need
10857 to fill in the value if this is an embedded PIC switch table
10860 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10861 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10866 /* If we are deleting this reloc entry, we must fill in the
10868 assert (fixP->fx_size == 2);
10870 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10874 case BFD_RELOC_LO16:
10875 /* When handling an embedded PIC switch statement, we can wind
10876 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10879 if (value + 0x8000 > 0xffff)
10880 as_bad_where (fixP->fx_file, fixP->fx_line,
10881 _("relocation overflow"));
10882 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10883 if (target_big_endian)
10885 md_number_to_chars ((char *) buf, value, 2);
10889 case BFD_RELOC_16_PCREL_S2:
10890 if ((value & 0x3) != 0)
10891 as_bad_where (fixP->fx_file, fixP->fx_line,
10892 _("Branch to odd address (%lx)"), (long) value);
10894 /* Fall through. */
10896 case BFD_RELOC_16_PCREL:
10898 * We need to save the bits in the instruction since fixup_segment()
10899 * might be deleting the relocation entry (i.e., a branch within
10900 * the current segment).
10902 if (!fixP->fx_done && value != 0)
10904 /* If 'value' is zero, the remaining reloc code won't actually
10905 do the store, so it must be done here. This is probably
10906 a bug somewhere. */
10908 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
10909 || fixP->fx_addsy == NULL /* ??? */
10910 || ! S_IS_DEFINED (fixP->fx_addsy)))
10911 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10913 value = (offsetT) value >> 2;
10915 /* update old instruction data */
10916 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
10917 if (target_big_endian)
10918 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
10920 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
10922 if (value + 0x8000 <= 0xffff)
10923 insn |= value & 0xffff;
10926 /* The branch offset is too large. If this is an
10927 unconditional branch, and we are not generating PIC code,
10928 we can convert it to an absolute jump instruction. */
10929 if (mips_pic == NO_PIC
10931 && fixP->fx_frag->fr_address >= text_section->vma
10932 && (fixP->fx_frag->fr_address
10933 < text_section->vma + text_section->_raw_size)
10934 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
10935 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
10936 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
10938 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
10939 insn = 0x0c000000; /* jal */
10941 insn = 0x08000000; /* j */
10942 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
10944 fixP->fx_addsy = section_symbol (text_section);
10945 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
10949 /* FIXME. It would be possible in principle to handle
10950 conditional branches which overflow. They could be
10951 transformed into a branch around a jump. This would
10952 require setting up variant frags for each different
10953 branch type. The native MIPS assembler attempts to
10954 handle these cases, but it appears to do it
10956 as_bad_where (fixP->fx_file, fixP->fx_line,
10957 _("Branch out of range"));
10961 md_number_to_chars ((char *) buf, (valueT) insn, 4);
10964 case BFD_RELOC_VTABLE_INHERIT:
10967 && !S_IS_DEFINED (fixP->fx_addsy)
10968 && !S_IS_WEAK (fixP->fx_addsy))
10969 S_SET_WEAK (fixP->fx_addsy);
10972 case BFD_RELOC_VTABLE_ENTRY:
10986 const struct mips_opcode *p;
10987 int treg, sreg, dreg, shamt;
10992 for (i = 0; i < NUMOPCODES; ++i)
10994 p = &mips_opcodes[i];
10995 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
10997 printf ("%08lx %s\t", oc, p->name);
10998 treg = (oc >> 16) & 0x1f;
10999 sreg = (oc >> 21) & 0x1f;
11000 dreg = (oc >> 11) & 0x1f;
11001 shamt = (oc >> 6) & 0x1f;
11003 for (args = p->args;; ++args)
11014 printf ("%c", *args);
11018 assert (treg == sreg);
11019 printf ("$%d,$%d", treg, sreg);
11024 printf ("$%d", dreg);
11029 printf ("$%d", treg);
11033 printf ("0x%x", treg);
11038 printf ("$%d", sreg);
11042 printf ("0x%08lx", oc & 0x1ffffff);
11049 printf ("%d", imm);
11054 printf ("$%d", shamt);
11065 printf (_("%08lx UNDEFINED\n"), oc);
11076 name = input_line_pointer;
11077 c = get_symbol_end ();
11078 p = (symbolS *) symbol_find_or_make (name);
11079 *input_line_pointer = c;
11083 /* Align the current frag to a given power of two. The MIPS assembler
11084 also automatically adjusts any preceding label. */
11087 mips_align (to, fill, label)
11092 mips_emit_delays (false);
11093 frag_align (to, fill, 0);
11094 record_alignment (now_seg, to);
11097 assert (S_GET_SEGMENT (label) == now_seg);
11098 symbol_set_frag (label, frag_now);
11099 S_SET_VALUE (label, (valueT) frag_now_fix ());
11103 /* Align to a given power of two. .align 0 turns off the automatic
11104 alignment used by the data creating pseudo-ops. */
11108 int x ATTRIBUTE_UNUSED;
11111 register long temp_fill;
11112 long max_alignment = 15;
11116 o Note that the assembler pulls down any immediately preceeding label
11117 to the aligned address.
11118 o It's not documented but auto alignment is reinstated by
11119 a .align pseudo instruction.
11120 o Note also that after auto alignment is turned off the mips assembler
11121 issues an error on attempt to assemble an improperly aligned data item.
11126 temp = get_absolute_expression ();
11127 if (temp > max_alignment)
11128 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11131 as_warn (_("Alignment negative: 0 assumed."));
11134 if (*input_line_pointer == ',')
11136 ++input_line_pointer;
11137 temp_fill = get_absolute_expression ();
11144 mips_align (temp, (int) temp_fill,
11145 insn_labels != NULL ? insn_labels->label : NULL);
11152 demand_empty_rest_of_line ();
11156 mips_flush_pending_output ()
11158 mips_emit_delays (false);
11159 mips_clear_insn_labels ();
11168 /* When generating embedded PIC code, we only use the .text, .lit8,
11169 .sdata and .sbss sections. We change the .data and .rdata
11170 pseudo-ops to use .sdata. */
11171 if (mips_pic == EMBEDDED_PIC
11172 && (sec == 'd' || sec == 'r'))
11176 /* The ELF backend needs to know that we are changing sections, so
11177 that .previous works correctly. We could do something like check
11178 for an obj_section_change_hook macro, but that might be confusing
11179 as it would not be appropriate to use it in the section changing
11180 functions in read.c, since obj-elf.c intercepts those. FIXME:
11181 This should be cleaner, somehow. */
11182 obj_elf_section_change_hook ();
11185 mips_emit_delays (false);
11195 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11196 demand_empty_rest_of_line ();
11200 if (USE_GLOBAL_POINTER_OPT)
11202 seg = subseg_new (RDATA_SECTION_NAME,
11203 (subsegT) get_absolute_expression ());
11204 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11206 bfd_set_section_flags (stdoutput, seg,
11212 if (strcmp (TARGET_OS, "elf") != 0)
11213 record_alignment (seg, 4);
11215 demand_empty_rest_of_line ();
11219 as_bad (_("No read only data section in this object file format"));
11220 demand_empty_rest_of_line ();
11226 if (USE_GLOBAL_POINTER_OPT)
11228 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11229 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11231 bfd_set_section_flags (stdoutput, seg,
11232 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11234 if (strcmp (TARGET_OS, "elf") != 0)
11235 record_alignment (seg, 4);
11237 demand_empty_rest_of_line ();
11242 as_bad (_("Global pointers not supported; recompile -G 0"));
11243 demand_empty_rest_of_line ();
11252 mips_enable_auto_align ()
11263 label = insn_labels != NULL ? insn_labels->label : NULL;
11264 mips_emit_delays (false);
11265 if (log_size > 0 && auto_align)
11266 mips_align (log_size, 0, label);
11267 mips_clear_insn_labels ();
11268 cons (1 << log_size);
11272 s_float_cons (type)
11277 label = insn_labels != NULL ? insn_labels->label : NULL;
11279 mips_emit_delays (false);
11284 mips_align (3, 0, label);
11286 mips_align (2, 0, label);
11289 mips_clear_insn_labels ();
11294 /* Handle .globl. We need to override it because on Irix 5 you are
11297 where foo is an undefined symbol, to mean that foo should be
11298 considered to be the address of a function. */
11302 int x ATTRIBUTE_UNUSED;
11309 name = input_line_pointer;
11310 c = get_symbol_end ();
11311 symbolP = symbol_find_or_make (name);
11312 *input_line_pointer = c;
11313 SKIP_WHITESPACE ();
11315 /* On Irix 5, every global symbol that is not explicitly labelled as
11316 being a function is apparently labelled as being an object. */
11319 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11324 secname = input_line_pointer;
11325 c = get_symbol_end ();
11326 sec = bfd_get_section_by_name (stdoutput, secname);
11328 as_bad (_("%s: no such section"), secname);
11329 *input_line_pointer = c;
11331 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11332 flag = BSF_FUNCTION;
11335 symbol_get_bfdsym (symbolP)->flags |= flag;
11337 S_SET_EXTERNAL (symbolP);
11338 demand_empty_rest_of_line ();
11343 int x ATTRIBUTE_UNUSED;
11348 opt = input_line_pointer;
11349 c = get_symbol_end ();
11353 /* FIXME: What does this mean? */
11355 else if (strncmp (opt, "pic", 3) == 0)
11359 i = atoi (opt + 3);
11363 mips_pic = SVR4_PIC;
11365 as_bad (_(".option pic%d not supported"), i);
11367 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11369 if (g_switch_seen && g_switch_value != 0)
11370 as_warn (_("-G may not be used with SVR4 PIC code"));
11371 g_switch_value = 0;
11372 bfd_set_gp_size (stdoutput, 0);
11376 as_warn (_("Unrecognized option \"%s\""), opt);
11378 *input_line_pointer = c;
11379 demand_empty_rest_of_line ();
11382 /* This structure is used to hold a stack of .set values. */
11384 struct mips_option_stack
11386 struct mips_option_stack *next;
11387 struct mips_set_options options;
11390 static struct mips_option_stack *mips_opts_stack;
11392 /* Handle the .set pseudo-op. */
11396 int x ATTRIBUTE_UNUSED;
11398 char *name = input_line_pointer, ch;
11400 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11401 ++input_line_pointer;
11402 ch = *input_line_pointer;
11403 *input_line_pointer = '\0';
11405 if (strcmp (name, "reorder") == 0)
11407 if (mips_opts.noreorder && prev_nop_frag != NULL)
11409 /* If we still have pending nops, we can discard them. The
11410 usual nop handling will insert any that are still
11412 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11413 * (mips_opts.mips16 ? 2 : 4));
11414 prev_nop_frag = NULL;
11416 mips_opts.noreorder = 0;
11418 else if (strcmp (name, "noreorder") == 0)
11420 mips_emit_delays (true);
11421 mips_opts.noreorder = 1;
11422 mips_any_noreorder = 1;
11424 else if (strcmp (name, "at") == 0)
11426 mips_opts.noat = 0;
11428 else if (strcmp (name, "noat") == 0)
11430 mips_opts.noat = 1;
11432 else if (strcmp (name, "macro") == 0)
11434 mips_opts.warn_about_macros = 0;
11436 else if (strcmp (name, "nomacro") == 0)
11438 if (mips_opts.noreorder == 0)
11439 as_bad (_("`noreorder' must be set before `nomacro'"));
11440 mips_opts.warn_about_macros = 1;
11442 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11444 mips_opts.nomove = 0;
11446 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11448 mips_opts.nomove = 1;
11450 else if (strcmp (name, "bopt") == 0)
11452 mips_opts.nobopt = 0;
11454 else if (strcmp (name, "nobopt") == 0)
11456 mips_opts.nobopt = 1;
11458 else if (strcmp (name, "mips16") == 0
11459 || strcmp (name, "MIPS-16") == 0)
11460 mips_opts.mips16 = 1;
11461 else if (strcmp (name, "nomips16") == 0
11462 || strcmp (name, "noMIPS-16") == 0)
11463 mips_opts.mips16 = 0;
11464 else if (strcmp (name, "mips3d") == 0)
11465 mips_opts.ase_mips3d = 1;
11466 else if (strcmp (name, "nomips3d") == 0)
11467 mips_opts.ase_mips3d = 0;
11468 else if (strcmp (name, "mdmx") == 0)
11469 mips_opts.ase_mdmx = 1;
11470 else if (strcmp (name, "nomdmx") == 0)
11471 mips_opts.ase_mdmx = 0;
11472 else if (strncmp (name, "mips", 4) == 0)
11476 /* Permit the user to change the ISA on the fly. Needless to
11477 say, misuse can cause serious problems. */
11478 isa = atoi (name + 4);
11482 mips_opts.gp32 = file_mips_gp32;
11483 mips_opts.fp32 = file_mips_fp32;
11488 mips_opts.gp32 = 1;
11489 mips_opts.fp32 = 1;
11495 mips_opts.gp32 = 0;
11496 mips_opts.fp32 = 0;
11499 as_bad (_("unknown ISA level %s"), name + 4);
11505 case 0: mips_opts.isa = file_mips_isa; break;
11506 case 1: mips_opts.isa = ISA_MIPS1; break;
11507 case 2: mips_opts.isa = ISA_MIPS2; break;
11508 case 3: mips_opts.isa = ISA_MIPS3; break;
11509 case 4: mips_opts.isa = ISA_MIPS4; break;
11510 case 5: mips_opts.isa = ISA_MIPS5; break;
11511 case 32: mips_opts.isa = ISA_MIPS32; break;
11512 case 64: mips_opts.isa = ISA_MIPS64; break;
11513 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11516 else if (strcmp (name, "autoextend") == 0)
11517 mips_opts.noautoextend = 0;
11518 else if (strcmp (name, "noautoextend") == 0)
11519 mips_opts.noautoextend = 1;
11520 else if (strcmp (name, "push") == 0)
11522 struct mips_option_stack *s;
11524 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11525 s->next = mips_opts_stack;
11526 s->options = mips_opts;
11527 mips_opts_stack = s;
11529 else if (strcmp (name, "pop") == 0)
11531 struct mips_option_stack *s;
11533 s = mips_opts_stack;
11535 as_bad (_(".set pop with no .set push"));
11538 /* If we're changing the reorder mode we need to handle
11539 delay slots correctly. */
11540 if (s->options.noreorder && ! mips_opts.noreorder)
11541 mips_emit_delays (true);
11542 else if (! s->options.noreorder && mips_opts.noreorder)
11544 if (prev_nop_frag != NULL)
11546 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11547 * (mips_opts.mips16 ? 2 : 4));
11548 prev_nop_frag = NULL;
11552 mips_opts = s->options;
11553 mips_opts_stack = s->next;
11559 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11561 *input_line_pointer = ch;
11562 demand_empty_rest_of_line ();
11565 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11566 .option pic2. It means to generate SVR4 PIC calls. */
11569 s_abicalls (ignore)
11570 int ignore ATTRIBUTE_UNUSED;
11572 mips_pic = SVR4_PIC;
11573 if (USE_GLOBAL_POINTER_OPT)
11575 if (g_switch_seen && g_switch_value != 0)
11576 as_warn (_("-G may not be used with SVR4 PIC code"));
11577 g_switch_value = 0;
11579 bfd_set_gp_size (stdoutput, 0);
11580 demand_empty_rest_of_line ();
11583 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11584 PIC code. It sets the $gp register for the function based on the
11585 function address, which is in the register named in the argument.
11586 This uses a relocation against _gp_disp, which is handled specially
11587 by the linker. The result is:
11588 lui $gp,%hi(_gp_disp)
11589 addiu $gp,$gp,%lo(_gp_disp)
11590 addu $gp,$gp,.cpload argument
11591 The .cpload argument is normally $25 == $t9. */
11595 int ignore ATTRIBUTE_UNUSED;
11600 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11601 .cpload is ignored. */
11602 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11608 /* .cpload should be in a .set noreorder section. */
11609 if (mips_opts.noreorder == 0)
11610 as_warn (_(".cpload not in noreorder section"));
11612 ex.X_op = O_symbol;
11613 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11614 ex.X_op_symbol = NULL;
11615 ex.X_add_number = 0;
11617 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11618 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11620 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11621 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11622 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11624 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11625 mips_gp_register, mips_gp_register, tc_get_register (0));
11627 demand_empty_rest_of_line ();
11630 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11631 .cpsetup $reg1, offset|$reg2, label
11633 If offset is given, this results in:
11634 sd $gp, offset($sp)
11635 lui $gp, %hi(%neg(%gp_rel(label)))
11636 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11637 daddu $gp, $gp, $reg1
11639 If $reg2 is given, this results in:
11640 daddu $reg2, $gp, $0
11641 lui $gp, %hi(%neg(%gp_rel(label)))
11642 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11643 daddu $gp, $gp, $reg1
11644 $reg1 is normally $25 == $t9. */
11647 int ignore ATTRIBUTE_UNUSED;
11649 expressionS ex_off;
11650 expressionS ex_sym;
11655 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11656 We also need NewABI support. */
11657 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11663 reg1 = tc_get_register (0);
11664 SKIP_WHITESPACE ();
11665 if (*input_line_pointer != ',')
11667 as_bad (_("missing argument separator ',' for .cpsetup"));
11671 ++input_line_pointer;
11672 SKIP_WHITESPACE ();
11673 if (*input_line_pointer == '$')
11675 mips_cpreturn_register = tc_get_register (0);
11676 mips_cpreturn_offset = -1;
11680 mips_cpreturn_offset = get_absolute_expression ();
11681 mips_cpreturn_register = -1;
11683 SKIP_WHITESPACE ();
11684 if (*input_line_pointer != ',')
11686 as_bad (_("missing argument separator ',' for .cpsetup"));
11690 ++input_line_pointer;
11691 SKIP_WHITESPACE ();
11692 sym = input_line_pointer;
11693 while (ISALNUM (*input_line_pointer))
11694 ++input_line_pointer;
11695 *input_line_pointer = 0;
11697 ex_sym.X_op = O_symbol;
11698 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11699 ex_sym.X_op_symbol = NULL;
11700 ex_sym.X_add_number = 0;
11702 if (mips_cpreturn_register == -1)
11704 ex_off.X_op = O_constant;
11705 ex_off.X_add_symbol = NULL;
11706 ex_off.X_op_symbol = NULL;
11707 ex_off.X_add_number = mips_cpreturn_offset;
11709 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11710 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11713 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11714 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11716 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11717 (int) BFD_RELOC_GPREL16);
11718 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11719 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11720 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11721 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11722 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11723 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16);
11724 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11725 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11726 mips_gp_register, mips_gp_register, reg1);
11728 demand_empty_rest_of_line ();
11733 int ignore ATTRIBUTE_UNUSED;
11735 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11736 .cplocal is ignored. */
11737 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11743 mips_gp_register = tc_get_register (0);
11744 demand_empty_rest_of_line ();
11747 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11748 offset from $sp. The offset is remembered, and after making a PIC
11749 call $gp is restored from that location. */
11752 s_cprestore (ignore)
11753 int ignore ATTRIBUTE_UNUSED;
11758 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11759 .cprestore is ignored. */
11760 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11766 mips_cprestore_offset = get_absolute_expression ();
11767 mips_cprestore_valid = 1;
11769 ex.X_op = O_constant;
11770 ex.X_add_symbol = NULL;
11771 ex.X_op_symbol = NULL;
11772 ex.X_add_number = mips_cprestore_offset;
11774 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11775 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11777 demand_empty_rest_of_line ();
11780 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11781 was given in the preceeding .gpsetup, it results in:
11782 ld $gp, offset($sp)
11784 If a register $reg2 was given there, it results in:
11785 daddiu $gp, $gp, $reg2
11788 s_cpreturn (ignore)
11789 int ignore ATTRIBUTE_UNUSED;
11794 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11795 We also need NewABI support. */
11796 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11802 if (mips_cpreturn_register == -1)
11804 ex.X_op = O_constant;
11805 ex.X_add_symbol = NULL;
11806 ex.X_op_symbol = NULL;
11807 ex.X_add_number = mips_cpreturn_offset;
11809 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11810 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11813 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11814 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11816 demand_empty_rest_of_line ();
11819 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11820 code. It sets the offset to use in gp_rel relocations. */
11824 int ignore ATTRIBUTE_UNUSED;
11826 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11827 We also need NewABI support. */
11828 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11834 mips_gprel_offset = get_absolute_expression ();
11836 demand_empty_rest_of_line ();
11839 /* Handle the .gpword pseudo-op. This is used when generating PIC
11840 code. It generates a 32 bit GP relative reloc. */
11844 int ignore ATTRIBUTE_UNUSED;
11850 /* When not generating PIC code, this is treated as .word. */
11851 if (mips_pic != SVR4_PIC)
11857 label = insn_labels != NULL ? insn_labels->label : NULL;
11858 mips_emit_delays (true);
11860 mips_align (2, 0, label);
11861 mips_clear_insn_labels ();
11865 if (ex.X_op != O_symbol || ex.X_add_number != 0)
11867 as_bad (_("Unsupported use of .gpword"));
11868 ignore_rest_of_line ();
11872 md_number_to_chars (p, (valueT) 0, 4);
11873 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
11874 BFD_RELOC_GPREL32);
11876 demand_empty_rest_of_line ();
11879 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11880 tables in SVR4 PIC code. */
11884 int ignore ATTRIBUTE_UNUSED;
11889 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11891 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11897 /* Add $gp to the register named as an argument. */
11898 reg = tc_get_register (0);
11899 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11900 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
11901 "d,v,t", reg, reg, mips_gp_register);
11903 demand_empty_rest_of_line ();
11906 /* Handle the .insn pseudo-op. This marks instruction labels in
11907 mips16 mode. This permits the linker to handle them specially,
11908 such as generating jalx instructions when needed. We also make
11909 them odd for the duration of the assembly, in order to generate the
11910 right sort of code. We will make them even in the adjust_symtab
11911 routine, while leaving them marked. This is convenient for the
11912 debugger and the disassembler. The linker knows to make them odd
11917 int ignore ATTRIBUTE_UNUSED;
11919 mips16_mark_labels ();
11921 demand_empty_rest_of_line ();
11924 /* Handle a .stabn directive. We need these in order to mark a label
11925 as being a mips16 text label correctly. Sometimes the compiler
11926 will emit a label, followed by a .stabn, and then switch sections.
11927 If the label and .stabn are in mips16 mode, then the label is
11928 really a mips16 text label. */
11935 mips16_mark_labels ();
11940 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11944 s_mips_weakext (ignore)
11945 int ignore ATTRIBUTE_UNUSED;
11952 name = input_line_pointer;
11953 c = get_symbol_end ();
11954 symbolP = symbol_find_or_make (name);
11955 S_SET_WEAK (symbolP);
11956 *input_line_pointer = c;
11958 SKIP_WHITESPACE ();
11960 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11962 if (S_IS_DEFINED (symbolP))
11964 as_bad ("ignoring attempt to redefine symbol %s",
11965 S_GET_NAME (symbolP));
11966 ignore_rest_of_line ();
11970 if (*input_line_pointer == ',')
11972 ++input_line_pointer;
11973 SKIP_WHITESPACE ();
11977 if (exp.X_op != O_symbol)
11979 as_bad ("bad .weakext directive");
11980 ignore_rest_of_line ();
11983 symbol_set_value_expression (symbolP, &exp);
11986 demand_empty_rest_of_line ();
11989 /* Parse a register string into a number. Called from the ECOFF code
11990 to parse .frame. The argument is non-zero if this is the frame
11991 register, so that we can record it in mips_frame_reg. */
11994 tc_get_register (frame)
11999 SKIP_WHITESPACE ();
12000 if (*input_line_pointer++ != '$')
12002 as_warn (_("expected `$'"));
12005 else if (ISDIGIT (*input_line_pointer))
12007 reg = get_absolute_expression ();
12008 if (reg < 0 || reg >= 32)
12010 as_warn (_("Bad register number"));
12016 if (strncmp (input_line_pointer, "ra", 2) == 0)
12019 input_line_pointer += 2;
12021 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12024 input_line_pointer += 2;
12026 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12029 input_line_pointer += 2;
12031 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12034 input_line_pointer += 2;
12036 else if (strncmp (input_line_pointer, "at", 2) == 0)
12039 input_line_pointer += 2;
12041 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12044 input_line_pointer += 3;
12046 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12049 input_line_pointer += 3;
12051 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12054 input_line_pointer += 4;
12058 as_warn (_("Unrecognized register name"));
12060 while (ISALNUM(*input_line_pointer))
12061 input_line_pointer++;
12066 mips_frame_reg = reg != 0 ? reg : SP;
12067 mips_frame_reg_valid = 1;
12068 mips_cprestore_valid = 0;
12074 md_section_align (seg, addr)
12078 int align = bfd_get_section_alignment (stdoutput, seg);
12081 /* We don't need to align ELF sections to the full alignment.
12082 However, Irix 5 may prefer that we align them at least to a 16
12083 byte boundary. We don't bother to align the sections if we are
12084 targeted for an embedded system. */
12085 if (strcmp (TARGET_OS, "elf") == 0)
12091 return ((addr + (1 << align) - 1) & (-1 << align));
12094 /* Utility routine, called from above as well. If called while the
12095 input file is still being read, it's only an approximation. (For
12096 example, a symbol may later become defined which appeared to be
12097 undefined earlier.) */
12100 nopic_need_relax (sym, before_relaxing)
12102 int before_relaxing;
12107 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12109 const char *symname;
12112 /* Find out whether this symbol can be referenced off the $gp
12113 register. It can be if it is smaller than the -G size or if
12114 it is in the .sdata or .sbss section. Certain symbols can
12115 not be referenced off the $gp, although it appears as though
12117 symname = S_GET_NAME (sym);
12118 if (symname != (const char *) NULL
12119 && (strcmp (symname, "eprol") == 0
12120 || strcmp (symname, "etext") == 0
12121 || strcmp (symname, "_gp") == 0
12122 || strcmp (symname, "edata") == 0
12123 || strcmp (symname, "_fbss") == 0
12124 || strcmp (symname, "_fdata") == 0
12125 || strcmp (symname, "_ftext") == 0
12126 || strcmp (symname, "end") == 0
12127 || strcmp (symname, "_gp_disp") == 0))
12129 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12131 #ifndef NO_ECOFF_DEBUGGING
12132 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12133 && (symbol_get_obj (sym)->ecoff_extern_size
12134 <= g_switch_value))
12136 /* We must defer this decision until after the whole
12137 file has been read, since there might be a .extern
12138 after the first use of this symbol. */
12139 || (before_relaxing
12140 #ifndef NO_ECOFF_DEBUGGING
12141 && symbol_get_obj (sym)->ecoff_extern_size == 0
12143 && S_GET_VALUE (sym) == 0)
12144 || (S_GET_VALUE (sym) != 0
12145 && S_GET_VALUE (sym) <= g_switch_value)))
12149 const char *segname;
12151 segname = segment_name (S_GET_SEGMENT (sym));
12152 assert (strcmp (segname, ".lit8") != 0
12153 && strcmp (segname, ".lit4") != 0);
12154 change = (strcmp (segname, ".sdata") != 0
12155 && strcmp (segname, ".sbss") != 0
12156 && strncmp (segname, ".sdata.", 7) != 0
12157 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12162 /* We are not optimizing for the $gp register. */
12166 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12167 extended opcode. SEC is the section the frag is in. */
12170 mips16_extended_frag (fragp, sec, stretch)
12176 register const struct mips16_immed_operand *op;
12178 int mintiny, maxtiny;
12182 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12184 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12187 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12188 op = mips16_immed_operands;
12189 while (op->type != type)
12192 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12197 if (type == '<' || type == '>' || type == '[' || type == ']')
12200 maxtiny = 1 << op->nbits;
12205 maxtiny = (1 << op->nbits) - 1;
12210 mintiny = - (1 << (op->nbits - 1));
12211 maxtiny = (1 << (op->nbits - 1)) - 1;
12214 sym_frag = symbol_get_frag (fragp->fr_symbol);
12215 val = S_GET_VALUE (fragp->fr_symbol);
12216 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12222 /* We won't have the section when we are called from
12223 mips_relax_frag. However, we will always have been called
12224 from md_estimate_size_before_relax first. If this is a
12225 branch to a different section, we mark it as such. If SEC is
12226 NULL, and the frag is not marked, then it must be a branch to
12227 the same section. */
12230 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12235 /* Must have been called from md_estimate_size_before_relax. */
12238 fragp->fr_subtype =
12239 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12241 /* FIXME: We should support this, and let the linker
12242 catch branches and loads that are out of range. */
12243 as_bad_where (fragp->fr_file, fragp->fr_line,
12244 _("unsupported PC relative reference to different section"));
12248 if (fragp != sym_frag && sym_frag->fr_address == 0)
12249 /* Assume non-extended on the first relaxation pass.
12250 The address we have calculated will be bogus if this is
12251 a forward branch to another frag, as the forward frag
12252 will have fr_address == 0. */
12256 /* In this case, we know for sure that the symbol fragment is in
12257 the same section. If the relax_marker of the symbol fragment
12258 differs from the relax_marker of this fragment, we have not
12259 yet adjusted the symbol fragment fr_address. We want to add
12260 in STRETCH in order to get a better estimate of the address.
12261 This particularly matters because of the shift bits. */
12263 && sym_frag->relax_marker != fragp->relax_marker)
12267 /* Adjust stretch for any alignment frag. Note that if have
12268 been expanding the earlier code, the symbol may be
12269 defined in what appears to be an earlier frag. FIXME:
12270 This doesn't handle the fr_subtype field, which specifies
12271 a maximum number of bytes to skip when doing an
12273 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12275 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12278 stretch = - ((- stretch)
12279 & ~ ((1 << (int) f->fr_offset) - 1));
12281 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12290 addr = fragp->fr_address + fragp->fr_fix;
12292 /* The base address rules are complicated. The base address of
12293 a branch is the following instruction. The base address of a
12294 PC relative load or add is the instruction itself, but if it
12295 is in a delay slot (in which case it can not be extended) use
12296 the address of the instruction whose delay slot it is in. */
12297 if (type == 'p' || type == 'q')
12301 /* If we are currently assuming that this frag should be
12302 extended, then, the current address is two bytes
12304 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12307 /* Ignore the low bit in the target, since it will be set
12308 for a text label. */
12309 if ((val & 1) != 0)
12312 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12314 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12317 val -= addr & ~ ((1 << op->shift) - 1);
12319 /* Branch offsets have an implicit 0 in the lowest bit. */
12320 if (type == 'p' || type == 'q')
12323 /* If any of the shifted bits are set, we must use an extended
12324 opcode. If the address depends on the size of this
12325 instruction, this can lead to a loop, so we arrange to always
12326 use an extended opcode. We only check this when we are in
12327 the main relaxation loop, when SEC is NULL. */
12328 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12330 fragp->fr_subtype =
12331 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12335 /* If we are about to mark a frag as extended because the value
12336 is precisely maxtiny + 1, then there is a chance of an
12337 infinite loop as in the following code:
12342 In this case when the la is extended, foo is 0x3fc bytes
12343 away, so the la can be shrunk, but then foo is 0x400 away, so
12344 the la must be extended. To avoid this loop, we mark the
12345 frag as extended if it was small, and is about to become
12346 extended with a value of maxtiny + 1. */
12347 if (val == ((maxtiny + 1) << op->shift)
12348 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12351 fragp->fr_subtype =
12352 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12356 else if (symsec != absolute_section && sec != NULL)
12357 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12359 if ((val & ((1 << op->shift) - 1)) != 0
12360 || val < (mintiny << op->shift)
12361 || val > (maxtiny << op->shift))
12367 /* Estimate the size of a frag before relaxing. Unless this is the
12368 mips16, we are not really relaxing here, and the final size is
12369 encoded in the subtype information. For the mips16, we have to
12370 decide whether we are using an extended opcode or not. */
12373 md_estimate_size_before_relax (fragp, segtype)
12378 boolean linkonce = false;
12380 if (RELAX_MIPS16_P (fragp->fr_subtype))
12381 /* We don't want to modify the EXTENDED bit here; it might get us
12382 into infinite loops. We change it only in mips_relax_frag(). */
12383 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12385 if (mips_pic == NO_PIC)
12387 change = nopic_need_relax (fragp->fr_symbol, 0);
12389 else if (mips_pic == SVR4_PIC)
12394 sym = fragp->fr_symbol;
12396 /* Handle the case of a symbol equated to another symbol. */
12397 while (symbol_equated_reloc_p (sym))
12401 /* It's possible to get a loop here in a badly written
12403 n = symbol_get_value_expression (sym)->X_add_symbol;
12409 symsec = S_GET_SEGMENT (sym);
12411 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12412 if (symsec != segtype && ! S_IS_LOCAL (sym))
12414 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12418 /* The GNU toolchain uses an extension for ELF: a section
12419 beginning with the magic string .gnu.linkonce is a linkonce
12421 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12422 sizeof ".gnu.linkonce" - 1) == 0)
12426 /* This must duplicate the test in adjust_reloc_syms. */
12427 change = (symsec != &bfd_und_section
12428 && symsec != &bfd_abs_section
12429 && ! bfd_is_com_section (symsec)
12432 /* A global or weak symbol is treated as external. */
12433 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12434 || (! S_IS_WEAK (sym)
12435 && (! S_IS_EXTERNAL (sym)
12436 || mips_pic == EMBEDDED_PIC)))
12445 /* Record the offset to the first reloc in the fr_opcode field.
12446 This lets md_convert_frag and tc_gen_reloc know that the code
12447 must be expanded. */
12448 fragp->fr_opcode = (fragp->fr_literal
12450 - RELAX_OLD (fragp->fr_subtype)
12451 + RELAX_RELOC1 (fragp->fr_subtype));
12452 /* FIXME: This really needs as_warn_where. */
12453 if (RELAX_WARN (fragp->fr_subtype))
12454 as_warn (_("AT used after \".set noat\" or macro used after "
12455 "\".set nomacro\""));
12457 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12463 /* This is called to see whether a reloc against a defined symbol
12464 should be converted into a reloc against a section. Don't adjust
12465 MIPS16 jump relocations, so we don't have to worry about the format
12466 of the offset in the .o file. Don't adjust relocations against
12467 mips16 symbols, so that the linker can find them if it needs to set
12471 mips_fix_adjustable (fixp)
12475 /* Prevent all adjustments to global symbols. */
12476 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12477 && mips_pic != EMBEDDED_PIC
12478 && (S_IS_EXTERNAL (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12481 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12483 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12484 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12486 if (fixp->fx_addsy == NULL)
12489 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12490 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12491 && fixp->fx_subsy == NULL)
12497 /* Translate internal representation of relocation info to BFD target
12501 tc_gen_reloc (section, fixp)
12502 asection *section ATTRIBUTE_UNUSED;
12505 static arelent *retval[4];
12507 bfd_reloc_code_real_type code;
12509 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12512 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12513 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12514 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12516 if (mips_pic == EMBEDDED_PIC
12517 && SWITCH_TABLE (fixp))
12519 /* For a switch table entry we use a special reloc. The addend
12520 is actually the difference between the reloc address and the
12522 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12523 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12524 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12525 fixp->fx_r_type = BFD_RELOC_GPREL32;
12527 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12529 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12530 reloc->addend = fixp->fx_addnumber;
12533 /* We use a special addend for an internal RELLO reloc. */
12534 if (symbol_section_p (fixp->fx_addsy))
12535 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12537 reloc->addend = fixp->fx_addnumber + reloc->address;
12540 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12542 assert (fixp->fx_next != NULL
12543 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12545 /* The reloc is relative to the RELLO; adjust the addend
12547 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12548 reloc->addend = fixp->fx_next->fx_addnumber;
12551 /* We use a special addend for an internal RELHI reloc. */
12552 if (symbol_section_p (fixp->fx_addsy))
12553 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12554 + fixp->fx_next->fx_where
12555 - S_GET_VALUE (fixp->fx_subsy));
12557 reloc->addend = (fixp->fx_addnumber
12558 + fixp->fx_next->fx_frag->fr_address
12559 + fixp->fx_next->fx_where);
12562 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12563 reloc->addend = fixp->fx_addnumber;
12566 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12567 /* A gruesome hack which is a result of the gruesome gas reloc
12569 reloc->addend = reloc->address;
12571 reloc->addend = -reloc->address;
12574 /* If this is a variant frag, we may need to adjust the existing
12575 reloc and generate a new one. */
12576 if (fixp->fx_frag->fr_opcode != NULL
12577 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12578 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12579 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12580 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12581 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12582 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12583 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12588 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12590 /* If this is not the last reloc in this frag, then we have two
12591 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12592 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12593 the second one handle all of them. */
12594 if (fixp->fx_next != NULL
12595 && fixp->fx_frag == fixp->fx_next->fx_frag)
12597 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12598 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12599 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12600 && (fixp->fx_next->fx_r_type
12601 == BFD_RELOC_MIPS_GOT_LO16))
12602 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12603 && (fixp->fx_next->fx_r_type
12604 == BFD_RELOC_MIPS_CALL_LO16)));
12609 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12610 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12611 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12613 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12614 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12615 reloc2->address = (reloc->address
12616 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12617 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12618 reloc2->addend = fixp->fx_addnumber;
12619 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12620 assert (reloc2->howto != NULL);
12622 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12626 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12629 reloc3->address += 4;
12632 if (mips_pic == NO_PIC)
12634 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12635 fixp->fx_r_type = BFD_RELOC_HI16_S;
12637 else if (mips_pic == SVR4_PIC)
12639 switch (fixp->fx_r_type)
12643 case BFD_RELOC_MIPS_GOT16:
12645 case BFD_RELOC_MIPS_CALL16:
12646 case BFD_RELOC_MIPS_GOT_LO16:
12647 case BFD_RELOC_MIPS_CALL_LO16:
12648 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12656 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12657 entry to be used in the relocation's section offset. */
12658 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12660 reloc->address = reloc->addend;
12664 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12665 fixup_segment converted a non-PC relative reloc into a PC
12666 relative reloc. In such a case, we need to convert the reloc
12668 code = fixp->fx_r_type;
12669 if (fixp->fx_pcrel)
12674 code = BFD_RELOC_8_PCREL;
12677 code = BFD_RELOC_16_PCREL;
12680 code = BFD_RELOC_32_PCREL;
12683 code = BFD_RELOC_64_PCREL;
12685 case BFD_RELOC_8_PCREL:
12686 case BFD_RELOC_16_PCREL:
12687 case BFD_RELOC_32_PCREL:
12688 case BFD_RELOC_64_PCREL:
12689 case BFD_RELOC_16_PCREL_S2:
12690 case BFD_RELOC_PCREL_HI16_S:
12691 case BFD_RELOC_PCREL_LO16:
12694 as_bad_where (fixp->fx_file, fixp->fx_line,
12695 _("Cannot make %s relocation PC relative"),
12696 bfd_get_reloc_code_name (code));
12701 /* md_apply_fix3 has a double-subtraction hack to get
12702 bfd_install_relocation to behave nicely. GPREL relocations are
12703 handled correctly without this hack, so undo it here. We can't
12704 stop md_apply_fix3 from subtracting twice in the first place since
12705 the fake addend is required for variant frags above. */
12706 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12707 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
12708 && reloc->addend != 0
12709 && mips_need_elf_addend_fixup (fixp))
12710 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12713 /* To support a PC relative reloc when generating embedded PIC code
12714 for ECOFF, we use a Cygnus extension. We check for that here to
12715 make sure that we don't let such a reloc escape normally. */
12716 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12717 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12718 && code == BFD_RELOC_16_PCREL_S2
12719 && mips_pic != EMBEDDED_PIC)
12720 reloc->howto = NULL;
12722 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12724 if (reloc->howto == NULL)
12726 as_bad_where (fixp->fx_file, fixp->fx_line,
12727 _("Can not represent %s relocation in this object file format"),
12728 bfd_get_reloc_code_name (code));
12735 /* Relax a machine dependent frag. This returns the amount by which
12736 the current size of the frag should change. */
12739 mips_relax_frag (fragp, stretch)
12743 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12746 if (mips16_extended_frag (fragp, NULL, stretch))
12748 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12750 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12755 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12757 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12764 /* Convert a machine dependent frag. */
12767 md_convert_frag (abfd, asec, fragp)
12768 bfd *abfd ATTRIBUTE_UNUSED;
12775 if (RELAX_MIPS16_P (fragp->fr_subtype))
12778 register const struct mips16_immed_operand *op;
12779 boolean small, ext;
12782 unsigned long insn;
12783 boolean use_extend;
12784 unsigned short extend;
12786 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12787 op = mips16_immed_operands;
12788 while (op->type != type)
12791 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12802 resolve_symbol_value (fragp->fr_symbol);
12803 val = S_GET_VALUE (fragp->fr_symbol);
12808 addr = fragp->fr_address + fragp->fr_fix;
12810 /* The rules for the base address of a PC relative reloc are
12811 complicated; see mips16_extended_frag. */
12812 if (type == 'p' || type == 'q')
12817 /* Ignore the low bit in the target, since it will be
12818 set for a text label. */
12819 if ((val & 1) != 0)
12822 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12824 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12827 addr &= ~ (addressT) ((1 << op->shift) - 1);
12830 /* Make sure the section winds up with the alignment we have
12833 record_alignment (asec, op->shift);
12837 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12838 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12839 as_warn_where (fragp->fr_file, fragp->fr_line,
12840 _("extended instruction in delay slot"));
12842 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
12844 if (target_big_endian)
12845 insn = bfd_getb16 (buf);
12847 insn = bfd_getl16 (buf);
12849 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
12850 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
12851 small, ext, &insn, &use_extend, &extend);
12855 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
12856 fragp->fr_fix += 2;
12860 md_number_to_chars ((char *) buf, insn, 2);
12861 fragp->fr_fix += 2;
12866 if (fragp->fr_opcode == NULL)
12869 old = RELAX_OLD (fragp->fr_subtype);
12870 new = RELAX_NEW (fragp->fr_subtype);
12871 fixptr = fragp->fr_literal + fragp->fr_fix;
12874 memcpy (fixptr - old, fixptr, new);
12876 fragp->fr_fix += new - old;
12882 /* This function is called after the relocs have been generated.
12883 We've been storing mips16 text labels as odd. Here we convert them
12884 back to even for the convenience of the debugger. */
12887 mips_frob_file_after_relocs ()
12890 unsigned int count, i;
12892 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12895 syms = bfd_get_outsymbols (stdoutput);
12896 count = bfd_get_symcount (stdoutput);
12897 for (i = 0; i < count; i++, syms++)
12899 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
12900 && ((*syms)->value & 1) != 0)
12902 (*syms)->value &= ~1;
12903 /* If the symbol has an odd size, it was probably computed
12904 incorrectly, so adjust that as well. */
12905 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
12906 ++elf_symbol (*syms)->internal_elf_sym.st_size;
12913 /* This function is called whenever a label is defined. It is used
12914 when handling branch delays; if a branch has a label, we assume we
12915 can not move it. */
12918 mips_define_label (sym)
12921 struct insn_label_list *l;
12923 if (free_insn_labels == NULL)
12924 l = (struct insn_label_list *) xmalloc (sizeof *l);
12927 l = free_insn_labels;
12928 free_insn_labels = l->next;
12932 l->next = insn_labels;
12936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12938 /* Some special processing for a MIPS ELF file. */
12941 mips_elf_final_processing ()
12943 /* Write out the register information. */
12944 if (mips_abi != N64_ABI)
12948 s.ri_gprmask = mips_gprmask;
12949 s.ri_cprmask[0] = mips_cprmask[0];
12950 s.ri_cprmask[1] = mips_cprmask[1];
12951 s.ri_cprmask[2] = mips_cprmask[2];
12952 s.ri_cprmask[3] = mips_cprmask[3];
12953 /* The gp_value field is set by the MIPS ELF backend. */
12955 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
12956 ((Elf32_External_RegInfo *)
12957 mips_regmask_frag));
12961 Elf64_Internal_RegInfo s;
12963 s.ri_gprmask = mips_gprmask;
12965 s.ri_cprmask[0] = mips_cprmask[0];
12966 s.ri_cprmask[1] = mips_cprmask[1];
12967 s.ri_cprmask[2] = mips_cprmask[2];
12968 s.ri_cprmask[3] = mips_cprmask[3];
12969 /* The gp_value field is set by the MIPS ELF backend. */
12971 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
12972 ((Elf64_External_RegInfo *)
12973 mips_regmask_frag));
12976 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12977 sort of BFD interface for this. */
12978 if (mips_any_noreorder)
12979 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
12980 if (mips_pic != NO_PIC)
12981 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
12983 /* Set MIPS ELF flags for ASEs. */
12984 if (file_ase_mips16)
12985 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
12986 #if 0 /* XXX FIXME */
12987 if (file_ase_mips3d)
12988 elf_elfheader (stdoutput)->e_flags |= ???;
12991 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
12993 /* Set the MIPS ELF ABI flags. */
12994 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
12995 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
12996 else if (mips_abi == O64_ABI)
12997 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
12998 else if (mips_abi == EABI_ABI)
13000 if (!file_mips_gp32)
13001 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13003 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13005 else if (mips_abi == N32_ABI)
13006 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13008 /* Nothing to do for N64_ABI. */
13010 if (mips_32bitmode)
13011 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13014 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13016 typedef struct proc {
13018 unsigned long reg_mask;
13019 unsigned long reg_offset;
13020 unsigned long fpreg_mask;
13021 unsigned long fpreg_offset;
13022 unsigned long frame_offset;
13023 unsigned long frame_reg;
13024 unsigned long pc_reg;
13027 static procS cur_proc;
13028 static procS *cur_proc_ptr;
13029 static int numprocs;
13031 /* Fill in an rs_align_code fragment. */
13034 mips_handle_align (fragp)
13037 if (fragp->fr_type != rs_align_code)
13040 if (mips_opts.mips16)
13042 static const unsigned char be_nop[] = { 0x65, 0x00 };
13043 static const unsigned char le_nop[] = { 0x00, 0x65 };
13048 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13049 p = fragp->fr_literal + fragp->fr_fix;
13057 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13061 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13072 /* check for premature end, nesting errors, etc */
13074 as_warn (_("missing .end at end of assembly"));
13083 if (*input_line_pointer == '-')
13085 ++input_line_pointer;
13088 if (!ISDIGIT (*input_line_pointer))
13089 as_bad (_("expected simple number"));
13090 if (input_line_pointer[0] == '0')
13092 if (input_line_pointer[1] == 'x')
13094 input_line_pointer += 2;
13095 while (ISXDIGIT (*input_line_pointer))
13098 val |= hex_value (*input_line_pointer++);
13100 return negative ? -val : val;
13104 ++input_line_pointer;
13105 while (ISDIGIT (*input_line_pointer))
13108 val |= *input_line_pointer++ - '0';
13110 return negative ? -val : val;
13113 if (!ISDIGIT (*input_line_pointer))
13115 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13116 *input_line_pointer, *input_line_pointer);
13117 as_warn (_("invalid number"));
13120 while (ISDIGIT (*input_line_pointer))
13123 val += *input_line_pointer++ - '0';
13125 return negative ? -val : val;
13128 /* The .file directive; just like the usual .file directive, but there
13129 is an initial number which is the ECOFF file index. In the non-ECOFF
13130 case .file implies DWARF-2. */
13134 int x ATTRIBUTE_UNUSED;
13136 static int first_file_directive = 0;
13138 if (ECOFF_DEBUGGING)
13147 filename = dwarf2_directive_file (0);
13149 /* Versions of GCC up to 3.1 start files with a ".file"
13150 directive even for stabs output. Make sure that this
13151 ".file" is handled. Note that you need a version of GCC
13152 after 3.1 in order to support DWARF-2 on MIPS. */
13153 if (filename != NULL && ! first_file_directive)
13155 (void) new_logical_line (filename, -1);
13156 s_app_file_string (filename);
13158 first_file_directive = 1;
13162 /* The .loc directive, implying DWARF-2. */
13166 int x ATTRIBUTE_UNUSED;
13168 if (!ECOFF_DEBUGGING)
13169 dwarf2_directive_loc (0);
13172 /* The .end directive. */
13176 int x ATTRIBUTE_UNUSED;
13181 /* Following functions need their own .frame and .cprestore directives. */
13182 mips_frame_reg_valid = 0;
13183 mips_cprestore_valid = 0;
13185 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13188 demand_empty_rest_of_line ();
13193 #ifdef BFD_ASSEMBLER
13194 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13199 if (now_seg != data_section && now_seg != bss_section)
13206 as_warn (_(".end not in text section"));
13210 as_warn (_(".end directive without a preceding .ent directive."));
13211 demand_empty_rest_of_line ();
13217 assert (S_GET_NAME (p));
13218 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13219 as_warn (_(".end symbol does not match .ent symbol."));
13221 if (debug_type == DEBUG_STABS)
13222 stabs_generate_asm_endfunc (S_GET_NAME (p),
13226 as_warn (_(".end directive missing or unknown symbol"));
13229 /* Generate a .pdr section. */
13230 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13232 segT saved_seg = now_seg;
13233 subsegT saved_subseg = now_subseg;
13238 dot = frag_now_fix ();
13240 #ifdef md_flush_pending_output
13241 md_flush_pending_output ();
13245 subseg_set (pdr_seg, 0);
13247 /* Write the symbol. */
13248 exp.X_op = O_symbol;
13249 exp.X_add_symbol = p;
13250 exp.X_add_number = 0;
13251 emit_expr (&exp, 4);
13253 fragp = frag_more (7 * 4);
13255 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13256 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13257 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13258 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13259 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13260 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13261 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13263 subseg_set (saved_seg, saved_subseg);
13265 #endif /* OBJ_ELF */
13267 cur_proc_ptr = NULL;
13270 /* The .aent and .ent directives. */
13279 symbolP = get_symbol ();
13280 if (*input_line_pointer == ',')
13281 ++input_line_pointer;
13282 SKIP_WHITESPACE ();
13283 if (ISDIGIT (*input_line_pointer)
13284 || *input_line_pointer == '-')
13287 #ifdef BFD_ASSEMBLER
13288 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13293 if (now_seg != data_section && now_seg != bss_section)
13300 as_warn (_(".ent or .aent not in text section."));
13302 if (!aent && cur_proc_ptr)
13303 as_warn (_("missing .end"));
13307 /* This function needs its own .frame and .cprestore directives. */
13308 mips_frame_reg_valid = 0;
13309 mips_cprestore_valid = 0;
13311 cur_proc_ptr = &cur_proc;
13312 memset (cur_proc_ptr, '\0', sizeof (procS));
13314 cur_proc_ptr->isym = symbolP;
13316 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13320 if (debug_type == DEBUG_STABS)
13321 stabs_generate_asm_func (S_GET_NAME (symbolP),
13322 S_GET_NAME (symbolP));
13325 demand_empty_rest_of_line ();
13328 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13329 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13330 s_mips_frame is used so that we can set the PDR information correctly.
13331 We can't use the ecoff routines because they make reference to the ecoff
13332 symbol table (in the mdebug section). */
13335 s_mips_frame (ignore)
13336 int ignore ATTRIBUTE_UNUSED;
13339 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13343 if (cur_proc_ptr == (procS *) NULL)
13345 as_warn (_(".frame outside of .ent"));
13346 demand_empty_rest_of_line ();
13350 cur_proc_ptr->frame_reg = tc_get_register (1);
13352 SKIP_WHITESPACE ();
13353 if (*input_line_pointer++ != ','
13354 || get_absolute_expression_and_terminator (&val) != ',')
13356 as_warn (_("Bad .frame directive"));
13357 --input_line_pointer;
13358 demand_empty_rest_of_line ();
13362 cur_proc_ptr->frame_offset = val;
13363 cur_proc_ptr->pc_reg = tc_get_register (0);
13365 demand_empty_rest_of_line ();
13368 #endif /* OBJ_ELF */
13372 /* The .fmask and .mask directives. If the mdebug section is present
13373 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13374 embedded targets, s_mips_mask is used so that we can set the PDR
13375 information correctly. We can't use the ecoff routines because they
13376 make reference to the ecoff symbol table (in the mdebug section). */
13379 s_mips_mask (reg_type)
13383 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13387 if (cur_proc_ptr == (procS *) NULL)
13389 as_warn (_(".mask/.fmask outside of .ent"));
13390 demand_empty_rest_of_line ();
13394 if (get_absolute_expression_and_terminator (&mask) != ',')
13396 as_warn (_("Bad .mask/.fmask directive"));
13397 --input_line_pointer;
13398 demand_empty_rest_of_line ();
13402 off = get_absolute_expression ();
13404 if (reg_type == 'F')
13406 cur_proc_ptr->fpreg_mask = mask;
13407 cur_proc_ptr->fpreg_offset = off;
13411 cur_proc_ptr->reg_mask = mask;
13412 cur_proc_ptr->reg_offset = off;
13415 demand_empty_rest_of_line ();
13418 #endif /* OBJ_ELF */
13419 s_ignore (reg_type);
13422 /* The .loc directive. */
13433 assert (now_seg == text_section);
13435 lineno = get_number ();
13436 addroff = frag_now_fix ();
13438 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13439 S_SET_TYPE (symbolP, N_SLINE);
13440 S_SET_OTHER (symbolP, 0);
13441 S_SET_DESC (symbolP, lineno);
13442 symbolP->sy_segment = now_seg;
13446 /* A table describing all the processors gas knows about. Names are
13447 matched in the order listed.
13449 To ease comparison, please keep this table in the same order as
13450 gcc's mips_cpu_info_table[]. */
13451 static const struct mips_cpu_info mips_cpu_info_table[] =
13453 /* Entries for generic ISAs */
13454 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13455 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13456 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13457 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13458 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13459 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13460 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13463 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13464 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13465 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13468 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13471 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13472 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13473 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13474 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13475 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13476 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13477 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13478 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13479 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13482 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13483 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13484 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13485 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13486 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13487 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13488 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13489 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13490 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13491 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
13494 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13495 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13496 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13499 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13500 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13502 /* Broadcom SB-1 CPU core */
13503 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13510 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13511 with a final "000" replaced by "k". Ignore case.
13513 Note: this function is shared between GCC and GAS. */
13516 mips_strict_matching_cpu_name_p (canonical, given)
13517 const char *canonical, *given;
13519 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13520 given++, canonical++;
13522 return ((*given == 0 && *canonical == 0)
13523 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13527 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13528 CPU name. We've traditionally allowed a lot of variation here.
13530 Note: this function is shared between GCC and GAS. */
13533 mips_matching_cpu_name_p (canonical, given)
13534 const char *canonical, *given;
13536 /* First see if the name matches exactly, or with a final "000"
13537 turned into "k". */
13538 if (mips_strict_matching_cpu_name_p (canonical, given))
13541 /* If not, try comparing based on numerical designation alone.
13542 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13543 if (TOLOWER (*given) == 'r')
13545 if (!ISDIGIT (*given))
13548 /* Skip over some well-known prefixes in the canonical name,
13549 hoping to find a number there too. */
13550 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13552 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13554 else if (TOLOWER (canonical[0]) == 'r')
13557 return mips_strict_matching_cpu_name_p (canonical, given);
13561 /* Parse an option that takes the name of a processor as its argument.
13562 OPTION is the name of the option and CPU_STRING is the argument.
13563 Return the corresponding processor enumeration if the CPU_STRING is
13564 recognized, otherwise report an error and return null.
13566 A similar function exists in GCC. */
13568 static const struct mips_cpu_info *
13569 mips_parse_cpu (option, cpu_string)
13570 const char *option, *cpu_string;
13572 const struct mips_cpu_info *p;
13574 /* 'from-abi' selects the most compatible architecture for the given
13575 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13576 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13577 version. Look first at the -mgp options, if given, otherwise base
13578 the choice on MIPS_DEFAULT_64BIT.
13580 Treat NO_ABI like the EABIs. One reason to do this is that the
13581 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13582 architecture. This code picks MIPS I for 'mips' and MIPS III for
13583 'mips64', just as we did in the days before 'from-abi'. */
13584 if (strcasecmp (cpu_string, "from-abi") == 0)
13586 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13587 return mips_cpu_info_from_isa (ISA_MIPS1);
13589 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13590 return mips_cpu_info_from_isa (ISA_MIPS3);
13592 if (file_mips_gp32 >= 0)
13593 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13595 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13600 /* 'default' has traditionally been a no-op. Probably not very useful. */
13601 if (strcasecmp (cpu_string, "default") == 0)
13604 for (p = mips_cpu_info_table; p->name != 0; p++)
13605 if (mips_matching_cpu_name_p (p->name, cpu_string))
13608 as_bad ("Bad value (%s) for %s", cpu_string, option);
13612 /* Return the canonical processor information for ISA (a member of the
13613 ISA_MIPS* enumeration). */
13615 static const struct mips_cpu_info *
13616 mips_cpu_info_from_isa (isa)
13621 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13622 if (mips_cpu_info_table[i].is_isa
13623 && isa == mips_cpu_info_table[i].isa)
13624 return (&mips_cpu_info_table[i]);
13630 show (stream, string, col_p, first_p)
13632 const char *string;
13638 fprintf (stream, "%24s", "");
13643 fprintf (stream, ", ");
13647 if (*col_p + strlen (string) > 72)
13649 fprintf (stream, "\n%24s", "");
13653 fprintf (stream, "%s", string);
13654 *col_p += strlen (string);
13660 md_show_usage (stream)
13666 fprintf (stream, _("\
13668 -membedded-pic generate embedded position independent code\n\
13669 -EB generate big endian output\n\
13670 -EL generate little endian output\n\
13671 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13672 -G NUM allow referencing objects up to NUM bytes\n\
13673 implicitly with the gp register [default 8]\n"));
13674 fprintf (stream, _("\
13675 -mips1 generate MIPS ISA I instructions\n\
13676 -mips2 generate MIPS ISA II instructions\n\
13677 -mips3 generate MIPS ISA III instructions\n\
13678 -mips4 generate MIPS ISA IV instructions\n\
13679 -mips5 generate MIPS ISA V instructions\n\
13680 -mips32 generate MIPS32 ISA instructions\n\
13681 -mips64 generate MIPS64 ISA instructions\n\
13682 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13686 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13687 show (stream, mips_cpu_info_table[i].name, &column, &first);
13688 show (stream, "from-abi", &column, &first);
13689 fputc ('\n', stream);
13691 fprintf (stream, _("\
13692 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13693 -no-mCPU don't generate code specific to CPU.\n\
13694 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13698 show (stream, "3900", &column, &first);
13699 show (stream, "4010", &column, &first);
13700 show (stream, "4100", &column, &first);
13701 show (stream, "4650", &column, &first);
13702 fputc ('\n', stream);
13704 fprintf (stream, _("\
13705 -mips16 generate mips16 instructions\n\
13706 -no-mips16 do not generate mips16 instructions\n"));
13707 fprintf (stream, _("\
13708 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13709 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13710 -O0 remove unneeded NOPs, do not swap branches\n\
13711 -O remove unneeded NOPs and swap branches\n\
13712 -n warn about NOPs generated from macros\n\
13713 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13714 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13715 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13717 fprintf (stream, _("\
13718 -KPIC, -call_shared generate SVR4 position independent code\n\
13719 -non_shared do not generate position independent code\n\
13720 -xgot assume a 32 bit GOT\n\
13721 -mabi=ABI create ABI conformant object file for:\n"));
13725 show (stream, "32", &column, &first);
13726 show (stream, "o64", &column, &first);
13727 show (stream, "n32", &column, &first);
13728 show (stream, "64", &column, &first);
13729 show (stream, "eabi", &column, &first);
13731 fputc ('\n', stream);
13733 fprintf (stream, _("\
13734 -32 create o32 ABI object file (default)\n\
13735 -n32 create n32 ABI object file\n\
13736 -64 create 64 ABI object file\n"));