1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
212 <asename>', by command line options, and based on the default
215 /* Whether we are assembling for the mips16 processor. 0 if we are
216 not, 1 if we are, and -1 if the value has not been initialized.
217 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
218 -nomips16 command line options, and the default CPU. */
220 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
221 1 if we are, and -1 if the value has not been initialized. Changed
222 by `.set micromips' and `.set nomicromips', and the -mmicromips
223 and -mno-micromips command line options, and the default CPU. */
225 /* Non-zero if we should not reorder instructions. Changed by `.set
226 reorder' and `.set noreorder'. */
228 /* Non-zero if we should not permit the register designated "assembler
229 temporary" to be used in instructions. The value is the register
230 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
231 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
233 /* Non-zero if we should warn when a macro instruction expands into
234 more than one machine instruction. Changed by `.set nomacro' and
236 int warn_about_macros;
237 /* Non-zero if we should not move instructions. Changed by `.set
238 move', `.set volatile', `.set nomove', and `.set novolatile'. */
240 /* Non-zero if we should not optimize branches by moving the target
241 of the branch into the delay slot. Actually, we don't perform
242 this optimization anyhow. Changed by `.set bopt' and `.set
245 /* Non-zero if we should not autoextend mips16 instructions.
246 Changed by `.set autoextend' and `.set noautoextend'. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float;
269 /* This is the struct we use to hold the current set of options. Note
270 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
271 -1 to indicate that they have not been initialized. */
273 /* True if -mgp32 was passed. */
274 static int file_mips_gp32 = -1;
276 /* True if -mfp32 was passed. */
277 static int file_mips_fp32 = -1;
279 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
280 static int file_mips_soft_float = 0;
282 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
283 static int file_mips_single_float = 0;
285 static struct mips_set_options mips_opts =
287 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
288 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
289 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
290 /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
291 /* soft_float */ FALSE, /* single_float */ FALSE
294 /* The set of ASEs that were selected on the command line, either
295 explicitly via ASE options or implicitly through things like -march. */
296 static unsigned int file_ase;
298 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
299 static unsigned int file_ase_explicit;
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask;
305 unsigned long mips_cprmask[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa = ISA_UNKNOWN;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
334 || mips_opts.isa == ISA_MIPS32R2)
336 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2 \
338 || mips_opts.micromips)
340 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
342 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.micromips)
346 #define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.micromips)
350 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
351 || mips_opts.isa == ISA_MIPS64R2)
353 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2 \
355 || mips_opts.micromips)
357 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
358 || mips_opts.isa == ISA_MIPS64R2 \
359 || mips_opts.micromips)
361 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \
362 || (mips_opts.micromips \
363 && ISA_HAS_64BIT_REGS (mips_opts.isa)))
365 /* The argument of the -march= flag. The architecture we are assembling. */
366 static int file_mips_arch = CPU_UNKNOWN;
367 static const char *mips_arch_string;
369 /* The argument of the -mtune= flag. The architecture for which we
371 static int mips_tune = CPU_UNKNOWN;
372 static const char *mips_tune_string;
374 /* True when generating 32-bit code for a 64-bit processor. */
375 static int mips_32bitmode = 0;
377 /* True if the given ABI requires 32-bit registers. */
378 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
380 /* Likewise 64-bit registers. */
381 #define ABI_NEEDS_64BIT_REGS(ABI) \
383 || (ABI) == N64_ABI \
386 /* Return true if ISA supports 64 bit wide gp registers. */
387 #define ISA_HAS_64BIT_REGS(ISA) \
388 ((ISA) == ISA_MIPS3 \
389 || (ISA) == ISA_MIPS4 \
390 || (ISA) == ISA_MIPS5 \
391 || (ISA) == ISA_MIPS64 \
392 || (ISA) == ISA_MIPS64R2)
394 /* Return true if ISA supports 64 bit wide float registers. */
395 #define ISA_HAS_64BIT_FPRS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports 64-bit right rotate (dror et al.)
405 #define ISA_HAS_DROR(ISA) \
406 ((ISA) == ISA_MIPS64R2 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS64R2 \
416 || (mips_opts.ase & ASE_SMARTMIPS) \
417 || mips_opts.micromips \
420 /* Return true if ISA supports single-precision floats in odd registers. */
421 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
422 ((ISA) == ISA_MIPS32 \
423 || (ISA) == ISA_MIPS32R2 \
424 || (ISA) == ISA_MIPS64 \
425 || (ISA) == ISA_MIPS64R2)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS64R2)
433 #define HAVE_32BIT_GPRS \
434 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
436 #define HAVE_32BIT_FPRS \
437 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
439 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
440 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
442 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
444 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
446 /* True if relocations are stored in-place. */
447 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
449 /* The ABI-derived address size. */
450 #define HAVE_64BIT_ADDRESSES \
451 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
452 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
454 /* The size of symbolic constants (i.e., expressions of the form
455 "SYMBOL" or "SYMBOL + OFFSET"). */
456 #define HAVE_32BIT_SYMBOLS \
457 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
458 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
460 /* Addresses are loaded in different ways, depending on the address size
461 in use. The n32 ABI Documentation also mandates the use of additions
462 with overflow checking, but existing implementations don't follow it. */
463 #define ADDRESS_ADD_INSN \
464 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
466 #define ADDRESS_ADDI_INSN \
467 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
469 #define ADDRESS_LOAD_INSN \
470 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
472 #define ADDRESS_STORE_INSN \
473 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
475 /* Return true if the given CPU supports the MIPS16 ASE. */
476 #define CPU_HAS_MIPS16(cpu) \
477 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
478 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
480 /* Return true if the given CPU supports the microMIPS ASE. */
481 #define CPU_HAS_MICROMIPS(cpu) 0
483 /* True if CPU has a dror instruction. */
484 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
486 /* True if CPU has a ror instruction. */
487 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
489 /* True if CPU is in the Octeon family */
490 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
492 /* True if CPU has seq/sne and seqi/snei instructions. */
493 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
495 /* True, if CPU has support for ldc1 and sdc1. */
496 #define CPU_HAS_LDC1_SDC1(CPU) \
497 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
499 /* True if mflo and mfhi can be immediately followed by instructions
500 which write to the HI and LO registers.
502 According to MIPS specifications, MIPS ISAs I, II, and III need
503 (at least) two instructions between the reads of HI/LO and
504 instructions which write them, and later ISAs do not. Contradicting
505 the MIPS specifications, some MIPS IV processor user manuals (e.g.
506 the UM for the NEC Vr5000) document needing the instructions between
507 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
508 MIPS64 and later ISAs to have the interlocks, plus any specific
509 earlier-ISA CPUs for which CPU documentation declares that the
510 instructions are really interlocked. */
511 #define hilo_interlocks \
512 (mips_opts.isa == ISA_MIPS32 \
513 || mips_opts.isa == ISA_MIPS32R2 \
514 || mips_opts.isa == ISA_MIPS64 \
515 || mips_opts.isa == ISA_MIPS64R2 \
516 || mips_opts.arch == CPU_R4010 \
517 || mips_opts.arch == CPU_R5900 \
518 || mips_opts.arch == CPU_R10000 \
519 || mips_opts.arch == CPU_R12000 \
520 || mips_opts.arch == CPU_R14000 \
521 || mips_opts.arch == CPU_R16000 \
522 || mips_opts.arch == CPU_RM7000 \
523 || mips_opts.arch == CPU_VR5500 \
524 || mips_opts.micromips \
527 /* Whether the processor uses hardware interlocks to protect reads
528 from the GPRs after they are loaded from memory, and thus does not
529 require nops to be inserted. This applies to instructions marked
530 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
531 level I and microMIPS mode instructions are always interlocked. */
532 #define gpr_interlocks \
533 (mips_opts.isa != ISA_MIPS1 \
534 || mips_opts.arch == CPU_R3900 \
535 || mips_opts.arch == CPU_R5900 \
536 || mips_opts.micromips \
539 /* Whether the processor uses hardware interlocks to avoid delays
540 required by coprocessor instructions, and thus does not require
541 nops to be inserted. This applies to instructions marked
542 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
543 between instructions marked INSN_WRITE_COND_CODE and ones marked
544 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
545 levels I, II, and III and microMIPS mode instructions are always
547 /* Itbl support may require additional care here. */
548 #define cop_interlocks \
549 ((mips_opts.isa != ISA_MIPS1 \
550 && mips_opts.isa != ISA_MIPS2 \
551 && mips_opts.isa != ISA_MIPS3) \
552 || mips_opts.arch == CPU_R4300 \
553 || mips_opts.micromips \
556 /* Whether the processor uses hardware interlocks to protect reads
557 from coprocessor registers after they are loaded from memory, and
558 thus does not require nops to be inserted. This applies to
559 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
560 requires at MIPS ISA level I and microMIPS mode instructions are
561 always interlocked. */
562 #define cop_mem_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.micromips \
567 /* Is this a mfhi or mflo instruction? */
568 #define MF_HILO_INSN(PINFO) \
569 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
571 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
572 has been selected. This implies, in particular, that addresses of text
573 labels have their LSB set. */
574 #define HAVE_CODE_COMPRESSION \
575 ((mips_opts.mips16 | mips_opts.micromips) != 0)
577 /* MIPS PIC level. */
579 enum mips_pic_level mips_pic;
581 /* 1 if we should generate 32 bit offsets from the $gp register in
582 SVR4_PIC mode. Currently has no meaning in other modes. */
583 static int mips_big_got = 0;
585 /* 1 if trap instructions should used for overflow rather than break
587 static int mips_trap = 0;
589 /* 1 if double width floating point constants should not be constructed
590 by assembling two single width halves into two single width floating
591 point registers which just happen to alias the double width destination
592 register. On some architectures this aliasing can be disabled by a bit
593 in the status register, and the setting of this bit cannot be determined
594 automatically at assemble time. */
595 static int mips_disable_float_construction;
597 /* Non-zero if any .set noreorder directives were used. */
599 static int mips_any_noreorder;
601 /* Non-zero if nops should be inserted when the register referenced in
602 an mfhi/mflo instruction is read in the next two instructions. */
603 static int mips_7000_hilo_fix;
605 /* The size of objects in the small data section. */
606 static unsigned int g_switch_value = 8;
607 /* Whether the -G option was used. */
608 static int g_switch_seen = 0;
613 /* If we can determine in advance that GP optimization won't be
614 possible, we can skip the relaxation stuff that tries to produce
615 GP-relative references. This makes delay slot optimization work
618 This function can only provide a guess, but it seems to work for
619 gcc output. It needs to guess right for gcc, otherwise gcc
620 will put what it thinks is a GP-relative instruction in a branch
623 I don't know if a fix is needed for the SVR4_PIC mode. I've only
624 fixed it for the non-PIC mode. KR 95/04/07 */
625 static int nopic_need_relax (symbolS *, int);
627 /* handle of the OPCODE hash table */
628 static struct hash_control *op_hash = NULL;
630 /* The opcode hash table we use for the mips16. */
631 static struct hash_control *mips16_op_hash = NULL;
633 /* The opcode hash table we use for the microMIPS ASE. */
634 static struct hash_control *micromips_op_hash = NULL;
636 /* This array holds the chars that always start a comment. If the
637 pre-processor is disabled, these aren't very useful */
638 const char comment_chars[] = "#";
640 /* This array holds the chars that only start a comment at the beginning of
641 a line. If the line seems to have the form '# 123 filename'
642 .line and .file directives will appear in the pre-processed output */
643 /* Note that input_file.c hand checks for '#' at the beginning of the
644 first line of the input file. This is because the compiler outputs
645 #NO_APP at the beginning of its output. */
646 /* Also note that C style comments are always supported. */
647 const char line_comment_chars[] = "#";
649 /* This array holds machine specific line separator characters. */
650 const char line_separator_chars[] = ";";
652 /* Chars that can be used to separate mant from exp in floating point nums */
653 const char EXP_CHARS[] = "eE";
655 /* Chars that mean this number is a floating point constant */
658 const char FLT_CHARS[] = "rRsSfFdDxXpP";
660 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
661 changed in read.c . Ideally it shouldn't have to know about it at all,
662 but nothing is ideal around here.
665 static char *insn_error;
667 static int auto_align = 1;
669 /* When outputting SVR4 PIC code, the assembler needs to know the
670 offset in the stack frame from which to restore the $gp register.
671 This is set by the .cprestore pseudo-op, and saved in this
673 static offsetT mips_cprestore_offset = -1;
675 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
676 more optimizations, it can use a register value instead of a memory-saved
677 offset and even an other register than $gp as global pointer. */
678 static offsetT mips_cpreturn_offset = -1;
679 static int mips_cpreturn_register = -1;
680 static int mips_gp_register = GP;
681 static int mips_gprel_offset = 0;
683 /* Whether mips_cprestore_offset has been set in the current function
684 (or whether it has already been warned about, if not). */
685 static int mips_cprestore_valid = 0;
687 /* This is the register which holds the stack frame, as set by the
688 .frame pseudo-op. This is needed to implement .cprestore. */
689 static int mips_frame_reg = SP;
691 /* Whether mips_frame_reg has been set in the current function
692 (or whether it has already been warned about, if not). */
693 static int mips_frame_reg_valid = 0;
695 /* To output NOP instructions correctly, we need to keep information
696 about the previous two instructions. */
698 /* Whether we are optimizing. The default value of 2 means to remove
699 unneeded NOPs and swap branch instructions when possible. A value
700 of 1 means to not swap branches. A value of 0 means to always
702 static int mips_optimize = 2;
704 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
705 equivalent to seeing no -g option at all. */
706 static int mips_debug = 0;
708 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
709 #define MAX_VR4130_NOPS 4
711 /* The maximum number of NOPs needed to fill delay slots. */
712 #define MAX_DELAY_NOPS 2
714 /* The maximum number of NOPs needed for any purpose. */
717 /* A list of previous instructions, with index 0 being the most recent.
718 We need to look back MAX_NOPS instructions when filling delay slots
719 or working around processor errata. We need to look back one
720 instruction further if we're thinking about using history[0] to
721 fill a branch delay slot. */
722 static struct mips_cl_insn history[1 + MAX_NOPS];
724 /* Nop instructions used by emit_nop. */
725 static struct mips_cl_insn nop_insn;
726 static struct mips_cl_insn mips16_nop_insn;
727 static struct mips_cl_insn micromips_nop16_insn;
728 static struct mips_cl_insn micromips_nop32_insn;
730 /* The appropriate nop for the current mode. */
731 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
732 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
734 /* The size of NOP_INSN in bytes. */
735 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
737 /* If this is set, it points to a frag holding nop instructions which
738 were inserted before the start of a noreorder section. If those
739 nops turn out to be unnecessary, the size of the frag can be
741 static fragS *prev_nop_frag;
743 /* The number of nop instructions we created in prev_nop_frag. */
744 static int prev_nop_frag_holds;
746 /* The number of nop instructions that we know we need in
748 static int prev_nop_frag_required;
750 /* The number of instructions we've seen since prev_nop_frag. */
751 static int prev_nop_frag_since;
753 /* For ECOFF and ELF, relocations against symbols are done in two
754 parts, with a HI relocation and a LO relocation. Each relocation
755 has only 16 bits of space to store an addend. This means that in
756 order for the linker to handle carries correctly, it must be able
757 to locate both the HI and the LO relocation. This means that the
758 relocations must appear in order in the relocation table.
760 In order to implement this, we keep track of each unmatched HI
761 relocation. We then sort them so that they immediately precede the
762 corresponding LO relocation. */
767 struct mips_hi_fixup *next;
770 /* The section this fixup is in. */
774 /* The list of unmatched HI relocs. */
776 static struct mips_hi_fixup *mips_hi_fixup_list;
778 /* The frag containing the last explicit relocation operator.
779 Null if explicit relocations have not been used. */
781 static fragS *prev_reloc_op_frag;
783 /* Map normal MIPS register numbers to mips16 register numbers. */
785 #define X ILLEGAL_REG
786 static const int mips32_to_16_reg_map[] =
788 X, X, 2, 3, 4, 5, 6, 7,
789 X, X, X, X, X, X, X, X,
790 0, 1, X, X, X, X, X, X,
791 X, X, X, X, X, X, X, X
795 /* Map mips16 register numbers to normal MIPS register numbers. */
797 static const unsigned int mips16_to_32_reg_map[] =
799 16, 17, 2, 3, 4, 5, 6, 7
802 /* Map normal MIPS register numbers to microMIPS register numbers. */
804 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
805 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
806 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
812 #define X ILLEGAL_REG
813 /* reg type h: 4, 5, 6. */
814 static const int mips32_to_micromips_reg_h_map[] =
816 X, X, X, X, 4, 5, 6, X,
817 X, X, X, X, X, X, X, X,
818 X, X, X, X, X, X, X, X,
819 X, X, X, X, X, X, X, X
822 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
823 static const int mips32_to_micromips_reg_m_map[] =
825 0, X, 2, 3, X, X, X, X,
826 X, X, X, X, X, X, X, X,
827 4, 1, 5, 6, 7, X, X, X,
828 X, X, X, X, X, X, X, X
831 /* reg type q: 0, 2-7. 17. */
832 static const int mips32_to_micromips_reg_q_map[] =
834 0, X, 2, 3, 4, 5, 6, 7,
835 X, X, X, X, X, X, X, X,
836 X, 1, X, X, X, X, X, X,
837 X, X, X, X, X, X, X, X
840 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
843 /* Map microMIPS register numbers to normal MIPS register numbers. */
845 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
846 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
847 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
852 /* The microMIPS registers with type h. */
853 static const unsigned int micromips_to_32_reg_h_map[] =
855 5, 5, 6, 4, 4, 4, 4, 4
858 /* The microMIPS registers with type i. */
859 static const unsigned int micromips_to_32_reg_i_map[] =
861 6, 7, 7, 21, 22, 5, 6, 7
864 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
866 /* The microMIPS registers with type m. */
867 static const unsigned int micromips_to_32_reg_m_map[] =
869 0, 17, 2, 3, 16, 18, 19, 20
872 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
874 /* The microMIPS registers with type q. */
875 static const unsigned int micromips_to_32_reg_q_map[] =
877 0, 17, 2, 3, 4, 5, 6, 7
880 /* microMIPS imm type B. */
881 static const int micromips_imm_b_map[] =
883 1, 4, 8, 12, 16, 20, 24, -1
886 /* microMIPS imm type C. */
887 static const int micromips_imm_c_map[] =
889 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
892 /* Classifies the kind of instructions we're interested in when
893 implementing -mfix-vr4120. */
894 enum fix_vr4120_class
902 NUM_FIX_VR4120_CLASSES
905 /* ...likewise -mfix-loongson2f-jump. */
906 static bfd_boolean mips_fix_loongson2f_jump;
908 /* ...likewise -mfix-loongson2f-nop. */
909 static bfd_boolean mips_fix_loongson2f_nop;
911 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
912 static bfd_boolean mips_fix_loongson2f;
914 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
915 there must be at least one other instruction between an instruction
916 of type X and an instruction of type Y. */
917 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
919 /* True if -mfix-vr4120 is in force. */
920 static int mips_fix_vr4120;
922 /* ...likewise -mfix-vr4130. */
923 static int mips_fix_vr4130;
925 /* ...likewise -mfix-24k. */
926 static int mips_fix_24k;
928 /* ...likewise -mfix-cn63xxp1 */
929 static bfd_boolean mips_fix_cn63xxp1;
931 /* We don't relax branches by default, since this causes us to expand
932 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
933 fail to compute the offset before expanding the macro to the most
934 efficient expansion. */
936 static int mips_relax_branch;
938 /* The expansion of many macros depends on the type of symbol that
939 they refer to. For example, when generating position-dependent code,
940 a macro that refers to a symbol may have two different expansions,
941 one which uses GP-relative addresses and one which uses absolute
942 addresses. When generating SVR4-style PIC, a macro may have
943 different expansions for local and global symbols.
945 We handle these situations by generating both sequences and putting
946 them in variant frags. In position-dependent code, the first sequence
947 will be the GP-relative one and the second sequence will be the
948 absolute one. In SVR4 PIC, the first sequence will be for global
949 symbols and the second will be for local symbols.
951 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
952 SECOND are the lengths of the two sequences in bytes. These fields
953 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
954 the subtype has the following flags:
957 Set if it has been decided that we should use the second
958 sequence instead of the first.
961 Set in the first variant frag if the macro's second implementation
962 is longer than its first. This refers to the macro as a whole,
963 not an individual relaxation.
966 Set in the first variant frag if the macro appeared in a .set nomacro
967 block and if one alternative requires a warning but the other does not.
970 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
973 RELAX_DELAY_SLOT_16BIT
974 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
977 RELAX_DELAY_SLOT_SIZE_FIRST
978 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
979 the macro is of the wrong size for the branch delay slot.
981 RELAX_DELAY_SLOT_SIZE_SECOND
982 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
983 the macro is of the wrong size for the branch delay slot.
985 The frag's "opcode" points to the first fixup for relaxable code.
987 Relaxable macros are generated using a sequence such as:
989 relax_start (SYMBOL);
990 ... generate first expansion ...
992 ... generate second expansion ...
995 The code and fixups for the unwanted alternative are discarded
996 by md_convert_frag. */
997 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
999 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1000 #define RELAX_SECOND(X) ((X) & 0xff)
1001 #define RELAX_USE_SECOND 0x10000
1002 #define RELAX_SECOND_LONGER 0x20000
1003 #define RELAX_NOMACRO 0x40000
1004 #define RELAX_DELAY_SLOT 0x80000
1005 #define RELAX_DELAY_SLOT_16BIT 0x100000
1006 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1007 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1009 /* Branch without likely bit. If label is out of range, we turn:
1011 beq reg1, reg2, label
1021 with the following opcode replacements:
1028 bltzal <-> bgezal (with jal label instead of j label)
1030 Even though keeping the delay slot instruction in the delay slot of
1031 the branch would be more efficient, it would be very tricky to do
1032 correctly, because we'd have to introduce a variable frag *after*
1033 the delay slot instruction, and expand that instead. Let's do it
1034 the easy way for now, even if the branch-not-taken case now costs
1035 one additional instruction. Out-of-range branches are not supposed
1036 to be common, anyway.
1038 Branch likely. If label is out of range, we turn:
1040 beql reg1, reg2, label
1041 delay slot (annulled if branch not taken)
1050 delay slot (executed only if branch taken)
1053 It would be possible to generate a shorter sequence by losing the
1054 likely bit, generating something like:
1059 delay slot (executed only if branch taken)
1071 bltzall -> bgezal (with jal label instead of j label)
1072 bgezall -> bltzal (ditto)
1075 but it's not clear that it would actually improve performance. */
1076 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1077 ((relax_substateT) \
1080 | ((toofar) ? 0x20 : 0) \
1081 | ((link) ? 0x40 : 0) \
1082 | ((likely) ? 0x80 : 0) \
1083 | ((uncond) ? 0x100 : 0)))
1084 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1085 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1086 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1087 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1088 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1089 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1091 /* For mips16 code, we use an entirely different form of relaxation.
1092 mips16 supports two versions of most instructions which take
1093 immediate values: a small one which takes some small value, and a
1094 larger one which takes a 16 bit value. Since branches also follow
1095 this pattern, relaxing these values is required.
1097 We can assemble both mips16 and normal MIPS code in a single
1098 object. Therefore, we need to support this type of relaxation at
1099 the same time that we support the relaxation described above. We
1100 use the high bit of the subtype field to distinguish these cases.
1102 The information we store for this type of relaxation is the
1103 argument code found in the opcode file for this relocation, whether
1104 the user explicitly requested a small or extended form, and whether
1105 the relocation is in a jump or jal delay slot. That tells us the
1106 size of the value, and how it should be stored. We also store
1107 whether the fragment is considered to be extended or not. We also
1108 store whether this is known to be a branch to a different section,
1109 whether we have tried to relax this frag yet, and whether we have
1110 ever extended a PC relative fragment because of a shift count. */
1111 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1114 | ((small) ? 0x100 : 0) \
1115 | ((ext) ? 0x200 : 0) \
1116 | ((dslot) ? 0x400 : 0) \
1117 | ((jal_dslot) ? 0x800 : 0))
1118 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1119 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1120 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1121 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1122 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1123 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1124 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1125 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1126 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1127 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1128 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1129 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1131 /* For microMIPS code, we use relaxation similar to one we use for
1132 MIPS16 code. Some instructions that take immediate values support
1133 two encodings: a small one which takes some small value, and a
1134 larger one which takes a 16 bit value. As some branches also follow
1135 this pattern, relaxing these values is required.
1137 We can assemble both microMIPS and normal MIPS code in a single
1138 object. Therefore, we need to support this type of relaxation at
1139 the same time that we support the relaxation described above. We
1140 use one of the high bits of the subtype field to distinguish these
1143 The information we store for this type of relaxation is the argument
1144 code found in the opcode file for this relocation, the register
1145 selected as the assembler temporary, whether the branch is
1146 unconditional, whether it is compact, whether it stores the link
1147 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1148 branches to a sequence of instructions is enabled, and whether the
1149 displacement of a branch is too large to fit as an immediate argument
1150 of a 16-bit and a 32-bit branch, respectively. */
1151 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1152 relax32, toofar16, toofar32) \
1155 | (((at) & 0x1f) << 8) \
1156 | ((uncond) ? 0x2000 : 0) \
1157 | ((compact) ? 0x4000 : 0) \
1158 | ((link) ? 0x8000 : 0) \
1159 | ((relax32) ? 0x10000 : 0) \
1160 | ((toofar16) ? 0x20000 : 0) \
1161 | ((toofar32) ? 0x40000 : 0))
1162 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1163 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1164 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1165 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1166 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1167 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1168 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1170 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1171 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1172 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1173 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1174 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1175 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1177 /* Sign-extend 16-bit value X. */
1178 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1180 /* Is the given value a sign-extended 32-bit value? */
1181 #define IS_SEXT_32BIT_NUM(x) \
1182 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1183 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1185 /* Is the given value a sign-extended 16-bit value? */
1186 #define IS_SEXT_16BIT_NUM(x) \
1187 (((x) &~ (offsetT) 0x7fff) == 0 \
1188 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1190 /* Is the given value a sign-extended 12-bit value? */
1191 #define IS_SEXT_12BIT_NUM(x) \
1192 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1194 /* Is the given value a sign-extended 9-bit value? */
1195 #define IS_SEXT_9BIT_NUM(x) \
1196 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1198 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1199 #define IS_ZEXT_32BIT_NUM(x) \
1200 (((x) &~ (offsetT) 0xffffffff) == 0 \
1201 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1203 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1204 VALUE << SHIFT. VALUE is evaluated exactly once. */
1205 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1206 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1207 | (((VALUE) & (MASK)) << (SHIFT)))
1209 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1211 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1212 (((STRUCT) >> (SHIFT)) & (MASK))
1214 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1215 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1217 include/opcode/mips.h specifies operand fields using the macros
1218 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1219 with "MIPS16OP" instead of "OP". */
1220 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1223 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1224 OP_MASK_##FIELD, OP_SH_##FIELD); \
1226 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1227 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1229 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1233 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1234 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1236 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1237 : EXTRACT_BITS ((INSN).insn_opcode, \
1238 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1239 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1240 EXTRACT_BITS ((INSN).insn_opcode, \
1241 MIPS16OP_MASK_##FIELD, \
1242 MIPS16OP_SH_##FIELD)
1244 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1245 #define MIPS16_EXTEND (0xf000U << 16)
1247 /* Whether or not we are emitting a branch-likely macro. */
1248 static bfd_boolean emit_branch_likely_macro = FALSE;
1250 /* Global variables used when generating relaxable macros. See the
1251 comment above RELAX_ENCODE for more details about how relaxation
1254 /* 0 if we're not emitting a relaxable macro.
1255 1 if we're emitting the first of the two relaxation alternatives.
1256 2 if we're emitting the second alternative. */
1259 /* The first relaxable fixup in the current frag. (In other words,
1260 the first fixup that refers to relaxable code.) */
1263 /* sizes[0] says how many bytes of the first alternative are stored in
1264 the current frag. Likewise sizes[1] for the second alternative. */
1265 unsigned int sizes[2];
1267 /* The symbol on which the choice of sequence depends. */
1271 /* Global variables used to decide whether a macro needs a warning. */
1273 /* True if the macro is in a branch delay slot. */
1274 bfd_boolean delay_slot_p;
1276 /* Set to the length in bytes required if the macro is in a delay slot
1277 that requires a specific length of instruction, otherwise zero. */
1278 unsigned int delay_slot_length;
1280 /* For relaxable macros, sizes[0] is the length of the first alternative
1281 in bytes and sizes[1] is the length of the second alternative.
1282 For non-relaxable macros, both elements give the length of the
1284 unsigned int sizes[2];
1286 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1287 instruction of the first alternative in bytes and first_insn_sizes[1]
1288 is the length of the first instruction of the second alternative.
1289 For non-relaxable macros, both elements give the length of the first
1290 instruction in bytes.
1292 Set to zero if we haven't yet seen the first instruction. */
1293 unsigned int first_insn_sizes[2];
1295 /* For relaxable macros, insns[0] is the number of instructions for the
1296 first alternative and insns[1] is the number of instructions for the
1299 For non-relaxable macros, both elements give the number of
1300 instructions for the macro. */
1301 unsigned int insns[2];
1303 /* The first variant frag for this macro. */
1305 } mips_macro_warning;
1307 /* Prototypes for static functions. */
1309 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1311 static void append_insn
1312 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1313 bfd_boolean expansionp);
1314 static void mips_no_prev_insn (void);
1315 static void macro_build (expressionS *, const char *, const char *, ...);
1316 static void mips16_macro_build
1317 (expressionS *, const char *, const char *, va_list *);
1318 static void load_register (int, expressionS *, int);
1319 static void macro_start (void);
1320 static void macro_end (void);
1321 static void macro (struct mips_cl_insn * ip);
1322 static void mips16_macro (struct mips_cl_insn * ip);
1323 static void mips_ip (char *str, struct mips_cl_insn * ip);
1324 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1325 static void mips16_immed
1326 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1327 unsigned int, unsigned long *);
1328 static size_t my_getSmallExpression
1329 (expressionS *, bfd_reloc_code_real_type *, char *);
1330 static void my_getExpression (expressionS *, char *);
1331 static void s_align (int);
1332 static void s_change_sec (int);
1333 static void s_change_section (int);
1334 static void s_cons (int);
1335 static void s_float_cons (int);
1336 static void s_mips_globl (int);
1337 static void s_option (int);
1338 static void s_mipsset (int);
1339 static void s_abicalls (int);
1340 static void s_cpload (int);
1341 static void s_cpsetup (int);
1342 static void s_cplocal (int);
1343 static void s_cprestore (int);
1344 static void s_cpreturn (int);
1345 static void s_dtprelword (int);
1346 static void s_dtpreldword (int);
1347 static void s_tprelword (int);
1348 static void s_tpreldword (int);
1349 static void s_gpvalue (int);
1350 static void s_gpword (int);
1351 static void s_gpdword (int);
1352 static void s_ehword (int);
1353 static void s_cpadd (int);
1354 static void s_insn (int);
1355 static void md_obj_begin (void);
1356 static void md_obj_end (void);
1357 static void s_mips_ent (int);
1358 static void s_mips_end (int);
1359 static void s_mips_frame (int);
1360 static void s_mips_mask (int reg_type);
1361 static void s_mips_stab (int);
1362 static void s_mips_weakext (int);
1363 static void s_mips_file (int);
1364 static void s_mips_loc (int);
1365 static bfd_boolean pic_need_relax (symbolS *, asection *);
1366 static int relaxed_branch_length (fragS *, asection *, int);
1367 static int validate_mips_insn (const struct mips_opcode *);
1368 static int validate_micromips_insn (const struct mips_opcode *);
1369 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1370 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1372 /* Table and functions used to map between CPU/ISA names, and
1373 ISA levels, and CPU numbers. */
1375 struct mips_cpu_info
1377 const char *name; /* CPU or ISA name. */
1378 int flags; /* MIPS_CPU_* flags. */
1379 int ase; /* Set of ASEs implemented by the CPU. */
1380 int isa; /* ISA level. */
1381 int cpu; /* CPU number (default CPU if ISA). */
1384 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1386 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1387 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1388 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1392 The following pseudo-ops from the Kane and Heinrich MIPS book
1393 should be defined here, but are currently unsupported: .alias,
1394 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1396 The following pseudo-ops from the Kane and Heinrich MIPS book are
1397 specific to the type of debugging information being generated, and
1398 should be defined by the object format: .aent, .begin, .bend,
1399 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 not MIPS CPU specific, but are also not specific to the object file
1404 format. This file is probably the best place to define them, but
1405 they are not currently supported: .asm0, .endr, .lab, .struct. */
1407 static const pseudo_typeS mips_pseudo_table[] =
1409 /* MIPS specific pseudo-ops. */
1410 {"option", s_option, 0},
1411 {"set", s_mipsset, 0},
1412 {"rdata", s_change_sec, 'r'},
1413 {"sdata", s_change_sec, 's'},
1414 {"livereg", s_ignore, 0},
1415 {"abicalls", s_abicalls, 0},
1416 {"cpload", s_cpload, 0},
1417 {"cpsetup", s_cpsetup, 0},
1418 {"cplocal", s_cplocal, 0},
1419 {"cprestore", s_cprestore, 0},
1420 {"cpreturn", s_cpreturn, 0},
1421 {"dtprelword", s_dtprelword, 0},
1422 {"dtpreldword", s_dtpreldword, 0},
1423 {"tprelword", s_tprelword, 0},
1424 {"tpreldword", s_tpreldword, 0},
1425 {"gpvalue", s_gpvalue, 0},
1426 {"gpword", s_gpword, 0},
1427 {"gpdword", s_gpdword, 0},
1428 {"ehword", s_ehword, 0},
1429 {"cpadd", s_cpadd, 0},
1430 {"insn", s_insn, 0},
1432 /* Relatively generic pseudo-ops that happen to be used on MIPS
1434 {"asciiz", stringer, 8 + 1},
1435 {"bss", s_change_sec, 'b'},
1437 {"half", s_cons, 1},
1438 {"dword", s_cons, 3},
1439 {"weakext", s_mips_weakext, 0},
1440 {"origin", s_org, 0},
1441 {"repeat", s_rept, 0},
1443 /* For MIPS this is non-standard, but we define it for consistency. */
1444 {"sbss", s_change_sec, 'B'},
1446 /* These pseudo-ops are defined in read.c, but must be overridden
1447 here for one reason or another. */
1448 {"align", s_align, 0},
1449 {"byte", s_cons, 0},
1450 {"data", s_change_sec, 'd'},
1451 {"double", s_float_cons, 'd'},
1452 {"float", s_float_cons, 'f'},
1453 {"globl", s_mips_globl, 0},
1454 {"global", s_mips_globl, 0},
1455 {"hword", s_cons, 1},
1457 {"long", s_cons, 2},
1458 {"octa", s_cons, 4},
1459 {"quad", s_cons, 3},
1460 {"section", s_change_section, 0},
1461 {"short", s_cons, 1},
1462 {"single", s_float_cons, 'f'},
1463 {"stabd", s_mips_stab, 'd'},
1464 {"stabn", s_mips_stab, 'n'},
1465 {"stabs", s_mips_stab, 's'},
1466 {"text", s_change_sec, 't'},
1467 {"word", s_cons, 2},
1469 { "extern", ecoff_directive_extern, 0},
1474 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1476 /* These pseudo-ops should be defined by the object file format.
1477 However, a.out doesn't support them, so we have versions here. */
1478 {"aent", s_mips_ent, 1},
1479 {"bgnb", s_ignore, 0},
1480 {"end", s_mips_end, 0},
1481 {"endb", s_ignore, 0},
1482 {"ent", s_mips_ent, 0},
1483 {"file", s_mips_file, 0},
1484 {"fmask", s_mips_mask, 'F'},
1485 {"frame", s_mips_frame, 0},
1486 {"loc", s_mips_loc, 0},
1487 {"mask", s_mips_mask, 'R'},
1488 {"verstamp", s_ignore, 0},
1492 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1493 purpose of the `.dc.a' internal pseudo-op. */
1496 mips_address_bytes (void)
1498 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1501 extern void pop_insert (const pseudo_typeS *);
1504 mips_pop_insert (void)
1506 pop_insert (mips_pseudo_table);
1507 if (! ECOFF_DEBUGGING)
1508 pop_insert (mips_nonecoff_pseudo_table);
1511 /* Symbols labelling the current insn. */
1513 struct insn_label_list
1515 struct insn_label_list *next;
1519 static struct insn_label_list *free_insn_labels;
1520 #define label_list tc_segment_info_data.labels
1522 static void mips_clear_insn_labels (void);
1523 static void mips_mark_labels (void);
1524 static void mips_compressed_mark_labels (void);
1527 mips_clear_insn_labels (void)
1529 register struct insn_label_list **pl;
1530 segment_info_type *si;
1534 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1537 si = seg_info (now_seg);
1538 *pl = si->label_list;
1539 si->label_list = NULL;
1543 /* Mark instruction labels in MIPS16/microMIPS mode. */
1546 mips_mark_labels (void)
1548 if (HAVE_CODE_COMPRESSION)
1549 mips_compressed_mark_labels ();
1552 static char *expr_end;
1554 /* Expressions which appear in instructions. These are set by
1557 static expressionS imm_expr;
1558 static expressionS imm2_expr;
1559 static expressionS offset_expr;
1561 /* Relocs associated with imm_expr and offset_expr. */
1563 static bfd_reloc_code_real_type imm_reloc[3]
1564 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1565 static bfd_reloc_code_real_type offset_reloc[3]
1566 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1568 /* This is set to the resulting size of the instruction to be produced
1569 by mips16_ip if an explicit extension is used or by mips_ip if an
1570 explicit size is supplied. */
1572 static unsigned int forced_insn_length;
1574 /* True if we are assembling an instruction. All dot symbols defined during
1575 this time should be treated as code labels. */
1577 static bfd_boolean mips_assembling_insn;
1580 /* The pdr segment for per procedure frame/regmask info. Not used for
1583 static segT pdr_seg;
1586 /* The default target format to use. */
1588 #if defined (TE_FreeBSD)
1589 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1590 #elif defined (TE_TMIPS)
1591 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1593 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1597 mips_target_format (void)
1599 switch (OUTPUT_FLAVOR)
1601 case bfd_target_ecoff_flavour:
1602 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1603 case bfd_target_coff_flavour:
1605 case bfd_target_elf_flavour:
1607 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1608 return (target_big_endian
1609 ? "elf32-bigmips-vxworks"
1610 : "elf32-littlemips-vxworks");
1612 return (target_big_endian
1613 ? (HAVE_64BIT_OBJECTS
1614 ? ELF_TARGET ("elf64-", "big")
1616 ? ELF_TARGET ("elf32-n", "big")
1617 : ELF_TARGET ("elf32-", "big")))
1618 : (HAVE_64BIT_OBJECTS
1619 ? ELF_TARGET ("elf64-", "little")
1621 ? ELF_TARGET ("elf32-n", "little")
1622 : ELF_TARGET ("elf32-", "little"))));
1629 /* Return the length of a microMIPS instruction in bytes. If bits of
1630 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1631 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1632 major opcode) will require further modifications to the opcode
1635 static inline unsigned int
1636 micromips_insn_length (const struct mips_opcode *mo)
1638 return (mo->mask >> 16) == 0 ? 2 : 4;
1641 /* Return the length of MIPS16 instruction OPCODE. */
1643 static inline unsigned int
1644 mips16_opcode_length (unsigned long opcode)
1646 return (opcode >> 16) == 0 ? 2 : 4;
1649 /* Return the length of instruction INSN. */
1651 static inline unsigned int
1652 insn_length (const struct mips_cl_insn *insn)
1654 if (mips_opts.micromips)
1655 return micromips_insn_length (insn->insn_mo);
1656 else if (mips_opts.mips16)
1657 return mips16_opcode_length (insn->insn_opcode);
1662 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1665 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1670 insn->insn_opcode = mo->match;
1673 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1674 insn->fixp[i] = NULL;
1675 insn->fixed_p = (mips_opts.noreorder > 0);
1676 insn->noreorder_p = (mips_opts.noreorder > 0);
1677 insn->mips16_absolute_jump_p = 0;
1678 insn->complete_p = 0;
1679 insn->cleared_p = 0;
1682 /* Record the current MIPS16/microMIPS mode in now_seg. */
1685 mips_record_compressed_mode (void)
1687 segment_info_type *si;
1689 si = seg_info (now_seg);
1690 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1691 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1692 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1693 si->tc_segment_info_data.micromips = mips_opts.micromips;
1696 /* Read a standard MIPS instruction from BUF. */
1698 static unsigned long
1699 read_insn (char *buf)
1701 if (target_big_endian)
1702 return bfd_getb32 ((bfd_byte *) buf);
1704 return bfd_getl32 ((bfd_byte *) buf);
1707 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1711 write_insn (char *buf, unsigned int insn)
1713 md_number_to_chars (buf, insn, 4);
1717 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1718 has length LENGTH. */
1720 static unsigned long
1721 read_compressed_insn (char *buf, unsigned int length)
1727 for (i = 0; i < length; i += 2)
1730 if (target_big_endian)
1731 insn |= bfd_getb16 ((char *) buf);
1733 insn |= bfd_getl16 ((char *) buf);
1739 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1740 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1743 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1747 for (i = 0; i < length; i += 2)
1748 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1749 return buf + length;
1752 /* Install INSN at the location specified by its "frag" and "where" fields. */
1755 install_insn (const struct mips_cl_insn *insn)
1757 char *f = insn->frag->fr_literal + insn->where;
1758 if (HAVE_CODE_COMPRESSION)
1759 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1761 write_insn (f, insn->insn_opcode);
1762 mips_record_compressed_mode ();
1765 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1766 and install the opcode in the new location. */
1769 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1774 insn->where = where;
1775 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1776 if (insn->fixp[i] != NULL)
1778 insn->fixp[i]->fx_frag = frag;
1779 insn->fixp[i]->fx_where = where;
1781 install_insn (insn);
1784 /* Add INSN to the end of the output. */
1787 add_fixed_insn (struct mips_cl_insn *insn)
1789 char *f = frag_more (insn_length (insn));
1790 move_insn (insn, frag_now, f - frag_now->fr_literal);
1793 /* Start a variant frag and move INSN to the start of the variant part,
1794 marking it as fixed. The other arguments are as for frag_var. */
1797 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1798 relax_substateT subtype, symbolS *symbol, offsetT offset)
1800 frag_grow (max_chars);
1801 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1803 frag_var (rs_machine_dependent, max_chars, var,
1804 subtype, symbol, offset, NULL);
1807 /* Insert N copies of INSN into the history buffer, starting at
1808 position FIRST. Neither FIRST nor N need to be clipped. */
1811 insert_into_history (unsigned int first, unsigned int n,
1812 const struct mips_cl_insn *insn)
1814 if (mips_relax.sequence != 2)
1818 for (i = ARRAY_SIZE (history); i-- > first;)
1820 history[i] = history[i - n];
1826 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1827 the idea is to make it obvious at a glance that each errata is
1831 init_vr4120_conflicts (void)
1833 #define CONFLICT(FIRST, SECOND) \
1834 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1836 /* Errata 21 - [D]DIV[U] after [D]MACC */
1837 CONFLICT (MACC, DIV);
1838 CONFLICT (DMACC, DIV);
1840 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1841 CONFLICT (DMULT, DMULT);
1842 CONFLICT (DMULT, DMACC);
1843 CONFLICT (DMACC, DMULT);
1844 CONFLICT (DMACC, DMACC);
1846 /* Errata 24 - MT{LO,HI} after [D]MACC */
1847 CONFLICT (MACC, MTHILO);
1848 CONFLICT (DMACC, MTHILO);
1850 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1851 instruction is executed immediately after a MACC or DMACC
1852 instruction, the result of [either instruction] is incorrect." */
1853 CONFLICT (MACC, MULT);
1854 CONFLICT (MACC, DMULT);
1855 CONFLICT (DMACC, MULT);
1856 CONFLICT (DMACC, DMULT);
1858 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1859 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1860 DDIV or DDIVU instruction, the result of the MACC or
1861 DMACC instruction is incorrect.". */
1862 CONFLICT (DMULT, MACC);
1863 CONFLICT (DMULT, DMACC);
1864 CONFLICT (DIV, MACC);
1865 CONFLICT (DIV, DMACC);
1875 #define RTYPE_MASK 0x1ff00
1876 #define RTYPE_NUM 0x00100
1877 #define RTYPE_FPU 0x00200
1878 #define RTYPE_FCC 0x00400
1879 #define RTYPE_VEC 0x00800
1880 #define RTYPE_GP 0x01000
1881 #define RTYPE_CP0 0x02000
1882 #define RTYPE_PC 0x04000
1883 #define RTYPE_ACC 0x08000
1884 #define RTYPE_CCC 0x10000
1885 #define RNUM_MASK 0x000ff
1886 #define RWARN 0x80000
1888 #define GENERIC_REGISTER_NUMBERS \
1889 {"$0", RTYPE_NUM | 0}, \
1890 {"$1", RTYPE_NUM | 1}, \
1891 {"$2", RTYPE_NUM | 2}, \
1892 {"$3", RTYPE_NUM | 3}, \
1893 {"$4", RTYPE_NUM | 4}, \
1894 {"$5", RTYPE_NUM | 5}, \
1895 {"$6", RTYPE_NUM | 6}, \
1896 {"$7", RTYPE_NUM | 7}, \
1897 {"$8", RTYPE_NUM | 8}, \
1898 {"$9", RTYPE_NUM | 9}, \
1899 {"$10", RTYPE_NUM | 10}, \
1900 {"$11", RTYPE_NUM | 11}, \
1901 {"$12", RTYPE_NUM | 12}, \
1902 {"$13", RTYPE_NUM | 13}, \
1903 {"$14", RTYPE_NUM | 14}, \
1904 {"$15", RTYPE_NUM | 15}, \
1905 {"$16", RTYPE_NUM | 16}, \
1906 {"$17", RTYPE_NUM | 17}, \
1907 {"$18", RTYPE_NUM | 18}, \
1908 {"$19", RTYPE_NUM | 19}, \
1909 {"$20", RTYPE_NUM | 20}, \
1910 {"$21", RTYPE_NUM | 21}, \
1911 {"$22", RTYPE_NUM | 22}, \
1912 {"$23", RTYPE_NUM | 23}, \
1913 {"$24", RTYPE_NUM | 24}, \
1914 {"$25", RTYPE_NUM | 25}, \
1915 {"$26", RTYPE_NUM | 26}, \
1916 {"$27", RTYPE_NUM | 27}, \
1917 {"$28", RTYPE_NUM | 28}, \
1918 {"$29", RTYPE_NUM | 29}, \
1919 {"$30", RTYPE_NUM | 30}, \
1920 {"$31", RTYPE_NUM | 31}
1922 #define FPU_REGISTER_NAMES \
1923 {"$f0", RTYPE_FPU | 0}, \
1924 {"$f1", RTYPE_FPU | 1}, \
1925 {"$f2", RTYPE_FPU | 2}, \
1926 {"$f3", RTYPE_FPU | 3}, \
1927 {"$f4", RTYPE_FPU | 4}, \
1928 {"$f5", RTYPE_FPU | 5}, \
1929 {"$f6", RTYPE_FPU | 6}, \
1930 {"$f7", RTYPE_FPU | 7}, \
1931 {"$f8", RTYPE_FPU | 8}, \
1932 {"$f9", RTYPE_FPU | 9}, \
1933 {"$f10", RTYPE_FPU | 10}, \
1934 {"$f11", RTYPE_FPU | 11}, \
1935 {"$f12", RTYPE_FPU | 12}, \
1936 {"$f13", RTYPE_FPU | 13}, \
1937 {"$f14", RTYPE_FPU | 14}, \
1938 {"$f15", RTYPE_FPU | 15}, \
1939 {"$f16", RTYPE_FPU | 16}, \
1940 {"$f17", RTYPE_FPU | 17}, \
1941 {"$f18", RTYPE_FPU | 18}, \
1942 {"$f19", RTYPE_FPU | 19}, \
1943 {"$f20", RTYPE_FPU | 20}, \
1944 {"$f21", RTYPE_FPU | 21}, \
1945 {"$f22", RTYPE_FPU | 22}, \
1946 {"$f23", RTYPE_FPU | 23}, \
1947 {"$f24", RTYPE_FPU | 24}, \
1948 {"$f25", RTYPE_FPU | 25}, \
1949 {"$f26", RTYPE_FPU | 26}, \
1950 {"$f27", RTYPE_FPU | 27}, \
1951 {"$f28", RTYPE_FPU | 28}, \
1952 {"$f29", RTYPE_FPU | 29}, \
1953 {"$f30", RTYPE_FPU | 30}, \
1954 {"$f31", RTYPE_FPU | 31}
1956 #define FPU_CONDITION_CODE_NAMES \
1957 {"$fcc0", RTYPE_FCC | 0}, \
1958 {"$fcc1", RTYPE_FCC | 1}, \
1959 {"$fcc2", RTYPE_FCC | 2}, \
1960 {"$fcc3", RTYPE_FCC | 3}, \
1961 {"$fcc4", RTYPE_FCC | 4}, \
1962 {"$fcc5", RTYPE_FCC | 5}, \
1963 {"$fcc6", RTYPE_FCC | 6}, \
1964 {"$fcc7", RTYPE_FCC | 7}
1966 #define COPROC_CONDITION_CODE_NAMES \
1967 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1968 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1969 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1970 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1971 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1972 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1973 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1974 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1976 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1977 {"$a4", RTYPE_GP | 8}, \
1978 {"$a5", RTYPE_GP | 9}, \
1979 {"$a6", RTYPE_GP | 10}, \
1980 {"$a7", RTYPE_GP | 11}, \
1981 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1982 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1983 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1984 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1985 {"$t0", RTYPE_GP | 12}, \
1986 {"$t1", RTYPE_GP | 13}, \
1987 {"$t2", RTYPE_GP | 14}, \
1988 {"$t3", RTYPE_GP | 15}
1990 #define O32_SYMBOLIC_REGISTER_NAMES \
1991 {"$t0", RTYPE_GP | 8}, \
1992 {"$t1", RTYPE_GP | 9}, \
1993 {"$t2", RTYPE_GP | 10}, \
1994 {"$t3", RTYPE_GP | 11}, \
1995 {"$t4", RTYPE_GP | 12}, \
1996 {"$t5", RTYPE_GP | 13}, \
1997 {"$t6", RTYPE_GP | 14}, \
1998 {"$t7", RTYPE_GP | 15}, \
1999 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2000 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2001 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2002 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2004 /* Remaining symbolic register names */
2005 #define SYMBOLIC_REGISTER_NAMES \
2006 {"$zero", RTYPE_GP | 0}, \
2007 {"$at", RTYPE_GP | 1}, \
2008 {"$AT", RTYPE_GP | 1}, \
2009 {"$v0", RTYPE_GP | 2}, \
2010 {"$v1", RTYPE_GP | 3}, \
2011 {"$a0", RTYPE_GP | 4}, \
2012 {"$a1", RTYPE_GP | 5}, \
2013 {"$a2", RTYPE_GP | 6}, \
2014 {"$a3", RTYPE_GP | 7}, \
2015 {"$s0", RTYPE_GP | 16}, \
2016 {"$s1", RTYPE_GP | 17}, \
2017 {"$s2", RTYPE_GP | 18}, \
2018 {"$s3", RTYPE_GP | 19}, \
2019 {"$s4", RTYPE_GP | 20}, \
2020 {"$s5", RTYPE_GP | 21}, \
2021 {"$s6", RTYPE_GP | 22}, \
2022 {"$s7", RTYPE_GP | 23}, \
2023 {"$t8", RTYPE_GP | 24}, \
2024 {"$t9", RTYPE_GP | 25}, \
2025 {"$k0", RTYPE_GP | 26}, \
2026 {"$kt0", RTYPE_GP | 26}, \
2027 {"$k1", RTYPE_GP | 27}, \
2028 {"$kt1", RTYPE_GP | 27}, \
2029 {"$gp", RTYPE_GP | 28}, \
2030 {"$sp", RTYPE_GP | 29}, \
2031 {"$s8", RTYPE_GP | 30}, \
2032 {"$fp", RTYPE_GP | 30}, \
2033 {"$ra", RTYPE_GP | 31}
2035 #define MIPS16_SPECIAL_REGISTER_NAMES \
2036 {"$pc", RTYPE_PC | 0}
2038 #define MDMX_VECTOR_REGISTER_NAMES \
2039 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2040 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2041 {"$v2", RTYPE_VEC | 2}, \
2042 {"$v3", RTYPE_VEC | 3}, \
2043 {"$v4", RTYPE_VEC | 4}, \
2044 {"$v5", RTYPE_VEC | 5}, \
2045 {"$v6", RTYPE_VEC | 6}, \
2046 {"$v7", RTYPE_VEC | 7}, \
2047 {"$v8", RTYPE_VEC | 8}, \
2048 {"$v9", RTYPE_VEC | 9}, \
2049 {"$v10", RTYPE_VEC | 10}, \
2050 {"$v11", RTYPE_VEC | 11}, \
2051 {"$v12", RTYPE_VEC | 12}, \
2052 {"$v13", RTYPE_VEC | 13}, \
2053 {"$v14", RTYPE_VEC | 14}, \
2054 {"$v15", RTYPE_VEC | 15}, \
2055 {"$v16", RTYPE_VEC | 16}, \
2056 {"$v17", RTYPE_VEC | 17}, \
2057 {"$v18", RTYPE_VEC | 18}, \
2058 {"$v19", RTYPE_VEC | 19}, \
2059 {"$v20", RTYPE_VEC | 20}, \
2060 {"$v21", RTYPE_VEC | 21}, \
2061 {"$v22", RTYPE_VEC | 22}, \
2062 {"$v23", RTYPE_VEC | 23}, \
2063 {"$v24", RTYPE_VEC | 24}, \
2064 {"$v25", RTYPE_VEC | 25}, \
2065 {"$v26", RTYPE_VEC | 26}, \
2066 {"$v27", RTYPE_VEC | 27}, \
2067 {"$v28", RTYPE_VEC | 28}, \
2068 {"$v29", RTYPE_VEC | 29}, \
2069 {"$v30", RTYPE_VEC | 30}, \
2070 {"$v31", RTYPE_VEC | 31}
2072 #define MIPS_DSP_ACCUMULATOR_NAMES \
2073 {"$ac0", RTYPE_ACC | 0}, \
2074 {"$ac1", RTYPE_ACC | 1}, \
2075 {"$ac2", RTYPE_ACC | 2}, \
2076 {"$ac3", RTYPE_ACC | 3}
2078 static const struct regname reg_names[] = {
2079 GENERIC_REGISTER_NUMBERS,
2081 FPU_CONDITION_CODE_NAMES,
2082 COPROC_CONDITION_CODE_NAMES,
2084 /* The $txx registers depends on the abi,
2085 these will be added later into the symbol table from
2086 one of the tables below once mips_abi is set after
2087 parsing of arguments from the command line. */
2088 SYMBOLIC_REGISTER_NAMES,
2090 MIPS16_SPECIAL_REGISTER_NAMES,
2091 MDMX_VECTOR_REGISTER_NAMES,
2092 MIPS_DSP_ACCUMULATOR_NAMES,
2096 static const struct regname reg_names_o32[] = {
2097 O32_SYMBOLIC_REGISTER_NAMES,
2101 static const struct regname reg_names_n32n64[] = {
2102 N32N64_SYMBOLIC_REGISTER_NAMES,
2106 /* Check if S points at a valid register specifier according to TYPES.
2107 If so, then return 1, advance S to consume the specifier and store
2108 the register's number in REGNOP, otherwise return 0. */
2111 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2118 /* Find end of name. */
2120 if (is_name_beginner (*e))
2122 while (is_part_of_name (*e))
2125 /* Terminate name. */
2129 /* Look for a register symbol. */
2130 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2132 int r = S_GET_VALUE (symbolP);
2134 reg = r & RNUM_MASK;
2135 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2136 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2137 reg = (r & RNUM_MASK) - 2;
2139 /* Else see if this is a register defined in an itbl entry. */
2140 else if ((types & RTYPE_GP) && itbl_have_entries)
2147 if (itbl_get_reg_val (n, &r))
2148 reg = r & RNUM_MASK;
2151 /* Advance to next token if a register was recognised. */
2154 else if (types & RWARN)
2155 as_warn (_("Unrecognized register name `%s'"), *s);
2163 /* Check if S points at a valid register list according to TYPES.
2164 If so, then return 1, advance S to consume the list and store
2165 the registers present on the list as a bitmask of ones in REGLISTP,
2166 otherwise return 0. A valid list comprises a comma-separated
2167 enumeration of valid single registers and/or dash-separated
2168 contiguous register ranges as determined by their numbers.
2170 As a special exception if one of s0-s7 registers is specified as
2171 the range's lower delimiter and s8 (fp) is its upper one, then no
2172 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2173 are selected; they have to be listed separately if needed. */
2176 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2178 unsigned int reglist = 0;
2179 unsigned int lastregno;
2180 bfd_boolean ok = TRUE;
2181 unsigned int regmask;
2182 char *s_endlist = *s;
2186 while (reg_lookup (s, types, ®no))
2192 ok = reg_lookup (s, types, &lastregno);
2193 if (ok && lastregno < regno)
2199 if (lastregno == FP && regno >= S0 && regno <= S7)
2204 regmask = 1 << lastregno;
2205 regmask = (regmask << 1) - 1;
2206 regmask ^= (1 << regno) - 1;
2220 *reglistp = reglist;
2221 return ok && reglist != 0;
2224 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2225 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2228 is_opcode_valid (const struct mips_opcode *mo)
2230 int isa = mips_opts.isa;
2231 int ase = mips_opts.ase;
2234 if ((ase & ASE_DSP) && ISA_SUPPORTS_DSP64_ASE)
2236 if ((ase & ASE_VIRT) && ISA_SUPPORTS_VIRT64_ASE)
2239 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2242 /* Check whether the instruction or macro requires single-precision or
2243 double-precision floating-point support. Note that this information is
2244 stored differently in the opcode table for insns and macros. */
2245 if (mo->pinfo == INSN_MACRO)
2247 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2248 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2252 fp_s = mo->pinfo & FP_S;
2253 fp_d = mo->pinfo & FP_D;
2256 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2259 if (fp_s && mips_opts.soft_float)
2265 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2266 selected ISA and architecture. */
2269 is_opcode_valid_16 (const struct mips_opcode *mo)
2271 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2274 /* Return TRUE if the size of the microMIPS opcode MO matches one
2275 explicitly requested. Always TRUE in the standard MIPS mode. */
2278 is_size_valid (const struct mips_opcode *mo)
2280 if (!mips_opts.micromips)
2283 if (!forced_insn_length)
2285 if (mo->pinfo == INSN_MACRO)
2287 return forced_insn_length == micromips_insn_length (mo);
2290 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2291 of the preceding instruction. Always TRUE in the standard MIPS mode.
2293 We don't accept macros in 16-bit delay slots to avoid a case where
2294 a macro expansion fails because it relies on a preceding 32-bit real
2295 instruction to have matched and does not handle the operands correctly.
2296 The only macros that may expand to 16-bit instructions are JAL that
2297 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2298 and BGT (that likewise cannot be placed in a delay slot) that decay to
2299 a NOP. In all these cases the macros precede any corresponding real
2300 instruction definitions in the opcode table, so they will match in the
2301 second pass where the size of the delay slot is ignored and therefore
2302 produce correct code. */
2305 is_delay_slot_valid (const struct mips_opcode *mo)
2307 if (!mips_opts.micromips)
2310 if (mo->pinfo == INSN_MACRO)
2311 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2312 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2313 && micromips_insn_length (mo) != 4)
2315 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2316 && micromips_insn_length (mo) != 2)
2322 /* This function is called once, at assembler startup time. It should set up
2323 all the tables, etc. that the MD part of the assembler will need. */
2328 const char *retval = NULL;
2332 if (mips_pic != NO_PIC)
2334 if (g_switch_seen && g_switch_value != 0)
2335 as_bad (_("-G may not be used in position-independent code"));
2339 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2340 as_warn (_("Could not set architecture and machine"));
2342 op_hash = hash_new ();
2344 for (i = 0; i < NUMOPCODES;)
2346 const char *name = mips_opcodes[i].name;
2348 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2351 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2352 mips_opcodes[i].name, retval);
2353 /* Probably a memory allocation problem? Give up now. */
2354 as_fatal (_("Broken assembler. No assembly attempted."));
2358 if (mips_opcodes[i].pinfo != INSN_MACRO)
2360 if (!validate_mips_insn (&mips_opcodes[i]))
2362 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2364 create_insn (&nop_insn, mips_opcodes + i);
2365 if (mips_fix_loongson2f_nop)
2366 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2367 nop_insn.fixed_p = 1;
2372 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2375 mips16_op_hash = hash_new ();
2378 while (i < bfd_mips16_num_opcodes)
2380 const char *name = mips16_opcodes[i].name;
2382 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2384 as_fatal (_("internal: can't hash `%s': %s"),
2385 mips16_opcodes[i].name, retval);
2388 if (mips16_opcodes[i].pinfo != INSN_MACRO
2389 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2390 != mips16_opcodes[i].match))
2392 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2393 mips16_opcodes[i].name, mips16_opcodes[i].args);
2396 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2398 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2399 mips16_nop_insn.fixed_p = 1;
2403 while (i < bfd_mips16_num_opcodes
2404 && strcmp (mips16_opcodes[i].name, name) == 0);
2407 micromips_op_hash = hash_new ();
2410 while (i < bfd_micromips_num_opcodes)
2412 const char *name = micromips_opcodes[i].name;
2414 retval = hash_insert (micromips_op_hash, name,
2415 (void *) µmips_opcodes[i]);
2417 as_fatal (_("internal: can't hash `%s': %s"),
2418 micromips_opcodes[i].name, retval);
2420 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2422 struct mips_cl_insn *micromips_nop_insn;
2424 if (!validate_micromips_insn (µmips_opcodes[i]))
2427 if (micromips_insn_length (micromips_opcodes + i) == 2)
2428 micromips_nop_insn = µmips_nop16_insn;
2429 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2430 micromips_nop_insn = µmips_nop32_insn;
2434 if (micromips_nop_insn->insn_mo == NULL
2435 && strcmp (name, "nop") == 0)
2437 create_insn (micromips_nop_insn, micromips_opcodes + i);
2438 micromips_nop_insn->fixed_p = 1;
2441 while (++i < bfd_micromips_num_opcodes
2442 && strcmp (micromips_opcodes[i].name, name) == 0);
2446 as_fatal (_("Broken assembler. No assembly attempted."));
2448 /* We add all the general register names to the symbol table. This
2449 helps us detect invalid uses of them. */
2450 for (i = 0; reg_names[i].name; i++)
2451 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2452 reg_names[i].num, /* & RNUM_MASK, */
2453 &zero_address_frag));
2455 for (i = 0; reg_names_n32n64[i].name; i++)
2456 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2457 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2458 &zero_address_frag));
2460 for (i = 0; reg_names_o32[i].name; i++)
2461 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2462 reg_names_o32[i].num, /* & RNUM_MASK, */
2463 &zero_address_frag));
2465 mips_no_prev_insn ();
2468 mips_cprmask[0] = 0;
2469 mips_cprmask[1] = 0;
2470 mips_cprmask[2] = 0;
2471 mips_cprmask[3] = 0;
2473 /* set the default alignment for the text section (2**2) */
2474 record_alignment (text_section, 2);
2476 bfd_set_gp_size (stdoutput, g_switch_value);
2481 /* On a native system other than VxWorks, sections must be aligned
2482 to 16 byte boundaries. When configured for an embedded ELF
2483 target, we don't bother. */
2484 if (strncmp (TARGET_OS, "elf", 3) != 0
2485 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2487 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2488 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2489 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2492 /* Create a .reginfo section for register masks and a .mdebug
2493 section for debugging information. */
2501 subseg = now_subseg;
2503 /* The ABI says this section should be loaded so that the
2504 running program can access it. However, we don't load it
2505 if we are configured for an embedded target */
2506 flags = SEC_READONLY | SEC_DATA;
2507 if (strncmp (TARGET_OS, "elf", 3) != 0)
2508 flags |= SEC_ALLOC | SEC_LOAD;
2510 if (mips_abi != N64_ABI)
2512 sec = subseg_new (".reginfo", (subsegT) 0);
2514 bfd_set_section_flags (stdoutput, sec, flags);
2515 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2517 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2521 /* The 64-bit ABI uses a .MIPS.options section rather than
2522 .reginfo section. */
2523 sec = subseg_new (".MIPS.options", (subsegT) 0);
2524 bfd_set_section_flags (stdoutput, sec, flags);
2525 bfd_set_section_alignment (stdoutput, sec, 3);
2527 /* Set up the option header. */
2529 Elf_Internal_Options opthdr;
2532 opthdr.kind = ODK_REGINFO;
2533 opthdr.size = (sizeof (Elf_External_Options)
2534 + sizeof (Elf64_External_RegInfo));
2537 f = frag_more (sizeof (Elf_External_Options));
2538 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2539 (Elf_External_Options *) f);
2541 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2545 if (ECOFF_DEBUGGING)
2547 sec = subseg_new (".mdebug", (subsegT) 0);
2548 (void) bfd_set_section_flags (stdoutput, sec,
2549 SEC_HAS_CONTENTS | SEC_READONLY);
2550 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2552 else if (mips_flag_pdr)
2554 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2555 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2556 SEC_READONLY | SEC_RELOC
2558 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2561 subseg_set (seg, subseg);
2564 #endif /* OBJ_ELF */
2566 if (! ECOFF_DEBUGGING)
2569 if (mips_fix_vr4120)
2570 init_vr4120_conflicts ();
2576 mips_emit_delays ();
2577 if (! ECOFF_DEBUGGING)
2582 md_assemble (char *str)
2584 struct mips_cl_insn insn;
2585 bfd_reloc_code_real_type unused_reloc[3]
2586 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2588 imm_expr.X_op = O_absent;
2589 imm2_expr.X_op = O_absent;
2590 offset_expr.X_op = O_absent;
2591 imm_reloc[0] = BFD_RELOC_UNUSED;
2592 imm_reloc[1] = BFD_RELOC_UNUSED;
2593 imm_reloc[2] = BFD_RELOC_UNUSED;
2594 offset_reloc[0] = BFD_RELOC_UNUSED;
2595 offset_reloc[1] = BFD_RELOC_UNUSED;
2596 offset_reloc[2] = BFD_RELOC_UNUSED;
2598 mips_mark_labels ();
2599 mips_assembling_insn = TRUE;
2601 if (mips_opts.mips16)
2602 mips16_ip (str, &insn);
2605 mips_ip (str, &insn);
2606 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2607 str, insn.insn_opcode));
2611 as_bad ("%s `%s'", insn_error, str);
2612 else if (insn.insn_mo->pinfo == INSN_MACRO)
2615 if (mips_opts.mips16)
2616 mips16_macro (&insn);
2623 if (imm_expr.X_op != O_absent)
2624 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2625 else if (offset_expr.X_op != O_absent)
2626 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2628 append_insn (&insn, NULL, unused_reloc, FALSE);
2631 mips_assembling_insn = FALSE;
2634 /* Convenience functions for abstracting away the differences between
2635 MIPS16 and non-MIPS16 relocations. */
2637 static inline bfd_boolean
2638 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2642 case BFD_RELOC_MIPS16_JMP:
2643 case BFD_RELOC_MIPS16_GPREL:
2644 case BFD_RELOC_MIPS16_GOT16:
2645 case BFD_RELOC_MIPS16_CALL16:
2646 case BFD_RELOC_MIPS16_HI16_S:
2647 case BFD_RELOC_MIPS16_HI16:
2648 case BFD_RELOC_MIPS16_LO16:
2656 static inline bfd_boolean
2657 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2661 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2662 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2663 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2664 case BFD_RELOC_MICROMIPS_GPREL16:
2665 case BFD_RELOC_MICROMIPS_JMP:
2666 case BFD_RELOC_MICROMIPS_HI16:
2667 case BFD_RELOC_MICROMIPS_HI16_S:
2668 case BFD_RELOC_MICROMIPS_LO16:
2669 case BFD_RELOC_MICROMIPS_LITERAL:
2670 case BFD_RELOC_MICROMIPS_GOT16:
2671 case BFD_RELOC_MICROMIPS_CALL16:
2672 case BFD_RELOC_MICROMIPS_GOT_HI16:
2673 case BFD_RELOC_MICROMIPS_GOT_LO16:
2674 case BFD_RELOC_MICROMIPS_CALL_HI16:
2675 case BFD_RELOC_MICROMIPS_CALL_LO16:
2676 case BFD_RELOC_MICROMIPS_SUB:
2677 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2678 case BFD_RELOC_MICROMIPS_GOT_OFST:
2679 case BFD_RELOC_MICROMIPS_GOT_DISP:
2680 case BFD_RELOC_MICROMIPS_HIGHEST:
2681 case BFD_RELOC_MICROMIPS_HIGHER:
2682 case BFD_RELOC_MICROMIPS_SCN_DISP:
2683 case BFD_RELOC_MICROMIPS_JALR:
2691 static inline bfd_boolean
2692 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2694 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2697 static inline bfd_boolean
2698 got16_reloc_p (bfd_reloc_code_real_type reloc)
2700 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2701 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2704 static inline bfd_boolean
2705 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2707 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2708 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2711 static inline bfd_boolean
2712 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2714 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2715 || reloc == BFD_RELOC_MICROMIPS_LO16);
2718 static inline bfd_boolean
2719 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2721 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2724 /* Return true if RELOC is a PC-relative relocation that does not have
2725 full address range. */
2727 static inline bfd_boolean
2728 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
2732 case BFD_RELOC_16_PCREL_S2:
2733 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2734 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2735 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2738 case BFD_RELOC_32_PCREL:
2739 return HAVE_64BIT_ADDRESSES;
2746 /* Return true if the given relocation might need a matching %lo().
2747 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2748 need a matching %lo() when applied to local symbols. */
2750 static inline bfd_boolean
2751 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2753 return (HAVE_IN_PLACE_ADDENDS
2754 && (hi16_reloc_p (reloc)
2755 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2756 all GOT16 relocations evaluate to "G". */
2757 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2760 /* Return the type of %lo() reloc needed by RELOC, given that
2761 reloc_needs_lo_p. */
2763 static inline bfd_reloc_code_real_type
2764 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2766 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2767 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2771 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2774 static inline bfd_boolean
2775 fixup_has_matching_lo_p (fixS *fixp)
2777 return (fixp->fx_next != NULL
2778 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2779 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2780 && fixp->fx_offset == fixp->fx_next->fx_offset);
2783 /* This function returns true if modifying a register requires a
2787 reg_needs_delay (unsigned int reg)
2789 unsigned long prev_pinfo;
2791 prev_pinfo = history[0].insn_mo->pinfo;
2792 if (! mips_opts.noreorder
2793 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2794 && ! gpr_interlocks)
2795 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2796 && ! cop_interlocks)))
2798 /* A load from a coprocessor or from memory. All load delays
2799 delay the use of general register rt for one instruction. */
2800 /* Itbl support may require additional care here. */
2801 know (prev_pinfo & INSN_WRITE_GPR_T);
2802 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2809 /* Move all labels in LABELS to the current insertion point. TEXT_P
2810 says whether the labels refer to text or data. */
2813 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2815 struct insn_label_list *l;
2818 for (l = labels; l != NULL; l = l->next)
2820 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2821 symbol_set_frag (l->label, frag_now);
2822 val = (valueT) frag_now_fix ();
2823 /* MIPS16/microMIPS text labels are stored as odd. */
2824 if (text_p && HAVE_CODE_COMPRESSION)
2826 S_SET_VALUE (l->label, val);
2830 /* Move all labels in insn_labels to the current insertion point
2831 and treat them as text labels. */
2834 mips_move_text_labels (void)
2836 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2840 s_is_linkonce (symbolS *sym, segT from_seg)
2842 bfd_boolean linkonce = FALSE;
2843 segT symseg = S_GET_SEGMENT (sym);
2845 if (symseg != from_seg && !S_IS_LOCAL (sym))
2847 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2850 /* The GNU toolchain uses an extension for ELF: a section
2851 beginning with the magic string .gnu.linkonce is a
2852 linkonce section. */
2853 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2854 sizeof ".gnu.linkonce" - 1) == 0)
2861 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2862 linker to handle them specially, such as generating jalx instructions
2863 when needed. We also make them odd for the duration of the assembly,
2864 in order to generate the right sort of code. We will make them even
2865 in the adjust_symtab routine, while leaving them marked. This is
2866 convenient for the debugger and the disassembler. The linker knows
2867 to make them odd again. */
2870 mips_compressed_mark_label (symbolS *label)
2872 gas_assert (HAVE_CODE_COMPRESSION);
2874 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2877 if (mips_opts.mips16)
2878 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2880 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2883 if ((S_GET_VALUE (label) & 1) == 0
2884 /* Don't adjust the address if the label is global or weak, or
2885 in a link-once section, since we'll be emitting symbol reloc
2886 references to it which will be patched up by the linker, and
2887 the final value of the symbol may or may not be MIPS16/microMIPS. */
2888 && !S_IS_WEAK (label)
2889 && !S_IS_EXTERNAL (label)
2890 && !s_is_linkonce (label, now_seg))
2891 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2894 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2897 mips_compressed_mark_labels (void)
2899 struct insn_label_list *l;
2901 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2902 mips_compressed_mark_label (l->label);
2905 /* End the current frag. Make it a variant frag and record the
2909 relax_close_frag (void)
2911 mips_macro_warning.first_frag = frag_now;
2912 frag_var (rs_machine_dependent, 0, 0,
2913 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2914 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2916 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2917 mips_relax.first_fixup = 0;
2920 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2921 See the comment above RELAX_ENCODE for more details. */
2924 relax_start (symbolS *symbol)
2926 gas_assert (mips_relax.sequence == 0);
2927 mips_relax.sequence = 1;
2928 mips_relax.symbol = symbol;
2931 /* Start generating the second version of a relaxable sequence.
2932 See the comment above RELAX_ENCODE for more details. */
2937 gas_assert (mips_relax.sequence == 1);
2938 mips_relax.sequence = 2;
2941 /* End the current relaxable sequence. */
2946 gas_assert (mips_relax.sequence == 2);
2947 relax_close_frag ();
2948 mips_relax.sequence = 0;
2951 /* Return true if IP is a delayed branch or jump. */
2953 static inline bfd_boolean
2954 delayed_branch_p (const struct mips_cl_insn *ip)
2956 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2957 | INSN_COND_BRANCH_DELAY
2958 | INSN_COND_BRANCH_LIKELY)) != 0;
2961 /* Return true if IP is a compact branch or jump. */
2963 static inline bfd_boolean
2964 compact_branch_p (const struct mips_cl_insn *ip)
2966 if (mips_opts.mips16)
2967 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2968 | MIPS16_INSN_COND_BRANCH)) != 0;
2970 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2971 | INSN2_COND_BRANCH)) != 0;
2974 /* Return true if IP is an unconditional branch or jump. */
2976 static inline bfd_boolean
2977 uncond_branch_p (const struct mips_cl_insn *ip)
2979 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2980 || (mips_opts.mips16
2981 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2982 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2985 /* Return true if IP is a branch-likely instruction. */
2987 static inline bfd_boolean
2988 branch_likely_p (const struct mips_cl_insn *ip)
2990 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2993 /* Return the type of nop that should be used to fill the delay slot
2994 of delayed branch IP. */
2996 static struct mips_cl_insn *
2997 get_delay_slot_nop (const struct mips_cl_insn *ip)
2999 if (mips_opts.micromips
3000 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3001 return µmips_nop32_insn;
3005 /* Return the mask of core registers that IP reads or writes. */
3008 gpr_mod_mask (const struct mips_cl_insn *ip)
3010 unsigned long pinfo2;
3014 pinfo2 = ip->insn_mo->pinfo2;
3015 if (mips_opts.micromips)
3017 if (pinfo2 & INSN2_MOD_GPR_MD)
3018 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3019 if (pinfo2 & INSN2_MOD_GPR_MF)
3020 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3021 if (pinfo2 & INSN2_MOD_SP)
3027 /* Return the mask of core registers that IP reads. */
3030 gpr_read_mask (const struct mips_cl_insn *ip)
3032 unsigned long pinfo, pinfo2;
3035 mask = gpr_mod_mask (ip);
3036 pinfo = ip->insn_mo->pinfo;
3037 pinfo2 = ip->insn_mo->pinfo2;
3038 if (mips_opts.mips16)
3040 if (pinfo & MIPS16_INSN_READ_X)
3041 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3042 if (pinfo & MIPS16_INSN_READ_Y)
3043 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3044 if (pinfo & MIPS16_INSN_READ_T)
3046 if (pinfo & MIPS16_INSN_READ_SP)
3048 if (pinfo & MIPS16_INSN_READ_31)
3050 if (pinfo & MIPS16_INSN_READ_Z)
3051 mask |= 1 << (mips16_to_32_reg_map
3052 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3053 if (pinfo & MIPS16_INSN_READ_GPR_X)
3054 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3058 if (pinfo2 & INSN2_READ_GPR_D)
3059 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3060 if (pinfo & INSN_READ_GPR_T)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3062 if (pinfo & INSN_READ_GPR_S)
3063 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3064 if (pinfo2 & INSN2_READ_GP)
3066 if (pinfo2 & INSN2_READ_GPR_31)
3068 if (pinfo2 & INSN2_READ_GPR_Z)
3069 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3071 if (mips_opts.micromips)
3073 if (pinfo2 & INSN2_READ_GPR_MC)
3074 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3075 if (pinfo2 & INSN2_READ_GPR_ME)
3076 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3077 if (pinfo2 & INSN2_READ_GPR_MG)
3078 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3079 if (pinfo2 & INSN2_READ_GPR_MJ)
3080 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3081 if (pinfo2 & INSN2_READ_GPR_MMN)
3083 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3084 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3086 if (pinfo2 & INSN2_READ_GPR_MP)
3087 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3088 if (pinfo2 & INSN2_READ_GPR_MQ)
3089 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3091 /* Don't include register 0. */
3095 /* Return the mask of core registers that IP writes. */
3098 gpr_write_mask (const struct mips_cl_insn *ip)
3100 unsigned long pinfo, pinfo2;
3103 mask = gpr_mod_mask (ip);
3104 pinfo = ip->insn_mo->pinfo;
3105 pinfo2 = ip->insn_mo->pinfo2;
3106 if (mips_opts.mips16)
3108 if (pinfo & MIPS16_INSN_WRITE_X)
3109 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3110 if (pinfo & MIPS16_INSN_WRITE_Y)
3111 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3112 if (pinfo & MIPS16_INSN_WRITE_Z)
3113 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3114 if (pinfo & MIPS16_INSN_WRITE_T)
3116 if (pinfo & MIPS16_INSN_WRITE_SP)
3118 if (pinfo & MIPS16_INSN_WRITE_31)
3120 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3121 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3125 if (pinfo & INSN_WRITE_GPR_D)
3126 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3127 if (pinfo & INSN_WRITE_GPR_T)
3128 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3129 if (pinfo & INSN_WRITE_GPR_S)
3130 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3131 if (pinfo & INSN_WRITE_GPR_31)
3133 if (pinfo2 & INSN2_WRITE_GPR_Z)
3134 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3136 if (mips_opts.micromips)
3138 if (pinfo2 & INSN2_WRITE_GPR_MB)
3139 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3140 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3142 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3143 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3145 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3146 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3147 if (pinfo2 & INSN2_WRITE_GPR_MP)
3148 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3150 /* Don't include register 0. */
3154 /* Return the mask of floating-point registers that IP reads. */
3157 fpr_read_mask (const struct mips_cl_insn *ip)
3159 unsigned long pinfo, pinfo2;
3163 pinfo = ip->insn_mo->pinfo;
3164 pinfo2 = ip->insn_mo->pinfo2;
3165 if (!mips_opts.mips16)
3167 if (pinfo2 & INSN2_READ_FPR_D)
3168 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3169 if (pinfo & INSN_READ_FPR_S)
3170 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3171 if (pinfo & INSN_READ_FPR_T)
3172 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3173 if (pinfo & INSN_READ_FPR_R)
3174 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3175 if (pinfo2 & INSN2_READ_FPR_Z)
3176 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3178 /* Conservatively treat all operands to an FP_D instruction are doubles.
3179 (This is overly pessimistic for things like cvt.d.s.) */
3180 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3185 /* Return the mask of floating-point registers that IP writes. */
3188 fpr_write_mask (const struct mips_cl_insn *ip)
3190 unsigned long pinfo, pinfo2;
3194 pinfo = ip->insn_mo->pinfo;
3195 pinfo2 = ip->insn_mo->pinfo2;
3196 if (!mips_opts.mips16)
3198 if (pinfo & INSN_WRITE_FPR_D)
3199 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3200 if (pinfo & INSN_WRITE_FPR_S)
3201 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3202 if (pinfo & INSN_WRITE_FPR_T)
3203 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3204 if (pinfo2 & INSN2_WRITE_FPR_Z)
3205 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3207 /* Conservatively treat all operands to an FP_D instruction are doubles.
3208 (This is overly pessimistic for things like cvt.s.d.) */
3209 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3214 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3215 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3216 by VR4120 errata. */
3219 classify_vr4120_insn (const char *name)
3221 if (strncmp (name, "macc", 4) == 0)
3222 return FIX_VR4120_MACC;
3223 if (strncmp (name, "dmacc", 5) == 0)
3224 return FIX_VR4120_DMACC;
3225 if (strncmp (name, "mult", 4) == 0)
3226 return FIX_VR4120_MULT;
3227 if (strncmp (name, "dmult", 5) == 0)
3228 return FIX_VR4120_DMULT;
3229 if (strstr (name, "div"))
3230 return FIX_VR4120_DIV;
3231 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3232 return FIX_VR4120_MTHILO;
3233 return NUM_FIX_VR4120_CLASSES;
3236 #define INSN_ERET 0x42000018
3237 #define INSN_DERET 0x4200001f
3239 /* Return the number of instructions that must separate INSN1 and INSN2,
3240 where INSN1 is the earlier instruction. Return the worst-case value
3241 for any INSN2 if INSN2 is null. */
3244 insns_between (const struct mips_cl_insn *insn1,
3245 const struct mips_cl_insn *insn2)
3247 unsigned long pinfo1, pinfo2;
3250 /* This function needs to know which pinfo flags are set for INSN2
3251 and which registers INSN2 uses. The former is stored in PINFO2 and
3252 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3253 will have every flag set and INSN2_USES_GPR will always return true. */
3254 pinfo1 = insn1->insn_mo->pinfo;
3255 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3257 #define INSN2_USES_GPR(REG) \
3258 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3260 /* For most targets, write-after-read dependencies on the HI and LO
3261 registers must be separated by at least two instructions. */
3262 if (!hilo_interlocks)
3264 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3266 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3270 /* If we're working around r7000 errata, there must be two instructions
3271 between an mfhi or mflo and any instruction that uses the result. */
3272 if (mips_7000_hilo_fix
3273 && !mips_opts.micromips
3274 && MF_HILO_INSN (pinfo1)
3275 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3278 /* If we're working around 24K errata, one instruction is required
3279 if an ERET or DERET is followed by a branch instruction. */
3280 if (mips_fix_24k && !mips_opts.micromips)
3282 if (insn1->insn_opcode == INSN_ERET
3283 || insn1->insn_opcode == INSN_DERET)
3286 || insn2->insn_opcode == INSN_ERET
3287 || insn2->insn_opcode == INSN_DERET
3288 || delayed_branch_p (insn2))
3293 /* If working around VR4120 errata, check for combinations that need
3294 a single intervening instruction. */
3295 if (mips_fix_vr4120 && !mips_opts.micromips)
3297 unsigned int class1, class2;
3299 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3300 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3304 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3305 if (vr4120_conflicts[class1] & (1 << class2))
3310 if (!HAVE_CODE_COMPRESSION)
3312 /* Check for GPR or coprocessor load delays. All such delays
3313 are on the RT register. */
3314 /* Itbl support may require additional care here. */
3315 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3316 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3318 know (pinfo1 & INSN_WRITE_GPR_T);
3319 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3323 /* Check for generic coprocessor hazards.
3325 This case is not handled very well. There is no special
3326 knowledge of CP0 handling, and the coprocessors other than
3327 the floating point unit are not distinguished at all. */
3328 /* Itbl support may require additional care here. FIXME!
3329 Need to modify this to include knowledge about
3330 user specified delays! */
3331 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3332 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3334 /* Handle cases where INSN1 writes to a known general coprocessor
3335 register. There must be a one instruction delay before INSN2
3336 if INSN2 reads that register, otherwise no delay is needed. */
3337 mask = fpr_write_mask (insn1);
3340 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3345 /* Read-after-write dependencies on the control registers
3346 require a two-instruction gap. */
3347 if ((pinfo1 & INSN_WRITE_COND_CODE)
3348 && (pinfo2 & INSN_READ_COND_CODE))
3351 /* We don't know exactly what INSN1 does. If INSN2 is
3352 also a coprocessor instruction, assume there must be
3353 a one instruction gap. */
3354 if (pinfo2 & INSN_COP)
3359 /* Check for read-after-write dependencies on the coprocessor
3360 control registers in cases where INSN1 does not need a general
3361 coprocessor delay. This means that INSN1 is a floating point
3362 comparison instruction. */
3363 /* Itbl support may require additional care here. */
3364 else if (!cop_interlocks
3365 && (pinfo1 & INSN_WRITE_COND_CODE)
3366 && (pinfo2 & INSN_READ_COND_CODE))
3370 #undef INSN2_USES_GPR
3375 /* Return the number of nops that would be needed to work around the
3376 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3377 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3378 that are contained within the first IGNORE instructions of HIST. */
3381 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3382 const struct mips_cl_insn *insn)
3387 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3388 are not affected by the errata. */
3390 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3391 || strcmp (insn->insn_mo->name, "mtlo") == 0
3392 || strcmp (insn->insn_mo->name, "mthi") == 0))
3395 /* Search for the first MFLO or MFHI. */
3396 for (i = 0; i < MAX_VR4130_NOPS; i++)
3397 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3399 /* Extract the destination register. */
3400 mask = gpr_write_mask (&hist[i]);
3402 /* No nops are needed if INSN reads that register. */
3403 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3406 /* ...or if any of the intervening instructions do. */
3407 for (j = 0; j < i; j++)
3408 if (gpr_read_mask (&hist[j]) & mask)
3412 return MAX_VR4130_NOPS - i;
3417 #define BASE_REG_EQ(INSN1, INSN2) \
3418 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3419 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3421 /* Return the minimum alignment for this store instruction. */
3424 fix_24k_align_to (const struct mips_opcode *mo)
3426 if (strcmp (mo->name, "sh") == 0)
3429 if (strcmp (mo->name, "swc1") == 0
3430 || strcmp (mo->name, "swc2") == 0
3431 || strcmp (mo->name, "sw") == 0
3432 || strcmp (mo->name, "sc") == 0
3433 || strcmp (mo->name, "s.s") == 0)
3436 if (strcmp (mo->name, "sdc1") == 0
3437 || strcmp (mo->name, "sdc2") == 0
3438 || strcmp (mo->name, "s.d") == 0)
3445 struct fix_24k_store_info
3447 /* Immediate offset, if any, for this store instruction. */
3449 /* Alignment required by this store instruction. */
3451 /* True for register offsets. */
3452 int register_offset;
3455 /* Comparison function used by qsort. */
3458 fix_24k_sort (const void *a, const void *b)
3460 const struct fix_24k_store_info *pos1 = a;
3461 const struct fix_24k_store_info *pos2 = b;
3463 return (pos1->off - pos2->off);
3466 /* INSN is a store instruction. Try to record the store information
3467 in STINFO. Return false if the information isn't known. */
3470 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3471 const struct mips_cl_insn *insn)
3473 /* The instruction must have a known offset. */
3474 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3477 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3478 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3482 /* Return the number of nops that would be needed to work around the 24k
3483 "lost data on stores during refill" errata if instruction INSN
3484 immediately followed the 2 instructions described by HIST.
3485 Ignore hazards that are contained within the first IGNORE
3486 instructions of HIST.
3488 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3489 for the data cache refills and store data. The following describes
3490 the scenario where the store data could be lost.
3492 * A data cache miss, due to either a load or a store, causing fill
3493 data to be supplied by the memory subsystem
3494 * The first three doublewords of fill data are returned and written
3496 * A sequence of four stores occurs in consecutive cycles around the
3497 final doubleword of the fill:
3501 * Zero, One or more instructions
3504 The four stores A-D must be to different doublewords of the line that
3505 is being filled. The fourth instruction in the sequence above permits
3506 the fill of the final doubleword to be transferred from the FSB into
3507 the cache. In the sequence above, the stores may be either integer
3508 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3509 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3510 different doublewords on the line. If the floating point unit is
3511 running in 1:2 mode, it is not possible to create the sequence above
3512 using only floating point store instructions.
3514 In this case, the cache line being filled is incorrectly marked
3515 invalid, thereby losing the data from any store to the line that
3516 occurs between the original miss and the completion of the five
3517 cycle sequence shown above.
3519 The workarounds are:
3521 * Run the data cache in write-through mode.
3522 * Insert a non-store instruction between
3523 Store A and Store B or Store B and Store C. */
3526 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3527 const struct mips_cl_insn *insn)
3529 struct fix_24k_store_info pos[3];
3530 int align, i, base_offset;
3535 /* If the previous instruction wasn't a store, there's nothing to
3537 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3540 /* If the instructions after the previous one are unknown, we have
3541 to assume the worst. */
3545 /* Check whether we are dealing with three consecutive stores. */
3546 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3547 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3550 /* If we don't know the relationship between the store addresses,
3551 assume the worst. */
3552 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3553 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3556 if (!fix_24k_record_store_info (&pos[0], insn)
3557 || !fix_24k_record_store_info (&pos[1], &hist[0])
3558 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3561 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3563 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3564 X bytes and such that the base register + X is known to be aligned
3567 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3571 align = pos[0].align_to;
3572 base_offset = pos[0].off;
3573 for (i = 1; i < 3; i++)
3574 if (align < pos[i].align_to)
3576 align = pos[i].align_to;
3577 base_offset = pos[i].off;
3579 for (i = 0; i < 3; i++)
3580 pos[i].off -= base_offset;
3583 pos[0].off &= ~align + 1;
3584 pos[1].off &= ~align + 1;
3585 pos[2].off &= ~align + 1;
3587 /* If any two stores write to the same chunk, they also write to the
3588 same doubleword. The offsets are still sorted at this point. */
3589 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3592 /* A range of at least 9 bytes is needed for the stores to be in
3593 non-overlapping doublewords. */
3594 if (pos[2].off - pos[0].off <= 8)
3597 if (pos[2].off - pos[1].off >= 24
3598 || pos[1].off - pos[0].off >= 24
3599 || pos[2].off - pos[0].off >= 32)
3605 /* Return the number of nops that would be needed if instruction INSN
3606 immediately followed the MAX_NOPS instructions given by HIST,
3607 where HIST[0] is the most recent instruction. Ignore hazards
3608 between INSN and the first IGNORE instructions in HIST.
3610 If INSN is null, return the worse-case number of nops for any
3614 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3615 const struct mips_cl_insn *insn)
3617 int i, nops, tmp_nops;
3620 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3622 tmp_nops = insns_between (hist + i, insn) - i;
3623 if (tmp_nops > nops)
3627 if (mips_fix_vr4130 && !mips_opts.micromips)
3629 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3630 if (tmp_nops > nops)
3634 if (mips_fix_24k && !mips_opts.micromips)
3636 tmp_nops = nops_for_24k (ignore, hist, insn);
3637 if (tmp_nops > nops)
3644 /* The variable arguments provide NUM_INSNS extra instructions that
3645 might be added to HIST. Return the largest number of nops that
3646 would be needed after the extended sequence, ignoring hazards
3647 in the first IGNORE instructions. */
3650 nops_for_sequence (int num_insns, int ignore,
3651 const struct mips_cl_insn *hist, ...)
3654 struct mips_cl_insn buffer[MAX_NOPS];
3655 struct mips_cl_insn *cursor;
3658 va_start (args, hist);
3659 cursor = buffer + num_insns;
3660 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3661 while (cursor > buffer)
3662 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3664 nops = nops_for_insn (ignore, buffer, NULL);
3669 /* Like nops_for_insn, but if INSN is a branch, take into account the
3670 worst-case delay for the branch target. */
3673 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3674 const struct mips_cl_insn *insn)
3678 nops = nops_for_insn (ignore, hist, insn);
3679 if (delayed_branch_p (insn))
3681 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3682 hist, insn, get_delay_slot_nop (insn));
3683 if (tmp_nops > nops)
3686 else if (compact_branch_p (insn))
3688 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3689 if (tmp_nops > nops)
3695 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3698 fix_loongson2f_nop (struct mips_cl_insn * ip)
3700 gas_assert (!HAVE_CODE_COMPRESSION);
3701 if (strcmp (ip->insn_mo->name, "nop") == 0)
3702 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3705 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3706 jr target pc &= 'hffff_ffff_cfff_ffff. */
3709 fix_loongson2f_jump (struct mips_cl_insn * ip)
3711 gas_assert (!HAVE_CODE_COMPRESSION);
3712 if (strcmp (ip->insn_mo->name, "j") == 0
3713 || strcmp (ip->insn_mo->name, "jr") == 0
3714 || strcmp (ip->insn_mo->name, "jalr") == 0)
3722 sreg = EXTRACT_OPERAND (0, RS, *ip);
3723 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3726 ep.X_op = O_constant;
3727 ep.X_add_number = 0xcfff0000;
3728 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3729 ep.X_add_number = 0xffff;
3730 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3731 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3736 fix_loongson2f (struct mips_cl_insn * ip)
3738 if (mips_fix_loongson2f_nop)
3739 fix_loongson2f_nop (ip);
3741 if (mips_fix_loongson2f_jump)
3742 fix_loongson2f_jump (ip);
3745 /* IP is a branch that has a delay slot, and we need to fill it
3746 automatically. Return true if we can do that by swapping IP
3747 with the previous instruction.
3748 ADDRESS_EXPR is an operand of the instruction to be used with
3752 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3753 bfd_reloc_code_real_type *reloc_type)
3755 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3756 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3758 /* -O2 and above is required for this optimization. */
3759 if (mips_optimize < 2)
3762 /* If we have seen .set volatile or .set nomove, don't optimize. */
3763 if (mips_opts.nomove)
3766 /* We can't swap if the previous instruction's position is fixed. */
3767 if (history[0].fixed_p)
3770 /* If the previous previous insn was in a .set noreorder, we can't
3771 swap. Actually, the MIPS assembler will swap in this situation.
3772 However, gcc configured -with-gnu-as will generate code like
3780 in which we can not swap the bne and INSN. If gcc is not configured
3781 -with-gnu-as, it does not output the .set pseudo-ops. */
3782 if (history[1].noreorder_p)
3785 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3786 This means that the previous instruction was a 4-byte one anyhow. */
3787 if (mips_opts.mips16 && history[0].fixp[0])
3790 /* If the branch is itself the target of a branch, we can not swap.
3791 We cheat on this; all we check for is whether there is a label on
3792 this instruction. If there are any branches to anything other than
3793 a label, users must use .set noreorder. */
3794 if (seg_info (now_seg)->label_list)
3797 /* If the previous instruction is in a variant frag other than this
3798 branch's one, we cannot do the swap. This does not apply to
3799 MIPS16 code, which uses variant frags for different purposes. */
3800 if (!mips_opts.mips16
3802 && history[0].frag->fr_type == rs_machine_dependent)
3805 /* We do not swap with instructions that cannot architecturally
3806 be placed in a branch delay slot, such as SYNC or ERET. We
3807 also refrain from swapping with a trap instruction, since it
3808 complicates trap handlers to have the trap instruction be in
3810 prev_pinfo = history[0].insn_mo->pinfo;
3811 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3814 /* Check for conflicts between the branch and the instructions
3815 before the candidate delay slot. */
3816 if (nops_for_insn (0, history + 1, ip) > 0)
3819 /* Check for conflicts between the swapped sequence and the
3820 target of the branch. */
3821 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3824 /* If the branch reads a register that the previous
3825 instruction sets, we can not swap. */
3826 gpr_read = gpr_read_mask (ip);
3827 prev_gpr_write = gpr_write_mask (&history[0]);
3828 if (gpr_read & prev_gpr_write)
3831 /* If the branch writes a register that the previous
3832 instruction sets, we can not swap. */
3833 gpr_write = gpr_write_mask (ip);
3834 if (gpr_write & prev_gpr_write)
3837 /* If the branch writes a register that the previous
3838 instruction reads, we can not swap. */
3839 prev_gpr_read = gpr_read_mask (&history[0]);
3840 if (gpr_write & prev_gpr_read)
3843 /* If one instruction sets a condition code and the
3844 other one uses a condition code, we can not swap. */
3845 pinfo = ip->insn_mo->pinfo;
3846 if ((pinfo & INSN_READ_COND_CODE)
3847 && (prev_pinfo & INSN_WRITE_COND_CODE))
3849 if ((pinfo & INSN_WRITE_COND_CODE)
3850 && (prev_pinfo & INSN_READ_COND_CODE))
3853 /* If the previous instruction uses the PC, we can not swap. */
3854 prev_pinfo2 = history[0].insn_mo->pinfo2;
3855 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3857 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3860 /* If the previous instruction has an incorrect size for a fixed
3861 branch delay slot in microMIPS mode, we cannot swap. */
3862 pinfo2 = ip->insn_mo->pinfo2;
3863 if (mips_opts.micromips
3864 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3865 && insn_length (history) != 2)
3867 if (mips_opts.micromips
3868 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3869 && insn_length (history) != 4)
3872 /* On R5900 short loops need to be fixed by inserting a nop in
3873 the branch delay slots.
3874 A short loop can be terminated too early. */
3875 if (mips_opts.arch == CPU_R5900
3876 /* Check if instruction has a parameter, ignore "j $31". */
3877 && (address_expr != NULL)
3878 /* Parameter must be 16 bit. */
3879 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3880 /* Branch to same segment. */
3881 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3882 /* Branch to same code fragment. */
3883 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3884 /* Can only calculate branch offset if value is known. */
3885 && symbol_constant_p(address_expr->X_add_symbol)
3886 /* Check if branch is really conditional. */
3887 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3888 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3889 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3892 /* Check if loop is shorter than 6 instructions including
3893 branch and delay slot. */
3894 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3901 /* When the loop includes branches or jumps,
3902 it is not a short loop. */
3903 for (i = 0; i < (distance / 4); i++)
3905 if ((history[i].cleared_p)
3906 || delayed_branch_p(&history[i]))
3914 /* Insert nop after branch to fix short loop. */
3923 /* Decide how we should add IP to the instruction stream.
3924 ADDRESS_EXPR is an operand of the instruction to be used with
3927 static enum append_method
3928 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3929 bfd_reloc_code_real_type *reloc_type)
3931 unsigned long pinfo;
3933 /* The relaxed version of a macro sequence must be inherently
3935 if (mips_relax.sequence == 2)
3938 /* We must not dabble with instructions in a ".set norerorder" block. */
3939 if (mips_opts.noreorder)
3942 /* Otherwise, it's our responsibility to fill branch delay slots. */
3943 if (delayed_branch_p (ip))
3945 if (!branch_likely_p (ip)
3946 && can_swap_branch_p (ip, address_expr, reloc_type))
3949 pinfo = ip->insn_mo->pinfo;
3950 if (mips_opts.mips16
3951 && ISA_SUPPORTS_MIPS16E
3952 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3953 return APPEND_ADD_COMPACT;
3955 return APPEND_ADD_WITH_NOP;
3961 /* IP is a MIPS16 instruction whose opcode we have just changed.
3962 Point IP->insn_mo to the new opcode's definition. */
3965 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3967 const struct mips_opcode *mo, *end;
3969 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3970 for (mo = ip->insn_mo; mo < end; mo++)
3971 if ((ip->insn_opcode & mo->mask) == mo->match)
3979 /* For microMIPS macros, we need to generate a local number label
3980 as the target of branches. */
3981 #define MICROMIPS_LABEL_CHAR '\037'
3982 static unsigned long micromips_target_label;
3983 static char micromips_target_name[32];
3986 micromips_label_name (void)
3988 char *p = micromips_target_name;
3989 char symbol_name_temporary[24];
3997 l = micromips_target_label;
3998 #ifdef LOCAL_LABEL_PREFIX
3999 *p++ = LOCAL_LABEL_PREFIX;
4002 *p++ = MICROMIPS_LABEL_CHAR;
4005 symbol_name_temporary[i++] = l % 10 + '0';
4010 *p++ = symbol_name_temporary[--i];
4013 return micromips_target_name;
4017 micromips_label_expr (expressionS *label_expr)
4019 label_expr->X_op = O_symbol;
4020 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4021 label_expr->X_add_number = 0;
4025 micromips_label_inc (void)
4027 micromips_target_label++;
4028 *micromips_target_name = '\0';
4032 micromips_add_label (void)
4036 s = colon (micromips_label_name ());
4037 micromips_label_inc ();
4038 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4040 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4046 /* If assembling microMIPS code, then return the microMIPS reloc
4047 corresponding to the requested one if any. Otherwise return
4048 the reloc unchanged. */
4050 static bfd_reloc_code_real_type
4051 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4053 static const bfd_reloc_code_real_type relocs[][2] =
4055 /* Keep sorted incrementally by the left-hand key. */
4056 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4057 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4058 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4059 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4060 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4061 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4062 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4063 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4064 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4065 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4066 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4067 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4068 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4069 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4070 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4071 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4072 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4073 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4074 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4075 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4076 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4077 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4078 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4079 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4080 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4081 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4082 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4084 bfd_reloc_code_real_type r;
4087 if (!mips_opts.micromips)
4089 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4095 return relocs[i][1];
4100 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4101 Return true on success, storing the resolved value in RESULT. */
4104 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4109 case BFD_RELOC_MIPS_HIGHEST:
4110 case BFD_RELOC_MICROMIPS_HIGHEST:
4111 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4114 case BFD_RELOC_MIPS_HIGHER:
4115 case BFD_RELOC_MICROMIPS_HIGHER:
4116 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4119 case BFD_RELOC_HI16_S:
4120 case BFD_RELOC_MICROMIPS_HI16_S:
4121 case BFD_RELOC_MIPS16_HI16_S:
4122 *result = ((operand + 0x8000) >> 16) & 0xffff;
4125 case BFD_RELOC_HI16:
4126 case BFD_RELOC_MICROMIPS_HI16:
4127 case BFD_RELOC_MIPS16_HI16:
4128 *result = (operand >> 16) & 0xffff;
4131 case BFD_RELOC_LO16:
4132 case BFD_RELOC_MICROMIPS_LO16:
4133 case BFD_RELOC_MIPS16_LO16:
4134 *result = operand & 0xffff;
4137 case BFD_RELOC_UNUSED:
4146 /* Output an instruction. IP is the instruction information.
4147 ADDRESS_EXPR is an operand of the instruction to be used with
4148 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4149 a macro expansion. */
4152 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4153 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4155 unsigned long prev_pinfo2, pinfo;
4156 bfd_boolean relaxed_branch = FALSE;
4157 enum append_method method;
4158 bfd_boolean relax32;
4161 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4162 fix_loongson2f (ip);
4164 file_ase_mips16 |= mips_opts.mips16;
4165 file_ase_micromips |= mips_opts.micromips;
4167 prev_pinfo2 = history[0].insn_mo->pinfo2;
4168 pinfo = ip->insn_mo->pinfo;
4170 if (mips_opts.micromips
4172 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4173 && micromips_insn_length (ip->insn_mo) != 2)
4174 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4175 && micromips_insn_length (ip->insn_mo) != 4)))
4176 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4177 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4179 if (address_expr == NULL)
4181 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4182 && reloc_type[1] == BFD_RELOC_UNUSED
4183 && reloc_type[2] == BFD_RELOC_UNUSED
4184 && address_expr->X_op == O_constant)
4186 switch (*reloc_type)
4188 case BFD_RELOC_MIPS_JMP:
4192 shift = mips_opts.micromips ? 1 : 2;
4193 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4194 as_bad (_("jump to misaligned address (0x%lx)"),
4195 (unsigned long) address_expr->X_add_number);
4196 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4202 case BFD_RELOC_MIPS16_JMP:
4203 if ((address_expr->X_add_number & 3) != 0)
4204 as_bad (_("jump to misaligned address (0x%lx)"),
4205 (unsigned long) address_expr->X_add_number);
4207 (((address_expr->X_add_number & 0x7c0000) << 3)
4208 | ((address_expr->X_add_number & 0xf800000) >> 7)
4209 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4213 case BFD_RELOC_16_PCREL_S2:
4217 shift = mips_opts.micromips ? 1 : 2;
4218 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4219 as_bad (_("branch to misaligned address (0x%lx)"),
4220 (unsigned long) address_expr->X_add_number);
4221 if (!mips_relax_branch)
4223 if ((address_expr->X_add_number + (1 << (shift + 15)))
4224 & ~((1 << (shift + 16)) - 1))
4225 as_bad (_("branch address range overflow (0x%lx)"),
4226 (unsigned long) address_expr->X_add_number);
4227 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4237 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4240 ip->insn_opcode |= value & 0xffff;
4248 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4250 /* There are a lot of optimizations we could do that we don't.
4251 In particular, we do not, in general, reorder instructions.
4252 If you use gcc with optimization, it will reorder
4253 instructions and generally do much more optimization then we
4254 do here; repeating all that work in the assembler would only
4255 benefit hand written assembly code, and does not seem worth
4257 int nops = (mips_optimize == 0
4258 ? nops_for_insn (0, history, NULL)
4259 : nops_for_insn_or_target (0, history, ip));
4263 unsigned long old_frag_offset;
4266 old_frag = frag_now;
4267 old_frag_offset = frag_now_fix ();
4269 for (i = 0; i < nops; i++)
4270 add_fixed_insn (NOP_INSN);
4271 insert_into_history (0, nops, NOP_INSN);
4275 listing_prev_line ();
4276 /* We may be at the start of a variant frag. In case we
4277 are, make sure there is enough space for the frag
4278 after the frags created by listing_prev_line. The
4279 argument to frag_grow here must be at least as large
4280 as the argument to all other calls to frag_grow in
4281 this file. We don't have to worry about being in the
4282 middle of a variant frag, because the variants insert
4283 all needed nop instructions themselves. */
4287 mips_move_text_labels ();
4289 #ifndef NO_ECOFF_DEBUGGING
4290 if (ECOFF_DEBUGGING)
4291 ecoff_fix_loc (old_frag, old_frag_offset);
4295 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4299 /* Work out how many nops in prev_nop_frag are needed by IP,
4300 ignoring hazards generated by the first prev_nop_frag_since
4302 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4303 gas_assert (nops <= prev_nop_frag_holds);
4305 /* Enforce NOPS as a minimum. */
4306 if (nops > prev_nop_frag_required)
4307 prev_nop_frag_required = nops;
4309 if (prev_nop_frag_holds == prev_nop_frag_required)
4311 /* Settle for the current number of nops. Update the history
4312 accordingly (for the benefit of any future .set reorder code). */
4313 prev_nop_frag = NULL;
4314 insert_into_history (prev_nop_frag_since,
4315 prev_nop_frag_holds, NOP_INSN);
4319 /* Allow this instruction to replace one of the nops that was
4320 tentatively added to prev_nop_frag. */
4321 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4322 prev_nop_frag_holds--;
4323 prev_nop_frag_since++;
4327 method = get_append_method (ip, address_expr, reloc_type);
4328 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4331 dwarf2_emit_insn (0);
4332 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4333 so "move" the instruction address accordingly.
4335 Also, it doesn't seem appropriate for the assembler to reorder .loc
4336 entries. If this instruction is a branch that we are going to swap
4337 with the previous instruction, the two instructions should be
4338 treated as a unit, and the debug information for both instructions
4339 should refer to the start of the branch sequence. Using the
4340 current position is certainly wrong when swapping a 32-bit branch
4341 and a 16-bit delay slot, since the current position would then be
4342 in the middle of a branch. */
4343 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4346 relax32 = (mips_relax_branch
4347 /* Don't try branch relaxation within .set nomacro, or within
4348 .set noat if we use $at for PIC computations. If it turns
4349 out that the branch was out-of-range, we'll get an error. */
4350 && !mips_opts.warn_about_macros
4351 && (mips_opts.at || mips_pic == NO_PIC)
4352 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4353 as they have no complementing branches. */
4354 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4356 if (!HAVE_CODE_COMPRESSION
4359 && *reloc_type == BFD_RELOC_16_PCREL_S2
4360 && delayed_branch_p (ip))
4362 relaxed_branch = TRUE;
4363 add_relaxed_insn (ip, (relaxed_branch_length
4365 uncond_branch_p (ip) ? -1
4366 : branch_likely_p (ip) ? 1
4370 uncond_branch_p (ip),
4371 branch_likely_p (ip),
4372 pinfo & INSN_WRITE_GPR_31,
4374 address_expr->X_add_symbol,
4375 address_expr->X_add_number);
4376 *reloc_type = BFD_RELOC_UNUSED;
4378 else if (mips_opts.micromips
4380 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4381 || *reloc_type > BFD_RELOC_UNUSED)
4382 && (delayed_branch_p (ip) || compact_branch_p (ip))
4383 /* Don't try branch relaxation when users specify
4384 16-bit/32-bit instructions. */
4385 && !forced_insn_length)
4387 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4388 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4389 int uncond = uncond_branch_p (ip) ? -1 : 0;
4390 int compact = compact_branch_p (ip);
4391 int al = pinfo & INSN_WRITE_GPR_31;
4394 gas_assert (address_expr != NULL);
4395 gas_assert (!mips_relax.sequence);
4397 relaxed_branch = TRUE;
4398 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4399 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4400 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4402 address_expr->X_add_symbol,
4403 address_expr->X_add_number);
4404 *reloc_type = BFD_RELOC_UNUSED;
4406 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4408 /* We need to set up a variant frag. */
4409 gas_assert (address_expr != NULL);
4410 add_relaxed_insn (ip, 4, 0,
4412 (*reloc_type - BFD_RELOC_UNUSED,
4413 forced_insn_length == 2, forced_insn_length == 4,
4414 delayed_branch_p (&history[0]),
4415 history[0].mips16_absolute_jump_p),
4416 make_expr_symbol (address_expr), 0);
4418 else if (mips_opts.mips16 && insn_length (ip) == 2)
4420 if (!delayed_branch_p (ip))
4421 /* Make sure there is enough room to swap this instruction with
4422 a following jump instruction. */
4424 add_fixed_insn (ip);
4428 if (mips_opts.mips16
4429 && mips_opts.noreorder
4430 && delayed_branch_p (&history[0]))
4431 as_warn (_("extended instruction in delay slot"));
4433 if (mips_relax.sequence)
4435 /* If we've reached the end of this frag, turn it into a variant
4436 frag and record the information for the instructions we've
4438 if (frag_room () < 4)
4439 relax_close_frag ();
4440 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4443 if (mips_relax.sequence != 2)
4445 if (mips_macro_warning.first_insn_sizes[0] == 0)
4446 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4447 mips_macro_warning.sizes[0] += insn_length (ip);
4448 mips_macro_warning.insns[0]++;
4450 if (mips_relax.sequence != 1)
4452 if (mips_macro_warning.first_insn_sizes[1] == 0)
4453 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4454 mips_macro_warning.sizes[1] += insn_length (ip);
4455 mips_macro_warning.insns[1]++;
4458 if (mips_opts.mips16)
4461 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4463 add_fixed_insn (ip);
4466 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4468 bfd_reloc_code_real_type final_type[3];
4469 reloc_howto_type *howto0;
4470 reloc_howto_type *howto;
4473 /* Perform any necessary conversion to microMIPS relocations
4474 and find out how many relocations there actually are. */
4475 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4476 final_type[i] = micromips_map_reloc (reloc_type[i]);
4478 /* In a compound relocation, it is the final (outermost)
4479 operator that determines the relocated field. */
4480 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4484 /* To reproduce this failure try assembling gas/testsuites/
4485 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4487 as_bad (_("Unsupported MIPS relocation number %d"),
4489 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4493 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4494 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4495 bfd_get_reloc_size (howto),
4497 howto0 && howto0->pc_relative,
4500 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4501 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4502 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4504 /* These relocations can have an addend that won't fit in
4505 4 octets for 64bit assembly. */
4507 && ! howto->partial_inplace
4508 && (reloc_type[0] == BFD_RELOC_16
4509 || reloc_type[0] == BFD_RELOC_32
4510 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4511 || reloc_type[0] == BFD_RELOC_GPREL16
4512 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4513 || reloc_type[0] == BFD_RELOC_GPREL32
4514 || reloc_type[0] == BFD_RELOC_64
4515 || reloc_type[0] == BFD_RELOC_CTOR
4516 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4517 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4518 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4519 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4520 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4521 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4522 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4523 || hi16_reloc_p (reloc_type[0])
4524 || lo16_reloc_p (reloc_type[0])))
4525 ip->fixp[0]->fx_no_overflow = 1;
4527 /* These relocations can have an addend that won't fit in 2 octets. */
4528 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4529 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4530 ip->fixp[0]->fx_no_overflow = 1;
4532 if (mips_relax.sequence)
4534 if (mips_relax.first_fixup == 0)
4535 mips_relax.first_fixup = ip->fixp[0];
4537 else if (reloc_needs_lo_p (*reloc_type))
4539 struct mips_hi_fixup *hi_fixup;
4541 /* Reuse the last entry if it already has a matching %lo. */
4542 hi_fixup = mips_hi_fixup_list;
4544 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4546 hi_fixup = ((struct mips_hi_fixup *)
4547 xmalloc (sizeof (struct mips_hi_fixup)));
4548 hi_fixup->next = mips_hi_fixup_list;
4549 mips_hi_fixup_list = hi_fixup;
4551 hi_fixup->fixp = ip->fixp[0];
4552 hi_fixup->seg = now_seg;
4555 /* Add fixups for the second and third relocations, if given.
4556 Note that the ABI allows the second relocation to be
4557 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4558 moment we only use RSS_UNDEF, but we could add support
4559 for the others if it ever becomes necessary. */
4560 for (i = 1; i < 3; i++)
4561 if (reloc_type[i] != BFD_RELOC_UNUSED)
4563 ip->fixp[i] = fix_new (ip->frag, ip->where,
4564 ip->fixp[0]->fx_size, NULL, 0,
4565 FALSE, final_type[i]);
4567 /* Use fx_tcbit to mark compound relocs. */
4568 ip->fixp[0]->fx_tcbit = 1;
4569 ip->fixp[i]->fx_tcbit = 1;
4574 /* Update the register mask information. */
4575 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4576 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4581 insert_into_history (0, 1, ip);
4584 case APPEND_ADD_WITH_NOP:
4586 struct mips_cl_insn *nop;
4588 insert_into_history (0, 1, ip);
4589 nop = get_delay_slot_nop (ip);
4590 add_fixed_insn (nop);
4591 insert_into_history (0, 1, nop);
4592 if (mips_relax.sequence)
4593 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4597 case APPEND_ADD_COMPACT:
4598 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4599 gas_assert (mips_opts.mips16);
4600 ip->insn_opcode |= 0x0080;
4601 find_altered_mips16_opcode (ip);
4603 insert_into_history (0, 1, ip);
4608 struct mips_cl_insn delay = history[0];
4609 if (mips_opts.mips16)
4611 know (delay.frag == ip->frag);
4612 move_insn (ip, delay.frag, delay.where);
4613 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4615 else if (relaxed_branch || delay.frag != ip->frag)
4617 /* Add the delay slot instruction to the end of the
4618 current frag and shrink the fixed part of the
4619 original frag. If the branch occupies the tail of
4620 the latter, move it backwards to cover the gap. */
4621 delay.frag->fr_fix -= branch_disp;
4622 if (delay.frag == ip->frag)
4623 move_insn (ip, ip->frag, ip->where - branch_disp);
4624 add_fixed_insn (&delay);
4628 move_insn (&delay, ip->frag,
4629 ip->where - branch_disp + insn_length (ip));
4630 move_insn (ip, history[0].frag, history[0].where);
4634 insert_into_history (0, 1, &delay);
4639 /* If we have just completed an unconditional branch, clear the history. */
4640 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4641 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4645 mips_no_prev_insn ();
4647 for (i = 0; i < ARRAY_SIZE (history); i++)
4648 history[i].cleared_p = 1;
4651 /* We need to emit a label at the end of branch-likely macros. */
4652 if (emit_branch_likely_macro)
4654 emit_branch_likely_macro = FALSE;
4655 micromips_add_label ();
4658 /* We just output an insn, so the next one doesn't have a label. */
4659 mips_clear_insn_labels ();
4662 /* Forget that there was any previous instruction or label.
4663 When BRANCH is true, the branch history is also flushed. */
4666 mips_no_prev_insn (void)
4668 prev_nop_frag = NULL;
4669 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4670 mips_clear_insn_labels ();
4673 /* This function must be called before we emit something other than
4674 instructions. It is like mips_no_prev_insn except that it inserts
4675 any NOPS that might be needed by previous instructions. */
4678 mips_emit_delays (void)
4680 if (! mips_opts.noreorder)
4682 int nops = nops_for_insn (0, history, NULL);
4686 add_fixed_insn (NOP_INSN);
4687 mips_move_text_labels ();
4690 mips_no_prev_insn ();
4693 /* Start a (possibly nested) noreorder block. */
4696 start_noreorder (void)
4698 if (mips_opts.noreorder == 0)
4703 /* None of the instructions before the .set noreorder can be moved. */
4704 for (i = 0; i < ARRAY_SIZE (history); i++)
4705 history[i].fixed_p = 1;
4707 /* Insert any nops that might be needed between the .set noreorder
4708 block and the previous instructions. We will later remove any
4709 nops that turn out not to be needed. */
4710 nops = nops_for_insn (0, history, NULL);
4713 if (mips_optimize != 0)
4715 /* Record the frag which holds the nop instructions, so
4716 that we can remove them if we don't need them. */
4717 frag_grow (nops * NOP_INSN_SIZE);
4718 prev_nop_frag = frag_now;
4719 prev_nop_frag_holds = nops;
4720 prev_nop_frag_required = 0;
4721 prev_nop_frag_since = 0;
4724 for (; nops > 0; --nops)
4725 add_fixed_insn (NOP_INSN);
4727 /* Move on to a new frag, so that it is safe to simply
4728 decrease the size of prev_nop_frag. */
4729 frag_wane (frag_now);
4731 mips_move_text_labels ();
4733 mips_mark_labels ();
4734 mips_clear_insn_labels ();
4736 mips_opts.noreorder++;
4737 mips_any_noreorder = 1;
4740 /* End a nested noreorder block. */
4743 end_noreorder (void)
4745 mips_opts.noreorder--;
4746 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4748 /* Commit to inserting prev_nop_frag_required nops and go back to
4749 handling nop insertion the .set reorder way. */
4750 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4752 insert_into_history (prev_nop_frag_since,
4753 prev_nop_frag_required, NOP_INSN);
4754 prev_nop_frag = NULL;
4758 /* Set up global variables for the start of a new macro. */
4763 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4764 memset (&mips_macro_warning.first_insn_sizes, 0,
4765 sizeof (mips_macro_warning.first_insn_sizes));
4766 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4767 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4768 && delayed_branch_p (&history[0]));
4769 switch (history[0].insn_mo->pinfo2
4770 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4772 case INSN2_BRANCH_DELAY_32BIT:
4773 mips_macro_warning.delay_slot_length = 4;
4775 case INSN2_BRANCH_DELAY_16BIT:
4776 mips_macro_warning.delay_slot_length = 2;
4779 mips_macro_warning.delay_slot_length = 0;
4782 mips_macro_warning.first_frag = NULL;
4785 /* Given that a macro is longer than one instruction or of the wrong size,
4786 return the appropriate warning for it. Return null if no warning is
4787 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4788 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4789 and RELAX_NOMACRO. */
4792 macro_warning (relax_substateT subtype)
4794 if (subtype & RELAX_DELAY_SLOT)
4795 return _("Macro instruction expanded into multiple instructions"
4796 " in a branch delay slot");
4797 else if (subtype & RELAX_NOMACRO)
4798 return _("Macro instruction expanded into multiple instructions");
4799 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4800 | RELAX_DELAY_SLOT_SIZE_SECOND))
4801 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4802 ? _("Macro instruction expanded into a wrong size instruction"
4803 " in a 16-bit branch delay slot")
4804 : _("Macro instruction expanded into a wrong size instruction"
4805 " in a 32-bit branch delay slot"));
4810 /* Finish up a macro. Emit warnings as appropriate. */
4815 /* Relaxation warning flags. */
4816 relax_substateT subtype = 0;
4818 /* Check delay slot size requirements. */
4819 if (mips_macro_warning.delay_slot_length == 2)
4820 subtype |= RELAX_DELAY_SLOT_16BIT;
4821 if (mips_macro_warning.delay_slot_length != 0)
4823 if (mips_macro_warning.delay_slot_length
4824 != mips_macro_warning.first_insn_sizes[0])
4825 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4826 if (mips_macro_warning.delay_slot_length
4827 != mips_macro_warning.first_insn_sizes[1])
4828 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4831 /* Check instruction count requirements. */
4832 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4834 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4835 subtype |= RELAX_SECOND_LONGER;
4836 if (mips_opts.warn_about_macros)
4837 subtype |= RELAX_NOMACRO;
4838 if (mips_macro_warning.delay_slot_p)
4839 subtype |= RELAX_DELAY_SLOT;
4842 /* If both alternatives fail to fill a delay slot correctly,
4843 emit the warning now. */
4844 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4845 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4850 s = subtype & (RELAX_DELAY_SLOT_16BIT
4851 | RELAX_DELAY_SLOT_SIZE_FIRST
4852 | RELAX_DELAY_SLOT_SIZE_SECOND);
4853 msg = macro_warning (s);
4855 as_warn ("%s", msg);
4859 /* If both implementations are longer than 1 instruction, then emit the
4861 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4866 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4867 msg = macro_warning (s);
4869 as_warn ("%s", msg);
4873 /* If any flags still set, then one implementation might need a warning
4874 and the other either will need one of a different kind or none at all.
4875 Pass any remaining flags over to relaxation. */
4876 if (mips_macro_warning.first_frag != NULL)
4877 mips_macro_warning.first_frag->fr_subtype |= subtype;
4880 /* Instruction operand formats used in macros that vary between
4881 standard MIPS and microMIPS code. */
4883 static const char * const brk_fmt[2] = { "c", "mF" };
4884 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4885 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4886 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4887 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4888 static const char * const mfhl_fmt[2] = { "d", "mj" };
4889 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4890 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4892 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4893 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4894 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4895 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4896 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4897 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4898 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4899 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4901 /* Read a macro's relocation codes from *ARGS and store them in *R.
4902 The first argument in *ARGS will be either the code for a single
4903 relocation or -1 followed by the three codes that make up a
4904 composite relocation. */
4907 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4911 next = va_arg (*args, int);
4913 r[0] = (bfd_reloc_code_real_type) next;
4915 for (i = 0; i < 3; i++)
4916 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4919 /* Build an instruction created by a macro expansion. This is passed
4920 a pointer to the count of instructions created so far, an
4921 expression, the name of the instruction to build, an operand format
4922 string, and corresponding arguments. */
4925 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4927 const struct mips_opcode *mo = NULL;
4928 bfd_reloc_code_real_type r[3];
4929 const struct mips_opcode *amo;
4930 struct hash_control *hash;
4931 struct mips_cl_insn insn;
4934 va_start (args, fmt);
4936 if (mips_opts.mips16)
4938 mips16_macro_build (ep, name, fmt, &args);
4943 r[0] = BFD_RELOC_UNUSED;
4944 r[1] = BFD_RELOC_UNUSED;
4945 r[2] = BFD_RELOC_UNUSED;
4946 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4947 amo = (struct mips_opcode *) hash_find (hash, name);
4949 gas_assert (strcmp (name, amo->name) == 0);
4953 /* Search until we get a match for NAME. It is assumed here that
4954 macros will never generate MDMX, MIPS-3D, or MT instructions.
4955 We try to match an instruction that fulfils the branch delay
4956 slot instruction length requirement (if any) of the previous
4957 instruction. While doing this we record the first instruction
4958 seen that matches all the other conditions and use it anyway
4959 if the requirement cannot be met; we will issue an appropriate
4960 warning later on. */
4961 if (strcmp (fmt, amo->args) == 0
4962 && amo->pinfo != INSN_MACRO
4963 && is_opcode_valid (amo)
4964 && is_size_valid (amo))
4966 if (is_delay_slot_valid (amo))
4976 gas_assert (amo->name);
4978 while (strcmp (name, amo->name) == 0);
4981 create_insn (&insn, mo);
4999 INSERT_OPERAND (mips_opts.micromips,
5000 EXTLSB, insn, va_arg (args, int));
5005 /* Note that in the macro case, these arguments are already
5006 in MSB form. (When handling the instruction in the
5007 non-macro case, these arguments are sizes from which
5008 MSB values must be calculated.) */
5009 INSERT_OPERAND (mips_opts.micromips,
5010 INSMSB, insn, va_arg (args, int));
5014 gas_assert (!mips_opts.micromips);
5015 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5021 /* Note that in the macro case, these arguments are already
5022 in MSBD form. (When handling the instruction in the
5023 non-macro case, these arguments are sizes from which
5024 MSBD values must be calculated.) */
5025 INSERT_OPERAND (mips_opts.micromips,
5026 EXTMSBD, insn, va_arg (args, int));
5030 gas_assert (!mips_opts.micromips);
5031 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5035 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5044 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5048 gas_assert (mips_opts.micromips);
5052 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5056 gas_assert (!mips_opts.micromips);
5057 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5061 gas_assert (!mips_opts.micromips);
5063 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5067 if (mips_opts.micromips)
5068 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5070 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5074 gas_assert (!mips_opts.micromips);
5076 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5080 gas_assert (!mips_opts.micromips);
5082 int tmp = va_arg (args, int);
5084 INSERT_OPERAND (0, RT, insn, tmp);
5085 INSERT_OPERAND (0, RD, insn, tmp);
5091 gas_assert (!mips_opts.micromips);
5092 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5099 INSERT_OPERAND (mips_opts.micromips,
5100 SHAMT, insn, va_arg (args, int));
5104 gas_assert (!mips_opts.micromips);
5105 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5109 gas_assert (!mips_opts.micromips);
5110 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5114 gas_assert (!mips_opts.micromips);
5115 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5119 gas_assert (!mips_opts.micromips);
5120 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5127 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5132 macro_read_relocs (&args, r);
5133 gas_assert (*r == BFD_RELOC_GPREL16
5134 || *r == BFD_RELOC_MIPS_HIGHER
5135 || *r == BFD_RELOC_HI16_S
5136 || *r == BFD_RELOC_LO16
5137 || *r == BFD_RELOC_MIPS_GOT_OFST);
5141 macro_read_relocs (&args, r);
5145 macro_read_relocs (&args, r);
5146 gas_assert (ep != NULL
5147 && (ep->X_op == O_constant
5148 || (ep->X_op == O_symbol
5149 && (*r == BFD_RELOC_MIPS_HIGHEST
5150 || *r == BFD_RELOC_HI16_S
5151 || *r == BFD_RELOC_HI16
5152 || *r == BFD_RELOC_GPREL16
5153 || *r == BFD_RELOC_MIPS_GOT_HI16
5154 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5158 gas_assert (ep != NULL);
5161 * This allows macro() to pass an immediate expression for
5162 * creating short branches without creating a symbol.
5164 * We don't allow branch relaxation for these branches, as
5165 * they should only appear in ".set nomacro" anyway.
5167 if (ep->X_op == O_constant)
5169 /* For microMIPS we always use relocations for branches.
5170 So we should not resolve immediate values. */
5171 gas_assert (!mips_opts.micromips);
5173 if ((ep->X_add_number & 3) != 0)
5174 as_bad (_("branch to misaligned address (0x%lx)"),
5175 (unsigned long) ep->X_add_number);
5176 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5177 as_bad (_("branch address range overflow (0x%lx)"),
5178 (unsigned long) ep->X_add_number);
5179 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5183 *r = BFD_RELOC_16_PCREL_S2;
5187 gas_assert (ep != NULL);
5188 *r = BFD_RELOC_MIPS_JMP;
5192 gas_assert (!mips_opts.micromips);
5193 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5197 INSERT_OPERAND (mips_opts.micromips,
5198 CACHE, insn, va_arg (args, unsigned long));
5202 gas_assert (mips_opts.micromips);
5203 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5207 gas_assert (mips_opts.micromips);
5208 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5212 INSERT_OPERAND (mips_opts.micromips,
5213 3BITPOS, insn, va_arg (args, unsigned int));
5217 INSERT_OPERAND (mips_opts.micromips,
5218 OFFSET12, insn, va_arg (args, unsigned long));
5222 gas_assert (mips_opts.micromips);
5223 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5226 case 'm': /* Opcode extension character. */
5227 gas_assert (mips_opts.micromips);
5231 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5235 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5239 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5253 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5255 append_insn (&insn, ep, r, TRUE);
5259 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5262 struct mips_opcode *mo;
5263 struct mips_cl_insn insn;
5264 bfd_reloc_code_real_type r[3]
5265 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5267 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5269 gas_assert (strcmp (name, mo->name) == 0);
5271 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5274 gas_assert (mo->name);
5275 gas_assert (strcmp (name, mo->name) == 0);
5278 create_insn (&insn, mo);
5296 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5301 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5305 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5309 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5319 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5326 regno = va_arg (*args, int);
5327 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5328 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5351 gas_assert (ep != NULL);
5353 if (ep->X_op != O_constant)
5354 *r = (int) BFD_RELOC_UNUSED + c;
5355 else if (calculate_reloc (*r, ep->X_add_number, &value))
5357 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5359 *r = BFD_RELOC_UNUSED;
5365 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5372 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5374 append_insn (&insn, ep, r, TRUE);
5378 * Sign-extend 32-bit mode constants that have bit 31 set and all
5379 * higher bits unset.
5382 normalize_constant_expr (expressionS *ex)
5384 if (ex->X_op == O_constant
5385 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5386 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5391 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5392 * all higher bits unset.
5395 normalize_address_expr (expressionS *ex)
5397 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5398 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5399 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5400 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5405 * Generate a "jalr" instruction with a relocation hint to the called
5406 * function. This occurs in NewABI PIC code.
5409 macro_build_jalr (expressionS *ep, int cprestore)
5411 static const bfd_reloc_code_real_type jalr_relocs[2]
5412 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5413 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5417 if (MIPS_JALR_HINT_P (ep))
5422 if (mips_opts.micromips)
5424 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5425 if (MIPS_JALR_HINT_P (ep)
5426 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5427 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5429 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5432 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5433 if (MIPS_JALR_HINT_P (ep))
5434 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5438 * Generate a "lui" instruction.
5441 macro_build_lui (expressionS *ep, int regnum)
5443 gas_assert (! mips_opts.mips16);
5445 if (ep->X_op != O_constant)
5447 gas_assert (ep->X_op == O_symbol);
5448 /* _gp_disp is a special case, used from s_cpload.
5449 __gnu_local_gp is used if mips_no_shared. */
5450 gas_assert (mips_pic == NO_PIC
5452 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5453 || (! mips_in_shared
5454 && strcmp (S_GET_NAME (ep->X_add_symbol),
5455 "__gnu_local_gp") == 0));
5458 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5461 /* Generate a sequence of instructions to do a load or store from a constant
5462 offset off of a base register (breg) into/from a target register (treg),
5463 using AT if necessary. */
5465 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5466 int treg, int breg, int dbl)
5468 gas_assert (ep->X_op == O_constant);
5470 /* Sign-extending 32-bit constants makes their handling easier. */
5472 normalize_constant_expr (ep);
5474 /* Right now, this routine can only handle signed 32-bit constants. */
5475 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5476 as_warn (_("operand overflow"));
5478 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5480 /* Signed 16-bit offset will fit in the op. Easy! */
5481 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5485 /* 32-bit offset, need multiple instructions and AT, like:
5486 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5487 addu $tempreg,$tempreg,$breg
5488 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5489 to handle the complete offset. */
5490 macro_build_lui (ep, AT);
5491 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5492 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5495 as_bad (_("Macro used $at after \".set noat\""));
5500 * Generates code to set the $at register to true (one)
5501 * if reg is less than the immediate expression.
5504 set_at (int reg, int unsignedp)
5506 if (imm_expr.X_op == O_constant
5507 && imm_expr.X_add_number >= -0x8000
5508 && imm_expr.X_add_number < 0x8000)
5509 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5510 AT, reg, BFD_RELOC_LO16);
5513 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5514 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5518 /* Warn if an expression is not a constant. */
5521 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5523 if (ex->X_op == O_big)
5524 as_bad (_("unsupported large constant"));
5525 else if (ex->X_op != O_constant)
5526 as_bad (_("Instruction %s requires absolute expression"),
5529 if (HAVE_32BIT_GPRS)
5530 normalize_constant_expr (ex);
5533 /* Count the leading zeroes by performing a binary chop. This is a
5534 bulky bit of source, but performance is a LOT better for the
5535 majority of values than a simple loop to count the bits:
5536 for (lcnt = 0; (lcnt < 32); lcnt++)
5537 if ((v) & (1 << (31 - lcnt)))
5539 However it is not code size friendly, and the gain will drop a bit
5540 on certain cached systems.
5542 #define COUNT_TOP_ZEROES(v) \
5543 (((v) & ~0xffff) == 0 \
5544 ? ((v) & ~0xff) == 0 \
5545 ? ((v) & ~0xf) == 0 \
5546 ? ((v) & ~0x3) == 0 \
5547 ? ((v) & ~0x1) == 0 \
5552 : ((v) & ~0x7) == 0 \
5555 : ((v) & ~0x3f) == 0 \
5556 ? ((v) & ~0x1f) == 0 \
5559 : ((v) & ~0x7f) == 0 \
5562 : ((v) & ~0xfff) == 0 \
5563 ? ((v) & ~0x3ff) == 0 \
5564 ? ((v) & ~0x1ff) == 0 \
5567 : ((v) & ~0x7ff) == 0 \
5570 : ((v) & ~0x3fff) == 0 \
5571 ? ((v) & ~0x1fff) == 0 \
5574 : ((v) & ~0x7fff) == 0 \
5577 : ((v) & ~0xffffff) == 0 \
5578 ? ((v) & ~0xfffff) == 0 \
5579 ? ((v) & ~0x3ffff) == 0 \
5580 ? ((v) & ~0x1ffff) == 0 \
5583 : ((v) & ~0x7ffff) == 0 \
5586 : ((v) & ~0x3fffff) == 0 \
5587 ? ((v) & ~0x1fffff) == 0 \
5590 : ((v) & ~0x7fffff) == 0 \
5593 : ((v) & ~0xfffffff) == 0 \
5594 ? ((v) & ~0x3ffffff) == 0 \
5595 ? ((v) & ~0x1ffffff) == 0 \
5598 : ((v) & ~0x7ffffff) == 0 \
5601 : ((v) & ~0x3fffffff) == 0 \
5602 ? ((v) & ~0x1fffffff) == 0 \
5605 : ((v) & ~0x7fffffff) == 0 \
5610 * This routine generates the least number of instructions necessary to load
5611 * an absolute expression value into a register.
5614 load_register (int reg, expressionS *ep, int dbl)
5617 expressionS hi32, lo32;
5619 if (ep->X_op != O_big)
5621 gas_assert (ep->X_op == O_constant);
5623 /* Sign-extending 32-bit constants makes their handling easier. */
5625 normalize_constant_expr (ep);
5627 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5629 /* We can handle 16 bit signed values with an addiu to
5630 $zero. No need to ever use daddiu here, since $zero and
5631 the result are always correct in 32 bit mode. */
5632 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5635 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5637 /* We can handle 16 bit unsigned values with an ori to
5639 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5642 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5644 /* 32 bit values require an lui. */
5645 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5646 if ((ep->X_add_number & 0xffff) != 0)
5647 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5652 /* The value is larger than 32 bits. */
5654 if (!dbl || HAVE_32BIT_GPRS)
5658 sprintf_vma (value, ep->X_add_number);
5659 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5660 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5664 if (ep->X_op != O_big)
5667 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5668 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5669 hi32.X_add_number &= 0xffffffff;
5671 lo32.X_add_number &= 0xffffffff;
5675 gas_assert (ep->X_add_number > 2);
5676 if (ep->X_add_number == 3)
5677 generic_bignum[3] = 0;
5678 else if (ep->X_add_number > 4)
5679 as_bad (_("Number larger than 64 bits"));
5680 lo32.X_op = O_constant;
5681 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5682 hi32.X_op = O_constant;
5683 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5686 if (hi32.X_add_number == 0)
5691 unsigned long hi, lo;
5693 if (hi32.X_add_number == (offsetT) 0xffffffff)
5695 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5697 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5700 if (lo32.X_add_number & 0x80000000)
5702 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5703 if (lo32.X_add_number & 0xffff)
5704 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5709 /* Check for 16bit shifted constant. We know that hi32 is
5710 non-zero, so start the mask on the first bit of the hi32
5715 unsigned long himask, lomask;
5719 himask = 0xffff >> (32 - shift);
5720 lomask = (0xffff << shift) & 0xffffffff;
5724 himask = 0xffff << (shift - 32);
5727 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5728 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5732 tmp.X_op = O_constant;
5734 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5735 | (lo32.X_add_number >> shift));
5737 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5738 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5739 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5740 reg, reg, (shift >= 32) ? shift - 32 : shift);
5745 while (shift <= (64 - 16));
5747 /* Find the bit number of the lowest one bit, and store the
5748 shifted value in hi/lo. */
5749 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5750 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5754 while ((lo & 1) == 0)
5759 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5765 while ((hi & 1) == 0)
5774 /* Optimize if the shifted value is a (power of 2) - 1. */
5775 if ((hi == 0 && ((lo + 1) & lo) == 0)
5776 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5778 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5783 /* This instruction will set the register to be all
5785 tmp.X_op = O_constant;
5786 tmp.X_add_number = (offsetT) -1;
5787 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5791 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5792 reg, reg, (bit >= 32) ? bit - 32 : bit);
5794 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5795 reg, reg, (shift >= 32) ? shift - 32 : shift);
5800 /* Sign extend hi32 before calling load_register, because we can
5801 generally get better code when we load a sign extended value. */
5802 if ((hi32.X_add_number & 0x80000000) != 0)
5803 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5804 load_register (reg, &hi32, 0);
5807 if ((lo32.X_add_number & 0xffff0000) == 0)
5811 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5819 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5821 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5822 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5828 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5832 mid16.X_add_number >>= 16;
5833 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5834 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5837 if ((lo32.X_add_number & 0xffff) != 0)
5838 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5842 load_delay_nop (void)
5844 if (!gpr_interlocks)
5845 macro_build (NULL, "nop", "");
5848 /* Load an address into a register. */
5851 load_address (int reg, expressionS *ep, int *used_at)
5853 if (ep->X_op != O_constant
5854 && ep->X_op != O_symbol)
5856 as_bad (_("expression too complex"));
5857 ep->X_op = O_constant;
5860 if (ep->X_op == O_constant)
5862 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5866 if (mips_pic == NO_PIC)
5868 /* If this is a reference to a GP relative symbol, we want
5869 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5871 lui $reg,<sym> (BFD_RELOC_HI16_S)
5872 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5873 If we have an addend, we always use the latter form.
5875 With 64bit address space and a usable $at we want
5876 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5877 lui $at,<sym> (BFD_RELOC_HI16_S)
5878 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5879 daddiu $at,<sym> (BFD_RELOC_LO16)
5883 If $at is already in use, we use a path which is suboptimal
5884 on superscalar processors.
5885 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5886 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5888 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5890 daddiu $reg,<sym> (BFD_RELOC_LO16)
5892 For GP relative symbols in 64bit address space we can use
5893 the same sequence as in 32bit address space. */
5894 if (HAVE_64BIT_SYMBOLS)
5896 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5897 && !nopic_need_relax (ep->X_add_symbol, 1))
5899 relax_start (ep->X_add_symbol);
5900 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5901 mips_gp_register, BFD_RELOC_GPREL16);
5905 if (*used_at == 0 && mips_opts.at)
5907 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5908 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5909 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5910 BFD_RELOC_MIPS_HIGHER);
5911 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5912 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5913 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5918 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5919 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5920 BFD_RELOC_MIPS_HIGHER);
5921 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5922 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5923 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5924 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5927 if (mips_relax.sequence)
5932 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5933 && !nopic_need_relax (ep->X_add_symbol, 1))
5935 relax_start (ep->X_add_symbol);
5936 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5937 mips_gp_register, BFD_RELOC_GPREL16);
5940 macro_build_lui (ep, reg);
5941 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5942 reg, reg, BFD_RELOC_LO16);
5943 if (mips_relax.sequence)
5947 else if (!mips_big_got)
5951 /* If this is a reference to an external symbol, we want
5952 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5954 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5956 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5957 If there is a constant, it must be added in after.
5959 If we have NewABI, we want
5960 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5961 unless we're referencing a global symbol with a non-zero
5962 offset, in which case cst must be added separately. */
5965 if (ep->X_add_number)
5967 ex.X_add_number = ep->X_add_number;
5968 ep->X_add_number = 0;
5969 relax_start (ep->X_add_symbol);
5970 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5971 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5972 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5973 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5974 ex.X_op = O_constant;
5975 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5976 reg, reg, BFD_RELOC_LO16);
5977 ep->X_add_number = ex.X_add_number;
5980 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5981 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5982 if (mips_relax.sequence)
5987 ex.X_add_number = ep->X_add_number;
5988 ep->X_add_number = 0;
5989 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5990 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5992 relax_start (ep->X_add_symbol);
5994 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5998 if (ex.X_add_number != 0)
6000 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6001 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6002 ex.X_op = O_constant;
6003 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6004 reg, reg, BFD_RELOC_LO16);
6008 else if (mips_big_got)
6012 /* This is the large GOT case. If this is a reference to an
6013 external symbol, we want
6014 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6016 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6018 Otherwise, for a reference to a local symbol in old ABI, we want
6019 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6021 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6022 If there is a constant, it must be added in after.
6024 In the NewABI, for local symbols, with or without offsets, we want:
6025 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6026 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6030 ex.X_add_number = ep->X_add_number;
6031 ep->X_add_number = 0;
6032 relax_start (ep->X_add_symbol);
6033 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6035 reg, reg, mips_gp_register);
6036 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6037 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6038 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6039 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6040 else if (ex.X_add_number)
6042 ex.X_op = O_constant;
6043 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6047 ep->X_add_number = ex.X_add_number;
6049 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6050 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6051 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6052 BFD_RELOC_MIPS_GOT_OFST);
6057 ex.X_add_number = ep->X_add_number;
6058 ep->X_add_number = 0;
6059 relax_start (ep->X_add_symbol);
6060 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6062 reg, reg, mips_gp_register);
6063 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6064 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6066 if (reg_needs_delay (mips_gp_register))
6068 /* We need a nop before loading from $gp. This special
6069 check is required because the lui which starts the main
6070 instruction stream does not refer to $gp, and so will not
6071 insert the nop which may be required. */
6072 macro_build (NULL, "nop", "");
6074 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6075 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6077 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6081 if (ex.X_add_number != 0)
6083 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6084 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6085 ex.X_op = O_constant;
6086 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6094 if (!mips_opts.at && *used_at == 1)
6095 as_bad (_("Macro used $at after \".set noat\""));
6098 /* Move the contents of register SOURCE into register DEST. */
6101 move_register (int dest, int source)
6103 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6104 instruction specifically requires a 32-bit one. */
6105 if (mips_opts.micromips
6106 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6107 macro_build (NULL, "move", "mp,mj", dest, source);
6109 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6113 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6114 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6115 The two alternatives are:
6117 Global symbol Local sybmol
6118 ------------- ------------
6119 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6121 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6123 load_got_offset emits the first instruction and add_got_offset
6124 emits the second for a 16-bit offset or add_got_offset_hilo emits
6125 a sequence to add a 32-bit offset using a scratch register. */
6128 load_got_offset (int dest, expressionS *local)
6133 global.X_add_number = 0;
6135 relax_start (local->X_add_symbol);
6136 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6137 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6139 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6140 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6145 add_got_offset (int dest, expressionS *local)
6149 global.X_op = O_constant;
6150 global.X_op_symbol = NULL;
6151 global.X_add_symbol = NULL;
6152 global.X_add_number = local->X_add_number;
6154 relax_start (local->X_add_symbol);
6155 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6156 dest, dest, BFD_RELOC_LO16);
6158 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6163 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6166 int hold_mips_optimize;
6168 global.X_op = O_constant;
6169 global.X_op_symbol = NULL;
6170 global.X_add_symbol = NULL;
6171 global.X_add_number = local->X_add_number;
6173 relax_start (local->X_add_symbol);
6174 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6176 /* Set mips_optimize around the lui instruction to avoid
6177 inserting an unnecessary nop after the lw. */
6178 hold_mips_optimize = mips_optimize;
6180 macro_build_lui (&global, tmp);
6181 mips_optimize = hold_mips_optimize;
6182 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6185 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6188 /* Emit a sequence of instructions to emulate a branch likely operation.
6189 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6190 is its complementing branch with the original condition negated.
6191 CALL is set if the original branch specified the link operation.
6192 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6194 Code like this is produced in the noreorder mode:
6199 delay slot (executed only if branch taken)
6207 delay slot (executed only if branch taken)
6210 In the reorder mode the delay slot would be filled with a nop anyway,
6211 so code produced is simply:
6216 This function is used when producing code for the microMIPS ASE that
6217 does not implement branch likely instructions in hardware. */
6220 macro_build_branch_likely (const char *br, const char *brneg,
6221 int call, expressionS *ep, const char *fmt,
6222 unsigned int sreg, unsigned int treg)
6224 int noreorder = mips_opts.noreorder;
6227 gas_assert (mips_opts.micromips);
6231 micromips_label_expr (&expr1);
6232 macro_build (&expr1, brneg, fmt, sreg, treg);
6233 macro_build (NULL, "nop", "");
6234 macro_build (ep, call ? "bal" : "b", "p");
6236 /* Set to true so that append_insn adds a label. */
6237 emit_branch_likely_macro = TRUE;
6241 macro_build (ep, br, fmt, sreg, treg);
6242 macro_build (NULL, "nop", "");
6247 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6248 the condition code tested. EP specifies the branch target. */
6251 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6278 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6281 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6282 the register tested. EP specifies the branch target. */
6285 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6287 const char *brneg = NULL;
6297 br = mips_opts.micromips ? "bgez" : "bgezl";
6301 gas_assert (mips_opts.micromips);
6310 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6317 br = mips_opts.micromips ? "blez" : "blezl";
6324 br = mips_opts.micromips ? "bltz" : "bltzl";
6328 gas_assert (mips_opts.micromips);
6336 if (mips_opts.micromips && brneg)
6337 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6339 macro_build (ep, br, "s,p", sreg);
6342 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6343 TREG as the registers tested. EP specifies the branch target. */
6346 macro_build_branch_rsrt (int type, expressionS *ep,
6347 unsigned int sreg, unsigned int treg)
6349 const char *brneg = NULL;
6361 br = mips_opts.micromips ? "beq" : "beql";
6370 br = mips_opts.micromips ? "bne" : "bnel";
6376 if (mips_opts.micromips && brneg)
6377 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6379 macro_build (ep, br, "s,t,p", sreg, treg);
6384 * This routine implements the seemingly endless macro or synthesized
6385 * instructions and addressing modes in the mips assembly language. Many
6386 * of these macros are simple and are similar to each other. These could
6387 * probably be handled by some kind of table or grammar approach instead of
6388 * this verbose method. Others are not simple macros but are more like
6389 * optimizing code generation.
6390 * One interesting optimization is when several store macros appear
6391 * consecutively that would load AT with the upper half of the same address.
6392 * The ensuing load upper instructions are ommited. This implies some kind
6393 * of global optimization. We currently only optimize within a single macro.
6394 * For many of the load and store macros if the address is specified as a
6395 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6396 * first load register 'at' with zero and use it as the base register. The
6397 * mips assembler simply uses register $zero. Just one tiny optimization
6401 macro (struct mips_cl_insn *ip)
6403 unsigned int treg, sreg, dreg, breg;
6404 unsigned int tempreg;
6407 expressionS label_expr;
6425 bfd_reloc_code_real_type r;
6426 int hold_mips_optimize;
6428 gas_assert (! mips_opts.mips16);
6430 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6431 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6432 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6433 mask = ip->insn_mo->mask;
6435 label_expr.X_op = O_constant;
6436 label_expr.X_op_symbol = NULL;
6437 label_expr.X_add_symbol = NULL;
6438 label_expr.X_add_number = 0;
6440 expr1.X_op = O_constant;
6441 expr1.X_op_symbol = NULL;
6442 expr1.X_add_symbol = NULL;
6443 expr1.X_add_number = 1;
6458 if (mips_opts.micromips)
6459 micromips_label_expr (&label_expr);
6461 label_expr.X_add_number = 8;
6462 macro_build (&label_expr, "bgez", "s,p", sreg);
6464 macro_build (NULL, "nop", "");
6466 move_register (dreg, sreg);
6467 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6468 if (mips_opts.micromips)
6469 micromips_add_label ();
6486 if (!mips_opts.micromips)
6488 if (imm_expr.X_op == O_constant
6489 && imm_expr.X_add_number >= -0x200
6490 && imm_expr.X_add_number < 0x200)
6492 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6501 if (imm_expr.X_op == O_constant
6502 && imm_expr.X_add_number >= -0x8000
6503 && imm_expr.X_add_number < 0x8000)
6505 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6510 load_register (AT, &imm_expr, dbl);
6511 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6530 if (imm_expr.X_op == O_constant
6531 && imm_expr.X_add_number >= 0
6532 && imm_expr.X_add_number < 0x10000)
6534 if (mask != M_NOR_I)
6535 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6538 macro_build (&imm_expr, "ori", "t,r,i",
6539 treg, sreg, BFD_RELOC_LO16);
6540 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6546 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6547 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6551 switch (imm_expr.X_add_number)
6554 macro_build (NULL, "nop", "");
6557 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6561 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6562 (int) imm_expr.X_add_number);
6565 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6566 (unsigned long) imm_expr.X_add_number);
6575 gas_assert (mips_opts.micromips);
6576 macro_build_branch_ccl (mask, &offset_expr,
6577 EXTRACT_OPERAND (1, BCC, *ip));
6584 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6590 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6595 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6602 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6604 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6608 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6609 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6610 &offset_expr, AT, ZERO);
6620 macro_build_branch_rs (mask, &offset_expr, sreg);
6626 /* Check for > max integer. */
6627 maxnum = 0x7fffffff;
6628 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6635 if (imm_expr.X_op == O_constant
6636 && imm_expr.X_add_number >= maxnum
6637 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6640 /* Result is always false. */
6642 macro_build (NULL, "nop", "");
6644 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6647 if (imm_expr.X_op != O_constant)
6648 as_bad (_("Unsupported large constant"));
6649 ++imm_expr.X_add_number;
6653 if (mask == M_BGEL_I)
6655 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6657 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6658 &offset_expr, sreg);
6661 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6663 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6664 &offset_expr, sreg);
6667 maxnum = 0x7fffffff;
6668 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6675 maxnum = - maxnum - 1;
6676 if (imm_expr.X_op == O_constant
6677 && imm_expr.X_add_number <= maxnum
6678 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6681 /* result is always true */
6682 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6683 macro_build (&offset_expr, "b", "p");
6688 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6689 &offset_expr, AT, ZERO);
6698 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6699 &offset_expr, ZERO, treg);
6703 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6704 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6705 &offset_expr, AT, ZERO);
6714 && imm_expr.X_op == O_constant
6715 && imm_expr.X_add_number == -1))
6717 if (imm_expr.X_op != O_constant)
6718 as_bad (_("Unsupported large constant"));
6719 ++imm_expr.X_add_number;
6723 if (mask == M_BGEUL_I)
6725 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6727 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6728 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6729 &offset_expr, sreg, ZERO);
6734 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6735 &offset_expr, AT, ZERO);
6743 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6745 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6749 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6750 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6751 &offset_expr, AT, ZERO);
6759 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6760 &offset_expr, sreg, ZERO);
6766 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6767 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6768 &offset_expr, AT, ZERO);
6776 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6778 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6782 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6783 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6784 &offset_expr, AT, ZERO);
6791 maxnum = 0x7fffffff;
6792 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6799 if (imm_expr.X_op == O_constant
6800 && imm_expr.X_add_number >= maxnum
6801 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6803 if (imm_expr.X_op != O_constant)
6804 as_bad (_("Unsupported large constant"));
6805 ++imm_expr.X_add_number;
6809 if (mask == M_BLTL_I)
6811 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6812 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6813 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6814 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6819 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6820 &offset_expr, AT, ZERO);
6828 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6829 &offset_expr, sreg, ZERO);
6835 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6836 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6837 &offset_expr, AT, ZERO);
6846 && imm_expr.X_op == O_constant
6847 && imm_expr.X_add_number == -1))
6849 if (imm_expr.X_op != O_constant)
6850 as_bad (_("Unsupported large constant"));
6851 ++imm_expr.X_add_number;
6855 if (mask == M_BLTUL_I)
6857 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6859 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6860 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6861 &offset_expr, sreg, ZERO);
6866 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6867 &offset_expr, AT, ZERO);
6875 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6877 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6881 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6882 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6883 &offset_expr, AT, ZERO);
6893 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6894 &offset_expr, ZERO, treg);
6898 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6899 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6900 &offset_expr, AT, ZERO);
6906 /* Use unsigned arithmetic. */
6910 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6912 as_bad (_("Unsupported large constant"));
6917 pos = imm_expr.X_add_number;
6918 size = imm2_expr.X_add_number;
6923 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6926 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6928 as_bad (_("Improper extract size (%lu, position %lu)"),
6929 (unsigned long) size, (unsigned long) pos);
6933 if (size <= 32 && pos < 32)
6938 else if (size <= 32)
6948 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6955 /* Use unsigned arithmetic. */
6959 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6961 as_bad (_("Unsupported large constant"));
6966 pos = imm_expr.X_add_number;
6967 size = imm2_expr.X_add_number;
6972 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6975 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6977 as_bad (_("Improper insert size (%lu, position %lu)"),
6978 (unsigned long) size, (unsigned long) pos);
6982 if (pos < 32 && (pos + size - 1) < 32)
6997 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6998 (int) (pos + size - 1));
7014 as_warn (_("Divide by zero."));
7016 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7018 macro_build (NULL, "break", BRK_FMT, 7);
7025 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7026 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7030 if (mips_opts.micromips)
7031 micromips_label_expr (&label_expr);
7033 label_expr.X_add_number = 8;
7034 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7035 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7036 macro_build (NULL, "break", BRK_FMT, 7);
7037 if (mips_opts.micromips)
7038 micromips_add_label ();
7040 expr1.X_add_number = -1;
7042 load_register (AT, &expr1, dbl);
7043 if (mips_opts.micromips)
7044 micromips_label_expr (&label_expr);
7046 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7047 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7050 expr1.X_add_number = 1;
7051 load_register (AT, &expr1, dbl);
7052 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7056 expr1.X_add_number = 0x80000000;
7057 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7061 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7062 /* We want to close the noreorder block as soon as possible, so
7063 that later insns are available for delay slot filling. */
7068 if (mips_opts.micromips)
7069 micromips_label_expr (&label_expr);
7071 label_expr.X_add_number = 8;
7072 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7073 macro_build (NULL, "nop", "");
7075 /* We want to close the noreorder block as soon as possible, so
7076 that later insns are available for delay slot filling. */
7079 macro_build (NULL, "break", BRK_FMT, 6);
7081 if (mips_opts.micromips)
7082 micromips_add_label ();
7083 macro_build (NULL, s, MFHL_FMT, dreg);
7122 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7124 as_warn (_("Divide by zero."));
7126 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7128 macro_build (NULL, "break", BRK_FMT, 7);
7131 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7133 if (strcmp (s2, "mflo") == 0)
7134 move_register (dreg, sreg);
7136 move_register (dreg, ZERO);
7139 if (imm_expr.X_op == O_constant
7140 && imm_expr.X_add_number == -1
7141 && s[strlen (s) - 1] != 'u')
7143 if (strcmp (s2, "mflo") == 0)
7145 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7148 move_register (dreg, ZERO);
7153 load_register (AT, &imm_expr, dbl);
7154 macro_build (NULL, s, "z,s,t", sreg, AT);
7155 macro_build (NULL, s2, MFHL_FMT, dreg);
7177 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7178 macro_build (NULL, s, "z,s,t", sreg, treg);
7179 /* We want to close the noreorder block as soon as possible, so
7180 that later insns are available for delay slot filling. */
7185 if (mips_opts.micromips)
7186 micromips_label_expr (&label_expr);
7188 label_expr.X_add_number = 8;
7189 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7190 macro_build (NULL, s, "z,s,t", sreg, treg);
7192 /* We want to close the noreorder block as soon as possible, so
7193 that later insns are available for delay slot filling. */
7195 macro_build (NULL, "break", BRK_FMT, 7);
7196 if (mips_opts.micromips)
7197 micromips_add_label ();
7199 macro_build (NULL, s2, MFHL_FMT, dreg);
7211 /* Load the address of a symbol into a register. If breg is not
7212 zero, we then add a base register to it. */
7214 if (dbl && HAVE_32BIT_GPRS)
7215 as_warn (_("dla used to load 32-bit register"));
7217 if (!dbl && HAVE_64BIT_OBJECTS)
7218 as_warn (_("la used to load 64-bit address"));
7220 if (offset_expr.X_op == O_constant
7221 && offset_expr.X_add_number >= -0x8000
7222 && offset_expr.X_add_number < 0x8000)
7224 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7225 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7229 if (mips_opts.at && (treg == breg))
7239 if (offset_expr.X_op != O_symbol
7240 && offset_expr.X_op != O_constant)
7242 as_bad (_("Expression too complex"));
7243 offset_expr.X_op = O_constant;
7246 if (offset_expr.X_op == O_constant)
7247 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7248 else if (mips_pic == NO_PIC)
7250 /* If this is a reference to a GP relative symbol, we want
7251 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7253 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7254 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7255 If we have a constant, we need two instructions anyhow,
7256 so we may as well always use the latter form.
7258 With 64bit address space and a usable $at we want
7259 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7260 lui $at,<sym> (BFD_RELOC_HI16_S)
7261 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7262 daddiu $at,<sym> (BFD_RELOC_LO16)
7264 daddu $tempreg,$tempreg,$at
7266 If $at is already in use, we use a path which is suboptimal
7267 on superscalar processors.
7268 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7269 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7271 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7273 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7275 For GP relative symbols in 64bit address space we can use
7276 the same sequence as in 32bit address space. */
7277 if (HAVE_64BIT_SYMBOLS)
7279 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7280 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7282 relax_start (offset_expr.X_add_symbol);
7283 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7284 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7288 if (used_at == 0 && mips_opts.at)
7290 macro_build (&offset_expr, "lui", LUI_FMT,
7291 tempreg, BFD_RELOC_MIPS_HIGHEST);
7292 macro_build (&offset_expr, "lui", LUI_FMT,
7293 AT, BFD_RELOC_HI16_S);
7294 macro_build (&offset_expr, "daddiu", "t,r,j",
7295 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7296 macro_build (&offset_expr, "daddiu", "t,r,j",
7297 AT, AT, BFD_RELOC_LO16);
7298 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7299 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7304 macro_build (&offset_expr, "lui", LUI_FMT,
7305 tempreg, BFD_RELOC_MIPS_HIGHEST);
7306 macro_build (&offset_expr, "daddiu", "t,r,j",
7307 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7308 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7309 macro_build (&offset_expr, "daddiu", "t,r,j",
7310 tempreg, tempreg, BFD_RELOC_HI16_S);
7311 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7312 macro_build (&offset_expr, "daddiu", "t,r,j",
7313 tempreg, tempreg, BFD_RELOC_LO16);
7316 if (mips_relax.sequence)
7321 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7322 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7324 relax_start (offset_expr.X_add_symbol);
7325 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7326 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7329 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7330 as_bad (_("Offset too large"));
7331 macro_build_lui (&offset_expr, tempreg);
7332 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7333 tempreg, tempreg, BFD_RELOC_LO16);
7334 if (mips_relax.sequence)
7338 else if (!mips_big_got && !HAVE_NEWABI)
7340 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7342 /* If this is a reference to an external symbol, and there
7343 is no constant, we want
7344 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7345 or for lca or if tempreg is PIC_CALL_REG
7346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7347 For a local symbol, we want
7348 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7350 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7352 If we have a small constant, and this is a reference to
7353 an external symbol, we want
7354 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7356 addiu $tempreg,$tempreg,<constant>
7357 For a local symbol, we want the same instruction
7358 sequence, but we output a BFD_RELOC_LO16 reloc on the
7361 If we have a large constant, and this is a reference to
7362 an external symbol, we want
7363 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7364 lui $at,<hiconstant>
7365 addiu $at,$at,<loconstant>
7366 addu $tempreg,$tempreg,$at
7367 For a local symbol, we want the same instruction
7368 sequence, but we output a BFD_RELOC_LO16 reloc on the
7372 if (offset_expr.X_add_number == 0)
7374 if (mips_pic == SVR4_PIC
7376 && (call || tempreg == PIC_CALL_REG))
7377 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7379 relax_start (offset_expr.X_add_symbol);
7380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7381 lw_reloc_type, mips_gp_register);
7384 /* We're going to put in an addu instruction using
7385 tempreg, so we may as well insert the nop right
7390 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7391 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7393 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7394 tempreg, tempreg, BFD_RELOC_LO16);
7396 /* FIXME: If breg == 0, and the next instruction uses
7397 $tempreg, then if this variant case is used an extra
7398 nop will be generated. */
7400 else if (offset_expr.X_add_number >= -0x8000
7401 && offset_expr.X_add_number < 0x8000)
7403 load_got_offset (tempreg, &offset_expr);
7405 add_got_offset (tempreg, &offset_expr);
7409 expr1.X_add_number = offset_expr.X_add_number;
7410 offset_expr.X_add_number =
7411 SEXT_16BIT (offset_expr.X_add_number);
7412 load_got_offset (tempreg, &offset_expr);
7413 offset_expr.X_add_number = expr1.X_add_number;
7414 /* If we are going to add in a base register, and the
7415 target register and the base register are the same,
7416 then we are using AT as a temporary register. Since
7417 we want to load the constant into AT, we add our
7418 current AT (from the global offset table) and the
7419 register into the register now, and pretend we were
7420 not using a base register. */
7424 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7429 add_got_offset_hilo (tempreg, &offset_expr, AT);
7433 else if (!mips_big_got && HAVE_NEWABI)
7435 int add_breg_early = 0;
7437 /* If this is a reference to an external, and there is no
7438 constant, or local symbol (*), with or without a
7440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7441 or for lca or if tempreg is PIC_CALL_REG
7442 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7444 If we have a small constant, and this is a reference to
7445 an external symbol, we want
7446 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7447 addiu $tempreg,$tempreg,<constant>
7449 If we have a large constant, and this is a reference to
7450 an external symbol, we want
7451 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7452 lui $at,<hiconstant>
7453 addiu $at,$at,<loconstant>
7454 addu $tempreg,$tempreg,$at
7456 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7457 local symbols, even though it introduces an additional
7460 if (offset_expr.X_add_number)
7462 expr1.X_add_number = offset_expr.X_add_number;
7463 offset_expr.X_add_number = 0;
7465 relax_start (offset_expr.X_add_symbol);
7466 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7467 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7469 if (expr1.X_add_number >= -0x8000
7470 && expr1.X_add_number < 0x8000)
7472 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7473 tempreg, tempreg, BFD_RELOC_LO16);
7475 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7477 /* If we are going to add in a base register, and the
7478 target register and the base register are the same,
7479 then we are using AT as a temporary register. Since
7480 we want to load the constant into AT, we add our
7481 current AT (from the global offset table) and the
7482 register into the register now, and pretend we were
7483 not using a base register. */
7488 gas_assert (tempreg == AT);
7489 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7495 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7496 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7502 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7505 offset_expr.X_add_number = expr1.X_add_number;
7507 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7508 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7511 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7512 treg, tempreg, breg);
7518 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7520 relax_start (offset_expr.X_add_symbol);
7521 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7522 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7524 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7525 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7530 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7531 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7534 else if (mips_big_got && !HAVE_NEWABI)
7537 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7538 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7539 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7541 /* This is the large GOT case. If this is a reference to an
7542 external symbol, and there is no constant, we want
7543 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7544 addu $tempreg,$tempreg,$gp
7545 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7546 or for lca or if tempreg is PIC_CALL_REG
7547 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7548 addu $tempreg,$tempreg,$gp
7549 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7550 For a local symbol, we want
7551 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7553 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7555 If we have a small constant, and this is a reference to
7556 an external symbol, we want
7557 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7558 addu $tempreg,$tempreg,$gp
7559 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7561 addiu $tempreg,$tempreg,<constant>
7562 For a local symbol, we want
7563 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7565 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7567 If we have a large constant, and this is a reference to
7568 an external symbol, we want
7569 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7570 addu $tempreg,$tempreg,$gp
7571 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7572 lui $at,<hiconstant>
7573 addiu $at,$at,<loconstant>
7574 addu $tempreg,$tempreg,$at
7575 For a local symbol, we want
7576 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7577 lui $at,<hiconstant>
7578 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7579 addu $tempreg,$tempreg,$at
7582 expr1.X_add_number = offset_expr.X_add_number;
7583 offset_expr.X_add_number = 0;
7584 relax_start (offset_expr.X_add_symbol);
7585 gpdelay = reg_needs_delay (mips_gp_register);
7586 if (expr1.X_add_number == 0 && breg == 0
7587 && (call || tempreg == PIC_CALL_REG))
7589 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7590 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7592 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7593 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7594 tempreg, tempreg, mips_gp_register);
7595 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7596 tempreg, lw_reloc_type, tempreg);
7597 if (expr1.X_add_number == 0)
7601 /* We're going to put in an addu instruction using
7602 tempreg, so we may as well insert the nop right
7607 else if (expr1.X_add_number >= -0x8000
7608 && expr1.X_add_number < 0x8000)
7611 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7612 tempreg, tempreg, BFD_RELOC_LO16);
7616 /* If we are going to add in a base register, and the
7617 target register and the base register are the same,
7618 then we are using AT as a temporary register. Since
7619 we want to load the constant into AT, we add our
7620 current AT (from the global offset table) and the
7621 register into the register now, and pretend we were
7622 not using a base register. */
7627 gas_assert (tempreg == AT);
7629 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7634 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7635 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7639 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7644 /* This is needed because this instruction uses $gp, but
7645 the first instruction on the main stream does not. */
7646 macro_build (NULL, "nop", "");
7649 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7650 local_reloc_type, mips_gp_register);
7651 if (expr1.X_add_number >= -0x8000
7652 && expr1.X_add_number < 0x8000)
7655 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7656 tempreg, tempreg, BFD_RELOC_LO16);
7657 /* FIXME: If add_number is 0, and there was no base
7658 register, the external symbol case ended with a load,
7659 so if the symbol turns out to not be external, and
7660 the next instruction uses tempreg, an unnecessary nop
7661 will be inserted. */
7667 /* We must add in the base register now, as in the
7668 external symbol case. */
7669 gas_assert (tempreg == AT);
7671 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7674 /* We set breg to 0 because we have arranged to add
7675 it in in both cases. */
7679 macro_build_lui (&expr1, AT);
7680 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7681 AT, AT, BFD_RELOC_LO16);
7682 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7683 tempreg, tempreg, AT);
7688 else if (mips_big_got && HAVE_NEWABI)
7690 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7691 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7692 int add_breg_early = 0;
7694 /* This is the large GOT case. If this is a reference to an
7695 external symbol, and there is no constant, we want
7696 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7697 add $tempreg,$tempreg,$gp
7698 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7699 or for lca or if tempreg is PIC_CALL_REG
7700 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7701 add $tempreg,$tempreg,$gp
7702 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7704 If we have a small constant, and this is a reference to
7705 an external symbol, we want
7706 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7707 add $tempreg,$tempreg,$gp
7708 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7709 addi $tempreg,$tempreg,<constant>
7711 If we have a large constant, and this is a reference to
7712 an external symbol, we want
7713 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7714 addu $tempreg,$tempreg,$gp
7715 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7716 lui $at,<hiconstant>
7717 addi $at,$at,<loconstant>
7718 add $tempreg,$tempreg,$at
7720 If we have NewABI, and we know it's a local symbol, we want
7721 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7722 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7723 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7725 relax_start (offset_expr.X_add_symbol);
7727 expr1.X_add_number = offset_expr.X_add_number;
7728 offset_expr.X_add_number = 0;
7730 if (expr1.X_add_number == 0 && breg == 0
7731 && (call || tempreg == PIC_CALL_REG))
7733 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7734 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7736 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7737 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7738 tempreg, tempreg, mips_gp_register);
7739 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7740 tempreg, lw_reloc_type, tempreg);
7742 if (expr1.X_add_number == 0)
7744 else if (expr1.X_add_number >= -0x8000
7745 && expr1.X_add_number < 0x8000)
7747 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7748 tempreg, tempreg, BFD_RELOC_LO16);
7750 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7752 /* If we are going to add in a base register, and the
7753 target register and the base register are the same,
7754 then we are using AT as a temporary register. Since
7755 we want to load the constant into AT, we add our
7756 current AT (from the global offset table) and the
7757 register into the register now, and pretend we were
7758 not using a base register. */
7763 gas_assert (tempreg == AT);
7764 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7770 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7771 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7776 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7779 offset_expr.X_add_number = expr1.X_add_number;
7780 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7781 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7782 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7783 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7786 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7787 treg, tempreg, breg);
7797 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7801 gas_assert (!mips_opts.micromips);
7803 unsigned long temp = (treg << 16) | (0x01);
7804 macro_build (NULL, "c2", "C", temp);
7809 gas_assert (!mips_opts.micromips);
7811 unsigned long temp = (0x02);
7812 macro_build (NULL, "c2", "C", temp);
7817 gas_assert (!mips_opts.micromips);
7819 unsigned long temp = (treg << 16) | (0x02);
7820 macro_build (NULL, "c2", "C", temp);
7825 gas_assert (!mips_opts.micromips);
7826 macro_build (NULL, "c2", "C", 3);
7830 gas_assert (!mips_opts.micromips);
7832 unsigned long temp = (treg << 16) | 0x03;
7833 macro_build (NULL, "c2", "C", temp);
7838 /* The j instruction may not be used in PIC code, since it
7839 requires an absolute address. We convert it to a b
7841 if (mips_pic == NO_PIC)
7842 macro_build (&offset_expr, "j", "a");
7844 macro_build (&offset_expr, "b", "p");
7847 /* The jal instructions must be handled as macros because when
7848 generating PIC code they expand to multi-instruction
7849 sequences. Normally they are simple instructions. */
7854 gas_assert (mips_opts.micromips);
7862 if (mips_pic == NO_PIC)
7864 s = jals ? "jalrs" : "jalr";
7865 if (mips_opts.micromips
7867 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7868 macro_build (NULL, s, "mj", sreg);
7870 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7874 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7875 && mips_cprestore_offset >= 0);
7877 if (sreg != PIC_CALL_REG)
7878 as_warn (_("MIPS PIC call to register other than $25"));
7880 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7881 ? "jalrs" : "jalr");
7882 if (mips_opts.micromips
7884 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7885 macro_build (NULL, s, "mj", sreg);
7887 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7888 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7890 if (mips_cprestore_offset < 0)
7891 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7894 if (!mips_frame_reg_valid)
7896 as_warn (_("No .frame pseudo-op used in PIC code"));
7897 /* Quiet this warning. */
7898 mips_frame_reg_valid = 1;
7900 if (!mips_cprestore_valid)
7902 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7903 /* Quiet this warning. */
7904 mips_cprestore_valid = 1;
7906 if (mips_opts.noreorder)
7907 macro_build (NULL, "nop", "");
7908 expr1.X_add_number = mips_cprestore_offset;
7909 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7912 HAVE_64BIT_ADDRESSES);
7920 gas_assert (mips_opts.micromips);
7924 if (mips_pic == NO_PIC)
7925 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7926 else if (mips_pic == SVR4_PIC)
7928 /* If this is a reference to an external symbol, and we are
7929 using a small GOT, we want
7930 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7934 lw $gp,cprestore($sp)
7935 The cprestore value is set using the .cprestore
7936 pseudo-op. If we are using a big GOT, we want
7937 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7939 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7943 lw $gp,cprestore($sp)
7944 If the symbol is not external, we want
7945 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7947 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7950 lw $gp,cprestore($sp)
7952 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7953 sequences above, minus nops, unless the symbol is local,
7954 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7960 relax_start (offset_expr.X_add_symbol);
7961 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7962 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7965 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7966 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7972 relax_start (offset_expr.X_add_symbol);
7973 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7974 BFD_RELOC_MIPS_CALL_HI16);
7975 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7976 PIC_CALL_REG, mips_gp_register);
7977 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7978 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7981 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7982 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7984 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7985 PIC_CALL_REG, PIC_CALL_REG,
7986 BFD_RELOC_MIPS_GOT_OFST);
7990 macro_build_jalr (&offset_expr, 0);
7994 relax_start (offset_expr.X_add_symbol);
7997 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7998 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8007 gpdelay = reg_needs_delay (mips_gp_register);
8008 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8009 BFD_RELOC_MIPS_CALL_HI16);
8010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8011 PIC_CALL_REG, mips_gp_register);
8012 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8013 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8018 macro_build (NULL, "nop", "");
8020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8021 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8024 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8025 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8027 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8029 if (mips_cprestore_offset < 0)
8030 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8033 if (!mips_frame_reg_valid)
8035 as_warn (_("No .frame pseudo-op used in PIC code"));
8036 /* Quiet this warning. */
8037 mips_frame_reg_valid = 1;
8039 if (!mips_cprestore_valid)
8041 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8042 /* Quiet this warning. */
8043 mips_cprestore_valid = 1;
8045 if (mips_opts.noreorder)
8046 macro_build (NULL, "nop", "");
8047 expr1.X_add_number = mips_cprestore_offset;
8048 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8051 HAVE_64BIT_ADDRESSES);
8055 else if (mips_pic == VXWORKS_PIC)
8056 as_bad (_("Non-PIC jump used in PIC library"));
8164 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8172 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8203 gas_assert (!mips_opts.micromips);
8206 /* Itbl support may require additional care here. */
8213 /* Itbl support may require additional care here. */
8221 offbits = (mips_opts.micromips ? 12 : 16);
8222 /* Itbl support may require additional care here. */
8227 gas_assert (!mips_opts.micromips);
8230 /* Itbl support may require additional care here. */
8238 offbits = (mips_opts.micromips ? 12 : 16);
8245 offbits = (mips_opts.micromips ? 12 : 16);
8251 /* Itbl support may require additional care here. */
8259 offbits = (mips_opts.micromips ? 12 : 16);
8260 /* Itbl support may require additional care here. */
8267 /* Itbl support may require additional care here. */
8274 /* Itbl support may require additional care here. */
8282 offbits = (mips_opts.micromips ? 12 : 16);
8289 offbits = (mips_opts.micromips ? 12 : 16);
8296 offbits = (mips_opts.micromips ? 12 : 16);
8303 offbits = (mips_opts.micromips ? 12 : 16);
8310 offbits = (mips_opts.micromips ? 12 : 16);
8315 gas_assert (mips_opts.micromips);
8324 gas_assert (mips_opts.micromips);
8333 gas_assert (mips_opts.micromips);
8341 gas_assert (mips_opts.micromips);
8348 /* We don't want to use $0 as tempreg. */
8349 if (breg == treg + lp || treg + lp == ZERO)
8352 tempreg = treg + lp;
8372 gas_assert (!mips_opts.micromips);
8375 /* Itbl support may require additional care here. */
8382 /* Itbl support may require additional care here. */
8390 offbits = (mips_opts.micromips ? 12 : 16);
8391 /* Itbl support may require additional care here. */
8396 gas_assert (!mips_opts.micromips);
8399 /* Itbl support may require additional care here. */
8407 offbits = (mips_opts.micromips ? 12 : 16);
8414 offbits = (mips_opts.micromips ? 12 : 16);
8421 offbits = (mips_opts.micromips ? 12 : 16);
8428 offbits = (mips_opts.micromips ? 12 : 16);
8434 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8435 offbits = (mips_opts.micromips ? 12 : 16);
8448 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8449 offbits = (mips_opts.micromips ? 12 : 16);
8463 /* Itbl support may require additional care here. */
8470 offbits = (mips_opts.micromips ? 12 : 16);
8471 /* Itbl support may require additional care here. */
8478 /* Itbl support may require additional care here. */
8483 gas_assert (!mips_opts.micromips);
8486 /* Itbl support may require additional care here. */
8494 offbits = (mips_opts.micromips ? 12 : 16);
8501 offbits = (mips_opts.micromips ? 12 : 16);
8506 gas_assert (mips_opts.micromips);
8514 gas_assert (mips_opts.micromips);
8522 gas_assert (mips_opts.micromips);
8530 gas_assert (mips_opts.micromips);
8539 if (offset_expr.X_op != O_constant
8540 && offset_expr.X_op != O_symbol)
8542 as_bad (_("Expression too complex"));
8543 offset_expr.X_op = O_constant;
8546 if (HAVE_32BIT_ADDRESSES
8547 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8551 sprintf_vma (value, offset_expr.X_add_number);
8552 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8555 /* A constant expression in PIC code can be handled just as it
8556 is in non PIC code. */
8557 if (offset_expr.X_op == O_constant)
8561 expr1.X_add_number = offset_expr.X_add_number;
8562 normalize_address_expr (&expr1);
8563 if ((offbits == 0 || offbits == 16)
8564 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8566 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8567 & ~(bfd_vma) 0xffff);
8570 else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8572 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8573 & ~(bfd_vma) 0xfff);
8576 else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number))
8578 expr1.X_add_number = ((expr1.X_add_number + 0x100)
8579 & ~(bfd_vma) 0x1ff);
8584 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8586 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8587 tempreg, tempreg, breg);
8592 if (offset_expr.X_add_number == 0)
8595 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8596 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8597 macro_build (NULL, s, fmt, treg, tempreg);
8599 else if (offbits == 16)
8600 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8602 macro_build (NULL, s, fmt,
8603 treg, (unsigned long) offset_expr.X_add_number, breg);
8605 else if (offbits != 16)
8607 /* The offset field is too narrow to be used for a low-part
8608 relocation, so load the whole address into the auxillary
8609 register. In the case of "A(b)" addresses, we first load
8610 absolute address "A" into the register and then add base
8611 register "b". In the case of "o(b)" addresses, we simply
8612 need to add 16-bit offset "o" to base register "b", and
8613 offset_reloc already contains the relocations associated
8617 load_address (tempreg, &offset_expr, &used_at);
8619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8620 tempreg, tempreg, breg);
8623 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8625 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8626 expr1.X_add_number = 0;
8628 macro_build (NULL, s, fmt, treg, tempreg);
8630 macro_build (NULL, s, fmt,
8631 treg, (unsigned long) expr1.X_add_number, tempreg);
8633 else if (mips_pic == NO_PIC)
8635 /* If this is a reference to a GP relative symbol, and there
8636 is no base register, we want
8637 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8638 Otherwise, if there is no base register, we want
8639 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8640 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8641 If we have a constant, we need two instructions anyhow,
8642 so we always use the latter form.
8644 If we have a base register, and this is a reference to a
8645 GP relative symbol, we want
8646 addu $tempreg,$breg,$gp
8647 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8649 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8650 addu $tempreg,$tempreg,$breg
8651 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8652 With a constant we always use the latter case.
8654 With 64bit address space and no base register and $at usable,
8656 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8657 lui $at,<sym> (BFD_RELOC_HI16_S)
8658 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8661 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8662 If we have a base register, we want
8663 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8664 lui $at,<sym> (BFD_RELOC_HI16_S)
8665 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8669 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8671 Without $at we can't generate the optimal path for superscalar
8672 processors here since this would require two temporary registers.
8673 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8674 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8676 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8678 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8679 If we have a base register, we want
8680 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8681 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8683 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8685 daddu $tempreg,$tempreg,$breg
8686 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8688 For GP relative symbols in 64bit address space we can use
8689 the same sequence as in 32bit address space. */
8690 if (HAVE_64BIT_SYMBOLS)
8692 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8693 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8695 relax_start (offset_expr.X_add_symbol);
8698 macro_build (&offset_expr, s, fmt, treg,
8699 BFD_RELOC_GPREL16, mips_gp_register);
8703 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8704 tempreg, breg, mips_gp_register);
8705 macro_build (&offset_expr, s, fmt, treg,
8706 BFD_RELOC_GPREL16, tempreg);
8711 if (used_at == 0 && mips_opts.at)
8713 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8714 BFD_RELOC_MIPS_HIGHEST);
8715 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8717 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8718 tempreg, BFD_RELOC_MIPS_HIGHER);
8720 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8721 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8722 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8723 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8729 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8730 BFD_RELOC_MIPS_HIGHEST);
8731 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8732 tempreg, BFD_RELOC_MIPS_HIGHER);
8733 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8734 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8735 tempreg, BFD_RELOC_HI16_S);
8736 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8738 macro_build (NULL, "daddu", "d,v,t",
8739 tempreg, tempreg, breg);
8740 macro_build (&offset_expr, s, fmt, treg,
8741 BFD_RELOC_LO16, tempreg);
8744 if (mips_relax.sequence)
8751 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8752 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8754 relax_start (offset_expr.X_add_symbol);
8755 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8759 macro_build_lui (&offset_expr, tempreg);
8760 macro_build (&offset_expr, s, fmt, treg,
8761 BFD_RELOC_LO16, tempreg);
8762 if (mips_relax.sequence)
8767 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8768 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8770 relax_start (offset_expr.X_add_symbol);
8771 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8772 tempreg, breg, mips_gp_register);
8773 macro_build (&offset_expr, s, fmt, treg,
8774 BFD_RELOC_GPREL16, tempreg);
8777 macro_build_lui (&offset_expr, tempreg);
8778 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8779 tempreg, tempreg, breg);
8780 macro_build (&offset_expr, s, fmt, treg,
8781 BFD_RELOC_LO16, tempreg);
8782 if (mips_relax.sequence)
8786 else if (!mips_big_got)
8788 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8790 /* If this is a reference to an external symbol, we want
8791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8793 <op> $treg,0($tempreg)
8795 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8797 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8798 <op> $treg,0($tempreg)
8801 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8802 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8804 If there is a base register, we add it to $tempreg before
8805 the <op>. If there is a constant, we stick it in the
8806 <op> instruction. We don't handle constants larger than
8807 16 bits, because we have no way to load the upper 16 bits
8808 (actually, we could handle them for the subset of cases
8809 in which we are not using $at). */
8810 gas_assert (offset_expr.X_op == O_symbol);
8813 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8814 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8816 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8817 tempreg, tempreg, breg);
8818 macro_build (&offset_expr, s, fmt, treg,
8819 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8822 expr1.X_add_number = offset_expr.X_add_number;
8823 offset_expr.X_add_number = 0;
8824 if (expr1.X_add_number < -0x8000
8825 || expr1.X_add_number >= 0x8000)
8826 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8827 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8828 lw_reloc_type, mips_gp_register);
8830 relax_start (offset_expr.X_add_symbol);
8832 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8833 tempreg, BFD_RELOC_LO16);
8836 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8837 tempreg, tempreg, breg);
8838 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8840 else if (mips_big_got && !HAVE_NEWABI)
8844 /* If this is a reference to an external symbol, we want
8845 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8846 addu $tempreg,$tempreg,$gp
8847 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8848 <op> $treg,0($tempreg)
8850 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8852 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8853 <op> $treg,0($tempreg)
8854 If there is a base register, we add it to $tempreg before
8855 the <op>. If there is a constant, we stick it in the
8856 <op> instruction. We don't handle constants larger than
8857 16 bits, because we have no way to load the upper 16 bits
8858 (actually, we could handle them for the subset of cases
8859 in which we are not using $at). */
8860 gas_assert (offset_expr.X_op == O_symbol);
8861 expr1.X_add_number = offset_expr.X_add_number;
8862 offset_expr.X_add_number = 0;
8863 if (expr1.X_add_number < -0x8000
8864 || expr1.X_add_number >= 0x8000)
8865 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8866 gpdelay = reg_needs_delay (mips_gp_register);
8867 relax_start (offset_expr.X_add_symbol);
8868 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8869 BFD_RELOC_MIPS_GOT_HI16);
8870 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8872 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8873 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8876 macro_build (NULL, "nop", "");
8877 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8878 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8880 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8881 tempreg, BFD_RELOC_LO16);
8885 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8886 tempreg, tempreg, breg);
8887 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8889 else if (mips_big_got && HAVE_NEWABI)
8891 /* If this is a reference to an external symbol, we want
8892 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8893 add $tempreg,$tempreg,$gp
8894 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8895 <op> $treg,<ofst>($tempreg)
8896 Otherwise, for local symbols, we want:
8897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8898 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8899 gas_assert (offset_expr.X_op == O_symbol);
8900 expr1.X_add_number = offset_expr.X_add_number;
8901 offset_expr.X_add_number = 0;
8902 if (expr1.X_add_number < -0x8000
8903 || expr1.X_add_number >= 0x8000)
8904 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8905 relax_start (offset_expr.X_add_symbol);
8906 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8907 BFD_RELOC_MIPS_GOT_HI16);
8908 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8910 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8911 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8913 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8914 tempreg, tempreg, breg);
8915 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8918 offset_expr.X_add_number = expr1.X_add_number;
8919 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8920 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8922 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8923 tempreg, tempreg, breg);
8924 macro_build (&offset_expr, s, fmt, treg,
8925 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8935 load_register (treg, &imm_expr, 0);
8939 load_register (treg, &imm_expr, 1);
8943 if (imm_expr.X_op == O_constant)
8946 load_register (AT, &imm_expr, 0);
8947 macro_build (NULL, "mtc1", "t,G", AT, treg);
8952 gas_assert (offset_expr.X_op == O_symbol
8953 && strcmp (segment_name (S_GET_SEGMENT
8954 (offset_expr.X_add_symbol)),
8956 && offset_expr.X_add_number == 0);
8957 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8958 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8963 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8964 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8965 order 32 bits of the value and the low order 32 bits are either
8966 zero or in OFFSET_EXPR. */
8967 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8969 if (HAVE_64BIT_GPRS)
8970 load_register (treg, &imm_expr, 1);
8975 if (target_big_endian)
8987 load_register (hreg, &imm_expr, 0);
8990 if (offset_expr.X_op == O_absent)
8991 move_register (lreg, 0);
8994 gas_assert (offset_expr.X_op == O_constant);
8995 load_register (lreg, &offset_expr, 0);
9002 /* We know that sym is in the .rdata section. First we get the
9003 upper 16 bits of the address. */
9004 if (mips_pic == NO_PIC)
9006 macro_build_lui (&offset_expr, AT);
9011 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9012 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9016 /* Now we load the register(s). */
9017 if (HAVE_64BIT_GPRS)
9020 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9025 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9028 /* FIXME: How in the world do we deal with the possible
9030 offset_expr.X_add_number += 4;
9031 macro_build (&offset_expr, "lw", "t,o(b)",
9032 treg + 1, BFD_RELOC_LO16, AT);
9038 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9039 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9040 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9041 the value and the low order 32 bits are either zero or in
9043 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9046 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9047 if (HAVE_64BIT_FPRS)
9049 gas_assert (HAVE_64BIT_GPRS);
9050 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9054 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9055 if (offset_expr.X_op == O_absent)
9056 macro_build (NULL, "mtc1", "t,G", 0, treg);
9059 gas_assert (offset_expr.X_op == O_constant);
9060 load_register (AT, &offset_expr, 0);
9061 macro_build (NULL, "mtc1", "t,G", AT, treg);
9067 gas_assert (offset_expr.X_op == O_symbol
9068 && offset_expr.X_add_number == 0);
9069 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9070 if (strcmp (s, ".lit8") == 0)
9072 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9074 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
9075 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9078 breg = mips_gp_register;
9079 r = BFD_RELOC_MIPS_LITERAL;
9084 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9086 if (mips_pic != NO_PIC)
9087 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9088 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9091 /* FIXME: This won't work for a 64 bit address. */
9092 macro_build_lui (&offset_expr, AT);
9095 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9097 macro_build (&offset_expr, "ldc1", "T,o(b)",
9098 treg, BFD_RELOC_LO16, AT);
9107 /* Even on a big endian machine $fn comes before $fn+1. We have
9108 to adjust when loading from memory. */
9111 gas_assert (!mips_opts.micromips);
9112 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9113 macro_build (&offset_expr, "lwc1", "T,o(b)",
9114 target_big_endian ? treg + 1 : treg, r, breg);
9115 /* FIXME: A possible overflow which I don't know how to deal
9117 offset_expr.X_add_number += 4;
9118 macro_build (&offset_expr, "lwc1", "T,o(b)",
9119 target_big_endian ? treg : treg + 1, r, breg);
9123 gas_assert (!mips_opts.micromips);
9124 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9125 /* Even on a big endian machine $fn comes before $fn+1. We have
9126 to adjust when storing to memory. */
9127 macro_build (&offset_expr, "swc1", "T,o(b)",
9128 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
9129 offset_expr.X_add_number += 4;
9130 macro_build (&offset_expr, "swc1", "T,o(b)",
9131 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
9135 gas_assert (!mips_opts.micromips);
9137 * The MIPS assembler seems to check for X_add_number not
9138 * being double aligned and generating:
9141 * addiu at,at,%lo(foo+1)
9144 * But, the resulting address is the same after relocation so why
9145 * generate the extra instruction?
9147 /* Itbl support may require additional care here. */
9150 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9159 gas_assert (!mips_opts.micromips);
9160 /* Itbl support may require additional care here. */
9163 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9183 if (HAVE_64BIT_GPRS)
9193 if (HAVE_64BIT_GPRS)
9201 if (offset_expr.X_op != O_symbol
9202 && offset_expr.X_op != O_constant)
9204 as_bad (_("Expression too complex"));
9205 offset_expr.X_op = O_constant;
9208 if (HAVE_32BIT_ADDRESSES
9209 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9213 sprintf_vma (value, offset_expr.X_add_number);
9214 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9217 /* Even on a big endian machine $fn comes before $fn+1. We have
9218 to adjust when loading from memory. We set coproc if we must
9219 load $fn+1 first. */
9220 /* Itbl support may require additional care here. */
9221 if (!target_big_endian)
9224 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9226 /* If this is a reference to a GP relative symbol, we want
9227 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9228 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9229 If we have a base register, we use this
9231 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9232 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9233 If this is not a GP relative symbol, we want
9234 lui $at,<sym> (BFD_RELOC_HI16_S)
9235 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9236 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9237 If there is a base register, we add it to $at after the
9238 lui instruction. If there is a constant, we always use
9240 if (offset_expr.X_op == O_symbol
9241 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9242 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9244 relax_start (offset_expr.X_add_symbol);
9247 tempreg = mips_gp_register;
9251 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9252 AT, breg, mips_gp_register);
9257 /* Itbl support may require additional care here. */
9258 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9259 BFD_RELOC_GPREL16, tempreg);
9260 offset_expr.X_add_number += 4;
9262 /* Set mips_optimize to 2 to avoid inserting an
9264 hold_mips_optimize = mips_optimize;
9266 /* Itbl support may require additional care here. */
9267 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9268 BFD_RELOC_GPREL16, tempreg);
9269 mips_optimize = hold_mips_optimize;
9273 offset_expr.X_add_number -= 4;
9276 macro_build_lui (&offset_expr, AT);
9278 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9279 /* Itbl support may require additional care here. */
9280 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9281 BFD_RELOC_LO16, AT);
9282 /* FIXME: How do we handle overflow here? */
9283 offset_expr.X_add_number += 4;
9284 /* Itbl support may require additional care here. */
9285 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9286 BFD_RELOC_LO16, AT);
9287 if (mips_relax.sequence)
9290 else if (!mips_big_got)
9292 /* If this is a reference to an external symbol, we want
9293 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9298 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9300 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9301 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9302 If there is a base register we add it to $at before the
9303 lwc1 instructions. If there is a constant we include it
9304 in the lwc1 instructions. */
9306 expr1.X_add_number = offset_expr.X_add_number;
9307 if (expr1.X_add_number < -0x8000
9308 || expr1.X_add_number >= 0x8000 - 4)
9309 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9310 load_got_offset (AT, &offset_expr);
9313 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9315 /* Set mips_optimize to 2 to avoid inserting an undesired
9317 hold_mips_optimize = mips_optimize;
9320 /* Itbl support may require additional care here. */
9321 relax_start (offset_expr.X_add_symbol);
9322 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9323 BFD_RELOC_LO16, AT);
9324 expr1.X_add_number += 4;
9325 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9326 BFD_RELOC_LO16, AT);
9328 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9329 BFD_RELOC_LO16, AT);
9330 offset_expr.X_add_number += 4;
9331 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9332 BFD_RELOC_LO16, AT);
9335 mips_optimize = hold_mips_optimize;
9337 else if (mips_big_got)
9341 /* If this is a reference to an external symbol, we want
9342 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9344 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9349 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9351 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9352 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9353 If there is a base register we add it to $at before the
9354 lwc1 instructions. If there is a constant we include it
9355 in the lwc1 instructions. */
9357 expr1.X_add_number = offset_expr.X_add_number;
9358 offset_expr.X_add_number = 0;
9359 if (expr1.X_add_number < -0x8000
9360 || expr1.X_add_number >= 0x8000 - 4)
9361 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9362 gpdelay = reg_needs_delay (mips_gp_register);
9363 relax_start (offset_expr.X_add_symbol);
9364 macro_build (&offset_expr, "lui", LUI_FMT,
9365 AT, BFD_RELOC_MIPS_GOT_HI16);
9366 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9367 AT, AT, mips_gp_register);
9368 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9369 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9372 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9373 /* Itbl support may require additional care here. */
9374 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9375 BFD_RELOC_LO16, AT);
9376 expr1.X_add_number += 4;
9378 /* Set mips_optimize to 2 to avoid inserting an undesired
9380 hold_mips_optimize = mips_optimize;
9382 /* Itbl support may require additional care here. */
9383 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9384 BFD_RELOC_LO16, AT);
9385 mips_optimize = hold_mips_optimize;
9386 expr1.X_add_number -= 4;
9389 offset_expr.X_add_number = expr1.X_add_number;
9391 macro_build (NULL, "nop", "");
9392 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9393 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9396 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9397 /* Itbl support may require additional care here. */
9398 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9399 BFD_RELOC_LO16, AT);
9400 offset_expr.X_add_number += 4;
9402 /* Set mips_optimize to 2 to avoid inserting an undesired
9404 hold_mips_optimize = mips_optimize;
9406 /* Itbl support may require additional care here. */
9407 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9408 BFD_RELOC_LO16, AT);
9409 mips_optimize = hold_mips_optimize;
9418 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9421 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9423 macro_build (&offset_expr, s, "t,o(b)", treg,
9424 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9426 if (!HAVE_64BIT_GPRS)
9428 offset_expr.X_add_number += 4;
9429 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9430 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9451 /* New code added to support COPZ instructions.
9452 This code builds table entries out of the macros in mip_opcodes.
9453 R4000 uses interlocks to handle coproc delays.
9454 Other chips (like the R3000) require nops to be inserted for delays.
9456 FIXME: Currently, we require that the user handle delays.
9457 In order to fill delay slots for non-interlocked chips,
9458 we must have a way to specify delays based on the coprocessor.
9459 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9460 What are the side-effects of the cop instruction?
9461 What cache support might we have and what are its effects?
9462 Both coprocessor & memory require delays. how long???
9463 What registers are read/set/modified?
9465 If an itbl is provided to interpret cop instructions,
9466 this knowledge can be encoded in the itbl spec. */
9480 gas_assert (!mips_opts.micromips);
9481 /* For now we just do C (same as Cz). The parameter will be
9482 stored in insn_opcode by mips_ip. */
9483 macro_build (NULL, s, "C", ip->insn_opcode);
9487 move_register (dreg, sreg);
9493 if (mips_opts.arch == CPU_R5900)
9495 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9499 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9500 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9507 /* The MIPS assembler some times generates shifts and adds. I'm
9508 not trying to be that fancy. GCC should do this for us
9511 load_register (AT, &imm_expr, dbl);
9512 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9513 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9529 load_register (AT, &imm_expr, dbl);
9530 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9531 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9532 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9533 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9535 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9538 if (mips_opts.micromips)
9539 micromips_label_expr (&label_expr);
9541 label_expr.X_add_number = 8;
9542 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9543 macro_build (NULL, "nop", "");
9544 macro_build (NULL, "break", BRK_FMT, 6);
9545 if (mips_opts.micromips)
9546 micromips_add_label ();
9549 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9565 load_register (AT, &imm_expr, dbl);
9566 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9567 sreg, imm ? AT : treg);
9568 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9569 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9571 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9574 if (mips_opts.micromips)
9575 micromips_label_expr (&label_expr);
9577 label_expr.X_add_number = 8;
9578 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9579 macro_build (NULL, "nop", "");
9580 macro_build (NULL, "break", BRK_FMT, 6);
9581 if (mips_opts.micromips)
9582 micromips_add_label ();
9588 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9599 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9600 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9604 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9605 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9606 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9607 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9611 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9622 macro_build (NULL, "negu", "d,w", tempreg, treg);
9623 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9627 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9628 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9629 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9630 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9639 if (imm_expr.X_op != O_constant)
9640 as_bad (_("Improper rotate count"));
9641 rot = imm_expr.X_add_number & 0x3f;
9642 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9644 rot = (64 - rot) & 0x3f;
9646 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9648 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9653 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9656 l = (rot < 0x20) ? "dsll" : "dsll32";
9657 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9660 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9661 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9662 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9670 if (imm_expr.X_op != O_constant)
9671 as_bad (_("Improper rotate count"));
9672 rot = imm_expr.X_add_number & 0x1f;
9673 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9675 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9680 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9684 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9685 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9686 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9691 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9693 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9697 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9698 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9699 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9700 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9704 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9706 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9710 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9711 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9712 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9713 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9722 if (imm_expr.X_op != O_constant)
9723 as_bad (_("Improper rotate count"));
9724 rot = imm_expr.X_add_number & 0x3f;
9725 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9728 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9730 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9735 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9738 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9739 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9742 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9743 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9744 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9752 if (imm_expr.X_op != O_constant)
9753 as_bad (_("Improper rotate count"));
9754 rot = imm_expr.X_add_number & 0x1f;
9755 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9757 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9762 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9766 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9767 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9768 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9774 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9776 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9779 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9780 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9785 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9787 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9792 as_warn (_("Instruction %s: result is always false"),
9794 move_register (dreg, 0);
9797 if (CPU_HAS_SEQ (mips_opts.arch)
9798 && -512 <= imm_expr.X_add_number
9799 && imm_expr.X_add_number < 512)
9801 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9802 (int) imm_expr.X_add_number);
9805 if (imm_expr.X_op == O_constant
9806 && imm_expr.X_add_number >= 0
9807 && imm_expr.X_add_number < 0x10000)
9809 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9811 else if (imm_expr.X_op == O_constant
9812 && imm_expr.X_add_number > -0x8000
9813 && imm_expr.X_add_number < 0)
9815 imm_expr.X_add_number = -imm_expr.X_add_number;
9816 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9817 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9819 else if (CPU_HAS_SEQ (mips_opts.arch))
9822 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9823 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9828 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9829 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9832 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9835 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9841 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9842 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9845 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9847 if (imm_expr.X_op == O_constant
9848 && imm_expr.X_add_number >= -0x8000
9849 && imm_expr.X_add_number < 0x8000)
9851 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9852 dreg, sreg, BFD_RELOC_LO16);
9856 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9857 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9861 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9864 case M_SGT: /* sreg > treg <==> treg < sreg */
9870 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9873 case M_SGT_I: /* sreg > I <==> I < sreg */
9880 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9881 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9884 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9890 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9891 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9894 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9901 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9902 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9903 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9907 if (imm_expr.X_op == O_constant
9908 && imm_expr.X_add_number >= -0x8000
9909 && imm_expr.X_add_number < 0x8000)
9911 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9915 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9916 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9920 if (imm_expr.X_op == O_constant
9921 && imm_expr.X_add_number >= -0x8000
9922 && imm_expr.X_add_number < 0x8000)
9924 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9929 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9930 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9935 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9937 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9940 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9941 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9946 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9948 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9953 as_warn (_("Instruction %s: result is always true"),
9955 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9956 dreg, 0, BFD_RELOC_LO16);
9959 if (CPU_HAS_SEQ (mips_opts.arch)
9960 && -512 <= imm_expr.X_add_number
9961 && imm_expr.X_add_number < 512)
9963 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9964 (int) imm_expr.X_add_number);
9967 if (imm_expr.X_op == O_constant
9968 && imm_expr.X_add_number >= 0
9969 && imm_expr.X_add_number < 0x10000)
9971 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9973 else if (imm_expr.X_op == O_constant
9974 && imm_expr.X_add_number > -0x8000
9975 && imm_expr.X_add_number < 0)
9977 imm_expr.X_add_number = -imm_expr.X_add_number;
9978 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9979 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9981 else if (CPU_HAS_SEQ (mips_opts.arch))
9984 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9985 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9990 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9991 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9994 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10009 if (!mips_opts.micromips)
10011 if (imm_expr.X_op == O_constant
10012 && imm_expr.X_add_number > -0x200
10013 && imm_expr.X_add_number <= 0x200)
10015 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10024 if (imm_expr.X_op == O_constant
10025 && imm_expr.X_add_number > -0x8000
10026 && imm_expr.X_add_number <= 0x8000)
10028 imm_expr.X_add_number = -imm_expr.X_add_number;
10029 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10034 load_register (AT, &imm_expr, dbl);
10035 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10057 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10058 macro_build (NULL, s, "s,t", sreg, AT);
10063 gas_assert (!mips_opts.micromips);
10064 gas_assert (mips_opts.isa == ISA_MIPS1);
10066 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10067 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10070 * Is the double cfc1 instruction a bug in the mips assembler;
10071 * or is there a reason for it?
10073 start_noreorder ();
10074 macro_build (NULL, "cfc1", "t,G", treg, RA);
10075 macro_build (NULL, "cfc1", "t,G", treg, RA);
10076 macro_build (NULL, "nop", "");
10077 expr1.X_add_number = 3;
10078 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10079 expr1.X_add_number = 2;
10080 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10081 macro_build (NULL, "ctc1", "t,G", AT, RA);
10082 macro_build (NULL, "nop", "");
10083 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10085 macro_build (NULL, "ctc1", "t,G", treg, RA);
10086 macro_build (NULL, "nop", "");
10109 offbits = (mips_opts.micromips ? 12 : 16);
10117 offbits = (mips_opts.micromips ? 12 : 16);
10133 offbits = (mips_opts.micromips ? 12 : 16);
10142 offbits = (mips_opts.micromips ? 12 : 16);
10147 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10148 as_bad (_("Operand overflow"));
10151 expr1.X_add_number = 0;
10156 load_address (tempreg, ep, &used_at);
10158 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10159 tempreg, tempreg, breg);
10164 else if (offbits == 12
10165 && (offset_expr.X_op != O_constant
10166 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10167 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10171 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10172 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10177 else if (!ust && treg == breg)
10188 if (!target_big_endian)
10189 ep->X_add_number += off;
10191 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10193 macro_build (NULL, s, "t,~(b)",
10194 tempreg, (unsigned long) ep->X_add_number, breg);
10196 if (!target_big_endian)
10197 ep->X_add_number -= off;
10199 ep->X_add_number += off;
10201 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10203 macro_build (NULL, s2, "t,~(b)",
10204 tempreg, (unsigned long) ep->X_add_number, breg);
10206 /* If necessary, move the result in tempreg to the final destination. */
10207 if (!ust && treg != tempreg)
10209 /* Protect second load's delay slot. */
10211 move_register (treg, tempreg);
10217 if (target_big_endian == ust)
10218 ep->X_add_number += off;
10219 tempreg = ust || ab ? treg : AT;
10220 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10222 /* For halfword transfers we need a temporary register to shuffle
10223 bytes. Unfortunately for M_USH_A we have none available before
10224 the next store as AT holds the base address. We deal with this
10225 case by clobbering TREG and then restoring it as with ULH. */
10226 tempreg = ust == ab ? treg : AT;
10228 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10230 if (target_big_endian == ust)
10231 ep->X_add_number -= off;
10233 ep->X_add_number += off;
10234 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10236 /* For M_USH_A re-retrieve the LSB. */
10239 if (target_big_endian)
10240 ep->X_add_number += off;
10242 ep->X_add_number -= off;
10243 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10245 /* For ULH and M_USH_A OR the LSB in. */
10248 tempreg = !ab ? AT : treg;
10249 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10250 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10255 /* FIXME: Check if this is one of the itbl macros, since they
10256 are added dynamically. */
10257 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10260 if (!mips_opts.at && used_at)
10261 as_bad (_("Macro used $at after \".set noat\""));
10264 /* Implement macros in mips16 mode. */
10267 mips16_macro (struct mips_cl_insn *ip)
10270 int xreg, yreg, zreg, tmp;
10273 const char *s, *s2, *s3;
10275 mask = ip->insn_mo->mask;
10277 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10278 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10279 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10281 expr1.X_op = O_constant;
10282 expr1.X_op_symbol = NULL;
10283 expr1.X_add_symbol = NULL;
10284 expr1.X_add_number = 1;
10303 start_noreorder ();
10304 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10305 expr1.X_add_number = 2;
10306 macro_build (&expr1, "bnez", "x,p", yreg);
10307 macro_build (NULL, "break", "6", 7);
10309 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10310 since that causes an overflow. We should do that as well,
10311 but I don't see how to do the comparisons without a temporary
10314 macro_build (NULL, s, "x", zreg);
10333 start_noreorder ();
10334 macro_build (NULL, s, "0,x,y", xreg, yreg);
10335 expr1.X_add_number = 2;
10336 macro_build (&expr1, "bnez", "x,p", yreg);
10337 macro_build (NULL, "break", "6", 7);
10339 macro_build (NULL, s2, "x", zreg);
10345 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10346 macro_build (NULL, "mflo", "x", zreg);
10354 if (imm_expr.X_op != O_constant)
10355 as_bad (_("Unsupported large constant"));
10356 imm_expr.X_add_number = -imm_expr.X_add_number;
10357 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10361 if (imm_expr.X_op != O_constant)
10362 as_bad (_("Unsupported large constant"));
10363 imm_expr.X_add_number = -imm_expr.X_add_number;
10364 macro_build (&imm_expr, "addiu", "x,k", xreg);
10368 if (imm_expr.X_op != O_constant)
10369 as_bad (_("Unsupported large constant"));
10370 imm_expr.X_add_number = -imm_expr.X_add_number;
10371 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10393 goto do_reverse_branch;
10397 goto do_reverse_branch;
10409 goto do_reverse_branch;
10420 macro_build (NULL, s, "x,y", xreg, yreg);
10421 macro_build (&offset_expr, s2, "p");
10448 goto do_addone_branch_i;
10453 goto do_addone_branch_i;
10468 goto do_addone_branch_i;
10474 do_addone_branch_i:
10475 if (imm_expr.X_op != O_constant)
10476 as_bad (_("Unsupported large constant"));
10477 ++imm_expr.X_add_number;
10480 macro_build (&imm_expr, s, s3, xreg);
10481 macro_build (&offset_expr, s2, "p");
10485 expr1.X_add_number = 0;
10486 macro_build (&expr1, "slti", "x,8", yreg);
10488 move_register (xreg, yreg);
10489 expr1.X_add_number = 2;
10490 macro_build (&expr1, "bteqz", "p");
10491 macro_build (NULL, "neg", "x,w", xreg, xreg);
10495 /* For consistency checking, verify that all bits are specified either
10496 by the match/mask part of the instruction definition, or by the
10499 validate_mips_insn (const struct mips_opcode *opc)
10501 const char *p = opc->args;
10503 unsigned long used_bits = opc->mask;
10505 if ((used_bits & opc->match) != opc->match)
10507 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10508 opc->name, opc->args);
10511 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10521 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10522 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10523 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10524 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10525 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10526 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10527 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10528 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10529 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10530 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10531 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10532 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10533 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10535 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10536 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10537 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10538 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10539 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10540 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10541 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10542 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10543 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10544 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10545 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10546 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10547 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10548 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10549 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10550 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10551 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10554 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10555 c, opc->name, opc->args);
10559 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10560 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10562 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10563 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10564 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10565 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10567 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10568 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10570 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10571 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10573 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10574 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10575 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10576 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10577 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10578 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10579 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10580 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10581 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10582 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10583 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10584 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10585 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10586 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10587 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10588 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10589 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10591 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10592 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10593 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10594 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10596 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10597 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10598 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10599 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10600 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10601 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10602 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10603 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10604 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10607 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10608 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10609 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10610 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10611 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10614 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10615 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10616 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10617 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10618 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10619 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10620 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10621 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10622 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10623 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10624 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10625 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10626 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10627 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10628 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10629 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10630 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10631 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10632 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10633 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10635 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10636 c, opc->name, opc->args);
10640 if (used_bits != 0xffffffff)
10642 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10643 ~used_bits & 0xffffffff, opc->name, opc->args);
10649 /* For consistency checking, verify that the length implied matches the
10650 major opcode and that all bits are specified either by the match/mask
10651 part of the instruction definition, or by the operand list. */
10654 validate_micromips_insn (const struct mips_opcode *opc)
10656 unsigned long match = opc->match;
10657 unsigned long mask = opc->mask;
10658 const char *p = opc->args;
10659 unsigned long insn_bits;
10660 unsigned long used_bits;
10661 unsigned long major;
10662 unsigned int length;
10666 if ((mask & match) != match)
10668 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10669 opc->name, opc->args);
10672 length = micromips_insn_length (opc);
10673 if (length != 2 && length != 4)
10675 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10676 "%s %s"), length, opc->name, opc->args);
10679 major = match >> (10 + 8 * (length - 2));
10680 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10681 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10683 as_bad (_("Internal error: bad microMIPS opcode "
10684 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10688 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10689 insn_bits = 1 << 4 * length;
10690 insn_bits <<= 4 * length;
10693 #define USE_BITS(field) \
10694 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10705 case 'A': USE_BITS (EXTLSB); break;
10706 case 'B': USE_BITS (INSMSB); break;
10707 case 'C': USE_BITS (EXTMSBD); break;
10708 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10709 case 'E': USE_BITS (EXTLSB); break;
10710 case 'F': USE_BITS (INSMSB); break;
10711 case 'G': USE_BITS (EXTMSBD); break;
10712 case 'H': USE_BITS (EXTMSBD); break;
10713 case 'j': USE_BITS (EVAOFFSET); break;
10715 as_bad (_("Internal error: bad mips opcode "
10716 "(unknown extension operand type `%c%c'): %s %s"),
10717 e, c, opc->name, opc->args);
10725 case 'A': USE_BITS (IMMA); break;
10726 case 'B': USE_BITS (IMMB); break;
10727 case 'C': USE_BITS (IMMC); break;
10728 case 'D': USE_BITS (IMMD); break;
10729 case 'E': USE_BITS (IMME); break;
10730 case 'F': USE_BITS (IMMF); break;
10731 case 'G': USE_BITS (IMMG); break;
10732 case 'H': USE_BITS (IMMH); break;
10733 case 'I': USE_BITS (IMMI); break;
10734 case 'J': USE_BITS (IMMJ); break;
10735 case 'L': USE_BITS (IMML); break;
10736 case 'M': USE_BITS (IMMM); break;
10737 case 'N': USE_BITS (IMMN); break;
10738 case 'O': USE_BITS (IMMO); break;
10739 case 'P': USE_BITS (IMMP); break;
10740 case 'Q': USE_BITS (IMMQ); break;
10741 case 'U': USE_BITS (IMMU); break;
10742 case 'W': USE_BITS (IMMW); break;
10743 case 'X': USE_BITS (IMMX); break;
10744 case 'Y': USE_BITS (IMMY); break;
10747 case 'b': USE_BITS (MB); break;
10748 case 'c': USE_BITS (MC); break;
10749 case 'd': USE_BITS (MD); break;
10750 case 'e': USE_BITS (ME); break;
10751 case 'f': USE_BITS (MF); break;
10752 case 'g': USE_BITS (MG); break;
10753 case 'h': USE_BITS (MH); break;
10754 case 'i': USE_BITS (MI); break;
10755 case 'j': USE_BITS (MJ); break;
10756 case 'l': USE_BITS (ML); break;
10757 case 'm': USE_BITS (MM); break;
10758 case 'n': USE_BITS (MN); break;
10759 case 'p': USE_BITS (MP); break;
10760 case 'q': USE_BITS (MQ); break;
10768 as_bad (_("Internal error: bad mips opcode "
10769 "(unknown extension operand type `%c%c'): %s %s"),
10770 e, c, opc->name, opc->args);
10774 case '.': USE_BITS (OFFSET10); break;
10775 case '1': USE_BITS (STYPE); break;
10776 case '2': USE_BITS (BP); break;
10777 case '3': USE_BITS (SA3); break;
10778 case '4': USE_BITS (SA4); break;
10779 case '5': USE_BITS (IMM8); break;
10780 case '6': USE_BITS (RS); break;
10781 case '7': USE_BITS (DSPACC); break;
10782 case '8': USE_BITS (WRDSP); break;
10783 case '0': USE_BITS (DSPSFT); break;
10784 case '<': USE_BITS (SHAMT); break;
10785 case '>': USE_BITS (SHAMT); break;
10786 case '@': USE_BITS (IMM10); break;
10787 case 'B': USE_BITS (CODE10); break;
10788 case 'C': USE_BITS (COPZ); break;
10789 case 'D': USE_BITS (FD); break;
10790 case 'E': USE_BITS (RT); break;
10791 case 'G': USE_BITS (RS); break;
10792 case 'H': USE_BITS (SEL); break;
10793 case 'K': USE_BITS (RS); break;
10794 case 'M': USE_BITS (CCC); break;
10795 case 'N': USE_BITS (BCC); break;
10796 case 'R': USE_BITS (FR); break;
10797 case 'S': USE_BITS (FS); break;
10798 case 'T': USE_BITS (FT); break;
10799 case 'V': USE_BITS (FS); break;
10800 case '\\': USE_BITS (3BITPOS); break;
10801 case '^': USE_BITS (RD); break;
10802 case 'a': USE_BITS (TARGET); break;
10803 case 'b': USE_BITS (RS); break;
10804 case 'c': USE_BITS (CODE); break;
10805 case 'd': USE_BITS (RD); break;
10806 case 'h': USE_BITS (PREFX); break;
10807 case 'i': USE_BITS (IMMEDIATE); break;
10808 case 'j': USE_BITS (DELTA); break;
10809 case 'k': USE_BITS (CACHE); break;
10810 case 'n': USE_BITS (RT); break;
10811 case 'o': USE_BITS (DELTA); break;
10812 case 'p': USE_BITS (DELTA); break;
10813 case 'q': USE_BITS (CODE2); break;
10814 case 'r': USE_BITS (RS); break;
10815 case 's': USE_BITS (RS); break;
10816 case 't': USE_BITS (RT); break;
10817 case 'u': USE_BITS (IMMEDIATE); break;
10818 case 'v': USE_BITS (RS); break;
10819 case 'w': USE_BITS (RT); break;
10820 case 'y': USE_BITS (RS3); break;
10822 case '|': USE_BITS (TRAP); break;
10823 case '~': USE_BITS (OFFSET12); break;
10825 as_bad (_("Internal error: bad microMIPS opcode "
10826 "(unknown operand type `%c'): %s %s"),
10827 c, opc->name, opc->args);
10831 if (used_bits != insn_bits)
10833 if (~used_bits & insn_bits)
10834 as_bad (_("Internal error: bad microMIPS opcode "
10835 "(bits 0x%lx undefined): %s %s"),
10836 ~used_bits & insn_bits, opc->name, opc->args);
10837 if (used_bits & ~insn_bits)
10838 as_bad (_("Internal error: bad microMIPS opcode "
10839 "(bits 0x%lx defined): %s %s"),
10840 used_bits & ~insn_bits, opc->name, opc->args);
10846 /* UDI immediates. */
10847 struct mips_immed {
10849 unsigned int shift;
10850 unsigned long mask;
10854 static const struct mips_immed mips_immed[] = {
10855 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10856 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10857 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10858 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10862 /* Check whether an odd floating-point register is allowed. */
10864 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10866 const char *s = insn->name;
10868 if (insn->pinfo == INSN_MACRO)
10869 /* Let a macro pass, we'll catch it later when it is expanded. */
10872 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10874 /* Allow odd registers for single-precision ops. */
10875 switch (insn->pinfo & (FP_S | FP_D))
10879 return 1; /* both single precision - ok */
10881 return 0; /* both double precision - fail */
10886 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10887 s = strchr (insn->name, '.');
10889 s = s != NULL ? strchr (s + 1, '.') : NULL;
10890 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10893 /* Single-precision coprocessor loads and moves are OK too. */
10894 if ((insn->pinfo & FP_S)
10895 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10896 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10902 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10903 taking bits from BIT up. */
10905 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10907 return (ep->X_op == O_constant
10908 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10909 && ep->X_add_number >= min << bit
10910 && ep->X_add_number < max << bit);
10913 /* This routine assembles an instruction into its binary format. As a
10914 side effect, it sets one of the global variables imm_reloc or
10915 offset_reloc to the type of relocation to do if one of the operands
10916 is an address expression. */
10919 mips_ip (char *str, struct mips_cl_insn *ip)
10921 bfd_boolean wrong_delay_slot_insns = FALSE;
10922 bfd_boolean need_delay_slot_ok = TRUE;
10923 struct mips_opcode *firstinsn = NULL;
10924 const struct mips_opcode *past;
10925 struct hash_control *hash;
10929 struct mips_opcode *insn;
10931 unsigned int regno;
10932 unsigned int lastregno;
10933 unsigned int destregno = 0;
10934 unsigned int lastpos = 0;
10935 unsigned int limlo, limhi;
10938 offsetT min_range, max_range;
10942 unsigned int rtype;
10948 if (mips_opts.micromips)
10950 hash = micromips_op_hash;
10951 past = µmips_opcodes[bfd_micromips_num_opcodes];
10956 past = &mips_opcodes[NUMOPCODES];
10958 forced_insn_length = 0;
10961 /* We first try to match an instruction up to a space or to the end. */
10962 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10965 /* Make a copy of the instruction so that we can fiddle with it. */
10966 name = alloca (end + 1);
10967 memcpy (name, str, end);
10972 insn = (struct mips_opcode *) hash_find (hash, name);
10974 if (insn != NULL || !mips_opts.micromips)
10976 if (forced_insn_length)
10979 /* See if there's an instruction size override suffix,
10980 either `16' or `32', at the end of the mnemonic proper,
10981 that defines the operation, i.e. before the first `.'
10982 character if any. Strip it and retry. */
10983 dot = strchr (name, '.');
10984 opend = dot != NULL ? dot - name : end;
10987 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10988 forced_insn_length = 2;
10989 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10990 forced_insn_length = 4;
10993 memcpy (name + opend - 2, name + opend, end - opend + 1);
10997 insn_error = _("Unrecognized opcode");
11001 /* For microMIPS instructions placed in a fixed-length branch delay slot
11002 we make up to two passes over the relevant fragment of the opcode
11003 table. First we try instructions that meet the delay slot's length
11004 requirement. If none matched, then we retry with the remaining ones
11005 and if one matches, then we use it and then issue an appropriate
11006 warning later on. */
11007 argsStart = s = str + end;
11010 bfd_boolean delay_slot_ok;
11011 bfd_boolean size_ok;
11014 gas_assert (strcmp (insn->name, name) == 0);
11016 ok = is_opcode_valid (insn);
11017 size_ok = is_size_valid (insn);
11018 delay_slot_ok = is_delay_slot_valid (insn);
11019 if (!delay_slot_ok && !wrong_delay_slot_insns)
11022 wrong_delay_slot_insns = TRUE;
11024 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11026 static char buf[256];
11028 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11033 if (wrong_delay_slot_insns && need_delay_slot_ok)
11035 gas_assert (firstinsn);
11036 need_delay_slot_ok = FALSE;
11046 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11047 mips_cpu_info_from_arch (mips_opts.arch)->name,
11048 mips_cpu_info_from_isa (mips_opts.isa)->name);
11050 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11051 8 * forced_insn_length);
11057 create_insn (ip, insn);
11060 lastregno = 0xffffffff;
11061 for (args = insn->args;; ++args)
11065 s += strspn (s, " \t");
11069 case '\0': /* end of args */
11075 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11076 code) or 14 (for microMIPS code). */
11077 my_getExpression (&imm_expr, s);
11078 check_absolute_expr (ip, &imm_expr);
11079 if ((unsigned long) imm_expr.X_add_number != 1
11080 && (unsigned long) imm_expr.X_add_number != 3)
11082 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11083 (unsigned long) imm_expr.X_add_number);
11085 INSERT_OPERAND (mips_opts.micromips,
11086 BP, *ip, imm_expr.X_add_number);
11087 imm_expr.X_op = O_absent;
11092 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11093 code) or 21 (for microMIPS code). */
11095 unsigned long mask = (mips_opts.micromips
11096 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11098 my_getExpression (&imm_expr, s);
11099 check_absolute_expr (ip, &imm_expr);
11100 if ((unsigned long) imm_expr.X_add_number > mask)
11101 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11102 mask, (unsigned long) imm_expr.X_add_number);
11103 INSERT_OPERAND (mips_opts.micromips,
11104 SA3, *ip, imm_expr.X_add_number);
11105 imm_expr.X_op = O_absent;
11111 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11112 code) or 21 (for microMIPS code). */
11114 unsigned long mask = (mips_opts.micromips
11115 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11117 my_getExpression (&imm_expr, s);
11118 check_absolute_expr (ip, &imm_expr);
11119 if ((unsigned long) imm_expr.X_add_number > mask)
11120 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11121 mask, (unsigned long) imm_expr.X_add_number);
11122 INSERT_OPERAND (mips_opts.micromips,
11123 SA4, *ip, imm_expr.X_add_number);
11124 imm_expr.X_op = O_absent;
11130 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11131 code) or 16 (for microMIPS code). */
11133 unsigned long mask = (mips_opts.micromips
11134 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11136 my_getExpression (&imm_expr, s);
11137 check_absolute_expr (ip, &imm_expr);
11138 if ((unsigned long) imm_expr.X_add_number > mask)
11139 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11140 mask, (unsigned long) imm_expr.X_add_number);
11141 INSERT_OPERAND (mips_opts.micromips,
11142 IMM8, *ip, imm_expr.X_add_number);
11143 imm_expr.X_op = O_absent;
11149 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11150 code) or 21 (for microMIPS code). */
11152 unsigned long mask = (mips_opts.micromips
11153 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11155 my_getExpression (&imm_expr, s);
11156 check_absolute_expr (ip, &imm_expr);
11157 if ((unsigned long) imm_expr.X_add_number > mask)
11158 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11159 mask, (unsigned long) imm_expr.X_add_number);
11160 INSERT_OPERAND (mips_opts.micromips,
11161 RS, *ip, imm_expr.X_add_number);
11162 imm_expr.X_op = O_absent;
11167 case '7': /* Four DSP accumulators in bits 11,12. */
11168 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11169 && s[3] >= '0' && s[3] <= '3')
11171 regno = s[3] - '0';
11173 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11177 as_bad (_("Invalid dsp acc register"));
11181 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11182 code) or 14 (for microMIPS code). */
11184 unsigned long mask = (mips_opts.micromips
11185 ? MICROMIPSOP_MASK_WRDSP
11188 my_getExpression (&imm_expr, s);
11189 check_absolute_expr (ip, &imm_expr);
11190 if ((unsigned long) imm_expr.X_add_number > mask)
11191 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11192 mask, (unsigned long) imm_expr.X_add_number);
11193 INSERT_OPERAND (mips_opts.micromips,
11194 WRDSP, *ip, imm_expr.X_add_number);
11195 imm_expr.X_op = O_absent;
11200 case '9': /* Four DSP accumulators in bits 21,22. */
11201 gas_assert (!mips_opts.micromips);
11202 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11203 && s[3] >= '0' && s[3] <= '3')
11205 regno = s[3] - '0';
11207 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11211 as_bad (_("Invalid dsp acc register"));
11215 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11216 code) or 20 (for microMIPS code). */
11218 long mask = (mips_opts.micromips
11219 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11221 my_getExpression (&imm_expr, s);
11222 check_absolute_expr (ip, &imm_expr);
11223 min_range = -((mask + 1) >> 1);
11224 max_range = ((mask + 1) >> 1) - 1;
11225 if (imm_expr.X_add_number < min_range
11226 || imm_expr.X_add_number > max_range)
11227 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11228 (long) min_range, (long) max_range,
11229 (long) imm_expr.X_add_number);
11230 INSERT_OPERAND (mips_opts.micromips,
11231 DSPSFT, *ip, imm_expr.X_add_number);
11232 imm_expr.X_op = O_absent;
11237 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11238 gas_assert (!mips_opts.micromips);
11239 my_getExpression (&imm_expr, s);
11240 check_absolute_expr (ip, &imm_expr);
11241 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11243 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11245 (unsigned long) imm_expr.X_add_number);
11247 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11248 imm_expr.X_op = O_absent;
11252 case ':': /* DSP 7-bit signed immediate in bit 19. */
11253 gas_assert (!mips_opts.micromips);
11254 my_getExpression (&imm_expr, s);
11255 check_absolute_expr (ip, &imm_expr);
11256 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11257 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11258 if (imm_expr.X_add_number < min_range ||
11259 imm_expr.X_add_number > max_range)
11261 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11262 (long) min_range, (long) max_range,
11263 (long) imm_expr.X_add_number);
11265 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11266 imm_expr.X_op = O_absent;
11270 case '@': /* DSP 10-bit signed immediate in bit 16. */
11272 long mask = (mips_opts.micromips
11273 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11275 my_getExpression (&imm_expr, s);
11276 check_absolute_expr (ip, &imm_expr);
11277 min_range = -((mask + 1) >> 1);
11278 max_range = ((mask + 1) >> 1) - 1;
11279 if (imm_expr.X_add_number < min_range
11280 || imm_expr.X_add_number > max_range)
11281 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11282 (long) min_range, (long) max_range,
11283 (long) imm_expr.X_add_number);
11284 INSERT_OPERAND (mips_opts.micromips,
11285 IMM10, *ip, imm_expr.X_add_number);
11286 imm_expr.X_op = O_absent;
11291 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11292 gas_assert (mips_opts.micromips);
11293 my_getExpression (&imm_expr, s);
11294 check_absolute_expr (ip, &imm_expr);
11295 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11296 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11297 MICROMIPSOP_MASK_RD,
11298 (unsigned long) imm_expr.X_add_number);
11299 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11300 imm_expr.X_op = O_absent;
11304 case '!': /* MT usermode flag bit. */
11305 gas_assert (!mips_opts.micromips);
11306 my_getExpression (&imm_expr, s);
11307 check_absolute_expr (ip, &imm_expr);
11308 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11309 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11310 (unsigned long) imm_expr.X_add_number);
11311 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11312 imm_expr.X_op = O_absent;
11316 case '$': /* MT load high flag bit. */
11317 gas_assert (!mips_opts.micromips);
11318 my_getExpression (&imm_expr, s);
11319 check_absolute_expr (ip, &imm_expr);
11320 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11321 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11322 (unsigned long) imm_expr.X_add_number);
11323 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11324 imm_expr.X_op = O_absent;
11328 case '*': /* Four DSP accumulators in bits 18,19. */
11329 gas_assert (!mips_opts.micromips);
11330 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11331 s[3] >= '0' && s[3] <= '3')
11333 regno = s[3] - '0';
11335 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11339 as_bad (_("Invalid dsp/smartmips acc register"));
11342 case '&': /* Four DSP accumulators in bits 13,14. */
11343 gas_assert (!mips_opts.micromips);
11344 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11345 s[3] >= '0' && s[3] <= '3')
11347 regno = s[3] - '0';
11349 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11353 as_bad (_("Invalid dsp/smartmips acc register"));
11356 case '\\': /* 3-bit bit position. */
11358 unsigned long mask = (mips_opts.micromips
11359 ? MICROMIPSOP_MASK_3BITPOS
11360 : OP_MASK_3BITPOS);
11362 my_getExpression (&imm_expr, s);
11363 check_absolute_expr (ip, &imm_expr);
11364 if ((unsigned long) imm_expr.X_add_number > mask)
11365 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11367 mask, (unsigned long) imm_expr.X_add_number);
11368 INSERT_OPERAND (mips_opts.micromips,
11369 3BITPOS, *ip, imm_expr.X_add_number);
11370 imm_expr.X_op = O_absent;
11384 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11388 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11392 gas_assert (!mips_opts.micromips);
11393 INSERT_OPERAND (0, FT, *ip, lastregno);
11397 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11403 /* Handle optional base register.
11404 Either the base register is omitted or
11405 we must have a left paren. */
11406 /* This is dependent on the next operand specifier
11407 is a base register specification. */
11408 gas_assert (args[1] == 'b'
11409 || (mips_opts.micromips
11411 && (args[2] == 'l' || args[2] == 'n'
11412 || args[2] == 's' || args[2] == 'a')));
11413 if (*s == '\0' && args[1] == 'b')
11415 /* Fall through. */
11417 case ')': /* These must match exactly. */
11422 case '[': /* These must match exactly. */
11424 gas_assert (!mips_opts.micromips);
11429 case '+': /* Opcode extension character. */
11432 case '1': /* UDI immediates. */
11436 gas_assert (!mips_opts.micromips);
11438 const struct mips_immed *imm = mips_immed;
11440 while (imm->type && imm->type != *args)
11444 my_getExpression (&imm_expr, s);
11445 check_absolute_expr (ip, &imm_expr);
11446 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11448 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11449 imm->desc ? imm->desc : ip->insn_mo->name,
11450 (unsigned long) imm_expr.X_add_number,
11451 (unsigned long) imm_expr.X_add_number);
11452 imm_expr.X_add_number &= imm->mask;
11454 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11456 imm_expr.X_op = O_absent;
11461 case 'J': /* 10-bit hypcall code. */
11462 gas_assert (!mips_opts.micromips);
11464 unsigned long mask = OP_MASK_CODE10;
11466 my_getExpression (&imm_expr, s);
11467 check_absolute_expr (ip, &imm_expr);
11468 if ((unsigned long) imm_expr.X_add_number > mask)
11469 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11471 mask, (unsigned long) imm_expr.X_add_number);
11472 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11473 imm_expr.X_op = O_absent;
11478 case 'A': /* ins/ext position, becomes LSB. */
11487 my_getExpression (&imm_expr, s);
11488 check_absolute_expr (ip, &imm_expr);
11489 if ((unsigned long) imm_expr.X_add_number < limlo
11490 || (unsigned long) imm_expr.X_add_number > limhi)
11492 as_bad (_("Improper position (%lu)"),
11493 (unsigned long) imm_expr.X_add_number);
11494 imm_expr.X_add_number = limlo;
11496 lastpos = imm_expr.X_add_number;
11497 INSERT_OPERAND (mips_opts.micromips,
11498 EXTLSB, *ip, imm_expr.X_add_number);
11499 imm_expr.X_op = O_absent;
11503 case 'B': /* ins size, becomes MSB. */
11512 my_getExpression (&imm_expr, s);
11513 check_absolute_expr (ip, &imm_expr);
11514 /* Check for negative input so that small negative numbers
11515 will not succeed incorrectly. The checks against
11516 (pos+size) transitively check "size" itself,
11517 assuming that "pos" is reasonable. */
11518 if ((long) imm_expr.X_add_number < 0
11519 || ((unsigned long) imm_expr.X_add_number
11521 || ((unsigned long) imm_expr.X_add_number
11522 + lastpos) > limhi)
11524 as_bad (_("Improper insert size (%lu, position %lu)"),
11525 (unsigned long) imm_expr.X_add_number,
11526 (unsigned long) lastpos);
11527 imm_expr.X_add_number = limlo - lastpos;
11529 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11530 lastpos + imm_expr.X_add_number - 1);
11531 imm_expr.X_op = O_absent;
11535 case 'C': /* ext size, becomes MSBD. */
11551 my_getExpression (&imm_expr, s);
11552 check_absolute_expr (ip, &imm_expr);
11553 /* The checks against (pos+size) don't transitively check
11554 "size" itself, assuming that "pos" is reasonable.
11555 We also need to check the lower bound of "size". */
11556 if ((long) imm_expr.X_add_number < sizelo
11557 || ((unsigned long) imm_expr.X_add_number
11559 || ((unsigned long) imm_expr.X_add_number
11560 + lastpos) > limhi)
11562 as_bad (_("Improper extract size (%lu, position %lu)"),
11563 (unsigned long) imm_expr.X_add_number,
11564 (unsigned long) lastpos);
11565 imm_expr.X_add_number = limlo - lastpos;
11567 INSERT_OPERAND (mips_opts.micromips,
11568 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11569 imm_expr.X_op = O_absent;
11574 /* +D is for disassembly only; never match. */
11578 /* "+I" is like "I", except that imm2_expr is used. */
11579 my_getExpression (&imm2_expr, s);
11580 if (imm2_expr.X_op != O_big
11581 && imm2_expr.X_op != O_constant)
11582 insn_error = _("absolute expression required");
11583 if (HAVE_32BIT_GPRS)
11584 normalize_constant_expr (&imm2_expr);
11588 case 'T': /* Coprocessor register. */
11589 gas_assert (!mips_opts.micromips);
11590 /* +T is for disassembly only; never match. */
11593 case 't': /* Coprocessor register number. */
11594 gas_assert (!mips_opts.micromips);
11595 if (s[0] == '$' && ISDIGIT (s[1]))
11605 while (ISDIGIT (*s));
11607 as_bad (_("Invalid register number (%d)"), regno);
11610 INSERT_OPERAND (0, RT, *ip, regno);
11615 as_bad (_("Invalid coprocessor 0 register number"));
11619 /* bbit[01] and bbit[01]32 bit index. Give error if index
11620 is not in the valid range. */
11621 gas_assert (!mips_opts.micromips);
11622 my_getExpression (&imm_expr, s);
11623 check_absolute_expr (ip, &imm_expr);
11624 if ((unsigned) imm_expr.X_add_number > 31)
11626 as_bad (_("Improper bit index (%lu)"),
11627 (unsigned long) imm_expr.X_add_number);
11628 imm_expr.X_add_number = 0;
11630 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11631 imm_expr.X_op = O_absent;
11636 /* bbit[01] bit index when bbit is used but we generate
11637 bbit[01]32 because the index is over 32. Move to the
11638 next candidate if index is not in the valid range. */
11639 gas_assert (!mips_opts.micromips);
11640 my_getExpression (&imm_expr, s);
11641 check_absolute_expr (ip, &imm_expr);
11642 if ((unsigned) imm_expr.X_add_number < 32
11643 || (unsigned) imm_expr.X_add_number > 63)
11645 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11646 imm_expr.X_op = O_absent;
11651 /* cins, cins32, exts and exts32 position field. Give error
11652 if it's not in the valid range. */
11653 gas_assert (!mips_opts.micromips);
11654 my_getExpression (&imm_expr, s);
11655 check_absolute_expr (ip, &imm_expr);
11656 if ((unsigned) imm_expr.X_add_number > 31)
11658 as_bad (_("Improper position (%lu)"),
11659 (unsigned long) imm_expr.X_add_number);
11660 imm_expr.X_add_number = 0;
11662 /* Make the pos explicit to simplify +S. */
11663 lastpos = imm_expr.X_add_number + 32;
11664 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11665 imm_expr.X_op = O_absent;
11670 /* cins, cins32, exts and exts32 position field. Move to
11671 the next candidate if it's not in the valid range. */
11672 gas_assert (!mips_opts.micromips);
11673 my_getExpression (&imm_expr, s);
11674 check_absolute_expr (ip, &imm_expr);
11675 if ((unsigned) imm_expr.X_add_number < 32
11676 || (unsigned) imm_expr.X_add_number > 63)
11678 lastpos = imm_expr.X_add_number;
11679 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11680 imm_expr.X_op = O_absent;
11685 /* cins and exts length-minus-one field. */
11686 gas_assert (!mips_opts.micromips);
11687 my_getExpression (&imm_expr, s);
11688 check_absolute_expr (ip, &imm_expr);
11689 if ((unsigned long) imm_expr.X_add_number > 31)
11691 as_bad (_("Improper size (%lu)"),
11692 (unsigned long) imm_expr.X_add_number);
11693 imm_expr.X_add_number = 0;
11695 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11696 imm_expr.X_op = O_absent;
11701 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11702 length-minus-one field. */
11703 gas_assert (!mips_opts.micromips);
11704 my_getExpression (&imm_expr, s);
11705 check_absolute_expr (ip, &imm_expr);
11706 if ((long) imm_expr.X_add_number < 0
11707 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11709 as_bad (_("Improper size (%lu)"),
11710 (unsigned long) imm_expr.X_add_number);
11711 imm_expr.X_add_number = 0;
11713 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11714 imm_expr.X_op = O_absent;
11719 /* seqi/snei immediate field. */
11720 gas_assert (!mips_opts.micromips);
11721 my_getExpression (&imm_expr, s);
11722 check_absolute_expr (ip, &imm_expr);
11723 if ((long) imm_expr.X_add_number < -512
11724 || (long) imm_expr.X_add_number >= 512)
11726 as_bad (_("Improper immediate (%ld)"),
11727 (long) imm_expr.X_add_number);
11728 imm_expr.X_add_number = 0;
11730 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11731 imm_expr.X_op = O_absent;
11735 case 'a': /* 8-bit signed offset in bit 6 */
11736 gas_assert (!mips_opts.micromips);
11737 my_getExpression (&imm_expr, s);
11738 check_absolute_expr (ip, &imm_expr);
11739 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11740 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11741 if (imm_expr.X_add_number < min_range
11742 || imm_expr.X_add_number > max_range)
11744 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11745 (long) min_range, (long) max_range,
11746 (long) imm_expr.X_add_number);
11748 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11749 imm_expr.X_op = O_absent;
11753 case 'b': /* 8-bit signed offset in bit 3 */
11754 gas_assert (!mips_opts.micromips);
11755 my_getExpression (&imm_expr, s);
11756 check_absolute_expr (ip, &imm_expr);
11757 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11758 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11759 if (imm_expr.X_add_number < min_range
11760 || imm_expr.X_add_number > max_range)
11762 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11763 (long) min_range, (long) max_range,
11764 (long) imm_expr.X_add_number);
11766 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11767 imm_expr.X_op = O_absent;
11771 case 'c': /* 9-bit signed offset in bit 6 */
11772 gas_assert (!mips_opts.micromips);
11773 my_getExpression (&imm_expr, s);
11774 check_absolute_expr (ip, &imm_expr);
11775 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11776 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11777 /* We check the offset range before adjusted. */
11780 if (imm_expr.X_add_number < min_range
11781 || imm_expr.X_add_number > max_range)
11783 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11784 (long) min_range, (long) max_range,
11785 (long) imm_expr.X_add_number);
11787 if (imm_expr.X_add_number & 0xf)
11789 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11790 (long) imm_expr.X_add_number);
11792 /* Right shift 4 bits to adjust the offset operand. */
11793 INSERT_OPERAND (0, OFFSET_C, *ip,
11794 imm_expr.X_add_number >> 4);
11795 imm_expr.X_op = O_absent;
11800 gas_assert (!mips_opts.micromips);
11801 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11803 if (regno == AT && mips_opts.at)
11805 if (mips_opts.at == ATREG)
11806 as_warn (_("used $at without \".set noat\""));
11808 as_warn (_("used $%u with \".set at=$%u\""),
11809 regno, mips_opts.at);
11811 INSERT_OPERAND (0, RZ, *ip, regno);
11815 gas_assert (!mips_opts.micromips);
11816 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11818 INSERT_OPERAND (0, FZ, *ip, regno);
11825 /* Check whether there is only a single bracketed expression
11826 left. If so, it must be the base register and the
11827 constant must be zero. */
11828 if (*s == '(' && strchr (s + 1, '(') == 0)
11831 /* If this value won't fit into the offset, then go find
11832 a macro that will generate a 16- or 32-bit offset code
11834 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11835 if ((i == 0 && (imm_expr.X_op != O_constant
11836 || imm_expr.X_add_number >= 1 << shift
11837 || imm_expr.X_add_number < -1 << shift))
11840 imm_expr.X_op = O_absent;
11843 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
11844 imm_expr.X_add_number);
11845 imm_expr.X_op = O_absent;
11851 as_bad (_("Internal error: bad %s opcode "
11852 "(unknown extension operand type `+%c'): %s %s"),
11853 mips_opts.micromips ? "microMIPS" : "MIPS",
11854 *args, insn->name, insn->args);
11855 /* Further processing is fruitless. */
11860 case '.': /* 10-bit offset. */
11861 gas_assert (mips_opts.micromips);
11862 case '~': /* 12-bit offset. */
11864 int shift = *args == '.' ? 9 : 11;
11867 /* Check whether there is only a single bracketed expression
11868 left. If so, it must be the base register and the
11869 constant must be zero. */
11870 if (*s == '(' && strchr (s + 1, '(') == 0)
11873 /* If this value won't fit into the offset, then go find
11874 a macro that will generate a 16- or 32-bit offset code
11876 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11877 if ((i == 0 && (imm_expr.X_op != O_constant
11878 || imm_expr.X_add_number >= 1 << shift
11879 || imm_expr.X_add_number < -1 << shift))
11882 imm_expr.X_op = O_absent;
11886 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11888 INSERT_OPERAND (mips_opts.micromips,
11889 OFFSET12, *ip, imm_expr.X_add_number);
11890 imm_expr.X_op = O_absent;
11895 case '<': /* must be at least one digit */
11897 * According to the manual, if the shift amount is greater
11898 * than 31 or less than 0, then the shift amount should be
11899 * mod 32. In reality the mips assembler issues an error.
11900 * We issue a warning and mask out all but the low 5 bits.
11902 my_getExpression (&imm_expr, s);
11903 check_absolute_expr (ip, &imm_expr);
11904 if ((unsigned long) imm_expr.X_add_number > 31)
11905 as_warn (_("Improper shift amount (%lu)"),
11906 (unsigned long) imm_expr.X_add_number);
11907 INSERT_OPERAND (mips_opts.micromips,
11908 SHAMT, *ip, imm_expr.X_add_number);
11909 imm_expr.X_op = O_absent;
11913 case '>': /* shift amount minus 32 */
11914 my_getExpression (&imm_expr, s);
11915 check_absolute_expr (ip, &imm_expr);
11916 if ((unsigned long) imm_expr.X_add_number < 32
11917 || (unsigned long) imm_expr.X_add_number > 63)
11919 INSERT_OPERAND (mips_opts.micromips,
11920 SHAMT, *ip, imm_expr.X_add_number - 32);
11921 imm_expr.X_op = O_absent;
11925 case 'k': /* CACHE code. */
11926 case 'h': /* PREFX code. */
11927 case '1': /* SYNC type. */
11928 my_getExpression (&imm_expr, s);
11929 check_absolute_expr (ip, &imm_expr);
11930 if ((unsigned long) imm_expr.X_add_number > 31)
11931 as_warn (_("Invalid value for `%s' (%lu)"),
11933 (unsigned long) imm_expr.X_add_number);
11937 if (mips_fix_cn63xxp1
11938 && !mips_opts.micromips
11939 && strcmp ("pref", insn->name) == 0)
11940 switch (imm_expr.X_add_number)
11949 case 31: /* These are ok. */
11952 default: /* The rest must be changed to 28. */
11953 imm_expr.X_add_number = 28;
11956 INSERT_OPERAND (mips_opts.micromips,
11957 CACHE, *ip, imm_expr.X_add_number);
11960 INSERT_OPERAND (mips_opts.micromips,
11961 PREFX, *ip, imm_expr.X_add_number);
11964 INSERT_OPERAND (mips_opts.micromips,
11965 STYPE, *ip, imm_expr.X_add_number);
11968 imm_expr.X_op = O_absent;
11972 case 'c': /* BREAK code. */
11974 unsigned long mask = (mips_opts.micromips
11975 ? MICROMIPSOP_MASK_CODE
11978 my_getExpression (&imm_expr, s);
11979 check_absolute_expr (ip, &imm_expr);
11980 if ((unsigned long) imm_expr.X_add_number > mask)
11981 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11983 mask, (unsigned long) imm_expr.X_add_number);
11984 INSERT_OPERAND (mips_opts.micromips,
11985 CODE, *ip, imm_expr.X_add_number);
11986 imm_expr.X_op = O_absent;
11991 case 'q': /* Lower BREAK code. */
11993 unsigned long mask = (mips_opts.micromips
11994 ? MICROMIPSOP_MASK_CODE2
11997 my_getExpression (&imm_expr, s);
11998 check_absolute_expr (ip, &imm_expr);
11999 if ((unsigned long) imm_expr.X_add_number > mask)
12000 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12002 mask, (unsigned long) imm_expr.X_add_number);
12003 INSERT_OPERAND (mips_opts.micromips,
12004 CODE2, *ip, imm_expr.X_add_number);
12005 imm_expr.X_op = O_absent;
12010 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12012 unsigned long mask = (mips_opts.micromips
12013 ? MICROMIPSOP_MASK_CODE10
12016 my_getExpression (&imm_expr, s);
12017 check_absolute_expr (ip, &imm_expr);
12018 if ((unsigned long) imm_expr.X_add_number > mask)
12019 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12021 mask, (unsigned long) imm_expr.X_add_number);
12022 if (mips_opts.micromips)
12023 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12025 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12026 imm_expr.X_op = O_absent;
12031 case 'C': /* 25- or 23-bit coprocessor code. */
12033 unsigned long mask = (mips_opts.micromips
12034 ? MICROMIPSOP_MASK_COPZ
12037 my_getExpression (&imm_expr, s);
12038 check_absolute_expr (ip, &imm_expr);
12039 if ((unsigned long) imm_expr.X_add_number > mask)
12040 as_warn (_("Coproccesor code > %u bits (%lu)"),
12041 mips_opts.micromips ? 23U : 25U,
12042 (unsigned long) imm_expr.X_add_number);
12043 INSERT_OPERAND (mips_opts.micromips,
12044 COPZ, *ip, imm_expr.X_add_number);
12045 imm_expr.X_op = O_absent;
12050 case 'J': /* 19-bit WAIT code. */
12051 gas_assert (!mips_opts.micromips);
12052 my_getExpression (&imm_expr, s);
12053 check_absolute_expr (ip, &imm_expr);
12054 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12056 as_warn (_("Illegal 19-bit code (%lu)"),
12057 (unsigned long) imm_expr.X_add_number);
12058 imm_expr.X_add_number &= OP_MASK_CODE19;
12060 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12061 imm_expr.X_op = O_absent;
12065 case 'P': /* Performance register. */
12066 gas_assert (!mips_opts.micromips);
12067 my_getExpression (&imm_expr, s);
12068 check_absolute_expr (ip, &imm_expr);
12069 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12070 as_warn (_("Invalid performance register (%lu)"),
12071 (unsigned long) imm_expr.X_add_number);
12072 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12073 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12074 as_warn (_("Invalid performance register (%lu)"),
12075 (unsigned long) imm_expr.X_add_number);
12076 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12077 imm_expr.X_op = O_absent;
12081 case 'G': /* Coprocessor destination register. */
12083 unsigned long opcode = ip->insn_opcode;
12084 unsigned long mask;
12085 unsigned int types;
12088 if (mips_opts.micromips)
12090 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12091 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12092 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12096 case 0x000000fc: /* mfc0 */
12097 case 0x000002fc: /* mtc0 */
12098 case 0x580000fc: /* dmfc0 */
12099 case 0x580002fc: /* dmtc0 */
12109 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12110 cop0 = opcode == OP_OP_COP0;
12112 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12113 ok = reg_lookup (&s, types, ®no);
12114 if (mips_opts.micromips)
12115 INSERT_OPERAND (1, RS, *ip, regno);
12117 INSERT_OPERAND (0, RD, *ip, regno);
12126 case 'y': /* ALNV.PS source register. */
12127 gas_assert (mips_opts.micromips);
12129 case 'x': /* Ignore register name. */
12130 case 'U': /* Destination register (CLO/CLZ). */
12131 case 'g': /* Coprocessor destination register. */
12132 gas_assert (!mips_opts.micromips);
12133 case 'b': /* Base register. */
12134 case 'd': /* Destination register. */
12135 case 's': /* Source register. */
12136 case 't': /* Target register. */
12137 case 'r': /* Both target and source. */
12138 case 'v': /* Both dest and source. */
12139 case 'w': /* Both dest and target. */
12140 case 'E': /* Coprocessor target register. */
12141 case 'K': /* RDHWR destination register. */
12142 case 'z': /* Must be zero register. */
12145 if (*args == 'E' || *args == 'K')
12146 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12149 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12150 if (regno == AT && mips_opts.at)
12152 if (mips_opts.at == ATREG)
12153 as_warn (_("Used $at without \".set noat\""));
12155 as_warn (_("Used $%u with \".set at=$%u\""),
12156 regno, mips_opts.at);
12166 if (c == 'r' || c == 'v' || c == 'w')
12173 /* 'z' only matches $0. */
12174 if (c == 'z' && regno != 0)
12177 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12179 if (regno == lastregno)
12182 = _("Source and destination must be different");
12185 if (regno == 31 && lastregno == 0xffffffff)
12188 = _("A destination register must be supplied");
12192 /* Now that we have assembled one operand, we use the args
12193 string to figure out where it goes in the instruction. */
12200 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12204 if (mips_opts.micromips)
12205 INSERT_OPERAND (1, RS, *ip, regno);
12207 INSERT_OPERAND (0, RD, *ip, regno);
12212 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12216 gas_assert (!mips_opts.micromips);
12217 INSERT_OPERAND (0, RD, *ip, regno);
12218 INSERT_OPERAND (0, RT, *ip, regno);
12224 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12228 gas_assert (mips_opts.micromips);
12229 INSERT_OPERAND (1, RS3, *ip, regno);
12233 /* This case exists because on the r3000 trunc
12234 expands into a macro which requires a gp
12235 register. On the r6000 or r4000 it is
12236 assembled into a single instruction which
12237 ignores the register. Thus the insn version
12238 is MIPS_ISA2 and uses 'x', and the macro
12239 version is MIPS_ISA1 and uses 't'. */
12243 /* This case is for the div instruction, which
12244 acts differently if the destination argument
12245 is $0. This only matches $0, and is checked
12246 outside the switch. */
12256 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12260 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12265 case 'O': /* MDMX alignment immediate constant. */
12266 gas_assert (!mips_opts.micromips);
12267 my_getExpression (&imm_expr, s);
12268 check_absolute_expr (ip, &imm_expr);
12269 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12270 as_warn (_("Improper align amount (%ld), using low bits"),
12271 (long) imm_expr.X_add_number);
12272 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12273 imm_expr.X_op = O_absent;
12277 case 'Q': /* MDMX vector, element sel, or const. */
12280 /* MDMX Immediate. */
12281 gas_assert (!mips_opts.micromips);
12282 my_getExpression (&imm_expr, s);
12283 check_absolute_expr (ip, &imm_expr);
12284 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12285 as_warn (_("Invalid MDMX Immediate (%ld)"),
12286 (long) imm_expr.X_add_number);
12287 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12288 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12289 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12291 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12292 imm_expr.X_op = O_absent;
12296 /* Not MDMX Immediate. Fall through. */
12297 case 'X': /* MDMX destination register. */
12298 case 'Y': /* MDMX source register. */
12299 case 'Z': /* MDMX target register. */
12302 gas_assert (!mips_opts.micromips);
12303 case 'D': /* Floating point destination register. */
12304 case 'S': /* Floating point source register. */
12305 case 'T': /* Floating point target register. */
12306 case 'R': /* Floating point source register. */
12310 || ((mips_opts.ase & ASE_MDMX)
12311 && (ip->insn_mo->pinfo & FP_D)
12312 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12313 | INSN_COPROC_MEMORY_DELAY
12314 | INSN_LOAD_COPROC_DELAY
12315 | INSN_LOAD_MEMORY_DELAY
12316 | INSN_STORE_MEMORY))))
12317 rtype |= RTYPE_VEC;
12319 if (reg_lookup (&s, rtype, ®no))
12321 if ((regno & 1) != 0
12323 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12324 as_warn (_("Float register should be even, was %d"),
12332 if (c == 'V' || c == 'W')
12343 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12349 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12353 /* This is like 'Z', but also needs to fix the MDMX
12354 vector/scalar select bits. Note that the
12355 scalar immediate case is handled above. */
12358 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12359 int max_el = (is_qh ? 3 : 7);
12361 my_getExpression(&imm_expr, s);
12362 check_absolute_expr (ip, &imm_expr);
12364 if (imm_expr.X_add_number > max_el)
12365 as_bad (_("Bad element selector %ld"),
12366 (long) imm_expr.X_add_number);
12367 imm_expr.X_add_number &= max_el;
12368 ip->insn_opcode |= (imm_expr.X_add_number
12371 imm_expr.X_op = O_absent;
12373 as_warn (_("Expecting ']' found '%s'"), s);
12379 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12380 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12383 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12386 /* Fall through. */
12390 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12394 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12404 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12408 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12414 my_getExpression (&imm_expr, s);
12415 if (imm_expr.X_op != O_big
12416 && imm_expr.X_op != O_constant)
12417 insn_error = _("absolute expression required");
12418 if (HAVE_32BIT_GPRS)
12419 normalize_constant_expr (&imm_expr);
12424 my_getExpression (&offset_expr, s);
12425 normalize_address_expr (&offset_expr);
12426 *imm_reloc = BFD_RELOC_32;
12439 unsigned char temp[8];
12441 unsigned int length;
12446 /* These only appear as the last operand in an
12447 instruction, and every instruction that accepts
12448 them in any variant accepts them in all variants.
12449 This means we don't have to worry about backing out
12450 any changes if the instruction does not match.
12452 The difference between them is the size of the
12453 floating point constant and where it goes. For 'F'
12454 and 'L' the constant is 64 bits; for 'f' and 'l' it
12455 is 32 bits. Where the constant is placed is based
12456 on how the MIPS assembler does things:
12459 f -- immediate value
12462 The .lit4 and .lit8 sections are only used if
12463 permitted by the -G argument.
12465 The code below needs to know whether the target register
12466 is 32 or 64 bits wide. It relies on the fact 'f' and
12467 'F' are used with GPR-based instructions and 'l' and
12468 'L' are used with FPR-based instructions. */
12470 f64 = *args == 'F' || *args == 'L';
12471 using_gprs = *args == 'F' || *args == 'f';
12473 save_in = input_line_pointer;
12474 input_line_pointer = s;
12475 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12477 s = input_line_pointer;
12478 input_line_pointer = save_in;
12479 if (err != NULL && *err != '\0')
12481 as_bad (_("Bad floating point constant: %s"), err);
12482 memset (temp, '\0', sizeof temp);
12483 length = f64 ? 8 : 4;
12486 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12490 && (g_switch_value < 4
12491 || (temp[0] == 0 && temp[1] == 0)
12492 || (temp[2] == 0 && temp[3] == 0))))
12494 imm_expr.X_op = O_constant;
12495 if (!target_big_endian)
12496 imm_expr.X_add_number = bfd_getl32 (temp);
12498 imm_expr.X_add_number = bfd_getb32 (temp);
12500 else if (length > 4
12501 && !mips_disable_float_construction
12502 /* Constants can only be constructed in GPRs and
12503 copied to FPRs if the GPRs are at least as wide
12504 as the FPRs. Force the constant into memory if
12505 we are using 64-bit FPRs but the GPRs are only
12508 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12509 && ((temp[0] == 0 && temp[1] == 0)
12510 || (temp[2] == 0 && temp[3] == 0))
12511 && ((temp[4] == 0 && temp[5] == 0)
12512 || (temp[6] == 0 && temp[7] == 0)))
12514 /* The value is simple enough to load with a couple of
12515 instructions. If using 32-bit registers, set
12516 imm_expr to the high order 32 bits and offset_expr to
12517 the low order 32 bits. Otherwise, set imm_expr to
12518 the entire 64 bit constant. */
12519 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12521 imm_expr.X_op = O_constant;
12522 offset_expr.X_op = O_constant;
12523 if (!target_big_endian)
12525 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12526 offset_expr.X_add_number = bfd_getl32 (temp);
12530 imm_expr.X_add_number = bfd_getb32 (temp);
12531 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12533 if (offset_expr.X_add_number == 0)
12534 offset_expr.X_op = O_absent;
12536 else if (sizeof (imm_expr.X_add_number) > 4)
12538 imm_expr.X_op = O_constant;
12539 if (!target_big_endian)
12540 imm_expr.X_add_number = bfd_getl64 (temp);
12542 imm_expr.X_add_number = bfd_getb64 (temp);
12546 imm_expr.X_op = O_big;
12547 imm_expr.X_add_number = 4;
12548 if (!target_big_endian)
12550 generic_bignum[0] = bfd_getl16 (temp);
12551 generic_bignum[1] = bfd_getl16 (temp + 2);
12552 generic_bignum[2] = bfd_getl16 (temp + 4);
12553 generic_bignum[3] = bfd_getl16 (temp + 6);
12557 generic_bignum[0] = bfd_getb16 (temp + 6);
12558 generic_bignum[1] = bfd_getb16 (temp + 4);
12559 generic_bignum[2] = bfd_getb16 (temp + 2);
12560 generic_bignum[3] = bfd_getb16 (temp);
12566 const char *newname;
12569 /* Switch to the right section. */
12571 subseg = now_subseg;
12574 default: /* unused default case avoids warnings. */
12576 newname = RDATA_SECTION_NAME;
12577 if (g_switch_value >= 8)
12581 newname = RDATA_SECTION_NAME;
12584 gas_assert (g_switch_value >= 4);
12588 new_seg = subseg_new (newname, (subsegT) 0);
12590 bfd_set_section_flags (stdoutput, new_seg,
12595 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12596 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12597 record_alignment (new_seg, 4);
12599 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12600 if (seg == now_seg)
12601 as_bad (_("Can't use floating point insn in this section"));
12603 /* Set the argument to the current address in the
12605 offset_expr.X_op = O_symbol;
12606 offset_expr.X_add_symbol = symbol_temp_new_now ();
12607 offset_expr.X_add_number = 0;
12609 /* Put the floating point number into the section. */
12610 p = frag_more ((int) length);
12611 memcpy (p, temp, length);
12613 /* Switch back to the original section. */
12614 subseg_set (seg, subseg);
12619 case 'i': /* 16-bit unsigned immediate. */
12620 case 'j': /* 16-bit signed immediate. */
12621 *imm_reloc = BFD_RELOC_LO16;
12622 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12625 offsetT minval, maxval;
12627 more = (insn + 1 < past
12628 && strcmp (insn->name, insn[1].name) == 0);
12630 /* If the expression was written as an unsigned number,
12631 only treat it as signed if there are no more
12635 && sizeof (imm_expr.X_add_number) <= 4
12636 && imm_expr.X_op == O_constant
12637 && imm_expr.X_add_number < 0
12638 && imm_expr.X_unsigned
12639 && HAVE_64BIT_GPRS)
12642 /* For compatibility with older assemblers, we accept
12643 0x8000-0xffff as signed 16-bit numbers when only
12644 signed numbers are allowed. */
12646 minval = 0, maxval = 0xffff;
12648 minval = -0x8000, maxval = 0x7fff;
12650 minval = -0x8000, maxval = 0xffff;
12652 if (imm_expr.X_op != O_constant
12653 || imm_expr.X_add_number < minval
12654 || imm_expr.X_add_number > maxval)
12658 if (imm_expr.X_op == O_constant
12659 || imm_expr.X_op == O_big)
12660 as_bad (_("Expression out of range"));
12666 case 'o': /* 16-bit offset. */
12667 offset_reloc[0] = BFD_RELOC_LO16;
12668 offset_reloc[1] = BFD_RELOC_UNUSED;
12669 offset_reloc[2] = BFD_RELOC_UNUSED;
12671 /* Check whether there is only a single bracketed expression
12672 left. If so, it must be the base register and the
12673 constant must be zero. */
12674 if (*s == '(' && strchr (s + 1, '(') == 0)
12676 offset_expr.X_op = O_constant;
12677 offset_expr.X_add_number = 0;
12681 /* If this value won't fit into a 16 bit offset, then go
12682 find a macro that will generate the 32 bit offset
12684 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12685 && (offset_expr.X_op != O_constant
12686 || offset_expr.X_add_number >= 0x8000
12687 || offset_expr.X_add_number < -0x8000))
12693 case 'p': /* PC-relative offset. */
12694 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12695 my_getExpression (&offset_expr, s);
12699 case 'u': /* Upper 16 bits. */
12700 *imm_reloc = BFD_RELOC_LO16;
12701 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12702 && imm_expr.X_op == O_constant
12703 && (imm_expr.X_add_number < 0
12704 || imm_expr.X_add_number >= 0x10000))
12705 as_bad (_("lui expression (%lu) not in range 0..65535"),
12706 (unsigned long) imm_expr.X_add_number);
12710 case 'a': /* 26-bit address. */
12711 *offset_reloc = BFD_RELOC_MIPS_JMP;
12712 my_getExpression (&offset_expr, s);
12716 case 'N': /* 3-bit branch condition code. */
12717 case 'M': /* 3-bit compare condition code. */
12719 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12720 rtype |= RTYPE_FCC;
12721 if (!reg_lookup (&s, rtype, ®no))
12723 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12724 || strcmp (str + strlen (str) - 5, "any2f") == 0
12725 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12726 && (regno & 1) != 0)
12727 as_warn (_("Condition code register should be even for %s, "
12730 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12731 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12732 && (regno & 3) != 0)
12733 as_warn (_("Condition code register should be 0 or 4 for %s, "
12737 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12739 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12743 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12754 while (ISDIGIT (*s));
12757 c = 8; /* Invalid sel value. */
12760 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12761 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12765 gas_assert (!mips_opts.micromips);
12766 /* Must be at least one digit. */
12767 my_getExpression (&imm_expr, s);
12768 check_absolute_expr (ip, &imm_expr);
12770 if ((unsigned long) imm_expr.X_add_number
12771 > (unsigned long) OP_MASK_VECBYTE)
12773 as_bad (_("bad byte vector index (%ld)"),
12774 (long) imm_expr.X_add_number);
12775 imm_expr.X_add_number = 0;
12778 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12779 imm_expr.X_op = O_absent;
12784 gas_assert (!mips_opts.micromips);
12785 my_getExpression (&imm_expr, s);
12786 check_absolute_expr (ip, &imm_expr);
12788 if ((unsigned long) imm_expr.X_add_number
12789 > (unsigned long) OP_MASK_VECALIGN)
12791 as_bad (_("bad byte vector index (%ld)"),
12792 (long) imm_expr.X_add_number);
12793 imm_expr.X_add_number = 0;
12796 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12797 imm_expr.X_op = O_absent;
12801 case 'm': /* Opcode extension character. */
12802 gas_assert (mips_opts.micromips);
12807 if (strncmp (s, "$pc", 3) == 0)
12835 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12836 if (regno == AT && mips_opts.at)
12838 if (mips_opts.at == ATREG)
12839 as_warn (_("Used $at without \".set noat\""));
12841 as_warn (_("Used $%u with \".set at=$%u\""),
12842 regno, mips_opts.at);
12848 gas_assert (args[1] == ',');
12854 gas_assert (args[1] == ',');
12856 continue; /* Nothing to do. */
12862 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12864 if (regno == lastregno)
12867 = _("Source and destination must be different");
12870 if (regno == 31 && lastregno == 0xffffffff)
12873 = _("A destination register must be supplied");
12884 gas_assert (args[1] == ',');
12891 gas_assert (args[1] == ',');
12894 continue; /* Nothing to do. */
12898 /* Make sure regno is the same as lastregno. */
12899 if (c == 't' && regno != lastregno)
12902 /* Make sure regno is the same as destregno. */
12903 if (c == 'x' && regno != destregno)
12906 /* We need to save regno, before regno maps to the
12907 microMIPS register encoding. */
12917 regno = ILLEGAL_REG;
12921 regno = mips32_to_micromips_reg_b_map[regno];
12925 regno = mips32_to_micromips_reg_c_map[regno];
12929 regno = mips32_to_micromips_reg_d_map[regno];
12933 regno = mips32_to_micromips_reg_e_map[regno];
12937 regno = mips32_to_micromips_reg_f_map[regno];
12941 regno = mips32_to_micromips_reg_g_map[regno];
12945 regno = mips32_to_micromips_reg_h_map[regno];
12949 switch (EXTRACT_OPERAND (1, MI, *ip))
12954 else if (regno == 22)
12956 else if (regno == 5)
12958 else if (regno == 6)
12960 else if (regno == 7)
12963 regno = ILLEGAL_REG;
12969 else if (regno == 7)
12972 regno = ILLEGAL_REG;
12979 regno = ILLEGAL_REG;
12983 regno = ILLEGAL_REG;
12989 regno = mips32_to_micromips_reg_l_map[regno];
12993 regno = mips32_to_micromips_reg_m_map[regno];
12997 regno = mips32_to_micromips_reg_n_map[regno];
13001 regno = mips32_to_micromips_reg_q_map[regno];
13006 regno = ILLEGAL_REG;
13011 regno = ILLEGAL_REG;
13016 regno = ILLEGAL_REG;
13019 case 'j': /* Do nothing. */
13029 if (regno == ILLEGAL_REG)
13035 INSERT_OPERAND (1, MB, *ip, regno);
13039 INSERT_OPERAND (1, MC, *ip, regno);
13043 INSERT_OPERAND (1, MD, *ip, regno);
13047 INSERT_OPERAND (1, ME, *ip, regno);
13051 INSERT_OPERAND (1, MF, *ip, regno);
13055 INSERT_OPERAND (1, MG, *ip, regno);
13059 INSERT_OPERAND (1, MH, *ip, regno);
13063 INSERT_OPERAND (1, MI, *ip, regno);
13067 INSERT_OPERAND (1, MJ, *ip, regno);
13071 INSERT_OPERAND (1, ML, *ip, regno);
13075 INSERT_OPERAND (1, MM, *ip, regno);
13079 INSERT_OPERAND (1, MN, *ip, regno);
13083 INSERT_OPERAND (1, MP, *ip, regno);
13087 INSERT_OPERAND (1, MQ, *ip, regno);
13090 case 'a': /* Do nothing. */
13091 case 's': /* Do nothing. */
13092 case 't': /* Do nothing. */
13093 case 'x': /* Do nothing. */
13094 case 'y': /* Do nothing. */
13095 case 'z': /* Do nothing. */
13105 bfd_reloc_code_real_type r[3];
13109 /* Check whether there is only a single bracketed
13110 expression left. If so, it must be the base register
13111 and the constant must be zero. */
13112 if (*s == '(' && strchr (s + 1, '(') == 0)
13114 INSERT_OPERAND (1, IMMA, *ip, 0);
13118 if (my_getSmallExpression (&ep, r, s) > 0
13119 || !expr_const_in_range (&ep, -64, 64, 2))
13122 imm = ep.X_add_number >> 2;
13123 INSERT_OPERAND (1, IMMA, *ip, imm);
13130 bfd_reloc_code_real_type r[3];
13134 if (my_getSmallExpression (&ep, r, s) > 0
13135 || ep.X_op != O_constant)
13138 for (imm = 0; imm < 8; imm++)
13139 if (micromips_imm_b_map[imm] == ep.X_add_number)
13144 INSERT_OPERAND (1, IMMB, *ip, imm);
13151 bfd_reloc_code_real_type r[3];
13155 if (my_getSmallExpression (&ep, r, s) > 0
13156 || ep.X_op != O_constant)
13159 for (imm = 0; imm < 16; imm++)
13160 if (micromips_imm_c_map[imm] == ep.X_add_number)
13165 INSERT_OPERAND (1, IMMC, *ip, imm);
13170 case 'D': /* pc relative offset */
13171 case 'E': /* pc relative offset */
13172 my_getExpression (&offset_expr, s);
13173 if (offset_expr.X_op == O_register)
13176 if (!forced_insn_length)
13177 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13179 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13181 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13187 bfd_reloc_code_real_type r[3];
13191 if (my_getSmallExpression (&ep, r, s) > 0
13192 || !expr_const_in_range (&ep, 0, 16, 0))
13195 imm = ep.X_add_number;
13196 INSERT_OPERAND (1, IMMF, *ip, imm);
13203 bfd_reloc_code_real_type r[3];
13207 /* Check whether there is only a single bracketed
13208 expression left. If so, it must be the base register
13209 and the constant must be zero. */
13210 if (*s == '(' && strchr (s + 1, '(') == 0)
13212 INSERT_OPERAND (1, IMMG, *ip, 0);
13216 if (my_getSmallExpression (&ep, r, s) > 0
13217 || !expr_const_in_range (&ep, -1, 15, 0))
13220 imm = ep.X_add_number & 15;
13221 INSERT_OPERAND (1, IMMG, *ip, imm);
13228 bfd_reloc_code_real_type r[3];
13232 /* Check whether there is only a single bracketed
13233 expression left. If so, it must be the base register
13234 and the constant must be zero. */
13235 if (*s == '(' && strchr (s + 1, '(') == 0)
13237 INSERT_OPERAND (1, IMMH, *ip, 0);
13241 if (my_getSmallExpression (&ep, r, s) > 0
13242 || !expr_const_in_range (&ep, 0, 16, 1))
13245 imm = ep.X_add_number >> 1;
13246 INSERT_OPERAND (1, IMMH, *ip, imm);
13253 bfd_reloc_code_real_type r[3];
13257 if (my_getSmallExpression (&ep, r, s) > 0
13258 || !expr_const_in_range (&ep, -1, 127, 0))
13261 imm = ep.X_add_number & 127;
13262 INSERT_OPERAND (1, IMMI, *ip, imm);
13269 bfd_reloc_code_real_type r[3];
13273 /* Check whether there is only a single bracketed
13274 expression left. If so, it must be the base register
13275 and the constant must be zero. */
13276 if (*s == '(' && strchr (s + 1, '(') == 0)
13278 INSERT_OPERAND (1, IMMJ, *ip, 0);
13282 if (my_getSmallExpression (&ep, r, s) > 0
13283 || !expr_const_in_range (&ep, 0, 16, 2))
13286 imm = ep.X_add_number >> 2;
13287 INSERT_OPERAND (1, IMMJ, *ip, imm);
13294 bfd_reloc_code_real_type r[3];
13298 /* Check whether there is only a single bracketed
13299 expression left. If so, it must be the base register
13300 and the constant must be zero. */
13301 if (*s == '(' && strchr (s + 1, '(') == 0)
13303 INSERT_OPERAND (1, IMML, *ip, 0);
13307 if (my_getSmallExpression (&ep, r, s) > 0
13308 || !expr_const_in_range (&ep, 0, 16, 0))
13311 imm = ep.X_add_number;
13312 INSERT_OPERAND (1, IMML, *ip, imm);
13319 bfd_reloc_code_real_type r[3];
13323 if (my_getSmallExpression (&ep, r, s) > 0
13324 || !expr_const_in_range (&ep, 1, 9, 0))
13327 imm = ep.X_add_number & 7;
13328 INSERT_OPERAND (1, IMMM, *ip, imm);
13333 case 'N': /* Register list for lwm and swm. */
13335 /* A comma-separated list of registers and/or
13336 dash-separated contiguous ranges including
13337 both ra and a set of one or more registers
13338 starting at s0 up to s3 which have to be
13345 and any permutations of these. */
13346 unsigned int reglist;
13349 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13352 if ((reglist & 0xfff1ffff) != 0x80010000)
13355 reglist = (reglist >> 17) & 7;
13357 if ((reglist & -reglist) != reglist)
13360 imm = ffs (reglist) - 1;
13361 INSERT_OPERAND (1, IMMN, *ip, imm);
13365 case 'O': /* sdbbp 4-bit code. */
13367 bfd_reloc_code_real_type r[3];
13371 if (my_getSmallExpression (&ep, r, s) > 0
13372 || !expr_const_in_range (&ep, 0, 16, 0))
13375 imm = ep.X_add_number;
13376 INSERT_OPERAND (1, IMMO, *ip, imm);
13383 bfd_reloc_code_real_type r[3];
13387 if (my_getSmallExpression (&ep, r, s) > 0
13388 || !expr_const_in_range (&ep, 0, 32, 2))
13391 imm = ep.X_add_number >> 2;
13392 INSERT_OPERAND (1, IMMP, *ip, imm);
13399 bfd_reloc_code_real_type r[3];
13403 if (my_getSmallExpression (&ep, r, s) > 0
13404 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13407 imm = ep.X_add_number >> 2;
13408 INSERT_OPERAND (1, IMMQ, *ip, imm);
13415 bfd_reloc_code_real_type r[3];
13419 /* Check whether there is only a single bracketed
13420 expression left. If so, it must be the base register
13421 and the constant must be zero. */
13422 if (*s == '(' && strchr (s + 1, '(') == 0)
13424 INSERT_OPERAND (1, IMMU, *ip, 0);
13428 if (my_getSmallExpression (&ep, r, s) > 0
13429 || !expr_const_in_range (&ep, 0, 32, 2))
13432 imm = ep.X_add_number >> 2;
13433 INSERT_OPERAND (1, IMMU, *ip, imm);
13440 bfd_reloc_code_real_type r[3];
13444 if (my_getSmallExpression (&ep, r, s) > 0
13445 || !expr_const_in_range (&ep, 0, 64, 2))
13448 imm = ep.X_add_number >> 2;
13449 INSERT_OPERAND (1, IMMW, *ip, imm);
13456 bfd_reloc_code_real_type r[3];
13460 if (my_getSmallExpression (&ep, r, s) > 0
13461 || !expr_const_in_range (&ep, -8, 8, 0))
13464 imm = ep.X_add_number;
13465 INSERT_OPERAND (1, IMMX, *ip, imm);
13472 bfd_reloc_code_real_type r[3];
13476 if (my_getSmallExpression (&ep, r, s) > 0
13477 || expr_const_in_range (&ep, -2, 2, 2)
13478 || !expr_const_in_range (&ep, -258, 258, 2))
13481 imm = ep.X_add_number >> 2;
13482 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13483 INSERT_OPERAND (1, IMMY, *ip, imm);
13490 bfd_reloc_code_real_type r[3];
13493 if (my_getSmallExpression (&ep, r, s) > 0
13494 || !expr_const_in_range (&ep, 0, 1, 0))
13501 as_bad (_("Internal error: bad microMIPS opcode "
13502 "(unknown extension operand type `m%c'): %s %s"),
13503 *args, insn->name, insn->args);
13504 /* Further processing is fruitless. */
13509 case 'n': /* Register list for 32-bit lwm and swm. */
13510 gas_assert (mips_opts.micromips);
13512 /* A comma-separated list of registers and/or
13513 dash-separated contiguous ranges including
13514 at least one of ra and a set of one or more
13515 registers starting at s0 up to s7 and then
13516 s8 which have to be consecutive, e.g.:
13524 and any permutations of these. */
13525 unsigned int reglist;
13529 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13532 if ((reglist & 0x3f00ffff) != 0)
13535 ra = (reglist >> 27) & 0x10;
13536 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13538 if ((reglist & -reglist) != reglist)
13541 imm = (ffs (reglist) - 1) | ra;
13542 INSERT_OPERAND (1, RT, *ip, imm);
13543 imm_expr.X_op = O_absent;
13547 case '|': /* 4-bit trap code. */
13548 gas_assert (mips_opts.micromips);
13549 my_getExpression (&imm_expr, s);
13550 check_absolute_expr (ip, &imm_expr);
13551 if ((unsigned long) imm_expr.X_add_number
13552 > MICROMIPSOP_MASK_TRAP)
13553 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13554 (unsigned long) imm_expr.X_add_number,
13555 ip->insn_mo->name);
13556 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13557 imm_expr.X_op = O_absent;
13562 as_bad (_("Bad char = '%c'\n"), *args);
13567 /* Args don't match. */
13569 insn_error = _("Illegal operands");
13570 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13575 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13577 gas_assert (firstinsn);
13578 need_delay_slot_ok = FALSE;
13587 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13589 /* This routine assembles an instruction into its binary format when
13590 assembling for the mips16. As a side effect, it sets one of the
13591 global variables imm_reloc or offset_reloc to the type of relocation
13592 to do if one of the operands is an address expression. It also sets
13593 forced_insn_length to the resulting instruction size in bytes if the
13594 user explicitly requested a small or extended instruction. */
13597 mips16_ip (char *str, struct mips_cl_insn *ip)
13601 struct mips_opcode *insn;
13603 unsigned int regno;
13604 unsigned int lastregno = 0;
13610 forced_insn_length = 0;
13612 for (s = str; ISLOWER (*s); ++s)
13624 if (s[1] == 't' && s[2] == ' ')
13627 forced_insn_length = 2;
13631 else if (s[1] == 'e' && s[2] == ' ')
13634 forced_insn_length = 4;
13638 /* Fall through. */
13640 insn_error = _("unknown opcode");
13644 if (mips_opts.noautoextend && !forced_insn_length)
13645 forced_insn_length = 2;
13647 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13649 insn_error = _("unrecognized opcode");
13658 gas_assert (strcmp (insn->name, str) == 0);
13660 ok = is_opcode_valid_16 (insn);
13663 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13664 && strcmp (insn->name, insn[1].name) == 0)
13673 static char buf[100];
13675 _("Opcode not supported on this processor: %s (%s)"),
13676 mips_cpu_info_from_arch (mips_opts.arch)->name,
13677 mips_cpu_info_from_isa (mips_opts.isa)->name);
13684 create_insn (ip, insn);
13685 imm_expr.X_op = O_absent;
13686 imm_reloc[0] = BFD_RELOC_UNUSED;
13687 imm_reloc[1] = BFD_RELOC_UNUSED;
13688 imm_reloc[2] = BFD_RELOC_UNUSED;
13689 imm2_expr.X_op = O_absent;
13690 offset_expr.X_op = O_absent;
13691 offset_reloc[0] = BFD_RELOC_UNUSED;
13692 offset_reloc[1] = BFD_RELOC_UNUSED;
13693 offset_reloc[2] = BFD_RELOC_UNUSED;
13694 for (args = insn->args; 1; ++args)
13701 /* In this switch statement we call break if we did not find
13702 a match, continue if we did find a match, or return if we
13713 /* Stuff the immediate value in now, if we can. */
13714 if (imm_expr.X_op == O_constant
13715 && *imm_reloc > BFD_RELOC_UNUSED
13716 && insn->pinfo != INSN_MACRO
13717 && calculate_reloc (*offset_reloc,
13718 imm_expr.X_add_number, &value))
13720 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13721 *offset_reloc, value, forced_insn_length,
13723 imm_expr.X_op = O_absent;
13724 *imm_reloc = BFD_RELOC_UNUSED;
13725 *offset_reloc = BFD_RELOC_UNUSED;
13739 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13742 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13758 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13760 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13764 /* Fall through. */
13775 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13777 if (c == 'v' || c == 'w')
13780 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13782 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13793 if (c == 'v' || c == 'w')
13795 regno = mips16_to_32_reg_map[lastregno];
13809 regno = mips32_to_16_reg_map[regno];
13814 regno = ILLEGAL_REG;
13819 regno = ILLEGAL_REG;
13824 regno = ILLEGAL_REG;
13829 if (regno == AT && mips_opts.at)
13831 if (mips_opts.at == ATREG)
13832 as_warn (_("used $at without \".set noat\""));
13834 as_warn (_("used $%u with \".set at=$%u\""),
13835 regno, mips_opts.at);
13843 if (regno == ILLEGAL_REG)
13850 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13854 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13857 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13860 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13866 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13869 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13870 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13880 if (strncmp (s, "$pc", 3) == 0)
13897 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13900 if (imm_expr.X_op != O_constant)
13902 forced_insn_length = 4;
13903 ip->insn_opcode |= MIPS16_EXTEND;
13907 /* We need to relax this instruction. */
13908 *offset_reloc = *imm_reloc;
13909 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13914 *imm_reloc = BFD_RELOC_UNUSED;
13915 /* Fall through. */
13922 my_getExpression (&imm_expr, s);
13923 if (imm_expr.X_op == O_register)
13925 /* What we thought was an expression turned out to
13928 if (s[0] == '(' && args[1] == '(')
13930 /* It looks like the expression was omitted
13931 before a register indirection, which means
13932 that the expression is implicitly zero. We
13933 still set up imm_expr, so that we handle
13934 explicit extensions correctly. */
13935 imm_expr.X_op = O_constant;
13936 imm_expr.X_add_number = 0;
13937 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13944 /* We need to relax this instruction. */
13945 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13954 /* We use offset_reloc rather than imm_reloc for the PC
13955 relative operands. This lets macros with both
13956 immediate and address operands work correctly. */
13957 my_getExpression (&offset_expr, s);
13959 if (offset_expr.X_op == O_register)
13962 /* We need to relax this instruction. */
13963 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13967 case '6': /* break code */
13968 my_getExpression (&imm_expr, s);
13969 check_absolute_expr (ip, &imm_expr);
13970 if ((unsigned long) imm_expr.X_add_number > 63)
13971 as_warn (_("Invalid value for `%s' (%lu)"),
13973 (unsigned long) imm_expr.X_add_number);
13974 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13975 imm_expr.X_op = O_absent;
13979 case 'a': /* 26 bit address */
13980 my_getExpression (&offset_expr, s);
13982 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13983 ip->insn_opcode <<= 16;
13986 case 'l': /* register list for entry macro */
13987 case 'L': /* register list for exit macro */
13997 unsigned int freg, reg1, reg2;
13999 while (*s == ' ' || *s == ',')
14001 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14003 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14007 as_bad (_("can't parse register list"));
14017 if (!reg_lookup (&s, freg ? RTYPE_FPU
14018 : (RTYPE_GP | RTYPE_NUM), ®2))
14020 as_bad (_("invalid register list"));
14024 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14026 mask &= ~ (7 << 3);
14029 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14031 mask &= ~ (7 << 3);
14034 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14035 mask |= (reg2 - 3) << 3;
14036 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14037 mask |= (reg2 - 15) << 1;
14038 else if (reg1 == RA && reg2 == RA)
14042 as_bad (_("invalid register list"));
14046 /* The mask is filled in in the opcode table for the
14047 benefit of the disassembler. We remove it before
14048 applying the actual mask. */
14049 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14050 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14054 case 'm': /* Register list for save insn. */
14055 case 'M': /* Register list for restore insn. */
14057 int opcode = ip->insn_opcode;
14058 int framesz = 0, seen_framesz = 0;
14059 int nargs = 0, statics = 0, sregs = 0;
14063 unsigned int reg1, reg2;
14065 SKIP_SPACE_TABS (s);
14068 SKIP_SPACE_TABS (s);
14070 my_getExpression (&imm_expr, s);
14071 if (imm_expr.X_op == O_constant)
14073 /* Handle the frame size. */
14076 as_bad (_("more than one frame size in list"));
14080 framesz = imm_expr.X_add_number;
14081 imm_expr.X_op = O_absent;
14086 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14088 as_bad (_("can't parse register list"));
14100 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14103 as_bad (_("can't parse register list"));
14108 while (reg1 <= reg2)
14110 if (reg1 >= 4 && reg1 <= 7)
14114 nargs |= 1 << (reg1 - 4);
14116 /* statics $a0-$a3 */
14117 statics |= 1 << (reg1 - 4);
14119 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14122 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14124 else if (reg1 == 31)
14126 /* Add $ra to insn. */
14131 as_bad (_("unexpected register in list"));
14139 /* Encode args/statics combination. */
14140 if (nargs & statics)
14141 as_bad (_("arg/static registers overlap"));
14142 else if (nargs == 0xf)
14143 /* All $a0-$a3 are args. */
14144 opcode |= MIPS16_ALL_ARGS << 16;
14145 else if (statics == 0xf)
14146 /* All $a0-$a3 are statics. */
14147 opcode |= MIPS16_ALL_STATICS << 16;
14150 int narg = 0, nstat = 0;
14152 /* Count arg registers. */
14153 while (nargs & 0x1)
14159 as_bad (_("invalid arg register list"));
14161 /* Count static registers. */
14162 while (statics & 0x8)
14164 statics = (statics << 1) & 0xf;
14168 as_bad (_("invalid static register list"));
14170 /* Encode args/statics. */
14171 opcode |= ((narg << 2) | nstat) << 16;
14174 /* Encode $s0/$s1. */
14175 if (sregs & (1 << 0)) /* $s0 */
14177 if (sregs & (1 << 1)) /* $s1 */
14183 /* Count regs $s2-$s8. */
14191 as_bad (_("invalid static register list"));
14192 /* Encode $s2-$s8. */
14193 opcode |= nsreg << 24;
14196 /* Encode frame size. */
14198 as_bad (_("missing frame size"));
14199 else if ((framesz & 7) != 0 || framesz < 0
14200 || framesz > 0xff * 8)
14201 as_bad (_("invalid frame size"));
14202 else if (framesz != 128 || (opcode >> 16) != 0)
14205 opcode |= (((framesz & 0xf0) << 16)
14206 | (framesz & 0x0f));
14209 /* Finally build the instruction. */
14210 if ((opcode >> 16) != 0 || framesz == 0)
14211 opcode |= MIPS16_EXTEND;
14212 ip->insn_opcode = opcode;
14216 case 'e': /* extend code */
14217 my_getExpression (&imm_expr, s);
14218 check_absolute_expr (ip, &imm_expr);
14219 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14221 as_warn (_("Invalid value for `%s' (%lu)"),
14223 (unsigned long) imm_expr.X_add_number);
14224 imm_expr.X_add_number &= 0x7ff;
14226 ip->insn_opcode |= imm_expr.X_add_number;
14227 imm_expr.X_op = O_absent;
14237 /* Args don't match. */
14238 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14239 strcmp (insn->name, insn[1].name) == 0)
14246 insn_error = _("illegal operands");
14252 /* This structure holds information we know about a mips16 immediate
14255 struct mips16_immed_operand
14257 /* The type code used in the argument string in the opcode table. */
14259 /* The number of bits in the short form of the opcode. */
14261 /* The number of bits in the extended form of the opcode. */
14263 /* The amount by which the short form is shifted when it is used;
14264 for example, the sw instruction has a shift count of 2. */
14266 /* The amount by which the short form is shifted when it is stored
14267 into the instruction code. */
14269 /* Non-zero if the short form is unsigned. */
14271 /* Non-zero if the extended form is unsigned. */
14273 /* Non-zero if the value is PC relative. */
14277 /* The mips16 immediate operand types. */
14279 static const struct mips16_immed_operand mips16_immed_operands[] =
14281 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14282 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14283 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14284 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14285 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14286 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14287 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14288 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14289 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14290 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14291 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14292 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14293 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14294 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14295 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14296 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14297 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14298 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14299 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14300 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14301 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14304 #define MIPS16_NUM_IMMED \
14305 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14307 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14308 NBITS is the number of significant bits in VAL. */
14310 static unsigned long
14311 mips16_immed_extend (offsetT val, unsigned int nbits)
14316 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14319 else if (nbits == 15)
14321 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14326 extval = ((val & 0x1f) << 6) | (val & 0x20);
14329 return (extval << 16) | val;
14332 /* Install immediate value VAL into MIPS16 instruction *INSN,
14333 extending it if necessary. The instruction in *INSN may
14334 already be extended.
14336 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14337 if none. In the former case, VAL is a 16-bit number with no
14338 defined signedness.
14340 TYPE is the type of the immediate field. USER_INSN_LENGTH
14341 is the length that the user requested, or 0 if none. */
14344 mips16_immed (char *file, unsigned int line, int type,
14345 bfd_reloc_code_real_type reloc, offsetT val,
14346 unsigned int user_insn_length, unsigned long *insn)
14348 const struct mips16_immed_operand *op;
14349 int mintiny, maxtiny;
14351 op = mips16_immed_operands;
14352 while (op->type != type)
14355 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14360 if (type == '<' || type == '>' || type == '[' || type == ']')
14363 maxtiny = 1 << op->nbits;
14368 maxtiny = (1 << op->nbits) - 1;
14370 if (reloc != BFD_RELOC_UNUSED)
14375 mintiny = - (1 << (op->nbits - 1));
14376 maxtiny = (1 << (op->nbits - 1)) - 1;
14377 if (reloc != BFD_RELOC_UNUSED)
14378 val = SEXT_16BIT (val);
14381 /* Branch offsets have an implicit 0 in the lowest bit. */
14382 if (type == 'p' || type == 'q')
14385 if ((val & ((1 << op->shift) - 1)) != 0
14386 || val < (mintiny << op->shift)
14387 || val > (maxtiny << op->shift))
14389 /* We need an extended instruction. */
14390 if (user_insn_length == 2)
14391 as_bad_where (file, line, _("invalid unextended operand value"));
14393 *insn |= MIPS16_EXTEND;
14395 else if (user_insn_length == 4)
14397 /* The operand doesn't force an unextended instruction to be extended.
14398 Warn if the user wanted an extended instruction anyway. */
14399 *insn |= MIPS16_EXTEND;
14400 as_warn_where (file, line,
14401 _("extended operand requested but not required"));
14404 if (mips16_opcode_length (*insn) == 2)
14408 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14409 insnval <<= op->op_shift;
14414 long minext, maxext;
14416 if (reloc == BFD_RELOC_UNUSED)
14421 maxext = (1 << op->extbits) - 1;
14425 minext = - (1 << (op->extbits - 1));
14426 maxext = (1 << (op->extbits - 1)) - 1;
14428 if (val < minext || val > maxext)
14429 as_bad_where (file, line,
14430 _("operand value out of range for instruction"));
14433 *insn |= mips16_immed_extend (val, op->extbits);
14437 struct percent_op_match
14440 bfd_reloc_code_real_type reloc;
14443 static const struct percent_op_match mips_percent_op[] =
14445 {"%lo", BFD_RELOC_LO16},
14447 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14448 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14449 {"%call16", BFD_RELOC_MIPS_CALL16},
14450 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14451 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14452 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14453 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14454 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14455 {"%got", BFD_RELOC_MIPS_GOT16},
14456 {"%gp_rel", BFD_RELOC_GPREL16},
14457 {"%half", BFD_RELOC_16},
14458 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14459 {"%higher", BFD_RELOC_MIPS_HIGHER},
14460 {"%neg", BFD_RELOC_MIPS_SUB},
14461 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14462 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14463 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14464 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14465 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14466 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14467 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14469 {"%hi", BFD_RELOC_HI16_S}
14472 static const struct percent_op_match mips16_percent_op[] =
14474 {"%lo", BFD_RELOC_MIPS16_LO16},
14475 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14476 {"%got", BFD_RELOC_MIPS16_GOT16},
14477 {"%call16", BFD_RELOC_MIPS16_CALL16},
14478 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14479 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14480 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14481 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14482 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14483 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14484 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14485 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14489 /* Return true if *STR points to a relocation operator. When returning true,
14490 move *STR over the operator and store its relocation code in *RELOC.
14491 Leave both *STR and *RELOC alone when returning false. */
14494 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14496 const struct percent_op_match *percent_op;
14499 if (mips_opts.mips16)
14501 percent_op = mips16_percent_op;
14502 limit = ARRAY_SIZE (mips16_percent_op);
14506 percent_op = mips_percent_op;
14507 limit = ARRAY_SIZE (mips_percent_op);
14510 for (i = 0; i < limit; i++)
14511 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14513 int len = strlen (percent_op[i].str);
14515 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14518 *str += strlen (percent_op[i].str);
14519 *reloc = percent_op[i].reloc;
14521 /* Check whether the output BFD supports this relocation.
14522 If not, issue an error and fall back on something safe. */
14523 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14525 as_bad (_("relocation %s isn't supported by the current ABI"),
14526 percent_op[i].str);
14527 *reloc = BFD_RELOC_UNUSED;
14535 /* Parse string STR as a 16-bit relocatable operand. Store the
14536 expression in *EP and the relocations in the array starting
14537 at RELOC. Return the number of relocation operators used.
14539 On exit, EXPR_END points to the first character after the expression. */
14542 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14545 bfd_reloc_code_real_type reversed_reloc[3];
14546 size_t reloc_index, i;
14547 int crux_depth, str_depth;
14550 /* Search for the start of the main expression, recoding relocations
14551 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14552 of the main expression and with CRUX_DEPTH containing the number
14553 of open brackets at that point. */
14560 crux_depth = str_depth;
14562 /* Skip over whitespace and brackets, keeping count of the number
14564 while (*str == ' ' || *str == '\t' || *str == '(')
14569 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14570 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14572 my_getExpression (ep, crux);
14575 /* Match every open bracket. */
14576 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14580 if (crux_depth > 0)
14581 as_bad (_("unclosed '('"));
14585 if (reloc_index != 0)
14587 prev_reloc_op_frag = frag_now;
14588 for (i = 0; i < reloc_index; i++)
14589 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14592 return reloc_index;
14596 my_getExpression (expressionS *ep, char *str)
14600 save_in = input_line_pointer;
14601 input_line_pointer = str;
14603 expr_end = input_line_pointer;
14604 input_line_pointer = save_in;
14608 md_atof (int type, char *litP, int *sizeP)
14610 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14614 md_number_to_chars (char *buf, valueT val, int n)
14616 if (target_big_endian)
14617 number_to_chars_bigendian (buf, val, n);
14619 number_to_chars_littleendian (buf, val, n);
14623 static int support_64bit_objects(void)
14625 const char **list, **l;
14628 list = bfd_target_list ();
14629 for (l = list; *l != NULL; l++)
14630 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14631 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14633 yes = (*l != NULL);
14637 #endif /* OBJ_ELF */
14639 const char *md_shortopts = "O::g::G:";
14643 OPTION_MARCH = OPTION_MD_BASE,
14667 OPTION_NO_SMARTMIPS,
14673 OPTION_NO_MICROMIPS,
14676 OPTION_COMPAT_ARCH_BASE,
14685 OPTION_M7000_HILO_FIX,
14686 OPTION_MNO_7000_HILO_FIX,
14689 OPTION_FIX_LOONGSON2F_JUMP,
14690 OPTION_NO_FIX_LOONGSON2F_JUMP,
14691 OPTION_FIX_LOONGSON2F_NOP,
14692 OPTION_NO_FIX_LOONGSON2F_NOP,
14694 OPTION_NO_FIX_VR4120,
14696 OPTION_NO_FIX_VR4130,
14697 OPTION_FIX_CN63XXP1,
14698 OPTION_NO_FIX_CN63XXP1,
14705 OPTION_CONSTRUCT_FLOATS,
14706 OPTION_NO_CONSTRUCT_FLOATS,
14709 OPTION_RELAX_BRANCH,
14710 OPTION_NO_RELAX_BRANCH,
14717 OPTION_SINGLE_FLOAT,
14718 OPTION_DOUBLE_FLOAT,
14721 OPTION_CALL_SHARED,
14722 OPTION_CALL_NONPIC,
14732 OPTION_MVXWORKS_PIC,
14733 #endif /* OBJ_ELF */
14737 struct option md_longopts[] =
14739 /* Options which specify architecture. */
14740 {"march", required_argument, NULL, OPTION_MARCH},
14741 {"mtune", required_argument, NULL, OPTION_MTUNE},
14742 {"mips0", no_argument, NULL, OPTION_MIPS1},
14743 {"mips1", no_argument, NULL, OPTION_MIPS1},
14744 {"mips2", no_argument, NULL, OPTION_MIPS2},
14745 {"mips3", no_argument, NULL, OPTION_MIPS3},
14746 {"mips4", no_argument, NULL, OPTION_MIPS4},
14747 {"mips5", no_argument, NULL, OPTION_MIPS5},
14748 {"mips32", no_argument, NULL, OPTION_MIPS32},
14749 {"mips64", no_argument, NULL, OPTION_MIPS64},
14750 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14751 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14753 /* Options which specify Application Specific Extensions (ASEs). */
14754 {"mips16", no_argument, NULL, OPTION_MIPS16},
14755 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14756 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14757 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14758 {"mdmx", no_argument, NULL, OPTION_MDMX},
14759 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14760 {"mdsp", no_argument, NULL, OPTION_DSP},
14761 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14762 {"mmt", no_argument, NULL, OPTION_MT},
14763 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14764 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14765 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14766 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14767 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14768 {"meva", no_argument, NULL, OPTION_EVA},
14769 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
14770 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14771 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14772 {"mmcu", no_argument, NULL, OPTION_MCU},
14773 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14774 {"mvirt", no_argument, NULL, OPTION_VIRT},
14775 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
14777 /* Old-style architecture options. Don't add more of these. */
14778 {"m4650", no_argument, NULL, OPTION_M4650},
14779 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14780 {"m4010", no_argument, NULL, OPTION_M4010},
14781 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14782 {"m4100", no_argument, NULL, OPTION_M4100},
14783 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14784 {"m3900", no_argument, NULL, OPTION_M3900},
14785 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14787 /* Options which enable bug fixes. */
14788 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14789 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14790 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14791 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14792 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14793 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14794 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14795 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14796 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14797 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14798 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14799 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14800 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14801 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14802 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14804 /* Miscellaneous options. */
14805 {"trap", no_argument, NULL, OPTION_TRAP},
14806 {"no-break", no_argument, NULL, OPTION_TRAP},
14807 {"break", no_argument, NULL, OPTION_BREAK},
14808 {"no-trap", no_argument, NULL, OPTION_BREAK},
14809 {"EB", no_argument, NULL, OPTION_EB},
14810 {"EL", no_argument, NULL, OPTION_EL},
14811 {"mfp32", no_argument, NULL, OPTION_FP32},
14812 {"mgp32", no_argument, NULL, OPTION_GP32},
14813 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14814 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14815 {"mfp64", no_argument, NULL, OPTION_FP64},
14816 {"mgp64", no_argument, NULL, OPTION_GP64},
14817 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14818 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14819 {"mshared", no_argument, NULL, OPTION_MSHARED},
14820 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14821 {"msym32", no_argument, NULL, OPTION_MSYM32},
14822 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14823 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14824 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14825 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14826 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14828 /* Strictly speaking this next option is ELF specific,
14829 but we allow it for other ports as well in order to
14830 make testing easier. */
14831 {"32", no_argument, NULL, OPTION_32},
14833 /* ELF-specific options. */
14835 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14836 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14837 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14838 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14839 {"xgot", no_argument, NULL, OPTION_XGOT},
14840 {"mabi", required_argument, NULL, OPTION_MABI},
14841 {"n32", no_argument, NULL, OPTION_N32},
14842 {"64", no_argument, NULL, OPTION_64},
14843 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14844 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14845 {"mpdr", no_argument, NULL, OPTION_PDR},
14846 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14847 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14848 #endif /* OBJ_ELF */
14850 {NULL, no_argument, NULL, 0}
14852 size_t md_longopts_size = sizeof (md_longopts);
14854 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14855 NEW_VALUE. Warn if another value was already specified. Note:
14856 we have to defer parsing the -march and -mtune arguments in order
14857 to handle 'from-abi' correctly, since the ABI might be specified
14858 in a later argument. */
14861 mips_set_option_string (const char **string_ptr, const char *new_value)
14863 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14864 as_warn (_("A different %s was already specified, is now %s"),
14865 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14868 *string_ptr = new_value;
14872 md_parse_option (int c, char *arg)
14876 case OPTION_CONSTRUCT_FLOATS:
14877 mips_disable_float_construction = 0;
14880 case OPTION_NO_CONSTRUCT_FLOATS:
14881 mips_disable_float_construction = 1;
14893 target_big_endian = 1;
14897 target_big_endian = 0;
14903 else if (arg[0] == '0')
14905 else if (arg[0] == '1')
14915 mips_debug = atoi (arg);
14919 file_mips_isa = ISA_MIPS1;
14923 file_mips_isa = ISA_MIPS2;
14927 file_mips_isa = ISA_MIPS3;
14931 file_mips_isa = ISA_MIPS4;
14935 file_mips_isa = ISA_MIPS5;
14938 case OPTION_MIPS32:
14939 file_mips_isa = ISA_MIPS32;
14942 case OPTION_MIPS32R2:
14943 file_mips_isa = ISA_MIPS32R2;
14946 case OPTION_MIPS64R2:
14947 file_mips_isa = ISA_MIPS64R2;
14950 case OPTION_MIPS64:
14951 file_mips_isa = ISA_MIPS64;
14955 mips_set_option_string (&mips_tune_string, arg);
14959 mips_set_option_string (&mips_arch_string, arg);
14963 mips_set_option_string (&mips_arch_string, "4650");
14964 mips_set_option_string (&mips_tune_string, "4650");
14967 case OPTION_NO_M4650:
14971 mips_set_option_string (&mips_arch_string, "4010");
14972 mips_set_option_string (&mips_tune_string, "4010");
14975 case OPTION_NO_M4010:
14979 mips_set_option_string (&mips_arch_string, "4100");
14980 mips_set_option_string (&mips_tune_string, "4100");
14983 case OPTION_NO_M4100:
14987 mips_set_option_string (&mips_arch_string, "3900");
14988 mips_set_option_string (&mips_tune_string, "3900");
14991 case OPTION_NO_M3900:
14995 mips_opts.ase |= ASE_MDMX;
14996 file_ase_explicit |= ASE_MDMX;
14999 case OPTION_NO_MDMX:
15000 mips_opts.ase &= ~ASE_MDMX;
15001 file_ase_explicit |= ASE_MDMX;
15005 mips_opts.ase |= ASE_DSP;
15006 mips_opts.ase &= ~ASE_DSPR2;
15007 file_ase_explicit |= ASE_DSP | ASE_DSPR2;
15011 mips_opts.ase |= ASE_DSP | ASE_DSPR2;
15012 file_ase_explicit |= ASE_DSP | ASE_DSPR2;
15015 case OPTION_NO_DSP:
15016 case OPTION_NO_DSPR2:
15017 mips_opts.ase &= ~(ASE_DSP | ASE_DSPR2);
15018 file_ase_explicit |= ASE_DSP | ASE_DSPR2;
15022 mips_opts.ase |= ASE_EVA;
15023 file_ase_explicit |= ASE_EVA;
15026 case OPTION_NO_EVA:
15027 mips_opts.ase &= ~ASE_EVA;
15028 file_ase_explicit |= ASE_EVA;
15032 mips_opts.ase |= ASE_MT;
15033 file_ase_explicit |= ASE_MT;
15037 mips_opts.ase &= ~ASE_MT;
15038 file_ase_explicit |= ASE_MT;
15042 mips_opts.ase |= ASE_MCU;
15043 file_ase_explicit |= ASE_MCU;
15046 case OPTION_NO_MCU:
15047 mips_opts.ase &= ~ASE_MCU;
15048 file_ase_explicit |= ASE_MCU;
15051 case OPTION_MICROMIPS:
15052 if (mips_opts.mips16 == 1)
15054 as_bad (_("-mmicromips cannot be used with -mips16"));
15057 mips_opts.micromips = 1;
15058 mips_no_prev_insn ();
15061 case OPTION_NO_MICROMIPS:
15062 mips_opts.micromips = 0;
15063 mips_no_prev_insn ();
15067 mips_opts.ase |= ASE_VIRT;
15068 file_ase_explicit |= ASE_VIRT;
15071 case OPTION_NO_VIRT:
15072 mips_opts.ase &= ~ASE_VIRT;
15073 file_ase_explicit |= ASE_VIRT;
15076 case OPTION_MIPS16:
15077 if (mips_opts.micromips == 1)
15079 as_bad (_("-mips16 cannot be used with -micromips"));
15082 mips_opts.mips16 = 1;
15083 mips_no_prev_insn ();
15086 case OPTION_NO_MIPS16:
15087 mips_opts.mips16 = 0;
15088 mips_no_prev_insn ();
15091 case OPTION_MIPS3D:
15092 mips_opts.ase |= ASE_MIPS3D;
15093 file_ase_explicit |= ASE_MIPS3D;
15096 case OPTION_NO_MIPS3D:
15097 mips_opts.ase &= ~ASE_MIPS3D;
15098 file_ase_explicit |= ASE_MIPS3D;
15101 case OPTION_SMARTMIPS:
15102 mips_opts.ase |= ASE_SMARTMIPS;
15103 file_ase_explicit |= ASE_SMARTMIPS;
15106 case OPTION_NO_SMARTMIPS:
15107 mips_opts.ase &= ~ASE_SMARTMIPS;
15108 file_ase_explicit |= ASE_SMARTMIPS;
15111 case OPTION_FIX_24K:
15115 case OPTION_NO_FIX_24K:
15119 case OPTION_FIX_LOONGSON2F_JUMP:
15120 mips_fix_loongson2f_jump = TRUE;
15123 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15124 mips_fix_loongson2f_jump = FALSE;
15127 case OPTION_FIX_LOONGSON2F_NOP:
15128 mips_fix_loongson2f_nop = TRUE;
15131 case OPTION_NO_FIX_LOONGSON2F_NOP:
15132 mips_fix_loongson2f_nop = FALSE;
15135 case OPTION_FIX_VR4120:
15136 mips_fix_vr4120 = 1;
15139 case OPTION_NO_FIX_VR4120:
15140 mips_fix_vr4120 = 0;
15143 case OPTION_FIX_VR4130:
15144 mips_fix_vr4130 = 1;
15147 case OPTION_NO_FIX_VR4130:
15148 mips_fix_vr4130 = 0;
15151 case OPTION_FIX_CN63XXP1:
15152 mips_fix_cn63xxp1 = TRUE;
15155 case OPTION_NO_FIX_CN63XXP1:
15156 mips_fix_cn63xxp1 = FALSE;
15159 case OPTION_RELAX_BRANCH:
15160 mips_relax_branch = 1;
15163 case OPTION_NO_RELAX_BRANCH:
15164 mips_relax_branch = 0;
15167 case OPTION_MSHARED:
15168 mips_in_shared = TRUE;
15171 case OPTION_MNO_SHARED:
15172 mips_in_shared = FALSE;
15175 case OPTION_MSYM32:
15176 mips_opts.sym32 = TRUE;
15179 case OPTION_MNO_SYM32:
15180 mips_opts.sym32 = FALSE;
15184 /* When generating ELF code, we permit -KPIC and -call_shared to
15185 select SVR4_PIC, and -non_shared to select no PIC. This is
15186 intended to be compatible with Irix 5. */
15187 case OPTION_CALL_SHARED:
15190 as_bad (_("-call_shared is supported only for ELF format"));
15193 mips_pic = SVR4_PIC;
15194 mips_abicalls = TRUE;
15197 case OPTION_CALL_NONPIC:
15200 as_bad (_("-call_nonpic is supported only for ELF format"));
15204 mips_abicalls = TRUE;
15207 case OPTION_NON_SHARED:
15210 as_bad (_("-non_shared is supported only for ELF format"));
15214 mips_abicalls = FALSE;
15217 /* The -xgot option tells the assembler to use 32 bit offsets
15218 when accessing the got in SVR4_PIC mode. It is for Irix
15223 #endif /* OBJ_ELF */
15226 g_switch_value = atoi (arg);
15230 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15234 mips_abi = O32_ABI;
15235 /* We silently ignore -32 for non-ELF targets. This greatly
15236 simplifies the construction of the MIPS GAS test cases. */
15243 as_bad (_("-n32 is supported for ELF format only"));
15246 mips_abi = N32_ABI;
15252 as_bad (_("-64 is supported for ELF format only"));
15255 mips_abi = N64_ABI;
15256 if (!support_64bit_objects())
15257 as_fatal (_("No compiled in support for 64 bit object file format"));
15259 #endif /* OBJ_ELF */
15262 file_mips_gp32 = 1;
15266 file_mips_gp32 = 0;
15270 file_mips_fp32 = 1;
15274 file_mips_fp32 = 0;
15277 case OPTION_SINGLE_FLOAT:
15278 file_mips_single_float = 1;
15281 case OPTION_DOUBLE_FLOAT:
15282 file_mips_single_float = 0;
15285 case OPTION_SOFT_FLOAT:
15286 file_mips_soft_float = 1;
15289 case OPTION_HARD_FLOAT:
15290 file_mips_soft_float = 0;
15297 as_bad (_("-mabi is supported for ELF format only"));
15300 if (strcmp (arg, "32") == 0)
15301 mips_abi = O32_ABI;
15302 else if (strcmp (arg, "o64") == 0)
15303 mips_abi = O64_ABI;
15304 else if (strcmp (arg, "n32") == 0)
15305 mips_abi = N32_ABI;
15306 else if (strcmp (arg, "64") == 0)
15308 mips_abi = N64_ABI;
15309 if (! support_64bit_objects())
15310 as_fatal (_("No compiled in support for 64 bit object file "
15313 else if (strcmp (arg, "eabi") == 0)
15314 mips_abi = EABI_ABI;
15317 as_fatal (_("invalid abi -mabi=%s"), arg);
15321 #endif /* OBJ_ELF */
15323 case OPTION_M7000_HILO_FIX:
15324 mips_7000_hilo_fix = TRUE;
15327 case OPTION_MNO_7000_HILO_FIX:
15328 mips_7000_hilo_fix = FALSE;
15332 case OPTION_MDEBUG:
15333 mips_flag_mdebug = TRUE;
15336 case OPTION_NO_MDEBUG:
15337 mips_flag_mdebug = FALSE;
15341 mips_flag_pdr = TRUE;
15344 case OPTION_NO_PDR:
15345 mips_flag_pdr = FALSE;
15348 case OPTION_MVXWORKS_PIC:
15349 mips_pic = VXWORKS_PIC;
15351 #endif /* OBJ_ELF */
15357 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15362 /* Set up globals to generate code for the ISA or processor
15363 described by INFO. */
15366 mips_set_architecture (const struct mips_cpu_info *info)
15370 file_mips_arch = info->cpu;
15371 mips_opts.arch = info->cpu;
15372 mips_opts.isa = info->isa;
15377 /* Likewise for tuning. */
15380 mips_set_tune (const struct mips_cpu_info *info)
15383 mips_tune = info->cpu;
15388 mips_after_parse_args (void)
15390 const struct mips_cpu_info *arch_info = 0;
15391 const struct mips_cpu_info *tune_info = 0;
15393 /* GP relative stuff not working for PE */
15394 if (strncmp (TARGET_OS, "pe", 2) == 0)
15396 if (g_switch_seen && g_switch_value != 0)
15397 as_bad (_("-G not supported in this configuration."));
15398 g_switch_value = 0;
15401 if (mips_abi == NO_ABI)
15402 mips_abi = MIPS_DEFAULT_ABI;
15404 /* The following code determines the architecture and register size.
15405 Similar code was added to GCC 3.3 (see override_options() in
15406 config/mips/mips.c). The GAS and GCC code should be kept in sync
15407 as much as possible. */
15409 if (mips_arch_string != 0)
15410 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15412 if (file_mips_isa != ISA_UNKNOWN)
15414 /* Handle -mipsN. At this point, file_mips_isa contains the
15415 ISA level specified by -mipsN, while arch_info->isa contains
15416 the -march selection (if any). */
15417 if (arch_info != 0)
15419 /* -march takes precedence over -mipsN, since it is more descriptive.
15420 There's no harm in specifying both as long as the ISA levels
15422 if (file_mips_isa != arch_info->isa)
15423 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15424 mips_cpu_info_from_isa (file_mips_isa)->name,
15425 mips_cpu_info_from_isa (arch_info->isa)->name);
15428 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15431 if (arch_info == 0)
15433 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15434 gas_assert (arch_info);
15437 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15438 as_bad (_("-march=%s is not compatible with the selected ABI"),
15441 mips_set_architecture (arch_info);
15443 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15444 if (mips_tune_string != 0)
15445 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15447 if (tune_info == 0)
15448 mips_set_tune (arch_info);
15450 mips_set_tune (tune_info);
15452 if (file_mips_gp32 >= 0)
15454 /* The user specified the size of the integer registers. Make sure
15455 it agrees with the ABI and ISA. */
15456 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15457 as_bad (_("-mgp64 used with a 32-bit processor"));
15458 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15459 as_bad (_("-mgp32 used with a 64-bit ABI"));
15460 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15461 as_bad (_("-mgp64 used with a 32-bit ABI"));
15465 /* Infer the integer register size from the ABI and processor.
15466 Restrict ourselves to 32-bit registers if that's all the
15467 processor has, or if the ABI cannot handle 64-bit registers. */
15468 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15469 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15472 switch (file_mips_fp32)
15476 /* No user specified float register size.
15477 ??? GAS treats single-float processors as though they had 64-bit
15478 float registers (although it complains when double-precision
15479 instructions are used). As things stand, saying they have 32-bit
15480 registers would lead to spurious "register must be even" messages.
15481 So here we assume float registers are never smaller than the
15483 if (file_mips_gp32 == 0)
15484 /* 64-bit integer registers implies 64-bit float registers. */
15485 file_mips_fp32 = 0;
15486 else if ((mips_opts.ase & (ASE_MIPS3D | ASE_MDMX))
15487 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15488 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15489 file_mips_fp32 = 0;
15491 /* 32-bit float registers. */
15492 file_mips_fp32 = 1;
15495 /* The user specified the size of the float registers. Check if it
15496 agrees with the ABI and ISA. */
15498 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15499 as_bad (_("-mfp64 used with a 32-bit fpu"));
15500 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15501 && !ISA_HAS_MXHC1 (mips_opts.isa))
15502 as_warn (_("-mfp64 used with a 32-bit ABI"));
15505 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15506 as_warn (_("-mfp32 used with a 64-bit ABI"));
15510 /* End of GCC-shared inference code. */
15512 /* This flag is set when we have a 64-bit capable CPU but use only
15513 32-bit wide registers. Note that EABI does not use it. */
15514 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15515 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15516 || mips_abi == O32_ABI))
15517 mips_32bitmode = 1;
15519 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15520 as_bad (_("trap exception not supported at ISA 1"));
15522 /* If the selected architecture includes support for ASEs, enable
15523 generation of code for them. */
15524 if (mips_opts.mips16 == -1)
15525 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15526 if (mips_opts.micromips == -1)
15527 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15529 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15530 ASEs from being selected implicitly. */
15531 if (file_mips_fp32 == 1)
15532 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15534 /* If the user didn't explicitly select or deselect a particular ASE,
15535 use the default setting for the CPU. */
15536 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15538 if ((mips_opts.ase & ASE_MIPS3D) && file_mips_fp32 == 1)
15539 as_bad (_("-mfp32 used with -mips3d"));
15541 if ((mips_opts.ase & ASE_MDMX) && file_mips_fp32 == 1)
15542 as_bad (_("-mfp32 used with -mdmx"));
15544 if ((mips_opts.ase & ASE_SMARTMIPS) && !ISA_SUPPORTS_SMARTMIPS)
15545 as_warn (_("%s ISA does not support SmartMIPS"),
15546 mips_cpu_info_from_isa (mips_opts.isa)->name);
15548 if ((mips_opts.ase & ASE_DSP) && !ISA_SUPPORTS_DSP_ASE)
15549 as_warn (_("%s ISA does not support DSP ASE"),
15550 mips_cpu_info_from_isa (mips_opts.isa)->name);
15552 if ((mips_opts.ase & ASE_DSPR2) && !ISA_SUPPORTS_DSPR2_ASE)
15553 as_warn (_("%s ISA does not support DSP R2 ASE"),
15554 mips_cpu_info_from_isa (mips_opts.isa)->name);
15556 if ((mips_opts.ase & ASE_EVA) && !ISA_SUPPORTS_EVA_ASE)
15557 as_warn (_("%s ISA does not support EVA ASE"),
15558 mips_cpu_info_from_isa (mips_opts.isa)->name);
15560 if ((mips_opts.ase & ASE_MT) && !ISA_SUPPORTS_MT_ASE)
15561 as_warn (_("%s ISA does not support MT ASE"),
15562 mips_cpu_info_from_isa (mips_opts.isa)->name);
15564 if ((mips_opts.ase & ASE_MCU) && !ISA_SUPPORTS_MCU_ASE)
15565 as_warn (_("%s ISA does not support MCU ASE"),
15566 mips_cpu_info_from_isa (mips_opts.isa)->name);
15568 if ((mips_opts.ase & ASE_VIRT) && !ISA_SUPPORTS_VIRT_ASE)
15569 as_warn (_("%s ISA does not support Virtualization ASE"),
15570 mips_cpu_info_from_isa (mips_opts.isa)->name);
15572 file_mips_isa = mips_opts.isa;
15573 file_ase = mips_opts.ase;
15574 mips_opts.gp32 = file_mips_gp32;
15575 mips_opts.fp32 = file_mips_fp32;
15576 mips_opts.soft_float = file_mips_soft_float;
15577 mips_opts.single_float = file_mips_single_float;
15579 if (mips_flag_mdebug < 0)
15581 #ifdef OBJ_MAYBE_ECOFF
15582 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15583 mips_flag_mdebug = 1;
15585 #endif /* OBJ_MAYBE_ECOFF */
15586 mips_flag_mdebug = 0;
15591 mips_init_after_args (void)
15593 /* initialize opcodes */
15594 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15595 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15599 md_pcrel_from (fixS *fixP)
15601 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15602 switch (fixP->fx_r_type)
15604 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15605 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15606 /* Return the address of the delay slot. */
15609 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15610 case BFD_RELOC_MICROMIPS_JMP:
15611 case BFD_RELOC_16_PCREL_S2:
15612 case BFD_RELOC_MIPS_JMP:
15613 /* Return the address of the delay slot. */
15616 case BFD_RELOC_32_PCREL:
15620 /* We have no relocation type for PC relative MIPS16 instructions. */
15621 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15622 as_bad_where (fixP->fx_file, fixP->fx_line,
15623 _("PC relative MIPS16 instruction references a different section"));
15628 /* This is called before the symbol table is processed. In order to
15629 work with gcc when using mips-tfile, we must keep all local labels.
15630 However, in other cases, we want to discard them. If we were
15631 called with -g, but we didn't see any debugging information, it may
15632 mean that gcc is smuggling debugging information through to
15633 mips-tfile, in which case we must generate all local labels. */
15636 mips_frob_file_before_adjust (void)
15638 #ifndef NO_ECOFF_DEBUGGING
15639 if (ECOFF_DEBUGGING
15641 && ! ecoff_debugging_seen)
15642 flag_keep_locals = 1;
15646 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15647 the corresponding LO16 reloc. This is called before md_apply_fix and
15648 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15649 relocation operators.
15651 For our purposes, a %lo() expression matches a %got() or %hi()
15654 (a) it refers to the same symbol; and
15655 (b) the offset applied in the %lo() expression is no lower than
15656 the offset applied in the %got() or %hi().
15658 (b) allows us to cope with code like:
15661 lh $4,%lo(foo+2)($4)
15663 ...which is legal on RELA targets, and has a well-defined behaviour
15664 if the user knows that adding 2 to "foo" will not induce a carry to
15667 When several %lo()s match a particular %got() or %hi(), we use the
15668 following rules to distinguish them:
15670 (1) %lo()s with smaller offsets are a better match than %lo()s with
15673 (2) %lo()s with no matching %got() or %hi() are better than those
15674 that already have a matching %got() or %hi().
15676 (3) later %lo()s are better than earlier %lo()s.
15678 These rules are applied in order.
15680 (1) means, among other things, that %lo()s with identical offsets are
15681 chosen if they exist.
15683 (2) means that we won't associate several high-part relocations with
15684 the same low-part relocation unless there's no alternative. Having
15685 several high parts for the same low part is a GNU extension; this rule
15686 allows careful users to avoid it.
15688 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15689 with the last high-part relocation being at the front of the list.
15690 It therefore makes sense to choose the last matching low-part
15691 relocation, all other things being equal. It's also easier
15692 to code that way. */
15695 mips_frob_file (void)
15697 struct mips_hi_fixup *l;
15698 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15700 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15702 segment_info_type *seginfo;
15703 bfd_boolean matched_lo_p;
15704 fixS **hi_pos, **lo_pos, **pos;
15706 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15708 /* If a GOT16 relocation turns out to be against a global symbol,
15709 there isn't supposed to be a matching LO. Ignore %gots against
15710 constants; we'll report an error for those later. */
15711 if (got16_reloc_p (l->fixp->fx_r_type)
15712 && !(l->fixp->fx_addsy
15713 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15716 /* Check quickly whether the next fixup happens to be a matching %lo. */
15717 if (fixup_has_matching_lo_p (l->fixp))
15720 seginfo = seg_info (l->seg);
15722 /* Set HI_POS to the position of this relocation in the chain.
15723 Set LO_POS to the position of the chosen low-part relocation.
15724 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15725 relocation that matches an immediately-preceding high-part
15729 matched_lo_p = FALSE;
15730 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15732 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15734 if (*pos == l->fixp)
15737 if ((*pos)->fx_r_type == looking_for_rtype
15738 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15739 && (*pos)->fx_offset >= l->fixp->fx_offset
15741 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15743 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15746 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15747 && fixup_has_matching_lo_p (*pos));
15750 /* If we found a match, remove the high-part relocation from its
15751 current position and insert it before the low-part relocation.
15752 Make the offsets match so that fixup_has_matching_lo_p()
15755 We don't warn about unmatched high-part relocations since some
15756 versions of gcc have been known to emit dead "lui ...%hi(...)"
15758 if (lo_pos != NULL)
15760 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15761 if (l->fixp->fx_next != *lo_pos)
15763 *hi_pos = l->fixp->fx_next;
15764 l->fixp->fx_next = *lo_pos;
15772 mips_force_relocation (fixS *fixp)
15774 if (generic_force_reloc (fixp))
15777 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15778 so that the linker relaxation can update targets. */
15779 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15780 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15781 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15787 /* Read the instruction associated with RELOC from BUF. */
15789 static unsigned int
15790 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15792 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15793 return read_compressed_insn (buf, 4);
15795 return read_insn (buf);
15798 /* Write instruction INSN to BUF, given that it has been relocated
15802 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15803 unsigned long insn)
15805 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15806 write_compressed_insn (buf, insn, 4);
15808 write_insn (buf, insn);
15811 /* Apply a fixup to the object file. */
15814 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15817 unsigned long insn;
15818 reloc_howto_type *howto;
15820 /* We ignore generic BFD relocations we don't know about. */
15821 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15825 gas_assert (fixP->fx_size == 2
15826 || fixP->fx_size == 4
15827 || fixP->fx_r_type == BFD_RELOC_16
15828 || fixP->fx_r_type == BFD_RELOC_64
15829 || fixP->fx_r_type == BFD_RELOC_CTOR
15830 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15831 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15832 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15833 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15834 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15836 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15838 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15839 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15840 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15841 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15842 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15844 /* Don't treat parts of a composite relocation as done. There are two
15847 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15848 should nevertheless be emitted if the first part is.
15850 (2) In normal usage, composite relocations are never assembly-time
15851 constants. The easiest way of dealing with the pathological
15852 exceptions is to generate a relocation against STN_UNDEF and
15853 leave everything up to the linker. */
15854 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15857 switch (fixP->fx_r_type)
15859 case BFD_RELOC_MIPS_TLS_GD:
15860 case BFD_RELOC_MIPS_TLS_LDM:
15861 case BFD_RELOC_MIPS_TLS_DTPREL32:
15862 case BFD_RELOC_MIPS_TLS_DTPREL64:
15863 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15864 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15865 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15866 case BFD_RELOC_MIPS_TLS_TPREL32:
15867 case BFD_RELOC_MIPS_TLS_TPREL64:
15868 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15869 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15870 case BFD_RELOC_MICROMIPS_TLS_GD:
15871 case BFD_RELOC_MICROMIPS_TLS_LDM:
15872 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15873 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15874 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15875 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15876 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15877 case BFD_RELOC_MIPS16_TLS_GD:
15878 case BFD_RELOC_MIPS16_TLS_LDM:
15879 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15880 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15881 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15882 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15883 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15884 if (!fixP->fx_addsy)
15886 as_bad_where (fixP->fx_file, fixP->fx_line,
15887 _("TLS relocation against a constant"));
15890 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15893 case BFD_RELOC_MIPS_JMP:
15894 case BFD_RELOC_MIPS_SHIFT5:
15895 case BFD_RELOC_MIPS_SHIFT6:
15896 case BFD_RELOC_MIPS_GOT_DISP:
15897 case BFD_RELOC_MIPS_GOT_PAGE:
15898 case BFD_RELOC_MIPS_GOT_OFST:
15899 case BFD_RELOC_MIPS_SUB:
15900 case BFD_RELOC_MIPS_INSERT_A:
15901 case BFD_RELOC_MIPS_INSERT_B:
15902 case BFD_RELOC_MIPS_DELETE:
15903 case BFD_RELOC_MIPS_HIGHEST:
15904 case BFD_RELOC_MIPS_HIGHER:
15905 case BFD_RELOC_MIPS_SCN_DISP:
15906 case BFD_RELOC_MIPS_REL16:
15907 case BFD_RELOC_MIPS_RELGOT:
15908 case BFD_RELOC_MIPS_JALR:
15909 case BFD_RELOC_HI16:
15910 case BFD_RELOC_HI16_S:
15911 case BFD_RELOC_LO16:
15912 case BFD_RELOC_GPREL16:
15913 case BFD_RELOC_MIPS_LITERAL:
15914 case BFD_RELOC_MIPS_CALL16:
15915 case BFD_RELOC_MIPS_GOT16:
15916 case BFD_RELOC_GPREL32:
15917 case BFD_RELOC_MIPS_GOT_HI16:
15918 case BFD_RELOC_MIPS_GOT_LO16:
15919 case BFD_RELOC_MIPS_CALL_HI16:
15920 case BFD_RELOC_MIPS_CALL_LO16:
15921 case BFD_RELOC_MIPS16_GPREL:
15922 case BFD_RELOC_MIPS16_GOT16:
15923 case BFD_RELOC_MIPS16_CALL16:
15924 case BFD_RELOC_MIPS16_HI16:
15925 case BFD_RELOC_MIPS16_HI16_S:
15926 case BFD_RELOC_MIPS16_LO16:
15927 case BFD_RELOC_MIPS16_JMP:
15928 case BFD_RELOC_MICROMIPS_JMP:
15929 case BFD_RELOC_MICROMIPS_GOT_DISP:
15930 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15931 case BFD_RELOC_MICROMIPS_GOT_OFST:
15932 case BFD_RELOC_MICROMIPS_SUB:
15933 case BFD_RELOC_MICROMIPS_HIGHEST:
15934 case BFD_RELOC_MICROMIPS_HIGHER:
15935 case BFD_RELOC_MICROMIPS_SCN_DISP:
15936 case BFD_RELOC_MICROMIPS_JALR:
15937 case BFD_RELOC_MICROMIPS_HI16:
15938 case BFD_RELOC_MICROMIPS_HI16_S:
15939 case BFD_RELOC_MICROMIPS_LO16:
15940 case BFD_RELOC_MICROMIPS_GPREL16:
15941 case BFD_RELOC_MICROMIPS_LITERAL:
15942 case BFD_RELOC_MICROMIPS_CALL16:
15943 case BFD_RELOC_MICROMIPS_GOT16:
15944 case BFD_RELOC_MICROMIPS_GOT_HI16:
15945 case BFD_RELOC_MICROMIPS_GOT_LO16:
15946 case BFD_RELOC_MICROMIPS_CALL_HI16:
15947 case BFD_RELOC_MICROMIPS_CALL_LO16:
15948 case BFD_RELOC_MIPS_EH:
15953 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15955 insn = read_reloc_insn (buf, fixP->fx_r_type);
15956 if (mips16_reloc_p (fixP->fx_r_type))
15957 insn |= mips16_immed_extend (value, 16);
15959 insn |= (value & 0xffff);
15960 write_reloc_insn (buf, fixP->fx_r_type, insn);
15963 as_bad_where (fixP->fx_file, fixP->fx_line,
15964 _("Unsupported constant in relocation"));
15969 /* This is handled like BFD_RELOC_32, but we output a sign
15970 extended value if we are only 32 bits. */
15973 if (8 <= sizeof (valueT))
15974 md_number_to_chars (buf, *valP, 8);
15979 if ((*valP & 0x80000000) != 0)
15983 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15984 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15989 case BFD_RELOC_RVA:
15991 case BFD_RELOC_32_PCREL:
15993 /* If we are deleting this reloc entry, we must fill in the
15994 value now. This can happen if we have a .word which is not
15995 resolved when it appears but is later defined. */
15997 md_number_to_chars (buf, *valP, fixP->fx_size);
16000 case BFD_RELOC_16_PCREL_S2:
16001 if ((*valP & 0x3) != 0)
16002 as_bad_where (fixP->fx_file, fixP->fx_line,
16003 _("Branch to misaligned address (%lx)"), (long) *valP);
16005 /* We need to save the bits in the instruction since fixup_segment()
16006 might be deleting the relocation entry (i.e., a branch within
16007 the current segment). */
16008 if (! fixP->fx_done)
16011 /* Update old instruction data. */
16012 insn = read_insn (buf);
16014 if (*valP + 0x20000 <= 0x3ffff)
16016 insn |= (*valP >> 2) & 0xffff;
16017 write_insn (buf, insn);
16019 else if (mips_pic == NO_PIC
16021 && fixP->fx_frag->fr_address >= text_section->vma
16022 && (fixP->fx_frag->fr_address
16023 < text_section->vma + bfd_get_section_size (text_section))
16024 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
16025 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
16026 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
16028 /* The branch offset is too large. If this is an
16029 unconditional branch, and we are not generating PIC code,
16030 we can convert it to an absolute jump instruction. */
16031 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
16032 insn = 0x0c000000; /* jal */
16034 insn = 0x08000000; /* j */
16035 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
16037 fixP->fx_addsy = section_symbol (text_section);
16038 *valP += md_pcrel_from (fixP);
16039 write_insn (buf, insn);
16043 /* If we got here, we have branch-relaxation disabled,
16044 and there's nothing we can do to fix this instruction
16045 without turning it into a longer sequence. */
16046 as_bad_where (fixP->fx_file, fixP->fx_line,
16047 _("Branch out of range"));
16051 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
16052 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
16053 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
16054 /* We adjust the offset back to even. */
16055 if ((*valP & 0x1) != 0)
16058 if (! fixP->fx_done)
16061 /* Should never visit here, because we keep the relocation. */
16065 case BFD_RELOC_VTABLE_INHERIT:
16068 && !S_IS_DEFINED (fixP->fx_addsy)
16069 && !S_IS_WEAK (fixP->fx_addsy))
16070 S_SET_WEAK (fixP->fx_addsy);
16073 case BFD_RELOC_VTABLE_ENTRY:
16081 /* Remember value for tc_gen_reloc. */
16082 fixP->fx_addnumber = *valP;
16092 name = input_line_pointer;
16093 c = get_symbol_end ();
16094 p = (symbolS *) symbol_find_or_make (name);
16095 *input_line_pointer = c;
16099 /* Align the current frag to a given power of two. If a particular
16100 fill byte should be used, FILL points to an integer that contains
16101 that byte, otherwise FILL is null.
16103 This function used to have the comment:
16105 The MIPS assembler also automatically adjusts any preceding label.
16107 The implementation therefore applied the adjustment to a maximum of
16108 one label. However, other label adjustments are applied to batches
16109 of labels, and adjusting just one caused problems when new labels
16110 were added for the sake of debugging or unwind information.
16111 We therefore adjust all preceding labels (given as LABELS) instead. */
16114 mips_align (int to, int *fill, struct insn_label_list *labels)
16116 mips_emit_delays ();
16117 mips_record_compressed_mode ();
16118 if (fill == NULL && subseg_text_p (now_seg))
16119 frag_align_code (to, 0);
16121 frag_align (to, fill ? *fill : 0, 0);
16122 record_alignment (now_seg, to);
16123 mips_move_labels (labels, FALSE);
16126 /* Align to a given power of two. .align 0 turns off the automatic
16127 alignment used by the data creating pseudo-ops. */
16130 s_align (int x ATTRIBUTE_UNUSED)
16132 int temp, fill_value, *fill_ptr;
16133 long max_alignment = 28;
16135 /* o Note that the assembler pulls down any immediately preceding label
16136 to the aligned address.
16137 o It's not documented but auto alignment is reinstated by
16138 a .align pseudo instruction.
16139 o Note also that after auto alignment is turned off the mips assembler
16140 issues an error on attempt to assemble an improperly aligned data item.
16143 temp = get_absolute_expression ();
16144 if (temp > max_alignment)
16145 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16148 as_warn (_("Alignment negative: 0 assumed."));
16151 if (*input_line_pointer == ',')
16153 ++input_line_pointer;
16154 fill_value = get_absolute_expression ();
16155 fill_ptr = &fill_value;
16161 segment_info_type *si = seg_info (now_seg);
16162 struct insn_label_list *l = si->label_list;
16163 /* Auto alignment should be switched on by next section change. */
16165 mips_align (temp, fill_ptr, l);
16172 demand_empty_rest_of_line ();
16176 s_change_sec (int sec)
16181 /* The ELF backend needs to know that we are changing sections, so
16182 that .previous works correctly. We could do something like check
16183 for an obj_section_change_hook macro, but that might be confusing
16184 as it would not be appropriate to use it in the section changing
16185 functions in read.c, since obj-elf.c intercepts those. FIXME:
16186 This should be cleaner, somehow. */
16188 obj_elf_section_change_hook ();
16191 mips_emit_delays ();
16202 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16203 demand_empty_rest_of_line ();
16207 seg = subseg_new (RDATA_SECTION_NAME,
16208 (subsegT) get_absolute_expression ());
16211 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16212 | SEC_READONLY | SEC_RELOC
16214 if (strncmp (TARGET_OS, "elf", 3) != 0)
16215 record_alignment (seg, 4);
16217 demand_empty_rest_of_line ();
16221 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16224 bfd_set_section_flags (stdoutput, seg,
16225 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16226 if (strncmp (TARGET_OS, "elf", 3) != 0)
16227 record_alignment (seg, 4);
16229 demand_empty_rest_of_line ();
16233 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16236 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16237 if (strncmp (TARGET_OS, "elf", 3) != 0)
16238 record_alignment (seg, 4);
16240 demand_empty_rest_of_line ();
16248 s_change_section (int ignore ATTRIBUTE_UNUSED)
16251 char *section_name;
16256 int section_entry_size;
16257 int section_alignment;
16262 section_name = input_line_pointer;
16263 c = get_symbol_end ();
16265 next_c = *(input_line_pointer + 1);
16267 /* Do we have .section Name<,"flags">? */
16268 if (c != ',' || (c == ',' && next_c == '"'))
16270 /* just after name is now '\0'. */
16271 *input_line_pointer = c;
16272 input_line_pointer = section_name;
16273 obj_elf_section (ignore);
16276 input_line_pointer++;
16278 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16280 section_type = get_absolute_expression ();
16283 if (*input_line_pointer++ == ',')
16284 section_flag = get_absolute_expression ();
16287 if (*input_line_pointer++ == ',')
16288 section_entry_size = get_absolute_expression ();
16290 section_entry_size = 0;
16291 if (*input_line_pointer++ == ',')
16292 section_alignment = get_absolute_expression ();
16294 section_alignment = 0;
16295 /* FIXME: really ignore? */
16296 (void) section_alignment;
16298 section_name = xstrdup (section_name);
16300 /* When using the generic form of .section (as implemented by obj-elf.c),
16301 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16302 traditionally had to fall back on the more common @progbits instead.
16304 There's nothing really harmful in this, since bfd will correct
16305 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16306 means that, for backwards compatibility, the special_section entries
16307 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16309 Even so, we shouldn't force users of the MIPS .section syntax to
16310 incorrectly label the sections as SHT_PROGBITS. The best compromise
16311 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16312 generic type-checking code. */
16313 if (section_type == SHT_MIPS_DWARF)
16314 section_type = SHT_PROGBITS;
16316 obj_elf_change_section (section_name, section_type, section_flag,
16317 section_entry_size, 0, 0, 0);
16319 if (now_seg->name != section_name)
16320 free (section_name);
16321 #endif /* OBJ_ELF */
16325 mips_enable_auto_align (void)
16331 s_cons (int log_size)
16333 segment_info_type *si = seg_info (now_seg);
16334 struct insn_label_list *l = si->label_list;
16336 mips_emit_delays ();
16337 if (log_size > 0 && auto_align)
16338 mips_align (log_size, 0, l);
16339 cons (1 << log_size);
16340 mips_clear_insn_labels ();
16344 s_float_cons (int type)
16346 segment_info_type *si = seg_info (now_seg);
16347 struct insn_label_list *l = si->label_list;
16349 mips_emit_delays ();
16354 mips_align (3, 0, l);
16356 mips_align (2, 0, l);
16360 mips_clear_insn_labels ();
16363 /* Handle .globl. We need to override it because on Irix 5 you are
16366 where foo is an undefined symbol, to mean that foo should be
16367 considered to be the address of a function. */
16370 s_mips_globl (int x ATTRIBUTE_UNUSED)
16379 name = input_line_pointer;
16380 c = get_symbol_end ();
16381 symbolP = symbol_find_or_make (name);
16382 S_SET_EXTERNAL (symbolP);
16384 *input_line_pointer = c;
16385 SKIP_WHITESPACE ();
16387 /* On Irix 5, every global symbol that is not explicitly labelled as
16388 being a function is apparently labelled as being an object. */
16391 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16392 && (*input_line_pointer != ','))
16397 secname = input_line_pointer;
16398 c = get_symbol_end ();
16399 sec = bfd_get_section_by_name (stdoutput, secname);
16401 as_bad (_("%s: no such section"), secname);
16402 *input_line_pointer = c;
16404 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16405 flag = BSF_FUNCTION;
16408 symbol_get_bfdsym (symbolP)->flags |= flag;
16410 c = *input_line_pointer;
16413 input_line_pointer++;
16414 SKIP_WHITESPACE ();
16415 if (is_end_of_line[(unsigned char) *input_line_pointer])
16421 demand_empty_rest_of_line ();
16425 s_option (int x ATTRIBUTE_UNUSED)
16430 opt = input_line_pointer;
16431 c = get_symbol_end ();
16435 /* FIXME: What does this mean? */
16437 else if (strncmp (opt, "pic", 3) == 0)
16441 i = atoi (opt + 3);
16446 mips_pic = SVR4_PIC;
16447 mips_abicalls = TRUE;
16450 as_bad (_(".option pic%d not supported"), i);
16452 if (mips_pic == SVR4_PIC)
16454 if (g_switch_seen && g_switch_value != 0)
16455 as_warn (_("-G may not be used with SVR4 PIC code"));
16456 g_switch_value = 0;
16457 bfd_set_gp_size (stdoutput, 0);
16461 as_warn (_("Unrecognized option \"%s\""), opt);
16463 *input_line_pointer = c;
16464 demand_empty_rest_of_line ();
16467 /* This structure is used to hold a stack of .set values. */
16469 struct mips_option_stack
16471 struct mips_option_stack *next;
16472 struct mips_set_options options;
16475 static struct mips_option_stack *mips_opts_stack;
16477 /* Handle the .set pseudo-op. */
16480 s_mipsset (int x ATTRIBUTE_UNUSED)
16482 char *name = input_line_pointer, ch;
16484 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16485 ++input_line_pointer;
16486 ch = *input_line_pointer;
16487 *input_line_pointer = '\0';
16489 if (strcmp (name, "reorder") == 0)
16491 if (mips_opts.noreorder)
16494 else if (strcmp (name, "noreorder") == 0)
16496 if (!mips_opts.noreorder)
16497 start_noreorder ();
16499 else if (strncmp (name, "at=", 3) == 0)
16501 char *s = name + 3;
16503 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16504 as_bad (_("Unrecognized register name `%s'"), s);
16506 else if (strcmp (name, "at") == 0)
16508 mips_opts.at = ATREG;
16510 else if (strcmp (name, "noat") == 0)
16512 mips_opts.at = ZERO;
16514 else if (strcmp (name, "macro") == 0)
16516 mips_opts.warn_about_macros = 0;
16518 else if (strcmp (name, "nomacro") == 0)
16520 if (mips_opts.noreorder == 0)
16521 as_bad (_("`noreorder' must be set before `nomacro'"));
16522 mips_opts.warn_about_macros = 1;
16524 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16526 mips_opts.nomove = 0;
16528 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16530 mips_opts.nomove = 1;
16532 else if (strcmp (name, "bopt") == 0)
16534 mips_opts.nobopt = 0;
16536 else if (strcmp (name, "nobopt") == 0)
16538 mips_opts.nobopt = 1;
16540 else if (strcmp (name, "gp=default") == 0)
16541 mips_opts.gp32 = file_mips_gp32;
16542 else if (strcmp (name, "gp=32") == 0)
16543 mips_opts.gp32 = 1;
16544 else if (strcmp (name, "gp=64") == 0)
16546 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16547 as_warn (_("%s isa does not support 64-bit registers"),
16548 mips_cpu_info_from_isa (mips_opts.isa)->name);
16549 mips_opts.gp32 = 0;
16551 else if (strcmp (name, "fp=default") == 0)
16552 mips_opts.fp32 = file_mips_fp32;
16553 else if (strcmp (name, "fp=32") == 0)
16554 mips_opts.fp32 = 1;
16555 else if (strcmp (name, "fp=64") == 0)
16557 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16558 as_warn (_("%s isa does not support 64-bit floating point registers"),
16559 mips_cpu_info_from_isa (mips_opts.isa)->name);
16560 mips_opts.fp32 = 0;
16562 else if (strcmp (name, "softfloat") == 0)
16563 mips_opts.soft_float = 1;
16564 else if (strcmp (name, "hardfloat") == 0)
16565 mips_opts.soft_float = 0;
16566 else if (strcmp (name, "singlefloat") == 0)
16567 mips_opts.single_float = 1;
16568 else if (strcmp (name, "doublefloat") == 0)
16569 mips_opts.single_float = 0;
16570 else if (strcmp (name, "mips16") == 0
16571 || strcmp (name, "MIPS-16") == 0)
16573 if (mips_opts.micromips == 1)
16574 as_fatal (_("`mips16' cannot be used with `micromips'"));
16575 mips_opts.mips16 = 1;
16577 else if (strcmp (name, "nomips16") == 0
16578 || strcmp (name, "noMIPS-16") == 0)
16579 mips_opts.mips16 = 0;
16580 else if (strcmp (name, "micromips") == 0)
16582 if (mips_opts.mips16 == 1)
16583 as_fatal (_("`micromips' cannot be used with `mips16'"));
16584 mips_opts.micromips = 1;
16586 else if (strcmp (name, "nomicromips") == 0)
16587 mips_opts.micromips = 0;
16588 else if (strcmp (name, "smartmips") == 0)
16590 if (!ISA_SUPPORTS_SMARTMIPS)
16591 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16592 mips_cpu_info_from_isa (mips_opts.isa)->name);
16593 mips_opts.ase |= ASE_SMARTMIPS;
16595 else if (strcmp (name, "nosmartmips") == 0)
16596 mips_opts.ase &= ~ASE_SMARTMIPS;
16597 else if (strcmp (name, "mips3d") == 0)
16598 mips_opts.ase |= ASE_MIPS3D;
16599 else if (strcmp (name, "nomips3d") == 0)
16600 mips_opts.ase &= ~ASE_MIPS3D;
16601 else if (strcmp (name, "mdmx") == 0)
16602 mips_opts.ase |= ASE_MDMX;
16603 else if (strcmp (name, "nomdmx") == 0)
16604 mips_opts.ase &= ~ASE_MDMX;
16605 else if (strcmp (name, "dsp") == 0)
16607 if (!ISA_SUPPORTS_DSP_ASE)
16608 as_warn (_("%s ISA does not support DSP ASE"),
16609 mips_cpu_info_from_isa (mips_opts.isa)->name);
16610 mips_opts.ase |= ASE_DSP;
16611 mips_opts.ase &= ~ASE_DSPR2;
16613 else if (strcmp (name, "dspr2") == 0)
16615 if (!ISA_SUPPORTS_DSPR2_ASE)
16616 as_warn (_("%s ISA does not support DSP R2 ASE"),
16617 mips_cpu_info_from_isa (mips_opts.isa)->name);
16618 mips_opts.ase |= ASE_DSP | ASE_DSPR2;
16620 else if (strcmp (name, "nodsp") == 0
16621 || strcmp (name, "nodspr2") == 0)
16622 mips_opts.ase &= ~(ASE_DSP | ASE_DSPR2);
16623 else if (strcmp (name, "eva") == 0)
16625 if (!ISA_SUPPORTS_EVA_ASE)
16626 as_warn (_("%s ISA does not support EVA ASE"),
16627 mips_cpu_info_from_isa (mips_opts.isa)->name);
16628 mips_opts.ase |= ASE_EVA;
16630 else if (strcmp (name, "noeva") == 0)
16631 mips_opts.ase &= ~ASE_EVA;
16632 else if (strcmp (name, "mt") == 0)
16634 if (!ISA_SUPPORTS_MT_ASE)
16635 as_warn (_("%s ISA does not support MT ASE"),
16636 mips_cpu_info_from_isa (mips_opts.isa)->name);
16637 mips_opts.ase |= ASE_MT;
16639 else if (strcmp (name, "nomt") == 0)
16640 mips_opts.ase &= ~ASE_MT;
16641 else if (strcmp (name, "mcu") == 0)
16642 mips_opts.ase |= ASE_MCU;
16643 else if (strcmp (name, "nomcu") == 0)
16644 mips_opts.ase &= ~ASE_MCU;
16645 else if (strcmp (name, "virt") == 0)
16647 if (!ISA_SUPPORTS_VIRT_ASE)
16648 as_warn (_("%s ISA does not support Virtualization ASE"),
16649 mips_cpu_info_from_isa (mips_opts.isa)->name);
16650 mips_opts.ase |= ASE_VIRT;
16652 else if (strcmp (name, "novirt") == 0)
16653 mips_opts.ase &= ~ASE_VIRT;
16654 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16658 /* Permit the user to change the ISA and architecture on the fly.
16659 Needless to say, misuse can cause serious problems. */
16660 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16663 mips_opts.isa = file_mips_isa;
16664 mips_opts.arch = file_mips_arch;
16666 else if (strncmp (name, "arch=", 5) == 0)
16668 const struct mips_cpu_info *p;
16670 p = mips_parse_cpu("internal use", name + 5);
16672 as_bad (_("unknown architecture %s"), name + 5);
16675 mips_opts.arch = p->cpu;
16676 mips_opts.isa = p->isa;
16679 else if (strncmp (name, "mips", 4) == 0)
16681 const struct mips_cpu_info *p;
16683 p = mips_parse_cpu("internal use", name);
16685 as_bad (_("unknown ISA level %s"), name + 4);
16688 mips_opts.arch = p->cpu;
16689 mips_opts.isa = p->isa;
16693 as_bad (_("unknown ISA or architecture %s"), name);
16695 switch (mips_opts.isa)
16703 mips_opts.gp32 = 1;
16704 mips_opts.fp32 = 1;
16711 mips_opts.gp32 = 0;
16712 if (mips_opts.arch == CPU_R5900)
16714 mips_opts.fp32 = 1;
16718 mips_opts.fp32 = 0;
16722 as_bad (_("unknown ISA level %s"), name + 4);
16727 mips_opts.gp32 = file_mips_gp32;
16728 mips_opts.fp32 = file_mips_fp32;
16731 else if (strcmp (name, "autoextend") == 0)
16732 mips_opts.noautoextend = 0;
16733 else if (strcmp (name, "noautoextend") == 0)
16734 mips_opts.noautoextend = 1;
16735 else if (strcmp (name, "push") == 0)
16737 struct mips_option_stack *s;
16739 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16740 s->next = mips_opts_stack;
16741 s->options = mips_opts;
16742 mips_opts_stack = s;
16744 else if (strcmp (name, "pop") == 0)
16746 struct mips_option_stack *s;
16748 s = mips_opts_stack;
16750 as_bad (_(".set pop with no .set push"));
16753 /* If we're changing the reorder mode we need to handle
16754 delay slots correctly. */
16755 if (s->options.noreorder && ! mips_opts.noreorder)
16756 start_noreorder ();
16757 else if (! s->options.noreorder && mips_opts.noreorder)
16760 mips_opts = s->options;
16761 mips_opts_stack = s->next;
16765 else if (strcmp (name, "sym32") == 0)
16766 mips_opts.sym32 = TRUE;
16767 else if (strcmp (name, "nosym32") == 0)
16768 mips_opts.sym32 = FALSE;
16769 else if (strchr (name, ','))
16771 /* Generic ".set" directive; use the generic handler. */
16772 *input_line_pointer = ch;
16773 input_line_pointer = name;
16779 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16781 *input_line_pointer = ch;
16782 demand_empty_rest_of_line ();
16785 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16786 .option pic2. It means to generate SVR4 PIC calls. */
16789 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16791 mips_pic = SVR4_PIC;
16792 mips_abicalls = TRUE;
16794 if (g_switch_seen && g_switch_value != 0)
16795 as_warn (_("-G may not be used with SVR4 PIC code"));
16796 g_switch_value = 0;
16798 bfd_set_gp_size (stdoutput, 0);
16799 demand_empty_rest_of_line ();
16802 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16803 PIC code. It sets the $gp register for the function based on the
16804 function address, which is in the register named in the argument.
16805 This uses a relocation against _gp_disp, which is handled specially
16806 by the linker. The result is:
16807 lui $gp,%hi(_gp_disp)
16808 addiu $gp,$gp,%lo(_gp_disp)
16809 addu $gp,$gp,.cpload argument
16810 The .cpload argument is normally $25 == $t9.
16812 The -mno-shared option changes this to:
16813 lui $gp,%hi(__gnu_local_gp)
16814 addiu $gp,$gp,%lo(__gnu_local_gp)
16815 and the argument is ignored. This saves an instruction, but the
16816 resulting code is not position independent; it uses an absolute
16817 address for __gnu_local_gp. Thus code assembled with -mno-shared
16818 can go into an ordinary executable, but not into a shared library. */
16821 s_cpload (int ignore ATTRIBUTE_UNUSED)
16827 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16828 .cpload is ignored. */
16829 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16835 if (mips_opts.mips16)
16837 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16838 ignore_rest_of_line ();
16842 /* .cpload should be in a .set noreorder section. */
16843 if (mips_opts.noreorder == 0)
16844 as_warn (_(".cpload not in noreorder section"));
16846 reg = tc_get_register (0);
16848 /* If we need to produce a 64-bit address, we are better off using
16849 the default instruction sequence. */
16850 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16852 ex.X_op = O_symbol;
16853 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16855 ex.X_op_symbol = NULL;
16856 ex.X_add_number = 0;
16858 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16859 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16861 mips_mark_labels ();
16862 mips_assembling_insn = TRUE;
16865 macro_build_lui (&ex, mips_gp_register);
16866 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16867 mips_gp_register, BFD_RELOC_LO16);
16869 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16870 mips_gp_register, reg);
16873 mips_assembling_insn = FALSE;
16874 demand_empty_rest_of_line ();
16877 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16878 .cpsetup $reg1, offset|$reg2, label
16880 If offset is given, this results in:
16881 sd $gp, offset($sp)
16882 lui $gp, %hi(%neg(%gp_rel(label)))
16883 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16884 daddu $gp, $gp, $reg1
16886 If $reg2 is given, this results in:
16887 daddu $reg2, $gp, $0
16888 lui $gp, %hi(%neg(%gp_rel(label)))
16889 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16890 daddu $gp, $gp, $reg1
16891 $reg1 is normally $25 == $t9.
16893 The -mno-shared option replaces the last three instructions with
16895 addiu $gp,$gp,%lo(_gp) */
16898 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16900 expressionS ex_off;
16901 expressionS ex_sym;
16904 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16905 We also need NewABI support. */
16906 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16912 if (mips_opts.mips16)
16914 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16915 ignore_rest_of_line ();
16919 reg1 = tc_get_register (0);
16920 SKIP_WHITESPACE ();
16921 if (*input_line_pointer != ',')
16923 as_bad (_("missing argument separator ',' for .cpsetup"));
16927 ++input_line_pointer;
16928 SKIP_WHITESPACE ();
16929 if (*input_line_pointer == '$')
16931 mips_cpreturn_register = tc_get_register (0);
16932 mips_cpreturn_offset = -1;
16936 mips_cpreturn_offset = get_absolute_expression ();
16937 mips_cpreturn_register = -1;
16939 SKIP_WHITESPACE ();
16940 if (*input_line_pointer != ',')
16942 as_bad (_("missing argument separator ',' for .cpsetup"));
16946 ++input_line_pointer;
16947 SKIP_WHITESPACE ();
16948 expression (&ex_sym);
16950 mips_mark_labels ();
16951 mips_assembling_insn = TRUE;
16954 if (mips_cpreturn_register == -1)
16956 ex_off.X_op = O_constant;
16957 ex_off.X_add_symbol = NULL;
16958 ex_off.X_op_symbol = NULL;
16959 ex_off.X_add_number = mips_cpreturn_offset;
16961 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16962 BFD_RELOC_LO16, SP);
16965 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16966 mips_gp_register, 0);
16968 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16970 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16971 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16974 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16975 mips_gp_register, -1, BFD_RELOC_GPREL16,
16976 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16979 mips_gp_register, reg1);
16985 ex.X_op = O_symbol;
16986 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16987 ex.X_op_symbol = NULL;
16988 ex.X_add_number = 0;
16990 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16991 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16993 macro_build_lui (&ex, mips_gp_register);
16994 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16995 mips_gp_register, BFD_RELOC_LO16);
17000 mips_assembling_insn = FALSE;
17001 demand_empty_rest_of_line ();
17005 s_cplocal (int ignore ATTRIBUTE_UNUSED)
17007 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17008 .cplocal is ignored. */
17009 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17015 if (mips_opts.mips16)
17017 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17018 ignore_rest_of_line ();
17022 mips_gp_register = tc_get_register (0);
17023 demand_empty_rest_of_line ();
17026 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17027 offset from $sp. The offset is remembered, and after making a PIC
17028 call $gp is restored from that location. */
17031 s_cprestore (int ignore ATTRIBUTE_UNUSED)
17035 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17036 .cprestore is ignored. */
17037 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
17043 if (mips_opts.mips16)
17045 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17046 ignore_rest_of_line ();
17050 mips_cprestore_offset = get_absolute_expression ();
17051 mips_cprestore_valid = 1;
17053 ex.X_op = O_constant;
17054 ex.X_add_symbol = NULL;
17055 ex.X_op_symbol = NULL;
17056 ex.X_add_number = mips_cprestore_offset;
17058 mips_mark_labels ();
17059 mips_assembling_insn = TRUE;
17062 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
17063 SP, HAVE_64BIT_ADDRESSES);
17066 mips_assembling_insn = FALSE;
17067 demand_empty_rest_of_line ();
17070 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17071 was given in the preceding .cpsetup, it results in:
17072 ld $gp, offset($sp)
17074 If a register $reg2 was given there, it results in:
17075 daddu $gp, $reg2, $0 */
17078 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
17082 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17083 We also need NewABI support. */
17084 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17090 if (mips_opts.mips16)
17092 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17093 ignore_rest_of_line ();
17097 mips_mark_labels ();
17098 mips_assembling_insn = TRUE;
17101 if (mips_cpreturn_register == -1)
17103 ex.X_op = O_constant;
17104 ex.X_add_symbol = NULL;
17105 ex.X_op_symbol = NULL;
17106 ex.X_add_number = mips_cpreturn_offset;
17108 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
17111 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17112 mips_cpreturn_register, 0);
17115 mips_assembling_insn = FALSE;
17116 demand_empty_rest_of_line ();
17119 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17120 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17121 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17122 debug information or MIPS16 TLS. */
17125 s_tls_rel_directive (const size_t bytes, const char *dirstr,
17126 bfd_reloc_code_real_type rtype)
17133 if (ex.X_op != O_symbol)
17135 as_bad (_("Unsupported use of %s"), dirstr);
17136 ignore_rest_of_line ();
17139 p = frag_more (bytes);
17140 md_number_to_chars (p, 0, bytes);
17141 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
17142 demand_empty_rest_of_line ();
17143 mips_clear_insn_labels ();
17146 /* Handle .dtprelword. */
17149 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
17151 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
17154 /* Handle .dtpreldword. */
17157 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
17159 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
17162 /* Handle .tprelword. */
17165 s_tprelword (int ignore ATTRIBUTE_UNUSED)
17167 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
17170 /* Handle .tpreldword. */
17173 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17175 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17178 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17179 code. It sets the offset to use in gp_rel relocations. */
17182 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17184 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17185 We also need NewABI support. */
17186 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17192 mips_gprel_offset = get_absolute_expression ();
17194 demand_empty_rest_of_line ();
17197 /* Handle the .gpword pseudo-op. This is used when generating PIC
17198 code. It generates a 32 bit GP relative reloc. */
17201 s_gpword (int ignore ATTRIBUTE_UNUSED)
17203 segment_info_type *si;
17204 struct insn_label_list *l;
17208 /* When not generating PIC code, this is treated as .word. */
17209 if (mips_pic != SVR4_PIC)
17215 si = seg_info (now_seg);
17216 l = si->label_list;
17217 mips_emit_delays ();
17219 mips_align (2, 0, l);
17222 mips_clear_insn_labels ();
17224 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17226 as_bad (_("Unsupported use of .gpword"));
17227 ignore_rest_of_line ();
17231 md_number_to_chars (p, 0, 4);
17232 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17233 BFD_RELOC_GPREL32);
17235 demand_empty_rest_of_line ();
17239 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17241 segment_info_type *si;
17242 struct insn_label_list *l;
17246 /* When not generating PIC code, this is treated as .dword. */
17247 if (mips_pic != SVR4_PIC)
17253 si = seg_info (now_seg);
17254 l = si->label_list;
17255 mips_emit_delays ();
17257 mips_align (3, 0, l);
17260 mips_clear_insn_labels ();
17262 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17264 as_bad (_("Unsupported use of .gpdword"));
17265 ignore_rest_of_line ();
17269 md_number_to_chars (p, 0, 8);
17270 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17271 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17273 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17274 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17275 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17277 demand_empty_rest_of_line ();
17280 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17281 tables. It generates a R_MIPS_EH reloc. */
17284 s_ehword (int ignore ATTRIBUTE_UNUSED)
17289 mips_emit_delays ();
17292 mips_clear_insn_labels ();
17294 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17296 as_bad (_("Unsupported use of .ehword"));
17297 ignore_rest_of_line ();
17301 md_number_to_chars (p, 0, 4);
17302 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17303 BFD_RELOC_MIPS_EH);
17305 demand_empty_rest_of_line ();
17308 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17309 tables in SVR4 PIC code. */
17312 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17316 /* This is ignored when not generating SVR4 PIC code. */
17317 if (mips_pic != SVR4_PIC)
17323 mips_mark_labels ();
17324 mips_assembling_insn = TRUE;
17326 /* Add $gp to the register named as an argument. */
17328 reg = tc_get_register (0);
17329 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17332 mips_assembling_insn = FALSE;
17333 demand_empty_rest_of_line ();
17336 /* Handle the .insn pseudo-op. This marks instruction labels in
17337 mips16/micromips mode. This permits the linker to handle them specially,
17338 such as generating jalx instructions when needed. We also make
17339 them odd for the duration of the assembly, in order to generate the
17340 right sort of code. We will make them even in the adjust_symtab
17341 routine, while leaving them marked. This is convenient for the
17342 debugger and the disassembler. The linker knows to make them odd
17346 s_insn (int ignore ATTRIBUTE_UNUSED)
17348 mips_mark_labels ();
17350 demand_empty_rest_of_line ();
17353 /* Handle a .stab[snd] directive. Ideally these directives would be
17354 implemented in a transparent way, so that removing them would not
17355 have any effect on the generated instructions. However, s_stab
17356 internally changes the section, so in practice we need to decide
17357 now whether the preceding label marks compressed code. We do not
17358 support changing the compression mode of a label after a .stab*
17359 directive, such as in:
17365 so the current mode wins. */
17368 s_mips_stab (int type)
17370 mips_mark_labels ();
17374 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17377 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17384 name = input_line_pointer;
17385 c = get_symbol_end ();
17386 symbolP = symbol_find_or_make (name);
17387 S_SET_WEAK (symbolP);
17388 *input_line_pointer = c;
17390 SKIP_WHITESPACE ();
17392 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17394 if (S_IS_DEFINED (symbolP))
17396 as_bad (_("ignoring attempt to redefine symbol %s"),
17397 S_GET_NAME (symbolP));
17398 ignore_rest_of_line ();
17402 if (*input_line_pointer == ',')
17404 ++input_line_pointer;
17405 SKIP_WHITESPACE ();
17409 if (exp.X_op != O_symbol)
17411 as_bad (_("bad .weakext directive"));
17412 ignore_rest_of_line ();
17415 symbol_set_value_expression (symbolP, &exp);
17418 demand_empty_rest_of_line ();
17421 /* Parse a register string into a number. Called from the ECOFF code
17422 to parse .frame. The argument is non-zero if this is the frame
17423 register, so that we can record it in mips_frame_reg. */
17426 tc_get_register (int frame)
17430 SKIP_WHITESPACE ();
17431 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17435 mips_frame_reg = reg != 0 ? reg : SP;
17436 mips_frame_reg_valid = 1;
17437 mips_cprestore_valid = 0;
17443 md_section_align (asection *seg, valueT addr)
17445 int align = bfd_get_section_alignment (stdoutput, seg);
17449 /* We don't need to align ELF sections to the full alignment.
17450 However, Irix 5 may prefer that we align them at least to a 16
17451 byte boundary. We don't bother to align the sections if we
17452 are targeted for an embedded system. */
17453 if (strncmp (TARGET_OS, "elf", 3) == 0)
17459 return ((addr + (1 << align) - 1) & (-1 << align));
17462 /* Utility routine, called from above as well. If called while the
17463 input file is still being read, it's only an approximation. (For
17464 example, a symbol may later become defined which appeared to be
17465 undefined earlier.) */
17468 nopic_need_relax (symbolS *sym, int before_relaxing)
17473 if (g_switch_value > 0)
17475 const char *symname;
17478 /* Find out whether this symbol can be referenced off the $gp
17479 register. It can be if it is smaller than the -G size or if
17480 it is in the .sdata or .sbss section. Certain symbols can
17481 not be referenced off the $gp, although it appears as though
17483 symname = S_GET_NAME (sym);
17484 if (symname != (const char *) NULL
17485 && (strcmp (symname, "eprol") == 0
17486 || strcmp (symname, "etext") == 0
17487 || strcmp (symname, "_gp") == 0
17488 || strcmp (symname, "edata") == 0
17489 || strcmp (symname, "_fbss") == 0
17490 || strcmp (symname, "_fdata") == 0
17491 || strcmp (symname, "_ftext") == 0
17492 || strcmp (symname, "end") == 0
17493 || strcmp (symname, "_gp_disp") == 0))
17495 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17497 #ifndef NO_ECOFF_DEBUGGING
17498 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17499 && (symbol_get_obj (sym)->ecoff_extern_size
17500 <= g_switch_value))
17502 /* We must defer this decision until after the whole
17503 file has been read, since there might be a .extern
17504 after the first use of this symbol. */
17505 || (before_relaxing
17506 #ifndef NO_ECOFF_DEBUGGING
17507 && symbol_get_obj (sym)->ecoff_extern_size == 0
17509 && S_GET_VALUE (sym) == 0)
17510 || (S_GET_VALUE (sym) != 0
17511 && S_GET_VALUE (sym) <= g_switch_value)))
17515 const char *segname;
17517 segname = segment_name (S_GET_SEGMENT (sym));
17518 gas_assert (strcmp (segname, ".lit8") != 0
17519 && strcmp (segname, ".lit4") != 0);
17520 change = (strcmp (segname, ".sdata") != 0
17521 && strcmp (segname, ".sbss") != 0
17522 && strncmp (segname, ".sdata.", 7) != 0
17523 && strncmp (segname, ".sbss.", 6) != 0
17524 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17525 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17530 /* We are not optimizing for the $gp register. */
17535 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17538 pic_need_relax (symbolS *sym, asection *segtype)
17542 /* Handle the case of a symbol equated to another symbol. */
17543 while (symbol_equated_reloc_p (sym))
17547 /* It's possible to get a loop here in a badly written program. */
17548 n = symbol_get_value_expression (sym)->X_add_symbol;
17554 if (symbol_section_p (sym))
17557 symsec = S_GET_SEGMENT (sym);
17559 /* This must duplicate the test in adjust_reloc_syms. */
17560 return (!bfd_is_und_section (symsec)
17561 && !bfd_is_abs_section (symsec)
17562 && !bfd_is_com_section (symsec)
17563 && !s_is_linkonce (sym, segtype)
17565 /* A global or weak symbol is treated as external. */
17566 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17572 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17573 extended opcode. SEC is the section the frag is in. */
17576 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17579 const struct mips16_immed_operand *op;
17581 int mintiny, maxtiny;
17585 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17587 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17590 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17591 op = mips16_immed_operands;
17592 while (op->type != type)
17595 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17600 if (type == '<' || type == '>' || type == '[' || type == ']')
17603 maxtiny = 1 << op->nbits;
17608 maxtiny = (1 << op->nbits) - 1;
17613 mintiny = - (1 << (op->nbits - 1));
17614 maxtiny = (1 << (op->nbits - 1)) - 1;
17617 sym_frag = symbol_get_frag (fragp->fr_symbol);
17618 val = S_GET_VALUE (fragp->fr_symbol);
17619 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17625 /* We won't have the section when we are called from
17626 mips_relax_frag. However, we will always have been called
17627 from md_estimate_size_before_relax first. If this is a
17628 branch to a different section, we mark it as such. If SEC is
17629 NULL, and the frag is not marked, then it must be a branch to
17630 the same section. */
17633 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17638 /* Must have been called from md_estimate_size_before_relax. */
17641 fragp->fr_subtype =
17642 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17644 /* FIXME: We should support this, and let the linker
17645 catch branches and loads that are out of range. */
17646 as_bad_where (fragp->fr_file, fragp->fr_line,
17647 _("unsupported PC relative reference to different section"));
17651 if (fragp != sym_frag && sym_frag->fr_address == 0)
17652 /* Assume non-extended on the first relaxation pass.
17653 The address we have calculated will be bogus if this is
17654 a forward branch to another frag, as the forward frag
17655 will have fr_address == 0. */
17659 /* In this case, we know for sure that the symbol fragment is in
17660 the same section. If the relax_marker of the symbol fragment
17661 differs from the relax_marker of this fragment, we have not
17662 yet adjusted the symbol fragment fr_address. We want to add
17663 in STRETCH in order to get a better estimate of the address.
17664 This particularly matters because of the shift bits. */
17666 && sym_frag->relax_marker != fragp->relax_marker)
17670 /* Adjust stretch for any alignment frag. Note that if have
17671 been expanding the earlier code, the symbol may be
17672 defined in what appears to be an earlier frag. FIXME:
17673 This doesn't handle the fr_subtype field, which specifies
17674 a maximum number of bytes to skip when doing an
17676 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17678 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17681 stretch = - ((- stretch)
17682 & ~ ((1 << (int) f->fr_offset) - 1));
17684 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17693 addr = fragp->fr_address + fragp->fr_fix;
17695 /* The base address rules are complicated. The base address of
17696 a branch is the following instruction. The base address of a
17697 PC relative load or add is the instruction itself, but if it
17698 is in a delay slot (in which case it can not be extended) use
17699 the address of the instruction whose delay slot it is in. */
17700 if (type == 'p' || type == 'q')
17704 /* If we are currently assuming that this frag should be
17705 extended, then, the current address is two bytes
17707 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17710 /* Ignore the low bit in the target, since it will be set
17711 for a text label. */
17712 if ((val & 1) != 0)
17715 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17717 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17720 val -= addr & ~ ((1 << op->shift) - 1);
17722 /* Branch offsets have an implicit 0 in the lowest bit. */
17723 if (type == 'p' || type == 'q')
17726 /* If any of the shifted bits are set, we must use an extended
17727 opcode. If the address depends on the size of this
17728 instruction, this can lead to a loop, so we arrange to always
17729 use an extended opcode. We only check this when we are in
17730 the main relaxation loop, when SEC is NULL. */
17731 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17733 fragp->fr_subtype =
17734 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17738 /* If we are about to mark a frag as extended because the value
17739 is precisely maxtiny + 1, then there is a chance of an
17740 infinite loop as in the following code:
17745 In this case when the la is extended, foo is 0x3fc bytes
17746 away, so the la can be shrunk, but then foo is 0x400 away, so
17747 the la must be extended. To avoid this loop, we mark the
17748 frag as extended if it was small, and is about to become
17749 extended with a value of maxtiny + 1. */
17750 if (val == ((maxtiny + 1) << op->shift)
17751 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17754 fragp->fr_subtype =
17755 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17759 else if (symsec != absolute_section && sec != NULL)
17760 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17762 if ((val & ((1 << op->shift) - 1)) != 0
17763 || val < (mintiny << op->shift)
17764 || val > (maxtiny << op->shift))
17770 /* Compute the length of a branch sequence, and adjust the
17771 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17772 worst-case length is computed, with UPDATE being used to indicate
17773 whether an unconditional (-1), branch-likely (+1) or regular (0)
17774 branch is to be computed. */
17776 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17778 bfd_boolean toofar;
17782 && S_IS_DEFINED (fragp->fr_symbol)
17783 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17788 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17790 addr = fragp->fr_address + fragp->fr_fix + 4;
17794 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17797 /* If the symbol is not defined or it's in a different segment,
17798 assume the user knows what's going on and emit a short
17804 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17806 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17807 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17808 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17809 RELAX_BRANCH_LINK (fragp->fr_subtype),
17815 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17818 if (mips_pic != NO_PIC)
17820 /* Additional space for PIC loading of target address. */
17822 if (mips_opts.isa == ISA_MIPS1)
17823 /* Additional space for $at-stabilizing nop. */
17827 /* If branch is conditional. */
17828 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17835 /* Compute the length of a branch sequence, and adjust the
17836 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17837 worst-case length is computed, with UPDATE being used to indicate
17838 whether an unconditional (-1), or regular (0) branch is to be
17842 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17844 bfd_boolean toofar;
17848 && S_IS_DEFINED (fragp->fr_symbol)
17849 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17854 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17855 /* Ignore the low bit in the target, since it will be set
17856 for a text label. */
17857 if ((val & 1) != 0)
17860 addr = fragp->fr_address + fragp->fr_fix + 4;
17864 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17867 /* If the symbol is not defined or it's in a different segment,
17868 assume the user knows what's going on and emit a short
17874 if (fragp && update
17875 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17876 fragp->fr_subtype = (toofar
17877 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17878 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17883 bfd_boolean compact_known = fragp != NULL;
17884 bfd_boolean compact = FALSE;
17885 bfd_boolean uncond;
17888 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17890 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17892 uncond = update < 0;
17894 /* If label is out of range, we turn branch <br>:
17896 <br> label # 4 bytes
17902 nop # 2 bytes if compact && !PIC
17905 if (mips_pic == NO_PIC && (!compact_known || compact))
17908 /* If assembling PIC code, we further turn:
17914 lw/ld at, %got(label)(gp) # 4 bytes
17915 d/addiu at, %lo(label) # 4 bytes
17918 if (mips_pic != NO_PIC)
17921 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17923 <brneg> 0f # 4 bytes
17924 nop # 2 bytes if !compact
17927 length += (compact_known && compact) ? 4 : 6;
17933 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17934 bit accordingly. */
17937 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17939 bfd_boolean toofar;
17942 && S_IS_DEFINED (fragp->fr_symbol)
17943 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17949 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17950 /* Ignore the low bit in the target, since it will be set
17951 for a text label. */
17952 if ((val & 1) != 0)
17955 /* Assume this is a 2-byte branch. */
17956 addr = fragp->fr_address + fragp->fr_fix + 2;
17958 /* We try to avoid the infinite loop by not adding 2 more bytes for
17963 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17965 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17966 else if (type == 'E')
17967 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17972 /* If the symbol is not defined or it's in a different segment,
17973 we emit a normal 32-bit branch. */
17976 if (fragp && update
17977 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17979 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17980 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17988 /* Estimate the size of a frag before relaxing. Unless this is the
17989 mips16, we are not really relaxing here, and the final size is
17990 encoded in the subtype information. For the mips16, we have to
17991 decide whether we are using an extended opcode or not. */
17994 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17998 if (RELAX_BRANCH_P (fragp->fr_subtype))
18001 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
18003 return fragp->fr_var;
18006 if (RELAX_MIPS16_P (fragp->fr_subtype))
18007 /* We don't want to modify the EXTENDED bit here; it might get us
18008 into infinite loops. We change it only in mips_relax_frag(). */
18009 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
18011 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18015 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18016 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
18017 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18018 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
18019 fragp->fr_var = length;
18024 if (mips_pic == NO_PIC)
18025 change = nopic_need_relax (fragp->fr_symbol, 0);
18026 else if (mips_pic == SVR4_PIC)
18027 change = pic_need_relax (fragp->fr_symbol, segtype);
18028 else if (mips_pic == VXWORKS_PIC)
18029 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18036 fragp->fr_subtype |= RELAX_USE_SECOND;
18037 return -RELAX_FIRST (fragp->fr_subtype);
18040 return -RELAX_SECOND (fragp->fr_subtype);
18043 /* This is called to see whether a reloc against a defined symbol
18044 should be converted into a reloc against a section. */
18047 mips_fix_adjustable (fixS *fixp)
18049 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
18050 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18053 if (fixp->fx_addsy == NULL)
18056 /* If symbol SYM is in a mergeable section, relocations of the form
18057 SYM + 0 can usually be made section-relative. The mergeable data
18058 is then identified by the section offset rather than by the symbol.
18060 However, if we're generating REL LO16 relocations, the offset is split
18061 between the LO16 and parterning high part relocation. The linker will
18062 need to recalculate the complete offset in order to correctly identify
18065 The linker has traditionally not looked for the parterning high part
18066 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18067 placed anywhere. Rather than break backwards compatibility by changing
18068 this, it seems better not to force the issue, and instead keep the
18069 original symbol. This will work with either linker behavior. */
18070 if ((lo16_reloc_p (fixp->fx_r_type)
18071 || reloc_needs_lo_p (fixp->fx_r_type))
18072 && HAVE_IN_PLACE_ADDENDS
18073 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
18076 /* There is no place to store an in-place offset for JALR relocations.
18077 Likewise an in-range offset of limited PC-relative relocations may
18078 overflow the in-place relocatable field if recalculated against the
18079 start address of the symbol's containing section. */
18080 if (HAVE_IN_PLACE_ADDENDS
18081 && (limited_pcrel_reloc_p (fixp->fx_r_type)
18082 || jalr_reloc_p (fixp->fx_r_type)))
18086 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18087 to a floating-point stub. The same is true for non-R_MIPS16_26
18088 relocations against MIPS16 functions; in this case, the stub becomes
18089 the function's canonical address.
18091 Floating-point stubs are stored in unique .mips16.call.* or
18092 .mips16.fn.* sections. If a stub T for function F is in section S,
18093 the first relocation in section S must be against F; this is how the
18094 linker determines the target function. All relocations that might
18095 resolve to T must also be against F. We therefore have the following
18096 restrictions, which are given in an intentionally-redundant way:
18098 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18101 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18102 if that stub might be used.
18104 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18107 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18108 that stub might be used.
18110 There is a further restriction:
18112 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18113 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
18114 targets with in-place addends; the relocation field cannot
18115 encode the low bit.
18117 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18118 against a MIPS16 symbol. We deal with (5) by by not reducing any
18119 such relocations on REL targets.
18121 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18122 relocation against some symbol R, no relocation against R may be
18123 reduced. (Note that this deals with (2) as well as (1) because
18124 relocations against global symbols will never be reduced on ELF
18125 targets.) This approach is a little simpler than trying to detect
18126 stub sections, and gives the "all or nothing" per-symbol consistency
18127 that we have for MIPS16 symbols. */
18129 && fixp->fx_subsy == NULL
18130 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18131 || *symbol_get_tc (fixp->fx_addsy)
18132 || (HAVE_IN_PLACE_ADDENDS
18133 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18134 && jmp_reloc_p (fixp->fx_r_type))))
18141 /* Translate internal representation of relocation info to BFD target
18145 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18147 static arelent *retval[4];
18149 bfd_reloc_code_real_type code;
18151 memset (retval, 0, sizeof(retval));
18152 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
18153 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
18154 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18155 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18157 if (fixp->fx_pcrel)
18159 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18160 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18161 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18162 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18163 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18165 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18166 Relocations want only the symbol offset. */
18167 reloc->addend = fixp->fx_addnumber + reloc->address;
18170 /* A gruesome hack which is a result of the gruesome gas
18171 reloc handling. What's worse, for COFF (as opposed to
18172 ECOFF), we might need yet another copy of reloc->address.
18173 See bfd_install_relocation. */
18174 reloc->addend += reloc->address;
18178 reloc->addend = fixp->fx_addnumber;
18180 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18181 entry to be used in the relocation's section offset. */
18182 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18184 reloc->address = reloc->addend;
18188 code = fixp->fx_r_type;
18190 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18191 if (reloc->howto == NULL)
18193 as_bad_where (fixp->fx_file, fixp->fx_line,
18194 _("Can not represent %s relocation in this object file format"),
18195 bfd_get_reloc_code_name (code));
18202 /* Relax a machine dependent frag. This returns the amount by which
18203 the current size of the frag should change. */
18206 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18208 if (RELAX_BRANCH_P (fragp->fr_subtype))
18210 offsetT old_var = fragp->fr_var;
18212 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18214 return fragp->fr_var - old_var;
18217 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18219 offsetT old_var = fragp->fr_var;
18220 offsetT new_var = 4;
18222 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18223 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18224 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18225 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18226 fragp->fr_var = new_var;
18228 return new_var - old_var;
18231 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18234 if (mips16_extended_frag (fragp, NULL, stretch))
18236 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18238 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18243 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18245 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18252 /* Convert a machine dependent frag. */
18255 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18257 if (RELAX_BRANCH_P (fragp->fr_subtype))
18260 unsigned long insn;
18264 buf = fragp->fr_literal + fragp->fr_fix;
18265 insn = read_insn (buf);
18267 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18269 /* We generate a fixup instead of applying it right now
18270 because, if there are linker relaxations, we're going to
18271 need the relocations. */
18272 exp.X_op = O_symbol;
18273 exp.X_add_symbol = fragp->fr_symbol;
18274 exp.X_add_number = fragp->fr_offset;
18276 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18277 BFD_RELOC_16_PCREL_S2);
18278 fixp->fx_file = fragp->fr_file;
18279 fixp->fx_line = fragp->fr_line;
18281 buf = write_insn (buf, insn);
18287 as_warn_where (fragp->fr_file, fragp->fr_line,
18288 _("Relaxed out-of-range branch into a jump"));
18290 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18293 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18295 /* Reverse the branch. */
18296 switch ((insn >> 28) & 0xf)
18299 /* bc[0-3][tf]l? instructions can have the condition
18300 reversed by tweaking a single TF bit, and their
18301 opcodes all have 0x4???????. */
18302 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18303 insn ^= 0x00010000;
18307 /* bltz 0x04000000 bgez 0x04010000
18308 bltzal 0x04100000 bgezal 0x04110000 */
18309 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18310 insn ^= 0x00010000;
18314 /* beq 0x10000000 bne 0x14000000
18315 blez 0x18000000 bgtz 0x1c000000 */
18316 insn ^= 0x04000000;
18324 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18326 /* Clear the and-link bit. */
18327 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18329 /* bltzal 0x04100000 bgezal 0x04110000
18330 bltzall 0x04120000 bgezall 0x04130000 */
18331 insn &= ~0x00100000;
18334 /* Branch over the branch (if the branch was likely) or the
18335 full jump (not likely case). Compute the offset from the
18336 current instruction to branch to. */
18337 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18341 /* How many bytes in instructions we've already emitted? */
18342 i = buf - fragp->fr_literal - fragp->fr_fix;
18343 /* How many bytes in instructions from here to the end? */
18344 i = fragp->fr_var - i;
18346 /* Convert to instruction count. */
18348 /* Branch counts from the next instruction. */
18351 /* Branch over the jump. */
18352 buf = write_insn (buf, insn);
18355 buf = write_insn (buf, 0);
18357 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18359 /* beql $0, $0, 2f */
18361 /* Compute the PC offset from the current instruction to
18362 the end of the variable frag. */
18363 /* How many bytes in instructions we've already emitted? */
18364 i = buf - fragp->fr_literal - fragp->fr_fix;
18365 /* How many bytes in instructions from here to the end? */
18366 i = fragp->fr_var - i;
18367 /* Convert to instruction count. */
18369 /* Don't decrement i, because we want to branch over the
18373 buf = write_insn (buf, insn);
18374 buf = write_insn (buf, 0);
18378 if (mips_pic == NO_PIC)
18381 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18382 ? 0x0c000000 : 0x08000000);
18383 exp.X_op = O_symbol;
18384 exp.X_add_symbol = fragp->fr_symbol;
18385 exp.X_add_number = fragp->fr_offset;
18387 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18388 FALSE, BFD_RELOC_MIPS_JMP);
18389 fixp->fx_file = fragp->fr_file;
18390 fixp->fx_line = fragp->fr_line;
18392 buf = write_insn (buf, insn);
18396 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18398 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18399 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18400 insn |= at << OP_SH_RT;
18401 exp.X_op = O_symbol;
18402 exp.X_add_symbol = fragp->fr_symbol;
18403 exp.X_add_number = fragp->fr_offset;
18405 if (fragp->fr_offset)
18407 exp.X_add_symbol = make_expr_symbol (&exp);
18408 exp.X_add_number = 0;
18411 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18412 FALSE, BFD_RELOC_MIPS_GOT16);
18413 fixp->fx_file = fragp->fr_file;
18414 fixp->fx_line = fragp->fr_line;
18416 buf = write_insn (buf, insn);
18418 if (mips_opts.isa == ISA_MIPS1)
18420 buf = write_insn (buf, 0);
18422 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18423 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18424 insn |= at << OP_SH_RS | at << OP_SH_RT;
18426 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18427 FALSE, BFD_RELOC_LO16);
18428 fixp->fx_file = fragp->fr_file;
18429 fixp->fx_line = fragp->fr_line;
18431 buf = write_insn (buf, insn);
18434 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18438 insn |= at << OP_SH_RS;
18440 buf = write_insn (buf, insn);
18444 fragp->fr_fix += fragp->fr_var;
18445 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18449 /* Relax microMIPS branches. */
18450 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18452 char *buf = fragp->fr_literal + fragp->fr_fix;
18453 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18454 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18455 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18456 bfd_boolean short_ds;
18457 unsigned long insn;
18461 exp.X_op = O_symbol;
18462 exp.X_add_symbol = fragp->fr_symbol;
18463 exp.X_add_number = fragp->fr_offset;
18465 fragp->fr_fix += fragp->fr_var;
18467 /* Handle 16-bit branches that fit or are forced to fit. */
18468 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18470 /* We generate a fixup instead of applying it right now,
18471 because if there is linker relaxation, we're going to
18472 need the relocations. */
18474 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18475 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18476 else if (type == 'E')
18477 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18478 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18482 fixp->fx_file = fragp->fr_file;
18483 fixp->fx_line = fragp->fr_line;
18485 /* These relocations can have an addend that won't fit in
18487 fixp->fx_no_overflow = 1;
18492 /* Handle 32-bit branches that fit or are forced to fit. */
18493 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18494 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18496 /* We generate a fixup instead of applying it right now,
18497 because if there is linker relaxation, we're going to
18498 need the relocations. */
18499 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18500 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18501 fixp->fx_file = fragp->fr_file;
18502 fixp->fx_line = fragp->fr_line;
18508 /* Relax 16-bit branches to 32-bit branches. */
18511 insn = read_compressed_insn (buf, 2);
18513 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18514 insn = 0x94000000; /* beq */
18515 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18517 unsigned long regno;
18519 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18520 regno = micromips_to_32_reg_d_map [regno];
18521 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18522 insn |= regno << MICROMIPSOP_SH_RS;
18527 /* Nothing else to do, just write it out. */
18528 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18529 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18531 buf = write_compressed_insn (buf, insn, 4);
18532 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18537 insn = read_compressed_insn (buf, 4);
18539 /* Relax 32-bit branches to a sequence of instructions. */
18540 as_warn_where (fragp->fr_file, fragp->fr_line,
18541 _("Relaxed out-of-range branch into a jump"));
18543 /* Set the short-delay-slot bit. */
18544 short_ds = al && (insn & 0x02000000) != 0;
18546 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18550 /* Reverse the branch. */
18551 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18552 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18553 insn ^= 0x20000000;
18554 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18555 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18556 || (insn & 0xffe00000) == 0x40800000 /* blez */
18557 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18558 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18559 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18560 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18561 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18562 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18563 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18564 insn ^= 0x00400000;
18565 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18566 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18567 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18568 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18569 insn ^= 0x00200000;
18575 /* Clear the and-link and short-delay-slot bits. */
18576 gas_assert ((insn & 0xfda00000) == 0x40200000);
18578 /* bltzal 0x40200000 bgezal 0x40600000 */
18579 /* bltzals 0x42200000 bgezals 0x42600000 */
18580 insn &= ~0x02200000;
18583 /* Make a label at the end for use with the branch. */
18584 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18585 micromips_label_inc ();
18586 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18588 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18592 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18593 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18594 fixp->fx_file = fragp->fr_file;
18595 fixp->fx_line = fragp->fr_line;
18597 /* Branch over the jump. */
18598 buf = write_compressed_insn (buf, insn, 4);
18601 buf = write_compressed_insn (buf, 0x0c00, 2);
18604 if (mips_pic == NO_PIC)
18606 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18608 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18609 insn = al ? jal : 0xd4000000;
18611 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18612 BFD_RELOC_MICROMIPS_JMP);
18613 fixp->fx_file = fragp->fr_file;
18614 fixp->fx_line = fragp->fr_line;
18616 buf = write_compressed_insn (buf, insn, 4);
18619 buf = write_compressed_insn (buf, 0x0c00, 2);
18623 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18624 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18625 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18627 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18628 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18629 insn |= at << MICROMIPSOP_SH_RT;
18631 if (exp.X_add_number)
18633 exp.X_add_symbol = make_expr_symbol (&exp);
18634 exp.X_add_number = 0;
18637 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18638 BFD_RELOC_MICROMIPS_GOT16);
18639 fixp->fx_file = fragp->fr_file;
18640 fixp->fx_line = fragp->fr_line;
18642 buf = write_compressed_insn (buf, insn, 4);
18644 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18645 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18646 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18648 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18649 BFD_RELOC_MICROMIPS_LO16);
18650 fixp->fx_file = fragp->fr_file;
18651 fixp->fx_line = fragp->fr_line;
18653 buf = write_compressed_insn (buf, insn, 4);
18655 /* jr/jrc/jalr/jalrs $at */
18656 insn = al ? jalr : jr;
18657 insn |= at << MICROMIPSOP_SH_MJ;
18659 buf = write_compressed_insn (buf, insn, 2);
18662 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18666 if (RELAX_MIPS16_P (fragp->fr_subtype))
18669 const struct mips16_immed_operand *op;
18672 unsigned int user_length, length;
18673 unsigned long insn;
18676 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18677 op = mips16_immed_operands;
18678 while (op->type != type)
18681 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18682 val = resolve_symbol_value (fragp->fr_symbol);
18687 addr = fragp->fr_address + fragp->fr_fix;
18689 /* The rules for the base address of a PC relative reloc are
18690 complicated; see mips16_extended_frag. */
18691 if (type == 'p' || type == 'q')
18696 /* Ignore the low bit in the target, since it will be
18697 set for a text label. */
18698 if ((val & 1) != 0)
18701 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18703 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18706 addr &= ~ (addressT) ((1 << op->shift) - 1);
18709 /* Make sure the section winds up with the alignment we have
18712 record_alignment (asec, op->shift);
18716 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18717 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18718 as_warn_where (fragp->fr_file, fragp->fr_line,
18719 _("extended instruction in delay slot"));
18721 buf = fragp->fr_literal + fragp->fr_fix;
18723 insn = read_compressed_insn (buf, 2);
18725 insn |= MIPS16_EXTEND;
18727 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18729 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18734 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18735 BFD_RELOC_UNUSED, val, user_length, &insn);
18737 length = (ext ? 4 : 2);
18738 gas_assert (mips16_opcode_length (insn) == length);
18739 write_compressed_insn (buf, insn, length);
18740 fragp->fr_fix += length;
18744 relax_substateT subtype = fragp->fr_subtype;
18745 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18746 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18750 first = RELAX_FIRST (subtype);
18751 second = RELAX_SECOND (subtype);
18752 fixp = (fixS *) fragp->fr_opcode;
18754 /* If the delay slot chosen does not match the size of the instruction,
18755 then emit a warning. */
18756 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18757 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18762 s = subtype & (RELAX_DELAY_SLOT_16BIT
18763 | RELAX_DELAY_SLOT_SIZE_FIRST
18764 | RELAX_DELAY_SLOT_SIZE_SECOND);
18765 msg = macro_warning (s);
18767 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18771 /* Possibly emit a warning if we've chosen the longer option. */
18772 if (use_second == second_longer)
18778 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18779 msg = macro_warning (s);
18781 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18785 /* Go through all the fixups for the first sequence. Disable them
18786 (by marking them as done) if we're going to use the second
18787 sequence instead. */
18789 && fixp->fx_frag == fragp
18790 && fixp->fx_where < fragp->fr_fix - second)
18792 if (subtype & RELAX_USE_SECOND)
18794 fixp = fixp->fx_next;
18797 /* Go through the fixups for the second sequence. Disable them if
18798 we're going to use the first sequence, otherwise adjust their
18799 addresses to account for the relaxation. */
18800 while (fixp && fixp->fx_frag == fragp)
18802 if (subtype & RELAX_USE_SECOND)
18803 fixp->fx_where -= first;
18806 fixp = fixp->fx_next;
18809 /* Now modify the frag contents. */
18810 if (subtype & RELAX_USE_SECOND)
18814 start = fragp->fr_literal + fragp->fr_fix - first - second;
18815 memmove (start, start + first, second);
18816 fragp->fr_fix -= first;
18819 fragp->fr_fix -= second;
18825 /* This function is called after the relocs have been generated.
18826 We've been storing mips16 text labels as odd. Here we convert them
18827 back to even for the convenience of the debugger. */
18830 mips_frob_file_after_relocs (void)
18833 unsigned int count, i;
18838 syms = bfd_get_outsymbols (stdoutput);
18839 count = bfd_get_symcount (stdoutput);
18840 for (i = 0; i < count; i++, syms++)
18841 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18842 && ((*syms)->value & 1) != 0)
18844 (*syms)->value &= ~1;
18845 /* If the symbol has an odd size, it was probably computed
18846 incorrectly, so adjust that as well. */
18847 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18848 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18854 /* This function is called whenever a label is defined, including fake
18855 labels instantiated off the dot special symbol. It is used when
18856 handling branch delays; if a branch has a label, we assume we cannot
18857 move it. This also bumps the value of the symbol by 1 in compressed
18861 mips_record_label (symbolS *sym)
18863 segment_info_type *si = seg_info (now_seg);
18864 struct insn_label_list *l;
18866 if (free_insn_labels == NULL)
18867 l = (struct insn_label_list *) xmalloc (sizeof *l);
18870 l = free_insn_labels;
18871 free_insn_labels = l->next;
18875 l->next = si->label_list;
18876 si->label_list = l;
18879 /* This function is called as tc_frob_label() whenever a label is defined
18880 and adds a DWARF-2 record we only want for true labels. */
18883 mips_define_label (symbolS *sym)
18885 mips_record_label (sym);
18887 dwarf2_emit_label (sym);
18891 /* This function is called by tc_new_dot_label whenever a new dot symbol
18895 mips_add_dot_label (symbolS *sym)
18897 mips_record_label (sym);
18898 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18899 mips_compressed_mark_label (sym);
18902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18904 /* Some special processing for a MIPS ELF file. */
18907 mips_elf_final_processing (void)
18909 /* Write out the register information. */
18910 if (mips_abi != N64_ABI)
18914 s.ri_gprmask = mips_gprmask;
18915 s.ri_cprmask[0] = mips_cprmask[0];
18916 s.ri_cprmask[1] = mips_cprmask[1];
18917 s.ri_cprmask[2] = mips_cprmask[2];
18918 s.ri_cprmask[3] = mips_cprmask[3];
18919 /* The gp_value field is set by the MIPS ELF backend. */
18921 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18922 ((Elf32_External_RegInfo *)
18923 mips_regmask_frag));
18927 Elf64_Internal_RegInfo s;
18929 s.ri_gprmask = mips_gprmask;
18931 s.ri_cprmask[0] = mips_cprmask[0];
18932 s.ri_cprmask[1] = mips_cprmask[1];
18933 s.ri_cprmask[2] = mips_cprmask[2];
18934 s.ri_cprmask[3] = mips_cprmask[3];
18935 /* The gp_value field is set by the MIPS ELF backend. */
18937 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18938 ((Elf64_External_RegInfo *)
18939 mips_regmask_frag));
18942 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18943 sort of BFD interface for this. */
18944 if (mips_any_noreorder)
18945 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18946 if (mips_pic != NO_PIC)
18948 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18949 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18952 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18954 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18955 defined at present; this might need to change in future. */
18956 if (file_ase_mips16)
18957 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18958 if (file_ase_micromips)
18959 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18960 if (file_ase & ASE_MDMX)
18961 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18963 /* Set the MIPS ELF ABI flags. */
18964 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18965 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18966 else if (mips_abi == O64_ABI)
18967 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18968 else if (mips_abi == EABI_ABI)
18970 if (!file_mips_gp32)
18971 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18973 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18975 else if (mips_abi == N32_ABI)
18976 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18978 /* Nothing to do for N64_ABI. */
18980 if (mips_32bitmode)
18981 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18983 #if 0 /* XXX FIXME */
18984 /* 32 bit code with 64 bit FP registers. */
18985 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18986 elf_elfheader (stdoutput)->e_flags |= ???;
18990 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18992 typedef struct proc {
18994 symbolS *func_end_sym;
18995 unsigned long reg_mask;
18996 unsigned long reg_offset;
18997 unsigned long fpreg_mask;
18998 unsigned long fpreg_offset;
18999 unsigned long frame_offset;
19000 unsigned long frame_reg;
19001 unsigned long pc_reg;
19004 static procS cur_proc;
19005 static procS *cur_proc_ptr;
19006 static int numprocs;
19008 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19009 as "2", and a normal nop as "0". */
19011 #define NOP_OPCODE_MIPS 0
19012 #define NOP_OPCODE_MIPS16 1
19013 #define NOP_OPCODE_MICROMIPS 2
19016 mips_nop_opcode (void)
19018 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19019 return NOP_OPCODE_MICROMIPS;
19020 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19021 return NOP_OPCODE_MIPS16;
19023 return NOP_OPCODE_MIPS;
19026 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19027 32-bit microMIPS NOPs here (if applicable). */
19030 mips_handle_align (fragS *fragp)
19034 int bytes, size, excess;
19037 if (fragp->fr_type != rs_align_code)
19040 p = fragp->fr_literal + fragp->fr_fix;
19042 switch (nop_opcode)
19044 case NOP_OPCODE_MICROMIPS:
19045 opcode = micromips_nop32_insn.insn_opcode;
19048 case NOP_OPCODE_MIPS16:
19049 opcode = mips16_nop_insn.insn_opcode;
19052 case NOP_OPCODE_MIPS:
19054 opcode = nop_insn.insn_opcode;
19059 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19060 excess = bytes % size;
19062 /* Handle the leading part if we're not inserting a whole number of
19063 instructions, and make it the end of the fixed part of the frag.
19064 Try to fit in a short microMIPS NOP if applicable and possible,
19065 and use zeroes otherwise. */
19066 gas_assert (excess < 4);
19067 fragp->fr_fix += excess;
19072 /* Fall through. */
19074 if (nop_opcode == NOP_OPCODE_MICROMIPS)
19076 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19080 /* Fall through. */
19083 /* Fall through. */
19088 md_number_to_chars (p, opcode, size);
19089 fragp->fr_var = size;
19093 md_obj_begin (void)
19100 /* Check for premature end, nesting errors, etc. */
19102 as_warn (_("missing .end at end of assembly"));
19111 if (*input_line_pointer == '-')
19113 ++input_line_pointer;
19116 if (!ISDIGIT (*input_line_pointer))
19117 as_bad (_("expected simple number"));
19118 if (input_line_pointer[0] == '0')
19120 if (input_line_pointer[1] == 'x')
19122 input_line_pointer += 2;
19123 while (ISXDIGIT (*input_line_pointer))
19126 val |= hex_value (*input_line_pointer++);
19128 return negative ? -val : val;
19132 ++input_line_pointer;
19133 while (ISDIGIT (*input_line_pointer))
19136 val |= *input_line_pointer++ - '0';
19138 return negative ? -val : val;
19141 if (!ISDIGIT (*input_line_pointer))
19143 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19144 *input_line_pointer, *input_line_pointer);
19145 as_warn (_("invalid number"));
19148 while (ISDIGIT (*input_line_pointer))
19151 val += *input_line_pointer++ - '0';
19153 return negative ? -val : val;
19156 /* The .file directive; just like the usual .file directive, but there
19157 is an initial number which is the ECOFF file index. In the non-ECOFF
19158 case .file implies DWARF-2. */
19161 s_mips_file (int x ATTRIBUTE_UNUSED)
19163 static int first_file_directive = 0;
19165 if (ECOFF_DEBUGGING)
19174 filename = dwarf2_directive_file (0);
19176 /* Versions of GCC up to 3.1 start files with a ".file"
19177 directive even for stabs output. Make sure that this
19178 ".file" is handled. Note that you need a version of GCC
19179 after 3.1 in order to support DWARF-2 on MIPS. */
19180 if (filename != NULL && ! first_file_directive)
19182 (void) new_logical_line (filename, -1);
19183 s_app_file_string (filename, 0);
19185 first_file_directive = 1;
19189 /* The .loc directive, implying DWARF-2. */
19192 s_mips_loc (int x ATTRIBUTE_UNUSED)
19194 if (!ECOFF_DEBUGGING)
19195 dwarf2_directive_loc (0);
19198 /* The .end directive. */
19201 s_mips_end (int x ATTRIBUTE_UNUSED)
19205 /* Following functions need their own .frame and .cprestore directives. */
19206 mips_frame_reg_valid = 0;
19207 mips_cprestore_valid = 0;
19209 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19212 demand_empty_rest_of_line ();
19217 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19218 as_warn (_(".end not in text section"));
19222 as_warn (_(".end directive without a preceding .ent directive."));
19223 demand_empty_rest_of_line ();
19229 gas_assert (S_GET_NAME (p));
19230 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19231 as_warn (_(".end symbol does not match .ent symbol."));
19233 if (debug_type == DEBUG_STABS)
19234 stabs_generate_asm_endfunc (S_GET_NAME (p),
19238 as_warn (_(".end directive missing or unknown symbol"));
19241 /* Create an expression to calculate the size of the function. */
19242 if (p && cur_proc_ptr)
19244 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19245 expressionS *exp = xmalloc (sizeof (expressionS));
19248 exp->X_op = O_subtract;
19249 exp->X_add_symbol = symbol_temp_new_now ();
19250 exp->X_op_symbol = p;
19251 exp->X_add_number = 0;
19253 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19256 /* Generate a .pdr section. */
19257 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
19259 segT saved_seg = now_seg;
19260 subsegT saved_subseg = now_subseg;
19264 #ifdef md_flush_pending_output
19265 md_flush_pending_output ();
19268 gas_assert (pdr_seg);
19269 subseg_set (pdr_seg, 0);
19271 /* Write the symbol. */
19272 exp.X_op = O_symbol;
19273 exp.X_add_symbol = p;
19274 exp.X_add_number = 0;
19275 emit_expr (&exp, 4);
19277 fragp = frag_more (7 * 4);
19279 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19280 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19281 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19282 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19283 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19284 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19285 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19287 subseg_set (saved_seg, saved_subseg);
19289 #endif /* OBJ_ELF */
19291 cur_proc_ptr = NULL;
19294 /* The .aent and .ent directives. */
19297 s_mips_ent (int aent)
19301 symbolP = get_symbol ();
19302 if (*input_line_pointer == ',')
19303 ++input_line_pointer;
19304 SKIP_WHITESPACE ();
19305 if (ISDIGIT (*input_line_pointer)
19306 || *input_line_pointer == '-')
19309 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19310 as_warn (_(".ent or .aent not in text section."));
19312 if (!aent && cur_proc_ptr)
19313 as_warn (_("missing .end"));
19317 /* This function needs its own .frame and .cprestore directives. */
19318 mips_frame_reg_valid = 0;
19319 mips_cprestore_valid = 0;
19321 cur_proc_ptr = &cur_proc;
19322 memset (cur_proc_ptr, '\0', sizeof (procS));
19324 cur_proc_ptr->func_sym = symbolP;
19328 if (debug_type == DEBUG_STABS)
19329 stabs_generate_asm_func (S_GET_NAME (symbolP),
19330 S_GET_NAME (symbolP));
19333 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19335 demand_empty_rest_of_line ();
19338 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19339 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19340 s_mips_frame is used so that we can set the PDR information correctly.
19341 We can't use the ecoff routines because they make reference to the ecoff
19342 symbol table (in the mdebug section). */
19345 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19348 if (IS_ELF && !ECOFF_DEBUGGING)
19352 if (cur_proc_ptr == (procS *) NULL)
19354 as_warn (_(".frame outside of .ent"));
19355 demand_empty_rest_of_line ();
19359 cur_proc_ptr->frame_reg = tc_get_register (1);
19361 SKIP_WHITESPACE ();
19362 if (*input_line_pointer++ != ','
19363 || get_absolute_expression_and_terminator (&val) != ',')
19365 as_warn (_("Bad .frame directive"));
19366 --input_line_pointer;
19367 demand_empty_rest_of_line ();
19371 cur_proc_ptr->frame_offset = val;
19372 cur_proc_ptr->pc_reg = tc_get_register (0);
19374 demand_empty_rest_of_line ();
19377 #endif /* OBJ_ELF */
19381 /* The .fmask and .mask directives. If the mdebug section is present
19382 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19383 embedded targets, s_mips_mask is used so that we can set the PDR
19384 information correctly. We can't use the ecoff routines because they
19385 make reference to the ecoff symbol table (in the mdebug section). */
19388 s_mips_mask (int reg_type)
19391 if (IS_ELF && !ECOFF_DEBUGGING)
19395 if (cur_proc_ptr == (procS *) NULL)
19397 as_warn (_(".mask/.fmask outside of .ent"));
19398 demand_empty_rest_of_line ();
19402 if (get_absolute_expression_and_terminator (&mask) != ',')
19404 as_warn (_("Bad .mask/.fmask directive"));
19405 --input_line_pointer;
19406 demand_empty_rest_of_line ();
19410 off = get_absolute_expression ();
19412 if (reg_type == 'F')
19414 cur_proc_ptr->fpreg_mask = mask;
19415 cur_proc_ptr->fpreg_offset = off;
19419 cur_proc_ptr->reg_mask = mask;
19420 cur_proc_ptr->reg_offset = off;
19423 demand_empty_rest_of_line ();
19426 #endif /* OBJ_ELF */
19427 s_ignore (reg_type);
19430 /* A table describing all the processors gas knows about. Names are
19431 matched in the order listed.
19433 To ease comparison, please keep this table in the same order as
19434 gcc's mips_cpu_info_table[]. */
19435 static const struct mips_cpu_info mips_cpu_info_table[] =
19437 /* Entries for generic ISAs */
19438 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19439 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19440 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19441 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19442 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19443 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19444 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19445 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19446 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19449 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19450 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19451 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19454 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19457 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19458 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19459 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19460 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19461 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19462 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19463 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19464 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19465 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19466 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19467 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19468 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19469 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19470 /* ST Microelectronics Loongson 2E and 2F cores */
19471 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19472 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19475 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19476 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19477 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19478 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19479 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19480 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19481 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19482 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19483 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19484 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19485 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19486 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19487 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19488 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19489 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19492 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19493 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19494 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19495 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19497 /* MIPS 32 Release 2 */
19498 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19499 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19500 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19501 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19502 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19503 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19504 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19505 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19506 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19507 ISA_MIPS32R2, CPU_MIPS32R2 },
19508 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19509 ISA_MIPS32R2, CPU_MIPS32R2 },
19510 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19511 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19512 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19513 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19514 /* Deprecated forms of the above. */
19515 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19516 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19517 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19518 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19519 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19520 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19521 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19522 /* Deprecated forms of the above. */
19523 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19524 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19525 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19526 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19527 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19528 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19529 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19530 /* Deprecated forms of the above. */
19531 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19532 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19533 /* 34Kn is a 34kc without DSP. */
19534 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19535 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19536 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19537 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19538 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19539 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19540 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19541 /* Deprecated forms of the above. */
19542 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19543 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19544 /* 1004K cores are multiprocessor versions of the 34K. */
19545 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19546 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19547 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19548 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19551 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19552 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19553 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19554 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19556 /* Broadcom SB-1 CPU core */
19557 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19558 /* Broadcom SB-1A CPU core */
19559 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19561 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19563 /* MIPS 64 Release 2 */
19565 /* Cavium Networks Octeon CPU core */
19566 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19567 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19568 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19571 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19574 XLP is mostly like XLR, with the prominent exception that it is
19575 MIPS64R2 rather than MIPS64. */
19576 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19579 { NULL, 0, 0, 0, 0 }
19583 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19584 with a final "000" replaced by "k". Ignore case.
19586 Note: this function is shared between GCC and GAS. */
19589 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19591 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19592 given++, canonical++;
19594 return ((*given == 0 && *canonical == 0)
19595 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19599 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19600 CPU name. We've traditionally allowed a lot of variation here.
19602 Note: this function is shared between GCC and GAS. */
19605 mips_matching_cpu_name_p (const char *canonical, const char *given)
19607 /* First see if the name matches exactly, or with a final "000"
19608 turned into "k". */
19609 if (mips_strict_matching_cpu_name_p (canonical, given))
19612 /* If not, try comparing based on numerical designation alone.
19613 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19614 if (TOLOWER (*given) == 'r')
19616 if (!ISDIGIT (*given))
19619 /* Skip over some well-known prefixes in the canonical name,
19620 hoping to find a number there too. */
19621 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19623 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19625 else if (TOLOWER (canonical[0]) == 'r')
19628 return mips_strict_matching_cpu_name_p (canonical, given);
19632 /* Parse an option that takes the name of a processor as its argument.
19633 OPTION is the name of the option and CPU_STRING is the argument.
19634 Return the corresponding processor enumeration if the CPU_STRING is
19635 recognized, otherwise report an error and return null.
19637 A similar function exists in GCC. */
19639 static const struct mips_cpu_info *
19640 mips_parse_cpu (const char *option, const char *cpu_string)
19642 const struct mips_cpu_info *p;
19644 /* 'from-abi' selects the most compatible architecture for the given
19645 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19646 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19647 version. Look first at the -mgp options, if given, otherwise base
19648 the choice on MIPS_DEFAULT_64BIT.
19650 Treat NO_ABI like the EABIs. One reason to do this is that the
19651 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19652 architecture. This code picks MIPS I for 'mips' and MIPS III for
19653 'mips64', just as we did in the days before 'from-abi'. */
19654 if (strcasecmp (cpu_string, "from-abi") == 0)
19656 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19657 return mips_cpu_info_from_isa (ISA_MIPS1);
19659 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19660 return mips_cpu_info_from_isa (ISA_MIPS3);
19662 if (file_mips_gp32 >= 0)
19663 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19665 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19670 /* 'default' has traditionally been a no-op. Probably not very useful. */
19671 if (strcasecmp (cpu_string, "default") == 0)
19674 for (p = mips_cpu_info_table; p->name != 0; p++)
19675 if (mips_matching_cpu_name_p (p->name, cpu_string))
19678 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19682 /* Return the canonical processor information for ISA (a member of the
19683 ISA_MIPS* enumeration). */
19685 static const struct mips_cpu_info *
19686 mips_cpu_info_from_isa (int isa)
19690 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19691 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19692 && isa == mips_cpu_info_table[i].isa)
19693 return (&mips_cpu_info_table[i]);
19698 static const struct mips_cpu_info *
19699 mips_cpu_info_from_arch (int arch)
19703 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19704 if (arch == mips_cpu_info_table[i].cpu)
19705 return (&mips_cpu_info_table[i]);
19711 show (FILE *stream, const char *string, int *col_p, int *first_p)
19715 fprintf (stream, "%24s", "");
19720 fprintf (stream, ", ");
19724 if (*col_p + strlen (string) > 72)
19726 fprintf (stream, "\n%24s", "");
19730 fprintf (stream, "%s", string);
19731 *col_p += strlen (string);
19737 md_show_usage (FILE *stream)
19742 fprintf (stream, _("\
19744 -EB generate big endian output\n\
19745 -EL generate little endian output\n\
19746 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19747 -G NUM allow referencing objects up to NUM bytes\n\
19748 implicitly with the gp register [default 8]\n"));
19749 fprintf (stream, _("\
19750 -mips1 generate MIPS ISA I instructions\n\
19751 -mips2 generate MIPS ISA II instructions\n\
19752 -mips3 generate MIPS ISA III instructions\n\
19753 -mips4 generate MIPS ISA IV instructions\n\
19754 -mips5 generate MIPS ISA V instructions\n\
19755 -mips32 generate MIPS32 ISA instructions\n\
19756 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19757 -mips64 generate MIPS64 ISA instructions\n\
19758 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19759 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19763 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19764 show (stream, mips_cpu_info_table[i].name, &column, &first);
19765 show (stream, "from-abi", &column, &first);
19766 fputc ('\n', stream);
19768 fprintf (stream, _("\
19769 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19770 -no-mCPU don't generate code specific to CPU.\n\
19771 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19775 show (stream, "3900", &column, &first);
19776 show (stream, "4010", &column, &first);
19777 show (stream, "4100", &column, &first);
19778 show (stream, "4650", &column, &first);
19779 fputc ('\n', stream);
19781 fprintf (stream, _("\
19782 -mips16 generate mips16 instructions\n\
19783 -no-mips16 do not generate mips16 instructions\n"));
19784 fprintf (stream, _("\
19785 -mmicromips generate microMIPS instructions\n\
19786 -mno-micromips do not generate microMIPS instructions\n"));
19787 fprintf (stream, _("\
19788 -msmartmips generate smartmips instructions\n\
19789 -mno-smartmips do not generate smartmips instructions\n"));
19790 fprintf (stream, _("\
19791 -mdsp generate DSP instructions\n\
19792 -mno-dsp do not generate DSP instructions\n"));
19793 fprintf (stream, _("\
19794 -mdspr2 generate DSP R2 instructions\n\
19795 -mno-dspr2 do not generate DSP R2 instructions\n"));
19796 fprintf (stream, _("\
19797 -mmt generate MT instructions\n\
19798 -mno-mt do not generate MT instructions\n"));
19799 fprintf (stream, _("\
19800 -mmcu generate MCU instructions\n\
19801 -mno-mcu do not generate MCU instructions\n"));
19802 fprintf (stream, _("\
19803 -mvirt generate Virtualization instructions\n\
19804 -mno-virt do not generate Virtualization instructions\n"));
19805 fprintf (stream, _("\
19806 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19807 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19808 -mfix-vr4120 work around certain VR4120 errata\n\
19809 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19810 -mfix-24k insert a nop after ERET and DERET instructions\n\
19811 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19812 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19813 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19814 -msym32 assume all symbols have 32-bit values\n\
19815 -O0 remove unneeded NOPs, do not swap branches\n\
19816 -O remove unneeded NOPs and swap branches\n\
19817 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19818 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19819 fprintf (stream, _("\
19820 -mhard-float allow floating-point instructions\n\
19821 -msoft-float do not allow floating-point instructions\n\
19822 -msingle-float only allow 32-bit floating-point operations\n\
19823 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19824 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19825 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19828 fprintf (stream, _("\
19829 -KPIC, -call_shared generate SVR4 position independent code\n\
19830 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19831 -mvxworks-pic generate VxWorks position independent code\n\
19832 -non_shared do not generate code that can operate with DSOs\n\
19833 -xgot assume a 32 bit GOT\n\
19834 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19835 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19836 position dependent (non shared) code\n\
19837 -mabi=ABI create ABI conformant object file for:\n"));
19841 show (stream, "32", &column, &first);
19842 show (stream, "o64", &column, &first);
19843 show (stream, "n32", &column, &first);
19844 show (stream, "64", &column, &first);
19845 show (stream, "eabi", &column, &first);
19847 fputc ('\n', stream);
19849 fprintf (stream, _("\
19850 -32 create o32 ABI object file (default)\n\
19851 -n32 create n32 ABI object file\n\
19852 -64 create 64 ABI object file\n"));
19858 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19860 if (HAVE_64BIT_SYMBOLS)
19861 return dwarf2_format_64bit_irix;
19863 return dwarf2_format_32bit;
19868 mips_dwarf2_addr_size (void)
19870 if (HAVE_64BIT_OBJECTS)
19876 /* Standard calling conventions leave the CFA at SP on entry. */
19878 mips_cfi_frame_initial_instructions (void)
19880 cfi_add_CFA_def_cfa_register (SP);
19884 tc_mips_regname_to_dw2regnum (char *regname)
19886 unsigned int regnum = -1;
19889 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))