1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi = NO_ABI;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls = FALSE;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared = TRUE;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
192 /* True if ".set sym32" is in effect. */
196 /* True if -mgp32 was passed. */
197 static int file_mips_gp32 = -1;
199 /* True if -mfp32 was passed. */
200 static int file_mips_fp32 = -1;
202 /* This is the struct we use to hold the current set of options. Note
203 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
204 -1 to indicate that they have not been initialized. */
206 static struct mips_set_options mips_opts =
208 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
211 /* These variables are filled in with the masks of registers used.
212 The object format code reads them and puts them in the appropriate
214 unsigned long mips_gprmask;
215 unsigned long mips_cprmask[4];
217 /* MIPS ISA we are using for this output file. */
218 static int file_mips_isa = ISA_UNKNOWN;
220 /* True if -mips16 was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips16;
224 /* True if -mips3d was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mips3d;
228 /* True if -mdmx was passed or implied by arguments passed on the
229 command line (e.g., by -march). */
230 static int file_ase_mdmx;
232 /* The argument of the -march= flag. The architecture we are assembling. */
233 static int file_mips_arch = CPU_UNKNOWN;
234 static const char *mips_arch_string;
236 /* The argument of the -mtune= flag. The architecture for which we
238 static int mips_tune = CPU_UNKNOWN;
239 static const char *mips_tune_string;
241 /* True when generating 32-bit code for a 64-bit processor. */
242 static int mips_32bitmode = 0;
244 /* True if the given ABI requires 32-bit registers. */
245 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
247 /* Likewise 64-bit registers. */
248 #define ABI_NEEDS_64BIT_REGS(ABI) \
250 || (ABI) == N64_ABI \
253 /* Return true if ISA supports 64 bit gp register instructions. */
254 #define ISA_HAS_64BIT_REGS(ISA) ( \
256 || (ISA) == ISA_MIPS4 \
257 || (ISA) == ISA_MIPS5 \
258 || (ISA) == ISA_MIPS64 \
259 || (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 64-bit right rotate (dror et al.)
264 #define ISA_HAS_DROR(ISA) ( \
265 (ISA) == ISA_MIPS64R2 \
268 /* Return true if ISA supports 32-bit right rotate (ror et al.)
270 #define ISA_HAS_ROR(ISA) ( \
271 (ISA) == ISA_MIPS32R2 \
272 || (ISA) == ISA_MIPS64R2 \
275 #define HAVE_32BIT_GPRS \
276 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
278 #define HAVE_32BIT_FPRS \
279 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
282 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
284 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
286 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
288 /* True if relocations are stored in-place. */
289 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
291 /* The ABI-derived address size. */
292 #define HAVE_64BIT_ADDRESSES \
293 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
294 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
296 /* The size of symbolic constants (i.e., expressions of the form
297 "SYMBOL" or "SYMBOL + OFFSET"). */
298 #define HAVE_32BIT_SYMBOLS \
299 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
300 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
302 /* Addresses are loaded in different ways, depending on the address size
303 in use. The n32 ABI Documentation also mandates the use of additions
304 with overflow checking, but existing implementations don't follow it. */
305 #define ADDRESS_ADD_INSN \
306 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
308 #define ADDRESS_ADDI_INSN \
309 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
311 #define ADDRESS_LOAD_INSN \
312 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
314 #define ADDRESS_STORE_INSN \
315 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
317 /* Return true if the given CPU supports the MIPS16 ASE. */
318 #define CPU_HAS_MIPS16(cpu) \
319 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
320 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
322 /* Return true if the given CPU supports the MIPS3D ASE. */
323 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
326 /* Return true if the given CPU supports the MDMX ASE. */
327 #define CPU_HAS_MDMX(cpu) (FALSE \
330 /* True if CPU has a dror instruction. */
331 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
333 /* True if CPU has a ror instruction. */
334 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
336 /* True if mflo and mfhi can be immediately followed by instructions
337 which write to the HI and LO registers.
339 According to MIPS specifications, MIPS ISAs I, II, and III need
340 (at least) two instructions between the reads of HI/LO and
341 instructions which write them, and later ISAs do not. Contradicting
342 the MIPS specifications, some MIPS IV processor user manuals (e.g.
343 the UM for the NEC Vr5000) document needing the instructions between
344 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
345 MIPS64 and later ISAs to have the interlocks, plus any specific
346 earlier-ISA CPUs for which CPU documentation declares that the
347 instructions are really interlocked. */
348 #define hilo_interlocks \
349 (mips_opts.isa == ISA_MIPS32 \
350 || mips_opts.isa == ISA_MIPS32R2 \
351 || mips_opts.isa == ISA_MIPS64 \
352 || mips_opts.isa == ISA_MIPS64R2 \
353 || mips_opts.arch == CPU_R4010 \
354 || mips_opts.arch == CPU_R10000 \
355 || mips_opts.arch == CPU_R12000 \
356 || mips_opts.arch == CPU_RM7000 \
357 || mips_opts.arch == CPU_VR5500 \
360 /* Whether the processor uses hardware interlocks to protect reads
361 from the GPRs after they are loaded from memory, and thus does not
362 require nops to be inserted. This applies to instructions marked
363 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
365 #define gpr_interlocks \
366 (mips_opts.isa != ISA_MIPS1 \
367 || mips_opts.arch == CPU_R3900)
369 /* Whether the processor uses hardware interlocks to avoid delays
370 required by coprocessor instructions, and thus does not require
371 nops to be inserted. This applies to instructions marked
372 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
373 between instructions marked INSN_WRITE_COND_CODE and ones marked
374 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
375 levels I, II, and III. */
376 /* Itbl support may require additional care here. */
377 #define cop_interlocks \
378 ((mips_opts.isa != ISA_MIPS1 \
379 && mips_opts.isa != ISA_MIPS2 \
380 && mips_opts.isa != ISA_MIPS3) \
381 || mips_opts.arch == CPU_R4300 \
384 /* Whether the processor uses hardware interlocks to protect reads
385 from coprocessor registers after they are loaded from memory, and
386 thus does not require nops to be inserted. This applies to
387 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
388 requires at MIPS ISA level I. */
389 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
391 /* Is this a mfhi or mflo instruction? */
392 #define MF_HILO_INSN(PINFO) \
393 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
395 /* MIPS PIC level. */
397 enum mips_pic_level mips_pic;
399 /* 1 if we should generate 32 bit offsets from the $gp register in
400 SVR4_PIC mode. Currently has no meaning in other modes. */
401 static int mips_big_got = 0;
403 /* 1 if trap instructions should used for overflow rather than break
405 static int mips_trap = 0;
407 /* 1 if double width floating point constants should not be constructed
408 by assembling two single width halves into two single width floating
409 point registers which just happen to alias the double width destination
410 register. On some architectures this aliasing can be disabled by a bit
411 in the status register, and the setting of this bit cannot be determined
412 automatically at assemble time. */
413 static int mips_disable_float_construction;
415 /* Non-zero if any .set noreorder directives were used. */
417 static int mips_any_noreorder;
419 /* Non-zero if nops should be inserted when the register referenced in
420 an mfhi/mflo instruction is read in the next two instructions. */
421 static int mips_7000_hilo_fix;
423 /* The size of the small data section. */
424 static unsigned int g_switch_value = 8;
425 /* Whether the -G option was used. */
426 static int g_switch_seen = 0;
431 /* If we can determine in advance that GP optimization won't be
432 possible, we can skip the relaxation stuff that tries to produce
433 GP-relative references. This makes delay slot optimization work
436 This function can only provide a guess, but it seems to work for
437 gcc output. It needs to guess right for gcc, otherwise gcc
438 will put what it thinks is a GP-relative instruction in a branch
441 I don't know if a fix is needed for the SVR4_PIC mode. I've only
442 fixed it for the non-PIC mode. KR 95/04/07 */
443 static int nopic_need_relax (symbolS *, int);
445 /* handle of the OPCODE hash table */
446 static struct hash_control *op_hash = NULL;
448 /* The opcode hash table we use for the mips16. */
449 static struct hash_control *mips16_op_hash = NULL;
451 /* This array holds the chars that always start a comment. If the
452 pre-processor is disabled, these aren't very useful */
453 const char comment_chars[] = "#";
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output */
458 /* Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output. */
461 /* Also note that C style comments are always supported. */
462 const char line_comment_chars[] = "#";
464 /* This array holds machine specific line separator characters. */
465 const char line_separator_chars[] = ";";
467 /* Chars that can be used to separate mant from exp in floating point nums */
468 const char EXP_CHARS[] = "eE";
470 /* Chars that mean this number is a floating point constant */
473 const char FLT_CHARS[] = "rRsSfFdDxXpP";
475 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
476 changed in read.c . Ideally it shouldn't have to know about it at all,
477 but nothing is ideal around here.
480 static char *insn_error;
482 static int auto_align = 1;
484 /* When outputting SVR4 PIC code, the assembler needs to know the
485 offset in the stack frame from which to restore the $gp register.
486 This is set by the .cprestore pseudo-op, and saved in this
488 static offsetT mips_cprestore_offset = -1;
490 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
491 more optimizations, it can use a register value instead of a memory-saved
492 offset and even an other register than $gp as global pointer. */
493 static offsetT mips_cpreturn_offset = -1;
494 static int mips_cpreturn_register = -1;
495 static int mips_gp_register = GP;
496 static int mips_gprel_offset = 0;
498 /* Whether mips_cprestore_offset has been set in the current function
499 (or whether it has already been warned about, if not). */
500 static int mips_cprestore_valid = 0;
502 /* This is the register which holds the stack frame, as set by the
503 .frame pseudo-op. This is needed to implement .cprestore. */
504 static int mips_frame_reg = SP;
506 /* Whether mips_frame_reg has been set in the current function
507 (or whether it has already been warned about, if not). */
508 static int mips_frame_reg_valid = 0;
510 /* To output NOP instructions correctly, we need to keep information
511 about the previous two instructions. */
513 /* Whether we are optimizing. The default value of 2 means to remove
514 unneeded NOPs and swap branch instructions when possible. A value
515 of 1 means to not swap branches. A value of 0 means to always
517 static int mips_optimize = 2;
519 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
520 equivalent to seeing no -g option at all. */
521 static int mips_debug = 0;
523 /* The previous instruction. */
524 static struct mips_cl_insn prev_insn;
526 /* The instruction before prev_insn. */
527 static struct mips_cl_insn prev_prev_insn;
529 /* If we don't want information for prev_insn or prev_prev_insn, we
530 point the insn_mo field at this dummy integer. */
531 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 };
533 /* Non-zero if prev_insn is valid. */
534 static int prev_insn_valid;
536 /* The frag for the previous instruction. */
537 static struct frag *prev_insn_frag;
539 /* The offset into prev_insn_frag for the previous instruction. */
540 static long prev_insn_where;
542 /* The reloc type for the previous instruction, if any. */
543 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
545 /* The reloc for the previous instruction, if any. */
546 static fixS *prev_insn_fixp[3];
548 /* Non-zero if the previous instruction was in a delay slot. */
549 static int prev_insn_is_delay_slot;
551 /* Non-zero if the previous instruction was in a .set noreorder. */
552 static int prev_insn_unreordered;
554 /* Non-zero if the previous instruction uses an extend opcode (if
556 static int prev_insn_extended;
558 /* Non-zero if the previous previous instruction was in a .set
560 static int prev_prev_insn_unreordered;
562 /* If this is set, it points to a frag holding nop instructions which
563 were inserted before the start of a noreorder section. If those
564 nops turn out to be unnecessary, the size of the frag can be
566 static fragS *prev_nop_frag;
568 /* The number of nop instructions we created in prev_nop_frag. */
569 static int prev_nop_frag_holds;
571 /* The number of nop instructions that we know we need in
573 static int prev_nop_frag_required;
575 /* The number of instructions we've seen since prev_nop_frag. */
576 static int prev_nop_frag_since;
578 /* For ECOFF and ELF, relocations against symbols are done in two
579 parts, with a HI relocation and a LO relocation. Each relocation
580 has only 16 bits of space to store an addend. This means that in
581 order for the linker to handle carries correctly, it must be able
582 to locate both the HI and the LO relocation. This means that the
583 relocations must appear in order in the relocation table.
585 In order to implement this, we keep track of each unmatched HI
586 relocation. We then sort them so that they immediately precede the
587 corresponding LO relocation. */
592 struct mips_hi_fixup *next;
595 /* The section this fixup is in. */
599 /* The list of unmatched HI relocs. */
601 static struct mips_hi_fixup *mips_hi_fixup_list;
603 /* The frag containing the last explicit relocation operator.
604 Null if explicit relocations have not been used. */
606 static fragS *prev_reloc_op_frag;
608 /* Map normal MIPS register numbers to mips16 register numbers. */
610 #define X ILLEGAL_REG
611 static const int mips32_to_16_reg_map[] =
613 X, X, 2, 3, 4, 5, 6, 7,
614 X, X, X, X, X, X, X, X,
615 0, 1, X, X, X, X, X, X,
616 X, X, X, X, X, X, X, X
620 /* Map mips16 register numbers to normal MIPS register numbers. */
622 static const unsigned int mips16_to_32_reg_map[] =
624 16, 17, 2, 3, 4, 5, 6, 7
627 static int mips_fix_vr4120;
629 /* We don't relax branches by default, since this causes us to expand
630 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
631 fail to compute the offset before expanding the macro to the most
632 efficient expansion. */
634 static int mips_relax_branch;
636 /* The expansion of many macros depends on the type of symbol that
637 they refer to. For example, when generating position-dependent code,
638 a macro that refers to a symbol may have two different expansions,
639 one which uses GP-relative addresses and one which uses absolute
640 addresses. When generating SVR4-style PIC, a macro may have
641 different expansions for local and global symbols.
643 We handle these situations by generating both sequences and putting
644 them in variant frags. In position-dependent code, the first sequence
645 will be the GP-relative one and the second sequence will be the
646 absolute one. In SVR4 PIC, the first sequence will be for global
647 symbols and the second will be for local symbols.
649 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
650 SECOND are the lengths of the two sequences in bytes. These fields
651 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
652 the subtype has the following flags:
655 Set if it has been decided that we should use the second
656 sequence instead of the first.
659 Set in the first variant frag if the macro's second implementation
660 is longer than its first. This refers to the macro as a whole,
661 not an individual relaxation.
664 Set in the first variant frag if the macro appeared in a .set nomacro
665 block and if one alternative requires a warning but the other does not.
668 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
671 The frag's "opcode" points to the first fixup for relaxable code.
673 Relaxable macros are generated using a sequence such as:
675 relax_start (SYMBOL);
676 ... generate first expansion ...
678 ... generate second expansion ...
681 The code and fixups for the unwanted alternative are discarded
682 by md_convert_frag. */
683 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
685 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
686 #define RELAX_SECOND(X) ((X) & 0xff)
687 #define RELAX_USE_SECOND 0x10000
688 #define RELAX_SECOND_LONGER 0x20000
689 #define RELAX_NOMACRO 0x40000
690 #define RELAX_DELAY_SLOT 0x80000
692 /* Branch without likely bit. If label is out of range, we turn:
694 beq reg1, reg2, label
704 with the following opcode replacements:
711 bltzal <-> bgezal (with jal label instead of j label)
713 Even though keeping the delay slot instruction in the delay slot of
714 the branch would be more efficient, it would be very tricky to do
715 correctly, because we'd have to introduce a variable frag *after*
716 the delay slot instruction, and expand that instead. Let's do it
717 the easy way for now, even if the branch-not-taken case now costs
718 one additional instruction. Out-of-range branches are not supposed
719 to be common, anyway.
721 Branch likely. If label is out of range, we turn:
723 beql reg1, reg2, label
724 delay slot (annulled if branch not taken)
733 delay slot (executed only if branch taken)
736 It would be possible to generate a shorter sequence by losing the
737 likely bit, generating something like:
742 delay slot (executed only if branch taken)
754 bltzall -> bgezal (with jal label instead of j label)
755 bgezall -> bltzal (ditto)
758 but it's not clear that it would actually improve performance. */
759 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
762 | ((toofar) ? 1 : 0) \
764 | ((likely) ? 4 : 0) \
765 | ((uncond) ? 8 : 0)))
766 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
767 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
768 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
769 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
770 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
772 /* For mips16 code, we use an entirely different form of relaxation.
773 mips16 supports two versions of most instructions which take
774 immediate values: a small one which takes some small value, and a
775 larger one which takes a 16 bit value. Since branches also follow
776 this pattern, relaxing these values is required.
778 We can assemble both mips16 and normal MIPS code in a single
779 object. Therefore, we need to support this type of relaxation at
780 the same time that we support the relaxation described above. We
781 use the high bit of the subtype field to distinguish these cases.
783 The information we store for this type of relaxation is the
784 argument code found in the opcode file for this relocation, whether
785 the user explicitly requested a small or extended form, and whether
786 the relocation is in a jump or jal delay slot. That tells us the
787 size of the value, and how it should be stored. We also store
788 whether the fragment is considered to be extended or not. We also
789 store whether this is known to be a branch to a different section,
790 whether we have tried to relax this frag yet, and whether we have
791 ever extended a PC relative fragment because of a shift count. */
792 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
795 | ((small) ? 0x100 : 0) \
796 | ((ext) ? 0x200 : 0) \
797 | ((dslot) ? 0x400 : 0) \
798 | ((jal_dslot) ? 0x800 : 0))
799 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
800 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
801 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
802 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
803 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
804 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
805 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
806 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
807 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
808 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
809 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
810 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
812 /* Is the given value a sign-extended 32-bit value? */
813 #define IS_SEXT_32BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fffffff) == 0 \
815 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
817 /* Is the given value a sign-extended 16-bit value? */
818 #define IS_SEXT_16BIT_NUM(x) \
819 (((x) &~ (offsetT) 0x7fff) == 0 \
820 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
823 /* Global variables used when generating relaxable macros. See the
824 comment above RELAX_ENCODE for more details about how relaxation
827 /* 0 if we're not emitting a relaxable macro.
828 1 if we're emitting the first of the two relaxation alternatives.
829 2 if we're emitting the second alternative. */
832 /* The first relaxable fixup in the current frag. (In other words,
833 the first fixup that refers to relaxable code.) */
836 /* sizes[0] says how many bytes of the first alternative are stored in
837 the current frag. Likewise sizes[1] for the second alternative. */
838 unsigned int sizes[2];
840 /* The symbol on which the choice of sequence depends. */
844 /* Global variables used to decide whether a macro needs a warning. */
846 /* True if the macro is in a branch delay slot. */
847 bfd_boolean delay_slot_p;
849 /* For relaxable macros, sizes[0] is the length of the first alternative
850 in bytes and sizes[1] is the length of the second alternative.
851 For non-relaxable macros, both elements give the length of the
853 unsigned int sizes[2];
855 /* The first variant frag for this macro. */
857 } mips_macro_warning;
859 /* Prototypes for static functions. */
861 #define internalError() \
862 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
864 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
866 static void append_insn
867 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
868 static void mips_no_prev_insn (int);
869 static void mips16_macro_build
870 (expressionS *, const char *, const char *, va_list);
871 static void load_register (int, expressionS *, int);
872 static void macro_start (void);
873 static void macro_end (void);
874 static void macro (struct mips_cl_insn * ip);
875 static void mips16_macro (struct mips_cl_insn * ip);
876 #ifdef LOSING_COMPILER
877 static void macro2 (struct mips_cl_insn * ip);
879 static void mips_ip (char *str, struct mips_cl_insn * ip);
880 static void mips16_ip (char *str, struct mips_cl_insn * ip);
881 static void mips16_immed
882 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
883 unsigned long *, bfd_boolean *, unsigned short *);
884 static size_t my_getSmallExpression
885 (expressionS *, bfd_reloc_code_real_type *, char *);
886 static void my_getExpression (expressionS *, char *);
887 static void s_align (int);
888 static void s_change_sec (int);
889 static void s_change_section (int);
890 static void s_cons (int);
891 static void s_float_cons (int);
892 static void s_mips_globl (int);
893 static void s_option (int);
894 static void s_mipsset (int);
895 static void s_abicalls (int);
896 static void s_cpload (int);
897 static void s_cpsetup (int);
898 static void s_cplocal (int);
899 static void s_cprestore (int);
900 static void s_cpreturn (int);
901 static void s_gpvalue (int);
902 static void s_gpword (int);
903 static void s_gpdword (int);
904 static void s_cpadd (int);
905 static void s_insn (int);
906 static void md_obj_begin (void);
907 static void md_obj_end (void);
908 static void s_mips_ent (int);
909 static void s_mips_end (int);
910 static void s_mips_frame (int);
911 static void s_mips_mask (int reg_type);
912 static void s_mips_stab (int);
913 static void s_mips_weakext (int);
914 static void s_mips_file (int);
915 static void s_mips_loc (int);
916 static bfd_boolean pic_need_relax (symbolS *, asection *);
917 static int relaxed_branch_length (fragS *, asection *, int);
918 static int validate_mips_insn (const struct mips_opcode *);
920 /* Table and functions used to map between CPU/ISA names, and
921 ISA levels, and CPU numbers. */
925 const char *name; /* CPU or ISA name. */
926 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
927 int isa; /* ISA level. */
928 int cpu; /* CPU number (default CPU if ISA). */
931 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
932 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
933 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
937 The following pseudo-ops from the Kane and Heinrich MIPS book
938 should be defined here, but are currently unsupported: .alias,
939 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
941 The following pseudo-ops from the Kane and Heinrich MIPS book are
942 specific to the type of debugging information being generated, and
943 should be defined by the object format: .aent, .begin, .bend,
944 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
947 The following pseudo-ops from the Kane and Heinrich MIPS book are
948 not MIPS CPU specific, but are also not specific to the object file
949 format. This file is probably the best place to define them, but
950 they are not currently supported: .asm0, .endr, .lab, .repeat,
953 static const pseudo_typeS mips_pseudo_table[] =
955 /* MIPS specific pseudo-ops. */
956 {"option", s_option, 0},
957 {"set", s_mipsset, 0},
958 {"rdata", s_change_sec, 'r'},
959 {"sdata", s_change_sec, 's'},
960 {"livereg", s_ignore, 0},
961 {"abicalls", s_abicalls, 0},
962 {"cpload", s_cpload, 0},
963 {"cpsetup", s_cpsetup, 0},
964 {"cplocal", s_cplocal, 0},
965 {"cprestore", s_cprestore, 0},
966 {"cpreturn", s_cpreturn, 0},
967 {"gpvalue", s_gpvalue, 0},
968 {"gpword", s_gpword, 0},
969 {"gpdword", s_gpdword, 0},
970 {"cpadd", s_cpadd, 0},
973 /* Relatively generic pseudo-ops that happen to be used on MIPS
975 {"asciiz", stringer, 1},
976 {"bss", s_change_sec, 'b'},
979 {"dword", s_cons, 3},
980 {"weakext", s_mips_weakext, 0},
982 /* These pseudo-ops are defined in read.c, but must be overridden
983 here for one reason or another. */
984 {"align", s_align, 0},
986 {"data", s_change_sec, 'd'},
987 {"double", s_float_cons, 'd'},
988 {"float", s_float_cons, 'f'},
989 {"globl", s_mips_globl, 0},
990 {"global", s_mips_globl, 0},
991 {"hword", s_cons, 1},
996 {"section", s_change_section, 0},
997 {"short", s_cons, 1},
998 {"single", s_float_cons, 'f'},
999 {"stabn", s_mips_stab, 'n'},
1000 {"text", s_change_sec, 't'},
1001 {"word", s_cons, 2},
1003 { "extern", ecoff_directive_extern, 0},
1008 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1010 /* These pseudo-ops should be defined by the object file format.
1011 However, a.out doesn't support them, so we have versions here. */
1012 {"aent", s_mips_ent, 1},
1013 {"bgnb", s_ignore, 0},
1014 {"end", s_mips_end, 0},
1015 {"endb", s_ignore, 0},
1016 {"ent", s_mips_ent, 0},
1017 {"file", s_mips_file, 0},
1018 {"fmask", s_mips_mask, 'F'},
1019 {"frame", s_mips_frame, 0},
1020 {"loc", s_mips_loc, 0},
1021 {"mask", s_mips_mask, 'R'},
1022 {"verstamp", s_ignore, 0},
1026 extern void pop_insert (const pseudo_typeS *);
1029 mips_pop_insert (void)
1031 pop_insert (mips_pseudo_table);
1032 if (! ECOFF_DEBUGGING)
1033 pop_insert (mips_nonecoff_pseudo_table);
1036 /* Symbols labelling the current insn. */
1038 struct insn_label_list
1040 struct insn_label_list *next;
1044 static struct insn_label_list *insn_labels;
1045 static struct insn_label_list *free_insn_labels;
1047 static void mips_clear_insn_labels (void);
1050 mips_clear_insn_labels (void)
1052 register struct insn_label_list **pl;
1054 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1060 static char *expr_end;
1062 /* Expressions which appear in instructions. These are set by
1065 static expressionS imm_expr;
1066 static expressionS imm2_expr;
1067 static expressionS offset_expr;
1069 /* Relocs associated with imm_expr and offset_expr. */
1071 static bfd_reloc_code_real_type imm_reloc[3]
1072 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1073 static bfd_reloc_code_real_type offset_reloc[3]
1074 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1076 /* These are set by mips16_ip if an explicit extension is used. */
1078 static bfd_boolean mips16_small, mips16_ext;
1081 /* The pdr segment for per procedure frame/regmask info. Not used for
1084 static segT pdr_seg;
1087 /* The default target format to use. */
1090 mips_target_format (void)
1092 switch (OUTPUT_FLAVOR)
1094 case bfd_target_ecoff_flavour:
1095 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1096 case bfd_target_coff_flavour:
1098 case bfd_target_elf_flavour:
1100 /* This is traditional mips. */
1101 return (target_big_endian
1102 ? (HAVE_64BIT_OBJECTS
1103 ? "elf64-tradbigmips"
1105 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1106 : (HAVE_64BIT_OBJECTS
1107 ? "elf64-tradlittlemips"
1109 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1111 return (target_big_endian
1112 ? (HAVE_64BIT_OBJECTS
1115 ? "elf32-nbigmips" : "elf32-bigmips"))
1116 : (HAVE_64BIT_OBJECTS
1117 ? "elf64-littlemips"
1119 ? "elf32-nlittlemips" : "elf32-littlemips")));
1127 /* This function is called once, at assembler startup time. It should
1128 set up all the tables, etc. that the MD part of the assembler will need. */
1133 register const char *retval = NULL;
1137 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1138 as_warn (_("Could not set architecture and machine"));
1140 op_hash = hash_new ();
1142 for (i = 0; i < NUMOPCODES;)
1144 const char *name = mips_opcodes[i].name;
1146 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1149 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1150 mips_opcodes[i].name, retval);
1151 /* Probably a memory allocation problem? Give up now. */
1152 as_fatal (_("Broken assembler. No assembly attempted."));
1156 if (mips_opcodes[i].pinfo != INSN_MACRO)
1158 if (!validate_mips_insn (&mips_opcodes[i]))
1163 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1166 mips16_op_hash = hash_new ();
1169 while (i < bfd_mips16_num_opcodes)
1171 const char *name = mips16_opcodes[i].name;
1173 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1175 as_fatal (_("internal: can't hash `%s': %s"),
1176 mips16_opcodes[i].name, retval);
1179 if (mips16_opcodes[i].pinfo != INSN_MACRO
1180 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1181 != mips16_opcodes[i].match))
1183 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1184 mips16_opcodes[i].name, mips16_opcodes[i].args);
1189 while (i < bfd_mips16_num_opcodes
1190 && strcmp (mips16_opcodes[i].name, name) == 0);
1194 as_fatal (_("Broken assembler. No assembly attempted."));
1196 /* We add all the general register names to the symbol table. This
1197 helps us detect invalid uses of them. */
1198 for (i = 0; i < 32; i++)
1202 sprintf (buf, "$%d", i);
1203 symbol_table_insert (symbol_new (buf, reg_section, i,
1204 &zero_address_frag));
1206 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1207 &zero_address_frag));
1208 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1209 &zero_address_frag));
1210 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1211 &zero_address_frag));
1212 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1213 &zero_address_frag));
1214 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1215 &zero_address_frag));
1216 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1217 &zero_address_frag));
1218 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1219 &zero_address_frag));
1220 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1221 &zero_address_frag));
1222 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1223 &zero_address_frag));
1225 /* If we don't add these register names to the symbol table, they
1226 may end up being added as regular symbols by operand(), and then
1227 make it to the object file as undefined in case they're not
1228 regarded as local symbols. They're local in o32, since `$' is a
1229 local symbol prefix, but not in n32 or n64. */
1230 for (i = 0; i < 8; i++)
1234 sprintf (buf, "$fcc%i", i);
1235 symbol_table_insert (symbol_new (buf, reg_section, -1,
1236 &zero_address_frag));
1239 mips_no_prev_insn (FALSE);
1242 mips_cprmask[0] = 0;
1243 mips_cprmask[1] = 0;
1244 mips_cprmask[2] = 0;
1245 mips_cprmask[3] = 0;
1247 /* set the default alignment for the text section (2**2) */
1248 record_alignment (text_section, 2);
1250 bfd_set_gp_size (stdoutput, g_switch_value);
1252 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1254 /* On a native system, sections must be aligned to 16 byte
1255 boundaries. When configured for an embedded ELF target, we
1257 if (strcmp (TARGET_OS, "elf") != 0)
1259 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1260 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1261 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1264 /* Create a .reginfo section for register masks and a .mdebug
1265 section for debugging information. */
1273 subseg = now_subseg;
1275 /* The ABI says this section should be loaded so that the
1276 running program can access it. However, we don't load it
1277 if we are configured for an embedded target */
1278 flags = SEC_READONLY | SEC_DATA;
1279 if (strcmp (TARGET_OS, "elf") != 0)
1280 flags |= SEC_ALLOC | SEC_LOAD;
1282 if (mips_abi != N64_ABI)
1284 sec = subseg_new (".reginfo", (subsegT) 0);
1286 bfd_set_section_flags (stdoutput, sec, flags);
1287 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1290 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1295 /* The 64-bit ABI uses a .MIPS.options section rather than
1296 .reginfo section. */
1297 sec = subseg_new (".MIPS.options", (subsegT) 0);
1298 bfd_set_section_flags (stdoutput, sec, flags);
1299 bfd_set_section_alignment (stdoutput, sec, 3);
1302 /* Set up the option header. */
1304 Elf_Internal_Options opthdr;
1307 opthdr.kind = ODK_REGINFO;
1308 opthdr.size = (sizeof (Elf_External_Options)
1309 + sizeof (Elf64_External_RegInfo));
1312 f = frag_more (sizeof (Elf_External_Options));
1313 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1314 (Elf_External_Options *) f);
1316 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1321 if (ECOFF_DEBUGGING)
1323 sec = subseg_new (".mdebug", (subsegT) 0);
1324 (void) bfd_set_section_flags (stdoutput, sec,
1325 SEC_HAS_CONTENTS | SEC_READONLY);
1326 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1329 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1331 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1332 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1333 SEC_READONLY | SEC_RELOC
1335 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1339 subseg_set (seg, subseg);
1343 if (! ECOFF_DEBUGGING)
1350 if (! ECOFF_DEBUGGING)
1355 md_assemble (char *str)
1357 struct mips_cl_insn insn;
1358 bfd_reloc_code_real_type unused_reloc[3]
1359 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1361 imm_expr.X_op = O_absent;
1362 imm2_expr.X_op = O_absent;
1363 offset_expr.X_op = O_absent;
1364 imm_reloc[0] = BFD_RELOC_UNUSED;
1365 imm_reloc[1] = BFD_RELOC_UNUSED;
1366 imm_reloc[2] = BFD_RELOC_UNUSED;
1367 offset_reloc[0] = BFD_RELOC_UNUSED;
1368 offset_reloc[1] = BFD_RELOC_UNUSED;
1369 offset_reloc[2] = BFD_RELOC_UNUSED;
1371 if (mips_opts.mips16)
1372 mips16_ip (str, &insn);
1375 mips_ip (str, &insn);
1376 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1377 str, insn.insn_opcode));
1382 as_bad ("%s `%s'", insn_error, str);
1386 if (insn.insn_mo->pinfo == INSN_MACRO)
1389 if (mips_opts.mips16)
1390 mips16_macro (&insn);
1397 if (imm_expr.X_op != O_absent)
1398 append_insn (&insn, &imm_expr, imm_reloc);
1399 else if (offset_expr.X_op != O_absent)
1400 append_insn (&insn, &offset_expr, offset_reloc);
1402 append_insn (&insn, NULL, unused_reloc);
1406 /* Return true if the given relocation might need a matching %lo().
1407 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1408 applied to local symbols. */
1410 static inline bfd_boolean
1411 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1413 return (HAVE_IN_PLACE_ADDENDS
1414 && (reloc == BFD_RELOC_HI16_S
1415 || reloc == BFD_RELOC_MIPS_GOT16
1416 || reloc == BFD_RELOC_MIPS16_HI16_S));
1419 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1422 static inline bfd_boolean
1423 fixup_has_matching_lo_p (fixS *fixp)
1425 return (fixp->fx_next != NULL
1426 && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1427 || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
1428 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1429 && fixp->fx_offset == fixp->fx_next->fx_offset);
1432 /* See whether instruction IP reads register REG. CLASS is the type
1436 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1437 enum mips_regclass class)
1439 if (class == MIPS16_REG)
1441 assert (mips_opts.mips16);
1442 reg = mips16_to_32_reg_map[reg];
1443 class = MIPS_GR_REG;
1446 /* Don't report on general register ZERO, since it never changes. */
1447 if (class == MIPS_GR_REG && reg == ZERO)
1450 if (class == MIPS_FP_REG)
1452 assert (! mips_opts.mips16);
1453 /* If we are called with either $f0 or $f1, we must check $f0.
1454 This is not optimal, because it will introduce an unnecessary
1455 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1456 need to distinguish reading both $f0 and $f1 or just one of
1457 them. Note that we don't have to check the other way,
1458 because there is no instruction that sets both $f0 and $f1
1459 and requires a delay. */
1460 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1461 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1462 == (reg &~ (unsigned) 1)))
1464 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1465 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1466 == (reg &~ (unsigned) 1)))
1469 else if (! mips_opts.mips16)
1471 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1472 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1474 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1475 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1480 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1481 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1482 & MIPS16OP_MASK_RX)]
1485 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1486 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1487 & MIPS16OP_MASK_RY)]
1490 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1491 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1492 & MIPS16OP_MASK_MOVE32Z)]
1495 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1497 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1499 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1501 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1502 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1503 & MIPS16OP_MASK_REGR32) == reg)
1510 /* This function returns true if modifying a register requires a
1514 reg_needs_delay (unsigned int reg)
1516 unsigned long prev_pinfo;
1518 prev_pinfo = prev_insn.insn_mo->pinfo;
1519 if (! mips_opts.noreorder
1520 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1521 && ! gpr_interlocks)
1522 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1523 && ! cop_interlocks)))
1525 /* A load from a coprocessor or from memory. All load delays
1526 delay the use of general register rt for one instruction. */
1527 /* Itbl support may require additional care here. */
1528 know (prev_pinfo & INSN_WRITE_GPR_T);
1529 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1536 /* Mark instruction labels in mips16 mode. This permits the linker to
1537 handle them specially, such as generating jalx instructions when
1538 needed. We also make them odd for the duration of the assembly, in
1539 order to generate the right sort of code. We will make them even
1540 in the adjust_symtab routine, while leaving them marked. This is
1541 convenient for the debugger and the disassembler. The linker knows
1542 to make them odd again. */
1545 mips16_mark_labels (void)
1547 if (mips_opts.mips16)
1549 struct insn_label_list *l;
1552 for (l = insn_labels; l != NULL; l = l->next)
1555 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1556 S_SET_OTHER (l->label, STO_MIPS16);
1558 val = S_GET_VALUE (l->label);
1560 S_SET_VALUE (l->label, val + 1);
1565 /* End the current frag. Make it a variant frag and record the
1569 relax_close_frag (void)
1571 mips_macro_warning.first_frag = frag_now;
1572 frag_var (rs_machine_dependent, 0, 0,
1573 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1574 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1576 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1577 mips_relax.first_fixup = 0;
1580 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1581 See the comment above RELAX_ENCODE for more details. */
1584 relax_start (symbolS *symbol)
1586 assert (mips_relax.sequence == 0);
1587 mips_relax.sequence = 1;
1588 mips_relax.symbol = symbol;
1591 /* Start generating the second version of a relaxable sequence.
1592 See the comment above RELAX_ENCODE for more details. */
1597 assert (mips_relax.sequence == 1);
1598 mips_relax.sequence = 2;
1601 /* End the current relaxable sequence. */
1606 assert (mips_relax.sequence == 2);
1607 relax_close_frag ();
1608 mips_relax.sequence = 0;
1611 /* Output an instruction. IP is the instruction information.
1612 ADDRESS_EXPR is an operand of the instruction to be used with
1616 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1617 bfd_reloc_code_real_type *reloc_type)
1619 register unsigned long prev_pinfo, pinfo;
1623 relax_stateT prev_insn_frag_type = 0;
1624 bfd_boolean relaxed_branch = FALSE;
1625 bfd_boolean force_new_frag = FALSE;
1627 /* Mark instruction labels in mips16 mode. */
1628 mips16_mark_labels ();
1630 prev_pinfo = prev_insn.insn_mo->pinfo;
1631 pinfo = ip->insn_mo->pinfo;
1633 if (mips_relax.sequence != 2
1634 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1638 /* If the previous insn required any delay slots, see if we need
1639 to insert a NOP or two. There are eight kinds of possible
1640 hazards, of which an instruction can have at most one type.
1641 (1) a load from memory delay
1642 (2) a load from a coprocessor delay
1643 (3) an unconditional branch delay
1644 (4) a conditional branch delay
1645 (5) a move to coprocessor register delay
1646 (6) a load coprocessor register from memory delay
1647 (7) a coprocessor condition code delay
1648 (8) a HI/LO special register delay
1650 There are a lot of optimizations we could do that we don't.
1651 In particular, we do not, in general, reorder instructions.
1652 If you use gcc with optimization, it will reorder
1653 instructions and generally do much more optimization then we
1654 do here; repeating all that work in the assembler would only
1655 benefit hand written assembly code, and does not seem worth
1658 /* This is how a NOP is emitted. */
1659 #define emit_nop() \
1661 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1662 : md_number_to_chars (frag_more (4), 0, 4))
1664 /* The previous insn might require a delay slot, depending upon
1665 the contents of the current insn. */
1666 if (! mips_opts.mips16
1667 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1668 && ! gpr_interlocks)
1669 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1670 && ! cop_interlocks)))
1672 /* A load from a coprocessor or from memory. All load
1673 delays delay the use of general register rt for one
1675 /* Itbl support may require additional care here. */
1676 know (prev_pinfo & INSN_WRITE_GPR_T);
1677 if (mips_optimize == 0
1678 || insn_uses_reg (ip,
1679 ((prev_insn.insn_opcode >> OP_SH_RT)
1684 else if (! mips_opts.mips16
1685 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1686 && ! cop_interlocks)
1687 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1688 && ! cop_mem_interlocks)))
1690 /* A generic coprocessor delay. The previous instruction
1691 modified a coprocessor general or control register. If
1692 it modified a control register, we need to avoid any
1693 coprocessor instruction (this is probably not always
1694 required, but it sometimes is). If it modified a general
1695 register, we avoid using that register.
1697 This case is not handled very well. There is no special
1698 knowledge of CP0 handling, and the coprocessors other
1699 than the floating point unit are not distinguished at
1701 /* Itbl support may require additional care here. FIXME!
1702 Need to modify this to include knowledge about
1703 user specified delays! */
1704 if (prev_pinfo & INSN_WRITE_FPR_T)
1706 if (mips_optimize == 0
1707 || insn_uses_reg (ip,
1708 ((prev_insn.insn_opcode >> OP_SH_FT)
1713 else if (prev_pinfo & INSN_WRITE_FPR_S)
1715 if (mips_optimize == 0
1716 || insn_uses_reg (ip,
1717 ((prev_insn.insn_opcode >> OP_SH_FS)
1724 /* We don't know exactly what the previous instruction
1725 does. If the current instruction uses a coprocessor
1726 register, we must insert a NOP. If previous
1727 instruction may set the condition codes, and the
1728 current instruction uses them, we must insert two
1730 /* Itbl support may require additional care here. */
1731 if (mips_optimize == 0
1732 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1733 && (pinfo & INSN_READ_COND_CODE)))
1735 else if (pinfo & INSN_COP)
1739 else if (! mips_opts.mips16
1740 && (prev_pinfo & INSN_WRITE_COND_CODE)
1741 && ! cop_interlocks)
1743 /* The previous instruction sets the coprocessor condition
1744 codes, but does not require a general coprocessor delay
1745 (this means it is a floating point comparison
1746 instruction). If this instruction uses the condition
1747 codes, we need to insert a single NOP. */
1748 /* Itbl support may require additional care here. */
1749 if (mips_optimize == 0
1750 || (pinfo & INSN_READ_COND_CODE))
1754 /* If we're fixing up mfhi/mflo for the r7000 and the
1755 previous insn was an mfhi/mflo and the current insn
1756 reads the register that the mfhi/mflo wrote to, then
1759 else if (mips_7000_hilo_fix
1760 && MF_HILO_INSN (prev_pinfo)
1761 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1768 /* If we're fixing up mfhi/mflo for the r7000 and the
1769 2nd previous insn was an mfhi/mflo and the current insn
1770 reads the register that the mfhi/mflo wrote to, then
1773 else if (mips_7000_hilo_fix
1774 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1775 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1783 else if (prev_pinfo & INSN_READ_LO)
1785 /* The previous instruction reads the LO register; if the
1786 current instruction writes to the LO register, we must
1787 insert two NOPS. Some newer processors have interlocks.
1788 Also the tx39's multiply instructions can be executed
1789 immediately after a read from HI/LO (without the delay),
1790 though the tx39's divide insns still do require the
1792 if (! (hilo_interlocks
1793 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1794 && (mips_optimize == 0
1795 || (pinfo & INSN_WRITE_LO)))
1797 /* Most mips16 branch insns don't have a delay slot.
1798 If a read from LO is immediately followed by a branch
1799 to a write to LO we have a read followed by a write
1800 less than 2 insns away. We assume the target of
1801 a branch might be a write to LO, and insert a nop
1802 between a read and an immediately following branch. */
1803 else if (mips_opts.mips16
1804 && (mips_optimize == 0
1805 || (pinfo & MIPS16_INSN_BRANCH)))
1808 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1810 /* The previous instruction reads the HI register; if the
1811 current instruction writes to the HI register, we must
1812 insert a NOP. Some newer processors have interlocks.
1813 Also the note tx39's multiply above. */
1814 if (! (hilo_interlocks
1815 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1816 && (mips_optimize == 0
1817 || (pinfo & INSN_WRITE_HI)))
1819 /* Most mips16 branch insns don't have a delay slot.
1820 If a read from HI is immediately followed by a branch
1821 to a write to HI we have a read followed by a write
1822 less than 2 insns away. We assume the target of
1823 a branch might be a write to HI, and insert a nop
1824 between a read and an immediately following branch. */
1825 else if (mips_opts.mips16
1826 && (mips_optimize == 0
1827 || (pinfo & MIPS16_INSN_BRANCH)))
1831 /* If the previous instruction was in a noreorder section, then
1832 we don't want to insert the nop after all. */
1833 /* Itbl support may require additional care here. */
1834 if (prev_insn_unreordered)
1837 /* There are two cases which require two intervening
1838 instructions: 1) setting the condition codes using a move to
1839 coprocessor instruction which requires a general coprocessor
1840 delay and then reading the condition codes 2) reading the HI
1841 or LO register and then writing to it (except on processors
1842 which have interlocks). If we are not already emitting a NOP
1843 instruction, we must check for these cases compared to the
1844 instruction previous to the previous instruction. */
1845 if ((! mips_opts.mips16
1846 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1847 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1848 && (pinfo & INSN_READ_COND_CODE)
1849 && ! cop_interlocks)
1850 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1851 && (pinfo & INSN_WRITE_LO)
1852 && ! (hilo_interlocks
1853 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1854 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1855 && (pinfo & INSN_WRITE_HI)
1856 && ! (hilo_interlocks
1857 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1862 if (prev_prev_insn_unreordered)
1865 if (prev_prev_nop && nops == 0)
1868 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1870 /* We're out of bits in pinfo, so we must resort to string
1871 ops here. Shortcuts are selected based on opcodes being
1872 limited to the VR4120 instruction set. */
1874 const char *pn = prev_insn.insn_mo->name;
1875 const char *tn = ip->insn_mo->name;
1876 if (strncmp (pn, "macc", 4) == 0
1877 || strncmp (pn, "dmacc", 5) == 0)
1879 /* Errata 21 - [D]DIV[U] after [D]MACC */
1880 if (strstr (tn, "div"))
1883 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1884 instruction is executed immediately after a MACC or
1885 DMACC instruction, the result of [either instruction]
1887 if (strncmp (tn, "mult", 4) == 0
1888 || strncmp (tn, "dmult", 5) == 0)
1891 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1892 Applies on top of VR4181A MD(1) errata. */
1893 if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
1896 /* Errata 24 - MT{LO,HI} after [D]MACC */
1897 if (strcmp (tn, "mtlo") == 0
1898 || strcmp (tn, "mthi") == 0)
1901 else if (strncmp (pn, "dmult", 5) == 0
1902 && (strncmp (tn, "dmult", 5) == 0
1903 || strncmp (tn, "dmacc", 5) == 0))
1905 /* Here is the rest of errata 23. */
1908 else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
1909 && (strncmp (tn, "macc", 4) == 0
1910 || strncmp (tn, "dmacc", 5) == 0))
1912 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1913 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1914 DDIV or DDIVU instruction, the result of the MACC or
1915 DMACC instruction is incorrect.". This partly overlaps
1916 the workaround for errata 23. */
1919 if (nops < min_nops)
1923 /* If we are being given a nop instruction, don't bother with
1924 one of the nops we would otherwise output. This will only
1925 happen when a nop instruction is used with mips_optimize set
1928 && ! mips_opts.noreorder
1929 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1932 /* Now emit the right number of NOP instructions. */
1933 if (nops > 0 && ! mips_opts.noreorder)
1936 unsigned long old_frag_offset;
1938 struct insn_label_list *l;
1940 old_frag = frag_now;
1941 old_frag_offset = frag_now_fix ();
1943 for (i = 0; i < nops; i++)
1948 listing_prev_line ();
1949 /* We may be at the start of a variant frag. In case we
1950 are, make sure there is enough space for the frag
1951 after the frags created by listing_prev_line. The
1952 argument to frag_grow here must be at least as large
1953 as the argument to all other calls to frag_grow in
1954 this file. We don't have to worry about being in the
1955 middle of a variant frag, because the variants insert
1956 all needed nop instructions themselves. */
1960 for (l = insn_labels; l != NULL; l = l->next)
1964 assert (S_GET_SEGMENT (l->label) == now_seg);
1965 symbol_set_frag (l->label, frag_now);
1966 val = (valueT) frag_now_fix ();
1967 /* mips16 text labels are stored as odd. */
1968 if (mips_opts.mips16)
1970 S_SET_VALUE (l->label, val);
1973 #ifndef NO_ECOFF_DEBUGGING
1974 if (ECOFF_DEBUGGING)
1975 ecoff_fix_loc (old_frag, old_frag_offset);
1978 else if (prev_nop_frag != NULL)
1980 /* We have a frag holding nops we may be able to remove. If
1981 we don't need any nops, we can decrease the size of
1982 prev_nop_frag by the size of one instruction. If we do
1983 need some nops, we count them in prev_nops_required. */
1984 if (prev_nop_frag_since == 0)
1988 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1989 --prev_nop_frag_holds;
1992 prev_nop_frag_required += nops;
1996 if (prev_prev_nop == 0)
1998 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1999 --prev_nop_frag_holds;
2002 ++prev_nop_frag_required;
2005 if (prev_nop_frag_holds <= prev_nop_frag_required)
2006 prev_nop_frag = NULL;
2008 ++prev_nop_frag_since;
2010 /* Sanity check: by the time we reach the second instruction
2011 after prev_nop_frag, we should have used up all the nops
2012 one way or another. */
2013 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2018 /* The value passed to dwarf2_emit_insn is the distance between
2019 the beginning of the current instruction and the address that
2020 should be recorded in the debug tables. For MIPS16 debug info
2021 we want to use ISA-encoded addresses, so we pass -1 for an
2022 address higher by one than the current. */
2023 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2026 /* Record the frag type before frag_var. */
2028 prev_insn_frag_type = prev_insn_frag->fr_type;
2031 && *reloc_type == BFD_RELOC_16_PCREL_S2
2032 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2033 || pinfo & INSN_COND_BRANCH_LIKELY)
2034 && mips_relax_branch
2035 /* Don't try branch relaxation within .set nomacro, or within
2036 .set noat if we use $at for PIC computations. If it turns
2037 out that the branch was out-of-range, we'll get an error. */
2038 && !mips_opts.warn_about_macros
2039 && !(mips_opts.noat && mips_pic != NO_PIC)
2040 && !mips_opts.mips16)
2042 relaxed_branch = TRUE;
2043 f = frag_var (rs_machine_dependent,
2044 relaxed_branch_length
2046 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2047 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2049 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2050 pinfo & INSN_COND_BRANCH_LIKELY,
2051 pinfo & INSN_WRITE_GPR_31,
2053 address_expr->X_add_symbol,
2054 address_expr->X_add_number,
2056 *reloc_type = BFD_RELOC_UNUSED;
2058 else if (*reloc_type > BFD_RELOC_UNUSED)
2060 /* We need to set up a variant frag. */
2061 assert (mips_opts.mips16 && address_expr != NULL);
2062 f = frag_var (rs_machine_dependent, 4, 0,
2063 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2064 mips16_small, mips16_ext,
2066 & INSN_UNCOND_BRANCH_DELAY),
2067 (*prev_insn_reloc_type
2068 == BFD_RELOC_MIPS16_JMP)),
2069 make_expr_symbol (address_expr), 0, NULL);
2071 else if (mips_opts.mips16
2073 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2075 /* Make sure there is enough room to swap this instruction with
2076 a following jump instruction. */
2082 if (mips_opts.mips16
2083 && mips_opts.noreorder
2084 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2085 as_warn (_("extended instruction in delay slot"));
2087 if (mips_relax.sequence)
2089 /* If we've reached the end of this frag, turn it into a variant
2090 frag and record the information for the instructions we've
2092 if (frag_room () < 4)
2093 relax_close_frag ();
2094 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2097 if (mips_relax.sequence != 2)
2098 mips_macro_warning.sizes[0] += 4;
2099 if (mips_relax.sequence != 1)
2100 mips_macro_warning.sizes[1] += 4;
2105 fixp[0] = fixp[1] = fixp[2] = NULL;
2106 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2108 if (address_expr->X_op == O_constant)
2112 switch (*reloc_type)
2115 ip->insn_opcode |= address_expr->X_add_number;
2118 case BFD_RELOC_MIPS_HIGHEST:
2119 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2120 ip->insn_opcode |= tmp & 0xffff;
2123 case BFD_RELOC_MIPS_HIGHER:
2124 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2125 ip->insn_opcode |= tmp & 0xffff;
2128 case BFD_RELOC_HI16_S:
2129 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2130 ip->insn_opcode |= tmp & 0xffff;
2133 case BFD_RELOC_HI16:
2134 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2137 case BFD_RELOC_UNUSED:
2138 case BFD_RELOC_LO16:
2139 case BFD_RELOC_MIPS_GOT_DISP:
2140 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2143 case BFD_RELOC_MIPS_JMP:
2144 if ((address_expr->X_add_number & 3) != 0)
2145 as_bad (_("jump to misaligned address (0x%lx)"),
2146 (unsigned long) address_expr->X_add_number);
2147 if (address_expr->X_add_number & ~0xfffffff)
2148 as_bad (_("jump address range overflow (0x%lx)"),
2149 (unsigned long) address_expr->X_add_number);
2150 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2153 case BFD_RELOC_MIPS16_JMP:
2154 if ((address_expr->X_add_number & 3) != 0)
2155 as_bad (_("jump to misaligned address (0x%lx)"),
2156 (unsigned long) address_expr->X_add_number);
2157 if (address_expr->X_add_number & ~0xfffffff)
2158 as_bad (_("jump address range overflow (0x%lx)"),
2159 (unsigned long) address_expr->X_add_number);
2161 (((address_expr->X_add_number & 0x7c0000) << 3)
2162 | ((address_expr->X_add_number & 0xf800000) >> 7)
2163 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2166 case BFD_RELOC_16_PCREL_S2:
2173 else if (*reloc_type < BFD_RELOC_UNUSED)
2176 reloc_howto_type *howto;
2179 /* In a compound relocation, it is the final (outermost)
2180 operator that determines the relocated field. */
2181 for (i = 1; i < 3; i++)
2182 if (reloc_type[i] == BFD_RELOC_UNUSED)
2185 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2186 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2187 bfd_get_reloc_size(howto),
2189 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2192 /* These relocations can have an addend that won't fit in
2193 4 octets for 64bit assembly. */
2195 && ! howto->partial_inplace
2196 && (reloc_type[0] == BFD_RELOC_16
2197 || reloc_type[0] == BFD_RELOC_32
2198 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2199 || reloc_type[0] == BFD_RELOC_HI16_S
2200 || reloc_type[0] == BFD_RELOC_LO16
2201 || reloc_type[0] == BFD_RELOC_GPREL16
2202 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2203 || reloc_type[0] == BFD_RELOC_GPREL32
2204 || reloc_type[0] == BFD_RELOC_64
2205 || reloc_type[0] == BFD_RELOC_CTOR
2206 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2207 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2208 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2209 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2210 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2211 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
2212 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
2213 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
2214 || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
2215 fixp[0]->fx_no_overflow = 1;
2217 if (mips_relax.sequence)
2219 if (mips_relax.first_fixup == 0)
2220 mips_relax.first_fixup = fixp[0];
2222 else if (reloc_needs_lo_p (*reloc_type))
2224 struct mips_hi_fixup *hi_fixup;
2226 /* Reuse the last entry if it already has a matching %lo. */
2227 hi_fixup = mips_hi_fixup_list;
2229 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2231 hi_fixup = ((struct mips_hi_fixup *)
2232 xmalloc (sizeof (struct mips_hi_fixup)));
2233 hi_fixup->next = mips_hi_fixup_list;
2234 mips_hi_fixup_list = hi_fixup;
2236 hi_fixup->fixp = fixp[0];
2237 hi_fixup->seg = now_seg;
2240 /* Add fixups for the second and third relocations, if given.
2241 Note that the ABI allows the second relocation to be
2242 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2243 moment we only use RSS_UNDEF, but we could add support
2244 for the others if it ever becomes necessary. */
2245 for (i = 1; i < 3; i++)
2246 if (reloc_type[i] != BFD_RELOC_UNUSED)
2248 fixp[i] = fix_new (frag_now, fixp[0]->fx_where,
2249 fixp[0]->fx_size, NULL, 0,
2250 FALSE, reloc_type[i]);
2252 /* Use fx_tcbit to mark compound relocs. */
2253 fixp[0]->fx_tcbit = 1;
2254 fixp[i]->fx_tcbit = 1;
2259 if (! mips_opts.mips16)
2260 md_number_to_chars (f, ip->insn_opcode, 4);
2261 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2263 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2264 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2270 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2273 md_number_to_chars (f, ip->insn_opcode, 2);
2276 /* Update the register mask information. */
2277 if (! mips_opts.mips16)
2279 if (pinfo & INSN_WRITE_GPR_D)
2280 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2281 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2282 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2283 if (pinfo & INSN_READ_GPR_S)
2284 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2285 if (pinfo & INSN_WRITE_GPR_31)
2286 mips_gprmask |= 1 << RA;
2287 if (pinfo & INSN_WRITE_FPR_D)
2288 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2289 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2290 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2291 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2292 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2293 if ((pinfo & INSN_READ_FPR_R) != 0)
2294 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2295 if (pinfo & INSN_COP)
2297 /* We don't keep enough information to sort these cases out.
2298 The itbl support does keep this information however, although
2299 we currently don't support itbl fprmats as part of the cop
2300 instruction. May want to add this support in the future. */
2302 /* Never set the bit for $0, which is always zero. */
2303 mips_gprmask &= ~1 << 0;
2307 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2308 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2309 & MIPS16OP_MASK_RX);
2310 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2311 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2312 & MIPS16OP_MASK_RY);
2313 if (pinfo & MIPS16_INSN_WRITE_Z)
2314 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2315 & MIPS16OP_MASK_RZ);
2316 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2317 mips_gprmask |= 1 << TREG;
2318 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2319 mips_gprmask |= 1 << SP;
2320 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2321 mips_gprmask |= 1 << RA;
2322 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2323 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2324 if (pinfo & MIPS16_INSN_READ_Z)
2325 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2326 & MIPS16OP_MASK_MOVE32Z);
2327 if (pinfo & MIPS16_INSN_READ_GPR_X)
2328 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2329 & MIPS16OP_MASK_REGR32);
2332 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2334 /* Filling the branch delay slot is more complex. We try to
2335 switch the branch with the previous instruction, which we can
2336 do if the previous instruction does not set up a condition
2337 that the branch tests and if the branch is not itself the
2338 target of any branch. */
2339 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2340 || (pinfo & INSN_COND_BRANCH_DELAY))
2342 if (mips_optimize < 2
2343 /* If we have seen .set volatile or .set nomove, don't
2345 || mips_opts.nomove != 0
2346 /* If we had to emit any NOP instructions, then we
2347 already know we can not swap. */
2349 /* If we don't even know the previous insn, we can not
2351 || ! prev_insn_valid
2352 /* If the previous insn is already in a branch delay
2353 slot, then we can not swap. */
2354 || prev_insn_is_delay_slot
2355 /* If the previous previous insn was in a .set
2356 noreorder, we can't swap. Actually, the MIPS
2357 assembler will swap in this situation. However, gcc
2358 configured -with-gnu-as will generate code like
2364 in which we can not swap the bne and INSN. If gcc is
2365 not configured -with-gnu-as, it does not output the
2366 .set pseudo-ops. We don't have to check
2367 prev_insn_unreordered, because prev_insn_valid will
2368 be 0 in that case. We don't want to use
2369 prev_prev_insn_valid, because we do want to be able
2370 to swap at the start of a function. */
2371 || prev_prev_insn_unreordered
2372 /* If the branch is itself the target of a branch, we
2373 can not swap. We cheat on this; all we check for is
2374 whether there is a label on this instruction. If
2375 there are any branches to anything other than a
2376 label, users must use .set noreorder. */
2377 || insn_labels != NULL
2378 /* If the previous instruction is in a variant frag
2379 other than this branch's one, we cannot do the swap.
2380 This does not apply to the mips16, which uses variant
2381 frags for different purposes. */
2382 || (! mips_opts.mips16
2383 && prev_insn_frag_type == rs_machine_dependent)
2384 /* If the branch reads the condition codes, we don't
2385 even try to swap, because in the sequence
2390 we can not swap, and I don't feel like handling that
2392 || (! mips_opts.mips16
2393 && (pinfo & INSN_READ_COND_CODE)
2394 && ! cop_interlocks)
2395 /* We can not swap with an instruction that requires a
2396 delay slot, because the target of the branch might
2397 interfere with that instruction. */
2398 || (! mips_opts.mips16
2400 /* Itbl support may require additional care here. */
2401 & (INSN_LOAD_COPROC_DELAY
2402 | INSN_COPROC_MOVE_DELAY
2403 | INSN_WRITE_COND_CODE))
2404 && ! cop_interlocks)
2405 || (! (hilo_interlocks
2406 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2410 || (! mips_opts.mips16
2411 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2412 && ! gpr_interlocks)
2413 || (! mips_opts.mips16
2414 /* Itbl support may require additional care here. */
2415 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2416 && ! cop_mem_interlocks)
2417 /* We can not swap with a branch instruction. */
2419 & (INSN_UNCOND_BRANCH_DELAY
2420 | INSN_COND_BRANCH_DELAY
2421 | INSN_COND_BRANCH_LIKELY))
2422 /* We do not swap with a trap instruction, since it
2423 complicates trap handlers to have the trap
2424 instruction be in a delay slot. */
2425 || (prev_pinfo & INSN_TRAP)
2426 /* If the branch reads a register that the previous
2427 instruction sets, we can not swap. */
2428 || (! mips_opts.mips16
2429 && (prev_pinfo & INSN_WRITE_GPR_T)
2430 && insn_uses_reg (ip,
2431 ((prev_insn.insn_opcode >> OP_SH_RT)
2434 || (! mips_opts.mips16
2435 && (prev_pinfo & INSN_WRITE_GPR_D)
2436 && insn_uses_reg (ip,
2437 ((prev_insn.insn_opcode >> OP_SH_RD)
2440 || (mips_opts.mips16
2441 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2442 && insn_uses_reg (ip,
2443 ((prev_insn.insn_opcode
2445 & MIPS16OP_MASK_RX),
2447 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2448 && insn_uses_reg (ip,
2449 ((prev_insn.insn_opcode
2451 & MIPS16OP_MASK_RY),
2453 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2454 && insn_uses_reg (ip,
2455 ((prev_insn.insn_opcode
2457 & MIPS16OP_MASK_RZ),
2459 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2460 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2461 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2462 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2463 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2464 && insn_uses_reg (ip,
2465 MIPS16OP_EXTRACT_REG32R (prev_insn.
2468 /* If the branch writes a register that the previous
2469 instruction sets, we can not swap (we know that
2470 branches write only to RD or to $31). */
2471 || (! mips_opts.mips16
2472 && (prev_pinfo & INSN_WRITE_GPR_T)
2473 && (((pinfo & INSN_WRITE_GPR_D)
2474 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2475 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2476 || ((pinfo & INSN_WRITE_GPR_31)
2477 && (((prev_insn.insn_opcode >> OP_SH_RT)
2480 || (! mips_opts.mips16
2481 && (prev_pinfo & INSN_WRITE_GPR_D)
2482 && (((pinfo & INSN_WRITE_GPR_D)
2483 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2484 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2485 || ((pinfo & INSN_WRITE_GPR_31)
2486 && (((prev_insn.insn_opcode >> OP_SH_RD)
2489 || (mips_opts.mips16
2490 && (pinfo & MIPS16_INSN_WRITE_31)
2491 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2492 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2493 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2495 /* If the branch writes a register that the previous
2496 instruction reads, we can not swap (we know that
2497 branches only write to RD or to $31). */
2498 || (! mips_opts.mips16
2499 && (pinfo & INSN_WRITE_GPR_D)
2500 && insn_uses_reg (&prev_insn,
2501 ((ip->insn_opcode >> OP_SH_RD)
2504 || (! mips_opts.mips16
2505 && (pinfo & INSN_WRITE_GPR_31)
2506 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2507 || (mips_opts.mips16
2508 && (pinfo & MIPS16_INSN_WRITE_31)
2509 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2510 /* If the previous previous instruction has a load
2511 delay, and sets a register that the branch reads, we
2513 || (! mips_opts.mips16
2514 /* Itbl support may require additional care here. */
2515 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2516 && ! cop_interlocks)
2517 || ((prev_prev_insn.insn_mo->pinfo
2518 & INSN_LOAD_MEMORY_DELAY)
2519 && ! gpr_interlocks))
2520 && insn_uses_reg (ip,
2521 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2524 /* If one instruction sets a condition code and the
2525 other one uses a condition code, we can not swap. */
2526 || ((pinfo & INSN_READ_COND_CODE)
2527 && (prev_pinfo & INSN_WRITE_COND_CODE))
2528 || ((pinfo & INSN_WRITE_COND_CODE)
2529 && (prev_pinfo & INSN_READ_COND_CODE))
2530 /* If the previous instruction uses the PC, we can not
2532 || (mips_opts.mips16
2533 && (prev_pinfo & MIPS16_INSN_READ_PC))
2534 /* If the previous instruction was extended, we can not
2536 || (mips_opts.mips16 && prev_insn_extended)
2537 /* If the previous instruction had a fixup in mips16
2538 mode, we can not swap. This normally means that the
2539 previous instruction was a 4 byte branch anyhow. */
2540 || (mips_opts.mips16 && prev_insn_fixp[0])
2541 /* If the previous instruction is a sync, sync.l, or
2542 sync.p, we can not swap. */
2543 || (prev_pinfo & INSN_SYNC))
2545 /* We could do even better for unconditional branches to
2546 portions of this object file; we could pick up the
2547 instruction at the destination, put it in the delay
2548 slot, and bump the destination address. */
2550 if (mips_relax.sequence)
2551 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2552 /* Update the previous insn information. */
2553 prev_prev_insn = *ip;
2554 prev_insn.insn_mo = &dummy_opcode;
2558 /* It looks like we can actually do the swap. */
2559 if (! mips_opts.mips16)
2564 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2565 if (!relaxed_branch)
2567 /* If this is not a relaxed branch, then just
2568 swap the instructions. */
2569 memcpy (temp, prev_f, 4);
2570 memcpy (prev_f, f, 4);
2571 memcpy (f, temp, 4);
2575 /* If this is a relaxed branch, then we move the
2576 instruction to be placed in the delay slot to
2577 the current frag, shrinking the fixed part of
2578 the originating frag. If the branch occupies
2579 the tail of the latter, we move it backwards,
2580 into the space freed by the moved instruction. */
2582 memcpy (f, prev_f, 4);
2583 prev_insn_frag->fr_fix -= 4;
2584 if (prev_insn_frag->fr_type == rs_machine_dependent)
2585 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2588 if (prev_insn_fixp[0])
2590 prev_insn_fixp[0]->fx_frag = frag_now;
2591 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2593 if (prev_insn_fixp[1])
2595 prev_insn_fixp[1]->fx_frag = frag_now;
2596 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2598 if (prev_insn_fixp[2])
2600 prev_insn_fixp[2]->fx_frag = frag_now;
2601 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2603 if (prev_insn_fixp[0] && HAVE_NEWABI
2604 && prev_insn_frag != frag_now
2605 && (prev_insn_fixp[0]->fx_r_type
2606 == BFD_RELOC_MIPS_GOT_DISP
2607 || (prev_insn_fixp[0]->fx_r_type
2608 == BFD_RELOC_MIPS_CALL16)))
2610 /* To avoid confusion in tc_gen_reloc, we must
2611 ensure that this does not become a variant
2613 force_new_frag = TRUE;
2616 if (!relaxed_branch)
2620 fixp[0]->fx_frag = prev_insn_frag;
2621 fixp[0]->fx_where = prev_insn_where;
2625 fixp[1]->fx_frag = prev_insn_frag;
2626 fixp[1]->fx_where = prev_insn_where;
2630 fixp[2]->fx_frag = prev_insn_frag;
2631 fixp[2]->fx_where = prev_insn_where;
2634 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2637 fixp[0]->fx_where -= 4;
2639 fixp[1]->fx_where -= 4;
2641 fixp[2]->fx_where -= 4;
2649 assert (prev_insn_fixp[0] == NULL);
2650 assert (prev_insn_fixp[1] == NULL);
2651 assert (prev_insn_fixp[2] == NULL);
2652 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2653 memcpy (temp, prev_f, 2);
2654 memcpy (prev_f, f, 2);
2655 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2657 assert (*reloc_type == BFD_RELOC_UNUSED);
2658 memcpy (f, temp, 2);
2662 memcpy (f, f + 2, 2);
2663 memcpy (f + 2, temp, 2);
2667 fixp[0]->fx_frag = prev_insn_frag;
2668 fixp[0]->fx_where = prev_insn_where;
2672 fixp[1]->fx_frag = prev_insn_frag;
2673 fixp[1]->fx_where = prev_insn_where;
2677 fixp[2]->fx_frag = prev_insn_frag;
2678 fixp[2]->fx_where = prev_insn_where;
2682 /* Update the previous insn information; leave prev_insn
2684 prev_prev_insn = *ip;
2686 prev_insn_is_delay_slot = 1;
2688 /* If that was an unconditional branch, forget the previous
2689 insn information. */
2690 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2692 prev_prev_insn.insn_mo = &dummy_opcode;
2693 prev_insn.insn_mo = &dummy_opcode;
2696 prev_insn_fixp[0] = NULL;
2697 prev_insn_fixp[1] = NULL;
2698 prev_insn_fixp[2] = NULL;
2699 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2700 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2701 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2702 prev_insn_extended = 0;
2704 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2706 /* We don't yet optimize a branch likely. What we should do
2707 is look at the target, copy the instruction found there
2708 into the delay slot, and increment the branch to jump to
2709 the next instruction. */
2711 /* Update the previous insn information. */
2712 prev_prev_insn = *ip;
2713 prev_insn.insn_mo = &dummy_opcode;
2714 prev_insn_fixp[0] = NULL;
2715 prev_insn_fixp[1] = NULL;
2716 prev_insn_fixp[2] = NULL;
2717 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2718 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2719 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2720 prev_insn_extended = 0;
2721 prev_insn_is_delay_slot = 1;
2725 /* Update the previous insn information. */
2727 prev_prev_insn.insn_mo = &dummy_opcode;
2729 prev_prev_insn = prev_insn;
2732 /* Any time we see a branch, we always fill the delay slot
2733 immediately; since this insn is not a branch, we know it
2734 is not in a delay slot. */
2735 prev_insn_is_delay_slot = 0;
2737 prev_insn_fixp[0] = fixp[0];
2738 prev_insn_fixp[1] = fixp[1];
2739 prev_insn_fixp[2] = fixp[2];
2740 prev_insn_reloc_type[0] = reloc_type[0];
2741 prev_insn_reloc_type[1] = reloc_type[1];
2742 prev_insn_reloc_type[2] = reloc_type[2];
2743 if (mips_opts.mips16)
2744 prev_insn_extended = (ip->use_extend
2745 || *reloc_type > BFD_RELOC_UNUSED);
2748 prev_prev_insn_unreordered = prev_insn_unreordered;
2749 prev_insn_unreordered = 0;
2750 prev_insn_frag = frag_now;
2751 prev_insn_where = f - frag_now->fr_literal;
2752 prev_insn_valid = 1;
2754 else if (mips_relax.sequence != 2)
2756 /* We need to record a bit of information even when we are not
2757 reordering, in order to determine the base address for mips16
2758 PC relative relocs. */
2759 prev_prev_insn = prev_insn;
2761 prev_insn_reloc_type[0] = reloc_type[0];
2762 prev_insn_reloc_type[1] = reloc_type[1];
2763 prev_insn_reloc_type[2] = reloc_type[2];
2764 prev_prev_insn_unreordered = prev_insn_unreordered;
2765 prev_insn_unreordered = 1;
2768 /* We just output an insn, so the next one doesn't have a label. */
2769 mips_clear_insn_labels ();
2772 /* This function forgets that there was any previous instruction or
2773 label. If PRESERVE is non-zero, it remembers enough information to
2774 know whether nops are needed before a noreorder section. */
2777 mips_no_prev_insn (int preserve)
2781 prev_insn.insn_mo = &dummy_opcode;
2782 prev_prev_insn.insn_mo = &dummy_opcode;
2783 prev_nop_frag = NULL;
2784 prev_nop_frag_holds = 0;
2785 prev_nop_frag_required = 0;
2786 prev_nop_frag_since = 0;
2788 prev_insn_valid = 0;
2789 prev_insn_is_delay_slot = 0;
2790 prev_insn_unreordered = 0;
2791 prev_insn_extended = 0;
2792 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2793 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2794 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2795 prev_prev_insn_unreordered = 0;
2796 mips_clear_insn_labels ();
2799 /* This function must be called whenever we turn on noreorder or emit
2800 something other than instructions. It inserts any NOPS which might
2801 be needed by the previous instruction, and clears the information
2802 kept for the previous instructions. The INSNS parameter is true if
2803 instructions are to follow. */
2806 mips_emit_delays (bfd_boolean insns)
2808 if (! mips_opts.noreorder)
2813 if ((! mips_opts.mips16
2814 && ((prev_insn.insn_mo->pinfo
2815 & (INSN_LOAD_COPROC_DELAY
2816 | INSN_COPROC_MOVE_DELAY
2817 | INSN_WRITE_COND_CODE))
2818 && ! cop_interlocks))
2819 || (! hilo_interlocks
2820 && (prev_insn.insn_mo->pinfo
2823 || (! mips_opts.mips16
2824 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2825 && ! gpr_interlocks)
2826 || (! mips_opts.mips16
2827 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2828 && ! cop_mem_interlocks))
2830 /* Itbl support may require additional care here. */
2832 if ((! mips_opts.mips16
2833 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2834 && ! cop_interlocks))
2835 || (! hilo_interlocks
2836 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2837 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2840 if (prev_insn_unreordered)
2843 else if ((! mips_opts.mips16
2844 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2845 && ! cop_interlocks))
2846 || (! hilo_interlocks
2847 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2848 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2850 /* Itbl support may require additional care here. */
2851 if (! prev_prev_insn_unreordered)
2855 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2858 const char *pn = prev_insn.insn_mo->name;
2859 if (strncmp (pn, "macc", 4) == 0
2860 || strncmp (pn, "dmacc", 5) == 0
2861 || strncmp (pn, "dmult", 5) == 0
2862 || strstr (pn, "div"))
2864 if (nops < min_nops)
2870 struct insn_label_list *l;
2874 /* Record the frag which holds the nop instructions, so
2875 that we can remove them if we don't need them. */
2876 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2877 prev_nop_frag = frag_now;
2878 prev_nop_frag_holds = nops;
2879 prev_nop_frag_required = 0;
2880 prev_nop_frag_since = 0;
2883 for (; nops > 0; --nops)
2888 /* Move on to a new frag, so that it is safe to simply
2889 decrease the size of prev_nop_frag. */
2890 frag_wane (frag_now);
2894 for (l = insn_labels; l != NULL; l = l->next)
2898 assert (S_GET_SEGMENT (l->label) == now_seg);
2899 symbol_set_frag (l->label, frag_now);
2900 val = (valueT) frag_now_fix ();
2901 /* mips16 text labels are stored as odd. */
2902 if (mips_opts.mips16)
2904 S_SET_VALUE (l->label, val);
2909 /* Mark instruction labels in mips16 mode. */
2911 mips16_mark_labels ();
2913 mips_no_prev_insn (insns);
2916 /* Set up global variables for the start of a new macro. */
2921 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2922 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2923 && (prev_insn.insn_mo->pinfo
2924 & (INSN_UNCOND_BRANCH_DELAY
2925 | INSN_COND_BRANCH_DELAY
2926 | INSN_COND_BRANCH_LIKELY)) != 0);
2929 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2930 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2931 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2934 macro_warning (relax_substateT subtype)
2936 if (subtype & RELAX_DELAY_SLOT)
2937 return _("Macro instruction expanded into multiple instructions"
2938 " in a branch delay slot");
2939 else if (subtype & RELAX_NOMACRO)
2940 return _("Macro instruction expanded into multiple instructions");
2945 /* Finish up a macro. Emit warnings as appropriate. */
2950 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2952 relax_substateT subtype;
2954 /* Set up the relaxation warning flags. */
2956 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2957 subtype |= RELAX_SECOND_LONGER;
2958 if (mips_opts.warn_about_macros)
2959 subtype |= RELAX_NOMACRO;
2960 if (mips_macro_warning.delay_slot_p)
2961 subtype |= RELAX_DELAY_SLOT;
2963 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2965 /* Either the macro has a single implementation or both
2966 implementations are longer than 4 bytes. Emit the
2968 const char *msg = macro_warning (subtype);
2974 /* One implementation might need a warning but the other
2975 definitely doesn't. */
2976 mips_macro_warning.first_frag->fr_subtype |= subtype;
2981 /* Read a macro's relocation codes from *ARGS and store them in *R.
2982 The first argument in *ARGS will be either the code for a single
2983 relocation or -1 followed by the three codes that make up a
2984 composite relocation. */
2987 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
2991 next = va_arg (*args, int);
2993 r[0] = (bfd_reloc_code_real_type) next;
2995 for (i = 0; i < 3; i++)
2996 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
2999 /* Build an instruction created by a macro expansion. This is passed
3000 a pointer to the count of instructions created so far, an
3001 expression, the name of the instruction to build, an operand format
3002 string, and corresponding arguments. */
3005 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3007 struct mips_cl_insn insn;
3008 bfd_reloc_code_real_type r[3];
3011 va_start (args, fmt);
3013 if (mips_opts.mips16)
3015 mips16_macro_build (ep, name, fmt, args);
3020 r[0] = BFD_RELOC_UNUSED;
3021 r[1] = BFD_RELOC_UNUSED;
3022 r[2] = BFD_RELOC_UNUSED;
3023 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3024 assert (insn.insn_mo);
3025 assert (strcmp (name, insn.insn_mo->name) == 0);
3027 /* Search until we get a match for NAME. */
3030 /* It is assumed here that macros will never generate
3031 MDMX or MIPS-3D instructions. */
3032 if (strcmp (fmt, insn.insn_mo->args) == 0
3033 && insn.insn_mo->pinfo != INSN_MACRO
3034 && OPCODE_IS_MEMBER (insn.insn_mo,
3036 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3038 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3042 assert (insn.insn_mo->name);
3043 assert (strcmp (name, insn.insn_mo->name) == 0);
3046 insn.insn_opcode = insn.insn_mo->match;
3064 insn.insn_opcode |= (va_arg (args, int)
3065 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3070 /* Note that in the macro case, these arguments are already
3071 in MSB form. (When handling the instruction in the
3072 non-macro case, these arguments are sizes from which
3073 MSB values must be calculated.) */
3074 insn.insn_opcode |= (va_arg (args, int)
3075 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3081 /* Note that in the macro case, these arguments are already
3082 in MSBD form. (When handling the instruction in the
3083 non-macro case, these arguments are sizes from which
3084 MSBD values must be calculated.) */
3085 insn.insn_opcode |= (va_arg (args, int)
3086 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3097 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3101 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3106 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3112 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3117 int tmp = va_arg (args, int);
3119 insn.insn_opcode |= tmp << OP_SH_RT;
3120 insn.insn_opcode |= tmp << OP_SH_RD;
3126 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3133 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3137 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3141 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3145 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3149 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3156 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3162 macro_read_relocs (&args, r);
3163 assert (*r == BFD_RELOC_GPREL16
3164 || *r == BFD_RELOC_MIPS_LITERAL
3165 || *r == BFD_RELOC_MIPS_HIGHER
3166 || *r == BFD_RELOC_HI16_S
3167 || *r == BFD_RELOC_LO16
3168 || *r == BFD_RELOC_MIPS_GOT16
3169 || *r == BFD_RELOC_MIPS_CALL16
3170 || *r == BFD_RELOC_MIPS_GOT_DISP
3171 || *r == BFD_RELOC_MIPS_GOT_PAGE
3172 || *r == BFD_RELOC_MIPS_GOT_OFST
3173 || *r == BFD_RELOC_MIPS_GOT_LO16
3174 || *r == BFD_RELOC_MIPS_CALL_LO16);
3178 macro_read_relocs (&args, r);
3180 && (ep->X_op == O_constant
3181 || (ep->X_op == O_symbol
3182 && (*r == BFD_RELOC_MIPS_HIGHEST
3183 || *r == BFD_RELOC_HI16_S
3184 || *r == BFD_RELOC_HI16
3185 || *r == BFD_RELOC_GPREL16
3186 || *r == BFD_RELOC_MIPS_GOT_HI16
3187 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3191 assert (ep != NULL);
3193 * This allows macro() to pass an immediate expression for
3194 * creating short branches without creating a symbol.
3195 * Note that the expression still might come from the assembly
3196 * input, in which case the value is not checked for range nor
3197 * is a relocation entry generated (yuck).
3199 if (ep->X_op == O_constant)
3201 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3205 *r = BFD_RELOC_16_PCREL_S2;
3209 assert (ep != NULL);
3210 *r = BFD_RELOC_MIPS_JMP;
3214 insn.insn_opcode |= va_arg (args, unsigned long);
3223 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3225 append_insn (&insn, ep, r);
3229 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3232 struct mips_cl_insn insn;
3233 bfd_reloc_code_real_type r[3]
3234 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3236 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3237 assert (insn.insn_mo);
3238 assert (strcmp (name, insn.insn_mo->name) == 0);
3240 while (strcmp (fmt, insn.insn_mo->args) != 0
3241 || insn.insn_mo->pinfo == INSN_MACRO)
3244 assert (insn.insn_mo->name);
3245 assert (strcmp (name, insn.insn_mo->name) == 0);
3248 insn.insn_opcode = insn.insn_mo->match;
3249 insn.use_extend = FALSE;
3268 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3273 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3277 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3281 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3291 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3298 regno = va_arg (args, int);
3299 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3300 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3321 assert (ep != NULL);
3323 if (ep->X_op != O_constant)
3324 *r = (int) BFD_RELOC_UNUSED + c;
3327 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3328 FALSE, &insn.insn_opcode, &insn.use_extend,
3331 *r = BFD_RELOC_UNUSED;
3337 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3344 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3346 append_insn (&insn, ep, r);
3350 * Generate a "jalr" instruction with a relocation hint to the called
3351 * function. This occurs in NewABI PIC code.
3354 macro_build_jalr (expressionS *ep)
3363 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3365 fix_new_exp (frag_now, f - frag_now->fr_literal,
3366 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3370 * Generate a "lui" instruction.
3373 macro_build_lui (expressionS *ep, int regnum)
3375 expressionS high_expr;
3376 struct mips_cl_insn insn;
3377 bfd_reloc_code_real_type r[3]
3378 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3379 const char *name = "lui";
3380 const char *fmt = "t,u";
3382 assert (! mips_opts.mips16);
3386 if (high_expr.X_op == O_constant)
3388 /* we can compute the instruction now without a relocation entry */
3389 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3391 *r = BFD_RELOC_UNUSED;
3395 assert (ep->X_op == O_symbol);
3396 /* _gp_disp is a special case, used from s_cpload.
3397 __gnu_local_gp is used if mips_no_shared. */
3398 assert (mips_pic == NO_PIC
3400 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
3401 || (! mips_in_shared
3402 && strcmp (S_GET_NAME (ep->X_add_symbol),
3403 "__gnu_local_gp") == 0));
3404 *r = BFD_RELOC_HI16_S;
3407 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3408 assert (insn.insn_mo);
3409 assert (strcmp (name, insn.insn_mo->name) == 0);
3410 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3412 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3413 if (*r == BFD_RELOC_UNUSED)
3415 insn.insn_opcode |= high_expr.X_add_number;
3416 append_insn (&insn, NULL, r);
3419 append_insn (&insn, &high_expr, r);
3422 /* Generate a sequence of instructions to do a load or store from a constant
3423 offset off of a base register (breg) into/from a target register (treg),
3424 using AT if necessary. */
3426 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3427 int treg, int breg, int dbl)
3429 assert (ep->X_op == O_constant);
3431 /* Sign-extending 32-bit constants makes their handling easier. */
3432 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3433 == ~((bfd_vma) 0x7fffffff)))
3435 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3436 as_bad (_("constant too large"));
3438 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3442 /* Right now, this routine can only handle signed 32-bit constants. */
3443 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3444 as_warn (_("operand overflow"));
3446 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3448 /* Signed 16-bit offset will fit in the op. Easy! */
3449 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3453 /* 32-bit offset, need multiple instructions and AT, like:
3454 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3455 addu $tempreg,$tempreg,$breg
3456 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3457 to handle the complete offset. */
3458 macro_build_lui (ep, AT);
3459 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3460 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3463 as_bad (_("Macro used $at after \".set noat\""));
3468 * Generates code to set the $at register to true (one)
3469 * if reg is less than the immediate expression.
3472 set_at (int reg, int unsignedp)
3474 if (imm_expr.X_op == O_constant
3475 && imm_expr.X_add_number >= -0x8000
3476 && imm_expr.X_add_number < 0x8000)
3477 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3478 AT, reg, BFD_RELOC_LO16);
3481 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3482 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3487 normalize_constant_expr (expressionS *ex)
3489 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3490 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3494 /* Warn if an expression is not a constant. */
3497 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3499 if (ex->X_op == O_big)
3500 as_bad (_("unsupported large constant"));
3501 else if (ex->X_op != O_constant)
3502 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3504 normalize_constant_expr (ex);
3507 /* Count the leading zeroes by performing a binary chop. This is a
3508 bulky bit of source, but performance is a LOT better for the
3509 majority of values than a simple loop to count the bits:
3510 for (lcnt = 0; (lcnt < 32); lcnt++)
3511 if ((v) & (1 << (31 - lcnt)))
3513 However it is not code size friendly, and the gain will drop a bit
3514 on certain cached systems.
3516 #define COUNT_TOP_ZEROES(v) \
3517 (((v) & ~0xffff) == 0 \
3518 ? ((v) & ~0xff) == 0 \
3519 ? ((v) & ~0xf) == 0 \
3520 ? ((v) & ~0x3) == 0 \
3521 ? ((v) & ~0x1) == 0 \
3526 : ((v) & ~0x7) == 0 \
3529 : ((v) & ~0x3f) == 0 \
3530 ? ((v) & ~0x1f) == 0 \
3533 : ((v) & ~0x7f) == 0 \
3536 : ((v) & ~0xfff) == 0 \
3537 ? ((v) & ~0x3ff) == 0 \
3538 ? ((v) & ~0x1ff) == 0 \
3541 : ((v) & ~0x7ff) == 0 \
3544 : ((v) & ~0x3fff) == 0 \
3545 ? ((v) & ~0x1fff) == 0 \
3548 : ((v) & ~0x7fff) == 0 \
3551 : ((v) & ~0xffffff) == 0 \
3552 ? ((v) & ~0xfffff) == 0 \
3553 ? ((v) & ~0x3ffff) == 0 \
3554 ? ((v) & ~0x1ffff) == 0 \
3557 : ((v) & ~0x7ffff) == 0 \
3560 : ((v) & ~0x3fffff) == 0 \
3561 ? ((v) & ~0x1fffff) == 0 \
3564 : ((v) & ~0x7fffff) == 0 \
3567 : ((v) & ~0xfffffff) == 0 \
3568 ? ((v) & ~0x3ffffff) == 0 \
3569 ? ((v) & ~0x1ffffff) == 0 \
3572 : ((v) & ~0x7ffffff) == 0 \
3575 : ((v) & ~0x3fffffff) == 0 \
3576 ? ((v) & ~0x1fffffff) == 0 \
3579 : ((v) & ~0x7fffffff) == 0 \
3584 * This routine generates the least number of instructions necessary to load
3585 * an absolute expression value into a register.
3588 load_register (int reg, expressionS *ep, int dbl)
3591 expressionS hi32, lo32;
3593 if (ep->X_op != O_big)
3595 assert (ep->X_op == O_constant);
3597 /* Sign-extending 32-bit constants makes their handling easier. */
3598 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3599 == ~((bfd_vma) 0x7fffffff)))
3601 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3602 as_bad (_("constant too large"));
3604 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3608 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3610 /* We can handle 16 bit signed values with an addiu to
3611 $zero. No need to ever use daddiu here, since $zero and
3612 the result are always correct in 32 bit mode. */
3613 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3616 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3618 /* We can handle 16 bit unsigned values with an ori to
3620 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3623 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3625 /* 32 bit values require an lui. */
3626 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3627 if ((ep->X_add_number & 0xffff) != 0)
3628 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3633 /* The value is larger than 32 bits. */
3635 if (HAVE_32BIT_GPRS)
3637 as_bad (_("Number (0x%lx) larger than 32 bits"),
3638 (unsigned long) ep->X_add_number);
3639 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3643 if (ep->X_op != O_big)
3646 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3647 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3648 hi32.X_add_number &= 0xffffffff;
3650 lo32.X_add_number &= 0xffffffff;
3654 assert (ep->X_add_number > 2);
3655 if (ep->X_add_number == 3)
3656 generic_bignum[3] = 0;
3657 else if (ep->X_add_number > 4)
3658 as_bad (_("Number larger than 64 bits"));
3659 lo32.X_op = O_constant;
3660 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3661 hi32.X_op = O_constant;
3662 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3665 if (hi32.X_add_number == 0)
3670 unsigned long hi, lo;
3672 if (hi32.X_add_number == (offsetT) 0xffffffff)
3674 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3676 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3679 if (lo32.X_add_number & 0x80000000)
3681 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3682 if (lo32.X_add_number & 0xffff)
3683 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3688 /* Check for 16bit shifted constant. We know that hi32 is
3689 non-zero, so start the mask on the first bit of the hi32
3694 unsigned long himask, lomask;
3698 himask = 0xffff >> (32 - shift);
3699 lomask = (0xffff << shift) & 0xffffffff;
3703 himask = 0xffff << (shift - 32);
3706 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3707 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3711 tmp.X_op = O_constant;
3713 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3714 | (lo32.X_add_number >> shift));
3716 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3717 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3718 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3719 reg, reg, (shift >= 32) ? shift - 32 : shift);
3724 while (shift <= (64 - 16));
3726 /* Find the bit number of the lowest one bit, and store the
3727 shifted value in hi/lo. */
3728 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3729 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3733 while ((lo & 1) == 0)
3738 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3744 while ((hi & 1) == 0)
3753 /* Optimize if the shifted value is a (power of 2) - 1. */
3754 if ((hi == 0 && ((lo + 1) & lo) == 0)
3755 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3757 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3762 /* This instruction will set the register to be all
3764 tmp.X_op = O_constant;
3765 tmp.X_add_number = (offsetT) -1;
3766 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3770 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3771 reg, reg, (bit >= 32) ? bit - 32 : bit);
3773 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3774 reg, reg, (shift >= 32) ? shift - 32 : shift);
3779 /* Sign extend hi32 before calling load_register, because we can
3780 generally get better code when we load a sign extended value. */
3781 if ((hi32.X_add_number & 0x80000000) != 0)
3782 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3783 load_register (reg, &hi32, 0);
3786 if ((lo32.X_add_number & 0xffff0000) == 0)
3790 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3798 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3800 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3801 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3807 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3811 mid16.X_add_number >>= 16;
3812 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3813 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3816 if ((lo32.X_add_number & 0xffff) != 0)
3817 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3821 load_delay_nop (void)
3823 if (!gpr_interlocks)
3824 macro_build (NULL, "nop", "");
3827 /* Load an address into a register. */
3830 load_address (int reg, expressionS *ep, int *used_at)
3832 if (ep->X_op != O_constant
3833 && ep->X_op != O_symbol)
3835 as_bad (_("expression too complex"));
3836 ep->X_op = O_constant;
3839 if (ep->X_op == O_constant)
3841 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3845 if (mips_pic == NO_PIC)
3847 /* If this is a reference to a GP relative symbol, we want
3848 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3850 lui $reg,<sym> (BFD_RELOC_HI16_S)
3851 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3852 If we have an addend, we always use the latter form.
3854 With 64bit address space and a usable $at we want
3855 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3856 lui $at,<sym> (BFD_RELOC_HI16_S)
3857 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3858 daddiu $at,<sym> (BFD_RELOC_LO16)
3862 If $at is already in use, we use a path which is suboptimal
3863 on superscalar processors.
3864 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3865 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3867 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3869 daddiu $reg,<sym> (BFD_RELOC_LO16)
3871 For GP relative symbols in 64bit address space we can use
3872 the same sequence as in 32bit address space. */
3873 if (HAVE_64BIT_SYMBOLS)
3875 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3876 && !nopic_need_relax (ep->X_add_symbol, 1))
3878 relax_start (ep->X_add_symbol);
3879 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3880 mips_gp_register, BFD_RELOC_GPREL16);
3884 if (*used_at == 0 && !mips_opts.noat)
3886 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3887 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3888 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3889 BFD_RELOC_MIPS_HIGHER);
3890 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3891 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3892 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3897 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3898 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3899 BFD_RELOC_MIPS_HIGHER);
3900 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3901 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3902 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3903 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3906 if (mips_relax.sequence)
3911 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3912 && !nopic_need_relax (ep->X_add_symbol, 1))
3914 relax_start (ep->X_add_symbol);
3915 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3916 mips_gp_register, BFD_RELOC_GPREL16);
3919 macro_build_lui (ep, reg);
3920 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3921 reg, reg, BFD_RELOC_LO16);
3922 if (mips_relax.sequence)
3926 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3930 /* If this is a reference to an external symbol, we want
3931 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3933 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3935 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3936 If there is a constant, it must be added in after.
3938 If we have NewABI, we want
3939 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3940 unless we're referencing a global symbol with a non-zero
3941 offset, in which case cst must be added separately. */
3944 if (ep->X_add_number)
3946 ex.X_add_number = ep->X_add_number;
3947 ep->X_add_number = 0;
3948 relax_start (ep->X_add_symbol);
3949 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3950 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3951 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3952 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3953 ex.X_op = O_constant;
3954 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3955 reg, reg, BFD_RELOC_LO16);
3956 ep->X_add_number = ex.X_add_number;
3959 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3960 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3961 if (mips_relax.sequence)
3966 ex.X_add_number = ep->X_add_number;
3967 ep->X_add_number = 0;
3968 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3969 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3971 relax_start (ep->X_add_symbol);
3973 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3977 if (ex.X_add_number != 0)
3979 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3980 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3981 ex.X_op = O_constant;
3982 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3983 reg, reg, BFD_RELOC_LO16);
3987 else if (mips_pic == SVR4_PIC)
3991 /* This is the large GOT case. If this is a reference to an
3992 external symbol, we want
3993 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3995 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3997 Otherwise, for a reference to a local symbol in old ABI, we want
3998 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4000 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4001 If there is a constant, it must be added in after.
4003 In the NewABI, for local symbols, with or without offsets, we want:
4004 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4005 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4009 ex.X_add_number = ep->X_add_number;
4010 ep->X_add_number = 0;
4011 relax_start (ep->X_add_symbol);
4012 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4014 reg, reg, mips_gp_register);
4015 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4016 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4017 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4018 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4019 else if (ex.X_add_number)
4021 ex.X_op = O_constant;
4022 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4026 ep->X_add_number = ex.X_add_number;
4028 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4029 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4030 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4031 BFD_RELOC_MIPS_GOT_OFST);
4036 ex.X_add_number = ep->X_add_number;
4037 ep->X_add_number = 0;
4038 relax_start (ep->X_add_symbol);
4039 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4040 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4041 reg, reg, mips_gp_register);
4042 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4043 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4045 if (reg_needs_delay (mips_gp_register))
4047 /* We need a nop before loading from $gp. This special
4048 check is required because the lui which starts the main
4049 instruction stream does not refer to $gp, and so will not
4050 insert the nop which may be required. */
4051 macro_build (NULL, "nop", "");
4053 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4054 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4056 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4060 if (ex.X_add_number != 0)
4062 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4063 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4064 ex.X_op = O_constant;
4065 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4073 if (mips_opts.noat && *used_at == 1)
4074 as_bad (_("Macro used $at after \".set noat\""));
4077 /* Move the contents of register SOURCE into register DEST. */
4080 move_register (int dest, int source)
4082 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4086 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4087 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4088 The two alternatives are:
4090 Global symbol Local sybmol
4091 ------------- ------------
4092 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4094 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4096 load_got_offset emits the first instruction and add_got_offset
4097 emits the second for a 16-bit offset or add_got_offset_hilo emits
4098 a sequence to add a 32-bit offset using a scratch register. */
4101 load_got_offset (int dest, expressionS *local)
4106 global.X_add_number = 0;
4108 relax_start (local->X_add_symbol);
4109 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4110 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4112 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4113 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4118 add_got_offset (int dest, expressionS *local)
4122 global.X_op = O_constant;
4123 global.X_op_symbol = NULL;
4124 global.X_add_symbol = NULL;
4125 global.X_add_number = local->X_add_number;
4127 relax_start (local->X_add_symbol);
4128 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4129 dest, dest, BFD_RELOC_LO16);
4131 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4136 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4139 int hold_mips_optimize;
4141 global.X_op = O_constant;
4142 global.X_op_symbol = NULL;
4143 global.X_add_symbol = NULL;
4144 global.X_add_number = local->X_add_number;
4146 relax_start (local->X_add_symbol);
4147 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4149 /* Set mips_optimize around the lui instruction to avoid
4150 inserting an unnecessary nop after the lw. */
4151 hold_mips_optimize = mips_optimize;
4153 macro_build_lui (&global, tmp);
4154 mips_optimize = hold_mips_optimize;
4155 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4158 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4163 * This routine implements the seemingly endless macro or synthesized
4164 * instructions and addressing modes in the mips assembly language. Many
4165 * of these macros are simple and are similar to each other. These could
4166 * probably be handled by some kind of table or grammar approach instead of
4167 * this verbose method. Others are not simple macros but are more like
4168 * optimizing code generation.
4169 * One interesting optimization is when several store macros appear
4170 * consecutively that would load AT with the upper half of the same address.
4171 * The ensuing load upper instructions are ommited. This implies some kind
4172 * of global optimization. We currently only optimize within a single macro.
4173 * For many of the load and store macros if the address is specified as a
4174 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4175 * first load register 'at' with zero and use it as the base register. The
4176 * mips assembler simply uses register $zero. Just one tiny optimization
4180 macro (struct mips_cl_insn *ip)
4182 register int treg, sreg, dreg, breg;
4198 bfd_reloc_code_real_type r;
4199 int hold_mips_optimize;
4201 assert (! mips_opts.mips16);
4203 treg = (ip->insn_opcode >> 16) & 0x1f;
4204 dreg = (ip->insn_opcode >> 11) & 0x1f;
4205 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4206 mask = ip->insn_mo->mask;
4208 expr1.X_op = O_constant;
4209 expr1.X_op_symbol = NULL;
4210 expr1.X_add_symbol = NULL;
4211 expr1.X_add_number = 1;
4223 mips_emit_delays (TRUE);
4224 ++mips_opts.noreorder;
4225 mips_any_noreorder = 1;
4227 expr1.X_add_number = 8;
4228 macro_build (&expr1, "bgez", "s,p", sreg);
4230 macro_build (NULL, "nop", "", 0);
4232 move_register (dreg, sreg);
4233 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4235 --mips_opts.noreorder;
4256 if (imm_expr.X_op == O_constant
4257 && imm_expr.X_add_number >= -0x8000
4258 && imm_expr.X_add_number < 0x8000)
4260 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4264 load_register (AT, &imm_expr, dbl);
4265 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4284 if (imm_expr.X_op == O_constant
4285 && imm_expr.X_add_number >= 0
4286 && imm_expr.X_add_number < 0x10000)
4288 if (mask != M_NOR_I)
4289 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4292 macro_build (&imm_expr, "ori", "t,r,i",
4293 treg, sreg, BFD_RELOC_LO16);
4294 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4300 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4301 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4318 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4320 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4324 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4325 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4333 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4338 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4342 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4343 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4349 /* check for > max integer */
4350 maxnum = 0x7fffffff;
4351 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4358 if (imm_expr.X_op == O_constant
4359 && imm_expr.X_add_number >= maxnum
4360 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4363 /* result is always false */
4365 macro_build (NULL, "nop", "", 0);
4367 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4370 if (imm_expr.X_op != O_constant)
4371 as_bad (_("Unsupported large constant"));
4372 ++imm_expr.X_add_number;
4376 if (mask == M_BGEL_I)
4378 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4380 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4383 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4385 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4388 maxnum = 0x7fffffff;
4389 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4396 maxnum = - maxnum - 1;
4397 if (imm_expr.X_op == O_constant
4398 && imm_expr.X_add_number <= maxnum
4399 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4402 /* result is always true */
4403 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4404 macro_build (&offset_expr, "b", "p");
4409 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4419 macro_build (&offset_expr, likely ? "beql" : "beq",
4424 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4425 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4433 && imm_expr.X_op == O_constant
4434 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4436 if (imm_expr.X_op != O_constant)
4437 as_bad (_("Unsupported large constant"));
4438 ++imm_expr.X_add_number;
4442 if (mask == M_BGEUL_I)
4444 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4446 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4448 macro_build (&offset_expr, likely ? "bnel" : "bne",
4454 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4462 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4467 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4471 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4472 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4480 macro_build (&offset_expr, likely ? "bnel" : "bne",
4487 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4488 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4496 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4501 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4505 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4506 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4512 maxnum = 0x7fffffff;
4513 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4520 if (imm_expr.X_op == O_constant
4521 && imm_expr.X_add_number >= maxnum
4522 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4524 if (imm_expr.X_op != O_constant)
4525 as_bad (_("Unsupported large constant"));
4526 ++imm_expr.X_add_number;
4530 if (mask == M_BLTL_I)
4532 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4534 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4537 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4539 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4544 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4552 macro_build (&offset_expr, likely ? "beql" : "beq",
4559 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4560 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4568 && imm_expr.X_op == O_constant
4569 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4571 if (imm_expr.X_op != O_constant)
4572 as_bad (_("Unsupported large constant"));
4573 ++imm_expr.X_add_number;
4577 if (mask == M_BLTUL_I)
4579 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4581 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4583 macro_build (&offset_expr, likely ? "beql" : "beq",
4589 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4597 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4602 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4606 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4607 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4617 macro_build (&offset_expr, likely ? "bnel" : "bne",
4622 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4623 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4631 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4633 as_bad (_("Unsupported large constant"));
4638 pos = (unsigned long) imm_expr.X_add_number;
4639 size = (unsigned long) imm2_expr.X_add_number;
4644 as_bad (_("Improper position (%lu)"), pos);
4647 if (size == 0 || size > 64
4648 || (pos + size - 1) > 63)
4650 as_bad (_("Improper extract size (%lu, position %lu)"),
4655 if (size <= 32 && pos < 32)
4660 else if (size <= 32)
4670 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4679 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4681 as_bad (_("Unsupported large constant"));
4686 pos = (unsigned long) imm_expr.X_add_number;
4687 size = (unsigned long) imm2_expr.X_add_number;
4692 as_bad (_("Improper position (%lu)"), pos);
4695 if (size == 0 || size > 64
4696 || (pos + size - 1) > 63)
4698 as_bad (_("Improper insert size (%lu, position %lu)"),
4703 if (pos < 32 && (pos + size - 1) < 32)
4718 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4735 as_warn (_("Divide by zero."));
4737 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4739 macro_build (NULL, "break", "c", 7);
4743 mips_emit_delays (TRUE);
4744 ++mips_opts.noreorder;
4745 mips_any_noreorder = 1;
4748 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4749 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4753 expr1.X_add_number = 8;
4754 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4755 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4756 macro_build (NULL, "break", "c", 7);
4758 expr1.X_add_number = -1;
4760 load_register (AT, &expr1, dbl);
4761 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4762 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4765 expr1.X_add_number = 1;
4766 load_register (AT, &expr1, dbl);
4767 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4771 expr1.X_add_number = 0x80000000;
4772 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4776 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4777 /* We want to close the noreorder block as soon as possible, so
4778 that later insns are available for delay slot filling. */
4779 --mips_opts.noreorder;
4783 expr1.X_add_number = 8;
4784 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4785 macro_build (NULL, "nop", "", 0);
4787 /* We want to close the noreorder block as soon as possible, so
4788 that later insns are available for delay slot filling. */
4789 --mips_opts.noreorder;
4791 macro_build (NULL, "break", "c", 6);
4793 macro_build (NULL, s, "d", dreg);
4832 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4834 as_warn (_("Divide by zero."));
4836 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4838 macro_build (NULL, "break", "c", 7);
4841 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4843 if (strcmp (s2, "mflo") == 0)
4844 move_register (dreg, sreg);
4846 move_register (dreg, 0);
4849 if (imm_expr.X_op == O_constant
4850 && imm_expr.X_add_number == -1
4851 && s[strlen (s) - 1] != 'u')
4853 if (strcmp (s2, "mflo") == 0)
4855 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4858 move_register (dreg, 0);
4863 load_register (AT, &imm_expr, dbl);
4864 macro_build (NULL, s, "z,s,t", sreg, AT);
4865 macro_build (NULL, s2, "d", dreg);
4884 mips_emit_delays (TRUE);
4885 ++mips_opts.noreorder;
4886 mips_any_noreorder = 1;
4889 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4890 macro_build (NULL, s, "z,s,t", sreg, treg);
4891 /* We want to close the noreorder block as soon as possible, so
4892 that later insns are available for delay slot filling. */
4893 --mips_opts.noreorder;
4897 expr1.X_add_number = 8;
4898 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4899 macro_build (NULL, s, "z,s,t", sreg, treg);
4901 /* We want to close the noreorder block as soon as possible, so
4902 that later insns are available for delay slot filling. */
4903 --mips_opts.noreorder;
4904 macro_build (NULL, "break", "c", 7);
4906 macro_build (NULL, s2, "d", dreg);
4918 /* Load the address of a symbol into a register. If breg is not
4919 zero, we then add a base register to it. */
4921 if (dbl && HAVE_32BIT_GPRS)
4922 as_warn (_("dla used to load 32-bit register"));
4924 if (! dbl && HAVE_64BIT_OBJECTS)
4925 as_warn (_("la used to load 64-bit address"));
4927 if (offset_expr.X_op == O_constant
4928 && offset_expr.X_add_number >= -0x8000
4929 && offset_expr.X_add_number < 0x8000)
4931 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
4932 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4936 if (!mips_opts.noat && (treg == breg))
4946 if (offset_expr.X_op != O_symbol
4947 && offset_expr.X_op != O_constant)
4949 as_bad (_("expression too complex"));
4950 offset_expr.X_op = O_constant;
4953 if (offset_expr.X_op == O_constant)
4954 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
4955 else if (mips_pic == NO_PIC)
4957 /* If this is a reference to a GP relative symbol, we want
4958 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4960 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4961 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4962 If we have a constant, we need two instructions anyhow,
4963 so we may as well always use the latter form.
4965 With 64bit address space and a usable $at we want
4966 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4967 lui $at,<sym> (BFD_RELOC_HI16_S)
4968 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4969 daddiu $at,<sym> (BFD_RELOC_LO16)
4971 daddu $tempreg,$tempreg,$at
4973 If $at is already in use, we use a path which is suboptimal
4974 on superscalar processors.
4975 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4976 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4978 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4980 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4982 For GP relative symbols in 64bit address space we can use
4983 the same sequence as in 32bit address space. */
4984 if (HAVE_64BIT_SYMBOLS)
4986 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4987 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
4989 relax_start (offset_expr.X_add_symbol);
4990 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4991 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4995 if (used_at == 0 && !mips_opts.noat)
4997 macro_build (&offset_expr, "lui", "t,u",
4998 tempreg, BFD_RELOC_MIPS_HIGHEST);
4999 macro_build (&offset_expr, "lui", "t,u",
5000 AT, BFD_RELOC_HI16_S);
5001 macro_build (&offset_expr, "daddiu", "t,r,j",
5002 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5003 macro_build (&offset_expr, "daddiu", "t,r,j",
5004 AT, AT, BFD_RELOC_LO16);
5005 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5006 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5011 macro_build (&offset_expr, "lui", "t,u",
5012 tempreg, BFD_RELOC_MIPS_HIGHEST);
5013 macro_build (&offset_expr, "daddiu", "t,r,j",
5014 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5015 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5016 macro_build (&offset_expr, "daddiu", "t,r,j",
5017 tempreg, tempreg, BFD_RELOC_HI16_S);
5018 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5019 macro_build (&offset_expr, "daddiu", "t,r,j",
5020 tempreg, tempreg, BFD_RELOC_LO16);
5023 if (mips_relax.sequence)
5028 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5029 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5031 relax_start (offset_expr.X_add_symbol);
5032 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5033 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5036 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5037 as_bad (_("offset too large"));
5038 macro_build_lui (&offset_expr, tempreg);
5039 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5040 tempreg, tempreg, BFD_RELOC_LO16);
5041 if (mips_relax.sequence)
5045 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5047 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5049 /* If this is a reference to an external symbol, and there
5050 is no constant, we want
5051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5052 or for lca or if tempreg is PIC_CALL_REG
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5054 For a local symbol, we want
5055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5057 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5059 If we have a small constant, and this is a reference to
5060 an external symbol, we want
5061 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5063 addiu $tempreg,$tempreg,<constant>
5064 For a local symbol, we want the same instruction
5065 sequence, but we output a BFD_RELOC_LO16 reloc on the
5068 If we have a large constant, and this is a reference to
5069 an external symbol, we want
5070 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5071 lui $at,<hiconstant>
5072 addiu $at,$at,<loconstant>
5073 addu $tempreg,$tempreg,$at
5074 For a local symbol, we want the same instruction
5075 sequence, but we output a BFD_RELOC_LO16 reloc on the
5079 if (offset_expr.X_add_number == 0)
5081 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5082 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5084 relax_start (offset_expr.X_add_symbol);
5085 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5086 lw_reloc_type, mips_gp_register);
5089 /* We're going to put in an addu instruction using
5090 tempreg, so we may as well insert the nop right
5095 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5096 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5098 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5099 tempreg, tempreg, BFD_RELOC_LO16);
5101 /* FIXME: If breg == 0, and the next instruction uses
5102 $tempreg, then if this variant case is used an extra
5103 nop will be generated. */
5105 else if (offset_expr.X_add_number >= -0x8000
5106 && offset_expr.X_add_number < 0x8000)
5108 load_got_offset (tempreg, &offset_expr);
5110 add_got_offset (tempreg, &offset_expr);
5114 expr1.X_add_number = offset_expr.X_add_number;
5115 offset_expr.X_add_number =
5116 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5117 load_got_offset (tempreg, &offset_expr);
5118 offset_expr.X_add_number = expr1.X_add_number;
5119 /* If we are going to add in a base register, and the
5120 target register and the base register are the same,
5121 then we are using AT as a temporary register. Since
5122 we want to load the constant into AT, we add our
5123 current AT (from the global offset table) and the
5124 register into the register now, and pretend we were
5125 not using a base register. */
5129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5134 add_got_offset_hilo (tempreg, &offset_expr, AT);
5138 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5140 int add_breg_early = 0;
5142 /* If this is a reference to an external, and there is no
5143 constant, or local symbol (*), with or without a
5145 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5146 or for lca or if tempreg is PIC_CALL_REG
5147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5149 If we have a small constant, and this is a reference to
5150 an external symbol, we want
5151 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5152 addiu $tempreg,$tempreg,<constant>
5154 If we have a large constant, and this is a reference to
5155 an external symbol, we want
5156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5157 lui $at,<hiconstant>
5158 addiu $at,$at,<loconstant>
5159 addu $tempreg,$tempreg,$at
5161 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5162 local symbols, even though it introduces an additional
5165 if (offset_expr.X_add_number)
5167 expr1.X_add_number = offset_expr.X_add_number;
5168 offset_expr.X_add_number = 0;
5170 relax_start (offset_expr.X_add_symbol);
5171 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5172 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5174 if (expr1.X_add_number >= -0x8000
5175 && expr1.X_add_number < 0x8000)
5177 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5178 tempreg, tempreg, BFD_RELOC_LO16);
5180 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5184 /* If we are going to add in a base register, and the
5185 target register and the base register are the same,
5186 then we are using AT as a temporary register. Since
5187 we want to load the constant into AT, we add our
5188 current AT (from the global offset table) and the
5189 register into the register now, and pretend we were
5190 not using a base register. */
5195 assert (tempreg == AT);
5196 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5202 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5203 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5209 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5212 offset_expr.X_add_number = expr1.X_add_number;
5214 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5215 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5218 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5219 treg, tempreg, breg);
5225 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5227 relax_start (offset_expr.X_add_symbol);
5228 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5229 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5231 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5232 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5237 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5238 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5241 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5244 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5245 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5246 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5248 /* This is the large GOT case. If this is a reference to an
5249 external symbol, and there is no constant, we want
5250 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5251 addu $tempreg,$tempreg,$gp
5252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5253 or for lca or if tempreg is PIC_CALL_REG
5254 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5255 addu $tempreg,$tempreg,$gp
5256 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5257 For a local symbol, we want
5258 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5260 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5262 If we have a small constant, and this is a reference to
5263 an external symbol, we want
5264 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5265 addu $tempreg,$tempreg,$gp
5266 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5268 addiu $tempreg,$tempreg,<constant>
5269 For a local symbol, we want
5270 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5272 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5274 If we have a large constant, and this is a reference to
5275 an external symbol, we want
5276 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5277 addu $tempreg,$tempreg,$gp
5278 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5279 lui $at,<hiconstant>
5280 addiu $at,$at,<loconstant>
5281 addu $tempreg,$tempreg,$at
5282 For a local symbol, we want
5283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5284 lui $at,<hiconstant>
5285 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5286 addu $tempreg,$tempreg,$at
5289 expr1.X_add_number = offset_expr.X_add_number;
5290 offset_expr.X_add_number = 0;
5291 relax_start (offset_expr.X_add_symbol);
5292 gpdelay = reg_needs_delay (mips_gp_register);
5293 if (expr1.X_add_number == 0 && breg == 0
5294 && (call || tempreg == PIC_CALL_REG))
5296 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5297 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5299 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5300 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5301 tempreg, tempreg, mips_gp_register);
5302 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5303 tempreg, lw_reloc_type, tempreg);
5304 if (expr1.X_add_number == 0)
5308 /* We're going to put in an addu instruction using
5309 tempreg, so we may as well insert the nop right
5314 else if (expr1.X_add_number >= -0x8000
5315 && expr1.X_add_number < 0x8000)
5318 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5319 tempreg, tempreg, BFD_RELOC_LO16);
5325 /* If we are going to add in a base register, and the
5326 target register and the base register are the same,
5327 then we are using AT as a temporary register. Since
5328 we want to load the constant into AT, we add our
5329 current AT (from the global offset table) and the
5330 register into the register now, and pretend we were
5331 not using a base register. */
5336 assert (tempreg == AT);
5338 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5343 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5344 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5348 offset_expr.X_add_number =
5349 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5354 /* This is needed because this instruction uses $gp, but
5355 the first instruction on the main stream does not. */
5356 macro_build (NULL, "nop", "");
5359 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5360 local_reloc_type, mips_gp_register);
5361 if (expr1.X_add_number >= -0x8000
5362 && expr1.X_add_number < 0x8000)
5365 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5366 tempreg, tempreg, BFD_RELOC_LO16);
5367 /* FIXME: If add_number is 0, and there was no base
5368 register, the external symbol case ended with a load,
5369 so if the symbol turns out to not be external, and
5370 the next instruction uses tempreg, an unnecessary nop
5371 will be inserted. */
5377 /* We must add in the base register now, as in the
5378 external symbol case. */
5379 assert (tempreg == AT);
5381 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5384 /* We set breg to 0 because we have arranged to add
5385 it in in both cases. */
5389 macro_build_lui (&expr1, AT);
5390 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5391 AT, AT, BFD_RELOC_LO16);
5392 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5393 tempreg, tempreg, AT);
5398 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5400 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5401 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5402 int add_breg_early = 0;
5404 /* This is the large GOT case. If this is a reference to an
5405 external symbol, and there is no constant, we want
5406 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5407 add $tempreg,$tempreg,$gp
5408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5409 or for lca or if tempreg is PIC_CALL_REG
5410 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5411 add $tempreg,$tempreg,$gp
5412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5414 If we have a small constant, and this is a reference to
5415 an external symbol, we want
5416 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5417 add $tempreg,$tempreg,$gp
5418 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5419 addi $tempreg,$tempreg,<constant>
5421 If we have a large constant, and this is a reference to
5422 an external symbol, we want
5423 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5424 addu $tempreg,$tempreg,$gp
5425 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5426 lui $at,<hiconstant>
5427 addi $at,$at,<loconstant>
5428 add $tempreg,$tempreg,$at
5430 If we have NewABI, and we know it's a local symbol, we want
5431 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5432 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5433 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5435 relax_start (offset_expr.X_add_symbol);
5437 expr1.X_add_number = offset_expr.X_add_number;
5438 offset_expr.X_add_number = 0;
5440 if (expr1.X_add_number == 0 && breg == 0
5441 && (call || tempreg == PIC_CALL_REG))
5443 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5444 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5446 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5447 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5448 tempreg, tempreg, mips_gp_register);
5449 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5450 tempreg, lw_reloc_type, tempreg);
5452 if (expr1.X_add_number == 0)
5454 else if (expr1.X_add_number >= -0x8000
5455 && expr1.X_add_number < 0x8000)
5457 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5458 tempreg, tempreg, BFD_RELOC_LO16);
5460 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5464 /* If we are going to add in a base register, and the
5465 target register and the base register are the same,
5466 then we are using AT as a temporary register. Since
5467 we want to load the constant into AT, we add our
5468 current AT (from the global offset table) and the
5469 register into the register now, and pretend we were
5470 not using a base register. */
5475 assert (tempreg == AT);
5476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5482 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5483 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5488 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5491 offset_expr.X_add_number = expr1.X_add_number;
5492 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5493 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5494 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5495 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5499 treg, tempreg, breg);
5509 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
5513 /* The j instruction may not be used in PIC code, since it
5514 requires an absolute address. We convert it to a b
5516 if (mips_pic == NO_PIC)
5517 macro_build (&offset_expr, "j", "a");
5519 macro_build (&offset_expr, "b", "p");
5522 /* The jal instructions must be handled as macros because when
5523 generating PIC code they expand to multi-instruction
5524 sequences. Normally they are simple instructions. */
5529 if (mips_pic == NO_PIC)
5530 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5531 else if (mips_pic == SVR4_PIC)
5533 if (sreg != PIC_CALL_REG)
5534 as_warn (_("MIPS PIC call to register other than $25"));
5536 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5539 if (mips_cprestore_offset < 0)
5540 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5543 if (! mips_frame_reg_valid)
5545 as_warn (_("No .frame pseudo-op used in PIC code"));
5546 /* Quiet this warning. */
5547 mips_frame_reg_valid = 1;
5549 if (! mips_cprestore_valid)
5551 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5552 /* Quiet this warning. */
5553 mips_cprestore_valid = 1;
5555 expr1.X_add_number = mips_cprestore_offset;
5556 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5559 HAVE_64BIT_ADDRESSES);
5569 if (mips_pic == NO_PIC)
5570 macro_build (&offset_expr, "jal", "a");
5571 else if (mips_pic == SVR4_PIC)
5573 /* If this is a reference to an external symbol, and we are
5574 using a small GOT, we want
5575 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5579 lw $gp,cprestore($sp)
5580 The cprestore value is set using the .cprestore
5581 pseudo-op. If we are using a big GOT, we want
5582 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5584 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5588 lw $gp,cprestore($sp)
5589 If the symbol is not external, we want
5590 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5592 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5595 lw $gp,cprestore($sp)
5597 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5598 sequences above, minus nops, unless the symbol is local,
5599 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5605 relax_start (offset_expr.X_add_symbol);
5606 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5607 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5610 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5611 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5617 relax_start (offset_expr.X_add_symbol);
5618 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5619 BFD_RELOC_MIPS_CALL_HI16);
5620 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5621 PIC_CALL_REG, mips_gp_register);
5622 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5623 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5626 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5627 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5629 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5630 PIC_CALL_REG, PIC_CALL_REG,
5631 BFD_RELOC_MIPS_GOT_OFST);
5635 macro_build_jalr (&offset_expr);
5639 relax_start (offset_expr.X_add_symbol);
5642 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5643 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5652 gpdelay = reg_needs_delay (mips_gp_register);
5653 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5654 BFD_RELOC_MIPS_CALL_HI16);
5655 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5656 PIC_CALL_REG, mips_gp_register);
5657 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5658 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5663 macro_build (NULL, "nop", "");
5665 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5666 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5669 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5670 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5672 macro_build_jalr (&offset_expr);
5674 if (mips_cprestore_offset < 0)
5675 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5678 if (! mips_frame_reg_valid)
5680 as_warn (_("No .frame pseudo-op used in PIC code"));
5681 /* Quiet this warning. */
5682 mips_frame_reg_valid = 1;
5684 if (! mips_cprestore_valid)
5686 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5687 /* Quiet this warning. */
5688 mips_cprestore_valid = 1;
5690 if (mips_opts.noreorder)
5691 macro_build (NULL, "nop", "");
5692 expr1.X_add_number = mips_cprestore_offset;
5693 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5696 HAVE_64BIT_ADDRESSES);
5722 /* Itbl support may require additional care here. */
5727 /* Itbl support may require additional care here. */
5732 /* Itbl support may require additional care here. */
5737 /* Itbl support may require additional care here. */
5749 if (mips_opts.arch == CPU_R4650)
5751 as_bad (_("opcode not supported on this processor"));
5755 /* Itbl support may require additional care here. */
5760 /* Itbl support may require additional care here. */
5765 /* Itbl support may require additional care here. */
5785 if (breg == treg || coproc || lr)
5806 /* Itbl support may require additional care here. */
5811 /* Itbl support may require additional care here. */
5816 /* Itbl support may require additional care here. */
5821 /* Itbl support may require additional care here. */
5837 if (mips_opts.arch == CPU_R4650)
5839 as_bad (_("opcode not supported on this processor"));
5844 /* Itbl support may require additional care here. */
5848 /* Itbl support may require additional care here. */
5853 /* Itbl support may require additional care here. */
5865 /* Itbl support may require additional care here. */
5866 if (mask == M_LWC1_AB
5867 || mask == M_SWC1_AB
5868 || mask == M_LDC1_AB
5869 || mask == M_SDC1_AB
5878 if (offset_expr.X_op != O_constant
5879 && offset_expr.X_op != O_symbol)
5881 as_bad (_("expression too complex"));
5882 offset_expr.X_op = O_constant;
5885 /* A constant expression in PIC code can be handled just as it
5886 is in non PIC code. */
5887 if (offset_expr.X_op == O_constant)
5889 if (HAVE_32BIT_ADDRESSES
5890 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5891 as_bad (_("constant too large"));
5893 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
5894 & ~(bfd_vma) 0xffff);
5895 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
5897 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5898 tempreg, tempreg, breg);
5899 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
5901 else if (mips_pic == NO_PIC)
5903 /* If this is a reference to a GP relative symbol, and there
5904 is no base register, we want
5905 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5906 Otherwise, if there is no base register, we want
5907 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5908 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5909 If we have a constant, we need two instructions anyhow,
5910 so we always use the latter form.
5912 If we have a base register, and this is a reference to a
5913 GP relative symbol, we want
5914 addu $tempreg,$breg,$gp
5915 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5917 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5918 addu $tempreg,$tempreg,$breg
5919 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5920 With a constant we always use the latter case.
5922 With 64bit address space and no base register and $at usable,
5924 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5925 lui $at,<sym> (BFD_RELOC_HI16_S)
5926 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5929 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5930 If we have a base register, we want
5931 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5932 lui $at,<sym> (BFD_RELOC_HI16_S)
5933 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5937 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5939 Without $at we can't generate the optimal path for superscalar
5940 processors here since this would require two temporary registers.
5941 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5942 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5944 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5946 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5947 If we have a base register, we want
5948 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5949 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5951 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5953 daddu $tempreg,$tempreg,$breg
5954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5956 For GP relative symbols in 64bit address space we can use
5957 the same sequence as in 32bit address space. */
5958 if (HAVE_64BIT_SYMBOLS)
5960 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5961 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5963 relax_start (offset_expr.X_add_symbol);
5966 macro_build (&offset_expr, s, fmt, treg,
5967 BFD_RELOC_GPREL16, mips_gp_register);
5971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5972 tempreg, breg, mips_gp_register);
5973 macro_build (&offset_expr, s, fmt, treg,
5974 BFD_RELOC_GPREL16, tempreg);
5979 if (used_at == 0 && !mips_opts.noat)
5981 macro_build (&offset_expr, "lui", "t,u", tempreg,
5982 BFD_RELOC_MIPS_HIGHEST);
5983 macro_build (&offset_expr, "lui", "t,u", AT,
5985 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5986 tempreg, BFD_RELOC_MIPS_HIGHER);
5988 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
5989 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5990 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5991 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
5997 macro_build (&offset_expr, "lui", "t,u", tempreg,
5998 BFD_RELOC_MIPS_HIGHEST);
5999 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6000 tempreg, BFD_RELOC_MIPS_HIGHER);
6001 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6002 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6003 tempreg, BFD_RELOC_HI16_S);
6004 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6006 macro_build (NULL, "daddu", "d,v,t",
6007 tempreg, tempreg, breg);
6008 macro_build (&offset_expr, s, fmt, treg,
6009 BFD_RELOC_LO16, tempreg);
6012 if (mips_relax.sequence)
6019 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6020 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6022 relax_start (offset_expr.X_add_symbol);
6023 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6027 macro_build_lui (&offset_expr, tempreg);
6028 macro_build (&offset_expr, s, fmt, treg,
6029 BFD_RELOC_LO16, tempreg);
6030 if (mips_relax.sequence)
6035 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6036 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6038 relax_start (offset_expr.X_add_symbol);
6039 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6040 tempreg, breg, mips_gp_register);
6041 macro_build (&offset_expr, s, fmt, treg,
6042 BFD_RELOC_GPREL16, tempreg);
6045 macro_build_lui (&offset_expr, tempreg);
6046 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6047 tempreg, tempreg, breg);
6048 macro_build (&offset_expr, s, fmt, treg,
6049 BFD_RELOC_LO16, tempreg);
6050 if (mips_relax.sequence)
6054 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6056 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6058 /* If this is a reference to an external symbol, we want
6059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6061 <op> $treg,0($tempreg)
6063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6065 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6066 <op> $treg,0($tempreg)
6069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6070 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6072 If there is a base register, we add it to $tempreg before
6073 the <op>. If there is a constant, we stick it in the
6074 <op> instruction. We don't handle constants larger than
6075 16 bits, because we have no way to load the upper 16 bits
6076 (actually, we could handle them for the subset of cases
6077 in which we are not using $at). */
6078 assert (offset_expr.X_op == O_symbol);
6081 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6082 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6084 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6085 tempreg, tempreg, breg);
6086 macro_build (&offset_expr, s, fmt, treg,
6087 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6090 expr1.X_add_number = offset_expr.X_add_number;
6091 offset_expr.X_add_number = 0;
6092 if (expr1.X_add_number < -0x8000
6093 || expr1.X_add_number >= 0x8000)
6094 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6095 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6096 lw_reloc_type, mips_gp_register);
6098 relax_start (offset_expr.X_add_symbol);
6100 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6101 tempreg, BFD_RELOC_LO16);
6104 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6105 tempreg, tempreg, breg);
6106 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6108 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6112 /* If this is a reference to an external symbol, we want
6113 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6114 addu $tempreg,$tempreg,$gp
6115 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6116 <op> $treg,0($tempreg)
6118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6120 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6121 <op> $treg,0($tempreg)
6122 If there is a base register, we add it to $tempreg before
6123 the <op>. If there is a constant, we stick it in the
6124 <op> instruction. We don't handle constants larger than
6125 16 bits, because we have no way to load the upper 16 bits
6126 (actually, we could handle them for the subset of cases
6127 in which we are not using $at). */
6128 assert (offset_expr.X_op == O_symbol);
6129 expr1.X_add_number = offset_expr.X_add_number;
6130 offset_expr.X_add_number = 0;
6131 if (expr1.X_add_number < -0x8000
6132 || expr1.X_add_number >= 0x8000)
6133 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6134 gpdelay = reg_needs_delay (mips_gp_register);
6135 relax_start (offset_expr.X_add_symbol);
6136 macro_build (&offset_expr, "lui", "t,u", tempreg,
6137 BFD_RELOC_MIPS_GOT_HI16);
6138 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6140 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6141 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6144 macro_build (NULL, "nop", "");
6145 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6146 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6148 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6149 tempreg, BFD_RELOC_LO16);
6153 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6154 tempreg, tempreg, breg);
6155 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6157 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6159 /* If this is a reference to an external symbol, we want
6160 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6161 add $tempreg,$tempreg,$gp
6162 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6163 <op> $treg,<ofst>($tempreg)
6164 Otherwise, for local symbols, we want:
6165 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6166 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6167 assert (offset_expr.X_op == O_symbol);
6168 expr1.X_add_number = offset_expr.X_add_number;
6169 offset_expr.X_add_number = 0;
6170 if (expr1.X_add_number < -0x8000
6171 || expr1.X_add_number >= 0x8000)
6172 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6173 relax_start (offset_expr.X_add_symbol);
6174 macro_build (&offset_expr, "lui", "t,u", tempreg,
6175 BFD_RELOC_MIPS_GOT_HI16);
6176 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6178 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6179 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6181 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6182 tempreg, tempreg, breg);
6183 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6186 offset_expr.X_add_number = expr1.X_add_number;
6187 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6188 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6191 tempreg, tempreg, breg);
6192 macro_build (&offset_expr, s, fmt, treg,
6193 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6203 load_register (treg, &imm_expr, 0);
6207 load_register (treg, &imm_expr, 1);
6211 if (imm_expr.X_op == O_constant)
6214 load_register (AT, &imm_expr, 0);
6215 macro_build (NULL, "mtc1", "t,G", AT, treg);
6220 assert (offset_expr.X_op == O_symbol
6221 && strcmp (segment_name (S_GET_SEGMENT
6222 (offset_expr.X_add_symbol)),
6224 && offset_expr.X_add_number == 0);
6225 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6226 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6231 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6232 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6233 order 32 bits of the value and the low order 32 bits are either
6234 zero or in OFFSET_EXPR. */
6235 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6237 if (HAVE_64BIT_GPRS)
6238 load_register (treg, &imm_expr, 1);
6243 if (target_big_endian)
6255 load_register (hreg, &imm_expr, 0);
6258 if (offset_expr.X_op == O_absent)
6259 move_register (lreg, 0);
6262 assert (offset_expr.X_op == O_constant);
6263 load_register (lreg, &offset_expr, 0);
6270 /* We know that sym is in the .rdata section. First we get the
6271 upper 16 bits of the address. */
6272 if (mips_pic == NO_PIC)
6274 macro_build_lui (&offset_expr, AT);
6277 else if (mips_pic == SVR4_PIC)
6279 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6280 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6286 /* Now we load the register(s). */
6287 if (HAVE_64BIT_GPRS)
6290 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6295 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6298 /* FIXME: How in the world do we deal with the possible
6300 offset_expr.X_add_number += 4;
6301 macro_build (&offset_expr, "lw", "t,o(b)",
6302 treg + 1, BFD_RELOC_LO16, AT);
6308 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6309 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6310 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6311 the value and the low order 32 bits are either zero or in
6313 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6316 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6317 if (HAVE_64BIT_FPRS)
6319 assert (HAVE_64BIT_GPRS);
6320 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6324 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6325 if (offset_expr.X_op == O_absent)
6326 macro_build (NULL, "mtc1", "t,G", 0, treg);
6329 assert (offset_expr.X_op == O_constant);
6330 load_register (AT, &offset_expr, 0);
6331 macro_build (NULL, "mtc1", "t,G", AT, treg);
6337 assert (offset_expr.X_op == O_symbol
6338 && offset_expr.X_add_number == 0);
6339 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6340 if (strcmp (s, ".lit8") == 0)
6342 if (mips_opts.isa != ISA_MIPS1)
6344 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6345 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6348 breg = mips_gp_register;
6349 r = BFD_RELOC_MIPS_LITERAL;
6354 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6356 if (mips_pic == SVR4_PIC)
6357 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6358 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6361 /* FIXME: This won't work for a 64 bit address. */
6362 macro_build_lui (&offset_expr, AT);
6365 if (mips_opts.isa != ISA_MIPS1)
6367 macro_build (&offset_expr, "ldc1", "T,o(b)",
6368 treg, BFD_RELOC_LO16, AT);
6377 if (mips_opts.arch == CPU_R4650)
6379 as_bad (_("opcode not supported on this processor"));
6382 /* Even on a big endian machine $fn comes before $fn+1. We have
6383 to adjust when loading from memory. */
6386 assert (mips_opts.isa == ISA_MIPS1);
6387 macro_build (&offset_expr, "lwc1", "T,o(b)",
6388 target_big_endian ? treg + 1 : treg, r, breg);
6389 /* FIXME: A possible overflow which I don't know how to deal
6391 offset_expr.X_add_number += 4;
6392 macro_build (&offset_expr, "lwc1", "T,o(b)",
6393 target_big_endian ? treg : treg + 1, r, breg);
6398 * The MIPS assembler seems to check for X_add_number not
6399 * being double aligned and generating:
6402 * addiu at,at,%lo(foo+1)
6405 * But, the resulting address is the same after relocation so why
6406 * generate the extra instruction?
6408 if (mips_opts.arch == CPU_R4650)
6410 as_bad (_("opcode not supported on this processor"));
6413 /* Itbl support may require additional care here. */
6415 if (mips_opts.isa != ISA_MIPS1)
6426 if (mips_opts.arch == CPU_R4650)
6428 as_bad (_("opcode not supported on this processor"));
6432 if (mips_opts.isa != ISA_MIPS1)
6440 /* Itbl support may require additional care here. */
6445 if (HAVE_64BIT_GPRS)
6456 if (HAVE_64BIT_GPRS)
6466 if (offset_expr.X_op != O_symbol
6467 && offset_expr.X_op != O_constant)
6469 as_bad (_("expression too complex"));
6470 offset_expr.X_op = O_constant;
6473 /* Even on a big endian machine $fn comes before $fn+1. We have
6474 to adjust when loading from memory. We set coproc if we must
6475 load $fn+1 first. */
6476 /* Itbl support may require additional care here. */
6477 if (! target_big_endian)
6480 if (mips_pic == NO_PIC
6481 || offset_expr.X_op == O_constant)
6483 /* If this is a reference to a GP relative symbol, we want
6484 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6485 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6486 If we have a base register, we use this
6488 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6489 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6490 If this is not a GP relative symbol, we want
6491 lui $at,<sym> (BFD_RELOC_HI16_S)
6492 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6493 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6494 If there is a base register, we add it to $at after the
6495 lui instruction. If there is a constant, we always use
6497 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6498 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6500 relax_start (offset_expr.X_add_symbol);
6503 tempreg = mips_gp_register;
6507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6508 AT, breg, mips_gp_register);
6513 /* Itbl support may require additional care here. */
6514 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6515 BFD_RELOC_GPREL16, tempreg);
6516 offset_expr.X_add_number += 4;
6518 /* Set mips_optimize to 2 to avoid inserting an
6520 hold_mips_optimize = mips_optimize;
6522 /* Itbl support may require additional care here. */
6523 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6524 BFD_RELOC_GPREL16, tempreg);
6525 mips_optimize = hold_mips_optimize;
6529 /* We just generated two relocs. When tc_gen_reloc
6530 handles this case, it will skip the first reloc and
6531 handle the second. The second reloc already has an
6532 extra addend of 4, which we added above. We must
6533 subtract it out, and then subtract another 4 to make
6534 the first reloc come out right. The second reloc
6535 will come out right because we are going to add 4 to
6536 offset_expr when we build its instruction below.
6538 If we have a symbol, then we don't want to include
6539 the offset, because it will wind up being included
6540 when we generate the reloc. */
6542 if (offset_expr.X_op == O_constant)
6543 offset_expr.X_add_number -= 8;
6546 offset_expr.X_add_number = -4;
6547 offset_expr.X_op = O_constant;
6551 macro_build_lui (&offset_expr, AT);
6553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6554 /* Itbl support may require additional care here. */
6555 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6556 BFD_RELOC_LO16, AT);
6557 /* FIXME: How do we handle overflow here? */
6558 offset_expr.X_add_number += 4;
6559 /* Itbl support may require additional care here. */
6560 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6561 BFD_RELOC_LO16, AT);
6562 if (mips_relax.sequence)
6565 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6567 /* If this is a reference to an external symbol, we want
6568 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6573 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6575 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6576 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6577 If there is a base register we add it to $at before the
6578 lwc1 instructions. If there is a constant we include it
6579 in the lwc1 instructions. */
6581 expr1.X_add_number = offset_expr.X_add_number;
6582 if (expr1.X_add_number < -0x8000
6583 || expr1.X_add_number >= 0x8000 - 4)
6584 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6585 load_got_offset (AT, &offset_expr);
6588 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6590 /* Set mips_optimize to 2 to avoid inserting an undesired
6592 hold_mips_optimize = mips_optimize;
6595 /* Itbl support may require additional care here. */
6596 relax_start (offset_expr.X_add_symbol);
6597 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6598 BFD_RELOC_LO16, AT);
6599 expr1.X_add_number += 4;
6600 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6601 BFD_RELOC_LO16, AT);
6603 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6604 BFD_RELOC_LO16, AT);
6605 offset_expr.X_add_number += 4;
6606 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6607 BFD_RELOC_LO16, AT);
6610 mips_optimize = hold_mips_optimize;
6612 else if (mips_pic == SVR4_PIC)
6616 /* If this is a reference to an external symbol, we want
6617 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6619 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6624 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6626 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6627 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6628 If there is a base register we add it to $at before the
6629 lwc1 instructions. If there is a constant we include it
6630 in the lwc1 instructions. */
6632 expr1.X_add_number = offset_expr.X_add_number;
6633 offset_expr.X_add_number = 0;
6634 if (expr1.X_add_number < -0x8000
6635 || expr1.X_add_number >= 0x8000 - 4)
6636 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6637 gpdelay = reg_needs_delay (mips_gp_register);
6638 relax_start (offset_expr.X_add_symbol);
6639 macro_build (&offset_expr, "lui", "t,u",
6640 AT, BFD_RELOC_MIPS_GOT_HI16);
6641 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6642 AT, AT, mips_gp_register);
6643 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6644 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6647 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6648 /* Itbl support may require additional care here. */
6649 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6650 BFD_RELOC_LO16, AT);
6651 expr1.X_add_number += 4;
6653 /* Set mips_optimize to 2 to avoid inserting an undesired
6655 hold_mips_optimize = mips_optimize;
6657 /* Itbl support may require additional care here. */
6658 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6659 BFD_RELOC_LO16, AT);
6660 mips_optimize = hold_mips_optimize;
6661 expr1.X_add_number -= 4;
6664 offset_expr.X_add_number = expr1.X_add_number;
6666 macro_build (NULL, "nop", "");
6667 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6668 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6671 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6672 /* Itbl support may require additional care here. */
6673 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6674 BFD_RELOC_LO16, AT);
6675 offset_expr.X_add_number += 4;
6677 /* Set mips_optimize to 2 to avoid inserting an undesired
6679 hold_mips_optimize = mips_optimize;
6681 /* Itbl support may require additional care here. */
6682 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6683 BFD_RELOC_LO16, AT);
6684 mips_optimize = hold_mips_optimize;
6698 assert (HAVE_32BIT_ADDRESSES);
6699 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6700 offset_expr.X_add_number += 4;
6701 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6704 /* New code added to support COPZ instructions.
6705 This code builds table entries out of the macros in mip_opcodes.
6706 R4000 uses interlocks to handle coproc delays.
6707 Other chips (like the R3000) require nops to be inserted for delays.
6709 FIXME: Currently, we require that the user handle delays.
6710 In order to fill delay slots for non-interlocked chips,
6711 we must have a way to specify delays based on the coprocessor.
6712 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6713 What are the side-effects of the cop instruction?
6714 What cache support might we have and what are its effects?
6715 Both coprocessor & memory require delays. how long???
6716 What registers are read/set/modified?
6718 If an itbl is provided to interpret cop instructions,
6719 this knowledge can be encoded in the itbl spec. */
6733 /* For now we just do C (same as Cz). The parameter will be
6734 stored in insn_opcode by mips_ip. */
6735 macro_build (NULL, s, "C", ip->insn_opcode);
6739 move_register (dreg, sreg);
6742 #ifdef LOSING_COMPILER
6744 /* Try and see if this is a new itbl instruction.
6745 This code builds table entries out of the macros in mip_opcodes.
6746 FIXME: For now we just assemble the expression and pass it's
6747 value along as a 32-bit immediate.
6748 We may want to have the assembler assemble this value,
6749 so that we gain the assembler's knowledge of delay slots,
6751 Would it be more efficient to use mask (id) here? */
6752 if (itbl_have_entries
6753 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6755 s = ip->insn_mo->name;
6757 coproc = ITBL_DECODE_PNUM (immed_expr);;
6758 macro_build (&immed_expr, s, "C");
6764 if (mips_opts.noat && used_at)
6765 as_bad (_("Macro used $at after \".set noat\""));
6769 macro2 (struct mips_cl_insn *ip)
6771 register int treg, sreg, dreg, breg;
6786 bfd_reloc_code_real_type r;
6788 treg = (ip->insn_opcode >> 16) & 0x1f;
6789 dreg = (ip->insn_opcode >> 11) & 0x1f;
6790 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6791 mask = ip->insn_mo->mask;
6793 expr1.X_op = O_constant;
6794 expr1.X_op_symbol = NULL;
6795 expr1.X_add_symbol = NULL;
6796 expr1.X_add_number = 1;
6800 #endif /* LOSING_COMPILER */
6805 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6806 macro_build (NULL, "mflo", "d", dreg);
6812 /* The MIPS assembler some times generates shifts and adds. I'm
6813 not trying to be that fancy. GCC should do this for us
6816 load_register (AT, &imm_expr, dbl);
6817 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6818 macro_build (NULL, "mflo", "d", dreg);
6831 mips_emit_delays (TRUE);
6832 ++mips_opts.noreorder;
6833 mips_any_noreorder = 1;
6836 load_register (AT, &imm_expr, dbl);
6837 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6838 macro_build (NULL, "mflo", "d", dreg);
6839 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6840 macro_build (NULL, "mfhi", "d", AT);
6842 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6845 expr1.X_add_number = 8;
6846 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6847 macro_build (NULL, "nop", "", 0);
6848 macro_build (NULL, "break", "c", 6);
6850 --mips_opts.noreorder;
6851 macro_build (NULL, "mflo", "d", dreg);
6864 mips_emit_delays (TRUE);
6865 ++mips_opts.noreorder;
6866 mips_any_noreorder = 1;
6869 load_register (AT, &imm_expr, dbl);
6870 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6871 sreg, imm ? AT : treg);
6872 macro_build (NULL, "mfhi", "d", AT);
6873 macro_build (NULL, "mflo", "d", dreg);
6875 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6878 expr1.X_add_number = 8;
6879 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6880 macro_build (NULL, "nop", "", 0);
6881 macro_build (NULL, "break", "c", 6);
6883 --mips_opts.noreorder;
6887 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6898 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6899 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6903 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6904 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6905 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6906 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6910 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6921 macro_build (NULL, "negu", "d,w", tempreg, treg);
6922 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6926 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6927 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6928 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6929 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6937 if (imm_expr.X_op != O_constant)
6938 as_bad (_("Improper rotate count"));
6939 rot = imm_expr.X_add_number & 0x3f;
6940 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6942 rot = (64 - rot) & 0x3f;
6944 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6946 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6951 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
6954 l = (rot < 0x20) ? "dsll" : "dsll32";
6955 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6958 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
6959 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6960 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6968 if (imm_expr.X_op != O_constant)
6969 as_bad (_("Improper rotate count"));
6970 rot = imm_expr.X_add_number & 0x1f;
6971 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6973 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6978 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
6982 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
6983 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6984 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6989 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6991 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
6995 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6996 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
6997 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
6998 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7002 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7004 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7008 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7009 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7010 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7011 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7019 if (imm_expr.X_op != O_constant)
7020 as_bad (_("Improper rotate count"));
7021 rot = imm_expr.X_add_number & 0x3f;
7022 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7025 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7027 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7032 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7035 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7036 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7039 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7040 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7041 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7049 if (imm_expr.X_op != O_constant)
7050 as_bad (_("Improper rotate count"));
7051 rot = imm_expr.X_add_number & 0x1f;
7052 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7054 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7059 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7063 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7064 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7065 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7070 if (mips_opts.arch == CPU_R4650)
7072 as_bad (_("opcode not supported on this processor"));
7075 assert (mips_opts.isa == ISA_MIPS1);
7076 /* Even on a big endian machine $fn comes before $fn+1. We have
7077 to adjust when storing to memory. */
7078 macro_build (&offset_expr, "swc1", "T,o(b)",
7079 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7080 offset_expr.X_add_number += 4;
7081 macro_build (&offset_expr, "swc1", "T,o(b)",
7082 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7087 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7089 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7092 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7093 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7098 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7100 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7105 as_warn (_("Instruction %s: result is always false"),
7107 move_register (dreg, 0);
7110 if (imm_expr.X_op == O_constant
7111 && imm_expr.X_add_number >= 0
7112 && imm_expr.X_add_number < 0x10000)
7114 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7116 else if (imm_expr.X_op == O_constant
7117 && imm_expr.X_add_number > -0x8000
7118 && imm_expr.X_add_number < 0)
7120 imm_expr.X_add_number = -imm_expr.X_add_number;
7121 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7122 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7126 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7127 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7130 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7133 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7139 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7140 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7143 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7145 if (imm_expr.X_op == O_constant
7146 && imm_expr.X_add_number >= -0x8000
7147 && imm_expr.X_add_number < 0x8000)
7149 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7150 dreg, sreg, BFD_RELOC_LO16);
7154 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7155 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7159 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7162 case M_SGT: /* sreg > treg <==> treg < sreg */
7168 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7171 case M_SGT_I: /* sreg > I <==> I < sreg */
7178 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7179 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7182 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7188 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7189 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7192 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7199 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7200 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7201 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7205 if (imm_expr.X_op == O_constant
7206 && imm_expr.X_add_number >= -0x8000
7207 && imm_expr.X_add_number < 0x8000)
7209 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7213 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7214 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7218 if (imm_expr.X_op == O_constant
7219 && imm_expr.X_add_number >= -0x8000
7220 && imm_expr.X_add_number < 0x8000)
7222 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7227 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7228 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7233 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7235 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7238 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7239 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7244 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7246 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7251 as_warn (_("Instruction %s: result is always true"),
7253 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7254 dreg, 0, BFD_RELOC_LO16);
7257 if (imm_expr.X_op == O_constant
7258 && imm_expr.X_add_number >= 0
7259 && imm_expr.X_add_number < 0x10000)
7261 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7263 else if (imm_expr.X_op == O_constant
7264 && imm_expr.X_add_number > -0x8000
7265 && imm_expr.X_add_number < 0)
7267 imm_expr.X_add_number = -imm_expr.X_add_number;
7268 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7269 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7273 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7274 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7277 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7283 if (imm_expr.X_op == O_constant
7284 && imm_expr.X_add_number > -0x8000
7285 && imm_expr.X_add_number <= 0x8000)
7287 imm_expr.X_add_number = -imm_expr.X_add_number;
7288 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7289 dreg, sreg, BFD_RELOC_LO16);
7293 load_register (AT, &imm_expr, dbl);
7294 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7300 if (imm_expr.X_op == O_constant
7301 && imm_expr.X_add_number > -0x8000
7302 && imm_expr.X_add_number <= 0x8000)
7304 imm_expr.X_add_number = -imm_expr.X_add_number;
7305 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7306 dreg, sreg, BFD_RELOC_LO16);
7310 load_register (AT, &imm_expr, dbl);
7311 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7333 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7334 macro_build (NULL, s, "s,t", sreg, AT);
7339 assert (mips_opts.isa == ISA_MIPS1);
7341 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7342 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7345 * Is the double cfc1 instruction a bug in the mips assembler;
7346 * or is there a reason for it?
7348 mips_emit_delays (TRUE);
7349 ++mips_opts.noreorder;
7350 mips_any_noreorder = 1;
7351 macro_build (NULL, "cfc1", "t,G", treg, RA);
7352 macro_build (NULL, "cfc1", "t,G", treg, RA);
7353 macro_build (NULL, "nop", "");
7354 expr1.X_add_number = 3;
7355 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7356 expr1.X_add_number = 2;
7357 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7358 macro_build (NULL, "ctc1", "t,G", AT, RA);
7359 macro_build (NULL, "nop", "");
7360 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7362 macro_build (NULL, "ctc1", "t,G", treg, RA);
7363 macro_build (NULL, "nop", "");
7364 --mips_opts.noreorder;
7374 if (offset_expr.X_add_number >= 0x7fff)
7375 as_bad (_("operand overflow"));
7376 if (! target_big_endian)
7377 ++offset_expr.X_add_number;
7378 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7379 if (! target_big_endian)
7380 --offset_expr.X_add_number;
7382 ++offset_expr.X_add_number;
7383 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7384 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7385 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7398 if (offset_expr.X_add_number >= 0x8000 - off)
7399 as_bad (_("operand overflow"));
7407 if (! target_big_endian)
7408 offset_expr.X_add_number += off;
7409 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7410 if (! target_big_endian)
7411 offset_expr.X_add_number -= off;
7413 offset_expr.X_add_number += off;
7414 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7416 /* If necessary, move the result in tempreg the final destination. */
7417 if (treg == tempreg)
7419 /* Protect second load's delay slot. */
7421 move_register (treg, tempreg);
7435 load_address (AT, &offset_expr, &used_at);
7437 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7438 if (! target_big_endian)
7439 expr1.X_add_number = off;
7441 expr1.X_add_number = 0;
7442 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7443 if (! target_big_endian)
7444 expr1.X_add_number = 0;
7446 expr1.X_add_number = off;
7447 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7453 load_address (AT, &offset_expr, &used_at);
7455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7456 if (target_big_endian)
7457 expr1.X_add_number = 0;
7458 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7459 treg, BFD_RELOC_LO16, AT);
7460 if (target_big_endian)
7461 expr1.X_add_number = 1;
7463 expr1.X_add_number = 0;
7464 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7465 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7466 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7471 if (offset_expr.X_add_number >= 0x7fff)
7472 as_bad (_("operand overflow"));
7473 if (target_big_endian)
7474 ++offset_expr.X_add_number;
7475 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7476 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7477 if (target_big_endian)
7478 --offset_expr.X_add_number;
7480 ++offset_expr.X_add_number;
7481 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7494 if (offset_expr.X_add_number >= 0x8000 - off)
7495 as_bad (_("operand overflow"));
7496 if (! target_big_endian)
7497 offset_expr.X_add_number += off;
7498 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7499 if (! target_big_endian)
7500 offset_expr.X_add_number -= off;
7502 offset_expr.X_add_number += off;
7503 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7517 load_address (AT, &offset_expr, &used_at);
7519 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7520 if (! target_big_endian)
7521 expr1.X_add_number = off;
7523 expr1.X_add_number = 0;
7524 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7525 if (! target_big_endian)
7526 expr1.X_add_number = 0;
7528 expr1.X_add_number = off;
7529 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7534 load_address (AT, &offset_expr, &used_at);
7536 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7537 if (! target_big_endian)
7538 expr1.X_add_number = 0;
7539 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7540 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7541 if (! target_big_endian)
7542 expr1.X_add_number = 1;
7544 expr1.X_add_number = 0;
7545 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7546 if (! target_big_endian)
7547 expr1.X_add_number = 0;
7549 expr1.X_add_number = 1;
7550 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7551 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7552 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7556 /* FIXME: Check if this is one of the itbl macros, since they
7557 are added dynamically. */
7558 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7561 if (mips_opts.noat && used_at)
7562 as_bad (_("Macro used $at after \".set noat\""));
7565 /* Implement macros in mips16 mode. */
7568 mips16_macro (struct mips_cl_insn *ip)
7571 int xreg, yreg, zreg, tmp;
7574 const char *s, *s2, *s3;
7576 mask = ip->insn_mo->mask;
7578 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7579 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7580 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7582 expr1.X_op = O_constant;
7583 expr1.X_op_symbol = NULL;
7584 expr1.X_add_symbol = NULL;
7585 expr1.X_add_number = 1;
7604 mips_emit_delays (TRUE);
7605 ++mips_opts.noreorder;
7606 mips_any_noreorder = 1;
7607 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7608 expr1.X_add_number = 2;
7609 macro_build (&expr1, "bnez", "x,p", yreg);
7610 macro_build (NULL, "break", "6", 7);
7612 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7613 since that causes an overflow. We should do that as well,
7614 but I don't see how to do the comparisons without a temporary
7616 --mips_opts.noreorder;
7617 macro_build (NULL, s, "x", zreg);
7636 mips_emit_delays (TRUE);
7637 ++mips_opts.noreorder;
7638 mips_any_noreorder = 1;
7639 macro_build (NULL, s, "0,x,y", xreg, yreg);
7640 expr1.X_add_number = 2;
7641 macro_build (&expr1, "bnez", "x,p", yreg);
7642 macro_build (NULL, "break", "6", 7);
7643 --mips_opts.noreorder;
7644 macro_build (NULL, s2, "x", zreg);
7650 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7651 macro_build (NULL, "mflo", "x", zreg);
7659 if (imm_expr.X_op != O_constant)
7660 as_bad (_("Unsupported large constant"));
7661 imm_expr.X_add_number = -imm_expr.X_add_number;
7662 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7666 if (imm_expr.X_op != O_constant)
7667 as_bad (_("Unsupported large constant"));
7668 imm_expr.X_add_number = -imm_expr.X_add_number;
7669 macro_build (&imm_expr, "addiu", "x,k", xreg);
7673 if (imm_expr.X_op != O_constant)
7674 as_bad (_("Unsupported large constant"));
7675 imm_expr.X_add_number = -imm_expr.X_add_number;
7676 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7698 goto do_reverse_branch;
7702 goto do_reverse_branch;
7714 goto do_reverse_branch;
7725 macro_build (NULL, s, "x,y", xreg, yreg);
7726 macro_build (&offset_expr, s2, "p");
7753 goto do_addone_branch_i;
7758 goto do_addone_branch_i;
7773 goto do_addone_branch_i;
7780 if (imm_expr.X_op != O_constant)
7781 as_bad (_("Unsupported large constant"));
7782 ++imm_expr.X_add_number;
7785 macro_build (&imm_expr, s, s3, xreg);
7786 macro_build (&offset_expr, s2, "p");
7790 expr1.X_add_number = 0;
7791 macro_build (&expr1, "slti", "x,8", yreg);
7793 move_register (xreg, yreg);
7794 expr1.X_add_number = 2;
7795 macro_build (&expr1, "bteqz", "p");
7796 macro_build (NULL, "neg", "x,w", xreg, xreg);
7800 /* For consistency checking, verify that all bits are specified either
7801 by the match/mask part of the instruction definition, or by the
7804 validate_mips_insn (const struct mips_opcode *opc)
7806 const char *p = opc->args;
7808 unsigned long used_bits = opc->mask;
7810 if ((used_bits & opc->match) != opc->match)
7812 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7813 opc->name, opc->args);
7816 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7826 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7827 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7828 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7829 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7830 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7831 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7832 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7833 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7834 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7837 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7838 c, opc->name, opc->args);
7842 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7843 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7845 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7846 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7847 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7848 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7850 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7851 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7853 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7854 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7856 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7857 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7858 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7859 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7860 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7861 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7862 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7863 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7864 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7865 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7866 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7867 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7868 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7869 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7870 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7871 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7872 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7874 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7875 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7876 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7877 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7879 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7880 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7881 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7882 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7883 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7884 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7885 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7886 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7887 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7890 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7891 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7892 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7893 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7894 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7898 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7899 c, opc->name, opc->args);
7903 if (used_bits != 0xffffffff)
7905 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7906 ~used_bits & 0xffffffff, opc->name, opc->args);
7912 /* This routine assembles an instruction into its binary format. As a
7913 side effect, it sets one of the global variables imm_reloc or
7914 offset_reloc to the type of relocation to do if one of the operands
7915 is an address expression. */
7918 mips_ip (char *str, struct mips_cl_insn *ip)
7923 struct mips_opcode *insn;
7926 unsigned int lastregno = 0;
7927 unsigned int lastpos = 0;
7928 unsigned int limlo, limhi;
7934 /* If the instruction contains a '.', we first try to match an instruction
7935 including the '.'. Then we try again without the '.'. */
7937 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7940 /* If we stopped on whitespace, then replace the whitespace with null for
7941 the call to hash_find. Save the character we replaced just in case we
7942 have to re-parse the instruction. */
7949 insn = (struct mips_opcode *) hash_find (op_hash, str);
7951 /* If we didn't find the instruction in the opcode table, try again, but
7952 this time with just the instruction up to, but not including the
7956 /* Restore the character we overwrite above (if any). */
7960 /* Scan up to the first '.' or whitespace. */
7962 *s != '\0' && *s != '.' && !ISSPACE (*s);
7966 /* If we did not find a '.', then we can quit now. */
7969 insn_error = "unrecognized opcode";
7973 /* Lookup the instruction in the hash table. */
7975 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7977 insn_error = "unrecognized opcode";
7987 assert (strcmp (insn->name, str) == 0);
7989 if (OPCODE_IS_MEMBER (insn,
7991 | (file_ase_mips16 ? INSN_MIPS16 : 0)
7992 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7993 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7999 if (insn->pinfo != INSN_MACRO)
8001 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8007 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8008 && strcmp (insn->name, insn[1].name) == 0)
8017 static char buf[100];
8019 _("opcode not supported on this processor: %s (%s)"),
8020 mips_cpu_info_from_arch (mips_opts.arch)->name,
8021 mips_cpu_info_from_isa (mips_opts.isa)->name);
8031 ip->insn_opcode = insn->match;
8033 for (args = insn->args;; ++args)
8037 s += strspn (s, " \t");
8041 case '\0': /* end of args */
8054 ip->insn_opcode |= lastregno << OP_SH_RS;
8058 ip->insn_opcode |= lastregno << OP_SH_RT;
8062 ip->insn_opcode |= lastregno << OP_SH_FT;
8066 ip->insn_opcode |= lastregno << OP_SH_FS;
8072 /* Handle optional base register.
8073 Either the base register is omitted or
8074 we must have a left paren. */
8075 /* This is dependent on the next operand specifier
8076 is a base register specification. */
8077 assert (args[1] == 'b' || args[1] == '5'
8078 || args[1] == '-' || args[1] == '4');
8082 case ')': /* these must match exactly */
8089 case '+': /* Opcode extension character. */
8092 case 'A': /* ins/ext position, becomes LSB. */
8101 my_getExpression (&imm_expr, s);
8102 check_absolute_expr (ip, &imm_expr);
8103 if ((unsigned long) imm_expr.X_add_number < limlo
8104 || (unsigned long) imm_expr.X_add_number > limhi)
8106 as_bad (_("Improper position (%lu)"),
8107 (unsigned long) imm_expr.X_add_number);
8108 imm_expr.X_add_number = limlo;
8110 lastpos = imm_expr.X_add_number;
8111 ip->insn_opcode |= (imm_expr.X_add_number
8112 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8113 imm_expr.X_op = O_absent;
8117 case 'B': /* ins size, becomes MSB. */
8126 my_getExpression (&imm_expr, s);
8127 check_absolute_expr (ip, &imm_expr);
8128 /* Check for negative input so that small negative numbers
8129 will not succeed incorrectly. The checks against
8130 (pos+size) transitively check "size" itself,
8131 assuming that "pos" is reasonable. */
8132 if ((long) imm_expr.X_add_number < 0
8133 || ((unsigned long) imm_expr.X_add_number
8135 || ((unsigned long) imm_expr.X_add_number
8138 as_bad (_("Improper insert size (%lu, position %lu)"),
8139 (unsigned long) imm_expr.X_add_number,
8140 (unsigned long) lastpos);
8141 imm_expr.X_add_number = limlo - lastpos;
8143 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8144 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8145 imm_expr.X_op = O_absent;
8149 case 'C': /* ext size, becomes MSBD. */
8162 my_getExpression (&imm_expr, s);
8163 check_absolute_expr (ip, &imm_expr);
8164 /* Check for negative input so that small negative numbers
8165 will not succeed incorrectly. The checks against
8166 (pos+size) transitively check "size" itself,
8167 assuming that "pos" is reasonable. */
8168 if ((long) imm_expr.X_add_number < 0
8169 || ((unsigned long) imm_expr.X_add_number
8171 || ((unsigned long) imm_expr.X_add_number
8174 as_bad (_("Improper extract size (%lu, position %lu)"),
8175 (unsigned long) imm_expr.X_add_number,
8176 (unsigned long) lastpos);
8177 imm_expr.X_add_number = limlo - lastpos;
8179 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8180 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8181 imm_expr.X_op = O_absent;
8186 /* +D is for disassembly only; never match. */
8190 /* "+I" is like "I", except that imm2_expr is used. */
8191 my_getExpression (&imm2_expr, s);
8192 if (imm2_expr.X_op != O_big
8193 && imm2_expr.X_op != O_constant)
8194 insn_error = _("absolute expression required");
8195 normalize_constant_expr (&imm2_expr);
8200 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8201 *args, insn->name, insn->args);
8202 /* Further processing is fruitless. */
8207 case '<': /* must be at least one digit */
8209 * According to the manual, if the shift amount is greater
8210 * than 31 or less than 0, then the shift amount should be
8211 * mod 32. In reality the mips assembler issues an error.
8212 * We issue a warning and mask out all but the low 5 bits.
8214 my_getExpression (&imm_expr, s);
8215 check_absolute_expr (ip, &imm_expr);
8216 if ((unsigned long) imm_expr.X_add_number > 31)
8218 as_warn (_("Improper shift amount (%lu)"),
8219 (unsigned long) imm_expr.X_add_number);
8220 imm_expr.X_add_number &= OP_MASK_SHAMT;
8222 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8223 imm_expr.X_op = O_absent;
8227 case '>': /* shift amount minus 32 */
8228 my_getExpression (&imm_expr, s);
8229 check_absolute_expr (ip, &imm_expr);
8230 if ((unsigned long) imm_expr.X_add_number < 32
8231 || (unsigned long) imm_expr.X_add_number > 63)
8233 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8234 imm_expr.X_op = O_absent;
8238 case 'k': /* cache code */
8239 case 'h': /* prefx code */
8240 my_getExpression (&imm_expr, s);
8241 check_absolute_expr (ip, &imm_expr);
8242 if ((unsigned long) imm_expr.X_add_number > 31)
8244 as_warn (_("Invalid value for `%s' (%lu)"),
8246 (unsigned long) imm_expr.X_add_number);
8247 imm_expr.X_add_number &= 0x1f;
8250 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8252 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8253 imm_expr.X_op = O_absent;
8257 case 'c': /* break code */
8258 my_getExpression (&imm_expr, s);
8259 check_absolute_expr (ip, &imm_expr);
8260 if ((unsigned long) imm_expr.X_add_number > 1023)
8262 as_warn (_("Illegal break code (%lu)"),
8263 (unsigned long) imm_expr.X_add_number);
8264 imm_expr.X_add_number &= OP_MASK_CODE;
8266 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8267 imm_expr.X_op = O_absent;
8271 case 'q': /* lower break code */
8272 my_getExpression (&imm_expr, s);
8273 check_absolute_expr (ip, &imm_expr);
8274 if ((unsigned long) imm_expr.X_add_number > 1023)
8276 as_warn (_("Illegal lower break code (%lu)"),
8277 (unsigned long) imm_expr.X_add_number);
8278 imm_expr.X_add_number &= OP_MASK_CODE2;
8280 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8281 imm_expr.X_op = O_absent;
8285 case 'B': /* 20-bit syscall/break code. */
8286 my_getExpression (&imm_expr, s);
8287 check_absolute_expr (ip, &imm_expr);
8288 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8289 as_warn (_("Illegal 20-bit code (%lu)"),
8290 (unsigned long) imm_expr.X_add_number);
8291 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8292 imm_expr.X_op = O_absent;
8296 case 'C': /* Coprocessor code */
8297 my_getExpression (&imm_expr, s);
8298 check_absolute_expr (ip, &imm_expr);
8299 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8301 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8302 (unsigned long) imm_expr.X_add_number);
8303 imm_expr.X_add_number &= ((1 << 25) - 1);
8305 ip->insn_opcode |= imm_expr.X_add_number;
8306 imm_expr.X_op = O_absent;
8310 case 'J': /* 19-bit wait code. */
8311 my_getExpression (&imm_expr, s);
8312 check_absolute_expr (ip, &imm_expr);
8313 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8314 as_warn (_("Illegal 19-bit code (%lu)"),
8315 (unsigned long) imm_expr.X_add_number);
8316 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8317 imm_expr.X_op = O_absent;
8321 case 'P': /* Performance register */
8322 my_getExpression (&imm_expr, s);
8323 check_absolute_expr (ip, &imm_expr);
8324 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8326 as_warn (_("Invalid performance register (%lu)"),
8327 (unsigned long) imm_expr.X_add_number);
8328 imm_expr.X_add_number &= OP_MASK_PERFREG;
8330 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8331 imm_expr.X_op = O_absent;
8335 case 'b': /* base register */
8336 case 'd': /* destination register */
8337 case 's': /* source register */
8338 case 't': /* target register */
8339 case 'r': /* both target and source */
8340 case 'v': /* both dest and source */
8341 case 'w': /* both dest and target */
8342 case 'E': /* coprocessor target register */
8343 case 'G': /* coprocessor destination register */
8344 case 'K': /* 'rdhwr' destination register */
8345 case 'x': /* ignore register name */
8346 case 'z': /* must be zero register */
8347 case 'U': /* destination register (clo/clz). */
8362 while (ISDIGIT (*s));
8364 as_bad (_("Invalid register number (%d)"), regno);
8366 else if (*args == 'E' || *args == 'G' || *args == 'K')
8370 if (s[1] == 'r' && s[2] == 'a')
8375 else if (s[1] == 'f' && s[2] == 'p')
8380 else if (s[1] == 's' && s[2] == 'p')
8385 else if (s[1] == 'g' && s[2] == 'p')
8390 else if (s[1] == 'a' && s[2] == 't')
8395 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8400 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8405 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8410 else if (itbl_have_entries)
8415 p = s + 1; /* advance past '$' */
8416 n = itbl_get_field (&p); /* n is name */
8418 /* See if this is a register defined in an
8420 if (itbl_get_reg_val (n, &r))
8422 /* Get_field advances to the start of
8423 the next field, so we need to back
8424 rack to the end of the last field. */
8428 s = strchr (s, '\0');
8442 as_warn (_("Used $at without \".set noat\""));
8448 if (c == 'r' || c == 'v' || c == 'w')
8455 /* 'z' only matches $0. */
8456 if (c == 'z' && regno != 0)
8459 /* Now that we have assembled one operand, we use the args string
8460 * to figure out where it goes in the instruction. */
8467 ip->insn_opcode |= regno << OP_SH_RS;
8472 ip->insn_opcode |= regno << OP_SH_RD;
8475 ip->insn_opcode |= regno << OP_SH_RD;
8476 ip->insn_opcode |= regno << OP_SH_RT;
8481 ip->insn_opcode |= regno << OP_SH_RT;
8484 /* This case exists because on the r3000 trunc
8485 expands into a macro which requires a gp
8486 register. On the r6000 or r4000 it is
8487 assembled into a single instruction which
8488 ignores the register. Thus the insn version
8489 is MIPS_ISA2 and uses 'x', and the macro
8490 version is MIPS_ISA1 and uses 't'. */
8493 /* This case is for the div instruction, which
8494 acts differently if the destination argument
8495 is $0. This only matches $0, and is checked
8496 outside the switch. */
8499 /* Itbl operand; not yet implemented. FIXME ?? */
8501 /* What about all other operands like 'i', which
8502 can be specified in the opcode table? */
8512 ip->insn_opcode |= lastregno << OP_SH_RS;
8515 ip->insn_opcode |= lastregno << OP_SH_RT;
8520 case 'O': /* MDMX alignment immediate constant. */
8521 my_getExpression (&imm_expr, s);
8522 check_absolute_expr (ip, &imm_expr);
8523 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8525 as_warn ("Improper align amount (%ld), using low bits",
8526 (long) imm_expr.X_add_number);
8527 imm_expr.X_add_number &= OP_MASK_ALN;
8529 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8530 imm_expr.X_op = O_absent;
8534 case 'Q': /* MDMX vector, element sel, or const. */
8537 /* MDMX Immediate. */
8538 my_getExpression (&imm_expr, s);
8539 check_absolute_expr (ip, &imm_expr);
8540 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8542 as_warn (_("Invalid MDMX Immediate (%ld)"),
8543 (long) imm_expr.X_add_number);
8544 imm_expr.X_add_number &= OP_MASK_FT;
8546 imm_expr.X_add_number &= OP_MASK_FT;
8547 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8548 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8550 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8551 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8552 imm_expr.X_op = O_absent;
8556 /* Not MDMX Immediate. Fall through. */
8557 case 'X': /* MDMX destination register. */
8558 case 'Y': /* MDMX source register. */
8559 case 'Z': /* MDMX target register. */
8561 case 'D': /* floating point destination register */
8562 case 'S': /* floating point source register */
8563 case 'T': /* floating point target register */
8564 case 'R': /* floating point source register */
8568 /* Accept $fN for FP and MDMX register numbers, and in
8569 addition accept $vN for MDMX register numbers. */
8570 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8571 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8582 while (ISDIGIT (*s));
8585 as_bad (_("Invalid float register number (%d)"), regno);
8587 if ((regno & 1) != 0
8589 && ! (strcmp (str, "mtc1") == 0
8590 || strcmp (str, "mfc1") == 0
8591 || strcmp (str, "lwc1") == 0
8592 || strcmp (str, "swc1") == 0
8593 || strcmp (str, "l.s") == 0
8594 || strcmp (str, "s.s") == 0))
8595 as_warn (_("Float register should be even, was %d"),
8603 if (c == 'V' || c == 'W')
8614 ip->insn_opcode |= regno << OP_SH_FD;
8619 ip->insn_opcode |= regno << OP_SH_FS;
8622 /* This is like 'Z', but also needs to fix the MDMX
8623 vector/scalar select bits. Note that the
8624 scalar immediate case is handled above. */
8627 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8628 int max_el = (is_qh ? 3 : 7);
8630 my_getExpression(&imm_expr, s);
8631 check_absolute_expr (ip, &imm_expr);
8633 if (imm_expr.X_add_number > max_el)
8634 as_bad(_("Bad element selector %ld"),
8635 (long) imm_expr.X_add_number);
8636 imm_expr.X_add_number &= max_el;
8637 ip->insn_opcode |= (imm_expr.X_add_number
8640 imm_expr.X_op = O_absent;
8642 as_warn(_("Expecting ']' found '%s'"), s);
8648 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8649 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8652 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8659 ip->insn_opcode |= regno << OP_SH_FT;
8662 ip->insn_opcode |= regno << OP_SH_FR;
8672 ip->insn_opcode |= lastregno << OP_SH_FS;
8675 ip->insn_opcode |= lastregno << OP_SH_FT;
8681 my_getExpression (&imm_expr, s);
8682 if (imm_expr.X_op != O_big
8683 && imm_expr.X_op != O_constant)
8684 insn_error = _("absolute expression required");
8685 normalize_constant_expr (&imm_expr);
8690 my_getExpression (&offset_expr, s);
8691 *imm_reloc = BFD_RELOC_32;
8704 unsigned char temp[8];
8706 unsigned int length;
8711 /* These only appear as the last operand in an
8712 instruction, and every instruction that accepts
8713 them in any variant accepts them in all variants.
8714 This means we don't have to worry about backing out
8715 any changes if the instruction does not match.
8717 The difference between them is the size of the
8718 floating point constant and where it goes. For 'F'
8719 and 'L' the constant is 64 bits; for 'f' and 'l' it
8720 is 32 bits. Where the constant is placed is based
8721 on how the MIPS assembler does things:
8724 f -- immediate value
8727 The .lit4 and .lit8 sections are only used if
8728 permitted by the -G argument.
8730 The code below needs to know whether the target register
8731 is 32 or 64 bits wide. It relies on the fact 'f' and
8732 'F' are used with GPR-based instructions and 'l' and
8733 'L' are used with FPR-based instructions. */
8735 f64 = *args == 'F' || *args == 'L';
8736 using_gprs = *args == 'F' || *args == 'f';
8738 save_in = input_line_pointer;
8739 input_line_pointer = s;
8740 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8742 s = input_line_pointer;
8743 input_line_pointer = save_in;
8744 if (err != NULL && *err != '\0')
8746 as_bad (_("Bad floating point constant: %s"), err);
8747 memset (temp, '\0', sizeof temp);
8748 length = f64 ? 8 : 4;
8751 assert (length == (unsigned) (f64 ? 8 : 4));
8755 && (g_switch_value < 4
8756 || (temp[0] == 0 && temp[1] == 0)
8757 || (temp[2] == 0 && temp[3] == 0))))
8759 imm_expr.X_op = O_constant;
8760 if (! target_big_endian)
8761 imm_expr.X_add_number = bfd_getl32 (temp);
8763 imm_expr.X_add_number = bfd_getb32 (temp);
8766 && ! mips_disable_float_construction
8767 /* Constants can only be constructed in GPRs and
8768 copied to FPRs if the GPRs are at least as wide
8769 as the FPRs. Force the constant into memory if
8770 we are using 64-bit FPRs but the GPRs are only
8773 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8774 && ((temp[0] == 0 && temp[1] == 0)
8775 || (temp[2] == 0 && temp[3] == 0))
8776 && ((temp[4] == 0 && temp[5] == 0)
8777 || (temp[6] == 0 && temp[7] == 0)))
8779 /* The value is simple enough to load with a couple of
8780 instructions. If using 32-bit registers, set
8781 imm_expr to the high order 32 bits and offset_expr to
8782 the low order 32 bits. Otherwise, set imm_expr to
8783 the entire 64 bit constant. */
8784 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8786 imm_expr.X_op = O_constant;
8787 offset_expr.X_op = O_constant;
8788 if (! target_big_endian)
8790 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8791 offset_expr.X_add_number = bfd_getl32 (temp);
8795 imm_expr.X_add_number = bfd_getb32 (temp);
8796 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8798 if (offset_expr.X_add_number == 0)
8799 offset_expr.X_op = O_absent;
8801 else if (sizeof (imm_expr.X_add_number) > 4)
8803 imm_expr.X_op = O_constant;
8804 if (! target_big_endian)
8805 imm_expr.X_add_number = bfd_getl64 (temp);
8807 imm_expr.X_add_number = bfd_getb64 (temp);
8811 imm_expr.X_op = O_big;
8812 imm_expr.X_add_number = 4;
8813 if (! target_big_endian)
8815 generic_bignum[0] = bfd_getl16 (temp);
8816 generic_bignum[1] = bfd_getl16 (temp + 2);
8817 generic_bignum[2] = bfd_getl16 (temp + 4);
8818 generic_bignum[3] = bfd_getl16 (temp + 6);
8822 generic_bignum[0] = bfd_getb16 (temp + 6);
8823 generic_bignum[1] = bfd_getb16 (temp + 4);
8824 generic_bignum[2] = bfd_getb16 (temp + 2);
8825 generic_bignum[3] = bfd_getb16 (temp);
8831 const char *newname;
8834 /* Switch to the right section. */
8836 subseg = now_subseg;
8839 default: /* unused default case avoids warnings. */
8841 newname = RDATA_SECTION_NAME;
8842 if (g_switch_value >= 8)
8846 newname = RDATA_SECTION_NAME;
8849 assert (g_switch_value >= 4);
8853 new_seg = subseg_new (newname, (subsegT) 0);
8854 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8855 bfd_set_section_flags (stdoutput, new_seg,
8860 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8861 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8862 && strcmp (TARGET_OS, "elf") != 0)
8863 record_alignment (new_seg, 4);
8865 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8867 as_bad (_("Can't use floating point insn in this section"));
8869 /* Set the argument to the current address in the
8871 offset_expr.X_op = O_symbol;
8872 offset_expr.X_add_symbol =
8873 symbol_new ("L0\001", now_seg,
8874 (valueT) frag_now_fix (), frag_now);
8875 offset_expr.X_add_number = 0;
8877 /* Put the floating point number into the section. */
8878 p = frag_more ((int) length);
8879 memcpy (p, temp, length);
8881 /* Switch back to the original section. */
8882 subseg_set (seg, subseg);
8887 case 'i': /* 16 bit unsigned immediate */
8888 case 'j': /* 16 bit signed immediate */
8889 *imm_reloc = BFD_RELOC_LO16;
8890 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
8893 offsetT minval, maxval;
8895 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
8896 && strcmp (insn->name, insn[1].name) == 0);
8898 /* If the expression was written as an unsigned number,
8899 only treat it as signed if there are no more
8903 && sizeof (imm_expr.X_add_number) <= 4
8904 && imm_expr.X_op == O_constant
8905 && imm_expr.X_add_number < 0
8906 && imm_expr.X_unsigned
8910 /* For compatibility with older assemblers, we accept
8911 0x8000-0xffff as signed 16-bit numbers when only
8912 signed numbers are allowed. */
8914 minval = 0, maxval = 0xffff;
8916 minval = -0x8000, maxval = 0x7fff;
8918 minval = -0x8000, maxval = 0xffff;
8920 if (imm_expr.X_op != O_constant
8921 || imm_expr.X_add_number < minval
8922 || imm_expr.X_add_number > maxval)
8926 if (imm_expr.X_op == O_constant
8927 || imm_expr.X_op == O_big)
8928 as_bad (_("expression out of range"));
8934 case 'o': /* 16 bit offset */
8935 /* Check whether there is only a single bracketed expression
8936 left. If so, it must be the base register and the
8937 constant must be zero. */
8938 if (*s == '(' && strchr (s + 1, '(') == 0)
8940 offset_expr.X_op = O_constant;
8941 offset_expr.X_add_number = 0;
8945 /* If this value won't fit into a 16 bit offset, then go
8946 find a macro that will generate the 32 bit offset
8948 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
8949 && (offset_expr.X_op != O_constant
8950 || offset_expr.X_add_number >= 0x8000
8951 || offset_expr.X_add_number < -0x8000))
8957 case 'p': /* pc relative offset */
8958 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8959 my_getExpression (&offset_expr, s);
8963 case 'u': /* upper 16 bits */
8964 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
8965 && imm_expr.X_op == O_constant
8966 && (imm_expr.X_add_number < 0
8967 || imm_expr.X_add_number >= 0x10000))
8968 as_bad (_("lui expression not in range 0..65535"));
8972 case 'a': /* 26 bit address */
8973 my_getExpression (&offset_expr, s);
8975 *offset_reloc = BFD_RELOC_MIPS_JMP;
8978 case 'N': /* 3 bit branch condition code */
8979 case 'M': /* 3 bit compare condition code */
8980 if (strncmp (s, "$fcc", 4) != 0)
8990 while (ISDIGIT (*s));
8992 as_bad (_("Invalid condition code register $fcc%d"), regno);
8993 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
8994 || strcmp(str + strlen(str) - 5, "any2f") == 0
8995 || strcmp(str + strlen(str) - 5, "any2t") == 0)
8996 && (regno & 1) != 0)
8997 as_warn(_("Condition code register should be even for %s, was %d"),
8999 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9000 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9001 && (regno & 3) != 0)
9002 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9005 ip->insn_opcode |= regno << OP_SH_BCC;
9007 ip->insn_opcode |= regno << OP_SH_CCC;
9011 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9022 while (ISDIGIT (*s));
9025 c = 8; /* Invalid sel value. */
9028 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9029 ip->insn_opcode |= c;
9033 /* Must be at least one digit. */
9034 my_getExpression (&imm_expr, s);
9035 check_absolute_expr (ip, &imm_expr);
9037 if ((unsigned long) imm_expr.X_add_number
9038 > (unsigned long) OP_MASK_VECBYTE)
9040 as_bad (_("bad byte vector index (%ld)"),
9041 (long) imm_expr.X_add_number);
9042 imm_expr.X_add_number = 0;
9045 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9046 imm_expr.X_op = O_absent;
9051 my_getExpression (&imm_expr, s);
9052 check_absolute_expr (ip, &imm_expr);
9054 if ((unsigned long) imm_expr.X_add_number
9055 > (unsigned long) OP_MASK_VECALIGN)
9057 as_bad (_("bad byte vector index (%ld)"),
9058 (long) imm_expr.X_add_number);
9059 imm_expr.X_add_number = 0;
9062 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9063 imm_expr.X_op = O_absent;
9068 as_bad (_("bad char = '%c'\n"), *args);
9073 /* Args don't match. */
9074 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9075 !strcmp (insn->name, insn[1].name))
9079 insn_error = _("illegal operands");
9084 insn_error = _("illegal operands");
9089 /* This routine assembles an instruction into its binary format when
9090 assembling for the mips16. As a side effect, it sets one of the
9091 global variables imm_reloc or offset_reloc to the type of
9092 relocation to do if one of the operands is an address expression.
9093 It also sets mips16_small and mips16_ext if the user explicitly
9094 requested a small or extended instruction. */
9097 mips16_ip (char *str, struct mips_cl_insn *ip)
9101 struct mips_opcode *insn;
9104 unsigned int lastregno = 0;
9110 mips16_small = FALSE;
9113 for (s = str; ISLOWER (*s); ++s)
9125 if (s[1] == 't' && s[2] == ' ')
9128 mips16_small = TRUE;
9132 else if (s[1] == 'e' && s[2] == ' ')
9141 insn_error = _("unknown opcode");
9145 if (mips_opts.noautoextend && ! mips16_ext)
9146 mips16_small = TRUE;
9148 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9150 insn_error = _("unrecognized opcode");
9157 assert (strcmp (insn->name, str) == 0);
9160 ip->insn_opcode = insn->match;
9161 ip->use_extend = FALSE;
9162 imm_expr.X_op = O_absent;
9163 imm_reloc[0] = BFD_RELOC_UNUSED;
9164 imm_reloc[1] = BFD_RELOC_UNUSED;
9165 imm_reloc[2] = BFD_RELOC_UNUSED;
9166 imm2_expr.X_op = O_absent;
9167 offset_expr.X_op = O_absent;
9168 offset_reloc[0] = BFD_RELOC_UNUSED;
9169 offset_reloc[1] = BFD_RELOC_UNUSED;
9170 offset_reloc[2] = BFD_RELOC_UNUSED;
9171 for (args = insn->args; 1; ++args)
9178 /* In this switch statement we call break if we did not find
9179 a match, continue if we did find a match, or return if we
9188 /* Stuff the immediate value in now, if we can. */
9189 if (imm_expr.X_op == O_constant
9190 && *imm_reloc > BFD_RELOC_UNUSED
9191 && insn->pinfo != INSN_MACRO)
9195 switch (*offset_reloc)
9197 case BFD_RELOC_MIPS16_HI16_S:
9198 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
9201 case BFD_RELOC_MIPS16_HI16:
9202 tmp = imm_expr.X_add_number >> 16;
9205 case BFD_RELOC_MIPS16_LO16:
9206 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
9210 case BFD_RELOC_UNUSED:
9211 tmp = imm_expr.X_add_number;
9217 *offset_reloc = BFD_RELOC_UNUSED;
9219 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9220 tmp, TRUE, mips16_small,
9221 mips16_ext, &ip->insn_opcode,
9222 &ip->use_extend, &ip->extend);
9223 imm_expr.X_op = O_absent;
9224 *imm_reloc = BFD_RELOC_UNUSED;
9238 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9241 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9257 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9259 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9286 while (ISDIGIT (*s));
9289 as_bad (_("invalid register number (%d)"), regno);
9295 if (s[1] == 'r' && s[2] == 'a')
9300 else if (s[1] == 'f' && s[2] == 'p')
9305 else if (s[1] == 's' && s[2] == 'p')
9310 else if (s[1] == 'g' && s[2] == 'p')
9315 else if (s[1] == 'a' && s[2] == 't')
9320 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9325 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9330 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9343 if (c == 'v' || c == 'w')
9345 regno = mips16_to_32_reg_map[lastregno];
9359 regno = mips32_to_16_reg_map[regno];
9364 regno = ILLEGAL_REG;
9369 regno = ILLEGAL_REG;
9374 regno = ILLEGAL_REG;
9379 if (regno == AT && ! mips_opts.noat)
9380 as_warn (_("used $at without \".set noat\""));
9387 if (regno == ILLEGAL_REG)
9394 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9398 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9401 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9404 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9410 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9413 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9414 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9424 if (strncmp (s, "$pc", 3) == 0)
9441 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
9444 if (imm_expr.X_op != O_constant)
9447 ip->use_extend = TRUE;
9452 /* We need to relax this instruction. */
9453 *offset_reloc = *imm_reloc;
9454 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9459 *imm_reloc = BFD_RELOC_UNUSED;
9467 my_getExpression (&imm_expr, s);
9468 if (imm_expr.X_op == O_register)
9470 /* What we thought was an expression turned out to
9473 if (s[0] == '(' && args[1] == '(')
9475 /* It looks like the expression was omitted
9476 before a register indirection, which means
9477 that the expression is implicitly zero. We
9478 still set up imm_expr, so that we handle
9479 explicit extensions correctly. */
9480 imm_expr.X_op = O_constant;
9481 imm_expr.X_add_number = 0;
9482 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9489 /* We need to relax this instruction. */
9490 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9499 /* We use offset_reloc rather than imm_reloc for the PC
9500 relative operands. This lets macros with both
9501 immediate and address operands work correctly. */
9502 my_getExpression (&offset_expr, s);
9504 if (offset_expr.X_op == O_register)
9507 /* We need to relax this instruction. */
9508 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9512 case '6': /* break code */
9513 my_getExpression (&imm_expr, s);
9514 check_absolute_expr (ip, &imm_expr);
9515 if ((unsigned long) imm_expr.X_add_number > 63)
9517 as_warn (_("Invalid value for `%s' (%lu)"),
9519 (unsigned long) imm_expr.X_add_number);
9520 imm_expr.X_add_number &= 0x3f;
9522 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9523 imm_expr.X_op = O_absent;
9527 case 'a': /* 26 bit address */
9528 my_getExpression (&offset_expr, s);
9530 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9531 ip->insn_opcode <<= 16;
9534 case 'l': /* register list for entry macro */
9535 case 'L': /* register list for exit macro */
9545 int freg, reg1, reg2;
9547 while (*s == ' ' || *s == ',')
9551 as_bad (_("can't parse register list"));
9563 while (ISDIGIT (*s))
9585 as_bad (_("invalid register list"));
9590 while (ISDIGIT (*s))
9597 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9602 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9607 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9608 mask |= (reg2 - 3) << 3;
9609 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9610 mask |= (reg2 - 15) << 1;
9611 else if (reg1 == RA && reg2 == RA)
9615 as_bad (_("invalid register list"));
9619 /* The mask is filled in in the opcode table for the
9620 benefit of the disassembler. We remove it before
9621 applying the actual mask. */
9622 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9623 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9627 case 'e': /* extend code */
9628 my_getExpression (&imm_expr, s);
9629 check_absolute_expr (ip, &imm_expr);
9630 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9632 as_warn (_("Invalid value for `%s' (%lu)"),
9634 (unsigned long) imm_expr.X_add_number);
9635 imm_expr.X_add_number &= 0x7ff;
9637 ip->insn_opcode |= imm_expr.X_add_number;
9638 imm_expr.X_op = O_absent;
9648 /* Args don't match. */
9649 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9650 strcmp (insn->name, insn[1].name) == 0)
9657 insn_error = _("illegal operands");
9663 /* This structure holds information we know about a mips16 immediate
9666 struct mips16_immed_operand
9668 /* The type code used in the argument string in the opcode table. */
9670 /* The number of bits in the short form of the opcode. */
9672 /* The number of bits in the extended form of the opcode. */
9674 /* The amount by which the short form is shifted when it is used;
9675 for example, the sw instruction has a shift count of 2. */
9677 /* The amount by which the short form is shifted when it is stored
9678 into the instruction code. */
9680 /* Non-zero if the short form is unsigned. */
9682 /* Non-zero if the extended form is unsigned. */
9684 /* Non-zero if the value is PC relative. */
9688 /* The mips16 immediate operand types. */
9690 static const struct mips16_immed_operand mips16_immed_operands[] =
9692 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9693 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9694 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9695 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9696 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9697 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9698 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9699 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9700 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9701 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9702 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9703 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9704 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9705 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9706 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9707 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9708 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9709 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9710 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9711 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9712 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9715 #define MIPS16_NUM_IMMED \
9716 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9718 /* Handle a mips16 instruction with an immediate value. This or's the
9719 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9720 whether an extended value is needed; if one is needed, it sets
9721 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9722 If SMALL is true, an unextended opcode was explicitly requested.
9723 If EXT is true, an extended opcode was explicitly requested. If
9724 WARN is true, warn if EXT does not match reality. */
9727 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9728 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9729 unsigned long *insn, bfd_boolean *use_extend,
9730 unsigned short *extend)
9732 register const struct mips16_immed_operand *op;
9733 int mintiny, maxtiny;
9734 bfd_boolean needext;
9736 op = mips16_immed_operands;
9737 while (op->type != type)
9740 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9745 if (type == '<' || type == '>' || type == '[' || type == ']')
9748 maxtiny = 1 << op->nbits;
9753 maxtiny = (1 << op->nbits) - 1;
9758 mintiny = - (1 << (op->nbits - 1));
9759 maxtiny = (1 << (op->nbits - 1)) - 1;
9762 /* Branch offsets have an implicit 0 in the lowest bit. */
9763 if (type == 'p' || type == 'q')
9766 if ((val & ((1 << op->shift) - 1)) != 0
9767 || val < (mintiny << op->shift)
9768 || val > (maxtiny << op->shift))
9773 if (warn && ext && ! needext)
9774 as_warn_where (file, line,
9775 _("extended operand requested but not required"));
9776 if (small && needext)
9777 as_bad_where (file, line, _("invalid unextended operand value"));
9779 if (small || (! ext && ! needext))
9783 *use_extend = FALSE;
9784 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9785 insnval <<= op->op_shift;
9790 long minext, maxext;
9796 maxext = (1 << op->extbits) - 1;
9800 minext = - (1 << (op->extbits - 1));
9801 maxext = (1 << (op->extbits - 1)) - 1;
9803 if (val < minext || val > maxext)
9804 as_bad_where (file, line,
9805 _("operand value out of range for instruction"));
9808 if (op->extbits == 16)
9810 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9813 else if (op->extbits == 15)
9815 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9820 extval = ((val & 0x1f) << 6) | (val & 0x20);
9824 *extend = (unsigned short) extval;
9829 struct percent_op_match
9832 bfd_reloc_code_real_type reloc;
9835 static const struct percent_op_match mips_percent_op[] =
9837 {"%lo", BFD_RELOC_LO16},
9839 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9840 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9841 {"%call16", BFD_RELOC_MIPS_CALL16},
9842 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9843 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9844 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9845 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9846 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9847 {"%got", BFD_RELOC_MIPS_GOT16},
9848 {"%gp_rel", BFD_RELOC_GPREL16},
9849 {"%half", BFD_RELOC_16},
9850 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9851 {"%higher", BFD_RELOC_MIPS_HIGHER},
9852 {"%neg", BFD_RELOC_MIPS_SUB},
9853 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
9854 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
9855 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
9856 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
9857 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
9858 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
9859 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
9861 {"%hi", BFD_RELOC_HI16_S}
9864 static const struct percent_op_match mips16_percent_op[] =
9866 {"%lo", BFD_RELOC_MIPS16_LO16},
9867 {"%gprel", BFD_RELOC_MIPS16_GPREL},
9868 {"%hi", BFD_RELOC_MIPS16_HI16_S}
9872 /* Return true if *STR points to a relocation operator. When returning true,
9873 move *STR over the operator and store its relocation code in *RELOC.
9874 Leave both *STR and *RELOC alone when returning false. */
9877 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9879 const struct percent_op_match *percent_op;
9882 if (mips_opts.mips16)
9884 percent_op = mips16_percent_op;
9885 limit = ARRAY_SIZE (mips16_percent_op);
9889 percent_op = mips_percent_op;
9890 limit = ARRAY_SIZE (mips_percent_op);
9893 for (i = 0; i < limit; i++)
9894 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9896 int len = strlen (percent_op[i].str);
9898 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
9901 *str += strlen (percent_op[i].str);
9902 *reloc = percent_op[i].reloc;
9904 /* Check whether the output BFD supports this relocation.
9905 If not, issue an error and fall back on something safe. */
9906 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9908 as_bad ("relocation %s isn't supported by the current ABI",
9910 *reloc = BFD_RELOC_UNUSED;
9918 /* Parse string STR as a 16-bit relocatable operand. Store the
9919 expression in *EP and the relocations in the array starting
9920 at RELOC. Return the number of relocation operators used.
9922 On exit, EXPR_END points to the first character after the expression. */
9925 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
9928 bfd_reloc_code_real_type reversed_reloc[3];
9929 size_t reloc_index, i;
9930 int crux_depth, str_depth;
9933 /* Search for the start of the main expression, recoding relocations
9934 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9935 of the main expression and with CRUX_DEPTH containing the number
9936 of open brackets at that point. */
9943 crux_depth = str_depth;
9945 /* Skip over whitespace and brackets, keeping count of the number
9947 while (*str == ' ' || *str == '\t' || *str == '(')
9952 && reloc_index < (HAVE_NEWABI ? 3 : 1)
9953 && parse_relocation (&str, &reversed_reloc[reloc_index]));
9955 my_getExpression (ep, crux);
9958 /* Match every open bracket. */
9959 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
9964 as_bad ("unclosed '('");
9968 if (reloc_index != 0)
9970 prev_reloc_op_frag = frag_now;
9971 for (i = 0; i < reloc_index; i++)
9972 reloc[i] = reversed_reloc[reloc_index - 1 - i];
9979 my_getExpression (expressionS *ep, char *str)
9984 save_in = input_line_pointer;
9985 input_line_pointer = str;
9987 expr_end = input_line_pointer;
9988 input_line_pointer = save_in;
9990 /* If we are in mips16 mode, and this is an expression based on `.',
9991 then we bump the value of the symbol by 1 since that is how other
9992 text symbols are handled. We don't bother to handle complex
9993 expressions, just `.' plus or minus a constant. */
9994 if (mips_opts.mips16
9995 && ep->X_op == O_symbol
9996 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9997 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9998 && symbol_get_frag (ep->X_add_symbol) == frag_now
9999 && symbol_constant_p (ep->X_add_symbol)
10000 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10001 S_SET_VALUE (ep->X_add_symbol, val + 1);
10004 /* Turn a string in input_line_pointer into a floating point constant
10005 of type TYPE, and store the appropriate bytes in *LITP. The number
10006 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10007 returned, or NULL on OK. */
10010 md_atof (int type, char *litP, int *sizeP)
10013 LITTLENUM_TYPE words[4];
10029 return _("bad call to md_atof");
10032 t = atof_ieee (input_line_pointer, type, words);
10034 input_line_pointer = t;
10038 if (! target_big_endian)
10040 for (i = prec - 1; i >= 0; i--)
10042 md_number_to_chars (litP, words[i], 2);
10048 for (i = 0; i < prec; i++)
10050 md_number_to_chars (litP, words[i], 2);
10059 md_number_to_chars (char *buf, valueT val, int n)
10061 if (target_big_endian)
10062 number_to_chars_bigendian (buf, val, n);
10064 number_to_chars_littleendian (buf, val, n);
10068 static int support_64bit_objects(void)
10070 const char **list, **l;
10073 list = bfd_target_list ();
10074 for (l = list; *l != NULL; l++)
10076 /* This is traditional mips */
10077 if (strcmp (*l, "elf64-tradbigmips") == 0
10078 || strcmp (*l, "elf64-tradlittlemips") == 0)
10080 if (strcmp (*l, "elf64-bigmips") == 0
10081 || strcmp (*l, "elf64-littlemips") == 0)
10084 yes = (*l != NULL);
10088 #endif /* OBJ_ELF */
10090 const char *md_shortopts = "O::g::G:";
10092 struct option md_longopts[] =
10094 /* Options which specify architecture. */
10095 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10096 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10097 {"march", required_argument, NULL, OPTION_MARCH},
10098 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10099 {"mtune", required_argument, NULL, OPTION_MTUNE},
10100 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10101 {"mips0", no_argument, NULL, OPTION_MIPS1},
10102 {"mips1", no_argument, NULL, OPTION_MIPS1},
10103 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10104 {"mips2", no_argument, NULL, OPTION_MIPS2},
10105 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10106 {"mips3", no_argument, NULL, OPTION_MIPS3},
10107 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10108 {"mips4", no_argument, NULL, OPTION_MIPS4},
10109 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10110 {"mips5", no_argument, NULL, OPTION_MIPS5},
10111 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10112 {"mips32", no_argument, NULL, OPTION_MIPS32},
10113 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10114 {"mips64", no_argument, NULL, OPTION_MIPS64},
10115 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10116 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10117 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10118 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10120 /* Options which specify Application Specific Extensions (ASEs). */
10121 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10122 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10123 {"mips16", no_argument, NULL, OPTION_MIPS16},
10124 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10125 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10126 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10127 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10128 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10129 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10130 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10131 {"mdmx", no_argument, NULL, OPTION_MDMX},
10132 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10133 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10135 /* Old-style architecture options. Don't add more of these. */
10136 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10137 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10138 {"m4650", no_argument, NULL, OPTION_M4650},
10139 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10140 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10141 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10142 {"m4010", no_argument, NULL, OPTION_M4010},
10143 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10144 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10145 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10146 {"m4100", no_argument, NULL, OPTION_M4100},
10147 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10148 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10149 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10150 {"m3900", no_argument, NULL, OPTION_M3900},
10151 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10152 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10154 /* Options which enable bug fixes. */
10155 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10156 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10157 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10158 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10159 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10160 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10161 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10162 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10163 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10164 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10166 /* Miscellaneous options. */
10167 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10168 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10169 {"trap", no_argument, NULL, OPTION_TRAP},
10170 {"no-break", no_argument, NULL, OPTION_TRAP},
10171 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10172 {"break", no_argument, NULL, OPTION_BREAK},
10173 {"no-trap", no_argument, NULL, OPTION_BREAK},
10174 #define OPTION_EB (OPTION_MISC_BASE + 2)
10175 {"EB", no_argument, NULL, OPTION_EB},
10176 #define OPTION_EL (OPTION_MISC_BASE + 3)
10177 {"EL", no_argument, NULL, OPTION_EL},
10178 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10179 {"mfp32", no_argument, NULL, OPTION_FP32},
10180 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10181 {"mgp32", no_argument, NULL, OPTION_GP32},
10182 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10183 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10184 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10185 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10186 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10187 {"mfp64", no_argument, NULL, OPTION_FP64},
10188 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10189 {"mgp64", no_argument, NULL, OPTION_GP64},
10190 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10191 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10192 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10193 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10194 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10195 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10196 {"mshared", no_argument, NULL, OPTION_MSHARED},
10197 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
10198 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10199 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10200 {"msym32", no_argument, NULL, OPTION_MSYM32},
10201 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
10203 /* ELF-specific options. */
10205 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10206 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10207 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10208 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10209 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10210 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10211 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10212 {"xgot", no_argument, NULL, OPTION_XGOT},
10213 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10214 {"mabi", required_argument, NULL, OPTION_MABI},
10215 #define OPTION_32 (OPTION_ELF_BASE + 4)
10216 {"32", no_argument, NULL, OPTION_32},
10217 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10218 {"n32", no_argument, NULL, OPTION_N32},
10219 #define OPTION_64 (OPTION_ELF_BASE + 6)
10220 {"64", no_argument, NULL, OPTION_64},
10221 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10222 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10223 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10224 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10225 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10226 {"mpdr", no_argument, NULL, OPTION_PDR},
10227 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10228 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10229 #endif /* OBJ_ELF */
10231 {NULL, no_argument, NULL, 0}
10233 size_t md_longopts_size = sizeof (md_longopts);
10235 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10236 NEW_VALUE. Warn if another value was already specified. Note:
10237 we have to defer parsing the -march and -mtune arguments in order
10238 to handle 'from-abi' correctly, since the ABI might be specified
10239 in a later argument. */
10242 mips_set_option_string (const char **string_ptr, const char *new_value)
10244 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10245 as_warn (_("A different %s was already specified, is now %s"),
10246 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10249 *string_ptr = new_value;
10253 md_parse_option (int c, char *arg)
10257 case OPTION_CONSTRUCT_FLOATS:
10258 mips_disable_float_construction = 0;
10261 case OPTION_NO_CONSTRUCT_FLOATS:
10262 mips_disable_float_construction = 1;
10274 target_big_endian = 1;
10278 target_big_endian = 0;
10282 if (arg && arg[1] == '0')
10292 mips_debug = atoi (arg);
10293 /* When the MIPS assembler sees -g or -g2, it does not do
10294 optimizations which limit full symbolic debugging. We take
10295 that to be equivalent to -O0. */
10296 if (mips_debug == 2)
10301 file_mips_isa = ISA_MIPS1;
10305 file_mips_isa = ISA_MIPS2;
10309 file_mips_isa = ISA_MIPS3;
10313 file_mips_isa = ISA_MIPS4;
10317 file_mips_isa = ISA_MIPS5;
10320 case OPTION_MIPS32:
10321 file_mips_isa = ISA_MIPS32;
10324 case OPTION_MIPS32R2:
10325 file_mips_isa = ISA_MIPS32R2;
10328 case OPTION_MIPS64R2:
10329 file_mips_isa = ISA_MIPS64R2;
10332 case OPTION_MIPS64:
10333 file_mips_isa = ISA_MIPS64;
10337 mips_set_option_string (&mips_tune_string, arg);
10341 mips_set_option_string (&mips_arch_string, arg);
10345 mips_set_option_string (&mips_arch_string, "4650");
10346 mips_set_option_string (&mips_tune_string, "4650");
10349 case OPTION_NO_M4650:
10353 mips_set_option_string (&mips_arch_string, "4010");
10354 mips_set_option_string (&mips_tune_string, "4010");
10357 case OPTION_NO_M4010:
10361 mips_set_option_string (&mips_arch_string, "4100");
10362 mips_set_option_string (&mips_tune_string, "4100");
10365 case OPTION_NO_M4100:
10369 mips_set_option_string (&mips_arch_string, "3900");
10370 mips_set_option_string (&mips_tune_string, "3900");
10373 case OPTION_NO_M3900:
10377 mips_opts.ase_mdmx = 1;
10380 case OPTION_NO_MDMX:
10381 mips_opts.ase_mdmx = 0;
10384 case OPTION_MIPS16:
10385 mips_opts.mips16 = 1;
10386 mips_no_prev_insn (FALSE);
10389 case OPTION_NO_MIPS16:
10390 mips_opts.mips16 = 0;
10391 mips_no_prev_insn (FALSE);
10394 case OPTION_MIPS3D:
10395 mips_opts.ase_mips3d = 1;
10398 case OPTION_NO_MIPS3D:
10399 mips_opts.ase_mips3d = 0;
10402 case OPTION_FIX_VR4120:
10403 mips_fix_vr4120 = 1;
10406 case OPTION_NO_FIX_VR4120:
10407 mips_fix_vr4120 = 0;
10410 case OPTION_RELAX_BRANCH:
10411 mips_relax_branch = 1;
10414 case OPTION_NO_RELAX_BRANCH:
10415 mips_relax_branch = 0;
10418 case OPTION_MSHARED:
10419 mips_in_shared = TRUE;
10422 case OPTION_MNO_SHARED:
10423 mips_in_shared = FALSE;
10426 case OPTION_MSYM32:
10427 mips_opts.sym32 = TRUE;
10430 case OPTION_MNO_SYM32:
10431 mips_opts.sym32 = FALSE;
10435 /* When generating ELF code, we permit -KPIC and -call_shared to
10436 select SVR4_PIC, and -non_shared to select no PIC. This is
10437 intended to be compatible with Irix 5. */
10438 case OPTION_CALL_SHARED:
10439 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10441 as_bad (_("-call_shared is supported only for ELF format"));
10444 mips_pic = SVR4_PIC;
10445 mips_abicalls = TRUE;
10446 if (g_switch_seen && g_switch_value != 0)
10448 as_bad (_("-G may not be used with SVR4 PIC code"));
10451 g_switch_value = 0;
10454 case OPTION_NON_SHARED:
10455 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10457 as_bad (_("-non_shared is supported only for ELF format"));
10461 mips_abicalls = FALSE;
10464 /* The -xgot option tells the assembler to use 32 offsets when
10465 accessing the got in SVR4_PIC mode. It is for Irix
10470 #endif /* OBJ_ELF */
10473 g_switch_value = atoi (arg);
10475 if (mips_pic == SVR4_PIC && g_switch_value != 0)
10477 as_bad (_("-G may not be used with SVR4 PIC code"));
10483 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10486 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10488 as_bad (_("-32 is supported for ELF format only"));
10491 mips_abi = O32_ABI;
10495 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10497 as_bad (_("-n32 is supported for ELF format only"));
10500 mips_abi = N32_ABI;
10504 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10506 as_bad (_("-64 is supported for ELF format only"));
10509 mips_abi = N64_ABI;
10510 if (! support_64bit_objects())
10511 as_fatal (_("No compiled in support for 64 bit object file format"));
10513 #endif /* OBJ_ELF */
10516 file_mips_gp32 = 1;
10520 file_mips_gp32 = 0;
10524 file_mips_fp32 = 1;
10528 file_mips_fp32 = 0;
10533 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10535 as_bad (_("-mabi is supported for ELF format only"));
10538 if (strcmp (arg, "32") == 0)
10539 mips_abi = O32_ABI;
10540 else if (strcmp (arg, "o64") == 0)
10541 mips_abi = O64_ABI;
10542 else if (strcmp (arg, "n32") == 0)
10543 mips_abi = N32_ABI;
10544 else if (strcmp (arg, "64") == 0)
10546 mips_abi = N64_ABI;
10547 if (! support_64bit_objects())
10548 as_fatal (_("No compiled in support for 64 bit object file "
10551 else if (strcmp (arg, "eabi") == 0)
10552 mips_abi = EABI_ABI;
10555 as_fatal (_("invalid abi -mabi=%s"), arg);
10559 #endif /* OBJ_ELF */
10561 case OPTION_M7000_HILO_FIX:
10562 mips_7000_hilo_fix = TRUE;
10565 case OPTION_MNO_7000_HILO_FIX:
10566 mips_7000_hilo_fix = FALSE;
10570 case OPTION_MDEBUG:
10571 mips_flag_mdebug = TRUE;
10574 case OPTION_NO_MDEBUG:
10575 mips_flag_mdebug = FALSE;
10579 mips_flag_pdr = TRUE;
10582 case OPTION_NO_PDR:
10583 mips_flag_pdr = FALSE;
10585 #endif /* OBJ_ELF */
10594 /* Set up globals to generate code for the ISA or processor
10595 described by INFO. */
10598 mips_set_architecture (const struct mips_cpu_info *info)
10602 file_mips_arch = info->cpu;
10603 mips_opts.arch = info->cpu;
10604 mips_opts.isa = info->isa;
10609 /* Likewise for tuning. */
10612 mips_set_tune (const struct mips_cpu_info *info)
10615 mips_tune = info->cpu;
10620 mips_after_parse_args (void)
10622 const struct mips_cpu_info *arch_info = 0;
10623 const struct mips_cpu_info *tune_info = 0;
10625 /* GP relative stuff not working for PE */
10626 if (strncmp (TARGET_OS, "pe", 2) == 0)
10628 if (g_switch_seen && g_switch_value != 0)
10629 as_bad (_("-G not supported in this configuration."));
10630 g_switch_value = 0;
10633 if (mips_abi == NO_ABI)
10634 mips_abi = MIPS_DEFAULT_ABI;
10636 /* The following code determines the architecture and register size.
10637 Similar code was added to GCC 3.3 (see override_options() in
10638 config/mips/mips.c). The GAS and GCC code should be kept in sync
10639 as much as possible. */
10641 if (mips_arch_string != 0)
10642 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10644 if (file_mips_isa != ISA_UNKNOWN)
10646 /* Handle -mipsN. At this point, file_mips_isa contains the
10647 ISA level specified by -mipsN, while arch_info->isa contains
10648 the -march selection (if any). */
10649 if (arch_info != 0)
10651 /* -march takes precedence over -mipsN, since it is more descriptive.
10652 There's no harm in specifying both as long as the ISA levels
10654 if (file_mips_isa != arch_info->isa)
10655 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10656 mips_cpu_info_from_isa (file_mips_isa)->name,
10657 mips_cpu_info_from_isa (arch_info->isa)->name);
10660 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10663 if (arch_info == 0)
10664 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10666 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10667 as_bad ("-march=%s is not compatible with the selected ABI",
10670 mips_set_architecture (arch_info);
10672 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10673 if (mips_tune_string != 0)
10674 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10676 if (tune_info == 0)
10677 mips_set_tune (arch_info);
10679 mips_set_tune (tune_info);
10681 if (file_mips_gp32 >= 0)
10683 /* The user specified the size of the integer registers. Make sure
10684 it agrees with the ABI and ISA. */
10685 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10686 as_bad (_("-mgp64 used with a 32-bit processor"));
10687 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10688 as_bad (_("-mgp32 used with a 64-bit ABI"));
10689 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10690 as_bad (_("-mgp64 used with a 32-bit ABI"));
10694 /* Infer the integer register size from the ABI and processor.
10695 Restrict ourselves to 32-bit registers if that's all the
10696 processor has, or if the ABI cannot handle 64-bit registers. */
10697 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10698 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10701 /* ??? GAS treats single-float processors as though they had 64-bit
10702 float registers (although it complains when double-precision
10703 instructions are used). As things stand, saying they have 32-bit
10704 registers would lead to spurious "register must be even" messages.
10705 So here we assume float registers are always the same size as
10706 integer ones, unless the user says otherwise. */
10707 if (file_mips_fp32 < 0)
10708 file_mips_fp32 = file_mips_gp32;
10710 /* End of GCC-shared inference code. */
10712 /* This flag is set when we have a 64-bit capable CPU but use only
10713 32-bit wide registers. Note that EABI does not use it. */
10714 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10715 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10716 || mips_abi == O32_ABI))
10717 mips_32bitmode = 1;
10719 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10720 as_bad (_("trap exception not supported at ISA 1"));
10722 /* If the selected architecture includes support for ASEs, enable
10723 generation of code for them. */
10724 if (mips_opts.mips16 == -1)
10725 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10726 if (mips_opts.ase_mips3d == -1)
10727 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10728 if (mips_opts.ase_mdmx == -1)
10729 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10731 file_mips_isa = mips_opts.isa;
10732 file_ase_mips16 = mips_opts.mips16;
10733 file_ase_mips3d = mips_opts.ase_mips3d;
10734 file_ase_mdmx = mips_opts.ase_mdmx;
10735 mips_opts.gp32 = file_mips_gp32;
10736 mips_opts.fp32 = file_mips_fp32;
10738 if (mips_flag_mdebug < 0)
10740 #ifdef OBJ_MAYBE_ECOFF
10741 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10742 mips_flag_mdebug = 1;
10744 #endif /* OBJ_MAYBE_ECOFF */
10745 mips_flag_mdebug = 0;
10750 mips_init_after_args (void)
10752 /* initialize opcodes */
10753 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10754 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10758 md_pcrel_from (fixS *fixP)
10760 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10761 switch (fixP->fx_r_type)
10763 case BFD_RELOC_16_PCREL_S2:
10764 case BFD_RELOC_MIPS_JMP:
10765 /* Return the address of the delay slot. */
10772 /* This is called before the symbol table is processed. In order to
10773 work with gcc when using mips-tfile, we must keep all local labels.
10774 However, in other cases, we want to discard them. If we were
10775 called with -g, but we didn't see any debugging information, it may
10776 mean that gcc is smuggling debugging information through to
10777 mips-tfile, in which case we must generate all local labels. */
10780 mips_frob_file_before_adjust (void)
10782 #ifndef NO_ECOFF_DEBUGGING
10783 if (ECOFF_DEBUGGING
10785 && ! ecoff_debugging_seen)
10786 flag_keep_locals = 1;
10790 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10791 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10792 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10793 relocation operators.
10795 For our purposes, a %lo() expression matches a %got() or %hi()
10798 (a) it refers to the same symbol; and
10799 (b) the offset applied in the %lo() expression is no lower than
10800 the offset applied in the %got() or %hi().
10802 (b) allows us to cope with code like:
10805 lh $4,%lo(foo+2)($4)
10807 ...which is legal on RELA targets, and has a well-defined behaviour
10808 if the user knows that adding 2 to "foo" will not induce a carry to
10811 When several %lo()s match a particular %got() or %hi(), we use the
10812 following rules to distinguish them:
10814 (1) %lo()s with smaller offsets are a better match than %lo()s with
10817 (2) %lo()s with no matching %got() or %hi() are better than those
10818 that already have a matching %got() or %hi().
10820 (3) later %lo()s are better than earlier %lo()s.
10822 These rules are applied in order.
10824 (1) means, among other things, that %lo()s with identical offsets are
10825 chosen if they exist.
10827 (2) means that we won't associate several high-part relocations with
10828 the same low-part relocation unless there's no alternative. Having
10829 several high parts for the same low part is a GNU extension; this rule
10830 allows careful users to avoid it.
10832 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10833 with the last high-part relocation being at the front of the list.
10834 It therefore makes sense to choose the last matching low-part
10835 relocation, all other things being equal. It's also easier
10836 to code that way. */
10839 mips_frob_file (void)
10841 struct mips_hi_fixup *l;
10843 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10845 segment_info_type *seginfo;
10846 bfd_boolean matched_lo_p;
10847 fixS **hi_pos, **lo_pos, **pos;
10849 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10851 /* If a GOT16 relocation turns out to be against a global symbol,
10852 there isn't supposed to be a matching LO. */
10853 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10854 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10857 /* Check quickly whether the next fixup happens to be a matching %lo. */
10858 if (fixup_has_matching_lo_p (l->fixp))
10861 seginfo = seg_info (l->seg);
10863 /* Set HI_POS to the position of this relocation in the chain.
10864 Set LO_POS to the position of the chosen low-part relocation.
10865 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10866 relocation that matches an immediately-preceding high-part
10870 matched_lo_p = FALSE;
10871 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10873 if (*pos == l->fixp)
10876 if ((*pos)->fx_r_type == BFD_RELOC_LO16
10877 && (*pos)->fx_addsy == l->fixp->fx_addsy
10878 && (*pos)->fx_offset >= l->fixp->fx_offset
10880 || (*pos)->fx_offset < (*lo_pos)->fx_offset
10882 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
10885 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
10886 && fixup_has_matching_lo_p (*pos));
10889 /* If we found a match, remove the high-part relocation from its
10890 current position and insert it before the low-part relocation.
10891 Make the offsets match so that fixup_has_matching_lo_p()
10894 We don't warn about unmatched high-part relocations since some
10895 versions of gcc have been known to emit dead "lui ...%hi(...)"
10897 if (lo_pos != NULL)
10899 l->fixp->fx_offset = (*lo_pos)->fx_offset;
10900 if (l->fixp->fx_next != *lo_pos)
10902 *hi_pos = l->fixp->fx_next;
10903 l->fixp->fx_next = *lo_pos;
10910 /* We may have combined relocations without symbols in the N32/N64 ABI.
10911 We have to prevent gas from dropping them. */
10914 mips_force_relocation (fixS *fixp)
10916 if (generic_force_reloc (fixp))
10920 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10921 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10922 || fixp->fx_r_type == BFD_RELOC_HI16_S
10923 || fixp->fx_r_type == BFD_RELOC_LO16))
10929 /* This hook is called before a fix is simplified. We don't really
10930 decide whether to skip a fix here. Rather, we turn global symbols
10931 used as branch targets into local symbols, such that they undergo
10932 simplification. We can only do this if the symbol is defined and
10933 it is in the same section as the branch. If this doesn't hold, we
10934 emit a better error message than just saying the relocation is not
10935 valid for the selected object format.
10937 FIXP is the fix-up we're going to try to simplify, SEG is the
10938 segment in which the fix up occurs. The return value should be
10939 non-zero to indicate the fix-up is valid for further
10940 simplifications. */
10943 mips_validate_fix (struct fix *fixP, asection *seg)
10945 /* There's a lot of discussion on whether it should be possible to
10946 use R_MIPS_PC16 to represent branch relocations. The outcome
10947 seems to be that it can, but gas/bfd are very broken in creating
10948 RELA relocations for this, so for now we only accept branches to
10949 symbols in the same section. Anything else is of dubious value,
10950 since there's no guarantee that at link time the symbol would be
10951 in range. Even for branches to local symbols this is arguably
10952 wrong, since it we assume the symbol is not going to be
10953 overridden, which should be possible per ELF library semantics,
10954 but then, there isn't a dynamic relocation that could be used to
10955 this effect, and the target would likely be out of range as well.
10957 Unfortunately, it seems that there is too much code out there
10958 that relies on branches to symbols that are global to be resolved
10959 as if they were local, like the IRIX tools do, so we do it as
10960 well, but with a warning so that people are reminded to fix their
10961 code. If we ever get back to using R_MIPS_PC16 for branch
10962 targets, this entire block should go away (and probably the
10963 whole function). */
10965 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
10966 && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
10967 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
10968 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
10971 if (! S_IS_DEFINED (fixP->fx_addsy))
10973 as_bad_where (fixP->fx_file, fixP->fx_line,
10974 _("Cannot branch to undefined symbol."));
10975 /* Avoid any further errors about this fixup. */
10978 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
10980 as_bad_where (fixP->fx_file, fixP->fx_line,
10981 _("Cannot branch to symbol in another section."));
10984 else if (S_IS_EXTERNAL (fixP->fx_addsy))
10986 symbolS *sym = fixP->fx_addsy;
10988 if (mips_pic == SVR4_PIC)
10989 as_warn_where (fixP->fx_file, fixP->fx_line,
10990 _("Pretending global symbol used as branch target is local."));
10992 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
10993 S_GET_SEGMENT (sym),
10995 symbol_get_frag (sym));
10996 copy_symbol_attributes (fixP->fx_addsy, sym);
10997 S_CLEAR_EXTERNAL (fixP->fx_addsy);
10998 assert (symbol_resolved_p (sym));
10999 symbol_mark_resolved (fixP->fx_addsy);
11006 /* Apply a fixup to the object file. */
11009 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11013 reloc_howto_type *howto;
11015 /* We ignore generic BFD relocations we don't know about. */
11016 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11020 assert (fixP->fx_size == 4
11021 || fixP->fx_r_type == BFD_RELOC_16
11022 || fixP->fx_r_type == BFD_RELOC_64
11023 || fixP->fx_r_type == BFD_RELOC_CTOR
11024 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11025 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11026 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11028 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11030 assert (! fixP->fx_pcrel);
11032 /* Don't treat parts of a composite relocation as done. There are two
11035 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11036 should nevertheless be emitted if the first part is.
11038 (2) In normal usage, composite relocations are never assembly-time
11039 constants. The easiest way of dealing with the pathological
11040 exceptions is to generate a relocation against STN_UNDEF and
11041 leave everything up to the linker. */
11042 if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0)
11045 switch (fixP->fx_r_type)
11047 case BFD_RELOC_MIPS_TLS_GD:
11048 case BFD_RELOC_MIPS_TLS_LDM:
11049 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
11050 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
11051 case BFD_RELOC_MIPS_TLS_GOTTPREL:
11052 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
11053 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
11054 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11057 case BFD_RELOC_MIPS_JMP:
11058 case BFD_RELOC_MIPS_SHIFT5:
11059 case BFD_RELOC_MIPS_SHIFT6:
11060 case BFD_RELOC_MIPS_GOT_DISP:
11061 case BFD_RELOC_MIPS_GOT_PAGE:
11062 case BFD_RELOC_MIPS_GOT_OFST:
11063 case BFD_RELOC_MIPS_SUB:
11064 case BFD_RELOC_MIPS_INSERT_A:
11065 case BFD_RELOC_MIPS_INSERT_B:
11066 case BFD_RELOC_MIPS_DELETE:
11067 case BFD_RELOC_MIPS_HIGHEST:
11068 case BFD_RELOC_MIPS_HIGHER:
11069 case BFD_RELOC_MIPS_SCN_DISP:
11070 case BFD_RELOC_MIPS_REL16:
11071 case BFD_RELOC_MIPS_RELGOT:
11072 case BFD_RELOC_MIPS_JALR:
11073 case BFD_RELOC_HI16:
11074 case BFD_RELOC_HI16_S:
11075 case BFD_RELOC_GPREL16:
11076 case BFD_RELOC_MIPS_LITERAL:
11077 case BFD_RELOC_MIPS_CALL16:
11078 case BFD_RELOC_MIPS_GOT16:
11079 case BFD_RELOC_GPREL32:
11080 case BFD_RELOC_MIPS_GOT_HI16:
11081 case BFD_RELOC_MIPS_GOT_LO16:
11082 case BFD_RELOC_MIPS_CALL_HI16:
11083 case BFD_RELOC_MIPS_CALL_LO16:
11084 case BFD_RELOC_MIPS16_GPREL:
11085 case BFD_RELOC_MIPS16_HI16:
11086 case BFD_RELOC_MIPS16_HI16_S:
11087 assert (! fixP->fx_pcrel);
11088 /* Nothing needed to do. The value comes from the reloc entry */
11091 case BFD_RELOC_MIPS16_JMP:
11092 /* We currently always generate a reloc against a symbol, which
11093 means that we don't want an addend even if the symbol is
11099 /* This is handled like BFD_RELOC_32, but we output a sign
11100 extended value if we are only 32 bits. */
11103 if (8 <= sizeof (valueT))
11104 md_number_to_chars ((char *) buf, *valP, 8);
11109 if ((*valP & 0x80000000) != 0)
11113 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11115 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11121 case BFD_RELOC_RVA:
11123 /* If we are deleting this reloc entry, we must fill in the
11124 value now. This can happen if we have a .word which is not
11125 resolved when it appears but is later defined. */
11127 md_number_to_chars ((char *) buf, *valP, 4);
11131 /* If we are deleting this reloc entry, we must fill in the
11134 md_number_to_chars ((char *) buf, *valP, 2);
11137 case BFD_RELOC_LO16:
11138 case BFD_RELOC_MIPS16_LO16:
11139 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11140 may be safe to remove, but if so it's not obvious. */
11141 /* When handling an embedded PIC switch statement, we can wind
11142 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11145 if (*valP + 0x8000 > 0xffff)
11146 as_bad_where (fixP->fx_file, fixP->fx_line,
11147 _("relocation overflow"));
11148 if (target_big_endian)
11150 md_number_to_chars ((char *) buf, *valP, 2);
11154 case BFD_RELOC_16_PCREL_S2:
11155 if ((*valP & 0x3) != 0)
11156 as_bad_where (fixP->fx_file, fixP->fx_line,
11157 _("Branch to odd address (%lx)"), (long) *valP);
11160 * We need to save the bits in the instruction since fixup_segment()
11161 * might be deleting the relocation entry (i.e., a branch within
11162 * the current segment).
11164 if (! fixP->fx_done)
11167 /* update old instruction data */
11168 if (target_big_endian)
11169 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11171 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11173 if (*valP + 0x20000 <= 0x3ffff)
11175 insn |= (*valP >> 2) & 0xffff;
11176 md_number_to_chars ((char *) buf, insn, 4);
11178 else if (mips_pic == NO_PIC
11180 && fixP->fx_frag->fr_address >= text_section->vma
11181 && (fixP->fx_frag->fr_address
11182 < text_section->vma + bfd_get_section_size (text_section))
11183 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11184 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11185 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11187 /* The branch offset is too large. If this is an
11188 unconditional branch, and we are not generating PIC code,
11189 we can convert it to an absolute jump instruction. */
11190 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11191 insn = 0x0c000000; /* jal */
11193 insn = 0x08000000; /* j */
11194 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11196 fixP->fx_addsy = section_symbol (text_section);
11197 *valP += md_pcrel_from (fixP);
11198 md_number_to_chars ((char *) buf, insn, 4);
11202 /* If we got here, we have branch-relaxation disabled,
11203 and there's nothing we can do to fix this instruction
11204 without turning it into a longer sequence. */
11205 as_bad_where (fixP->fx_file, fixP->fx_line,
11206 _("Branch out of range"));
11210 case BFD_RELOC_VTABLE_INHERIT:
11213 && !S_IS_DEFINED (fixP->fx_addsy)
11214 && !S_IS_WEAK (fixP->fx_addsy))
11215 S_SET_WEAK (fixP->fx_addsy);
11218 case BFD_RELOC_VTABLE_ENTRY:
11226 /* Remember value for tc_gen_reloc. */
11227 fixP->fx_addnumber = *valP;
11237 name = input_line_pointer;
11238 c = get_symbol_end ();
11239 p = (symbolS *) symbol_find_or_make (name);
11240 *input_line_pointer = c;
11244 /* Align the current frag to a given power of two. The MIPS assembler
11245 also automatically adjusts any preceding label. */
11248 mips_align (int to, int fill, symbolS *label)
11250 mips_emit_delays (FALSE);
11251 frag_align (to, fill, 0);
11252 record_alignment (now_seg, to);
11255 assert (S_GET_SEGMENT (label) == now_seg);
11256 symbol_set_frag (label, frag_now);
11257 S_SET_VALUE (label, (valueT) frag_now_fix ());
11261 /* Align to a given power of two. .align 0 turns off the automatic
11262 alignment used by the data creating pseudo-ops. */
11265 s_align (int x ATTRIBUTE_UNUSED)
11268 register long temp_fill;
11269 long max_alignment = 15;
11273 o Note that the assembler pulls down any immediately preceding label
11274 to the aligned address.
11275 o It's not documented but auto alignment is reinstated by
11276 a .align pseudo instruction.
11277 o Note also that after auto alignment is turned off the mips assembler
11278 issues an error on attempt to assemble an improperly aligned data item.
11283 temp = get_absolute_expression ();
11284 if (temp > max_alignment)
11285 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11288 as_warn (_("Alignment negative: 0 assumed."));
11291 if (*input_line_pointer == ',')
11293 ++input_line_pointer;
11294 temp_fill = get_absolute_expression ();
11301 mips_align (temp, (int) temp_fill,
11302 insn_labels != NULL ? insn_labels->label : NULL);
11309 demand_empty_rest_of_line ();
11313 mips_flush_pending_output (void)
11315 mips_emit_delays (FALSE);
11316 mips_clear_insn_labels ();
11320 s_change_sec (int sec)
11325 /* The ELF backend needs to know that we are changing sections, so
11326 that .previous works correctly. We could do something like check
11327 for an obj_section_change_hook macro, but that might be confusing
11328 as it would not be appropriate to use it in the section changing
11329 functions in read.c, since obj-elf.c intercepts those. FIXME:
11330 This should be cleaner, somehow. */
11331 obj_elf_section_change_hook ();
11334 mips_emit_delays (FALSE);
11344 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11345 demand_empty_rest_of_line ();
11349 seg = subseg_new (RDATA_SECTION_NAME,
11350 (subsegT) get_absolute_expression ());
11351 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11353 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11354 | SEC_READONLY | SEC_RELOC
11356 if (strcmp (TARGET_OS, "elf") != 0)
11357 record_alignment (seg, 4);
11359 demand_empty_rest_of_line ();
11363 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11364 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11366 bfd_set_section_flags (stdoutput, seg,
11367 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11368 if (strcmp (TARGET_OS, "elf") != 0)
11369 record_alignment (seg, 4);
11371 demand_empty_rest_of_line ();
11379 s_change_section (int ignore ATTRIBUTE_UNUSED)
11382 char *section_name;
11387 int section_entry_size;
11388 int section_alignment;
11390 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11393 section_name = input_line_pointer;
11394 c = get_symbol_end ();
11396 next_c = *(input_line_pointer + 1);
11398 /* Do we have .section Name<,"flags">? */
11399 if (c != ',' || (c == ',' && next_c == '"'))
11401 /* just after name is now '\0'. */
11402 *input_line_pointer = c;
11403 input_line_pointer = section_name;
11404 obj_elf_section (ignore);
11407 input_line_pointer++;
11409 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11411 section_type = get_absolute_expression ();
11414 if (*input_line_pointer++ == ',')
11415 section_flag = get_absolute_expression ();
11418 if (*input_line_pointer++ == ',')
11419 section_entry_size = get_absolute_expression ();
11421 section_entry_size = 0;
11422 if (*input_line_pointer++ == ',')
11423 section_alignment = get_absolute_expression ();
11425 section_alignment = 0;
11427 section_name = xstrdup (section_name);
11429 /* When using the generic form of .section (as implemented by obj-elf.c),
11430 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11431 traditionally had to fall back on the more common @progbits instead.
11433 There's nothing really harmful in this, since bfd will correct
11434 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11435 means that, for backwards compatibiltiy, the special_section entries
11436 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11438 Even so, we shouldn't force users of the MIPS .section syntax to
11439 incorrectly label the sections as SHT_PROGBITS. The best compromise
11440 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11441 generic type-checking code. */
11442 if (section_type == SHT_MIPS_DWARF)
11443 section_type = SHT_PROGBITS;
11445 obj_elf_change_section (section_name, section_type, section_flag,
11446 section_entry_size, 0, 0, 0);
11448 if (now_seg->name != section_name)
11449 free (section_name);
11450 #endif /* OBJ_ELF */
11454 mips_enable_auto_align (void)
11460 s_cons (int log_size)
11464 label = insn_labels != NULL ? insn_labels->label : NULL;
11465 mips_emit_delays (FALSE);
11466 if (log_size > 0 && auto_align)
11467 mips_align (log_size, 0, label);
11468 mips_clear_insn_labels ();
11469 cons (1 << log_size);
11473 s_float_cons (int type)
11477 label = insn_labels != NULL ? insn_labels->label : NULL;
11479 mips_emit_delays (FALSE);
11484 mips_align (3, 0, label);
11486 mips_align (2, 0, label);
11489 mips_clear_insn_labels ();
11494 /* Handle .globl. We need to override it because on Irix 5 you are
11497 where foo is an undefined symbol, to mean that foo should be
11498 considered to be the address of a function. */
11501 s_mips_globl (int x ATTRIBUTE_UNUSED)
11508 name = input_line_pointer;
11509 c = get_symbol_end ();
11510 symbolP = symbol_find_or_make (name);
11511 *input_line_pointer = c;
11512 SKIP_WHITESPACE ();
11514 /* On Irix 5, every global symbol that is not explicitly labelled as
11515 being a function is apparently labelled as being an object. */
11518 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11523 secname = input_line_pointer;
11524 c = get_symbol_end ();
11525 sec = bfd_get_section_by_name (stdoutput, secname);
11527 as_bad (_("%s: no such section"), secname);
11528 *input_line_pointer = c;
11530 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11531 flag = BSF_FUNCTION;
11534 symbol_get_bfdsym (symbolP)->flags |= flag;
11536 S_SET_EXTERNAL (symbolP);
11537 demand_empty_rest_of_line ();
11541 s_option (int x ATTRIBUTE_UNUSED)
11546 opt = input_line_pointer;
11547 c = get_symbol_end ();
11551 /* FIXME: What does this mean? */
11553 else if (strncmp (opt, "pic", 3) == 0)
11557 i = atoi (opt + 3);
11562 mips_pic = SVR4_PIC;
11563 mips_abicalls = TRUE;
11566 as_bad (_(".option pic%d not supported"), i);
11568 if (mips_pic == SVR4_PIC)
11570 if (g_switch_seen && g_switch_value != 0)
11571 as_warn (_("-G may not be used with SVR4 PIC code"));
11572 g_switch_value = 0;
11573 bfd_set_gp_size (stdoutput, 0);
11577 as_warn (_("Unrecognized option \"%s\""), opt);
11579 *input_line_pointer = c;
11580 demand_empty_rest_of_line ();
11583 /* This structure is used to hold a stack of .set values. */
11585 struct mips_option_stack
11587 struct mips_option_stack *next;
11588 struct mips_set_options options;
11591 static struct mips_option_stack *mips_opts_stack;
11593 /* Handle the .set pseudo-op. */
11596 s_mipsset (int x ATTRIBUTE_UNUSED)
11598 char *name = input_line_pointer, ch;
11600 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11601 ++input_line_pointer;
11602 ch = *input_line_pointer;
11603 *input_line_pointer = '\0';
11605 if (strcmp (name, "reorder") == 0)
11607 if (mips_opts.noreorder && prev_nop_frag != NULL)
11609 /* If we still have pending nops, we can discard them. The
11610 usual nop handling will insert any that are still
11612 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11613 * (mips_opts.mips16 ? 2 : 4));
11614 prev_nop_frag = NULL;
11616 mips_opts.noreorder = 0;
11618 else if (strcmp (name, "noreorder") == 0)
11620 mips_emit_delays (TRUE);
11621 mips_opts.noreorder = 1;
11622 mips_any_noreorder = 1;
11624 else if (strcmp (name, "at") == 0)
11626 mips_opts.noat = 0;
11628 else if (strcmp (name, "noat") == 0)
11630 mips_opts.noat = 1;
11632 else if (strcmp (name, "macro") == 0)
11634 mips_opts.warn_about_macros = 0;
11636 else if (strcmp (name, "nomacro") == 0)
11638 if (mips_opts.noreorder == 0)
11639 as_bad (_("`noreorder' must be set before `nomacro'"));
11640 mips_opts.warn_about_macros = 1;
11642 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11644 mips_opts.nomove = 0;
11646 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11648 mips_opts.nomove = 1;
11650 else if (strcmp (name, "bopt") == 0)
11652 mips_opts.nobopt = 0;
11654 else if (strcmp (name, "nobopt") == 0)
11656 mips_opts.nobopt = 1;
11658 else if (strcmp (name, "mips16") == 0
11659 || strcmp (name, "MIPS-16") == 0)
11660 mips_opts.mips16 = 1;
11661 else if (strcmp (name, "nomips16") == 0
11662 || strcmp (name, "noMIPS-16") == 0)
11663 mips_opts.mips16 = 0;
11664 else if (strcmp (name, "mips3d") == 0)
11665 mips_opts.ase_mips3d = 1;
11666 else if (strcmp (name, "nomips3d") == 0)
11667 mips_opts.ase_mips3d = 0;
11668 else if (strcmp (name, "mdmx") == 0)
11669 mips_opts.ase_mdmx = 1;
11670 else if (strcmp (name, "nomdmx") == 0)
11671 mips_opts.ase_mdmx = 0;
11672 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11676 /* Permit the user to change the ISA and architecture on the fly.
11677 Needless to say, misuse can cause serious problems. */
11678 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11681 mips_opts.isa = file_mips_isa;
11682 mips_opts.arch = file_mips_arch;
11684 else if (strncmp (name, "arch=", 5) == 0)
11686 const struct mips_cpu_info *p;
11688 p = mips_parse_cpu("internal use", name + 5);
11690 as_bad (_("unknown architecture %s"), name + 5);
11693 mips_opts.arch = p->cpu;
11694 mips_opts.isa = p->isa;
11697 else if (strncmp (name, "mips", 4) == 0)
11699 const struct mips_cpu_info *p;
11701 p = mips_parse_cpu("internal use", name);
11703 as_bad (_("unknown ISA level %s"), name + 4);
11706 mips_opts.arch = p->cpu;
11707 mips_opts.isa = p->isa;
11711 as_bad (_("unknown ISA or architecture %s"), name);
11713 switch (mips_opts.isa)
11721 mips_opts.gp32 = 1;
11722 mips_opts.fp32 = 1;
11729 mips_opts.gp32 = 0;
11730 mips_opts.fp32 = 0;
11733 as_bad (_("unknown ISA level %s"), name + 4);
11738 mips_opts.gp32 = file_mips_gp32;
11739 mips_opts.fp32 = file_mips_fp32;
11742 else if (strcmp (name, "autoextend") == 0)
11743 mips_opts.noautoextend = 0;
11744 else if (strcmp (name, "noautoextend") == 0)
11745 mips_opts.noautoextend = 1;
11746 else if (strcmp (name, "push") == 0)
11748 struct mips_option_stack *s;
11750 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11751 s->next = mips_opts_stack;
11752 s->options = mips_opts;
11753 mips_opts_stack = s;
11755 else if (strcmp (name, "pop") == 0)
11757 struct mips_option_stack *s;
11759 s = mips_opts_stack;
11761 as_bad (_(".set pop with no .set push"));
11764 /* If we're changing the reorder mode we need to handle
11765 delay slots correctly. */
11766 if (s->options.noreorder && ! mips_opts.noreorder)
11767 mips_emit_delays (TRUE);
11768 else if (! s->options.noreorder && mips_opts.noreorder)
11770 if (prev_nop_frag != NULL)
11772 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11773 * (mips_opts.mips16 ? 2 : 4));
11774 prev_nop_frag = NULL;
11778 mips_opts = s->options;
11779 mips_opts_stack = s->next;
11783 else if (strcmp (name, "sym32") == 0)
11784 mips_opts.sym32 = TRUE;
11785 else if (strcmp (name, "nosym32") == 0)
11786 mips_opts.sym32 = FALSE;
11789 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11791 *input_line_pointer = ch;
11792 demand_empty_rest_of_line ();
11795 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11796 .option pic2. It means to generate SVR4 PIC calls. */
11799 s_abicalls (int ignore ATTRIBUTE_UNUSED)
11801 mips_pic = SVR4_PIC;
11802 mips_abicalls = TRUE;
11804 if (g_switch_seen && g_switch_value != 0)
11805 as_warn (_("-G may not be used with SVR4 PIC code"));
11806 g_switch_value = 0;
11808 bfd_set_gp_size (stdoutput, 0);
11809 demand_empty_rest_of_line ();
11812 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11813 PIC code. It sets the $gp register for the function based on the
11814 function address, which is in the register named in the argument.
11815 This uses a relocation against _gp_disp, which is handled specially
11816 by the linker. The result is:
11817 lui $gp,%hi(_gp_disp)
11818 addiu $gp,$gp,%lo(_gp_disp)
11819 addu $gp,$gp,.cpload argument
11820 The .cpload argument is normally $25 == $t9.
11822 The -mno-shared option changes this to:
11823 lui $gp,%hi(__gnu_local_gp)
11824 addiu $gp,$gp,%lo(__gnu_local_gp)
11825 and the argument is ignored. This saves an instruction, but the
11826 resulting code is not position independent; it uses an absolute
11827 address for __gnu_local_gp. Thus code assembled with -mno-shared
11828 can go into an ordinary executable, but not into a shared library. */
11831 s_cpload (int ignore ATTRIBUTE_UNUSED)
11837 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11838 .cpload is ignored. */
11839 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11845 /* .cpload should be in a .set noreorder section. */
11846 if (mips_opts.noreorder == 0)
11847 as_warn (_(".cpload not in noreorder section"));
11849 reg = tc_get_register (0);
11851 /* If we need to produce a 64-bit address, we are better off using
11852 the default instruction sequence. */
11853 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
11855 ex.X_op = O_symbol;
11856 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
11858 ex.X_op_symbol = NULL;
11859 ex.X_add_number = 0;
11861 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11862 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11865 macro_build_lui (&ex, mips_gp_register);
11866 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11867 mips_gp_register, BFD_RELOC_LO16);
11869 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
11870 mips_gp_register, reg);
11873 demand_empty_rest_of_line ();
11876 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11877 .cpsetup $reg1, offset|$reg2, label
11879 If offset is given, this results in:
11880 sd $gp, offset($sp)
11881 lui $gp, %hi(%neg(%gp_rel(label)))
11882 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11883 daddu $gp, $gp, $reg1
11885 If $reg2 is given, this results in:
11886 daddu $reg2, $gp, $0
11887 lui $gp, %hi(%neg(%gp_rel(label)))
11888 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11889 daddu $gp, $gp, $reg1
11890 $reg1 is normally $25 == $t9.
11892 The -mno-shared option replaces the last three instructions with
11894 addiu $gp,$gp,%lo(_gp)
11898 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
11900 expressionS ex_off;
11901 expressionS ex_sym;
11904 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11905 We also need NewABI support. */
11906 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11912 reg1 = tc_get_register (0);
11913 SKIP_WHITESPACE ();
11914 if (*input_line_pointer != ',')
11916 as_bad (_("missing argument separator ',' for .cpsetup"));
11920 ++input_line_pointer;
11921 SKIP_WHITESPACE ();
11922 if (*input_line_pointer == '$')
11924 mips_cpreturn_register = tc_get_register (0);
11925 mips_cpreturn_offset = -1;
11929 mips_cpreturn_offset = get_absolute_expression ();
11930 mips_cpreturn_register = -1;
11932 SKIP_WHITESPACE ();
11933 if (*input_line_pointer != ',')
11935 as_bad (_("missing argument separator ',' for .cpsetup"));
11939 ++input_line_pointer;
11940 SKIP_WHITESPACE ();
11941 expression (&ex_sym);
11944 if (mips_cpreturn_register == -1)
11946 ex_off.X_op = O_constant;
11947 ex_off.X_add_symbol = NULL;
11948 ex_off.X_op_symbol = NULL;
11949 ex_off.X_add_number = mips_cpreturn_offset;
11951 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
11952 BFD_RELOC_LO16, SP);
11955 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
11956 mips_gp_register, 0);
11958 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
11960 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
11961 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
11964 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
11965 mips_gp_register, -1, BFD_RELOC_GPREL16,
11966 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
11968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
11969 mips_gp_register, reg1);
11975 ex.X_op = O_symbol;
11976 ex.X_add_symbol = symbol_find_or_make ("_gp");
11977 ex.X_op_symbol = NULL;
11978 ex.X_add_number = 0;
11980 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11981 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11983 macro_build_lui (&ex, mips_gp_register);
11984 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11985 mips_gp_register, BFD_RELOC_LO16);
11990 demand_empty_rest_of_line ();
11994 s_cplocal (int ignore ATTRIBUTE_UNUSED)
11996 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11997 .cplocal is ignored. */
11998 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12004 mips_gp_register = tc_get_register (0);
12005 demand_empty_rest_of_line ();
12008 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12009 offset from $sp. The offset is remembered, and after making a PIC
12010 call $gp is restored from that location. */
12013 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12017 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12018 .cprestore is ignored. */
12019 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12025 mips_cprestore_offset = get_absolute_expression ();
12026 mips_cprestore_valid = 1;
12028 ex.X_op = O_constant;
12029 ex.X_add_symbol = NULL;
12030 ex.X_op_symbol = NULL;
12031 ex.X_add_number = mips_cprestore_offset;
12034 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12035 SP, HAVE_64BIT_ADDRESSES);
12038 demand_empty_rest_of_line ();
12041 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12042 was given in the preceding .cpsetup, it results in:
12043 ld $gp, offset($sp)
12045 If a register $reg2 was given there, it results in:
12046 daddu $gp, $reg2, $0
12049 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12053 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12054 We also need NewABI support. */
12055 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12062 if (mips_cpreturn_register == -1)
12064 ex.X_op = O_constant;
12065 ex.X_add_symbol = NULL;
12066 ex.X_op_symbol = NULL;
12067 ex.X_add_number = mips_cpreturn_offset;
12069 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12072 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12073 mips_cpreturn_register, 0);
12076 demand_empty_rest_of_line ();
12079 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12080 code. It sets the offset to use in gp_rel relocations. */
12083 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12085 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12086 We also need NewABI support. */
12087 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12093 mips_gprel_offset = get_absolute_expression ();
12095 demand_empty_rest_of_line ();
12098 /* Handle the .gpword pseudo-op. This is used when generating PIC
12099 code. It generates a 32 bit GP relative reloc. */
12102 s_gpword (int ignore ATTRIBUTE_UNUSED)
12108 /* When not generating PIC code, this is treated as .word. */
12109 if (mips_pic != SVR4_PIC)
12115 label = insn_labels != NULL ? insn_labels->label : NULL;
12116 mips_emit_delays (TRUE);
12118 mips_align (2, 0, label);
12119 mips_clear_insn_labels ();
12123 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12125 as_bad (_("Unsupported use of .gpword"));
12126 ignore_rest_of_line ();
12130 md_number_to_chars (p, 0, 4);
12131 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12132 BFD_RELOC_GPREL32);
12134 demand_empty_rest_of_line ();
12138 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12144 /* When not generating PIC code, this is treated as .dword. */
12145 if (mips_pic != SVR4_PIC)
12151 label = insn_labels != NULL ? insn_labels->label : NULL;
12152 mips_emit_delays (TRUE);
12154 mips_align (3, 0, label);
12155 mips_clear_insn_labels ();
12159 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12161 as_bad (_("Unsupported use of .gpdword"));
12162 ignore_rest_of_line ();
12166 md_number_to_chars (p, 0, 8);
12167 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12168 BFD_RELOC_GPREL32)->fx_tcbit = 1;
12170 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12171 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
12172 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
12174 demand_empty_rest_of_line ();
12177 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12178 tables in SVR4 PIC code. */
12181 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12185 /* This is ignored when not generating SVR4 PIC code. */
12186 if (mips_pic != SVR4_PIC)
12192 /* Add $gp to the register named as an argument. */
12194 reg = tc_get_register (0);
12195 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12198 demand_empty_rest_of_line ();
12201 /* Handle the .insn pseudo-op. This marks instruction labels in
12202 mips16 mode. This permits the linker to handle them specially,
12203 such as generating jalx instructions when needed. We also make
12204 them odd for the duration of the assembly, in order to generate the
12205 right sort of code. We will make them even in the adjust_symtab
12206 routine, while leaving them marked. This is convenient for the
12207 debugger and the disassembler. The linker knows to make them odd
12211 s_insn (int ignore ATTRIBUTE_UNUSED)
12213 mips16_mark_labels ();
12215 demand_empty_rest_of_line ();
12218 /* Handle a .stabn directive. We need these in order to mark a label
12219 as being a mips16 text label correctly. Sometimes the compiler
12220 will emit a label, followed by a .stabn, and then switch sections.
12221 If the label and .stabn are in mips16 mode, then the label is
12222 really a mips16 text label. */
12225 s_mips_stab (int type)
12228 mips16_mark_labels ();
12233 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12237 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12244 name = input_line_pointer;
12245 c = get_symbol_end ();
12246 symbolP = symbol_find_or_make (name);
12247 S_SET_WEAK (symbolP);
12248 *input_line_pointer = c;
12250 SKIP_WHITESPACE ();
12252 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12254 if (S_IS_DEFINED (symbolP))
12256 as_bad ("ignoring attempt to redefine symbol %s",
12257 S_GET_NAME (symbolP));
12258 ignore_rest_of_line ();
12262 if (*input_line_pointer == ',')
12264 ++input_line_pointer;
12265 SKIP_WHITESPACE ();
12269 if (exp.X_op != O_symbol)
12271 as_bad ("bad .weakext directive");
12272 ignore_rest_of_line ();
12275 symbol_set_value_expression (symbolP, &exp);
12278 demand_empty_rest_of_line ();
12281 /* Parse a register string into a number. Called from the ECOFF code
12282 to parse .frame. The argument is non-zero if this is the frame
12283 register, so that we can record it in mips_frame_reg. */
12286 tc_get_register (int frame)
12290 SKIP_WHITESPACE ();
12291 if (*input_line_pointer++ != '$')
12293 as_warn (_("expected `$'"));
12296 else if (ISDIGIT (*input_line_pointer))
12298 reg = get_absolute_expression ();
12299 if (reg < 0 || reg >= 32)
12301 as_warn (_("Bad register number"));
12307 if (strncmp (input_line_pointer, "ra", 2) == 0)
12310 input_line_pointer += 2;
12312 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12315 input_line_pointer += 2;
12317 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12320 input_line_pointer += 2;
12322 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12325 input_line_pointer += 2;
12327 else if (strncmp (input_line_pointer, "at", 2) == 0)
12330 input_line_pointer += 2;
12332 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12335 input_line_pointer += 3;
12337 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12340 input_line_pointer += 3;
12342 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12345 input_line_pointer += 4;
12349 as_warn (_("Unrecognized register name"));
12351 while (ISALNUM(*input_line_pointer))
12352 input_line_pointer++;
12357 mips_frame_reg = reg != 0 ? reg : SP;
12358 mips_frame_reg_valid = 1;
12359 mips_cprestore_valid = 0;
12365 md_section_align (asection *seg, valueT addr)
12367 int align = bfd_get_section_alignment (stdoutput, seg);
12370 /* We don't need to align ELF sections to the full alignment.
12371 However, Irix 5 may prefer that we align them at least to a 16
12372 byte boundary. We don't bother to align the sections if we are
12373 targeted for an embedded system. */
12374 if (strcmp (TARGET_OS, "elf") == 0)
12380 return ((addr + (1 << align) - 1) & (-1 << align));
12383 /* Utility routine, called from above as well. If called while the
12384 input file is still being read, it's only an approximation. (For
12385 example, a symbol may later become defined which appeared to be
12386 undefined earlier.) */
12389 nopic_need_relax (symbolS *sym, int before_relaxing)
12394 if (g_switch_value > 0)
12396 const char *symname;
12399 /* Find out whether this symbol can be referenced off the $gp
12400 register. It can be if it is smaller than the -G size or if
12401 it is in the .sdata or .sbss section. Certain symbols can
12402 not be referenced off the $gp, although it appears as though
12404 symname = S_GET_NAME (sym);
12405 if (symname != (const char *) NULL
12406 && (strcmp (symname, "eprol") == 0
12407 || strcmp (symname, "etext") == 0
12408 || strcmp (symname, "_gp") == 0
12409 || strcmp (symname, "edata") == 0
12410 || strcmp (symname, "_fbss") == 0
12411 || strcmp (symname, "_fdata") == 0
12412 || strcmp (symname, "_ftext") == 0
12413 || strcmp (symname, "end") == 0
12414 || strcmp (symname, "_gp_disp") == 0))
12416 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12418 #ifndef NO_ECOFF_DEBUGGING
12419 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12420 && (symbol_get_obj (sym)->ecoff_extern_size
12421 <= g_switch_value))
12423 /* We must defer this decision until after the whole
12424 file has been read, since there might be a .extern
12425 after the first use of this symbol. */
12426 || (before_relaxing
12427 #ifndef NO_ECOFF_DEBUGGING
12428 && symbol_get_obj (sym)->ecoff_extern_size == 0
12430 && S_GET_VALUE (sym) == 0)
12431 || (S_GET_VALUE (sym) != 0
12432 && S_GET_VALUE (sym) <= g_switch_value)))
12436 const char *segname;
12438 segname = segment_name (S_GET_SEGMENT (sym));
12439 assert (strcmp (segname, ".lit8") != 0
12440 && strcmp (segname, ".lit4") != 0);
12441 change = (strcmp (segname, ".sdata") != 0
12442 && strcmp (segname, ".sbss") != 0
12443 && strncmp (segname, ".sdata.", 7) != 0
12444 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12449 /* We are not optimizing for the $gp register. */
12454 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12457 pic_need_relax (symbolS *sym, asection *segtype)
12460 bfd_boolean linkonce;
12462 /* Handle the case of a symbol equated to another symbol. */
12463 while (symbol_equated_reloc_p (sym))
12467 /* It's possible to get a loop here in a badly written
12469 n = symbol_get_value_expression (sym)->X_add_symbol;
12475 symsec = S_GET_SEGMENT (sym);
12477 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12479 if (symsec != segtype && ! S_IS_LOCAL (sym))
12481 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12485 /* The GNU toolchain uses an extension for ELF: a section
12486 beginning with the magic string .gnu.linkonce is a linkonce
12488 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12489 sizeof ".gnu.linkonce" - 1) == 0)
12493 /* This must duplicate the test in adjust_reloc_syms. */
12494 return (symsec != &bfd_und_section
12495 && symsec != &bfd_abs_section
12496 && ! bfd_is_com_section (symsec)
12499 /* A global or weak symbol is treated as external. */
12500 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12501 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12507 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12508 extended opcode. SEC is the section the frag is in. */
12511 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12514 register const struct mips16_immed_operand *op;
12516 int mintiny, maxtiny;
12520 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12522 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12525 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12526 op = mips16_immed_operands;
12527 while (op->type != type)
12530 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12535 if (type == '<' || type == '>' || type == '[' || type == ']')
12538 maxtiny = 1 << op->nbits;
12543 maxtiny = (1 << op->nbits) - 1;
12548 mintiny = - (1 << (op->nbits - 1));
12549 maxtiny = (1 << (op->nbits - 1)) - 1;
12552 sym_frag = symbol_get_frag (fragp->fr_symbol);
12553 val = S_GET_VALUE (fragp->fr_symbol);
12554 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12560 /* We won't have the section when we are called from
12561 mips_relax_frag. However, we will always have been called
12562 from md_estimate_size_before_relax first. If this is a
12563 branch to a different section, we mark it as such. If SEC is
12564 NULL, and the frag is not marked, then it must be a branch to
12565 the same section. */
12568 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12573 /* Must have been called from md_estimate_size_before_relax. */
12576 fragp->fr_subtype =
12577 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12579 /* FIXME: We should support this, and let the linker
12580 catch branches and loads that are out of range. */
12581 as_bad_where (fragp->fr_file, fragp->fr_line,
12582 _("unsupported PC relative reference to different section"));
12586 if (fragp != sym_frag && sym_frag->fr_address == 0)
12587 /* Assume non-extended on the first relaxation pass.
12588 The address we have calculated will be bogus if this is
12589 a forward branch to another frag, as the forward frag
12590 will have fr_address == 0. */
12594 /* In this case, we know for sure that the symbol fragment is in
12595 the same section. If the relax_marker of the symbol fragment
12596 differs from the relax_marker of this fragment, we have not
12597 yet adjusted the symbol fragment fr_address. We want to add
12598 in STRETCH in order to get a better estimate of the address.
12599 This particularly matters because of the shift bits. */
12601 && sym_frag->relax_marker != fragp->relax_marker)
12605 /* Adjust stretch for any alignment frag. Note that if have
12606 been expanding the earlier code, the symbol may be
12607 defined in what appears to be an earlier frag. FIXME:
12608 This doesn't handle the fr_subtype field, which specifies
12609 a maximum number of bytes to skip when doing an
12611 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12613 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12616 stretch = - ((- stretch)
12617 & ~ ((1 << (int) f->fr_offset) - 1));
12619 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12628 addr = fragp->fr_address + fragp->fr_fix;
12630 /* The base address rules are complicated. The base address of
12631 a branch is the following instruction. The base address of a
12632 PC relative load or add is the instruction itself, but if it
12633 is in a delay slot (in which case it can not be extended) use
12634 the address of the instruction whose delay slot it is in. */
12635 if (type == 'p' || type == 'q')
12639 /* If we are currently assuming that this frag should be
12640 extended, then, the current address is two bytes
12642 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12645 /* Ignore the low bit in the target, since it will be set
12646 for a text label. */
12647 if ((val & 1) != 0)
12650 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12652 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12655 val -= addr & ~ ((1 << op->shift) - 1);
12657 /* Branch offsets have an implicit 0 in the lowest bit. */
12658 if (type == 'p' || type == 'q')
12661 /* If any of the shifted bits are set, we must use an extended
12662 opcode. If the address depends on the size of this
12663 instruction, this can lead to a loop, so we arrange to always
12664 use an extended opcode. We only check this when we are in
12665 the main relaxation loop, when SEC is NULL. */
12666 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12668 fragp->fr_subtype =
12669 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12673 /* If we are about to mark a frag as extended because the value
12674 is precisely maxtiny + 1, then there is a chance of an
12675 infinite loop as in the following code:
12680 In this case when the la is extended, foo is 0x3fc bytes
12681 away, so the la can be shrunk, but then foo is 0x400 away, so
12682 the la must be extended. To avoid this loop, we mark the
12683 frag as extended if it was small, and is about to become
12684 extended with a value of maxtiny + 1. */
12685 if (val == ((maxtiny + 1) << op->shift)
12686 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12689 fragp->fr_subtype =
12690 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12694 else if (symsec != absolute_section && sec != NULL)
12695 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12697 if ((val & ((1 << op->shift) - 1)) != 0
12698 || val < (mintiny << op->shift)
12699 || val > (maxtiny << op->shift))
12705 /* Compute the length of a branch sequence, and adjust the
12706 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12707 worst-case length is computed, with UPDATE being used to indicate
12708 whether an unconditional (-1), branch-likely (+1) or regular (0)
12709 branch is to be computed. */
12711 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12713 bfd_boolean toofar;
12717 && S_IS_DEFINED (fragp->fr_symbol)
12718 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12723 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12725 addr = fragp->fr_address + fragp->fr_fix + 4;
12729 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12732 /* If the symbol is not defined or it's in a different segment,
12733 assume the user knows what's going on and emit a short
12739 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12741 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12742 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12743 RELAX_BRANCH_LINK (fragp->fr_subtype),
12749 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12752 if (mips_pic != NO_PIC)
12754 /* Additional space for PIC loading of target address. */
12756 if (mips_opts.isa == ISA_MIPS1)
12757 /* Additional space for $at-stabilizing nop. */
12761 /* If branch is conditional. */
12762 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12769 /* Estimate the size of a frag before relaxing. Unless this is the
12770 mips16, we are not really relaxing here, and the final size is
12771 encoded in the subtype information. For the mips16, we have to
12772 decide whether we are using an extended opcode or not. */
12775 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12779 if (RELAX_BRANCH_P (fragp->fr_subtype))
12782 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12784 return fragp->fr_var;
12787 if (RELAX_MIPS16_P (fragp->fr_subtype))
12788 /* We don't want to modify the EXTENDED bit here; it might get us
12789 into infinite loops. We change it only in mips_relax_frag(). */
12790 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12792 if (mips_pic == NO_PIC)
12793 change = nopic_need_relax (fragp->fr_symbol, 0);
12794 else if (mips_pic == SVR4_PIC)
12795 change = pic_need_relax (fragp->fr_symbol, segtype);
12801 fragp->fr_subtype |= RELAX_USE_SECOND;
12802 return -RELAX_FIRST (fragp->fr_subtype);
12805 return -RELAX_SECOND (fragp->fr_subtype);
12808 /* This is called to see whether a reloc against a defined symbol
12809 should be converted into a reloc against a section. */
12812 mips_fix_adjustable (fixS *fixp)
12814 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12815 about the format of the offset in the .o file. */
12816 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12819 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12820 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12823 if (fixp->fx_addsy == NULL)
12826 /* If symbol SYM is in a mergeable section, relocations of the form
12827 SYM + 0 can usually be made section-relative. The mergeable data
12828 is then identified by the section offset rather than by the symbol.
12830 However, if we're generating REL LO16 relocations, the offset is split
12831 between the LO16 and parterning high part relocation. The linker will
12832 need to recalculate the complete offset in order to correctly identify
12835 The linker has traditionally not looked for the parterning high part
12836 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12837 placed anywhere. Rather than break backwards compatibility by changing
12838 this, it seems better not to force the issue, and instead keep the
12839 original symbol. This will work with either linker behavior. */
12840 if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
12841 && HAVE_IN_PLACE_ADDENDS
12842 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
12846 /* Don't adjust relocations against mips16 symbols, so that the linker
12847 can find them if it needs to set up a stub. */
12848 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12849 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12850 && fixp->fx_subsy == NULL)
12857 /* Translate internal representation of relocation info to BFD target
12861 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12863 static arelent *retval[4];
12865 bfd_reloc_code_real_type code;
12867 memset (retval, 0, sizeof(retval));
12868 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
12869 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12870 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12871 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12873 assert (! fixp->fx_pcrel);
12874 reloc->addend = fixp->fx_addnumber;
12876 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12877 entry to be used in the relocation's section offset. */
12878 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12880 reloc->address = reloc->addend;
12884 code = fixp->fx_r_type;
12886 /* To support a PC relative reloc, we used a Cygnus extension.
12887 We check for that here to make sure that we don't let such a
12888 reloc escape normally. (FIXME: This was formerly used by
12889 embedded-PIC support, but is now used by branch handling in
12890 general. That probably should be fixed.) */
12891 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12892 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12893 && code == BFD_RELOC_16_PCREL_S2)
12894 reloc->howto = NULL;
12896 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12898 if (reloc->howto == NULL)
12900 as_bad_where (fixp->fx_file, fixp->fx_line,
12901 _("Can not represent %s relocation in this object file format"),
12902 bfd_get_reloc_code_name (code));
12909 /* Relax a machine dependent frag. This returns the amount by which
12910 the current size of the frag should change. */
12913 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
12915 if (RELAX_BRANCH_P (fragp->fr_subtype))
12917 offsetT old_var = fragp->fr_var;
12919 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
12921 return fragp->fr_var - old_var;
12924 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12927 if (mips16_extended_frag (fragp, NULL, stretch))
12929 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12931 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12936 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12938 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12945 /* Convert a machine dependent frag. */
12948 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
12950 if (RELAX_BRANCH_P (fragp->fr_subtype))
12953 unsigned long insn;
12957 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
12959 if (target_big_endian)
12960 insn = bfd_getb32 (buf);
12962 insn = bfd_getl32 (buf);
12964 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12966 /* We generate a fixup instead of applying it right now
12967 because, if there are linker relaxations, we're going to
12968 need the relocations. */
12969 exp.X_op = O_symbol;
12970 exp.X_add_symbol = fragp->fr_symbol;
12971 exp.X_add_number = fragp->fr_offset;
12973 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
12975 BFD_RELOC_16_PCREL_S2);
12976 fixp->fx_file = fragp->fr_file;
12977 fixp->fx_line = fragp->fr_line;
12979 md_number_to_chars ((char *) buf, insn, 4);
12986 as_warn_where (fragp->fr_file, fragp->fr_line,
12987 _("relaxed out-of-range branch into a jump"));
12989 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
12992 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12994 /* Reverse the branch. */
12995 switch ((insn >> 28) & 0xf)
12998 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12999 have the condition reversed by tweaking a single
13000 bit, and their opcodes all have 0x4???????. */
13001 assert ((insn & 0xf1000000) == 0x41000000);
13002 insn ^= 0x00010000;
13006 /* bltz 0x04000000 bgez 0x04010000
13007 bltzal 0x04100000 bgezal 0x04110000 */
13008 assert ((insn & 0xfc0e0000) == 0x04000000);
13009 insn ^= 0x00010000;
13013 /* beq 0x10000000 bne 0x14000000
13014 blez 0x18000000 bgtz 0x1c000000 */
13015 insn ^= 0x04000000;
13023 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13025 /* Clear the and-link bit. */
13026 assert ((insn & 0xfc1c0000) == 0x04100000);
13028 /* bltzal 0x04100000 bgezal 0x04110000
13029 bltzall 0x04120000 bgezall 0x04130000 */
13030 insn &= ~0x00100000;
13033 /* Branch over the branch (if the branch was likely) or the
13034 full jump (not likely case). Compute the offset from the
13035 current instruction to branch to. */
13036 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13040 /* How many bytes in instructions we've already emitted? */
13041 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13042 /* How many bytes in instructions from here to the end? */
13043 i = fragp->fr_var - i;
13045 /* Convert to instruction count. */
13047 /* Branch counts from the next instruction. */
13050 /* Branch over the jump. */
13051 md_number_to_chars ((char *) buf, insn, 4);
13055 md_number_to_chars ((char *) buf, 0, 4);
13058 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13060 /* beql $0, $0, 2f */
13062 /* Compute the PC offset from the current instruction to
13063 the end of the variable frag. */
13064 /* How many bytes in instructions we've already emitted? */
13065 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13066 /* How many bytes in instructions from here to the end? */
13067 i = fragp->fr_var - i;
13068 /* Convert to instruction count. */
13070 /* Don't decrement i, because we want to branch over the
13074 md_number_to_chars ((char *) buf, insn, 4);
13077 md_number_to_chars ((char *) buf, 0, 4);
13082 if (mips_pic == NO_PIC)
13085 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13086 ? 0x0c000000 : 0x08000000);
13087 exp.X_op = O_symbol;
13088 exp.X_add_symbol = fragp->fr_symbol;
13089 exp.X_add_number = fragp->fr_offset;
13091 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13092 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13093 fixp->fx_file = fragp->fr_file;
13094 fixp->fx_line = fragp->fr_line;
13096 md_number_to_chars ((char *) buf, insn, 4);
13101 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13102 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13103 exp.X_op = O_symbol;
13104 exp.X_add_symbol = fragp->fr_symbol;
13105 exp.X_add_number = fragp->fr_offset;
13107 if (fragp->fr_offset)
13109 exp.X_add_symbol = make_expr_symbol (&exp);
13110 exp.X_add_number = 0;
13113 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13114 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13115 fixp->fx_file = fragp->fr_file;
13116 fixp->fx_line = fragp->fr_line;
13118 md_number_to_chars ((char *) buf, insn, 4);
13121 if (mips_opts.isa == ISA_MIPS1)
13124 md_number_to_chars ((char *) buf, 0, 4);
13128 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13129 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13131 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13132 4, &exp, 0, BFD_RELOC_LO16);
13133 fixp->fx_file = fragp->fr_file;
13134 fixp->fx_line = fragp->fr_line;
13136 md_number_to_chars ((char *) buf, insn, 4);
13140 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13145 md_number_to_chars ((char *) buf, insn, 4);
13150 assert (buf == (bfd_byte *)fragp->fr_literal
13151 + fragp->fr_fix + fragp->fr_var);
13153 fragp->fr_fix += fragp->fr_var;
13158 if (RELAX_MIPS16_P (fragp->fr_subtype))
13161 register const struct mips16_immed_operand *op;
13162 bfd_boolean small, ext;
13165 unsigned long insn;
13166 bfd_boolean use_extend;
13167 unsigned short extend;
13169 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13170 op = mips16_immed_operands;
13171 while (op->type != type)
13174 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13185 resolve_symbol_value (fragp->fr_symbol);
13186 val = S_GET_VALUE (fragp->fr_symbol);
13191 addr = fragp->fr_address + fragp->fr_fix;
13193 /* The rules for the base address of a PC relative reloc are
13194 complicated; see mips16_extended_frag. */
13195 if (type == 'p' || type == 'q')
13200 /* Ignore the low bit in the target, since it will be
13201 set for a text label. */
13202 if ((val & 1) != 0)
13205 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13207 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13210 addr &= ~ (addressT) ((1 << op->shift) - 1);
13213 /* Make sure the section winds up with the alignment we have
13216 record_alignment (asec, op->shift);
13220 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13221 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13222 as_warn_where (fragp->fr_file, fragp->fr_line,
13223 _("extended instruction in delay slot"));
13225 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13227 if (target_big_endian)
13228 insn = bfd_getb16 (buf);
13230 insn = bfd_getl16 (buf);
13232 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13233 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13234 small, ext, &insn, &use_extend, &extend);
13238 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13239 fragp->fr_fix += 2;
13243 md_number_to_chars ((char *) buf, insn, 2);
13244 fragp->fr_fix += 2;
13252 first = RELAX_FIRST (fragp->fr_subtype);
13253 second = RELAX_SECOND (fragp->fr_subtype);
13254 fixp = (fixS *) fragp->fr_opcode;
13256 /* Possibly emit a warning if we've chosen the longer option. */
13257 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13258 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13260 const char *msg = macro_warning (fragp->fr_subtype);
13262 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13265 /* Go through all the fixups for the first sequence. Disable them
13266 (by marking them as done) if we're going to use the second
13267 sequence instead. */
13269 && fixp->fx_frag == fragp
13270 && fixp->fx_where < fragp->fr_fix - second)
13272 if (fragp->fr_subtype & RELAX_USE_SECOND)
13274 fixp = fixp->fx_next;
13277 /* Go through the fixups for the second sequence. Disable them if
13278 we're going to use the first sequence, otherwise adjust their
13279 addresses to account for the relaxation. */
13280 while (fixp && fixp->fx_frag == fragp)
13282 if (fragp->fr_subtype & RELAX_USE_SECOND)
13283 fixp->fx_where -= first;
13286 fixp = fixp->fx_next;
13289 /* Now modify the frag contents. */
13290 if (fragp->fr_subtype & RELAX_USE_SECOND)
13294 start = fragp->fr_literal + fragp->fr_fix - first - second;
13295 memmove (start, start + first, second);
13296 fragp->fr_fix -= first;
13299 fragp->fr_fix -= second;
13305 /* This function is called after the relocs have been generated.
13306 We've been storing mips16 text labels as odd. Here we convert them
13307 back to even for the convenience of the debugger. */
13310 mips_frob_file_after_relocs (void)
13313 unsigned int count, i;
13315 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13318 syms = bfd_get_outsymbols (stdoutput);
13319 count = bfd_get_symcount (stdoutput);
13320 for (i = 0; i < count; i++, syms++)
13322 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13323 && ((*syms)->value & 1) != 0)
13325 (*syms)->value &= ~1;
13326 /* If the symbol has an odd size, it was probably computed
13327 incorrectly, so adjust that as well. */
13328 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13329 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13336 /* This function is called whenever a label is defined. It is used
13337 when handling branch delays; if a branch has a label, we assume we
13338 can not move it. */
13341 mips_define_label (symbolS *sym)
13343 struct insn_label_list *l;
13345 if (free_insn_labels == NULL)
13346 l = (struct insn_label_list *) xmalloc (sizeof *l);
13349 l = free_insn_labels;
13350 free_insn_labels = l->next;
13354 l->next = insn_labels;
13358 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13360 /* Some special processing for a MIPS ELF file. */
13363 mips_elf_final_processing (void)
13365 /* Write out the register information. */
13366 if (mips_abi != N64_ABI)
13370 s.ri_gprmask = mips_gprmask;
13371 s.ri_cprmask[0] = mips_cprmask[0];
13372 s.ri_cprmask[1] = mips_cprmask[1];
13373 s.ri_cprmask[2] = mips_cprmask[2];
13374 s.ri_cprmask[3] = mips_cprmask[3];
13375 /* The gp_value field is set by the MIPS ELF backend. */
13377 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13378 ((Elf32_External_RegInfo *)
13379 mips_regmask_frag));
13383 Elf64_Internal_RegInfo s;
13385 s.ri_gprmask = mips_gprmask;
13387 s.ri_cprmask[0] = mips_cprmask[0];
13388 s.ri_cprmask[1] = mips_cprmask[1];
13389 s.ri_cprmask[2] = mips_cprmask[2];
13390 s.ri_cprmask[3] = mips_cprmask[3];
13391 /* The gp_value field is set by the MIPS ELF backend. */
13393 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13394 ((Elf64_External_RegInfo *)
13395 mips_regmask_frag));
13398 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13399 sort of BFD interface for this. */
13400 if (mips_any_noreorder)
13401 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13402 if (mips_pic != NO_PIC)
13404 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13405 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13408 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13410 /* Set MIPS ELF flags for ASEs. */
13411 if (file_ase_mips16)
13412 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13413 #if 0 /* XXX FIXME */
13414 if (file_ase_mips3d)
13415 elf_elfheader (stdoutput)->e_flags |= ???;
13418 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13420 /* Set the MIPS ELF ABI flags. */
13421 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13422 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13423 else if (mips_abi == O64_ABI)
13424 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13425 else if (mips_abi == EABI_ABI)
13427 if (!file_mips_gp32)
13428 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13430 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13432 else if (mips_abi == N32_ABI)
13433 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13435 /* Nothing to do for N64_ABI. */
13437 if (mips_32bitmode)
13438 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13441 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13443 typedef struct proc {
13445 symbolS *func_end_sym;
13446 unsigned long reg_mask;
13447 unsigned long reg_offset;
13448 unsigned long fpreg_mask;
13449 unsigned long fpreg_offset;
13450 unsigned long frame_offset;
13451 unsigned long frame_reg;
13452 unsigned long pc_reg;
13455 static procS cur_proc;
13456 static procS *cur_proc_ptr;
13457 static int numprocs;
13459 /* Fill in an rs_align_code fragment. */
13462 mips_handle_align (fragS *fragp)
13464 if (fragp->fr_type != rs_align_code)
13467 if (mips_opts.mips16)
13469 static const unsigned char be_nop[] = { 0x65, 0x00 };
13470 static const unsigned char le_nop[] = { 0x00, 0x65 };
13475 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13476 p = fragp->fr_literal + fragp->fr_fix;
13484 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13488 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13492 md_obj_begin (void)
13499 /* check for premature end, nesting errors, etc */
13501 as_warn (_("missing .end at end of assembly"));
13510 if (*input_line_pointer == '-')
13512 ++input_line_pointer;
13515 if (!ISDIGIT (*input_line_pointer))
13516 as_bad (_("expected simple number"));
13517 if (input_line_pointer[0] == '0')
13519 if (input_line_pointer[1] == 'x')
13521 input_line_pointer += 2;
13522 while (ISXDIGIT (*input_line_pointer))
13525 val |= hex_value (*input_line_pointer++);
13527 return negative ? -val : val;
13531 ++input_line_pointer;
13532 while (ISDIGIT (*input_line_pointer))
13535 val |= *input_line_pointer++ - '0';
13537 return negative ? -val : val;
13540 if (!ISDIGIT (*input_line_pointer))
13542 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13543 *input_line_pointer, *input_line_pointer);
13544 as_warn (_("invalid number"));
13547 while (ISDIGIT (*input_line_pointer))
13550 val += *input_line_pointer++ - '0';
13552 return negative ? -val : val;
13555 /* The .file directive; just like the usual .file directive, but there
13556 is an initial number which is the ECOFF file index. In the non-ECOFF
13557 case .file implies DWARF-2. */
13560 s_mips_file (int x ATTRIBUTE_UNUSED)
13562 static int first_file_directive = 0;
13564 if (ECOFF_DEBUGGING)
13573 filename = dwarf2_directive_file (0);
13575 /* Versions of GCC up to 3.1 start files with a ".file"
13576 directive even for stabs output. Make sure that this
13577 ".file" is handled. Note that you need a version of GCC
13578 after 3.1 in order to support DWARF-2 on MIPS. */
13579 if (filename != NULL && ! first_file_directive)
13581 (void) new_logical_line (filename, -1);
13582 s_app_file_string (filename, 0);
13584 first_file_directive = 1;
13588 /* The .loc directive, implying DWARF-2. */
13591 s_mips_loc (int x ATTRIBUTE_UNUSED)
13593 if (!ECOFF_DEBUGGING)
13594 dwarf2_directive_loc (0);
13597 /* The .end directive. */
13600 s_mips_end (int x ATTRIBUTE_UNUSED)
13604 /* Following functions need their own .frame and .cprestore directives. */
13605 mips_frame_reg_valid = 0;
13606 mips_cprestore_valid = 0;
13608 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13611 demand_empty_rest_of_line ();
13616 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13617 as_warn (_(".end not in text section"));
13621 as_warn (_(".end directive without a preceding .ent directive."));
13622 demand_empty_rest_of_line ();
13628 assert (S_GET_NAME (p));
13629 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
13630 as_warn (_(".end symbol does not match .ent symbol."));
13632 if (debug_type == DEBUG_STABS)
13633 stabs_generate_asm_endfunc (S_GET_NAME (p),
13637 as_warn (_(".end directive missing or unknown symbol"));
13640 /* Create an expression to calculate the size of the function. */
13641 if (p && cur_proc_ptr)
13643 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
13644 expressionS *exp = xmalloc (sizeof (expressionS));
13647 exp->X_op = O_subtract;
13648 exp->X_add_symbol = symbol_temp_new_now ();
13649 exp->X_op_symbol = p;
13650 exp->X_add_number = 0;
13652 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
13655 /* Generate a .pdr section. */
13656 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13659 segT saved_seg = now_seg;
13660 subsegT saved_subseg = now_subseg;
13665 dot = frag_now_fix ();
13667 #ifdef md_flush_pending_output
13668 md_flush_pending_output ();
13672 subseg_set (pdr_seg, 0);
13674 /* Write the symbol. */
13675 exp.X_op = O_symbol;
13676 exp.X_add_symbol = p;
13677 exp.X_add_number = 0;
13678 emit_expr (&exp, 4);
13680 fragp = frag_more (7 * 4);
13682 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13683 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13684 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13685 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13686 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13687 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13688 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13690 subseg_set (saved_seg, saved_subseg);
13692 #endif /* OBJ_ELF */
13694 cur_proc_ptr = NULL;
13697 /* The .aent and .ent directives. */
13700 s_mips_ent (int aent)
13704 symbolP = get_symbol ();
13705 if (*input_line_pointer == ',')
13706 ++input_line_pointer;
13707 SKIP_WHITESPACE ();
13708 if (ISDIGIT (*input_line_pointer)
13709 || *input_line_pointer == '-')
13712 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13713 as_warn (_(".ent or .aent not in text section."));
13715 if (!aent && cur_proc_ptr)
13716 as_warn (_("missing .end"));
13720 /* This function needs its own .frame and .cprestore directives. */
13721 mips_frame_reg_valid = 0;
13722 mips_cprestore_valid = 0;
13724 cur_proc_ptr = &cur_proc;
13725 memset (cur_proc_ptr, '\0', sizeof (procS));
13727 cur_proc_ptr->func_sym = symbolP;
13729 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13733 if (debug_type == DEBUG_STABS)
13734 stabs_generate_asm_func (S_GET_NAME (symbolP),
13735 S_GET_NAME (symbolP));
13738 demand_empty_rest_of_line ();
13741 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13742 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13743 s_mips_frame is used so that we can set the PDR information correctly.
13744 We can't use the ecoff routines because they make reference to the ecoff
13745 symbol table (in the mdebug section). */
13748 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13751 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13755 if (cur_proc_ptr == (procS *) NULL)
13757 as_warn (_(".frame outside of .ent"));
13758 demand_empty_rest_of_line ();
13762 cur_proc_ptr->frame_reg = tc_get_register (1);
13764 SKIP_WHITESPACE ();
13765 if (*input_line_pointer++ != ','
13766 || get_absolute_expression_and_terminator (&val) != ',')
13768 as_warn (_("Bad .frame directive"));
13769 --input_line_pointer;
13770 demand_empty_rest_of_line ();
13774 cur_proc_ptr->frame_offset = val;
13775 cur_proc_ptr->pc_reg = tc_get_register (0);
13777 demand_empty_rest_of_line ();
13780 #endif /* OBJ_ELF */
13784 /* The .fmask and .mask directives. If the mdebug section is present
13785 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13786 embedded targets, s_mips_mask is used so that we can set the PDR
13787 information correctly. We can't use the ecoff routines because they
13788 make reference to the ecoff symbol table (in the mdebug section). */
13791 s_mips_mask (int reg_type)
13794 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13798 if (cur_proc_ptr == (procS *) NULL)
13800 as_warn (_(".mask/.fmask outside of .ent"));
13801 demand_empty_rest_of_line ();
13805 if (get_absolute_expression_and_terminator (&mask) != ',')
13807 as_warn (_("Bad .mask/.fmask directive"));
13808 --input_line_pointer;
13809 demand_empty_rest_of_line ();
13813 off = get_absolute_expression ();
13815 if (reg_type == 'F')
13817 cur_proc_ptr->fpreg_mask = mask;
13818 cur_proc_ptr->fpreg_offset = off;
13822 cur_proc_ptr->reg_mask = mask;
13823 cur_proc_ptr->reg_offset = off;
13826 demand_empty_rest_of_line ();
13829 #endif /* OBJ_ELF */
13830 s_ignore (reg_type);
13833 /* A table describing all the processors gas knows about. Names are
13834 matched in the order listed.
13836 To ease comparison, please keep this table in the same order as
13837 gcc's mips_cpu_info_table[]. */
13838 static const struct mips_cpu_info mips_cpu_info_table[] =
13840 /* Entries for generic ISAs */
13841 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13842 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13843 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13844 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13845 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13846 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13847 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
13848 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13849 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
13852 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13853 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13854 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13857 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13860 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13861 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13862 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13863 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13864 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
13865 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
13866 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
13867 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13868 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13869 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13870 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13871 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13874 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13875 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13876 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13877 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13878 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
13879 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
13880 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13881 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13882 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13883 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13884 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13885 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
13886 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
13889 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
13890 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13891 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13894 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13895 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13897 /* Broadcom SB-1 CPU core */
13898 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13905 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13906 with a final "000" replaced by "k". Ignore case.
13908 Note: this function is shared between GCC and GAS. */
13911 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13913 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13914 given++, canonical++;
13916 return ((*given == 0 && *canonical == 0)
13917 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13921 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13922 CPU name. We've traditionally allowed a lot of variation here.
13924 Note: this function is shared between GCC and GAS. */
13927 mips_matching_cpu_name_p (const char *canonical, const char *given)
13929 /* First see if the name matches exactly, or with a final "000"
13930 turned into "k". */
13931 if (mips_strict_matching_cpu_name_p (canonical, given))
13934 /* If not, try comparing based on numerical designation alone.
13935 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13936 if (TOLOWER (*given) == 'r')
13938 if (!ISDIGIT (*given))
13941 /* Skip over some well-known prefixes in the canonical name,
13942 hoping to find a number there too. */
13943 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13945 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13947 else if (TOLOWER (canonical[0]) == 'r')
13950 return mips_strict_matching_cpu_name_p (canonical, given);
13954 /* Parse an option that takes the name of a processor as its argument.
13955 OPTION is the name of the option and CPU_STRING is the argument.
13956 Return the corresponding processor enumeration if the CPU_STRING is
13957 recognized, otherwise report an error and return null.
13959 A similar function exists in GCC. */
13961 static const struct mips_cpu_info *
13962 mips_parse_cpu (const char *option, const char *cpu_string)
13964 const struct mips_cpu_info *p;
13966 /* 'from-abi' selects the most compatible architecture for the given
13967 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13968 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13969 version. Look first at the -mgp options, if given, otherwise base
13970 the choice on MIPS_DEFAULT_64BIT.
13972 Treat NO_ABI like the EABIs. One reason to do this is that the
13973 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13974 architecture. This code picks MIPS I for 'mips' and MIPS III for
13975 'mips64', just as we did in the days before 'from-abi'. */
13976 if (strcasecmp (cpu_string, "from-abi") == 0)
13978 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13979 return mips_cpu_info_from_isa (ISA_MIPS1);
13981 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13982 return mips_cpu_info_from_isa (ISA_MIPS3);
13984 if (file_mips_gp32 >= 0)
13985 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13987 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13992 /* 'default' has traditionally been a no-op. Probably not very useful. */
13993 if (strcasecmp (cpu_string, "default") == 0)
13996 for (p = mips_cpu_info_table; p->name != 0; p++)
13997 if (mips_matching_cpu_name_p (p->name, cpu_string))
14000 as_bad ("Bad value (%s) for %s", cpu_string, option);
14004 /* Return the canonical processor information for ISA (a member of the
14005 ISA_MIPS* enumeration). */
14007 static const struct mips_cpu_info *
14008 mips_cpu_info_from_isa (int isa)
14012 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14013 if (mips_cpu_info_table[i].is_isa
14014 && isa == mips_cpu_info_table[i].isa)
14015 return (&mips_cpu_info_table[i]);
14020 static const struct mips_cpu_info *
14021 mips_cpu_info_from_arch (int arch)
14025 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14026 if (arch == mips_cpu_info_table[i].cpu)
14027 return (&mips_cpu_info_table[i]);
14033 show (FILE *stream, const char *string, int *col_p, int *first_p)
14037 fprintf (stream, "%24s", "");
14042 fprintf (stream, ", ");
14046 if (*col_p + strlen (string) > 72)
14048 fprintf (stream, "\n%24s", "");
14052 fprintf (stream, "%s", string);
14053 *col_p += strlen (string);
14059 md_show_usage (FILE *stream)
14064 fprintf (stream, _("\
14066 -EB generate big endian output\n\
14067 -EL generate little endian output\n\
14068 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14069 -G NUM allow referencing objects up to NUM bytes\n\
14070 implicitly with the gp register [default 8]\n"));
14071 fprintf (stream, _("\
14072 -mips1 generate MIPS ISA I instructions\n\
14073 -mips2 generate MIPS ISA II instructions\n\
14074 -mips3 generate MIPS ISA III instructions\n\
14075 -mips4 generate MIPS ISA IV instructions\n\
14076 -mips5 generate MIPS ISA V instructions\n\
14077 -mips32 generate MIPS32 ISA instructions\n\
14078 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14079 -mips64 generate MIPS64 ISA instructions\n\
14080 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14081 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14085 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14086 show (stream, mips_cpu_info_table[i].name, &column, &first);
14087 show (stream, "from-abi", &column, &first);
14088 fputc ('\n', stream);
14090 fprintf (stream, _("\
14091 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14092 -no-mCPU don't generate code specific to CPU.\n\
14093 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14097 show (stream, "3900", &column, &first);
14098 show (stream, "4010", &column, &first);
14099 show (stream, "4100", &column, &first);
14100 show (stream, "4650", &column, &first);
14101 fputc ('\n', stream);
14103 fprintf (stream, _("\
14104 -mips16 generate mips16 instructions\n\
14105 -no-mips16 do not generate mips16 instructions\n"));
14106 fprintf (stream, _("\
14107 -mfix-vr4120 work around certain VR4120 errata\n\
14108 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14109 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14110 -mno-shared optimize output for executables\n\
14111 -msym32 assume all symbols have 32-bit values\n\
14112 -O0 remove unneeded NOPs, do not swap branches\n\
14113 -O remove unneeded NOPs and swap branches\n\
14114 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14115 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14116 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14118 fprintf (stream, _("\
14119 -KPIC, -call_shared generate SVR4 position independent code\n\
14120 -non_shared do not generate position independent code\n\
14121 -xgot assume a 32 bit GOT\n\
14122 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14123 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14125 -mabi=ABI create ABI conformant object file for:\n"));
14129 show (stream, "32", &column, &first);
14130 show (stream, "o64", &column, &first);
14131 show (stream, "n32", &column, &first);
14132 show (stream, "64", &column, &first);
14133 show (stream, "eabi", &column, &first);
14135 fputc ('\n', stream);
14137 fprintf (stream, _("\
14138 -32 create o32 ABI object file (default)\n\
14139 -n32 create n32 ABI object file\n\
14140 -64 create 64 ABI object file\n"));
14145 mips_dwarf2_format (void)
14147 if (mips_abi == N64_ABI)
14150 return dwarf2_format_64bit_irix;
14152 return dwarf2_format_64bit;
14156 return dwarf2_format_32bit;
14160 mips_dwarf2_addr_size (void)
14162 if (mips_abi == N64_ABI)