1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* True if mflo and mfhi can be immediately followed by instructions
329 which write to the HI and LO registers.
331 According to MIPS specifications, MIPS ISAs I, II, and III need
332 (at least) two instructions between the reads of HI/LO and
333 instructions which write them, and later ISAs do not. Contradicting
334 the MIPS specifications, some MIPS IV processor user manuals (e.g.
335 the UM for the NEC Vr5000) document needing the instructions between
336 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
337 MIPS64 and later ISAs to have the interlocks, plus any specific
338 earlier-ISA CPUs for which CPU documentation declares that the
339 instructions are really interlocked. */
340 #define hilo_interlocks \
341 (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64 \
344 || mips_opts.isa == ISA_MIPS64R2 \
345 || mips_opts.arch == CPU_R4010 \
346 || mips_opts.arch == CPU_R10000 \
347 || mips_opts.arch == CPU_R12000 \
348 || mips_opts.arch == CPU_RM7000 \
349 || mips_opts.arch == CPU_VR5500 \
352 /* Whether the processor uses hardware interlocks to protect reads
353 from the GPRs after they are loaded from memory, and thus does not
354 require nops to be inserted. This applies to instructions marked
355 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
357 #define gpr_interlocks \
358 (mips_opts.isa != ISA_MIPS1 \
359 || mips_opts.arch == CPU_R3900)
361 /* Whether the processor uses hardware interlocks to avoid delays
362 required by coprocessor instructions, and thus does not require
363 nops to be inserted. This applies to instructions marked
364 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
365 between instructions marked INSN_WRITE_COND_CODE and ones marked
366 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
367 levels I, II, and III. */
368 /* Itbl support may require additional care here. */
369 #define cop_interlocks \
370 ((mips_opts.isa != ISA_MIPS1 \
371 && mips_opts.isa != ISA_MIPS2 \
372 && mips_opts.isa != ISA_MIPS3) \
373 || mips_opts.arch == CPU_R4300 \
376 /* Whether the processor uses hardware interlocks to protect reads
377 from coprocessor registers after they are loaded from memory, and
378 thus does not require nops to be inserted. This applies to
379 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
380 requires at MIPS ISA level I. */
381 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
383 /* Is this a mfhi or mflo instruction? */
384 #define MF_HILO_INSN(PINFO) \
385 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
387 /* MIPS PIC level. */
389 enum mips_pic_level mips_pic;
391 /* 1 if we should generate 32 bit offsets from the $gp register in
392 SVR4_PIC mode. Currently has no meaning in other modes. */
393 static int mips_big_got = 0;
395 /* 1 if trap instructions should used for overflow rather than break
397 static int mips_trap = 0;
399 /* 1 if double width floating point constants should not be constructed
400 by assembling two single width halves into two single width floating
401 point registers which just happen to alias the double width destination
402 register. On some architectures this aliasing can be disabled by a bit
403 in the status register, and the setting of this bit cannot be determined
404 automatically at assemble time. */
405 static int mips_disable_float_construction;
407 /* Non-zero if any .set noreorder directives were used. */
409 static int mips_any_noreorder;
411 /* Non-zero if nops should be inserted when the register referenced in
412 an mfhi/mflo instruction is read in the next two instructions. */
413 static int mips_7000_hilo_fix;
415 /* The size of the small data section. */
416 static unsigned int g_switch_value = 8;
417 /* Whether the -G option was used. */
418 static int g_switch_seen = 0;
423 /* If we can determine in advance that GP optimization won't be
424 possible, we can skip the relaxation stuff that tries to produce
425 GP-relative references. This makes delay slot optimization work
428 This function can only provide a guess, but it seems to work for
429 gcc output. It needs to guess right for gcc, otherwise gcc
430 will put what it thinks is a GP-relative instruction in a branch
433 I don't know if a fix is needed for the SVR4_PIC mode. I've only
434 fixed it for the non-PIC mode. KR 95/04/07 */
435 static int nopic_need_relax (symbolS *, int);
437 /* handle of the OPCODE hash table */
438 static struct hash_control *op_hash = NULL;
440 /* The opcode hash table we use for the mips16. */
441 static struct hash_control *mips16_op_hash = NULL;
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful */
445 const char comment_chars[] = "#";
447 /* This array holds the chars that only start a comment at the beginning of
448 a line. If the line seems to have the form '# 123 filename'
449 .line and .file directives will appear in the pre-processed output */
450 /* Note that input_file.c hand checks for '#' at the beginning of the
451 first line of the input file. This is because the compiler outputs
452 #NO_APP at the beginning of its output. */
453 /* Also note that C style comments are always supported. */
454 const char line_comment_chars[] = "#";
456 /* This array holds machine specific line separator characters. */
457 const char line_separator_chars[] = ";";
459 /* Chars that can be used to separate mant from exp in floating point nums */
460 const char EXP_CHARS[] = "eE";
462 /* Chars that mean this number is a floating point constant */
465 const char FLT_CHARS[] = "rRsSfFdDxXpP";
467 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
468 changed in read.c . Ideally it shouldn't have to know about it at all,
469 but nothing is ideal around here.
472 static char *insn_error;
474 static int auto_align = 1;
476 /* When outputting SVR4 PIC code, the assembler needs to know the
477 offset in the stack frame from which to restore the $gp register.
478 This is set by the .cprestore pseudo-op, and saved in this
480 static offsetT mips_cprestore_offset = -1;
482 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
483 more optimizations, it can use a register value instead of a memory-saved
484 offset and even an other register than $gp as global pointer. */
485 static offsetT mips_cpreturn_offset = -1;
486 static int mips_cpreturn_register = -1;
487 static int mips_gp_register = GP;
488 static int mips_gprel_offset = 0;
490 /* Whether mips_cprestore_offset has been set in the current function
491 (or whether it has already been warned about, if not). */
492 static int mips_cprestore_valid = 0;
494 /* This is the register which holds the stack frame, as set by the
495 .frame pseudo-op. This is needed to implement .cprestore. */
496 static int mips_frame_reg = SP;
498 /* Whether mips_frame_reg has been set in the current function
499 (or whether it has already been warned about, if not). */
500 static int mips_frame_reg_valid = 0;
502 /* To output NOP instructions correctly, we need to keep information
503 about the previous two instructions. */
505 /* Whether we are optimizing. The default value of 2 means to remove
506 unneeded NOPs and swap branch instructions when possible. A value
507 of 1 means to not swap branches. A value of 0 means to always
509 static int mips_optimize = 2;
511 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
512 equivalent to seeing no -g option at all. */
513 static int mips_debug = 0;
515 /* The previous instruction. */
516 static struct mips_cl_insn prev_insn;
518 /* The instruction before prev_insn. */
519 static struct mips_cl_insn prev_prev_insn;
521 /* If we don't want information for prev_insn or prev_prev_insn, we
522 point the insn_mo field at this dummy integer. */
523 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
525 /* Non-zero if prev_insn is valid. */
526 static int prev_insn_valid;
528 /* The frag for the previous instruction. */
529 static struct frag *prev_insn_frag;
531 /* The offset into prev_insn_frag for the previous instruction. */
532 static long prev_insn_where;
534 /* The reloc type for the previous instruction, if any. */
535 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
537 /* The reloc for the previous instruction, if any. */
538 static fixS *prev_insn_fixp[3];
540 /* Non-zero if the previous instruction was in a delay slot. */
541 static int prev_insn_is_delay_slot;
543 /* Non-zero if the previous instruction was in a .set noreorder. */
544 static int prev_insn_unreordered;
546 /* Non-zero if the previous instruction uses an extend opcode (if
548 static int prev_insn_extended;
550 /* Non-zero if the previous previous instruction was in a .set
552 static int prev_prev_insn_unreordered;
554 /* If this is set, it points to a frag holding nop instructions which
555 were inserted before the start of a noreorder section. If those
556 nops turn out to be unnecessary, the size of the frag can be
558 static fragS *prev_nop_frag;
560 /* The number of nop instructions we created in prev_nop_frag. */
561 static int prev_nop_frag_holds;
563 /* The number of nop instructions that we know we need in
565 static int prev_nop_frag_required;
567 /* The number of instructions we've seen since prev_nop_frag. */
568 static int prev_nop_frag_since;
570 /* For ECOFF and ELF, relocations against symbols are done in two
571 parts, with a HI relocation and a LO relocation. Each relocation
572 has only 16 bits of space to store an addend. This means that in
573 order for the linker to handle carries correctly, it must be able
574 to locate both the HI and the LO relocation. This means that the
575 relocations must appear in order in the relocation table.
577 In order to implement this, we keep track of each unmatched HI
578 relocation. We then sort them so that they immediately precede the
579 corresponding LO relocation. */
584 struct mips_hi_fixup *next;
587 /* The section this fixup is in. */
591 /* The list of unmatched HI relocs. */
593 static struct mips_hi_fixup *mips_hi_fixup_list;
595 /* The frag containing the last explicit relocation operator.
596 Null if explicit relocations have not been used. */
598 static fragS *prev_reloc_op_frag;
600 /* Map normal MIPS register numbers to mips16 register numbers. */
602 #define X ILLEGAL_REG
603 static const int mips32_to_16_reg_map[] =
605 X, X, 2, 3, 4, 5, 6, 7,
606 X, X, X, X, X, X, X, X,
607 0, 1, X, X, X, X, X, X,
608 X, X, X, X, X, X, X, X
612 /* Map mips16 register numbers to normal MIPS register numbers. */
614 static const unsigned int mips16_to_32_reg_map[] =
616 16, 17, 2, 3, 4, 5, 6, 7
619 static int mips_fix_vr4120;
621 /* We don't relax branches by default, since this causes us to expand
622 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
623 fail to compute the offset before expanding the macro to the most
624 efficient expansion. */
626 static int mips_relax_branch;
628 /* The expansion of many macros depends on the type of symbol that
629 they refer to. For example, when generating position-dependent code,
630 a macro that refers to a symbol may have two different expansions,
631 one which uses GP-relative addresses and one which uses absolute
632 addresses. When generating SVR4-style PIC, a macro may have
633 different expansions for local and global symbols.
635 We handle these situations by generating both sequences and putting
636 them in variant frags. In position-dependent code, the first sequence
637 will be the GP-relative one and the second sequence will be the
638 absolute one. In SVR4 PIC, the first sequence will be for global
639 symbols and the second will be for local symbols.
641 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
642 SECOND are the lengths of the two sequences in bytes. These fields
643 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
644 the subtype has the following flags:
647 Set if it has been decided that we should use the second
648 sequence instead of the first.
651 Set in the first variant frag if the macro's second implementation
652 is longer than its first. This refers to the macro as a whole,
653 not an individual relaxation.
656 Set in the first variant frag if the macro appeared in a .set nomacro
657 block and if one alternative requires a warning but the other does not.
660 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
663 The frag's "opcode" points to the first fixup for relaxable code.
665 Relaxable macros are generated using a sequence such as:
667 relax_start (SYMBOL);
668 ... generate first expansion ...
670 ... generate second expansion ...
673 The code and fixups for the unwanted alternative are discarded
674 by md_convert_frag. */
675 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
677 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
678 #define RELAX_SECOND(X) ((X) & 0xff)
679 #define RELAX_USE_SECOND 0x10000
680 #define RELAX_SECOND_LONGER 0x20000
681 #define RELAX_NOMACRO 0x40000
682 #define RELAX_DELAY_SLOT 0x80000
684 /* Branch without likely bit. If label is out of range, we turn:
686 beq reg1, reg2, label
696 with the following opcode replacements:
703 bltzal <-> bgezal (with jal label instead of j label)
705 Even though keeping the delay slot instruction in the delay slot of
706 the branch would be more efficient, it would be very tricky to do
707 correctly, because we'd have to introduce a variable frag *after*
708 the delay slot instruction, and expand that instead. Let's do it
709 the easy way for now, even if the branch-not-taken case now costs
710 one additional instruction. Out-of-range branches are not supposed
711 to be common, anyway.
713 Branch likely. If label is out of range, we turn:
715 beql reg1, reg2, label
716 delay slot (annulled if branch not taken)
725 delay slot (executed only if branch taken)
728 It would be possible to generate a shorter sequence by losing the
729 likely bit, generating something like:
734 delay slot (executed only if branch taken)
746 bltzall -> bgezal (with jal label instead of j label)
747 bgezall -> bltzal (ditto)
750 but it's not clear that it would actually improve performance. */
751 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
754 | ((toofar) ? 1 : 0) \
756 | ((likely) ? 4 : 0) \
757 | ((uncond) ? 8 : 0)))
758 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
759 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
760 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
761 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
762 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
764 /* For mips16 code, we use an entirely different form of relaxation.
765 mips16 supports two versions of most instructions which take
766 immediate values: a small one which takes some small value, and a
767 larger one which takes a 16 bit value. Since branches also follow
768 this pattern, relaxing these values is required.
770 We can assemble both mips16 and normal MIPS code in a single
771 object. Therefore, we need to support this type of relaxation at
772 the same time that we support the relaxation described above. We
773 use the high bit of the subtype field to distinguish these cases.
775 The information we store for this type of relaxation is the
776 argument code found in the opcode file for this relocation, whether
777 the user explicitly requested a small or extended form, and whether
778 the relocation is in a jump or jal delay slot. That tells us the
779 size of the value, and how it should be stored. We also store
780 whether the fragment is considered to be extended or not. We also
781 store whether this is known to be a branch to a different section,
782 whether we have tried to relax this frag yet, and whether we have
783 ever extended a PC relative fragment because of a shift count. */
784 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
787 | ((small) ? 0x100 : 0) \
788 | ((ext) ? 0x200 : 0) \
789 | ((dslot) ? 0x400 : 0) \
790 | ((jal_dslot) ? 0x800 : 0))
791 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
792 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
793 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
794 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
795 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
796 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
797 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
798 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
799 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
800 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
801 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
802 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
804 /* Is the given value a sign-extended 32-bit value? */
805 #define IS_SEXT_32BIT_NUM(x) \
806 (((x) &~ (offsetT) 0x7fffffff) == 0 \
807 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
809 /* Is the given value a sign-extended 16-bit value? */
810 #define IS_SEXT_16BIT_NUM(x) \
811 (((x) &~ (offsetT) 0x7fff) == 0 \
812 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
815 /* Global variables used when generating relaxable macros. See the
816 comment above RELAX_ENCODE for more details about how relaxation
819 /* 0 if we're not emitting a relaxable macro.
820 1 if we're emitting the first of the two relaxation alternatives.
821 2 if we're emitting the second alternative. */
824 /* The first relaxable fixup in the current frag. (In other words,
825 the first fixup that refers to relaxable code.) */
828 /* sizes[0] says how many bytes of the first alternative are stored in
829 the current frag. Likewise sizes[1] for the second alternative. */
830 unsigned int sizes[2];
832 /* The symbol on which the choice of sequence depends. */
836 /* Global variables used to decide whether a macro needs a warning. */
838 /* True if the macro is in a branch delay slot. */
839 bfd_boolean delay_slot_p;
841 /* For relaxable macros, sizes[0] is the length of the first alternative
842 in bytes and sizes[1] is the length of the second alternative.
843 For non-relaxable macros, both elements give the length of the
845 unsigned int sizes[2];
847 /* The first variant frag for this macro. */
849 } mips_macro_warning;
851 /* Prototypes for static functions. */
853 #define internalError() \
854 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
856 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
858 static void append_insn
859 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
860 static void mips_no_prev_insn (int);
861 static void mips16_macro_build
862 (expressionS *, const char *, const char *, va_list);
863 static void load_register (int, expressionS *, int);
864 static void macro_start (void);
865 static void macro_end (void);
866 static void macro (struct mips_cl_insn * ip);
867 static void mips16_macro (struct mips_cl_insn * ip);
868 #ifdef LOSING_COMPILER
869 static void macro2 (struct mips_cl_insn * ip);
871 static void mips_ip (char *str, struct mips_cl_insn * ip);
872 static void mips16_ip (char *str, struct mips_cl_insn * ip);
873 static void mips16_immed
874 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
875 unsigned long *, bfd_boolean *, unsigned short *);
876 static size_t my_getSmallExpression
877 (expressionS *, bfd_reloc_code_real_type *, char *);
878 static void my_getExpression (expressionS *, char *);
879 static void s_align (int);
880 static void s_change_sec (int);
881 static void s_change_section (int);
882 static void s_cons (int);
883 static void s_float_cons (int);
884 static void s_mips_globl (int);
885 static void s_option (int);
886 static void s_mipsset (int);
887 static void s_abicalls (int);
888 static void s_cpload (int);
889 static void s_cpsetup (int);
890 static void s_cplocal (int);
891 static void s_cprestore (int);
892 static void s_cpreturn (int);
893 static void s_gpvalue (int);
894 static void s_gpword (int);
895 static void s_gpdword (int);
896 static void s_cpadd (int);
897 static void s_insn (int);
898 static void md_obj_begin (void);
899 static void md_obj_end (void);
900 static void s_mips_ent (int);
901 static void s_mips_end (int);
902 static void s_mips_frame (int);
903 static void s_mips_mask (int reg_type);
904 static void s_mips_stab (int);
905 static void s_mips_weakext (int);
906 static void s_mips_file (int);
907 static void s_mips_loc (int);
908 static bfd_boolean pic_need_relax (symbolS *, asection *);
909 static int relaxed_branch_length (fragS *, asection *, int);
910 static int validate_mips_insn (const struct mips_opcode *);
912 /* Table and functions used to map between CPU/ISA names, and
913 ISA levels, and CPU numbers. */
917 const char *name; /* CPU or ISA name. */
918 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
919 int isa; /* ISA level. */
920 int cpu; /* CPU number (default CPU if ISA). */
923 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
924 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
925 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
929 The following pseudo-ops from the Kane and Heinrich MIPS book
930 should be defined here, but are currently unsupported: .alias,
931 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
933 The following pseudo-ops from the Kane and Heinrich MIPS book are
934 specific to the type of debugging information being generated, and
935 should be defined by the object format: .aent, .begin, .bend,
936 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
939 The following pseudo-ops from the Kane and Heinrich MIPS book are
940 not MIPS CPU specific, but are also not specific to the object file
941 format. This file is probably the best place to define them, but
942 they are not currently supported: .asm0, .endr, .lab, .repeat,
945 static const pseudo_typeS mips_pseudo_table[] =
947 /* MIPS specific pseudo-ops. */
948 {"option", s_option, 0},
949 {"set", s_mipsset, 0},
950 {"rdata", s_change_sec, 'r'},
951 {"sdata", s_change_sec, 's'},
952 {"livereg", s_ignore, 0},
953 {"abicalls", s_abicalls, 0},
954 {"cpload", s_cpload, 0},
955 {"cpsetup", s_cpsetup, 0},
956 {"cplocal", s_cplocal, 0},
957 {"cprestore", s_cprestore, 0},
958 {"cpreturn", s_cpreturn, 0},
959 {"gpvalue", s_gpvalue, 0},
960 {"gpword", s_gpword, 0},
961 {"gpdword", s_gpdword, 0},
962 {"cpadd", s_cpadd, 0},
965 /* Relatively generic pseudo-ops that happen to be used on MIPS
967 {"asciiz", stringer, 1},
968 {"bss", s_change_sec, 'b'},
971 {"dword", s_cons, 3},
972 {"weakext", s_mips_weakext, 0},
974 /* These pseudo-ops are defined in read.c, but must be overridden
975 here for one reason or another. */
976 {"align", s_align, 0},
978 {"data", s_change_sec, 'd'},
979 {"double", s_float_cons, 'd'},
980 {"float", s_float_cons, 'f'},
981 {"globl", s_mips_globl, 0},
982 {"global", s_mips_globl, 0},
983 {"hword", s_cons, 1},
988 {"section", s_change_section, 0},
989 {"short", s_cons, 1},
990 {"single", s_float_cons, 'f'},
991 {"stabn", s_mips_stab, 'n'},
992 {"text", s_change_sec, 't'},
995 { "extern", ecoff_directive_extern, 0},
1000 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1002 /* These pseudo-ops should be defined by the object file format.
1003 However, a.out doesn't support them, so we have versions here. */
1004 {"aent", s_mips_ent, 1},
1005 {"bgnb", s_ignore, 0},
1006 {"end", s_mips_end, 0},
1007 {"endb", s_ignore, 0},
1008 {"ent", s_mips_ent, 0},
1009 {"file", s_mips_file, 0},
1010 {"fmask", s_mips_mask, 'F'},
1011 {"frame", s_mips_frame, 0},
1012 {"loc", s_mips_loc, 0},
1013 {"mask", s_mips_mask, 'R'},
1014 {"verstamp", s_ignore, 0},
1018 extern void pop_insert (const pseudo_typeS *);
1021 mips_pop_insert (void)
1023 pop_insert (mips_pseudo_table);
1024 if (! ECOFF_DEBUGGING)
1025 pop_insert (mips_nonecoff_pseudo_table);
1028 /* Symbols labelling the current insn. */
1030 struct insn_label_list
1032 struct insn_label_list *next;
1036 static struct insn_label_list *insn_labels;
1037 static struct insn_label_list *free_insn_labels;
1039 static void mips_clear_insn_labels (void);
1042 mips_clear_insn_labels (void)
1044 register struct insn_label_list **pl;
1046 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1052 static char *expr_end;
1054 /* Expressions which appear in instructions. These are set by
1057 static expressionS imm_expr;
1058 static expressionS imm2_expr;
1059 static expressionS offset_expr;
1061 /* Relocs associated with imm_expr and offset_expr. */
1063 static bfd_reloc_code_real_type imm_reloc[3]
1064 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1065 static bfd_reloc_code_real_type offset_reloc[3]
1066 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1068 /* These are set by mips16_ip if an explicit extension is used. */
1070 static bfd_boolean mips16_small, mips16_ext;
1073 /* The pdr segment for per procedure frame/regmask info. Not used for
1076 static segT pdr_seg;
1079 /* The default target format to use. */
1082 mips_target_format (void)
1084 switch (OUTPUT_FLAVOR)
1086 case bfd_target_aout_flavour:
1087 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1088 case bfd_target_ecoff_flavour:
1089 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1090 case bfd_target_coff_flavour:
1092 case bfd_target_elf_flavour:
1094 /* This is traditional mips. */
1095 return (target_big_endian
1096 ? (HAVE_64BIT_OBJECTS
1097 ? "elf64-tradbigmips"
1099 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1100 : (HAVE_64BIT_OBJECTS
1101 ? "elf64-tradlittlemips"
1103 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1105 return (target_big_endian
1106 ? (HAVE_64BIT_OBJECTS
1109 ? "elf32-nbigmips" : "elf32-bigmips"))
1110 : (HAVE_64BIT_OBJECTS
1111 ? "elf64-littlemips"
1113 ? "elf32-nlittlemips" : "elf32-littlemips")));
1121 /* This function is called once, at assembler startup time. It should
1122 set up all the tables, etc. that the MD part of the assembler will need. */
1127 register const char *retval = NULL;
1131 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1132 as_warn (_("Could not set architecture and machine"));
1134 op_hash = hash_new ();
1136 for (i = 0; i < NUMOPCODES;)
1138 const char *name = mips_opcodes[i].name;
1140 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1143 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1144 mips_opcodes[i].name, retval);
1145 /* Probably a memory allocation problem? Give up now. */
1146 as_fatal (_("Broken assembler. No assembly attempted."));
1150 if (mips_opcodes[i].pinfo != INSN_MACRO)
1152 if (!validate_mips_insn (&mips_opcodes[i]))
1157 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1160 mips16_op_hash = hash_new ();
1163 while (i < bfd_mips16_num_opcodes)
1165 const char *name = mips16_opcodes[i].name;
1167 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1169 as_fatal (_("internal: can't hash `%s': %s"),
1170 mips16_opcodes[i].name, retval);
1173 if (mips16_opcodes[i].pinfo != INSN_MACRO
1174 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1175 != mips16_opcodes[i].match))
1177 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1178 mips16_opcodes[i].name, mips16_opcodes[i].args);
1183 while (i < bfd_mips16_num_opcodes
1184 && strcmp (mips16_opcodes[i].name, name) == 0);
1188 as_fatal (_("Broken assembler. No assembly attempted."));
1190 /* We add all the general register names to the symbol table. This
1191 helps us detect invalid uses of them. */
1192 for (i = 0; i < 32; i++)
1196 sprintf (buf, "$%d", i);
1197 symbol_table_insert (symbol_new (buf, reg_section, i,
1198 &zero_address_frag));
1200 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1201 &zero_address_frag));
1202 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1203 &zero_address_frag));
1204 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1205 &zero_address_frag));
1206 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1207 &zero_address_frag));
1208 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1209 &zero_address_frag));
1210 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1211 &zero_address_frag));
1212 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1213 &zero_address_frag));
1214 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1215 &zero_address_frag));
1216 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1217 &zero_address_frag));
1219 /* If we don't add these register names to the symbol table, they
1220 may end up being added as regular symbols by operand(), and then
1221 make it to the object file as undefined in case they're not
1222 regarded as local symbols. They're local in o32, since `$' is a
1223 local symbol prefix, but not in n32 or n64. */
1224 for (i = 0; i < 8; i++)
1228 sprintf (buf, "$fcc%i", i);
1229 symbol_table_insert (symbol_new (buf, reg_section, -1,
1230 &zero_address_frag));
1233 mips_no_prev_insn (FALSE);
1236 mips_cprmask[0] = 0;
1237 mips_cprmask[1] = 0;
1238 mips_cprmask[2] = 0;
1239 mips_cprmask[3] = 0;
1241 /* set the default alignment for the text section (2**2) */
1242 record_alignment (text_section, 2);
1244 if (USE_GLOBAL_POINTER_OPT)
1245 bfd_set_gp_size (stdoutput, g_switch_value);
1247 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1255 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1256 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg = now_subseg;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags = SEC_READONLY | SEC_DATA;
1274 if (strcmp (TARGET_OS, "elf") != 0)
1275 flags |= SEC_ALLOC | SEC_LOAD;
1277 if (mips_abi != N64_ABI)
1279 sec = subseg_new (".reginfo", (subsegT) 0);
1281 bfd_set_section_flags (stdoutput, sec, flags);
1282 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1285 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec = subseg_new (".MIPS.options", (subsegT) 0);
1293 bfd_set_section_flags (stdoutput, sec, flags);
1294 bfd_set_section_alignment (stdoutput, sec, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr;
1302 opthdr.kind = ODK_REGINFO;
1303 opthdr.size = (sizeof (Elf_External_Options)
1304 + sizeof (Elf64_External_RegInfo));
1307 f = frag_more (sizeof (Elf_External_Options));
1308 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1309 (Elf_External_Options *) f);
1311 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1316 if (ECOFF_DEBUGGING)
1318 sec = subseg_new (".mdebug", (subsegT) 0);
1319 (void) bfd_set_section_flags (stdoutput, sec,
1320 SEC_HAS_CONTENTS | SEC_READONLY);
1321 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1324 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1326 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1327 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1328 SEC_READONLY | SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1334 subseg_set (seg, subseg);
1338 if (! ECOFF_DEBUGGING)
1345 if (! ECOFF_DEBUGGING)
1350 md_assemble (char *str)
1352 struct mips_cl_insn insn;
1353 bfd_reloc_code_real_type unused_reloc[3]
1354 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1356 imm_expr.X_op = O_absent;
1357 imm2_expr.X_op = O_absent;
1358 offset_expr.X_op = O_absent;
1359 imm_reloc[0] = BFD_RELOC_UNUSED;
1360 imm_reloc[1] = BFD_RELOC_UNUSED;
1361 imm_reloc[2] = BFD_RELOC_UNUSED;
1362 offset_reloc[0] = BFD_RELOC_UNUSED;
1363 offset_reloc[1] = BFD_RELOC_UNUSED;
1364 offset_reloc[2] = BFD_RELOC_UNUSED;
1366 if (mips_opts.mips16)
1367 mips16_ip (str, &insn);
1370 mips_ip (str, &insn);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str, insn.insn_opcode));
1377 as_bad ("%s `%s'", insn_error, str);
1381 if (insn.insn_mo->pinfo == INSN_MACRO)
1384 if (mips_opts.mips16)
1385 mips16_macro (&insn);
1392 if (imm_expr.X_op != O_absent)
1393 append_insn (&insn, &imm_expr, imm_reloc);
1394 else if (offset_expr.X_op != O_absent)
1395 append_insn (&insn, &offset_expr, offset_reloc);
1397 append_insn (&insn, NULL, unused_reloc);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1408 return (reloc == BFD_RELOC_HI16_S
1409 || reloc == BFD_RELOC_MIPS_GOT16);
1412 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1415 static inline bfd_boolean
1416 fixup_has_matching_lo_p (fixS *fixp)
1418 return (fixp->fx_next != NULL
1419 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1420 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1421 && fixp->fx_offset == fixp->fx_next->fx_offset);
1424 /* See whether instruction IP reads register REG. CLASS is the type
1428 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1429 enum mips_regclass class)
1431 if (class == MIPS16_REG)
1433 assert (mips_opts.mips16);
1434 reg = mips16_to_32_reg_map[reg];
1435 class = MIPS_GR_REG;
1438 /* Don't report on general register ZERO, since it never changes. */
1439 if (class == MIPS_GR_REG && reg == ZERO)
1442 if (class == MIPS_FP_REG)
1444 assert (! mips_opts.mips16);
1445 /* If we are called with either $f0 or $f1, we must check $f0.
1446 This is not optimal, because it will introduce an unnecessary
1447 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1448 need to distinguish reading both $f0 and $f1 or just one of
1449 them. Note that we don't have to check the other way,
1450 because there is no instruction that sets both $f0 and $f1
1451 and requires a delay. */
1452 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1453 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1454 == (reg &~ (unsigned) 1)))
1456 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1457 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1458 == (reg &~ (unsigned) 1)))
1461 else if (! mips_opts.mips16)
1463 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1464 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1466 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1467 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1472 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1473 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1474 & MIPS16OP_MASK_RX)]
1477 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1478 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1479 & MIPS16OP_MASK_RY)]
1482 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1483 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1484 & MIPS16OP_MASK_MOVE32Z)]
1487 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1489 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1491 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1493 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1494 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1495 & MIPS16OP_MASK_REGR32) == reg)
1502 /* This function returns true if modifying a register requires a
1506 reg_needs_delay (unsigned int reg)
1508 unsigned long prev_pinfo;
1510 prev_pinfo = prev_insn.insn_mo->pinfo;
1511 if (! mips_opts.noreorder
1512 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1513 && ! gpr_interlocks)
1514 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1515 && ! cop_interlocks)))
1517 /* A load from a coprocessor or from memory. All load delays
1518 delay the use of general register rt for one instruction. */
1519 /* Itbl support may require additional care here. */
1520 know (prev_pinfo & INSN_WRITE_GPR_T);
1521 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1528 /* Mark instruction labels in mips16 mode. This permits the linker to
1529 handle them specially, such as generating jalx instructions when
1530 needed. We also make them odd for the duration of the assembly, in
1531 order to generate the right sort of code. We will make them even
1532 in the adjust_symtab routine, while leaving them marked. This is
1533 convenient for the debugger and the disassembler. The linker knows
1534 to make them odd again. */
1537 mips16_mark_labels (void)
1539 if (mips_opts.mips16)
1541 struct insn_label_list *l;
1544 for (l = insn_labels; l != NULL; l = l->next)
1547 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1548 S_SET_OTHER (l->label, STO_MIPS16);
1550 val = S_GET_VALUE (l->label);
1552 S_SET_VALUE (l->label, val + 1);
1557 /* End the current frag. Make it a variant frag and record the
1561 relax_close_frag (void)
1563 mips_macro_warning.first_frag = frag_now;
1564 frag_var (rs_machine_dependent, 0, 0,
1565 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1566 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1568 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1569 mips_relax.first_fixup = 0;
1572 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1573 See the comment above RELAX_ENCODE for more details. */
1576 relax_start (symbolS *symbol)
1578 assert (mips_relax.sequence == 0);
1579 mips_relax.sequence = 1;
1580 mips_relax.symbol = symbol;
1583 /* Start generating the second version of a relaxable sequence.
1584 See the comment above RELAX_ENCODE for more details. */
1589 assert (mips_relax.sequence == 1);
1590 mips_relax.sequence = 2;
1593 /* End the current relaxable sequence. */
1598 assert (mips_relax.sequence == 2);
1599 relax_close_frag ();
1600 mips_relax.sequence = 0;
1603 /* Output an instruction. IP is the instruction information.
1604 ADDRESS_EXPR is an operand of the instruction to be used with
1608 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1609 bfd_reloc_code_real_type *reloc_type)
1611 register unsigned long prev_pinfo, pinfo;
1615 relax_stateT prev_insn_frag_type = 0;
1616 bfd_boolean relaxed_branch = FALSE;
1617 bfd_boolean force_new_frag = FALSE;
1619 /* Mark instruction labels in mips16 mode. */
1620 mips16_mark_labels ();
1622 prev_pinfo = prev_insn.insn_mo->pinfo;
1623 pinfo = ip->insn_mo->pinfo;
1625 if (mips_relax.sequence != 2
1626 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1630 /* If the previous insn required any delay slots, see if we need
1631 to insert a NOP or two. There are eight kinds of possible
1632 hazards, of which an instruction can have at most one type.
1633 (1) a load from memory delay
1634 (2) a load from a coprocessor delay
1635 (3) an unconditional branch delay
1636 (4) a conditional branch delay
1637 (5) a move to coprocessor register delay
1638 (6) a load coprocessor register from memory delay
1639 (7) a coprocessor condition code delay
1640 (8) a HI/LO special register delay
1642 There are a lot of optimizations we could do that we don't.
1643 In particular, we do not, in general, reorder instructions.
1644 If you use gcc with optimization, it will reorder
1645 instructions and generally do much more optimization then we
1646 do here; repeating all that work in the assembler would only
1647 benefit hand written assembly code, and does not seem worth
1650 /* This is how a NOP is emitted. */
1651 #define emit_nop() \
1653 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1654 : md_number_to_chars (frag_more (4), 0, 4))
1656 /* The previous insn might require a delay slot, depending upon
1657 the contents of the current insn. */
1658 if (! mips_opts.mips16
1659 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1660 && ! gpr_interlocks)
1661 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1662 && ! cop_interlocks)))
1664 /* A load from a coprocessor or from memory. All load
1665 delays delay the use of general register rt for one
1667 /* Itbl support may require additional care here. */
1668 know (prev_pinfo & INSN_WRITE_GPR_T);
1669 if (mips_optimize == 0
1670 || insn_uses_reg (ip,
1671 ((prev_insn.insn_opcode >> OP_SH_RT)
1676 else if (! mips_opts.mips16
1677 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1678 && ! cop_interlocks)
1679 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1680 && ! cop_mem_interlocks)))
1682 /* A generic coprocessor delay. The previous instruction
1683 modified a coprocessor general or control register. If
1684 it modified a control register, we need to avoid any
1685 coprocessor instruction (this is probably not always
1686 required, but it sometimes is). If it modified a general
1687 register, we avoid using that register.
1689 This case is not handled very well. There is no special
1690 knowledge of CP0 handling, and the coprocessors other
1691 than the floating point unit are not distinguished at
1693 /* Itbl support may require additional care here. FIXME!
1694 Need to modify this to include knowledge about
1695 user specified delays! */
1696 if (prev_pinfo & INSN_WRITE_FPR_T)
1698 if (mips_optimize == 0
1699 || insn_uses_reg (ip,
1700 ((prev_insn.insn_opcode >> OP_SH_FT)
1705 else if (prev_pinfo & INSN_WRITE_FPR_S)
1707 if (mips_optimize == 0
1708 || insn_uses_reg (ip,
1709 ((prev_insn.insn_opcode >> OP_SH_FS)
1716 /* We don't know exactly what the previous instruction
1717 does. If the current instruction uses a coprocessor
1718 register, we must insert a NOP. If previous
1719 instruction may set the condition codes, and the
1720 current instruction uses them, we must insert two
1722 /* Itbl support may require additional care here. */
1723 if (mips_optimize == 0
1724 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1725 && (pinfo & INSN_READ_COND_CODE)))
1727 else if (pinfo & INSN_COP)
1731 else if (! mips_opts.mips16
1732 && (prev_pinfo & INSN_WRITE_COND_CODE)
1733 && ! cop_interlocks)
1735 /* The previous instruction sets the coprocessor condition
1736 codes, but does not require a general coprocessor delay
1737 (this means it is a floating point comparison
1738 instruction). If this instruction uses the condition
1739 codes, we need to insert a single NOP. */
1740 /* Itbl support may require additional care here. */
1741 if (mips_optimize == 0
1742 || (pinfo & INSN_READ_COND_CODE))
1746 /* If we're fixing up mfhi/mflo for the r7000 and the
1747 previous insn was an mfhi/mflo and the current insn
1748 reads the register that the mfhi/mflo wrote to, then
1751 else if (mips_7000_hilo_fix
1752 && MF_HILO_INSN (prev_pinfo)
1753 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1760 /* If we're fixing up mfhi/mflo for the r7000 and the
1761 2nd previous insn was an mfhi/mflo and the current insn
1762 reads the register that the mfhi/mflo wrote to, then
1765 else if (mips_7000_hilo_fix
1766 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1767 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1775 else if (prev_pinfo & INSN_READ_LO)
1777 /* The previous instruction reads the LO register; if the
1778 current instruction writes to the LO register, we must
1779 insert two NOPS. Some newer processors have interlocks.
1780 Also the tx39's multiply instructions can be executed
1781 immediately after a read from HI/LO (without the delay),
1782 though the tx39's divide insns still do require the
1784 if (! (hilo_interlocks
1785 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1786 && (mips_optimize == 0
1787 || (pinfo & INSN_WRITE_LO)))
1789 /* Most mips16 branch insns don't have a delay slot.
1790 If a read from LO is immediately followed by a branch
1791 to a write to LO we have a read followed by a write
1792 less than 2 insns away. We assume the target of
1793 a branch might be a write to LO, and insert a nop
1794 between a read and an immediately following branch. */
1795 else if (mips_opts.mips16
1796 && (mips_optimize == 0
1797 || (pinfo & MIPS16_INSN_BRANCH)))
1800 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1802 /* The previous instruction reads the HI register; if the
1803 current instruction writes to the HI register, we must
1804 insert a NOP. Some newer processors have interlocks.
1805 Also the note tx39's multiply above. */
1806 if (! (hilo_interlocks
1807 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1808 && (mips_optimize == 0
1809 || (pinfo & INSN_WRITE_HI)))
1811 /* Most mips16 branch insns don't have a delay slot.
1812 If a read from HI is immediately followed by a branch
1813 to a write to HI we have a read followed by a write
1814 less than 2 insns away. We assume the target of
1815 a branch might be a write to HI, and insert a nop
1816 between a read and an immediately following branch. */
1817 else if (mips_opts.mips16
1818 && (mips_optimize == 0
1819 || (pinfo & MIPS16_INSN_BRANCH)))
1823 /* If the previous instruction was in a noreorder section, then
1824 we don't want to insert the nop after all. */
1825 /* Itbl support may require additional care here. */
1826 if (prev_insn_unreordered)
1829 /* There are two cases which require two intervening
1830 instructions: 1) setting the condition codes using a move to
1831 coprocessor instruction which requires a general coprocessor
1832 delay and then reading the condition codes 2) reading the HI
1833 or LO register and then writing to it (except on processors
1834 which have interlocks). If we are not already emitting a NOP
1835 instruction, we must check for these cases compared to the
1836 instruction previous to the previous instruction. */
1837 if ((! mips_opts.mips16
1838 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1839 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1840 && (pinfo & INSN_READ_COND_CODE)
1841 && ! cop_interlocks)
1842 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1843 && (pinfo & INSN_WRITE_LO)
1844 && ! (hilo_interlocks
1845 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1846 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1847 && (pinfo & INSN_WRITE_HI)
1848 && ! (hilo_interlocks
1849 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1854 if (prev_prev_insn_unreordered)
1857 if (prev_prev_nop && nops == 0)
1860 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1862 /* We're out of bits in pinfo, so we must resort to string
1863 ops here. Shortcuts are selected based on opcodes being
1864 limited to the VR4120 instruction set. */
1866 const char *pn = prev_insn.insn_mo->name;
1867 const char *tn = ip->insn_mo->name;
1868 if (strncmp(pn, "macc", 4) == 0
1869 || strncmp(pn, "dmacc", 5) == 0)
1871 /* Errata 21 - [D]DIV[U] after [D]MACC */
1872 if (strstr (tn, "div"))
1877 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1878 if (pn[0] == 'd' /* dmacc */
1879 && (strncmp(tn, "dmult", 5) == 0
1880 || strncmp(tn, "dmacc", 5) == 0))
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn, "mtlo") == 0
1887 || strcmp (tn, "mthi") == 0)
1893 else if (strncmp(pn, "dmult", 5) == 0
1894 && (strncmp(tn, "dmult", 5) == 0
1895 || strncmp(tn, "dmacc", 5) == 0))
1897 /* Here is the rest of errata 23. */
1900 if (nops < min_nops)
1904 /* If we are being given a nop instruction, don't bother with
1905 one of the nops we would otherwise output. This will only
1906 happen when a nop instruction is used with mips_optimize set
1909 && ! mips_opts.noreorder
1910 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1913 /* Now emit the right number of NOP instructions. */
1914 if (nops > 0 && ! mips_opts.noreorder)
1917 unsigned long old_frag_offset;
1919 struct insn_label_list *l;
1921 old_frag = frag_now;
1922 old_frag_offset = frag_now_fix ();
1924 for (i = 0; i < nops; i++)
1929 listing_prev_line ();
1930 /* We may be at the start of a variant frag. In case we
1931 are, make sure there is enough space for the frag
1932 after the frags created by listing_prev_line. The
1933 argument to frag_grow here must be at least as large
1934 as the argument to all other calls to frag_grow in
1935 this file. We don't have to worry about being in the
1936 middle of a variant frag, because the variants insert
1937 all needed nop instructions themselves. */
1941 for (l = insn_labels; l != NULL; l = l->next)
1945 assert (S_GET_SEGMENT (l->label) == now_seg);
1946 symbol_set_frag (l->label, frag_now);
1947 val = (valueT) frag_now_fix ();
1948 /* mips16 text labels are stored as odd. */
1949 if (mips_opts.mips16)
1951 S_SET_VALUE (l->label, val);
1954 #ifndef NO_ECOFF_DEBUGGING
1955 if (ECOFF_DEBUGGING)
1956 ecoff_fix_loc (old_frag, old_frag_offset);
1959 else if (prev_nop_frag != NULL)
1961 /* We have a frag holding nops we may be able to remove. If
1962 we don't need any nops, we can decrease the size of
1963 prev_nop_frag by the size of one instruction. If we do
1964 need some nops, we count them in prev_nops_required. */
1965 if (prev_nop_frag_since == 0)
1969 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1970 --prev_nop_frag_holds;
1973 prev_nop_frag_required += nops;
1977 if (prev_prev_nop == 0)
1979 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1980 --prev_nop_frag_holds;
1983 ++prev_nop_frag_required;
1986 if (prev_nop_frag_holds <= prev_nop_frag_required)
1987 prev_nop_frag = NULL;
1989 ++prev_nop_frag_since;
1991 /* Sanity check: by the time we reach the second instruction
1992 after prev_nop_frag, we should have used up all the nops
1993 one way or another. */
1994 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1998 /* Record the frag type before frag_var. */
2000 prev_insn_frag_type = prev_insn_frag->fr_type;
2003 && *reloc_type == BFD_RELOC_16_PCREL_S2
2004 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2005 || pinfo & INSN_COND_BRANCH_LIKELY)
2006 && mips_relax_branch
2007 /* Don't try branch relaxation within .set nomacro, or within
2008 .set noat if we use $at for PIC computations. If it turns
2009 out that the branch was out-of-range, we'll get an error. */
2010 && !mips_opts.warn_about_macros
2011 && !(mips_opts.noat && mips_pic != NO_PIC)
2012 && !mips_opts.mips16)
2014 relaxed_branch = TRUE;
2015 f = frag_var (rs_machine_dependent,
2016 relaxed_branch_length
2018 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2019 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2021 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2022 pinfo & INSN_COND_BRANCH_LIKELY,
2023 pinfo & INSN_WRITE_GPR_31,
2025 address_expr->X_add_symbol,
2026 address_expr->X_add_number,
2028 *reloc_type = BFD_RELOC_UNUSED;
2030 else if (*reloc_type > BFD_RELOC_UNUSED)
2032 /* We need to set up a variant frag. */
2033 assert (mips_opts.mips16 && address_expr != NULL);
2034 f = frag_var (rs_machine_dependent, 4, 0,
2035 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2036 mips16_small, mips16_ext,
2038 & INSN_UNCOND_BRANCH_DELAY),
2039 (*prev_insn_reloc_type
2040 == BFD_RELOC_MIPS16_JMP)),
2041 make_expr_symbol (address_expr), 0, NULL);
2043 else if (mips_opts.mips16
2045 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2047 /* Make sure there is enough room to swap this instruction with
2048 a following jump instruction. */
2054 if (mips_opts.mips16
2055 && mips_opts.noreorder
2056 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2057 as_warn (_("extended instruction in delay slot"));
2059 if (mips_relax.sequence)
2061 /* If we've reached the end of this frag, turn it into a variant
2062 frag and record the information for the instructions we've
2064 if (frag_room () < 4)
2065 relax_close_frag ();
2066 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2069 if (mips_relax.sequence != 2)
2070 mips_macro_warning.sizes[0] += 4;
2071 if (mips_relax.sequence != 1)
2072 mips_macro_warning.sizes[1] += 4;
2077 fixp[0] = fixp[1] = fixp[2] = NULL;
2078 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2080 if (address_expr->X_op == O_constant)
2084 switch (*reloc_type)
2087 ip->insn_opcode |= address_expr->X_add_number;
2090 case BFD_RELOC_MIPS_HIGHEST:
2091 tmp = (address_expr->X_add_number
2092 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2094 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2097 case BFD_RELOC_MIPS_HIGHER:
2098 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2099 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2102 case BFD_RELOC_HI16_S:
2103 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2107 case BFD_RELOC_HI16:
2108 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2111 case BFD_RELOC_LO16:
2112 case BFD_RELOC_MIPS_GOT_DISP:
2113 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2116 case BFD_RELOC_MIPS_JMP:
2117 if ((address_expr->X_add_number & 3) != 0)
2118 as_bad (_("jump to misaligned address (0x%lx)"),
2119 (unsigned long) address_expr->X_add_number);
2120 if (address_expr->X_add_number & ~0xfffffff)
2121 as_bad (_("jump address range overflow (0x%lx)"),
2122 (unsigned long) address_expr->X_add_number);
2123 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2126 case BFD_RELOC_MIPS16_JMP:
2127 if ((address_expr->X_add_number & 3) != 0)
2128 as_bad (_("jump to misaligned address (0x%lx)"),
2129 (unsigned long) address_expr->X_add_number);
2130 if (address_expr->X_add_number & ~0xfffffff)
2131 as_bad (_("jump address range overflow (0x%lx)"),
2132 (unsigned long) address_expr->X_add_number);
2134 (((address_expr->X_add_number & 0x7c0000) << 3)
2135 | ((address_expr->X_add_number & 0xf800000) >> 7)
2136 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2139 case BFD_RELOC_16_PCREL_S2:
2149 reloc_howto_type *howto;
2152 /* In a compound relocation, it is the final (outermost)
2153 operator that determines the relocated field. */
2154 for (i = 1; i < 3; i++)
2155 if (reloc_type[i] == BFD_RELOC_UNUSED)
2158 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2159 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2160 bfd_get_reloc_size(howto),
2162 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2165 /* These relocations can have an addend that won't fit in
2166 4 octets for 64bit assembly. */
2168 && ! howto->partial_inplace
2169 && (reloc_type[0] == BFD_RELOC_16
2170 || reloc_type[0] == BFD_RELOC_32
2171 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2172 || reloc_type[0] == BFD_RELOC_HI16_S
2173 || reloc_type[0] == BFD_RELOC_LO16
2174 || reloc_type[0] == BFD_RELOC_GPREL16
2175 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2176 || reloc_type[0] == BFD_RELOC_GPREL32
2177 || reloc_type[0] == BFD_RELOC_64
2178 || reloc_type[0] == BFD_RELOC_CTOR
2179 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2180 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2181 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2182 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2183 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2184 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2185 fixp[0]->fx_no_overflow = 1;
2187 if (mips_relax.sequence)
2189 if (mips_relax.first_fixup == 0)
2190 mips_relax.first_fixup = fixp[0];
2192 else if (reloc_needs_lo_p (*reloc_type))
2194 struct mips_hi_fixup *hi_fixup;
2196 /* Reuse the last entry if it already has a matching %lo. */
2197 hi_fixup = mips_hi_fixup_list;
2199 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2201 hi_fixup = ((struct mips_hi_fixup *)
2202 xmalloc (sizeof (struct mips_hi_fixup)));
2203 hi_fixup->next = mips_hi_fixup_list;
2204 mips_hi_fixup_list = hi_fixup;
2206 hi_fixup->fixp = fixp[0];
2207 hi_fixup->seg = now_seg;
2210 /* Add fixups for the second and third relocations, if given.
2211 Note that the ABI allows the second relocation to be
2212 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2213 moment we only use RSS_UNDEF, but we could add support
2214 for the others if it ever becomes necessary. */
2215 for (i = 1; i < 3; i++)
2216 if (reloc_type[i] != BFD_RELOC_UNUSED)
2218 address_expr->X_op = O_absent;
2219 address_expr->X_add_symbol = 0;
2220 address_expr->X_add_number = 0;
2222 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2223 fixp[0]->fx_size, address_expr,
2224 FALSE, reloc_type[i]);
2229 if (! mips_opts.mips16)
2231 md_number_to_chars (f, ip->insn_opcode, 4);
2233 dwarf2_emit_insn (4);
2236 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2238 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2239 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2241 dwarf2_emit_insn (4);
2248 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2251 md_number_to_chars (f, ip->insn_opcode, 2);
2253 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2257 /* Update the register mask information. */
2258 if (! mips_opts.mips16)
2260 if (pinfo & INSN_WRITE_GPR_D)
2261 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2262 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2263 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2264 if (pinfo & INSN_READ_GPR_S)
2265 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2266 if (pinfo & INSN_WRITE_GPR_31)
2267 mips_gprmask |= 1 << RA;
2268 if (pinfo & INSN_WRITE_FPR_D)
2269 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2270 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2271 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2272 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2273 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2274 if ((pinfo & INSN_READ_FPR_R) != 0)
2275 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2276 if (pinfo & INSN_COP)
2278 /* We don't keep enough information to sort these cases out.
2279 The itbl support does keep this information however, although
2280 we currently don't support itbl fprmats as part of the cop
2281 instruction. May want to add this support in the future. */
2283 /* Never set the bit for $0, which is always zero. */
2284 mips_gprmask &= ~1 << 0;
2288 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2289 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2290 & MIPS16OP_MASK_RX);
2291 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2292 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2293 & MIPS16OP_MASK_RY);
2294 if (pinfo & MIPS16_INSN_WRITE_Z)
2295 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2296 & MIPS16OP_MASK_RZ);
2297 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2298 mips_gprmask |= 1 << TREG;
2299 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2300 mips_gprmask |= 1 << SP;
2301 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2302 mips_gprmask |= 1 << RA;
2303 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2304 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2305 if (pinfo & MIPS16_INSN_READ_Z)
2306 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2307 & MIPS16OP_MASK_MOVE32Z);
2308 if (pinfo & MIPS16_INSN_READ_GPR_X)
2309 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2310 & MIPS16OP_MASK_REGR32);
2313 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2315 /* Filling the branch delay slot is more complex. We try to
2316 switch the branch with the previous instruction, which we can
2317 do if the previous instruction does not set up a condition
2318 that the branch tests and if the branch is not itself the
2319 target of any branch. */
2320 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2321 || (pinfo & INSN_COND_BRANCH_DELAY))
2323 if (mips_optimize < 2
2324 /* If we have seen .set volatile or .set nomove, don't
2326 || mips_opts.nomove != 0
2327 /* If we had to emit any NOP instructions, then we
2328 already know we can not swap. */
2330 /* If we don't even know the previous insn, we can not
2332 || ! prev_insn_valid
2333 /* If the previous insn is already in a branch delay
2334 slot, then we can not swap. */
2335 || prev_insn_is_delay_slot
2336 /* If the previous previous insn was in a .set
2337 noreorder, we can't swap. Actually, the MIPS
2338 assembler will swap in this situation. However, gcc
2339 configured -with-gnu-as will generate code like
2345 in which we can not swap the bne and INSN. If gcc is
2346 not configured -with-gnu-as, it does not output the
2347 .set pseudo-ops. We don't have to check
2348 prev_insn_unreordered, because prev_insn_valid will
2349 be 0 in that case. We don't want to use
2350 prev_prev_insn_valid, because we do want to be able
2351 to swap at the start of a function. */
2352 || prev_prev_insn_unreordered
2353 /* If the branch is itself the target of a branch, we
2354 can not swap. We cheat on this; all we check for is
2355 whether there is a label on this instruction. If
2356 there are any branches to anything other than a
2357 label, users must use .set noreorder. */
2358 || insn_labels != NULL
2359 /* If the previous instruction is in a variant frag
2360 other than this branch's one, we cannot do the swap.
2361 This does not apply to the mips16, which uses variant
2362 frags for different purposes. */
2363 || (! mips_opts.mips16
2364 && prev_insn_frag_type == rs_machine_dependent)
2365 /* If the branch reads the condition codes, we don't
2366 even try to swap, because in the sequence
2371 we can not swap, and I don't feel like handling that
2373 || (! mips_opts.mips16
2374 && (pinfo & INSN_READ_COND_CODE)
2375 && ! cop_interlocks)
2376 /* We can not swap with an instruction that requires a
2377 delay slot, because the target of the branch might
2378 interfere with that instruction. */
2379 || (! mips_opts.mips16
2381 /* Itbl support may require additional care here. */
2382 & (INSN_LOAD_COPROC_DELAY
2383 | INSN_COPROC_MOVE_DELAY
2384 | INSN_WRITE_COND_CODE))
2385 && ! cop_interlocks)
2386 || (! (hilo_interlocks
2387 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2391 || (! mips_opts.mips16
2392 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2393 && ! gpr_interlocks)
2394 || (! mips_opts.mips16
2395 /* Itbl support may require additional care here. */
2396 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2397 && ! cop_mem_interlocks)
2398 /* We can not swap with a branch instruction. */
2400 & (INSN_UNCOND_BRANCH_DELAY
2401 | INSN_COND_BRANCH_DELAY
2402 | INSN_COND_BRANCH_LIKELY))
2403 /* We do not swap with a trap instruction, since it
2404 complicates trap handlers to have the trap
2405 instruction be in a delay slot. */
2406 || (prev_pinfo & INSN_TRAP)
2407 /* If the branch reads a register that the previous
2408 instruction sets, we can not swap. */
2409 || (! mips_opts.mips16
2410 && (prev_pinfo & INSN_WRITE_GPR_T)
2411 && insn_uses_reg (ip,
2412 ((prev_insn.insn_opcode >> OP_SH_RT)
2415 || (! mips_opts.mips16
2416 && (prev_pinfo & INSN_WRITE_GPR_D)
2417 && insn_uses_reg (ip,
2418 ((prev_insn.insn_opcode >> OP_SH_RD)
2421 || (mips_opts.mips16
2422 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2423 && insn_uses_reg (ip,
2424 ((prev_insn.insn_opcode
2426 & MIPS16OP_MASK_RX),
2428 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2429 && insn_uses_reg (ip,
2430 ((prev_insn.insn_opcode
2432 & MIPS16OP_MASK_RY),
2434 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2435 && insn_uses_reg (ip,
2436 ((prev_insn.insn_opcode
2438 & MIPS16OP_MASK_RZ),
2440 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2441 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2442 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2443 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2444 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2445 && insn_uses_reg (ip,
2446 MIPS16OP_EXTRACT_REG32R (prev_insn.
2449 /* If the branch writes a register that the previous
2450 instruction sets, we can not swap (we know that
2451 branches write only to RD or to $31). */
2452 || (! mips_opts.mips16
2453 && (prev_pinfo & INSN_WRITE_GPR_T)
2454 && (((pinfo & INSN_WRITE_GPR_D)
2455 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2456 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2457 || ((pinfo & INSN_WRITE_GPR_31)
2458 && (((prev_insn.insn_opcode >> OP_SH_RT)
2461 || (! mips_opts.mips16
2462 && (prev_pinfo & INSN_WRITE_GPR_D)
2463 && (((pinfo & INSN_WRITE_GPR_D)
2464 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2465 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2466 || ((pinfo & INSN_WRITE_GPR_31)
2467 && (((prev_insn.insn_opcode >> OP_SH_RD)
2470 || (mips_opts.mips16
2471 && (pinfo & MIPS16_INSN_WRITE_31)
2472 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2473 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2474 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2476 /* If the branch writes a register that the previous
2477 instruction reads, we can not swap (we know that
2478 branches only write to RD or to $31). */
2479 || (! mips_opts.mips16
2480 && (pinfo & INSN_WRITE_GPR_D)
2481 && insn_uses_reg (&prev_insn,
2482 ((ip->insn_opcode >> OP_SH_RD)
2485 || (! mips_opts.mips16
2486 && (pinfo & INSN_WRITE_GPR_31)
2487 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2488 || (mips_opts.mips16
2489 && (pinfo & MIPS16_INSN_WRITE_31)
2490 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2491 /* If we are generating embedded PIC code, the branch
2492 might be expanded into a sequence which uses $at, so
2493 we can't swap with an instruction which reads it. */
2494 || (mips_pic == EMBEDDED_PIC
2495 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2496 /* If the previous previous instruction has a load
2497 delay, and sets a register that the branch reads, we
2499 || (! mips_opts.mips16
2500 /* Itbl support may require additional care here. */
2501 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2502 && ! cop_interlocks)
2503 || ((prev_prev_insn.insn_mo->pinfo
2504 & INSN_LOAD_MEMORY_DELAY)
2505 && ! gpr_interlocks))
2506 && insn_uses_reg (ip,
2507 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2510 /* If one instruction sets a condition code and the
2511 other one uses a condition code, we can not swap. */
2512 || ((pinfo & INSN_READ_COND_CODE)
2513 && (prev_pinfo & INSN_WRITE_COND_CODE))
2514 || ((pinfo & INSN_WRITE_COND_CODE)
2515 && (prev_pinfo & INSN_READ_COND_CODE))
2516 /* If the previous instruction uses the PC, we can not
2518 || (mips_opts.mips16
2519 && (prev_pinfo & MIPS16_INSN_READ_PC))
2520 /* If the previous instruction was extended, we can not
2522 || (mips_opts.mips16 && prev_insn_extended)
2523 /* If the previous instruction had a fixup in mips16
2524 mode, we can not swap. This normally means that the
2525 previous instruction was a 4 byte branch anyhow. */
2526 || (mips_opts.mips16 && prev_insn_fixp[0])
2527 /* If the previous instruction is a sync, sync.l, or
2528 sync.p, we can not swap. */
2529 || (prev_pinfo & INSN_SYNC))
2531 /* We could do even better for unconditional branches to
2532 portions of this object file; we could pick up the
2533 instruction at the destination, put it in the delay
2534 slot, and bump the destination address. */
2536 /* Update the previous insn information. */
2537 prev_prev_insn = *ip;
2538 prev_insn.insn_mo = &dummy_opcode;
2542 /* It looks like we can actually do the swap. */
2543 if (! mips_opts.mips16)
2548 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2549 if (!relaxed_branch)
2551 /* If this is not a relaxed branch, then just
2552 swap the instructions. */
2553 memcpy (temp, prev_f, 4);
2554 memcpy (prev_f, f, 4);
2555 memcpy (f, temp, 4);
2559 /* If this is a relaxed branch, then we move the
2560 instruction to be placed in the delay slot to
2561 the current frag, shrinking the fixed part of
2562 the originating frag. If the branch occupies
2563 the tail of the latter, we move it backwards,
2564 into the space freed by the moved instruction. */
2566 memcpy (f, prev_f, 4);
2567 prev_insn_frag->fr_fix -= 4;
2568 if (prev_insn_frag->fr_type == rs_machine_dependent)
2569 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2572 if (prev_insn_fixp[0])
2574 prev_insn_fixp[0]->fx_frag = frag_now;
2575 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2577 if (prev_insn_fixp[1])
2579 prev_insn_fixp[1]->fx_frag = frag_now;
2580 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2582 if (prev_insn_fixp[2])
2584 prev_insn_fixp[2]->fx_frag = frag_now;
2585 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2587 if (prev_insn_fixp[0] && HAVE_NEWABI
2588 && prev_insn_frag != frag_now
2589 && (prev_insn_fixp[0]->fx_r_type
2590 == BFD_RELOC_MIPS_GOT_DISP
2591 || (prev_insn_fixp[0]->fx_r_type
2592 == BFD_RELOC_MIPS_CALL16)))
2594 /* To avoid confusion in tc_gen_reloc, we must
2595 ensure that this does not become a variant
2597 force_new_frag = TRUE;
2600 if (!relaxed_branch)
2604 fixp[0]->fx_frag = prev_insn_frag;
2605 fixp[0]->fx_where = prev_insn_where;
2609 fixp[1]->fx_frag = prev_insn_frag;
2610 fixp[1]->fx_where = prev_insn_where;
2614 fixp[2]->fx_frag = prev_insn_frag;
2615 fixp[2]->fx_where = prev_insn_where;
2618 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2621 fixp[0]->fx_where -= 4;
2623 fixp[1]->fx_where -= 4;
2625 fixp[2]->fx_where -= 4;
2633 assert (prev_insn_fixp[0] == NULL);
2634 assert (prev_insn_fixp[1] == NULL);
2635 assert (prev_insn_fixp[2] == NULL);
2636 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2637 memcpy (temp, prev_f, 2);
2638 memcpy (prev_f, f, 2);
2639 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2641 assert (*reloc_type == BFD_RELOC_UNUSED);
2642 memcpy (f, temp, 2);
2646 memcpy (f, f + 2, 2);
2647 memcpy (f + 2, temp, 2);
2651 fixp[0]->fx_frag = prev_insn_frag;
2652 fixp[0]->fx_where = prev_insn_where;
2656 fixp[1]->fx_frag = prev_insn_frag;
2657 fixp[1]->fx_where = prev_insn_where;
2661 fixp[2]->fx_frag = prev_insn_frag;
2662 fixp[2]->fx_where = prev_insn_where;
2666 /* Update the previous insn information; leave prev_insn
2668 prev_prev_insn = *ip;
2670 prev_insn_is_delay_slot = 1;
2672 /* If that was an unconditional branch, forget the previous
2673 insn information. */
2674 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2676 prev_prev_insn.insn_mo = &dummy_opcode;
2677 prev_insn.insn_mo = &dummy_opcode;
2680 prev_insn_fixp[0] = NULL;
2681 prev_insn_fixp[1] = NULL;
2682 prev_insn_fixp[2] = NULL;
2683 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2684 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2685 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2686 prev_insn_extended = 0;
2688 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2690 /* We don't yet optimize a branch likely. What we should do
2691 is look at the target, copy the instruction found there
2692 into the delay slot, and increment the branch to jump to
2693 the next instruction. */
2695 /* Update the previous insn information. */
2696 prev_prev_insn = *ip;
2697 prev_insn.insn_mo = &dummy_opcode;
2698 prev_insn_fixp[0] = NULL;
2699 prev_insn_fixp[1] = NULL;
2700 prev_insn_fixp[2] = NULL;
2701 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2702 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2703 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2704 prev_insn_extended = 0;
2708 /* Update the previous insn information. */
2710 prev_prev_insn.insn_mo = &dummy_opcode;
2712 prev_prev_insn = prev_insn;
2715 /* Any time we see a branch, we always fill the delay slot
2716 immediately; since this insn is not a branch, we know it
2717 is not in a delay slot. */
2718 prev_insn_is_delay_slot = 0;
2720 prev_insn_fixp[0] = fixp[0];
2721 prev_insn_fixp[1] = fixp[1];
2722 prev_insn_fixp[2] = fixp[2];
2723 prev_insn_reloc_type[0] = reloc_type[0];
2724 prev_insn_reloc_type[1] = reloc_type[1];
2725 prev_insn_reloc_type[2] = reloc_type[2];
2726 if (mips_opts.mips16)
2727 prev_insn_extended = (ip->use_extend
2728 || *reloc_type > BFD_RELOC_UNUSED);
2731 prev_prev_insn_unreordered = prev_insn_unreordered;
2732 prev_insn_unreordered = 0;
2733 prev_insn_frag = frag_now;
2734 prev_insn_where = f - frag_now->fr_literal;
2735 prev_insn_valid = 1;
2737 else if (mips_relax.sequence != 2)
2739 /* We need to record a bit of information even when we are not
2740 reordering, in order to determine the base address for mips16
2741 PC relative relocs. */
2742 prev_prev_insn = prev_insn;
2744 prev_insn_reloc_type[0] = reloc_type[0];
2745 prev_insn_reloc_type[1] = reloc_type[1];
2746 prev_insn_reloc_type[2] = reloc_type[2];
2747 prev_prev_insn_unreordered = prev_insn_unreordered;
2748 prev_insn_unreordered = 1;
2751 /* We just output an insn, so the next one doesn't have a label. */
2752 mips_clear_insn_labels ();
2755 /* This function forgets that there was any previous instruction or
2756 label. If PRESERVE is non-zero, it remembers enough information to
2757 know whether nops are needed before a noreorder section. */
2760 mips_no_prev_insn (int preserve)
2764 prev_insn.insn_mo = &dummy_opcode;
2765 prev_prev_insn.insn_mo = &dummy_opcode;
2766 prev_nop_frag = NULL;
2767 prev_nop_frag_holds = 0;
2768 prev_nop_frag_required = 0;
2769 prev_nop_frag_since = 0;
2771 prev_insn_valid = 0;
2772 prev_insn_is_delay_slot = 0;
2773 prev_insn_unreordered = 0;
2774 prev_insn_extended = 0;
2775 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2776 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2777 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2778 prev_prev_insn_unreordered = 0;
2779 mips_clear_insn_labels ();
2782 /* This function must be called whenever we turn on noreorder or emit
2783 something other than instructions. It inserts any NOPS which might
2784 be needed by the previous instruction, and clears the information
2785 kept for the previous instructions. The INSNS parameter is true if
2786 instructions are to follow. */
2789 mips_emit_delays (bfd_boolean insns)
2791 if (! mips_opts.noreorder)
2796 if ((! mips_opts.mips16
2797 && ((prev_insn.insn_mo->pinfo
2798 & (INSN_LOAD_COPROC_DELAY
2799 | INSN_COPROC_MOVE_DELAY
2800 | INSN_WRITE_COND_CODE))
2801 && ! cop_interlocks))
2802 || (! hilo_interlocks
2803 && (prev_insn.insn_mo->pinfo
2806 || (! mips_opts.mips16
2807 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2808 && ! gpr_interlocks)
2809 || (! mips_opts.mips16
2810 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2811 && ! cop_mem_interlocks))
2813 /* Itbl support may require additional care here. */
2815 if ((! mips_opts.mips16
2816 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2817 && ! cop_interlocks))
2818 || (! hilo_interlocks
2819 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2820 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2823 if (prev_insn_unreordered)
2826 else if ((! mips_opts.mips16
2827 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2828 && ! cop_interlocks))
2829 || (! hilo_interlocks
2830 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2831 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2833 /* Itbl support may require additional care here. */
2834 if (! prev_prev_insn_unreordered)
2838 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2841 const char *pn = prev_insn.insn_mo->name;
2842 if (strncmp(pn, "macc", 4) == 0
2843 || strncmp(pn, "dmacc", 5) == 0
2844 || strncmp(pn, "dmult", 5) == 0)
2848 if (nops < min_nops)
2854 struct insn_label_list *l;
2858 /* Record the frag which holds the nop instructions, so
2859 that we can remove them if we don't need them. */
2860 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2861 prev_nop_frag = frag_now;
2862 prev_nop_frag_holds = nops;
2863 prev_nop_frag_required = 0;
2864 prev_nop_frag_since = 0;
2867 for (; nops > 0; --nops)
2872 /* Move on to a new frag, so that it is safe to simply
2873 decrease the size of prev_nop_frag. */
2874 frag_wane (frag_now);
2878 for (l = insn_labels; l != NULL; l = l->next)
2882 assert (S_GET_SEGMENT (l->label) == now_seg);
2883 symbol_set_frag (l->label, frag_now);
2884 val = (valueT) frag_now_fix ();
2885 /* mips16 text labels are stored as odd. */
2886 if (mips_opts.mips16)
2888 S_SET_VALUE (l->label, val);
2893 /* Mark instruction labels in mips16 mode. */
2895 mips16_mark_labels ();
2897 mips_no_prev_insn (insns);
2900 /* Set up global variables for the start of a new macro. */
2905 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2906 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2907 && (prev_insn.insn_mo->pinfo
2908 & (INSN_UNCOND_BRANCH_DELAY
2909 | INSN_COND_BRANCH_DELAY
2910 | INSN_COND_BRANCH_LIKELY)) != 0);
2913 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2914 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2915 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2918 macro_warning (relax_substateT subtype)
2920 if (subtype & RELAX_DELAY_SLOT)
2921 return _("Macro instruction expanded into multiple instructions"
2922 " in a branch delay slot");
2923 else if (subtype & RELAX_NOMACRO)
2924 return _("Macro instruction expanded into multiple instructions");
2929 /* Finish up a macro. Emit warnings as appropriate. */
2934 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2936 relax_substateT subtype;
2938 /* Set up the relaxation warning flags. */
2940 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2941 subtype |= RELAX_SECOND_LONGER;
2942 if (mips_opts.warn_about_macros)
2943 subtype |= RELAX_NOMACRO;
2944 if (mips_macro_warning.delay_slot_p)
2945 subtype |= RELAX_DELAY_SLOT;
2947 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2949 /* Either the macro has a single implementation or both
2950 implementations are longer than 4 bytes. Emit the
2952 const char *msg = macro_warning (subtype);
2958 /* One implementation might need a warning but the other
2959 definitely doesn't. */
2960 mips_macro_warning.first_frag->fr_subtype |= subtype;
2965 /* Build an instruction created by a macro expansion. This is passed
2966 a pointer to the count of instructions created so far, an
2967 expression, the name of the instruction to build, an operand format
2968 string, and corresponding arguments. */
2971 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2973 struct mips_cl_insn insn;
2974 bfd_reloc_code_real_type r[3];
2977 va_start (args, fmt);
2979 if (mips_opts.mips16)
2981 mips16_macro_build (ep, name, fmt, args);
2986 r[0] = BFD_RELOC_UNUSED;
2987 r[1] = BFD_RELOC_UNUSED;
2988 r[2] = BFD_RELOC_UNUSED;
2989 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2990 assert (insn.insn_mo);
2991 assert (strcmp (name, insn.insn_mo->name) == 0);
2993 /* Search until we get a match for NAME. */
2996 /* It is assumed here that macros will never generate
2997 MDMX or MIPS-3D instructions. */
2998 if (strcmp (fmt, insn.insn_mo->args) == 0
2999 && insn.insn_mo->pinfo != INSN_MACRO
3000 && OPCODE_IS_MEMBER (insn.insn_mo,
3002 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3004 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3008 assert (insn.insn_mo->name);
3009 assert (strcmp (name, insn.insn_mo->name) == 0);
3012 insn.insn_opcode = insn.insn_mo->match;
3030 insn.insn_opcode |= (va_arg (args, int)
3031 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3036 /* Note that in the macro case, these arguments are already
3037 in MSB form. (When handling the instruction in the
3038 non-macro case, these arguments are sizes from which
3039 MSB values must be calculated.) */
3040 insn.insn_opcode |= (va_arg (args, int)
3041 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3047 /* Note that in the macro case, these arguments are already
3048 in MSBD form. (When handling the instruction in the
3049 non-macro case, these arguments are sizes from which
3050 MSBD values must be calculated.) */
3051 insn.insn_opcode |= (va_arg (args, int)
3052 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3063 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3067 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3072 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3078 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3083 int tmp = va_arg (args, int);
3085 insn.insn_opcode |= tmp << OP_SH_RT;
3086 insn.insn_opcode |= tmp << OP_SH_RD;
3092 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3099 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3103 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3107 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3111 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3115 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3122 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3128 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3129 assert (*r == BFD_RELOC_GPREL16
3130 || *r == BFD_RELOC_MIPS_LITERAL
3131 || *r == BFD_RELOC_MIPS_HIGHER
3132 || *r == BFD_RELOC_HI16_S
3133 || *r == BFD_RELOC_LO16
3134 || *r == BFD_RELOC_MIPS_GOT16
3135 || *r == BFD_RELOC_MIPS_CALL16
3136 || *r == BFD_RELOC_MIPS_GOT_DISP
3137 || *r == BFD_RELOC_MIPS_GOT_PAGE
3138 || *r == BFD_RELOC_MIPS_GOT_OFST
3139 || *r == BFD_RELOC_MIPS_GOT_LO16
3140 || *r == BFD_RELOC_MIPS_CALL_LO16
3141 || (ep->X_op == O_subtract
3142 && *r == BFD_RELOC_PCREL_LO16));
3146 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3148 && (ep->X_op == O_constant
3149 || (ep->X_op == O_symbol
3150 && (*r == BFD_RELOC_MIPS_HIGHEST
3151 || *r == BFD_RELOC_HI16_S
3152 || *r == BFD_RELOC_HI16
3153 || *r == BFD_RELOC_GPREL16
3154 || *r == BFD_RELOC_MIPS_GOT_HI16
3155 || *r == BFD_RELOC_MIPS_CALL_HI16))
3156 || (ep->X_op == O_subtract
3157 && *r == BFD_RELOC_PCREL_HI16_S)));
3161 assert (ep != NULL);
3163 * This allows macro() to pass an immediate expression for
3164 * creating short branches without creating a symbol.
3165 * Note that the expression still might come from the assembly
3166 * input, in which case the value is not checked for range nor
3167 * is a relocation entry generated (yuck).
3169 if (ep->X_op == O_constant)
3171 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3175 *r = BFD_RELOC_16_PCREL_S2;
3179 assert (ep != NULL);
3180 *r = BFD_RELOC_MIPS_JMP;
3184 insn.insn_opcode |= va_arg (args, unsigned long);
3193 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3195 append_insn (&insn, ep, r);
3199 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3202 struct mips_cl_insn insn;
3203 bfd_reloc_code_real_type r[3]
3204 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3206 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3207 assert (insn.insn_mo);
3208 assert (strcmp (name, insn.insn_mo->name) == 0);
3210 while (strcmp (fmt, insn.insn_mo->args) != 0
3211 || insn.insn_mo->pinfo == INSN_MACRO)
3214 assert (insn.insn_mo->name);
3215 assert (strcmp (name, insn.insn_mo->name) == 0);
3218 insn.insn_opcode = insn.insn_mo->match;
3219 insn.use_extend = FALSE;
3238 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3243 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3251 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3261 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3268 regno = va_arg (args, int);
3269 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3270 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3291 assert (ep != NULL);
3293 if (ep->X_op != O_constant)
3294 *r = (int) BFD_RELOC_UNUSED + c;
3297 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3298 FALSE, &insn.insn_opcode, &insn.use_extend,
3301 *r = BFD_RELOC_UNUSED;
3307 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3314 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3316 append_insn (&insn, ep, r);
3320 * Generate a "jalr" instruction with a relocation hint to the called
3321 * function. This occurs in NewABI PIC code.
3324 macro_build_jalr (expressionS *ep)
3333 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3335 fix_new_exp (frag_now, f - frag_now->fr_literal,
3336 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3340 * Generate a "lui" instruction.
3343 macro_build_lui (expressionS *ep, int regnum)
3345 expressionS high_expr;
3346 struct mips_cl_insn insn;
3347 bfd_reloc_code_real_type r[3]
3348 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3349 const char *name = "lui";
3350 const char *fmt = "t,u";
3352 assert (! mips_opts.mips16);
3356 if (high_expr.X_op == O_constant)
3358 /* we can compute the instruction now without a relocation entry */
3359 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3361 *r = BFD_RELOC_UNUSED;
3365 assert (ep->X_op == O_symbol);
3366 /* _gp_disp is a special case, used from s_cpload. */
3367 assert (mips_pic == NO_PIC
3369 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3370 *r = BFD_RELOC_HI16_S;
3373 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3374 assert (insn.insn_mo);
3375 assert (strcmp (name, insn.insn_mo->name) == 0);
3376 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3378 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3379 if (*r == BFD_RELOC_UNUSED)
3381 insn.insn_opcode |= high_expr.X_add_number;
3382 append_insn (&insn, NULL, r);
3385 append_insn (&insn, &high_expr, r);
3388 /* Generate a sequence of instructions to do a load or store from a constant
3389 offset off of a base register (breg) into/from a target register (treg),
3390 using AT if necessary. */
3392 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3393 int treg, int breg, int dbl)
3395 assert (ep->X_op == O_constant);
3397 /* Sign-extending 32-bit constants makes their handling easier. */
3398 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3399 == ~((bfd_vma) 0x7fffffff)))
3401 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3402 as_bad (_("constant too large"));
3404 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3408 /* Right now, this routine can only handle signed 32-bit constants. */
3409 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3410 as_warn (_("operand overflow"));
3412 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3414 /* Signed 16-bit offset will fit in the op. Easy! */
3415 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3419 /* 32-bit offset, need multiple instructions and AT, like:
3420 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3421 addu $tempreg,$tempreg,$breg
3422 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3423 to handle the complete offset. */
3424 macro_build_lui (ep, AT);
3425 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3426 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3429 as_warn (_("Macro used $at after \".set noat\""));
3434 * Generates code to set the $at register to true (one)
3435 * if reg is less than the immediate expression.
3438 set_at (int reg, int unsignedp)
3440 if (imm_expr.X_op == O_constant
3441 && imm_expr.X_add_number >= -0x8000
3442 && imm_expr.X_add_number < 0x8000)
3443 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3444 AT, reg, BFD_RELOC_LO16);
3447 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3448 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3453 normalize_constant_expr (expressionS *ex)
3455 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3456 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3460 /* Warn if an expression is not a constant. */
3463 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3465 if (ex->X_op == O_big)
3466 as_bad (_("unsupported large constant"));
3467 else if (ex->X_op != O_constant)
3468 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3470 normalize_constant_expr (ex);
3473 /* Count the leading zeroes by performing a binary chop. This is a
3474 bulky bit of source, but performance is a LOT better for the
3475 majority of values than a simple loop to count the bits:
3476 for (lcnt = 0; (lcnt < 32); lcnt++)
3477 if ((v) & (1 << (31 - lcnt)))
3479 However it is not code size friendly, and the gain will drop a bit
3480 on certain cached systems.
3482 #define COUNT_TOP_ZEROES(v) \
3483 (((v) & ~0xffff) == 0 \
3484 ? ((v) & ~0xff) == 0 \
3485 ? ((v) & ~0xf) == 0 \
3486 ? ((v) & ~0x3) == 0 \
3487 ? ((v) & ~0x1) == 0 \
3492 : ((v) & ~0x7) == 0 \
3495 : ((v) & ~0x3f) == 0 \
3496 ? ((v) & ~0x1f) == 0 \
3499 : ((v) & ~0x7f) == 0 \
3502 : ((v) & ~0xfff) == 0 \
3503 ? ((v) & ~0x3ff) == 0 \
3504 ? ((v) & ~0x1ff) == 0 \
3507 : ((v) & ~0x7ff) == 0 \
3510 : ((v) & ~0x3fff) == 0 \
3511 ? ((v) & ~0x1fff) == 0 \
3514 : ((v) & ~0x7fff) == 0 \
3517 : ((v) & ~0xffffff) == 0 \
3518 ? ((v) & ~0xfffff) == 0 \
3519 ? ((v) & ~0x3ffff) == 0 \
3520 ? ((v) & ~0x1ffff) == 0 \
3523 : ((v) & ~0x7ffff) == 0 \
3526 : ((v) & ~0x3fffff) == 0 \
3527 ? ((v) & ~0x1fffff) == 0 \
3530 : ((v) & ~0x7fffff) == 0 \
3533 : ((v) & ~0xfffffff) == 0 \
3534 ? ((v) & ~0x3ffffff) == 0 \
3535 ? ((v) & ~0x1ffffff) == 0 \
3538 : ((v) & ~0x7ffffff) == 0 \
3541 : ((v) & ~0x3fffffff) == 0 \
3542 ? ((v) & ~0x1fffffff) == 0 \
3545 : ((v) & ~0x7fffffff) == 0 \
3550 * This routine generates the least number of instructions necessary to load
3551 * an absolute expression value into a register.
3554 load_register (int reg, expressionS *ep, int dbl)
3557 expressionS hi32, lo32;
3559 if (ep->X_op != O_big)
3561 assert (ep->X_op == O_constant);
3563 /* Sign-extending 32-bit constants makes their handling easier. */
3564 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3565 == ~((bfd_vma) 0x7fffffff)))
3567 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3568 as_bad (_("constant too large"));
3570 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3574 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3576 /* We can handle 16 bit signed values with an addiu to
3577 $zero. No need to ever use daddiu here, since $zero and
3578 the result are always correct in 32 bit mode. */
3579 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3582 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3584 /* We can handle 16 bit unsigned values with an ori to
3586 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3589 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3591 /* 32 bit values require an lui. */
3592 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3593 if ((ep->X_add_number & 0xffff) != 0)
3594 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3599 /* The value is larger than 32 bits. */
3601 if (HAVE_32BIT_GPRS)
3603 as_bad (_("Number (0x%lx) larger than 32 bits"),
3604 (unsigned long) ep->X_add_number);
3605 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3609 if (ep->X_op != O_big)
3612 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3613 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3614 hi32.X_add_number &= 0xffffffff;
3616 lo32.X_add_number &= 0xffffffff;
3620 assert (ep->X_add_number > 2);
3621 if (ep->X_add_number == 3)
3622 generic_bignum[3] = 0;
3623 else if (ep->X_add_number > 4)
3624 as_bad (_("Number larger than 64 bits"));
3625 lo32.X_op = O_constant;
3626 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3627 hi32.X_op = O_constant;
3628 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3631 if (hi32.X_add_number == 0)
3636 unsigned long hi, lo;
3638 if (hi32.X_add_number == (offsetT) 0xffffffff)
3640 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3642 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3645 if (lo32.X_add_number & 0x80000000)
3647 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3648 if (lo32.X_add_number & 0xffff)
3649 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3654 /* Check for 16bit shifted constant. We know that hi32 is
3655 non-zero, so start the mask on the first bit of the hi32
3660 unsigned long himask, lomask;
3664 himask = 0xffff >> (32 - shift);
3665 lomask = (0xffff << shift) & 0xffffffff;
3669 himask = 0xffff << (shift - 32);
3672 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3673 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3677 tmp.X_op = O_constant;
3679 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3680 | (lo32.X_add_number >> shift));
3682 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3683 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3684 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3685 reg, reg, (shift >= 32) ? shift - 32 : shift);
3690 while (shift <= (64 - 16));
3692 /* Find the bit number of the lowest one bit, and store the
3693 shifted value in hi/lo. */
3694 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3695 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3699 while ((lo & 1) == 0)
3704 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3710 while ((hi & 1) == 0)
3719 /* Optimize if the shifted value is a (power of 2) - 1. */
3720 if ((hi == 0 && ((lo + 1) & lo) == 0)
3721 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3723 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3728 /* This instruction will set the register to be all
3730 tmp.X_op = O_constant;
3731 tmp.X_add_number = (offsetT) -1;
3732 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3736 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3737 reg, reg, (bit >= 32) ? bit - 32 : bit);
3739 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3740 reg, reg, (shift >= 32) ? shift - 32 : shift);
3745 /* Sign extend hi32 before calling load_register, because we can
3746 generally get better code when we load a sign extended value. */
3747 if ((hi32.X_add_number & 0x80000000) != 0)
3748 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3749 load_register (reg, &hi32, 0);
3752 if ((lo32.X_add_number & 0xffff0000) == 0)
3756 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3764 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3766 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3767 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3773 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3777 mid16.X_add_number >>= 16;
3778 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3779 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3782 if ((lo32.X_add_number & 0xffff) != 0)
3783 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3787 load_delay_nop (void)
3789 if (!gpr_interlocks)
3790 macro_build (NULL, "nop", "");
3793 /* Load an address into a register. */
3796 load_address (int reg, expressionS *ep, int *used_at)
3798 if (ep->X_op != O_constant
3799 && ep->X_op != O_symbol)
3801 as_bad (_("expression too complex"));
3802 ep->X_op = O_constant;
3805 if (ep->X_op == O_constant)
3807 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3811 if (mips_pic == NO_PIC)
3813 /* If this is a reference to a GP relative symbol, we want
3814 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3816 lui $reg,<sym> (BFD_RELOC_HI16_S)
3817 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3818 If we have an addend, we always use the latter form.
3820 With 64bit address space and a usable $at we want
3821 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3822 lui $at,<sym> (BFD_RELOC_HI16_S)
3823 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3824 daddiu $at,<sym> (BFD_RELOC_LO16)
3828 If $at is already in use, we use a path which is suboptimal
3829 on superscalar processors.
3830 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3831 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3833 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3835 daddiu $reg,<sym> (BFD_RELOC_LO16)
3837 if (HAVE_64BIT_ADDRESSES)
3839 /* ??? We don't provide a GP-relative alternative for these macros.
3840 It used not to be possible with the original relaxation code,
3841 but it could be done now. */
3843 if (*used_at == 0 && ! mips_opts.noat)
3845 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3846 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3847 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3848 BFD_RELOC_MIPS_HIGHER);
3849 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3850 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3851 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3856 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3857 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3858 BFD_RELOC_MIPS_HIGHER);
3859 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3860 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3861 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3862 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3867 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3868 && ! nopic_need_relax (ep->X_add_symbol, 1))
3870 relax_start (ep->X_add_symbol);
3871 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3872 mips_gp_register, BFD_RELOC_GPREL16);
3875 macro_build_lui (ep, reg);
3876 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3877 reg, reg, BFD_RELOC_LO16);
3878 if (mips_relax.sequence)
3882 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3886 /* If this is a reference to an external symbol, we want
3887 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3889 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3891 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3892 If there is a constant, it must be added in after.
3894 If we have NewABI, we want
3895 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3896 unless we're referencing a global symbol with a non-zero
3897 offset, in which case cst must be added separately. */
3900 if (ep->X_add_number)
3902 ex.X_add_number = ep->X_add_number;
3903 ep->X_add_number = 0;
3904 relax_start (ep->X_add_symbol);
3905 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3906 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3907 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3908 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3909 ex.X_op = O_constant;
3910 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3911 reg, reg, BFD_RELOC_LO16);
3912 ep->X_add_number = ex.X_add_number;
3915 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3916 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3917 if (mips_relax.sequence)
3922 ex.X_add_number = ep->X_add_number;
3923 ep->X_add_number = 0;
3924 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3925 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3927 relax_start (ep->X_add_symbol);
3929 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3933 if (ex.X_add_number != 0)
3935 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3936 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3937 ex.X_op = O_constant;
3938 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3939 reg, reg, BFD_RELOC_LO16);
3943 else if (mips_pic == SVR4_PIC)
3947 /* This is the large GOT case. If this is a reference to an
3948 external symbol, we want
3949 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3951 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3953 Otherwise, for a reference to a local symbol in old ABI, we want
3954 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3956 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3957 If there is a constant, it must be added in after.
3959 In the NewABI, for local symbols, with or without offsets, we want:
3960 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3961 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3965 ex.X_add_number = ep->X_add_number;
3966 ep->X_add_number = 0;
3967 relax_start (ep->X_add_symbol);
3968 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3969 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3970 reg, reg, mips_gp_register);
3971 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3972 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3973 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3974 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3975 else if (ex.X_add_number)
3977 ex.X_op = O_constant;
3978 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3982 ep->X_add_number = ex.X_add_number;
3984 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3985 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3986 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3987 BFD_RELOC_MIPS_GOT_OFST);
3992 ex.X_add_number = ep->X_add_number;
3993 ep->X_add_number = 0;
3994 relax_start (ep->X_add_symbol);
3995 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3996 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3997 reg, reg, mips_gp_register);
3998 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3999 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4001 if (reg_needs_delay (mips_gp_register))
4003 /* We need a nop before loading from $gp. This special
4004 check is required because the lui which starts the main
4005 instruction stream does not refer to $gp, and so will not
4006 insert the nop which may be required. */
4007 macro_build (NULL, "nop", "");
4009 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4010 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4012 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4016 if (ex.X_add_number != 0)
4018 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4019 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4020 ex.X_op = O_constant;
4021 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4026 else if (mips_pic == EMBEDDED_PIC)
4029 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4031 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4032 reg, mips_gp_register, BFD_RELOC_GPREL16);
4038 /* Move the contents of register SOURCE into register DEST. */
4041 move_register (int dest, int source)
4043 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4047 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4048 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4049 The two alternatives are:
4051 Global symbol Local sybmol
4052 ------------- ------------
4053 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4055 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4057 load_got_offset emits the first instruction and add_got_offset
4058 emits the second for a 16-bit offset or add_got_offset_hilo emits
4059 a sequence to add a 32-bit offset using a scratch register. */
4062 load_got_offset (int dest, expressionS *local)
4067 global.X_add_number = 0;
4069 relax_start (local->X_add_symbol);
4070 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4071 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4073 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4074 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4079 add_got_offset (int dest, expressionS *local)
4083 global.X_op = O_constant;
4084 global.X_op_symbol = NULL;
4085 global.X_add_symbol = NULL;
4086 global.X_add_number = local->X_add_number;
4088 relax_start (local->X_add_symbol);
4089 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4090 dest, dest, BFD_RELOC_LO16);
4092 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4097 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4100 int hold_mips_optimize;
4102 global.X_op = O_constant;
4103 global.X_op_symbol = NULL;
4104 global.X_add_symbol = NULL;
4105 global.X_add_number = local->X_add_number;
4107 relax_start (local->X_add_symbol);
4108 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4110 /* Set mips_optimize around the lui instruction to avoid
4111 inserting an unnecessary nop after the lw. */
4112 hold_mips_optimize = mips_optimize;
4114 macro_build_lui (&global, tmp);
4115 mips_optimize = hold_mips_optimize;
4116 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4124 * This routine implements the seemingly endless macro or synthesized
4125 * instructions and addressing modes in the mips assembly language. Many
4126 * of these macros are simple and are similar to each other. These could
4127 * probably be handled by some kind of table or grammar approach instead of
4128 * this verbose method. Others are not simple macros but are more like
4129 * optimizing code generation.
4130 * One interesting optimization is when several store macros appear
4131 * consecutively that would load AT with the upper half of the same address.
4132 * The ensuing load upper instructions are ommited. This implies some kind
4133 * of global optimization. We currently only optimize within a single macro.
4134 * For many of the load and store macros if the address is specified as a
4135 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4136 * first load register 'at' with zero and use it as the base register. The
4137 * mips assembler simply uses register $zero. Just one tiny optimization
4141 macro (struct mips_cl_insn *ip)
4143 register int treg, sreg, dreg, breg;
4159 bfd_reloc_code_real_type r;
4160 int hold_mips_optimize;
4162 assert (! mips_opts.mips16);
4164 treg = (ip->insn_opcode >> 16) & 0x1f;
4165 dreg = (ip->insn_opcode >> 11) & 0x1f;
4166 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4167 mask = ip->insn_mo->mask;
4169 expr1.X_op = O_constant;
4170 expr1.X_op_symbol = NULL;
4171 expr1.X_add_symbol = NULL;
4172 expr1.X_add_number = 1;
4184 mips_emit_delays (TRUE);
4185 ++mips_opts.noreorder;
4186 mips_any_noreorder = 1;
4188 expr1.X_add_number = 8;
4189 macro_build (&expr1, "bgez", "s,p", sreg);
4191 macro_build (NULL, "nop", "", 0);
4193 move_register (dreg, sreg);
4194 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4196 --mips_opts.noreorder;
4217 if (imm_expr.X_op == O_constant
4218 && imm_expr.X_add_number >= -0x8000
4219 && imm_expr.X_add_number < 0x8000)
4221 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4224 load_register (AT, &imm_expr, dbl);
4225 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4244 if (imm_expr.X_op == O_constant
4245 && imm_expr.X_add_number >= 0
4246 && imm_expr.X_add_number < 0x10000)
4248 if (mask != M_NOR_I)
4249 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4252 macro_build (&imm_expr, "ori", "t,r,i",
4253 treg, sreg, BFD_RELOC_LO16);
4254 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4259 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4260 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4277 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4279 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4282 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4283 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4291 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4296 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4299 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4300 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4306 /* check for > max integer */
4307 maxnum = 0x7fffffff;
4308 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4315 if (imm_expr.X_op == O_constant
4316 && imm_expr.X_add_number >= maxnum
4317 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4320 /* result is always false */
4322 macro_build (NULL, "nop", "", 0);
4324 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4327 if (imm_expr.X_op != O_constant)
4328 as_bad (_("Unsupported large constant"));
4329 ++imm_expr.X_add_number;
4333 if (mask == M_BGEL_I)
4335 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4337 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4340 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4342 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4345 maxnum = 0x7fffffff;
4346 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4353 maxnum = - maxnum - 1;
4354 if (imm_expr.X_op == O_constant
4355 && imm_expr.X_add_number <= maxnum
4356 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4359 /* result is always true */
4360 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4361 macro_build (&offset_expr, "b", "p");
4365 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4375 macro_build (&offset_expr, likely ? "beql" : "beq",
4379 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4380 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4388 && imm_expr.X_op == O_constant
4389 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4391 if (imm_expr.X_op != O_constant)
4392 as_bad (_("Unsupported large constant"));
4393 ++imm_expr.X_add_number;
4397 if (mask == M_BGEUL_I)
4399 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4401 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4403 macro_build (&offset_expr, likely ? "bnel" : "bne",
4408 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4416 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4421 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4424 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4425 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4433 macro_build (&offset_expr, likely ? "bnel" : "bne",
4439 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4440 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4448 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4453 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4456 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4457 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4463 maxnum = 0x7fffffff;
4464 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4471 if (imm_expr.X_op == O_constant
4472 && imm_expr.X_add_number >= maxnum
4473 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4475 if (imm_expr.X_op != O_constant)
4476 as_bad (_("Unsupported large constant"));
4477 ++imm_expr.X_add_number;
4481 if (mask == M_BLTL_I)
4483 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4485 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4488 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4490 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4494 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4502 macro_build (&offset_expr, likely ? "beql" : "beq",
4508 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4509 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4517 && imm_expr.X_op == O_constant
4518 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4520 if (imm_expr.X_op != O_constant)
4521 as_bad (_("Unsupported large constant"));
4522 ++imm_expr.X_add_number;
4526 if (mask == M_BLTUL_I)
4528 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4530 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4532 macro_build (&offset_expr, likely ? "beql" : "beq",
4537 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4545 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4550 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4553 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4554 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4564 macro_build (&offset_expr, likely ? "bnel" : "bne",
4568 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4569 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4577 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4579 as_bad (_("Unsupported large constant"));
4584 pos = (unsigned long) imm_expr.X_add_number;
4585 size = (unsigned long) imm2_expr.X_add_number;
4590 as_bad (_("Improper position (%lu)"), pos);
4593 if (size == 0 || size > 64
4594 || (pos + size - 1) > 63)
4596 as_bad (_("Improper extract size (%lu, position %lu)"),
4601 if (size <= 32 && pos < 32)
4606 else if (size <= 32)
4616 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4625 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4627 as_bad (_("Unsupported large constant"));
4632 pos = (unsigned long) imm_expr.X_add_number;
4633 size = (unsigned long) imm2_expr.X_add_number;
4638 as_bad (_("Improper position (%lu)"), pos);
4641 if (size == 0 || size > 64
4642 || (pos + size - 1) > 63)
4644 as_bad (_("Improper insert size (%lu, position %lu)"),
4649 if (pos < 32 && (pos + size - 1) < 32)
4664 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4681 as_warn (_("Divide by zero."));
4683 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4685 macro_build (NULL, "break", "c", 7);
4689 mips_emit_delays (TRUE);
4690 ++mips_opts.noreorder;
4691 mips_any_noreorder = 1;
4694 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4695 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4699 expr1.X_add_number = 8;
4700 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4701 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4702 macro_build (NULL, "break", "c", 7);
4704 expr1.X_add_number = -1;
4705 load_register (AT, &expr1, dbl);
4706 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4707 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4710 expr1.X_add_number = 1;
4711 load_register (AT, &expr1, dbl);
4712 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4716 expr1.X_add_number = 0x80000000;
4717 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4721 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4722 /* We want to close the noreorder block as soon as possible, so
4723 that later insns are available for delay slot filling. */
4724 --mips_opts.noreorder;
4728 expr1.X_add_number = 8;
4729 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4730 macro_build (NULL, "nop", "", 0);
4732 /* We want to close the noreorder block as soon as possible, so
4733 that later insns are available for delay slot filling. */
4734 --mips_opts.noreorder;
4736 macro_build (NULL, "break", "c", 6);
4738 macro_build (NULL, s, "d", dreg);
4777 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4779 as_warn (_("Divide by zero."));
4781 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4783 macro_build (NULL, "break", "c", 7);
4786 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4788 if (strcmp (s2, "mflo") == 0)
4789 move_register (dreg, sreg);
4791 move_register (dreg, 0);
4794 if (imm_expr.X_op == O_constant
4795 && imm_expr.X_add_number == -1
4796 && s[strlen (s) - 1] != 'u')
4798 if (strcmp (s2, "mflo") == 0)
4800 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4803 move_register (dreg, 0);
4807 load_register (AT, &imm_expr, dbl);
4808 macro_build (NULL, s, "z,s,t", sreg, AT);
4809 macro_build (NULL, s2, "d", dreg);
4828 mips_emit_delays (TRUE);
4829 ++mips_opts.noreorder;
4830 mips_any_noreorder = 1;
4833 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4834 macro_build (NULL, s, "z,s,t", sreg, treg);
4835 /* We want to close the noreorder block as soon as possible, so
4836 that later insns are available for delay slot filling. */
4837 --mips_opts.noreorder;
4841 expr1.X_add_number = 8;
4842 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4843 macro_build (NULL, s, "z,s,t", sreg, treg);
4845 /* We want to close the noreorder block as soon as possible, so
4846 that later insns are available for delay slot filling. */
4847 --mips_opts.noreorder;
4848 macro_build (NULL, "break", "c", 7);
4850 macro_build (NULL, s2, "d", dreg);
4862 /* Load the address of a symbol into a register. If breg is not
4863 zero, we then add a base register to it. */
4865 if (dbl && HAVE_32BIT_GPRS)
4866 as_warn (_("dla used to load 32-bit register"));
4868 if (! dbl && HAVE_64BIT_OBJECTS)
4869 as_warn (_("la used to load 64-bit address"));
4871 if (offset_expr.X_op == O_constant
4872 && offset_expr.X_add_number >= -0x8000
4873 && offset_expr.X_add_number < 0x8000)
4875 macro_build (&offset_expr,
4876 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4877 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4892 /* When generating embedded PIC code, we permit expressions of
4895 la $treg,foo-bar($breg)
4896 where bar is an address in the current section. These are used
4897 when getting the addresses of functions. We don't permit
4898 X_add_number to be non-zero, because if the symbol is
4899 external the relaxing code needs to know that any addend is
4900 purely the offset to X_op_symbol. */
4901 if (mips_pic == EMBEDDED_PIC
4902 && offset_expr.X_op == O_subtract
4903 && (symbol_constant_p (offset_expr.X_op_symbol)
4904 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4905 : (symbol_equated_p (offset_expr.X_op_symbol)
4907 (symbol_get_value_expression (offset_expr.X_op_symbol)
4910 && (offset_expr.X_add_number == 0
4911 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4917 macro_build (&offset_expr, "lui", "t,u",
4918 tempreg, BFD_RELOC_PCREL_HI16_S);
4922 macro_build (&offset_expr, "lui", "t,u",
4923 tempreg, BFD_RELOC_PCREL_HI16_S);
4925 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4926 "d,v,t", tempreg, tempreg, breg);
4928 macro_build (&offset_expr,
4929 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4930 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4936 if (offset_expr.X_op != O_symbol
4937 && offset_expr.X_op != O_constant)
4939 as_bad (_("expression too complex"));
4940 offset_expr.X_op = O_constant;
4943 if (offset_expr.X_op == O_constant)
4944 load_register (tempreg, &offset_expr,
4945 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4946 ? (dbl || HAVE_64BIT_ADDRESSES)
4947 : HAVE_64BIT_ADDRESSES));
4948 else if (mips_pic == NO_PIC)
4950 /* If this is a reference to a GP relative symbol, we want
4951 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4953 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4954 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4955 If we have a constant, we need two instructions anyhow,
4956 so we may as well always use the latter form.
4958 With 64bit address space and a usable $at we want
4959 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4960 lui $at,<sym> (BFD_RELOC_HI16_S)
4961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4962 daddiu $at,<sym> (BFD_RELOC_LO16)
4964 daddu $tempreg,$tempreg,$at
4966 If $at is already in use, we use a path which is suboptimal
4967 on superscalar processors.
4968 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4969 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4971 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4973 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4975 if (HAVE_64BIT_ADDRESSES)
4977 /* ??? We don't provide a GP-relative alternative for
4978 these macros. It used not to be possible with the
4979 original relaxation code, but it could be done now. */
4981 if (used_at == 0 && ! mips_opts.noat)
4983 macro_build (&offset_expr, "lui", "t,u",
4984 tempreg, BFD_RELOC_MIPS_HIGHEST);
4985 macro_build (&offset_expr, "lui", "t,u",
4986 AT, BFD_RELOC_HI16_S);
4987 macro_build (&offset_expr, "daddiu", "t,r,j",
4988 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4989 macro_build (&offset_expr, "daddiu", "t,r,j",
4990 AT, AT, BFD_RELOC_LO16);
4991 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4992 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4997 macro_build (&offset_expr, "lui", "t,u",
4998 tempreg, BFD_RELOC_MIPS_HIGHEST);
4999 macro_build (&offset_expr, "daddiu", "t,r,j",
5000 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5001 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5002 macro_build (&offset_expr, "daddiu", "t,r,j",
5003 tempreg, tempreg, BFD_RELOC_HI16_S);
5004 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5005 macro_build (&offset_expr, "daddiu", "t,r,j",
5006 tempreg, tempreg, BFD_RELOC_LO16);
5011 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5012 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5014 relax_start (offset_expr.X_add_symbol);
5015 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5016 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5019 macro_build_lui (&offset_expr, tempreg);
5020 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5021 tempreg, tempreg, BFD_RELOC_LO16);
5022 if (mips_relax.sequence)
5026 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5028 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5030 /* If this is a reference to an external symbol, and there
5031 is no constant, we want
5032 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5033 or for lca or if tempreg is PIC_CALL_REG
5034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5035 For a local symbol, we want
5036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5038 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5040 If we have a small constant, and this is a reference to
5041 an external symbol, we want
5042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5044 addiu $tempreg,$tempreg,<constant>
5045 For a local symbol, we want the same instruction
5046 sequence, but we output a BFD_RELOC_LO16 reloc on the
5049 If we have a large constant, and this is a reference to
5050 an external symbol, we want
5051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5052 lui $at,<hiconstant>
5053 addiu $at,$at,<loconstant>
5054 addu $tempreg,$tempreg,$at
5055 For a local symbol, we want the same instruction
5056 sequence, but we output a BFD_RELOC_LO16 reloc on the
5060 if (offset_expr.X_add_number == 0)
5062 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5063 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5065 relax_start (offset_expr.X_add_symbol);
5066 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5067 lw_reloc_type, mips_gp_register);
5070 /* We're going to put in an addu instruction using
5071 tempreg, so we may as well insert the nop right
5076 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5077 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5079 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5080 tempreg, tempreg, BFD_RELOC_LO16);
5082 /* FIXME: If breg == 0, and the next instruction uses
5083 $tempreg, then if this variant case is used an extra
5084 nop will be generated. */
5086 else if (offset_expr.X_add_number >= -0x8000
5087 && offset_expr.X_add_number < 0x8000)
5089 load_got_offset (tempreg, &offset_expr);
5091 add_got_offset (tempreg, &offset_expr);
5095 expr1.X_add_number = offset_expr.X_add_number;
5096 offset_expr.X_add_number =
5097 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5098 load_got_offset (tempreg, &offset_expr);
5099 offset_expr.X_add_number = expr1.X_add_number;
5100 /* If we are going to add in a base register, and the
5101 target register and the base register are the same,
5102 then we are using AT as a temporary register. Since
5103 we want to load the constant into AT, we add our
5104 current AT (from the global offset table) and the
5105 register into the register now, and pretend we were
5106 not using a base register. */
5110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5115 add_got_offset_hilo (tempreg, &offset_expr, AT);
5119 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5121 int add_breg_early = 0;
5123 /* If this is a reference to an external, and there is no
5124 constant, or local symbol (*), with or without a
5126 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5127 or for lca or if tempreg is PIC_CALL_REG
5128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5130 If we have a small constant, and this is a reference to
5131 an external symbol, we want
5132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5133 addiu $tempreg,$tempreg,<constant>
5135 If we have a large constant, and this is a reference to
5136 an external symbol, we want
5137 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5138 lui $at,<hiconstant>
5139 addiu $at,$at,<loconstant>
5140 addu $tempreg,$tempreg,$at
5142 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5143 local symbols, even though it introduces an additional
5146 if (offset_expr.X_add_number)
5148 expr1.X_add_number = offset_expr.X_add_number;
5149 offset_expr.X_add_number = 0;
5151 relax_start (offset_expr.X_add_symbol);
5152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5153 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5155 if (expr1.X_add_number >= -0x8000
5156 && expr1.X_add_number < 0x8000)
5158 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5159 tempreg, tempreg, BFD_RELOC_LO16);
5161 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5165 /* If we are going to add in a base register, and the
5166 target register and the base register are the same,
5167 then we are using AT as a temporary register. Since
5168 we want to load the constant into AT, we add our
5169 current AT (from the global offset table) and the
5170 register into the register now, and pretend we were
5171 not using a base register. */
5176 assert (tempreg == AT);
5177 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5183 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5184 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5190 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5193 offset_expr.X_add_number = expr1.X_add_number;
5195 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5196 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5199 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5200 treg, tempreg, breg);
5206 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5208 relax_start (offset_expr.X_add_symbol);
5209 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5210 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5212 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5213 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5218 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5219 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5222 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5225 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5226 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5227 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5229 /* This is the large GOT case. If this is a reference to an
5230 external symbol, and there is no constant, we want
5231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5232 addu $tempreg,$tempreg,$gp
5233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5234 or for lca or if tempreg is PIC_CALL_REG
5235 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5236 addu $tempreg,$tempreg,$gp
5237 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5238 For a local symbol, we want
5239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5241 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5243 If we have a small constant, and this is a reference to
5244 an external symbol, we want
5245 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5246 addu $tempreg,$tempreg,$gp
5247 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5249 addiu $tempreg,$tempreg,<constant>
5250 For a local symbol, we want
5251 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5253 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5255 If we have a large constant, and this is a reference to
5256 an external symbol, we want
5257 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5258 addu $tempreg,$tempreg,$gp
5259 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5260 lui $at,<hiconstant>
5261 addiu $at,$at,<loconstant>
5262 addu $tempreg,$tempreg,$at
5263 For a local symbol, we want
5264 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5265 lui $at,<hiconstant>
5266 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5267 addu $tempreg,$tempreg,$at
5270 expr1.X_add_number = offset_expr.X_add_number;
5271 offset_expr.X_add_number = 0;
5272 relax_start (offset_expr.X_add_symbol);
5273 gpdelay = reg_needs_delay (mips_gp_register);
5274 if (expr1.X_add_number == 0 && breg == 0
5275 && (call || tempreg == PIC_CALL_REG))
5277 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5278 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5280 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5281 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5282 tempreg, tempreg, mips_gp_register);
5283 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5284 tempreg, lw_reloc_type, tempreg);
5285 if (expr1.X_add_number == 0)
5289 /* We're going to put in an addu instruction using
5290 tempreg, so we may as well insert the nop right
5295 else if (expr1.X_add_number >= -0x8000
5296 && expr1.X_add_number < 0x8000)
5299 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5300 tempreg, tempreg, BFD_RELOC_LO16);
5306 /* If we are going to add in a base register, and the
5307 target register and the base register are the same,
5308 then we are using AT as a temporary register. Since
5309 we want to load the constant into AT, we add our
5310 current AT (from the global offset table) and the
5311 register into the register now, and pretend we were
5312 not using a base register. */
5317 assert (tempreg == AT);
5319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5324 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5329 offset_expr.X_add_number =
5330 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5335 /* This is needed because this instruction uses $gp, but
5336 the first instruction on the main stream does not. */
5337 macro_build (NULL, "nop", "");
5340 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5341 local_reloc_type, mips_gp_register);
5342 if (expr1.X_add_number >= -0x8000
5343 && expr1.X_add_number < 0x8000)
5346 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5347 tempreg, tempreg, BFD_RELOC_LO16);
5348 /* FIXME: If add_number is 0, and there was no base
5349 register, the external symbol case ended with a load,
5350 so if the symbol turns out to not be external, and
5351 the next instruction uses tempreg, an unnecessary nop
5352 will be inserted. */
5358 /* We must add in the base register now, as in the
5359 external symbol case. */
5360 assert (tempreg == AT);
5362 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5365 /* We set breg to 0 because we have arranged to add
5366 it in in both cases. */
5370 macro_build_lui (&expr1, AT);
5371 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5372 AT, AT, BFD_RELOC_LO16);
5373 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5374 tempreg, tempreg, AT);
5378 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5380 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5381 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5382 int add_breg_early = 0;
5384 /* This is the large GOT case. If this is a reference to an
5385 external symbol, and there is no constant, we want
5386 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5387 add $tempreg,$tempreg,$gp
5388 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5389 or for lca or if tempreg is PIC_CALL_REG
5390 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5391 add $tempreg,$tempreg,$gp
5392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5394 If we have a small constant, and this is a reference to
5395 an external symbol, we want
5396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5397 add $tempreg,$tempreg,$gp
5398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5399 addi $tempreg,$tempreg,<constant>
5401 If we have a large constant, and this is a reference to
5402 an external symbol, we want
5403 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5404 addu $tempreg,$tempreg,$gp
5405 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5406 lui $at,<hiconstant>
5407 addi $at,$at,<loconstant>
5408 add $tempreg,$tempreg,$at
5410 If we have NewABI, and we know it's a local symbol, we want
5411 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5412 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5413 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5415 relax_start (offset_expr.X_add_symbol);
5417 expr1.X_add_number = offset_expr.X_add_number;
5418 offset_expr.X_add_number = 0;
5420 if (expr1.X_add_number == 0 && breg == 0
5421 && (call || tempreg == PIC_CALL_REG))
5423 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5424 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5426 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5427 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5428 tempreg, tempreg, mips_gp_register);
5429 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5430 tempreg, lw_reloc_type, tempreg);
5432 if (expr1.X_add_number == 0)
5434 else if (expr1.X_add_number >= -0x8000
5435 && expr1.X_add_number < 0x8000)
5437 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5438 tempreg, tempreg, BFD_RELOC_LO16);
5440 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5444 /* If we are going to add in a base register, and the
5445 target register and the base register are the same,
5446 then we are using AT as a temporary register. Since
5447 we want to load the constant into AT, we add our
5448 current AT (from the global offset table) and the
5449 register into the register now, and pretend we were
5450 not using a base register. */
5455 assert (tempreg == AT);
5456 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5462 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5463 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5468 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5471 offset_expr.X_add_number = expr1.X_add_number;
5472 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5473 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5474 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5475 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5478 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5479 treg, tempreg, breg);
5485 else if (mips_pic == EMBEDDED_PIC)
5488 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5490 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5491 mips_gp_register, BFD_RELOC_GPREL16);
5500 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5501 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5503 s = ADDRESS_ADD_INSN;
5505 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5514 /* The j instruction may not be used in PIC code, since it
5515 requires an absolute address. We convert it to a b
5517 if (mips_pic == NO_PIC)
5518 macro_build (&offset_expr, "j", "a");
5520 macro_build (&offset_expr, "b", "p");
5523 /* The jal instructions must be handled as macros because when
5524 generating PIC code they expand to multi-instruction
5525 sequences. Normally they are simple instructions. */
5530 if (mips_pic == NO_PIC
5531 || mips_pic == EMBEDDED_PIC)
5532 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5533 else if (mips_pic == SVR4_PIC)
5535 if (sreg != PIC_CALL_REG)
5536 as_warn (_("MIPS PIC call to register other than $25"));
5538 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5541 if (mips_cprestore_offset < 0)
5542 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5545 if (! mips_frame_reg_valid)
5547 as_warn (_("No .frame pseudo-op used in PIC code"));
5548 /* Quiet this warning. */
5549 mips_frame_reg_valid = 1;
5551 if (! mips_cprestore_valid)
5553 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5554 /* Quiet this warning. */
5555 mips_cprestore_valid = 1;
5557 expr1.X_add_number = mips_cprestore_offset;
5558 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5561 HAVE_64BIT_ADDRESSES);
5571 if (mips_pic == NO_PIC)
5572 macro_build (&offset_expr, "jal", "a");
5573 else if (mips_pic == SVR4_PIC)
5575 /* If this is a reference to an external symbol, and we are
5576 using a small GOT, we want
5577 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5581 lw $gp,cprestore($sp)
5582 The cprestore value is set using the .cprestore
5583 pseudo-op. If we are using a big GOT, we want
5584 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5586 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5590 lw $gp,cprestore($sp)
5591 If the symbol is not external, we want
5592 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5594 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5597 lw $gp,cprestore($sp)
5599 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5600 sequences above, minus nops, unless the symbol is local,
5601 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5607 relax_start (offset_expr.X_add_symbol);
5608 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5609 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5613 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5619 relax_start (offset_expr.X_add_symbol);
5620 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5621 BFD_RELOC_MIPS_CALL_HI16);
5622 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5623 PIC_CALL_REG, mips_gp_register);
5624 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5625 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5628 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5629 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5631 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5632 PIC_CALL_REG, PIC_CALL_REG,
5633 BFD_RELOC_MIPS_GOT_OFST);
5637 macro_build_jalr (&offset_expr);
5641 relax_start (offset_expr.X_add_symbol);
5644 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5645 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5654 gpdelay = reg_needs_delay (mips_gp_register);
5655 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5656 BFD_RELOC_MIPS_CALL_HI16);
5657 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5658 PIC_CALL_REG, mips_gp_register);
5659 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5660 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5665 macro_build (NULL, "nop", "");
5667 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5668 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5671 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5672 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5674 macro_build_jalr (&offset_expr);
5676 if (mips_cprestore_offset < 0)
5677 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5680 if (! mips_frame_reg_valid)
5682 as_warn (_("No .frame pseudo-op used in PIC code"));
5683 /* Quiet this warning. */
5684 mips_frame_reg_valid = 1;
5686 if (! mips_cprestore_valid)
5688 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5689 /* Quiet this warning. */
5690 mips_cprestore_valid = 1;
5692 if (mips_opts.noreorder)
5693 macro_build (NULL, "nop", "");
5694 expr1.X_add_number = mips_cprestore_offset;
5695 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5698 HAVE_64BIT_ADDRESSES);
5702 else if (mips_pic == EMBEDDED_PIC)
5704 macro_build (&offset_expr, "bal", "p");
5705 /* The linker may expand the call to a longer sequence which
5706 uses $at, so we must break rather than return. */
5731 /* Itbl support may require additional care here. */
5736 /* Itbl support may require additional care here. */
5741 /* Itbl support may require additional care here. */
5746 /* Itbl support may require additional care here. */
5758 if (mips_opts.arch == CPU_R4650)
5760 as_bad (_("opcode not supported on this processor"));
5764 /* Itbl support may require additional care here. */
5769 /* Itbl support may require additional care here. */
5774 /* Itbl support may require additional care here. */
5794 if (breg == treg || coproc || lr)
5816 /* Itbl support may require additional care here. */
5821 /* Itbl support may require additional care here. */
5826 /* Itbl support may require additional care here. */
5831 /* Itbl support may require additional care here. */
5847 if (mips_opts.arch == CPU_R4650)
5849 as_bad (_("opcode not supported on this processor"));
5854 /* Itbl support may require additional care here. */
5858 /* Itbl support may require additional care here. */
5863 /* Itbl support may require additional care here. */
5875 /* Itbl support may require additional care here. */
5876 if (mask == M_LWC1_AB
5877 || mask == M_SWC1_AB
5878 || mask == M_LDC1_AB
5879 || mask == M_SDC1_AB
5888 /* Sign-extending 32-bit constants makes their handling easier.
5889 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5891 if ((! HAVE_64BIT_ADDRESSES
5892 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5893 && (offset_expr.X_op == O_constant)
5894 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5895 == ~((bfd_vma) 0x7fffffff)))
5897 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5898 as_bad (_("constant too large"));
5900 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5901 ^ 0x80000000) - 0x80000000);
5904 /* For embedded PIC, we allow loads where the offset is calculated
5905 by subtracting a symbol in the current segment from an unknown
5906 symbol, relative to a base register, e.g.:
5907 <op> $treg, <sym>-<localsym>($breg)
5908 This is used by the compiler for switch statements. */
5909 if (mips_pic == EMBEDDED_PIC
5910 && offset_expr.X_op == O_subtract
5911 && (symbol_constant_p (offset_expr.X_op_symbol)
5912 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5913 : (symbol_equated_p (offset_expr.X_op_symbol)
5915 (symbol_get_value_expression (offset_expr.X_op_symbol)
5919 && (offset_expr.X_add_number == 0
5920 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5922 /* For this case, we output the instructions:
5923 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5924 addiu $tempreg,$tempreg,$breg
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5926 If the relocation would fit entirely in 16 bits, it would be
5928 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5929 instead, but that seems quite difficult. */
5930 macro_build (&offset_expr, "lui", "t,u", tempreg,
5931 BFD_RELOC_PCREL_HI16_S);
5933 ((bfd_arch_bits_per_address (stdoutput) == 32
5934 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5935 ? "addu" : "daddu"),
5936 "d,v,t", tempreg, tempreg, breg);
5937 macro_build (&offset_expr, s, fmt, treg,
5938 BFD_RELOC_PCREL_LO16, tempreg);
5944 if (offset_expr.X_op != O_constant
5945 && offset_expr.X_op != O_symbol)
5947 as_bad (_("expression too complex"));
5948 offset_expr.X_op = O_constant;
5951 /* A constant expression in PIC code can be handled just as it
5952 is in non PIC code. */
5953 if (mips_pic == NO_PIC
5954 || offset_expr.X_op == O_constant)
5956 /* If this is a reference to a GP relative symbol, and there
5957 is no base register, we want
5958 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5959 Otherwise, if there is no base register, we want
5960 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5961 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5962 If we have a constant, we need two instructions anyhow,
5963 so we always use the latter form.
5965 If we have a base register, and this is a reference to a
5966 GP relative symbol, we want
5967 addu $tempreg,$breg,$gp
5968 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5970 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5971 addu $tempreg,$tempreg,$breg
5972 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5973 With a constant we always use the latter case.
5975 With 64bit address space and no base register and $at usable,
5977 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5978 lui $at,<sym> (BFD_RELOC_HI16_S)
5979 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5982 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5983 If we have a base register, we want
5984 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5985 lui $at,<sym> (BFD_RELOC_HI16_S)
5986 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5990 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5992 Without $at we can't generate the optimal path for superscalar
5993 processors here since this would require two temporary registers.
5994 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5995 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5997 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5999 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6000 If we have a base register, we want
6001 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6002 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6004 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6006 daddu $tempreg,$tempreg,$breg
6007 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6009 If we have 64-bit addresses, as an optimization, for
6010 addresses which are 32-bit constants (e.g. kseg0/kseg1
6011 addresses) we fall back to the 32-bit address generation
6012 mechanism since it is more efficient. Note that due to
6013 the signed offset used by memory operations, the 32-bit
6014 range is shifted down by 32768 here. This code should
6015 probably attempt to generate 64-bit constants more
6016 efficiently in general.
6018 As an extension for architectures with 64-bit registers,
6019 we don't truncate 64-bit addresses given as literal
6020 constants down to 32 bits, to support existing practice
6021 in the mips64 Linux (the kernel), that compiles source
6022 files with -mabi=64, assembling them as o32 or n32 (with
6023 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6024 the whole kernel is loaded into a memory region that is
6025 addressable with sign-extended 32-bit addresses, it is
6026 wasteful to compute the upper 32 bits of every
6027 non-literal address, that takes more space and time.
6028 Some day this should probably be implemented as an
6029 assembler option, such that the kernel doesn't have to
6030 use such ugly hacks, even though it will still have to
6031 end up converting the binary to ELF32 for a number of
6032 platforms whose boot loaders don't support ELF64
6034 if ((HAVE_64BIT_ADDRESSES
6035 && ! (offset_expr.X_op == O_constant
6036 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6038 && offset_expr.X_op == O_constant
6039 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6041 /* ??? We don't provide a GP-relative alternative for
6042 these macros. It used not to be possible with the
6043 original relaxation code, but it could be done now. */
6045 if (used_at == 0 && ! mips_opts.noat)
6047 macro_build (&offset_expr, "lui", "t,u", tempreg,
6048 BFD_RELOC_MIPS_HIGHEST);
6049 macro_build (&offset_expr, "lui", "t,u", AT,
6051 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6052 tempreg, BFD_RELOC_MIPS_HIGHER);
6054 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6055 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6056 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6057 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6063 macro_build (&offset_expr, "lui", "t,u", tempreg,
6064 BFD_RELOC_MIPS_HIGHEST);
6065 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6066 tempreg, BFD_RELOC_MIPS_HIGHER);
6067 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6068 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6069 tempreg, BFD_RELOC_HI16_S);
6070 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6072 macro_build (NULL, "daddu", "d,v,t",
6073 tempreg, tempreg, breg);
6074 macro_build (&offset_expr, s, fmt, treg,
6075 BFD_RELOC_LO16, tempreg);
6081 if (offset_expr.X_op == O_constant
6082 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6083 as_bad (_("load/store address overflow (max 32 bits)"));
6087 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6088 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6090 relax_start (offset_expr.X_add_symbol);
6091 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6096 macro_build_lui (&offset_expr, tempreg);
6097 macro_build (&offset_expr, s, fmt, treg,
6098 BFD_RELOC_LO16, tempreg);
6099 if (mips_relax.sequence)
6104 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6105 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6107 relax_start (offset_expr.X_add_symbol);
6108 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6109 tempreg, breg, mips_gp_register);
6110 macro_build (&offset_expr, s, fmt, treg,
6111 BFD_RELOC_GPREL16, tempreg);
6114 macro_build_lui (&offset_expr, tempreg);
6115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6116 tempreg, tempreg, breg);
6117 macro_build (&offset_expr, s, fmt, treg,
6118 BFD_RELOC_LO16, tempreg);
6119 if (mips_relax.sequence)
6123 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6125 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6127 /* If this is a reference to an external symbol, we want
6128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6130 <op> $treg,0($tempreg)
6132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6134 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6135 <op> $treg,0($tempreg)
6138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6139 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6141 If there is a base register, we add it to $tempreg before
6142 the <op>. If there is a constant, we stick it in the
6143 <op> instruction. We don't handle constants larger than
6144 16 bits, because we have no way to load the upper 16 bits
6145 (actually, we could handle them for the subset of cases
6146 in which we are not using $at). */
6147 assert (offset_expr.X_op == O_symbol);
6150 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6151 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6153 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6154 tempreg, tempreg, breg);
6155 macro_build (&offset_expr, s, fmt, treg,
6156 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6163 expr1.X_add_number = offset_expr.X_add_number;
6164 offset_expr.X_add_number = 0;
6165 if (expr1.X_add_number < -0x8000
6166 || expr1.X_add_number >= 0x8000)
6167 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6168 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6169 lw_reloc_type, mips_gp_register);
6171 relax_start (offset_expr.X_add_symbol);
6173 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6174 tempreg, BFD_RELOC_LO16);
6177 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6178 tempreg, tempreg, breg);
6179 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6181 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6185 /* If this is a reference to an external symbol, we want
6186 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6187 addu $tempreg,$tempreg,$gp
6188 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6189 <op> $treg,0($tempreg)
6191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6193 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6194 <op> $treg,0($tempreg)
6195 If there is a base register, we add it to $tempreg before
6196 the <op>. If there is a constant, we stick it in the
6197 <op> instruction. We don't handle constants larger than
6198 16 bits, because we have no way to load the upper 16 bits
6199 (actually, we could handle them for the subset of cases
6200 in which we are not using $at). */
6201 assert (offset_expr.X_op == O_symbol);
6202 expr1.X_add_number = offset_expr.X_add_number;
6203 offset_expr.X_add_number = 0;
6204 if (expr1.X_add_number < -0x8000
6205 || expr1.X_add_number >= 0x8000)
6206 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6207 gpdelay = reg_needs_delay (mips_gp_register);
6208 relax_start (offset_expr.X_add_symbol);
6209 macro_build (&offset_expr, "lui", "t,u", tempreg,
6210 BFD_RELOC_MIPS_GOT_HI16);
6211 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6213 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6214 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6217 macro_build (NULL, "nop", "");
6218 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6219 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6221 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6222 tempreg, BFD_RELOC_LO16);
6226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6227 tempreg, tempreg, breg);
6228 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6230 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6232 /* If this is a reference to an external symbol, we want
6233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6234 add $tempreg,$tempreg,$gp
6235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6236 <op> $treg,<ofst>($tempreg)
6237 Otherwise, for local symbols, we want:
6238 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6239 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6240 assert (offset_expr.X_op == O_symbol);
6241 expr1.X_add_number = offset_expr.X_add_number;
6242 offset_expr.X_add_number = 0;
6243 if (expr1.X_add_number < -0x8000
6244 || expr1.X_add_number >= 0x8000)
6245 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6246 relax_start (offset_expr.X_add_symbol);
6247 macro_build (&offset_expr, "lui", "t,u", tempreg,
6248 BFD_RELOC_MIPS_GOT_HI16);
6249 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6251 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6252 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6254 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6255 tempreg, tempreg, breg);
6256 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6259 offset_expr.X_add_number = expr1.X_add_number;
6260 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6261 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6264 tempreg, tempreg, breg);
6265 macro_build (&offset_expr, s, fmt, treg,
6266 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6269 else if (mips_pic == EMBEDDED_PIC)
6271 /* If there is no base register, we want
6272 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6273 If there is a base register, we want
6274 addu $tempreg,$breg,$gp
6275 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6277 assert (offset_expr.X_op == O_symbol);
6280 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6286 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6287 tempreg, breg, mips_gp_register);
6288 macro_build (&offset_expr, s, fmt, treg,
6289 BFD_RELOC_GPREL16, tempreg);
6302 load_register (treg, &imm_expr, 0);
6306 load_register (treg, &imm_expr, 1);
6310 if (imm_expr.X_op == O_constant)
6312 load_register (AT, &imm_expr, 0);
6313 macro_build (NULL, "mtc1", "t,G", AT, treg);
6318 assert (offset_expr.X_op == O_symbol
6319 && strcmp (segment_name (S_GET_SEGMENT
6320 (offset_expr.X_add_symbol)),
6322 && offset_expr.X_add_number == 0);
6323 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6324 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6329 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6330 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6331 order 32 bits of the value and the low order 32 bits are either
6332 zero or in OFFSET_EXPR. */
6333 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6335 if (HAVE_64BIT_GPRS)
6336 load_register (treg, &imm_expr, 1);
6341 if (target_big_endian)
6353 load_register (hreg, &imm_expr, 0);
6356 if (offset_expr.X_op == O_absent)
6357 move_register (lreg, 0);
6360 assert (offset_expr.X_op == O_constant);
6361 load_register (lreg, &offset_expr, 0);
6368 /* We know that sym is in the .rdata section. First we get the
6369 upper 16 bits of the address. */
6370 if (mips_pic == NO_PIC)
6372 macro_build_lui (&offset_expr, AT);
6374 else if (mips_pic == SVR4_PIC)
6376 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6377 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6379 else if (mips_pic == EMBEDDED_PIC)
6381 /* For embedded PIC we pick up the entire address off $gp in
6382 a single instruction. */
6383 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
6384 mips_gp_register, BFD_RELOC_GPREL16);
6385 offset_expr.X_op = O_constant;
6386 offset_expr.X_add_number = 0;
6391 /* Now we load the register(s). */
6392 if (HAVE_64BIT_GPRS)
6393 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6396 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6399 /* FIXME: How in the world do we deal with the possible
6401 offset_expr.X_add_number += 4;
6402 macro_build (&offset_expr, "lw", "t,o(b)",
6403 treg + 1, BFD_RELOC_LO16, AT);
6409 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6410 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6411 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6412 the value and the low order 32 bits are either zero or in
6414 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6416 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6417 if (HAVE_64BIT_FPRS)
6419 assert (HAVE_64BIT_GPRS);
6420 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6424 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6425 if (offset_expr.X_op == O_absent)
6426 macro_build (NULL, "mtc1", "t,G", 0, treg);
6429 assert (offset_expr.X_op == O_constant);
6430 load_register (AT, &offset_expr, 0);
6431 macro_build (NULL, "mtc1", "t,G", AT, treg);
6437 assert (offset_expr.X_op == O_symbol
6438 && offset_expr.X_add_number == 0);
6439 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6440 if (strcmp (s, ".lit8") == 0)
6442 if (mips_opts.isa != ISA_MIPS1)
6444 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6445 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6448 breg = mips_gp_register;
6449 r = BFD_RELOC_MIPS_LITERAL;
6454 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6455 if (mips_pic == SVR4_PIC)
6456 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6457 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6460 /* FIXME: This won't work for a 64 bit address. */
6461 macro_build_lui (&offset_expr, AT);
6464 if (mips_opts.isa != ISA_MIPS1)
6466 macro_build (&offset_expr, "ldc1", "T,o(b)",
6467 treg, BFD_RELOC_LO16, AT);
6476 if (mips_opts.arch == CPU_R4650)
6478 as_bad (_("opcode not supported on this processor"));
6481 /* Even on a big endian machine $fn comes before $fn+1. We have
6482 to adjust when loading from memory. */
6485 assert (mips_opts.isa == ISA_MIPS1);
6486 macro_build (&offset_expr, "lwc1", "T,o(b)",
6487 target_big_endian ? treg + 1 : treg, r, breg);
6488 /* FIXME: A possible overflow which I don't know how to deal
6490 offset_expr.X_add_number += 4;
6491 macro_build (&offset_expr, "lwc1", "T,o(b)",
6492 target_big_endian ? treg : treg + 1, r, breg);
6500 * The MIPS assembler seems to check for X_add_number not
6501 * being double aligned and generating:
6504 * addiu at,at,%lo(foo+1)
6507 * But, the resulting address is the same after relocation so why
6508 * generate the extra instruction?
6510 if (mips_opts.arch == CPU_R4650)
6512 as_bad (_("opcode not supported on this processor"));
6515 /* Itbl support may require additional care here. */
6517 if (mips_opts.isa != ISA_MIPS1)
6528 if (mips_opts.arch == CPU_R4650)
6530 as_bad (_("opcode not supported on this processor"));
6534 if (mips_opts.isa != ISA_MIPS1)
6542 /* Itbl support may require additional care here. */
6547 if (HAVE_64BIT_GPRS)
6558 if (HAVE_64BIT_GPRS)
6568 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6569 loads for the case of doing a pair of loads to simulate an 'ld'.
6570 This is not currently done by the compiler, and assembly coders
6571 writing embedded-pic code can cope. */
6573 if (offset_expr.X_op != O_symbol
6574 && offset_expr.X_op != O_constant)
6576 as_bad (_("expression too complex"));
6577 offset_expr.X_op = O_constant;
6580 /* Even on a big endian machine $fn comes before $fn+1. We have
6581 to adjust when loading from memory. We set coproc if we must
6582 load $fn+1 first. */
6583 /* Itbl support may require additional care here. */
6584 if (! target_big_endian)
6587 if (mips_pic == NO_PIC
6588 || offset_expr.X_op == O_constant)
6590 /* If this is a reference to a GP relative symbol, we want
6591 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6592 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6593 If we have a base register, we use this
6595 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6596 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6597 If this is not a GP relative symbol, we want
6598 lui $at,<sym> (BFD_RELOC_HI16_S)
6599 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6600 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6601 If there is a base register, we add it to $at after the
6602 lui instruction. If there is a constant, we always use
6604 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6605 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6609 relax_start (offset_expr.X_add_symbol);
6612 tempreg = mips_gp_register;
6617 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6618 AT, breg, mips_gp_register);
6623 /* Itbl support may require additional care here. */
6624 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6625 BFD_RELOC_GPREL16, tempreg);
6626 offset_expr.X_add_number += 4;
6628 /* Set mips_optimize to 2 to avoid inserting an
6630 hold_mips_optimize = mips_optimize;
6632 /* Itbl support may require additional care here. */
6633 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6634 BFD_RELOC_GPREL16, tempreg);
6635 mips_optimize = hold_mips_optimize;
6639 /* We just generated two relocs. When tc_gen_reloc
6640 handles this case, it will skip the first reloc and
6641 handle the second. The second reloc already has an
6642 extra addend of 4, which we added above. We must
6643 subtract it out, and then subtract another 4 to make
6644 the first reloc come out right. The second reloc
6645 will come out right because we are going to add 4 to
6646 offset_expr when we build its instruction below.
6648 If we have a symbol, then we don't want to include
6649 the offset, because it will wind up being included
6650 when we generate the reloc. */
6652 if (offset_expr.X_op == O_constant)
6653 offset_expr.X_add_number -= 8;
6656 offset_expr.X_add_number = -4;
6657 offset_expr.X_op = O_constant;
6660 macro_build_lui (&offset_expr, AT);
6662 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6663 /* Itbl support may require additional care here. */
6664 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6665 BFD_RELOC_LO16, AT);
6666 /* FIXME: How do we handle overflow here? */
6667 offset_expr.X_add_number += 4;
6668 /* Itbl support may require additional care here. */
6669 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6670 BFD_RELOC_LO16, AT);
6671 if (mips_relax.sequence)
6674 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6676 /* If this is a reference to an external symbol, we want
6677 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6682 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6684 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6685 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6686 If there is a base register we add it to $at before the
6687 lwc1 instructions. If there is a constant we include it
6688 in the lwc1 instructions. */
6690 expr1.X_add_number = offset_expr.X_add_number;
6691 if (expr1.X_add_number < -0x8000
6692 || expr1.X_add_number >= 0x8000 - 4)
6693 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6694 load_got_offset (AT, &offset_expr);
6697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6699 /* Set mips_optimize to 2 to avoid inserting an undesired
6701 hold_mips_optimize = mips_optimize;
6704 /* Itbl support may require additional care here. */
6705 relax_start (offset_expr.X_add_symbol);
6706 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6707 BFD_RELOC_LO16, AT);
6708 expr1.X_add_number += 4;
6709 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6710 BFD_RELOC_LO16, AT);
6712 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6713 BFD_RELOC_LO16, AT);
6714 offset_expr.X_add_number += 4;
6715 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6716 BFD_RELOC_LO16, AT);
6719 mips_optimize = hold_mips_optimize;
6721 else if (mips_pic == SVR4_PIC)
6725 /* If this is a reference to an external symbol, we want
6726 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6728 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6733 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6735 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6736 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6737 If there is a base register we add it to $at before the
6738 lwc1 instructions. If there is a constant we include it
6739 in the lwc1 instructions. */
6741 expr1.X_add_number = offset_expr.X_add_number;
6742 offset_expr.X_add_number = 0;
6743 if (expr1.X_add_number < -0x8000
6744 || expr1.X_add_number >= 0x8000 - 4)
6745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6746 gpdelay = reg_needs_delay (mips_gp_register);
6747 relax_start (offset_expr.X_add_symbol);
6748 macro_build (&offset_expr, "lui", "t,u",
6749 AT, BFD_RELOC_MIPS_GOT_HI16);
6750 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6751 AT, AT, mips_gp_register);
6752 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6753 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6756 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6757 /* Itbl support may require additional care here. */
6758 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6759 BFD_RELOC_LO16, AT);
6760 expr1.X_add_number += 4;
6762 /* Set mips_optimize to 2 to avoid inserting an undesired
6764 hold_mips_optimize = mips_optimize;
6766 /* Itbl support may require additional care here. */
6767 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6768 BFD_RELOC_LO16, AT);
6769 mips_optimize = hold_mips_optimize;
6770 expr1.X_add_number -= 4;
6773 offset_expr.X_add_number = expr1.X_add_number;
6775 macro_build (NULL, "nop", "");
6776 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6777 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6780 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6781 /* Itbl support may require additional care here. */
6782 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6783 BFD_RELOC_LO16, AT);
6784 offset_expr.X_add_number += 4;
6786 /* Set mips_optimize to 2 to avoid inserting an undesired
6788 hold_mips_optimize = mips_optimize;
6790 /* Itbl support may require additional care here. */
6791 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6792 BFD_RELOC_LO16, AT);
6793 mips_optimize = hold_mips_optimize;
6796 else if (mips_pic == EMBEDDED_PIC)
6798 /* If there is no base register, we use
6799 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6800 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6801 If we have a base register, we use
6803 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6804 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6808 tempreg = mips_gp_register;
6813 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6814 AT, breg, mips_gp_register);
6819 /* Itbl support may require additional care here. */
6820 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6821 BFD_RELOC_GPREL16, tempreg);
6822 offset_expr.X_add_number += 4;
6823 /* Itbl support may require additional care here. */
6824 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6825 BFD_RELOC_GPREL16, tempreg);
6841 assert (HAVE_32BIT_ADDRESSES);
6842 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6843 offset_expr.X_add_number += 4;
6844 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6847 /* New code added to support COPZ instructions.
6848 This code builds table entries out of the macros in mip_opcodes.
6849 R4000 uses interlocks to handle coproc delays.
6850 Other chips (like the R3000) require nops to be inserted for delays.
6852 FIXME: Currently, we require that the user handle delays.
6853 In order to fill delay slots for non-interlocked chips,
6854 we must have a way to specify delays based on the coprocessor.
6855 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6856 What are the side-effects of the cop instruction?
6857 What cache support might we have and what are its effects?
6858 Both coprocessor & memory require delays. how long???
6859 What registers are read/set/modified?
6861 If an itbl is provided to interpret cop instructions,
6862 this knowledge can be encoded in the itbl spec. */
6876 /* For now we just do C (same as Cz). The parameter will be
6877 stored in insn_opcode by mips_ip. */
6878 macro_build (NULL, s, "C", ip->insn_opcode);
6882 move_register (dreg, sreg);
6885 #ifdef LOSING_COMPILER
6887 /* Try and see if this is a new itbl instruction.
6888 This code builds table entries out of the macros in mip_opcodes.
6889 FIXME: For now we just assemble the expression and pass it's
6890 value along as a 32-bit immediate.
6891 We may want to have the assembler assemble this value,
6892 so that we gain the assembler's knowledge of delay slots,
6894 Would it be more efficient to use mask (id) here? */
6895 if (itbl_have_entries
6896 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6898 s = ip->insn_mo->name;
6900 coproc = ITBL_DECODE_PNUM (immed_expr);;
6901 macro_build (&immed_expr, s, "C");
6908 as_warn (_("Macro used $at after \".set noat\""));
6912 macro2 (struct mips_cl_insn *ip)
6914 register int treg, sreg, dreg, breg;
6929 bfd_reloc_code_real_type r;
6931 treg = (ip->insn_opcode >> 16) & 0x1f;
6932 dreg = (ip->insn_opcode >> 11) & 0x1f;
6933 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6934 mask = ip->insn_mo->mask;
6936 expr1.X_op = O_constant;
6937 expr1.X_op_symbol = NULL;
6938 expr1.X_add_symbol = NULL;
6939 expr1.X_add_number = 1;
6943 #endif /* LOSING_COMPILER */
6948 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6949 macro_build (NULL, "mflo", "d", dreg);
6955 /* The MIPS assembler some times generates shifts and adds. I'm
6956 not trying to be that fancy. GCC should do this for us
6958 load_register (AT, &imm_expr, dbl);
6959 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6960 macro_build (NULL, "mflo", "d", dreg);
6973 mips_emit_delays (TRUE);
6974 ++mips_opts.noreorder;
6975 mips_any_noreorder = 1;
6977 load_register (AT, &imm_expr, dbl);
6978 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6979 macro_build (NULL, "mflo", "d", dreg);
6980 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6981 macro_build (NULL, "mfhi", "d", AT);
6983 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6986 expr1.X_add_number = 8;
6987 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6988 macro_build (NULL, "nop", "", 0);
6989 macro_build (NULL, "break", "c", 6);
6991 --mips_opts.noreorder;
6992 macro_build (NULL, "mflo", "d", dreg);
7005 mips_emit_delays (TRUE);
7006 ++mips_opts.noreorder;
7007 mips_any_noreorder = 1;
7009 load_register (AT, &imm_expr, dbl);
7010 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7011 sreg, imm ? AT : treg);
7012 macro_build (NULL, "mfhi", "d", AT);
7013 macro_build (NULL, "mflo", "d", dreg);
7015 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7018 expr1.X_add_number = 8;
7019 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7020 macro_build (NULL, "nop", "", 0);
7021 macro_build (NULL, "break", "c", 6);
7023 --mips_opts.noreorder;
7027 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7039 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7040 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7045 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7046 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7047 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7048 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7052 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7064 macro_build (NULL, "negu", "d,w", tempreg, treg);
7065 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7070 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7071 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7072 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7073 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7081 if (imm_expr.X_op != O_constant)
7082 as_bad (_("Improper rotate count"));
7083 rot = imm_expr.X_add_number & 0x3f;
7084 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7086 rot = (64 - rot) & 0x3f;
7088 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7090 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7095 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7098 l = (rot < 0x20) ? "dsll" : "dsll32";
7099 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7101 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7102 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7103 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7111 if (imm_expr.X_op != O_constant)
7112 as_bad (_("Improper rotate count"));
7113 rot = imm_expr.X_add_number & 0x1f;
7114 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7116 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7121 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7124 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7125 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7126 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7131 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7133 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7136 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7137 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7138 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7139 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7143 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7145 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7148 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7149 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7150 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7151 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7159 if (imm_expr.X_op != O_constant)
7160 as_bad (_("Improper rotate count"));
7161 rot = imm_expr.X_add_number & 0x3f;
7162 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7165 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7167 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7172 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7175 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7176 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7178 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7179 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7180 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7188 if (imm_expr.X_op != O_constant)
7189 as_bad (_("Improper rotate count"));
7190 rot = imm_expr.X_add_number & 0x1f;
7191 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7193 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7198 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7201 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7202 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7203 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7208 if (mips_opts.arch == CPU_R4650)
7210 as_bad (_("opcode not supported on this processor"));
7213 assert (mips_opts.isa == ISA_MIPS1);
7214 /* Even on a big endian machine $fn comes before $fn+1. We have
7215 to adjust when storing to memory. */
7216 macro_build (&offset_expr, "swc1", "T,o(b)",
7217 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7218 offset_expr.X_add_number += 4;
7219 macro_build (&offset_expr, "swc1", "T,o(b)",
7220 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7225 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7227 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7230 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7231 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7236 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7238 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7243 as_warn (_("Instruction %s: result is always false"),
7245 move_register (dreg, 0);
7248 if (imm_expr.X_op == O_constant
7249 && imm_expr.X_add_number >= 0
7250 && imm_expr.X_add_number < 0x10000)
7252 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7255 else if (imm_expr.X_op == O_constant
7256 && imm_expr.X_add_number > -0x8000
7257 && imm_expr.X_add_number < 0)
7259 imm_expr.X_add_number = -imm_expr.X_add_number;
7260 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7261 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7266 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7267 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7270 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7275 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7281 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7282 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7285 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7287 if (imm_expr.X_op == O_constant
7288 && imm_expr.X_add_number >= -0x8000
7289 && imm_expr.X_add_number < 0x8000)
7291 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7292 dreg, sreg, BFD_RELOC_LO16);
7297 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7298 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7302 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7307 case M_SGT: /* sreg > treg <==> treg < sreg */
7313 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7316 case M_SGT_I: /* sreg > I <==> I < sreg */
7322 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7323 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7326 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7332 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7333 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7336 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7342 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7343 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7344 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7348 if (imm_expr.X_op == O_constant
7349 && imm_expr.X_add_number >= -0x8000
7350 && imm_expr.X_add_number < 0x8000)
7352 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7355 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7356 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7360 if (imm_expr.X_op == O_constant
7361 && imm_expr.X_add_number >= -0x8000
7362 && imm_expr.X_add_number < 0x8000)
7364 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7368 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7369 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7374 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7376 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7379 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7380 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7385 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7387 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7392 as_warn (_("Instruction %s: result is always true"),
7394 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7395 dreg, 0, BFD_RELOC_LO16);
7398 if (imm_expr.X_op == O_constant
7399 && imm_expr.X_add_number >= 0
7400 && imm_expr.X_add_number < 0x10000)
7402 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7405 else if (imm_expr.X_op == O_constant
7406 && imm_expr.X_add_number > -0x8000
7407 && imm_expr.X_add_number < 0)
7409 imm_expr.X_add_number = -imm_expr.X_add_number;
7410 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7411 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7416 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7417 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7420 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7428 if (imm_expr.X_op == O_constant
7429 && imm_expr.X_add_number > -0x8000
7430 && imm_expr.X_add_number <= 0x8000)
7432 imm_expr.X_add_number = -imm_expr.X_add_number;
7433 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7434 dreg, sreg, BFD_RELOC_LO16);
7437 load_register (AT, &imm_expr, dbl);
7438 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7444 if (imm_expr.X_op == O_constant
7445 && imm_expr.X_add_number > -0x8000
7446 && imm_expr.X_add_number <= 0x8000)
7448 imm_expr.X_add_number = -imm_expr.X_add_number;
7449 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7450 dreg, sreg, BFD_RELOC_LO16);
7453 load_register (AT, &imm_expr, dbl);
7454 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7475 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7476 macro_build (NULL, s, "s,t", sreg, AT);
7481 assert (mips_opts.isa == ISA_MIPS1);
7482 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7483 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7486 * Is the double cfc1 instruction a bug in the mips assembler;
7487 * or is there a reason for it?
7489 mips_emit_delays (TRUE);
7490 ++mips_opts.noreorder;
7491 mips_any_noreorder = 1;
7492 macro_build (NULL, "cfc1", "t,G", treg, RA);
7493 macro_build (NULL, "cfc1", "t,G", treg, RA);
7494 macro_build (NULL, "nop", "");
7495 expr1.X_add_number = 3;
7496 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7497 expr1.X_add_number = 2;
7498 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7499 macro_build (NULL, "ctc1", "t,G", AT, RA);
7500 macro_build (NULL, "nop", "");
7501 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7503 macro_build (NULL, "ctc1", "t,G", treg, RA);
7504 macro_build (NULL, "nop", "");
7505 --mips_opts.noreorder;
7514 if (offset_expr.X_add_number >= 0x7fff)
7515 as_bad (_("operand overflow"));
7516 if (! target_big_endian)
7517 ++offset_expr.X_add_number;
7518 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7519 if (! target_big_endian)
7520 --offset_expr.X_add_number;
7522 ++offset_expr.X_add_number;
7523 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7524 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7525 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7538 if (offset_expr.X_add_number >= 0x8000 - off)
7539 as_bad (_("operand overflow"));
7544 if (! target_big_endian)
7545 offset_expr.X_add_number += off;
7546 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7547 if (! target_big_endian)
7548 offset_expr.X_add_number -= off;
7550 offset_expr.X_add_number += off;
7551 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7553 /* If necessary, move the result in tempreg the final destination. */
7554 if (treg == tempreg)
7556 /* Protect second load's delay slot. */
7558 move_register (treg, tempreg);
7572 load_address (AT, &offset_expr, &used_at);
7574 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7575 if (! target_big_endian)
7576 expr1.X_add_number = off;
7578 expr1.X_add_number = 0;
7579 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7580 if (! target_big_endian)
7581 expr1.X_add_number = 0;
7583 expr1.X_add_number = off;
7584 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7590 load_address (AT, &offset_expr, &used_at);
7592 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7593 if (target_big_endian)
7594 expr1.X_add_number = 0;
7595 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7596 treg, BFD_RELOC_LO16, AT);
7597 if (target_big_endian)
7598 expr1.X_add_number = 1;
7600 expr1.X_add_number = 0;
7601 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7602 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7603 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7607 if (offset_expr.X_add_number >= 0x7fff)
7608 as_bad (_("operand overflow"));
7609 if (target_big_endian)
7610 ++offset_expr.X_add_number;
7611 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7612 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7613 if (target_big_endian)
7614 --offset_expr.X_add_number;
7616 ++offset_expr.X_add_number;
7617 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7630 if (offset_expr.X_add_number >= 0x8000 - off)
7631 as_bad (_("operand overflow"));
7632 if (! target_big_endian)
7633 offset_expr.X_add_number += off;
7634 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7635 if (! target_big_endian)
7636 offset_expr.X_add_number -= off;
7638 offset_expr.X_add_number += off;
7639 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7653 load_address (AT, &offset_expr, &used_at);
7655 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7656 if (! target_big_endian)
7657 expr1.X_add_number = off;
7659 expr1.X_add_number = 0;
7660 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7661 if (! target_big_endian)
7662 expr1.X_add_number = 0;
7664 expr1.X_add_number = off;
7665 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7670 load_address (AT, &offset_expr, &used_at);
7672 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7673 if (! target_big_endian)
7674 expr1.X_add_number = 0;
7675 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7676 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7677 if (! target_big_endian)
7678 expr1.X_add_number = 1;
7680 expr1.X_add_number = 0;
7681 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7682 if (! target_big_endian)
7683 expr1.X_add_number = 0;
7685 expr1.X_add_number = 1;
7686 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7687 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7688 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7692 /* FIXME: Check if this is one of the itbl macros, since they
7693 are added dynamically. */
7694 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7698 as_warn (_("Macro used $at after \".set noat\""));
7701 /* Implement macros in mips16 mode. */
7704 mips16_macro (struct mips_cl_insn *ip)
7707 int xreg, yreg, zreg, tmp;
7710 const char *s, *s2, *s3;
7712 mask = ip->insn_mo->mask;
7714 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7715 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7716 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7718 expr1.X_op = O_constant;
7719 expr1.X_op_symbol = NULL;
7720 expr1.X_add_symbol = NULL;
7721 expr1.X_add_number = 1;
7740 mips_emit_delays (TRUE);
7741 ++mips_opts.noreorder;
7742 mips_any_noreorder = 1;
7743 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7744 expr1.X_add_number = 2;
7745 macro_build (&expr1, "bnez", "x,p", yreg);
7746 macro_build (NULL, "break", "6", 7);
7748 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7749 since that causes an overflow. We should do that as well,
7750 but I don't see how to do the comparisons without a temporary
7752 --mips_opts.noreorder;
7753 macro_build (NULL, s, "x", zreg);
7772 mips_emit_delays (TRUE);
7773 ++mips_opts.noreorder;
7774 mips_any_noreorder = 1;
7775 macro_build (NULL, s, "0,x,y", xreg, yreg);
7776 expr1.X_add_number = 2;
7777 macro_build (&expr1, "bnez", "x,p", yreg);
7778 macro_build (NULL, "break", "6", 7);
7779 --mips_opts.noreorder;
7780 macro_build (NULL, s2, "x", zreg);
7786 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7787 macro_build (NULL, "mflo", "x", zreg);
7795 if (imm_expr.X_op != O_constant)
7796 as_bad (_("Unsupported large constant"));
7797 imm_expr.X_add_number = -imm_expr.X_add_number;
7798 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7802 if (imm_expr.X_op != O_constant)
7803 as_bad (_("Unsupported large constant"));
7804 imm_expr.X_add_number = -imm_expr.X_add_number;
7805 macro_build (&imm_expr, "addiu", "x,k", xreg);
7809 if (imm_expr.X_op != O_constant)
7810 as_bad (_("Unsupported large constant"));
7811 imm_expr.X_add_number = -imm_expr.X_add_number;
7812 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7834 goto do_reverse_branch;
7838 goto do_reverse_branch;
7850 goto do_reverse_branch;
7861 macro_build (NULL, s, "x,y", xreg, yreg);
7862 macro_build (&offset_expr, s2, "p");
7889 goto do_addone_branch_i;
7894 goto do_addone_branch_i;
7909 goto do_addone_branch_i;
7916 if (imm_expr.X_op != O_constant)
7917 as_bad (_("Unsupported large constant"));
7918 ++imm_expr.X_add_number;
7921 macro_build (&imm_expr, s, s3, xreg);
7922 macro_build (&offset_expr, s2, "p");
7926 expr1.X_add_number = 0;
7927 macro_build (&expr1, "slti", "x,8", yreg);
7929 move_register (xreg, yreg);
7930 expr1.X_add_number = 2;
7931 macro_build (&expr1, "bteqz", "p");
7932 macro_build (NULL, "neg", "x,w", xreg, xreg);
7936 /* For consistency checking, verify that all bits are specified either
7937 by the match/mask part of the instruction definition, or by the
7940 validate_mips_insn (const struct mips_opcode *opc)
7942 const char *p = opc->args;
7944 unsigned long used_bits = opc->mask;
7946 if ((used_bits & opc->match) != opc->match)
7948 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7949 opc->name, opc->args);
7952 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7962 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7963 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7964 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7965 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7966 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7967 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7968 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7969 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7970 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7973 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7974 c, opc->name, opc->args);
7978 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7979 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7981 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7982 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7983 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7984 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7986 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7987 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7989 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7990 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7992 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7993 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7994 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7995 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7996 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7997 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7998 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7999 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8000 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8001 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8002 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8003 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8004 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8005 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8006 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8007 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8008 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8010 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8011 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8012 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8013 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8015 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8016 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8017 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8018 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8019 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8020 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8021 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8022 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8023 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8026 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8027 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8028 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8029 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8030 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8034 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8035 c, opc->name, opc->args);
8039 if (used_bits != 0xffffffff)
8041 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8042 ~used_bits & 0xffffffff, opc->name, opc->args);
8048 /* This routine assembles an instruction into its binary format. As a
8049 side effect, it sets one of the global variables imm_reloc or
8050 offset_reloc to the type of relocation to do if one of the operands
8051 is an address expression. */
8054 mips_ip (char *str, struct mips_cl_insn *ip)
8059 struct mips_opcode *insn;
8062 unsigned int lastregno = 0;
8063 unsigned int lastpos = 0;
8064 unsigned int limlo, limhi;
8070 /* If the instruction contains a '.', we first try to match an instruction
8071 including the '.'. Then we try again without the '.'. */
8073 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8076 /* If we stopped on whitespace, then replace the whitespace with null for
8077 the call to hash_find. Save the character we replaced just in case we
8078 have to re-parse the instruction. */
8085 insn = (struct mips_opcode *) hash_find (op_hash, str);
8087 /* If we didn't find the instruction in the opcode table, try again, but
8088 this time with just the instruction up to, but not including the
8092 /* Restore the character we overwrite above (if any). */
8096 /* Scan up to the first '.' or whitespace. */
8098 *s != '\0' && *s != '.' && !ISSPACE (*s);
8102 /* If we did not find a '.', then we can quit now. */
8105 insn_error = "unrecognized opcode";
8109 /* Lookup the instruction in the hash table. */
8111 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8113 insn_error = "unrecognized opcode";
8123 assert (strcmp (insn->name, str) == 0);
8125 if (OPCODE_IS_MEMBER (insn,
8127 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8128 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8129 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8135 if (insn->pinfo != INSN_MACRO)
8137 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8143 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8144 && strcmp (insn->name, insn[1].name) == 0)
8153 static char buf[100];
8155 _("opcode not supported on this processor: %s (%s)"),
8156 mips_cpu_info_from_arch (mips_opts.arch)->name,
8157 mips_cpu_info_from_isa (mips_opts.isa)->name);
8167 ip->insn_opcode = insn->match;
8169 for (args = insn->args;; ++args)
8173 s += strspn (s, " \t");
8177 case '\0': /* end of args */
8190 ip->insn_opcode |= lastregno << OP_SH_RS;
8194 ip->insn_opcode |= lastregno << OP_SH_RT;
8198 ip->insn_opcode |= lastregno << OP_SH_FT;
8202 ip->insn_opcode |= lastregno << OP_SH_FS;
8208 /* Handle optional base register.
8209 Either the base register is omitted or
8210 we must have a left paren. */
8211 /* This is dependent on the next operand specifier
8212 is a base register specification. */
8213 assert (args[1] == 'b' || args[1] == '5'
8214 || args[1] == '-' || args[1] == '4');
8218 case ')': /* these must match exactly */
8225 case '+': /* Opcode extension character. */
8228 case 'A': /* ins/ext position, becomes LSB. */
8237 my_getExpression (&imm_expr, s);
8238 check_absolute_expr (ip, &imm_expr);
8239 if ((unsigned long) imm_expr.X_add_number < limlo
8240 || (unsigned long) imm_expr.X_add_number > limhi)
8242 as_bad (_("Improper position (%lu)"),
8243 (unsigned long) imm_expr.X_add_number);
8244 imm_expr.X_add_number = limlo;
8246 lastpos = imm_expr.X_add_number;
8247 ip->insn_opcode |= (imm_expr.X_add_number
8248 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8249 imm_expr.X_op = O_absent;
8253 case 'B': /* ins size, becomes MSB. */
8262 my_getExpression (&imm_expr, s);
8263 check_absolute_expr (ip, &imm_expr);
8264 /* Check for negative input so that small negative numbers
8265 will not succeed incorrectly. The checks against
8266 (pos+size) transitively check "size" itself,
8267 assuming that "pos" is reasonable. */
8268 if ((long) imm_expr.X_add_number < 0
8269 || ((unsigned long) imm_expr.X_add_number
8271 || ((unsigned long) imm_expr.X_add_number
8274 as_bad (_("Improper insert size (%lu, position %lu)"),
8275 (unsigned long) imm_expr.X_add_number,
8276 (unsigned long) lastpos);
8277 imm_expr.X_add_number = limlo - lastpos;
8279 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8280 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8281 imm_expr.X_op = O_absent;
8285 case 'C': /* ext size, becomes MSBD. */
8298 my_getExpression (&imm_expr, s);
8299 check_absolute_expr (ip, &imm_expr);
8300 /* Check for negative input so that small negative numbers
8301 will not succeed incorrectly. The checks against
8302 (pos+size) transitively check "size" itself,
8303 assuming that "pos" is reasonable. */
8304 if ((long) imm_expr.X_add_number < 0
8305 || ((unsigned long) imm_expr.X_add_number
8307 || ((unsigned long) imm_expr.X_add_number
8310 as_bad (_("Improper extract size (%lu, position %lu)"),
8311 (unsigned long) imm_expr.X_add_number,
8312 (unsigned long) lastpos);
8313 imm_expr.X_add_number = limlo - lastpos;
8315 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8316 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8317 imm_expr.X_op = O_absent;
8322 /* +D is for disassembly only; never match. */
8326 /* "+I" is like "I", except that imm2_expr is used. */
8327 my_getExpression (&imm2_expr, s);
8328 if (imm2_expr.X_op != O_big
8329 && imm2_expr.X_op != O_constant)
8330 insn_error = _("absolute expression required");
8331 normalize_constant_expr (&imm2_expr);
8336 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8337 *args, insn->name, insn->args);
8338 /* Further processing is fruitless. */
8343 case '<': /* must be at least one digit */
8345 * According to the manual, if the shift amount is greater
8346 * than 31 or less than 0, then the shift amount should be
8347 * mod 32. In reality the mips assembler issues an error.
8348 * We issue a warning and mask out all but the low 5 bits.
8350 my_getExpression (&imm_expr, s);
8351 check_absolute_expr (ip, &imm_expr);
8352 if ((unsigned long) imm_expr.X_add_number > 31)
8354 as_warn (_("Improper shift amount (%lu)"),
8355 (unsigned long) imm_expr.X_add_number);
8356 imm_expr.X_add_number &= OP_MASK_SHAMT;
8358 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8359 imm_expr.X_op = O_absent;
8363 case '>': /* shift amount minus 32 */
8364 my_getExpression (&imm_expr, s);
8365 check_absolute_expr (ip, &imm_expr);
8366 if ((unsigned long) imm_expr.X_add_number < 32
8367 || (unsigned long) imm_expr.X_add_number > 63)
8369 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8370 imm_expr.X_op = O_absent;
8374 case 'k': /* cache code */
8375 case 'h': /* prefx code */
8376 my_getExpression (&imm_expr, s);
8377 check_absolute_expr (ip, &imm_expr);
8378 if ((unsigned long) imm_expr.X_add_number > 31)
8380 as_warn (_("Invalid value for `%s' (%lu)"),
8382 (unsigned long) imm_expr.X_add_number);
8383 imm_expr.X_add_number &= 0x1f;
8386 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8388 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8389 imm_expr.X_op = O_absent;
8393 case 'c': /* break code */
8394 my_getExpression (&imm_expr, s);
8395 check_absolute_expr (ip, &imm_expr);
8396 if ((unsigned long) imm_expr.X_add_number > 1023)
8398 as_warn (_("Illegal break code (%lu)"),
8399 (unsigned long) imm_expr.X_add_number);
8400 imm_expr.X_add_number &= OP_MASK_CODE;
8402 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8403 imm_expr.X_op = O_absent;
8407 case 'q': /* lower break code */
8408 my_getExpression (&imm_expr, s);
8409 check_absolute_expr (ip, &imm_expr);
8410 if ((unsigned long) imm_expr.X_add_number > 1023)
8412 as_warn (_("Illegal lower break code (%lu)"),
8413 (unsigned long) imm_expr.X_add_number);
8414 imm_expr.X_add_number &= OP_MASK_CODE2;
8416 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8417 imm_expr.X_op = O_absent;
8421 case 'B': /* 20-bit syscall/break code. */
8422 my_getExpression (&imm_expr, s);
8423 check_absolute_expr (ip, &imm_expr);
8424 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8425 as_warn (_("Illegal 20-bit code (%lu)"),
8426 (unsigned long) imm_expr.X_add_number);
8427 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8428 imm_expr.X_op = O_absent;
8432 case 'C': /* Coprocessor code */
8433 my_getExpression (&imm_expr, s);
8434 check_absolute_expr (ip, &imm_expr);
8435 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8437 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8438 (unsigned long) imm_expr.X_add_number);
8439 imm_expr.X_add_number &= ((1 << 25) - 1);
8441 ip->insn_opcode |= imm_expr.X_add_number;
8442 imm_expr.X_op = O_absent;
8446 case 'J': /* 19-bit wait code. */
8447 my_getExpression (&imm_expr, s);
8448 check_absolute_expr (ip, &imm_expr);
8449 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8450 as_warn (_("Illegal 19-bit code (%lu)"),
8451 (unsigned long) imm_expr.X_add_number);
8452 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8453 imm_expr.X_op = O_absent;
8457 case 'P': /* Performance register */
8458 my_getExpression (&imm_expr, s);
8459 check_absolute_expr (ip, &imm_expr);
8460 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8462 as_warn (_("Invalid performance register (%lu)"),
8463 (unsigned long) imm_expr.X_add_number);
8464 imm_expr.X_add_number &= OP_MASK_PERFREG;
8466 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8467 imm_expr.X_op = O_absent;
8471 case 'b': /* base register */
8472 case 'd': /* destination register */
8473 case 's': /* source register */
8474 case 't': /* target register */
8475 case 'r': /* both target and source */
8476 case 'v': /* both dest and source */
8477 case 'w': /* both dest and target */
8478 case 'E': /* coprocessor target register */
8479 case 'G': /* coprocessor destination register */
8480 case 'K': /* 'rdhwr' destination register */
8481 case 'x': /* ignore register name */
8482 case 'z': /* must be zero register */
8483 case 'U': /* destination register (clo/clz). */
8498 while (ISDIGIT (*s));
8500 as_bad (_("Invalid register number (%d)"), regno);
8502 else if (*args == 'E' || *args == 'G' || *args == 'K')
8506 if (s[1] == 'r' && s[2] == 'a')
8511 else if (s[1] == 'f' && s[2] == 'p')
8516 else if (s[1] == 's' && s[2] == 'p')
8521 else if (s[1] == 'g' && s[2] == 'p')
8526 else if (s[1] == 'a' && s[2] == 't')
8531 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8536 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8541 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8546 else if (itbl_have_entries)
8551 p = s + 1; /* advance past '$' */
8552 n = itbl_get_field (&p); /* n is name */
8554 /* See if this is a register defined in an
8556 if (itbl_get_reg_val (n, &r))
8558 /* Get_field advances to the start of
8559 the next field, so we need to back
8560 rack to the end of the last field. */
8564 s = strchr (s, '\0');
8578 as_warn (_("Used $at without \".set noat\""));
8584 if (c == 'r' || c == 'v' || c == 'w')
8591 /* 'z' only matches $0. */
8592 if (c == 'z' && regno != 0)
8595 /* Now that we have assembled one operand, we use the args string
8596 * to figure out where it goes in the instruction. */
8603 ip->insn_opcode |= regno << OP_SH_RS;
8608 ip->insn_opcode |= regno << OP_SH_RD;
8611 ip->insn_opcode |= regno << OP_SH_RD;
8612 ip->insn_opcode |= regno << OP_SH_RT;
8617 ip->insn_opcode |= regno << OP_SH_RT;
8620 /* This case exists because on the r3000 trunc
8621 expands into a macro which requires a gp
8622 register. On the r6000 or r4000 it is
8623 assembled into a single instruction which
8624 ignores the register. Thus the insn version
8625 is MIPS_ISA2 and uses 'x', and the macro
8626 version is MIPS_ISA1 and uses 't'. */
8629 /* This case is for the div instruction, which
8630 acts differently if the destination argument
8631 is $0. This only matches $0, and is checked
8632 outside the switch. */
8635 /* Itbl operand; not yet implemented. FIXME ?? */
8637 /* What about all other operands like 'i', which
8638 can be specified in the opcode table? */
8648 ip->insn_opcode |= lastregno << OP_SH_RS;
8651 ip->insn_opcode |= lastregno << OP_SH_RT;
8656 case 'O': /* MDMX alignment immediate constant. */
8657 my_getExpression (&imm_expr, s);
8658 check_absolute_expr (ip, &imm_expr);
8659 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8661 as_warn ("Improper align amount (%ld), using low bits",
8662 (long) imm_expr.X_add_number);
8663 imm_expr.X_add_number &= OP_MASK_ALN;
8665 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8666 imm_expr.X_op = O_absent;
8670 case 'Q': /* MDMX vector, element sel, or const. */
8673 /* MDMX Immediate. */
8674 my_getExpression (&imm_expr, s);
8675 check_absolute_expr (ip, &imm_expr);
8676 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8678 as_warn (_("Invalid MDMX Immediate (%ld)"),
8679 (long) imm_expr.X_add_number);
8680 imm_expr.X_add_number &= OP_MASK_FT;
8682 imm_expr.X_add_number &= OP_MASK_FT;
8683 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8684 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8686 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8687 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8688 imm_expr.X_op = O_absent;
8692 /* Not MDMX Immediate. Fall through. */
8693 case 'X': /* MDMX destination register. */
8694 case 'Y': /* MDMX source register. */
8695 case 'Z': /* MDMX target register. */
8697 case 'D': /* floating point destination register */
8698 case 'S': /* floating point source register */
8699 case 'T': /* floating point target register */
8700 case 'R': /* floating point source register */
8704 /* Accept $fN for FP and MDMX register numbers, and in
8705 addition accept $vN for MDMX register numbers. */
8706 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8707 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8718 while (ISDIGIT (*s));
8721 as_bad (_("Invalid float register number (%d)"), regno);
8723 if ((regno & 1) != 0
8725 && ! (strcmp (str, "mtc1") == 0
8726 || strcmp (str, "mfc1") == 0
8727 || strcmp (str, "lwc1") == 0
8728 || strcmp (str, "swc1") == 0
8729 || strcmp (str, "l.s") == 0
8730 || strcmp (str, "s.s") == 0))
8731 as_warn (_("Float register should be even, was %d"),
8739 if (c == 'V' || c == 'W')
8750 ip->insn_opcode |= regno << OP_SH_FD;
8755 ip->insn_opcode |= regno << OP_SH_FS;
8758 /* This is like 'Z', but also needs to fix the MDMX
8759 vector/scalar select bits. Note that the
8760 scalar immediate case is handled above. */
8763 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8764 int max_el = (is_qh ? 3 : 7);
8766 my_getExpression(&imm_expr, s);
8767 check_absolute_expr (ip, &imm_expr);
8769 if (imm_expr.X_add_number > max_el)
8770 as_bad(_("Bad element selector %ld"),
8771 (long) imm_expr.X_add_number);
8772 imm_expr.X_add_number &= max_el;
8773 ip->insn_opcode |= (imm_expr.X_add_number
8777 as_warn(_("Expecting ']' found '%s'"), s);
8783 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8784 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8787 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8794 ip->insn_opcode |= regno << OP_SH_FT;
8797 ip->insn_opcode |= regno << OP_SH_FR;
8807 ip->insn_opcode |= lastregno << OP_SH_FS;
8810 ip->insn_opcode |= lastregno << OP_SH_FT;
8816 my_getExpression (&imm_expr, s);
8817 if (imm_expr.X_op != O_big
8818 && imm_expr.X_op != O_constant)
8819 insn_error = _("absolute expression required");
8820 normalize_constant_expr (&imm_expr);
8825 my_getExpression (&offset_expr, s);
8826 *imm_reloc = BFD_RELOC_32;
8839 unsigned char temp[8];
8841 unsigned int length;
8846 /* These only appear as the last operand in an
8847 instruction, and every instruction that accepts
8848 them in any variant accepts them in all variants.
8849 This means we don't have to worry about backing out
8850 any changes if the instruction does not match.
8852 The difference between them is the size of the
8853 floating point constant and where it goes. For 'F'
8854 and 'L' the constant is 64 bits; for 'f' and 'l' it
8855 is 32 bits. Where the constant is placed is based
8856 on how the MIPS assembler does things:
8859 f -- immediate value
8862 The .lit4 and .lit8 sections are only used if
8863 permitted by the -G argument.
8865 When generating embedded PIC code, we use the
8866 .lit8 section but not the .lit4 section (we can do
8867 .lit4 inline easily; we need to put .lit8
8868 somewhere in the data segment, and using .lit8
8869 permits the linker to eventually combine identical
8872 The code below needs to know whether the target register
8873 is 32 or 64 bits wide. It relies on the fact 'f' and
8874 'F' are used with GPR-based instructions and 'l' and
8875 'L' are used with FPR-based instructions. */
8877 f64 = *args == 'F' || *args == 'L';
8878 using_gprs = *args == 'F' || *args == 'f';
8880 save_in = input_line_pointer;
8881 input_line_pointer = s;
8882 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8884 s = input_line_pointer;
8885 input_line_pointer = save_in;
8886 if (err != NULL && *err != '\0')
8888 as_bad (_("Bad floating point constant: %s"), err);
8889 memset (temp, '\0', sizeof temp);
8890 length = f64 ? 8 : 4;
8893 assert (length == (unsigned) (f64 ? 8 : 4));
8897 && (! USE_GLOBAL_POINTER_OPT
8898 || mips_pic == EMBEDDED_PIC
8899 || g_switch_value < 4
8900 || (temp[0] == 0 && temp[1] == 0)
8901 || (temp[2] == 0 && temp[3] == 0))))
8903 imm_expr.X_op = O_constant;
8904 if (! target_big_endian)
8905 imm_expr.X_add_number = bfd_getl32 (temp);
8907 imm_expr.X_add_number = bfd_getb32 (temp);
8910 && ! mips_disable_float_construction
8911 /* Constants can only be constructed in GPRs and
8912 copied to FPRs if the GPRs are at least as wide
8913 as the FPRs. Force the constant into memory if
8914 we are using 64-bit FPRs but the GPRs are only
8917 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8918 && ((temp[0] == 0 && temp[1] == 0)
8919 || (temp[2] == 0 && temp[3] == 0))
8920 && ((temp[4] == 0 && temp[5] == 0)
8921 || (temp[6] == 0 && temp[7] == 0)))
8923 /* The value is simple enough to load with a couple of
8924 instructions. If using 32-bit registers, set
8925 imm_expr to the high order 32 bits and offset_expr to
8926 the low order 32 bits. Otherwise, set imm_expr to
8927 the entire 64 bit constant. */
8928 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8930 imm_expr.X_op = O_constant;
8931 offset_expr.X_op = O_constant;
8932 if (! target_big_endian)
8934 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8935 offset_expr.X_add_number = bfd_getl32 (temp);
8939 imm_expr.X_add_number = bfd_getb32 (temp);
8940 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8942 if (offset_expr.X_add_number == 0)
8943 offset_expr.X_op = O_absent;
8945 else if (sizeof (imm_expr.X_add_number) > 4)
8947 imm_expr.X_op = O_constant;
8948 if (! target_big_endian)
8949 imm_expr.X_add_number = bfd_getl64 (temp);
8951 imm_expr.X_add_number = bfd_getb64 (temp);
8955 imm_expr.X_op = O_big;
8956 imm_expr.X_add_number = 4;
8957 if (! target_big_endian)
8959 generic_bignum[0] = bfd_getl16 (temp);
8960 generic_bignum[1] = bfd_getl16 (temp + 2);
8961 generic_bignum[2] = bfd_getl16 (temp + 4);
8962 generic_bignum[3] = bfd_getl16 (temp + 6);
8966 generic_bignum[0] = bfd_getb16 (temp + 6);
8967 generic_bignum[1] = bfd_getb16 (temp + 4);
8968 generic_bignum[2] = bfd_getb16 (temp + 2);
8969 generic_bignum[3] = bfd_getb16 (temp);
8975 const char *newname;
8978 /* Switch to the right section. */
8980 subseg = now_subseg;
8983 default: /* unused default case avoids warnings. */
8985 newname = RDATA_SECTION_NAME;
8986 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8987 || mips_pic == EMBEDDED_PIC)
8991 if (mips_pic == EMBEDDED_PIC)
8994 newname = RDATA_SECTION_NAME;
8997 assert (!USE_GLOBAL_POINTER_OPT
8998 || g_switch_value >= 4);
9002 new_seg = subseg_new (newname, (subsegT) 0);
9003 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9004 bfd_set_section_flags (stdoutput, new_seg,
9009 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9010 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9011 && strcmp (TARGET_OS, "elf") != 0)
9012 record_alignment (new_seg, 4);
9014 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9016 as_bad (_("Can't use floating point insn in this section"));
9018 /* Set the argument to the current address in the
9020 offset_expr.X_op = O_symbol;
9021 offset_expr.X_add_symbol =
9022 symbol_new ("L0\001", now_seg,
9023 (valueT) frag_now_fix (), frag_now);
9024 offset_expr.X_add_number = 0;
9026 /* Put the floating point number into the section. */
9027 p = frag_more ((int) length);
9028 memcpy (p, temp, length);
9030 /* Switch back to the original section. */
9031 subseg_set (seg, subseg);
9036 case 'i': /* 16 bit unsigned immediate */
9037 case 'j': /* 16 bit signed immediate */
9038 *imm_reloc = BFD_RELOC_LO16;
9039 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9042 offsetT minval, maxval;
9044 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9045 && strcmp (insn->name, insn[1].name) == 0);
9047 /* If the expression was written as an unsigned number,
9048 only treat it as signed if there are no more
9052 && sizeof (imm_expr.X_add_number) <= 4
9053 && imm_expr.X_op == O_constant
9054 && imm_expr.X_add_number < 0
9055 && imm_expr.X_unsigned
9059 /* For compatibility with older assemblers, we accept
9060 0x8000-0xffff as signed 16-bit numbers when only
9061 signed numbers are allowed. */
9063 minval = 0, maxval = 0xffff;
9065 minval = -0x8000, maxval = 0x7fff;
9067 minval = -0x8000, maxval = 0xffff;
9069 if (imm_expr.X_op != O_constant
9070 || imm_expr.X_add_number < minval
9071 || imm_expr.X_add_number > maxval)
9075 if (imm_expr.X_op == O_constant
9076 || imm_expr.X_op == O_big)
9077 as_bad (_("expression out of range"));
9083 case 'o': /* 16 bit offset */
9084 /* Check whether there is only a single bracketed expression
9085 left. If so, it must be the base register and the
9086 constant must be zero. */
9087 if (*s == '(' && strchr (s + 1, '(') == 0)
9089 offset_expr.X_op = O_constant;
9090 offset_expr.X_add_number = 0;
9094 /* If this value won't fit into a 16 bit offset, then go
9095 find a macro that will generate the 32 bit offset
9097 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9098 && (offset_expr.X_op != O_constant
9099 || offset_expr.X_add_number >= 0x8000
9100 || offset_expr.X_add_number < -0x8000))
9106 case 'p': /* pc relative offset */
9107 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9108 my_getExpression (&offset_expr, s);
9112 case 'u': /* upper 16 bits */
9113 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9114 && imm_expr.X_op == O_constant
9115 && (imm_expr.X_add_number < 0
9116 || imm_expr.X_add_number >= 0x10000))
9117 as_bad (_("lui expression not in range 0..65535"));
9121 case 'a': /* 26 bit address */
9122 my_getExpression (&offset_expr, s);
9124 *offset_reloc = BFD_RELOC_MIPS_JMP;
9127 case 'N': /* 3 bit branch condition code */
9128 case 'M': /* 3 bit compare condition code */
9129 if (strncmp (s, "$fcc", 4) != 0)
9139 while (ISDIGIT (*s));
9141 as_bad (_("Invalid condition code register $fcc%d"), regno);
9142 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9143 || strcmp(str + strlen(str) - 5, "any2f") == 0
9144 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9145 && (regno & 1) != 0)
9146 as_warn(_("Condition code register should be even for %s, was %d"),
9148 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9149 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9150 && (regno & 3) != 0)
9151 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9154 ip->insn_opcode |= regno << OP_SH_BCC;
9156 ip->insn_opcode |= regno << OP_SH_CCC;
9160 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9171 while (ISDIGIT (*s));
9174 c = 8; /* Invalid sel value. */
9177 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9178 ip->insn_opcode |= c;
9182 /* Must be at least one digit. */
9183 my_getExpression (&imm_expr, s);
9184 check_absolute_expr (ip, &imm_expr);
9186 if ((unsigned long) imm_expr.X_add_number
9187 > (unsigned long) OP_MASK_VECBYTE)
9189 as_bad (_("bad byte vector index (%ld)"),
9190 (long) imm_expr.X_add_number);
9191 imm_expr.X_add_number = 0;
9194 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9195 imm_expr.X_op = O_absent;
9200 my_getExpression (&imm_expr, s);
9201 check_absolute_expr (ip, &imm_expr);
9203 if ((unsigned long) imm_expr.X_add_number
9204 > (unsigned long) OP_MASK_VECALIGN)
9206 as_bad (_("bad byte vector index (%ld)"),
9207 (long) imm_expr.X_add_number);
9208 imm_expr.X_add_number = 0;
9211 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9212 imm_expr.X_op = O_absent;
9217 as_bad (_("bad char = '%c'\n"), *args);
9222 /* Args don't match. */
9223 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9224 !strcmp (insn->name, insn[1].name))
9228 insn_error = _("illegal operands");
9233 insn_error = _("illegal operands");
9238 /* This routine assembles an instruction into its binary format when
9239 assembling for the mips16. As a side effect, it sets one of the
9240 global variables imm_reloc or offset_reloc to the type of
9241 relocation to do if one of the operands is an address expression.
9242 It also sets mips16_small and mips16_ext if the user explicitly
9243 requested a small or extended instruction. */
9246 mips16_ip (char *str, struct mips_cl_insn *ip)
9250 struct mips_opcode *insn;
9253 unsigned int lastregno = 0;
9258 mips16_small = FALSE;
9261 for (s = str; ISLOWER (*s); ++s)
9273 if (s[1] == 't' && s[2] == ' ')
9276 mips16_small = TRUE;
9280 else if (s[1] == 'e' && s[2] == ' ')
9289 insn_error = _("unknown opcode");
9293 if (mips_opts.noautoextend && ! mips16_ext)
9294 mips16_small = TRUE;
9296 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9298 insn_error = _("unrecognized opcode");
9305 assert (strcmp (insn->name, str) == 0);
9308 ip->insn_opcode = insn->match;
9309 ip->use_extend = FALSE;
9310 imm_expr.X_op = O_absent;
9311 imm_reloc[0] = BFD_RELOC_UNUSED;
9312 imm_reloc[1] = BFD_RELOC_UNUSED;
9313 imm_reloc[2] = BFD_RELOC_UNUSED;
9314 imm2_expr.X_op = O_absent;
9315 offset_expr.X_op = O_absent;
9316 offset_reloc[0] = BFD_RELOC_UNUSED;
9317 offset_reloc[1] = BFD_RELOC_UNUSED;
9318 offset_reloc[2] = BFD_RELOC_UNUSED;
9319 for (args = insn->args; 1; ++args)
9326 /* In this switch statement we call break if we did not find
9327 a match, continue if we did find a match, or return if we
9336 /* Stuff the immediate value in now, if we can. */
9337 if (imm_expr.X_op == O_constant
9338 && *imm_reloc > BFD_RELOC_UNUSED
9339 && insn->pinfo != INSN_MACRO)
9341 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9342 imm_expr.X_add_number, TRUE, mips16_small,
9343 mips16_ext, &ip->insn_opcode,
9344 &ip->use_extend, &ip->extend);
9345 imm_expr.X_op = O_absent;
9346 *imm_reloc = BFD_RELOC_UNUSED;
9360 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9363 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9379 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9381 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9408 while (ISDIGIT (*s));
9411 as_bad (_("invalid register number (%d)"), regno);
9417 if (s[1] == 'r' && s[2] == 'a')
9422 else if (s[1] == 'f' && s[2] == 'p')
9427 else if (s[1] == 's' && s[2] == 'p')
9432 else if (s[1] == 'g' && s[2] == 'p')
9437 else if (s[1] == 'a' && s[2] == 't')
9442 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9447 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9452 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9465 if (c == 'v' || c == 'w')
9467 regno = mips16_to_32_reg_map[lastregno];
9481 regno = mips32_to_16_reg_map[regno];
9486 regno = ILLEGAL_REG;
9491 regno = ILLEGAL_REG;
9496 regno = ILLEGAL_REG;
9501 if (regno == AT && ! mips_opts.noat)
9502 as_warn (_("used $at without \".set noat\""));
9509 if (regno == ILLEGAL_REG)
9516 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9520 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9523 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9526 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9532 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9535 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9536 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9546 if (strncmp (s, "$pc", 3) == 0)
9570 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9572 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9573 and generate the appropriate reloc. If the text
9574 inside %gprel is not a symbol name with an
9575 optional offset, then we generate a normal reloc
9576 and will probably fail later. */
9577 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9578 if (imm_expr.X_op == O_symbol)
9581 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9583 ip->use_extend = TRUE;
9590 /* Just pick up a normal expression. */
9591 my_getExpression (&imm_expr, s);
9594 if (imm_expr.X_op == O_register)
9596 /* What we thought was an expression turned out to
9599 if (s[0] == '(' && args[1] == '(')
9601 /* It looks like the expression was omitted
9602 before a register indirection, which means
9603 that the expression is implicitly zero. We
9604 still set up imm_expr, so that we handle
9605 explicit extensions correctly. */
9606 imm_expr.X_op = O_constant;
9607 imm_expr.X_add_number = 0;
9608 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9615 /* We need to relax this instruction. */
9616 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9625 /* We use offset_reloc rather than imm_reloc for the PC
9626 relative operands. This lets macros with both
9627 immediate and address operands work correctly. */
9628 my_getExpression (&offset_expr, s);
9630 if (offset_expr.X_op == O_register)
9633 /* We need to relax this instruction. */
9634 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9638 case '6': /* break code */
9639 my_getExpression (&imm_expr, s);
9640 check_absolute_expr (ip, &imm_expr);
9641 if ((unsigned long) imm_expr.X_add_number > 63)
9643 as_warn (_("Invalid value for `%s' (%lu)"),
9645 (unsigned long) imm_expr.X_add_number);
9646 imm_expr.X_add_number &= 0x3f;
9648 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9649 imm_expr.X_op = O_absent;
9653 case 'a': /* 26 bit address */
9654 my_getExpression (&offset_expr, s);
9656 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9657 ip->insn_opcode <<= 16;
9660 case 'l': /* register list for entry macro */
9661 case 'L': /* register list for exit macro */
9671 int freg, reg1, reg2;
9673 while (*s == ' ' || *s == ',')
9677 as_bad (_("can't parse register list"));
9689 while (ISDIGIT (*s))
9711 as_bad (_("invalid register list"));
9716 while (ISDIGIT (*s))
9723 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9728 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9733 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9734 mask |= (reg2 - 3) << 3;
9735 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9736 mask |= (reg2 - 15) << 1;
9737 else if (reg1 == RA && reg2 == RA)
9741 as_bad (_("invalid register list"));
9745 /* The mask is filled in in the opcode table for the
9746 benefit of the disassembler. We remove it before
9747 applying the actual mask. */
9748 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9749 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9753 case 'e': /* extend code */
9754 my_getExpression (&imm_expr, s);
9755 check_absolute_expr (ip, &imm_expr);
9756 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9758 as_warn (_("Invalid value for `%s' (%lu)"),
9760 (unsigned long) imm_expr.X_add_number);
9761 imm_expr.X_add_number &= 0x7ff;
9763 ip->insn_opcode |= imm_expr.X_add_number;
9764 imm_expr.X_op = O_absent;
9774 /* Args don't match. */
9775 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9776 strcmp (insn->name, insn[1].name) == 0)
9783 insn_error = _("illegal operands");
9789 /* This structure holds information we know about a mips16 immediate
9792 struct mips16_immed_operand
9794 /* The type code used in the argument string in the opcode table. */
9796 /* The number of bits in the short form of the opcode. */
9798 /* The number of bits in the extended form of the opcode. */
9800 /* The amount by which the short form is shifted when it is used;
9801 for example, the sw instruction has a shift count of 2. */
9803 /* The amount by which the short form is shifted when it is stored
9804 into the instruction code. */
9806 /* Non-zero if the short form is unsigned. */
9808 /* Non-zero if the extended form is unsigned. */
9810 /* Non-zero if the value is PC relative. */
9814 /* The mips16 immediate operand types. */
9816 static const struct mips16_immed_operand mips16_immed_operands[] =
9818 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9819 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9820 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9821 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9822 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9823 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9824 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9825 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9826 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9827 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9828 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9829 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9830 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9831 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9832 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9833 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9834 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9835 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9836 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9837 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9838 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9841 #define MIPS16_NUM_IMMED \
9842 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9844 /* Handle a mips16 instruction with an immediate value. This or's the
9845 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9846 whether an extended value is needed; if one is needed, it sets
9847 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9848 If SMALL is true, an unextended opcode was explicitly requested.
9849 If EXT is true, an extended opcode was explicitly requested. If
9850 WARN is true, warn if EXT does not match reality. */
9853 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9854 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9855 unsigned long *insn, bfd_boolean *use_extend,
9856 unsigned short *extend)
9858 register const struct mips16_immed_operand *op;
9859 int mintiny, maxtiny;
9860 bfd_boolean needext;
9862 op = mips16_immed_operands;
9863 while (op->type != type)
9866 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9871 if (type == '<' || type == '>' || type == '[' || type == ']')
9874 maxtiny = 1 << op->nbits;
9879 maxtiny = (1 << op->nbits) - 1;
9884 mintiny = - (1 << (op->nbits - 1));
9885 maxtiny = (1 << (op->nbits - 1)) - 1;
9888 /* Branch offsets have an implicit 0 in the lowest bit. */
9889 if (type == 'p' || type == 'q')
9892 if ((val & ((1 << op->shift) - 1)) != 0
9893 || val < (mintiny << op->shift)
9894 || val > (maxtiny << op->shift))
9899 if (warn && ext && ! needext)
9900 as_warn_where (file, line,
9901 _("extended operand requested but not required"));
9902 if (small && needext)
9903 as_bad_where (file, line, _("invalid unextended operand value"));
9905 if (small || (! ext && ! needext))
9909 *use_extend = FALSE;
9910 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9911 insnval <<= op->op_shift;
9916 long minext, maxext;
9922 maxext = (1 << op->extbits) - 1;
9926 minext = - (1 << (op->extbits - 1));
9927 maxext = (1 << (op->extbits - 1)) - 1;
9929 if (val < minext || val > maxext)
9930 as_bad_where (file, line,
9931 _("operand value out of range for instruction"));
9934 if (op->extbits == 16)
9936 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9939 else if (op->extbits == 15)
9941 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9946 extval = ((val & 0x1f) << 6) | (val & 0x20);
9950 *extend = (unsigned short) extval;
9955 static const struct percent_op_match
9958 bfd_reloc_code_real_type reloc;
9961 {"%lo", BFD_RELOC_LO16},
9963 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9964 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9965 {"%call16", BFD_RELOC_MIPS_CALL16},
9966 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9967 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9968 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9969 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9970 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9971 {"%got", BFD_RELOC_MIPS_GOT16},
9972 {"%gp_rel", BFD_RELOC_GPREL16},
9973 {"%half", BFD_RELOC_16},
9974 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9975 {"%higher", BFD_RELOC_MIPS_HIGHER},
9976 {"%neg", BFD_RELOC_MIPS_SUB},
9978 {"%hi", BFD_RELOC_HI16_S}
9982 /* Return true if *STR points to a relocation operator. When returning true,
9983 move *STR over the operator and store its relocation code in *RELOC.
9984 Leave both *STR and *RELOC alone when returning false. */
9987 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9991 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9992 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9994 *str += strlen (percent_op[i].str);
9995 *reloc = percent_op[i].reloc;
9997 /* Check whether the output BFD supports this relocation.
9998 If not, issue an error and fall back on something safe. */
9999 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10001 as_bad ("relocation %s isn't supported by the current ABI",
10002 percent_op[i].str);
10003 *reloc = BFD_RELOC_LO16;
10011 /* Parse string STR as a 16-bit relocatable operand. Store the
10012 expression in *EP and the relocations in the array starting
10013 at RELOC. Return the number of relocation operators used.
10015 On exit, EXPR_END points to the first character after the expression.
10016 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10019 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10022 bfd_reloc_code_real_type reversed_reloc[3];
10023 size_t reloc_index, i;
10024 int crux_depth, str_depth;
10027 /* Search for the start of the main expression, recoding relocations
10028 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10029 of the main expression and with CRUX_DEPTH containing the number
10030 of open brackets at that point. */
10037 crux_depth = str_depth;
10039 /* Skip over whitespace and brackets, keeping count of the number
10041 while (*str == ' ' || *str == '\t' || *str == '(')
10046 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10047 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10049 my_getExpression (ep, crux);
10052 /* Match every open bracket. */
10053 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10057 if (crux_depth > 0)
10058 as_bad ("unclosed '('");
10062 if (reloc_index == 0)
10063 reloc[0] = BFD_RELOC_LO16;
10066 prev_reloc_op_frag = frag_now;
10067 for (i = 0; i < reloc_index; i++)
10068 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10071 return reloc_index;
10075 my_getExpression (expressionS *ep, char *str)
10080 save_in = input_line_pointer;
10081 input_line_pointer = str;
10083 expr_end = input_line_pointer;
10084 input_line_pointer = save_in;
10086 /* If we are in mips16 mode, and this is an expression based on `.',
10087 then we bump the value of the symbol by 1 since that is how other
10088 text symbols are handled. We don't bother to handle complex
10089 expressions, just `.' plus or minus a constant. */
10090 if (mips_opts.mips16
10091 && ep->X_op == O_symbol
10092 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10093 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10094 && symbol_get_frag (ep->X_add_symbol) == frag_now
10095 && symbol_constant_p (ep->X_add_symbol)
10096 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10097 S_SET_VALUE (ep->X_add_symbol, val + 1);
10100 /* Turn a string in input_line_pointer into a floating point constant
10101 of type TYPE, and store the appropriate bytes in *LITP. The number
10102 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10103 returned, or NULL on OK. */
10106 md_atof (int type, char *litP, int *sizeP)
10109 LITTLENUM_TYPE words[4];
10125 return _("bad call to md_atof");
10128 t = atof_ieee (input_line_pointer, type, words);
10130 input_line_pointer = t;
10134 if (! target_big_endian)
10136 for (i = prec - 1; i >= 0; i--)
10138 md_number_to_chars (litP, words[i], 2);
10144 for (i = 0; i < prec; i++)
10146 md_number_to_chars (litP, words[i], 2);
10155 md_number_to_chars (char *buf, valueT val, int n)
10157 if (target_big_endian)
10158 number_to_chars_bigendian (buf, val, n);
10160 number_to_chars_littleendian (buf, val, n);
10164 static int support_64bit_objects(void)
10166 const char **list, **l;
10169 list = bfd_target_list ();
10170 for (l = list; *l != NULL; l++)
10172 /* This is traditional mips */
10173 if (strcmp (*l, "elf64-tradbigmips") == 0
10174 || strcmp (*l, "elf64-tradlittlemips") == 0)
10176 if (strcmp (*l, "elf64-bigmips") == 0
10177 || strcmp (*l, "elf64-littlemips") == 0)
10180 yes = (*l != NULL);
10184 #endif /* OBJ_ELF */
10186 const char *md_shortopts = "O::g::G:";
10188 struct option md_longopts[] =
10190 /* Options which specify architecture. */
10191 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10192 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10193 {"march", required_argument, NULL, OPTION_MARCH},
10194 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10195 {"mtune", required_argument, NULL, OPTION_MTUNE},
10196 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10197 {"mips0", no_argument, NULL, OPTION_MIPS1},
10198 {"mips1", no_argument, NULL, OPTION_MIPS1},
10199 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10200 {"mips2", no_argument, NULL, OPTION_MIPS2},
10201 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10202 {"mips3", no_argument, NULL, OPTION_MIPS3},
10203 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10204 {"mips4", no_argument, NULL, OPTION_MIPS4},
10205 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10206 {"mips5", no_argument, NULL, OPTION_MIPS5},
10207 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10208 {"mips32", no_argument, NULL, OPTION_MIPS32},
10209 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10210 {"mips64", no_argument, NULL, OPTION_MIPS64},
10211 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10212 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10213 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10214 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10216 /* Options which specify Application Specific Extensions (ASEs). */
10217 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10218 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10219 {"mips16", no_argument, NULL, OPTION_MIPS16},
10220 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10221 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10222 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10223 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10224 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10225 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10226 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10227 {"mdmx", no_argument, NULL, OPTION_MDMX},
10228 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10229 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10231 /* Old-style architecture options. Don't add more of these. */
10232 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10233 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10234 {"m4650", no_argument, NULL, OPTION_M4650},
10235 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10236 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10237 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10238 {"m4010", no_argument, NULL, OPTION_M4010},
10239 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10240 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10241 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10242 {"m4100", no_argument, NULL, OPTION_M4100},
10243 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10244 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10245 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10246 {"m3900", no_argument, NULL, OPTION_M3900},
10247 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10248 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10250 /* Options which enable bug fixes. */
10251 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10252 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10253 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10254 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10255 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10256 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10257 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10258 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10259 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10260 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10262 /* Miscellaneous options. */
10263 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10264 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10265 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10266 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10267 {"trap", no_argument, NULL, OPTION_TRAP},
10268 {"no-break", no_argument, NULL, OPTION_TRAP},
10269 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10270 {"break", no_argument, NULL, OPTION_BREAK},
10271 {"no-trap", no_argument, NULL, OPTION_BREAK},
10272 #define OPTION_EB (OPTION_MISC_BASE + 3)
10273 {"EB", no_argument, NULL, OPTION_EB},
10274 #define OPTION_EL (OPTION_MISC_BASE + 4)
10275 {"EL", no_argument, NULL, OPTION_EL},
10276 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10277 {"mfp32", no_argument, NULL, OPTION_FP32},
10278 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10279 {"mgp32", no_argument, NULL, OPTION_GP32},
10280 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10281 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10282 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10283 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10284 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10285 {"mfp64", no_argument, NULL, OPTION_FP64},
10286 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10287 {"mgp64", no_argument, NULL, OPTION_GP64},
10288 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10289 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10290 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10291 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10293 /* ELF-specific options. */
10295 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10296 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10297 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10298 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10299 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10300 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10301 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10302 {"xgot", no_argument, NULL, OPTION_XGOT},
10303 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10304 {"mabi", required_argument, NULL, OPTION_MABI},
10305 #define OPTION_32 (OPTION_ELF_BASE + 4)
10306 {"32", no_argument, NULL, OPTION_32},
10307 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10308 {"n32", no_argument, NULL, OPTION_N32},
10309 #define OPTION_64 (OPTION_ELF_BASE + 6)
10310 {"64", no_argument, NULL, OPTION_64},
10311 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10312 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10313 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10314 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10315 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10316 {"mpdr", no_argument, NULL, OPTION_PDR},
10317 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10318 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10319 #endif /* OBJ_ELF */
10321 {NULL, no_argument, NULL, 0}
10323 size_t md_longopts_size = sizeof (md_longopts);
10325 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10326 NEW_VALUE. Warn if another value was already specified. Note:
10327 we have to defer parsing the -march and -mtune arguments in order
10328 to handle 'from-abi' correctly, since the ABI might be specified
10329 in a later argument. */
10332 mips_set_option_string (const char **string_ptr, const char *new_value)
10334 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10335 as_warn (_("A different %s was already specified, is now %s"),
10336 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10339 *string_ptr = new_value;
10343 md_parse_option (int c, char *arg)
10347 case OPTION_CONSTRUCT_FLOATS:
10348 mips_disable_float_construction = 0;
10351 case OPTION_NO_CONSTRUCT_FLOATS:
10352 mips_disable_float_construction = 1;
10364 target_big_endian = 1;
10368 target_big_endian = 0;
10372 if (arg && arg[1] == '0')
10382 mips_debug = atoi (arg);
10383 /* When the MIPS assembler sees -g or -g2, it does not do
10384 optimizations which limit full symbolic debugging. We take
10385 that to be equivalent to -O0. */
10386 if (mips_debug == 2)
10391 file_mips_isa = ISA_MIPS1;
10395 file_mips_isa = ISA_MIPS2;
10399 file_mips_isa = ISA_MIPS3;
10403 file_mips_isa = ISA_MIPS4;
10407 file_mips_isa = ISA_MIPS5;
10410 case OPTION_MIPS32:
10411 file_mips_isa = ISA_MIPS32;
10414 case OPTION_MIPS32R2:
10415 file_mips_isa = ISA_MIPS32R2;
10418 case OPTION_MIPS64R2:
10419 file_mips_isa = ISA_MIPS64R2;
10422 case OPTION_MIPS64:
10423 file_mips_isa = ISA_MIPS64;
10427 mips_set_option_string (&mips_tune_string, arg);
10431 mips_set_option_string (&mips_arch_string, arg);
10435 mips_set_option_string (&mips_arch_string, "4650");
10436 mips_set_option_string (&mips_tune_string, "4650");
10439 case OPTION_NO_M4650:
10443 mips_set_option_string (&mips_arch_string, "4010");
10444 mips_set_option_string (&mips_tune_string, "4010");
10447 case OPTION_NO_M4010:
10451 mips_set_option_string (&mips_arch_string, "4100");
10452 mips_set_option_string (&mips_tune_string, "4100");
10455 case OPTION_NO_M4100:
10459 mips_set_option_string (&mips_arch_string, "3900");
10460 mips_set_option_string (&mips_tune_string, "3900");
10463 case OPTION_NO_M3900:
10467 mips_opts.ase_mdmx = 1;
10470 case OPTION_NO_MDMX:
10471 mips_opts.ase_mdmx = 0;
10474 case OPTION_MIPS16:
10475 mips_opts.mips16 = 1;
10476 mips_no_prev_insn (FALSE);
10479 case OPTION_NO_MIPS16:
10480 mips_opts.mips16 = 0;
10481 mips_no_prev_insn (FALSE);
10484 case OPTION_MIPS3D:
10485 mips_opts.ase_mips3d = 1;
10488 case OPTION_NO_MIPS3D:
10489 mips_opts.ase_mips3d = 0;
10492 case OPTION_MEMBEDDED_PIC:
10493 mips_pic = EMBEDDED_PIC;
10494 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10496 as_bad (_("-G may not be used with embedded PIC code"));
10499 g_switch_value = 0x7fffffff;
10502 case OPTION_FIX_VR4120:
10503 mips_fix_vr4120 = 1;
10506 case OPTION_NO_FIX_VR4120:
10507 mips_fix_vr4120 = 0;
10510 case OPTION_RELAX_BRANCH:
10511 mips_relax_branch = 1;
10514 case OPTION_NO_RELAX_BRANCH:
10515 mips_relax_branch = 0;
10519 /* When generating ELF code, we permit -KPIC and -call_shared to
10520 select SVR4_PIC, and -non_shared to select no PIC. This is
10521 intended to be compatible with Irix 5. */
10522 case OPTION_CALL_SHARED:
10523 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10525 as_bad (_("-call_shared is supported only for ELF format"));
10528 mips_pic = SVR4_PIC;
10529 mips_abicalls = TRUE;
10530 if (g_switch_seen && g_switch_value != 0)
10532 as_bad (_("-G may not be used with SVR4 PIC code"));
10535 g_switch_value = 0;
10538 case OPTION_NON_SHARED:
10539 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10541 as_bad (_("-non_shared is supported only for ELF format"));
10545 mips_abicalls = FALSE;
10548 /* The -xgot option tells the assembler to use 32 offsets when
10549 accessing the got in SVR4_PIC mode. It is for Irix
10554 #endif /* OBJ_ELF */
10557 if (! USE_GLOBAL_POINTER_OPT)
10559 as_bad (_("-G is not supported for this configuration"));
10562 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10564 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10568 g_switch_value = atoi (arg);
10573 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10576 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10578 as_bad (_("-32 is supported for ELF format only"));
10581 mips_abi = O32_ABI;
10585 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10587 as_bad (_("-n32 is supported for ELF format only"));
10590 mips_abi = N32_ABI;
10594 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10596 as_bad (_("-64 is supported for ELF format only"));
10599 mips_abi = N64_ABI;
10600 if (! support_64bit_objects())
10601 as_fatal (_("No compiled in support for 64 bit object file format"));
10603 #endif /* OBJ_ELF */
10606 file_mips_gp32 = 1;
10610 file_mips_gp32 = 0;
10614 file_mips_fp32 = 1;
10618 file_mips_fp32 = 0;
10623 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10625 as_bad (_("-mabi is supported for ELF format only"));
10628 if (strcmp (arg, "32") == 0)
10629 mips_abi = O32_ABI;
10630 else if (strcmp (arg, "o64") == 0)
10631 mips_abi = O64_ABI;
10632 else if (strcmp (arg, "n32") == 0)
10633 mips_abi = N32_ABI;
10634 else if (strcmp (arg, "64") == 0)
10636 mips_abi = N64_ABI;
10637 if (! support_64bit_objects())
10638 as_fatal (_("No compiled in support for 64 bit object file "
10641 else if (strcmp (arg, "eabi") == 0)
10642 mips_abi = EABI_ABI;
10645 as_fatal (_("invalid abi -mabi=%s"), arg);
10649 #endif /* OBJ_ELF */
10651 case OPTION_M7000_HILO_FIX:
10652 mips_7000_hilo_fix = TRUE;
10655 case OPTION_MNO_7000_HILO_FIX:
10656 mips_7000_hilo_fix = FALSE;
10660 case OPTION_MDEBUG:
10661 mips_flag_mdebug = TRUE;
10664 case OPTION_NO_MDEBUG:
10665 mips_flag_mdebug = FALSE;
10669 mips_flag_pdr = TRUE;
10672 case OPTION_NO_PDR:
10673 mips_flag_pdr = FALSE;
10675 #endif /* OBJ_ELF */
10684 /* Set up globals to generate code for the ISA or processor
10685 described by INFO. */
10688 mips_set_architecture (const struct mips_cpu_info *info)
10692 file_mips_arch = info->cpu;
10693 mips_opts.arch = info->cpu;
10694 mips_opts.isa = info->isa;
10699 /* Likewise for tuning. */
10702 mips_set_tune (const struct mips_cpu_info *info)
10705 mips_tune = info->cpu;
10710 mips_after_parse_args (void)
10712 const struct mips_cpu_info *arch_info = 0;
10713 const struct mips_cpu_info *tune_info = 0;
10715 /* GP relative stuff not working for PE */
10716 if (strncmp (TARGET_OS, "pe", 2) == 0
10717 && g_switch_value != 0)
10720 as_bad (_("-G not supported in this configuration."));
10721 g_switch_value = 0;
10724 if (mips_abi == NO_ABI)
10725 mips_abi = MIPS_DEFAULT_ABI;
10727 /* The following code determines the architecture and register size.
10728 Similar code was added to GCC 3.3 (see override_options() in
10729 config/mips/mips.c). The GAS and GCC code should be kept in sync
10730 as much as possible. */
10732 if (mips_arch_string != 0)
10733 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10735 if (file_mips_isa != ISA_UNKNOWN)
10737 /* Handle -mipsN. At this point, file_mips_isa contains the
10738 ISA level specified by -mipsN, while arch_info->isa contains
10739 the -march selection (if any). */
10740 if (arch_info != 0)
10742 /* -march takes precedence over -mipsN, since it is more descriptive.
10743 There's no harm in specifying both as long as the ISA levels
10745 if (file_mips_isa != arch_info->isa)
10746 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10747 mips_cpu_info_from_isa (file_mips_isa)->name,
10748 mips_cpu_info_from_isa (arch_info->isa)->name);
10751 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10754 if (arch_info == 0)
10755 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10757 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10758 as_bad ("-march=%s is not compatible with the selected ABI",
10761 mips_set_architecture (arch_info);
10763 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10764 if (mips_tune_string != 0)
10765 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10767 if (tune_info == 0)
10768 mips_set_tune (arch_info);
10770 mips_set_tune (tune_info);
10772 if (file_mips_gp32 >= 0)
10774 /* The user specified the size of the integer registers. Make sure
10775 it agrees with the ABI and ISA. */
10776 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10777 as_bad (_("-mgp64 used with a 32-bit processor"));
10778 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10779 as_bad (_("-mgp32 used with a 64-bit ABI"));
10780 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10781 as_bad (_("-mgp64 used with a 32-bit ABI"));
10785 /* Infer the integer register size from the ABI and processor.
10786 Restrict ourselves to 32-bit registers if that's all the
10787 processor has, or if the ABI cannot handle 64-bit registers. */
10788 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10789 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10792 /* ??? GAS treats single-float processors as though they had 64-bit
10793 float registers (although it complains when double-precision
10794 instructions are used). As things stand, saying they have 32-bit
10795 registers would lead to spurious "register must be even" messages.
10796 So here we assume float registers are always the same size as
10797 integer ones, unless the user says otherwise. */
10798 if (file_mips_fp32 < 0)
10799 file_mips_fp32 = file_mips_gp32;
10801 /* End of GCC-shared inference code. */
10803 /* This flag is set when we have a 64-bit capable CPU but use only
10804 32-bit wide registers. Note that EABI does not use it. */
10805 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10806 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10807 || mips_abi == O32_ABI))
10808 mips_32bitmode = 1;
10810 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10811 as_bad (_("trap exception not supported at ISA 1"));
10813 /* If the selected architecture includes support for ASEs, enable
10814 generation of code for them. */
10815 if (mips_opts.mips16 == -1)
10816 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10817 if (mips_opts.ase_mips3d == -1)
10818 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10819 if (mips_opts.ase_mdmx == -1)
10820 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10822 file_mips_isa = mips_opts.isa;
10823 file_ase_mips16 = mips_opts.mips16;
10824 file_ase_mips3d = mips_opts.ase_mips3d;
10825 file_ase_mdmx = mips_opts.ase_mdmx;
10826 mips_opts.gp32 = file_mips_gp32;
10827 mips_opts.fp32 = file_mips_fp32;
10829 if (mips_flag_mdebug < 0)
10831 #ifdef OBJ_MAYBE_ECOFF
10832 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10833 mips_flag_mdebug = 1;
10835 #endif /* OBJ_MAYBE_ECOFF */
10836 mips_flag_mdebug = 0;
10841 mips_init_after_args (void)
10843 /* initialize opcodes */
10844 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10845 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10849 md_pcrel_from (fixS *fixP)
10851 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10852 switch (fixP->fx_r_type)
10854 case BFD_RELOC_16_PCREL_S2:
10855 case BFD_RELOC_MIPS_JMP:
10856 /* Return the address of the delay slot. */
10863 /* This is called before the symbol table is processed. In order to
10864 work with gcc when using mips-tfile, we must keep all local labels.
10865 However, in other cases, we want to discard them. If we were
10866 called with -g, but we didn't see any debugging information, it may
10867 mean that gcc is smuggling debugging information through to
10868 mips-tfile, in which case we must generate all local labels. */
10871 mips_frob_file_before_adjust (void)
10873 #ifndef NO_ECOFF_DEBUGGING
10874 if (ECOFF_DEBUGGING
10876 && ! ecoff_debugging_seen)
10877 flag_keep_locals = 1;
10881 /* Sort any unmatched HI16_S relocs so that they immediately precede
10882 the corresponding LO reloc. This is called before md_apply_fix3 and
10883 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10884 explicit use of the %hi modifier. */
10887 mips_frob_file (void)
10889 struct mips_hi_fixup *l;
10891 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10893 segment_info_type *seginfo;
10896 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10898 /* If a GOT16 relocation turns out to be against a global symbol,
10899 there isn't supposed to be a matching LO. */
10900 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10901 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10904 /* Check quickly whether the next fixup happens to be a matching %lo. */
10905 if (fixup_has_matching_lo_p (l->fixp))
10908 /* Look through the fixups for this segment for a matching %lo.
10909 When we find one, move the %hi just in front of it. We do
10910 this in two passes. In the first pass, we try to find a
10911 unique %lo. In the second pass, we permit multiple %hi
10912 relocs for a single %lo (this is a GNU extension). */
10913 seginfo = seg_info (l->seg);
10914 for (pass = 0; pass < 2; pass++)
10919 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10921 /* Check whether this is a %lo fixup which matches l->fixp. */
10922 if (f->fx_r_type == BFD_RELOC_LO16
10923 && f->fx_addsy == l->fixp->fx_addsy
10924 && f->fx_offset == l->fixp->fx_offset
10927 || !reloc_needs_lo_p (prev->fx_r_type)
10928 || !fixup_has_matching_lo_p (prev)))
10932 /* Move l->fixp before f. */
10933 for (pf = &seginfo->fix_root;
10935 pf = &(*pf)->fx_next)
10936 assert (*pf != NULL);
10938 *pf = l->fixp->fx_next;
10940 l->fixp->fx_next = f;
10942 seginfo->fix_root = l->fixp;
10944 prev->fx_next = l->fixp;
10955 #if 0 /* GCC code motion plus incomplete dead code elimination
10956 can leave a %hi without a %lo. */
10958 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10959 _("Unmatched %%hi reloc"));
10965 /* When generating embedded PIC code we need to use a special
10966 relocation to represent the difference of two symbols in the .text
10967 section (switch tables use a difference of this sort). See
10968 include/coff/mips.h for details. This macro checks whether this
10969 fixup requires the special reloc. */
10970 #define SWITCH_TABLE(fixp) \
10971 ((fixp)->fx_r_type == BFD_RELOC_32 \
10972 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10973 && (fixp)->fx_addsy != NULL \
10974 && (fixp)->fx_subsy != NULL \
10975 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10976 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10978 /* When generating embedded PIC code we must keep all PC relative
10979 relocations, in case the linker has to relax a call. We also need
10980 to keep relocations for switch table entries.
10982 We may have combined relocations without symbols in the N32/N64 ABI.
10983 We have to prevent gas from dropping them. */
10986 mips_force_relocation (fixS *fixp)
10988 if (generic_force_reloc (fixp))
10992 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10993 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10994 || fixp->fx_r_type == BFD_RELOC_HI16_S
10995 || fixp->fx_r_type == BFD_RELOC_LO16))
10998 return (mips_pic == EMBEDDED_PIC
11000 || SWITCH_TABLE (fixp)
11001 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11002 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11005 /* This hook is called before a fix is simplified. We don't really
11006 decide whether to skip a fix here. Rather, we turn global symbols
11007 used as branch targets into local symbols, such that they undergo
11008 simplification. We can only do this if the symbol is defined and
11009 it is in the same section as the branch. If this doesn't hold, we
11010 emit a better error message than just saying the relocation is not
11011 valid for the selected object format.
11013 FIXP is the fix-up we're going to try to simplify, SEG is the
11014 segment in which the fix up occurs. The return value should be
11015 non-zero to indicate the fix-up is valid for further
11016 simplifications. */
11019 mips_validate_fix (struct fix *fixP, asection *seg)
11021 /* There's a lot of discussion on whether it should be possible to
11022 use R_MIPS_PC16 to represent branch relocations. The outcome
11023 seems to be that it can, but gas/bfd are very broken in creating
11024 RELA relocations for this, so for now we only accept branches to
11025 symbols in the same section. Anything else is of dubious value,
11026 since there's no guarantee that at link time the symbol would be
11027 in range. Even for branches to local symbols this is arguably
11028 wrong, since it we assume the symbol is not going to be
11029 overridden, which should be possible per ELF library semantics,
11030 but then, there isn't a dynamic relocation that could be used to
11031 this effect, and the target would likely be out of range as well.
11033 Unfortunately, it seems that there is too much code out there
11034 that relies on branches to symbols that are global to be resolved
11035 as if they were local, like the IRIX tools do, so we do it as
11036 well, but with a warning so that people are reminded to fix their
11037 code. If we ever get back to using R_MIPS_PC16 for branch
11038 targets, this entire block should go away (and probably the
11039 whole function). */
11041 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11042 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11043 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11044 && mips_pic != EMBEDDED_PIC)
11045 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11048 if (! S_IS_DEFINED (fixP->fx_addsy))
11050 as_bad_where (fixP->fx_file, fixP->fx_line,
11051 _("Cannot branch to undefined symbol."));
11052 /* Avoid any further errors about this fixup. */
11055 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11057 as_bad_where (fixP->fx_file, fixP->fx_line,
11058 _("Cannot branch to symbol in another section."));
11061 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11063 symbolS *sym = fixP->fx_addsy;
11065 if (mips_pic == SVR4_PIC)
11066 as_warn_where (fixP->fx_file, fixP->fx_line,
11067 _("Pretending global symbol used as branch target is local."));
11069 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11070 S_GET_SEGMENT (sym),
11072 symbol_get_frag (sym));
11073 copy_symbol_attributes (fixP->fx_addsy, sym);
11074 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11075 assert (symbol_resolved_p (sym));
11076 symbol_mark_resolved (fixP->fx_addsy);
11083 /* Apply a fixup to the object file. */
11086 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11090 static int previous_fx_r_type = 0;
11091 reloc_howto_type *howto;
11093 /* We ignore generic BFD relocations we don't know about. */
11094 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11098 assert (fixP->fx_size == 4
11099 || fixP->fx_r_type == BFD_RELOC_16
11100 || fixP->fx_r_type == BFD_RELOC_64
11101 || fixP->fx_r_type == BFD_RELOC_CTOR
11102 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11103 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11104 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11106 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11108 /* We are not done if this is a composite relocation to set up gp. */
11109 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11110 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11111 || (fixP->fx_r_type == BFD_RELOC_64
11112 && (previous_fx_r_type == BFD_RELOC_GPREL32
11113 || previous_fx_r_type == BFD_RELOC_GPREL16))
11114 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11115 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11116 || fixP->fx_r_type == BFD_RELOC_LO16))))
11118 previous_fx_r_type = fixP->fx_r_type;
11120 switch (fixP->fx_r_type)
11122 case BFD_RELOC_MIPS_JMP:
11123 case BFD_RELOC_MIPS_SHIFT5:
11124 case BFD_RELOC_MIPS_SHIFT6:
11125 case BFD_RELOC_MIPS_GOT_DISP:
11126 case BFD_RELOC_MIPS_GOT_PAGE:
11127 case BFD_RELOC_MIPS_GOT_OFST:
11128 case BFD_RELOC_MIPS_SUB:
11129 case BFD_RELOC_MIPS_INSERT_A:
11130 case BFD_RELOC_MIPS_INSERT_B:
11131 case BFD_RELOC_MIPS_DELETE:
11132 case BFD_RELOC_MIPS_HIGHEST:
11133 case BFD_RELOC_MIPS_HIGHER:
11134 case BFD_RELOC_MIPS_SCN_DISP:
11135 case BFD_RELOC_MIPS_REL16:
11136 case BFD_RELOC_MIPS_RELGOT:
11137 case BFD_RELOC_MIPS_JALR:
11138 case BFD_RELOC_HI16:
11139 case BFD_RELOC_HI16_S:
11140 case BFD_RELOC_GPREL16:
11141 case BFD_RELOC_MIPS_LITERAL:
11142 case BFD_RELOC_MIPS_CALL16:
11143 case BFD_RELOC_MIPS_GOT16:
11144 case BFD_RELOC_GPREL32:
11145 case BFD_RELOC_MIPS_GOT_HI16:
11146 case BFD_RELOC_MIPS_GOT_LO16:
11147 case BFD_RELOC_MIPS_CALL_HI16:
11148 case BFD_RELOC_MIPS_CALL_LO16:
11149 case BFD_RELOC_MIPS16_GPREL:
11150 if (fixP->fx_pcrel)
11151 as_bad_where (fixP->fx_file, fixP->fx_line,
11152 _("Invalid PC relative reloc"));
11153 /* Nothing needed to do. The value comes from the reloc entry */
11156 case BFD_RELOC_MIPS16_JMP:
11157 /* We currently always generate a reloc against a symbol, which
11158 means that we don't want an addend even if the symbol is
11163 case BFD_RELOC_PCREL_HI16_S:
11164 /* The addend for this is tricky if it is internal, so we just
11165 do everything here rather than in bfd_install_relocation. */
11166 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11169 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11171 /* For an external symbol adjust by the address to make it
11172 pcrel_offset. We use the address of the RELLO reloc
11173 which follows this one. */
11174 *valP += (fixP->fx_next->fx_frag->fr_address
11175 + fixP->fx_next->fx_where);
11177 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11178 if (target_big_endian)
11180 md_number_to_chars (buf, *valP, 2);
11183 case BFD_RELOC_PCREL_LO16:
11184 /* The addend for this is tricky if it is internal, so we just
11185 do everything here rather than in bfd_install_relocation. */
11186 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11189 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11190 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11191 if (target_big_endian)
11193 md_number_to_chars (buf, *valP, 2);
11197 /* This is handled like BFD_RELOC_32, but we output a sign
11198 extended value if we are only 32 bits. */
11200 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11202 if (8 <= sizeof (valueT))
11203 md_number_to_chars (buf, *valP, 8);
11208 if ((*valP & 0x80000000) != 0)
11212 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11214 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11220 case BFD_RELOC_RVA:
11222 /* If we are deleting this reloc entry, we must fill in the
11223 value now. This can happen if we have a .word which is not
11224 resolved when it appears but is later defined. We also need
11225 to fill in the value if this is an embedded PIC switch table
11228 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11229 md_number_to_chars (buf, *valP, 4);
11233 /* If we are deleting this reloc entry, we must fill in the
11235 assert (fixP->fx_size == 2);
11237 md_number_to_chars (buf, *valP, 2);
11240 case BFD_RELOC_LO16:
11241 /* When handling an embedded PIC switch statement, we can wind
11242 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11245 if (*valP + 0x8000 > 0xffff)
11246 as_bad_where (fixP->fx_file, fixP->fx_line,
11247 _("relocation overflow"));
11248 if (target_big_endian)
11250 md_number_to_chars (buf, *valP, 2);
11254 case BFD_RELOC_16_PCREL_S2:
11255 if ((*valP & 0x3) != 0)
11256 as_bad_where (fixP->fx_file, fixP->fx_line,
11257 _("Branch to odd address (%lx)"), (long) *valP);
11260 * We need to save the bits in the instruction since fixup_segment()
11261 * might be deleting the relocation entry (i.e., a branch within
11262 * the current segment).
11264 if (! fixP->fx_done)
11267 /* update old instruction data */
11268 if (target_big_endian)
11269 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11271 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11273 if (*valP + 0x20000 <= 0x3ffff)
11275 insn |= (*valP >> 2) & 0xffff;
11276 md_number_to_chars (buf, insn, 4);
11278 else if (mips_pic == NO_PIC
11280 && fixP->fx_frag->fr_address >= text_section->vma
11281 && (fixP->fx_frag->fr_address
11282 < text_section->vma + text_section->_raw_size)
11283 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11284 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11285 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11287 /* The branch offset is too large. If this is an
11288 unconditional branch, and we are not generating PIC code,
11289 we can convert it to an absolute jump instruction. */
11290 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11291 insn = 0x0c000000; /* jal */
11293 insn = 0x08000000; /* j */
11294 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11296 fixP->fx_addsy = section_symbol (text_section);
11297 *valP += md_pcrel_from (fixP);
11298 md_number_to_chars (buf, insn, 4);
11302 /* If we got here, we have branch-relaxation disabled,
11303 and there's nothing we can do to fix this instruction
11304 without turning it into a longer sequence. */
11305 as_bad_where (fixP->fx_file, fixP->fx_line,
11306 _("Branch out of range"));
11310 case BFD_RELOC_VTABLE_INHERIT:
11313 && !S_IS_DEFINED (fixP->fx_addsy)
11314 && !S_IS_WEAK (fixP->fx_addsy))
11315 S_SET_WEAK (fixP->fx_addsy);
11318 case BFD_RELOC_VTABLE_ENTRY:
11326 /* Remember value for tc_gen_reloc. */
11327 fixP->fx_addnumber = *valP;
11332 printInsn (unsigned long oc)
11334 const struct mips_opcode *p;
11335 int treg, sreg, dreg, shamt;
11340 for (i = 0; i < NUMOPCODES; ++i)
11342 p = &mips_opcodes[i];
11343 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11345 printf ("%08lx %s\t", oc, p->name);
11346 treg = (oc >> 16) & 0x1f;
11347 sreg = (oc >> 21) & 0x1f;
11348 dreg = (oc >> 11) & 0x1f;
11349 shamt = (oc >> 6) & 0x1f;
11351 for (args = p->args;; ++args)
11362 printf ("%c", *args);
11366 assert (treg == sreg);
11367 printf ("$%d,$%d", treg, sreg);
11372 printf ("$%d", dreg);
11377 printf ("$%d", treg);
11381 printf ("0x%x", treg);
11386 printf ("$%d", sreg);
11390 printf ("0x%08lx", oc & 0x1ffffff);
11397 printf ("%d", imm);
11402 printf ("$%d", shamt);
11413 printf (_("%08lx UNDEFINED\n"), oc);
11424 name = input_line_pointer;
11425 c = get_symbol_end ();
11426 p = (symbolS *) symbol_find_or_make (name);
11427 *input_line_pointer = c;
11431 /* Align the current frag to a given power of two. The MIPS assembler
11432 also automatically adjusts any preceding label. */
11435 mips_align (int to, int fill, symbolS *label)
11437 mips_emit_delays (FALSE);
11438 frag_align (to, fill, 0);
11439 record_alignment (now_seg, to);
11442 assert (S_GET_SEGMENT (label) == now_seg);
11443 symbol_set_frag (label, frag_now);
11444 S_SET_VALUE (label, (valueT) frag_now_fix ());
11448 /* Align to a given power of two. .align 0 turns off the automatic
11449 alignment used by the data creating pseudo-ops. */
11452 s_align (int x ATTRIBUTE_UNUSED)
11455 register long temp_fill;
11456 long max_alignment = 15;
11460 o Note that the assembler pulls down any immediately preceding label
11461 to the aligned address.
11462 o It's not documented but auto alignment is reinstated by
11463 a .align pseudo instruction.
11464 o Note also that after auto alignment is turned off the mips assembler
11465 issues an error on attempt to assemble an improperly aligned data item.
11470 temp = get_absolute_expression ();
11471 if (temp > max_alignment)
11472 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11475 as_warn (_("Alignment negative: 0 assumed."));
11478 if (*input_line_pointer == ',')
11480 ++input_line_pointer;
11481 temp_fill = get_absolute_expression ();
11488 mips_align (temp, (int) temp_fill,
11489 insn_labels != NULL ? insn_labels->label : NULL);
11496 demand_empty_rest_of_line ();
11500 mips_flush_pending_output (void)
11502 mips_emit_delays (FALSE);
11503 mips_clear_insn_labels ();
11507 s_change_sec (int sec)
11511 /* When generating embedded PIC code, we only use the .text, .lit8,
11512 .sdata and .sbss sections. We change the .data and .rdata
11513 pseudo-ops to use .sdata. */
11514 if (mips_pic == EMBEDDED_PIC
11515 && (sec == 'd' || sec == 'r'))
11519 /* The ELF backend needs to know that we are changing sections, so
11520 that .previous works correctly. We could do something like check
11521 for an obj_section_change_hook macro, but that might be confusing
11522 as it would not be appropriate to use it in the section changing
11523 functions in read.c, since obj-elf.c intercepts those. FIXME:
11524 This should be cleaner, somehow. */
11525 obj_elf_section_change_hook ();
11528 mips_emit_delays (FALSE);
11538 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11539 demand_empty_rest_of_line ();
11543 if (USE_GLOBAL_POINTER_OPT)
11545 seg = subseg_new (RDATA_SECTION_NAME,
11546 (subsegT) get_absolute_expression ());
11547 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11549 bfd_set_section_flags (stdoutput, seg,
11555 if (strcmp (TARGET_OS, "elf") != 0)
11556 record_alignment (seg, 4);
11558 demand_empty_rest_of_line ();
11562 as_bad (_("No read only data section in this object file format"));
11563 demand_empty_rest_of_line ();
11569 if (USE_GLOBAL_POINTER_OPT)
11571 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11572 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11574 bfd_set_section_flags (stdoutput, seg,
11575 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11577 if (strcmp (TARGET_OS, "elf") != 0)
11578 record_alignment (seg, 4);
11580 demand_empty_rest_of_line ();
11585 as_bad (_("Global pointers not supported; recompile -G 0"));
11586 demand_empty_rest_of_line ();
11595 s_change_section (int ignore ATTRIBUTE_UNUSED)
11598 char *section_name;
11603 int section_entry_size;
11604 int section_alignment;
11606 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11609 section_name = input_line_pointer;
11610 c = get_symbol_end ();
11612 next_c = *(input_line_pointer + 1);
11614 /* Do we have .section Name<,"flags">? */
11615 if (c != ',' || (c == ',' && next_c == '"'))
11617 /* just after name is now '\0'. */
11618 *input_line_pointer = c;
11619 input_line_pointer = section_name;
11620 obj_elf_section (ignore);
11623 input_line_pointer++;
11625 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11627 section_type = get_absolute_expression ();
11630 if (*input_line_pointer++ == ',')
11631 section_flag = get_absolute_expression ();
11634 if (*input_line_pointer++ == ',')
11635 section_entry_size = get_absolute_expression ();
11637 section_entry_size = 0;
11638 if (*input_line_pointer++ == ',')
11639 section_alignment = get_absolute_expression ();
11641 section_alignment = 0;
11643 section_name = xstrdup (section_name);
11645 /* When using the generic form of .section (as implemented by obj-elf.c),
11646 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11647 traditionally had to fall back on the more common @progbits instead.
11649 There's nothing really harmful in this, since bfd will correct
11650 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11651 means that, for backwards compatibiltiy, the special_section entries
11652 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11654 Even so, we shouldn't force users of the MIPS .section syntax to
11655 incorrectly label the sections as SHT_PROGBITS. The best compromise
11656 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11657 generic type-checking code. */
11658 if (section_type == SHT_MIPS_DWARF)
11659 section_type = SHT_PROGBITS;
11661 obj_elf_change_section (section_name, section_type, section_flag,
11662 section_entry_size, 0, 0, 0);
11664 if (now_seg->name != section_name)
11665 free (section_name);
11666 #endif /* OBJ_ELF */
11670 mips_enable_auto_align (void)
11676 s_cons (int log_size)
11680 label = insn_labels != NULL ? insn_labels->label : NULL;
11681 mips_emit_delays (FALSE);
11682 if (log_size > 0 && auto_align)
11683 mips_align (log_size, 0, label);
11684 mips_clear_insn_labels ();
11685 cons (1 << log_size);
11689 s_float_cons (int type)
11693 label = insn_labels != NULL ? insn_labels->label : NULL;
11695 mips_emit_delays (FALSE);
11700 mips_align (3, 0, label);
11702 mips_align (2, 0, label);
11705 mips_clear_insn_labels ();
11710 /* Handle .globl. We need to override it because on Irix 5 you are
11713 where foo is an undefined symbol, to mean that foo should be
11714 considered to be the address of a function. */
11717 s_mips_globl (int x ATTRIBUTE_UNUSED)
11724 name = input_line_pointer;
11725 c = get_symbol_end ();
11726 symbolP = symbol_find_or_make (name);
11727 *input_line_pointer = c;
11728 SKIP_WHITESPACE ();
11730 /* On Irix 5, every global symbol that is not explicitly labelled as
11731 being a function is apparently labelled as being an object. */
11734 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11739 secname = input_line_pointer;
11740 c = get_symbol_end ();
11741 sec = bfd_get_section_by_name (stdoutput, secname);
11743 as_bad (_("%s: no such section"), secname);
11744 *input_line_pointer = c;
11746 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11747 flag = BSF_FUNCTION;
11750 symbol_get_bfdsym (symbolP)->flags |= flag;
11752 S_SET_EXTERNAL (symbolP);
11753 demand_empty_rest_of_line ();
11757 s_option (int x ATTRIBUTE_UNUSED)
11762 opt = input_line_pointer;
11763 c = get_symbol_end ();
11767 /* FIXME: What does this mean? */
11769 else if (strncmp (opt, "pic", 3) == 0)
11773 i = atoi (opt + 3);
11778 mips_pic = SVR4_PIC;
11779 mips_abicalls = TRUE;
11782 as_bad (_(".option pic%d not supported"), i);
11784 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11786 if (g_switch_seen && g_switch_value != 0)
11787 as_warn (_("-G may not be used with SVR4 PIC code"));
11788 g_switch_value = 0;
11789 bfd_set_gp_size (stdoutput, 0);
11793 as_warn (_("Unrecognized option \"%s\""), opt);
11795 *input_line_pointer = c;
11796 demand_empty_rest_of_line ();
11799 /* This structure is used to hold a stack of .set values. */
11801 struct mips_option_stack
11803 struct mips_option_stack *next;
11804 struct mips_set_options options;
11807 static struct mips_option_stack *mips_opts_stack;
11809 /* Handle the .set pseudo-op. */
11812 s_mipsset (int x ATTRIBUTE_UNUSED)
11814 char *name = input_line_pointer, ch;
11816 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11817 ++input_line_pointer;
11818 ch = *input_line_pointer;
11819 *input_line_pointer = '\0';
11821 if (strcmp (name, "reorder") == 0)
11823 if (mips_opts.noreorder && prev_nop_frag != NULL)
11825 /* If we still have pending nops, we can discard them. The
11826 usual nop handling will insert any that are still
11828 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11829 * (mips_opts.mips16 ? 2 : 4));
11830 prev_nop_frag = NULL;
11832 mips_opts.noreorder = 0;
11834 else if (strcmp (name, "noreorder") == 0)
11836 mips_emit_delays (TRUE);
11837 mips_opts.noreorder = 1;
11838 mips_any_noreorder = 1;
11840 else if (strcmp (name, "at") == 0)
11842 mips_opts.noat = 0;
11844 else if (strcmp (name, "noat") == 0)
11846 mips_opts.noat = 1;
11848 else if (strcmp (name, "macro") == 0)
11850 mips_opts.warn_about_macros = 0;
11852 else if (strcmp (name, "nomacro") == 0)
11854 if (mips_opts.noreorder == 0)
11855 as_bad (_("`noreorder' must be set before `nomacro'"));
11856 mips_opts.warn_about_macros = 1;
11858 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11860 mips_opts.nomove = 0;
11862 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11864 mips_opts.nomove = 1;
11866 else if (strcmp (name, "bopt") == 0)
11868 mips_opts.nobopt = 0;
11870 else if (strcmp (name, "nobopt") == 0)
11872 mips_opts.nobopt = 1;
11874 else if (strcmp (name, "mips16") == 0
11875 || strcmp (name, "MIPS-16") == 0)
11876 mips_opts.mips16 = 1;
11877 else if (strcmp (name, "nomips16") == 0
11878 || strcmp (name, "noMIPS-16") == 0)
11879 mips_opts.mips16 = 0;
11880 else if (strcmp (name, "mips3d") == 0)
11881 mips_opts.ase_mips3d = 1;
11882 else if (strcmp (name, "nomips3d") == 0)
11883 mips_opts.ase_mips3d = 0;
11884 else if (strcmp (name, "mdmx") == 0)
11885 mips_opts.ase_mdmx = 1;
11886 else if (strcmp (name, "nomdmx") == 0)
11887 mips_opts.ase_mdmx = 0;
11888 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11892 /* Permit the user to change the ISA and architecture on the fly.
11893 Needless to say, misuse can cause serious problems. */
11894 if (strcmp (name, "mips0") == 0)
11897 mips_opts.isa = file_mips_isa;
11899 else if (strcmp (name, "mips1") == 0)
11900 mips_opts.isa = ISA_MIPS1;
11901 else if (strcmp (name, "mips2") == 0)
11902 mips_opts.isa = ISA_MIPS2;
11903 else if (strcmp (name, "mips3") == 0)
11904 mips_opts.isa = ISA_MIPS3;
11905 else if (strcmp (name, "mips4") == 0)
11906 mips_opts.isa = ISA_MIPS4;
11907 else if (strcmp (name, "mips5") == 0)
11908 mips_opts.isa = ISA_MIPS5;
11909 else if (strcmp (name, "mips32") == 0)
11910 mips_opts.isa = ISA_MIPS32;
11911 else if (strcmp (name, "mips32r2") == 0)
11912 mips_opts.isa = ISA_MIPS32R2;
11913 else if (strcmp (name, "mips64") == 0)
11914 mips_opts.isa = ISA_MIPS64;
11915 else if (strcmp (name, "mips64r2") == 0)
11916 mips_opts.isa = ISA_MIPS64R2;
11917 else if (strcmp (name, "arch=default") == 0)
11920 mips_opts.arch = file_mips_arch;
11921 mips_opts.isa = file_mips_isa;
11923 else if (strncmp (name, "arch=", 5) == 0)
11925 const struct mips_cpu_info *p;
11927 p = mips_parse_cpu("internal use", name + 5);
11929 as_bad (_("unknown architecture %s"), name + 5);
11932 mips_opts.arch = p->cpu;
11933 mips_opts.isa = p->isa;
11937 as_bad (_("unknown ISA level %s"), name + 4);
11939 switch (mips_opts.isa)
11947 mips_opts.gp32 = 1;
11948 mips_opts.fp32 = 1;
11955 mips_opts.gp32 = 0;
11956 mips_opts.fp32 = 0;
11959 as_bad (_("unknown ISA level %s"), name + 4);
11964 mips_opts.gp32 = file_mips_gp32;
11965 mips_opts.fp32 = file_mips_fp32;
11968 else if (strcmp (name, "autoextend") == 0)
11969 mips_opts.noautoextend = 0;
11970 else if (strcmp (name, "noautoextend") == 0)
11971 mips_opts.noautoextend = 1;
11972 else if (strcmp (name, "push") == 0)
11974 struct mips_option_stack *s;
11976 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11977 s->next = mips_opts_stack;
11978 s->options = mips_opts;
11979 mips_opts_stack = s;
11981 else if (strcmp (name, "pop") == 0)
11983 struct mips_option_stack *s;
11985 s = mips_opts_stack;
11987 as_bad (_(".set pop with no .set push"));
11990 /* If we're changing the reorder mode we need to handle
11991 delay slots correctly. */
11992 if (s->options.noreorder && ! mips_opts.noreorder)
11993 mips_emit_delays (TRUE);
11994 else if (! s->options.noreorder && mips_opts.noreorder)
11996 if (prev_nop_frag != NULL)
11998 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11999 * (mips_opts.mips16 ? 2 : 4));
12000 prev_nop_frag = NULL;
12004 mips_opts = s->options;
12005 mips_opts_stack = s->next;
12011 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12013 *input_line_pointer = ch;
12014 demand_empty_rest_of_line ();
12017 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12018 .option pic2. It means to generate SVR4 PIC calls. */
12021 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12023 mips_pic = SVR4_PIC;
12024 mips_abicalls = TRUE;
12025 if (USE_GLOBAL_POINTER_OPT)
12027 if (g_switch_seen && g_switch_value != 0)
12028 as_warn (_("-G may not be used with SVR4 PIC code"));
12029 g_switch_value = 0;
12031 bfd_set_gp_size (stdoutput, 0);
12032 demand_empty_rest_of_line ();
12035 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12036 PIC code. It sets the $gp register for the function based on the
12037 function address, which is in the register named in the argument.
12038 This uses a relocation against _gp_disp, which is handled specially
12039 by the linker. The result is:
12040 lui $gp,%hi(_gp_disp)
12041 addiu $gp,$gp,%lo(_gp_disp)
12042 addu $gp,$gp,.cpload argument
12043 The .cpload argument is normally $25 == $t9. */
12046 s_cpload (int ignore ATTRIBUTE_UNUSED)
12050 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12051 .cpload is ignored. */
12052 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12058 /* .cpload should be in a .set noreorder section. */
12059 if (mips_opts.noreorder == 0)
12060 as_warn (_(".cpload not in noreorder section"));
12062 ex.X_op = O_symbol;
12063 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12064 ex.X_op_symbol = NULL;
12065 ex.X_add_number = 0;
12067 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12068 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12071 macro_build_lui (&ex, mips_gp_register);
12072 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12073 mips_gp_register, BFD_RELOC_LO16);
12074 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12075 mips_gp_register, tc_get_register (0));
12078 demand_empty_rest_of_line ();
12081 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12082 .cpsetup $reg1, offset|$reg2, label
12084 If offset is given, this results in:
12085 sd $gp, offset($sp)
12086 lui $gp, %hi(%neg(%gp_rel(label)))
12087 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12088 daddu $gp, $gp, $reg1
12090 If $reg2 is given, this results in:
12091 daddu $reg2, $gp, $0
12092 lui $gp, %hi(%neg(%gp_rel(label)))
12093 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12094 daddu $gp, $gp, $reg1
12095 $reg1 is normally $25 == $t9. */
12097 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12099 expressionS ex_off;
12100 expressionS ex_sym;
12104 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12105 We also need NewABI support. */
12106 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12112 reg1 = tc_get_register (0);
12113 SKIP_WHITESPACE ();
12114 if (*input_line_pointer != ',')
12116 as_bad (_("missing argument separator ',' for .cpsetup"));
12120 ++input_line_pointer;
12121 SKIP_WHITESPACE ();
12122 if (*input_line_pointer == '$')
12124 mips_cpreturn_register = tc_get_register (0);
12125 mips_cpreturn_offset = -1;
12129 mips_cpreturn_offset = get_absolute_expression ();
12130 mips_cpreturn_register = -1;
12132 SKIP_WHITESPACE ();
12133 if (*input_line_pointer != ',')
12135 as_bad (_("missing argument separator ',' for .cpsetup"));
12139 ++input_line_pointer;
12140 SKIP_WHITESPACE ();
12141 expression (&ex_sym);
12144 if (mips_cpreturn_register == -1)
12146 ex_off.X_op = O_constant;
12147 ex_off.X_add_symbol = NULL;
12148 ex_off.X_op_symbol = NULL;
12149 ex_off.X_add_number = mips_cpreturn_offset;
12151 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12152 BFD_RELOC_LO16, SP);
12155 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12156 mips_gp_register, 0);
12158 /* Ensure there's room for the next two instructions, so that `f'
12159 doesn't end up with an address in the wrong frag. */
12162 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
12163 fix_new (frag_now, f - frag_now->fr_literal,
12164 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12165 fix_new (frag_now, f - frag_now->fr_literal,
12166 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12169 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12170 mips_gp_register, BFD_RELOC_GPREL16);
12171 fix_new (frag_now, f - frag_now->fr_literal,
12172 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12173 fix_new (frag_now, f - frag_now->fr_literal,
12174 4, NULL, 0, 0, BFD_RELOC_LO16);
12176 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12177 mips_gp_register, reg1);
12180 demand_empty_rest_of_line ();
12184 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12186 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12187 .cplocal is ignored. */
12188 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12194 mips_gp_register = tc_get_register (0);
12195 demand_empty_rest_of_line ();
12198 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12199 offset from $sp. The offset is remembered, and after making a PIC
12200 call $gp is restored from that location. */
12203 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12207 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12208 .cprestore is ignored. */
12209 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12215 mips_cprestore_offset = get_absolute_expression ();
12216 mips_cprestore_valid = 1;
12218 ex.X_op = O_constant;
12219 ex.X_add_symbol = NULL;
12220 ex.X_op_symbol = NULL;
12221 ex.X_add_number = mips_cprestore_offset;
12224 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12225 SP, HAVE_64BIT_ADDRESSES);
12228 demand_empty_rest_of_line ();
12231 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12232 was given in the preceding .cpsetup, it results in:
12233 ld $gp, offset($sp)
12235 If a register $reg2 was given there, it results in:
12236 daddu $gp, $reg2, $0
12239 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12243 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12244 We also need NewABI support. */
12245 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12252 if (mips_cpreturn_register == -1)
12254 ex.X_op = O_constant;
12255 ex.X_add_symbol = NULL;
12256 ex.X_op_symbol = NULL;
12257 ex.X_add_number = mips_cpreturn_offset;
12259 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12262 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12263 mips_cpreturn_register, 0);
12266 demand_empty_rest_of_line ();
12269 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12270 code. It sets the offset to use in gp_rel relocations. */
12273 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12275 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12276 We also need NewABI support. */
12277 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12283 mips_gprel_offset = get_absolute_expression ();
12285 demand_empty_rest_of_line ();
12288 /* Handle the .gpword pseudo-op. This is used when generating PIC
12289 code. It generates a 32 bit GP relative reloc. */
12292 s_gpword (int ignore ATTRIBUTE_UNUSED)
12298 /* When not generating PIC code, this is treated as .word. */
12299 if (mips_pic != SVR4_PIC)
12305 label = insn_labels != NULL ? insn_labels->label : NULL;
12306 mips_emit_delays (TRUE);
12308 mips_align (2, 0, label);
12309 mips_clear_insn_labels ();
12313 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12315 as_bad (_("Unsupported use of .gpword"));
12316 ignore_rest_of_line ();
12320 md_number_to_chars (p, 0, 4);
12321 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12322 BFD_RELOC_GPREL32);
12324 demand_empty_rest_of_line ();
12328 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12334 /* When not generating PIC code, this is treated as .dword. */
12335 if (mips_pic != SVR4_PIC)
12341 label = insn_labels != NULL ? insn_labels->label : NULL;
12342 mips_emit_delays (TRUE);
12344 mips_align (3, 0, label);
12345 mips_clear_insn_labels ();
12349 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12351 as_bad (_("Unsupported use of .gpdword"));
12352 ignore_rest_of_line ();
12356 md_number_to_chars (p, 0, 8);
12357 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12358 BFD_RELOC_GPREL32);
12360 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12361 ex.X_op = O_absent;
12362 ex.X_add_symbol = 0;
12363 ex.X_add_number = 0;
12364 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12367 demand_empty_rest_of_line ();
12370 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12371 tables in SVR4 PIC code. */
12374 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12378 /* This is ignored when not generating SVR4 PIC code. */
12379 if (mips_pic != SVR4_PIC)
12385 /* Add $gp to the register named as an argument. */
12387 reg = tc_get_register (0);
12388 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12391 demand_empty_rest_of_line ();
12394 /* Handle the .insn pseudo-op. This marks instruction labels in
12395 mips16 mode. This permits the linker to handle them specially,
12396 such as generating jalx instructions when needed. We also make
12397 them odd for the duration of the assembly, in order to generate the
12398 right sort of code. We will make them even in the adjust_symtab
12399 routine, while leaving them marked. This is convenient for the
12400 debugger and the disassembler. The linker knows to make them odd
12404 s_insn (int ignore ATTRIBUTE_UNUSED)
12406 mips16_mark_labels ();
12408 demand_empty_rest_of_line ();
12411 /* Handle a .stabn directive. We need these in order to mark a label
12412 as being a mips16 text label correctly. Sometimes the compiler
12413 will emit a label, followed by a .stabn, and then switch sections.
12414 If the label and .stabn are in mips16 mode, then the label is
12415 really a mips16 text label. */
12418 s_mips_stab (int type)
12421 mips16_mark_labels ();
12426 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12430 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12437 name = input_line_pointer;
12438 c = get_symbol_end ();
12439 symbolP = symbol_find_or_make (name);
12440 S_SET_WEAK (symbolP);
12441 *input_line_pointer = c;
12443 SKIP_WHITESPACE ();
12445 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12447 if (S_IS_DEFINED (symbolP))
12449 as_bad ("ignoring attempt to redefine symbol %s",
12450 S_GET_NAME (symbolP));
12451 ignore_rest_of_line ();
12455 if (*input_line_pointer == ',')
12457 ++input_line_pointer;
12458 SKIP_WHITESPACE ();
12462 if (exp.X_op != O_symbol)
12464 as_bad ("bad .weakext directive");
12465 ignore_rest_of_line ();
12468 symbol_set_value_expression (symbolP, &exp);
12471 demand_empty_rest_of_line ();
12474 /* Parse a register string into a number. Called from the ECOFF code
12475 to parse .frame. The argument is non-zero if this is the frame
12476 register, so that we can record it in mips_frame_reg. */
12479 tc_get_register (int frame)
12483 SKIP_WHITESPACE ();
12484 if (*input_line_pointer++ != '$')
12486 as_warn (_("expected `$'"));
12489 else if (ISDIGIT (*input_line_pointer))
12491 reg = get_absolute_expression ();
12492 if (reg < 0 || reg >= 32)
12494 as_warn (_("Bad register number"));
12500 if (strncmp (input_line_pointer, "ra", 2) == 0)
12503 input_line_pointer += 2;
12505 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12508 input_line_pointer += 2;
12510 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12513 input_line_pointer += 2;
12515 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12518 input_line_pointer += 2;
12520 else if (strncmp (input_line_pointer, "at", 2) == 0)
12523 input_line_pointer += 2;
12525 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12528 input_line_pointer += 3;
12530 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12533 input_line_pointer += 3;
12535 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12538 input_line_pointer += 4;
12542 as_warn (_("Unrecognized register name"));
12544 while (ISALNUM(*input_line_pointer))
12545 input_line_pointer++;
12550 mips_frame_reg = reg != 0 ? reg : SP;
12551 mips_frame_reg_valid = 1;
12552 mips_cprestore_valid = 0;
12558 md_section_align (asection *seg, valueT addr)
12560 int align = bfd_get_section_alignment (stdoutput, seg);
12563 /* We don't need to align ELF sections to the full alignment.
12564 However, Irix 5 may prefer that we align them at least to a 16
12565 byte boundary. We don't bother to align the sections if we are
12566 targeted for an embedded system. */
12567 if (strcmp (TARGET_OS, "elf") == 0)
12573 return ((addr + (1 << align) - 1) & (-1 << align));
12576 /* Utility routine, called from above as well. If called while the
12577 input file is still being read, it's only an approximation. (For
12578 example, a symbol may later become defined which appeared to be
12579 undefined earlier.) */
12582 nopic_need_relax (symbolS *sym, int before_relaxing)
12587 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12589 const char *symname;
12592 /* Find out whether this symbol can be referenced off the $gp
12593 register. It can be if it is smaller than the -G size or if
12594 it is in the .sdata or .sbss section. Certain symbols can
12595 not be referenced off the $gp, although it appears as though
12597 symname = S_GET_NAME (sym);
12598 if (symname != (const char *) NULL
12599 && (strcmp (symname, "eprol") == 0
12600 || strcmp (symname, "etext") == 0
12601 || strcmp (symname, "_gp") == 0
12602 || strcmp (symname, "edata") == 0
12603 || strcmp (symname, "_fbss") == 0
12604 || strcmp (symname, "_fdata") == 0
12605 || strcmp (symname, "_ftext") == 0
12606 || strcmp (symname, "end") == 0
12607 || strcmp (symname, "_gp_disp") == 0))
12609 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12611 #ifndef NO_ECOFF_DEBUGGING
12612 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12613 && (symbol_get_obj (sym)->ecoff_extern_size
12614 <= g_switch_value))
12616 /* We must defer this decision until after the whole
12617 file has been read, since there might be a .extern
12618 after the first use of this symbol. */
12619 || (before_relaxing
12620 #ifndef NO_ECOFF_DEBUGGING
12621 && symbol_get_obj (sym)->ecoff_extern_size == 0
12623 && S_GET_VALUE (sym) == 0)
12624 || (S_GET_VALUE (sym) != 0
12625 && S_GET_VALUE (sym) <= g_switch_value)))
12629 const char *segname;
12631 segname = segment_name (S_GET_SEGMENT (sym));
12632 assert (strcmp (segname, ".lit8") != 0
12633 && strcmp (segname, ".lit4") != 0);
12634 change = (strcmp (segname, ".sdata") != 0
12635 && strcmp (segname, ".sbss") != 0
12636 && strncmp (segname, ".sdata.", 7) != 0
12637 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12642 /* We are not optimizing for the $gp register. */
12647 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12650 pic_need_relax (symbolS *sym, asection *segtype)
12653 bfd_boolean linkonce;
12655 /* Handle the case of a symbol equated to another symbol. */
12656 while (symbol_equated_reloc_p (sym))
12660 /* It's possible to get a loop here in a badly written
12662 n = symbol_get_value_expression (sym)->X_add_symbol;
12668 symsec = S_GET_SEGMENT (sym);
12670 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12672 if (symsec != segtype && ! S_IS_LOCAL (sym))
12674 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12678 /* The GNU toolchain uses an extension for ELF: a section
12679 beginning with the magic string .gnu.linkonce is a linkonce
12681 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12682 sizeof ".gnu.linkonce" - 1) == 0)
12686 /* This must duplicate the test in adjust_reloc_syms. */
12687 return (symsec != &bfd_und_section
12688 && symsec != &bfd_abs_section
12689 && ! bfd_is_com_section (symsec)
12692 /* A global or weak symbol is treated as external. */
12693 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12694 || (! S_IS_WEAK (sym)
12695 && (! S_IS_EXTERNAL (sym)
12696 || mips_pic == EMBEDDED_PIC)))
12702 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12703 extended opcode. SEC is the section the frag is in. */
12706 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12709 register const struct mips16_immed_operand *op;
12711 int mintiny, maxtiny;
12715 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12717 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12720 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12721 op = mips16_immed_operands;
12722 while (op->type != type)
12725 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12730 if (type == '<' || type == '>' || type == '[' || type == ']')
12733 maxtiny = 1 << op->nbits;
12738 maxtiny = (1 << op->nbits) - 1;
12743 mintiny = - (1 << (op->nbits - 1));
12744 maxtiny = (1 << (op->nbits - 1)) - 1;
12747 sym_frag = symbol_get_frag (fragp->fr_symbol);
12748 val = S_GET_VALUE (fragp->fr_symbol);
12749 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12755 /* We won't have the section when we are called from
12756 mips_relax_frag. However, we will always have been called
12757 from md_estimate_size_before_relax first. If this is a
12758 branch to a different section, we mark it as such. If SEC is
12759 NULL, and the frag is not marked, then it must be a branch to
12760 the same section. */
12763 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12768 /* Must have been called from md_estimate_size_before_relax. */
12771 fragp->fr_subtype =
12772 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12774 /* FIXME: We should support this, and let the linker
12775 catch branches and loads that are out of range. */
12776 as_bad_where (fragp->fr_file, fragp->fr_line,
12777 _("unsupported PC relative reference to different section"));
12781 if (fragp != sym_frag && sym_frag->fr_address == 0)
12782 /* Assume non-extended on the first relaxation pass.
12783 The address we have calculated will be bogus if this is
12784 a forward branch to another frag, as the forward frag
12785 will have fr_address == 0. */
12789 /* In this case, we know for sure that the symbol fragment is in
12790 the same section. If the relax_marker of the symbol fragment
12791 differs from the relax_marker of this fragment, we have not
12792 yet adjusted the symbol fragment fr_address. We want to add
12793 in STRETCH in order to get a better estimate of the address.
12794 This particularly matters because of the shift bits. */
12796 && sym_frag->relax_marker != fragp->relax_marker)
12800 /* Adjust stretch for any alignment frag. Note that if have
12801 been expanding the earlier code, the symbol may be
12802 defined in what appears to be an earlier frag. FIXME:
12803 This doesn't handle the fr_subtype field, which specifies
12804 a maximum number of bytes to skip when doing an
12806 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12808 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12811 stretch = - ((- stretch)
12812 & ~ ((1 << (int) f->fr_offset) - 1));
12814 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12823 addr = fragp->fr_address + fragp->fr_fix;
12825 /* The base address rules are complicated. The base address of
12826 a branch is the following instruction. The base address of a
12827 PC relative load or add is the instruction itself, but if it
12828 is in a delay slot (in which case it can not be extended) use
12829 the address of the instruction whose delay slot it is in. */
12830 if (type == 'p' || type == 'q')
12834 /* If we are currently assuming that this frag should be
12835 extended, then, the current address is two bytes
12837 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12840 /* Ignore the low bit in the target, since it will be set
12841 for a text label. */
12842 if ((val & 1) != 0)
12845 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12847 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12850 val -= addr & ~ ((1 << op->shift) - 1);
12852 /* Branch offsets have an implicit 0 in the lowest bit. */
12853 if (type == 'p' || type == 'q')
12856 /* If any of the shifted bits are set, we must use an extended
12857 opcode. If the address depends on the size of this
12858 instruction, this can lead to a loop, so we arrange to always
12859 use an extended opcode. We only check this when we are in
12860 the main relaxation loop, when SEC is NULL. */
12861 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12863 fragp->fr_subtype =
12864 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12868 /* If we are about to mark a frag as extended because the value
12869 is precisely maxtiny + 1, then there is a chance of an
12870 infinite loop as in the following code:
12875 In this case when the la is extended, foo is 0x3fc bytes
12876 away, so the la can be shrunk, but then foo is 0x400 away, so
12877 the la must be extended. To avoid this loop, we mark the
12878 frag as extended if it was small, and is about to become
12879 extended with a value of maxtiny + 1. */
12880 if (val == ((maxtiny + 1) << op->shift)
12881 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12884 fragp->fr_subtype =
12885 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12889 else if (symsec != absolute_section && sec != NULL)
12890 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12892 if ((val & ((1 << op->shift) - 1)) != 0
12893 || val < (mintiny << op->shift)
12894 || val > (maxtiny << op->shift))
12900 /* Compute the length of a branch sequence, and adjust the
12901 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12902 worst-case length is computed, with UPDATE being used to indicate
12903 whether an unconditional (-1), branch-likely (+1) or regular (0)
12904 branch is to be computed. */
12906 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12908 bfd_boolean toofar;
12912 && S_IS_DEFINED (fragp->fr_symbol)
12913 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12918 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12920 addr = fragp->fr_address + fragp->fr_fix + 4;
12924 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12927 /* If the symbol is not defined or it's in a different segment,
12928 assume the user knows what's going on and emit a short
12934 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12936 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12937 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12938 RELAX_BRANCH_LINK (fragp->fr_subtype),
12944 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12947 if (mips_pic != NO_PIC)
12949 /* Additional space for PIC loading of target address. */
12951 if (mips_opts.isa == ISA_MIPS1)
12952 /* Additional space for $at-stabilizing nop. */
12956 /* If branch is conditional. */
12957 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12964 /* Estimate the size of a frag before relaxing. Unless this is the
12965 mips16, we are not really relaxing here, and the final size is
12966 encoded in the subtype information. For the mips16, we have to
12967 decide whether we are using an extended opcode or not. */
12970 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12974 if (RELAX_BRANCH_P (fragp->fr_subtype))
12977 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12979 return fragp->fr_var;
12982 if (RELAX_MIPS16_P (fragp->fr_subtype))
12983 /* We don't want to modify the EXTENDED bit here; it might get us
12984 into infinite loops. We change it only in mips_relax_frag(). */
12985 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12987 if (mips_pic == NO_PIC)
12988 change = nopic_need_relax (fragp->fr_symbol, 0);
12989 else if (mips_pic == SVR4_PIC)
12990 change = pic_need_relax (fragp->fr_symbol, segtype);
12996 fragp->fr_subtype |= RELAX_USE_SECOND;
12997 return -RELAX_FIRST (fragp->fr_subtype);
13000 return -RELAX_SECOND (fragp->fr_subtype);
13003 /* This is called to see whether a reloc against a defined symbol
13004 should be converted into a reloc against a section. Don't adjust
13005 MIPS16 jump relocations, so we don't have to worry about the format
13006 of the offset in the .o file. Don't adjust relocations against
13007 mips16 symbols, so that the linker can find them if it needs to set
13011 mips_fix_adjustable (fixS *fixp)
13013 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13016 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13017 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13020 if (fixp->fx_addsy == NULL)
13024 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13025 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13026 && fixp->fx_subsy == NULL)
13033 /* Translate internal representation of relocation info to BFD target
13037 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13039 static arelent *retval[4];
13041 bfd_reloc_code_real_type code;
13043 memset (retval, 0, sizeof(retval));
13044 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13045 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13046 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13047 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13049 if (mips_pic == EMBEDDED_PIC
13050 && SWITCH_TABLE (fixp))
13052 /* For a switch table entry we use a special reloc. The addend
13053 is actually the difference between the reloc address and the
13055 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13056 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13057 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13058 fixp->fx_r_type = BFD_RELOC_GPREL32;
13060 else if (fixp->fx_pcrel)
13062 bfd_vma pcrel_address;
13064 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13065 high-part relocs is the address of the low-part reloc. */
13066 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13068 assert (fixp->fx_next != NULL
13069 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13070 pcrel_address = (fixp->fx_next->fx_where
13071 + fixp->fx_next->fx_frag->fr_address);
13074 pcrel_address = reloc->address;
13076 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13078 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13079 Relocations want only the symbol offset. */
13080 reloc->addend = fixp->fx_addnumber + pcrel_address;
13082 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13083 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13085 /* We use a special addend for an internal RELLO or RELHI reloc. */
13086 if (symbol_section_p (fixp->fx_addsy))
13087 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13089 reloc->addend = fixp->fx_addnumber + pcrel_address;
13093 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13094 /* A gruesome hack which is a result of the gruesome gas reloc
13096 reloc->addend = pcrel_address;
13098 reloc->addend = -pcrel_address;
13102 reloc->addend = fixp->fx_addnumber;
13104 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13105 entry to be used in the relocation's section offset. */
13106 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13108 reloc->address = reloc->addend;
13112 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13113 fixup_segment converted a non-PC relative reloc into a PC
13114 relative reloc. In such a case, we need to convert the reloc
13116 code = fixp->fx_r_type;
13117 if (fixp->fx_pcrel)
13122 code = BFD_RELOC_8_PCREL;
13125 code = BFD_RELOC_16_PCREL;
13128 code = BFD_RELOC_32_PCREL;
13131 code = BFD_RELOC_64_PCREL;
13133 case BFD_RELOC_8_PCREL:
13134 case BFD_RELOC_16_PCREL:
13135 case BFD_RELOC_32_PCREL:
13136 case BFD_RELOC_64_PCREL:
13137 case BFD_RELOC_16_PCREL_S2:
13138 case BFD_RELOC_PCREL_HI16_S:
13139 case BFD_RELOC_PCREL_LO16:
13142 as_bad_where (fixp->fx_file, fixp->fx_line,
13143 _("Cannot make %s relocation PC relative"),
13144 bfd_get_reloc_code_name (code));
13148 /* To support a PC relative reloc when generating embedded PIC code
13149 for ECOFF, we use a Cygnus extension. We check for that here to
13150 make sure that we don't let such a reloc escape normally. */
13151 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13152 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13153 && code == BFD_RELOC_16_PCREL_S2
13154 && mips_pic != EMBEDDED_PIC)
13155 reloc->howto = NULL;
13157 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13159 if (reloc->howto == NULL)
13161 as_bad_where (fixp->fx_file, fixp->fx_line,
13162 _("Can not represent %s relocation in this object file format"),
13163 bfd_get_reloc_code_name (code));
13170 /* Relax a machine dependent frag. This returns the amount by which
13171 the current size of the frag should change. */
13174 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13176 if (RELAX_BRANCH_P (fragp->fr_subtype))
13178 offsetT old_var = fragp->fr_var;
13180 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13182 return fragp->fr_var - old_var;
13185 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13188 if (mips16_extended_frag (fragp, NULL, stretch))
13190 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13192 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13197 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13199 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13206 /* Convert a machine dependent frag. */
13209 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13211 if (RELAX_BRANCH_P (fragp->fr_subtype))
13214 unsigned long insn;
13218 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13220 if (target_big_endian)
13221 insn = bfd_getb32 (buf);
13223 insn = bfd_getl32 (buf);
13225 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13227 /* We generate a fixup instead of applying it right now
13228 because, if there are linker relaxations, we're going to
13229 need the relocations. */
13230 exp.X_op = O_symbol;
13231 exp.X_add_symbol = fragp->fr_symbol;
13232 exp.X_add_number = fragp->fr_offset;
13234 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13236 BFD_RELOC_16_PCREL_S2);
13237 fixp->fx_file = fragp->fr_file;
13238 fixp->fx_line = fragp->fr_line;
13240 md_number_to_chars (buf, insn, 4);
13247 as_warn_where (fragp->fr_file, fragp->fr_line,
13248 _("relaxed out-of-range branch into a jump"));
13250 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13253 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13255 /* Reverse the branch. */
13256 switch ((insn >> 28) & 0xf)
13259 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13260 have the condition reversed by tweaking a single
13261 bit, and their opcodes all have 0x4???????. */
13262 assert ((insn & 0xf1000000) == 0x41000000);
13263 insn ^= 0x00010000;
13267 /* bltz 0x04000000 bgez 0x04010000
13268 bltzal 0x04100000 bgezal 0x04110000 */
13269 assert ((insn & 0xfc0e0000) == 0x04000000);
13270 insn ^= 0x00010000;
13274 /* beq 0x10000000 bne 0x14000000
13275 blez 0x18000000 bgtz 0x1c000000 */
13276 insn ^= 0x04000000;
13284 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13286 /* Clear the and-link bit. */
13287 assert ((insn & 0xfc1c0000) == 0x04100000);
13289 /* bltzal 0x04100000 bgezal 0x04110000
13290 bltzall 0x04120000 bgezall 0x04130000 */
13291 insn &= ~0x00100000;
13294 /* Branch over the branch (if the branch was likely) or the
13295 full jump (not likely case). Compute the offset from the
13296 current instruction to branch to. */
13297 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13301 /* How many bytes in instructions we've already emitted? */
13302 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13303 /* How many bytes in instructions from here to the end? */
13304 i = fragp->fr_var - i;
13306 /* Convert to instruction count. */
13308 /* Branch counts from the next instruction. */
13311 /* Branch over the jump. */
13312 md_number_to_chars (buf, insn, 4);
13316 md_number_to_chars (buf, 0, 4);
13319 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13321 /* beql $0, $0, 2f */
13323 /* Compute the PC offset from the current instruction to
13324 the end of the variable frag. */
13325 /* How many bytes in instructions we've already emitted? */
13326 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13327 /* How many bytes in instructions from here to the end? */
13328 i = fragp->fr_var - i;
13329 /* Convert to instruction count. */
13331 /* Don't decrement i, because we want to branch over the
13335 md_number_to_chars (buf, insn, 4);
13338 md_number_to_chars (buf, 0, 4);
13343 if (mips_pic == NO_PIC)
13346 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13347 ? 0x0c000000 : 0x08000000);
13348 exp.X_op = O_symbol;
13349 exp.X_add_symbol = fragp->fr_symbol;
13350 exp.X_add_number = fragp->fr_offset;
13352 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13353 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13354 fixp->fx_file = fragp->fr_file;
13355 fixp->fx_line = fragp->fr_line;
13357 md_number_to_chars (buf, insn, 4);
13362 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13363 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13364 exp.X_op = O_symbol;
13365 exp.X_add_symbol = fragp->fr_symbol;
13366 exp.X_add_number = fragp->fr_offset;
13368 if (fragp->fr_offset)
13370 exp.X_add_symbol = make_expr_symbol (&exp);
13371 exp.X_add_number = 0;
13374 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13375 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13376 fixp->fx_file = fragp->fr_file;
13377 fixp->fx_line = fragp->fr_line;
13379 md_number_to_chars (buf, insn, 4);
13382 if (mips_opts.isa == ISA_MIPS1)
13385 md_number_to_chars (buf, 0, 4);
13389 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13390 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13392 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13393 4, &exp, 0, BFD_RELOC_LO16);
13394 fixp->fx_file = fragp->fr_file;
13395 fixp->fx_line = fragp->fr_line;
13397 md_number_to_chars (buf, insn, 4);
13401 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13406 md_number_to_chars (buf, insn, 4);
13411 assert (buf == (bfd_byte *)fragp->fr_literal
13412 + fragp->fr_fix + fragp->fr_var);
13414 fragp->fr_fix += fragp->fr_var;
13419 if (RELAX_MIPS16_P (fragp->fr_subtype))
13422 register const struct mips16_immed_operand *op;
13423 bfd_boolean small, ext;
13426 unsigned long insn;
13427 bfd_boolean use_extend;
13428 unsigned short extend;
13430 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13431 op = mips16_immed_operands;
13432 while (op->type != type)
13435 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13446 resolve_symbol_value (fragp->fr_symbol);
13447 val = S_GET_VALUE (fragp->fr_symbol);
13452 addr = fragp->fr_address + fragp->fr_fix;
13454 /* The rules for the base address of a PC relative reloc are
13455 complicated; see mips16_extended_frag. */
13456 if (type == 'p' || type == 'q')
13461 /* Ignore the low bit in the target, since it will be
13462 set for a text label. */
13463 if ((val & 1) != 0)
13466 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13468 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13471 addr &= ~ (addressT) ((1 << op->shift) - 1);
13474 /* Make sure the section winds up with the alignment we have
13477 record_alignment (asec, op->shift);
13481 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13482 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13483 as_warn_where (fragp->fr_file, fragp->fr_line,
13484 _("extended instruction in delay slot"));
13486 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13488 if (target_big_endian)
13489 insn = bfd_getb16 (buf);
13491 insn = bfd_getl16 (buf);
13493 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13494 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13495 small, ext, &insn, &use_extend, &extend);
13499 md_number_to_chars (buf, 0xf000 | extend, 2);
13500 fragp->fr_fix += 2;
13504 md_number_to_chars (buf, insn, 2);
13505 fragp->fr_fix += 2;
13513 first = RELAX_FIRST (fragp->fr_subtype);
13514 second = RELAX_SECOND (fragp->fr_subtype);
13515 fixp = (fixS *) fragp->fr_opcode;
13517 /* Possibly emit a warning if we've chosen the longer option. */
13518 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13519 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13521 const char *msg = macro_warning (fragp->fr_subtype);
13523 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13526 /* Go through all the fixups for the first sequence. Disable them
13527 (by marking them as done) if we're going to use the second
13528 sequence instead. */
13530 && fixp->fx_frag == fragp
13531 && fixp->fx_where < fragp->fr_fix - second)
13533 if (fragp->fr_subtype & RELAX_USE_SECOND)
13535 fixp = fixp->fx_next;
13538 /* Go through the fixups for the second sequence. Disable them if
13539 we're going to use the first sequence, otherwise adjust their
13540 addresses to account for the relaxation. */
13541 while (fixp && fixp->fx_frag == fragp)
13543 if (fragp->fr_subtype & RELAX_USE_SECOND)
13544 fixp->fx_where -= first;
13547 fixp = fixp->fx_next;
13550 /* Now modify the frag contents. */
13551 if (fragp->fr_subtype & RELAX_USE_SECOND)
13555 start = fragp->fr_literal + fragp->fr_fix - first - second;
13556 memmove (start, start + first, second);
13557 fragp->fr_fix -= first;
13560 fragp->fr_fix -= second;
13566 /* This function is called after the relocs have been generated.
13567 We've been storing mips16 text labels as odd. Here we convert them
13568 back to even for the convenience of the debugger. */
13571 mips_frob_file_after_relocs (void)
13574 unsigned int count, i;
13576 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13579 syms = bfd_get_outsymbols (stdoutput);
13580 count = bfd_get_symcount (stdoutput);
13581 for (i = 0; i < count; i++, syms++)
13583 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13584 && ((*syms)->value & 1) != 0)
13586 (*syms)->value &= ~1;
13587 /* If the symbol has an odd size, it was probably computed
13588 incorrectly, so adjust that as well. */
13589 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13590 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13597 /* This function is called whenever a label is defined. It is used
13598 when handling branch delays; if a branch has a label, we assume we
13599 can not move it. */
13602 mips_define_label (symbolS *sym)
13604 struct insn_label_list *l;
13606 if (free_insn_labels == NULL)
13607 l = (struct insn_label_list *) xmalloc (sizeof *l);
13610 l = free_insn_labels;
13611 free_insn_labels = l->next;
13615 l->next = insn_labels;
13619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13621 /* Some special processing for a MIPS ELF file. */
13624 mips_elf_final_processing (void)
13626 /* Write out the register information. */
13627 if (mips_abi != N64_ABI)
13631 s.ri_gprmask = mips_gprmask;
13632 s.ri_cprmask[0] = mips_cprmask[0];
13633 s.ri_cprmask[1] = mips_cprmask[1];
13634 s.ri_cprmask[2] = mips_cprmask[2];
13635 s.ri_cprmask[3] = mips_cprmask[3];
13636 /* The gp_value field is set by the MIPS ELF backend. */
13638 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13639 ((Elf32_External_RegInfo *)
13640 mips_regmask_frag));
13644 Elf64_Internal_RegInfo s;
13646 s.ri_gprmask = mips_gprmask;
13648 s.ri_cprmask[0] = mips_cprmask[0];
13649 s.ri_cprmask[1] = mips_cprmask[1];
13650 s.ri_cprmask[2] = mips_cprmask[2];
13651 s.ri_cprmask[3] = mips_cprmask[3];
13652 /* The gp_value field is set by the MIPS ELF backend. */
13654 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13655 ((Elf64_External_RegInfo *)
13656 mips_regmask_frag));
13659 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13660 sort of BFD interface for this. */
13661 if (mips_any_noreorder)
13662 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13663 if (mips_pic != NO_PIC)
13665 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13666 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13669 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13671 /* Set MIPS ELF flags for ASEs. */
13672 if (file_ase_mips16)
13673 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13674 #if 0 /* XXX FIXME */
13675 if (file_ase_mips3d)
13676 elf_elfheader (stdoutput)->e_flags |= ???;
13679 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13681 /* Set the MIPS ELF ABI flags. */
13682 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13683 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13684 else if (mips_abi == O64_ABI)
13685 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13686 else if (mips_abi == EABI_ABI)
13688 if (!file_mips_gp32)
13689 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13691 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13693 else if (mips_abi == N32_ABI)
13694 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13696 /* Nothing to do for N64_ABI. */
13698 if (mips_32bitmode)
13699 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13702 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13704 typedef struct proc {
13706 unsigned long reg_mask;
13707 unsigned long reg_offset;
13708 unsigned long fpreg_mask;
13709 unsigned long fpreg_offset;
13710 unsigned long frame_offset;
13711 unsigned long frame_reg;
13712 unsigned long pc_reg;
13715 static procS cur_proc;
13716 static procS *cur_proc_ptr;
13717 static int numprocs;
13719 /* Fill in an rs_align_code fragment. */
13722 mips_handle_align (fragS *fragp)
13724 if (fragp->fr_type != rs_align_code)
13727 if (mips_opts.mips16)
13729 static const unsigned char be_nop[] = { 0x65, 0x00 };
13730 static const unsigned char le_nop[] = { 0x00, 0x65 };
13735 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13736 p = fragp->fr_literal + fragp->fr_fix;
13744 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13748 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13752 md_obj_begin (void)
13759 /* check for premature end, nesting errors, etc */
13761 as_warn (_("missing .end at end of assembly"));
13770 if (*input_line_pointer == '-')
13772 ++input_line_pointer;
13775 if (!ISDIGIT (*input_line_pointer))
13776 as_bad (_("expected simple number"));
13777 if (input_line_pointer[0] == '0')
13779 if (input_line_pointer[1] == 'x')
13781 input_line_pointer += 2;
13782 while (ISXDIGIT (*input_line_pointer))
13785 val |= hex_value (*input_line_pointer++);
13787 return negative ? -val : val;
13791 ++input_line_pointer;
13792 while (ISDIGIT (*input_line_pointer))
13795 val |= *input_line_pointer++ - '0';
13797 return negative ? -val : val;
13800 if (!ISDIGIT (*input_line_pointer))
13802 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13803 *input_line_pointer, *input_line_pointer);
13804 as_warn (_("invalid number"));
13807 while (ISDIGIT (*input_line_pointer))
13810 val += *input_line_pointer++ - '0';
13812 return negative ? -val : val;
13815 /* The .file directive; just like the usual .file directive, but there
13816 is an initial number which is the ECOFF file index. In the non-ECOFF
13817 case .file implies DWARF-2. */
13820 s_mips_file (int x ATTRIBUTE_UNUSED)
13822 static int first_file_directive = 0;
13824 if (ECOFF_DEBUGGING)
13833 filename = dwarf2_directive_file (0);
13835 /* Versions of GCC up to 3.1 start files with a ".file"
13836 directive even for stabs output. Make sure that this
13837 ".file" is handled. Note that you need a version of GCC
13838 after 3.1 in order to support DWARF-2 on MIPS. */
13839 if (filename != NULL && ! first_file_directive)
13841 (void) new_logical_line (filename, -1);
13842 s_app_file_string (filename);
13844 first_file_directive = 1;
13848 /* The .loc directive, implying DWARF-2. */
13851 s_mips_loc (int x ATTRIBUTE_UNUSED)
13853 if (!ECOFF_DEBUGGING)
13854 dwarf2_directive_loc (0);
13857 /* The .end directive. */
13860 s_mips_end (int x ATTRIBUTE_UNUSED)
13864 /* Following functions need their own .frame and .cprestore directives. */
13865 mips_frame_reg_valid = 0;
13866 mips_cprestore_valid = 0;
13868 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13871 demand_empty_rest_of_line ();
13876 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13877 as_warn (_(".end not in text section"));
13881 as_warn (_(".end directive without a preceding .ent directive."));
13882 demand_empty_rest_of_line ();
13888 assert (S_GET_NAME (p));
13889 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13890 as_warn (_(".end symbol does not match .ent symbol."));
13892 if (debug_type == DEBUG_STABS)
13893 stabs_generate_asm_endfunc (S_GET_NAME (p),
13897 as_warn (_(".end directive missing or unknown symbol"));
13900 /* Generate a .pdr section. */
13901 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13904 segT saved_seg = now_seg;
13905 subsegT saved_subseg = now_subseg;
13910 dot = frag_now_fix ();
13912 #ifdef md_flush_pending_output
13913 md_flush_pending_output ();
13917 subseg_set (pdr_seg, 0);
13919 /* Write the symbol. */
13920 exp.X_op = O_symbol;
13921 exp.X_add_symbol = p;
13922 exp.X_add_number = 0;
13923 emit_expr (&exp, 4);
13925 fragp = frag_more (7 * 4);
13927 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13928 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13929 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13930 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13931 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13932 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13933 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13935 subseg_set (saved_seg, saved_subseg);
13937 #endif /* OBJ_ELF */
13939 cur_proc_ptr = NULL;
13942 /* The .aent and .ent directives. */
13945 s_mips_ent (int aent)
13949 symbolP = get_symbol ();
13950 if (*input_line_pointer == ',')
13951 ++input_line_pointer;
13952 SKIP_WHITESPACE ();
13953 if (ISDIGIT (*input_line_pointer)
13954 || *input_line_pointer == '-')
13957 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13958 as_warn (_(".ent or .aent not in text section."));
13960 if (!aent && cur_proc_ptr)
13961 as_warn (_("missing .end"));
13965 /* This function needs its own .frame and .cprestore directives. */
13966 mips_frame_reg_valid = 0;
13967 mips_cprestore_valid = 0;
13969 cur_proc_ptr = &cur_proc;
13970 memset (cur_proc_ptr, '\0', sizeof (procS));
13972 cur_proc_ptr->isym = symbolP;
13974 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13978 if (debug_type == DEBUG_STABS)
13979 stabs_generate_asm_func (S_GET_NAME (symbolP),
13980 S_GET_NAME (symbolP));
13983 demand_empty_rest_of_line ();
13986 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13987 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13988 s_mips_frame is used so that we can set the PDR information correctly.
13989 We can't use the ecoff routines because they make reference to the ecoff
13990 symbol table (in the mdebug section). */
13993 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13996 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14000 if (cur_proc_ptr == (procS *) NULL)
14002 as_warn (_(".frame outside of .ent"));
14003 demand_empty_rest_of_line ();
14007 cur_proc_ptr->frame_reg = tc_get_register (1);
14009 SKIP_WHITESPACE ();
14010 if (*input_line_pointer++ != ','
14011 || get_absolute_expression_and_terminator (&val) != ',')
14013 as_warn (_("Bad .frame directive"));
14014 --input_line_pointer;
14015 demand_empty_rest_of_line ();
14019 cur_proc_ptr->frame_offset = val;
14020 cur_proc_ptr->pc_reg = tc_get_register (0);
14022 demand_empty_rest_of_line ();
14025 #endif /* OBJ_ELF */
14029 /* The .fmask and .mask directives. If the mdebug section is present
14030 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14031 embedded targets, s_mips_mask is used so that we can set the PDR
14032 information correctly. We can't use the ecoff routines because they
14033 make reference to the ecoff symbol table (in the mdebug section). */
14036 s_mips_mask (int reg_type)
14039 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14043 if (cur_proc_ptr == (procS *) NULL)
14045 as_warn (_(".mask/.fmask outside of .ent"));
14046 demand_empty_rest_of_line ();
14050 if (get_absolute_expression_and_terminator (&mask) != ',')
14052 as_warn (_("Bad .mask/.fmask directive"));
14053 --input_line_pointer;
14054 demand_empty_rest_of_line ();
14058 off = get_absolute_expression ();
14060 if (reg_type == 'F')
14062 cur_proc_ptr->fpreg_mask = mask;
14063 cur_proc_ptr->fpreg_offset = off;
14067 cur_proc_ptr->reg_mask = mask;
14068 cur_proc_ptr->reg_offset = off;
14071 demand_empty_rest_of_line ();
14074 #endif /* OBJ_ELF */
14075 s_ignore (reg_type);
14078 /* The .loc directive. */
14088 assert (now_seg == text_section);
14090 lineno = get_number ();
14091 addroff = frag_now_fix ();
14093 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14094 S_SET_TYPE (symbolP, N_SLINE);
14095 S_SET_OTHER (symbolP, 0);
14096 S_SET_DESC (symbolP, lineno);
14097 symbolP->sy_segment = now_seg;
14101 /* A table describing all the processors gas knows about. Names are
14102 matched in the order listed.
14104 To ease comparison, please keep this table in the same order as
14105 gcc's mips_cpu_info_table[]. */
14106 static const struct mips_cpu_info mips_cpu_info_table[] =
14108 /* Entries for generic ISAs */
14109 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14110 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14111 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14112 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14113 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14114 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14115 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14116 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14117 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14120 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14121 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14122 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14125 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14128 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14129 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14130 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14131 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14132 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14133 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14134 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14135 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14136 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14137 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14138 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14139 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14142 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14143 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14144 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14145 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14146 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14147 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14148 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14149 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14150 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14151 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14152 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14153 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14154 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14157 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14158 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14159 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14162 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14163 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14165 /* Broadcom SB-1 CPU core */
14166 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14173 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14174 with a final "000" replaced by "k". Ignore case.
14176 Note: this function is shared between GCC and GAS. */
14179 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14181 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14182 given++, canonical++;
14184 return ((*given == 0 && *canonical == 0)
14185 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14189 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14190 CPU name. We've traditionally allowed a lot of variation here.
14192 Note: this function is shared between GCC and GAS. */
14195 mips_matching_cpu_name_p (const char *canonical, const char *given)
14197 /* First see if the name matches exactly, or with a final "000"
14198 turned into "k". */
14199 if (mips_strict_matching_cpu_name_p (canonical, given))
14202 /* If not, try comparing based on numerical designation alone.
14203 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14204 if (TOLOWER (*given) == 'r')
14206 if (!ISDIGIT (*given))
14209 /* Skip over some well-known prefixes in the canonical name,
14210 hoping to find a number there too. */
14211 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14213 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14215 else if (TOLOWER (canonical[0]) == 'r')
14218 return mips_strict_matching_cpu_name_p (canonical, given);
14222 /* Parse an option that takes the name of a processor as its argument.
14223 OPTION is the name of the option and CPU_STRING is the argument.
14224 Return the corresponding processor enumeration if the CPU_STRING is
14225 recognized, otherwise report an error and return null.
14227 A similar function exists in GCC. */
14229 static const struct mips_cpu_info *
14230 mips_parse_cpu (const char *option, const char *cpu_string)
14232 const struct mips_cpu_info *p;
14234 /* 'from-abi' selects the most compatible architecture for the given
14235 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14236 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14237 version. Look first at the -mgp options, if given, otherwise base
14238 the choice on MIPS_DEFAULT_64BIT.
14240 Treat NO_ABI like the EABIs. One reason to do this is that the
14241 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14242 architecture. This code picks MIPS I for 'mips' and MIPS III for
14243 'mips64', just as we did in the days before 'from-abi'. */
14244 if (strcasecmp (cpu_string, "from-abi") == 0)
14246 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14247 return mips_cpu_info_from_isa (ISA_MIPS1);
14249 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14250 return mips_cpu_info_from_isa (ISA_MIPS3);
14252 if (file_mips_gp32 >= 0)
14253 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14255 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14260 /* 'default' has traditionally been a no-op. Probably not very useful. */
14261 if (strcasecmp (cpu_string, "default") == 0)
14264 for (p = mips_cpu_info_table; p->name != 0; p++)
14265 if (mips_matching_cpu_name_p (p->name, cpu_string))
14268 as_bad ("Bad value (%s) for %s", cpu_string, option);
14272 /* Return the canonical processor information for ISA (a member of the
14273 ISA_MIPS* enumeration). */
14275 static const struct mips_cpu_info *
14276 mips_cpu_info_from_isa (int isa)
14280 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14281 if (mips_cpu_info_table[i].is_isa
14282 && isa == mips_cpu_info_table[i].isa)
14283 return (&mips_cpu_info_table[i]);
14288 static const struct mips_cpu_info *
14289 mips_cpu_info_from_arch (int arch)
14293 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14294 if (arch == mips_cpu_info_table[i].cpu)
14295 return (&mips_cpu_info_table[i]);
14301 show (FILE *stream, const char *string, int *col_p, int *first_p)
14305 fprintf (stream, "%24s", "");
14310 fprintf (stream, ", ");
14314 if (*col_p + strlen (string) > 72)
14316 fprintf (stream, "\n%24s", "");
14320 fprintf (stream, "%s", string);
14321 *col_p += strlen (string);
14327 md_show_usage (FILE *stream)
14332 fprintf (stream, _("\
14334 -membedded-pic generate embedded position independent code\n\
14335 -EB generate big endian output\n\
14336 -EL generate little endian output\n\
14337 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14338 -G NUM allow referencing objects up to NUM bytes\n\
14339 implicitly with the gp register [default 8]\n"));
14340 fprintf (stream, _("\
14341 -mips1 generate MIPS ISA I instructions\n\
14342 -mips2 generate MIPS ISA II instructions\n\
14343 -mips3 generate MIPS ISA III instructions\n\
14344 -mips4 generate MIPS ISA IV instructions\n\
14345 -mips5 generate MIPS ISA V instructions\n\
14346 -mips32 generate MIPS32 ISA instructions\n\
14347 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14348 -mips64 generate MIPS64 ISA instructions\n\
14349 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14350 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14354 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14355 show (stream, mips_cpu_info_table[i].name, &column, &first);
14356 show (stream, "from-abi", &column, &first);
14357 fputc ('\n', stream);
14359 fprintf (stream, _("\
14360 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14361 -no-mCPU don't generate code specific to CPU.\n\
14362 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14366 show (stream, "3900", &column, &first);
14367 show (stream, "4010", &column, &first);
14368 show (stream, "4100", &column, &first);
14369 show (stream, "4650", &column, &first);
14370 fputc ('\n', stream);
14372 fprintf (stream, _("\
14373 -mips16 generate mips16 instructions\n\
14374 -no-mips16 do not generate mips16 instructions\n"));
14375 fprintf (stream, _("\
14376 -mfix-vr4120 work around certain VR4120 errata\n\
14377 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14378 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14379 -O0 remove unneeded NOPs, do not swap branches\n\
14380 -O remove unneeded NOPs and swap branches\n\
14381 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14382 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14383 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14385 fprintf (stream, _("\
14386 -KPIC, -call_shared generate SVR4 position independent code\n\
14387 -non_shared do not generate position independent code\n\
14388 -xgot assume a 32 bit GOT\n\
14389 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14390 -mabi=ABI create ABI conformant object file for:\n"));
14394 show (stream, "32", &column, &first);
14395 show (stream, "o64", &column, &first);
14396 show (stream, "n32", &column, &first);
14397 show (stream, "64", &column, &first);
14398 show (stream, "eabi", &column, &first);
14400 fputc ('\n', stream);
14402 fprintf (stream, _("\
14403 -32 create o32 ABI object file (default)\n\
14404 -n32 create n32 ABI object file\n\
14405 -64 create 64 ABI object file\n"));
14410 mips_dwarf2_format (void)
14412 if (mips_abi == N64_ABI)
14415 return dwarf2_format_64bit_irix;
14417 return dwarf2_format_64bit;
14421 return dwarf2_format_32bit;
14425 mips_dwarf2_addr_size (void)
14427 if (mips_abi == N64_ABI)