1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi = NO_ABI;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls = FALSE;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared = TRUE;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32 = -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32 = -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float = 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float = 0;
266 static struct mips_set_options mips_opts =
268 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
273 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask;
280 unsigned long mips_cprmask[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa = ISA_UNKNOWN;
285 /* True if -mips16 was passed or implied by arguments passed on the
286 command line (e.g., by -march). */
287 static int file_ase_mips16;
289 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
290 || mips_opts.isa == ISA_MIPS32R2 \
291 || mips_opts.isa == ISA_MIPS64 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* True if we want to create R_MIPS_JALR for jalr $25. */
296 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
298 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
299 because there's no place for any addend, the only acceptable
300 expression is a bare symbol. */
301 #define MIPS_JALR_HINT_P(EXPR) \
302 (!HAVE_IN_PLACE_ADDENDS \
303 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
306 /* True if -mips3d was passed or implied by arguments passed on the
307 command line (e.g., by -march). */
308 static int file_ase_mips3d;
310 /* True if -mdmx was passed or implied by arguments passed on the
311 command line (e.g., by -march). */
312 static int file_ase_mdmx;
314 /* True if -msmartmips was passed or implied by arguments passed on the
315 command line (e.g., by -march). */
316 static int file_ase_smartmips;
318 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
319 || mips_opts.isa == ISA_MIPS32R2)
321 /* True if -mdsp was passed or implied by arguments passed on the
322 command line (e.g., by -march). */
323 static int file_ase_dsp;
325 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
326 || mips_opts.isa == ISA_MIPS64R2)
328 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
330 /* True if -mdspr2 was passed or implied by arguments passed on the
331 command line (e.g., by -march). */
332 static int file_ase_dspr2;
334 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
335 || mips_opts.isa == ISA_MIPS64R2)
337 /* True if -mmt was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mt;
341 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64R2)
344 /* The argument of the -march= flag. The architecture we are assembling. */
345 static int file_mips_arch = CPU_UNKNOWN;
346 static const char *mips_arch_string;
348 /* The argument of the -mtune= flag. The architecture for which we
350 static int mips_tune = CPU_UNKNOWN;
351 static const char *mips_tune_string;
353 /* True when generating 32-bit code for a 64-bit processor. */
354 static int mips_32bitmode = 0;
356 /* True if the given ABI requires 32-bit registers. */
357 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
359 /* Likewise 64-bit registers. */
360 #define ABI_NEEDS_64BIT_REGS(ABI) \
362 || (ABI) == N64_ABI \
365 /* Return true if ISA supports 64 bit wide gp registers. */
366 #define ISA_HAS_64BIT_REGS(ISA) \
367 ((ISA) == ISA_MIPS3 \
368 || (ISA) == ISA_MIPS4 \
369 || (ISA) == ISA_MIPS5 \
370 || (ISA) == ISA_MIPS64 \
371 || (ISA) == ISA_MIPS64R2)
373 /* Return true if ISA supports 64 bit wide float registers. */
374 #define ISA_HAS_64BIT_FPRS(ISA) \
375 ((ISA) == ISA_MIPS3 \
376 || (ISA) == ISA_MIPS4 \
377 || (ISA) == ISA_MIPS5 \
378 || (ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2)
382 /* Return true if ISA supports 64-bit right rotate (dror et al.)
384 #define ISA_HAS_DROR(ISA) \
385 ((ISA) == ISA_MIPS64R2)
387 /* Return true if ISA supports 32-bit right rotate (ror et al.)
389 #define ISA_HAS_ROR(ISA) \
390 ((ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS64R2 \
392 || mips_opts.ase_smartmips)
394 /* Return true if ISA supports single-precision floats in odd registers. */
395 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
396 ((ISA) == ISA_MIPS32 \
397 || (ISA) == ISA_MIPS32R2 \
398 || (ISA) == ISA_MIPS64 \
399 || (ISA) == ISA_MIPS64R2)
401 /* Return true if ISA supports move to/from high part of a 64-bit
402 floating-point register. */
403 #define ISA_HAS_MXHC1(ISA) \
404 ((ISA) == ISA_MIPS32R2 \
405 || (ISA) == ISA_MIPS64R2)
407 #define HAVE_32BIT_GPRS \
408 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
410 #define HAVE_32BIT_FPRS \
411 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
413 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
414 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
416 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
418 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
420 /* True if relocations are stored in-place. */
421 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
423 /* The ABI-derived address size. */
424 #define HAVE_64BIT_ADDRESSES \
425 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
426 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
428 /* The size of symbolic constants (i.e., expressions of the form
429 "SYMBOL" or "SYMBOL + OFFSET"). */
430 #define HAVE_32BIT_SYMBOLS \
431 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
432 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
434 /* Addresses are loaded in different ways, depending on the address size
435 in use. The n32 ABI Documentation also mandates the use of additions
436 with overflow checking, but existing implementations don't follow it. */
437 #define ADDRESS_ADD_INSN \
438 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
440 #define ADDRESS_ADDI_INSN \
441 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
443 #define ADDRESS_LOAD_INSN \
444 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
446 #define ADDRESS_STORE_INSN \
447 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
449 /* Return true if the given CPU supports the MIPS16 ASE. */
450 #define CPU_HAS_MIPS16(cpu) \
451 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
452 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
454 /* True if CPU has a dror instruction. */
455 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
457 /* True if CPU has a ror instruction. */
458 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
460 /* True if CPU has seq/sne and seqi/snei instructions. */
461 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
463 /* True if CPU does not implement the all the coprocessor insns. For these
464 CPUs only those COP insns are accepted that are explicitly marked to be
465 available on the CPU. ISA membership for COP insns is ignored. */
466 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
468 /* True if mflo and mfhi can be immediately followed by instructions
469 which write to the HI and LO registers.
471 According to MIPS specifications, MIPS ISAs I, II, and III need
472 (at least) two instructions between the reads of HI/LO and
473 instructions which write them, and later ISAs do not. Contradicting
474 the MIPS specifications, some MIPS IV processor user manuals (e.g.
475 the UM for the NEC Vr5000) document needing the instructions between
476 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
477 MIPS64 and later ISAs to have the interlocks, plus any specific
478 earlier-ISA CPUs for which CPU documentation declares that the
479 instructions are really interlocked. */
480 #define hilo_interlocks \
481 (mips_opts.isa == ISA_MIPS32 \
482 || mips_opts.isa == ISA_MIPS32R2 \
483 || mips_opts.isa == ISA_MIPS64 \
484 || mips_opts.isa == ISA_MIPS64R2 \
485 || mips_opts.arch == CPU_R4010 \
486 || mips_opts.arch == CPU_R10000 \
487 || mips_opts.arch == CPU_R12000 \
488 || mips_opts.arch == CPU_R14000 \
489 || mips_opts.arch == CPU_R16000 \
490 || mips_opts.arch == CPU_RM7000 \
491 || mips_opts.arch == CPU_VR5500 \
494 /* Whether the processor uses hardware interlocks to protect reads
495 from the GPRs after they are loaded from memory, and thus does not
496 require nops to be inserted. This applies to instructions marked
497 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
499 #define gpr_interlocks \
500 (mips_opts.isa != ISA_MIPS1 \
501 || mips_opts.arch == CPU_R3900)
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III. */
510 /* Itbl support may require additional care here. */
511 #define cop_interlocks \
512 ((mips_opts.isa != ISA_MIPS1 \
513 && mips_opts.isa != ISA_MIPS2 \
514 && mips_opts.isa != ISA_MIPS3) \
515 || mips_opts.arch == CPU_R4300 \
518 /* Whether the processor uses hardware interlocks to protect reads
519 from coprocessor registers after they are loaded from memory, and
520 thus does not require nops to be inserted. This applies to
521 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
522 requires at MIPS ISA level I. */
523 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Returns true for a (non floating-point) coprocessor instruction. Reading
530 or writing the condition code is only possible on the coprocessors and
531 these insns are not marked with INSN_COP. Thus for these insns use the
532 condition-code flags. */
533 #define COP_INSN(PINFO) \
534 (PINFO != INSN_MACRO \
535 && ((PINFO) & (FP_S | FP_D)) == 0 \
536 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
538 /* MIPS PIC level. */
540 enum mips_pic_level mips_pic;
542 /* 1 if we should generate 32 bit offsets from the $gp register in
543 SVR4_PIC mode. Currently has no meaning in other modes. */
544 static int mips_big_got = 0;
546 /* 1 if trap instructions should used for overflow rather than break
548 static int mips_trap = 0;
550 /* 1 if double width floating point constants should not be constructed
551 by assembling two single width halves into two single width floating
552 point registers which just happen to alias the double width destination
553 register. On some architectures this aliasing can be disabled by a bit
554 in the status register, and the setting of this bit cannot be determined
555 automatically at assemble time. */
556 static int mips_disable_float_construction;
558 /* Non-zero if any .set noreorder directives were used. */
560 static int mips_any_noreorder;
562 /* Non-zero if nops should be inserted when the register referenced in
563 an mfhi/mflo instruction is read in the next two instructions. */
564 static int mips_7000_hilo_fix;
566 /* The size of objects in the small data section. */
567 static unsigned int g_switch_value = 8;
568 /* Whether the -G option was used. */
569 static int g_switch_seen = 0;
574 /* If we can determine in advance that GP optimization won't be
575 possible, we can skip the relaxation stuff that tries to produce
576 GP-relative references. This makes delay slot optimization work
579 This function can only provide a guess, but it seems to work for
580 gcc output. It needs to guess right for gcc, otherwise gcc
581 will put what it thinks is a GP-relative instruction in a branch
584 I don't know if a fix is needed for the SVR4_PIC mode. I've only
585 fixed it for the non-PIC mode. KR 95/04/07 */
586 static int nopic_need_relax (symbolS *, int);
588 /* handle of the OPCODE hash table */
589 static struct hash_control *op_hash = NULL;
591 /* The opcode hash table we use for the mips16. */
592 static struct hash_control *mips16_op_hash = NULL;
594 /* This array holds the chars that always start a comment. If the
595 pre-processor is disabled, these aren't very useful */
596 const char comment_chars[] = "#";
598 /* This array holds the chars that only start a comment at the beginning of
599 a line. If the line seems to have the form '# 123 filename'
600 .line and .file directives will appear in the pre-processed output */
601 /* Note that input_file.c hand checks for '#' at the beginning of the
602 first line of the input file. This is because the compiler outputs
603 #NO_APP at the beginning of its output. */
604 /* Also note that C style comments are always supported. */
605 const char line_comment_chars[] = "#";
607 /* This array holds machine specific line separator characters. */
608 const char line_separator_chars[] = ";";
610 /* Chars that can be used to separate mant from exp in floating point nums */
611 const char EXP_CHARS[] = "eE";
613 /* Chars that mean this number is a floating point constant */
616 const char FLT_CHARS[] = "rRsSfFdDxXpP";
618 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
619 changed in read.c . Ideally it shouldn't have to know about it at all,
620 but nothing is ideal around here.
623 static char *insn_error;
625 static int auto_align = 1;
627 /* When outputting SVR4 PIC code, the assembler needs to know the
628 offset in the stack frame from which to restore the $gp register.
629 This is set by the .cprestore pseudo-op, and saved in this
631 static offsetT mips_cprestore_offset = -1;
633 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
634 more optimizations, it can use a register value instead of a memory-saved
635 offset and even an other register than $gp as global pointer. */
636 static offsetT mips_cpreturn_offset = -1;
637 static int mips_cpreturn_register = -1;
638 static int mips_gp_register = GP;
639 static int mips_gprel_offset = 0;
641 /* Whether mips_cprestore_offset has been set in the current function
642 (or whether it has already been warned about, if not). */
643 static int mips_cprestore_valid = 0;
645 /* This is the register which holds the stack frame, as set by the
646 .frame pseudo-op. This is needed to implement .cprestore. */
647 static int mips_frame_reg = SP;
649 /* Whether mips_frame_reg has been set in the current function
650 (or whether it has already been warned about, if not). */
651 static int mips_frame_reg_valid = 0;
653 /* To output NOP instructions correctly, we need to keep information
654 about the previous two instructions. */
656 /* Whether we are optimizing. The default value of 2 means to remove
657 unneeded NOPs and swap branch instructions when possible. A value
658 of 1 means to not swap branches. A value of 0 means to always
660 static int mips_optimize = 2;
662 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
663 equivalent to seeing no -g option at all. */
664 static int mips_debug = 0;
666 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
667 #define MAX_VR4130_NOPS 4
669 /* The maximum number of NOPs needed to fill delay slots. */
670 #define MAX_DELAY_NOPS 2
672 /* The maximum number of NOPs needed for any purpose. */
675 /* A list of previous instructions, with index 0 being the most recent.
676 We need to look back MAX_NOPS instructions when filling delay slots
677 or working around processor errata. We need to look back one
678 instruction further if we're thinking about using history[0] to
679 fill a branch delay slot. */
680 static struct mips_cl_insn history[1 + MAX_NOPS];
682 /* Nop instructions used by emit_nop. */
683 static struct mips_cl_insn nop_insn, mips16_nop_insn;
685 /* The appropriate nop for the current mode. */
686 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
688 /* If this is set, it points to a frag holding nop instructions which
689 were inserted before the start of a noreorder section. If those
690 nops turn out to be unnecessary, the size of the frag can be
692 static fragS *prev_nop_frag;
694 /* The number of nop instructions we created in prev_nop_frag. */
695 static int prev_nop_frag_holds;
697 /* The number of nop instructions that we know we need in
699 static int prev_nop_frag_required;
701 /* The number of instructions we've seen since prev_nop_frag. */
702 static int prev_nop_frag_since;
704 /* For ECOFF and ELF, relocations against symbols are done in two
705 parts, with a HI relocation and a LO relocation. Each relocation
706 has only 16 bits of space to store an addend. This means that in
707 order for the linker to handle carries correctly, it must be able
708 to locate both the HI and the LO relocation. This means that the
709 relocations must appear in order in the relocation table.
711 In order to implement this, we keep track of each unmatched HI
712 relocation. We then sort them so that they immediately precede the
713 corresponding LO relocation. */
718 struct mips_hi_fixup *next;
721 /* The section this fixup is in. */
725 /* The list of unmatched HI relocs. */
727 static struct mips_hi_fixup *mips_hi_fixup_list;
729 /* The frag containing the last explicit relocation operator.
730 Null if explicit relocations have not been used. */
732 static fragS *prev_reloc_op_frag;
734 /* Map normal MIPS register numbers to mips16 register numbers. */
736 #define X ILLEGAL_REG
737 static const int mips32_to_16_reg_map[] =
739 X, X, 2, 3, 4, 5, 6, 7,
740 X, X, X, X, X, X, X, X,
741 0, 1, X, X, X, X, X, X,
742 X, X, X, X, X, X, X, X
746 /* Map mips16 register numbers to normal MIPS register numbers. */
748 static const unsigned int mips16_to_32_reg_map[] =
750 16, 17, 2, 3, 4, 5, 6, 7
753 /* Classifies the kind of instructions we're interested in when
754 implementing -mfix-vr4120. */
755 enum fix_vr4120_class
763 NUM_FIX_VR4120_CLASSES
766 /* ...likewise -mfix-loongson2f-jump. */
767 static bfd_boolean mips_fix_loongson2f_jump;
769 /* ...likewise -mfix-loongson2f-nop. */
770 static bfd_boolean mips_fix_loongson2f_nop;
772 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
773 static bfd_boolean mips_fix_loongson2f;
775 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
776 there must be at least one other instruction between an instruction
777 of type X and an instruction of type Y. */
778 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
780 /* True if -mfix-vr4120 is in force. */
781 static int mips_fix_vr4120;
783 /* ...likewise -mfix-vr4130. */
784 static int mips_fix_vr4130;
786 /* ...likewise -mfix-24k. */
787 static int mips_fix_24k;
789 /* We don't relax branches by default, since this causes us to expand
790 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
791 fail to compute the offset before expanding the macro to the most
792 efficient expansion. */
794 static int mips_relax_branch;
796 /* The expansion of many macros depends on the type of symbol that
797 they refer to. For example, when generating position-dependent code,
798 a macro that refers to a symbol may have two different expansions,
799 one which uses GP-relative addresses and one which uses absolute
800 addresses. When generating SVR4-style PIC, a macro may have
801 different expansions for local and global symbols.
803 We handle these situations by generating both sequences and putting
804 them in variant frags. In position-dependent code, the first sequence
805 will be the GP-relative one and the second sequence will be the
806 absolute one. In SVR4 PIC, the first sequence will be for global
807 symbols and the second will be for local symbols.
809 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
810 SECOND are the lengths of the two sequences in bytes. These fields
811 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
812 the subtype has the following flags:
815 Set if it has been decided that we should use the second
816 sequence instead of the first.
819 Set in the first variant frag if the macro's second implementation
820 is longer than its first. This refers to the macro as a whole,
821 not an individual relaxation.
824 Set in the first variant frag if the macro appeared in a .set nomacro
825 block and if one alternative requires a warning but the other does not.
828 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
831 The frag's "opcode" points to the first fixup for relaxable code.
833 Relaxable macros are generated using a sequence such as:
835 relax_start (SYMBOL);
836 ... generate first expansion ...
838 ... generate second expansion ...
841 The code and fixups for the unwanted alternative are discarded
842 by md_convert_frag. */
843 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
845 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
846 #define RELAX_SECOND(X) ((X) & 0xff)
847 #define RELAX_USE_SECOND 0x10000
848 #define RELAX_SECOND_LONGER 0x20000
849 #define RELAX_NOMACRO 0x40000
850 #define RELAX_DELAY_SLOT 0x80000
852 /* Branch without likely bit. If label is out of range, we turn:
854 beq reg1, reg2, label
864 with the following opcode replacements:
871 bltzal <-> bgezal (with jal label instead of j label)
873 Even though keeping the delay slot instruction in the delay slot of
874 the branch would be more efficient, it would be very tricky to do
875 correctly, because we'd have to introduce a variable frag *after*
876 the delay slot instruction, and expand that instead. Let's do it
877 the easy way for now, even if the branch-not-taken case now costs
878 one additional instruction. Out-of-range branches are not supposed
879 to be common, anyway.
881 Branch likely. If label is out of range, we turn:
883 beql reg1, reg2, label
884 delay slot (annulled if branch not taken)
893 delay slot (executed only if branch taken)
896 It would be possible to generate a shorter sequence by losing the
897 likely bit, generating something like:
902 delay slot (executed only if branch taken)
914 bltzall -> bgezal (with jal label instead of j label)
915 bgezall -> bltzal (ditto)
918 but it's not clear that it would actually improve performance. */
919 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
922 | ((toofar) ? 1 : 0) \
924 | ((likely) ? 4 : 0) \
925 | ((uncond) ? 8 : 0)))
926 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
927 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
928 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
929 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
930 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
932 /* For mips16 code, we use an entirely different form of relaxation.
933 mips16 supports two versions of most instructions which take
934 immediate values: a small one which takes some small value, and a
935 larger one which takes a 16 bit value. Since branches also follow
936 this pattern, relaxing these values is required.
938 We can assemble both mips16 and normal MIPS code in a single
939 object. Therefore, we need to support this type of relaxation at
940 the same time that we support the relaxation described above. We
941 use the high bit of the subtype field to distinguish these cases.
943 The information we store for this type of relaxation is the
944 argument code found in the opcode file for this relocation, whether
945 the user explicitly requested a small or extended form, and whether
946 the relocation is in a jump or jal delay slot. That tells us the
947 size of the value, and how it should be stored. We also store
948 whether the fragment is considered to be extended or not. We also
949 store whether this is known to be a branch to a different section,
950 whether we have tried to relax this frag yet, and whether we have
951 ever extended a PC relative fragment because of a shift count. */
952 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
955 | ((small) ? 0x100 : 0) \
956 | ((ext) ? 0x200 : 0) \
957 | ((dslot) ? 0x400 : 0) \
958 | ((jal_dslot) ? 0x800 : 0))
959 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
960 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
961 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
962 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
963 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
964 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
965 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
966 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
967 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
968 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
969 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
970 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
972 /* Is the given value a sign-extended 32-bit value? */
973 #define IS_SEXT_32BIT_NUM(x) \
974 (((x) &~ (offsetT) 0x7fffffff) == 0 \
975 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
977 /* Is the given value a sign-extended 16-bit value? */
978 #define IS_SEXT_16BIT_NUM(x) \
979 (((x) &~ (offsetT) 0x7fff) == 0 \
980 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
982 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
983 #define IS_ZEXT_32BIT_NUM(x) \
984 (((x) &~ (offsetT) 0xffffffff) == 0 \
985 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
987 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
988 VALUE << SHIFT. VALUE is evaluated exactly once. */
989 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
990 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
991 | (((VALUE) & (MASK)) << (SHIFT)))
993 /* Extract bits MASK << SHIFT from STRUCT and shift them right
995 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
996 (((STRUCT) >> (SHIFT)) & (MASK))
998 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
999 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1001 include/opcode/mips.h specifies operand fields using the macros
1002 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1003 with "MIPS16OP" instead of "OP". */
1004 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1005 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1006 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1007 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1008 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1010 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1011 #define EXTRACT_OPERAND(FIELD, INSN) \
1012 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1014 EXTRACT_BITS ((INSN).insn_opcode, \
1015 MIPS16OP_MASK_##FIELD, \
1016 MIPS16OP_SH_##FIELD)
1018 /* Global variables used when generating relaxable macros. See the
1019 comment above RELAX_ENCODE for more details about how relaxation
1022 /* 0 if we're not emitting a relaxable macro.
1023 1 if we're emitting the first of the two relaxation alternatives.
1024 2 if we're emitting the second alternative. */
1027 /* The first relaxable fixup in the current frag. (In other words,
1028 the first fixup that refers to relaxable code.) */
1031 /* sizes[0] says how many bytes of the first alternative are stored in
1032 the current frag. Likewise sizes[1] for the second alternative. */
1033 unsigned int sizes[2];
1035 /* The symbol on which the choice of sequence depends. */
1039 /* Global variables used to decide whether a macro needs a warning. */
1041 /* True if the macro is in a branch delay slot. */
1042 bfd_boolean delay_slot_p;
1044 /* For relaxable macros, sizes[0] is the length of the first alternative
1045 in bytes and sizes[1] is the length of the second alternative.
1046 For non-relaxable macros, both elements give the length of the
1048 unsigned int sizes[2];
1050 /* The first variant frag for this macro. */
1052 } mips_macro_warning;
1054 /* Prototypes for static functions. */
1056 #define internalError() \
1057 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1059 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1061 static void append_insn
1062 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1063 static void mips_no_prev_insn (void);
1064 static void macro_build (expressionS *, const char *, const char *, ...);
1065 static void mips16_macro_build
1066 (expressionS *, const char *, const char *, va_list *);
1067 static void load_register (int, expressionS *, int);
1068 static void macro_start (void);
1069 static void macro_end (void);
1070 static void macro (struct mips_cl_insn * ip);
1071 static void mips16_macro (struct mips_cl_insn * ip);
1072 #ifdef LOSING_COMPILER
1073 static void macro2 (struct mips_cl_insn * ip);
1075 static void mips_ip (char *str, struct mips_cl_insn * ip);
1076 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1077 static void mips16_immed
1078 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1079 unsigned long *, bfd_boolean *, unsigned short *);
1080 static size_t my_getSmallExpression
1081 (expressionS *, bfd_reloc_code_real_type *, char *);
1082 static void my_getExpression (expressionS *, char *);
1083 static void s_align (int);
1084 static void s_change_sec (int);
1085 static void s_change_section (int);
1086 static void s_cons (int);
1087 static void s_float_cons (int);
1088 static void s_mips_globl (int);
1089 static void s_option (int);
1090 static void s_mipsset (int);
1091 static void s_abicalls (int);
1092 static void s_cpload (int);
1093 static void s_cpsetup (int);
1094 static void s_cplocal (int);
1095 static void s_cprestore (int);
1096 static void s_cpreturn (int);
1097 static void s_dtprelword (int);
1098 static void s_dtpreldword (int);
1099 static void s_gpvalue (int);
1100 static void s_gpword (int);
1101 static void s_gpdword (int);
1102 static void s_cpadd (int);
1103 static void s_insn (int);
1104 static void md_obj_begin (void);
1105 static void md_obj_end (void);
1106 static void s_mips_ent (int);
1107 static void s_mips_end (int);
1108 static void s_mips_frame (int);
1109 static void s_mips_mask (int reg_type);
1110 static void s_mips_stab (int);
1111 static void s_mips_weakext (int);
1112 static void s_mips_file (int);
1113 static void s_mips_loc (int);
1114 static bfd_boolean pic_need_relax (symbolS *, asection *);
1115 static int relaxed_branch_length (fragS *, asection *, int);
1116 static int validate_mips_insn (const struct mips_opcode *);
1118 /* Table and functions used to map between CPU/ISA names, and
1119 ISA levels, and CPU numbers. */
1121 struct mips_cpu_info
1123 const char *name; /* CPU or ISA name. */
1124 int flags; /* ASEs available, or ISA flag. */
1125 int isa; /* ISA level. */
1126 int cpu; /* CPU number (default CPU if ISA). */
1129 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1130 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1131 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1132 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1133 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1134 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1135 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1137 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1138 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1139 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1143 The following pseudo-ops from the Kane and Heinrich MIPS book
1144 should be defined here, but are currently unsupported: .alias,
1145 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1147 The following pseudo-ops from the Kane and Heinrich MIPS book are
1148 specific to the type of debugging information being generated, and
1149 should be defined by the object format: .aent, .begin, .bend,
1150 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1153 The following pseudo-ops from the Kane and Heinrich MIPS book are
1154 not MIPS CPU specific, but are also not specific to the object file
1155 format. This file is probably the best place to define them, but
1156 they are not currently supported: .asm0, .endr, .lab, .struct. */
1158 static const pseudo_typeS mips_pseudo_table[] =
1160 /* MIPS specific pseudo-ops. */
1161 {"option", s_option, 0},
1162 {"set", s_mipsset, 0},
1163 {"rdata", s_change_sec, 'r'},
1164 {"sdata", s_change_sec, 's'},
1165 {"livereg", s_ignore, 0},
1166 {"abicalls", s_abicalls, 0},
1167 {"cpload", s_cpload, 0},
1168 {"cpsetup", s_cpsetup, 0},
1169 {"cplocal", s_cplocal, 0},
1170 {"cprestore", s_cprestore, 0},
1171 {"cpreturn", s_cpreturn, 0},
1172 {"dtprelword", s_dtprelword, 0},
1173 {"dtpreldword", s_dtpreldword, 0},
1174 {"gpvalue", s_gpvalue, 0},
1175 {"gpword", s_gpword, 0},
1176 {"gpdword", s_gpdword, 0},
1177 {"cpadd", s_cpadd, 0},
1178 {"insn", s_insn, 0},
1180 /* Relatively generic pseudo-ops that happen to be used on MIPS
1182 {"asciiz", stringer, 8 + 1},
1183 {"bss", s_change_sec, 'b'},
1185 {"half", s_cons, 1},
1186 {"dword", s_cons, 3},
1187 {"weakext", s_mips_weakext, 0},
1188 {"origin", s_org, 0},
1189 {"repeat", s_rept, 0},
1191 /* These pseudo-ops are defined in read.c, but must be overridden
1192 here for one reason or another. */
1193 {"align", s_align, 0},
1194 {"byte", s_cons, 0},
1195 {"data", s_change_sec, 'd'},
1196 {"double", s_float_cons, 'd'},
1197 {"float", s_float_cons, 'f'},
1198 {"globl", s_mips_globl, 0},
1199 {"global", s_mips_globl, 0},
1200 {"hword", s_cons, 1},
1202 {"long", s_cons, 2},
1203 {"octa", s_cons, 4},
1204 {"quad", s_cons, 3},
1205 {"section", s_change_section, 0},
1206 {"short", s_cons, 1},
1207 {"single", s_float_cons, 'f'},
1208 {"stabn", s_mips_stab, 'n'},
1209 {"text", s_change_sec, 't'},
1210 {"word", s_cons, 2},
1212 { "extern", ecoff_directive_extern, 0},
1217 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1219 /* These pseudo-ops should be defined by the object file format.
1220 However, a.out doesn't support them, so we have versions here. */
1221 {"aent", s_mips_ent, 1},
1222 {"bgnb", s_ignore, 0},
1223 {"end", s_mips_end, 0},
1224 {"endb", s_ignore, 0},
1225 {"ent", s_mips_ent, 0},
1226 {"file", s_mips_file, 0},
1227 {"fmask", s_mips_mask, 'F'},
1228 {"frame", s_mips_frame, 0},
1229 {"loc", s_mips_loc, 0},
1230 {"mask", s_mips_mask, 'R'},
1231 {"verstamp", s_ignore, 0},
1235 extern void pop_insert (const pseudo_typeS *);
1238 mips_pop_insert (void)
1240 pop_insert (mips_pseudo_table);
1241 if (! ECOFF_DEBUGGING)
1242 pop_insert (mips_nonecoff_pseudo_table);
1245 /* Symbols labelling the current insn. */
1247 struct insn_label_list
1249 struct insn_label_list *next;
1253 static struct insn_label_list *free_insn_labels;
1254 #define label_list tc_segment_info_data.labels
1256 static void mips_clear_insn_labels (void);
1259 mips_clear_insn_labels (void)
1261 register struct insn_label_list **pl;
1262 segment_info_type *si;
1266 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1269 si = seg_info (now_seg);
1270 *pl = si->label_list;
1271 si->label_list = NULL;
1276 static char *expr_end;
1278 /* Expressions which appear in instructions. These are set by
1281 static expressionS imm_expr;
1282 static expressionS imm2_expr;
1283 static expressionS offset_expr;
1285 /* Relocs associated with imm_expr and offset_expr. */
1287 static bfd_reloc_code_real_type imm_reloc[3]
1288 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1289 static bfd_reloc_code_real_type offset_reloc[3]
1290 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1292 /* These are set by mips16_ip if an explicit extension is used. */
1294 static bfd_boolean mips16_small, mips16_ext;
1297 /* The pdr segment for per procedure frame/regmask info. Not used for
1300 static segT pdr_seg;
1303 /* The default target format to use. */
1306 mips_target_format (void)
1308 switch (OUTPUT_FLAVOR)
1310 case bfd_target_ecoff_flavour:
1311 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1312 case bfd_target_coff_flavour:
1314 case bfd_target_elf_flavour:
1316 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1317 return (target_big_endian
1318 ? "elf32-bigmips-vxworks"
1319 : "elf32-littlemips-vxworks");
1322 /* This is traditional mips. */
1323 return (target_big_endian
1324 ? (HAVE_64BIT_OBJECTS
1325 ? "elf64-tradbigmips"
1327 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1328 : (HAVE_64BIT_OBJECTS
1329 ? "elf64-tradlittlemips"
1331 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1333 return (target_big_endian
1334 ? (HAVE_64BIT_OBJECTS
1337 ? "elf32-nbigmips" : "elf32-bigmips"))
1338 : (HAVE_64BIT_OBJECTS
1339 ? "elf64-littlemips"
1341 ? "elf32-nlittlemips" : "elf32-littlemips")));
1349 /* Return the length of instruction INSN. */
1351 static inline unsigned int
1352 insn_length (const struct mips_cl_insn *insn)
1354 if (!mips_opts.mips16)
1356 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1359 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1362 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1367 insn->use_extend = FALSE;
1369 insn->insn_opcode = mo->match;
1372 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1373 insn->fixp[i] = NULL;
1374 insn->fixed_p = (mips_opts.noreorder > 0);
1375 insn->noreorder_p = (mips_opts.noreorder > 0);
1376 insn->mips16_absolute_jump_p = 0;
1379 /* Record the current MIPS16 mode in now_seg. */
1382 mips_record_mips16_mode (void)
1384 segment_info_type *si;
1386 si = seg_info (now_seg);
1387 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1388 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1391 /* Install INSN at the location specified by its "frag" and "where" fields. */
1394 install_insn (const struct mips_cl_insn *insn)
1396 char *f = insn->frag->fr_literal + insn->where;
1397 if (!mips_opts.mips16)
1398 md_number_to_chars (f, insn->insn_opcode, 4);
1399 else if (insn->mips16_absolute_jump_p)
1401 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1402 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1406 if (insn->use_extend)
1408 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1411 md_number_to_chars (f, insn->insn_opcode, 2);
1413 mips_record_mips16_mode ();
1416 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1417 and install the opcode in the new location. */
1420 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1425 insn->where = where;
1426 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1427 if (insn->fixp[i] != NULL)
1429 insn->fixp[i]->fx_frag = frag;
1430 insn->fixp[i]->fx_where = where;
1432 install_insn (insn);
1435 /* Add INSN to the end of the output. */
1438 add_fixed_insn (struct mips_cl_insn *insn)
1440 char *f = frag_more (insn_length (insn));
1441 move_insn (insn, frag_now, f - frag_now->fr_literal);
1444 /* Start a variant frag and move INSN to the start of the variant part,
1445 marking it as fixed. The other arguments are as for frag_var. */
1448 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1449 relax_substateT subtype, symbolS *symbol, offsetT offset)
1451 frag_grow (max_chars);
1452 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1454 frag_var (rs_machine_dependent, max_chars, var,
1455 subtype, symbol, offset, NULL);
1458 /* Insert N copies of INSN into the history buffer, starting at
1459 position FIRST. Neither FIRST nor N need to be clipped. */
1462 insert_into_history (unsigned int first, unsigned int n,
1463 const struct mips_cl_insn *insn)
1465 if (mips_relax.sequence != 2)
1469 for (i = ARRAY_SIZE (history); i-- > first;)
1471 history[i] = history[i - n];
1477 /* Emit a nop instruction, recording it in the history buffer. */
1482 add_fixed_insn (NOP_INSN);
1483 insert_into_history (0, 1, NOP_INSN);
1486 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1487 the idea is to make it obvious at a glance that each errata is
1491 init_vr4120_conflicts (void)
1493 #define CONFLICT(FIRST, SECOND) \
1494 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1496 /* Errata 21 - [D]DIV[U] after [D]MACC */
1497 CONFLICT (MACC, DIV);
1498 CONFLICT (DMACC, DIV);
1500 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1501 CONFLICT (DMULT, DMULT);
1502 CONFLICT (DMULT, DMACC);
1503 CONFLICT (DMACC, DMULT);
1504 CONFLICT (DMACC, DMACC);
1506 /* Errata 24 - MT{LO,HI} after [D]MACC */
1507 CONFLICT (MACC, MTHILO);
1508 CONFLICT (DMACC, MTHILO);
1510 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1511 instruction is executed immediately after a MACC or DMACC
1512 instruction, the result of [either instruction] is incorrect." */
1513 CONFLICT (MACC, MULT);
1514 CONFLICT (MACC, DMULT);
1515 CONFLICT (DMACC, MULT);
1516 CONFLICT (DMACC, DMULT);
1518 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1519 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1520 DDIV or DDIVU instruction, the result of the MACC or
1521 DMACC instruction is incorrect.". */
1522 CONFLICT (DMULT, MACC);
1523 CONFLICT (DMULT, DMACC);
1524 CONFLICT (DIV, MACC);
1525 CONFLICT (DIV, DMACC);
1535 #define RTYPE_MASK 0x1ff00
1536 #define RTYPE_NUM 0x00100
1537 #define RTYPE_FPU 0x00200
1538 #define RTYPE_FCC 0x00400
1539 #define RTYPE_VEC 0x00800
1540 #define RTYPE_GP 0x01000
1541 #define RTYPE_CP0 0x02000
1542 #define RTYPE_PC 0x04000
1543 #define RTYPE_ACC 0x08000
1544 #define RTYPE_CCC 0x10000
1545 #define RNUM_MASK 0x000ff
1546 #define RWARN 0x80000
1548 #define GENERIC_REGISTER_NUMBERS \
1549 {"$0", RTYPE_NUM | 0}, \
1550 {"$1", RTYPE_NUM | 1}, \
1551 {"$2", RTYPE_NUM | 2}, \
1552 {"$3", RTYPE_NUM | 3}, \
1553 {"$4", RTYPE_NUM | 4}, \
1554 {"$5", RTYPE_NUM | 5}, \
1555 {"$6", RTYPE_NUM | 6}, \
1556 {"$7", RTYPE_NUM | 7}, \
1557 {"$8", RTYPE_NUM | 8}, \
1558 {"$9", RTYPE_NUM | 9}, \
1559 {"$10", RTYPE_NUM | 10}, \
1560 {"$11", RTYPE_NUM | 11}, \
1561 {"$12", RTYPE_NUM | 12}, \
1562 {"$13", RTYPE_NUM | 13}, \
1563 {"$14", RTYPE_NUM | 14}, \
1564 {"$15", RTYPE_NUM | 15}, \
1565 {"$16", RTYPE_NUM | 16}, \
1566 {"$17", RTYPE_NUM | 17}, \
1567 {"$18", RTYPE_NUM | 18}, \
1568 {"$19", RTYPE_NUM | 19}, \
1569 {"$20", RTYPE_NUM | 20}, \
1570 {"$21", RTYPE_NUM | 21}, \
1571 {"$22", RTYPE_NUM | 22}, \
1572 {"$23", RTYPE_NUM | 23}, \
1573 {"$24", RTYPE_NUM | 24}, \
1574 {"$25", RTYPE_NUM | 25}, \
1575 {"$26", RTYPE_NUM | 26}, \
1576 {"$27", RTYPE_NUM | 27}, \
1577 {"$28", RTYPE_NUM | 28}, \
1578 {"$29", RTYPE_NUM | 29}, \
1579 {"$30", RTYPE_NUM | 30}, \
1580 {"$31", RTYPE_NUM | 31}
1582 #define FPU_REGISTER_NAMES \
1583 {"$f0", RTYPE_FPU | 0}, \
1584 {"$f1", RTYPE_FPU | 1}, \
1585 {"$f2", RTYPE_FPU | 2}, \
1586 {"$f3", RTYPE_FPU | 3}, \
1587 {"$f4", RTYPE_FPU | 4}, \
1588 {"$f5", RTYPE_FPU | 5}, \
1589 {"$f6", RTYPE_FPU | 6}, \
1590 {"$f7", RTYPE_FPU | 7}, \
1591 {"$f8", RTYPE_FPU | 8}, \
1592 {"$f9", RTYPE_FPU | 9}, \
1593 {"$f10", RTYPE_FPU | 10}, \
1594 {"$f11", RTYPE_FPU | 11}, \
1595 {"$f12", RTYPE_FPU | 12}, \
1596 {"$f13", RTYPE_FPU | 13}, \
1597 {"$f14", RTYPE_FPU | 14}, \
1598 {"$f15", RTYPE_FPU | 15}, \
1599 {"$f16", RTYPE_FPU | 16}, \
1600 {"$f17", RTYPE_FPU | 17}, \
1601 {"$f18", RTYPE_FPU | 18}, \
1602 {"$f19", RTYPE_FPU | 19}, \
1603 {"$f20", RTYPE_FPU | 20}, \
1604 {"$f21", RTYPE_FPU | 21}, \
1605 {"$f22", RTYPE_FPU | 22}, \
1606 {"$f23", RTYPE_FPU | 23}, \
1607 {"$f24", RTYPE_FPU | 24}, \
1608 {"$f25", RTYPE_FPU | 25}, \
1609 {"$f26", RTYPE_FPU | 26}, \
1610 {"$f27", RTYPE_FPU | 27}, \
1611 {"$f28", RTYPE_FPU | 28}, \
1612 {"$f29", RTYPE_FPU | 29}, \
1613 {"$f30", RTYPE_FPU | 30}, \
1614 {"$f31", RTYPE_FPU | 31}
1616 #define FPU_CONDITION_CODE_NAMES \
1617 {"$fcc0", RTYPE_FCC | 0}, \
1618 {"$fcc1", RTYPE_FCC | 1}, \
1619 {"$fcc2", RTYPE_FCC | 2}, \
1620 {"$fcc3", RTYPE_FCC | 3}, \
1621 {"$fcc4", RTYPE_FCC | 4}, \
1622 {"$fcc5", RTYPE_FCC | 5}, \
1623 {"$fcc6", RTYPE_FCC | 6}, \
1624 {"$fcc7", RTYPE_FCC | 7}
1626 #define COPROC_CONDITION_CODE_NAMES \
1627 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1628 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1629 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1630 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1631 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1632 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1633 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1634 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1636 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1637 {"$a4", RTYPE_GP | 8}, \
1638 {"$a5", RTYPE_GP | 9}, \
1639 {"$a6", RTYPE_GP | 10}, \
1640 {"$a7", RTYPE_GP | 11}, \
1641 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1642 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1643 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1644 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1645 {"$t0", RTYPE_GP | 12}, \
1646 {"$t1", RTYPE_GP | 13}, \
1647 {"$t2", RTYPE_GP | 14}, \
1648 {"$t3", RTYPE_GP | 15}
1650 #define O32_SYMBOLIC_REGISTER_NAMES \
1651 {"$t0", RTYPE_GP | 8}, \
1652 {"$t1", RTYPE_GP | 9}, \
1653 {"$t2", RTYPE_GP | 10}, \
1654 {"$t3", RTYPE_GP | 11}, \
1655 {"$t4", RTYPE_GP | 12}, \
1656 {"$t5", RTYPE_GP | 13}, \
1657 {"$t6", RTYPE_GP | 14}, \
1658 {"$t7", RTYPE_GP | 15}, \
1659 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1660 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1661 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1662 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1664 /* Remaining symbolic register names */
1665 #define SYMBOLIC_REGISTER_NAMES \
1666 {"$zero", RTYPE_GP | 0}, \
1667 {"$at", RTYPE_GP | 1}, \
1668 {"$AT", RTYPE_GP | 1}, \
1669 {"$v0", RTYPE_GP | 2}, \
1670 {"$v1", RTYPE_GP | 3}, \
1671 {"$a0", RTYPE_GP | 4}, \
1672 {"$a1", RTYPE_GP | 5}, \
1673 {"$a2", RTYPE_GP | 6}, \
1674 {"$a3", RTYPE_GP | 7}, \
1675 {"$s0", RTYPE_GP | 16}, \
1676 {"$s1", RTYPE_GP | 17}, \
1677 {"$s2", RTYPE_GP | 18}, \
1678 {"$s3", RTYPE_GP | 19}, \
1679 {"$s4", RTYPE_GP | 20}, \
1680 {"$s5", RTYPE_GP | 21}, \
1681 {"$s6", RTYPE_GP | 22}, \
1682 {"$s7", RTYPE_GP | 23}, \
1683 {"$t8", RTYPE_GP | 24}, \
1684 {"$t9", RTYPE_GP | 25}, \
1685 {"$k0", RTYPE_GP | 26}, \
1686 {"$kt0", RTYPE_GP | 26}, \
1687 {"$k1", RTYPE_GP | 27}, \
1688 {"$kt1", RTYPE_GP | 27}, \
1689 {"$gp", RTYPE_GP | 28}, \
1690 {"$sp", RTYPE_GP | 29}, \
1691 {"$s8", RTYPE_GP | 30}, \
1692 {"$fp", RTYPE_GP | 30}, \
1693 {"$ra", RTYPE_GP | 31}
1695 #define MIPS16_SPECIAL_REGISTER_NAMES \
1696 {"$pc", RTYPE_PC | 0}
1698 #define MDMX_VECTOR_REGISTER_NAMES \
1699 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1700 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1701 {"$v2", RTYPE_VEC | 2}, \
1702 {"$v3", RTYPE_VEC | 3}, \
1703 {"$v4", RTYPE_VEC | 4}, \
1704 {"$v5", RTYPE_VEC | 5}, \
1705 {"$v6", RTYPE_VEC | 6}, \
1706 {"$v7", RTYPE_VEC | 7}, \
1707 {"$v8", RTYPE_VEC | 8}, \
1708 {"$v9", RTYPE_VEC | 9}, \
1709 {"$v10", RTYPE_VEC | 10}, \
1710 {"$v11", RTYPE_VEC | 11}, \
1711 {"$v12", RTYPE_VEC | 12}, \
1712 {"$v13", RTYPE_VEC | 13}, \
1713 {"$v14", RTYPE_VEC | 14}, \
1714 {"$v15", RTYPE_VEC | 15}, \
1715 {"$v16", RTYPE_VEC | 16}, \
1716 {"$v17", RTYPE_VEC | 17}, \
1717 {"$v18", RTYPE_VEC | 18}, \
1718 {"$v19", RTYPE_VEC | 19}, \
1719 {"$v20", RTYPE_VEC | 20}, \
1720 {"$v21", RTYPE_VEC | 21}, \
1721 {"$v22", RTYPE_VEC | 22}, \
1722 {"$v23", RTYPE_VEC | 23}, \
1723 {"$v24", RTYPE_VEC | 24}, \
1724 {"$v25", RTYPE_VEC | 25}, \
1725 {"$v26", RTYPE_VEC | 26}, \
1726 {"$v27", RTYPE_VEC | 27}, \
1727 {"$v28", RTYPE_VEC | 28}, \
1728 {"$v29", RTYPE_VEC | 29}, \
1729 {"$v30", RTYPE_VEC | 30}, \
1730 {"$v31", RTYPE_VEC | 31}
1732 #define MIPS_DSP_ACCUMULATOR_NAMES \
1733 {"$ac0", RTYPE_ACC | 0}, \
1734 {"$ac1", RTYPE_ACC | 1}, \
1735 {"$ac2", RTYPE_ACC | 2}, \
1736 {"$ac3", RTYPE_ACC | 3}
1738 static const struct regname reg_names[] = {
1739 GENERIC_REGISTER_NUMBERS,
1741 FPU_CONDITION_CODE_NAMES,
1742 COPROC_CONDITION_CODE_NAMES,
1744 /* The $txx registers depends on the abi,
1745 these will be added later into the symbol table from
1746 one of the tables below once mips_abi is set after
1747 parsing of arguments from the command line. */
1748 SYMBOLIC_REGISTER_NAMES,
1750 MIPS16_SPECIAL_REGISTER_NAMES,
1751 MDMX_VECTOR_REGISTER_NAMES,
1752 MIPS_DSP_ACCUMULATOR_NAMES,
1756 static const struct regname reg_names_o32[] = {
1757 O32_SYMBOLIC_REGISTER_NAMES,
1761 static const struct regname reg_names_n32n64[] = {
1762 N32N64_SYMBOLIC_REGISTER_NAMES,
1767 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1774 /* Find end of name. */
1776 if (is_name_beginner (*e))
1778 while (is_part_of_name (*e))
1781 /* Terminate name. */
1785 /* Look for a register symbol. */
1786 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1788 int r = S_GET_VALUE (symbolP);
1790 reg = r & RNUM_MASK;
1791 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1792 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1793 reg = (r & RNUM_MASK) - 2;
1795 /* Else see if this is a register defined in an itbl entry. */
1796 else if ((types & RTYPE_GP) && itbl_have_entries)
1803 if (itbl_get_reg_val (n, &r))
1804 reg = r & RNUM_MASK;
1807 /* Advance to next token if a register was recognised. */
1810 else if (types & RWARN)
1811 as_warn (_("Unrecognized register name `%s'"), *s);
1819 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1820 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1823 is_opcode_valid (const struct mips_opcode *mo)
1825 int isa = mips_opts.isa;
1828 if (mips_opts.ase_mdmx)
1830 if (mips_opts.ase_dsp)
1832 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1834 if (mips_opts.ase_dspr2)
1836 if (mips_opts.ase_mt)
1838 if (mips_opts.ase_mips3d)
1840 if (mips_opts.ase_smartmips)
1841 isa |= INSN_SMARTMIPS;
1843 /* Don't accept instructions based on the ISA if the CPU does not implement
1844 all the coprocessor insns. */
1845 if (NO_ISA_COP (mips_opts.arch)
1846 && COP_INSN (mo->pinfo))
1849 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1852 /* Check whether the instruction or macro requires single-precision or
1853 double-precision floating-point support. Note that this information is
1854 stored differently in the opcode table for insns and macros. */
1855 if (mo->pinfo == INSN_MACRO)
1857 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1858 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1862 fp_s = mo->pinfo & FP_S;
1863 fp_d = mo->pinfo & FP_D;
1866 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1869 if (fp_s && mips_opts.soft_float)
1875 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1876 selected ISA and architecture. */
1879 is_opcode_valid_16 (const struct mips_opcode *mo)
1881 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1884 /* This function is called once, at assembler startup time. It should set up
1885 all the tables, etc. that the MD part of the assembler will need. */
1890 const char *retval = NULL;
1894 if (mips_pic != NO_PIC)
1896 if (g_switch_seen && g_switch_value != 0)
1897 as_bad (_("-G may not be used in position-independent code"));
1901 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1902 as_warn (_("Could not set architecture and machine"));
1904 op_hash = hash_new ();
1906 for (i = 0; i < NUMOPCODES;)
1908 const char *name = mips_opcodes[i].name;
1910 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1913 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1914 mips_opcodes[i].name, retval);
1915 /* Probably a memory allocation problem? Give up now. */
1916 as_fatal (_("Broken assembler. No assembly attempted."));
1920 if (mips_opcodes[i].pinfo != INSN_MACRO)
1922 if (!validate_mips_insn (&mips_opcodes[i]))
1924 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1926 create_insn (&nop_insn, mips_opcodes + i);
1927 if (mips_fix_loongson2f_nop)
1928 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1929 nop_insn.fixed_p = 1;
1934 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1937 mips16_op_hash = hash_new ();
1940 while (i < bfd_mips16_num_opcodes)
1942 const char *name = mips16_opcodes[i].name;
1944 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1946 as_fatal (_("internal: can't hash `%s': %s"),
1947 mips16_opcodes[i].name, retval);
1950 if (mips16_opcodes[i].pinfo != INSN_MACRO
1951 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1952 != mips16_opcodes[i].match))
1954 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1955 mips16_opcodes[i].name, mips16_opcodes[i].args);
1958 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1960 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1961 mips16_nop_insn.fixed_p = 1;
1965 while (i < bfd_mips16_num_opcodes
1966 && strcmp (mips16_opcodes[i].name, name) == 0);
1970 as_fatal (_("Broken assembler. No assembly attempted."));
1972 /* We add all the general register names to the symbol table. This
1973 helps us detect invalid uses of them. */
1974 for (i = 0; reg_names[i].name; i++)
1975 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1976 reg_names[i].num, /* & RNUM_MASK, */
1977 &zero_address_frag));
1979 for (i = 0; reg_names_n32n64[i].name; i++)
1980 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1981 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1982 &zero_address_frag));
1984 for (i = 0; reg_names_o32[i].name; i++)
1985 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1986 reg_names_o32[i].num, /* & RNUM_MASK, */
1987 &zero_address_frag));
1989 mips_no_prev_insn ();
1992 mips_cprmask[0] = 0;
1993 mips_cprmask[1] = 0;
1994 mips_cprmask[2] = 0;
1995 mips_cprmask[3] = 0;
1997 /* set the default alignment for the text section (2**2) */
1998 record_alignment (text_section, 2);
2000 bfd_set_gp_size (stdoutput, g_switch_value);
2005 /* On a native system other than VxWorks, sections must be aligned
2006 to 16 byte boundaries. When configured for an embedded ELF
2007 target, we don't bother. */
2008 if (strncmp (TARGET_OS, "elf", 3) != 0
2009 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2011 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2012 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2013 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2016 /* Create a .reginfo section for register masks and a .mdebug
2017 section for debugging information. */
2025 subseg = now_subseg;
2027 /* The ABI says this section should be loaded so that the
2028 running program can access it. However, we don't load it
2029 if we are configured for an embedded target */
2030 flags = SEC_READONLY | SEC_DATA;
2031 if (strncmp (TARGET_OS, "elf", 3) != 0)
2032 flags |= SEC_ALLOC | SEC_LOAD;
2034 if (mips_abi != N64_ABI)
2036 sec = subseg_new (".reginfo", (subsegT) 0);
2038 bfd_set_section_flags (stdoutput, sec, flags);
2039 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2041 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2045 /* The 64-bit ABI uses a .MIPS.options section rather than
2046 .reginfo section. */
2047 sec = subseg_new (".MIPS.options", (subsegT) 0);
2048 bfd_set_section_flags (stdoutput, sec, flags);
2049 bfd_set_section_alignment (stdoutput, sec, 3);
2051 /* Set up the option header. */
2053 Elf_Internal_Options opthdr;
2056 opthdr.kind = ODK_REGINFO;
2057 opthdr.size = (sizeof (Elf_External_Options)
2058 + sizeof (Elf64_External_RegInfo));
2061 f = frag_more (sizeof (Elf_External_Options));
2062 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2063 (Elf_External_Options *) f);
2065 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2069 if (ECOFF_DEBUGGING)
2071 sec = subseg_new (".mdebug", (subsegT) 0);
2072 (void) bfd_set_section_flags (stdoutput, sec,
2073 SEC_HAS_CONTENTS | SEC_READONLY);
2074 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2076 else if (mips_flag_pdr)
2078 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2079 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2080 SEC_READONLY | SEC_RELOC
2082 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2085 subseg_set (seg, subseg);
2088 #endif /* OBJ_ELF */
2090 if (! ECOFF_DEBUGGING)
2093 if (mips_fix_vr4120)
2094 init_vr4120_conflicts ();
2100 if (! ECOFF_DEBUGGING)
2105 md_assemble (char *str)
2107 struct mips_cl_insn insn;
2108 bfd_reloc_code_real_type unused_reloc[3]
2109 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2111 imm_expr.X_op = O_absent;
2112 imm2_expr.X_op = O_absent;
2113 offset_expr.X_op = O_absent;
2114 imm_reloc[0] = BFD_RELOC_UNUSED;
2115 imm_reloc[1] = BFD_RELOC_UNUSED;
2116 imm_reloc[2] = BFD_RELOC_UNUSED;
2117 offset_reloc[0] = BFD_RELOC_UNUSED;
2118 offset_reloc[1] = BFD_RELOC_UNUSED;
2119 offset_reloc[2] = BFD_RELOC_UNUSED;
2121 if (mips_opts.mips16)
2122 mips16_ip (str, &insn);
2125 mips_ip (str, &insn);
2126 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2127 str, insn.insn_opcode));
2132 as_bad ("%s `%s'", insn_error, str);
2136 if (insn.insn_mo->pinfo == INSN_MACRO)
2139 if (mips_opts.mips16)
2140 mips16_macro (&insn);
2147 if (imm_expr.X_op != O_absent)
2148 append_insn (&insn, &imm_expr, imm_reloc);
2149 else if (offset_expr.X_op != O_absent)
2150 append_insn (&insn, &offset_expr, offset_reloc);
2152 append_insn (&insn, NULL, unused_reloc);
2156 /* Convenience functions for abstracting away the differences between
2157 MIPS16 and non-MIPS16 relocations. */
2159 static inline bfd_boolean
2160 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2164 case BFD_RELOC_MIPS16_JMP:
2165 case BFD_RELOC_MIPS16_GPREL:
2166 case BFD_RELOC_MIPS16_GOT16:
2167 case BFD_RELOC_MIPS16_CALL16:
2168 case BFD_RELOC_MIPS16_HI16_S:
2169 case BFD_RELOC_MIPS16_HI16:
2170 case BFD_RELOC_MIPS16_LO16:
2178 static inline bfd_boolean
2179 got16_reloc_p (bfd_reloc_code_real_type reloc)
2181 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2184 static inline bfd_boolean
2185 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2187 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2190 static inline bfd_boolean
2191 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2193 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2196 /* Return true if the given relocation might need a matching %lo().
2197 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2198 need a matching %lo() when applied to local symbols. */
2200 static inline bfd_boolean
2201 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2203 return (HAVE_IN_PLACE_ADDENDS
2204 && (hi16_reloc_p (reloc)
2205 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2206 all GOT16 relocations evaluate to "G". */
2207 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2210 /* Return the type of %lo() reloc needed by RELOC, given that
2211 reloc_needs_lo_p. */
2213 static inline bfd_reloc_code_real_type
2214 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2216 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2219 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2222 static inline bfd_boolean
2223 fixup_has_matching_lo_p (fixS *fixp)
2225 return (fixp->fx_next != NULL
2226 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2227 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2228 && fixp->fx_offset == fixp->fx_next->fx_offset);
2231 /* See whether instruction IP reads register REG. CLASS is the type
2235 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2236 enum mips_regclass regclass)
2238 if (regclass == MIPS16_REG)
2240 gas_assert (mips_opts.mips16);
2241 reg = mips16_to_32_reg_map[reg];
2242 regclass = MIPS_GR_REG;
2245 /* Don't report on general register ZERO, since it never changes. */
2246 if (regclass == MIPS_GR_REG && reg == ZERO)
2249 if (regclass == MIPS_FP_REG)
2251 gas_assert (! mips_opts.mips16);
2252 /* If we are called with either $f0 or $f1, we must check $f0.
2253 This is not optimal, because it will introduce an unnecessary
2254 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2255 need to distinguish reading both $f0 and $f1 or just one of
2256 them. Note that we don't have to check the other way,
2257 because there is no instruction that sets both $f0 and $f1
2258 and requires a delay. */
2259 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2260 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2261 == (reg &~ (unsigned) 1)))
2263 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2264 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2265 == (reg &~ (unsigned) 1)))
2268 else if (! mips_opts.mips16)
2270 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2271 && EXTRACT_OPERAND (RS, *ip) == reg)
2273 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2274 && EXTRACT_OPERAND (RT, *ip) == reg)
2279 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2280 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2282 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2283 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2285 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2286 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2289 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2291 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2293 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2295 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2296 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2303 /* This function returns true if modifying a register requires a
2307 reg_needs_delay (unsigned int reg)
2309 unsigned long prev_pinfo;
2311 prev_pinfo = history[0].insn_mo->pinfo;
2312 if (! mips_opts.noreorder
2313 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2314 && ! gpr_interlocks)
2315 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2316 && ! cop_interlocks)))
2318 /* A load from a coprocessor or from memory. All load delays
2319 delay the use of general register rt for one instruction. */
2320 /* Itbl support may require additional care here. */
2321 know (prev_pinfo & INSN_WRITE_GPR_T);
2322 if (reg == EXTRACT_OPERAND (RT, history[0]))
2329 /* Move all labels in insn_labels to the current insertion point. */
2332 mips_move_labels (void)
2334 segment_info_type *si = seg_info (now_seg);
2335 struct insn_label_list *l;
2338 for (l = si->label_list; l != NULL; l = l->next)
2340 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2341 symbol_set_frag (l->label, frag_now);
2342 val = (valueT) frag_now_fix ();
2343 /* mips16 text labels are stored as odd. */
2344 if (mips_opts.mips16)
2346 S_SET_VALUE (l->label, val);
2351 s_is_linkonce (symbolS *sym, segT from_seg)
2353 bfd_boolean linkonce = FALSE;
2354 segT symseg = S_GET_SEGMENT (sym);
2356 if (symseg != from_seg && !S_IS_LOCAL (sym))
2358 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2361 /* The GNU toolchain uses an extension for ELF: a section
2362 beginning with the magic string .gnu.linkonce is a
2363 linkonce section. */
2364 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2365 sizeof ".gnu.linkonce" - 1) == 0)
2372 /* Mark instruction labels in mips16 mode. This permits the linker to
2373 handle them specially, such as generating jalx instructions when
2374 needed. We also make them odd for the duration of the assembly, in
2375 order to generate the right sort of code. We will make them even
2376 in the adjust_symtab routine, while leaving them marked. This is
2377 convenient for the debugger and the disassembler. The linker knows
2378 to make them odd again. */
2381 mips16_mark_labels (void)
2383 segment_info_type *si = seg_info (now_seg);
2384 struct insn_label_list *l;
2386 if (!mips_opts.mips16)
2389 for (l = si->label_list; l != NULL; l = l->next)
2391 symbolS *label = l->label;
2393 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2395 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2397 if ((S_GET_VALUE (label) & 1) == 0
2398 /* Don't adjust the address if the label is global or weak, or
2399 in a link-once section, since we'll be emitting symbol reloc
2400 references to it which will be patched up by the linker, and
2401 the final value of the symbol may or may not be MIPS16. */
2402 && ! S_IS_WEAK (label)
2403 && ! S_IS_EXTERNAL (label)
2404 && ! s_is_linkonce (label, now_seg))
2405 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2409 /* End the current frag. Make it a variant frag and record the
2413 relax_close_frag (void)
2415 mips_macro_warning.first_frag = frag_now;
2416 frag_var (rs_machine_dependent, 0, 0,
2417 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2418 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2420 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2421 mips_relax.first_fixup = 0;
2424 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2425 See the comment above RELAX_ENCODE for more details. */
2428 relax_start (symbolS *symbol)
2430 gas_assert (mips_relax.sequence == 0);
2431 mips_relax.sequence = 1;
2432 mips_relax.symbol = symbol;
2435 /* Start generating the second version of a relaxable sequence.
2436 See the comment above RELAX_ENCODE for more details. */
2441 gas_assert (mips_relax.sequence == 1);
2442 mips_relax.sequence = 2;
2445 /* End the current relaxable sequence. */
2450 gas_assert (mips_relax.sequence == 2);
2451 relax_close_frag ();
2452 mips_relax.sequence = 0;
2455 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2456 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2457 by VR4120 errata. */
2460 classify_vr4120_insn (const char *name)
2462 if (strncmp (name, "macc", 4) == 0)
2463 return FIX_VR4120_MACC;
2464 if (strncmp (name, "dmacc", 5) == 0)
2465 return FIX_VR4120_DMACC;
2466 if (strncmp (name, "mult", 4) == 0)
2467 return FIX_VR4120_MULT;
2468 if (strncmp (name, "dmult", 5) == 0)
2469 return FIX_VR4120_DMULT;
2470 if (strstr (name, "div"))
2471 return FIX_VR4120_DIV;
2472 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2473 return FIX_VR4120_MTHILO;
2474 return NUM_FIX_VR4120_CLASSES;
2477 #define INSN_ERET 0x42000018
2478 #define INSN_DERET 0x4200001f
2480 /* Return the number of instructions that must separate INSN1 and INSN2,
2481 where INSN1 is the earlier instruction. Return the worst-case value
2482 for any INSN2 if INSN2 is null. */
2485 insns_between (const struct mips_cl_insn *insn1,
2486 const struct mips_cl_insn *insn2)
2488 unsigned long pinfo1, pinfo2;
2490 /* This function needs to know which pinfo flags are set for INSN2
2491 and which registers INSN2 uses. The former is stored in PINFO2 and
2492 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2493 will have every flag set and INSN2_USES_REG will always return true. */
2494 pinfo1 = insn1->insn_mo->pinfo;
2495 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2497 #define INSN2_USES_REG(REG, CLASS) \
2498 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2500 /* For most targets, write-after-read dependencies on the HI and LO
2501 registers must be separated by at least two instructions. */
2502 if (!hilo_interlocks)
2504 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2506 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2510 /* If we're working around r7000 errata, there must be two instructions
2511 between an mfhi or mflo and any instruction that uses the result. */
2512 if (mips_7000_hilo_fix
2513 && MF_HILO_INSN (pinfo1)
2514 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2517 /* If we're working around 24K errata, one instruction is required
2518 if an ERET or DERET is followed by a branch instruction. */
2521 if (insn1->insn_opcode == INSN_ERET
2522 || insn1->insn_opcode == INSN_DERET)
2525 || insn2->insn_opcode == INSN_ERET
2526 || insn2->insn_opcode == INSN_DERET
2527 || (insn2->insn_mo->pinfo
2528 & (INSN_UNCOND_BRANCH_DELAY
2529 | INSN_COND_BRANCH_DELAY
2530 | INSN_COND_BRANCH_LIKELY)) != 0)
2535 /* If working around VR4120 errata, check for combinations that need
2536 a single intervening instruction. */
2537 if (mips_fix_vr4120)
2539 unsigned int class1, class2;
2541 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2542 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2546 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2547 if (vr4120_conflicts[class1] & (1 << class2))
2552 if (!mips_opts.mips16)
2554 /* Check for GPR or coprocessor load delays. All such delays
2555 are on the RT register. */
2556 /* Itbl support may require additional care here. */
2557 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2558 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2560 know (pinfo1 & INSN_WRITE_GPR_T);
2561 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2565 /* Check for generic coprocessor hazards.
2567 This case is not handled very well. There is no special
2568 knowledge of CP0 handling, and the coprocessors other than
2569 the floating point unit are not distinguished at all. */
2570 /* Itbl support may require additional care here. FIXME!
2571 Need to modify this to include knowledge about
2572 user specified delays! */
2573 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2574 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2576 /* Handle cases where INSN1 writes to a known general coprocessor
2577 register. There must be a one instruction delay before INSN2
2578 if INSN2 reads that register, otherwise no delay is needed. */
2579 if (pinfo1 & INSN_WRITE_FPR_T)
2581 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2584 else if (pinfo1 & INSN_WRITE_FPR_S)
2586 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2591 /* Read-after-write dependencies on the control registers
2592 require a two-instruction gap. */
2593 if ((pinfo1 & INSN_WRITE_COND_CODE)
2594 && (pinfo2 & INSN_READ_COND_CODE))
2597 /* We don't know exactly what INSN1 does. If INSN2 is
2598 also a coprocessor instruction, assume there must be
2599 a one instruction gap. */
2600 if (pinfo2 & INSN_COP)
2605 /* Check for read-after-write dependencies on the coprocessor
2606 control registers in cases where INSN1 does not need a general
2607 coprocessor delay. This means that INSN1 is a floating point
2608 comparison instruction. */
2609 /* Itbl support may require additional care here. */
2610 else if (!cop_interlocks
2611 && (pinfo1 & INSN_WRITE_COND_CODE)
2612 && (pinfo2 & INSN_READ_COND_CODE))
2616 #undef INSN2_USES_REG
2621 /* Return the number of nops that would be needed to work around the
2622 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2623 the MAX_VR4130_NOPS instructions described by HIST. */
2626 nops_for_vr4130 (const struct mips_cl_insn *hist,
2627 const struct mips_cl_insn *insn)
2631 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2632 are not affected by the errata. */
2634 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2635 || strcmp (insn->insn_mo->name, "mtlo") == 0
2636 || strcmp (insn->insn_mo->name, "mthi") == 0))
2639 /* Search for the first MFLO or MFHI. */
2640 for (i = 0; i < MAX_VR4130_NOPS; i++)
2641 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2643 /* Extract the destination register. */
2644 if (mips_opts.mips16)
2645 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2647 reg = EXTRACT_OPERAND (RD, hist[i]);
2649 /* No nops are needed if INSN reads that register. */
2650 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2653 /* ...or if any of the intervening instructions do. */
2654 for (j = 0; j < i; j++)
2655 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2658 return MAX_VR4130_NOPS - i;
2663 /* Return the number of nops that would be needed if instruction INSN
2664 immediately followed the MAX_NOPS instructions given by HIST,
2665 where HIST[0] is the most recent instruction. If INSN is null,
2666 return the worse-case number of nops for any instruction. */
2669 nops_for_insn (const struct mips_cl_insn *hist,
2670 const struct mips_cl_insn *insn)
2672 int i, nops, tmp_nops;
2675 for (i = 0; i < MAX_DELAY_NOPS; i++)
2677 tmp_nops = insns_between (hist + i, insn) - i;
2678 if (tmp_nops > nops)
2682 if (mips_fix_vr4130)
2684 tmp_nops = nops_for_vr4130 (hist, insn);
2685 if (tmp_nops > nops)
2692 /* The variable arguments provide NUM_INSNS extra instructions that
2693 might be added to HIST. Return the largest number of nops that
2694 would be needed after the extended sequence. */
2697 nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...)
2700 struct mips_cl_insn buffer[MAX_NOPS];
2701 struct mips_cl_insn *cursor;
2704 va_start (args, hist);
2705 cursor = buffer + num_insns;
2706 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2707 while (cursor > buffer)
2708 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2710 nops = nops_for_insn (buffer, NULL);
2715 /* Like nops_for_insn, but if INSN is a branch, take into account the
2716 worst-case delay for the branch target. */
2719 nops_for_insn_or_target (const struct mips_cl_insn *hist,
2720 const struct mips_cl_insn *insn)
2724 nops = nops_for_insn (hist, insn);
2725 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2726 | INSN_COND_BRANCH_DELAY
2727 | INSN_COND_BRANCH_LIKELY))
2729 tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN);
2730 if (tmp_nops > nops)
2733 else if (mips_opts.mips16
2734 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2735 | MIPS16_INSN_COND_BRANCH)))
2737 tmp_nops = nops_for_sequence (1, hist, insn);
2738 if (tmp_nops > nops)
2744 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2747 fix_loongson2f_nop (struct mips_cl_insn * ip)
2749 if (strcmp (ip->insn_mo->name, "nop") == 0)
2750 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2753 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2754 jr target pc &= 'hffff_ffff_cfff_ffff. */
2757 fix_loongson2f_jump (struct mips_cl_insn * ip)
2759 if (strcmp (ip->insn_mo->name, "j") == 0
2760 || strcmp (ip->insn_mo->name, "jr") == 0
2761 || strcmp (ip->insn_mo->name, "jalr") == 0)
2769 sreg = EXTRACT_OPERAND (RS, *ip);
2770 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
2773 ep.X_op = O_constant;
2774 ep.X_add_number = 0xcfff0000;
2775 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
2776 ep.X_add_number = 0xffff;
2777 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
2778 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
2783 fix_loongson2f (struct mips_cl_insn * ip)
2785 if (mips_fix_loongson2f_nop)
2786 fix_loongson2f_nop (ip);
2788 if (mips_fix_loongson2f_jump)
2789 fix_loongson2f_jump (ip);
2792 /* Output an instruction. IP is the instruction information.
2793 ADDRESS_EXPR is an operand of the instruction to be used with
2797 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2798 bfd_reloc_code_real_type *reloc_type)
2800 unsigned long prev_pinfo, pinfo;
2801 relax_stateT prev_insn_frag_type = 0;
2802 bfd_boolean relaxed_branch = FALSE;
2803 segment_info_type *si = seg_info (now_seg);
2805 if (mips_fix_loongson2f)
2806 fix_loongson2f (ip);
2808 /* Mark instruction labels in mips16 mode. */
2809 mips16_mark_labels ();
2811 prev_pinfo = history[0].insn_mo->pinfo;
2812 pinfo = ip->insn_mo->pinfo;
2814 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2816 /* There are a lot of optimizations we could do that we don't.
2817 In particular, we do not, in general, reorder instructions.
2818 If you use gcc with optimization, it will reorder
2819 instructions and generally do much more optimization then we
2820 do here; repeating all that work in the assembler would only
2821 benefit hand written assembly code, and does not seem worth
2823 int nops = (mips_optimize == 0
2824 ? nops_for_insn (history, NULL)
2825 : nops_for_insn_or_target (history, ip));
2829 unsigned long old_frag_offset;
2832 old_frag = frag_now;
2833 old_frag_offset = frag_now_fix ();
2835 for (i = 0; i < nops; i++)
2840 listing_prev_line ();
2841 /* We may be at the start of a variant frag. In case we
2842 are, make sure there is enough space for the frag
2843 after the frags created by listing_prev_line. The
2844 argument to frag_grow here must be at least as large
2845 as the argument to all other calls to frag_grow in
2846 this file. We don't have to worry about being in the
2847 middle of a variant frag, because the variants insert
2848 all needed nop instructions themselves. */
2852 mips_move_labels ();
2854 #ifndef NO_ECOFF_DEBUGGING
2855 if (ECOFF_DEBUGGING)
2856 ecoff_fix_loc (old_frag, old_frag_offset);
2860 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2862 /* Work out how many nops in prev_nop_frag are needed by IP. */
2863 int nops = nops_for_insn_or_target (history, ip);
2864 gas_assert (nops <= prev_nop_frag_holds);
2866 /* Enforce NOPS as a minimum. */
2867 if (nops > prev_nop_frag_required)
2868 prev_nop_frag_required = nops;
2870 if (prev_nop_frag_holds == prev_nop_frag_required)
2872 /* Settle for the current number of nops. Update the history
2873 accordingly (for the benefit of any future .set reorder code). */
2874 prev_nop_frag = NULL;
2875 insert_into_history (prev_nop_frag_since,
2876 prev_nop_frag_holds, NOP_INSN);
2880 /* Allow this instruction to replace one of the nops that was
2881 tentatively added to prev_nop_frag. */
2882 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2883 prev_nop_frag_holds--;
2884 prev_nop_frag_since++;
2889 /* The value passed to dwarf2_emit_insn is the distance between
2890 the beginning of the current instruction and the address that
2891 should be recorded in the debug tables. For MIPS16 debug info
2892 we want to use ISA-encoded addresses, so we pass -1 for an
2893 address higher by one than the current. */
2894 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2897 /* Record the frag type before frag_var. */
2898 if (history[0].frag)
2899 prev_insn_frag_type = history[0].frag->fr_type;
2902 && *reloc_type == BFD_RELOC_16_PCREL_S2
2903 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2904 || pinfo & INSN_COND_BRANCH_LIKELY)
2905 && mips_relax_branch
2906 /* Don't try branch relaxation within .set nomacro, or within
2907 .set noat if we use $at for PIC computations. If it turns
2908 out that the branch was out-of-range, we'll get an error. */
2909 && !mips_opts.warn_about_macros
2910 && (mips_opts.at || mips_pic == NO_PIC)
2911 && !mips_opts.mips16)
2913 relaxed_branch = TRUE;
2914 add_relaxed_insn (ip, (relaxed_branch_length
2916 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2917 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2920 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2921 pinfo & INSN_COND_BRANCH_LIKELY,
2922 pinfo & INSN_WRITE_GPR_31,
2924 address_expr->X_add_symbol,
2925 address_expr->X_add_number);
2926 *reloc_type = BFD_RELOC_UNUSED;
2928 else if (*reloc_type > BFD_RELOC_UNUSED)
2930 /* We need to set up a variant frag. */
2931 gas_assert (mips_opts.mips16 && address_expr != NULL);
2932 add_relaxed_insn (ip, 4, 0,
2934 (*reloc_type - BFD_RELOC_UNUSED,
2935 mips16_small, mips16_ext,
2936 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2937 history[0].mips16_absolute_jump_p),
2938 make_expr_symbol (address_expr), 0);
2940 else if (mips_opts.mips16
2942 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2944 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2945 /* Make sure there is enough room to swap this instruction with
2946 a following jump instruction. */
2948 add_fixed_insn (ip);
2952 if (mips_opts.mips16
2953 && mips_opts.noreorder
2954 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2955 as_warn (_("extended instruction in delay slot"));
2957 if (mips_relax.sequence)
2959 /* If we've reached the end of this frag, turn it into a variant
2960 frag and record the information for the instructions we've
2962 if (frag_room () < 4)
2963 relax_close_frag ();
2964 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2967 if (mips_relax.sequence != 2)
2968 mips_macro_warning.sizes[0] += 4;
2969 if (mips_relax.sequence != 1)
2970 mips_macro_warning.sizes[1] += 4;
2972 if (mips_opts.mips16)
2975 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2977 add_fixed_insn (ip);
2980 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2982 if (address_expr->X_op == O_constant)
2986 switch (*reloc_type)
2989 ip->insn_opcode |= address_expr->X_add_number;
2992 case BFD_RELOC_MIPS_HIGHEST:
2993 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2994 ip->insn_opcode |= tmp & 0xffff;
2997 case BFD_RELOC_MIPS_HIGHER:
2998 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2999 ip->insn_opcode |= tmp & 0xffff;
3002 case BFD_RELOC_HI16_S:
3003 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3004 ip->insn_opcode |= tmp & 0xffff;
3007 case BFD_RELOC_HI16:
3008 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3011 case BFD_RELOC_UNUSED:
3012 case BFD_RELOC_LO16:
3013 case BFD_RELOC_MIPS_GOT_DISP:
3014 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3017 case BFD_RELOC_MIPS_JMP:
3018 if ((address_expr->X_add_number & 3) != 0)
3019 as_bad (_("jump to misaligned address (0x%lx)"),
3020 (unsigned long) address_expr->X_add_number);
3021 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3024 case BFD_RELOC_MIPS16_JMP:
3025 if ((address_expr->X_add_number & 3) != 0)
3026 as_bad (_("jump to misaligned address (0x%lx)"),
3027 (unsigned long) address_expr->X_add_number);
3029 (((address_expr->X_add_number & 0x7c0000) << 3)
3030 | ((address_expr->X_add_number & 0xf800000) >> 7)
3031 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3034 case BFD_RELOC_16_PCREL_S2:
3035 if ((address_expr->X_add_number & 3) != 0)
3036 as_bad (_("branch to misaligned address (0x%lx)"),
3037 (unsigned long) address_expr->X_add_number);
3038 if (mips_relax_branch)
3040 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3041 as_bad (_("branch address range overflow (0x%lx)"),
3042 (unsigned long) address_expr->X_add_number);
3043 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3050 else if (*reloc_type < BFD_RELOC_UNUSED)
3053 reloc_howto_type *howto;
3056 /* In a compound relocation, it is the final (outermost)
3057 operator that determines the relocated field. */
3058 for (i = 1; i < 3; i++)
3059 if (reloc_type[i] == BFD_RELOC_UNUSED)
3062 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3065 /* To reproduce this failure try assembling gas/testsuites/
3066 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3068 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3069 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3072 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3073 bfd_get_reloc_size (howto),
3075 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3078 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3079 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3080 && ip->fixp[0]->fx_addsy)
3081 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3083 /* These relocations can have an addend that won't fit in
3084 4 octets for 64bit assembly. */
3086 && ! howto->partial_inplace
3087 && (reloc_type[0] == BFD_RELOC_16
3088 || reloc_type[0] == BFD_RELOC_32
3089 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3090 || reloc_type[0] == BFD_RELOC_GPREL16
3091 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3092 || reloc_type[0] == BFD_RELOC_GPREL32
3093 || reloc_type[0] == BFD_RELOC_64
3094 || reloc_type[0] == BFD_RELOC_CTOR
3095 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3096 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3097 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3098 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3099 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3100 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3101 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3102 || hi16_reloc_p (reloc_type[0])
3103 || lo16_reloc_p (reloc_type[0])))
3104 ip->fixp[0]->fx_no_overflow = 1;
3106 if (mips_relax.sequence)
3108 if (mips_relax.first_fixup == 0)
3109 mips_relax.first_fixup = ip->fixp[0];
3111 else if (reloc_needs_lo_p (*reloc_type))
3113 struct mips_hi_fixup *hi_fixup;
3115 /* Reuse the last entry if it already has a matching %lo. */
3116 hi_fixup = mips_hi_fixup_list;
3118 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3120 hi_fixup = ((struct mips_hi_fixup *)
3121 xmalloc (sizeof (struct mips_hi_fixup)));
3122 hi_fixup->next = mips_hi_fixup_list;
3123 mips_hi_fixup_list = hi_fixup;
3125 hi_fixup->fixp = ip->fixp[0];
3126 hi_fixup->seg = now_seg;
3129 /* Add fixups for the second and third relocations, if given.
3130 Note that the ABI allows the second relocation to be
3131 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3132 moment we only use RSS_UNDEF, but we could add support
3133 for the others if it ever becomes necessary. */
3134 for (i = 1; i < 3; i++)
3135 if (reloc_type[i] != BFD_RELOC_UNUSED)
3137 ip->fixp[i] = fix_new (ip->frag, ip->where,
3138 ip->fixp[0]->fx_size, NULL, 0,
3139 FALSE, reloc_type[i]);
3141 /* Use fx_tcbit to mark compound relocs. */
3142 ip->fixp[0]->fx_tcbit = 1;
3143 ip->fixp[i]->fx_tcbit = 1;
3149 /* Update the register mask information. */
3150 if (! mips_opts.mips16)
3152 if (pinfo & INSN_WRITE_GPR_D)
3153 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3154 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3155 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3156 if (pinfo & INSN_READ_GPR_S)
3157 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3158 if (pinfo & INSN_WRITE_GPR_31)
3159 mips_gprmask |= 1 << RA;
3160 if (pinfo & INSN_WRITE_FPR_D)
3161 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3162 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3163 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3164 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3165 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3166 if ((pinfo & INSN_READ_FPR_R) != 0)
3167 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3168 if (pinfo & INSN_COP)
3170 /* We don't keep enough information to sort these cases out.
3171 The itbl support does keep this information however, although
3172 we currently don't support itbl fprmats as part of the cop
3173 instruction. May want to add this support in the future. */
3175 /* Never set the bit for $0, which is always zero. */
3176 mips_gprmask &= ~1 << 0;
3180 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3181 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3182 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3183 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3184 if (pinfo & MIPS16_INSN_WRITE_Z)
3185 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3186 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3187 mips_gprmask |= 1 << TREG;
3188 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3189 mips_gprmask |= 1 << SP;
3190 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3191 mips_gprmask |= 1 << RA;
3192 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3193 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3194 if (pinfo & MIPS16_INSN_READ_Z)
3195 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3196 if (pinfo & MIPS16_INSN_READ_GPR_X)
3197 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3200 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3202 /* Filling the branch delay slot is more complex. We try to
3203 switch the branch with the previous instruction, which we can
3204 do if the previous instruction does not set up a condition
3205 that the branch tests and if the branch is not itself the
3206 target of any branch. */
3207 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3208 || (pinfo & INSN_COND_BRANCH_DELAY))
3210 if (mips_optimize < 2
3211 /* If we have seen .set volatile or .set nomove, don't
3213 || mips_opts.nomove != 0
3214 /* We can't swap if the previous instruction's position
3216 || history[0].fixed_p
3217 /* If the previous previous insn was in a .set
3218 noreorder, we can't swap. Actually, the MIPS
3219 assembler will swap in this situation. However, gcc
3220 configured -with-gnu-as will generate code like
3226 in which we can not swap the bne and INSN. If gcc is
3227 not configured -with-gnu-as, it does not output the
3229 || history[1].noreorder_p
3230 /* If the branch is itself the target of a branch, we
3231 can not swap. We cheat on this; all we check for is
3232 whether there is a label on this instruction. If
3233 there are any branches to anything other than a
3234 label, users must use .set noreorder. */
3235 || si->label_list != NULL
3236 /* If the previous instruction is in a variant frag
3237 other than this branch's one, we cannot do the swap.
3238 This does not apply to the mips16, which uses variant
3239 frags for different purposes. */
3240 || (! mips_opts.mips16
3241 && prev_insn_frag_type == rs_machine_dependent)
3242 /* Check for conflicts between the branch and the instructions
3243 before the candidate delay slot. */
3244 || nops_for_insn (history + 1, ip) > 0
3245 /* Check for conflicts between the swapped sequence and the
3246 target of the branch. */
3247 || nops_for_sequence (2, history + 1, ip, history) > 0
3248 /* We do not swap with a trap instruction, since it
3249 complicates trap handlers to have the trap
3250 instruction be in a delay slot. */
3251 || (prev_pinfo & INSN_TRAP)
3252 /* If the branch reads a register that the previous
3253 instruction sets, we can not swap. */
3254 || (! mips_opts.mips16
3255 && (prev_pinfo & INSN_WRITE_GPR_T)
3256 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3258 || (! mips_opts.mips16
3259 && (prev_pinfo & INSN_WRITE_GPR_D)
3260 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3262 || (mips_opts.mips16
3263 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3265 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3267 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3269 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3271 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3273 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3275 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3276 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3277 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3278 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3279 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3280 && insn_uses_reg (ip,
3281 MIPS16OP_EXTRACT_REG32R
3282 (history[0].insn_opcode),
3284 /* If the branch writes a register that the previous
3285 instruction sets, we can not swap (we know that
3286 branches write only to RD or to $31). */
3287 || (! mips_opts.mips16
3288 && (prev_pinfo & INSN_WRITE_GPR_T)
3289 && (((pinfo & INSN_WRITE_GPR_D)
3290 && (EXTRACT_OPERAND (RT, history[0])
3291 == EXTRACT_OPERAND (RD, *ip)))
3292 || ((pinfo & INSN_WRITE_GPR_31)
3293 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3294 || (! mips_opts.mips16
3295 && (prev_pinfo & INSN_WRITE_GPR_D)
3296 && (((pinfo & INSN_WRITE_GPR_D)
3297 && (EXTRACT_OPERAND (RD, history[0])
3298 == EXTRACT_OPERAND (RD, *ip)))
3299 || ((pinfo & INSN_WRITE_GPR_31)
3300 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3301 || (mips_opts.mips16
3302 && (pinfo & MIPS16_INSN_WRITE_31)
3303 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3304 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3305 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3307 /* If the branch writes a register that the previous
3308 instruction reads, we can not swap (we know that
3309 branches only write to RD or to $31). */
3310 || (! mips_opts.mips16
3311 && (pinfo & INSN_WRITE_GPR_D)
3312 && insn_uses_reg (&history[0],
3313 EXTRACT_OPERAND (RD, *ip),
3315 || (! mips_opts.mips16
3316 && (pinfo & INSN_WRITE_GPR_31)
3317 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3318 || (mips_opts.mips16
3319 && (pinfo & MIPS16_INSN_WRITE_31)
3320 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3321 /* If one instruction sets a condition code and the
3322 other one uses a condition code, we can not swap. */
3323 || ((pinfo & INSN_READ_COND_CODE)
3324 && (prev_pinfo & INSN_WRITE_COND_CODE))
3325 || ((pinfo & INSN_WRITE_COND_CODE)
3326 && (prev_pinfo & INSN_READ_COND_CODE))
3327 /* If the previous instruction uses the PC, we can not
3329 || (mips_opts.mips16
3330 && (prev_pinfo & MIPS16_INSN_READ_PC))
3331 /* If the previous instruction had a fixup in mips16
3332 mode, we can not swap. This normally means that the
3333 previous instruction was a 4 byte branch anyhow. */
3334 || (mips_opts.mips16 && history[0].fixp[0])
3335 /* If the previous instruction is a sync, sync.l, or
3336 sync.p, we can not swap. */
3337 || (prev_pinfo & INSN_SYNC)
3338 /* If the previous instruction is an ERET or
3339 DERET, avoid the swap. */
3340 || (history[0].insn_opcode == INSN_ERET)
3341 || (history[0].insn_opcode == INSN_DERET))
3343 if (mips_opts.mips16
3344 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3345 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3346 && ISA_SUPPORTS_MIPS16E)
3348 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3349 ip->insn_opcode |= 0x0080;
3351 insert_into_history (0, 1, ip);
3355 /* We could do even better for unconditional branches to
3356 portions of this object file; we could pick up the
3357 instruction at the destination, put it in the delay
3358 slot, and bump the destination address. */
3359 insert_into_history (0, 1, ip);
3363 if (mips_relax.sequence)
3364 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3368 /* It looks like we can actually do the swap. */
3369 struct mips_cl_insn delay = history[0];
3370 if (mips_opts.mips16)
3372 know (delay.frag == ip->frag);
3373 move_insn (ip, delay.frag, delay.where);
3374 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3376 else if (relaxed_branch)
3378 /* Add the delay slot instruction to the end of the
3379 current frag and shrink the fixed part of the
3380 original frag. If the branch occupies the tail of
3381 the latter, move it backwards to cover the gap. */
3382 delay.frag->fr_fix -= 4;
3383 if (delay.frag == ip->frag)
3384 move_insn (ip, ip->frag, ip->where - 4);
3385 add_fixed_insn (&delay);
3389 move_insn (&delay, ip->frag, ip->where);
3390 move_insn (ip, history[0].frag, history[0].where);
3394 insert_into_history (0, 1, &delay);
3397 /* If that was an unconditional branch, forget the previous
3398 insn information. */
3399 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3401 mips_no_prev_insn ();
3404 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3406 /* We don't yet optimize a branch likely. What we should do
3407 is look at the target, copy the instruction found there
3408 into the delay slot, and increment the branch to jump to
3409 the next instruction. */
3410 insert_into_history (0, 1, ip);
3414 insert_into_history (0, 1, ip);
3417 insert_into_history (0, 1, ip);
3419 /* We just output an insn, so the next one doesn't have a label. */
3420 mips_clear_insn_labels ();
3423 /* Forget that there was any previous instruction or label. */
3426 mips_no_prev_insn (void)
3428 prev_nop_frag = NULL;
3429 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3430 mips_clear_insn_labels ();
3433 /* This function must be called before we emit something other than
3434 instructions. It is like mips_no_prev_insn except that it inserts
3435 any NOPS that might be needed by previous instructions. */
3438 mips_emit_delays (void)
3440 if (! mips_opts.noreorder)
3442 int nops = nops_for_insn (history, NULL);
3446 add_fixed_insn (NOP_INSN);
3447 mips_move_labels ();
3450 mips_no_prev_insn ();
3453 /* Start a (possibly nested) noreorder block. */
3456 start_noreorder (void)
3458 if (mips_opts.noreorder == 0)
3463 /* None of the instructions before the .set noreorder can be moved. */
3464 for (i = 0; i < ARRAY_SIZE (history); i++)
3465 history[i].fixed_p = 1;
3467 /* Insert any nops that might be needed between the .set noreorder
3468 block and the previous instructions. We will later remove any
3469 nops that turn out not to be needed. */
3470 nops = nops_for_insn (history, NULL);
3473 if (mips_optimize != 0)
3475 /* Record the frag which holds the nop instructions, so
3476 that we can remove them if we don't need them. */
3477 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3478 prev_nop_frag = frag_now;
3479 prev_nop_frag_holds = nops;
3480 prev_nop_frag_required = 0;
3481 prev_nop_frag_since = 0;
3484 for (; nops > 0; --nops)
3485 add_fixed_insn (NOP_INSN);
3487 /* Move on to a new frag, so that it is safe to simply
3488 decrease the size of prev_nop_frag. */
3489 frag_wane (frag_now);
3491 mips_move_labels ();
3493 mips16_mark_labels ();
3494 mips_clear_insn_labels ();
3496 mips_opts.noreorder++;
3497 mips_any_noreorder = 1;
3500 /* End a nested noreorder block. */
3503 end_noreorder (void)
3506 mips_opts.noreorder--;
3507 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3509 /* Commit to inserting prev_nop_frag_required nops and go back to
3510 handling nop insertion the .set reorder way. */
3511 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3512 * (mips_opts.mips16 ? 2 : 4));
3513 insert_into_history (prev_nop_frag_since,
3514 prev_nop_frag_required, NOP_INSN);
3515 prev_nop_frag = NULL;
3519 /* Set up global variables for the start of a new macro. */
3524 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3525 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3526 && (history[0].insn_mo->pinfo
3527 & (INSN_UNCOND_BRANCH_DELAY
3528 | INSN_COND_BRANCH_DELAY
3529 | INSN_COND_BRANCH_LIKELY)) != 0);
3532 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3533 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3534 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3537 macro_warning (relax_substateT subtype)
3539 if (subtype & RELAX_DELAY_SLOT)
3540 return _("Macro instruction expanded into multiple instructions"
3541 " in a branch delay slot");
3542 else if (subtype & RELAX_NOMACRO)
3543 return _("Macro instruction expanded into multiple instructions");
3548 /* Finish up a macro. Emit warnings as appropriate. */
3553 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3555 relax_substateT subtype;
3557 /* Set up the relaxation warning flags. */
3559 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3560 subtype |= RELAX_SECOND_LONGER;
3561 if (mips_opts.warn_about_macros)
3562 subtype |= RELAX_NOMACRO;
3563 if (mips_macro_warning.delay_slot_p)
3564 subtype |= RELAX_DELAY_SLOT;
3566 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3568 /* Either the macro has a single implementation or both
3569 implementations are longer than 4 bytes. Emit the
3571 const char *msg = macro_warning (subtype);
3573 as_warn ("%s", msg);
3577 /* One implementation might need a warning but the other
3578 definitely doesn't. */
3579 mips_macro_warning.first_frag->fr_subtype |= subtype;
3584 /* Read a macro's relocation codes from *ARGS and store them in *R.
3585 The first argument in *ARGS will be either the code for a single
3586 relocation or -1 followed by the three codes that make up a
3587 composite relocation. */
3590 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3594 next = va_arg (*args, int);
3596 r[0] = (bfd_reloc_code_real_type) next;
3598 for (i = 0; i < 3; i++)
3599 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3602 /* Build an instruction created by a macro expansion. This is passed
3603 a pointer to the count of instructions created so far, an
3604 expression, the name of the instruction to build, an operand format
3605 string, and corresponding arguments. */
3608 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3610 const struct mips_opcode *mo;
3611 struct mips_cl_insn insn;
3612 bfd_reloc_code_real_type r[3];
3615 va_start (args, fmt);
3617 if (mips_opts.mips16)
3619 mips16_macro_build (ep, name, fmt, &args);
3624 r[0] = BFD_RELOC_UNUSED;
3625 r[1] = BFD_RELOC_UNUSED;
3626 r[2] = BFD_RELOC_UNUSED;
3627 mo = (struct mips_opcode *) hash_find (op_hash, name);
3629 gas_assert (strcmp (name, mo->name) == 0);
3633 /* Search until we get a match for NAME. It is assumed here that
3634 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3635 if (strcmp (fmt, mo->args) == 0
3636 && mo->pinfo != INSN_MACRO
3637 && is_opcode_valid (mo))
3641 gas_assert (mo->name);
3642 gas_assert (strcmp (name, mo->name) == 0);
3645 create_insn (&insn, mo);
3663 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3668 /* Note that in the macro case, these arguments are already
3669 in MSB form. (When handling the instruction in the
3670 non-macro case, these arguments are sizes from which
3671 MSB values must be calculated.) */
3672 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3678 /* Note that in the macro case, these arguments are already
3679 in MSBD form. (When handling the instruction in the
3680 non-macro case, these arguments are sizes from which
3681 MSBD values must be calculated.) */
3682 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3686 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3695 INSERT_OPERAND (BP, insn, va_arg (args, int));
3701 INSERT_OPERAND (RT, insn, va_arg (args, int));
3705 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3710 INSERT_OPERAND (FT, insn, va_arg (args, int));
3716 INSERT_OPERAND (RD, insn, va_arg (args, int));
3721 int tmp = va_arg (args, int);
3723 INSERT_OPERAND (RT, insn, tmp);
3724 INSERT_OPERAND (RD, insn, tmp);
3730 INSERT_OPERAND (FS, insn, va_arg (args, int));
3737 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3741 INSERT_OPERAND (FD, insn, va_arg (args, int));
3745 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3749 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3753 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3760 INSERT_OPERAND (RS, insn, va_arg (args, int));
3766 macro_read_relocs (&args, r);
3767 gas_assert (*r == BFD_RELOC_GPREL16
3768 || *r == BFD_RELOC_MIPS_LITERAL
3769 || *r == BFD_RELOC_MIPS_HIGHER
3770 || *r == BFD_RELOC_HI16_S
3771 || *r == BFD_RELOC_LO16
3772 || *r == BFD_RELOC_MIPS_GOT16
3773 || *r == BFD_RELOC_MIPS_CALL16
3774 || *r == BFD_RELOC_MIPS_GOT_DISP
3775 || *r == BFD_RELOC_MIPS_GOT_PAGE
3776 || *r == BFD_RELOC_MIPS_GOT_OFST
3777 || *r == BFD_RELOC_MIPS_GOT_LO16
3778 || *r == BFD_RELOC_MIPS_CALL_LO16);
3782 macro_read_relocs (&args, r);
3783 gas_assert (ep != NULL
3784 && (ep->X_op == O_constant
3785 || (ep->X_op == O_symbol
3786 && (*r == BFD_RELOC_MIPS_HIGHEST
3787 || *r == BFD_RELOC_HI16_S
3788 || *r == BFD_RELOC_HI16
3789 || *r == BFD_RELOC_GPREL16
3790 || *r == BFD_RELOC_MIPS_GOT_HI16
3791 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3795 gas_assert (ep != NULL);
3798 * This allows macro() to pass an immediate expression for
3799 * creating short branches without creating a symbol.
3801 * We don't allow branch relaxation for these branches, as
3802 * they should only appear in ".set nomacro" anyway.
3804 if (ep->X_op == O_constant)
3806 if ((ep->X_add_number & 3) != 0)
3807 as_bad (_("branch to misaligned address (0x%lx)"),
3808 (unsigned long) ep->X_add_number);
3809 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3810 as_bad (_("branch address range overflow (0x%lx)"),
3811 (unsigned long) ep->X_add_number);
3812 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3816 *r = BFD_RELOC_16_PCREL_S2;
3820 gas_assert (ep != NULL);
3821 *r = BFD_RELOC_MIPS_JMP;
3825 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3829 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3838 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3840 append_insn (&insn, ep, r);
3844 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3847 struct mips_opcode *mo;
3848 struct mips_cl_insn insn;
3849 bfd_reloc_code_real_type r[3]
3850 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3852 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3854 gas_assert (strcmp (name, mo->name) == 0);
3856 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3859 gas_assert (mo->name);
3860 gas_assert (strcmp (name, mo->name) == 0);
3863 create_insn (&insn, mo);
3881 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
3886 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
3890 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
3894 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
3904 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
3911 regno = va_arg (*args, int);
3912 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3913 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3934 gas_assert (ep != NULL);
3936 if (ep->X_op != O_constant)
3937 *r = (int) BFD_RELOC_UNUSED + c;
3940 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3941 FALSE, &insn.insn_opcode, &insn.use_extend,
3944 *r = BFD_RELOC_UNUSED;
3950 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
3957 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3959 append_insn (&insn, ep, r);
3963 * Sign-extend 32-bit mode constants that have bit 31 set and all
3964 * higher bits unset.
3967 normalize_constant_expr (expressionS *ex)
3969 if (ex->X_op == O_constant
3970 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3971 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3976 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3977 * all higher bits unset.
3980 normalize_address_expr (expressionS *ex)
3982 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3983 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3984 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3985 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3990 * Generate a "jalr" instruction with a relocation hint to the called
3991 * function. This occurs in NewABI PIC code.
3994 macro_build_jalr (expressionS *ep)
3998 if (MIPS_JALR_HINT_P (ep))
4003 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4004 if (MIPS_JALR_HINT_P (ep))
4005 fix_new_exp (frag_now, f - frag_now->fr_literal,
4006 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4010 * Generate a "lui" instruction.
4013 macro_build_lui (expressionS *ep, int regnum)
4015 expressionS high_expr;
4016 const struct mips_opcode *mo;
4017 struct mips_cl_insn insn;
4018 bfd_reloc_code_real_type r[3]
4019 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4020 const char *name = "lui";
4021 const char *fmt = "t,u";
4023 gas_assert (! mips_opts.mips16);
4027 if (high_expr.X_op == O_constant)
4029 /* We can compute the instruction now without a relocation entry. */
4030 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4032 *r = BFD_RELOC_UNUSED;
4036 gas_assert (ep->X_op == O_symbol);
4037 /* _gp_disp is a special case, used from s_cpload.
4038 __gnu_local_gp is used if mips_no_shared. */
4039 gas_assert (mips_pic == NO_PIC
4041 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4042 || (! mips_in_shared
4043 && strcmp (S_GET_NAME (ep->X_add_symbol),
4044 "__gnu_local_gp") == 0));
4045 *r = BFD_RELOC_HI16_S;
4048 mo = hash_find (op_hash, name);
4049 gas_assert (strcmp (name, mo->name) == 0);
4050 gas_assert (strcmp (fmt, mo->args) == 0);
4051 create_insn (&insn, mo);
4053 insn.insn_opcode = insn.insn_mo->match;
4054 INSERT_OPERAND (RT, insn, regnum);
4055 if (*r == BFD_RELOC_UNUSED)
4057 insn.insn_opcode |= high_expr.X_add_number;
4058 append_insn (&insn, NULL, r);
4061 append_insn (&insn, &high_expr, r);
4064 /* Generate a sequence of instructions to do a load or store from a constant
4065 offset off of a base register (breg) into/from a target register (treg),
4066 using AT if necessary. */
4068 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4069 int treg, int breg, int dbl)
4071 gas_assert (ep->X_op == O_constant);
4073 /* Sign-extending 32-bit constants makes their handling easier. */
4075 normalize_constant_expr (ep);
4077 /* Right now, this routine can only handle signed 32-bit constants. */
4078 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4079 as_warn (_("operand overflow"));
4081 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4083 /* Signed 16-bit offset will fit in the op. Easy! */
4084 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4088 /* 32-bit offset, need multiple instructions and AT, like:
4089 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4090 addu $tempreg,$tempreg,$breg
4091 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4092 to handle the complete offset. */
4093 macro_build_lui (ep, AT);
4094 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4095 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4098 as_bad (_("Macro used $at after \".set noat\""));
4103 * Generates code to set the $at register to true (one)
4104 * if reg is less than the immediate expression.
4107 set_at (int reg, int unsignedp)
4109 if (imm_expr.X_op == O_constant
4110 && imm_expr.X_add_number >= -0x8000
4111 && imm_expr.X_add_number < 0x8000)
4112 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4113 AT, reg, BFD_RELOC_LO16);
4116 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4117 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4121 /* Warn if an expression is not a constant. */
4124 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4126 if (ex->X_op == O_big)
4127 as_bad (_("unsupported large constant"));
4128 else if (ex->X_op != O_constant)
4129 as_bad (_("Instruction %s requires absolute expression"),
4132 if (HAVE_32BIT_GPRS)
4133 normalize_constant_expr (ex);
4136 /* Count the leading zeroes by performing a binary chop. This is a
4137 bulky bit of source, but performance is a LOT better for the
4138 majority of values than a simple loop to count the bits:
4139 for (lcnt = 0; (lcnt < 32); lcnt++)
4140 if ((v) & (1 << (31 - lcnt)))
4142 However it is not code size friendly, and the gain will drop a bit
4143 on certain cached systems.
4145 #define COUNT_TOP_ZEROES(v) \
4146 (((v) & ~0xffff) == 0 \
4147 ? ((v) & ~0xff) == 0 \
4148 ? ((v) & ~0xf) == 0 \
4149 ? ((v) & ~0x3) == 0 \
4150 ? ((v) & ~0x1) == 0 \
4155 : ((v) & ~0x7) == 0 \
4158 : ((v) & ~0x3f) == 0 \
4159 ? ((v) & ~0x1f) == 0 \
4162 : ((v) & ~0x7f) == 0 \
4165 : ((v) & ~0xfff) == 0 \
4166 ? ((v) & ~0x3ff) == 0 \
4167 ? ((v) & ~0x1ff) == 0 \
4170 : ((v) & ~0x7ff) == 0 \
4173 : ((v) & ~0x3fff) == 0 \
4174 ? ((v) & ~0x1fff) == 0 \
4177 : ((v) & ~0x7fff) == 0 \
4180 : ((v) & ~0xffffff) == 0 \
4181 ? ((v) & ~0xfffff) == 0 \
4182 ? ((v) & ~0x3ffff) == 0 \
4183 ? ((v) & ~0x1ffff) == 0 \
4186 : ((v) & ~0x7ffff) == 0 \
4189 : ((v) & ~0x3fffff) == 0 \
4190 ? ((v) & ~0x1fffff) == 0 \
4193 : ((v) & ~0x7fffff) == 0 \
4196 : ((v) & ~0xfffffff) == 0 \
4197 ? ((v) & ~0x3ffffff) == 0 \
4198 ? ((v) & ~0x1ffffff) == 0 \
4201 : ((v) & ~0x7ffffff) == 0 \
4204 : ((v) & ~0x3fffffff) == 0 \
4205 ? ((v) & ~0x1fffffff) == 0 \
4208 : ((v) & ~0x7fffffff) == 0 \
4213 * This routine generates the least number of instructions necessary to load
4214 * an absolute expression value into a register.
4217 load_register (int reg, expressionS *ep, int dbl)
4220 expressionS hi32, lo32;
4222 if (ep->X_op != O_big)
4224 gas_assert (ep->X_op == O_constant);
4226 /* Sign-extending 32-bit constants makes their handling easier. */
4228 normalize_constant_expr (ep);
4230 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4232 /* We can handle 16 bit signed values with an addiu to
4233 $zero. No need to ever use daddiu here, since $zero and
4234 the result are always correct in 32 bit mode. */
4235 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4238 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4240 /* We can handle 16 bit unsigned values with an ori to
4242 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4245 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4247 /* 32 bit values require an lui. */
4248 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4249 if ((ep->X_add_number & 0xffff) != 0)
4250 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4255 /* The value is larger than 32 bits. */
4257 if (!dbl || HAVE_32BIT_GPRS)
4261 sprintf_vma (value, ep->X_add_number);
4262 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4263 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4267 if (ep->X_op != O_big)
4270 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4271 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4272 hi32.X_add_number &= 0xffffffff;
4274 lo32.X_add_number &= 0xffffffff;
4278 gas_assert (ep->X_add_number > 2);
4279 if (ep->X_add_number == 3)
4280 generic_bignum[3] = 0;
4281 else if (ep->X_add_number > 4)
4282 as_bad (_("Number larger than 64 bits"));
4283 lo32.X_op = O_constant;
4284 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4285 hi32.X_op = O_constant;
4286 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4289 if (hi32.X_add_number == 0)
4294 unsigned long hi, lo;
4296 if (hi32.X_add_number == (offsetT) 0xffffffff)
4298 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4300 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4303 if (lo32.X_add_number & 0x80000000)
4305 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4306 if (lo32.X_add_number & 0xffff)
4307 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4312 /* Check for 16bit shifted constant. We know that hi32 is
4313 non-zero, so start the mask on the first bit of the hi32
4318 unsigned long himask, lomask;
4322 himask = 0xffff >> (32 - shift);
4323 lomask = (0xffff << shift) & 0xffffffff;
4327 himask = 0xffff << (shift - 32);
4330 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4331 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4335 tmp.X_op = O_constant;
4337 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4338 | (lo32.X_add_number >> shift));
4340 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4341 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4342 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4343 reg, reg, (shift >= 32) ? shift - 32 : shift);
4348 while (shift <= (64 - 16));
4350 /* Find the bit number of the lowest one bit, and store the
4351 shifted value in hi/lo. */
4352 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4353 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4357 while ((lo & 1) == 0)
4362 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4368 while ((hi & 1) == 0)
4377 /* Optimize if the shifted value is a (power of 2) - 1. */
4378 if ((hi == 0 && ((lo + 1) & lo) == 0)
4379 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4381 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4386 /* This instruction will set the register to be all
4388 tmp.X_op = O_constant;
4389 tmp.X_add_number = (offsetT) -1;
4390 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4394 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4395 reg, reg, (bit >= 32) ? bit - 32 : bit);
4397 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4398 reg, reg, (shift >= 32) ? shift - 32 : shift);
4403 /* Sign extend hi32 before calling load_register, because we can
4404 generally get better code when we load a sign extended value. */
4405 if ((hi32.X_add_number & 0x80000000) != 0)
4406 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4407 load_register (reg, &hi32, 0);
4410 if ((lo32.X_add_number & 0xffff0000) == 0)
4414 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4422 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4424 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4425 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4431 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4435 mid16.X_add_number >>= 16;
4436 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4437 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4440 if ((lo32.X_add_number & 0xffff) != 0)
4441 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4445 load_delay_nop (void)
4447 if (!gpr_interlocks)
4448 macro_build (NULL, "nop", "");
4451 /* Load an address into a register. */
4454 load_address (int reg, expressionS *ep, int *used_at)
4456 if (ep->X_op != O_constant
4457 && ep->X_op != O_symbol)
4459 as_bad (_("expression too complex"));
4460 ep->X_op = O_constant;
4463 if (ep->X_op == O_constant)
4465 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4469 if (mips_pic == NO_PIC)
4471 /* If this is a reference to a GP relative symbol, we want
4472 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4474 lui $reg,<sym> (BFD_RELOC_HI16_S)
4475 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4476 If we have an addend, we always use the latter form.
4478 With 64bit address space and a usable $at we want
4479 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4480 lui $at,<sym> (BFD_RELOC_HI16_S)
4481 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4482 daddiu $at,<sym> (BFD_RELOC_LO16)
4486 If $at is already in use, we use a path which is suboptimal
4487 on superscalar processors.
4488 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4489 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4491 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4493 daddiu $reg,<sym> (BFD_RELOC_LO16)
4495 For GP relative symbols in 64bit address space we can use
4496 the same sequence as in 32bit address space. */
4497 if (HAVE_64BIT_SYMBOLS)
4499 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4500 && !nopic_need_relax (ep->X_add_symbol, 1))
4502 relax_start (ep->X_add_symbol);
4503 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4504 mips_gp_register, BFD_RELOC_GPREL16);
4508 if (*used_at == 0 && mips_opts.at)
4510 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4511 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4512 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4513 BFD_RELOC_MIPS_HIGHER);
4514 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4515 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4516 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4521 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4522 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4523 BFD_RELOC_MIPS_HIGHER);
4524 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4525 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4526 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4527 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4530 if (mips_relax.sequence)
4535 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4536 && !nopic_need_relax (ep->X_add_symbol, 1))
4538 relax_start (ep->X_add_symbol);
4539 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4540 mips_gp_register, BFD_RELOC_GPREL16);
4543 macro_build_lui (ep, reg);
4544 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4545 reg, reg, BFD_RELOC_LO16);
4546 if (mips_relax.sequence)
4550 else if (!mips_big_got)
4554 /* If this is a reference to an external symbol, we want
4555 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4557 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4559 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4560 If there is a constant, it must be added in after.
4562 If we have NewABI, we want
4563 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4564 unless we're referencing a global symbol with a non-zero
4565 offset, in which case cst must be added separately. */
4568 if (ep->X_add_number)
4570 ex.X_add_number = ep->X_add_number;
4571 ep->X_add_number = 0;
4572 relax_start (ep->X_add_symbol);
4573 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4574 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4575 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4576 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4577 ex.X_op = O_constant;
4578 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4579 reg, reg, BFD_RELOC_LO16);
4580 ep->X_add_number = ex.X_add_number;
4583 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4584 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4585 if (mips_relax.sequence)
4590 ex.X_add_number = ep->X_add_number;
4591 ep->X_add_number = 0;
4592 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4593 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4595 relax_start (ep->X_add_symbol);
4597 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4601 if (ex.X_add_number != 0)
4603 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4604 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4605 ex.X_op = O_constant;
4606 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4607 reg, reg, BFD_RELOC_LO16);
4611 else if (mips_big_got)
4615 /* This is the large GOT case. If this is a reference to an
4616 external symbol, we want
4617 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4619 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4621 Otherwise, for a reference to a local symbol in old ABI, we want
4622 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4624 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4625 If there is a constant, it must be added in after.
4627 In the NewABI, for local symbols, with or without offsets, we want:
4628 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4629 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4633 ex.X_add_number = ep->X_add_number;
4634 ep->X_add_number = 0;
4635 relax_start (ep->X_add_symbol);
4636 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4637 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4638 reg, reg, mips_gp_register);
4639 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4640 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4641 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4642 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4643 else if (ex.X_add_number)
4645 ex.X_op = O_constant;
4646 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4650 ep->X_add_number = ex.X_add_number;
4652 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4653 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4654 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4655 BFD_RELOC_MIPS_GOT_OFST);
4660 ex.X_add_number = ep->X_add_number;
4661 ep->X_add_number = 0;
4662 relax_start (ep->X_add_symbol);
4663 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4664 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4665 reg, reg, mips_gp_register);
4666 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4667 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4669 if (reg_needs_delay (mips_gp_register))
4671 /* We need a nop before loading from $gp. This special
4672 check is required because the lui which starts the main
4673 instruction stream does not refer to $gp, and so will not
4674 insert the nop which may be required. */
4675 macro_build (NULL, "nop", "");
4677 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4678 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4680 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4684 if (ex.X_add_number != 0)
4686 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4687 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4688 ex.X_op = O_constant;
4689 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4697 if (!mips_opts.at && *used_at == 1)
4698 as_bad (_("Macro used $at after \".set noat\""));
4701 /* Move the contents of register SOURCE into register DEST. */
4704 move_register (int dest, int source)
4706 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4710 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4711 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4712 The two alternatives are:
4714 Global symbol Local sybmol
4715 ------------- ------------
4716 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4718 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4720 load_got_offset emits the first instruction and add_got_offset
4721 emits the second for a 16-bit offset or add_got_offset_hilo emits
4722 a sequence to add a 32-bit offset using a scratch register. */
4725 load_got_offset (int dest, expressionS *local)
4730 global.X_add_number = 0;
4732 relax_start (local->X_add_symbol);
4733 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4734 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4736 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4737 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4742 add_got_offset (int dest, expressionS *local)
4746 global.X_op = O_constant;
4747 global.X_op_symbol = NULL;
4748 global.X_add_symbol = NULL;
4749 global.X_add_number = local->X_add_number;
4751 relax_start (local->X_add_symbol);
4752 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4753 dest, dest, BFD_RELOC_LO16);
4755 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4760 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4763 int hold_mips_optimize;
4765 global.X_op = O_constant;
4766 global.X_op_symbol = NULL;
4767 global.X_add_symbol = NULL;
4768 global.X_add_number = local->X_add_number;
4770 relax_start (local->X_add_symbol);
4771 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4773 /* Set mips_optimize around the lui instruction to avoid
4774 inserting an unnecessary nop after the lw. */
4775 hold_mips_optimize = mips_optimize;
4777 macro_build_lui (&global, tmp);
4778 mips_optimize = hold_mips_optimize;
4779 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4787 * This routine implements the seemingly endless macro or synthesized
4788 * instructions and addressing modes in the mips assembly language. Many
4789 * of these macros are simple and are similar to each other. These could
4790 * probably be handled by some kind of table or grammar approach instead of
4791 * this verbose method. Others are not simple macros but are more like
4792 * optimizing code generation.
4793 * One interesting optimization is when several store macros appear
4794 * consecutively that would load AT with the upper half of the same address.
4795 * The ensuing load upper instructions are ommited. This implies some kind
4796 * of global optimization. We currently only optimize within a single macro.
4797 * For many of the load and store macros if the address is specified as a
4798 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4799 * first load register 'at' with zero and use it as the base register. The
4800 * mips assembler simply uses register $zero. Just one tiny optimization
4804 macro (struct mips_cl_insn *ip)
4806 unsigned int treg, sreg, dreg, breg;
4807 unsigned int tempreg;
4822 bfd_reloc_code_real_type r;
4823 int hold_mips_optimize;
4825 gas_assert (! mips_opts.mips16);
4827 treg = (ip->insn_opcode >> 16) & 0x1f;
4828 dreg = (ip->insn_opcode >> 11) & 0x1f;
4829 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4830 mask = ip->insn_mo->mask;
4832 expr1.X_op = O_constant;
4833 expr1.X_op_symbol = NULL;
4834 expr1.X_add_symbol = NULL;
4835 expr1.X_add_number = 1;
4849 expr1.X_add_number = 8;
4850 macro_build (&expr1, "bgez", "s,p", sreg);
4852 macro_build (NULL, "nop", "", 0);
4854 move_register (dreg, sreg);
4855 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4878 if (imm_expr.X_op == O_constant
4879 && imm_expr.X_add_number >= -0x8000
4880 && imm_expr.X_add_number < 0x8000)
4882 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4886 load_register (AT, &imm_expr, dbl);
4887 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4906 if (imm_expr.X_op == O_constant
4907 && imm_expr.X_add_number >= 0
4908 && imm_expr.X_add_number < 0x10000)
4910 if (mask != M_NOR_I)
4911 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4914 macro_build (&imm_expr, "ori", "t,r,i",
4915 treg, sreg, BFD_RELOC_LO16);
4916 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4922 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4923 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4927 switch (imm_expr.X_add_number)
4930 macro_build (NULL, "nop", "");
4933 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4936 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4937 (int)imm_expr.X_add_number);
4956 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4958 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4962 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4963 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4971 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4976 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4980 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4981 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4987 /* check for > max integer */
4988 maxnum = 0x7fffffff;
4989 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4996 if (imm_expr.X_op == O_constant
4997 && imm_expr.X_add_number >= maxnum
4998 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5001 /* result is always false */
5003 macro_build (NULL, "nop", "", 0);
5005 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
5008 if (imm_expr.X_op != O_constant)
5009 as_bad (_("Unsupported large constant"));
5010 ++imm_expr.X_add_number;
5014 if (mask == M_BGEL_I)
5016 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5018 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5021 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5023 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5026 maxnum = 0x7fffffff;
5027 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5034 maxnum = - maxnum - 1;
5035 if (imm_expr.X_op == O_constant
5036 && imm_expr.X_add_number <= maxnum
5037 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5040 /* result is always true */
5041 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5042 macro_build (&offset_expr, "b", "p");
5047 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5057 macro_build (&offset_expr, likely ? "beql" : "beq",
5062 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5063 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5071 && imm_expr.X_op == O_constant
5072 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5074 if (imm_expr.X_op != O_constant)
5075 as_bad (_("Unsupported large constant"));
5076 ++imm_expr.X_add_number;
5080 if (mask == M_BGEUL_I)
5082 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5084 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5086 macro_build (&offset_expr, likely ? "bnel" : "bne",
5092 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5100 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5105 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5109 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5110 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5118 macro_build (&offset_expr, likely ? "bnel" : "bne",
5125 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5126 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5134 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5139 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5143 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5144 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5150 maxnum = 0x7fffffff;
5151 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5158 if (imm_expr.X_op == O_constant
5159 && imm_expr.X_add_number >= maxnum
5160 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5162 if (imm_expr.X_op != O_constant)
5163 as_bad (_("Unsupported large constant"));
5164 ++imm_expr.X_add_number;
5168 if (mask == M_BLTL_I)
5170 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5172 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5175 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5177 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5182 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5190 macro_build (&offset_expr, likely ? "beql" : "beq",
5197 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5198 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5206 && imm_expr.X_op == O_constant
5207 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5209 if (imm_expr.X_op != O_constant)
5210 as_bad (_("Unsupported large constant"));
5211 ++imm_expr.X_add_number;
5215 if (mask == M_BLTUL_I)
5217 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5219 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5221 macro_build (&offset_expr, likely ? "beql" : "beq",
5227 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5235 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5240 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5244 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5245 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5255 macro_build (&offset_expr, likely ? "bnel" : "bne",
5260 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5261 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5269 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5271 as_bad (_("Unsupported large constant"));
5276 pos = (unsigned long) imm_expr.X_add_number;
5277 size = (unsigned long) imm2_expr.X_add_number;
5282 as_bad (_("Improper position (%lu)"), pos);
5285 if (size == 0 || size > 64
5286 || (pos + size - 1) > 63)
5288 as_bad (_("Improper extract size (%lu, position %lu)"),
5293 if (size <= 32 && pos < 32)
5298 else if (size <= 32)
5308 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5317 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5319 as_bad (_("Unsupported large constant"));
5324 pos = (unsigned long) imm_expr.X_add_number;
5325 size = (unsigned long) imm2_expr.X_add_number;
5330 as_bad (_("Improper position (%lu)"), pos);
5333 if (size == 0 || size > 64
5334 || (pos + size - 1) > 63)
5336 as_bad (_("Improper insert size (%lu, position %lu)"),
5341 if (pos < 32 && (pos + size - 1) < 32)
5356 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5357 (int) (pos + size - 1));
5373 as_warn (_("Divide by zero."));
5375 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5377 macro_build (NULL, "break", "c", 7);
5384 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5385 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5389 expr1.X_add_number = 8;
5390 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5391 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5392 macro_build (NULL, "break", "c", 7);
5394 expr1.X_add_number = -1;
5396 load_register (AT, &expr1, dbl);
5397 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5398 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5401 expr1.X_add_number = 1;
5402 load_register (AT, &expr1, dbl);
5403 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5407 expr1.X_add_number = 0x80000000;
5408 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5412 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5413 /* We want to close the noreorder block as soon as possible, so
5414 that later insns are available for delay slot filling. */
5419 expr1.X_add_number = 8;
5420 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5421 macro_build (NULL, "nop", "", 0);
5423 /* We want to close the noreorder block as soon as possible, so
5424 that later insns are available for delay slot filling. */
5427 macro_build (NULL, "break", "c", 6);
5429 macro_build (NULL, s, "d", dreg);
5468 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5470 as_warn (_("Divide by zero."));
5472 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5474 macro_build (NULL, "break", "c", 7);
5477 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5479 if (strcmp (s2, "mflo") == 0)
5480 move_register (dreg, sreg);
5482 move_register (dreg, 0);
5485 if (imm_expr.X_op == O_constant
5486 && imm_expr.X_add_number == -1
5487 && s[strlen (s) - 1] != 'u')
5489 if (strcmp (s2, "mflo") == 0)
5491 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5494 move_register (dreg, 0);
5499 load_register (AT, &imm_expr, dbl);
5500 macro_build (NULL, s, "z,s,t", sreg, AT);
5501 macro_build (NULL, s2, "d", dreg);
5523 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5524 macro_build (NULL, s, "z,s,t", sreg, treg);
5525 /* We want to close the noreorder block as soon as possible, so
5526 that later insns are available for delay slot filling. */
5531 expr1.X_add_number = 8;
5532 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5533 macro_build (NULL, s, "z,s,t", sreg, treg);
5535 /* We want to close the noreorder block as soon as possible, so
5536 that later insns are available for delay slot filling. */
5538 macro_build (NULL, "break", "c", 7);
5540 macro_build (NULL, s2, "d", dreg);
5552 /* Load the address of a symbol into a register. If breg is not
5553 zero, we then add a base register to it. */
5555 if (dbl && HAVE_32BIT_GPRS)
5556 as_warn (_("dla used to load 32-bit register"));
5558 if (! dbl && HAVE_64BIT_OBJECTS)
5559 as_warn (_("la used to load 64-bit address"));
5561 if (offset_expr.X_op == O_constant
5562 && offset_expr.X_add_number >= -0x8000
5563 && offset_expr.X_add_number < 0x8000)
5565 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5566 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5570 if (mips_opts.at && (treg == breg))
5580 if (offset_expr.X_op != O_symbol
5581 && offset_expr.X_op != O_constant)
5583 as_bad (_("expression too complex"));
5584 offset_expr.X_op = O_constant;
5587 if (offset_expr.X_op == O_constant)
5588 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5589 else if (mips_pic == NO_PIC)
5591 /* If this is a reference to a GP relative symbol, we want
5592 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5594 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5595 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5596 If we have a constant, we need two instructions anyhow,
5597 so we may as well always use the latter form.
5599 With 64bit address space and a usable $at we want
5600 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5601 lui $at,<sym> (BFD_RELOC_HI16_S)
5602 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5603 daddiu $at,<sym> (BFD_RELOC_LO16)
5605 daddu $tempreg,$tempreg,$at
5607 If $at is already in use, we use a path which is suboptimal
5608 on superscalar processors.
5609 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5610 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5612 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5614 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5616 For GP relative symbols in 64bit address space we can use
5617 the same sequence as in 32bit address space. */
5618 if (HAVE_64BIT_SYMBOLS)
5620 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5621 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5623 relax_start (offset_expr.X_add_symbol);
5624 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5625 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5629 if (used_at == 0 && mips_opts.at)
5631 macro_build (&offset_expr, "lui", "t,u",
5632 tempreg, BFD_RELOC_MIPS_HIGHEST);
5633 macro_build (&offset_expr, "lui", "t,u",
5634 AT, BFD_RELOC_HI16_S);
5635 macro_build (&offset_expr, "daddiu", "t,r,j",
5636 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5637 macro_build (&offset_expr, "daddiu", "t,r,j",
5638 AT, AT, BFD_RELOC_LO16);
5639 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5640 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5645 macro_build (&offset_expr, "lui", "t,u",
5646 tempreg, BFD_RELOC_MIPS_HIGHEST);
5647 macro_build (&offset_expr, "daddiu", "t,r,j",
5648 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5649 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5650 macro_build (&offset_expr, "daddiu", "t,r,j",
5651 tempreg, tempreg, BFD_RELOC_HI16_S);
5652 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5653 macro_build (&offset_expr, "daddiu", "t,r,j",
5654 tempreg, tempreg, BFD_RELOC_LO16);
5657 if (mips_relax.sequence)
5662 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5663 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5665 relax_start (offset_expr.X_add_symbol);
5666 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5667 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5670 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5671 as_bad (_("offset too large"));
5672 macro_build_lui (&offset_expr, tempreg);
5673 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5674 tempreg, tempreg, BFD_RELOC_LO16);
5675 if (mips_relax.sequence)
5679 else if (!mips_big_got && !HAVE_NEWABI)
5681 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5683 /* If this is a reference to an external symbol, and there
5684 is no constant, we want
5685 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5686 or for lca or if tempreg is PIC_CALL_REG
5687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5688 For a local symbol, we want
5689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5691 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5693 If we have a small constant, and this is a reference to
5694 an external symbol, we want
5695 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5697 addiu $tempreg,$tempreg,<constant>
5698 For a local symbol, we want the same instruction
5699 sequence, but we output a BFD_RELOC_LO16 reloc on the
5702 If we have a large constant, and this is a reference to
5703 an external symbol, we want
5704 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5705 lui $at,<hiconstant>
5706 addiu $at,$at,<loconstant>
5707 addu $tempreg,$tempreg,$at
5708 For a local symbol, we want the same instruction
5709 sequence, but we output a BFD_RELOC_LO16 reloc on the
5713 if (offset_expr.X_add_number == 0)
5715 if (mips_pic == SVR4_PIC
5717 && (call || tempreg == PIC_CALL_REG))
5718 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5720 relax_start (offset_expr.X_add_symbol);
5721 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5722 lw_reloc_type, mips_gp_register);
5725 /* We're going to put in an addu instruction using
5726 tempreg, so we may as well insert the nop right
5731 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5732 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5734 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5735 tempreg, tempreg, BFD_RELOC_LO16);
5737 /* FIXME: If breg == 0, and the next instruction uses
5738 $tempreg, then if this variant case is used an extra
5739 nop will be generated. */
5741 else if (offset_expr.X_add_number >= -0x8000
5742 && offset_expr.X_add_number < 0x8000)
5744 load_got_offset (tempreg, &offset_expr);
5746 add_got_offset (tempreg, &offset_expr);
5750 expr1.X_add_number = offset_expr.X_add_number;
5751 offset_expr.X_add_number =
5752 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5753 load_got_offset (tempreg, &offset_expr);
5754 offset_expr.X_add_number = expr1.X_add_number;
5755 /* If we are going to add in a base register, and the
5756 target register and the base register are the same,
5757 then we are using AT as a temporary register. Since
5758 we want to load the constant into AT, we add our
5759 current AT (from the global offset table) and the
5760 register into the register now, and pretend we were
5761 not using a base register. */
5765 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5770 add_got_offset_hilo (tempreg, &offset_expr, AT);
5774 else if (!mips_big_got && HAVE_NEWABI)
5776 int add_breg_early = 0;
5778 /* If this is a reference to an external, and there is no
5779 constant, or local symbol (*), with or without a
5781 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5782 or for lca or if tempreg is PIC_CALL_REG
5783 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5785 If we have a small constant, and this is a reference to
5786 an external symbol, we want
5787 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5788 addiu $tempreg,$tempreg,<constant>
5790 If we have a large constant, and this is a reference to
5791 an external symbol, we want
5792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5793 lui $at,<hiconstant>
5794 addiu $at,$at,<loconstant>
5795 addu $tempreg,$tempreg,$at
5797 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5798 local symbols, even though it introduces an additional
5801 if (offset_expr.X_add_number)
5803 expr1.X_add_number = offset_expr.X_add_number;
5804 offset_expr.X_add_number = 0;
5806 relax_start (offset_expr.X_add_symbol);
5807 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5808 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5810 if (expr1.X_add_number >= -0x8000
5811 && expr1.X_add_number < 0x8000)
5813 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5814 tempreg, tempreg, BFD_RELOC_LO16);
5816 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5818 /* If we are going to add in a base register, and the
5819 target register and the base register are the same,
5820 then we are using AT as a temporary register. Since
5821 we want to load the constant into AT, we add our
5822 current AT (from the global offset table) and the
5823 register into the register now, and pretend we were
5824 not using a base register. */
5829 gas_assert (tempreg == AT);
5830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5836 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5837 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5843 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5846 offset_expr.X_add_number = expr1.X_add_number;
5848 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5849 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5852 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5853 treg, tempreg, breg);
5859 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5861 relax_start (offset_expr.X_add_symbol);
5862 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5863 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5865 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5866 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5871 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5872 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5875 else if (mips_big_got && !HAVE_NEWABI)
5878 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5879 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5880 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5882 /* This is the large GOT case. If this is a reference to an
5883 external symbol, and there is no constant, we want
5884 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5885 addu $tempreg,$tempreg,$gp
5886 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5887 or for lca or if tempreg is PIC_CALL_REG
5888 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5889 addu $tempreg,$tempreg,$gp
5890 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5891 For a local symbol, we want
5892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5894 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5896 If we have a small constant, and this is a reference to
5897 an external symbol, we want
5898 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5899 addu $tempreg,$tempreg,$gp
5900 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5902 addiu $tempreg,$tempreg,<constant>
5903 For a local symbol, we want
5904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5906 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5908 If we have a large constant, and this is a reference to
5909 an external symbol, we want
5910 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5911 addu $tempreg,$tempreg,$gp
5912 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5913 lui $at,<hiconstant>
5914 addiu $at,$at,<loconstant>
5915 addu $tempreg,$tempreg,$at
5916 For a local symbol, we want
5917 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5918 lui $at,<hiconstant>
5919 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5920 addu $tempreg,$tempreg,$at
5923 expr1.X_add_number = offset_expr.X_add_number;
5924 offset_expr.X_add_number = 0;
5925 relax_start (offset_expr.X_add_symbol);
5926 gpdelay = reg_needs_delay (mips_gp_register);
5927 if (expr1.X_add_number == 0 && breg == 0
5928 && (call || tempreg == PIC_CALL_REG))
5930 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5931 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5933 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5934 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5935 tempreg, tempreg, mips_gp_register);
5936 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5937 tempreg, lw_reloc_type, tempreg);
5938 if (expr1.X_add_number == 0)
5942 /* We're going to put in an addu instruction using
5943 tempreg, so we may as well insert the nop right
5948 else if (expr1.X_add_number >= -0x8000
5949 && expr1.X_add_number < 0x8000)
5952 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5953 tempreg, tempreg, BFD_RELOC_LO16);
5957 /* If we are going to add in a base register, and the
5958 target register and the base register are the same,
5959 then we are using AT as a temporary register. Since
5960 we want to load the constant into AT, we add our
5961 current AT (from the global offset table) and the
5962 register into the register now, and pretend we were
5963 not using a base register. */
5968 gas_assert (tempreg == AT);
5970 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5975 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5976 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5980 offset_expr.X_add_number =
5981 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5986 /* This is needed because this instruction uses $gp, but
5987 the first instruction on the main stream does not. */
5988 macro_build (NULL, "nop", "");
5991 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5992 local_reloc_type, mips_gp_register);
5993 if (expr1.X_add_number >= -0x8000
5994 && expr1.X_add_number < 0x8000)
5997 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5998 tempreg, tempreg, BFD_RELOC_LO16);
5999 /* FIXME: If add_number is 0, and there was no base
6000 register, the external symbol case ended with a load,
6001 so if the symbol turns out to not be external, and
6002 the next instruction uses tempreg, an unnecessary nop
6003 will be inserted. */
6009 /* We must add in the base register now, as in the
6010 external symbol case. */
6011 gas_assert (tempreg == AT);
6013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6016 /* We set breg to 0 because we have arranged to add
6017 it in in both cases. */
6021 macro_build_lui (&expr1, AT);
6022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6023 AT, AT, BFD_RELOC_LO16);
6024 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6025 tempreg, tempreg, AT);
6030 else if (mips_big_got && HAVE_NEWABI)
6032 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6033 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6034 int add_breg_early = 0;
6036 /* This is the large GOT case. If this is a reference to an
6037 external symbol, and there is no constant, we want
6038 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6039 add $tempreg,$tempreg,$gp
6040 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6041 or for lca or if tempreg is PIC_CALL_REG
6042 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6043 add $tempreg,$tempreg,$gp
6044 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6046 If we have a small constant, and this is a reference to
6047 an external symbol, we want
6048 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6049 add $tempreg,$tempreg,$gp
6050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6051 addi $tempreg,$tempreg,<constant>
6053 If we have a large constant, and this is a reference to
6054 an external symbol, we want
6055 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6056 addu $tempreg,$tempreg,$gp
6057 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6058 lui $at,<hiconstant>
6059 addi $at,$at,<loconstant>
6060 add $tempreg,$tempreg,$at
6062 If we have NewABI, and we know it's a local symbol, we want
6063 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6064 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6065 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6067 relax_start (offset_expr.X_add_symbol);
6069 expr1.X_add_number = offset_expr.X_add_number;
6070 offset_expr.X_add_number = 0;
6072 if (expr1.X_add_number == 0 && breg == 0
6073 && (call || tempreg == PIC_CALL_REG))
6075 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6076 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6078 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6079 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6080 tempreg, tempreg, mips_gp_register);
6081 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6082 tempreg, lw_reloc_type, tempreg);
6084 if (expr1.X_add_number == 0)
6086 else if (expr1.X_add_number >= -0x8000
6087 && expr1.X_add_number < 0x8000)
6089 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6090 tempreg, tempreg, BFD_RELOC_LO16);
6092 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6094 /* If we are going to add in a base register, and the
6095 target register and the base register are the same,
6096 then we are using AT as a temporary register. Since
6097 we want to load the constant into AT, we add our
6098 current AT (from the global offset table) and the
6099 register into the register now, and pretend we were
6100 not using a base register. */
6105 gas_assert (tempreg == AT);
6106 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6112 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6113 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6118 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6121 offset_expr.X_add_number = expr1.X_add_number;
6122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6123 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6124 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6125 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6128 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6129 treg, tempreg, breg);
6139 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6144 unsigned long temp = (treg << 16) | (0x01);
6145 macro_build (NULL, "c2", "C", temp);
6147 /* AT is not used, just return */
6152 unsigned long temp = (0x02);
6153 macro_build (NULL, "c2", "C", temp);
6155 /* AT is not used, just return */
6160 unsigned long temp = (treg << 16) | (0x02);
6161 macro_build (NULL, "c2", "C", temp);
6163 /* AT is not used, just return */
6167 macro_build (NULL, "c2", "C", 3);
6168 /* AT is not used, just return */
6173 unsigned long temp = (treg << 16) | 0x03;
6174 macro_build (NULL, "c2", "C", temp);
6176 /* AT is not used, just return */
6180 /* The j instruction may not be used in PIC code, since it
6181 requires an absolute address. We convert it to a b
6183 if (mips_pic == NO_PIC)
6184 macro_build (&offset_expr, "j", "a");
6186 macro_build (&offset_expr, "b", "p");
6189 /* The jal instructions must be handled as macros because when
6190 generating PIC code they expand to multi-instruction
6191 sequences. Normally they are simple instructions. */
6196 if (mips_pic == NO_PIC)
6197 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6200 if (sreg != PIC_CALL_REG)
6201 as_warn (_("MIPS PIC call to register other than $25"));
6203 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6204 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6206 if (mips_cprestore_offset < 0)
6207 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6210 if (! mips_frame_reg_valid)
6212 as_warn (_("No .frame pseudo-op used in PIC code"));
6213 /* Quiet this warning. */
6214 mips_frame_reg_valid = 1;
6216 if (! mips_cprestore_valid)
6218 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6219 /* Quiet this warning. */
6220 mips_cprestore_valid = 1;
6222 if (mips_opts.noreorder)
6223 macro_build (NULL, "nop", "");
6224 expr1.X_add_number = mips_cprestore_offset;
6225 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6228 HAVE_64BIT_ADDRESSES);
6236 if (mips_pic == NO_PIC)
6237 macro_build (&offset_expr, "jal", "a");
6238 else if (mips_pic == SVR4_PIC)
6240 /* If this is a reference to an external symbol, and we are
6241 using a small GOT, we want
6242 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6246 lw $gp,cprestore($sp)
6247 The cprestore value is set using the .cprestore
6248 pseudo-op. If we are using a big GOT, we want
6249 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6251 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6255 lw $gp,cprestore($sp)
6256 If the symbol is not external, we want
6257 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6259 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6262 lw $gp,cprestore($sp)
6264 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6265 sequences above, minus nops, unless the symbol is local,
6266 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6272 relax_start (offset_expr.X_add_symbol);
6273 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6274 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6277 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6278 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6284 relax_start (offset_expr.X_add_symbol);
6285 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6286 BFD_RELOC_MIPS_CALL_HI16);
6287 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6288 PIC_CALL_REG, mips_gp_register);
6289 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6290 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6293 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6294 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6296 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6297 PIC_CALL_REG, PIC_CALL_REG,
6298 BFD_RELOC_MIPS_GOT_OFST);
6302 macro_build_jalr (&offset_expr);
6306 relax_start (offset_expr.X_add_symbol);
6309 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6310 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6319 gpdelay = reg_needs_delay (mips_gp_register);
6320 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6321 BFD_RELOC_MIPS_CALL_HI16);
6322 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6323 PIC_CALL_REG, mips_gp_register);
6324 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6325 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6330 macro_build (NULL, "nop", "");
6332 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6333 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6336 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6337 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6339 macro_build_jalr (&offset_expr);
6341 if (mips_cprestore_offset < 0)
6342 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6345 if (! mips_frame_reg_valid)
6347 as_warn (_("No .frame pseudo-op used in PIC code"));
6348 /* Quiet this warning. */
6349 mips_frame_reg_valid = 1;
6351 if (! mips_cprestore_valid)
6353 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6354 /* Quiet this warning. */
6355 mips_cprestore_valid = 1;
6357 if (mips_opts.noreorder)
6358 macro_build (NULL, "nop", "");
6359 expr1.X_add_number = mips_cprestore_offset;
6360 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6363 HAVE_64BIT_ADDRESSES);
6367 else if (mips_pic == VXWORKS_PIC)
6368 as_bad (_("Non-PIC jump used in PIC library"));
6391 /* Itbl support may require additional care here. */
6396 /* Itbl support may require additional care here. */
6401 /* Itbl support may require additional care here. */
6406 /* Itbl support may require additional care here. */
6419 /* Itbl support may require additional care here. */
6424 /* Itbl support may require additional care here. */
6429 /* Itbl support may require additional care here. */
6449 if (breg == treg || coproc || lr)
6470 /* Itbl support may require additional care here. */
6475 /* Itbl support may require additional care here. */
6480 /* Itbl support may require additional care here. */
6485 /* Itbl support may require additional care here. */
6506 /* Itbl support may require additional care here. */
6510 /* Itbl support may require additional care here. */
6515 /* Itbl support may require additional care here. */
6528 && NO_ISA_COP (mips_opts.arch)
6529 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6531 as_bad (_("opcode not supported on this processor: %s"),
6532 mips_cpu_info_from_arch (mips_opts.arch)->name);
6536 /* Itbl support may require additional care here. */
6537 if (mask == M_LWC1_AB
6538 || mask == M_SWC1_AB
6539 || mask == M_LDC1_AB
6540 || mask == M_SDC1_AB
6544 else if (mask == M_CACHE_AB)
6551 if (offset_expr.X_op != O_constant
6552 && offset_expr.X_op != O_symbol)
6554 as_bad (_("expression too complex"));
6555 offset_expr.X_op = O_constant;
6558 if (HAVE_32BIT_ADDRESSES
6559 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6563 sprintf_vma (value, offset_expr.X_add_number);
6564 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6567 /* A constant expression in PIC code can be handled just as it
6568 is in non PIC code. */
6569 if (offset_expr.X_op == O_constant)
6571 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6572 & ~(bfd_vma) 0xffff);
6573 normalize_address_expr (&expr1);
6574 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6576 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6577 tempreg, tempreg, breg);
6578 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6580 else if (mips_pic == NO_PIC)
6582 /* If this is a reference to a GP relative symbol, and there
6583 is no base register, we want
6584 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6585 Otherwise, if there is no base register, we want
6586 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6587 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6588 If we have a constant, we need two instructions anyhow,
6589 so we always use the latter form.
6591 If we have a base register, and this is a reference to a
6592 GP relative symbol, we want
6593 addu $tempreg,$breg,$gp
6594 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6596 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6597 addu $tempreg,$tempreg,$breg
6598 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6599 With a constant we always use the latter case.
6601 With 64bit address space and no base register and $at usable,
6603 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6604 lui $at,<sym> (BFD_RELOC_HI16_S)
6605 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6608 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6609 If we have a base register, we want
6610 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6611 lui $at,<sym> (BFD_RELOC_HI16_S)
6612 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6616 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6618 Without $at we can't generate the optimal path for superscalar
6619 processors here since this would require two temporary registers.
6620 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6621 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6623 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6625 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6626 If we have a base register, we want
6627 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6628 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6630 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6632 daddu $tempreg,$tempreg,$breg
6633 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6635 For GP relative symbols in 64bit address space we can use
6636 the same sequence as in 32bit address space. */
6637 if (HAVE_64BIT_SYMBOLS)
6639 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6640 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6642 relax_start (offset_expr.X_add_symbol);
6645 macro_build (&offset_expr, s, fmt, treg,
6646 BFD_RELOC_GPREL16, mips_gp_register);
6650 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6651 tempreg, breg, mips_gp_register);
6652 macro_build (&offset_expr, s, fmt, treg,
6653 BFD_RELOC_GPREL16, tempreg);
6658 if (used_at == 0 && mips_opts.at)
6660 macro_build (&offset_expr, "lui", "t,u", tempreg,
6661 BFD_RELOC_MIPS_HIGHEST);
6662 macro_build (&offset_expr, "lui", "t,u", AT,
6664 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6665 tempreg, BFD_RELOC_MIPS_HIGHER);
6667 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6668 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6669 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6670 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6676 macro_build (&offset_expr, "lui", "t,u", tempreg,
6677 BFD_RELOC_MIPS_HIGHEST);
6678 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6679 tempreg, BFD_RELOC_MIPS_HIGHER);
6680 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6681 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6682 tempreg, BFD_RELOC_HI16_S);
6683 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6685 macro_build (NULL, "daddu", "d,v,t",
6686 tempreg, tempreg, breg);
6687 macro_build (&offset_expr, s, fmt, treg,
6688 BFD_RELOC_LO16, tempreg);
6691 if (mips_relax.sequence)
6698 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6699 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6701 relax_start (offset_expr.X_add_symbol);
6702 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6706 macro_build_lui (&offset_expr, tempreg);
6707 macro_build (&offset_expr, s, fmt, treg,
6708 BFD_RELOC_LO16, tempreg);
6709 if (mips_relax.sequence)
6714 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6715 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6717 relax_start (offset_expr.X_add_symbol);
6718 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6719 tempreg, breg, mips_gp_register);
6720 macro_build (&offset_expr, s, fmt, treg,
6721 BFD_RELOC_GPREL16, tempreg);
6724 macro_build_lui (&offset_expr, tempreg);
6725 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6726 tempreg, tempreg, breg);
6727 macro_build (&offset_expr, s, fmt, treg,
6728 BFD_RELOC_LO16, tempreg);
6729 if (mips_relax.sequence)
6733 else if (!mips_big_got)
6735 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6737 /* If this is a reference to an external symbol, we want
6738 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6740 <op> $treg,0($tempreg)
6742 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6744 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6745 <op> $treg,0($tempreg)
6748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6749 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6751 If there is a base register, we add it to $tempreg before
6752 the <op>. If there is a constant, we stick it in the
6753 <op> instruction. We don't handle constants larger than
6754 16 bits, because we have no way to load the upper 16 bits
6755 (actually, we could handle them for the subset of cases
6756 in which we are not using $at). */
6757 gas_assert (offset_expr.X_op == O_symbol);
6760 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6761 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6764 tempreg, tempreg, breg);
6765 macro_build (&offset_expr, s, fmt, treg,
6766 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6769 expr1.X_add_number = offset_expr.X_add_number;
6770 offset_expr.X_add_number = 0;
6771 if (expr1.X_add_number < -0x8000
6772 || expr1.X_add_number >= 0x8000)
6773 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6774 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6775 lw_reloc_type, mips_gp_register);
6777 relax_start (offset_expr.X_add_symbol);
6779 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6780 tempreg, BFD_RELOC_LO16);
6783 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6784 tempreg, tempreg, breg);
6785 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6787 else if (mips_big_got && !HAVE_NEWABI)
6791 /* If this is a reference to an external symbol, we want
6792 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6793 addu $tempreg,$tempreg,$gp
6794 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6795 <op> $treg,0($tempreg)
6797 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6799 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6800 <op> $treg,0($tempreg)
6801 If there is a base register, we add it to $tempreg before
6802 the <op>. If there is a constant, we stick it in the
6803 <op> instruction. We don't handle constants larger than
6804 16 bits, because we have no way to load the upper 16 bits
6805 (actually, we could handle them for the subset of cases
6806 in which we are not using $at). */
6807 gas_assert (offset_expr.X_op == O_symbol);
6808 expr1.X_add_number = offset_expr.X_add_number;
6809 offset_expr.X_add_number = 0;
6810 if (expr1.X_add_number < -0x8000
6811 || expr1.X_add_number >= 0x8000)
6812 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6813 gpdelay = reg_needs_delay (mips_gp_register);
6814 relax_start (offset_expr.X_add_symbol);
6815 macro_build (&offset_expr, "lui", "t,u", tempreg,
6816 BFD_RELOC_MIPS_GOT_HI16);
6817 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6819 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6820 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6823 macro_build (NULL, "nop", "");
6824 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6825 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6827 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6828 tempreg, BFD_RELOC_LO16);
6832 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6833 tempreg, tempreg, breg);
6834 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6836 else if (mips_big_got && HAVE_NEWABI)
6838 /* If this is a reference to an external symbol, we want
6839 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6840 add $tempreg,$tempreg,$gp
6841 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6842 <op> $treg,<ofst>($tempreg)
6843 Otherwise, for local symbols, we want:
6844 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6845 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6846 gas_assert (offset_expr.X_op == O_symbol);
6847 expr1.X_add_number = offset_expr.X_add_number;
6848 offset_expr.X_add_number = 0;
6849 if (expr1.X_add_number < -0x8000
6850 || expr1.X_add_number >= 0x8000)
6851 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6852 relax_start (offset_expr.X_add_symbol);
6853 macro_build (&offset_expr, "lui", "t,u", tempreg,
6854 BFD_RELOC_MIPS_GOT_HI16);
6855 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6857 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6858 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6861 tempreg, tempreg, breg);
6862 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6865 offset_expr.X_add_number = expr1.X_add_number;
6866 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6867 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6869 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6870 tempreg, tempreg, breg);
6871 macro_build (&offset_expr, s, fmt, treg,
6872 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6882 load_register (treg, &imm_expr, 0);
6886 load_register (treg, &imm_expr, 1);
6890 if (imm_expr.X_op == O_constant)
6893 load_register (AT, &imm_expr, 0);
6894 macro_build (NULL, "mtc1", "t,G", AT, treg);
6899 gas_assert (offset_expr.X_op == O_symbol
6900 && strcmp (segment_name (S_GET_SEGMENT
6901 (offset_expr.X_add_symbol)),
6903 && offset_expr.X_add_number == 0);
6904 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6905 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6910 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6911 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6912 order 32 bits of the value and the low order 32 bits are either
6913 zero or in OFFSET_EXPR. */
6914 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6916 if (HAVE_64BIT_GPRS)
6917 load_register (treg, &imm_expr, 1);
6922 if (target_big_endian)
6934 load_register (hreg, &imm_expr, 0);
6937 if (offset_expr.X_op == O_absent)
6938 move_register (lreg, 0);
6941 gas_assert (offset_expr.X_op == O_constant);
6942 load_register (lreg, &offset_expr, 0);
6949 /* We know that sym is in the .rdata section. First we get the
6950 upper 16 bits of the address. */
6951 if (mips_pic == NO_PIC)
6953 macro_build_lui (&offset_expr, AT);
6958 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6959 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6963 /* Now we load the register(s). */
6964 if (HAVE_64BIT_GPRS)
6967 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6972 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6975 /* FIXME: How in the world do we deal with the possible
6977 offset_expr.X_add_number += 4;
6978 macro_build (&offset_expr, "lw", "t,o(b)",
6979 treg + 1, BFD_RELOC_LO16, AT);
6985 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6986 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6987 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6988 the value and the low order 32 bits are either zero or in
6990 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6993 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6994 if (HAVE_64BIT_FPRS)
6996 gas_assert (HAVE_64BIT_GPRS);
6997 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7001 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7002 if (offset_expr.X_op == O_absent)
7003 macro_build (NULL, "mtc1", "t,G", 0, treg);
7006 gas_assert (offset_expr.X_op == O_constant);
7007 load_register (AT, &offset_expr, 0);
7008 macro_build (NULL, "mtc1", "t,G", AT, treg);
7014 gas_assert (offset_expr.X_op == O_symbol
7015 && offset_expr.X_add_number == 0);
7016 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7017 if (strcmp (s, ".lit8") == 0)
7019 if (mips_opts.isa != ISA_MIPS1)
7021 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7022 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7025 breg = mips_gp_register;
7026 r = BFD_RELOC_MIPS_LITERAL;
7031 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7033 if (mips_pic != NO_PIC)
7034 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7035 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7038 /* FIXME: This won't work for a 64 bit address. */
7039 macro_build_lui (&offset_expr, AT);
7042 if (mips_opts.isa != ISA_MIPS1)
7044 macro_build (&offset_expr, "ldc1", "T,o(b)",
7045 treg, BFD_RELOC_LO16, AT);
7054 /* Even on a big endian machine $fn comes before $fn+1. We have
7055 to adjust when loading from memory. */
7058 gas_assert (mips_opts.isa == ISA_MIPS1);
7059 macro_build (&offset_expr, "lwc1", "T,o(b)",
7060 target_big_endian ? treg + 1 : treg, r, breg);
7061 /* FIXME: A possible overflow which I don't know how to deal
7063 offset_expr.X_add_number += 4;
7064 macro_build (&offset_expr, "lwc1", "T,o(b)",
7065 target_big_endian ? treg : treg + 1, r, breg);
7070 * The MIPS assembler seems to check for X_add_number not
7071 * being double aligned and generating:
7074 * addiu at,at,%lo(foo+1)
7077 * But, the resulting address is the same after relocation so why
7078 * generate the extra instruction?
7080 /* Itbl support may require additional care here. */
7082 if (mips_opts.isa != ISA_MIPS1)
7093 if (mips_opts.isa != ISA_MIPS1)
7101 /* Itbl support may require additional care here. */
7106 if (HAVE_64BIT_GPRS)
7117 if (HAVE_64BIT_GPRS)
7127 if (offset_expr.X_op != O_symbol
7128 && offset_expr.X_op != O_constant)
7130 as_bad (_("expression too complex"));
7131 offset_expr.X_op = O_constant;
7134 if (HAVE_32BIT_ADDRESSES
7135 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7139 sprintf_vma (value, offset_expr.X_add_number);
7140 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7143 /* Even on a big endian machine $fn comes before $fn+1. We have
7144 to adjust when loading from memory. We set coproc if we must
7145 load $fn+1 first. */
7146 /* Itbl support may require additional care here. */
7147 if (! target_big_endian)
7150 if (mips_pic == NO_PIC
7151 || offset_expr.X_op == O_constant)
7153 /* If this is a reference to a GP relative symbol, we want
7154 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7155 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7156 If we have a base register, we use this
7158 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7159 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7160 If this is not a GP relative symbol, we want
7161 lui $at,<sym> (BFD_RELOC_HI16_S)
7162 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7163 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7164 If there is a base register, we add it to $at after the
7165 lui instruction. If there is a constant, we always use
7167 if (offset_expr.X_op == O_symbol
7168 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7169 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7171 relax_start (offset_expr.X_add_symbol);
7174 tempreg = mips_gp_register;
7178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7179 AT, breg, mips_gp_register);
7184 /* Itbl support may require additional care here. */
7185 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7186 BFD_RELOC_GPREL16, tempreg);
7187 offset_expr.X_add_number += 4;
7189 /* Set mips_optimize to 2 to avoid inserting an
7191 hold_mips_optimize = mips_optimize;
7193 /* Itbl support may require additional care here. */
7194 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7195 BFD_RELOC_GPREL16, tempreg);
7196 mips_optimize = hold_mips_optimize;
7200 /* We just generated two relocs. When tc_gen_reloc
7201 handles this case, it will skip the first reloc and
7202 handle the second. The second reloc already has an
7203 extra addend of 4, which we added above. We must
7204 subtract it out, and then subtract another 4 to make
7205 the first reloc come out right. The second reloc
7206 will come out right because we are going to add 4 to
7207 offset_expr when we build its instruction below.
7209 If we have a symbol, then we don't want to include
7210 the offset, because it will wind up being included
7211 when we generate the reloc. */
7213 if (offset_expr.X_op == O_constant)
7214 offset_expr.X_add_number -= 8;
7217 offset_expr.X_add_number = -4;
7218 offset_expr.X_op = O_constant;
7222 macro_build_lui (&offset_expr, AT);
7224 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7225 /* Itbl support may require additional care here. */
7226 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7227 BFD_RELOC_LO16, AT);
7228 /* FIXME: How do we handle overflow here? */
7229 offset_expr.X_add_number += 4;
7230 /* Itbl support may require additional care here. */
7231 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7232 BFD_RELOC_LO16, AT);
7233 if (mips_relax.sequence)
7236 else if (!mips_big_got)
7238 /* If this is a reference to an external symbol, we want
7239 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7244 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7246 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7247 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7248 If there is a base register we add it to $at before the
7249 lwc1 instructions. If there is a constant we include it
7250 in the lwc1 instructions. */
7252 expr1.X_add_number = offset_expr.X_add_number;
7253 if (expr1.X_add_number < -0x8000
7254 || expr1.X_add_number >= 0x8000 - 4)
7255 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7256 load_got_offset (AT, &offset_expr);
7259 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7261 /* Set mips_optimize to 2 to avoid inserting an undesired
7263 hold_mips_optimize = mips_optimize;
7266 /* Itbl support may require additional care here. */
7267 relax_start (offset_expr.X_add_symbol);
7268 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7269 BFD_RELOC_LO16, AT);
7270 expr1.X_add_number += 4;
7271 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7272 BFD_RELOC_LO16, AT);
7274 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7275 BFD_RELOC_LO16, AT);
7276 offset_expr.X_add_number += 4;
7277 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7278 BFD_RELOC_LO16, AT);
7281 mips_optimize = hold_mips_optimize;
7283 else if (mips_big_got)
7287 /* If this is a reference to an external symbol, we want
7288 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7290 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7295 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7297 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7298 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7299 If there is a base register we add it to $at before the
7300 lwc1 instructions. If there is a constant we include it
7301 in the lwc1 instructions. */
7303 expr1.X_add_number = offset_expr.X_add_number;
7304 offset_expr.X_add_number = 0;
7305 if (expr1.X_add_number < -0x8000
7306 || expr1.X_add_number >= 0x8000 - 4)
7307 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7308 gpdelay = reg_needs_delay (mips_gp_register);
7309 relax_start (offset_expr.X_add_symbol);
7310 macro_build (&offset_expr, "lui", "t,u",
7311 AT, BFD_RELOC_MIPS_GOT_HI16);
7312 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7313 AT, AT, mips_gp_register);
7314 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7315 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7319 /* Itbl support may require additional care here. */
7320 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7321 BFD_RELOC_LO16, AT);
7322 expr1.X_add_number += 4;
7324 /* Set mips_optimize to 2 to avoid inserting an undesired
7326 hold_mips_optimize = mips_optimize;
7328 /* Itbl support may require additional care here. */
7329 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7330 BFD_RELOC_LO16, AT);
7331 mips_optimize = hold_mips_optimize;
7332 expr1.X_add_number -= 4;
7335 offset_expr.X_add_number = expr1.X_add_number;
7337 macro_build (NULL, "nop", "");
7338 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7339 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7342 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7343 /* Itbl support may require additional care here. */
7344 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7345 BFD_RELOC_LO16, AT);
7346 offset_expr.X_add_number += 4;
7348 /* Set mips_optimize to 2 to avoid inserting an undesired
7350 hold_mips_optimize = mips_optimize;
7352 /* Itbl support may require additional care here. */
7353 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7354 BFD_RELOC_LO16, AT);
7355 mips_optimize = hold_mips_optimize;
7369 gas_assert (HAVE_32BIT_ADDRESSES);
7370 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7371 offset_expr.X_add_number += 4;
7372 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7375 /* New code added to support COPZ instructions.
7376 This code builds table entries out of the macros in mip_opcodes.
7377 R4000 uses interlocks to handle coproc delays.
7378 Other chips (like the R3000) require nops to be inserted for delays.
7380 FIXME: Currently, we require that the user handle delays.
7381 In order to fill delay slots for non-interlocked chips,
7382 we must have a way to specify delays based on the coprocessor.
7383 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7384 What are the side-effects of the cop instruction?
7385 What cache support might we have and what are its effects?
7386 Both coprocessor & memory require delays. how long???
7387 What registers are read/set/modified?
7389 If an itbl is provided to interpret cop instructions,
7390 this knowledge can be encoded in the itbl spec. */
7404 if (NO_ISA_COP (mips_opts.arch)
7405 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7407 as_bad (_("opcode not supported on this processor: %s"),
7408 mips_cpu_info_from_arch (mips_opts.arch)->name);
7412 /* For now we just do C (same as Cz). The parameter will be
7413 stored in insn_opcode by mips_ip. */
7414 macro_build (NULL, s, "C", ip->insn_opcode);
7418 move_register (dreg, sreg);
7421 #ifdef LOSING_COMPILER
7423 /* Try and see if this is a new itbl instruction.
7424 This code builds table entries out of the macros in mip_opcodes.
7425 FIXME: For now we just assemble the expression and pass it's
7426 value along as a 32-bit immediate.
7427 We may want to have the assembler assemble this value,
7428 so that we gain the assembler's knowledge of delay slots,
7430 Would it be more efficient to use mask (id) here? */
7431 if (itbl_have_entries
7432 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7434 s = ip->insn_mo->name;
7436 coproc = ITBL_DECODE_PNUM (immed_expr);;
7437 macro_build (&immed_expr, s, "C");
7443 if (!mips_opts.at && used_at)
7444 as_bad (_("Macro used $at after \".set noat\""));
7448 macro2 (struct mips_cl_insn *ip)
7450 unsigned int treg, sreg, dreg, breg;
7451 unsigned int tempreg;
7465 bfd_reloc_code_real_type r;
7467 treg = (ip->insn_opcode >> 16) & 0x1f;
7468 dreg = (ip->insn_opcode >> 11) & 0x1f;
7469 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7470 mask = ip->insn_mo->mask;
7472 expr1.X_op = O_constant;
7473 expr1.X_op_symbol = NULL;
7474 expr1.X_add_symbol = NULL;
7475 expr1.X_add_number = 1;
7479 #endif /* LOSING_COMPILER */
7484 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7485 macro_build (NULL, "mflo", "d", dreg);
7491 /* The MIPS assembler some times generates shifts and adds. I'm
7492 not trying to be that fancy. GCC should do this for us
7495 load_register (AT, &imm_expr, dbl);
7496 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7497 macro_build (NULL, "mflo", "d", dreg);
7513 load_register (AT, &imm_expr, dbl);
7514 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7515 macro_build (NULL, "mflo", "d", dreg);
7516 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7517 macro_build (NULL, "mfhi", "d", AT);
7519 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7522 expr1.X_add_number = 8;
7523 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7524 macro_build (NULL, "nop", "", 0);
7525 macro_build (NULL, "break", "c", 6);
7528 macro_build (NULL, "mflo", "d", dreg);
7544 load_register (AT, &imm_expr, dbl);
7545 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7546 sreg, imm ? AT : treg);
7547 macro_build (NULL, "mfhi", "d", AT);
7548 macro_build (NULL, "mflo", "d", dreg);
7550 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7553 expr1.X_add_number = 8;
7554 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7555 macro_build (NULL, "nop", "", 0);
7556 macro_build (NULL, "break", "c", 6);
7562 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7573 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7574 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7578 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7579 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7580 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7581 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7585 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7596 macro_build (NULL, "negu", "d,w", tempreg, treg);
7597 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7601 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7602 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7603 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7604 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7613 if (imm_expr.X_op != O_constant)
7614 as_bad (_("Improper rotate count"));
7615 rot = imm_expr.X_add_number & 0x3f;
7616 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7618 rot = (64 - rot) & 0x3f;
7620 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7622 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7627 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7630 l = (rot < 0x20) ? "dsll" : "dsll32";
7631 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7634 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7635 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7636 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7644 if (imm_expr.X_op != O_constant)
7645 as_bad (_("Improper rotate count"));
7646 rot = imm_expr.X_add_number & 0x1f;
7647 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7649 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7654 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7658 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7659 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7660 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7665 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7667 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7671 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7672 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7673 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7674 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7678 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7680 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7684 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7685 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7686 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7687 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7696 if (imm_expr.X_op != O_constant)
7697 as_bad (_("Improper rotate count"));
7698 rot = imm_expr.X_add_number & 0x3f;
7699 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7702 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7704 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7709 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7712 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7713 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7716 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7717 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7718 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7726 if (imm_expr.X_op != O_constant)
7727 as_bad (_("Improper rotate count"));
7728 rot = imm_expr.X_add_number & 0x1f;
7729 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7731 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7736 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7740 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7741 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7742 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7747 gas_assert (mips_opts.isa == ISA_MIPS1);
7748 /* Even on a big endian machine $fn comes before $fn+1. We have
7749 to adjust when storing to memory. */
7750 macro_build (&offset_expr, "swc1", "T,o(b)",
7751 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7752 offset_expr.X_add_number += 4;
7753 macro_build (&offset_expr, "swc1", "T,o(b)",
7754 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7759 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7761 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7764 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7765 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7770 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7772 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7777 as_warn (_("Instruction %s: result is always false"),
7779 move_register (dreg, 0);
7782 if (CPU_HAS_SEQ (mips_opts.arch)
7783 && -512 <= imm_expr.X_add_number
7784 && imm_expr.X_add_number < 512)
7786 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7787 (int) imm_expr.X_add_number);
7790 if (imm_expr.X_op == O_constant
7791 && imm_expr.X_add_number >= 0
7792 && imm_expr.X_add_number < 0x10000)
7794 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7796 else if (imm_expr.X_op == O_constant
7797 && imm_expr.X_add_number > -0x8000
7798 && imm_expr.X_add_number < 0)
7800 imm_expr.X_add_number = -imm_expr.X_add_number;
7801 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7802 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7804 else if (CPU_HAS_SEQ (mips_opts.arch))
7807 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7808 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7813 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7814 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7817 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7820 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7826 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7827 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7830 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7832 if (imm_expr.X_op == O_constant
7833 && imm_expr.X_add_number >= -0x8000
7834 && imm_expr.X_add_number < 0x8000)
7836 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7837 dreg, sreg, BFD_RELOC_LO16);
7841 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7842 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7846 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7849 case M_SGT: /* sreg > treg <==> treg < sreg */
7855 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7858 case M_SGT_I: /* sreg > I <==> I < sreg */
7865 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7866 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7869 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7875 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7876 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7879 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7886 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7887 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7888 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7892 if (imm_expr.X_op == O_constant
7893 && imm_expr.X_add_number >= -0x8000
7894 && imm_expr.X_add_number < 0x8000)
7896 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7900 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7901 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7905 if (imm_expr.X_op == O_constant
7906 && imm_expr.X_add_number >= -0x8000
7907 && imm_expr.X_add_number < 0x8000)
7909 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7914 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7915 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7920 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7922 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7925 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7926 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7931 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7933 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7938 as_warn (_("Instruction %s: result is always true"),
7940 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7941 dreg, 0, BFD_RELOC_LO16);
7944 if (CPU_HAS_SEQ (mips_opts.arch)
7945 && -512 <= imm_expr.X_add_number
7946 && imm_expr.X_add_number < 512)
7948 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7949 (int) imm_expr.X_add_number);
7952 if (imm_expr.X_op == O_constant
7953 && imm_expr.X_add_number >= 0
7954 && imm_expr.X_add_number < 0x10000)
7956 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7958 else if (imm_expr.X_op == O_constant
7959 && imm_expr.X_add_number > -0x8000
7960 && imm_expr.X_add_number < 0)
7962 imm_expr.X_add_number = -imm_expr.X_add_number;
7963 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7964 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7966 else if (CPU_HAS_SEQ (mips_opts.arch))
7969 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7970 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7975 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7976 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7979 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7985 if (imm_expr.X_op == O_constant
7986 && imm_expr.X_add_number > -0x8000
7987 && imm_expr.X_add_number <= 0x8000)
7989 imm_expr.X_add_number = -imm_expr.X_add_number;
7990 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7991 dreg, sreg, BFD_RELOC_LO16);
7995 load_register (AT, &imm_expr, dbl);
7996 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8002 if (imm_expr.X_op == O_constant
8003 && imm_expr.X_add_number > -0x8000
8004 && imm_expr.X_add_number <= 0x8000)
8006 imm_expr.X_add_number = -imm_expr.X_add_number;
8007 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8008 dreg, sreg, BFD_RELOC_LO16);
8012 load_register (AT, &imm_expr, dbl);
8013 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8035 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8036 macro_build (NULL, s, "s,t", sreg, AT);
8041 gas_assert (mips_opts.isa == ISA_MIPS1);
8043 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8044 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8047 * Is the double cfc1 instruction a bug in the mips assembler;
8048 * or is there a reason for it?
8051 macro_build (NULL, "cfc1", "t,G", treg, RA);
8052 macro_build (NULL, "cfc1", "t,G", treg, RA);
8053 macro_build (NULL, "nop", "");
8054 expr1.X_add_number = 3;
8055 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8056 expr1.X_add_number = 2;
8057 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8058 macro_build (NULL, "ctc1", "t,G", AT, RA);
8059 macro_build (NULL, "nop", "");
8060 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8062 macro_build (NULL, "ctc1", "t,G", treg, RA);
8063 macro_build (NULL, "nop", "");
8074 if (offset_expr.X_add_number >= 0x7fff)
8075 as_bad (_("operand overflow"));
8076 if (! target_big_endian)
8077 ++offset_expr.X_add_number;
8078 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8079 if (! target_big_endian)
8080 --offset_expr.X_add_number;
8082 ++offset_expr.X_add_number;
8083 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8084 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8085 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8098 if (offset_expr.X_add_number >= 0x8000 - off)
8099 as_bad (_("operand overflow"));
8107 if (! target_big_endian)
8108 offset_expr.X_add_number += off;
8109 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8110 if (! target_big_endian)
8111 offset_expr.X_add_number -= off;
8113 offset_expr.X_add_number += off;
8114 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8116 /* If necessary, move the result in tempreg the final destination. */
8117 if (treg == tempreg)
8119 /* Protect second load's delay slot. */
8121 move_register (treg, tempreg);
8135 load_address (AT, &offset_expr, &used_at);
8137 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8138 if (! target_big_endian)
8139 expr1.X_add_number = off;
8141 expr1.X_add_number = 0;
8142 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8143 if (! target_big_endian)
8144 expr1.X_add_number = 0;
8146 expr1.X_add_number = off;
8147 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8153 load_address (AT, &offset_expr, &used_at);
8155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8156 if (target_big_endian)
8157 expr1.X_add_number = 0;
8158 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8159 treg, BFD_RELOC_LO16, AT);
8160 if (target_big_endian)
8161 expr1.X_add_number = 1;
8163 expr1.X_add_number = 0;
8164 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8165 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8166 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8171 if (offset_expr.X_add_number >= 0x7fff)
8172 as_bad (_("operand overflow"));
8173 if (target_big_endian)
8174 ++offset_expr.X_add_number;
8175 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8176 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8177 if (target_big_endian)
8178 --offset_expr.X_add_number;
8180 ++offset_expr.X_add_number;
8181 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8194 if (offset_expr.X_add_number >= 0x8000 - off)
8195 as_bad (_("operand overflow"));
8196 if (! target_big_endian)
8197 offset_expr.X_add_number += off;
8198 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8199 if (! target_big_endian)
8200 offset_expr.X_add_number -= off;
8202 offset_expr.X_add_number += off;
8203 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8217 load_address (AT, &offset_expr, &used_at);
8219 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8220 if (! target_big_endian)
8221 expr1.X_add_number = off;
8223 expr1.X_add_number = 0;
8224 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8225 if (! target_big_endian)
8226 expr1.X_add_number = 0;
8228 expr1.X_add_number = off;
8229 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8234 load_address (AT, &offset_expr, &used_at);
8236 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8237 if (! target_big_endian)
8238 expr1.X_add_number = 0;
8239 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8240 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8241 if (! target_big_endian)
8242 expr1.X_add_number = 1;
8244 expr1.X_add_number = 0;
8245 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8246 if (! target_big_endian)
8247 expr1.X_add_number = 0;
8249 expr1.X_add_number = 1;
8250 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8251 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8252 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8256 /* FIXME: Check if this is one of the itbl macros, since they
8257 are added dynamically. */
8258 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8261 if (!mips_opts.at && used_at)
8262 as_bad (_("Macro used $at after \".set noat\""));
8265 /* Implement macros in mips16 mode. */
8268 mips16_macro (struct mips_cl_insn *ip)
8271 int xreg, yreg, zreg, tmp;
8274 const char *s, *s2, *s3;
8276 mask = ip->insn_mo->mask;
8278 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8279 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8280 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8282 expr1.X_op = O_constant;
8283 expr1.X_op_symbol = NULL;
8284 expr1.X_add_symbol = NULL;
8285 expr1.X_add_number = 1;
8305 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8306 expr1.X_add_number = 2;
8307 macro_build (&expr1, "bnez", "x,p", yreg);
8308 macro_build (NULL, "break", "6", 7);
8310 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8311 since that causes an overflow. We should do that as well,
8312 but I don't see how to do the comparisons without a temporary
8315 macro_build (NULL, s, "x", zreg);
8335 macro_build (NULL, s, "0,x,y", xreg, yreg);
8336 expr1.X_add_number = 2;
8337 macro_build (&expr1, "bnez", "x,p", yreg);
8338 macro_build (NULL, "break", "6", 7);
8340 macro_build (NULL, s2, "x", zreg);
8346 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8347 macro_build (NULL, "mflo", "x", zreg);
8355 if (imm_expr.X_op != O_constant)
8356 as_bad (_("Unsupported large constant"));
8357 imm_expr.X_add_number = -imm_expr.X_add_number;
8358 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8362 if (imm_expr.X_op != O_constant)
8363 as_bad (_("Unsupported large constant"));
8364 imm_expr.X_add_number = -imm_expr.X_add_number;
8365 macro_build (&imm_expr, "addiu", "x,k", xreg);
8369 if (imm_expr.X_op != O_constant)
8370 as_bad (_("Unsupported large constant"));
8371 imm_expr.X_add_number = -imm_expr.X_add_number;
8372 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8394 goto do_reverse_branch;
8398 goto do_reverse_branch;
8410 goto do_reverse_branch;
8421 macro_build (NULL, s, "x,y", xreg, yreg);
8422 macro_build (&offset_expr, s2, "p");
8449 goto do_addone_branch_i;
8454 goto do_addone_branch_i;
8469 goto do_addone_branch_i;
8476 if (imm_expr.X_op != O_constant)
8477 as_bad (_("Unsupported large constant"));
8478 ++imm_expr.X_add_number;
8481 macro_build (&imm_expr, s, s3, xreg);
8482 macro_build (&offset_expr, s2, "p");
8486 expr1.X_add_number = 0;
8487 macro_build (&expr1, "slti", "x,8", yreg);
8489 move_register (xreg, yreg);
8490 expr1.X_add_number = 2;
8491 macro_build (&expr1, "bteqz", "p");
8492 macro_build (NULL, "neg", "x,w", xreg, xreg);
8496 /* For consistency checking, verify that all bits are specified either
8497 by the match/mask part of the instruction definition, or by the
8500 validate_mips_insn (const struct mips_opcode *opc)
8502 const char *p = opc->args;
8504 unsigned long used_bits = opc->mask;
8506 if ((used_bits & opc->match) != opc->match)
8508 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8509 opc->name, opc->args);
8512 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8522 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8523 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8524 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8525 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8526 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8527 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8528 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8529 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8530 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8531 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8532 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8533 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8534 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8536 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8537 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8538 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8539 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8540 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8541 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8542 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8543 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8544 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8545 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8548 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8549 c, opc->name, opc->args);
8553 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8554 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8556 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8557 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8558 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8559 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8561 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8562 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8564 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8565 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8567 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8568 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8569 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8570 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8571 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8572 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8573 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8574 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8575 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8576 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8577 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8578 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8579 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8580 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8581 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8582 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8583 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8585 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8586 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8587 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8588 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8590 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8591 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8592 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8593 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8594 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8595 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8596 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8597 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8598 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8601 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8602 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8603 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8604 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8605 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8608 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8609 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8610 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8611 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8612 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8613 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8614 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8615 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8616 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8617 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8618 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8619 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8620 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8621 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8622 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8623 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8624 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8625 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8627 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8628 c, opc->name, opc->args);
8632 if (used_bits != 0xffffffff)
8634 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8635 ~used_bits & 0xffffffff, opc->name, opc->args);
8641 /* UDI immediates. */
8649 static const struct mips_immed mips_immed[] = {
8650 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8651 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8652 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8653 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8657 /* Check whether an odd floating-point register is allowed. */
8659 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8661 const char *s = insn->name;
8663 if (insn->pinfo == INSN_MACRO)
8664 /* Let a macro pass, we'll catch it later when it is expanded. */
8667 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8669 /* Allow odd registers for single-precision ops. */
8670 switch (insn->pinfo & (FP_S | FP_D))
8674 return 1; /* both single precision - ok */
8676 return 0; /* both double precision - fail */
8681 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8682 s = strchr (insn->name, '.');
8684 s = s != NULL ? strchr (s + 1, '.') : NULL;
8685 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8688 /* Single-precision coprocessor loads and moves are OK too. */
8689 if ((insn->pinfo & FP_S)
8690 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8691 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8697 /* This routine assembles an instruction into its binary format. As a
8698 side effect, it sets one of the global variables imm_reloc or
8699 offset_reloc to the type of relocation to do if one of the operands
8700 is an address expression. */
8703 mips_ip (char *str, struct mips_cl_insn *ip)
8708 struct mips_opcode *insn;
8711 unsigned int lastregno = 0;
8712 unsigned int lastpos = 0;
8713 unsigned int limlo, limhi;
8716 offsetT min_range, max_range;
8722 /* If the instruction contains a '.', we first try to match an instruction
8723 including the '.'. Then we try again without the '.'. */
8725 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8728 /* If we stopped on whitespace, then replace the whitespace with null for
8729 the call to hash_find. Save the character we replaced just in case we
8730 have to re-parse the instruction. */
8737 insn = (struct mips_opcode *) hash_find (op_hash, str);
8739 /* If we didn't find the instruction in the opcode table, try again, but
8740 this time with just the instruction up to, but not including the
8744 /* Restore the character we overwrite above (if any). */
8748 /* Scan up to the first '.' or whitespace. */
8750 *s != '\0' && *s != '.' && !ISSPACE (*s);
8754 /* If we did not find a '.', then we can quit now. */
8757 insn_error = _("unrecognized opcode");
8761 /* Lookup the instruction in the hash table. */
8763 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8765 insn_error = _("unrecognized opcode");
8775 gas_assert (strcmp (insn->name, str) == 0);
8777 ok = is_opcode_valid (insn);
8780 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8781 && strcmp (insn->name, insn[1].name) == 0)
8790 static char buf[100];
8792 _("opcode not supported on this processor: %s (%s)"),
8793 mips_cpu_info_from_arch (mips_opts.arch)->name,
8794 mips_cpu_info_from_isa (mips_opts.isa)->name);
8803 create_insn (ip, insn);
8806 lastregno = 0xffffffff;
8807 for (args = insn->args;; ++args)
8811 s += strspn (s, " \t");
8815 case '\0': /* end of args */
8820 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8821 my_getExpression (&imm_expr, s);
8822 check_absolute_expr (ip, &imm_expr);
8823 if ((unsigned long) imm_expr.X_add_number != 1
8824 && (unsigned long) imm_expr.X_add_number != 3)
8826 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8827 (unsigned long) imm_expr.X_add_number);
8829 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8830 imm_expr.X_op = O_absent;
8834 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8835 my_getExpression (&imm_expr, s);
8836 check_absolute_expr (ip, &imm_expr);
8837 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8839 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8840 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8842 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8843 imm_expr.X_op = O_absent;
8847 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8848 my_getExpression (&imm_expr, s);
8849 check_absolute_expr (ip, &imm_expr);
8850 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8852 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8853 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8855 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8856 imm_expr.X_op = O_absent;
8860 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8861 my_getExpression (&imm_expr, s);
8862 check_absolute_expr (ip, &imm_expr);
8863 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8865 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8866 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8868 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8869 imm_expr.X_op = O_absent;
8873 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8874 my_getExpression (&imm_expr, s);
8875 check_absolute_expr (ip, &imm_expr);
8876 if (imm_expr.X_add_number & ~OP_MASK_RS)
8878 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8879 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8881 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8882 imm_expr.X_op = O_absent;
8886 case '7': /* four dsp accumulators in bits 11,12 */
8887 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8888 s[3] >= '0' && s[3] <= '3')
8892 INSERT_OPERAND (DSPACC, *ip, regno);
8896 as_bad (_("Invalid dsp acc register"));
8899 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8900 my_getExpression (&imm_expr, s);
8901 check_absolute_expr (ip, &imm_expr);
8902 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8904 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8906 (unsigned long) imm_expr.X_add_number);
8908 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8909 imm_expr.X_op = O_absent;
8913 case '9': /* four dsp accumulators in bits 21,22 */
8914 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8915 s[3] >= '0' && s[3] <= '3')
8919 INSERT_OPERAND (DSPACC_S, *ip, regno);
8923 as_bad (_("Invalid dsp acc register"));
8926 case '0': /* dsp 6-bit signed immediate in bit 20 */
8927 my_getExpression (&imm_expr, s);
8928 check_absolute_expr (ip, &imm_expr);
8929 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8930 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8931 if (imm_expr.X_add_number < min_range ||
8932 imm_expr.X_add_number > max_range)
8934 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8935 (long) min_range, (long) max_range,
8936 (long) imm_expr.X_add_number);
8938 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8939 imm_expr.X_op = O_absent;
8943 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8944 my_getExpression (&imm_expr, s);
8945 check_absolute_expr (ip, &imm_expr);
8946 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8948 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8950 (unsigned long) imm_expr.X_add_number);
8952 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8953 imm_expr.X_op = O_absent;
8957 case ':': /* dsp 7-bit signed immediate in bit 19 */
8958 my_getExpression (&imm_expr, s);
8959 check_absolute_expr (ip, &imm_expr);
8960 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8961 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8962 if (imm_expr.X_add_number < min_range ||
8963 imm_expr.X_add_number > max_range)
8965 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8966 (long) min_range, (long) max_range,
8967 (long) imm_expr.X_add_number);
8969 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8970 imm_expr.X_op = O_absent;
8974 case '@': /* dsp 10-bit signed immediate in bit 16 */
8975 my_getExpression (&imm_expr, s);
8976 check_absolute_expr (ip, &imm_expr);
8977 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8978 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8979 if (imm_expr.X_add_number < min_range ||
8980 imm_expr.X_add_number > max_range)
8982 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8983 (long) min_range, (long) max_range,
8984 (long) imm_expr.X_add_number);
8986 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8987 imm_expr.X_op = O_absent;
8991 case '!': /* MT usermode flag bit. */
8992 my_getExpression (&imm_expr, s);
8993 check_absolute_expr (ip, &imm_expr);
8994 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8995 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8996 (unsigned long) imm_expr.X_add_number);
8997 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8998 imm_expr.X_op = O_absent;
9002 case '$': /* MT load high flag bit. */
9003 my_getExpression (&imm_expr, s);
9004 check_absolute_expr (ip, &imm_expr);
9005 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9006 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9007 (unsigned long) imm_expr.X_add_number);
9008 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9009 imm_expr.X_op = O_absent;
9013 case '*': /* four dsp accumulators in bits 18,19 */
9014 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9015 s[3] >= '0' && s[3] <= '3')
9019 INSERT_OPERAND (MTACC_T, *ip, regno);
9023 as_bad (_("Invalid dsp/smartmips acc register"));
9026 case '&': /* four dsp accumulators in bits 13,14 */
9027 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9028 s[3] >= '0' && s[3] <= '3')
9032 INSERT_OPERAND (MTACC_D, *ip, regno);
9036 as_bad (_("Invalid dsp/smartmips acc register"));
9048 INSERT_OPERAND (RS, *ip, lastregno);
9052 INSERT_OPERAND (RT, *ip, lastregno);
9056 INSERT_OPERAND (FT, *ip, lastregno);
9060 INSERT_OPERAND (FS, *ip, lastregno);
9066 /* Handle optional base register.
9067 Either the base register is omitted or
9068 we must have a left paren. */
9069 /* This is dependent on the next operand specifier
9070 is a base register specification. */
9071 gas_assert (args[1] == 'b' || args[1] == '5'
9072 || args[1] == '-' || args[1] == '4');
9076 case ')': /* these must match exactly */
9083 case '+': /* Opcode extension character. */
9086 case '1': /* UDI immediates. */
9091 const struct mips_immed *imm = mips_immed;
9093 while (imm->type && imm->type != *args)
9097 my_getExpression (&imm_expr, s);
9098 check_absolute_expr (ip, &imm_expr);
9099 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9101 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9102 imm->desc ? imm->desc : ip->insn_mo->name,
9103 (unsigned long) imm_expr.X_add_number,
9104 (unsigned long) imm_expr.X_add_number);
9105 imm_expr.X_add_number &= imm->mask;
9107 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9109 imm_expr.X_op = O_absent;
9114 case 'A': /* ins/ext position, becomes LSB. */
9123 my_getExpression (&imm_expr, s);
9124 check_absolute_expr (ip, &imm_expr);
9125 if ((unsigned long) imm_expr.X_add_number < limlo
9126 || (unsigned long) imm_expr.X_add_number > limhi)
9128 as_bad (_("Improper position (%lu)"),
9129 (unsigned long) imm_expr.X_add_number);
9130 imm_expr.X_add_number = limlo;
9132 lastpos = imm_expr.X_add_number;
9133 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9134 imm_expr.X_op = O_absent;
9138 case 'B': /* ins size, becomes MSB. */
9147 my_getExpression (&imm_expr, s);
9148 check_absolute_expr (ip, &imm_expr);
9149 /* Check for negative input so that small negative numbers
9150 will not succeed incorrectly. The checks against
9151 (pos+size) transitively check "size" itself,
9152 assuming that "pos" is reasonable. */
9153 if ((long) imm_expr.X_add_number < 0
9154 || ((unsigned long) imm_expr.X_add_number
9156 || ((unsigned long) imm_expr.X_add_number
9159 as_bad (_("Improper insert size (%lu, position %lu)"),
9160 (unsigned long) imm_expr.X_add_number,
9161 (unsigned long) lastpos);
9162 imm_expr.X_add_number = limlo - lastpos;
9164 INSERT_OPERAND (INSMSB, *ip,
9165 lastpos + imm_expr.X_add_number - 1);
9166 imm_expr.X_op = O_absent;
9170 case 'C': /* ext size, becomes MSBD. */
9183 my_getExpression (&imm_expr, s);
9184 check_absolute_expr (ip, &imm_expr);
9185 /* Check for negative input so that small negative numbers
9186 will not succeed incorrectly. The checks against
9187 (pos+size) transitively check "size" itself,
9188 assuming that "pos" is reasonable. */
9189 if ((long) imm_expr.X_add_number < 0
9190 || ((unsigned long) imm_expr.X_add_number
9192 || ((unsigned long) imm_expr.X_add_number
9195 as_bad (_("Improper extract size (%lu, position %lu)"),
9196 (unsigned long) imm_expr.X_add_number,
9197 (unsigned long) lastpos);
9198 imm_expr.X_add_number = limlo - lastpos;
9200 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9201 imm_expr.X_op = O_absent;
9206 /* +D is for disassembly only; never match. */
9210 /* "+I" is like "I", except that imm2_expr is used. */
9211 my_getExpression (&imm2_expr, s);
9212 if (imm2_expr.X_op != O_big
9213 && imm2_expr.X_op != O_constant)
9214 insn_error = _("absolute expression required");
9215 if (HAVE_32BIT_GPRS)
9216 normalize_constant_expr (&imm2_expr);
9220 case 'T': /* Coprocessor register. */
9221 /* +T is for disassembly only; never match. */
9224 case 't': /* Coprocessor register number. */
9225 if (s[0] == '$' && ISDIGIT (s[1]))
9235 while (ISDIGIT (*s));
9237 as_bad (_("Invalid register number (%d)"), regno);
9240 INSERT_OPERAND (RT, *ip, regno);
9245 as_bad (_("Invalid coprocessor 0 register number"));
9249 /* bbit[01] and bbit[01]32 bit index. Give error if index
9250 is not in the valid range. */
9251 my_getExpression (&imm_expr, s);
9252 check_absolute_expr (ip, &imm_expr);
9253 if ((unsigned) imm_expr.X_add_number > 31)
9255 as_bad (_("Improper bit index (%lu)"),
9256 (unsigned long) imm_expr.X_add_number);
9257 imm_expr.X_add_number = 0;
9259 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9260 imm_expr.X_op = O_absent;
9265 /* bbit[01] bit index when bbit is used but we generate
9266 bbit[01]32 because the index is over 32. Move to the
9267 next candidate if index is not in the valid range. */
9268 my_getExpression (&imm_expr, s);
9269 check_absolute_expr (ip, &imm_expr);
9270 if ((unsigned) imm_expr.X_add_number < 32
9271 || (unsigned) imm_expr.X_add_number > 63)
9273 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9274 imm_expr.X_op = O_absent;
9279 /* cins, cins32, exts and exts32 position field. Give error
9280 if it's not in the valid range. */
9281 my_getExpression (&imm_expr, s);
9282 check_absolute_expr (ip, &imm_expr);
9283 if ((unsigned) imm_expr.X_add_number > 31)
9285 as_bad (_("Improper position (%lu)"),
9286 (unsigned long) imm_expr.X_add_number);
9287 imm_expr.X_add_number = 0;
9289 /* Make the pos explicit to simplify +S. */
9290 lastpos = imm_expr.X_add_number + 32;
9291 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9292 imm_expr.X_op = O_absent;
9297 /* cins, cins32, exts and exts32 position field. Move to
9298 the next candidate if it's not in the valid range. */
9299 my_getExpression (&imm_expr, s);
9300 check_absolute_expr (ip, &imm_expr);
9301 if ((unsigned) imm_expr.X_add_number < 32
9302 || (unsigned) imm_expr.X_add_number > 63)
9304 lastpos = imm_expr.X_add_number;
9305 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9306 imm_expr.X_op = O_absent;
9311 /* cins and exts length-minus-one field. */
9312 my_getExpression (&imm_expr, s);
9313 check_absolute_expr (ip, &imm_expr);
9314 if ((unsigned long) imm_expr.X_add_number > 31)
9316 as_bad (_("Improper size (%lu)"),
9317 (unsigned long) imm_expr.X_add_number);
9318 imm_expr.X_add_number = 0;
9320 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9321 imm_expr.X_op = O_absent;
9326 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9327 length-minus-one field. */
9328 my_getExpression (&imm_expr, s);
9329 check_absolute_expr (ip, &imm_expr);
9330 if ((long) imm_expr.X_add_number < 0
9331 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9333 as_bad (_("Improper size (%lu)"),
9334 (unsigned long) imm_expr.X_add_number);
9335 imm_expr.X_add_number = 0;
9337 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9338 imm_expr.X_op = O_absent;
9343 /* seqi/snei immediate field. */
9344 my_getExpression (&imm_expr, s);
9345 check_absolute_expr (ip, &imm_expr);
9346 if ((long) imm_expr.X_add_number < -512
9347 || (long) imm_expr.X_add_number >= 512)
9349 as_bad (_("Improper immediate (%ld)"),
9350 (long) imm_expr.X_add_number);
9351 imm_expr.X_add_number = 0;
9353 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9354 imm_expr.X_op = O_absent;
9359 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9360 *args, insn->name, insn->args);
9361 /* Further processing is fruitless. */
9366 case '<': /* must be at least one digit */
9368 * According to the manual, if the shift amount is greater
9369 * than 31 or less than 0, then the shift amount should be
9370 * mod 32. In reality the mips assembler issues an error.
9371 * We issue a warning and mask out all but the low 5 bits.
9373 my_getExpression (&imm_expr, s);
9374 check_absolute_expr (ip, &imm_expr);
9375 if ((unsigned long) imm_expr.X_add_number > 31)
9376 as_warn (_("Improper shift amount (%lu)"),
9377 (unsigned long) imm_expr.X_add_number);
9378 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9379 imm_expr.X_op = O_absent;
9383 case '>': /* shift amount minus 32 */
9384 my_getExpression (&imm_expr, s);
9385 check_absolute_expr (ip, &imm_expr);
9386 if ((unsigned long) imm_expr.X_add_number < 32
9387 || (unsigned long) imm_expr.X_add_number > 63)
9389 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9390 imm_expr.X_op = O_absent;
9394 case 'k': /* cache code */
9395 case 'h': /* prefx code */
9396 case '1': /* sync type */
9397 my_getExpression (&imm_expr, s);
9398 check_absolute_expr (ip, &imm_expr);
9399 if ((unsigned long) imm_expr.X_add_number > 31)
9400 as_warn (_("Invalid value for `%s' (%lu)"),
9402 (unsigned long) imm_expr.X_add_number);
9404 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9405 else if (*args == 'h')
9406 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9408 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9409 imm_expr.X_op = O_absent;
9413 case 'c': /* break code */
9414 my_getExpression (&imm_expr, s);
9415 check_absolute_expr (ip, &imm_expr);
9416 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9417 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9419 (unsigned long) imm_expr.X_add_number);
9420 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9421 imm_expr.X_op = O_absent;
9425 case 'q': /* lower break code */
9426 my_getExpression (&imm_expr, s);
9427 check_absolute_expr (ip, &imm_expr);
9428 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9429 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9431 (unsigned long) imm_expr.X_add_number);
9432 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9433 imm_expr.X_op = O_absent;
9437 case 'B': /* 20-bit syscall/break code. */
9438 my_getExpression (&imm_expr, s);
9439 check_absolute_expr (ip, &imm_expr);
9440 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9441 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9443 (unsigned long) imm_expr.X_add_number);
9444 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9445 imm_expr.X_op = O_absent;
9449 case 'C': /* Coprocessor code */
9450 my_getExpression (&imm_expr, s);
9451 check_absolute_expr (ip, &imm_expr);
9452 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9454 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9455 (unsigned long) imm_expr.X_add_number);
9456 imm_expr.X_add_number &= OP_MASK_COPZ;
9458 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9459 imm_expr.X_op = O_absent;
9463 case 'J': /* 19-bit wait code. */
9464 my_getExpression (&imm_expr, s);
9465 check_absolute_expr (ip, &imm_expr);
9466 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9468 as_warn (_("Illegal 19-bit code (%lu)"),
9469 (unsigned long) imm_expr.X_add_number);
9470 imm_expr.X_add_number &= OP_MASK_CODE19;
9472 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9473 imm_expr.X_op = O_absent;
9477 case 'P': /* Performance register. */
9478 my_getExpression (&imm_expr, s);
9479 check_absolute_expr (ip, &imm_expr);
9480 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9481 as_warn (_("Invalid performance register (%lu)"),
9482 (unsigned long) imm_expr.X_add_number);
9483 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9484 imm_expr.X_op = O_absent;
9488 case 'G': /* Coprocessor destination register. */
9489 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9490 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9492 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9493 INSERT_OPERAND (RD, *ip, regno);
9502 case 'b': /* base register */
9503 case 'd': /* destination register */
9504 case 's': /* source register */
9505 case 't': /* target register */
9506 case 'r': /* both target and source */
9507 case 'v': /* both dest and source */
9508 case 'w': /* both dest and target */
9509 case 'E': /* coprocessor target register */
9510 case 'K': /* 'rdhwr' destination register */
9511 case 'x': /* ignore register name */
9512 case 'z': /* must be zero register */
9513 case 'U': /* destination register (clo/clz). */
9514 case 'g': /* coprocessor destination register */
9516 if (*args == 'E' || *args == 'K')
9517 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9520 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9521 if (regno == AT && mips_opts.at)
9523 if (mips_opts.at == ATREG)
9524 as_warn (_("used $at without \".set noat\""));
9526 as_warn (_("used $%u with \".set at=$%u\""),
9527 regno, mips_opts.at);
9537 if (c == 'r' || c == 'v' || c == 'w')
9544 /* 'z' only matches $0. */
9545 if (c == 'z' && regno != 0)
9548 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9550 if (regno == lastregno)
9552 insn_error = _("source and destination must be different");
9555 if (regno == 31 && lastregno == 0xffffffff)
9557 insn_error = _("a destination register must be supplied");
9561 /* Now that we have assembled one operand, we use the args string
9562 * to figure out where it goes in the instruction. */
9569 INSERT_OPERAND (RS, *ip, regno);
9575 INSERT_OPERAND (RD, *ip, regno);
9578 INSERT_OPERAND (RD, *ip, regno);
9579 INSERT_OPERAND (RT, *ip, regno);
9584 INSERT_OPERAND (RT, *ip, regno);
9587 /* This case exists because on the r3000 trunc
9588 expands into a macro which requires a gp
9589 register. On the r6000 or r4000 it is
9590 assembled into a single instruction which
9591 ignores the register. Thus the insn version
9592 is MIPS_ISA2 and uses 'x', and the macro
9593 version is MIPS_ISA1 and uses 't'. */
9596 /* This case is for the div instruction, which
9597 acts differently if the destination argument
9598 is $0. This only matches $0, and is checked
9599 outside the switch. */
9602 /* Itbl operand; not yet implemented. FIXME ?? */
9604 /* What about all other operands like 'i', which
9605 can be specified in the opcode table? */
9614 INSERT_OPERAND (RS, *ip, lastregno);
9617 INSERT_OPERAND (RT, *ip, lastregno);
9622 case 'O': /* MDMX alignment immediate constant. */
9623 my_getExpression (&imm_expr, s);
9624 check_absolute_expr (ip, &imm_expr);
9625 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9626 as_warn (_("Improper align amount (%ld), using low bits"),
9627 (long) imm_expr.X_add_number);
9628 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9629 imm_expr.X_op = O_absent;
9633 case 'Q': /* MDMX vector, element sel, or const. */
9636 /* MDMX Immediate. */
9637 my_getExpression (&imm_expr, s);
9638 check_absolute_expr (ip, &imm_expr);
9639 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9640 as_warn (_("Invalid MDMX Immediate (%ld)"),
9641 (long) imm_expr.X_add_number);
9642 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9643 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9644 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9646 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9647 imm_expr.X_op = O_absent;
9651 /* Not MDMX Immediate. Fall through. */
9652 case 'X': /* MDMX destination register. */
9653 case 'Y': /* MDMX source register. */
9654 case 'Z': /* MDMX target register. */
9656 case 'D': /* floating point destination register */
9657 case 'S': /* floating point source register */
9658 case 'T': /* floating point target register */
9659 case 'R': /* floating point source register */
9664 || (mips_opts.ase_mdmx
9665 && (ip->insn_mo->pinfo & FP_D)
9666 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9667 | INSN_COPROC_MEMORY_DELAY
9668 | INSN_LOAD_COPROC_DELAY
9669 | INSN_LOAD_MEMORY_DELAY
9670 | INSN_STORE_MEMORY))))
9673 if (reg_lookup (&s, rtype, ®no))
9675 if ((regno & 1) != 0
9677 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9678 as_warn (_("Float register should be even, was %d"),
9686 if (c == 'V' || c == 'W')
9697 INSERT_OPERAND (FD, *ip, regno);
9702 INSERT_OPERAND (FS, *ip, regno);
9705 /* This is like 'Z', but also needs to fix the MDMX
9706 vector/scalar select bits. Note that the
9707 scalar immediate case is handled above. */
9710 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9711 int max_el = (is_qh ? 3 : 7);
9713 my_getExpression(&imm_expr, s);
9714 check_absolute_expr (ip, &imm_expr);
9716 if (imm_expr.X_add_number > max_el)
9717 as_bad (_("Bad element selector %ld"),
9718 (long) imm_expr.X_add_number);
9719 imm_expr.X_add_number &= max_el;
9720 ip->insn_opcode |= (imm_expr.X_add_number
9723 imm_expr.X_op = O_absent;
9725 as_warn (_("Expecting ']' found '%s'"), s);
9731 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9732 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9735 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9742 INSERT_OPERAND (FT, *ip, regno);
9745 INSERT_OPERAND (FR, *ip, regno);
9755 INSERT_OPERAND (FS, *ip, lastregno);
9758 INSERT_OPERAND (FT, *ip, lastregno);
9764 my_getExpression (&imm_expr, s);
9765 if (imm_expr.X_op != O_big
9766 && imm_expr.X_op != O_constant)
9767 insn_error = _("absolute expression required");
9768 if (HAVE_32BIT_GPRS)
9769 normalize_constant_expr (&imm_expr);
9774 my_getExpression (&offset_expr, s);
9775 normalize_address_expr (&offset_expr);
9776 *imm_reloc = BFD_RELOC_32;
9789 unsigned char temp[8];
9791 unsigned int length;
9796 /* These only appear as the last operand in an
9797 instruction, and every instruction that accepts
9798 them in any variant accepts them in all variants.
9799 This means we don't have to worry about backing out
9800 any changes if the instruction does not match.
9802 The difference between them is the size of the
9803 floating point constant and where it goes. For 'F'
9804 and 'L' the constant is 64 bits; for 'f' and 'l' it
9805 is 32 bits. Where the constant is placed is based
9806 on how the MIPS assembler does things:
9809 f -- immediate value
9812 The .lit4 and .lit8 sections are only used if
9813 permitted by the -G argument.
9815 The code below needs to know whether the target register
9816 is 32 or 64 bits wide. It relies on the fact 'f' and
9817 'F' are used with GPR-based instructions and 'l' and
9818 'L' are used with FPR-based instructions. */
9820 f64 = *args == 'F' || *args == 'L';
9821 using_gprs = *args == 'F' || *args == 'f';
9823 save_in = input_line_pointer;
9824 input_line_pointer = s;
9825 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9827 s = input_line_pointer;
9828 input_line_pointer = save_in;
9829 if (err != NULL && *err != '\0')
9831 as_bad (_("Bad floating point constant: %s"), err);
9832 memset (temp, '\0', sizeof temp);
9833 length = f64 ? 8 : 4;
9836 gas_assert (length == (unsigned) (f64 ? 8 : 4));
9840 && (g_switch_value < 4
9841 || (temp[0] == 0 && temp[1] == 0)
9842 || (temp[2] == 0 && temp[3] == 0))))
9844 imm_expr.X_op = O_constant;
9845 if (! target_big_endian)
9846 imm_expr.X_add_number = bfd_getl32 (temp);
9848 imm_expr.X_add_number = bfd_getb32 (temp);
9851 && ! mips_disable_float_construction
9852 /* Constants can only be constructed in GPRs and
9853 copied to FPRs if the GPRs are at least as wide
9854 as the FPRs. Force the constant into memory if
9855 we are using 64-bit FPRs but the GPRs are only
9858 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9859 && ((temp[0] == 0 && temp[1] == 0)
9860 || (temp[2] == 0 && temp[3] == 0))
9861 && ((temp[4] == 0 && temp[5] == 0)
9862 || (temp[6] == 0 && temp[7] == 0)))
9864 /* The value is simple enough to load with a couple of
9865 instructions. If using 32-bit registers, set
9866 imm_expr to the high order 32 bits and offset_expr to
9867 the low order 32 bits. Otherwise, set imm_expr to
9868 the entire 64 bit constant. */
9869 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9871 imm_expr.X_op = O_constant;
9872 offset_expr.X_op = O_constant;
9873 if (! target_big_endian)
9875 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9876 offset_expr.X_add_number = bfd_getl32 (temp);
9880 imm_expr.X_add_number = bfd_getb32 (temp);
9881 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9883 if (offset_expr.X_add_number == 0)
9884 offset_expr.X_op = O_absent;
9886 else if (sizeof (imm_expr.X_add_number) > 4)
9888 imm_expr.X_op = O_constant;
9889 if (! target_big_endian)
9890 imm_expr.X_add_number = bfd_getl64 (temp);
9892 imm_expr.X_add_number = bfd_getb64 (temp);
9896 imm_expr.X_op = O_big;
9897 imm_expr.X_add_number = 4;
9898 if (! target_big_endian)
9900 generic_bignum[0] = bfd_getl16 (temp);
9901 generic_bignum[1] = bfd_getl16 (temp + 2);
9902 generic_bignum[2] = bfd_getl16 (temp + 4);
9903 generic_bignum[3] = bfd_getl16 (temp + 6);
9907 generic_bignum[0] = bfd_getb16 (temp + 6);
9908 generic_bignum[1] = bfd_getb16 (temp + 4);
9909 generic_bignum[2] = bfd_getb16 (temp + 2);
9910 generic_bignum[3] = bfd_getb16 (temp);
9916 const char *newname;
9919 /* Switch to the right section. */
9921 subseg = now_subseg;
9924 default: /* unused default case avoids warnings. */
9926 newname = RDATA_SECTION_NAME;
9927 if (g_switch_value >= 8)
9931 newname = RDATA_SECTION_NAME;
9934 gas_assert (g_switch_value >= 4);
9938 new_seg = subseg_new (newname, (subsegT) 0);
9940 bfd_set_section_flags (stdoutput, new_seg,
9945 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9946 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9947 record_alignment (new_seg, 4);
9949 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9951 as_bad (_("Can't use floating point insn in this section"));
9953 /* Set the argument to the current address in the
9955 offset_expr.X_op = O_symbol;
9956 offset_expr.X_add_symbol = symbol_temp_new_now ();
9957 offset_expr.X_add_number = 0;
9959 /* Put the floating point number into the section. */
9960 p = frag_more ((int) length);
9961 memcpy (p, temp, length);
9963 /* Switch back to the original section. */
9964 subseg_set (seg, subseg);
9969 case 'i': /* 16 bit unsigned immediate */
9970 case 'j': /* 16 bit signed immediate */
9971 *imm_reloc = BFD_RELOC_LO16;
9972 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9975 offsetT minval, maxval;
9977 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9978 && strcmp (insn->name, insn[1].name) == 0);
9980 /* If the expression was written as an unsigned number,
9981 only treat it as signed if there are no more
9985 && sizeof (imm_expr.X_add_number) <= 4
9986 && imm_expr.X_op == O_constant
9987 && imm_expr.X_add_number < 0
9988 && imm_expr.X_unsigned
9992 /* For compatibility with older assemblers, we accept
9993 0x8000-0xffff as signed 16-bit numbers when only
9994 signed numbers are allowed. */
9996 minval = 0, maxval = 0xffff;
9998 minval = -0x8000, maxval = 0x7fff;
10000 minval = -0x8000, maxval = 0xffff;
10002 if (imm_expr.X_op != O_constant
10003 || imm_expr.X_add_number < minval
10004 || imm_expr.X_add_number > maxval)
10008 if (imm_expr.X_op == O_constant
10009 || imm_expr.X_op == O_big)
10010 as_bad (_("expression out of range"));
10016 case 'o': /* 16 bit offset */
10017 /* Check whether there is only a single bracketed expression
10018 left. If so, it must be the base register and the
10019 constant must be zero. */
10020 if (*s == '(' && strchr (s + 1, '(') == 0)
10022 offset_expr.X_op = O_constant;
10023 offset_expr.X_add_number = 0;
10027 /* If this value won't fit into a 16 bit offset, then go
10028 find a macro that will generate the 32 bit offset
10030 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10031 && (offset_expr.X_op != O_constant
10032 || offset_expr.X_add_number >= 0x8000
10033 || offset_expr.X_add_number < -0x8000))
10039 case 'p': /* pc relative offset */
10040 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10041 my_getExpression (&offset_expr, s);
10045 case 'u': /* upper 16 bits */
10046 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10047 && imm_expr.X_op == O_constant
10048 && (imm_expr.X_add_number < 0
10049 || imm_expr.X_add_number >= 0x10000))
10050 as_bad (_("lui expression not in range 0..65535"));
10054 case 'a': /* 26 bit address */
10055 my_getExpression (&offset_expr, s);
10057 *offset_reloc = BFD_RELOC_MIPS_JMP;
10060 case 'N': /* 3 bit branch condition code */
10061 case 'M': /* 3 bit compare condition code */
10063 if (ip->insn_mo->pinfo & (FP_D| FP_S))
10064 rtype |= RTYPE_FCC;
10065 if (!reg_lookup (&s, rtype, ®no))
10067 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
10068 || strcmp(str + strlen(str) - 5, "any2f") == 0
10069 || strcmp(str + strlen(str) - 5, "any2t") == 0)
10070 && (regno & 1) != 0)
10071 as_warn (_("Condition code register should be even for %s, was %d"),
10073 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
10074 || strcmp(str + strlen(str) - 5, "any4t") == 0)
10075 && (regno & 3) != 0)
10076 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
10079 INSERT_OPERAND (BCC, *ip, regno);
10081 INSERT_OPERAND (CCC, *ip, regno);
10085 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10096 while (ISDIGIT (*s));
10099 c = 8; /* Invalid sel value. */
10102 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10103 ip->insn_opcode |= c;
10107 /* Must be at least one digit. */
10108 my_getExpression (&imm_expr, s);
10109 check_absolute_expr (ip, &imm_expr);
10111 if ((unsigned long) imm_expr.X_add_number
10112 > (unsigned long) OP_MASK_VECBYTE)
10114 as_bad (_("bad byte vector index (%ld)"),
10115 (long) imm_expr.X_add_number);
10116 imm_expr.X_add_number = 0;
10119 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10120 imm_expr.X_op = O_absent;
10125 my_getExpression (&imm_expr, s);
10126 check_absolute_expr (ip, &imm_expr);
10128 if ((unsigned long) imm_expr.X_add_number
10129 > (unsigned long) OP_MASK_VECALIGN)
10131 as_bad (_("bad byte vector index (%ld)"),
10132 (long) imm_expr.X_add_number);
10133 imm_expr.X_add_number = 0;
10136 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10137 imm_expr.X_op = O_absent;
10142 as_bad (_("bad char = '%c'\n"), *args);
10147 /* Args don't match. */
10148 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10149 !strcmp (insn->name, insn[1].name))
10153 insn_error = _("illegal operands");
10157 *(--argsStart) = save_c;
10158 insn_error = _("illegal operands");
10163 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10165 /* This routine assembles an instruction into its binary format when
10166 assembling for the mips16. As a side effect, it sets one of the
10167 global variables imm_reloc or offset_reloc to the type of
10168 relocation to do if one of the operands is an address expression.
10169 It also sets mips16_small and mips16_ext if the user explicitly
10170 requested a small or extended instruction. */
10173 mips16_ip (char *str, struct mips_cl_insn *ip)
10177 struct mips_opcode *insn;
10179 unsigned int regno;
10180 unsigned int lastregno = 0;
10186 mips16_small = FALSE;
10187 mips16_ext = FALSE;
10189 for (s = str; ISLOWER (*s); ++s)
10201 if (s[1] == 't' && s[2] == ' ')
10204 mips16_small = TRUE;
10208 else if (s[1] == 'e' && s[2] == ' ')
10215 /* Fall through. */
10217 insn_error = _("unknown opcode");
10221 if (mips_opts.noautoextend && ! mips16_ext)
10222 mips16_small = TRUE;
10224 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10226 insn_error = _("unrecognized opcode");
10235 gas_assert (strcmp (insn->name, str) == 0);
10237 ok = is_opcode_valid_16 (insn);
10240 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10241 && strcmp (insn->name, insn[1].name) == 0)
10250 static char buf[100];
10252 _("opcode not supported on this processor: %s (%s)"),
10253 mips_cpu_info_from_arch (mips_opts.arch)->name,
10254 mips_cpu_info_from_isa (mips_opts.isa)->name);
10261 create_insn (ip, insn);
10262 imm_expr.X_op = O_absent;
10263 imm_reloc[0] = BFD_RELOC_UNUSED;
10264 imm_reloc[1] = BFD_RELOC_UNUSED;
10265 imm_reloc[2] = BFD_RELOC_UNUSED;
10266 imm2_expr.X_op = O_absent;
10267 offset_expr.X_op = O_absent;
10268 offset_reloc[0] = BFD_RELOC_UNUSED;
10269 offset_reloc[1] = BFD_RELOC_UNUSED;
10270 offset_reloc[2] = BFD_RELOC_UNUSED;
10271 for (args = insn->args; 1; ++args)
10278 /* In this switch statement we call break if we did not find
10279 a match, continue if we did find a match, or return if we
10288 /* Stuff the immediate value in now, if we can. */
10289 if (imm_expr.X_op == O_constant
10290 && *imm_reloc > BFD_RELOC_UNUSED
10291 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10292 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10293 && insn->pinfo != INSN_MACRO)
10297 switch (*offset_reloc)
10299 case BFD_RELOC_MIPS16_HI16_S:
10300 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10303 case BFD_RELOC_MIPS16_HI16:
10304 tmp = imm_expr.X_add_number >> 16;
10307 case BFD_RELOC_MIPS16_LO16:
10308 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10312 case BFD_RELOC_UNUSED:
10313 tmp = imm_expr.X_add_number;
10319 *offset_reloc = BFD_RELOC_UNUSED;
10321 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10322 tmp, TRUE, mips16_small,
10323 mips16_ext, &ip->insn_opcode,
10324 &ip->use_extend, &ip->extend);
10325 imm_expr.X_op = O_absent;
10326 *imm_reloc = BFD_RELOC_UNUSED;
10340 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10343 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10359 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10361 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10365 /* Fall through. */
10376 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10378 if (c == 'v' || c == 'w')
10381 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10383 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10394 if (c == 'v' || c == 'w')
10396 regno = mips16_to_32_reg_map[lastregno];
10410 regno = mips32_to_16_reg_map[regno];
10415 regno = ILLEGAL_REG;
10420 regno = ILLEGAL_REG;
10425 regno = ILLEGAL_REG;
10430 if (regno == AT && mips_opts.at)
10432 if (mips_opts.at == ATREG)
10433 as_warn (_("used $at without \".set noat\""));
10435 as_warn (_("used $%u with \".set at=$%u\""),
10436 regno, mips_opts.at);
10444 if (regno == ILLEGAL_REG)
10451 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10455 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10458 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10461 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10467 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10470 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10471 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10481 if (strncmp (s, "$pc", 3) == 0)
10498 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10501 if (imm_expr.X_op != O_constant)
10504 ip->use_extend = TRUE;
10509 /* We need to relax this instruction. */
10510 *offset_reloc = *imm_reloc;
10511 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10516 *imm_reloc = BFD_RELOC_UNUSED;
10517 /* Fall through. */
10524 my_getExpression (&imm_expr, s);
10525 if (imm_expr.X_op == O_register)
10527 /* What we thought was an expression turned out to
10530 if (s[0] == '(' && args[1] == '(')
10532 /* It looks like the expression was omitted
10533 before a register indirection, which means
10534 that the expression is implicitly zero. We
10535 still set up imm_expr, so that we handle
10536 explicit extensions correctly. */
10537 imm_expr.X_op = O_constant;
10538 imm_expr.X_add_number = 0;
10539 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10546 /* We need to relax this instruction. */
10547 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10556 /* We use offset_reloc rather than imm_reloc for the PC
10557 relative operands. This lets macros with both
10558 immediate and address operands work correctly. */
10559 my_getExpression (&offset_expr, s);
10561 if (offset_expr.X_op == O_register)
10564 /* We need to relax this instruction. */
10565 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10569 case '6': /* break code */
10570 my_getExpression (&imm_expr, s);
10571 check_absolute_expr (ip, &imm_expr);
10572 if ((unsigned long) imm_expr.X_add_number > 63)
10573 as_warn (_("Invalid value for `%s' (%lu)"),
10575 (unsigned long) imm_expr.X_add_number);
10576 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10577 imm_expr.X_op = O_absent;
10581 case 'a': /* 26 bit address */
10582 my_getExpression (&offset_expr, s);
10584 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10585 ip->insn_opcode <<= 16;
10588 case 'l': /* register list for entry macro */
10589 case 'L': /* register list for exit macro */
10599 unsigned int freg, reg1, reg2;
10601 while (*s == ' ' || *s == ',')
10603 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10605 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10609 as_bad (_("can't parse register list"));
10619 if (!reg_lookup (&s, freg ? RTYPE_FPU
10620 : (RTYPE_GP | RTYPE_NUM), ®2))
10622 as_bad (_("invalid register list"));
10626 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10628 mask &= ~ (7 << 3);
10631 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10633 mask &= ~ (7 << 3);
10636 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10637 mask |= (reg2 - 3) << 3;
10638 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10639 mask |= (reg2 - 15) << 1;
10640 else if (reg1 == RA && reg2 == RA)
10644 as_bad (_("invalid register list"));
10648 /* The mask is filled in in the opcode table for the
10649 benefit of the disassembler. We remove it before
10650 applying the actual mask. */
10651 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10652 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10656 case 'm': /* Register list for save insn. */
10657 case 'M': /* Register list for restore insn. */
10660 int framesz = 0, seen_framesz = 0;
10661 int nargs = 0, statics = 0, sregs = 0;
10665 unsigned int reg1, reg2;
10667 SKIP_SPACE_TABS (s);
10670 SKIP_SPACE_TABS (s);
10672 my_getExpression (&imm_expr, s);
10673 if (imm_expr.X_op == O_constant)
10675 /* Handle the frame size. */
10678 as_bad (_("more than one frame size in list"));
10682 framesz = imm_expr.X_add_number;
10683 imm_expr.X_op = O_absent;
10688 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10690 as_bad (_("can't parse register list"));
10702 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10705 as_bad (_("can't parse register list"));
10710 while (reg1 <= reg2)
10712 if (reg1 >= 4 && reg1 <= 7)
10716 nargs |= 1 << (reg1 - 4);
10718 /* statics $a0-$a3 */
10719 statics |= 1 << (reg1 - 4);
10721 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10724 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10726 else if (reg1 == 31)
10728 /* Add $ra to insn. */
10733 as_bad (_("unexpected register in list"));
10741 /* Encode args/statics combination. */
10742 if (nargs & statics)
10743 as_bad (_("arg/static registers overlap"));
10744 else if (nargs == 0xf)
10745 /* All $a0-$a3 are args. */
10746 opcode |= MIPS16_ALL_ARGS << 16;
10747 else if (statics == 0xf)
10748 /* All $a0-$a3 are statics. */
10749 opcode |= MIPS16_ALL_STATICS << 16;
10752 int narg = 0, nstat = 0;
10754 /* Count arg registers. */
10755 while (nargs & 0x1)
10761 as_bad (_("invalid arg register list"));
10763 /* Count static registers. */
10764 while (statics & 0x8)
10766 statics = (statics << 1) & 0xf;
10770 as_bad (_("invalid static register list"));
10772 /* Encode args/statics. */
10773 opcode |= ((narg << 2) | nstat) << 16;
10776 /* Encode $s0/$s1. */
10777 if (sregs & (1 << 0)) /* $s0 */
10779 if (sregs & (1 << 1)) /* $s1 */
10785 /* Count regs $s2-$s8. */
10793 as_bad (_("invalid static register list"));
10794 /* Encode $s2-$s8. */
10795 opcode |= nsreg << 24;
10798 /* Encode frame size. */
10800 as_bad (_("missing frame size"));
10801 else if ((framesz & 7) != 0 || framesz < 0
10802 || framesz > 0xff * 8)
10803 as_bad (_("invalid frame size"));
10804 else if (framesz != 128 || (opcode >> 16) != 0)
10807 opcode |= (((framesz & 0xf0) << 16)
10808 | (framesz & 0x0f));
10811 /* Finally build the instruction. */
10812 if ((opcode >> 16) != 0 || framesz == 0)
10814 ip->use_extend = TRUE;
10815 ip->extend = opcode >> 16;
10817 ip->insn_opcode |= opcode & 0x7f;
10821 case 'e': /* extend code */
10822 my_getExpression (&imm_expr, s);
10823 check_absolute_expr (ip, &imm_expr);
10824 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10826 as_warn (_("Invalid value for `%s' (%lu)"),
10828 (unsigned long) imm_expr.X_add_number);
10829 imm_expr.X_add_number &= 0x7ff;
10831 ip->insn_opcode |= imm_expr.X_add_number;
10832 imm_expr.X_op = O_absent;
10842 /* Args don't match. */
10843 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10844 strcmp (insn->name, insn[1].name) == 0)
10851 insn_error = _("illegal operands");
10857 /* This structure holds information we know about a mips16 immediate
10860 struct mips16_immed_operand
10862 /* The type code used in the argument string in the opcode table. */
10864 /* The number of bits in the short form of the opcode. */
10866 /* The number of bits in the extended form of the opcode. */
10868 /* The amount by which the short form is shifted when it is used;
10869 for example, the sw instruction has a shift count of 2. */
10871 /* The amount by which the short form is shifted when it is stored
10872 into the instruction code. */
10874 /* Non-zero if the short form is unsigned. */
10876 /* Non-zero if the extended form is unsigned. */
10878 /* Non-zero if the value is PC relative. */
10882 /* The mips16 immediate operand types. */
10884 static const struct mips16_immed_operand mips16_immed_operands[] =
10886 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10887 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10888 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10889 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10890 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10891 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10892 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10893 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10894 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10895 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10896 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10897 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10898 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10899 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10900 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10901 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10902 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10903 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10904 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10905 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10906 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10909 #define MIPS16_NUM_IMMED \
10910 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10912 /* Handle a mips16 instruction with an immediate value. This or's the
10913 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10914 whether an extended value is needed; if one is needed, it sets
10915 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10916 If SMALL is true, an unextended opcode was explicitly requested.
10917 If EXT is true, an extended opcode was explicitly requested. If
10918 WARN is true, warn if EXT does not match reality. */
10921 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10922 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10923 unsigned long *insn, bfd_boolean *use_extend,
10924 unsigned short *extend)
10926 const struct mips16_immed_operand *op;
10927 int mintiny, maxtiny;
10928 bfd_boolean needext;
10930 op = mips16_immed_operands;
10931 while (op->type != type)
10934 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10939 if (type == '<' || type == '>' || type == '[' || type == ']')
10942 maxtiny = 1 << op->nbits;
10947 maxtiny = (1 << op->nbits) - 1;
10952 mintiny = - (1 << (op->nbits - 1));
10953 maxtiny = (1 << (op->nbits - 1)) - 1;
10956 /* Branch offsets have an implicit 0 in the lowest bit. */
10957 if (type == 'p' || type == 'q')
10960 if ((val & ((1 << op->shift) - 1)) != 0
10961 || val < (mintiny << op->shift)
10962 || val > (maxtiny << op->shift))
10967 if (warn && ext && ! needext)
10968 as_warn_where (file, line,
10969 _("extended operand requested but not required"));
10970 if (small && needext)
10971 as_bad_where (file, line, _("invalid unextended operand value"));
10973 if (small || (! ext && ! needext))
10977 *use_extend = FALSE;
10978 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10979 insnval <<= op->op_shift;
10984 long minext, maxext;
10990 maxext = (1 << op->extbits) - 1;
10994 minext = - (1 << (op->extbits - 1));
10995 maxext = (1 << (op->extbits - 1)) - 1;
10997 if (val < minext || val > maxext)
10998 as_bad_where (file, line,
10999 _("operand value out of range for instruction"));
11001 *use_extend = TRUE;
11002 if (op->extbits == 16)
11004 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11007 else if (op->extbits == 15)
11009 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11014 extval = ((val & 0x1f) << 6) | (val & 0x20);
11018 *extend = (unsigned short) extval;
11023 struct percent_op_match
11026 bfd_reloc_code_real_type reloc;
11029 static const struct percent_op_match mips_percent_op[] =
11031 {"%lo", BFD_RELOC_LO16},
11033 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11034 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11035 {"%call16", BFD_RELOC_MIPS_CALL16},
11036 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11037 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11038 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11039 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11040 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11041 {"%got", BFD_RELOC_MIPS_GOT16},
11042 {"%gp_rel", BFD_RELOC_GPREL16},
11043 {"%half", BFD_RELOC_16},
11044 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11045 {"%higher", BFD_RELOC_MIPS_HIGHER},
11046 {"%neg", BFD_RELOC_MIPS_SUB},
11047 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11048 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11049 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11050 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11051 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11052 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11053 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11055 {"%hi", BFD_RELOC_HI16_S}
11058 static const struct percent_op_match mips16_percent_op[] =
11060 {"%lo", BFD_RELOC_MIPS16_LO16},
11061 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11062 {"%got", BFD_RELOC_MIPS16_GOT16},
11063 {"%call16", BFD_RELOC_MIPS16_CALL16},
11064 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11068 /* Return true if *STR points to a relocation operator. When returning true,
11069 move *STR over the operator and store its relocation code in *RELOC.
11070 Leave both *STR and *RELOC alone when returning false. */
11073 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11075 const struct percent_op_match *percent_op;
11078 if (mips_opts.mips16)
11080 percent_op = mips16_percent_op;
11081 limit = ARRAY_SIZE (mips16_percent_op);
11085 percent_op = mips_percent_op;
11086 limit = ARRAY_SIZE (mips_percent_op);
11089 for (i = 0; i < limit; i++)
11090 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11092 int len = strlen (percent_op[i].str);
11094 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11097 *str += strlen (percent_op[i].str);
11098 *reloc = percent_op[i].reloc;
11100 /* Check whether the output BFD supports this relocation.
11101 If not, issue an error and fall back on something safe. */
11102 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11104 as_bad (_("relocation %s isn't supported by the current ABI"),
11105 percent_op[i].str);
11106 *reloc = BFD_RELOC_UNUSED;
11114 /* Parse string STR as a 16-bit relocatable operand. Store the
11115 expression in *EP and the relocations in the array starting
11116 at RELOC. Return the number of relocation operators used.
11118 On exit, EXPR_END points to the first character after the expression. */
11121 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11124 bfd_reloc_code_real_type reversed_reloc[3];
11125 size_t reloc_index, i;
11126 int crux_depth, str_depth;
11129 /* Search for the start of the main expression, recoding relocations
11130 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11131 of the main expression and with CRUX_DEPTH containing the number
11132 of open brackets at that point. */
11139 crux_depth = str_depth;
11141 /* Skip over whitespace and brackets, keeping count of the number
11143 while (*str == ' ' || *str == '\t' || *str == '(')
11148 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11149 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11151 my_getExpression (ep, crux);
11154 /* Match every open bracket. */
11155 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11159 if (crux_depth > 0)
11160 as_bad (_("unclosed '('"));
11164 if (reloc_index != 0)
11166 prev_reloc_op_frag = frag_now;
11167 for (i = 0; i < reloc_index; i++)
11168 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11171 return reloc_index;
11175 my_getExpression (expressionS *ep, char *str)
11180 save_in = input_line_pointer;
11181 input_line_pointer = str;
11183 expr_end = input_line_pointer;
11184 input_line_pointer = save_in;
11186 /* If we are in mips16 mode, and this is an expression based on `.',
11187 then we bump the value of the symbol by 1 since that is how other
11188 text symbols are handled. We don't bother to handle complex
11189 expressions, just `.' plus or minus a constant. */
11190 if (mips_opts.mips16
11191 && ep->X_op == O_symbol
11192 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11193 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11194 && symbol_get_frag (ep->X_add_symbol) == frag_now
11195 && symbol_constant_p (ep->X_add_symbol)
11196 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11197 S_SET_VALUE (ep->X_add_symbol, val + 1);
11201 md_atof (int type, char *litP, int *sizeP)
11203 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11207 md_number_to_chars (char *buf, valueT val, int n)
11209 if (target_big_endian)
11210 number_to_chars_bigendian (buf, val, n);
11212 number_to_chars_littleendian (buf, val, n);
11216 static int support_64bit_objects(void)
11218 const char **list, **l;
11221 list = bfd_target_list ();
11222 for (l = list; *l != NULL; l++)
11224 /* This is traditional mips */
11225 if (strcmp (*l, "elf64-tradbigmips") == 0
11226 || strcmp (*l, "elf64-tradlittlemips") == 0)
11228 if (strcmp (*l, "elf64-bigmips") == 0
11229 || strcmp (*l, "elf64-littlemips") == 0)
11232 yes = (*l != NULL);
11236 #endif /* OBJ_ELF */
11238 const char *md_shortopts = "O::g::G:";
11242 OPTION_MARCH = OPTION_MD_BASE,
11264 OPTION_NO_SMARTMIPS,
11267 OPTION_COMPAT_ARCH_BASE,
11276 OPTION_M7000_HILO_FIX,
11277 OPTION_MNO_7000_HILO_FIX,
11280 OPTION_FIX_LOONGSON2F_JUMP,
11281 OPTION_NO_FIX_LOONGSON2F_JUMP,
11282 OPTION_FIX_LOONGSON2F_NOP,
11283 OPTION_NO_FIX_LOONGSON2F_NOP,
11285 OPTION_NO_FIX_VR4120,
11287 OPTION_NO_FIX_VR4130,
11294 OPTION_CONSTRUCT_FLOATS,
11295 OPTION_NO_CONSTRUCT_FLOATS,
11298 OPTION_RELAX_BRANCH,
11299 OPTION_NO_RELAX_BRANCH,
11306 OPTION_SINGLE_FLOAT,
11307 OPTION_DOUBLE_FLOAT,
11310 OPTION_CALL_SHARED,
11311 OPTION_CALL_NONPIC,
11321 OPTION_MVXWORKS_PIC,
11322 #endif /* OBJ_ELF */
11326 struct option md_longopts[] =
11328 /* Options which specify architecture. */
11329 {"march", required_argument, NULL, OPTION_MARCH},
11330 {"mtune", required_argument, NULL, OPTION_MTUNE},
11331 {"mips0", no_argument, NULL, OPTION_MIPS1},
11332 {"mips1", no_argument, NULL, OPTION_MIPS1},
11333 {"mips2", no_argument, NULL, OPTION_MIPS2},
11334 {"mips3", no_argument, NULL, OPTION_MIPS3},
11335 {"mips4", no_argument, NULL, OPTION_MIPS4},
11336 {"mips5", no_argument, NULL, OPTION_MIPS5},
11337 {"mips32", no_argument, NULL, OPTION_MIPS32},
11338 {"mips64", no_argument, NULL, OPTION_MIPS64},
11339 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11340 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11342 /* Options which specify Application Specific Extensions (ASEs). */
11343 {"mips16", no_argument, NULL, OPTION_MIPS16},
11344 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11345 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11346 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11347 {"mdmx", no_argument, NULL, OPTION_MDMX},
11348 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11349 {"mdsp", no_argument, NULL, OPTION_DSP},
11350 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11351 {"mmt", no_argument, NULL, OPTION_MT},
11352 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11353 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11354 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11355 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11356 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11358 /* Old-style architecture options. Don't add more of these. */
11359 {"m4650", no_argument, NULL, OPTION_M4650},
11360 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11361 {"m4010", no_argument, NULL, OPTION_M4010},
11362 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11363 {"m4100", no_argument, NULL, OPTION_M4100},
11364 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11365 {"m3900", no_argument, NULL, OPTION_M3900},
11366 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11368 /* Options which enable bug fixes. */
11369 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11370 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11371 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11372 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11373 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11374 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11375 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11376 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11377 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11378 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11379 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11380 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11381 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11383 /* Miscellaneous options. */
11384 {"trap", no_argument, NULL, OPTION_TRAP},
11385 {"no-break", no_argument, NULL, OPTION_TRAP},
11386 {"break", no_argument, NULL, OPTION_BREAK},
11387 {"no-trap", no_argument, NULL, OPTION_BREAK},
11388 {"EB", no_argument, NULL, OPTION_EB},
11389 {"EL", no_argument, NULL, OPTION_EL},
11390 {"mfp32", no_argument, NULL, OPTION_FP32},
11391 {"mgp32", no_argument, NULL, OPTION_GP32},
11392 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11393 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11394 {"mfp64", no_argument, NULL, OPTION_FP64},
11395 {"mgp64", no_argument, NULL, OPTION_GP64},
11396 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11397 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11398 {"mshared", no_argument, NULL, OPTION_MSHARED},
11399 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11400 {"msym32", no_argument, NULL, OPTION_MSYM32},
11401 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11402 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11403 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11404 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11405 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11407 /* Strictly speaking this next option is ELF specific,
11408 but we allow it for other ports as well in order to
11409 make testing easier. */
11410 {"32", no_argument, NULL, OPTION_32},
11412 /* ELF-specific options. */
11414 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11415 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11416 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11417 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11418 {"xgot", no_argument, NULL, OPTION_XGOT},
11419 {"mabi", required_argument, NULL, OPTION_MABI},
11420 {"n32", no_argument, NULL, OPTION_N32},
11421 {"64", no_argument, NULL, OPTION_64},
11422 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11423 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11424 {"mpdr", no_argument, NULL, OPTION_PDR},
11425 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11426 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11427 #endif /* OBJ_ELF */
11429 {NULL, no_argument, NULL, 0}
11431 size_t md_longopts_size = sizeof (md_longopts);
11433 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11434 NEW_VALUE. Warn if another value was already specified. Note:
11435 we have to defer parsing the -march and -mtune arguments in order
11436 to handle 'from-abi' correctly, since the ABI might be specified
11437 in a later argument. */
11440 mips_set_option_string (const char **string_ptr, const char *new_value)
11442 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11443 as_warn (_("A different %s was already specified, is now %s"),
11444 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11447 *string_ptr = new_value;
11451 md_parse_option (int c, char *arg)
11455 case OPTION_CONSTRUCT_FLOATS:
11456 mips_disable_float_construction = 0;
11459 case OPTION_NO_CONSTRUCT_FLOATS:
11460 mips_disable_float_construction = 1;
11472 target_big_endian = 1;
11476 target_big_endian = 0;
11482 else if (arg[0] == '0')
11484 else if (arg[0] == '1')
11494 mips_debug = atoi (arg);
11498 file_mips_isa = ISA_MIPS1;
11502 file_mips_isa = ISA_MIPS2;
11506 file_mips_isa = ISA_MIPS3;
11510 file_mips_isa = ISA_MIPS4;
11514 file_mips_isa = ISA_MIPS5;
11517 case OPTION_MIPS32:
11518 file_mips_isa = ISA_MIPS32;
11521 case OPTION_MIPS32R2:
11522 file_mips_isa = ISA_MIPS32R2;
11525 case OPTION_MIPS64R2:
11526 file_mips_isa = ISA_MIPS64R2;
11529 case OPTION_MIPS64:
11530 file_mips_isa = ISA_MIPS64;
11534 mips_set_option_string (&mips_tune_string, arg);
11538 mips_set_option_string (&mips_arch_string, arg);
11542 mips_set_option_string (&mips_arch_string, "4650");
11543 mips_set_option_string (&mips_tune_string, "4650");
11546 case OPTION_NO_M4650:
11550 mips_set_option_string (&mips_arch_string, "4010");
11551 mips_set_option_string (&mips_tune_string, "4010");
11554 case OPTION_NO_M4010:
11558 mips_set_option_string (&mips_arch_string, "4100");
11559 mips_set_option_string (&mips_tune_string, "4100");
11562 case OPTION_NO_M4100:
11566 mips_set_option_string (&mips_arch_string, "3900");
11567 mips_set_option_string (&mips_tune_string, "3900");
11570 case OPTION_NO_M3900:
11574 mips_opts.ase_mdmx = 1;
11577 case OPTION_NO_MDMX:
11578 mips_opts.ase_mdmx = 0;
11582 mips_opts.ase_dsp = 1;
11583 mips_opts.ase_dspr2 = 0;
11586 case OPTION_NO_DSP:
11587 mips_opts.ase_dsp = 0;
11588 mips_opts.ase_dspr2 = 0;
11592 mips_opts.ase_dspr2 = 1;
11593 mips_opts.ase_dsp = 1;
11596 case OPTION_NO_DSPR2:
11597 mips_opts.ase_dspr2 = 0;
11598 mips_opts.ase_dsp = 0;
11602 mips_opts.ase_mt = 1;
11606 mips_opts.ase_mt = 0;
11609 case OPTION_MIPS16:
11610 mips_opts.mips16 = 1;
11611 mips_no_prev_insn ();
11614 case OPTION_NO_MIPS16:
11615 mips_opts.mips16 = 0;
11616 mips_no_prev_insn ();
11619 case OPTION_MIPS3D:
11620 mips_opts.ase_mips3d = 1;
11623 case OPTION_NO_MIPS3D:
11624 mips_opts.ase_mips3d = 0;
11627 case OPTION_SMARTMIPS:
11628 mips_opts.ase_smartmips = 1;
11631 case OPTION_NO_SMARTMIPS:
11632 mips_opts.ase_smartmips = 0;
11635 case OPTION_FIX_24K:
11639 case OPTION_NO_FIX_24K:
11643 case OPTION_FIX_LOONGSON2F_JUMP:
11644 mips_fix_loongson2f_jump = TRUE;
11647 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11648 mips_fix_loongson2f_jump = FALSE;
11651 case OPTION_FIX_LOONGSON2F_NOP:
11652 mips_fix_loongson2f_nop = TRUE;
11655 case OPTION_NO_FIX_LOONGSON2F_NOP:
11656 mips_fix_loongson2f_nop = FALSE;
11659 case OPTION_FIX_VR4120:
11660 mips_fix_vr4120 = 1;
11663 case OPTION_NO_FIX_VR4120:
11664 mips_fix_vr4120 = 0;
11667 case OPTION_FIX_VR4130:
11668 mips_fix_vr4130 = 1;
11671 case OPTION_NO_FIX_VR4130:
11672 mips_fix_vr4130 = 0;
11675 case OPTION_RELAX_BRANCH:
11676 mips_relax_branch = 1;
11679 case OPTION_NO_RELAX_BRANCH:
11680 mips_relax_branch = 0;
11683 case OPTION_MSHARED:
11684 mips_in_shared = TRUE;
11687 case OPTION_MNO_SHARED:
11688 mips_in_shared = FALSE;
11691 case OPTION_MSYM32:
11692 mips_opts.sym32 = TRUE;
11695 case OPTION_MNO_SYM32:
11696 mips_opts.sym32 = FALSE;
11700 /* When generating ELF code, we permit -KPIC and -call_shared to
11701 select SVR4_PIC, and -non_shared to select no PIC. This is
11702 intended to be compatible with Irix 5. */
11703 case OPTION_CALL_SHARED:
11706 as_bad (_("-call_shared is supported only for ELF format"));
11709 mips_pic = SVR4_PIC;
11710 mips_abicalls = TRUE;
11713 case OPTION_CALL_NONPIC:
11716 as_bad (_("-call_nonpic is supported only for ELF format"));
11720 mips_abicalls = TRUE;
11723 case OPTION_NON_SHARED:
11726 as_bad (_("-non_shared is supported only for ELF format"));
11730 mips_abicalls = FALSE;
11733 /* The -xgot option tells the assembler to use 32 bit offsets
11734 when accessing the got in SVR4_PIC mode. It is for Irix
11739 #endif /* OBJ_ELF */
11742 g_switch_value = atoi (arg);
11746 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11750 mips_abi = O32_ABI;
11751 /* We silently ignore -32 for non-ELF targets. This greatly
11752 simplifies the construction of the MIPS GAS test cases. */
11759 as_bad (_("-n32 is supported for ELF format only"));
11762 mips_abi = N32_ABI;
11768 as_bad (_("-64 is supported for ELF format only"));
11771 mips_abi = N64_ABI;
11772 if (!support_64bit_objects())
11773 as_fatal (_("No compiled in support for 64 bit object file format"));
11775 #endif /* OBJ_ELF */
11778 file_mips_gp32 = 1;
11782 file_mips_gp32 = 0;
11786 file_mips_fp32 = 1;
11790 file_mips_fp32 = 0;
11793 case OPTION_SINGLE_FLOAT:
11794 file_mips_single_float = 1;
11797 case OPTION_DOUBLE_FLOAT:
11798 file_mips_single_float = 0;
11801 case OPTION_SOFT_FLOAT:
11802 file_mips_soft_float = 1;
11805 case OPTION_HARD_FLOAT:
11806 file_mips_soft_float = 0;
11813 as_bad (_("-mabi is supported for ELF format only"));
11816 if (strcmp (arg, "32") == 0)
11817 mips_abi = O32_ABI;
11818 else if (strcmp (arg, "o64") == 0)
11819 mips_abi = O64_ABI;
11820 else if (strcmp (arg, "n32") == 0)
11821 mips_abi = N32_ABI;
11822 else if (strcmp (arg, "64") == 0)
11824 mips_abi = N64_ABI;
11825 if (! support_64bit_objects())
11826 as_fatal (_("No compiled in support for 64 bit object file "
11829 else if (strcmp (arg, "eabi") == 0)
11830 mips_abi = EABI_ABI;
11833 as_fatal (_("invalid abi -mabi=%s"), arg);
11837 #endif /* OBJ_ELF */
11839 case OPTION_M7000_HILO_FIX:
11840 mips_7000_hilo_fix = TRUE;
11843 case OPTION_MNO_7000_HILO_FIX:
11844 mips_7000_hilo_fix = FALSE;
11848 case OPTION_MDEBUG:
11849 mips_flag_mdebug = TRUE;
11852 case OPTION_NO_MDEBUG:
11853 mips_flag_mdebug = FALSE;
11857 mips_flag_pdr = TRUE;
11860 case OPTION_NO_PDR:
11861 mips_flag_pdr = FALSE;
11864 case OPTION_MVXWORKS_PIC:
11865 mips_pic = VXWORKS_PIC;
11867 #endif /* OBJ_ELF */
11873 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
11878 /* Set up globals to generate code for the ISA or processor
11879 described by INFO. */
11882 mips_set_architecture (const struct mips_cpu_info *info)
11886 file_mips_arch = info->cpu;
11887 mips_opts.arch = info->cpu;
11888 mips_opts.isa = info->isa;
11893 /* Likewise for tuning. */
11896 mips_set_tune (const struct mips_cpu_info *info)
11899 mips_tune = info->cpu;
11904 mips_after_parse_args (void)
11906 const struct mips_cpu_info *arch_info = 0;
11907 const struct mips_cpu_info *tune_info = 0;
11909 /* GP relative stuff not working for PE */
11910 if (strncmp (TARGET_OS, "pe", 2) == 0)
11912 if (g_switch_seen && g_switch_value != 0)
11913 as_bad (_("-G not supported in this configuration."));
11914 g_switch_value = 0;
11917 if (mips_abi == NO_ABI)
11918 mips_abi = MIPS_DEFAULT_ABI;
11920 /* The following code determines the architecture and register size.
11921 Similar code was added to GCC 3.3 (see override_options() in
11922 config/mips/mips.c). The GAS and GCC code should be kept in sync
11923 as much as possible. */
11925 if (mips_arch_string != 0)
11926 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11928 if (file_mips_isa != ISA_UNKNOWN)
11930 /* Handle -mipsN. At this point, file_mips_isa contains the
11931 ISA level specified by -mipsN, while arch_info->isa contains
11932 the -march selection (if any). */
11933 if (arch_info != 0)
11935 /* -march takes precedence over -mipsN, since it is more descriptive.
11936 There's no harm in specifying both as long as the ISA levels
11938 if (file_mips_isa != arch_info->isa)
11939 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11940 mips_cpu_info_from_isa (file_mips_isa)->name,
11941 mips_cpu_info_from_isa (arch_info->isa)->name);
11944 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11947 if (arch_info == 0)
11948 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11950 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11951 as_bad (_("-march=%s is not compatible with the selected ABI"),
11954 mips_set_architecture (arch_info);
11956 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11957 if (mips_tune_string != 0)
11958 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11960 if (tune_info == 0)
11961 mips_set_tune (arch_info);
11963 mips_set_tune (tune_info);
11965 if (file_mips_gp32 >= 0)
11967 /* The user specified the size of the integer registers. Make sure
11968 it agrees with the ABI and ISA. */
11969 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11970 as_bad (_("-mgp64 used with a 32-bit processor"));
11971 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11972 as_bad (_("-mgp32 used with a 64-bit ABI"));
11973 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11974 as_bad (_("-mgp64 used with a 32-bit ABI"));
11978 /* Infer the integer register size from the ABI and processor.
11979 Restrict ourselves to 32-bit registers if that's all the
11980 processor has, or if the ABI cannot handle 64-bit registers. */
11981 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11982 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11985 switch (file_mips_fp32)
11989 /* No user specified float register size.
11990 ??? GAS treats single-float processors as though they had 64-bit
11991 float registers (although it complains when double-precision
11992 instructions are used). As things stand, saying they have 32-bit
11993 registers would lead to spurious "register must be even" messages.
11994 So here we assume float registers are never smaller than the
11996 if (file_mips_gp32 == 0)
11997 /* 64-bit integer registers implies 64-bit float registers. */
11998 file_mips_fp32 = 0;
11999 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12000 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12001 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12002 file_mips_fp32 = 0;
12004 /* 32-bit float registers. */
12005 file_mips_fp32 = 1;
12008 /* The user specified the size of the float registers. Check if it
12009 agrees with the ABI and ISA. */
12011 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12012 as_bad (_("-mfp64 used with a 32-bit fpu"));
12013 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12014 && !ISA_HAS_MXHC1 (mips_opts.isa))
12015 as_warn (_("-mfp64 used with a 32-bit ABI"));
12018 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12019 as_warn (_("-mfp32 used with a 64-bit ABI"));
12023 /* End of GCC-shared inference code. */
12025 /* This flag is set when we have a 64-bit capable CPU but use only
12026 32-bit wide registers. Note that EABI does not use it. */
12027 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12028 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12029 || mips_abi == O32_ABI))
12030 mips_32bitmode = 1;
12032 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12033 as_bad (_("trap exception not supported at ISA 1"));
12035 /* If the selected architecture includes support for ASEs, enable
12036 generation of code for them. */
12037 if (mips_opts.mips16 == -1)
12038 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12039 if (mips_opts.ase_mips3d == -1)
12040 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12041 && file_mips_fp32 == 0) ? 1 : 0;
12042 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12043 as_bad (_("-mfp32 used with -mips3d"));
12045 if (mips_opts.ase_mdmx == -1)
12046 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12047 && file_mips_fp32 == 0) ? 1 : 0;
12048 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12049 as_bad (_("-mfp32 used with -mdmx"));
12051 if (mips_opts.ase_smartmips == -1)
12052 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12053 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12054 as_warn (_("%s ISA does not support SmartMIPS"),
12055 mips_cpu_info_from_isa (mips_opts.isa)->name);
12057 if (mips_opts.ase_dsp == -1)
12058 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12059 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12060 as_warn (_("%s ISA does not support DSP ASE"),
12061 mips_cpu_info_from_isa (mips_opts.isa)->name);
12063 if (mips_opts.ase_dspr2 == -1)
12065 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12066 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12068 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12069 as_warn (_("%s ISA does not support DSP R2 ASE"),
12070 mips_cpu_info_from_isa (mips_opts.isa)->name);
12072 if (mips_opts.ase_mt == -1)
12073 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12074 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12075 as_warn (_("%s ISA does not support MT ASE"),
12076 mips_cpu_info_from_isa (mips_opts.isa)->name);
12078 file_mips_isa = mips_opts.isa;
12079 file_ase_mips16 = mips_opts.mips16;
12080 file_ase_mips3d = mips_opts.ase_mips3d;
12081 file_ase_mdmx = mips_opts.ase_mdmx;
12082 file_ase_smartmips = mips_opts.ase_smartmips;
12083 file_ase_dsp = mips_opts.ase_dsp;
12084 file_ase_dspr2 = mips_opts.ase_dspr2;
12085 file_ase_mt = mips_opts.ase_mt;
12086 mips_opts.gp32 = file_mips_gp32;
12087 mips_opts.fp32 = file_mips_fp32;
12088 mips_opts.soft_float = file_mips_soft_float;
12089 mips_opts.single_float = file_mips_single_float;
12091 if (mips_flag_mdebug < 0)
12093 #ifdef OBJ_MAYBE_ECOFF
12094 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12095 mips_flag_mdebug = 1;
12097 #endif /* OBJ_MAYBE_ECOFF */
12098 mips_flag_mdebug = 0;
12103 mips_init_after_args (void)
12105 /* initialize opcodes */
12106 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12107 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12111 md_pcrel_from (fixS *fixP)
12113 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12114 switch (fixP->fx_r_type)
12116 case BFD_RELOC_16_PCREL_S2:
12117 case BFD_RELOC_MIPS_JMP:
12118 /* Return the address of the delay slot. */
12121 /* We have no relocation type for PC relative MIPS16 instructions. */
12122 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12123 as_bad_where (fixP->fx_file, fixP->fx_line,
12124 _("PC relative MIPS16 instruction references a different section"));
12129 /* This is called before the symbol table is processed. In order to
12130 work with gcc when using mips-tfile, we must keep all local labels.
12131 However, in other cases, we want to discard them. If we were
12132 called with -g, but we didn't see any debugging information, it may
12133 mean that gcc is smuggling debugging information through to
12134 mips-tfile, in which case we must generate all local labels. */
12137 mips_frob_file_before_adjust (void)
12139 #ifndef NO_ECOFF_DEBUGGING
12140 if (ECOFF_DEBUGGING
12142 && ! ecoff_debugging_seen)
12143 flag_keep_locals = 1;
12147 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12148 the corresponding LO16 reloc. This is called before md_apply_fix and
12149 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12150 relocation operators.
12152 For our purposes, a %lo() expression matches a %got() or %hi()
12155 (a) it refers to the same symbol; and
12156 (b) the offset applied in the %lo() expression is no lower than
12157 the offset applied in the %got() or %hi().
12159 (b) allows us to cope with code like:
12162 lh $4,%lo(foo+2)($4)
12164 ...which is legal on RELA targets, and has a well-defined behaviour
12165 if the user knows that adding 2 to "foo" will not induce a carry to
12168 When several %lo()s match a particular %got() or %hi(), we use the
12169 following rules to distinguish them:
12171 (1) %lo()s with smaller offsets are a better match than %lo()s with
12174 (2) %lo()s with no matching %got() or %hi() are better than those
12175 that already have a matching %got() or %hi().
12177 (3) later %lo()s are better than earlier %lo()s.
12179 These rules are applied in order.
12181 (1) means, among other things, that %lo()s with identical offsets are
12182 chosen if they exist.
12184 (2) means that we won't associate several high-part relocations with
12185 the same low-part relocation unless there's no alternative. Having
12186 several high parts for the same low part is a GNU extension; this rule
12187 allows careful users to avoid it.
12189 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12190 with the last high-part relocation being at the front of the list.
12191 It therefore makes sense to choose the last matching low-part
12192 relocation, all other things being equal. It's also easier
12193 to code that way. */
12196 mips_frob_file (void)
12198 struct mips_hi_fixup *l;
12199 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12201 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12203 segment_info_type *seginfo;
12204 bfd_boolean matched_lo_p;
12205 fixS **hi_pos, **lo_pos, **pos;
12207 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12209 /* If a GOT16 relocation turns out to be against a global symbol,
12210 there isn't supposed to be a matching LO. */
12211 if (got16_reloc_p (l->fixp->fx_r_type)
12212 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12215 /* Check quickly whether the next fixup happens to be a matching %lo. */
12216 if (fixup_has_matching_lo_p (l->fixp))
12219 seginfo = seg_info (l->seg);
12221 /* Set HI_POS to the position of this relocation in the chain.
12222 Set LO_POS to the position of the chosen low-part relocation.
12223 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12224 relocation that matches an immediately-preceding high-part
12228 matched_lo_p = FALSE;
12229 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12231 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12233 if (*pos == l->fixp)
12236 if ((*pos)->fx_r_type == looking_for_rtype
12237 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12238 && (*pos)->fx_offset >= l->fixp->fx_offset
12240 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12242 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12245 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12246 && fixup_has_matching_lo_p (*pos));
12249 /* If we found a match, remove the high-part relocation from its
12250 current position and insert it before the low-part relocation.
12251 Make the offsets match so that fixup_has_matching_lo_p()
12254 We don't warn about unmatched high-part relocations since some
12255 versions of gcc have been known to emit dead "lui ...%hi(...)"
12257 if (lo_pos != NULL)
12259 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12260 if (l->fixp->fx_next != *lo_pos)
12262 *hi_pos = l->fixp->fx_next;
12263 l->fixp->fx_next = *lo_pos;
12270 /* We may have combined relocations without symbols in the N32/N64 ABI.
12271 We have to prevent gas from dropping them. */
12274 mips_force_relocation (fixS *fixp)
12276 if (generic_force_reloc (fixp))
12280 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12281 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12282 || hi16_reloc_p (fixp->fx_r_type)
12283 || lo16_reloc_p (fixp->fx_r_type)))
12289 /* Apply a fixup to the object file. */
12292 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12296 reloc_howto_type *howto;
12298 /* We ignore generic BFD relocations we don't know about. */
12299 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12303 gas_assert (fixP->fx_size == 4
12304 || fixP->fx_r_type == BFD_RELOC_16
12305 || fixP->fx_r_type == BFD_RELOC_64
12306 || fixP->fx_r_type == BFD_RELOC_CTOR
12307 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12308 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12309 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12310 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12312 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12314 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12316 /* Don't treat parts of a composite relocation as done. There are two
12319 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12320 should nevertheless be emitted if the first part is.
12322 (2) In normal usage, composite relocations are never assembly-time
12323 constants. The easiest way of dealing with the pathological
12324 exceptions is to generate a relocation against STN_UNDEF and
12325 leave everything up to the linker. */
12326 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12329 switch (fixP->fx_r_type)
12331 case BFD_RELOC_MIPS_TLS_GD:
12332 case BFD_RELOC_MIPS_TLS_LDM:
12333 case BFD_RELOC_MIPS_TLS_DTPREL32:
12334 case BFD_RELOC_MIPS_TLS_DTPREL64:
12335 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12336 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12337 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12338 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12339 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12340 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12343 case BFD_RELOC_MIPS_JMP:
12344 case BFD_RELOC_MIPS_SHIFT5:
12345 case BFD_RELOC_MIPS_SHIFT6:
12346 case BFD_RELOC_MIPS_GOT_DISP:
12347 case BFD_RELOC_MIPS_GOT_PAGE:
12348 case BFD_RELOC_MIPS_GOT_OFST:
12349 case BFD_RELOC_MIPS_SUB:
12350 case BFD_RELOC_MIPS_INSERT_A:
12351 case BFD_RELOC_MIPS_INSERT_B:
12352 case BFD_RELOC_MIPS_DELETE:
12353 case BFD_RELOC_MIPS_HIGHEST:
12354 case BFD_RELOC_MIPS_HIGHER:
12355 case BFD_RELOC_MIPS_SCN_DISP:
12356 case BFD_RELOC_MIPS_REL16:
12357 case BFD_RELOC_MIPS_RELGOT:
12358 case BFD_RELOC_MIPS_JALR:
12359 case BFD_RELOC_HI16:
12360 case BFD_RELOC_HI16_S:
12361 case BFD_RELOC_GPREL16:
12362 case BFD_RELOC_MIPS_LITERAL:
12363 case BFD_RELOC_MIPS_CALL16:
12364 case BFD_RELOC_MIPS_GOT16:
12365 case BFD_RELOC_GPREL32:
12366 case BFD_RELOC_MIPS_GOT_HI16:
12367 case BFD_RELOC_MIPS_GOT_LO16:
12368 case BFD_RELOC_MIPS_CALL_HI16:
12369 case BFD_RELOC_MIPS_CALL_LO16:
12370 case BFD_RELOC_MIPS16_GPREL:
12371 case BFD_RELOC_MIPS16_GOT16:
12372 case BFD_RELOC_MIPS16_CALL16:
12373 case BFD_RELOC_MIPS16_HI16:
12374 case BFD_RELOC_MIPS16_HI16_S:
12375 case BFD_RELOC_MIPS16_JMP:
12376 /* Nothing needed to do. The value comes from the reloc entry. */
12380 /* This is handled like BFD_RELOC_32, but we output a sign
12381 extended value if we are only 32 bits. */
12384 if (8 <= sizeof (valueT))
12385 md_number_to_chars ((char *) buf, *valP, 8);
12390 if ((*valP & 0x80000000) != 0)
12394 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12396 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12402 case BFD_RELOC_RVA:
12405 /* If we are deleting this reloc entry, we must fill in the
12406 value now. This can happen if we have a .word which is not
12407 resolved when it appears but is later defined. */
12409 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12412 case BFD_RELOC_LO16:
12413 case BFD_RELOC_MIPS16_LO16:
12414 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12415 may be safe to remove, but if so it's not obvious. */
12416 /* When handling an embedded PIC switch statement, we can wind
12417 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12420 if (*valP + 0x8000 > 0xffff)
12421 as_bad_where (fixP->fx_file, fixP->fx_line,
12422 _("relocation overflow"));
12423 if (target_big_endian)
12425 md_number_to_chars ((char *) buf, *valP, 2);
12429 case BFD_RELOC_16_PCREL_S2:
12430 if ((*valP & 0x3) != 0)
12431 as_bad_where (fixP->fx_file, fixP->fx_line,
12432 _("Branch to misaligned address (%lx)"), (long) *valP);
12434 /* We need to save the bits in the instruction since fixup_segment()
12435 might be deleting the relocation entry (i.e., a branch within
12436 the current segment). */
12437 if (! fixP->fx_done)
12440 /* Update old instruction data. */
12441 if (target_big_endian)
12442 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12444 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12446 if (*valP + 0x20000 <= 0x3ffff)
12448 insn |= (*valP >> 2) & 0xffff;
12449 md_number_to_chars ((char *) buf, insn, 4);
12451 else if (mips_pic == NO_PIC
12453 && fixP->fx_frag->fr_address >= text_section->vma
12454 && (fixP->fx_frag->fr_address
12455 < text_section->vma + bfd_get_section_size (text_section))
12456 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12457 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12458 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12460 /* The branch offset is too large. If this is an
12461 unconditional branch, and we are not generating PIC code,
12462 we can convert it to an absolute jump instruction. */
12463 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12464 insn = 0x0c000000; /* jal */
12466 insn = 0x08000000; /* j */
12467 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12469 fixP->fx_addsy = section_symbol (text_section);
12470 *valP += md_pcrel_from (fixP);
12471 md_number_to_chars ((char *) buf, insn, 4);
12475 /* If we got here, we have branch-relaxation disabled,
12476 and there's nothing we can do to fix this instruction
12477 without turning it into a longer sequence. */
12478 as_bad_where (fixP->fx_file, fixP->fx_line,
12479 _("Branch out of range"));
12483 case BFD_RELOC_VTABLE_INHERIT:
12486 && !S_IS_DEFINED (fixP->fx_addsy)
12487 && !S_IS_WEAK (fixP->fx_addsy))
12488 S_SET_WEAK (fixP->fx_addsy);
12491 case BFD_RELOC_VTABLE_ENTRY:
12499 /* Remember value for tc_gen_reloc. */
12500 fixP->fx_addnumber = *valP;
12510 name = input_line_pointer;
12511 c = get_symbol_end ();
12512 p = (symbolS *) symbol_find_or_make (name);
12513 *input_line_pointer = c;
12517 /* Align the current frag to a given power of two. If a particular
12518 fill byte should be used, FILL points to an integer that contains
12519 that byte, otherwise FILL is null.
12521 The MIPS assembler also automatically adjusts any preceding
12525 mips_align (int to, int *fill, symbolS *label)
12527 mips_emit_delays ();
12528 mips_record_mips16_mode ();
12529 if (fill == NULL && subseg_text_p (now_seg))
12530 frag_align_code (to, 0);
12532 frag_align (to, fill ? *fill : 0, 0);
12533 record_alignment (now_seg, to);
12536 gas_assert (S_GET_SEGMENT (label) == now_seg);
12537 symbol_set_frag (label, frag_now);
12538 S_SET_VALUE (label, (valueT) frag_now_fix ());
12542 /* Align to a given power of two. .align 0 turns off the automatic
12543 alignment used by the data creating pseudo-ops. */
12546 s_align (int x ATTRIBUTE_UNUSED)
12548 int temp, fill_value, *fill_ptr;
12549 long max_alignment = 28;
12551 /* o Note that the assembler pulls down any immediately preceding label
12552 to the aligned address.
12553 o It's not documented but auto alignment is reinstated by
12554 a .align pseudo instruction.
12555 o Note also that after auto alignment is turned off the mips assembler
12556 issues an error on attempt to assemble an improperly aligned data item.
12559 temp = get_absolute_expression ();
12560 if (temp > max_alignment)
12561 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12564 as_warn (_("Alignment negative: 0 assumed."));
12567 if (*input_line_pointer == ',')
12569 ++input_line_pointer;
12570 fill_value = get_absolute_expression ();
12571 fill_ptr = &fill_value;
12577 segment_info_type *si = seg_info (now_seg);
12578 struct insn_label_list *l = si->label_list;
12579 /* Auto alignment should be switched on by next section change. */
12581 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12588 demand_empty_rest_of_line ();
12592 s_change_sec (int sec)
12597 /* The ELF backend needs to know that we are changing sections, so
12598 that .previous works correctly. We could do something like check
12599 for an obj_section_change_hook macro, but that might be confusing
12600 as it would not be appropriate to use it in the section changing
12601 functions in read.c, since obj-elf.c intercepts those. FIXME:
12602 This should be cleaner, somehow. */
12604 obj_elf_section_change_hook ();
12607 mips_emit_delays ();
12618 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12619 demand_empty_rest_of_line ();
12623 seg = subseg_new (RDATA_SECTION_NAME,
12624 (subsegT) get_absolute_expression ());
12627 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12628 | SEC_READONLY | SEC_RELOC
12630 if (strncmp (TARGET_OS, "elf", 3) != 0)
12631 record_alignment (seg, 4);
12633 demand_empty_rest_of_line ();
12637 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12640 bfd_set_section_flags (stdoutput, seg,
12641 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12642 if (strncmp (TARGET_OS, "elf", 3) != 0)
12643 record_alignment (seg, 4);
12645 demand_empty_rest_of_line ();
12653 s_change_section (int ignore ATTRIBUTE_UNUSED)
12656 char *section_name;
12661 int section_entry_size;
12662 int section_alignment;
12667 section_name = input_line_pointer;
12668 c = get_symbol_end ();
12670 next_c = *(input_line_pointer + 1);
12672 /* Do we have .section Name<,"flags">? */
12673 if (c != ',' || (c == ',' && next_c == '"'))
12675 /* just after name is now '\0'. */
12676 *input_line_pointer = c;
12677 input_line_pointer = section_name;
12678 obj_elf_section (ignore);
12681 input_line_pointer++;
12683 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12685 section_type = get_absolute_expression ();
12688 if (*input_line_pointer++ == ',')
12689 section_flag = get_absolute_expression ();
12692 if (*input_line_pointer++ == ',')
12693 section_entry_size = get_absolute_expression ();
12695 section_entry_size = 0;
12696 if (*input_line_pointer++ == ',')
12697 section_alignment = get_absolute_expression ();
12699 section_alignment = 0;
12700 /* FIXME: really ignore? */
12701 (void) section_alignment;
12703 section_name = xstrdup (section_name);
12705 /* When using the generic form of .section (as implemented by obj-elf.c),
12706 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12707 traditionally had to fall back on the more common @progbits instead.
12709 There's nothing really harmful in this, since bfd will correct
12710 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12711 means that, for backwards compatibility, the special_section entries
12712 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12714 Even so, we shouldn't force users of the MIPS .section syntax to
12715 incorrectly label the sections as SHT_PROGBITS. The best compromise
12716 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12717 generic type-checking code. */
12718 if (section_type == SHT_MIPS_DWARF)
12719 section_type = SHT_PROGBITS;
12721 obj_elf_change_section (section_name, section_type, section_flag,
12722 section_entry_size, 0, 0, 0);
12724 if (now_seg->name != section_name)
12725 free (section_name);
12726 #endif /* OBJ_ELF */
12730 mips_enable_auto_align (void)
12736 s_cons (int log_size)
12738 segment_info_type *si = seg_info (now_seg);
12739 struct insn_label_list *l = si->label_list;
12742 label = l != NULL ? l->label : NULL;
12743 mips_emit_delays ();
12744 if (log_size > 0 && auto_align)
12745 mips_align (log_size, 0, label);
12746 mips_clear_insn_labels ();
12747 cons (1 << log_size);
12751 s_float_cons (int type)
12753 segment_info_type *si = seg_info (now_seg);
12754 struct insn_label_list *l = si->label_list;
12757 label = l != NULL ? l->label : NULL;
12759 mips_emit_delays ();
12764 mips_align (3, 0, label);
12766 mips_align (2, 0, label);
12769 mips_clear_insn_labels ();
12774 /* Handle .globl. We need to override it because on Irix 5 you are
12777 where foo is an undefined symbol, to mean that foo should be
12778 considered to be the address of a function. */
12781 s_mips_globl (int x ATTRIBUTE_UNUSED)
12790 name = input_line_pointer;
12791 c = get_symbol_end ();
12792 symbolP = symbol_find_or_make (name);
12793 S_SET_EXTERNAL (symbolP);
12795 *input_line_pointer = c;
12796 SKIP_WHITESPACE ();
12798 /* On Irix 5, every global symbol that is not explicitly labelled as
12799 being a function is apparently labelled as being an object. */
12802 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12803 && (*input_line_pointer != ','))
12808 secname = input_line_pointer;
12809 c = get_symbol_end ();
12810 sec = bfd_get_section_by_name (stdoutput, secname);
12812 as_bad (_("%s: no such section"), secname);
12813 *input_line_pointer = c;
12815 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12816 flag = BSF_FUNCTION;
12819 symbol_get_bfdsym (symbolP)->flags |= flag;
12821 c = *input_line_pointer;
12824 input_line_pointer++;
12825 SKIP_WHITESPACE ();
12826 if (is_end_of_line[(unsigned char) *input_line_pointer])
12832 demand_empty_rest_of_line ();
12836 s_option (int x ATTRIBUTE_UNUSED)
12841 opt = input_line_pointer;
12842 c = get_symbol_end ();
12846 /* FIXME: What does this mean? */
12848 else if (strncmp (opt, "pic", 3) == 0)
12852 i = atoi (opt + 3);
12857 mips_pic = SVR4_PIC;
12858 mips_abicalls = TRUE;
12861 as_bad (_(".option pic%d not supported"), i);
12863 if (mips_pic == SVR4_PIC)
12865 if (g_switch_seen && g_switch_value != 0)
12866 as_warn (_("-G may not be used with SVR4 PIC code"));
12867 g_switch_value = 0;
12868 bfd_set_gp_size (stdoutput, 0);
12872 as_warn (_("Unrecognized option \"%s\""), opt);
12874 *input_line_pointer = c;
12875 demand_empty_rest_of_line ();
12878 /* This structure is used to hold a stack of .set values. */
12880 struct mips_option_stack
12882 struct mips_option_stack *next;
12883 struct mips_set_options options;
12886 static struct mips_option_stack *mips_opts_stack;
12888 /* Handle the .set pseudo-op. */
12891 s_mipsset (int x ATTRIBUTE_UNUSED)
12893 char *name = input_line_pointer, ch;
12895 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12896 ++input_line_pointer;
12897 ch = *input_line_pointer;
12898 *input_line_pointer = '\0';
12900 if (strcmp (name, "reorder") == 0)
12902 if (mips_opts.noreorder)
12905 else if (strcmp (name, "noreorder") == 0)
12907 if (!mips_opts.noreorder)
12908 start_noreorder ();
12910 else if (strncmp (name, "at=", 3) == 0)
12912 char *s = name + 3;
12914 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12915 as_bad (_("Unrecognized register name `%s'"), s);
12917 else if (strcmp (name, "at") == 0)
12919 mips_opts.at = ATREG;
12921 else if (strcmp (name, "noat") == 0)
12923 mips_opts.at = ZERO;
12925 else if (strcmp (name, "macro") == 0)
12927 mips_opts.warn_about_macros = 0;
12929 else if (strcmp (name, "nomacro") == 0)
12931 if (mips_opts.noreorder == 0)
12932 as_bad (_("`noreorder' must be set before `nomacro'"));
12933 mips_opts.warn_about_macros = 1;
12935 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12937 mips_opts.nomove = 0;
12939 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12941 mips_opts.nomove = 1;
12943 else if (strcmp (name, "bopt") == 0)
12945 mips_opts.nobopt = 0;
12947 else if (strcmp (name, "nobopt") == 0)
12949 mips_opts.nobopt = 1;
12951 else if (strcmp (name, "gp=default") == 0)
12952 mips_opts.gp32 = file_mips_gp32;
12953 else if (strcmp (name, "gp=32") == 0)
12954 mips_opts.gp32 = 1;
12955 else if (strcmp (name, "gp=64") == 0)
12957 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12958 as_warn (_("%s isa does not support 64-bit registers"),
12959 mips_cpu_info_from_isa (mips_opts.isa)->name);
12960 mips_opts.gp32 = 0;
12962 else if (strcmp (name, "fp=default") == 0)
12963 mips_opts.fp32 = file_mips_fp32;
12964 else if (strcmp (name, "fp=32") == 0)
12965 mips_opts.fp32 = 1;
12966 else if (strcmp (name, "fp=64") == 0)
12968 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12969 as_warn (_("%s isa does not support 64-bit floating point registers"),
12970 mips_cpu_info_from_isa (mips_opts.isa)->name);
12971 mips_opts.fp32 = 0;
12973 else if (strcmp (name, "softfloat") == 0)
12974 mips_opts.soft_float = 1;
12975 else if (strcmp (name, "hardfloat") == 0)
12976 mips_opts.soft_float = 0;
12977 else if (strcmp (name, "singlefloat") == 0)
12978 mips_opts.single_float = 1;
12979 else if (strcmp (name, "doublefloat") == 0)
12980 mips_opts.single_float = 0;
12981 else if (strcmp (name, "mips16") == 0
12982 || strcmp (name, "MIPS-16") == 0)
12983 mips_opts.mips16 = 1;
12984 else if (strcmp (name, "nomips16") == 0
12985 || strcmp (name, "noMIPS-16") == 0)
12986 mips_opts.mips16 = 0;
12987 else if (strcmp (name, "smartmips") == 0)
12989 if (!ISA_SUPPORTS_SMARTMIPS)
12990 as_warn (_("%s ISA does not support SmartMIPS ASE"),
12991 mips_cpu_info_from_isa (mips_opts.isa)->name);
12992 mips_opts.ase_smartmips = 1;
12994 else if (strcmp (name, "nosmartmips") == 0)
12995 mips_opts.ase_smartmips = 0;
12996 else if (strcmp (name, "mips3d") == 0)
12997 mips_opts.ase_mips3d = 1;
12998 else if (strcmp (name, "nomips3d") == 0)
12999 mips_opts.ase_mips3d = 0;
13000 else if (strcmp (name, "mdmx") == 0)
13001 mips_opts.ase_mdmx = 1;
13002 else if (strcmp (name, "nomdmx") == 0)
13003 mips_opts.ase_mdmx = 0;
13004 else if (strcmp (name, "dsp") == 0)
13006 if (!ISA_SUPPORTS_DSP_ASE)
13007 as_warn (_("%s ISA does not support DSP ASE"),
13008 mips_cpu_info_from_isa (mips_opts.isa)->name);
13009 mips_opts.ase_dsp = 1;
13010 mips_opts.ase_dspr2 = 0;
13012 else if (strcmp (name, "nodsp") == 0)
13014 mips_opts.ase_dsp = 0;
13015 mips_opts.ase_dspr2 = 0;
13017 else if (strcmp (name, "dspr2") == 0)
13019 if (!ISA_SUPPORTS_DSPR2_ASE)
13020 as_warn (_("%s ISA does not support DSP R2 ASE"),
13021 mips_cpu_info_from_isa (mips_opts.isa)->name);
13022 mips_opts.ase_dspr2 = 1;
13023 mips_opts.ase_dsp = 1;
13025 else if (strcmp (name, "nodspr2") == 0)
13027 mips_opts.ase_dspr2 = 0;
13028 mips_opts.ase_dsp = 0;
13030 else if (strcmp (name, "mt") == 0)
13032 if (!ISA_SUPPORTS_MT_ASE)
13033 as_warn (_("%s ISA does not support MT ASE"),
13034 mips_cpu_info_from_isa (mips_opts.isa)->name);
13035 mips_opts.ase_mt = 1;
13037 else if (strcmp (name, "nomt") == 0)
13038 mips_opts.ase_mt = 0;
13039 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13043 /* Permit the user to change the ISA and architecture on the fly.
13044 Needless to say, misuse can cause serious problems. */
13045 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13048 mips_opts.isa = file_mips_isa;
13049 mips_opts.arch = file_mips_arch;
13051 else if (strncmp (name, "arch=", 5) == 0)
13053 const struct mips_cpu_info *p;
13055 p = mips_parse_cpu("internal use", name + 5);
13057 as_bad (_("unknown architecture %s"), name + 5);
13060 mips_opts.arch = p->cpu;
13061 mips_opts.isa = p->isa;
13064 else if (strncmp (name, "mips", 4) == 0)
13066 const struct mips_cpu_info *p;
13068 p = mips_parse_cpu("internal use", name);
13070 as_bad (_("unknown ISA level %s"), name + 4);
13073 mips_opts.arch = p->cpu;
13074 mips_opts.isa = p->isa;
13078 as_bad (_("unknown ISA or architecture %s"), name);
13080 switch (mips_opts.isa)
13088 mips_opts.gp32 = 1;
13089 mips_opts.fp32 = 1;
13096 mips_opts.gp32 = 0;
13097 mips_opts.fp32 = 0;
13100 as_bad (_("unknown ISA level %s"), name + 4);
13105 mips_opts.gp32 = file_mips_gp32;
13106 mips_opts.fp32 = file_mips_fp32;
13109 else if (strcmp (name, "autoextend") == 0)
13110 mips_opts.noautoextend = 0;
13111 else if (strcmp (name, "noautoextend") == 0)
13112 mips_opts.noautoextend = 1;
13113 else if (strcmp (name, "push") == 0)
13115 struct mips_option_stack *s;
13117 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13118 s->next = mips_opts_stack;
13119 s->options = mips_opts;
13120 mips_opts_stack = s;
13122 else if (strcmp (name, "pop") == 0)
13124 struct mips_option_stack *s;
13126 s = mips_opts_stack;
13128 as_bad (_(".set pop with no .set push"));
13131 /* If we're changing the reorder mode we need to handle
13132 delay slots correctly. */
13133 if (s->options.noreorder && ! mips_opts.noreorder)
13134 start_noreorder ();
13135 else if (! s->options.noreorder && mips_opts.noreorder)
13138 mips_opts = s->options;
13139 mips_opts_stack = s->next;
13143 else if (strcmp (name, "sym32") == 0)
13144 mips_opts.sym32 = TRUE;
13145 else if (strcmp (name, "nosym32") == 0)
13146 mips_opts.sym32 = FALSE;
13147 else if (strchr (name, ','))
13149 /* Generic ".set" directive; use the generic handler. */
13150 *input_line_pointer = ch;
13151 input_line_pointer = name;
13157 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13159 *input_line_pointer = ch;
13160 demand_empty_rest_of_line ();
13163 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13164 .option pic2. It means to generate SVR4 PIC calls. */
13167 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13169 mips_pic = SVR4_PIC;
13170 mips_abicalls = TRUE;
13172 if (g_switch_seen && g_switch_value != 0)
13173 as_warn (_("-G may not be used with SVR4 PIC code"));
13174 g_switch_value = 0;
13176 bfd_set_gp_size (stdoutput, 0);
13177 demand_empty_rest_of_line ();
13180 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13181 PIC code. It sets the $gp register for the function based on the
13182 function address, which is in the register named in the argument.
13183 This uses a relocation against _gp_disp, which is handled specially
13184 by the linker. The result is:
13185 lui $gp,%hi(_gp_disp)
13186 addiu $gp,$gp,%lo(_gp_disp)
13187 addu $gp,$gp,.cpload argument
13188 The .cpload argument is normally $25 == $t9.
13190 The -mno-shared option changes this to:
13191 lui $gp,%hi(__gnu_local_gp)
13192 addiu $gp,$gp,%lo(__gnu_local_gp)
13193 and the argument is ignored. This saves an instruction, but the
13194 resulting code is not position independent; it uses an absolute
13195 address for __gnu_local_gp. Thus code assembled with -mno-shared
13196 can go into an ordinary executable, but not into a shared library. */
13199 s_cpload (int ignore ATTRIBUTE_UNUSED)
13205 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13206 .cpload is ignored. */
13207 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13213 /* .cpload should be in a .set noreorder section. */
13214 if (mips_opts.noreorder == 0)
13215 as_warn (_(".cpload not in noreorder section"));
13217 reg = tc_get_register (0);
13219 /* If we need to produce a 64-bit address, we are better off using
13220 the default instruction sequence. */
13221 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13223 ex.X_op = O_symbol;
13224 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13226 ex.X_op_symbol = NULL;
13227 ex.X_add_number = 0;
13229 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13230 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13233 macro_build_lui (&ex, mips_gp_register);
13234 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13235 mips_gp_register, BFD_RELOC_LO16);
13237 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13238 mips_gp_register, reg);
13241 demand_empty_rest_of_line ();
13244 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13245 .cpsetup $reg1, offset|$reg2, label
13247 If offset is given, this results in:
13248 sd $gp, offset($sp)
13249 lui $gp, %hi(%neg(%gp_rel(label)))
13250 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13251 daddu $gp, $gp, $reg1
13253 If $reg2 is given, this results in:
13254 daddu $reg2, $gp, $0
13255 lui $gp, %hi(%neg(%gp_rel(label)))
13256 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13257 daddu $gp, $gp, $reg1
13258 $reg1 is normally $25 == $t9.
13260 The -mno-shared option replaces the last three instructions with
13262 addiu $gp,$gp,%lo(_gp) */
13265 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13267 expressionS ex_off;
13268 expressionS ex_sym;
13271 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13272 We also need NewABI support. */
13273 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13279 reg1 = tc_get_register (0);
13280 SKIP_WHITESPACE ();
13281 if (*input_line_pointer != ',')
13283 as_bad (_("missing argument separator ',' for .cpsetup"));
13287 ++input_line_pointer;
13288 SKIP_WHITESPACE ();
13289 if (*input_line_pointer == '$')
13291 mips_cpreturn_register = tc_get_register (0);
13292 mips_cpreturn_offset = -1;
13296 mips_cpreturn_offset = get_absolute_expression ();
13297 mips_cpreturn_register = -1;
13299 SKIP_WHITESPACE ();
13300 if (*input_line_pointer != ',')
13302 as_bad (_("missing argument separator ',' for .cpsetup"));
13306 ++input_line_pointer;
13307 SKIP_WHITESPACE ();
13308 expression (&ex_sym);
13311 if (mips_cpreturn_register == -1)
13313 ex_off.X_op = O_constant;
13314 ex_off.X_add_symbol = NULL;
13315 ex_off.X_op_symbol = NULL;
13316 ex_off.X_add_number = mips_cpreturn_offset;
13318 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13319 BFD_RELOC_LO16, SP);
13322 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13323 mips_gp_register, 0);
13325 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13327 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13328 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13331 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13332 mips_gp_register, -1, BFD_RELOC_GPREL16,
13333 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13335 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13336 mips_gp_register, reg1);
13342 ex.X_op = O_symbol;
13343 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13344 ex.X_op_symbol = NULL;
13345 ex.X_add_number = 0;
13347 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13348 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13350 macro_build_lui (&ex, mips_gp_register);
13351 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13352 mips_gp_register, BFD_RELOC_LO16);
13357 demand_empty_rest_of_line ();
13361 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13363 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13364 .cplocal is ignored. */
13365 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13371 mips_gp_register = tc_get_register (0);
13372 demand_empty_rest_of_line ();
13375 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13376 offset from $sp. The offset is remembered, and after making a PIC
13377 call $gp is restored from that location. */
13380 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13384 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13385 .cprestore is ignored. */
13386 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13392 mips_cprestore_offset = get_absolute_expression ();
13393 mips_cprestore_valid = 1;
13395 ex.X_op = O_constant;
13396 ex.X_add_symbol = NULL;
13397 ex.X_op_symbol = NULL;
13398 ex.X_add_number = mips_cprestore_offset;
13401 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13402 SP, HAVE_64BIT_ADDRESSES);
13405 demand_empty_rest_of_line ();
13408 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13409 was given in the preceding .cpsetup, it results in:
13410 ld $gp, offset($sp)
13412 If a register $reg2 was given there, it results in:
13413 daddu $gp, $reg2, $0 */
13416 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13420 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13421 We also need NewABI support. */
13422 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13429 if (mips_cpreturn_register == -1)
13431 ex.X_op = O_constant;
13432 ex.X_add_symbol = NULL;
13433 ex.X_op_symbol = NULL;
13434 ex.X_add_number = mips_cpreturn_offset;
13436 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13439 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13440 mips_cpreturn_register, 0);
13443 demand_empty_rest_of_line ();
13446 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13447 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13448 use in DWARF debug information. */
13451 s_dtprel_internal (size_t bytes)
13458 if (ex.X_op != O_symbol)
13460 as_bad (_("Unsupported use of %s"), (bytes == 8
13463 ignore_rest_of_line ();
13466 p = frag_more (bytes);
13467 md_number_to_chars (p, 0, bytes);
13468 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13470 ? BFD_RELOC_MIPS_TLS_DTPREL64
13471 : BFD_RELOC_MIPS_TLS_DTPREL32));
13473 demand_empty_rest_of_line ();
13476 /* Handle .dtprelword. */
13479 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13481 s_dtprel_internal (4);
13484 /* Handle .dtpreldword. */
13487 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13489 s_dtprel_internal (8);
13492 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13493 code. It sets the offset to use in gp_rel relocations. */
13496 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13498 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13499 We also need NewABI support. */
13500 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13506 mips_gprel_offset = get_absolute_expression ();
13508 demand_empty_rest_of_line ();
13511 /* Handle the .gpword pseudo-op. This is used when generating PIC
13512 code. It generates a 32 bit GP relative reloc. */
13515 s_gpword (int ignore ATTRIBUTE_UNUSED)
13517 segment_info_type *si;
13518 struct insn_label_list *l;
13523 /* When not generating PIC code, this is treated as .word. */
13524 if (mips_pic != SVR4_PIC)
13530 si = seg_info (now_seg);
13531 l = si->label_list;
13532 label = l != NULL ? l->label : NULL;
13533 mips_emit_delays ();
13535 mips_align (2, 0, label);
13536 mips_clear_insn_labels ();
13540 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13542 as_bad (_("Unsupported use of .gpword"));
13543 ignore_rest_of_line ();
13547 md_number_to_chars (p, 0, 4);
13548 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13549 BFD_RELOC_GPREL32);
13551 demand_empty_rest_of_line ();
13555 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13557 segment_info_type *si;
13558 struct insn_label_list *l;
13563 /* When not generating PIC code, this is treated as .dword. */
13564 if (mips_pic != SVR4_PIC)
13570 si = seg_info (now_seg);
13571 l = si->label_list;
13572 label = l != NULL ? l->label : NULL;
13573 mips_emit_delays ();
13575 mips_align (3, 0, label);
13576 mips_clear_insn_labels ();
13580 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13582 as_bad (_("Unsupported use of .gpdword"));
13583 ignore_rest_of_line ();
13587 md_number_to_chars (p, 0, 8);
13588 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13589 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13591 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13592 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13593 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13595 demand_empty_rest_of_line ();
13598 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13599 tables in SVR4 PIC code. */
13602 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13606 /* This is ignored when not generating SVR4 PIC code. */
13607 if (mips_pic != SVR4_PIC)
13613 /* Add $gp to the register named as an argument. */
13615 reg = tc_get_register (0);
13616 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13619 demand_empty_rest_of_line ();
13622 /* Handle the .insn pseudo-op. This marks instruction labels in
13623 mips16 mode. This permits the linker to handle them specially,
13624 such as generating jalx instructions when needed. We also make
13625 them odd for the duration of the assembly, in order to generate the
13626 right sort of code. We will make them even in the adjust_symtab
13627 routine, while leaving them marked. This is convenient for the
13628 debugger and the disassembler. The linker knows to make them odd
13632 s_insn (int ignore ATTRIBUTE_UNUSED)
13634 mips16_mark_labels ();
13636 demand_empty_rest_of_line ();
13639 /* Handle a .stabn directive. We need these in order to mark a label
13640 as being a mips16 text label correctly. Sometimes the compiler
13641 will emit a label, followed by a .stabn, and then switch sections.
13642 If the label and .stabn are in mips16 mode, then the label is
13643 really a mips16 text label. */
13646 s_mips_stab (int type)
13649 mips16_mark_labels ();
13654 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13657 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13664 name = input_line_pointer;
13665 c = get_symbol_end ();
13666 symbolP = symbol_find_or_make (name);
13667 S_SET_WEAK (symbolP);
13668 *input_line_pointer = c;
13670 SKIP_WHITESPACE ();
13672 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13674 if (S_IS_DEFINED (symbolP))
13676 as_bad (_("ignoring attempt to redefine symbol %s"),
13677 S_GET_NAME (symbolP));
13678 ignore_rest_of_line ();
13682 if (*input_line_pointer == ',')
13684 ++input_line_pointer;
13685 SKIP_WHITESPACE ();
13689 if (exp.X_op != O_symbol)
13691 as_bad (_("bad .weakext directive"));
13692 ignore_rest_of_line ();
13695 symbol_set_value_expression (symbolP, &exp);
13698 demand_empty_rest_of_line ();
13701 /* Parse a register string into a number. Called from the ECOFF code
13702 to parse .frame. The argument is non-zero if this is the frame
13703 register, so that we can record it in mips_frame_reg. */
13706 tc_get_register (int frame)
13710 SKIP_WHITESPACE ();
13711 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13715 mips_frame_reg = reg != 0 ? reg : SP;
13716 mips_frame_reg_valid = 1;
13717 mips_cprestore_valid = 0;
13723 md_section_align (asection *seg, valueT addr)
13725 int align = bfd_get_section_alignment (stdoutput, seg);
13729 /* We don't need to align ELF sections to the full alignment.
13730 However, Irix 5 may prefer that we align them at least to a 16
13731 byte boundary. We don't bother to align the sections if we
13732 are targeted for an embedded system. */
13733 if (strncmp (TARGET_OS, "elf", 3) == 0)
13739 return ((addr + (1 << align) - 1) & (-1 << align));
13742 /* Utility routine, called from above as well. If called while the
13743 input file is still being read, it's only an approximation. (For
13744 example, a symbol may later become defined which appeared to be
13745 undefined earlier.) */
13748 nopic_need_relax (symbolS *sym, int before_relaxing)
13753 if (g_switch_value > 0)
13755 const char *symname;
13758 /* Find out whether this symbol can be referenced off the $gp
13759 register. It can be if it is smaller than the -G size or if
13760 it is in the .sdata or .sbss section. Certain symbols can
13761 not be referenced off the $gp, although it appears as though
13763 symname = S_GET_NAME (sym);
13764 if (symname != (const char *) NULL
13765 && (strcmp (symname, "eprol") == 0
13766 || strcmp (symname, "etext") == 0
13767 || strcmp (symname, "_gp") == 0
13768 || strcmp (symname, "edata") == 0
13769 || strcmp (symname, "_fbss") == 0
13770 || strcmp (symname, "_fdata") == 0
13771 || strcmp (symname, "_ftext") == 0
13772 || strcmp (symname, "end") == 0
13773 || strcmp (symname, "_gp_disp") == 0))
13775 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13777 #ifndef NO_ECOFF_DEBUGGING
13778 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13779 && (symbol_get_obj (sym)->ecoff_extern_size
13780 <= g_switch_value))
13782 /* We must defer this decision until after the whole
13783 file has been read, since there might be a .extern
13784 after the first use of this symbol. */
13785 || (before_relaxing
13786 #ifndef NO_ECOFF_DEBUGGING
13787 && symbol_get_obj (sym)->ecoff_extern_size == 0
13789 && S_GET_VALUE (sym) == 0)
13790 || (S_GET_VALUE (sym) != 0
13791 && S_GET_VALUE (sym) <= g_switch_value)))
13795 const char *segname;
13797 segname = segment_name (S_GET_SEGMENT (sym));
13798 gas_assert (strcmp (segname, ".lit8") != 0
13799 && strcmp (segname, ".lit4") != 0);
13800 change = (strcmp (segname, ".sdata") != 0
13801 && strcmp (segname, ".sbss") != 0
13802 && strncmp (segname, ".sdata.", 7) != 0
13803 && strncmp (segname, ".sbss.", 6) != 0
13804 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13805 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13810 /* We are not optimizing for the $gp register. */
13815 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13818 pic_need_relax (symbolS *sym, asection *segtype)
13822 /* Handle the case of a symbol equated to another symbol. */
13823 while (symbol_equated_reloc_p (sym))
13827 /* It's possible to get a loop here in a badly written program. */
13828 n = symbol_get_value_expression (sym)->X_add_symbol;
13834 if (symbol_section_p (sym))
13837 symsec = S_GET_SEGMENT (sym);
13839 /* This must duplicate the test in adjust_reloc_syms. */
13840 return (symsec != &bfd_und_section
13841 && symsec != &bfd_abs_section
13842 && !bfd_is_com_section (symsec)
13843 && !s_is_linkonce (sym, segtype)
13845 /* A global or weak symbol is treated as external. */
13846 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13852 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13853 extended opcode. SEC is the section the frag is in. */
13856 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13859 const struct mips16_immed_operand *op;
13861 int mintiny, maxtiny;
13865 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13867 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13870 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13871 op = mips16_immed_operands;
13872 while (op->type != type)
13875 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13880 if (type == '<' || type == '>' || type == '[' || type == ']')
13883 maxtiny = 1 << op->nbits;
13888 maxtiny = (1 << op->nbits) - 1;
13893 mintiny = - (1 << (op->nbits - 1));
13894 maxtiny = (1 << (op->nbits - 1)) - 1;
13897 sym_frag = symbol_get_frag (fragp->fr_symbol);
13898 val = S_GET_VALUE (fragp->fr_symbol);
13899 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13905 /* We won't have the section when we are called from
13906 mips_relax_frag. However, we will always have been called
13907 from md_estimate_size_before_relax first. If this is a
13908 branch to a different section, we mark it as such. If SEC is
13909 NULL, and the frag is not marked, then it must be a branch to
13910 the same section. */
13913 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13918 /* Must have been called from md_estimate_size_before_relax. */
13921 fragp->fr_subtype =
13922 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13924 /* FIXME: We should support this, and let the linker
13925 catch branches and loads that are out of range. */
13926 as_bad_where (fragp->fr_file, fragp->fr_line,
13927 _("unsupported PC relative reference to different section"));
13931 if (fragp != sym_frag && sym_frag->fr_address == 0)
13932 /* Assume non-extended on the first relaxation pass.
13933 The address we have calculated will be bogus if this is
13934 a forward branch to another frag, as the forward frag
13935 will have fr_address == 0. */
13939 /* In this case, we know for sure that the symbol fragment is in
13940 the same section. If the relax_marker of the symbol fragment
13941 differs from the relax_marker of this fragment, we have not
13942 yet adjusted the symbol fragment fr_address. We want to add
13943 in STRETCH in order to get a better estimate of the address.
13944 This particularly matters because of the shift bits. */
13946 && sym_frag->relax_marker != fragp->relax_marker)
13950 /* Adjust stretch for any alignment frag. Note that if have
13951 been expanding the earlier code, the symbol may be
13952 defined in what appears to be an earlier frag. FIXME:
13953 This doesn't handle the fr_subtype field, which specifies
13954 a maximum number of bytes to skip when doing an
13956 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13958 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13961 stretch = - ((- stretch)
13962 & ~ ((1 << (int) f->fr_offset) - 1));
13964 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13973 addr = fragp->fr_address + fragp->fr_fix;
13975 /* The base address rules are complicated. The base address of
13976 a branch is the following instruction. The base address of a
13977 PC relative load or add is the instruction itself, but if it
13978 is in a delay slot (in which case it can not be extended) use
13979 the address of the instruction whose delay slot it is in. */
13980 if (type == 'p' || type == 'q')
13984 /* If we are currently assuming that this frag should be
13985 extended, then, the current address is two bytes
13987 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13990 /* Ignore the low bit in the target, since it will be set
13991 for a text label. */
13992 if ((val & 1) != 0)
13995 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13997 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14000 val -= addr & ~ ((1 << op->shift) - 1);
14002 /* Branch offsets have an implicit 0 in the lowest bit. */
14003 if (type == 'p' || type == 'q')
14006 /* If any of the shifted bits are set, we must use an extended
14007 opcode. If the address depends on the size of this
14008 instruction, this can lead to a loop, so we arrange to always
14009 use an extended opcode. We only check this when we are in
14010 the main relaxation loop, when SEC is NULL. */
14011 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14013 fragp->fr_subtype =
14014 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14018 /* If we are about to mark a frag as extended because the value
14019 is precisely maxtiny + 1, then there is a chance of an
14020 infinite loop as in the following code:
14025 In this case when the la is extended, foo is 0x3fc bytes
14026 away, so the la can be shrunk, but then foo is 0x400 away, so
14027 the la must be extended. To avoid this loop, we mark the
14028 frag as extended if it was small, and is about to become
14029 extended with a value of maxtiny + 1. */
14030 if (val == ((maxtiny + 1) << op->shift)
14031 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14034 fragp->fr_subtype =
14035 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14039 else if (symsec != absolute_section && sec != NULL)
14040 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14042 if ((val & ((1 << op->shift) - 1)) != 0
14043 || val < (mintiny << op->shift)
14044 || val > (maxtiny << op->shift))
14050 /* Compute the length of a branch sequence, and adjust the
14051 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14052 worst-case length is computed, with UPDATE being used to indicate
14053 whether an unconditional (-1), branch-likely (+1) or regular (0)
14054 branch is to be computed. */
14056 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14058 bfd_boolean toofar;
14062 && S_IS_DEFINED (fragp->fr_symbol)
14063 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14068 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14070 addr = fragp->fr_address + fragp->fr_fix + 4;
14074 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14077 /* If the symbol is not defined or it's in a different segment,
14078 assume the user knows what's going on and emit a short
14084 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14086 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14087 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14088 RELAX_BRANCH_LINK (fragp->fr_subtype),
14094 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14097 if (mips_pic != NO_PIC)
14099 /* Additional space for PIC loading of target address. */
14101 if (mips_opts.isa == ISA_MIPS1)
14102 /* Additional space for $at-stabilizing nop. */
14106 /* If branch is conditional. */
14107 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14114 /* Estimate the size of a frag before relaxing. Unless this is the
14115 mips16, we are not really relaxing here, and the final size is
14116 encoded in the subtype information. For the mips16, we have to
14117 decide whether we are using an extended opcode or not. */
14120 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14124 if (RELAX_BRANCH_P (fragp->fr_subtype))
14127 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14129 return fragp->fr_var;
14132 if (RELAX_MIPS16_P (fragp->fr_subtype))
14133 /* We don't want to modify the EXTENDED bit here; it might get us
14134 into infinite loops. We change it only in mips_relax_frag(). */
14135 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14137 if (mips_pic == NO_PIC)
14138 change = nopic_need_relax (fragp->fr_symbol, 0);
14139 else if (mips_pic == SVR4_PIC)
14140 change = pic_need_relax (fragp->fr_symbol, segtype);
14141 else if (mips_pic == VXWORKS_PIC)
14142 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14149 fragp->fr_subtype |= RELAX_USE_SECOND;
14150 return -RELAX_FIRST (fragp->fr_subtype);
14153 return -RELAX_SECOND (fragp->fr_subtype);
14156 /* This is called to see whether a reloc against a defined symbol
14157 should be converted into a reloc against a section. */
14160 mips_fix_adjustable (fixS *fixp)
14162 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14163 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14166 if (fixp->fx_addsy == NULL)
14169 /* If symbol SYM is in a mergeable section, relocations of the form
14170 SYM + 0 can usually be made section-relative. The mergeable data
14171 is then identified by the section offset rather than by the symbol.
14173 However, if we're generating REL LO16 relocations, the offset is split
14174 between the LO16 and parterning high part relocation. The linker will
14175 need to recalculate the complete offset in order to correctly identify
14178 The linker has traditionally not looked for the parterning high part
14179 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14180 placed anywhere. Rather than break backwards compatibility by changing
14181 this, it seems better not to force the issue, and instead keep the
14182 original symbol. This will work with either linker behavior. */
14183 if ((lo16_reloc_p (fixp->fx_r_type)
14184 || reloc_needs_lo_p (fixp->fx_r_type))
14185 && HAVE_IN_PLACE_ADDENDS
14186 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14189 /* There is no place to store an in-place offset for JALR relocations. */
14190 if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS)
14194 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14195 to a floating-point stub. The same is true for non-R_MIPS16_26
14196 relocations against MIPS16 functions; in this case, the stub becomes
14197 the function's canonical address.
14199 Floating-point stubs are stored in unique .mips16.call.* or
14200 .mips16.fn.* sections. If a stub T for function F is in section S,
14201 the first relocation in section S must be against F; this is how the
14202 linker determines the target function. All relocations that might
14203 resolve to T must also be against F. We therefore have the following
14204 restrictions, which are given in an intentionally-redundant way:
14206 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14209 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14210 if that stub might be used.
14212 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14215 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14216 that stub might be used.
14218 There is a further restriction:
14220 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14221 on targets with in-place addends; the relocation field cannot
14222 encode the low bit.
14224 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14225 against a MIPS16 symbol.
14227 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14228 relocation against some symbol R, no relocation against R may be
14229 reduced. (Note that this deals with (2) as well as (1) because
14230 relocations against global symbols will never be reduced on ELF
14231 targets.) This approach is a little simpler than trying to detect
14232 stub sections, and gives the "all or nothing" per-symbol consistency
14233 that we have for MIPS16 symbols. */
14235 && fixp->fx_subsy == NULL
14236 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14237 || *symbol_get_tc (fixp->fx_addsy)))
14244 /* Translate internal representation of relocation info to BFD target
14248 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14250 static arelent *retval[4];
14252 bfd_reloc_code_real_type code;
14254 memset (retval, 0, sizeof(retval));
14255 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14256 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14257 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14258 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14260 if (fixp->fx_pcrel)
14262 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14264 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14265 Relocations want only the symbol offset. */
14266 reloc->addend = fixp->fx_addnumber + reloc->address;
14269 /* A gruesome hack which is a result of the gruesome gas
14270 reloc handling. What's worse, for COFF (as opposed to
14271 ECOFF), we might need yet another copy of reloc->address.
14272 See bfd_install_relocation. */
14273 reloc->addend += reloc->address;
14277 reloc->addend = fixp->fx_addnumber;
14279 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14280 entry to be used in the relocation's section offset. */
14281 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14283 reloc->address = reloc->addend;
14287 code = fixp->fx_r_type;
14289 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14290 if (reloc->howto == NULL)
14292 as_bad_where (fixp->fx_file, fixp->fx_line,
14293 _("Can not represent %s relocation in this object file format"),
14294 bfd_get_reloc_code_name (code));
14301 /* Relax a machine dependent frag. This returns the amount by which
14302 the current size of the frag should change. */
14305 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14307 if (RELAX_BRANCH_P (fragp->fr_subtype))
14309 offsetT old_var = fragp->fr_var;
14311 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14313 return fragp->fr_var - old_var;
14316 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14319 if (mips16_extended_frag (fragp, NULL, stretch))
14321 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14323 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14328 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14330 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14337 /* Convert a machine dependent frag. */
14340 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14342 if (RELAX_BRANCH_P (fragp->fr_subtype))
14345 unsigned long insn;
14349 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14351 if (target_big_endian)
14352 insn = bfd_getb32 (buf);
14354 insn = bfd_getl32 (buf);
14356 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14358 /* We generate a fixup instead of applying it right now
14359 because, if there are linker relaxations, we're going to
14360 need the relocations. */
14361 exp.X_op = O_symbol;
14362 exp.X_add_symbol = fragp->fr_symbol;
14363 exp.X_add_number = fragp->fr_offset;
14365 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14366 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14367 fixp->fx_file = fragp->fr_file;
14368 fixp->fx_line = fragp->fr_line;
14370 md_number_to_chars ((char *) buf, insn, 4);
14377 as_warn_where (fragp->fr_file, fragp->fr_line,
14378 _("relaxed out-of-range branch into a jump"));
14380 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14383 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14385 /* Reverse the branch. */
14386 switch ((insn >> 28) & 0xf)
14389 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14390 have the condition reversed by tweaking a single
14391 bit, and their opcodes all have 0x4???????. */
14392 gas_assert ((insn & 0xf1000000) == 0x41000000);
14393 insn ^= 0x00010000;
14397 /* bltz 0x04000000 bgez 0x04010000
14398 bltzal 0x04100000 bgezal 0x04110000 */
14399 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14400 insn ^= 0x00010000;
14404 /* beq 0x10000000 bne 0x14000000
14405 blez 0x18000000 bgtz 0x1c000000 */
14406 insn ^= 0x04000000;
14414 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14416 /* Clear the and-link bit. */
14417 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14419 /* bltzal 0x04100000 bgezal 0x04110000
14420 bltzall 0x04120000 bgezall 0x04130000 */
14421 insn &= ~0x00100000;
14424 /* Branch over the branch (if the branch was likely) or the
14425 full jump (not likely case). Compute the offset from the
14426 current instruction to branch to. */
14427 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14431 /* How many bytes in instructions we've already emitted? */
14432 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14433 /* How many bytes in instructions from here to the end? */
14434 i = fragp->fr_var - i;
14436 /* Convert to instruction count. */
14438 /* Branch counts from the next instruction. */
14441 /* Branch over the jump. */
14442 md_number_to_chars ((char *) buf, insn, 4);
14446 md_number_to_chars ((char *) buf, 0, 4);
14449 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14451 /* beql $0, $0, 2f */
14453 /* Compute the PC offset from the current instruction to
14454 the end of the variable frag. */
14455 /* How many bytes in instructions we've already emitted? */
14456 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14457 /* How many bytes in instructions from here to the end? */
14458 i = fragp->fr_var - i;
14459 /* Convert to instruction count. */
14461 /* Don't decrement i, because we want to branch over the
14465 md_number_to_chars ((char *) buf, insn, 4);
14468 md_number_to_chars ((char *) buf, 0, 4);
14473 if (mips_pic == NO_PIC)
14476 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14477 ? 0x0c000000 : 0x08000000);
14478 exp.X_op = O_symbol;
14479 exp.X_add_symbol = fragp->fr_symbol;
14480 exp.X_add_number = fragp->fr_offset;
14482 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14483 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14484 fixp->fx_file = fragp->fr_file;
14485 fixp->fx_line = fragp->fr_line;
14487 md_number_to_chars ((char *) buf, insn, 4);
14492 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14493 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14494 exp.X_op = O_symbol;
14495 exp.X_add_symbol = fragp->fr_symbol;
14496 exp.X_add_number = fragp->fr_offset;
14498 if (fragp->fr_offset)
14500 exp.X_add_symbol = make_expr_symbol (&exp);
14501 exp.X_add_number = 0;
14504 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14505 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14506 fixp->fx_file = fragp->fr_file;
14507 fixp->fx_line = fragp->fr_line;
14509 md_number_to_chars ((char *) buf, insn, 4);
14512 if (mips_opts.isa == ISA_MIPS1)
14515 md_number_to_chars ((char *) buf, 0, 4);
14519 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14520 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14522 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14523 4, &exp, FALSE, BFD_RELOC_LO16);
14524 fixp->fx_file = fragp->fr_file;
14525 fixp->fx_line = fragp->fr_line;
14527 md_number_to_chars ((char *) buf, insn, 4);
14531 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14536 md_number_to_chars ((char *) buf, insn, 4);
14541 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14542 + fragp->fr_fix + fragp->fr_var);
14544 fragp->fr_fix += fragp->fr_var;
14549 if (RELAX_MIPS16_P (fragp->fr_subtype))
14552 const struct mips16_immed_operand *op;
14553 bfd_boolean small, ext;
14556 unsigned long insn;
14557 bfd_boolean use_extend;
14558 unsigned short extend;
14560 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14561 op = mips16_immed_operands;
14562 while (op->type != type)
14565 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14576 resolve_symbol_value (fragp->fr_symbol);
14577 val = S_GET_VALUE (fragp->fr_symbol);
14582 addr = fragp->fr_address + fragp->fr_fix;
14584 /* The rules for the base address of a PC relative reloc are
14585 complicated; see mips16_extended_frag. */
14586 if (type == 'p' || type == 'q')
14591 /* Ignore the low bit in the target, since it will be
14592 set for a text label. */
14593 if ((val & 1) != 0)
14596 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14598 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14601 addr &= ~ (addressT) ((1 << op->shift) - 1);
14604 /* Make sure the section winds up with the alignment we have
14607 record_alignment (asec, op->shift);
14611 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14612 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14613 as_warn_where (fragp->fr_file, fragp->fr_line,
14614 _("extended instruction in delay slot"));
14616 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14618 if (target_big_endian)
14619 insn = bfd_getb16 (buf);
14621 insn = bfd_getl16 (buf);
14623 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14624 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14625 small, ext, &insn, &use_extend, &extend);
14629 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14630 fragp->fr_fix += 2;
14634 md_number_to_chars ((char *) buf, insn, 2);
14635 fragp->fr_fix += 2;
14643 first = RELAX_FIRST (fragp->fr_subtype);
14644 second = RELAX_SECOND (fragp->fr_subtype);
14645 fixp = (fixS *) fragp->fr_opcode;
14647 /* Possibly emit a warning if we've chosen the longer option. */
14648 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14649 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14651 const char *msg = macro_warning (fragp->fr_subtype);
14653 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14656 /* Go through all the fixups for the first sequence. Disable them
14657 (by marking them as done) if we're going to use the second
14658 sequence instead. */
14660 && fixp->fx_frag == fragp
14661 && fixp->fx_where < fragp->fr_fix - second)
14663 if (fragp->fr_subtype & RELAX_USE_SECOND)
14665 fixp = fixp->fx_next;
14668 /* Go through the fixups for the second sequence. Disable them if
14669 we're going to use the first sequence, otherwise adjust their
14670 addresses to account for the relaxation. */
14671 while (fixp && fixp->fx_frag == fragp)
14673 if (fragp->fr_subtype & RELAX_USE_SECOND)
14674 fixp->fx_where -= first;
14677 fixp = fixp->fx_next;
14680 /* Now modify the frag contents. */
14681 if (fragp->fr_subtype & RELAX_USE_SECOND)
14685 start = fragp->fr_literal + fragp->fr_fix - first - second;
14686 memmove (start, start + first, second);
14687 fragp->fr_fix -= first;
14690 fragp->fr_fix -= second;
14696 /* This function is called after the relocs have been generated.
14697 We've been storing mips16 text labels as odd. Here we convert them
14698 back to even for the convenience of the debugger. */
14701 mips_frob_file_after_relocs (void)
14704 unsigned int count, i;
14709 syms = bfd_get_outsymbols (stdoutput);
14710 count = bfd_get_symcount (stdoutput);
14711 for (i = 0; i < count; i++, syms++)
14713 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14714 && ((*syms)->value & 1) != 0)
14716 (*syms)->value &= ~1;
14717 /* If the symbol has an odd size, it was probably computed
14718 incorrectly, so adjust that as well. */
14719 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14720 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14727 /* This function is called whenever a label is defined. It is used
14728 when handling branch delays; if a branch has a label, we assume we
14729 can not move it. */
14732 mips_define_label (symbolS *sym)
14734 segment_info_type *si = seg_info (now_seg);
14735 struct insn_label_list *l;
14737 if (free_insn_labels == NULL)
14738 l = (struct insn_label_list *) xmalloc (sizeof *l);
14741 l = free_insn_labels;
14742 free_insn_labels = l->next;
14746 l->next = si->label_list;
14747 si->label_list = l;
14750 dwarf2_emit_label (sym);
14754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14756 /* Some special processing for a MIPS ELF file. */
14759 mips_elf_final_processing (void)
14761 /* Write out the register information. */
14762 if (mips_abi != N64_ABI)
14766 s.ri_gprmask = mips_gprmask;
14767 s.ri_cprmask[0] = mips_cprmask[0];
14768 s.ri_cprmask[1] = mips_cprmask[1];
14769 s.ri_cprmask[2] = mips_cprmask[2];
14770 s.ri_cprmask[3] = mips_cprmask[3];
14771 /* The gp_value field is set by the MIPS ELF backend. */
14773 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14774 ((Elf32_External_RegInfo *)
14775 mips_regmask_frag));
14779 Elf64_Internal_RegInfo s;
14781 s.ri_gprmask = mips_gprmask;
14783 s.ri_cprmask[0] = mips_cprmask[0];
14784 s.ri_cprmask[1] = mips_cprmask[1];
14785 s.ri_cprmask[2] = mips_cprmask[2];
14786 s.ri_cprmask[3] = mips_cprmask[3];
14787 /* The gp_value field is set by the MIPS ELF backend. */
14789 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14790 ((Elf64_External_RegInfo *)
14791 mips_regmask_frag));
14794 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14795 sort of BFD interface for this. */
14796 if (mips_any_noreorder)
14797 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14798 if (mips_pic != NO_PIC)
14800 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14804 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14806 /* Set MIPS ELF flags for ASEs. */
14807 /* We may need to define a new flag for DSP ASE, and set this flag when
14808 file_ase_dsp is true. */
14809 /* Same for DSP R2. */
14810 /* We may need to define a new flag for MT ASE, and set this flag when
14811 file_ase_mt is true. */
14812 if (file_ase_mips16)
14813 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14814 #if 0 /* XXX FIXME */
14815 if (file_ase_mips3d)
14816 elf_elfheader (stdoutput)->e_flags |= ???;
14819 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14821 /* Set the MIPS ELF ABI flags. */
14822 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14823 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14824 else if (mips_abi == O64_ABI)
14825 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14826 else if (mips_abi == EABI_ABI)
14828 if (!file_mips_gp32)
14829 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14831 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14833 else if (mips_abi == N32_ABI)
14834 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14836 /* Nothing to do for N64_ABI. */
14838 if (mips_32bitmode)
14839 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14841 #if 0 /* XXX FIXME */
14842 /* 32 bit code with 64 bit FP registers. */
14843 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14844 elf_elfheader (stdoutput)->e_flags |= ???;
14848 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14850 typedef struct proc {
14852 symbolS *func_end_sym;
14853 unsigned long reg_mask;
14854 unsigned long reg_offset;
14855 unsigned long fpreg_mask;
14856 unsigned long fpreg_offset;
14857 unsigned long frame_offset;
14858 unsigned long frame_reg;
14859 unsigned long pc_reg;
14862 static procS cur_proc;
14863 static procS *cur_proc_ptr;
14864 static int numprocs;
14866 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14870 mips_nop_opcode (void)
14872 return seg_info (now_seg)->tc_segment_info_data.mips16;
14875 /* Fill in an rs_align_code fragment. This only needs to do something
14876 for MIPS16 code, where 0 is not a nop. */
14879 mips_handle_align (fragS *fragp)
14882 int bytes, size, excess;
14885 if (fragp->fr_type != rs_align_code)
14888 p = fragp->fr_literal + fragp->fr_fix;
14891 opcode = mips16_nop_insn.insn_opcode;
14896 opcode = nop_insn.insn_opcode;
14900 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14901 excess = bytes % size;
14904 /* If we're not inserting a whole number of instructions,
14905 pad the end of the fixed part of the frag with zeros. */
14906 memset (p, 0, excess);
14908 fragp->fr_fix += excess;
14911 md_number_to_chars (p, opcode, size);
14912 fragp->fr_var = size;
14916 md_obj_begin (void)
14923 /* Check for premature end, nesting errors, etc. */
14925 as_warn (_("missing .end at end of assembly"));
14934 if (*input_line_pointer == '-')
14936 ++input_line_pointer;
14939 if (!ISDIGIT (*input_line_pointer))
14940 as_bad (_("expected simple number"));
14941 if (input_line_pointer[0] == '0')
14943 if (input_line_pointer[1] == 'x')
14945 input_line_pointer += 2;
14946 while (ISXDIGIT (*input_line_pointer))
14949 val |= hex_value (*input_line_pointer++);
14951 return negative ? -val : val;
14955 ++input_line_pointer;
14956 while (ISDIGIT (*input_line_pointer))
14959 val |= *input_line_pointer++ - '0';
14961 return negative ? -val : val;
14964 if (!ISDIGIT (*input_line_pointer))
14966 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14967 *input_line_pointer, *input_line_pointer);
14968 as_warn (_("invalid number"));
14971 while (ISDIGIT (*input_line_pointer))
14974 val += *input_line_pointer++ - '0';
14976 return negative ? -val : val;
14979 /* The .file directive; just like the usual .file directive, but there
14980 is an initial number which is the ECOFF file index. In the non-ECOFF
14981 case .file implies DWARF-2. */
14984 s_mips_file (int x ATTRIBUTE_UNUSED)
14986 static int first_file_directive = 0;
14988 if (ECOFF_DEBUGGING)
14997 filename = dwarf2_directive_file (0);
14999 /* Versions of GCC up to 3.1 start files with a ".file"
15000 directive even for stabs output. Make sure that this
15001 ".file" is handled. Note that you need a version of GCC
15002 after 3.1 in order to support DWARF-2 on MIPS. */
15003 if (filename != NULL && ! first_file_directive)
15005 (void) new_logical_line (filename, -1);
15006 s_app_file_string (filename, 0);
15008 first_file_directive = 1;
15012 /* The .loc directive, implying DWARF-2. */
15015 s_mips_loc (int x ATTRIBUTE_UNUSED)
15017 if (!ECOFF_DEBUGGING)
15018 dwarf2_directive_loc (0);
15021 /* The .end directive. */
15024 s_mips_end (int x ATTRIBUTE_UNUSED)
15028 /* Following functions need their own .frame and .cprestore directives. */
15029 mips_frame_reg_valid = 0;
15030 mips_cprestore_valid = 0;
15032 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15035 demand_empty_rest_of_line ();
15040 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15041 as_warn (_(".end not in text section"));
15045 as_warn (_(".end directive without a preceding .ent directive."));
15046 demand_empty_rest_of_line ();
15052 gas_assert (S_GET_NAME (p));
15053 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15054 as_warn (_(".end symbol does not match .ent symbol."));
15056 if (debug_type == DEBUG_STABS)
15057 stabs_generate_asm_endfunc (S_GET_NAME (p),
15061 as_warn (_(".end directive missing or unknown symbol"));
15064 /* Create an expression to calculate the size of the function. */
15065 if (p && cur_proc_ptr)
15067 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15068 expressionS *exp = xmalloc (sizeof (expressionS));
15071 exp->X_op = O_subtract;
15072 exp->X_add_symbol = symbol_temp_new_now ();
15073 exp->X_op_symbol = p;
15074 exp->X_add_number = 0;
15076 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15079 /* Generate a .pdr section. */
15080 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15082 segT saved_seg = now_seg;
15083 subsegT saved_subseg = now_subseg;
15087 #ifdef md_flush_pending_output
15088 md_flush_pending_output ();
15091 gas_assert (pdr_seg);
15092 subseg_set (pdr_seg, 0);
15094 /* Write the symbol. */
15095 exp.X_op = O_symbol;
15096 exp.X_add_symbol = p;
15097 exp.X_add_number = 0;
15098 emit_expr (&exp, 4);
15100 fragp = frag_more (7 * 4);
15102 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15103 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15104 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15105 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15106 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15107 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15108 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15110 subseg_set (saved_seg, saved_subseg);
15112 #endif /* OBJ_ELF */
15114 cur_proc_ptr = NULL;
15117 /* The .aent and .ent directives. */
15120 s_mips_ent (int aent)
15124 symbolP = get_symbol ();
15125 if (*input_line_pointer == ',')
15126 ++input_line_pointer;
15127 SKIP_WHITESPACE ();
15128 if (ISDIGIT (*input_line_pointer)
15129 || *input_line_pointer == '-')
15132 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15133 as_warn (_(".ent or .aent not in text section."));
15135 if (!aent && cur_proc_ptr)
15136 as_warn (_("missing .end"));
15140 /* This function needs its own .frame and .cprestore directives. */
15141 mips_frame_reg_valid = 0;
15142 mips_cprestore_valid = 0;
15144 cur_proc_ptr = &cur_proc;
15145 memset (cur_proc_ptr, '\0', sizeof (procS));
15147 cur_proc_ptr->func_sym = symbolP;
15151 if (debug_type == DEBUG_STABS)
15152 stabs_generate_asm_func (S_GET_NAME (symbolP),
15153 S_GET_NAME (symbolP));
15156 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15158 demand_empty_rest_of_line ();
15161 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15162 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15163 s_mips_frame is used so that we can set the PDR information correctly.
15164 We can't use the ecoff routines because they make reference to the ecoff
15165 symbol table (in the mdebug section). */
15168 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15171 if (IS_ELF && !ECOFF_DEBUGGING)
15175 if (cur_proc_ptr == (procS *) NULL)
15177 as_warn (_(".frame outside of .ent"));
15178 demand_empty_rest_of_line ();
15182 cur_proc_ptr->frame_reg = tc_get_register (1);
15184 SKIP_WHITESPACE ();
15185 if (*input_line_pointer++ != ','
15186 || get_absolute_expression_and_terminator (&val) != ',')
15188 as_warn (_("Bad .frame directive"));
15189 --input_line_pointer;
15190 demand_empty_rest_of_line ();
15194 cur_proc_ptr->frame_offset = val;
15195 cur_proc_ptr->pc_reg = tc_get_register (0);
15197 demand_empty_rest_of_line ();
15200 #endif /* OBJ_ELF */
15204 /* The .fmask and .mask directives. If the mdebug section is present
15205 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15206 embedded targets, s_mips_mask is used so that we can set the PDR
15207 information correctly. We can't use the ecoff routines because they
15208 make reference to the ecoff symbol table (in the mdebug section). */
15211 s_mips_mask (int reg_type)
15214 if (IS_ELF && !ECOFF_DEBUGGING)
15218 if (cur_proc_ptr == (procS *) NULL)
15220 as_warn (_(".mask/.fmask outside of .ent"));
15221 demand_empty_rest_of_line ();
15225 if (get_absolute_expression_and_terminator (&mask) != ',')
15227 as_warn (_("Bad .mask/.fmask directive"));
15228 --input_line_pointer;
15229 demand_empty_rest_of_line ();
15233 off = get_absolute_expression ();
15235 if (reg_type == 'F')
15237 cur_proc_ptr->fpreg_mask = mask;
15238 cur_proc_ptr->fpreg_offset = off;
15242 cur_proc_ptr->reg_mask = mask;
15243 cur_proc_ptr->reg_offset = off;
15246 demand_empty_rest_of_line ();
15249 #endif /* OBJ_ELF */
15250 s_ignore (reg_type);
15253 /* A table describing all the processors gas knows about. Names are
15254 matched in the order listed.
15256 To ease comparison, please keep this table in the same order as
15257 gcc's mips_cpu_info_table[]. */
15258 static const struct mips_cpu_info mips_cpu_info_table[] =
15260 /* Entries for generic ISAs */
15261 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15262 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15263 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15264 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15265 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15266 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15267 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15268 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15269 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15272 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15273 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15274 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15277 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15280 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15281 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15282 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15283 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15284 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15285 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15286 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15287 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15288 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15289 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15290 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15291 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15292 /* ST Microelectronics Loongson 2E and 2F cores */
15293 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15294 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15297 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15298 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15299 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15300 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15301 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15302 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15303 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15304 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15305 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15306 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15307 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15308 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15309 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15310 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15311 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15314 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15315 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15316 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15317 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15319 /* MIPS 32 Release 2 */
15320 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15321 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15322 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15323 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15324 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15325 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15326 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15327 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15328 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15329 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15330 /* Deprecated forms of the above. */
15331 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15332 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15333 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15334 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15335 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15336 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15337 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15338 /* Deprecated forms of the above. */
15339 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15340 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15341 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15342 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15343 ISA_MIPS32R2, CPU_MIPS32R2 },
15344 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15345 ISA_MIPS32R2, CPU_MIPS32R2 },
15346 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15347 ISA_MIPS32R2, CPU_MIPS32R2 },
15348 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15349 ISA_MIPS32R2, CPU_MIPS32R2 },
15350 /* Deprecated forms of the above. */
15351 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15352 ISA_MIPS32R2, CPU_MIPS32R2 },
15353 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15354 ISA_MIPS32R2, CPU_MIPS32R2 },
15355 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15356 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15357 ISA_MIPS32R2, CPU_MIPS32R2 },
15358 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15359 ISA_MIPS32R2, CPU_MIPS32R2 },
15360 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15361 ISA_MIPS32R2, CPU_MIPS32R2 },
15362 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15363 ISA_MIPS32R2, CPU_MIPS32R2 },
15364 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15365 ISA_MIPS32R2, CPU_MIPS32R2 },
15366 /* Deprecated forms of the above. */
15367 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15368 ISA_MIPS32R2, CPU_MIPS32R2 },
15369 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15370 ISA_MIPS32R2, CPU_MIPS32R2 },
15371 /* 1004K cores are multiprocessor versions of the 34K. */
15372 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15373 ISA_MIPS32R2, CPU_MIPS32R2 },
15374 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15375 ISA_MIPS32R2, CPU_MIPS32R2 },
15376 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15377 ISA_MIPS32R2, CPU_MIPS32R2 },
15378 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15379 ISA_MIPS32R2, CPU_MIPS32R2 },
15382 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15383 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15384 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15385 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15387 /* Broadcom SB-1 CPU core */
15388 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15389 ISA_MIPS64, CPU_SB1 },
15390 /* Broadcom SB-1A CPU core */
15391 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15392 ISA_MIPS64, CPU_SB1 },
15394 /* MIPS 64 Release 2 */
15396 /* Cavium Networks Octeon CPU core */
15397 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15400 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15407 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15408 with a final "000" replaced by "k". Ignore case.
15410 Note: this function is shared between GCC and GAS. */
15413 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15415 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15416 given++, canonical++;
15418 return ((*given == 0 && *canonical == 0)
15419 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15423 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15424 CPU name. We've traditionally allowed a lot of variation here.
15426 Note: this function is shared between GCC and GAS. */
15429 mips_matching_cpu_name_p (const char *canonical, const char *given)
15431 /* First see if the name matches exactly, or with a final "000"
15432 turned into "k". */
15433 if (mips_strict_matching_cpu_name_p (canonical, given))
15436 /* If not, try comparing based on numerical designation alone.
15437 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15438 if (TOLOWER (*given) == 'r')
15440 if (!ISDIGIT (*given))
15443 /* Skip over some well-known prefixes in the canonical name,
15444 hoping to find a number there too. */
15445 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15447 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15449 else if (TOLOWER (canonical[0]) == 'r')
15452 return mips_strict_matching_cpu_name_p (canonical, given);
15456 /* Parse an option that takes the name of a processor as its argument.
15457 OPTION is the name of the option and CPU_STRING is the argument.
15458 Return the corresponding processor enumeration if the CPU_STRING is
15459 recognized, otherwise report an error and return null.
15461 A similar function exists in GCC. */
15463 static const struct mips_cpu_info *
15464 mips_parse_cpu (const char *option, const char *cpu_string)
15466 const struct mips_cpu_info *p;
15468 /* 'from-abi' selects the most compatible architecture for the given
15469 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15470 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15471 version. Look first at the -mgp options, if given, otherwise base
15472 the choice on MIPS_DEFAULT_64BIT.
15474 Treat NO_ABI like the EABIs. One reason to do this is that the
15475 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15476 architecture. This code picks MIPS I for 'mips' and MIPS III for
15477 'mips64', just as we did in the days before 'from-abi'. */
15478 if (strcasecmp (cpu_string, "from-abi") == 0)
15480 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15481 return mips_cpu_info_from_isa (ISA_MIPS1);
15483 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15484 return mips_cpu_info_from_isa (ISA_MIPS3);
15486 if (file_mips_gp32 >= 0)
15487 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15489 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15494 /* 'default' has traditionally been a no-op. Probably not very useful. */
15495 if (strcasecmp (cpu_string, "default") == 0)
15498 for (p = mips_cpu_info_table; p->name != 0; p++)
15499 if (mips_matching_cpu_name_p (p->name, cpu_string))
15502 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15506 /* Return the canonical processor information for ISA (a member of the
15507 ISA_MIPS* enumeration). */
15509 static const struct mips_cpu_info *
15510 mips_cpu_info_from_isa (int isa)
15514 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15515 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15516 && isa == mips_cpu_info_table[i].isa)
15517 return (&mips_cpu_info_table[i]);
15522 static const struct mips_cpu_info *
15523 mips_cpu_info_from_arch (int arch)
15527 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15528 if (arch == mips_cpu_info_table[i].cpu)
15529 return (&mips_cpu_info_table[i]);
15535 show (FILE *stream, const char *string, int *col_p, int *first_p)
15539 fprintf (stream, "%24s", "");
15544 fprintf (stream, ", ");
15548 if (*col_p + strlen (string) > 72)
15550 fprintf (stream, "\n%24s", "");
15554 fprintf (stream, "%s", string);
15555 *col_p += strlen (string);
15561 md_show_usage (FILE *stream)
15566 fprintf (stream, _("\
15568 -EB generate big endian output\n\
15569 -EL generate little endian output\n\
15570 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15571 -G NUM allow referencing objects up to NUM bytes\n\
15572 implicitly with the gp register [default 8]\n"));
15573 fprintf (stream, _("\
15574 -mips1 generate MIPS ISA I instructions\n\
15575 -mips2 generate MIPS ISA II instructions\n\
15576 -mips3 generate MIPS ISA III instructions\n\
15577 -mips4 generate MIPS ISA IV instructions\n\
15578 -mips5 generate MIPS ISA V instructions\n\
15579 -mips32 generate MIPS32 ISA instructions\n\
15580 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15581 -mips64 generate MIPS64 ISA instructions\n\
15582 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15583 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15587 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15588 show (stream, mips_cpu_info_table[i].name, &column, &first);
15589 show (stream, "from-abi", &column, &first);
15590 fputc ('\n', stream);
15592 fprintf (stream, _("\
15593 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15594 -no-mCPU don't generate code specific to CPU.\n\
15595 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15599 show (stream, "3900", &column, &first);
15600 show (stream, "4010", &column, &first);
15601 show (stream, "4100", &column, &first);
15602 show (stream, "4650", &column, &first);
15603 fputc ('\n', stream);
15605 fprintf (stream, _("\
15606 -mips16 generate mips16 instructions\n\
15607 -no-mips16 do not generate mips16 instructions\n"));
15608 fprintf (stream, _("\
15609 -msmartmips generate smartmips instructions\n\
15610 -mno-smartmips do not generate smartmips instructions\n"));
15611 fprintf (stream, _("\
15612 -mdsp generate DSP instructions\n\
15613 -mno-dsp do not generate DSP instructions\n"));
15614 fprintf (stream, _("\
15615 -mdspr2 generate DSP R2 instructions\n\
15616 -mno-dspr2 do not generate DSP R2 instructions\n"));
15617 fprintf (stream, _("\
15618 -mmt generate MT instructions\n\
15619 -mno-mt do not generate MT instructions\n"));
15620 fprintf (stream, _("\
15621 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15622 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15623 -mfix-vr4120 work around certain VR4120 errata\n\
15624 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15625 -mfix-24k insert a nop after ERET and DERET instructions\n\
15626 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15627 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15628 -msym32 assume all symbols have 32-bit values\n\
15629 -O0 remove unneeded NOPs, do not swap branches\n\
15630 -O remove unneeded NOPs and swap branches\n\
15631 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15632 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15633 fprintf (stream, _("\
15634 -mhard-float allow floating-point instructions\n\
15635 -msoft-float do not allow floating-point instructions\n\
15636 -msingle-float only allow 32-bit floating-point operations\n\
15637 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15638 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15641 fprintf (stream, _("\
15642 -KPIC, -call_shared generate SVR4 position independent code\n\
15643 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15644 -mvxworks-pic generate VxWorks position independent code\n\
15645 -non_shared do not generate code that can operate with DSOs\n\
15646 -xgot assume a 32 bit GOT\n\
15647 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15648 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15649 position dependent (non shared) code\n\
15650 -mabi=ABI create ABI conformant object file for:\n"));
15654 show (stream, "32", &column, &first);
15655 show (stream, "o64", &column, &first);
15656 show (stream, "n32", &column, &first);
15657 show (stream, "64", &column, &first);
15658 show (stream, "eabi", &column, &first);
15660 fputc ('\n', stream);
15662 fprintf (stream, _("\
15663 -32 create o32 ABI object file (default)\n\
15664 -n32 create n32 ABI object file\n\
15665 -64 create 64 ABI object file\n"));
15671 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15673 if (HAVE_64BIT_SYMBOLS)
15674 return dwarf2_format_64bit_irix;
15676 return dwarf2_format_32bit;
15681 mips_dwarf2_addr_size (void)
15683 if (HAVE_64BIT_OBJECTS)
15689 /* Standard calling conventions leave the CFA at SP on entry. */
15691 mips_cfi_frame_initial_instructions (void)
15693 cfi_add_CFA_def_cfa_register (SP);
15697 tc_mips_regname_to_dw2regnum (char *regname)
15699 unsigned int regnum = -1;
15702 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))