1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi = NO_ABI;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls = FALSE;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32 = -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32 = -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts =
202 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask;
209 unsigned long mips_cprmask[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa = ISA_UNKNOWN;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch = CPU_UNKNOWN;
228 static const char *mips_arch_string;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune = CPU_UNKNOWN;
233 static const char *mips_tune_string;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode = 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* True if relocations are stored in-place. */
283 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
285 /* We can only have 64bit addresses if the object file format supports it. */
286 #define HAVE_32BIT_ADDRESSES \
288 || (bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS)) \
291 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
293 /* Addresses are loaded in different ways, depending on the address size
294 in use. The n32 ABI Documentation also mandates the use of additions
295 with overflow checking, but existing implementations don't follow it. */
296 #define ADDRESS_ADD_INSN \
297 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
299 #define ADDRESS_ADDI_INSN \
300 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
302 #define ADDRESS_LOAD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
305 #define ADDRESS_STORE_INSN \
306 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
308 /* Return true if the given CPU supports the MIPS16 ASE. */
309 #define CPU_HAS_MIPS16(cpu) \
310 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
311 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
313 /* Return true if the given CPU supports the MIPS3D ASE. */
314 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
317 /* Return true if the given CPU supports the MDMX ASE. */
318 #define CPU_HAS_MDMX(cpu) (FALSE \
321 /* True if CPU has a dror instruction. */
322 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
324 /* True if CPU has a ror instruction. */
325 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
327 /* True if mflo and mfhi can be immediately followed by instructions
328 which write to the HI and LO registers.
330 According to MIPS specifications, MIPS ISAs I, II, and III need
331 (at least) two instructions between the reads of HI/LO and
332 instructions which write them, and later ISAs do not. Contradicting
333 the MIPS specifications, some MIPS IV processor user manuals (e.g.
334 the UM for the NEC Vr5000) document needing the instructions between
335 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
336 MIPS64 and later ISAs to have the interlocks, plus any specific
337 earlier-ISA CPUs for which CPU documentation declares that the
338 instructions are really interlocked. */
339 #define hilo_interlocks \
340 (mips_opts.isa == ISA_MIPS32 \
341 || mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64 \
343 || mips_opts.isa == ISA_MIPS64R2 \
344 || mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_R10000 \
346 || mips_opts.arch == CPU_R12000 \
347 || mips_opts.arch == CPU_RM7000 \
348 || mips_opts.arch == CPU_VR5500 \
351 /* Whether the processor uses hardware interlocks to protect reads
352 from the GPRs after they are loaded from memory, and thus does not
353 require nops to be inserted. This applies to instructions marked
354 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
356 #define gpr_interlocks \
357 (mips_opts.isa != ISA_MIPS1 \
358 || mips_opts.arch == CPU_R3900)
360 /* Whether the processor uses hardware interlocks to avoid delays
361 required by coprocessor instructions, and thus does not require
362 nops to be inserted. This applies to instructions marked
363 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
364 between instructions marked INSN_WRITE_COND_CODE and ones marked
365 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
366 levels I, II, and III. */
367 /* Itbl support may require additional care here. */
368 #define cop_interlocks \
369 ((mips_opts.isa != ISA_MIPS1 \
370 && mips_opts.isa != ISA_MIPS2 \
371 && mips_opts.isa != ISA_MIPS3) \
372 || mips_opts.arch == CPU_R4300 \
375 /* Whether the processor uses hardware interlocks to protect reads
376 from coprocessor registers after they are loaded from memory, and
377 thus does not require nops to be inserted. This applies to
378 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
379 requires at MIPS ISA level I. */
380 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
382 /* Is this a mfhi or mflo instruction? */
383 #define MF_HILO_INSN(PINFO) \
384 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
386 /* MIPS PIC level. */
388 enum mips_pic_level mips_pic;
390 /* 1 if we should generate 32 bit offsets from the $gp register in
391 SVR4_PIC mode. Currently has no meaning in other modes. */
392 static int mips_big_got = 0;
394 /* 1 if trap instructions should used for overflow rather than break
396 static int mips_trap = 0;
398 /* 1 if double width floating point constants should not be constructed
399 by assembling two single width halves into two single width floating
400 point registers which just happen to alias the double width destination
401 register. On some architectures this aliasing can be disabled by a bit
402 in the status register, and the setting of this bit cannot be determined
403 automatically at assemble time. */
404 static int mips_disable_float_construction;
406 /* Non-zero if any .set noreorder directives were used. */
408 static int mips_any_noreorder;
410 /* Non-zero if nops should be inserted when the register referenced in
411 an mfhi/mflo instruction is read in the next two instructions. */
412 static int mips_7000_hilo_fix;
414 /* The size of the small data section. */
415 static unsigned int g_switch_value = 8;
416 /* Whether the -G option was used. */
417 static int g_switch_seen = 0;
422 /* If we can determine in advance that GP optimization won't be
423 possible, we can skip the relaxation stuff that tries to produce
424 GP-relative references. This makes delay slot optimization work
427 This function can only provide a guess, but it seems to work for
428 gcc output. It needs to guess right for gcc, otherwise gcc
429 will put what it thinks is a GP-relative instruction in a branch
432 I don't know if a fix is needed for the SVR4_PIC mode. I've only
433 fixed it for the non-PIC mode. KR 95/04/07 */
434 static int nopic_need_relax (symbolS *, int);
436 /* handle of the OPCODE hash table */
437 static struct hash_control *op_hash = NULL;
439 /* The opcode hash table we use for the mips16. */
440 static struct hash_control *mips16_op_hash = NULL;
442 /* This array holds the chars that always start a comment. If the
443 pre-processor is disabled, these aren't very useful */
444 const char comment_chars[] = "#";
446 /* This array holds the chars that only start a comment at the beginning of
447 a line. If the line seems to have the form '# 123 filename'
448 .line and .file directives will appear in the pre-processed output */
449 /* Note that input_file.c hand checks for '#' at the beginning of the
450 first line of the input file. This is because the compiler outputs
451 #NO_APP at the beginning of its output. */
452 /* Also note that C style comments are always supported. */
453 const char line_comment_chars[] = "#";
455 /* This array holds machine specific line separator characters. */
456 const char line_separator_chars[] = ";";
458 /* Chars that can be used to separate mant from exp in floating point nums */
459 const char EXP_CHARS[] = "eE";
461 /* Chars that mean this number is a floating point constant */
464 const char FLT_CHARS[] = "rRsSfFdDxXpP";
466 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
467 changed in read.c . Ideally it shouldn't have to know about it at all,
468 but nothing is ideal around here.
471 static char *insn_error;
473 static int auto_align = 1;
475 /* When outputting SVR4 PIC code, the assembler needs to know the
476 offset in the stack frame from which to restore the $gp register.
477 This is set by the .cprestore pseudo-op, and saved in this
479 static offsetT mips_cprestore_offset = -1;
481 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
482 more optimizations, it can use a register value instead of a memory-saved
483 offset and even an other register than $gp as global pointer. */
484 static offsetT mips_cpreturn_offset = -1;
485 static int mips_cpreturn_register = -1;
486 static int mips_gp_register = GP;
487 static int mips_gprel_offset = 0;
489 /* Whether mips_cprestore_offset has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_cprestore_valid = 0;
493 /* This is the register which holds the stack frame, as set by the
494 .frame pseudo-op. This is needed to implement .cprestore. */
495 static int mips_frame_reg = SP;
497 /* Whether mips_frame_reg has been set in the current function
498 (or whether it has already been warned about, if not). */
499 static int mips_frame_reg_valid = 0;
501 /* To output NOP instructions correctly, we need to keep information
502 about the previous two instructions. */
504 /* Whether we are optimizing. The default value of 2 means to remove
505 unneeded NOPs and swap branch instructions when possible. A value
506 of 1 means to not swap branches. A value of 0 means to always
508 static int mips_optimize = 2;
510 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
511 equivalent to seeing no -g option at all. */
512 static int mips_debug = 0;
514 /* The previous instruction. */
515 static struct mips_cl_insn prev_insn;
517 /* The instruction before prev_insn. */
518 static struct mips_cl_insn prev_prev_insn;
520 /* If we don't want information for prev_insn or prev_prev_insn, we
521 point the insn_mo field at this dummy integer. */
522 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
524 /* Non-zero if prev_insn is valid. */
525 static int prev_insn_valid;
527 /* The frag for the previous instruction. */
528 static struct frag *prev_insn_frag;
530 /* The offset into prev_insn_frag for the previous instruction. */
531 static long prev_insn_where;
533 /* The reloc type for the previous instruction, if any. */
534 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
536 /* The reloc for the previous instruction, if any. */
537 static fixS *prev_insn_fixp[3];
539 /* Non-zero if the previous instruction was in a delay slot. */
540 static int prev_insn_is_delay_slot;
542 /* Non-zero if the previous instruction was in a .set noreorder. */
543 static int prev_insn_unreordered;
545 /* Non-zero if the previous instruction uses an extend opcode (if
547 static int prev_insn_extended;
549 /* Non-zero if the previous previous instruction was in a .set
551 static int prev_prev_insn_unreordered;
553 /* If this is set, it points to a frag holding nop instructions which
554 were inserted before the start of a noreorder section. If those
555 nops turn out to be unnecessary, the size of the frag can be
557 static fragS *prev_nop_frag;
559 /* The number of nop instructions we created in prev_nop_frag. */
560 static int prev_nop_frag_holds;
562 /* The number of nop instructions that we know we need in
564 static int prev_nop_frag_required;
566 /* The number of instructions we've seen since prev_nop_frag. */
567 static int prev_nop_frag_since;
569 /* For ECOFF and ELF, relocations against symbols are done in two
570 parts, with a HI relocation and a LO relocation. Each relocation
571 has only 16 bits of space to store an addend. This means that in
572 order for the linker to handle carries correctly, it must be able
573 to locate both the HI and the LO relocation. This means that the
574 relocations must appear in order in the relocation table.
576 In order to implement this, we keep track of each unmatched HI
577 relocation. We then sort them so that they immediately precede the
578 corresponding LO relocation. */
583 struct mips_hi_fixup *next;
586 /* The section this fixup is in. */
590 /* The list of unmatched HI relocs. */
592 static struct mips_hi_fixup *mips_hi_fixup_list;
594 /* The frag containing the last explicit relocation operator.
595 Null if explicit relocations have not been used. */
597 static fragS *prev_reloc_op_frag;
599 /* Map normal MIPS register numbers to mips16 register numbers. */
601 #define X ILLEGAL_REG
602 static const int mips32_to_16_reg_map[] =
604 X, X, 2, 3, 4, 5, 6, 7,
605 X, X, X, X, X, X, X, X,
606 0, 1, X, X, X, X, X, X,
607 X, X, X, X, X, X, X, X
611 /* Map mips16 register numbers to normal MIPS register numbers. */
613 static const unsigned int mips16_to_32_reg_map[] =
615 16, 17, 2, 3, 4, 5, 6, 7
618 static int mips_fix_vr4120;
620 /* We don't relax branches by default, since this causes us to expand
621 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
622 fail to compute the offset before expanding the macro to the most
623 efficient expansion. */
625 static int mips_relax_branch;
627 /* The expansion of many macros depends on the type of symbol that
628 they refer to. For example, when generating position-dependent code,
629 a macro that refers to a symbol may have two different expansions,
630 one which uses GP-relative addresses and one which uses absolute
631 addresses. When generating SVR4-style PIC, a macro may have
632 different expansions for local and global symbols.
634 We handle these situations by generating both sequences and putting
635 them in variant frags. In position-dependent code, the first sequence
636 will be the GP-relative one and the second sequence will be the
637 absolute one. In SVR4 PIC, the first sequence will be for global
638 symbols and the second will be for local symbols.
640 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
641 SECOND are the lengths of the two sequences in bytes. These fields
642 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
643 the subtype has the following flags:
646 Set if it has been decided that we should use the second
647 sequence instead of the first.
650 Set in the first variant frag if the macro's second implementation
651 is longer than its first. This refers to the macro as a whole,
652 not an individual relaxation.
655 Set in the first variant frag if the macro appeared in a .set nomacro
656 block and if one alternative requires a warning but the other does not.
659 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
662 The frag's "opcode" points to the first fixup for relaxable code.
664 Relaxable macros are generated using a sequence such as:
666 relax_start (SYMBOL);
667 ... generate first expansion ...
669 ... generate second expansion ...
672 The code and fixups for the unwanted alternative are discarded
673 by md_convert_frag. */
674 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
676 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
677 #define RELAX_SECOND(X) ((X) & 0xff)
678 #define RELAX_USE_SECOND 0x10000
679 #define RELAX_SECOND_LONGER 0x20000
680 #define RELAX_NOMACRO 0x40000
681 #define RELAX_DELAY_SLOT 0x80000
683 /* Branch without likely bit. If label is out of range, we turn:
685 beq reg1, reg2, label
695 with the following opcode replacements:
702 bltzal <-> bgezal (with jal label instead of j label)
704 Even though keeping the delay slot instruction in the delay slot of
705 the branch would be more efficient, it would be very tricky to do
706 correctly, because we'd have to introduce a variable frag *after*
707 the delay slot instruction, and expand that instead. Let's do it
708 the easy way for now, even if the branch-not-taken case now costs
709 one additional instruction. Out-of-range branches are not supposed
710 to be common, anyway.
712 Branch likely. If label is out of range, we turn:
714 beql reg1, reg2, label
715 delay slot (annulled if branch not taken)
724 delay slot (executed only if branch taken)
727 It would be possible to generate a shorter sequence by losing the
728 likely bit, generating something like:
733 delay slot (executed only if branch taken)
745 bltzall -> bgezal (with jal label instead of j label)
746 bgezall -> bltzal (ditto)
749 but it's not clear that it would actually improve performance. */
750 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
753 | ((toofar) ? 1 : 0) \
755 | ((likely) ? 4 : 0) \
756 | ((uncond) ? 8 : 0)))
757 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
758 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
759 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
760 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
761 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
763 /* For mips16 code, we use an entirely different form of relaxation.
764 mips16 supports two versions of most instructions which take
765 immediate values: a small one which takes some small value, and a
766 larger one which takes a 16 bit value. Since branches also follow
767 this pattern, relaxing these values is required.
769 We can assemble both mips16 and normal MIPS code in a single
770 object. Therefore, we need to support this type of relaxation at
771 the same time that we support the relaxation described above. We
772 use the high bit of the subtype field to distinguish these cases.
774 The information we store for this type of relaxation is the
775 argument code found in the opcode file for this relocation, whether
776 the user explicitly requested a small or extended form, and whether
777 the relocation is in a jump or jal delay slot. That tells us the
778 size of the value, and how it should be stored. We also store
779 whether the fragment is considered to be extended or not. We also
780 store whether this is known to be a branch to a different section,
781 whether we have tried to relax this frag yet, and whether we have
782 ever extended a PC relative fragment because of a shift count. */
783 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
786 | ((small) ? 0x100 : 0) \
787 | ((ext) ? 0x200 : 0) \
788 | ((dslot) ? 0x400 : 0) \
789 | ((jal_dslot) ? 0x800 : 0))
790 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
791 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
792 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
793 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
794 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
795 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
796 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
797 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
798 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
799 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
800 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
801 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
803 /* Is the given value a sign-extended 32-bit value? */
804 #define IS_SEXT_32BIT_NUM(x) \
805 (((x) &~ (offsetT) 0x7fffffff) == 0 \
806 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
808 /* Is the given value a sign-extended 16-bit value? */
809 #define IS_SEXT_16BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fff) == 0 \
811 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
814 /* Global variables used when generating relaxable macros. See the
815 comment above RELAX_ENCODE for more details about how relaxation
818 /* 0 if we're not emitting a relaxable macro.
819 1 if we're emitting the first of the two relaxation alternatives.
820 2 if we're emitting the second alternative. */
823 /* The first relaxable fixup in the current frag. (In other words,
824 the first fixup that refers to relaxable code.) */
827 /* sizes[0] says how many bytes of the first alternative are stored in
828 the current frag. Likewise sizes[1] for the second alternative. */
829 unsigned int sizes[2];
831 /* The symbol on which the choice of sequence depends. */
835 /* Global variables used to decide whether a macro needs a warning. */
837 /* True if the macro is in a branch delay slot. */
838 bfd_boolean delay_slot_p;
840 /* For relaxable macros, sizes[0] is the length of the first alternative
841 in bytes and sizes[1] is the length of the second alternative.
842 For non-relaxable macros, both elements give the length of the
844 unsigned int sizes[2];
846 /* The first variant frag for this macro. */
848 } mips_macro_warning;
850 /* Prototypes for static functions. */
852 #define internalError() \
853 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
855 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
857 static void append_insn
858 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
859 static void mips_no_prev_insn (int);
860 static void mips16_macro_build
861 (expressionS *, const char *, const char *, va_list);
862 static void load_register (int, expressionS *, int);
863 static void macro_start (void);
864 static void macro_end (void);
865 static void macro (struct mips_cl_insn * ip);
866 static void mips16_macro (struct mips_cl_insn * ip);
867 #ifdef LOSING_COMPILER
868 static void macro2 (struct mips_cl_insn * ip);
870 static void mips_ip (char *str, struct mips_cl_insn * ip);
871 static void mips16_ip (char *str, struct mips_cl_insn * ip);
872 static void mips16_immed
873 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
874 unsigned long *, bfd_boolean *, unsigned short *);
875 static size_t my_getSmallExpression
876 (expressionS *, bfd_reloc_code_real_type *, char *);
877 static void my_getExpression (expressionS *, char *);
878 static void s_align (int);
879 static void s_change_sec (int);
880 static void s_change_section (int);
881 static void s_cons (int);
882 static void s_float_cons (int);
883 static void s_mips_globl (int);
884 static void s_option (int);
885 static void s_mipsset (int);
886 static void s_abicalls (int);
887 static void s_cpload (int);
888 static void s_cpsetup (int);
889 static void s_cplocal (int);
890 static void s_cprestore (int);
891 static void s_cpreturn (int);
892 static void s_gpvalue (int);
893 static void s_gpword (int);
894 static void s_gpdword (int);
895 static void s_cpadd (int);
896 static void s_insn (int);
897 static void md_obj_begin (void);
898 static void md_obj_end (void);
899 static void s_mips_ent (int);
900 static void s_mips_end (int);
901 static void s_mips_frame (int);
902 static void s_mips_mask (int reg_type);
903 static void s_mips_stab (int);
904 static void s_mips_weakext (int);
905 static void s_mips_file (int);
906 static void s_mips_loc (int);
907 static bfd_boolean pic_need_relax (symbolS *, asection *);
908 static int relaxed_branch_length (fragS *, asection *, int);
909 static int validate_mips_insn (const struct mips_opcode *);
911 /* Table and functions used to map between CPU/ISA names, and
912 ISA levels, and CPU numbers. */
916 const char *name; /* CPU or ISA name. */
917 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
918 int isa; /* ISA level. */
919 int cpu; /* CPU number (default CPU if ISA). */
922 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
923 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
924 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
928 The following pseudo-ops from the Kane and Heinrich MIPS book
929 should be defined here, but are currently unsupported: .alias,
930 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
932 The following pseudo-ops from the Kane and Heinrich MIPS book are
933 specific to the type of debugging information being generated, and
934 should be defined by the object format: .aent, .begin, .bend,
935 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
938 The following pseudo-ops from the Kane and Heinrich MIPS book are
939 not MIPS CPU specific, but are also not specific to the object file
940 format. This file is probably the best place to define them, but
941 they are not currently supported: .asm0, .endr, .lab, .repeat,
944 static const pseudo_typeS mips_pseudo_table[] =
946 /* MIPS specific pseudo-ops. */
947 {"option", s_option, 0},
948 {"set", s_mipsset, 0},
949 {"rdata", s_change_sec, 'r'},
950 {"sdata", s_change_sec, 's'},
951 {"livereg", s_ignore, 0},
952 {"abicalls", s_abicalls, 0},
953 {"cpload", s_cpload, 0},
954 {"cpsetup", s_cpsetup, 0},
955 {"cplocal", s_cplocal, 0},
956 {"cprestore", s_cprestore, 0},
957 {"cpreturn", s_cpreturn, 0},
958 {"gpvalue", s_gpvalue, 0},
959 {"gpword", s_gpword, 0},
960 {"gpdword", s_gpdword, 0},
961 {"cpadd", s_cpadd, 0},
964 /* Relatively generic pseudo-ops that happen to be used on MIPS
966 {"asciiz", stringer, 1},
967 {"bss", s_change_sec, 'b'},
970 {"dword", s_cons, 3},
971 {"weakext", s_mips_weakext, 0},
973 /* These pseudo-ops are defined in read.c, but must be overridden
974 here for one reason or another. */
975 {"align", s_align, 0},
977 {"data", s_change_sec, 'd'},
978 {"double", s_float_cons, 'd'},
979 {"float", s_float_cons, 'f'},
980 {"globl", s_mips_globl, 0},
981 {"global", s_mips_globl, 0},
982 {"hword", s_cons, 1},
987 {"section", s_change_section, 0},
988 {"short", s_cons, 1},
989 {"single", s_float_cons, 'f'},
990 {"stabn", s_mips_stab, 'n'},
991 {"text", s_change_sec, 't'},
994 { "extern", ecoff_directive_extern, 0},
999 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1001 /* These pseudo-ops should be defined by the object file format.
1002 However, a.out doesn't support them, so we have versions here. */
1003 {"aent", s_mips_ent, 1},
1004 {"bgnb", s_ignore, 0},
1005 {"end", s_mips_end, 0},
1006 {"endb", s_ignore, 0},
1007 {"ent", s_mips_ent, 0},
1008 {"file", s_mips_file, 0},
1009 {"fmask", s_mips_mask, 'F'},
1010 {"frame", s_mips_frame, 0},
1011 {"loc", s_mips_loc, 0},
1012 {"mask", s_mips_mask, 'R'},
1013 {"verstamp", s_ignore, 0},
1017 extern void pop_insert (const pseudo_typeS *);
1020 mips_pop_insert (void)
1022 pop_insert (mips_pseudo_table);
1023 if (! ECOFF_DEBUGGING)
1024 pop_insert (mips_nonecoff_pseudo_table);
1027 /* Symbols labelling the current insn. */
1029 struct insn_label_list
1031 struct insn_label_list *next;
1035 static struct insn_label_list *insn_labels;
1036 static struct insn_label_list *free_insn_labels;
1038 static void mips_clear_insn_labels (void);
1041 mips_clear_insn_labels (void)
1043 register struct insn_label_list **pl;
1045 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1051 static char *expr_end;
1053 /* Expressions which appear in instructions. These are set by
1056 static expressionS imm_expr;
1057 static expressionS imm2_expr;
1058 static expressionS offset_expr;
1060 /* Relocs associated with imm_expr and offset_expr. */
1062 static bfd_reloc_code_real_type imm_reloc[3]
1063 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1064 static bfd_reloc_code_real_type offset_reloc[3]
1065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1067 /* These are set by mips16_ip if an explicit extension is used. */
1069 static bfd_boolean mips16_small, mips16_ext;
1072 /* The pdr segment for per procedure frame/regmask info. Not used for
1075 static segT pdr_seg;
1078 /* The default target format to use. */
1081 mips_target_format (void)
1083 switch (OUTPUT_FLAVOR)
1085 case bfd_target_ecoff_flavour:
1086 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1087 case bfd_target_coff_flavour:
1089 case bfd_target_elf_flavour:
1091 /* This is traditional mips. */
1092 return (target_big_endian
1093 ? (HAVE_64BIT_OBJECTS
1094 ? "elf64-tradbigmips"
1096 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1097 : (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradlittlemips"
1100 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1102 return (target_big_endian
1103 ? (HAVE_64BIT_OBJECTS
1106 ? "elf32-nbigmips" : "elf32-bigmips"))
1107 : (HAVE_64BIT_OBJECTS
1108 ? "elf64-littlemips"
1110 ? "elf32-nlittlemips" : "elf32-littlemips")));
1118 /* This function is called once, at assembler startup time. It should
1119 set up all the tables, etc. that the MD part of the assembler will need. */
1124 register const char *retval = NULL;
1128 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1129 as_warn (_("Could not set architecture and machine"));
1131 op_hash = hash_new ();
1133 for (i = 0; i < NUMOPCODES;)
1135 const char *name = mips_opcodes[i].name;
1137 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1140 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1141 mips_opcodes[i].name, retval);
1142 /* Probably a memory allocation problem? Give up now. */
1143 as_fatal (_("Broken assembler. No assembly attempted."));
1147 if (mips_opcodes[i].pinfo != INSN_MACRO)
1149 if (!validate_mips_insn (&mips_opcodes[i]))
1154 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1157 mips16_op_hash = hash_new ();
1160 while (i < bfd_mips16_num_opcodes)
1162 const char *name = mips16_opcodes[i].name;
1164 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1166 as_fatal (_("internal: can't hash `%s': %s"),
1167 mips16_opcodes[i].name, retval);
1170 if (mips16_opcodes[i].pinfo != INSN_MACRO
1171 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1172 != mips16_opcodes[i].match))
1174 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1175 mips16_opcodes[i].name, mips16_opcodes[i].args);
1180 while (i < bfd_mips16_num_opcodes
1181 && strcmp (mips16_opcodes[i].name, name) == 0);
1185 as_fatal (_("Broken assembler. No assembly attempted."));
1187 /* We add all the general register names to the symbol table. This
1188 helps us detect invalid uses of them. */
1189 for (i = 0; i < 32; i++)
1193 sprintf (buf, "$%d", i);
1194 symbol_table_insert (symbol_new (buf, reg_section, i,
1195 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1208 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1214 &zero_address_frag));
1216 /* If we don't add these register names to the symbol table, they
1217 may end up being added as regular symbols by operand(), and then
1218 make it to the object file as undefined in case they're not
1219 regarded as local symbols. They're local in o32, since `$' is a
1220 local symbol prefix, but not in n32 or n64. */
1221 for (i = 0; i < 8; i++)
1225 sprintf (buf, "$fcc%i", i);
1226 symbol_table_insert (symbol_new (buf, reg_section, -1,
1227 &zero_address_frag));
1230 mips_no_prev_insn (FALSE);
1233 mips_cprmask[0] = 0;
1234 mips_cprmask[1] = 0;
1235 mips_cprmask[2] = 0;
1236 mips_cprmask[3] = 0;
1238 /* set the default alignment for the text section (2**2) */
1239 record_alignment (text_section, 2);
1241 bfd_set_gp_size (stdoutput, g_switch_value);
1243 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1245 /* On a native system, sections must be aligned to 16 byte
1246 boundaries. When configured for an embedded ELF target, we
1248 if (strcmp (TARGET_OS, "elf") != 0)
1250 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1251 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1252 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1255 /* Create a .reginfo section for register masks and a .mdebug
1256 section for debugging information. */
1264 subseg = now_subseg;
1266 /* The ABI says this section should be loaded so that the
1267 running program can access it. However, we don't load it
1268 if we are configured for an embedded target */
1269 flags = SEC_READONLY | SEC_DATA;
1270 if (strcmp (TARGET_OS, "elf") != 0)
1271 flags |= SEC_ALLOC | SEC_LOAD;
1273 if (mips_abi != N64_ABI)
1275 sec = subseg_new (".reginfo", (subsegT) 0);
1277 bfd_set_section_flags (stdoutput, sec, flags);
1278 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1281 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1286 /* The 64-bit ABI uses a .MIPS.options section rather than
1287 .reginfo section. */
1288 sec = subseg_new (".MIPS.options", (subsegT) 0);
1289 bfd_set_section_flags (stdoutput, sec, flags);
1290 bfd_set_section_alignment (stdoutput, sec, 3);
1293 /* Set up the option header. */
1295 Elf_Internal_Options opthdr;
1298 opthdr.kind = ODK_REGINFO;
1299 opthdr.size = (sizeof (Elf_External_Options)
1300 + sizeof (Elf64_External_RegInfo));
1303 f = frag_more (sizeof (Elf_External_Options));
1304 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1305 (Elf_External_Options *) f);
1307 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1312 if (ECOFF_DEBUGGING)
1314 sec = subseg_new (".mdebug", (subsegT) 0);
1315 (void) bfd_set_section_flags (stdoutput, sec,
1316 SEC_HAS_CONTENTS | SEC_READONLY);
1317 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1320 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1322 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1323 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1324 SEC_READONLY | SEC_RELOC
1326 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1330 subseg_set (seg, subseg);
1334 if (! ECOFF_DEBUGGING)
1341 if (! ECOFF_DEBUGGING)
1346 md_assemble (char *str)
1348 struct mips_cl_insn insn;
1349 bfd_reloc_code_real_type unused_reloc[3]
1350 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1352 imm_expr.X_op = O_absent;
1353 imm2_expr.X_op = O_absent;
1354 offset_expr.X_op = O_absent;
1355 imm_reloc[0] = BFD_RELOC_UNUSED;
1356 imm_reloc[1] = BFD_RELOC_UNUSED;
1357 imm_reloc[2] = BFD_RELOC_UNUSED;
1358 offset_reloc[0] = BFD_RELOC_UNUSED;
1359 offset_reloc[1] = BFD_RELOC_UNUSED;
1360 offset_reloc[2] = BFD_RELOC_UNUSED;
1362 if (mips_opts.mips16)
1363 mips16_ip (str, &insn);
1366 mips_ip (str, &insn);
1367 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1368 str, insn.insn_opcode));
1373 as_bad ("%s `%s'", insn_error, str);
1377 if (insn.insn_mo->pinfo == INSN_MACRO)
1380 if (mips_opts.mips16)
1381 mips16_macro (&insn);
1388 if (imm_expr.X_op != O_absent)
1389 append_insn (&insn, &imm_expr, imm_reloc);
1390 else if (offset_expr.X_op != O_absent)
1391 append_insn (&insn, &offset_expr, offset_reloc);
1393 append_insn (&insn, NULL, unused_reloc);
1397 /* Return true if the given relocation might need a matching %lo().
1398 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1399 applied to local symbols. */
1401 static inline bfd_boolean
1402 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1404 return (HAVE_IN_PLACE_ADDENDS
1405 && (reloc == BFD_RELOC_HI16_S
1406 || reloc == BFD_RELOC_MIPS_GOT16));
1409 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1412 static inline bfd_boolean
1413 fixup_has_matching_lo_p (fixS *fixp)
1415 return (fixp->fx_next != NULL
1416 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1417 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1418 && fixp->fx_offset == fixp->fx_next->fx_offset);
1421 /* See whether instruction IP reads register REG. CLASS is the type
1425 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1426 enum mips_regclass class)
1428 if (class == MIPS16_REG)
1430 assert (mips_opts.mips16);
1431 reg = mips16_to_32_reg_map[reg];
1432 class = MIPS_GR_REG;
1435 /* Don't report on general register ZERO, since it never changes. */
1436 if (class == MIPS_GR_REG && reg == ZERO)
1439 if (class == MIPS_FP_REG)
1441 assert (! mips_opts.mips16);
1442 /* If we are called with either $f0 or $f1, we must check $f0.
1443 This is not optimal, because it will introduce an unnecessary
1444 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1445 need to distinguish reading both $f0 and $f1 or just one of
1446 them. Note that we don't have to check the other way,
1447 because there is no instruction that sets both $f0 and $f1
1448 and requires a delay. */
1449 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1450 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1451 == (reg &~ (unsigned) 1)))
1453 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1454 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1455 == (reg &~ (unsigned) 1)))
1458 else if (! mips_opts.mips16)
1460 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1461 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1463 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1464 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1469 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1470 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1471 & MIPS16OP_MASK_RX)]
1474 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1475 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1476 & MIPS16OP_MASK_RY)]
1479 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1480 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1481 & MIPS16OP_MASK_MOVE32Z)]
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1488 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1490 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1491 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1492 & MIPS16OP_MASK_REGR32) == reg)
1499 /* This function returns true if modifying a register requires a
1503 reg_needs_delay (unsigned int reg)
1505 unsigned long prev_pinfo;
1507 prev_pinfo = prev_insn.insn_mo->pinfo;
1508 if (! mips_opts.noreorder
1509 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1510 && ! gpr_interlocks)
1511 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1512 && ! cop_interlocks)))
1514 /* A load from a coprocessor or from memory. All load delays
1515 delay the use of general register rt for one instruction. */
1516 /* Itbl support may require additional care here. */
1517 know (prev_pinfo & INSN_WRITE_GPR_T);
1518 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1525 /* Mark instruction labels in mips16 mode. This permits the linker to
1526 handle them specially, such as generating jalx instructions when
1527 needed. We also make them odd for the duration of the assembly, in
1528 order to generate the right sort of code. We will make them even
1529 in the adjust_symtab routine, while leaving them marked. This is
1530 convenient for the debugger and the disassembler. The linker knows
1531 to make them odd again. */
1534 mips16_mark_labels (void)
1536 if (mips_opts.mips16)
1538 struct insn_label_list *l;
1541 for (l = insn_labels; l != NULL; l = l->next)
1544 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1545 S_SET_OTHER (l->label, STO_MIPS16);
1547 val = S_GET_VALUE (l->label);
1549 S_SET_VALUE (l->label, val + 1);
1554 /* End the current frag. Make it a variant frag and record the
1558 relax_close_frag (void)
1560 mips_macro_warning.first_frag = frag_now;
1561 frag_var (rs_machine_dependent, 0, 0,
1562 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1563 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1565 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1566 mips_relax.first_fixup = 0;
1569 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1570 See the comment above RELAX_ENCODE for more details. */
1573 relax_start (symbolS *symbol)
1575 assert (mips_relax.sequence == 0);
1576 mips_relax.sequence = 1;
1577 mips_relax.symbol = symbol;
1580 /* Start generating the second version of a relaxable sequence.
1581 See the comment above RELAX_ENCODE for more details. */
1586 assert (mips_relax.sequence == 1);
1587 mips_relax.sequence = 2;
1590 /* End the current relaxable sequence. */
1595 assert (mips_relax.sequence == 2);
1596 relax_close_frag ();
1597 mips_relax.sequence = 0;
1600 /* Output an instruction. IP is the instruction information.
1601 ADDRESS_EXPR is an operand of the instruction to be used with
1605 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1606 bfd_reloc_code_real_type *reloc_type)
1608 register unsigned long prev_pinfo, pinfo;
1612 relax_stateT prev_insn_frag_type = 0;
1613 bfd_boolean relaxed_branch = FALSE;
1614 bfd_boolean force_new_frag = FALSE;
1616 /* Mark instruction labels in mips16 mode. */
1617 mips16_mark_labels ();
1619 prev_pinfo = prev_insn.insn_mo->pinfo;
1620 pinfo = ip->insn_mo->pinfo;
1622 if (mips_relax.sequence != 2
1623 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1627 /* If the previous insn required any delay slots, see if we need
1628 to insert a NOP or two. There are eight kinds of possible
1629 hazards, of which an instruction can have at most one type.
1630 (1) a load from memory delay
1631 (2) a load from a coprocessor delay
1632 (3) an unconditional branch delay
1633 (4) a conditional branch delay
1634 (5) a move to coprocessor register delay
1635 (6) a load coprocessor register from memory delay
1636 (7) a coprocessor condition code delay
1637 (8) a HI/LO special register delay
1639 There are a lot of optimizations we could do that we don't.
1640 In particular, we do not, in general, reorder instructions.
1641 If you use gcc with optimization, it will reorder
1642 instructions and generally do much more optimization then we
1643 do here; repeating all that work in the assembler would only
1644 benefit hand written assembly code, and does not seem worth
1647 /* This is how a NOP is emitted. */
1648 #define emit_nop() \
1650 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1651 : md_number_to_chars (frag_more (4), 0, 4))
1653 /* The previous insn might require a delay slot, depending upon
1654 the contents of the current insn. */
1655 if (! mips_opts.mips16
1656 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1657 && ! gpr_interlocks)
1658 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1659 && ! cop_interlocks)))
1661 /* A load from a coprocessor or from memory. All load
1662 delays delay the use of general register rt for one
1664 /* Itbl support may require additional care here. */
1665 know (prev_pinfo & INSN_WRITE_GPR_T);
1666 if (mips_optimize == 0
1667 || insn_uses_reg (ip,
1668 ((prev_insn.insn_opcode >> OP_SH_RT)
1673 else if (! mips_opts.mips16
1674 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1675 && ! cop_interlocks)
1676 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1677 && ! cop_mem_interlocks)))
1679 /* A generic coprocessor delay. The previous instruction
1680 modified a coprocessor general or control register. If
1681 it modified a control register, we need to avoid any
1682 coprocessor instruction (this is probably not always
1683 required, but it sometimes is). If it modified a general
1684 register, we avoid using that register.
1686 This case is not handled very well. There is no special
1687 knowledge of CP0 handling, and the coprocessors other
1688 than the floating point unit are not distinguished at
1690 /* Itbl support may require additional care here. FIXME!
1691 Need to modify this to include knowledge about
1692 user specified delays! */
1693 if (prev_pinfo & INSN_WRITE_FPR_T)
1695 if (mips_optimize == 0
1696 || insn_uses_reg (ip,
1697 ((prev_insn.insn_opcode >> OP_SH_FT)
1702 else if (prev_pinfo & INSN_WRITE_FPR_S)
1704 if (mips_optimize == 0
1705 || insn_uses_reg (ip,
1706 ((prev_insn.insn_opcode >> OP_SH_FS)
1713 /* We don't know exactly what the previous instruction
1714 does. If the current instruction uses a coprocessor
1715 register, we must insert a NOP. If previous
1716 instruction may set the condition codes, and the
1717 current instruction uses them, we must insert two
1719 /* Itbl support may require additional care here. */
1720 if (mips_optimize == 0
1721 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1722 && (pinfo & INSN_READ_COND_CODE)))
1724 else if (pinfo & INSN_COP)
1728 else if (! mips_opts.mips16
1729 && (prev_pinfo & INSN_WRITE_COND_CODE)
1730 && ! cop_interlocks)
1732 /* The previous instruction sets the coprocessor condition
1733 codes, but does not require a general coprocessor delay
1734 (this means it is a floating point comparison
1735 instruction). If this instruction uses the condition
1736 codes, we need to insert a single NOP. */
1737 /* Itbl support may require additional care here. */
1738 if (mips_optimize == 0
1739 || (pinfo & INSN_READ_COND_CODE))
1743 /* If we're fixing up mfhi/mflo for the r7000 and the
1744 previous insn was an mfhi/mflo and the current insn
1745 reads the register that the mfhi/mflo wrote to, then
1748 else if (mips_7000_hilo_fix
1749 && MF_HILO_INSN (prev_pinfo)
1750 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1757 /* If we're fixing up mfhi/mflo for the r7000 and the
1758 2nd previous insn was an mfhi/mflo and the current insn
1759 reads the register that the mfhi/mflo wrote to, then
1762 else if (mips_7000_hilo_fix
1763 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1764 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1772 else if (prev_pinfo & INSN_READ_LO)
1774 /* The previous instruction reads the LO register; if the
1775 current instruction writes to the LO register, we must
1776 insert two NOPS. Some newer processors have interlocks.
1777 Also the tx39's multiply instructions can be executed
1778 immediately after a read from HI/LO (without the delay),
1779 though the tx39's divide insns still do require the
1781 if (! (hilo_interlocks
1782 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1783 && (mips_optimize == 0
1784 || (pinfo & INSN_WRITE_LO)))
1786 /* Most mips16 branch insns don't have a delay slot.
1787 If a read from LO is immediately followed by a branch
1788 to a write to LO we have a read followed by a write
1789 less than 2 insns away. We assume the target of
1790 a branch might be a write to LO, and insert a nop
1791 between a read and an immediately following branch. */
1792 else if (mips_opts.mips16
1793 && (mips_optimize == 0
1794 || (pinfo & MIPS16_INSN_BRANCH)))
1797 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1799 /* The previous instruction reads the HI register; if the
1800 current instruction writes to the HI register, we must
1801 insert a NOP. Some newer processors have interlocks.
1802 Also the note tx39's multiply above. */
1803 if (! (hilo_interlocks
1804 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1805 && (mips_optimize == 0
1806 || (pinfo & INSN_WRITE_HI)))
1808 /* Most mips16 branch insns don't have a delay slot.
1809 If a read from HI is immediately followed by a branch
1810 to a write to HI we have a read followed by a write
1811 less than 2 insns away. We assume the target of
1812 a branch might be a write to HI, and insert a nop
1813 between a read and an immediately following branch. */
1814 else if (mips_opts.mips16
1815 && (mips_optimize == 0
1816 || (pinfo & MIPS16_INSN_BRANCH)))
1820 /* If the previous instruction was in a noreorder section, then
1821 we don't want to insert the nop after all. */
1822 /* Itbl support may require additional care here. */
1823 if (prev_insn_unreordered)
1826 /* There are two cases which require two intervening
1827 instructions: 1) setting the condition codes using a move to
1828 coprocessor instruction which requires a general coprocessor
1829 delay and then reading the condition codes 2) reading the HI
1830 or LO register and then writing to it (except on processors
1831 which have interlocks). If we are not already emitting a NOP
1832 instruction, we must check for these cases compared to the
1833 instruction previous to the previous instruction. */
1834 if ((! mips_opts.mips16
1835 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1836 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1837 && (pinfo & INSN_READ_COND_CODE)
1838 && ! cop_interlocks)
1839 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1840 && (pinfo & INSN_WRITE_LO)
1841 && ! (hilo_interlocks
1842 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1843 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1844 && (pinfo & INSN_WRITE_HI)
1845 && ! (hilo_interlocks
1846 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1851 if (prev_prev_insn_unreordered)
1854 if (prev_prev_nop && nops == 0)
1857 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1859 /* We're out of bits in pinfo, so we must resort to string
1860 ops here. Shortcuts are selected based on opcodes being
1861 limited to the VR4120 instruction set. */
1863 const char *pn = prev_insn.insn_mo->name;
1864 const char *tn = ip->insn_mo->name;
1865 if (strncmp (pn, "macc", 4) == 0
1866 || strncmp (pn, "dmacc", 5) == 0)
1868 /* Errata 21 - [D]DIV[U] after [D]MACC */
1869 if (strstr (tn, "div"))
1872 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1873 instruction is executed immediately after a MACC or
1874 DMACC instruction, the result of [either instruction]
1876 if (strncmp (tn, "mult", 4) == 0
1877 || strncmp (tn, "dmult", 5) == 0)
1880 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1881 Applies on top of VR4181A MD(1) errata. */
1882 if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn, "mtlo") == 0
1887 || strcmp (tn, "mthi") == 0)
1890 else if (strncmp (pn, "dmult", 5) == 0
1891 && (strncmp (tn, "dmult", 5) == 0
1892 || strncmp (tn, "dmacc", 5) == 0))
1894 /* Here is the rest of errata 23. */
1897 else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
1898 && (strncmp (tn, "macc", 4) == 0
1899 || strncmp (tn, "dmacc", 5) == 0))
1901 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1902 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1903 DDIV or DDIVU instruction, the result of the MACC or
1904 DMACC instruction is incorrect.". This partly overlaps
1905 the workaround for errata 23. */
1908 if (nops < min_nops)
1912 /* If we are being given a nop instruction, don't bother with
1913 one of the nops we would otherwise output. This will only
1914 happen when a nop instruction is used with mips_optimize set
1917 && ! mips_opts.noreorder
1918 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1921 /* Now emit the right number of NOP instructions. */
1922 if (nops > 0 && ! mips_opts.noreorder)
1925 unsigned long old_frag_offset;
1927 struct insn_label_list *l;
1929 old_frag = frag_now;
1930 old_frag_offset = frag_now_fix ();
1932 for (i = 0; i < nops; i++)
1937 listing_prev_line ();
1938 /* We may be at the start of a variant frag. In case we
1939 are, make sure there is enough space for the frag
1940 after the frags created by listing_prev_line. The
1941 argument to frag_grow here must be at least as large
1942 as the argument to all other calls to frag_grow in
1943 this file. We don't have to worry about being in the
1944 middle of a variant frag, because the variants insert
1945 all needed nop instructions themselves. */
1949 for (l = insn_labels; l != NULL; l = l->next)
1953 assert (S_GET_SEGMENT (l->label) == now_seg);
1954 symbol_set_frag (l->label, frag_now);
1955 val = (valueT) frag_now_fix ();
1956 /* mips16 text labels are stored as odd. */
1957 if (mips_opts.mips16)
1959 S_SET_VALUE (l->label, val);
1962 #ifndef NO_ECOFF_DEBUGGING
1963 if (ECOFF_DEBUGGING)
1964 ecoff_fix_loc (old_frag, old_frag_offset);
1967 else if (prev_nop_frag != NULL)
1969 /* We have a frag holding nops we may be able to remove. If
1970 we don't need any nops, we can decrease the size of
1971 prev_nop_frag by the size of one instruction. If we do
1972 need some nops, we count them in prev_nops_required. */
1973 if (prev_nop_frag_since == 0)
1977 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1978 --prev_nop_frag_holds;
1981 prev_nop_frag_required += nops;
1985 if (prev_prev_nop == 0)
1987 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1988 --prev_nop_frag_holds;
1991 ++prev_nop_frag_required;
1994 if (prev_nop_frag_holds <= prev_nop_frag_required)
1995 prev_nop_frag = NULL;
1997 ++prev_nop_frag_since;
1999 /* Sanity check: by the time we reach the second instruction
2000 after prev_nop_frag, we should have used up all the nops
2001 one way or another. */
2002 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2006 /* Record the frag type before frag_var. */
2008 prev_insn_frag_type = prev_insn_frag->fr_type;
2011 && *reloc_type == BFD_RELOC_16_PCREL_S2
2012 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2013 || pinfo & INSN_COND_BRANCH_LIKELY)
2014 && mips_relax_branch
2015 /* Don't try branch relaxation within .set nomacro, or within
2016 .set noat if we use $at for PIC computations. If it turns
2017 out that the branch was out-of-range, we'll get an error. */
2018 && !mips_opts.warn_about_macros
2019 && !(mips_opts.noat && mips_pic != NO_PIC)
2020 && !mips_opts.mips16)
2022 relaxed_branch = TRUE;
2023 f = frag_var (rs_machine_dependent,
2024 relaxed_branch_length
2026 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2027 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2029 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2030 pinfo & INSN_COND_BRANCH_LIKELY,
2031 pinfo & INSN_WRITE_GPR_31,
2033 address_expr->X_add_symbol,
2034 address_expr->X_add_number,
2036 *reloc_type = BFD_RELOC_UNUSED;
2038 else if (*reloc_type > BFD_RELOC_UNUSED)
2040 /* We need to set up a variant frag. */
2041 assert (mips_opts.mips16 && address_expr != NULL);
2042 f = frag_var (rs_machine_dependent, 4, 0,
2043 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2044 mips16_small, mips16_ext,
2046 & INSN_UNCOND_BRANCH_DELAY),
2047 (*prev_insn_reloc_type
2048 == BFD_RELOC_MIPS16_JMP)),
2049 make_expr_symbol (address_expr), 0, NULL);
2051 else if (mips_opts.mips16
2053 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2055 /* Make sure there is enough room to swap this instruction with
2056 a following jump instruction. */
2062 if (mips_opts.mips16
2063 && mips_opts.noreorder
2064 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2065 as_warn (_("extended instruction in delay slot"));
2067 if (mips_relax.sequence)
2069 /* If we've reached the end of this frag, turn it into a variant
2070 frag and record the information for the instructions we've
2072 if (frag_room () < 4)
2073 relax_close_frag ();
2074 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2077 if (mips_relax.sequence != 2)
2078 mips_macro_warning.sizes[0] += 4;
2079 if (mips_relax.sequence != 1)
2080 mips_macro_warning.sizes[1] += 4;
2085 fixp[0] = fixp[1] = fixp[2] = NULL;
2086 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2088 if (address_expr->X_op == O_constant)
2092 switch (*reloc_type)
2095 ip->insn_opcode |= address_expr->X_add_number;
2098 case BFD_RELOC_MIPS_HIGHEST:
2099 tmp = (address_expr->X_add_number
2100 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2102 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2105 case BFD_RELOC_MIPS_HIGHER:
2106 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2107 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2110 case BFD_RELOC_HI16_S:
2111 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2115 case BFD_RELOC_HI16:
2116 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2119 case BFD_RELOC_UNUSED:
2120 case BFD_RELOC_LO16:
2121 case BFD_RELOC_MIPS_GOT_DISP:
2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2125 case BFD_RELOC_MIPS_JMP:
2126 if ((address_expr->X_add_number & 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr->X_add_number);
2129 if (address_expr->X_add_number & ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr->X_add_number);
2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP:
2136 if ((address_expr->X_add_number & 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr->X_add_number);
2139 if (address_expr->X_add_number & ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr->X_add_number);
2143 (((address_expr->X_add_number & 0x7c0000) << 3)
2144 | ((address_expr->X_add_number & 0xf800000) >> 7)
2145 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2:
2155 else if (*reloc_type < BFD_RELOC_UNUSED)
2158 reloc_howto_type *howto;
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i = 1; i < 3; i++)
2164 if (reloc_type[i] == BFD_RELOC_UNUSED)
2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2169 bfd_get_reloc_size(howto),
2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2177 && ! howto->partial_inplace
2178 && (reloc_type[0] == BFD_RELOC_16
2179 || reloc_type[0] == BFD_RELOC_32
2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2181 || reloc_type[0] == BFD_RELOC_HI16_S
2182 || reloc_type[0] == BFD_RELOC_LO16
2183 || reloc_type[0] == BFD_RELOC_GPREL16
2184 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2185 || reloc_type[0] == BFD_RELOC_GPREL32
2186 || reloc_type[0] == BFD_RELOC_64
2187 || reloc_type[0] == BFD_RELOC_CTOR
2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2194 fixp[0]->fx_no_overflow = 1;
2196 if (mips_relax.sequence)
2198 if (mips_relax.first_fixup == 0)
2199 mips_relax.first_fixup = fixp[0];
2201 else if (reloc_needs_lo_p (*reloc_type))
2203 struct mips_hi_fixup *hi_fixup;
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup = mips_hi_fixup_list;
2208 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2210 hi_fixup = ((struct mips_hi_fixup *)
2211 xmalloc (sizeof (struct mips_hi_fixup)));
2212 hi_fixup->next = mips_hi_fixup_list;
2213 mips_hi_fixup_list = hi_fixup;
2215 hi_fixup->fixp = fixp[0];
2216 hi_fixup->seg = now_seg;
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i = 1; i < 3; i++)
2225 if (reloc_type[i] != BFD_RELOC_UNUSED)
2227 address_expr->X_op = O_absent;
2228 address_expr->X_add_symbol = 0;
2229 address_expr->X_add_number = 0;
2231 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2232 fixp[0]->fx_size, address_expr,
2233 FALSE, reloc_type[i]);
2238 if (! mips_opts.mips16)
2240 md_number_to_chars (f, ip->insn_opcode, 4);
2242 dwarf2_emit_insn (4);
2245 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2247 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2248 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2250 /* The value passed to dwarf2_emit_insn is the distance between
2251 the end of the current instruction and the address that should
2252 be recorded in the debug tables. Since we want to use ISA-encoded
2253 addresses in MIPS16 debug info, the value is one byte less than
2254 the real instruction length. */
2255 dwarf2_emit_insn (3);
2262 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2265 md_number_to_chars (f, ip->insn_opcode, 2);
2267 dwarf2_emit_insn (ip->use_extend ? 3 : 1);
2271 /* Update the register mask information. */
2272 if (! mips_opts.mips16)
2274 if (pinfo & INSN_WRITE_GPR_D)
2275 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2276 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2277 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2278 if (pinfo & INSN_READ_GPR_S)
2279 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2280 if (pinfo & INSN_WRITE_GPR_31)
2281 mips_gprmask |= 1 << RA;
2282 if (pinfo & INSN_WRITE_FPR_D)
2283 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2284 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2285 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2286 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2287 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2288 if ((pinfo & INSN_READ_FPR_R) != 0)
2289 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2290 if (pinfo & INSN_COP)
2292 /* We don't keep enough information to sort these cases out.
2293 The itbl support does keep this information however, although
2294 we currently don't support itbl fprmats as part of the cop
2295 instruction. May want to add this support in the future. */
2297 /* Never set the bit for $0, which is always zero. */
2298 mips_gprmask &= ~1 << 0;
2302 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2303 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2304 & MIPS16OP_MASK_RX);
2305 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2306 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2307 & MIPS16OP_MASK_RY);
2308 if (pinfo & MIPS16_INSN_WRITE_Z)
2309 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2310 & MIPS16OP_MASK_RZ);
2311 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2312 mips_gprmask |= 1 << TREG;
2313 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2314 mips_gprmask |= 1 << SP;
2315 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2316 mips_gprmask |= 1 << RA;
2317 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2318 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2319 if (pinfo & MIPS16_INSN_READ_Z)
2320 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2321 & MIPS16OP_MASK_MOVE32Z);
2322 if (pinfo & MIPS16_INSN_READ_GPR_X)
2323 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2324 & MIPS16OP_MASK_REGR32);
2327 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2329 /* Filling the branch delay slot is more complex. We try to
2330 switch the branch with the previous instruction, which we can
2331 do if the previous instruction does not set up a condition
2332 that the branch tests and if the branch is not itself the
2333 target of any branch. */
2334 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2335 || (pinfo & INSN_COND_BRANCH_DELAY))
2337 if (mips_optimize < 2
2338 /* If we have seen .set volatile or .set nomove, don't
2340 || mips_opts.nomove != 0
2341 /* If we had to emit any NOP instructions, then we
2342 already know we can not swap. */
2344 /* If we don't even know the previous insn, we can not
2346 || ! prev_insn_valid
2347 /* If the previous insn is already in a branch delay
2348 slot, then we can not swap. */
2349 || prev_insn_is_delay_slot
2350 /* If the previous previous insn was in a .set
2351 noreorder, we can't swap. Actually, the MIPS
2352 assembler will swap in this situation. However, gcc
2353 configured -with-gnu-as will generate code like
2359 in which we can not swap the bne and INSN. If gcc is
2360 not configured -with-gnu-as, it does not output the
2361 .set pseudo-ops. We don't have to check
2362 prev_insn_unreordered, because prev_insn_valid will
2363 be 0 in that case. We don't want to use
2364 prev_prev_insn_valid, because we do want to be able
2365 to swap at the start of a function. */
2366 || prev_prev_insn_unreordered
2367 /* If the branch is itself the target of a branch, we
2368 can not swap. We cheat on this; all we check for is
2369 whether there is a label on this instruction. If
2370 there are any branches to anything other than a
2371 label, users must use .set noreorder. */
2372 || insn_labels != NULL
2373 /* If the previous instruction is in a variant frag
2374 other than this branch's one, we cannot do the swap.
2375 This does not apply to the mips16, which uses variant
2376 frags for different purposes. */
2377 || (! mips_opts.mips16
2378 && prev_insn_frag_type == rs_machine_dependent)
2379 /* If the branch reads the condition codes, we don't
2380 even try to swap, because in the sequence
2385 we can not swap, and I don't feel like handling that
2387 || (! mips_opts.mips16
2388 && (pinfo & INSN_READ_COND_CODE)
2389 && ! cop_interlocks)
2390 /* We can not swap with an instruction that requires a
2391 delay slot, because the target of the branch might
2392 interfere with that instruction. */
2393 || (! mips_opts.mips16
2395 /* Itbl support may require additional care here. */
2396 & (INSN_LOAD_COPROC_DELAY
2397 | INSN_COPROC_MOVE_DELAY
2398 | INSN_WRITE_COND_CODE))
2399 && ! cop_interlocks)
2400 || (! (hilo_interlocks
2401 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2405 || (! mips_opts.mips16
2406 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2407 && ! gpr_interlocks)
2408 || (! mips_opts.mips16
2409 /* Itbl support may require additional care here. */
2410 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2411 && ! cop_mem_interlocks)
2412 /* We can not swap with a branch instruction. */
2414 & (INSN_UNCOND_BRANCH_DELAY
2415 | INSN_COND_BRANCH_DELAY
2416 | INSN_COND_BRANCH_LIKELY))
2417 /* We do not swap with a trap instruction, since it
2418 complicates trap handlers to have the trap
2419 instruction be in a delay slot. */
2420 || (prev_pinfo & INSN_TRAP)
2421 /* If the branch reads a register that the previous
2422 instruction sets, we can not swap. */
2423 || (! mips_opts.mips16
2424 && (prev_pinfo & INSN_WRITE_GPR_T)
2425 && insn_uses_reg (ip,
2426 ((prev_insn.insn_opcode >> OP_SH_RT)
2429 || (! mips_opts.mips16
2430 && (prev_pinfo & INSN_WRITE_GPR_D)
2431 && insn_uses_reg (ip,
2432 ((prev_insn.insn_opcode >> OP_SH_RD)
2435 || (mips_opts.mips16
2436 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2437 && insn_uses_reg (ip,
2438 ((prev_insn.insn_opcode
2440 & MIPS16OP_MASK_RX),
2442 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2443 && insn_uses_reg (ip,
2444 ((prev_insn.insn_opcode
2446 & MIPS16OP_MASK_RY),
2448 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2449 && insn_uses_reg (ip,
2450 ((prev_insn.insn_opcode
2452 & MIPS16OP_MASK_RZ),
2454 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2455 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2456 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2457 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2458 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2459 && insn_uses_reg (ip,
2460 MIPS16OP_EXTRACT_REG32R (prev_insn.
2463 /* If the branch writes a register that the previous
2464 instruction sets, we can not swap (we know that
2465 branches write only to RD or to $31). */
2466 || (! mips_opts.mips16
2467 && (prev_pinfo & INSN_WRITE_GPR_T)
2468 && (((pinfo & INSN_WRITE_GPR_D)
2469 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2470 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2471 || ((pinfo & INSN_WRITE_GPR_31)
2472 && (((prev_insn.insn_opcode >> OP_SH_RT)
2475 || (! mips_opts.mips16
2476 && (prev_pinfo & INSN_WRITE_GPR_D)
2477 && (((pinfo & INSN_WRITE_GPR_D)
2478 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2479 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2480 || ((pinfo & INSN_WRITE_GPR_31)
2481 && (((prev_insn.insn_opcode >> OP_SH_RD)
2484 || (mips_opts.mips16
2485 && (pinfo & MIPS16_INSN_WRITE_31)
2486 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2487 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2488 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2490 /* If the branch writes a register that the previous
2491 instruction reads, we can not swap (we know that
2492 branches only write to RD or to $31). */
2493 || (! mips_opts.mips16
2494 && (pinfo & INSN_WRITE_GPR_D)
2495 && insn_uses_reg (&prev_insn,
2496 ((ip->insn_opcode >> OP_SH_RD)
2499 || (! mips_opts.mips16
2500 && (pinfo & INSN_WRITE_GPR_31)
2501 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2502 || (mips_opts.mips16
2503 && (pinfo & MIPS16_INSN_WRITE_31)
2504 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2511 && ! cop_interlocks)
2512 || ((prev_prev_insn.insn_mo->pinfo
2513 & INSN_LOAD_MEMORY_DELAY)
2514 && ! gpr_interlocks))
2515 && insn_uses_reg (ip,
2516 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo & INSN_READ_COND_CODE)
2522 && (prev_pinfo & INSN_WRITE_COND_CODE))
2523 || ((pinfo & INSN_WRITE_COND_CODE)
2524 && (prev_pinfo & INSN_READ_COND_CODE))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts.mips16
2528 && (prev_pinfo & MIPS16_INSN_READ_PC))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts.mips16 && prev_insn_extended)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts.mips16 && prev_insn_fixp[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo & INSN_SYNC))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 /* Update the previous insn information. */
2546 prev_prev_insn = *ip;
2547 prev_insn.insn_mo = &dummy_opcode;
2551 /* It looks like we can actually do the swap. */
2552 if (! mips_opts.mips16)
2557 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2558 if (!relaxed_branch)
2560 /* If this is not a relaxed branch, then just
2561 swap the instructions. */
2562 memcpy (temp, prev_f, 4);
2563 memcpy (prev_f, f, 4);
2564 memcpy (f, temp, 4);
2568 /* If this is a relaxed branch, then we move the
2569 instruction to be placed in the delay slot to
2570 the current frag, shrinking the fixed part of
2571 the originating frag. If the branch occupies
2572 the tail of the latter, we move it backwards,
2573 into the space freed by the moved instruction. */
2575 memcpy (f, prev_f, 4);
2576 prev_insn_frag->fr_fix -= 4;
2577 if (prev_insn_frag->fr_type == rs_machine_dependent)
2578 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2581 if (prev_insn_fixp[0])
2583 prev_insn_fixp[0]->fx_frag = frag_now;
2584 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2586 if (prev_insn_fixp[1])
2588 prev_insn_fixp[1]->fx_frag = frag_now;
2589 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2591 if (prev_insn_fixp[2])
2593 prev_insn_fixp[2]->fx_frag = frag_now;
2594 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2596 if (prev_insn_fixp[0] && HAVE_NEWABI
2597 && prev_insn_frag != frag_now
2598 && (prev_insn_fixp[0]->fx_r_type
2599 == BFD_RELOC_MIPS_GOT_DISP
2600 || (prev_insn_fixp[0]->fx_r_type
2601 == BFD_RELOC_MIPS_CALL16)))
2603 /* To avoid confusion in tc_gen_reloc, we must
2604 ensure that this does not become a variant
2606 force_new_frag = TRUE;
2609 if (!relaxed_branch)
2613 fixp[0]->fx_frag = prev_insn_frag;
2614 fixp[0]->fx_where = prev_insn_where;
2618 fixp[1]->fx_frag = prev_insn_frag;
2619 fixp[1]->fx_where = prev_insn_where;
2623 fixp[2]->fx_frag = prev_insn_frag;
2624 fixp[2]->fx_where = prev_insn_where;
2627 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2630 fixp[0]->fx_where -= 4;
2632 fixp[1]->fx_where -= 4;
2634 fixp[2]->fx_where -= 4;
2642 assert (prev_insn_fixp[0] == NULL);
2643 assert (prev_insn_fixp[1] == NULL);
2644 assert (prev_insn_fixp[2] == NULL);
2645 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2646 memcpy (temp, prev_f, 2);
2647 memcpy (prev_f, f, 2);
2648 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2650 assert (*reloc_type == BFD_RELOC_UNUSED);
2651 memcpy (f, temp, 2);
2655 memcpy (f, f + 2, 2);
2656 memcpy (f + 2, temp, 2);
2660 fixp[0]->fx_frag = prev_insn_frag;
2661 fixp[0]->fx_where = prev_insn_where;
2665 fixp[1]->fx_frag = prev_insn_frag;
2666 fixp[1]->fx_where = prev_insn_where;
2670 fixp[2]->fx_frag = prev_insn_frag;
2671 fixp[2]->fx_where = prev_insn_where;
2675 /* Update the previous insn information; leave prev_insn
2677 prev_prev_insn = *ip;
2679 prev_insn_is_delay_slot = 1;
2681 /* If that was an unconditional branch, forget the previous
2682 insn information. */
2683 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2685 prev_prev_insn.insn_mo = &dummy_opcode;
2686 prev_insn.insn_mo = &dummy_opcode;
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2697 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2699 /* We don't yet optimize a branch likely. What we should do
2700 is look at the target, copy the instruction found there
2701 into the delay slot, and increment the branch to jump to
2702 the next instruction. */
2704 /* Update the previous insn information. */
2705 prev_prev_insn = *ip;
2706 prev_insn.insn_mo = &dummy_opcode;
2707 prev_insn_fixp[0] = NULL;
2708 prev_insn_fixp[1] = NULL;
2709 prev_insn_fixp[2] = NULL;
2710 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2711 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2712 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2713 prev_insn_extended = 0;
2717 /* Update the previous insn information. */
2719 prev_prev_insn.insn_mo = &dummy_opcode;
2721 prev_prev_insn = prev_insn;
2724 /* Any time we see a branch, we always fill the delay slot
2725 immediately; since this insn is not a branch, we know it
2726 is not in a delay slot. */
2727 prev_insn_is_delay_slot = 0;
2729 prev_insn_fixp[0] = fixp[0];
2730 prev_insn_fixp[1] = fixp[1];
2731 prev_insn_fixp[2] = fixp[2];
2732 prev_insn_reloc_type[0] = reloc_type[0];
2733 prev_insn_reloc_type[1] = reloc_type[1];
2734 prev_insn_reloc_type[2] = reloc_type[2];
2735 if (mips_opts.mips16)
2736 prev_insn_extended = (ip->use_extend
2737 || *reloc_type > BFD_RELOC_UNUSED);
2740 prev_prev_insn_unreordered = prev_insn_unreordered;
2741 prev_insn_unreordered = 0;
2742 prev_insn_frag = frag_now;
2743 prev_insn_where = f - frag_now->fr_literal;
2744 prev_insn_valid = 1;
2746 else if (mips_relax.sequence != 2)
2748 /* We need to record a bit of information even when we are not
2749 reordering, in order to determine the base address for mips16
2750 PC relative relocs. */
2751 prev_prev_insn = prev_insn;
2753 prev_insn_reloc_type[0] = reloc_type[0];
2754 prev_insn_reloc_type[1] = reloc_type[1];
2755 prev_insn_reloc_type[2] = reloc_type[2];
2756 prev_prev_insn_unreordered = prev_insn_unreordered;
2757 prev_insn_unreordered = 1;
2760 /* We just output an insn, so the next one doesn't have a label. */
2761 mips_clear_insn_labels ();
2764 /* This function forgets that there was any previous instruction or
2765 label. If PRESERVE is non-zero, it remembers enough information to
2766 know whether nops are needed before a noreorder section. */
2769 mips_no_prev_insn (int preserve)
2773 prev_insn.insn_mo = &dummy_opcode;
2774 prev_prev_insn.insn_mo = &dummy_opcode;
2775 prev_nop_frag = NULL;
2776 prev_nop_frag_holds = 0;
2777 prev_nop_frag_required = 0;
2778 prev_nop_frag_since = 0;
2780 prev_insn_valid = 0;
2781 prev_insn_is_delay_slot = 0;
2782 prev_insn_unreordered = 0;
2783 prev_insn_extended = 0;
2784 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2785 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2786 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2787 prev_prev_insn_unreordered = 0;
2788 mips_clear_insn_labels ();
2791 /* This function must be called whenever we turn on noreorder or emit
2792 something other than instructions. It inserts any NOPS which might
2793 be needed by the previous instruction, and clears the information
2794 kept for the previous instructions. The INSNS parameter is true if
2795 instructions are to follow. */
2798 mips_emit_delays (bfd_boolean insns)
2800 if (! mips_opts.noreorder)
2805 if ((! mips_opts.mips16
2806 && ((prev_insn.insn_mo->pinfo
2807 & (INSN_LOAD_COPROC_DELAY
2808 | INSN_COPROC_MOVE_DELAY
2809 | INSN_WRITE_COND_CODE))
2810 && ! cop_interlocks))
2811 || (! hilo_interlocks
2812 && (prev_insn.insn_mo->pinfo
2815 || (! mips_opts.mips16
2816 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2817 && ! gpr_interlocks)
2818 || (! mips_opts.mips16
2819 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2820 && ! cop_mem_interlocks))
2822 /* Itbl support may require additional care here. */
2824 if ((! mips_opts.mips16
2825 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2826 && ! cop_interlocks))
2827 || (! hilo_interlocks
2828 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2829 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2832 if (prev_insn_unreordered)
2835 else if ((! mips_opts.mips16
2836 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2837 && ! cop_interlocks))
2838 || (! hilo_interlocks
2839 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2840 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2842 /* Itbl support may require additional care here. */
2843 if (! prev_prev_insn_unreordered)
2847 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2850 const char *pn = prev_insn.insn_mo->name;
2851 if (strncmp (pn, "macc", 4) == 0
2852 || strncmp (pn, "dmacc", 5) == 0
2853 || strncmp (pn, "dmult", 5) == 0
2854 || strstr (pn, "div"))
2856 if (nops < min_nops)
2862 struct insn_label_list *l;
2866 /* Record the frag which holds the nop instructions, so
2867 that we can remove them if we don't need them. */
2868 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2869 prev_nop_frag = frag_now;
2870 prev_nop_frag_holds = nops;
2871 prev_nop_frag_required = 0;
2872 prev_nop_frag_since = 0;
2875 for (; nops > 0; --nops)
2880 /* Move on to a new frag, so that it is safe to simply
2881 decrease the size of prev_nop_frag. */
2882 frag_wane (frag_now);
2886 for (l = insn_labels; l != NULL; l = l->next)
2890 assert (S_GET_SEGMENT (l->label) == now_seg);
2891 symbol_set_frag (l->label, frag_now);
2892 val = (valueT) frag_now_fix ();
2893 /* mips16 text labels are stored as odd. */
2894 if (mips_opts.mips16)
2896 S_SET_VALUE (l->label, val);
2901 /* Mark instruction labels in mips16 mode. */
2903 mips16_mark_labels ();
2905 mips_no_prev_insn (insns);
2908 /* Set up global variables for the start of a new macro. */
2913 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2914 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2915 && (prev_insn.insn_mo->pinfo
2916 & (INSN_UNCOND_BRANCH_DELAY
2917 | INSN_COND_BRANCH_DELAY
2918 | INSN_COND_BRANCH_LIKELY)) != 0);
2921 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2922 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2923 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2926 macro_warning (relax_substateT subtype)
2928 if (subtype & RELAX_DELAY_SLOT)
2929 return _("Macro instruction expanded into multiple instructions"
2930 " in a branch delay slot");
2931 else if (subtype & RELAX_NOMACRO)
2932 return _("Macro instruction expanded into multiple instructions");
2937 /* Finish up a macro. Emit warnings as appropriate. */
2942 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2944 relax_substateT subtype;
2946 /* Set up the relaxation warning flags. */
2948 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2949 subtype |= RELAX_SECOND_LONGER;
2950 if (mips_opts.warn_about_macros)
2951 subtype |= RELAX_NOMACRO;
2952 if (mips_macro_warning.delay_slot_p)
2953 subtype |= RELAX_DELAY_SLOT;
2955 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2957 /* Either the macro has a single implementation or both
2958 implementations are longer than 4 bytes. Emit the
2960 const char *msg = macro_warning (subtype);
2966 /* One implementation might need a warning but the other
2967 definitely doesn't. */
2968 mips_macro_warning.first_frag->fr_subtype |= subtype;
2973 /* Build an instruction created by a macro expansion. This is passed
2974 a pointer to the count of instructions created so far, an
2975 expression, the name of the instruction to build, an operand format
2976 string, and corresponding arguments. */
2979 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2981 struct mips_cl_insn insn;
2982 bfd_reloc_code_real_type r[3];
2985 va_start (args, fmt);
2987 if (mips_opts.mips16)
2989 mips16_macro_build (ep, name, fmt, args);
2994 r[0] = BFD_RELOC_UNUSED;
2995 r[1] = BFD_RELOC_UNUSED;
2996 r[2] = BFD_RELOC_UNUSED;
2997 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2998 assert (insn.insn_mo);
2999 assert (strcmp (name, insn.insn_mo->name) == 0);
3001 /* Search until we get a match for NAME. */
3004 /* It is assumed here that macros will never generate
3005 MDMX or MIPS-3D instructions. */
3006 if (strcmp (fmt, insn.insn_mo->args) == 0
3007 && insn.insn_mo->pinfo != INSN_MACRO
3008 && OPCODE_IS_MEMBER (insn.insn_mo,
3010 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3012 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3016 assert (insn.insn_mo->name);
3017 assert (strcmp (name, insn.insn_mo->name) == 0);
3020 insn.insn_opcode = insn.insn_mo->match;
3038 insn.insn_opcode |= (va_arg (args, int)
3039 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3044 /* Note that in the macro case, these arguments are already
3045 in MSB form. (When handling the instruction in the
3046 non-macro case, these arguments are sizes from which
3047 MSB values must be calculated.) */
3048 insn.insn_opcode |= (va_arg (args, int)
3049 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3055 /* Note that in the macro case, these arguments are already
3056 in MSBD form. (When handling the instruction in the
3057 non-macro case, these arguments are sizes from which
3058 MSBD values must be calculated.) */
3059 insn.insn_opcode |= (va_arg (args, int)
3060 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3071 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3075 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3080 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3086 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3091 int tmp = va_arg (args, int);
3093 insn.insn_opcode |= tmp << OP_SH_RT;
3094 insn.insn_opcode |= tmp << OP_SH_RD;
3100 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3107 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3111 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3115 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3119 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3123 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3130 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3136 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3137 assert (*r == BFD_RELOC_GPREL16
3138 || *r == BFD_RELOC_MIPS_LITERAL
3139 || *r == BFD_RELOC_MIPS_HIGHER
3140 || *r == BFD_RELOC_HI16_S
3141 || *r == BFD_RELOC_LO16
3142 || *r == BFD_RELOC_MIPS_GOT16
3143 || *r == BFD_RELOC_MIPS_CALL16
3144 || *r == BFD_RELOC_MIPS_GOT_DISP
3145 || *r == BFD_RELOC_MIPS_GOT_PAGE
3146 || *r == BFD_RELOC_MIPS_GOT_OFST
3147 || *r == BFD_RELOC_MIPS_GOT_LO16
3148 || *r == BFD_RELOC_MIPS_CALL_LO16);
3152 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3154 && (ep->X_op == O_constant
3155 || (ep->X_op == O_symbol
3156 && (*r == BFD_RELOC_MIPS_HIGHEST
3157 || *r == BFD_RELOC_HI16_S
3158 || *r == BFD_RELOC_HI16
3159 || *r == BFD_RELOC_GPREL16
3160 || *r == BFD_RELOC_MIPS_GOT_HI16
3161 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3165 assert (ep != NULL);
3167 * This allows macro() to pass an immediate expression for
3168 * creating short branches without creating a symbol.
3169 * Note that the expression still might come from the assembly
3170 * input, in which case the value is not checked for range nor
3171 * is a relocation entry generated (yuck).
3173 if (ep->X_op == O_constant)
3175 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3179 *r = BFD_RELOC_16_PCREL_S2;
3183 assert (ep != NULL);
3184 *r = BFD_RELOC_MIPS_JMP;
3188 insn.insn_opcode |= va_arg (args, unsigned long);
3197 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3199 append_insn (&insn, ep, r);
3203 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3206 struct mips_cl_insn insn;
3207 bfd_reloc_code_real_type r[3]
3208 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3210 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3211 assert (insn.insn_mo);
3212 assert (strcmp (name, insn.insn_mo->name) == 0);
3214 while (strcmp (fmt, insn.insn_mo->args) != 0
3215 || insn.insn_mo->pinfo == INSN_MACRO)
3218 assert (insn.insn_mo->name);
3219 assert (strcmp (name, insn.insn_mo->name) == 0);
3222 insn.insn_opcode = insn.insn_mo->match;
3223 insn.use_extend = FALSE;
3242 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3251 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3255 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3265 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3272 regno = va_arg (args, int);
3273 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3274 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3295 assert (ep != NULL);
3297 if (ep->X_op != O_constant)
3298 *r = (int) BFD_RELOC_UNUSED + c;
3301 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3302 FALSE, &insn.insn_opcode, &insn.use_extend,
3305 *r = BFD_RELOC_UNUSED;
3311 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3318 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3320 append_insn (&insn, ep, r);
3324 * Generate a "jalr" instruction with a relocation hint to the called
3325 * function. This occurs in NewABI PIC code.
3328 macro_build_jalr (expressionS *ep)
3337 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3339 fix_new_exp (frag_now, f - frag_now->fr_literal,
3340 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3344 * Generate a "lui" instruction.
3347 macro_build_lui (expressionS *ep, int regnum)
3349 expressionS high_expr;
3350 struct mips_cl_insn insn;
3351 bfd_reloc_code_real_type r[3]
3352 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3353 const char *name = "lui";
3354 const char *fmt = "t,u";
3356 assert (! mips_opts.mips16);
3360 if (high_expr.X_op == O_constant)
3362 /* we can compute the instruction now without a relocation entry */
3363 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3365 *r = BFD_RELOC_UNUSED;
3369 assert (ep->X_op == O_symbol);
3370 /* _gp_disp is a special case, used from s_cpload. */
3371 assert (mips_pic == NO_PIC
3373 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3374 *r = BFD_RELOC_HI16_S;
3377 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3378 assert (insn.insn_mo);
3379 assert (strcmp (name, insn.insn_mo->name) == 0);
3380 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3382 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3383 if (*r == BFD_RELOC_UNUSED)
3385 insn.insn_opcode |= high_expr.X_add_number;
3386 append_insn (&insn, NULL, r);
3389 append_insn (&insn, &high_expr, r);
3392 /* Generate a sequence of instructions to do a load or store from a constant
3393 offset off of a base register (breg) into/from a target register (treg),
3394 using AT if necessary. */
3396 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3397 int treg, int breg, int dbl)
3399 assert (ep->X_op == O_constant);
3401 /* Sign-extending 32-bit constants makes their handling easier. */
3402 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3403 == ~((bfd_vma) 0x7fffffff)))
3405 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3406 as_bad (_("constant too large"));
3408 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3412 /* Right now, this routine can only handle signed 32-bit constants. */
3413 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3414 as_warn (_("operand overflow"));
3416 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3418 /* Signed 16-bit offset will fit in the op. Easy! */
3419 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3423 /* 32-bit offset, need multiple instructions and AT, like:
3424 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3425 addu $tempreg,$tempreg,$breg
3426 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3427 to handle the complete offset. */
3428 macro_build_lui (ep, AT);
3429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3430 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3433 as_warn (_("Macro used $at after \".set noat\""));
3438 * Generates code to set the $at register to true (one)
3439 * if reg is less than the immediate expression.
3442 set_at (int reg, int unsignedp)
3444 if (imm_expr.X_op == O_constant
3445 && imm_expr.X_add_number >= -0x8000
3446 && imm_expr.X_add_number < 0x8000)
3447 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3448 AT, reg, BFD_RELOC_LO16);
3451 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3452 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3457 normalize_constant_expr (expressionS *ex)
3459 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3460 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3464 /* Warn if an expression is not a constant. */
3467 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3469 if (ex->X_op == O_big)
3470 as_bad (_("unsupported large constant"));
3471 else if (ex->X_op != O_constant)
3472 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3474 normalize_constant_expr (ex);
3477 /* Count the leading zeroes by performing a binary chop. This is a
3478 bulky bit of source, but performance is a LOT better for the
3479 majority of values than a simple loop to count the bits:
3480 for (lcnt = 0; (lcnt < 32); lcnt++)
3481 if ((v) & (1 << (31 - lcnt)))
3483 However it is not code size friendly, and the gain will drop a bit
3484 on certain cached systems.
3486 #define COUNT_TOP_ZEROES(v) \
3487 (((v) & ~0xffff) == 0 \
3488 ? ((v) & ~0xff) == 0 \
3489 ? ((v) & ~0xf) == 0 \
3490 ? ((v) & ~0x3) == 0 \
3491 ? ((v) & ~0x1) == 0 \
3496 : ((v) & ~0x7) == 0 \
3499 : ((v) & ~0x3f) == 0 \
3500 ? ((v) & ~0x1f) == 0 \
3503 : ((v) & ~0x7f) == 0 \
3506 : ((v) & ~0xfff) == 0 \
3507 ? ((v) & ~0x3ff) == 0 \
3508 ? ((v) & ~0x1ff) == 0 \
3511 : ((v) & ~0x7ff) == 0 \
3514 : ((v) & ~0x3fff) == 0 \
3515 ? ((v) & ~0x1fff) == 0 \
3518 : ((v) & ~0x7fff) == 0 \
3521 : ((v) & ~0xffffff) == 0 \
3522 ? ((v) & ~0xfffff) == 0 \
3523 ? ((v) & ~0x3ffff) == 0 \
3524 ? ((v) & ~0x1ffff) == 0 \
3527 : ((v) & ~0x7ffff) == 0 \
3530 : ((v) & ~0x3fffff) == 0 \
3531 ? ((v) & ~0x1fffff) == 0 \
3534 : ((v) & ~0x7fffff) == 0 \
3537 : ((v) & ~0xfffffff) == 0 \
3538 ? ((v) & ~0x3ffffff) == 0 \
3539 ? ((v) & ~0x1ffffff) == 0 \
3542 : ((v) & ~0x7ffffff) == 0 \
3545 : ((v) & ~0x3fffffff) == 0 \
3546 ? ((v) & ~0x1fffffff) == 0 \
3549 : ((v) & ~0x7fffffff) == 0 \
3554 * This routine generates the least number of instructions necessary to load
3555 * an absolute expression value into a register.
3558 load_register (int reg, expressionS *ep, int dbl)
3561 expressionS hi32, lo32;
3563 if (ep->X_op != O_big)
3565 assert (ep->X_op == O_constant);
3567 /* Sign-extending 32-bit constants makes their handling easier. */
3568 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3569 == ~((bfd_vma) 0x7fffffff)))
3571 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3572 as_bad (_("constant too large"));
3574 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3578 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3580 /* We can handle 16 bit signed values with an addiu to
3581 $zero. No need to ever use daddiu here, since $zero and
3582 the result are always correct in 32 bit mode. */
3583 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3586 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3588 /* We can handle 16 bit unsigned values with an ori to
3590 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3593 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3595 /* 32 bit values require an lui. */
3596 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3597 if ((ep->X_add_number & 0xffff) != 0)
3598 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3603 /* The value is larger than 32 bits. */
3605 if (HAVE_32BIT_GPRS)
3607 as_bad (_("Number (0x%lx) larger than 32 bits"),
3608 (unsigned long) ep->X_add_number);
3609 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3613 if (ep->X_op != O_big)
3616 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3617 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3618 hi32.X_add_number &= 0xffffffff;
3620 lo32.X_add_number &= 0xffffffff;
3624 assert (ep->X_add_number > 2);
3625 if (ep->X_add_number == 3)
3626 generic_bignum[3] = 0;
3627 else if (ep->X_add_number > 4)
3628 as_bad (_("Number larger than 64 bits"));
3629 lo32.X_op = O_constant;
3630 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3631 hi32.X_op = O_constant;
3632 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3635 if (hi32.X_add_number == 0)
3640 unsigned long hi, lo;
3642 if (hi32.X_add_number == (offsetT) 0xffffffff)
3644 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3646 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3649 if (lo32.X_add_number & 0x80000000)
3651 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3652 if (lo32.X_add_number & 0xffff)
3653 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3658 /* Check for 16bit shifted constant. We know that hi32 is
3659 non-zero, so start the mask on the first bit of the hi32
3664 unsigned long himask, lomask;
3668 himask = 0xffff >> (32 - shift);
3669 lomask = (0xffff << shift) & 0xffffffff;
3673 himask = 0xffff << (shift - 32);
3676 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3677 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3681 tmp.X_op = O_constant;
3683 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3684 | (lo32.X_add_number >> shift));
3686 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3687 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3688 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3689 reg, reg, (shift >= 32) ? shift - 32 : shift);
3694 while (shift <= (64 - 16));
3696 /* Find the bit number of the lowest one bit, and store the
3697 shifted value in hi/lo. */
3698 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3699 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3703 while ((lo & 1) == 0)
3708 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3714 while ((hi & 1) == 0)
3723 /* Optimize if the shifted value is a (power of 2) - 1. */
3724 if ((hi == 0 && ((lo + 1) & lo) == 0)
3725 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3727 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3732 /* This instruction will set the register to be all
3734 tmp.X_op = O_constant;
3735 tmp.X_add_number = (offsetT) -1;
3736 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3740 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3741 reg, reg, (bit >= 32) ? bit - 32 : bit);
3743 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3744 reg, reg, (shift >= 32) ? shift - 32 : shift);
3749 /* Sign extend hi32 before calling load_register, because we can
3750 generally get better code when we load a sign extended value. */
3751 if ((hi32.X_add_number & 0x80000000) != 0)
3752 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3753 load_register (reg, &hi32, 0);
3756 if ((lo32.X_add_number & 0xffff0000) == 0)
3760 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3768 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3770 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3771 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3777 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3781 mid16.X_add_number >>= 16;
3782 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3783 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3786 if ((lo32.X_add_number & 0xffff) != 0)
3787 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3791 load_delay_nop (void)
3793 if (!gpr_interlocks)
3794 macro_build (NULL, "nop", "");
3797 /* Load an address into a register. */
3800 load_address (int reg, expressionS *ep, int *used_at)
3802 if (ep->X_op != O_constant
3803 && ep->X_op != O_symbol)
3805 as_bad (_("expression too complex"));
3806 ep->X_op = O_constant;
3809 if (ep->X_op == O_constant)
3811 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3815 if (mips_pic == NO_PIC)
3817 /* If this is a reference to a GP relative symbol, we want
3818 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3820 lui $reg,<sym> (BFD_RELOC_HI16_S)
3821 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3822 If we have an addend, we always use the latter form.
3824 With 64bit address space and a usable $at we want
3825 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3826 lui $at,<sym> (BFD_RELOC_HI16_S)
3827 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3828 daddiu $at,<sym> (BFD_RELOC_LO16)
3832 If $at is already in use, we use a path which is suboptimal
3833 on superscalar processors.
3834 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3835 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3837 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3839 daddiu $reg,<sym> (BFD_RELOC_LO16)
3841 if (HAVE_64BIT_ADDRESSES)
3843 /* ??? We don't provide a GP-relative alternative for these macros.
3844 It used not to be possible with the original relaxation code,
3845 but it could be done now. */
3847 if (*used_at == 0 && ! mips_opts.noat)
3849 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3850 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3851 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3852 BFD_RELOC_MIPS_HIGHER);
3853 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3854 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3855 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3860 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3861 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3862 BFD_RELOC_MIPS_HIGHER);
3863 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3864 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3865 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3866 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3871 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3872 && ! nopic_need_relax (ep->X_add_symbol, 1))
3874 relax_start (ep->X_add_symbol);
3875 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3876 mips_gp_register, BFD_RELOC_GPREL16);
3879 macro_build_lui (ep, reg);
3880 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3881 reg, reg, BFD_RELOC_LO16);
3882 if (mips_relax.sequence)
3886 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3890 /* If this is a reference to an external symbol, we want
3891 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3893 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3895 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3896 If there is a constant, it must be added in after.
3898 If we have NewABI, we want
3899 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3900 unless we're referencing a global symbol with a non-zero
3901 offset, in which case cst must be added separately. */
3904 if (ep->X_add_number)
3906 ex.X_add_number = ep->X_add_number;
3907 ep->X_add_number = 0;
3908 relax_start (ep->X_add_symbol);
3909 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3910 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3911 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3912 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3913 ex.X_op = O_constant;
3914 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3915 reg, reg, BFD_RELOC_LO16);
3916 ep->X_add_number = ex.X_add_number;
3919 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3920 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3921 if (mips_relax.sequence)
3926 ex.X_add_number = ep->X_add_number;
3927 ep->X_add_number = 0;
3928 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3929 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3931 relax_start (ep->X_add_symbol);
3933 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3937 if (ex.X_add_number != 0)
3939 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3941 ex.X_op = O_constant;
3942 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3943 reg, reg, BFD_RELOC_LO16);
3947 else if (mips_pic == SVR4_PIC)
3951 /* This is the large GOT case. If this is a reference to an
3952 external symbol, we want
3953 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3955 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3957 Otherwise, for a reference to a local symbol in old ABI, we want
3958 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3960 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3961 If there is a constant, it must be added in after.
3963 In the NewABI, for local symbols, with or without offsets, we want:
3964 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3965 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3969 ex.X_add_number = ep->X_add_number;
3970 ep->X_add_number = 0;
3971 relax_start (ep->X_add_symbol);
3972 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3973 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3974 reg, reg, mips_gp_register);
3975 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3976 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3977 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3978 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3979 else if (ex.X_add_number)
3981 ex.X_op = O_constant;
3982 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3986 ep->X_add_number = ex.X_add_number;
3988 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3989 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3990 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3991 BFD_RELOC_MIPS_GOT_OFST);
3996 ex.X_add_number = ep->X_add_number;
3997 ep->X_add_number = 0;
3998 relax_start (ep->X_add_symbol);
3999 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4000 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4001 reg, reg, mips_gp_register);
4002 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4003 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4005 if (reg_needs_delay (mips_gp_register))
4007 /* We need a nop before loading from $gp. This special
4008 check is required because the lui which starts the main
4009 instruction stream does not refer to $gp, and so will not
4010 insert the nop which may be required. */
4011 macro_build (NULL, "nop", "");
4013 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4014 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4016 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4020 if (ex.X_add_number != 0)
4022 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4023 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4024 ex.X_op = O_constant;
4025 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4034 /* Move the contents of register SOURCE into register DEST. */
4037 move_register (int dest, int source)
4039 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4043 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4044 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4045 The two alternatives are:
4047 Global symbol Local sybmol
4048 ------------- ------------
4049 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4051 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4053 load_got_offset emits the first instruction and add_got_offset
4054 emits the second for a 16-bit offset or add_got_offset_hilo emits
4055 a sequence to add a 32-bit offset using a scratch register. */
4058 load_got_offset (int dest, expressionS *local)
4063 global.X_add_number = 0;
4065 relax_start (local->X_add_symbol);
4066 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4067 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4069 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4070 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4075 add_got_offset (int dest, expressionS *local)
4079 global.X_op = O_constant;
4080 global.X_op_symbol = NULL;
4081 global.X_add_symbol = NULL;
4082 global.X_add_number = local->X_add_number;
4084 relax_start (local->X_add_symbol);
4085 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4086 dest, dest, BFD_RELOC_LO16);
4088 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4093 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4096 int hold_mips_optimize;
4098 global.X_op = O_constant;
4099 global.X_op_symbol = NULL;
4100 global.X_add_symbol = NULL;
4101 global.X_add_number = local->X_add_number;
4103 relax_start (local->X_add_symbol);
4104 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4106 /* Set mips_optimize around the lui instruction to avoid
4107 inserting an unnecessary nop after the lw. */
4108 hold_mips_optimize = mips_optimize;
4110 macro_build_lui (&global, tmp);
4111 mips_optimize = hold_mips_optimize;
4112 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4120 * This routine implements the seemingly endless macro or synthesized
4121 * instructions and addressing modes in the mips assembly language. Many
4122 * of these macros are simple and are similar to each other. These could
4123 * probably be handled by some kind of table or grammar approach instead of
4124 * this verbose method. Others are not simple macros but are more like
4125 * optimizing code generation.
4126 * One interesting optimization is when several store macros appear
4127 * consecutively that would load AT with the upper half of the same address.
4128 * The ensuing load upper instructions are ommited. This implies some kind
4129 * of global optimization. We currently only optimize within a single macro.
4130 * For many of the load and store macros if the address is specified as a
4131 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4132 * first load register 'at' with zero and use it as the base register. The
4133 * mips assembler simply uses register $zero. Just one tiny optimization
4137 macro (struct mips_cl_insn *ip)
4139 register int treg, sreg, dreg, breg;
4155 bfd_reloc_code_real_type r;
4156 int hold_mips_optimize;
4158 assert (! mips_opts.mips16);
4160 treg = (ip->insn_opcode >> 16) & 0x1f;
4161 dreg = (ip->insn_opcode >> 11) & 0x1f;
4162 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4163 mask = ip->insn_mo->mask;
4165 expr1.X_op = O_constant;
4166 expr1.X_op_symbol = NULL;
4167 expr1.X_add_symbol = NULL;
4168 expr1.X_add_number = 1;
4180 mips_emit_delays (TRUE);
4181 ++mips_opts.noreorder;
4182 mips_any_noreorder = 1;
4184 expr1.X_add_number = 8;
4185 macro_build (&expr1, "bgez", "s,p", sreg);
4187 macro_build (NULL, "nop", "", 0);
4189 move_register (dreg, sreg);
4190 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4192 --mips_opts.noreorder;
4213 if (imm_expr.X_op == O_constant
4214 && imm_expr.X_add_number >= -0x8000
4215 && imm_expr.X_add_number < 0x8000)
4217 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4220 load_register (AT, &imm_expr, dbl);
4221 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4240 if (imm_expr.X_op == O_constant
4241 && imm_expr.X_add_number >= 0
4242 && imm_expr.X_add_number < 0x10000)
4244 if (mask != M_NOR_I)
4245 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4248 macro_build (&imm_expr, "ori", "t,r,i",
4249 treg, sreg, BFD_RELOC_LO16);
4250 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4255 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4256 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4273 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4275 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4278 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4279 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4287 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4292 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4295 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4296 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4302 /* check for > max integer */
4303 maxnum = 0x7fffffff;
4304 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4311 if (imm_expr.X_op == O_constant
4312 && imm_expr.X_add_number >= maxnum
4313 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4316 /* result is always false */
4318 macro_build (NULL, "nop", "", 0);
4320 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4323 if (imm_expr.X_op != O_constant)
4324 as_bad (_("Unsupported large constant"));
4325 ++imm_expr.X_add_number;
4329 if (mask == M_BGEL_I)
4331 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4333 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4338 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4341 maxnum = 0x7fffffff;
4342 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4349 maxnum = - maxnum - 1;
4350 if (imm_expr.X_op == O_constant
4351 && imm_expr.X_add_number <= maxnum
4352 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4355 /* result is always true */
4356 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4357 macro_build (&offset_expr, "b", "p");
4361 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4371 macro_build (&offset_expr, likely ? "beql" : "beq",
4375 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4376 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4384 && imm_expr.X_op == O_constant
4385 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4387 if (imm_expr.X_op != O_constant)
4388 as_bad (_("Unsupported large constant"));
4389 ++imm_expr.X_add_number;
4393 if (mask == M_BGEUL_I)
4395 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4397 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4399 macro_build (&offset_expr, likely ? "bnel" : "bne",
4404 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4412 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4417 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4420 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4421 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4429 macro_build (&offset_expr, likely ? "bnel" : "bne",
4435 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4436 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4444 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4449 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4452 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4453 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4459 maxnum = 0x7fffffff;
4460 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4467 if (imm_expr.X_op == O_constant
4468 && imm_expr.X_add_number >= maxnum
4469 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4471 if (imm_expr.X_op != O_constant)
4472 as_bad (_("Unsupported large constant"));
4473 ++imm_expr.X_add_number;
4477 if (mask == M_BLTL_I)
4479 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4481 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4484 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4486 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4490 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4498 macro_build (&offset_expr, likely ? "beql" : "beq",
4504 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4505 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4513 && imm_expr.X_op == O_constant
4514 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4516 if (imm_expr.X_op != O_constant)
4517 as_bad (_("Unsupported large constant"));
4518 ++imm_expr.X_add_number;
4522 if (mask == M_BLTUL_I)
4524 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4526 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4528 macro_build (&offset_expr, likely ? "beql" : "beq",
4533 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4541 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4546 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4549 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4550 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4560 macro_build (&offset_expr, likely ? "bnel" : "bne",
4564 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4565 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4573 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4575 as_bad (_("Unsupported large constant"));
4580 pos = (unsigned long) imm_expr.X_add_number;
4581 size = (unsigned long) imm2_expr.X_add_number;
4586 as_bad (_("Improper position (%lu)"), pos);
4589 if (size == 0 || size > 64
4590 || (pos + size - 1) > 63)
4592 as_bad (_("Improper extract size (%lu, position %lu)"),
4597 if (size <= 32 && pos < 32)
4602 else if (size <= 32)
4612 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4621 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4623 as_bad (_("Unsupported large constant"));
4628 pos = (unsigned long) imm_expr.X_add_number;
4629 size = (unsigned long) imm2_expr.X_add_number;
4634 as_bad (_("Improper position (%lu)"), pos);
4637 if (size == 0 || size > 64
4638 || (pos + size - 1) > 63)
4640 as_bad (_("Improper insert size (%lu, position %lu)"),
4645 if (pos < 32 && (pos + size - 1) < 32)
4660 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4677 as_warn (_("Divide by zero."));
4679 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4681 macro_build (NULL, "break", "c", 7);
4685 mips_emit_delays (TRUE);
4686 ++mips_opts.noreorder;
4687 mips_any_noreorder = 1;
4690 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4691 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4695 expr1.X_add_number = 8;
4696 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4697 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4698 macro_build (NULL, "break", "c", 7);
4700 expr1.X_add_number = -1;
4701 load_register (AT, &expr1, dbl);
4702 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4703 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4706 expr1.X_add_number = 1;
4707 load_register (AT, &expr1, dbl);
4708 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4712 expr1.X_add_number = 0x80000000;
4713 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4717 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4718 /* We want to close the noreorder block as soon as possible, so
4719 that later insns are available for delay slot filling. */
4720 --mips_opts.noreorder;
4724 expr1.X_add_number = 8;
4725 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4726 macro_build (NULL, "nop", "", 0);
4728 /* We want to close the noreorder block as soon as possible, so
4729 that later insns are available for delay slot filling. */
4730 --mips_opts.noreorder;
4732 macro_build (NULL, "break", "c", 6);
4734 macro_build (NULL, s, "d", dreg);
4773 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4775 as_warn (_("Divide by zero."));
4777 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4779 macro_build (NULL, "break", "c", 7);
4782 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4784 if (strcmp (s2, "mflo") == 0)
4785 move_register (dreg, sreg);
4787 move_register (dreg, 0);
4790 if (imm_expr.X_op == O_constant
4791 && imm_expr.X_add_number == -1
4792 && s[strlen (s) - 1] != 'u')
4794 if (strcmp (s2, "mflo") == 0)
4796 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4799 move_register (dreg, 0);
4803 load_register (AT, &imm_expr, dbl);
4804 macro_build (NULL, s, "z,s,t", sreg, AT);
4805 macro_build (NULL, s2, "d", dreg);
4824 mips_emit_delays (TRUE);
4825 ++mips_opts.noreorder;
4826 mips_any_noreorder = 1;
4829 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4830 macro_build (NULL, s, "z,s,t", sreg, treg);
4831 /* We want to close the noreorder block as soon as possible, so
4832 that later insns are available for delay slot filling. */
4833 --mips_opts.noreorder;
4837 expr1.X_add_number = 8;
4838 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4839 macro_build (NULL, s, "z,s,t", sreg, treg);
4841 /* We want to close the noreorder block as soon as possible, so
4842 that later insns are available for delay slot filling. */
4843 --mips_opts.noreorder;
4844 macro_build (NULL, "break", "c", 7);
4846 macro_build (NULL, s2, "d", dreg);
4858 /* Load the address of a symbol into a register. If breg is not
4859 zero, we then add a base register to it. */
4861 if (dbl && HAVE_32BIT_GPRS)
4862 as_warn (_("dla used to load 32-bit register"));
4864 if (! dbl && HAVE_64BIT_OBJECTS)
4865 as_warn (_("la used to load 64-bit address"));
4867 if (offset_expr.X_op == O_constant
4868 && offset_expr.X_add_number >= -0x8000
4869 && offset_expr.X_add_number < 0x8000)
4871 macro_build (&offset_expr,
4872 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4873 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4888 if (offset_expr.X_op != O_symbol
4889 && offset_expr.X_op != O_constant)
4891 as_bad (_("expression too complex"));
4892 offset_expr.X_op = O_constant;
4895 if (offset_expr.X_op == O_constant)
4896 load_register (tempreg, &offset_expr,
4898 ? (dbl || HAVE_64BIT_ADDRESSES)
4899 : HAVE_64BIT_ADDRESSES));
4900 else if (mips_pic == NO_PIC)
4902 /* If this is a reference to a GP relative symbol, we want
4903 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4905 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4906 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4907 If we have a constant, we need two instructions anyhow,
4908 so we may as well always use the latter form.
4910 With 64bit address space and a usable $at we want
4911 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4912 lui $at,<sym> (BFD_RELOC_HI16_S)
4913 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4914 daddiu $at,<sym> (BFD_RELOC_LO16)
4916 daddu $tempreg,$tempreg,$at
4918 If $at is already in use, we use a path which is suboptimal
4919 on superscalar processors.
4920 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4921 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4923 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4925 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4927 if (HAVE_64BIT_ADDRESSES)
4929 /* ??? We don't provide a GP-relative alternative for
4930 these macros. It used not to be possible with the
4931 original relaxation code, but it could be done now. */
4933 if (used_at == 0 && ! mips_opts.noat)
4935 macro_build (&offset_expr, "lui", "t,u",
4936 tempreg, BFD_RELOC_MIPS_HIGHEST);
4937 macro_build (&offset_expr, "lui", "t,u",
4938 AT, BFD_RELOC_HI16_S);
4939 macro_build (&offset_expr, "daddiu", "t,r,j",
4940 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4941 macro_build (&offset_expr, "daddiu", "t,r,j",
4942 AT, AT, BFD_RELOC_LO16);
4943 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4944 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4949 macro_build (&offset_expr, "lui", "t,u",
4950 tempreg, BFD_RELOC_MIPS_HIGHEST);
4951 macro_build (&offset_expr, "daddiu", "t,r,j",
4952 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4953 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4954 macro_build (&offset_expr, "daddiu", "t,r,j",
4955 tempreg, tempreg, BFD_RELOC_HI16_S);
4956 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4957 macro_build (&offset_expr, "daddiu", "t,r,j",
4958 tempreg, tempreg, BFD_RELOC_LO16);
4963 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4964 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4966 relax_start (offset_expr.X_add_symbol);
4967 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4968 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4971 macro_build_lui (&offset_expr, tempreg);
4972 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4973 tempreg, tempreg, BFD_RELOC_LO16);
4974 if (mips_relax.sequence)
4978 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4980 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4982 /* If this is a reference to an external symbol, and there
4983 is no constant, we want
4984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4985 or for lca or if tempreg is PIC_CALL_REG
4986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4987 For a local symbol, we want
4988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4990 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4992 If we have a small constant, and this is a reference to
4993 an external symbol, we want
4994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4996 addiu $tempreg,$tempreg,<constant>
4997 For a local symbol, we want the same instruction
4998 sequence, but we output a BFD_RELOC_LO16 reloc on the
5001 If we have a large constant, and this is a reference to
5002 an external symbol, we want
5003 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 lui $at,<hiconstant>
5005 addiu $at,$at,<loconstant>
5006 addu $tempreg,$tempreg,$at
5007 For a local symbol, we want the same instruction
5008 sequence, but we output a BFD_RELOC_LO16 reloc on the
5012 if (offset_expr.X_add_number == 0)
5014 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5015 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5017 relax_start (offset_expr.X_add_symbol);
5018 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5019 lw_reloc_type, mips_gp_register);
5022 /* We're going to put in an addu instruction using
5023 tempreg, so we may as well insert the nop right
5028 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5029 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5031 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5032 tempreg, tempreg, BFD_RELOC_LO16);
5034 /* FIXME: If breg == 0, and the next instruction uses
5035 $tempreg, then if this variant case is used an extra
5036 nop will be generated. */
5038 else if (offset_expr.X_add_number >= -0x8000
5039 && offset_expr.X_add_number < 0x8000)
5041 load_got_offset (tempreg, &offset_expr);
5043 add_got_offset (tempreg, &offset_expr);
5047 expr1.X_add_number = offset_expr.X_add_number;
5048 offset_expr.X_add_number =
5049 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5050 load_got_offset (tempreg, &offset_expr);
5051 offset_expr.X_add_number = expr1.X_add_number;
5052 /* If we are going to add in a base register, and the
5053 target register and the base register are the same,
5054 then we are using AT as a temporary register. Since
5055 we want to load the constant into AT, we add our
5056 current AT (from the global offset table) and the
5057 register into the register now, and pretend we were
5058 not using a base register. */
5062 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5067 add_got_offset_hilo (tempreg, &offset_expr, AT);
5071 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5073 int add_breg_early = 0;
5075 /* If this is a reference to an external, and there is no
5076 constant, or local symbol (*), with or without a
5078 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5079 or for lca or if tempreg is PIC_CALL_REG
5080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5082 If we have a small constant, and this is a reference to
5083 an external symbol, we want
5084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5085 addiu $tempreg,$tempreg,<constant>
5087 If we have a large constant, and this is a reference to
5088 an external symbol, we want
5089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5090 lui $at,<hiconstant>
5091 addiu $at,$at,<loconstant>
5092 addu $tempreg,$tempreg,$at
5094 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5095 local symbols, even though it introduces an additional
5098 if (offset_expr.X_add_number)
5100 expr1.X_add_number = offset_expr.X_add_number;
5101 offset_expr.X_add_number = 0;
5103 relax_start (offset_expr.X_add_symbol);
5104 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5105 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5107 if (expr1.X_add_number >= -0x8000
5108 && expr1.X_add_number < 0x8000)
5110 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5111 tempreg, tempreg, BFD_RELOC_LO16);
5113 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5117 /* If we are going to add in a base register, and the
5118 target register and the base register are the same,
5119 then we are using AT as a temporary register. Since
5120 we want to load the constant into AT, we add our
5121 current AT (from the global offset table) and the
5122 register into the register now, and pretend we were
5123 not using a base register. */
5128 assert (tempreg == AT);
5129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5135 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5136 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5142 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5145 offset_expr.X_add_number = expr1.X_add_number;
5147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5148 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5151 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5152 treg, tempreg, breg);
5158 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5160 relax_start (offset_expr.X_add_symbol);
5161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5162 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5164 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5165 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5171 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5174 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5177 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5178 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5179 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5181 /* This is the large GOT case. If this is a reference to an
5182 external symbol, and there is no constant, we want
5183 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5184 addu $tempreg,$tempreg,$gp
5185 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5186 or for lca or if tempreg is PIC_CALL_REG
5187 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5188 addu $tempreg,$tempreg,$gp
5189 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5190 For a local symbol, we want
5191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5193 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5195 If we have a small constant, and this is a reference to
5196 an external symbol, we want
5197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5198 addu $tempreg,$tempreg,$gp
5199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5201 addiu $tempreg,$tempreg,<constant>
5202 For a local symbol, we want
5203 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5205 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5207 If we have a large constant, and this is a reference to
5208 an external symbol, we want
5209 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5210 addu $tempreg,$tempreg,$gp
5211 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5212 lui $at,<hiconstant>
5213 addiu $at,$at,<loconstant>
5214 addu $tempreg,$tempreg,$at
5215 For a local symbol, we want
5216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5217 lui $at,<hiconstant>
5218 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5219 addu $tempreg,$tempreg,$at
5222 expr1.X_add_number = offset_expr.X_add_number;
5223 offset_expr.X_add_number = 0;
5224 relax_start (offset_expr.X_add_symbol);
5225 gpdelay = reg_needs_delay (mips_gp_register);
5226 if (expr1.X_add_number == 0 && breg == 0
5227 && (call || tempreg == PIC_CALL_REG))
5229 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5230 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5232 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5233 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5234 tempreg, tempreg, mips_gp_register);
5235 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5236 tempreg, lw_reloc_type, tempreg);
5237 if (expr1.X_add_number == 0)
5241 /* We're going to put in an addu instruction using
5242 tempreg, so we may as well insert the nop right
5247 else if (expr1.X_add_number >= -0x8000
5248 && expr1.X_add_number < 0x8000)
5251 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5252 tempreg, tempreg, BFD_RELOC_LO16);
5258 /* If we are going to add in a base register, and the
5259 target register and the base register are the same,
5260 then we are using AT as a temporary register. Since
5261 we want to load the constant into AT, we add our
5262 current AT (from the global offset table) and the
5263 register into the register now, and pretend we were
5264 not using a base register. */
5269 assert (tempreg == AT);
5271 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5276 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5277 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5281 offset_expr.X_add_number =
5282 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5287 /* This is needed because this instruction uses $gp, but
5288 the first instruction on the main stream does not. */
5289 macro_build (NULL, "nop", "");
5292 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5293 local_reloc_type, mips_gp_register);
5294 if (expr1.X_add_number >= -0x8000
5295 && expr1.X_add_number < 0x8000)
5298 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5299 tempreg, tempreg, BFD_RELOC_LO16);
5300 /* FIXME: If add_number is 0, and there was no base
5301 register, the external symbol case ended with a load,
5302 so if the symbol turns out to not be external, and
5303 the next instruction uses tempreg, an unnecessary nop
5304 will be inserted. */
5310 /* We must add in the base register now, as in the
5311 external symbol case. */
5312 assert (tempreg == AT);
5314 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5317 /* We set breg to 0 because we have arranged to add
5318 it in in both cases. */
5322 macro_build_lui (&expr1, AT);
5323 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5324 AT, AT, BFD_RELOC_LO16);
5325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5326 tempreg, tempreg, AT);
5330 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5332 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5333 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5334 int add_breg_early = 0;
5336 /* This is the large GOT case. If this is a reference to an
5337 external symbol, and there is no constant, we want
5338 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5339 add $tempreg,$tempreg,$gp
5340 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5341 or for lca or if tempreg is PIC_CALL_REG
5342 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5343 add $tempreg,$tempreg,$gp
5344 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5346 If we have a small constant, and this is a reference to
5347 an external symbol, we want
5348 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5349 add $tempreg,$tempreg,$gp
5350 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5351 addi $tempreg,$tempreg,<constant>
5353 If we have a large constant, and this is a reference to
5354 an external symbol, we want
5355 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5356 addu $tempreg,$tempreg,$gp
5357 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5358 lui $at,<hiconstant>
5359 addi $at,$at,<loconstant>
5360 add $tempreg,$tempreg,$at
5362 If we have NewABI, and we know it's a local symbol, we want
5363 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5364 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5365 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5367 relax_start (offset_expr.X_add_symbol);
5369 expr1.X_add_number = offset_expr.X_add_number;
5370 offset_expr.X_add_number = 0;
5372 if (expr1.X_add_number == 0 && breg == 0
5373 && (call || tempreg == PIC_CALL_REG))
5375 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5376 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5378 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5379 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5380 tempreg, tempreg, mips_gp_register);
5381 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5382 tempreg, lw_reloc_type, tempreg);
5384 if (expr1.X_add_number == 0)
5386 else if (expr1.X_add_number >= -0x8000
5387 && expr1.X_add_number < 0x8000)
5389 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5390 tempreg, tempreg, BFD_RELOC_LO16);
5392 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5396 /* If we are going to add in a base register, and the
5397 target register and the base register are the same,
5398 then we are using AT as a temporary register. Since
5399 we want to load the constant into AT, we add our
5400 current AT (from the global offset table) and the
5401 register into the register now, and pretend we were
5402 not using a base register. */
5407 assert (tempreg == AT);
5408 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5414 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5415 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5420 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5423 offset_expr.X_add_number = expr1.X_add_number;
5424 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5425 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5426 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5427 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5430 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5431 treg, tempreg, breg);
5444 if (mips_pic == NO_PIC)
5445 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5447 s = ADDRESS_ADD_INSN;
5449 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5458 /* The j instruction may not be used in PIC code, since it
5459 requires an absolute address. We convert it to a b
5461 if (mips_pic == NO_PIC)
5462 macro_build (&offset_expr, "j", "a");
5464 macro_build (&offset_expr, "b", "p");
5467 /* The jal instructions must be handled as macros because when
5468 generating PIC code they expand to multi-instruction
5469 sequences. Normally they are simple instructions. */
5474 if (mips_pic == NO_PIC)
5475 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5476 else if (mips_pic == SVR4_PIC)
5478 if (sreg != PIC_CALL_REG)
5479 as_warn (_("MIPS PIC call to register other than $25"));
5481 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5484 if (mips_cprestore_offset < 0)
5485 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5488 if (! mips_frame_reg_valid)
5490 as_warn (_("No .frame pseudo-op used in PIC code"));
5491 /* Quiet this warning. */
5492 mips_frame_reg_valid = 1;
5494 if (! mips_cprestore_valid)
5496 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5497 /* Quiet this warning. */
5498 mips_cprestore_valid = 1;
5500 expr1.X_add_number = mips_cprestore_offset;
5501 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5504 HAVE_64BIT_ADDRESSES);
5514 if (mips_pic == NO_PIC)
5515 macro_build (&offset_expr, "jal", "a");
5516 else if (mips_pic == SVR4_PIC)
5518 /* If this is a reference to an external symbol, and we are
5519 using a small GOT, we want
5520 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5524 lw $gp,cprestore($sp)
5525 The cprestore value is set using the .cprestore
5526 pseudo-op. If we are using a big GOT, we want
5527 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5529 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5533 lw $gp,cprestore($sp)
5534 If the symbol is not external, we want
5535 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5537 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5540 lw $gp,cprestore($sp)
5542 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5543 sequences above, minus nops, unless the symbol is local,
5544 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5550 relax_start (offset_expr.X_add_symbol);
5551 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5552 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5555 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5556 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5562 relax_start (offset_expr.X_add_symbol);
5563 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5564 BFD_RELOC_MIPS_CALL_HI16);
5565 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5566 PIC_CALL_REG, mips_gp_register);
5567 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5568 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5571 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5572 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5574 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5575 PIC_CALL_REG, PIC_CALL_REG,
5576 BFD_RELOC_MIPS_GOT_OFST);
5580 macro_build_jalr (&offset_expr);
5584 relax_start (offset_expr.X_add_symbol);
5587 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5588 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5597 gpdelay = reg_needs_delay (mips_gp_register);
5598 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5599 BFD_RELOC_MIPS_CALL_HI16);
5600 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5601 PIC_CALL_REG, mips_gp_register);
5602 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5603 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5608 macro_build (NULL, "nop", "");
5610 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5611 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5614 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5615 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5617 macro_build_jalr (&offset_expr);
5619 if (mips_cprestore_offset < 0)
5620 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5623 if (! mips_frame_reg_valid)
5625 as_warn (_("No .frame pseudo-op used in PIC code"));
5626 /* Quiet this warning. */
5627 mips_frame_reg_valid = 1;
5629 if (! mips_cprestore_valid)
5631 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5632 /* Quiet this warning. */
5633 mips_cprestore_valid = 1;
5635 if (mips_opts.noreorder)
5636 macro_build (NULL, "nop", "");
5637 expr1.X_add_number = mips_cprestore_offset;
5638 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5641 HAVE_64BIT_ADDRESSES);
5667 /* Itbl support may require additional care here. */
5672 /* Itbl support may require additional care here. */
5677 /* Itbl support may require additional care here. */
5682 /* Itbl support may require additional care here. */
5694 if (mips_opts.arch == CPU_R4650)
5696 as_bad (_("opcode not supported on this processor"));
5700 /* Itbl support may require additional care here. */
5705 /* Itbl support may require additional care here. */
5710 /* Itbl support may require additional care here. */
5730 if (breg == treg || coproc || lr)
5752 /* Itbl support may require additional care here. */
5757 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5783 if (mips_opts.arch == CPU_R4650)
5785 as_bad (_("opcode not supported on this processor"));
5790 /* Itbl support may require additional care here. */
5794 /* Itbl support may require additional care here. */
5799 /* Itbl support may require additional care here. */
5811 /* Itbl support may require additional care here. */
5812 if (mask == M_LWC1_AB
5813 || mask == M_SWC1_AB
5814 || mask == M_LDC1_AB
5815 || mask == M_SDC1_AB
5824 /* Sign-extending 32-bit constants makes their handling easier.
5825 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5827 if ((! HAVE_64BIT_ADDRESSES
5828 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5829 && (offset_expr.X_op == O_constant)
5830 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5831 == ~((bfd_vma) 0x7fffffff)))
5833 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5834 as_bad (_("constant too large"));
5836 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5837 ^ 0x80000000) - 0x80000000);
5840 if (offset_expr.X_op != O_constant
5841 && offset_expr.X_op != O_symbol)
5843 as_bad (_("expression too complex"));
5844 offset_expr.X_op = O_constant;
5847 /* A constant expression in PIC code can be handled just as it
5848 is in non PIC code. */
5849 if (mips_pic == NO_PIC
5850 || offset_expr.X_op == O_constant)
5852 /* If this is a reference to a GP relative symbol, and there
5853 is no base register, we want
5854 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5855 Otherwise, if there is no base register, we want
5856 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5857 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5858 If we have a constant, we need two instructions anyhow,
5859 so we always use the latter form.
5861 If we have a base register, and this is a reference to a
5862 GP relative symbol, we want
5863 addu $tempreg,$breg,$gp
5864 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5866 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5867 addu $tempreg,$tempreg,$breg
5868 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5869 With a constant we always use the latter case.
5871 With 64bit address space and no base register and $at usable,
5873 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5874 lui $at,<sym> (BFD_RELOC_HI16_S)
5875 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5878 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5879 If we have a base register, we want
5880 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5881 lui $at,<sym> (BFD_RELOC_HI16_S)
5882 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5886 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5888 Without $at we can't generate the optimal path for superscalar
5889 processors here since this would require two temporary registers.
5890 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5891 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5893 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5895 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5896 If we have a base register, we want
5897 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5898 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5900 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5902 daddu $tempreg,$tempreg,$breg
5903 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5905 If we have 64-bit addresses, as an optimization, for
5906 addresses which are 32-bit constants (e.g. kseg0/kseg1
5907 addresses) we fall back to the 32-bit address generation
5908 mechanism since it is more efficient. Note that due to
5909 the signed offset used by memory operations, the 32-bit
5910 range is shifted down by 32768 here. This code should
5911 probably attempt to generate 64-bit constants more
5912 efficiently in general.
5914 As an extension for architectures with 64-bit registers,
5915 we don't truncate 64-bit addresses given as literal
5916 constants down to 32 bits, to support existing practice
5917 in the mips64 Linux (the kernel), that compiles source
5918 files with -mabi=64, assembling them as o32 or n32 (with
5919 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5920 the whole kernel is loaded into a memory region that is
5921 addressable with sign-extended 32-bit addresses, it is
5922 wasteful to compute the upper 32 bits of every
5923 non-literal address, that takes more space and time.
5924 Some day this should probably be implemented as an
5925 assembler option, such that the kernel doesn't have to
5926 use such ugly hacks, even though it will still have to
5927 end up converting the binary to ELF32 for a number of
5928 platforms whose boot loaders don't support ELF64
5930 if ((HAVE_64BIT_ADDRESSES
5931 && ! (offset_expr.X_op == O_constant
5932 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5934 && offset_expr.X_op == O_constant
5935 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5937 /* ??? We don't provide a GP-relative alternative for
5938 these macros. It used not to be possible with the
5939 original relaxation code, but it could be done now. */
5941 if (used_at == 0 && ! mips_opts.noat)
5943 macro_build (&offset_expr, "lui", "t,u", tempreg,
5944 BFD_RELOC_MIPS_HIGHEST);
5945 macro_build (&offset_expr, "lui", "t,u", AT,
5947 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5948 tempreg, BFD_RELOC_MIPS_HIGHER);
5950 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
5951 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5952 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5953 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
5959 macro_build (&offset_expr, "lui", "t,u", tempreg,
5960 BFD_RELOC_MIPS_HIGHEST);
5961 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5962 tempreg, BFD_RELOC_MIPS_HIGHER);
5963 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5964 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
5965 tempreg, BFD_RELOC_HI16_S);
5966 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5968 macro_build (NULL, "daddu", "d,v,t",
5969 tempreg, tempreg, breg);
5970 macro_build (&offset_expr, s, fmt, treg,
5971 BFD_RELOC_LO16, tempreg);
5977 if (offset_expr.X_op == O_constant
5978 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
5979 as_bad (_("load/store address overflow (max 32 bits)"));
5983 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5984 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5986 relax_start (offset_expr.X_add_symbol);
5987 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
5992 macro_build_lui (&offset_expr, tempreg);
5993 macro_build (&offset_expr, s, fmt, treg,
5994 BFD_RELOC_LO16, tempreg);
5995 if (mips_relax.sequence)
6000 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6001 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6003 relax_start (offset_expr.X_add_symbol);
6004 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6005 tempreg, breg, mips_gp_register);
6006 macro_build (&offset_expr, s, fmt, treg,
6007 BFD_RELOC_GPREL16, tempreg);
6010 macro_build_lui (&offset_expr, tempreg);
6011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6012 tempreg, tempreg, breg);
6013 macro_build (&offset_expr, s, fmt, treg,
6014 BFD_RELOC_LO16, tempreg);
6015 if (mips_relax.sequence)
6019 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6021 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6023 /* If this is a reference to an external symbol, we want
6024 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6026 <op> $treg,0($tempreg)
6028 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6030 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6031 <op> $treg,0($tempreg)
6034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6035 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6037 If there is a base register, we add it to $tempreg before
6038 the <op>. If there is a constant, we stick it in the
6039 <op> instruction. We don't handle constants larger than
6040 16 bits, because we have no way to load the upper 16 bits
6041 (actually, we could handle them for the subset of cases
6042 in which we are not using $at). */
6043 assert (offset_expr.X_op == O_symbol);
6046 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6047 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6050 tempreg, tempreg, breg);
6051 macro_build (&offset_expr, s, fmt, treg,
6052 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6059 expr1.X_add_number = offset_expr.X_add_number;
6060 offset_expr.X_add_number = 0;
6061 if (expr1.X_add_number < -0x8000
6062 || expr1.X_add_number >= 0x8000)
6063 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6064 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6065 lw_reloc_type, mips_gp_register);
6067 relax_start (offset_expr.X_add_symbol);
6069 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6070 tempreg, BFD_RELOC_LO16);
6073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6074 tempreg, tempreg, breg);
6075 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6077 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6081 /* If this is a reference to an external symbol, we want
6082 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6083 addu $tempreg,$tempreg,$gp
6084 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6085 <op> $treg,0($tempreg)
6087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6089 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6090 <op> $treg,0($tempreg)
6091 If there is a base register, we add it to $tempreg before
6092 the <op>. If there is a constant, we stick it in the
6093 <op> instruction. We don't handle constants larger than
6094 16 bits, because we have no way to load the upper 16 bits
6095 (actually, we could handle them for the subset of cases
6096 in which we are not using $at). */
6097 assert (offset_expr.X_op == O_symbol);
6098 expr1.X_add_number = offset_expr.X_add_number;
6099 offset_expr.X_add_number = 0;
6100 if (expr1.X_add_number < -0x8000
6101 || expr1.X_add_number >= 0x8000)
6102 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6103 gpdelay = reg_needs_delay (mips_gp_register);
6104 relax_start (offset_expr.X_add_symbol);
6105 macro_build (&offset_expr, "lui", "t,u", tempreg,
6106 BFD_RELOC_MIPS_GOT_HI16);
6107 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6109 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6110 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6113 macro_build (NULL, "nop", "");
6114 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6115 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6117 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6118 tempreg, BFD_RELOC_LO16);
6122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6123 tempreg, tempreg, breg);
6124 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6126 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6128 /* If this is a reference to an external symbol, we want
6129 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6130 add $tempreg,$tempreg,$gp
6131 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6132 <op> $treg,<ofst>($tempreg)
6133 Otherwise, for local symbols, we want:
6134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6135 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6136 assert (offset_expr.X_op == O_symbol);
6137 expr1.X_add_number = offset_expr.X_add_number;
6138 offset_expr.X_add_number = 0;
6139 if (expr1.X_add_number < -0x8000
6140 || expr1.X_add_number >= 0x8000)
6141 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6142 relax_start (offset_expr.X_add_symbol);
6143 macro_build (&offset_expr, "lui", "t,u", tempreg,
6144 BFD_RELOC_MIPS_GOT_HI16);
6145 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6148 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6151 tempreg, tempreg, breg);
6152 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6155 offset_expr.X_add_number = expr1.X_add_number;
6156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6157 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6159 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6160 tempreg, tempreg, breg);
6161 macro_build (&offset_expr, s, fmt, treg,
6162 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6175 load_register (treg, &imm_expr, 0);
6179 load_register (treg, &imm_expr, 1);
6183 if (imm_expr.X_op == O_constant)
6185 load_register (AT, &imm_expr, 0);
6186 macro_build (NULL, "mtc1", "t,G", AT, treg);
6191 assert (offset_expr.X_op == O_symbol
6192 && strcmp (segment_name (S_GET_SEGMENT
6193 (offset_expr.X_add_symbol)),
6195 && offset_expr.X_add_number == 0);
6196 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6197 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6202 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6203 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6204 order 32 bits of the value and the low order 32 bits are either
6205 zero or in OFFSET_EXPR. */
6206 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6208 if (HAVE_64BIT_GPRS)
6209 load_register (treg, &imm_expr, 1);
6214 if (target_big_endian)
6226 load_register (hreg, &imm_expr, 0);
6229 if (offset_expr.X_op == O_absent)
6230 move_register (lreg, 0);
6233 assert (offset_expr.X_op == O_constant);
6234 load_register (lreg, &offset_expr, 0);
6241 /* We know that sym is in the .rdata section. First we get the
6242 upper 16 bits of the address. */
6243 if (mips_pic == NO_PIC)
6245 macro_build_lui (&offset_expr, AT);
6247 else if (mips_pic == SVR4_PIC)
6249 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6250 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6255 /* Now we load the register(s). */
6256 if (HAVE_64BIT_GPRS)
6257 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6260 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6263 /* FIXME: How in the world do we deal with the possible
6265 offset_expr.X_add_number += 4;
6266 macro_build (&offset_expr, "lw", "t,o(b)",
6267 treg + 1, BFD_RELOC_LO16, AT);
6273 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6274 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6275 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6276 the value and the low order 32 bits are either zero or in
6278 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6280 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6281 if (HAVE_64BIT_FPRS)
6283 assert (HAVE_64BIT_GPRS);
6284 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6288 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6289 if (offset_expr.X_op == O_absent)
6290 macro_build (NULL, "mtc1", "t,G", 0, treg);
6293 assert (offset_expr.X_op == O_constant);
6294 load_register (AT, &offset_expr, 0);
6295 macro_build (NULL, "mtc1", "t,G", AT, treg);
6301 assert (offset_expr.X_op == O_symbol
6302 && offset_expr.X_add_number == 0);
6303 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6304 if (strcmp (s, ".lit8") == 0)
6306 if (mips_opts.isa != ISA_MIPS1)
6308 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6309 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6312 breg = mips_gp_register;
6313 r = BFD_RELOC_MIPS_LITERAL;
6318 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6319 if (mips_pic == SVR4_PIC)
6320 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6321 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6324 /* FIXME: This won't work for a 64 bit address. */
6325 macro_build_lui (&offset_expr, AT);
6328 if (mips_opts.isa != ISA_MIPS1)
6330 macro_build (&offset_expr, "ldc1", "T,o(b)",
6331 treg, BFD_RELOC_LO16, AT);
6340 if (mips_opts.arch == CPU_R4650)
6342 as_bad (_("opcode not supported on this processor"));
6345 /* Even on a big endian machine $fn comes before $fn+1. We have
6346 to adjust when loading from memory. */
6349 assert (mips_opts.isa == ISA_MIPS1);
6350 macro_build (&offset_expr, "lwc1", "T,o(b)",
6351 target_big_endian ? treg + 1 : treg, r, breg);
6352 /* FIXME: A possible overflow which I don't know how to deal
6354 offset_expr.X_add_number += 4;
6355 macro_build (&offset_expr, "lwc1", "T,o(b)",
6356 target_big_endian ? treg : treg + 1, r, breg);
6364 * The MIPS assembler seems to check for X_add_number not
6365 * being double aligned and generating:
6368 * addiu at,at,%lo(foo+1)
6371 * But, the resulting address is the same after relocation so why
6372 * generate the extra instruction?
6374 if (mips_opts.arch == CPU_R4650)
6376 as_bad (_("opcode not supported on this processor"));
6379 /* Itbl support may require additional care here. */
6381 if (mips_opts.isa != ISA_MIPS1)
6392 if (mips_opts.arch == CPU_R4650)
6394 as_bad (_("opcode not supported on this processor"));
6398 if (mips_opts.isa != ISA_MIPS1)
6406 /* Itbl support may require additional care here. */
6411 if (HAVE_64BIT_GPRS)
6422 if (HAVE_64BIT_GPRS)
6432 if (offset_expr.X_op != O_symbol
6433 && offset_expr.X_op != O_constant)
6435 as_bad (_("expression too complex"));
6436 offset_expr.X_op = O_constant;
6439 /* Even on a big endian machine $fn comes before $fn+1. We have
6440 to adjust when loading from memory. We set coproc if we must
6441 load $fn+1 first. */
6442 /* Itbl support may require additional care here. */
6443 if (! target_big_endian)
6446 if (mips_pic == NO_PIC
6447 || offset_expr.X_op == O_constant)
6449 /* If this is a reference to a GP relative symbol, we want
6450 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6451 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6452 If we have a base register, we use this
6454 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6455 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6456 If this is not a GP relative symbol, we want
6457 lui $at,<sym> (BFD_RELOC_HI16_S)
6458 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6459 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6460 If there is a base register, we add it to $at after the
6461 lui instruction. If there is a constant, we always use
6463 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6464 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6468 relax_start (offset_expr.X_add_symbol);
6471 tempreg = mips_gp_register;
6476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6477 AT, breg, mips_gp_register);
6482 /* Itbl support may require additional care here. */
6483 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6484 BFD_RELOC_GPREL16, tempreg);
6485 offset_expr.X_add_number += 4;
6487 /* Set mips_optimize to 2 to avoid inserting an
6489 hold_mips_optimize = mips_optimize;
6491 /* Itbl support may require additional care here. */
6492 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6493 BFD_RELOC_GPREL16, tempreg);
6494 mips_optimize = hold_mips_optimize;
6498 /* We just generated two relocs. When tc_gen_reloc
6499 handles this case, it will skip the first reloc and
6500 handle the second. The second reloc already has an
6501 extra addend of 4, which we added above. We must
6502 subtract it out, and then subtract another 4 to make
6503 the first reloc come out right. The second reloc
6504 will come out right because we are going to add 4 to
6505 offset_expr when we build its instruction below.
6507 If we have a symbol, then we don't want to include
6508 the offset, because it will wind up being included
6509 when we generate the reloc. */
6511 if (offset_expr.X_op == O_constant)
6512 offset_expr.X_add_number -= 8;
6515 offset_expr.X_add_number = -4;
6516 offset_expr.X_op = O_constant;
6519 macro_build_lui (&offset_expr, AT);
6521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6522 /* Itbl support may require additional care here. */
6523 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6524 BFD_RELOC_LO16, AT);
6525 /* FIXME: How do we handle overflow here? */
6526 offset_expr.X_add_number += 4;
6527 /* Itbl support may require additional care here. */
6528 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6529 BFD_RELOC_LO16, AT);
6530 if (mips_relax.sequence)
6533 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6535 /* If this is a reference to an external symbol, we want
6536 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6541 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6543 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6544 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6545 If there is a base register we add it to $at before the
6546 lwc1 instructions. If there is a constant we include it
6547 in the lwc1 instructions. */
6549 expr1.X_add_number = offset_expr.X_add_number;
6550 if (expr1.X_add_number < -0x8000
6551 || expr1.X_add_number >= 0x8000 - 4)
6552 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6553 load_got_offset (AT, &offset_expr);
6556 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6558 /* Set mips_optimize to 2 to avoid inserting an undesired
6560 hold_mips_optimize = mips_optimize;
6563 /* Itbl support may require additional care here. */
6564 relax_start (offset_expr.X_add_symbol);
6565 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6566 BFD_RELOC_LO16, AT);
6567 expr1.X_add_number += 4;
6568 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6569 BFD_RELOC_LO16, AT);
6571 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6572 BFD_RELOC_LO16, AT);
6573 offset_expr.X_add_number += 4;
6574 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6575 BFD_RELOC_LO16, AT);
6578 mips_optimize = hold_mips_optimize;
6580 else if (mips_pic == SVR4_PIC)
6584 /* If this is a reference to an external symbol, we want
6585 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6587 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6592 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6594 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6595 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6596 If there is a base register we add it to $at before the
6597 lwc1 instructions. If there is a constant we include it
6598 in the lwc1 instructions. */
6600 expr1.X_add_number = offset_expr.X_add_number;
6601 offset_expr.X_add_number = 0;
6602 if (expr1.X_add_number < -0x8000
6603 || expr1.X_add_number >= 0x8000 - 4)
6604 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6605 gpdelay = reg_needs_delay (mips_gp_register);
6606 relax_start (offset_expr.X_add_symbol);
6607 macro_build (&offset_expr, "lui", "t,u",
6608 AT, BFD_RELOC_MIPS_GOT_HI16);
6609 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6610 AT, AT, mips_gp_register);
6611 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6612 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6615 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6616 /* Itbl support may require additional care here. */
6617 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6618 BFD_RELOC_LO16, AT);
6619 expr1.X_add_number += 4;
6621 /* Set mips_optimize to 2 to avoid inserting an undesired
6623 hold_mips_optimize = mips_optimize;
6625 /* Itbl support may require additional care here. */
6626 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6627 BFD_RELOC_LO16, AT);
6628 mips_optimize = hold_mips_optimize;
6629 expr1.X_add_number -= 4;
6632 offset_expr.X_add_number = expr1.X_add_number;
6634 macro_build (NULL, "nop", "");
6635 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6636 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6639 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6640 /* Itbl support may require additional care here. */
6641 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6642 BFD_RELOC_LO16, AT);
6643 offset_expr.X_add_number += 4;
6645 /* Set mips_optimize to 2 to avoid inserting an undesired
6647 hold_mips_optimize = mips_optimize;
6649 /* Itbl support may require additional care here. */
6650 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6651 BFD_RELOC_LO16, AT);
6652 mips_optimize = hold_mips_optimize;
6669 assert (HAVE_32BIT_ADDRESSES);
6670 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6671 offset_expr.X_add_number += 4;
6672 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6675 /* New code added to support COPZ instructions.
6676 This code builds table entries out of the macros in mip_opcodes.
6677 R4000 uses interlocks to handle coproc delays.
6678 Other chips (like the R3000) require nops to be inserted for delays.
6680 FIXME: Currently, we require that the user handle delays.
6681 In order to fill delay slots for non-interlocked chips,
6682 we must have a way to specify delays based on the coprocessor.
6683 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6684 What are the side-effects of the cop instruction?
6685 What cache support might we have and what are its effects?
6686 Both coprocessor & memory require delays. how long???
6687 What registers are read/set/modified?
6689 If an itbl is provided to interpret cop instructions,
6690 this knowledge can be encoded in the itbl spec. */
6704 /* For now we just do C (same as Cz). The parameter will be
6705 stored in insn_opcode by mips_ip. */
6706 macro_build (NULL, s, "C", ip->insn_opcode);
6710 move_register (dreg, sreg);
6713 #ifdef LOSING_COMPILER
6715 /* Try and see if this is a new itbl instruction.
6716 This code builds table entries out of the macros in mip_opcodes.
6717 FIXME: For now we just assemble the expression and pass it's
6718 value along as a 32-bit immediate.
6719 We may want to have the assembler assemble this value,
6720 so that we gain the assembler's knowledge of delay slots,
6722 Would it be more efficient to use mask (id) here? */
6723 if (itbl_have_entries
6724 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6726 s = ip->insn_mo->name;
6728 coproc = ITBL_DECODE_PNUM (immed_expr);;
6729 macro_build (&immed_expr, s, "C");
6736 as_warn (_("Macro used $at after \".set noat\""));
6740 macro2 (struct mips_cl_insn *ip)
6742 register int treg, sreg, dreg, breg;
6757 bfd_reloc_code_real_type r;
6759 treg = (ip->insn_opcode >> 16) & 0x1f;
6760 dreg = (ip->insn_opcode >> 11) & 0x1f;
6761 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6762 mask = ip->insn_mo->mask;
6764 expr1.X_op = O_constant;
6765 expr1.X_op_symbol = NULL;
6766 expr1.X_add_symbol = NULL;
6767 expr1.X_add_number = 1;
6771 #endif /* LOSING_COMPILER */
6776 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6777 macro_build (NULL, "mflo", "d", dreg);
6783 /* The MIPS assembler some times generates shifts and adds. I'm
6784 not trying to be that fancy. GCC should do this for us
6786 load_register (AT, &imm_expr, dbl);
6787 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6788 macro_build (NULL, "mflo", "d", dreg);
6801 mips_emit_delays (TRUE);
6802 ++mips_opts.noreorder;
6803 mips_any_noreorder = 1;
6805 load_register (AT, &imm_expr, dbl);
6806 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6807 macro_build (NULL, "mflo", "d", dreg);
6808 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6809 macro_build (NULL, "mfhi", "d", AT);
6811 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6814 expr1.X_add_number = 8;
6815 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6816 macro_build (NULL, "nop", "", 0);
6817 macro_build (NULL, "break", "c", 6);
6819 --mips_opts.noreorder;
6820 macro_build (NULL, "mflo", "d", dreg);
6833 mips_emit_delays (TRUE);
6834 ++mips_opts.noreorder;
6835 mips_any_noreorder = 1;
6837 load_register (AT, &imm_expr, dbl);
6838 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6839 sreg, imm ? AT : treg);
6840 macro_build (NULL, "mfhi", "d", AT);
6841 macro_build (NULL, "mflo", "d", dreg);
6843 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6846 expr1.X_add_number = 8;
6847 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6848 macro_build (NULL, "nop", "", 0);
6849 macro_build (NULL, "break", "c", 6);
6851 --mips_opts.noreorder;
6855 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6867 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6868 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6873 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6874 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6875 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6876 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6880 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6892 macro_build (NULL, "negu", "d,w", tempreg, treg);
6893 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6898 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6899 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6900 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6901 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6909 if (imm_expr.X_op != O_constant)
6910 as_bad (_("Improper rotate count"));
6911 rot = imm_expr.X_add_number & 0x3f;
6912 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6914 rot = (64 - rot) & 0x3f;
6916 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6918 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6923 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
6926 l = (rot < 0x20) ? "dsll" : "dsll32";
6927 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6929 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
6930 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6931 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6939 if (imm_expr.X_op != O_constant)
6940 as_bad (_("Improper rotate count"));
6941 rot = imm_expr.X_add_number & 0x1f;
6942 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6944 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6949 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
6952 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
6953 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6954 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6959 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6961 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
6964 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6965 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
6966 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
6967 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6971 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6973 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
6976 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6977 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
6978 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
6979 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6987 if (imm_expr.X_op != O_constant)
6988 as_bad (_("Improper rotate count"));
6989 rot = imm_expr.X_add_number & 0x3f;
6990 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6993 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
6995 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7000 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7003 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7004 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7006 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7007 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7008 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7016 if (imm_expr.X_op != O_constant)
7017 as_bad (_("Improper rotate count"));
7018 rot = imm_expr.X_add_number & 0x1f;
7019 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7021 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7026 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7029 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7030 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7031 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7036 if (mips_opts.arch == CPU_R4650)
7038 as_bad (_("opcode not supported on this processor"));
7041 assert (mips_opts.isa == ISA_MIPS1);
7042 /* Even on a big endian machine $fn comes before $fn+1. We have
7043 to adjust when storing to memory. */
7044 macro_build (&offset_expr, "swc1", "T,o(b)",
7045 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7046 offset_expr.X_add_number += 4;
7047 macro_build (&offset_expr, "swc1", "T,o(b)",
7048 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7053 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7055 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7058 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7059 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7064 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7066 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7071 as_warn (_("Instruction %s: result is always false"),
7073 move_register (dreg, 0);
7076 if (imm_expr.X_op == O_constant
7077 && imm_expr.X_add_number >= 0
7078 && imm_expr.X_add_number < 0x10000)
7080 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7083 else if (imm_expr.X_op == O_constant
7084 && imm_expr.X_add_number > -0x8000
7085 && imm_expr.X_add_number < 0)
7087 imm_expr.X_add_number = -imm_expr.X_add_number;
7088 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7089 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7094 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7095 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7098 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7103 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7109 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7110 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7113 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7115 if (imm_expr.X_op == O_constant
7116 && imm_expr.X_add_number >= -0x8000
7117 && imm_expr.X_add_number < 0x8000)
7119 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7120 dreg, sreg, BFD_RELOC_LO16);
7125 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7126 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7130 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7135 case M_SGT: /* sreg > treg <==> treg < sreg */
7141 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7144 case M_SGT_I: /* sreg > I <==> I < sreg */
7150 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7151 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7154 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7160 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7161 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7164 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7170 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7171 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7172 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7176 if (imm_expr.X_op == O_constant
7177 && imm_expr.X_add_number >= -0x8000
7178 && imm_expr.X_add_number < 0x8000)
7180 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7183 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7184 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7188 if (imm_expr.X_op == O_constant
7189 && imm_expr.X_add_number >= -0x8000
7190 && imm_expr.X_add_number < 0x8000)
7192 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7196 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7197 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7202 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7204 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7207 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7208 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7213 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7215 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7220 as_warn (_("Instruction %s: result is always true"),
7222 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7223 dreg, 0, BFD_RELOC_LO16);
7226 if (imm_expr.X_op == O_constant
7227 && imm_expr.X_add_number >= 0
7228 && imm_expr.X_add_number < 0x10000)
7230 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7233 else if (imm_expr.X_op == O_constant
7234 && imm_expr.X_add_number > -0x8000
7235 && imm_expr.X_add_number < 0)
7237 imm_expr.X_add_number = -imm_expr.X_add_number;
7238 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7239 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7244 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7245 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7248 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7256 if (imm_expr.X_op == O_constant
7257 && imm_expr.X_add_number > -0x8000
7258 && imm_expr.X_add_number <= 0x8000)
7260 imm_expr.X_add_number = -imm_expr.X_add_number;
7261 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7262 dreg, sreg, BFD_RELOC_LO16);
7265 load_register (AT, &imm_expr, dbl);
7266 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7272 if (imm_expr.X_op == O_constant
7273 && imm_expr.X_add_number > -0x8000
7274 && imm_expr.X_add_number <= 0x8000)
7276 imm_expr.X_add_number = -imm_expr.X_add_number;
7277 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7278 dreg, sreg, BFD_RELOC_LO16);
7281 load_register (AT, &imm_expr, dbl);
7282 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7303 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7304 macro_build (NULL, s, "s,t", sreg, AT);
7309 assert (mips_opts.isa == ISA_MIPS1);
7310 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7311 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7314 * Is the double cfc1 instruction a bug in the mips assembler;
7315 * or is there a reason for it?
7317 mips_emit_delays (TRUE);
7318 ++mips_opts.noreorder;
7319 mips_any_noreorder = 1;
7320 macro_build (NULL, "cfc1", "t,G", treg, RA);
7321 macro_build (NULL, "cfc1", "t,G", treg, RA);
7322 macro_build (NULL, "nop", "");
7323 expr1.X_add_number = 3;
7324 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7325 expr1.X_add_number = 2;
7326 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7327 macro_build (NULL, "ctc1", "t,G", AT, RA);
7328 macro_build (NULL, "nop", "");
7329 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7331 macro_build (NULL, "ctc1", "t,G", treg, RA);
7332 macro_build (NULL, "nop", "");
7333 --mips_opts.noreorder;
7342 if (offset_expr.X_add_number >= 0x7fff)
7343 as_bad (_("operand overflow"));
7344 if (! target_big_endian)
7345 ++offset_expr.X_add_number;
7346 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7347 if (! target_big_endian)
7348 --offset_expr.X_add_number;
7350 ++offset_expr.X_add_number;
7351 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7352 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7353 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7366 if (offset_expr.X_add_number >= 0x8000 - off)
7367 as_bad (_("operand overflow"));
7372 if (! target_big_endian)
7373 offset_expr.X_add_number += off;
7374 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7375 if (! target_big_endian)
7376 offset_expr.X_add_number -= off;
7378 offset_expr.X_add_number += off;
7379 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7381 /* If necessary, move the result in tempreg the final destination. */
7382 if (treg == tempreg)
7384 /* Protect second load's delay slot. */
7386 move_register (treg, tempreg);
7400 load_address (AT, &offset_expr, &used_at);
7402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7403 if (! target_big_endian)
7404 expr1.X_add_number = off;
7406 expr1.X_add_number = 0;
7407 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7408 if (! target_big_endian)
7409 expr1.X_add_number = 0;
7411 expr1.X_add_number = off;
7412 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7418 load_address (AT, &offset_expr, &used_at);
7420 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7421 if (target_big_endian)
7422 expr1.X_add_number = 0;
7423 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7424 treg, BFD_RELOC_LO16, AT);
7425 if (target_big_endian)
7426 expr1.X_add_number = 1;
7428 expr1.X_add_number = 0;
7429 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7430 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7431 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7435 if (offset_expr.X_add_number >= 0x7fff)
7436 as_bad (_("operand overflow"));
7437 if (target_big_endian)
7438 ++offset_expr.X_add_number;
7439 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7440 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7441 if (target_big_endian)
7442 --offset_expr.X_add_number;
7444 ++offset_expr.X_add_number;
7445 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7458 if (offset_expr.X_add_number >= 0x8000 - off)
7459 as_bad (_("operand overflow"));
7460 if (! target_big_endian)
7461 offset_expr.X_add_number += off;
7462 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7463 if (! target_big_endian)
7464 offset_expr.X_add_number -= off;
7466 offset_expr.X_add_number += off;
7467 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7481 load_address (AT, &offset_expr, &used_at);
7483 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7484 if (! target_big_endian)
7485 expr1.X_add_number = off;
7487 expr1.X_add_number = 0;
7488 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7489 if (! target_big_endian)
7490 expr1.X_add_number = 0;
7492 expr1.X_add_number = off;
7493 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7498 load_address (AT, &offset_expr, &used_at);
7500 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7501 if (! target_big_endian)
7502 expr1.X_add_number = 0;
7503 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7504 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7505 if (! target_big_endian)
7506 expr1.X_add_number = 1;
7508 expr1.X_add_number = 0;
7509 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7510 if (! target_big_endian)
7511 expr1.X_add_number = 0;
7513 expr1.X_add_number = 1;
7514 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7515 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7516 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7520 /* FIXME: Check if this is one of the itbl macros, since they
7521 are added dynamically. */
7522 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7526 as_warn (_("Macro used $at after \".set noat\""));
7529 /* Implement macros in mips16 mode. */
7532 mips16_macro (struct mips_cl_insn *ip)
7535 int xreg, yreg, zreg, tmp;
7538 const char *s, *s2, *s3;
7540 mask = ip->insn_mo->mask;
7542 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7543 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7544 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7546 expr1.X_op = O_constant;
7547 expr1.X_op_symbol = NULL;
7548 expr1.X_add_symbol = NULL;
7549 expr1.X_add_number = 1;
7568 mips_emit_delays (TRUE);
7569 ++mips_opts.noreorder;
7570 mips_any_noreorder = 1;
7571 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7572 expr1.X_add_number = 2;
7573 macro_build (&expr1, "bnez", "x,p", yreg);
7574 macro_build (NULL, "break", "6", 7);
7576 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7577 since that causes an overflow. We should do that as well,
7578 but I don't see how to do the comparisons without a temporary
7580 --mips_opts.noreorder;
7581 macro_build (NULL, s, "x", zreg);
7600 mips_emit_delays (TRUE);
7601 ++mips_opts.noreorder;
7602 mips_any_noreorder = 1;
7603 macro_build (NULL, s, "0,x,y", xreg, yreg);
7604 expr1.X_add_number = 2;
7605 macro_build (&expr1, "bnez", "x,p", yreg);
7606 macro_build (NULL, "break", "6", 7);
7607 --mips_opts.noreorder;
7608 macro_build (NULL, s2, "x", zreg);
7614 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7615 macro_build (NULL, "mflo", "x", zreg);
7623 if (imm_expr.X_op != O_constant)
7624 as_bad (_("Unsupported large constant"));
7625 imm_expr.X_add_number = -imm_expr.X_add_number;
7626 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7630 if (imm_expr.X_op != O_constant)
7631 as_bad (_("Unsupported large constant"));
7632 imm_expr.X_add_number = -imm_expr.X_add_number;
7633 macro_build (&imm_expr, "addiu", "x,k", xreg);
7637 if (imm_expr.X_op != O_constant)
7638 as_bad (_("Unsupported large constant"));
7639 imm_expr.X_add_number = -imm_expr.X_add_number;
7640 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7662 goto do_reverse_branch;
7666 goto do_reverse_branch;
7678 goto do_reverse_branch;
7689 macro_build (NULL, s, "x,y", xreg, yreg);
7690 macro_build (&offset_expr, s2, "p");
7717 goto do_addone_branch_i;
7722 goto do_addone_branch_i;
7737 goto do_addone_branch_i;
7744 if (imm_expr.X_op != O_constant)
7745 as_bad (_("Unsupported large constant"));
7746 ++imm_expr.X_add_number;
7749 macro_build (&imm_expr, s, s3, xreg);
7750 macro_build (&offset_expr, s2, "p");
7754 expr1.X_add_number = 0;
7755 macro_build (&expr1, "slti", "x,8", yreg);
7757 move_register (xreg, yreg);
7758 expr1.X_add_number = 2;
7759 macro_build (&expr1, "bteqz", "p");
7760 macro_build (NULL, "neg", "x,w", xreg, xreg);
7764 /* For consistency checking, verify that all bits are specified either
7765 by the match/mask part of the instruction definition, or by the
7768 validate_mips_insn (const struct mips_opcode *opc)
7770 const char *p = opc->args;
7772 unsigned long used_bits = opc->mask;
7774 if ((used_bits & opc->match) != opc->match)
7776 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7777 opc->name, opc->args);
7780 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7790 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7791 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7792 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7793 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7794 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7795 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7796 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7797 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7798 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7801 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7802 c, opc->name, opc->args);
7806 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7807 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7809 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7810 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7811 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7812 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7814 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7815 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7817 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7818 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7820 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7821 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7822 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7823 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7824 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7825 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7826 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7827 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7828 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7829 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7830 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7831 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7832 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7833 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7834 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7835 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7836 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7838 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7839 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7840 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7841 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7843 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7844 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7845 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7846 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7847 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7848 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7849 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7850 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7851 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7854 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7855 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7856 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7857 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7858 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7862 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7863 c, opc->name, opc->args);
7867 if (used_bits != 0xffffffff)
7869 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7870 ~used_bits & 0xffffffff, opc->name, opc->args);
7876 /* This routine assembles an instruction into its binary format. As a
7877 side effect, it sets one of the global variables imm_reloc or
7878 offset_reloc to the type of relocation to do if one of the operands
7879 is an address expression. */
7882 mips_ip (char *str, struct mips_cl_insn *ip)
7887 struct mips_opcode *insn;
7890 unsigned int lastregno = 0;
7891 unsigned int lastpos = 0;
7892 unsigned int limlo, limhi;
7898 /* If the instruction contains a '.', we first try to match an instruction
7899 including the '.'. Then we try again without the '.'. */
7901 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7904 /* If we stopped on whitespace, then replace the whitespace with null for
7905 the call to hash_find. Save the character we replaced just in case we
7906 have to re-parse the instruction. */
7913 insn = (struct mips_opcode *) hash_find (op_hash, str);
7915 /* If we didn't find the instruction in the opcode table, try again, but
7916 this time with just the instruction up to, but not including the
7920 /* Restore the character we overwrite above (if any). */
7924 /* Scan up to the first '.' or whitespace. */
7926 *s != '\0' && *s != '.' && !ISSPACE (*s);
7930 /* If we did not find a '.', then we can quit now. */
7933 insn_error = "unrecognized opcode";
7937 /* Lookup the instruction in the hash table. */
7939 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7941 insn_error = "unrecognized opcode";
7951 assert (strcmp (insn->name, str) == 0);
7953 if (OPCODE_IS_MEMBER (insn,
7955 | (file_ase_mips16 ? INSN_MIPS16 : 0)
7956 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7957 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7963 if (insn->pinfo != INSN_MACRO)
7965 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7971 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7972 && strcmp (insn->name, insn[1].name) == 0)
7981 static char buf[100];
7983 _("opcode not supported on this processor: %s (%s)"),
7984 mips_cpu_info_from_arch (mips_opts.arch)->name,
7985 mips_cpu_info_from_isa (mips_opts.isa)->name);
7995 ip->insn_opcode = insn->match;
7997 for (args = insn->args;; ++args)
8001 s += strspn (s, " \t");
8005 case '\0': /* end of args */
8018 ip->insn_opcode |= lastregno << OP_SH_RS;
8022 ip->insn_opcode |= lastregno << OP_SH_RT;
8026 ip->insn_opcode |= lastregno << OP_SH_FT;
8030 ip->insn_opcode |= lastregno << OP_SH_FS;
8036 /* Handle optional base register.
8037 Either the base register is omitted or
8038 we must have a left paren. */
8039 /* This is dependent on the next operand specifier
8040 is a base register specification. */
8041 assert (args[1] == 'b' || args[1] == '5'
8042 || args[1] == '-' || args[1] == '4');
8046 case ')': /* these must match exactly */
8053 case '+': /* Opcode extension character. */
8056 case 'A': /* ins/ext position, becomes LSB. */
8065 my_getExpression (&imm_expr, s);
8066 check_absolute_expr (ip, &imm_expr);
8067 if ((unsigned long) imm_expr.X_add_number < limlo
8068 || (unsigned long) imm_expr.X_add_number > limhi)
8070 as_bad (_("Improper position (%lu)"),
8071 (unsigned long) imm_expr.X_add_number);
8072 imm_expr.X_add_number = limlo;
8074 lastpos = imm_expr.X_add_number;
8075 ip->insn_opcode |= (imm_expr.X_add_number
8076 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8077 imm_expr.X_op = O_absent;
8081 case 'B': /* ins size, becomes MSB. */
8090 my_getExpression (&imm_expr, s);
8091 check_absolute_expr (ip, &imm_expr);
8092 /* Check for negative input so that small negative numbers
8093 will not succeed incorrectly. The checks against
8094 (pos+size) transitively check "size" itself,
8095 assuming that "pos" is reasonable. */
8096 if ((long) imm_expr.X_add_number < 0
8097 || ((unsigned long) imm_expr.X_add_number
8099 || ((unsigned long) imm_expr.X_add_number
8102 as_bad (_("Improper insert size (%lu, position %lu)"),
8103 (unsigned long) imm_expr.X_add_number,
8104 (unsigned long) lastpos);
8105 imm_expr.X_add_number = limlo - lastpos;
8107 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8108 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8109 imm_expr.X_op = O_absent;
8113 case 'C': /* ext size, becomes MSBD. */
8126 my_getExpression (&imm_expr, s);
8127 check_absolute_expr (ip, &imm_expr);
8128 /* Check for negative input so that small negative numbers
8129 will not succeed incorrectly. The checks against
8130 (pos+size) transitively check "size" itself,
8131 assuming that "pos" is reasonable. */
8132 if ((long) imm_expr.X_add_number < 0
8133 || ((unsigned long) imm_expr.X_add_number
8135 || ((unsigned long) imm_expr.X_add_number
8138 as_bad (_("Improper extract size (%lu, position %lu)"),
8139 (unsigned long) imm_expr.X_add_number,
8140 (unsigned long) lastpos);
8141 imm_expr.X_add_number = limlo - lastpos;
8143 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8144 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8145 imm_expr.X_op = O_absent;
8150 /* +D is for disassembly only; never match. */
8154 /* "+I" is like "I", except that imm2_expr is used. */
8155 my_getExpression (&imm2_expr, s);
8156 if (imm2_expr.X_op != O_big
8157 && imm2_expr.X_op != O_constant)
8158 insn_error = _("absolute expression required");
8159 normalize_constant_expr (&imm2_expr);
8164 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8165 *args, insn->name, insn->args);
8166 /* Further processing is fruitless. */
8171 case '<': /* must be at least one digit */
8173 * According to the manual, if the shift amount is greater
8174 * than 31 or less than 0, then the shift amount should be
8175 * mod 32. In reality the mips assembler issues an error.
8176 * We issue a warning and mask out all but the low 5 bits.
8178 my_getExpression (&imm_expr, s);
8179 check_absolute_expr (ip, &imm_expr);
8180 if ((unsigned long) imm_expr.X_add_number > 31)
8182 as_warn (_("Improper shift amount (%lu)"),
8183 (unsigned long) imm_expr.X_add_number);
8184 imm_expr.X_add_number &= OP_MASK_SHAMT;
8186 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8187 imm_expr.X_op = O_absent;
8191 case '>': /* shift amount minus 32 */
8192 my_getExpression (&imm_expr, s);
8193 check_absolute_expr (ip, &imm_expr);
8194 if ((unsigned long) imm_expr.X_add_number < 32
8195 || (unsigned long) imm_expr.X_add_number > 63)
8197 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8198 imm_expr.X_op = O_absent;
8202 case 'k': /* cache code */
8203 case 'h': /* prefx code */
8204 my_getExpression (&imm_expr, s);
8205 check_absolute_expr (ip, &imm_expr);
8206 if ((unsigned long) imm_expr.X_add_number > 31)
8208 as_warn (_("Invalid value for `%s' (%lu)"),
8210 (unsigned long) imm_expr.X_add_number);
8211 imm_expr.X_add_number &= 0x1f;
8214 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8216 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8217 imm_expr.X_op = O_absent;
8221 case 'c': /* break code */
8222 my_getExpression (&imm_expr, s);
8223 check_absolute_expr (ip, &imm_expr);
8224 if ((unsigned long) imm_expr.X_add_number > 1023)
8226 as_warn (_("Illegal break code (%lu)"),
8227 (unsigned long) imm_expr.X_add_number);
8228 imm_expr.X_add_number &= OP_MASK_CODE;
8230 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8231 imm_expr.X_op = O_absent;
8235 case 'q': /* lower break code */
8236 my_getExpression (&imm_expr, s);
8237 check_absolute_expr (ip, &imm_expr);
8238 if ((unsigned long) imm_expr.X_add_number > 1023)
8240 as_warn (_("Illegal lower break code (%lu)"),
8241 (unsigned long) imm_expr.X_add_number);
8242 imm_expr.X_add_number &= OP_MASK_CODE2;
8244 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8245 imm_expr.X_op = O_absent;
8249 case 'B': /* 20-bit syscall/break code. */
8250 my_getExpression (&imm_expr, s);
8251 check_absolute_expr (ip, &imm_expr);
8252 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8253 as_warn (_("Illegal 20-bit code (%lu)"),
8254 (unsigned long) imm_expr.X_add_number);
8255 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8256 imm_expr.X_op = O_absent;
8260 case 'C': /* Coprocessor code */
8261 my_getExpression (&imm_expr, s);
8262 check_absolute_expr (ip, &imm_expr);
8263 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8265 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8266 (unsigned long) imm_expr.X_add_number);
8267 imm_expr.X_add_number &= ((1 << 25) - 1);
8269 ip->insn_opcode |= imm_expr.X_add_number;
8270 imm_expr.X_op = O_absent;
8274 case 'J': /* 19-bit wait code. */
8275 my_getExpression (&imm_expr, s);
8276 check_absolute_expr (ip, &imm_expr);
8277 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8278 as_warn (_("Illegal 19-bit code (%lu)"),
8279 (unsigned long) imm_expr.X_add_number);
8280 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8281 imm_expr.X_op = O_absent;
8285 case 'P': /* Performance register */
8286 my_getExpression (&imm_expr, s);
8287 check_absolute_expr (ip, &imm_expr);
8288 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8290 as_warn (_("Invalid performance register (%lu)"),
8291 (unsigned long) imm_expr.X_add_number);
8292 imm_expr.X_add_number &= OP_MASK_PERFREG;
8294 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8295 imm_expr.X_op = O_absent;
8299 case 'b': /* base register */
8300 case 'd': /* destination register */
8301 case 's': /* source register */
8302 case 't': /* target register */
8303 case 'r': /* both target and source */
8304 case 'v': /* both dest and source */
8305 case 'w': /* both dest and target */
8306 case 'E': /* coprocessor target register */
8307 case 'G': /* coprocessor destination register */
8308 case 'K': /* 'rdhwr' destination register */
8309 case 'x': /* ignore register name */
8310 case 'z': /* must be zero register */
8311 case 'U': /* destination register (clo/clz). */
8326 while (ISDIGIT (*s));
8328 as_bad (_("Invalid register number (%d)"), regno);
8330 else if (*args == 'E' || *args == 'G' || *args == 'K')
8334 if (s[1] == 'r' && s[2] == 'a')
8339 else if (s[1] == 'f' && s[2] == 'p')
8344 else if (s[1] == 's' && s[2] == 'p')
8349 else if (s[1] == 'g' && s[2] == 'p')
8354 else if (s[1] == 'a' && s[2] == 't')
8359 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8364 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8369 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8374 else if (itbl_have_entries)
8379 p = s + 1; /* advance past '$' */
8380 n = itbl_get_field (&p); /* n is name */
8382 /* See if this is a register defined in an
8384 if (itbl_get_reg_val (n, &r))
8386 /* Get_field advances to the start of
8387 the next field, so we need to back
8388 rack to the end of the last field. */
8392 s = strchr (s, '\0');
8406 as_warn (_("Used $at without \".set noat\""));
8412 if (c == 'r' || c == 'v' || c == 'w')
8419 /* 'z' only matches $0. */
8420 if (c == 'z' && regno != 0)
8423 /* Now that we have assembled one operand, we use the args string
8424 * to figure out where it goes in the instruction. */
8431 ip->insn_opcode |= regno << OP_SH_RS;
8436 ip->insn_opcode |= regno << OP_SH_RD;
8439 ip->insn_opcode |= regno << OP_SH_RD;
8440 ip->insn_opcode |= regno << OP_SH_RT;
8445 ip->insn_opcode |= regno << OP_SH_RT;
8448 /* This case exists because on the r3000 trunc
8449 expands into a macro which requires a gp
8450 register. On the r6000 or r4000 it is
8451 assembled into a single instruction which
8452 ignores the register. Thus the insn version
8453 is MIPS_ISA2 and uses 'x', and the macro
8454 version is MIPS_ISA1 and uses 't'. */
8457 /* This case is for the div instruction, which
8458 acts differently if the destination argument
8459 is $0. This only matches $0, and is checked
8460 outside the switch. */
8463 /* Itbl operand; not yet implemented. FIXME ?? */
8465 /* What about all other operands like 'i', which
8466 can be specified in the opcode table? */
8476 ip->insn_opcode |= lastregno << OP_SH_RS;
8479 ip->insn_opcode |= lastregno << OP_SH_RT;
8484 case 'O': /* MDMX alignment immediate constant. */
8485 my_getExpression (&imm_expr, s);
8486 check_absolute_expr (ip, &imm_expr);
8487 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8489 as_warn ("Improper align amount (%ld), using low bits",
8490 (long) imm_expr.X_add_number);
8491 imm_expr.X_add_number &= OP_MASK_ALN;
8493 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8494 imm_expr.X_op = O_absent;
8498 case 'Q': /* MDMX vector, element sel, or const. */
8501 /* MDMX Immediate. */
8502 my_getExpression (&imm_expr, s);
8503 check_absolute_expr (ip, &imm_expr);
8504 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8506 as_warn (_("Invalid MDMX Immediate (%ld)"),
8507 (long) imm_expr.X_add_number);
8508 imm_expr.X_add_number &= OP_MASK_FT;
8510 imm_expr.X_add_number &= OP_MASK_FT;
8511 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8512 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8514 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8515 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8516 imm_expr.X_op = O_absent;
8520 /* Not MDMX Immediate. Fall through. */
8521 case 'X': /* MDMX destination register. */
8522 case 'Y': /* MDMX source register. */
8523 case 'Z': /* MDMX target register. */
8525 case 'D': /* floating point destination register */
8526 case 'S': /* floating point source register */
8527 case 'T': /* floating point target register */
8528 case 'R': /* floating point source register */
8532 /* Accept $fN for FP and MDMX register numbers, and in
8533 addition accept $vN for MDMX register numbers. */
8534 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8535 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8546 while (ISDIGIT (*s));
8549 as_bad (_("Invalid float register number (%d)"), regno);
8551 if ((regno & 1) != 0
8553 && ! (strcmp (str, "mtc1") == 0
8554 || strcmp (str, "mfc1") == 0
8555 || strcmp (str, "lwc1") == 0
8556 || strcmp (str, "swc1") == 0
8557 || strcmp (str, "l.s") == 0
8558 || strcmp (str, "s.s") == 0))
8559 as_warn (_("Float register should be even, was %d"),
8567 if (c == 'V' || c == 'W')
8578 ip->insn_opcode |= regno << OP_SH_FD;
8583 ip->insn_opcode |= regno << OP_SH_FS;
8586 /* This is like 'Z', but also needs to fix the MDMX
8587 vector/scalar select bits. Note that the
8588 scalar immediate case is handled above. */
8591 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8592 int max_el = (is_qh ? 3 : 7);
8594 my_getExpression(&imm_expr, s);
8595 check_absolute_expr (ip, &imm_expr);
8597 if (imm_expr.X_add_number > max_el)
8598 as_bad(_("Bad element selector %ld"),
8599 (long) imm_expr.X_add_number);
8600 imm_expr.X_add_number &= max_el;
8601 ip->insn_opcode |= (imm_expr.X_add_number
8604 imm_expr.X_op = O_absent;
8606 as_warn(_("Expecting ']' found '%s'"), s);
8612 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8613 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8616 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8623 ip->insn_opcode |= regno << OP_SH_FT;
8626 ip->insn_opcode |= regno << OP_SH_FR;
8636 ip->insn_opcode |= lastregno << OP_SH_FS;
8639 ip->insn_opcode |= lastregno << OP_SH_FT;
8645 my_getExpression (&imm_expr, s);
8646 if (imm_expr.X_op != O_big
8647 && imm_expr.X_op != O_constant)
8648 insn_error = _("absolute expression required");
8649 normalize_constant_expr (&imm_expr);
8654 my_getExpression (&offset_expr, s);
8655 *imm_reloc = BFD_RELOC_32;
8668 unsigned char temp[8];
8670 unsigned int length;
8675 /* These only appear as the last operand in an
8676 instruction, and every instruction that accepts
8677 them in any variant accepts them in all variants.
8678 This means we don't have to worry about backing out
8679 any changes if the instruction does not match.
8681 The difference between them is the size of the
8682 floating point constant and where it goes. For 'F'
8683 and 'L' the constant is 64 bits; for 'f' and 'l' it
8684 is 32 bits. Where the constant is placed is based
8685 on how the MIPS assembler does things:
8688 f -- immediate value
8691 The .lit4 and .lit8 sections are only used if
8692 permitted by the -G argument.
8694 The code below needs to know whether the target register
8695 is 32 or 64 bits wide. It relies on the fact 'f' and
8696 'F' are used with GPR-based instructions and 'l' and
8697 'L' are used with FPR-based instructions. */
8699 f64 = *args == 'F' || *args == 'L';
8700 using_gprs = *args == 'F' || *args == 'f';
8702 save_in = input_line_pointer;
8703 input_line_pointer = s;
8704 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8706 s = input_line_pointer;
8707 input_line_pointer = save_in;
8708 if (err != NULL && *err != '\0')
8710 as_bad (_("Bad floating point constant: %s"), err);
8711 memset (temp, '\0', sizeof temp);
8712 length = f64 ? 8 : 4;
8715 assert (length == (unsigned) (f64 ? 8 : 4));
8719 && (g_switch_value < 4
8720 || (temp[0] == 0 && temp[1] == 0)
8721 || (temp[2] == 0 && temp[3] == 0))))
8723 imm_expr.X_op = O_constant;
8724 if (! target_big_endian)
8725 imm_expr.X_add_number = bfd_getl32 (temp);
8727 imm_expr.X_add_number = bfd_getb32 (temp);
8730 && ! mips_disable_float_construction
8731 /* Constants can only be constructed in GPRs and
8732 copied to FPRs if the GPRs are at least as wide
8733 as the FPRs. Force the constant into memory if
8734 we are using 64-bit FPRs but the GPRs are only
8737 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8738 && ((temp[0] == 0 && temp[1] == 0)
8739 || (temp[2] == 0 && temp[3] == 0))
8740 && ((temp[4] == 0 && temp[5] == 0)
8741 || (temp[6] == 0 && temp[7] == 0)))
8743 /* The value is simple enough to load with a couple of
8744 instructions. If using 32-bit registers, set
8745 imm_expr to the high order 32 bits and offset_expr to
8746 the low order 32 bits. Otherwise, set imm_expr to
8747 the entire 64 bit constant. */
8748 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8750 imm_expr.X_op = O_constant;
8751 offset_expr.X_op = O_constant;
8752 if (! target_big_endian)
8754 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8755 offset_expr.X_add_number = bfd_getl32 (temp);
8759 imm_expr.X_add_number = bfd_getb32 (temp);
8760 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8762 if (offset_expr.X_add_number == 0)
8763 offset_expr.X_op = O_absent;
8765 else if (sizeof (imm_expr.X_add_number) > 4)
8767 imm_expr.X_op = O_constant;
8768 if (! target_big_endian)
8769 imm_expr.X_add_number = bfd_getl64 (temp);
8771 imm_expr.X_add_number = bfd_getb64 (temp);
8775 imm_expr.X_op = O_big;
8776 imm_expr.X_add_number = 4;
8777 if (! target_big_endian)
8779 generic_bignum[0] = bfd_getl16 (temp);
8780 generic_bignum[1] = bfd_getl16 (temp + 2);
8781 generic_bignum[2] = bfd_getl16 (temp + 4);
8782 generic_bignum[3] = bfd_getl16 (temp + 6);
8786 generic_bignum[0] = bfd_getb16 (temp + 6);
8787 generic_bignum[1] = bfd_getb16 (temp + 4);
8788 generic_bignum[2] = bfd_getb16 (temp + 2);
8789 generic_bignum[3] = bfd_getb16 (temp);
8795 const char *newname;
8798 /* Switch to the right section. */
8800 subseg = now_subseg;
8803 default: /* unused default case avoids warnings. */
8805 newname = RDATA_SECTION_NAME;
8806 if (g_switch_value >= 8)
8810 newname = RDATA_SECTION_NAME;
8813 assert (g_switch_value >= 4);
8817 new_seg = subseg_new (newname, (subsegT) 0);
8818 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8819 bfd_set_section_flags (stdoutput, new_seg,
8824 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8825 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8826 && strcmp (TARGET_OS, "elf") != 0)
8827 record_alignment (new_seg, 4);
8829 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8831 as_bad (_("Can't use floating point insn in this section"));
8833 /* Set the argument to the current address in the
8835 offset_expr.X_op = O_symbol;
8836 offset_expr.X_add_symbol =
8837 symbol_new ("L0\001", now_seg,
8838 (valueT) frag_now_fix (), frag_now);
8839 offset_expr.X_add_number = 0;
8841 /* Put the floating point number into the section. */
8842 p = frag_more ((int) length);
8843 memcpy (p, temp, length);
8845 /* Switch back to the original section. */
8846 subseg_set (seg, subseg);
8851 case 'i': /* 16 bit unsigned immediate */
8852 case 'j': /* 16 bit signed immediate */
8853 *imm_reloc = BFD_RELOC_LO16;
8854 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
8857 offsetT minval, maxval;
8859 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
8860 && strcmp (insn->name, insn[1].name) == 0);
8862 /* If the expression was written as an unsigned number,
8863 only treat it as signed if there are no more
8867 && sizeof (imm_expr.X_add_number) <= 4
8868 && imm_expr.X_op == O_constant
8869 && imm_expr.X_add_number < 0
8870 && imm_expr.X_unsigned
8874 /* For compatibility with older assemblers, we accept
8875 0x8000-0xffff as signed 16-bit numbers when only
8876 signed numbers are allowed. */
8878 minval = 0, maxval = 0xffff;
8880 minval = -0x8000, maxval = 0x7fff;
8882 minval = -0x8000, maxval = 0xffff;
8884 if (imm_expr.X_op != O_constant
8885 || imm_expr.X_add_number < minval
8886 || imm_expr.X_add_number > maxval)
8890 if (imm_expr.X_op == O_constant
8891 || imm_expr.X_op == O_big)
8892 as_bad (_("expression out of range"));
8898 case 'o': /* 16 bit offset */
8899 /* Check whether there is only a single bracketed expression
8900 left. If so, it must be the base register and the
8901 constant must be zero. */
8902 if (*s == '(' && strchr (s + 1, '(') == 0)
8904 offset_expr.X_op = O_constant;
8905 offset_expr.X_add_number = 0;
8909 /* If this value won't fit into a 16 bit offset, then go
8910 find a macro that will generate the 32 bit offset
8912 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
8913 && (offset_expr.X_op != O_constant
8914 || offset_expr.X_add_number >= 0x8000
8915 || offset_expr.X_add_number < -0x8000))
8921 case 'p': /* pc relative offset */
8922 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8923 my_getExpression (&offset_expr, s);
8927 case 'u': /* upper 16 bits */
8928 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
8929 && imm_expr.X_op == O_constant
8930 && (imm_expr.X_add_number < 0
8931 || imm_expr.X_add_number >= 0x10000))
8932 as_bad (_("lui expression not in range 0..65535"));
8936 case 'a': /* 26 bit address */
8937 my_getExpression (&offset_expr, s);
8939 *offset_reloc = BFD_RELOC_MIPS_JMP;
8942 case 'N': /* 3 bit branch condition code */
8943 case 'M': /* 3 bit compare condition code */
8944 if (strncmp (s, "$fcc", 4) != 0)
8954 while (ISDIGIT (*s));
8956 as_bad (_("Invalid condition code register $fcc%d"), regno);
8957 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
8958 || strcmp(str + strlen(str) - 5, "any2f") == 0
8959 || strcmp(str + strlen(str) - 5, "any2t") == 0)
8960 && (regno & 1) != 0)
8961 as_warn(_("Condition code register should be even for %s, was %d"),
8963 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
8964 || strcmp(str + strlen(str) - 5, "any4t") == 0)
8965 && (regno & 3) != 0)
8966 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8969 ip->insn_opcode |= regno << OP_SH_BCC;
8971 ip->insn_opcode |= regno << OP_SH_CCC;
8975 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8986 while (ISDIGIT (*s));
8989 c = 8; /* Invalid sel value. */
8992 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8993 ip->insn_opcode |= c;
8997 /* Must be at least one digit. */
8998 my_getExpression (&imm_expr, s);
8999 check_absolute_expr (ip, &imm_expr);
9001 if ((unsigned long) imm_expr.X_add_number
9002 > (unsigned long) OP_MASK_VECBYTE)
9004 as_bad (_("bad byte vector index (%ld)"),
9005 (long) imm_expr.X_add_number);
9006 imm_expr.X_add_number = 0;
9009 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9010 imm_expr.X_op = O_absent;
9015 my_getExpression (&imm_expr, s);
9016 check_absolute_expr (ip, &imm_expr);
9018 if ((unsigned long) imm_expr.X_add_number
9019 > (unsigned long) OP_MASK_VECALIGN)
9021 as_bad (_("bad byte vector index (%ld)"),
9022 (long) imm_expr.X_add_number);
9023 imm_expr.X_add_number = 0;
9026 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9027 imm_expr.X_op = O_absent;
9032 as_bad (_("bad char = '%c'\n"), *args);
9037 /* Args don't match. */
9038 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9039 !strcmp (insn->name, insn[1].name))
9043 insn_error = _("illegal operands");
9048 insn_error = _("illegal operands");
9053 /* This routine assembles an instruction into its binary format when
9054 assembling for the mips16. As a side effect, it sets one of the
9055 global variables imm_reloc or offset_reloc to the type of
9056 relocation to do if one of the operands is an address expression.
9057 It also sets mips16_small and mips16_ext if the user explicitly
9058 requested a small or extended instruction. */
9061 mips16_ip (char *str, struct mips_cl_insn *ip)
9065 struct mips_opcode *insn;
9068 unsigned int lastregno = 0;
9073 mips16_small = FALSE;
9076 for (s = str; ISLOWER (*s); ++s)
9088 if (s[1] == 't' && s[2] == ' ')
9091 mips16_small = TRUE;
9095 else if (s[1] == 'e' && s[2] == ' ')
9104 insn_error = _("unknown opcode");
9108 if (mips_opts.noautoextend && ! mips16_ext)
9109 mips16_small = TRUE;
9111 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9113 insn_error = _("unrecognized opcode");
9120 assert (strcmp (insn->name, str) == 0);
9123 ip->insn_opcode = insn->match;
9124 ip->use_extend = FALSE;
9125 imm_expr.X_op = O_absent;
9126 imm_reloc[0] = BFD_RELOC_UNUSED;
9127 imm_reloc[1] = BFD_RELOC_UNUSED;
9128 imm_reloc[2] = BFD_RELOC_UNUSED;
9129 imm2_expr.X_op = O_absent;
9130 offset_expr.X_op = O_absent;
9131 offset_reloc[0] = BFD_RELOC_UNUSED;
9132 offset_reloc[1] = BFD_RELOC_UNUSED;
9133 offset_reloc[2] = BFD_RELOC_UNUSED;
9134 for (args = insn->args; 1; ++args)
9141 /* In this switch statement we call break if we did not find
9142 a match, continue if we did find a match, or return if we
9151 /* Stuff the immediate value in now, if we can. */
9152 if (imm_expr.X_op == O_constant
9153 && *imm_reloc > BFD_RELOC_UNUSED
9154 && insn->pinfo != INSN_MACRO)
9156 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9157 imm_expr.X_add_number, TRUE, mips16_small,
9158 mips16_ext, &ip->insn_opcode,
9159 &ip->use_extend, &ip->extend);
9160 imm_expr.X_op = O_absent;
9161 *imm_reloc = BFD_RELOC_UNUSED;
9175 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9178 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9194 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9196 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9223 while (ISDIGIT (*s));
9226 as_bad (_("invalid register number (%d)"), regno);
9232 if (s[1] == 'r' && s[2] == 'a')
9237 else if (s[1] == 'f' && s[2] == 'p')
9242 else if (s[1] == 's' && s[2] == 'p')
9247 else if (s[1] == 'g' && s[2] == 'p')
9252 else if (s[1] == 'a' && s[2] == 't')
9257 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9262 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9267 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9280 if (c == 'v' || c == 'w')
9282 regno = mips16_to_32_reg_map[lastregno];
9296 regno = mips32_to_16_reg_map[regno];
9301 regno = ILLEGAL_REG;
9306 regno = ILLEGAL_REG;
9311 regno = ILLEGAL_REG;
9316 if (regno == AT && ! mips_opts.noat)
9317 as_warn (_("used $at without \".set noat\""));
9324 if (regno == ILLEGAL_REG)
9331 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9335 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9338 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9341 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9347 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9350 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9351 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9361 if (strncmp (s, "$pc", 3) == 0)
9385 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9387 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9388 and generate the appropriate reloc. If the text
9389 inside %gprel is not a symbol name with an
9390 optional offset, then we generate a normal reloc
9391 and will probably fail later. */
9392 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9393 if (imm_expr.X_op == O_symbol)
9396 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9398 ip->use_extend = TRUE;
9405 /* Just pick up a normal expression. */
9406 my_getExpression (&imm_expr, s);
9409 if (imm_expr.X_op == O_register)
9411 /* What we thought was an expression turned out to
9414 if (s[0] == '(' && args[1] == '(')
9416 /* It looks like the expression was omitted
9417 before a register indirection, which means
9418 that the expression is implicitly zero. We
9419 still set up imm_expr, so that we handle
9420 explicit extensions correctly. */
9421 imm_expr.X_op = O_constant;
9422 imm_expr.X_add_number = 0;
9423 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9430 /* We need to relax this instruction. */
9431 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9440 /* We use offset_reloc rather than imm_reloc for the PC
9441 relative operands. This lets macros with both
9442 immediate and address operands work correctly. */
9443 my_getExpression (&offset_expr, s);
9445 if (offset_expr.X_op == O_register)
9448 /* We need to relax this instruction. */
9449 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9453 case '6': /* break code */
9454 my_getExpression (&imm_expr, s);
9455 check_absolute_expr (ip, &imm_expr);
9456 if ((unsigned long) imm_expr.X_add_number > 63)
9458 as_warn (_("Invalid value for `%s' (%lu)"),
9460 (unsigned long) imm_expr.X_add_number);
9461 imm_expr.X_add_number &= 0x3f;
9463 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9464 imm_expr.X_op = O_absent;
9468 case 'a': /* 26 bit address */
9469 my_getExpression (&offset_expr, s);
9471 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9472 ip->insn_opcode <<= 16;
9475 case 'l': /* register list for entry macro */
9476 case 'L': /* register list for exit macro */
9486 int freg, reg1, reg2;
9488 while (*s == ' ' || *s == ',')
9492 as_bad (_("can't parse register list"));
9504 while (ISDIGIT (*s))
9526 as_bad (_("invalid register list"));
9531 while (ISDIGIT (*s))
9538 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9543 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9548 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9549 mask |= (reg2 - 3) << 3;
9550 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9551 mask |= (reg2 - 15) << 1;
9552 else if (reg1 == RA && reg2 == RA)
9556 as_bad (_("invalid register list"));
9560 /* The mask is filled in in the opcode table for the
9561 benefit of the disassembler. We remove it before
9562 applying the actual mask. */
9563 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9564 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9568 case 'e': /* extend code */
9569 my_getExpression (&imm_expr, s);
9570 check_absolute_expr (ip, &imm_expr);
9571 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9573 as_warn (_("Invalid value for `%s' (%lu)"),
9575 (unsigned long) imm_expr.X_add_number);
9576 imm_expr.X_add_number &= 0x7ff;
9578 ip->insn_opcode |= imm_expr.X_add_number;
9579 imm_expr.X_op = O_absent;
9589 /* Args don't match. */
9590 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9591 strcmp (insn->name, insn[1].name) == 0)
9598 insn_error = _("illegal operands");
9604 /* This structure holds information we know about a mips16 immediate
9607 struct mips16_immed_operand
9609 /* The type code used in the argument string in the opcode table. */
9611 /* The number of bits in the short form of the opcode. */
9613 /* The number of bits in the extended form of the opcode. */
9615 /* The amount by which the short form is shifted when it is used;
9616 for example, the sw instruction has a shift count of 2. */
9618 /* The amount by which the short form is shifted when it is stored
9619 into the instruction code. */
9621 /* Non-zero if the short form is unsigned. */
9623 /* Non-zero if the extended form is unsigned. */
9625 /* Non-zero if the value is PC relative. */
9629 /* The mips16 immediate operand types. */
9631 static const struct mips16_immed_operand mips16_immed_operands[] =
9633 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9634 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9635 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9636 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9637 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9638 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9639 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9640 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9641 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9642 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9643 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9644 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9645 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9646 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9647 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9648 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9649 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9650 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9651 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9652 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9653 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9656 #define MIPS16_NUM_IMMED \
9657 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9659 /* Handle a mips16 instruction with an immediate value. This or's the
9660 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9661 whether an extended value is needed; if one is needed, it sets
9662 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9663 If SMALL is true, an unextended opcode was explicitly requested.
9664 If EXT is true, an extended opcode was explicitly requested. If
9665 WARN is true, warn if EXT does not match reality. */
9668 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9669 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9670 unsigned long *insn, bfd_boolean *use_extend,
9671 unsigned short *extend)
9673 register const struct mips16_immed_operand *op;
9674 int mintiny, maxtiny;
9675 bfd_boolean needext;
9677 op = mips16_immed_operands;
9678 while (op->type != type)
9681 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9686 if (type == '<' || type == '>' || type == '[' || type == ']')
9689 maxtiny = 1 << op->nbits;
9694 maxtiny = (1 << op->nbits) - 1;
9699 mintiny = - (1 << (op->nbits - 1));
9700 maxtiny = (1 << (op->nbits - 1)) - 1;
9703 /* Branch offsets have an implicit 0 in the lowest bit. */
9704 if (type == 'p' || type == 'q')
9707 if ((val & ((1 << op->shift) - 1)) != 0
9708 || val < (mintiny << op->shift)
9709 || val > (maxtiny << op->shift))
9714 if (warn && ext && ! needext)
9715 as_warn_where (file, line,
9716 _("extended operand requested but not required"));
9717 if (small && needext)
9718 as_bad_where (file, line, _("invalid unextended operand value"));
9720 if (small || (! ext && ! needext))
9724 *use_extend = FALSE;
9725 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9726 insnval <<= op->op_shift;
9731 long minext, maxext;
9737 maxext = (1 << op->extbits) - 1;
9741 minext = - (1 << (op->extbits - 1));
9742 maxext = (1 << (op->extbits - 1)) - 1;
9744 if (val < minext || val > maxext)
9745 as_bad_where (file, line,
9746 _("operand value out of range for instruction"));
9749 if (op->extbits == 16)
9751 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9754 else if (op->extbits == 15)
9756 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9761 extval = ((val & 0x1f) << 6) | (val & 0x20);
9765 *extend = (unsigned short) extval;
9770 static const struct percent_op_match
9773 bfd_reloc_code_real_type reloc;
9776 {"%lo", BFD_RELOC_LO16},
9778 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9779 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9780 {"%call16", BFD_RELOC_MIPS_CALL16},
9781 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9782 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9783 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9784 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9785 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9786 {"%got", BFD_RELOC_MIPS_GOT16},
9787 {"%gp_rel", BFD_RELOC_GPREL16},
9788 {"%half", BFD_RELOC_16},
9789 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9790 {"%higher", BFD_RELOC_MIPS_HIGHER},
9791 {"%neg", BFD_RELOC_MIPS_SUB},
9793 {"%hi", BFD_RELOC_HI16_S}
9797 /* Return true if *STR points to a relocation operator. When returning true,
9798 move *STR over the operator and store its relocation code in *RELOC.
9799 Leave both *STR and *RELOC alone when returning false. */
9802 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9806 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9807 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9809 *str += strlen (percent_op[i].str);
9810 *reloc = percent_op[i].reloc;
9812 /* Check whether the output BFD supports this relocation.
9813 If not, issue an error and fall back on something safe. */
9814 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9816 as_bad ("relocation %s isn't supported by the current ABI",
9818 *reloc = BFD_RELOC_UNUSED;
9826 /* Parse string STR as a 16-bit relocatable operand. Store the
9827 expression in *EP and the relocations in the array starting
9828 at RELOC. Return the number of relocation operators used.
9830 On exit, EXPR_END points to the first character after the expression. */
9833 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
9836 bfd_reloc_code_real_type reversed_reloc[3];
9837 size_t reloc_index, i;
9838 int crux_depth, str_depth;
9841 /* Search for the start of the main expression, recoding relocations
9842 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9843 of the main expression and with CRUX_DEPTH containing the number
9844 of open brackets at that point. */
9851 crux_depth = str_depth;
9853 /* Skip over whitespace and brackets, keeping count of the number
9855 while (*str == ' ' || *str == '\t' || *str == '(')
9860 && reloc_index < (HAVE_NEWABI ? 3 : 1)
9861 && parse_relocation (&str, &reversed_reloc[reloc_index]));
9863 my_getExpression (ep, crux);
9866 /* Match every open bracket. */
9867 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
9872 as_bad ("unclosed '('");
9876 if (reloc_index != 0)
9878 prev_reloc_op_frag = frag_now;
9879 for (i = 0; i < reloc_index; i++)
9880 reloc[i] = reversed_reloc[reloc_index - 1 - i];
9887 my_getExpression (expressionS *ep, char *str)
9892 save_in = input_line_pointer;
9893 input_line_pointer = str;
9895 expr_end = input_line_pointer;
9896 input_line_pointer = save_in;
9898 /* If we are in mips16 mode, and this is an expression based on `.',
9899 then we bump the value of the symbol by 1 since that is how other
9900 text symbols are handled. We don't bother to handle complex
9901 expressions, just `.' plus or minus a constant. */
9902 if (mips_opts.mips16
9903 && ep->X_op == O_symbol
9904 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9905 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9906 && symbol_get_frag (ep->X_add_symbol) == frag_now
9907 && symbol_constant_p (ep->X_add_symbol)
9908 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9909 S_SET_VALUE (ep->X_add_symbol, val + 1);
9912 /* Turn a string in input_line_pointer into a floating point constant
9913 of type TYPE, and store the appropriate bytes in *LITP. The number
9914 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9915 returned, or NULL on OK. */
9918 md_atof (int type, char *litP, int *sizeP)
9921 LITTLENUM_TYPE words[4];
9937 return _("bad call to md_atof");
9940 t = atof_ieee (input_line_pointer, type, words);
9942 input_line_pointer = t;
9946 if (! target_big_endian)
9948 for (i = prec - 1; i >= 0; i--)
9950 md_number_to_chars (litP, words[i], 2);
9956 for (i = 0; i < prec; i++)
9958 md_number_to_chars (litP, words[i], 2);
9967 md_number_to_chars (char *buf, valueT val, int n)
9969 if (target_big_endian)
9970 number_to_chars_bigendian (buf, val, n);
9972 number_to_chars_littleendian (buf, val, n);
9976 static int support_64bit_objects(void)
9978 const char **list, **l;
9981 list = bfd_target_list ();
9982 for (l = list; *l != NULL; l++)
9984 /* This is traditional mips */
9985 if (strcmp (*l, "elf64-tradbigmips") == 0
9986 || strcmp (*l, "elf64-tradlittlemips") == 0)
9988 if (strcmp (*l, "elf64-bigmips") == 0
9989 || strcmp (*l, "elf64-littlemips") == 0)
9996 #endif /* OBJ_ELF */
9998 const char *md_shortopts = "O::g::G:";
10000 struct option md_longopts[] =
10002 /* Options which specify architecture. */
10003 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10004 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10005 {"march", required_argument, NULL, OPTION_MARCH},
10006 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10007 {"mtune", required_argument, NULL, OPTION_MTUNE},
10008 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10009 {"mips0", no_argument, NULL, OPTION_MIPS1},
10010 {"mips1", no_argument, NULL, OPTION_MIPS1},
10011 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10012 {"mips2", no_argument, NULL, OPTION_MIPS2},
10013 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10014 {"mips3", no_argument, NULL, OPTION_MIPS3},
10015 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10016 {"mips4", no_argument, NULL, OPTION_MIPS4},
10017 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10018 {"mips5", no_argument, NULL, OPTION_MIPS5},
10019 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10020 {"mips32", no_argument, NULL, OPTION_MIPS32},
10021 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10022 {"mips64", no_argument, NULL, OPTION_MIPS64},
10023 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10024 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10025 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10026 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10028 /* Options which specify Application Specific Extensions (ASEs). */
10029 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10030 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10031 {"mips16", no_argument, NULL, OPTION_MIPS16},
10032 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10033 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10034 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10035 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10036 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10037 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10038 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10039 {"mdmx", no_argument, NULL, OPTION_MDMX},
10040 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10041 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10043 /* Old-style architecture options. Don't add more of these. */
10044 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10045 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10046 {"m4650", no_argument, NULL, OPTION_M4650},
10047 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10048 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10049 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10050 {"m4010", no_argument, NULL, OPTION_M4010},
10051 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10052 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10053 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10054 {"m4100", no_argument, NULL, OPTION_M4100},
10055 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10056 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10057 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10058 {"m3900", no_argument, NULL, OPTION_M3900},
10059 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10060 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10062 /* Options which enable bug fixes. */
10063 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10064 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10065 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10066 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10067 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10068 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10069 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10070 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10071 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10072 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10074 /* Miscellaneous options. */
10075 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10076 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10077 {"trap", no_argument, NULL, OPTION_TRAP},
10078 {"no-break", no_argument, NULL, OPTION_TRAP},
10079 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10080 {"break", no_argument, NULL, OPTION_BREAK},
10081 {"no-trap", no_argument, NULL, OPTION_BREAK},
10082 #define OPTION_EB (OPTION_MISC_BASE + 2)
10083 {"EB", no_argument, NULL, OPTION_EB},
10084 #define OPTION_EL (OPTION_MISC_BASE + 3)
10085 {"EL", no_argument, NULL, OPTION_EL},
10086 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10087 {"mfp32", no_argument, NULL, OPTION_FP32},
10088 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10089 {"mgp32", no_argument, NULL, OPTION_GP32},
10090 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10091 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10092 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10093 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10094 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10095 {"mfp64", no_argument, NULL, OPTION_FP64},
10096 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10097 {"mgp64", no_argument, NULL, OPTION_GP64},
10098 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10099 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10100 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10101 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10103 /* ELF-specific options. */
10105 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10106 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10107 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10108 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10109 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10110 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10111 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10112 {"xgot", no_argument, NULL, OPTION_XGOT},
10113 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10114 {"mabi", required_argument, NULL, OPTION_MABI},
10115 #define OPTION_32 (OPTION_ELF_BASE + 4)
10116 {"32", no_argument, NULL, OPTION_32},
10117 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10118 {"n32", no_argument, NULL, OPTION_N32},
10119 #define OPTION_64 (OPTION_ELF_BASE + 6)
10120 {"64", no_argument, NULL, OPTION_64},
10121 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10122 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10123 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10124 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10125 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10126 {"mpdr", no_argument, NULL, OPTION_PDR},
10127 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10128 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10129 #endif /* OBJ_ELF */
10131 {NULL, no_argument, NULL, 0}
10133 size_t md_longopts_size = sizeof (md_longopts);
10135 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10136 NEW_VALUE. Warn if another value was already specified. Note:
10137 we have to defer parsing the -march and -mtune arguments in order
10138 to handle 'from-abi' correctly, since the ABI might be specified
10139 in a later argument. */
10142 mips_set_option_string (const char **string_ptr, const char *new_value)
10144 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10145 as_warn (_("A different %s was already specified, is now %s"),
10146 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10149 *string_ptr = new_value;
10153 md_parse_option (int c, char *arg)
10157 case OPTION_CONSTRUCT_FLOATS:
10158 mips_disable_float_construction = 0;
10161 case OPTION_NO_CONSTRUCT_FLOATS:
10162 mips_disable_float_construction = 1;
10174 target_big_endian = 1;
10178 target_big_endian = 0;
10182 if (arg && arg[1] == '0')
10192 mips_debug = atoi (arg);
10193 /* When the MIPS assembler sees -g or -g2, it does not do
10194 optimizations which limit full symbolic debugging. We take
10195 that to be equivalent to -O0. */
10196 if (mips_debug == 2)
10201 file_mips_isa = ISA_MIPS1;
10205 file_mips_isa = ISA_MIPS2;
10209 file_mips_isa = ISA_MIPS3;
10213 file_mips_isa = ISA_MIPS4;
10217 file_mips_isa = ISA_MIPS5;
10220 case OPTION_MIPS32:
10221 file_mips_isa = ISA_MIPS32;
10224 case OPTION_MIPS32R2:
10225 file_mips_isa = ISA_MIPS32R2;
10228 case OPTION_MIPS64R2:
10229 file_mips_isa = ISA_MIPS64R2;
10232 case OPTION_MIPS64:
10233 file_mips_isa = ISA_MIPS64;
10237 mips_set_option_string (&mips_tune_string, arg);
10241 mips_set_option_string (&mips_arch_string, arg);
10245 mips_set_option_string (&mips_arch_string, "4650");
10246 mips_set_option_string (&mips_tune_string, "4650");
10249 case OPTION_NO_M4650:
10253 mips_set_option_string (&mips_arch_string, "4010");
10254 mips_set_option_string (&mips_tune_string, "4010");
10257 case OPTION_NO_M4010:
10261 mips_set_option_string (&mips_arch_string, "4100");
10262 mips_set_option_string (&mips_tune_string, "4100");
10265 case OPTION_NO_M4100:
10269 mips_set_option_string (&mips_arch_string, "3900");
10270 mips_set_option_string (&mips_tune_string, "3900");
10273 case OPTION_NO_M3900:
10277 mips_opts.ase_mdmx = 1;
10280 case OPTION_NO_MDMX:
10281 mips_opts.ase_mdmx = 0;
10284 case OPTION_MIPS16:
10285 mips_opts.mips16 = 1;
10286 mips_no_prev_insn (FALSE);
10289 case OPTION_NO_MIPS16:
10290 mips_opts.mips16 = 0;
10291 mips_no_prev_insn (FALSE);
10294 case OPTION_MIPS3D:
10295 mips_opts.ase_mips3d = 1;
10298 case OPTION_NO_MIPS3D:
10299 mips_opts.ase_mips3d = 0;
10302 case OPTION_FIX_VR4120:
10303 mips_fix_vr4120 = 1;
10306 case OPTION_NO_FIX_VR4120:
10307 mips_fix_vr4120 = 0;
10310 case OPTION_RELAX_BRANCH:
10311 mips_relax_branch = 1;
10314 case OPTION_NO_RELAX_BRANCH:
10315 mips_relax_branch = 0;
10319 /* When generating ELF code, we permit -KPIC and -call_shared to
10320 select SVR4_PIC, and -non_shared to select no PIC. This is
10321 intended to be compatible with Irix 5. */
10322 case OPTION_CALL_SHARED:
10323 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10325 as_bad (_("-call_shared is supported only for ELF format"));
10328 mips_pic = SVR4_PIC;
10329 mips_abicalls = TRUE;
10330 if (g_switch_seen && g_switch_value != 0)
10332 as_bad (_("-G may not be used with SVR4 PIC code"));
10335 g_switch_value = 0;
10338 case OPTION_NON_SHARED:
10339 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10341 as_bad (_("-non_shared is supported only for ELF format"));
10345 mips_abicalls = FALSE;
10348 /* The -xgot option tells the assembler to use 32 offsets when
10349 accessing the got in SVR4_PIC mode. It is for Irix
10354 #endif /* OBJ_ELF */
10357 if (mips_pic == SVR4_PIC)
10359 as_bad (_("-G may not be used with SVR4 PIC code"));
10363 g_switch_value = atoi (arg);
10368 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10371 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10373 as_bad (_("-32 is supported for ELF format only"));
10376 mips_abi = O32_ABI;
10380 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10382 as_bad (_("-n32 is supported for ELF format only"));
10385 mips_abi = N32_ABI;
10389 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10391 as_bad (_("-64 is supported for ELF format only"));
10394 mips_abi = N64_ABI;
10395 if (! support_64bit_objects())
10396 as_fatal (_("No compiled in support for 64 bit object file format"));
10398 #endif /* OBJ_ELF */
10401 file_mips_gp32 = 1;
10405 file_mips_gp32 = 0;
10409 file_mips_fp32 = 1;
10413 file_mips_fp32 = 0;
10418 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10420 as_bad (_("-mabi is supported for ELF format only"));
10423 if (strcmp (arg, "32") == 0)
10424 mips_abi = O32_ABI;
10425 else if (strcmp (arg, "o64") == 0)
10426 mips_abi = O64_ABI;
10427 else if (strcmp (arg, "n32") == 0)
10428 mips_abi = N32_ABI;
10429 else if (strcmp (arg, "64") == 0)
10431 mips_abi = N64_ABI;
10432 if (! support_64bit_objects())
10433 as_fatal (_("No compiled in support for 64 bit object file "
10436 else if (strcmp (arg, "eabi") == 0)
10437 mips_abi = EABI_ABI;
10440 as_fatal (_("invalid abi -mabi=%s"), arg);
10444 #endif /* OBJ_ELF */
10446 case OPTION_M7000_HILO_FIX:
10447 mips_7000_hilo_fix = TRUE;
10450 case OPTION_MNO_7000_HILO_FIX:
10451 mips_7000_hilo_fix = FALSE;
10455 case OPTION_MDEBUG:
10456 mips_flag_mdebug = TRUE;
10459 case OPTION_NO_MDEBUG:
10460 mips_flag_mdebug = FALSE;
10464 mips_flag_pdr = TRUE;
10467 case OPTION_NO_PDR:
10468 mips_flag_pdr = FALSE;
10470 #endif /* OBJ_ELF */
10479 /* Set up globals to generate code for the ISA or processor
10480 described by INFO. */
10483 mips_set_architecture (const struct mips_cpu_info *info)
10487 file_mips_arch = info->cpu;
10488 mips_opts.arch = info->cpu;
10489 mips_opts.isa = info->isa;
10494 /* Likewise for tuning. */
10497 mips_set_tune (const struct mips_cpu_info *info)
10500 mips_tune = info->cpu;
10505 mips_after_parse_args (void)
10507 const struct mips_cpu_info *arch_info = 0;
10508 const struct mips_cpu_info *tune_info = 0;
10510 /* GP relative stuff not working for PE */
10511 if (strncmp (TARGET_OS, "pe", 2) == 0
10512 && g_switch_value != 0)
10515 as_bad (_("-G not supported in this configuration."));
10516 g_switch_value = 0;
10519 if (mips_abi == NO_ABI)
10520 mips_abi = MIPS_DEFAULT_ABI;
10522 /* The following code determines the architecture and register size.
10523 Similar code was added to GCC 3.3 (see override_options() in
10524 config/mips/mips.c). The GAS and GCC code should be kept in sync
10525 as much as possible. */
10527 if (mips_arch_string != 0)
10528 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10530 if (file_mips_isa != ISA_UNKNOWN)
10532 /* Handle -mipsN. At this point, file_mips_isa contains the
10533 ISA level specified by -mipsN, while arch_info->isa contains
10534 the -march selection (if any). */
10535 if (arch_info != 0)
10537 /* -march takes precedence over -mipsN, since it is more descriptive.
10538 There's no harm in specifying both as long as the ISA levels
10540 if (file_mips_isa != arch_info->isa)
10541 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10542 mips_cpu_info_from_isa (file_mips_isa)->name,
10543 mips_cpu_info_from_isa (arch_info->isa)->name);
10546 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10549 if (arch_info == 0)
10550 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10552 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10553 as_bad ("-march=%s is not compatible with the selected ABI",
10556 mips_set_architecture (arch_info);
10558 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10559 if (mips_tune_string != 0)
10560 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10562 if (tune_info == 0)
10563 mips_set_tune (arch_info);
10565 mips_set_tune (tune_info);
10567 if (file_mips_gp32 >= 0)
10569 /* The user specified the size of the integer registers. Make sure
10570 it agrees with the ABI and ISA. */
10571 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10572 as_bad (_("-mgp64 used with a 32-bit processor"));
10573 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10574 as_bad (_("-mgp32 used with a 64-bit ABI"));
10575 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10576 as_bad (_("-mgp64 used with a 32-bit ABI"));
10580 /* Infer the integer register size from the ABI and processor.
10581 Restrict ourselves to 32-bit registers if that's all the
10582 processor has, or if the ABI cannot handle 64-bit registers. */
10583 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10584 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10587 /* ??? GAS treats single-float processors as though they had 64-bit
10588 float registers (although it complains when double-precision
10589 instructions are used). As things stand, saying they have 32-bit
10590 registers would lead to spurious "register must be even" messages.
10591 So here we assume float registers are always the same size as
10592 integer ones, unless the user says otherwise. */
10593 if (file_mips_fp32 < 0)
10594 file_mips_fp32 = file_mips_gp32;
10596 /* End of GCC-shared inference code. */
10598 /* This flag is set when we have a 64-bit capable CPU but use only
10599 32-bit wide registers. Note that EABI does not use it. */
10600 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10601 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10602 || mips_abi == O32_ABI))
10603 mips_32bitmode = 1;
10605 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10606 as_bad (_("trap exception not supported at ISA 1"));
10608 /* If the selected architecture includes support for ASEs, enable
10609 generation of code for them. */
10610 if (mips_opts.mips16 == -1)
10611 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10612 if (mips_opts.ase_mips3d == -1)
10613 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10614 if (mips_opts.ase_mdmx == -1)
10615 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10617 file_mips_isa = mips_opts.isa;
10618 file_ase_mips16 = mips_opts.mips16;
10619 file_ase_mips3d = mips_opts.ase_mips3d;
10620 file_ase_mdmx = mips_opts.ase_mdmx;
10621 mips_opts.gp32 = file_mips_gp32;
10622 mips_opts.fp32 = file_mips_fp32;
10624 if (mips_flag_mdebug < 0)
10626 #ifdef OBJ_MAYBE_ECOFF
10627 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10628 mips_flag_mdebug = 1;
10630 #endif /* OBJ_MAYBE_ECOFF */
10631 mips_flag_mdebug = 0;
10636 mips_init_after_args (void)
10638 /* initialize opcodes */
10639 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10640 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10644 md_pcrel_from (fixS *fixP)
10646 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10647 switch (fixP->fx_r_type)
10649 case BFD_RELOC_16_PCREL_S2:
10650 case BFD_RELOC_MIPS_JMP:
10651 /* Return the address of the delay slot. */
10658 /* This is called before the symbol table is processed. In order to
10659 work with gcc when using mips-tfile, we must keep all local labels.
10660 However, in other cases, we want to discard them. If we were
10661 called with -g, but we didn't see any debugging information, it may
10662 mean that gcc is smuggling debugging information through to
10663 mips-tfile, in which case we must generate all local labels. */
10666 mips_frob_file_before_adjust (void)
10668 #ifndef NO_ECOFF_DEBUGGING
10669 if (ECOFF_DEBUGGING
10671 && ! ecoff_debugging_seen)
10672 flag_keep_locals = 1;
10676 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10677 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10678 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10679 relocation operators.
10681 For our purposes, a %lo() expression matches a %got() or %hi()
10684 (a) it refers to the same symbol; and
10685 (b) the offset applied in the %lo() expression is no lower than
10686 the offset applied in the %got() or %hi().
10688 (b) allows us to cope with code like:
10691 lh $4,%lo(foo+2)($4)
10693 ...which is legal on RELA targets, and has a well-defined behaviour
10694 if the user knows that adding 2 to "foo" will not induce a carry to
10697 When several %lo()s match a particular %got() or %hi(), we use the
10698 following rules to distinguish them:
10700 (1) %lo()s with smaller offsets are a better match than %lo()s with
10703 (2) %lo()s with no matching %got() or %hi() are better than those
10704 that already have a matching %got() or %hi().
10706 (3) later %lo()s are better than earlier %lo()s.
10708 These rules are applied in order.
10710 (1) means, among other things, that %lo()s with identical offsets are
10711 chosen if they exist.
10713 (2) means that we won't associate several high-part relocations with
10714 the same low-part relocation unless there's no alternative. Having
10715 several high parts for the same low part is a GNU extension; this rule
10716 allows careful users to avoid it.
10718 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10719 with the last high-part relocation being at the front of the list.
10720 It therefore makes sense to choose the last matching low-part
10721 relocation, all other things being equal. It's also easier
10722 to code that way. */
10725 mips_frob_file (void)
10727 struct mips_hi_fixup *l;
10729 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10731 segment_info_type *seginfo;
10732 bfd_boolean matched_lo_p;
10733 fixS **hi_pos, **lo_pos, **pos;
10735 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10737 /* If a GOT16 relocation turns out to be against a global symbol,
10738 there isn't supposed to be a matching LO. */
10739 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10740 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10743 /* Check quickly whether the next fixup happens to be a matching %lo. */
10744 if (fixup_has_matching_lo_p (l->fixp))
10747 seginfo = seg_info (l->seg);
10749 /* Set HI_POS to the position of this relocation in the chain.
10750 Set LO_POS to the position of the chosen low-part relocation.
10751 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10752 relocation that matches an immediately-preceding high-part
10756 matched_lo_p = FALSE;
10757 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10759 if (*pos == l->fixp)
10762 if ((*pos)->fx_r_type == BFD_RELOC_LO16
10763 && (*pos)->fx_addsy == l->fixp->fx_addsy
10764 && (*pos)->fx_offset >= l->fixp->fx_offset
10766 || (*pos)->fx_offset < (*lo_pos)->fx_offset
10768 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
10771 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
10772 && fixup_has_matching_lo_p (*pos));
10775 /* If we found a match, remove the high-part relocation from its
10776 current position and insert it before the low-part relocation.
10777 Make the offsets match so that fixup_has_matching_lo_p()
10780 We don't warn about unmatched high-part relocations since some
10781 versions of gcc have been known to emit dead "lui ...%hi(...)"
10783 if (lo_pos != NULL)
10785 l->fixp->fx_offset = (*lo_pos)->fx_offset;
10786 if (l->fixp->fx_next != *lo_pos)
10788 *hi_pos = l->fixp->fx_next;
10789 l->fixp->fx_next = *lo_pos;
10796 /* We may have combined relocations without symbols in the N32/N64 ABI.
10797 We have to prevent gas from dropping them. */
10800 mips_force_relocation (fixS *fixp)
10802 if (generic_force_reloc (fixp))
10806 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10807 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10808 || fixp->fx_r_type == BFD_RELOC_HI16_S
10809 || fixp->fx_r_type == BFD_RELOC_LO16))
10815 /* This hook is called before a fix is simplified. We don't really
10816 decide whether to skip a fix here. Rather, we turn global symbols
10817 used as branch targets into local symbols, such that they undergo
10818 simplification. We can only do this if the symbol is defined and
10819 it is in the same section as the branch. If this doesn't hold, we
10820 emit a better error message than just saying the relocation is not
10821 valid for the selected object format.
10823 FIXP is the fix-up we're going to try to simplify, SEG is the
10824 segment in which the fix up occurs. The return value should be
10825 non-zero to indicate the fix-up is valid for further
10826 simplifications. */
10829 mips_validate_fix (struct fix *fixP, asection *seg)
10831 /* There's a lot of discussion on whether it should be possible to
10832 use R_MIPS_PC16 to represent branch relocations. The outcome
10833 seems to be that it can, but gas/bfd are very broken in creating
10834 RELA relocations for this, so for now we only accept branches to
10835 symbols in the same section. Anything else is of dubious value,
10836 since there's no guarantee that at link time the symbol would be
10837 in range. Even for branches to local symbols this is arguably
10838 wrong, since it we assume the symbol is not going to be
10839 overridden, which should be possible per ELF library semantics,
10840 but then, there isn't a dynamic relocation that could be used to
10841 this effect, and the target would likely be out of range as well.
10843 Unfortunately, it seems that there is too much code out there
10844 that relies on branches to symbols that are global to be resolved
10845 as if they were local, like the IRIX tools do, so we do it as
10846 well, but with a warning so that people are reminded to fix their
10847 code. If we ever get back to using R_MIPS_PC16 for branch
10848 targets, this entire block should go away (and probably the
10849 whole function). */
10851 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
10852 && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
10853 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
10854 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
10857 if (! S_IS_DEFINED (fixP->fx_addsy))
10859 as_bad_where (fixP->fx_file, fixP->fx_line,
10860 _("Cannot branch to undefined symbol."));
10861 /* Avoid any further errors about this fixup. */
10864 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
10866 as_bad_where (fixP->fx_file, fixP->fx_line,
10867 _("Cannot branch to symbol in another section."));
10870 else if (S_IS_EXTERNAL (fixP->fx_addsy))
10872 symbolS *sym = fixP->fx_addsy;
10874 if (mips_pic == SVR4_PIC)
10875 as_warn_where (fixP->fx_file, fixP->fx_line,
10876 _("Pretending global symbol used as branch target is local."));
10878 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
10879 S_GET_SEGMENT (sym),
10881 symbol_get_frag (sym));
10882 copy_symbol_attributes (fixP->fx_addsy, sym);
10883 S_CLEAR_EXTERNAL (fixP->fx_addsy);
10884 assert (symbol_resolved_p (sym));
10885 symbol_mark_resolved (fixP->fx_addsy);
10892 /* Apply a fixup to the object file. */
10895 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10899 static int previous_fx_r_type = 0;
10900 reloc_howto_type *howto;
10902 /* We ignore generic BFD relocations we don't know about. */
10903 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10907 assert (fixP->fx_size == 4
10908 || fixP->fx_r_type == BFD_RELOC_16
10909 || fixP->fx_r_type == BFD_RELOC_64
10910 || fixP->fx_r_type == BFD_RELOC_CTOR
10911 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10912 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10913 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10915 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
10917 /* We are not done if this is a composite relocation to set up gp. */
10918 assert (! fixP->fx_pcrel);
10919 if (fixP->fx_addsy == NULL
10920 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10921 || (fixP->fx_r_type == BFD_RELOC_64
10922 && (previous_fx_r_type == BFD_RELOC_GPREL32
10923 || previous_fx_r_type == BFD_RELOC_GPREL16))
10924 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
10925 && (fixP->fx_r_type == BFD_RELOC_HI16_S
10926 || fixP->fx_r_type == BFD_RELOC_LO16))))
10928 previous_fx_r_type = fixP->fx_r_type;
10930 switch (fixP->fx_r_type)
10932 case BFD_RELOC_MIPS_JMP:
10933 case BFD_RELOC_MIPS_SHIFT5:
10934 case BFD_RELOC_MIPS_SHIFT6:
10935 case BFD_RELOC_MIPS_GOT_DISP:
10936 case BFD_RELOC_MIPS_GOT_PAGE:
10937 case BFD_RELOC_MIPS_GOT_OFST:
10938 case BFD_RELOC_MIPS_SUB:
10939 case BFD_RELOC_MIPS_INSERT_A:
10940 case BFD_RELOC_MIPS_INSERT_B:
10941 case BFD_RELOC_MIPS_DELETE:
10942 case BFD_RELOC_MIPS_HIGHEST:
10943 case BFD_RELOC_MIPS_HIGHER:
10944 case BFD_RELOC_MIPS_SCN_DISP:
10945 case BFD_RELOC_MIPS_REL16:
10946 case BFD_RELOC_MIPS_RELGOT:
10947 case BFD_RELOC_MIPS_JALR:
10948 case BFD_RELOC_HI16:
10949 case BFD_RELOC_HI16_S:
10950 case BFD_RELOC_GPREL16:
10951 case BFD_RELOC_MIPS_LITERAL:
10952 case BFD_RELOC_MIPS_CALL16:
10953 case BFD_RELOC_MIPS_GOT16:
10954 case BFD_RELOC_GPREL32:
10955 case BFD_RELOC_MIPS_GOT_HI16:
10956 case BFD_RELOC_MIPS_GOT_LO16:
10957 case BFD_RELOC_MIPS_CALL_HI16:
10958 case BFD_RELOC_MIPS_CALL_LO16:
10959 case BFD_RELOC_MIPS16_GPREL:
10960 assert (! fixP->fx_pcrel);
10961 /* Nothing needed to do. The value comes from the reloc entry */
10964 case BFD_RELOC_MIPS16_JMP:
10965 /* We currently always generate a reloc against a symbol, which
10966 means that we don't want an addend even if the symbol is
10972 /* This is handled like BFD_RELOC_32, but we output a sign
10973 extended value if we are only 32 bits. */
10976 if (8 <= sizeof (valueT))
10977 md_number_to_chars (buf, *valP, 8);
10982 if ((*valP & 0x80000000) != 0)
10986 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
10988 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
10994 case BFD_RELOC_RVA:
10996 /* If we are deleting this reloc entry, we must fill in the
10997 value now. This can happen if we have a .word which is not
10998 resolved when it appears but is later defined. */
11000 md_number_to_chars (buf, *valP, 4);
11004 /* If we are deleting this reloc entry, we must fill in the
11006 assert (fixP->fx_size == 2);
11008 md_number_to_chars (buf, *valP, 2);
11011 case BFD_RELOC_LO16:
11012 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11013 may be safe to remove, but if so it's not obvious. */
11014 /* When handling an embedded PIC switch statement, we can wind
11015 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11018 if (*valP + 0x8000 > 0xffff)
11019 as_bad_where (fixP->fx_file, fixP->fx_line,
11020 _("relocation overflow"));
11021 if (target_big_endian)
11023 md_number_to_chars (buf, *valP, 2);
11027 case BFD_RELOC_16_PCREL_S2:
11028 if ((*valP & 0x3) != 0)
11029 as_bad_where (fixP->fx_file, fixP->fx_line,
11030 _("Branch to odd address (%lx)"), (long) *valP);
11033 * We need to save the bits in the instruction since fixup_segment()
11034 * might be deleting the relocation entry (i.e., a branch within
11035 * the current segment).
11037 if (! fixP->fx_done)
11040 /* update old instruction data */
11041 if (target_big_endian)
11042 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11044 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11046 if (*valP + 0x20000 <= 0x3ffff)
11048 insn |= (*valP >> 2) & 0xffff;
11049 md_number_to_chars (buf, insn, 4);
11051 else if (mips_pic == NO_PIC
11053 && fixP->fx_frag->fr_address >= text_section->vma
11054 && (fixP->fx_frag->fr_address
11055 < text_section->vma + bfd_get_section_size (text_section))
11056 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11057 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11058 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11060 /* The branch offset is too large. If this is an
11061 unconditional branch, and we are not generating PIC code,
11062 we can convert it to an absolute jump instruction. */
11063 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11064 insn = 0x0c000000; /* jal */
11066 insn = 0x08000000; /* j */
11067 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11069 fixP->fx_addsy = section_symbol (text_section);
11070 *valP += md_pcrel_from (fixP);
11071 md_number_to_chars (buf, insn, 4);
11075 /* If we got here, we have branch-relaxation disabled,
11076 and there's nothing we can do to fix this instruction
11077 without turning it into a longer sequence. */
11078 as_bad_where (fixP->fx_file, fixP->fx_line,
11079 _("Branch out of range"));
11083 case BFD_RELOC_VTABLE_INHERIT:
11086 && !S_IS_DEFINED (fixP->fx_addsy)
11087 && !S_IS_WEAK (fixP->fx_addsy))
11088 S_SET_WEAK (fixP->fx_addsy);
11091 case BFD_RELOC_VTABLE_ENTRY:
11099 /* Remember value for tc_gen_reloc. */
11100 fixP->fx_addnumber = *valP;
11105 printInsn (unsigned long oc)
11107 const struct mips_opcode *p;
11108 int treg, sreg, dreg, shamt;
11113 for (i = 0; i < NUMOPCODES; ++i)
11115 p = &mips_opcodes[i];
11116 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11118 printf ("%08lx %s\t", oc, p->name);
11119 treg = (oc >> 16) & 0x1f;
11120 sreg = (oc >> 21) & 0x1f;
11121 dreg = (oc >> 11) & 0x1f;
11122 shamt = (oc >> 6) & 0x1f;
11124 for (args = p->args;; ++args)
11135 printf ("%c", *args);
11139 assert (treg == sreg);
11140 printf ("$%d,$%d", treg, sreg);
11145 printf ("$%d", dreg);
11150 printf ("$%d", treg);
11154 printf ("0x%x", treg);
11159 printf ("$%d", sreg);
11163 printf ("0x%08lx", oc & 0x1ffffff);
11170 printf ("%d", imm);
11175 printf ("$%d", shamt);
11186 printf (_("%08lx UNDEFINED\n"), oc);
11197 name = input_line_pointer;
11198 c = get_symbol_end ();
11199 p = (symbolS *) symbol_find_or_make (name);
11200 *input_line_pointer = c;
11204 /* Align the current frag to a given power of two. The MIPS assembler
11205 also automatically adjusts any preceding label. */
11208 mips_align (int to, int fill, symbolS *label)
11210 mips_emit_delays (FALSE);
11211 frag_align (to, fill, 0);
11212 record_alignment (now_seg, to);
11215 assert (S_GET_SEGMENT (label) == now_seg);
11216 symbol_set_frag (label, frag_now);
11217 S_SET_VALUE (label, (valueT) frag_now_fix ());
11221 /* Align to a given power of two. .align 0 turns off the automatic
11222 alignment used by the data creating pseudo-ops. */
11225 s_align (int x ATTRIBUTE_UNUSED)
11228 register long temp_fill;
11229 long max_alignment = 15;
11233 o Note that the assembler pulls down any immediately preceding label
11234 to the aligned address.
11235 o It's not documented but auto alignment is reinstated by
11236 a .align pseudo instruction.
11237 o Note also that after auto alignment is turned off the mips assembler
11238 issues an error on attempt to assemble an improperly aligned data item.
11243 temp = get_absolute_expression ();
11244 if (temp > max_alignment)
11245 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11248 as_warn (_("Alignment negative: 0 assumed."));
11251 if (*input_line_pointer == ',')
11253 ++input_line_pointer;
11254 temp_fill = get_absolute_expression ();
11261 mips_align (temp, (int) temp_fill,
11262 insn_labels != NULL ? insn_labels->label : NULL);
11269 demand_empty_rest_of_line ();
11273 mips_flush_pending_output (void)
11275 mips_emit_delays (FALSE);
11276 mips_clear_insn_labels ();
11280 s_change_sec (int sec)
11285 /* The ELF backend needs to know that we are changing sections, so
11286 that .previous works correctly. We could do something like check
11287 for an obj_section_change_hook macro, but that might be confusing
11288 as it would not be appropriate to use it in the section changing
11289 functions in read.c, since obj-elf.c intercepts those. FIXME:
11290 This should be cleaner, somehow. */
11291 obj_elf_section_change_hook ();
11294 mips_emit_delays (FALSE);
11304 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11305 demand_empty_rest_of_line ();
11309 seg = subseg_new (RDATA_SECTION_NAME,
11310 (subsegT) get_absolute_expression ());
11311 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11313 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11314 | SEC_READONLY | SEC_RELOC
11316 if (strcmp (TARGET_OS, "elf") != 0)
11317 record_alignment (seg, 4);
11319 demand_empty_rest_of_line ();
11323 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11324 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11326 bfd_set_section_flags (stdoutput, seg,
11327 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11328 if (strcmp (TARGET_OS, "elf") != 0)
11329 record_alignment (seg, 4);
11331 demand_empty_rest_of_line ();
11339 s_change_section (int ignore ATTRIBUTE_UNUSED)
11342 char *section_name;
11347 int section_entry_size;
11348 int section_alignment;
11350 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11353 section_name = input_line_pointer;
11354 c = get_symbol_end ();
11356 next_c = *(input_line_pointer + 1);
11358 /* Do we have .section Name<,"flags">? */
11359 if (c != ',' || (c == ',' && next_c == '"'))
11361 /* just after name is now '\0'. */
11362 *input_line_pointer = c;
11363 input_line_pointer = section_name;
11364 obj_elf_section (ignore);
11367 input_line_pointer++;
11369 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11371 section_type = get_absolute_expression ();
11374 if (*input_line_pointer++ == ',')
11375 section_flag = get_absolute_expression ();
11378 if (*input_line_pointer++ == ',')
11379 section_entry_size = get_absolute_expression ();
11381 section_entry_size = 0;
11382 if (*input_line_pointer++ == ',')
11383 section_alignment = get_absolute_expression ();
11385 section_alignment = 0;
11387 section_name = xstrdup (section_name);
11389 /* When using the generic form of .section (as implemented by obj-elf.c),
11390 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11391 traditionally had to fall back on the more common @progbits instead.
11393 There's nothing really harmful in this, since bfd will correct
11394 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11395 means that, for backwards compatibiltiy, the special_section entries
11396 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11398 Even so, we shouldn't force users of the MIPS .section syntax to
11399 incorrectly label the sections as SHT_PROGBITS. The best compromise
11400 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11401 generic type-checking code. */
11402 if (section_type == SHT_MIPS_DWARF)
11403 section_type = SHT_PROGBITS;
11405 obj_elf_change_section (section_name, section_type, section_flag,
11406 section_entry_size, 0, 0, 0);
11408 if (now_seg->name != section_name)
11409 free (section_name);
11410 #endif /* OBJ_ELF */
11414 mips_enable_auto_align (void)
11420 s_cons (int log_size)
11424 label = insn_labels != NULL ? insn_labels->label : NULL;
11425 mips_emit_delays (FALSE);
11426 if (log_size > 0 && auto_align)
11427 mips_align (log_size, 0, label);
11428 mips_clear_insn_labels ();
11429 cons (1 << log_size);
11433 s_float_cons (int type)
11437 label = insn_labels != NULL ? insn_labels->label : NULL;
11439 mips_emit_delays (FALSE);
11444 mips_align (3, 0, label);
11446 mips_align (2, 0, label);
11449 mips_clear_insn_labels ();
11454 /* Handle .globl. We need to override it because on Irix 5 you are
11457 where foo is an undefined symbol, to mean that foo should be
11458 considered to be the address of a function. */
11461 s_mips_globl (int x ATTRIBUTE_UNUSED)
11468 name = input_line_pointer;
11469 c = get_symbol_end ();
11470 symbolP = symbol_find_or_make (name);
11471 *input_line_pointer = c;
11472 SKIP_WHITESPACE ();
11474 /* On Irix 5, every global symbol that is not explicitly labelled as
11475 being a function is apparently labelled as being an object. */
11478 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11483 secname = input_line_pointer;
11484 c = get_symbol_end ();
11485 sec = bfd_get_section_by_name (stdoutput, secname);
11487 as_bad (_("%s: no such section"), secname);
11488 *input_line_pointer = c;
11490 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11491 flag = BSF_FUNCTION;
11494 symbol_get_bfdsym (symbolP)->flags |= flag;
11496 S_SET_EXTERNAL (symbolP);
11497 demand_empty_rest_of_line ();
11501 s_option (int x ATTRIBUTE_UNUSED)
11506 opt = input_line_pointer;
11507 c = get_symbol_end ();
11511 /* FIXME: What does this mean? */
11513 else if (strncmp (opt, "pic", 3) == 0)
11517 i = atoi (opt + 3);
11522 mips_pic = SVR4_PIC;
11523 mips_abicalls = TRUE;
11526 as_bad (_(".option pic%d not supported"), i);
11528 if (mips_pic == SVR4_PIC)
11530 if (g_switch_seen && g_switch_value != 0)
11531 as_warn (_("-G may not be used with SVR4 PIC code"));
11532 g_switch_value = 0;
11533 bfd_set_gp_size (stdoutput, 0);
11537 as_warn (_("Unrecognized option \"%s\""), opt);
11539 *input_line_pointer = c;
11540 demand_empty_rest_of_line ();
11543 /* This structure is used to hold a stack of .set values. */
11545 struct mips_option_stack
11547 struct mips_option_stack *next;
11548 struct mips_set_options options;
11551 static struct mips_option_stack *mips_opts_stack;
11553 /* Handle the .set pseudo-op. */
11556 s_mipsset (int x ATTRIBUTE_UNUSED)
11558 char *name = input_line_pointer, ch;
11560 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11561 ++input_line_pointer;
11562 ch = *input_line_pointer;
11563 *input_line_pointer = '\0';
11565 if (strcmp (name, "reorder") == 0)
11567 if (mips_opts.noreorder && prev_nop_frag != NULL)
11569 /* If we still have pending nops, we can discard them. The
11570 usual nop handling will insert any that are still
11572 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11573 * (mips_opts.mips16 ? 2 : 4));
11574 prev_nop_frag = NULL;
11576 mips_opts.noreorder = 0;
11578 else if (strcmp (name, "noreorder") == 0)
11580 mips_emit_delays (TRUE);
11581 mips_opts.noreorder = 1;
11582 mips_any_noreorder = 1;
11584 else if (strcmp (name, "at") == 0)
11586 mips_opts.noat = 0;
11588 else if (strcmp (name, "noat") == 0)
11590 mips_opts.noat = 1;
11592 else if (strcmp (name, "macro") == 0)
11594 mips_opts.warn_about_macros = 0;
11596 else if (strcmp (name, "nomacro") == 0)
11598 if (mips_opts.noreorder == 0)
11599 as_bad (_("`noreorder' must be set before `nomacro'"));
11600 mips_opts.warn_about_macros = 1;
11602 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11604 mips_opts.nomove = 0;
11606 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11608 mips_opts.nomove = 1;
11610 else if (strcmp (name, "bopt") == 0)
11612 mips_opts.nobopt = 0;
11614 else if (strcmp (name, "nobopt") == 0)
11616 mips_opts.nobopt = 1;
11618 else if (strcmp (name, "mips16") == 0
11619 || strcmp (name, "MIPS-16") == 0)
11620 mips_opts.mips16 = 1;
11621 else if (strcmp (name, "nomips16") == 0
11622 || strcmp (name, "noMIPS-16") == 0)
11623 mips_opts.mips16 = 0;
11624 else if (strcmp (name, "mips3d") == 0)
11625 mips_opts.ase_mips3d = 1;
11626 else if (strcmp (name, "nomips3d") == 0)
11627 mips_opts.ase_mips3d = 0;
11628 else if (strcmp (name, "mdmx") == 0)
11629 mips_opts.ase_mdmx = 1;
11630 else if (strcmp (name, "nomdmx") == 0)
11631 mips_opts.ase_mdmx = 0;
11632 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11636 /* Permit the user to change the ISA and architecture on the fly.
11637 Needless to say, misuse can cause serious problems. */
11638 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11641 mips_opts.isa = file_mips_isa;
11642 mips_opts.arch = file_mips_arch;
11644 else if (strncmp (name, "arch=", 5) == 0)
11646 const struct mips_cpu_info *p;
11648 p = mips_parse_cpu("internal use", name + 5);
11650 as_bad (_("unknown architecture %s"), name + 5);
11653 mips_opts.arch = p->cpu;
11654 mips_opts.isa = p->isa;
11657 else if (strncmp (name, "mips", 4) == 0)
11659 const struct mips_cpu_info *p;
11661 p = mips_parse_cpu("internal use", name);
11663 as_bad (_("unknown ISA level %s"), name + 4);
11666 mips_opts.arch = p->cpu;
11667 mips_opts.isa = p->isa;
11671 as_bad (_("unknown ISA or architecture %s"), name);
11673 switch (mips_opts.isa)
11681 mips_opts.gp32 = 1;
11682 mips_opts.fp32 = 1;
11689 mips_opts.gp32 = 0;
11690 mips_opts.fp32 = 0;
11693 as_bad (_("unknown ISA level %s"), name + 4);
11698 mips_opts.gp32 = file_mips_gp32;
11699 mips_opts.fp32 = file_mips_fp32;
11702 else if (strcmp (name, "autoextend") == 0)
11703 mips_opts.noautoextend = 0;
11704 else if (strcmp (name, "noautoextend") == 0)
11705 mips_opts.noautoextend = 1;
11706 else if (strcmp (name, "push") == 0)
11708 struct mips_option_stack *s;
11710 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11711 s->next = mips_opts_stack;
11712 s->options = mips_opts;
11713 mips_opts_stack = s;
11715 else if (strcmp (name, "pop") == 0)
11717 struct mips_option_stack *s;
11719 s = mips_opts_stack;
11721 as_bad (_(".set pop with no .set push"));
11724 /* If we're changing the reorder mode we need to handle
11725 delay slots correctly. */
11726 if (s->options.noreorder && ! mips_opts.noreorder)
11727 mips_emit_delays (TRUE);
11728 else if (! s->options.noreorder && mips_opts.noreorder)
11730 if (prev_nop_frag != NULL)
11732 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11733 * (mips_opts.mips16 ? 2 : 4));
11734 prev_nop_frag = NULL;
11738 mips_opts = s->options;
11739 mips_opts_stack = s->next;
11745 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11747 *input_line_pointer = ch;
11748 demand_empty_rest_of_line ();
11751 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11752 .option pic2. It means to generate SVR4 PIC calls. */
11755 s_abicalls (int ignore ATTRIBUTE_UNUSED)
11757 mips_pic = SVR4_PIC;
11758 mips_abicalls = TRUE;
11760 if (g_switch_seen && g_switch_value != 0)
11761 as_warn (_("-G may not be used with SVR4 PIC code"));
11762 g_switch_value = 0;
11764 bfd_set_gp_size (stdoutput, 0);
11765 demand_empty_rest_of_line ();
11768 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11769 PIC code. It sets the $gp register for the function based on the
11770 function address, which is in the register named in the argument.
11771 This uses a relocation against _gp_disp, which is handled specially
11772 by the linker. The result is:
11773 lui $gp,%hi(_gp_disp)
11774 addiu $gp,$gp,%lo(_gp_disp)
11775 addu $gp,$gp,.cpload argument
11776 The .cpload argument is normally $25 == $t9. */
11779 s_cpload (int ignore ATTRIBUTE_UNUSED)
11783 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11784 .cpload is ignored. */
11785 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11791 /* .cpload should be in a .set noreorder section. */
11792 if (mips_opts.noreorder == 0)
11793 as_warn (_(".cpload not in noreorder section"));
11795 ex.X_op = O_symbol;
11796 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11797 ex.X_op_symbol = NULL;
11798 ex.X_add_number = 0;
11800 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11801 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11804 macro_build_lui (&ex, mips_gp_register);
11805 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
11806 mips_gp_register, BFD_RELOC_LO16);
11807 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
11808 mips_gp_register, tc_get_register (0));
11811 demand_empty_rest_of_line ();
11814 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11815 .cpsetup $reg1, offset|$reg2, label
11817 If offset is given, this results in:
11818 sd $gp, offset($sp)
11819 lui $gp, %hi(%neg(%gp_rel(label)))
11820 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11821 daddu $gp, $gp, $reg1
11823 If $reg2 is given, this results in:
11824 daddu $reg2, $gp, $0
11825 lui $gp, %hi(%neg(%gp_rel(label)))
11826 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11827 daddu $gp, $gp, $reg1
11828 $reg1 is normally $25 == $t9. */
11830 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
11832 expressionS ex_off;
11833 expressionS ex_sym;
11837 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11838 We also need NewABI support. */
11839 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11845 reg1 = tc_get_register (0);
11846 SKIP_WHITESPACE ();
11847 if (*input_line_pointer != ',')
11849 as_bad (_("missing argument separator ',' for .cpsetup"));
11853 ++input_line_pointer;
11854 SKIP_WHITESPACE ();
11855 if (*input_line_pointer == '$')
11857 mips_cpreturn_register = tc_get_register (0);
11858 mips_cpreturn_offset = -1;
11862 mips_cpreturn_offset = get_absolute_expression ();
11863 mips_cpreturn_register = -1;
11865 SKIP_WHITESPACE ();
11866 if (*input_line_pointer != ',')
11868 as_bad (_("missing argument separator ',' for .cpsetup"));
11872 ++input_line_pointer;
11873 SKIP_WHITESPACE ();
11874 expression (&ex_sym);
11877 if (mips_cpreturn_register == -1)
11879 ex_off.X_op = O_constant;
11880 ex_off.X_add_symbol = NULL;
11881 ex_off.X_op_symbol = NULL;
11882 ex_off.X_add_number = mips_cpreturn_offset;
11884 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
11885 BFD_RELOC_LO16, SP);
11888 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
11889 mips_gp_register, 0);
11891 /* Ensure there's room for the next two instructions, so that `f'
11892 doesn't end up with an address in the wrong frag. */
11895 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
11896 fix_new (frag_now, f - frag_now->fr_literal,
11897 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11898 fix_new (frag_now, f - frag_now->fr_literal,
11899 4, NULL, 0, 0, BFD_RELOC_HI16_S);
11902 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
11903 mips_gp_register, BFD_RELOC_GPREL16);
11904 fix_new (frag_now, f - frag_now->fr_literal,
11905 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11906 fix_new (frag_now, f - frag_now->fr_literal,
11907 4, NULL, 0, 0, BFD_RELOC_LO16);
11909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
11910 mips_gp_register, reg1);
11913 demand_empty_rest_of_line ();
11917 s_cplocal (int ignore ATTRIBUTE_UNUSED)
11919 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11920 .cplocal is ignored. */
11921 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11927 mips_gp_register = tc_get_register (0);
11928 demand_empty_rest_of_line ();
11931 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11932 offset from $sp. The offset is remembered, and after making a PIC
11933 call $gp is restored from that location. */
11936 s_cprestore (int ignore ATTRIBUTE_UNUSED)
11940 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11941 .cprestore is ignored. */
11942 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11948 mips_cprestore_offset = get_absolute_expression ();
11949 mips_cprestore_valid = 1;
11951 ex.X_op = O_constant;
11952 ex.X_add_symbol = NULL;
11953 ex.X_op_symbol = NULL;
11954 ex.X_add_number = mips_cprestore_offset;
11957 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
11958 SP, HAVE_64BIT_ADDRESSES);
11961 demand_empty_rest_of_line ();
11964 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11965 was given in the preceding .cpsetup, it results in:
11966 ld $gp, offset($sp)
11968 If a register $reg2 was given there, it results in:
11969 daddu $gp, $reg2, $0
11972 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
11976 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11977 We also need NewABI support. */
11978 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11985 if (mips_cpreturn_register == -1)
11987 ex.X_op = O_constant;
11988 ex.X_add_symbol = NULL;
11989 ex.X_op_symbol = NULL;
11990 ex.X_add_number = mips_cpreturn_offset;
11992 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
11995 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
11996 mips_cpreturn_register, 0);
11999 demand_empty_rest_of_line ();
12002 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12003 code. It sets the offset to use in gp_rel relocations. */
12006 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12008 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12009 We also need NewABI support. */
12010 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12016 mips_gprel_offset = get_absolute_expression ();
12018 demand_empty_rest_of_line ();
12021 /* Handle the .gpword pseudo-op. This is used when generating PIC
12022 code. It generates a 32 bit GP relative reloc. */
12025 s_gpword (int ignore ATTRIBUTE_UNUSED)
12031 /* When not generating PIC code, this is treated as .word. */
12032 if (mips_pic != SVR4_PIC)
12038 label = insn_labels != NULL ? insn_labels->label : NULL;
12039 mips_emit_delays (TRUE);
12041 mips_align (2, 0, label);
12042 mips_clear_insn_labels ();
12046 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12048 as_bad (_("Unsupported use of .gpword"));
12049 ignore_rest_of_line ();
12053 md_number_to_chars (p, 0, 4);
12054 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12055 BFD_RELOC_GPREL32);
12057 demand_empty_rest_of_line ();
12061 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12067 /* When not generating PIC code, this is treated as .dword. */
12068 if (mips_pic != SVR4_PIC)
12074 label = insn_labels != NULL ? insn_labels->label : NULL;
12075 mips_emit_delays (TRUE);
12077 mips_align (3, 0, label);
12078 mips_clear_insn_labels ();
12082 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12084 as_bad (_("Unsupported use of .gpdword"));
12085 ignore_rest_of_line ();
12089 md_number_to_chars (p, 0, 8);
12090 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12091 BFD_RELOC_GPREL32);
12093 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12094 ex.X_op = O_absent;
12095 ex.X_add_symbol = 0;
12096 ex.X_add_number = 0;
12097 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12100 demand_empty_rest_of_line ();
12103 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12104 tables in SVR4 PIC code. */
12107 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12111 /* This is ignored when not generating SVR4 PIC code. */
12112 if (mips_pic != SVR4_PIC)
12118 /* Add $gp to the register named as an argument. */
12120 reg = tc_get_register (0);
12121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12124 demand_empty_rest_of_line ();
12127 /* Handle the .insn pseudo-op. This marks instruction labels in
12128 mips16 mode. This permits the linker to handle them specially,
12129 such as generating jalx instructions when needed. We also make
12130 them odd for the duration of the assembly, in order to generate the
12131 right sort of code. We will make them even in the adjust_symtab
12132 routine, while leaving them marked. This is convenient for the
12133 debugger and the disassembler. The linker knows to make them odd
12137 s_insn (int ignore ATTRIBUTE_UNUSED)
12139 mips16_mark_labels ();
12141 demand_empty_rest_of_line ();
12144 /* Handle a .stabn directive. We need these in order to mark a label
12145 as being a mips16 text label correctly. Sometimes the compiler
12146 will emit a label, followed by a .stabn, and then switch sections.
12147 If the label and .stabn are in mips16 mode, then the label is
12148 really a mips16 text label. */
12151 s_mips_stab (int type)
12154 mips16_mark_labels ();
12159 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12163 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12170 name = input_line_pointer;
12171 c = get_symbol_end ();
12172 symbolP = symbol_find_or_make (name);
12173 S_SET_WEAK (symbolP);
12174 *input_line_pointer = c;
12176 SKIP_WHITESPACE ();
12178 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12180 if (S_IS_DEFINED (symbolP))
12182 as_bad ("ignoring attempt to redefine symbol %s",
12183 S_GET_NAME (symbolP));
12184 ignore_rest_of_line ();
12188 if (*input_line_pointer == ',')
12190 ++input_line_pointer;
12191 SKIP_WHITESPACE ();
12195 if (exp.X_op != O_symbol)
12197 as_bad ("bad .weakext directive");
12198 ignore_rest_of_line ();
12201 symbol_set_value_expression (symbolP, &exp);
12204 demand_empty_rest_of_line ();
12207 /* Parse a register string into a number. Called from the ECOFF code
12208 to parse .frame. The argument is non-zero if this is the frame
12209 register, so that we can record it in mips_frame_reg. */
12212 tc_get_register (int frame)
12216 SKIP_WHITESPACE ();
12217 if (*input_line_pointer++ != '$')
12219 as_warn (_("expected `$'"));
12222 else if (ISDIGIT (*input_line_pointer))
12224 reg = get_absolute_expression ();
12225 if (reg < 0 || reg >= 32)
12227 as_warn (_("Bad register number"));
12233 if (strncmp (input_line_pointer, "ra", 2) == 0)
12236 input_line_pointer += 2;
12238 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12241 input_line_pointer += 2;
12243 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12246 input_line_pointer += 2;
12248 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12251 input_line_pointer += 2;
12253 else if (strncmp (input_line_pointer, "at", 2) == 0)
12256 input_line_pointer += 2;
12258 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12261 input_line_pointer += 3;
12263 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12266 input_line_pointer += 3;
12268 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12271 input_line_pointer += 4;
12275 as_warn (_("Unrecognized register name"));
12277 while (ISALNUM(*input_line_pointer))
12278 input_line_pointer++;
12283 mips_frame_reg = reg != 0 ? reg : SP;
12284 mips_frame_reg_valid = 1;
12285 mips_cprestore_valid = 0;
12291 md_section_align (asection *seg, valueT addr)
12293 int align = bfd_get_section_alignment (stdoutput, seg);
12296 /* We don't need to align ELF sections to the full alignment.
12297 However, Irix 5 may prefer that we align them at least to a 16
12298 byte boundary. We don't bother to align the sections if we are
12299 targeted for an embedded system. */
12300 if (strcmp (TARGET_OS, "elf") == 0)
12306 return ((addr + (1 << align) - 1) & (-1 << align));
12309 /* Utility routine, called from above as well. If called while the
12310 input file is still being read, it's only an approximation. (For
12311 example, a symbol may later become defined which appeared to be
12312 undefined earlier.) */
12315 nopic_need_relax (symbolS *sym, int before_relaxing)
12320 if (g_switch_value > 0)
12322 const char *symname;
12325 /* Find out whether this symbol can be referenced off the $gp
12326 register. It can be if it is smaller than the -G size or if
12327 it is in the .sdata or .sbss section. Certain symbols can
12328 not be referenced off the $gp, although it appears as though
12330 symname = S_GET_NAME (sym);
12331 if (symname != (const char *) NULL
12332 && (strcmp (symname, "eprol") == 0
12333 || strcmp (symname, "etext") == 0
12334 || strcmp (symname, "_gp") == 0
12335 || strcmp (symname, "edata") == 0
12336 || strcmp (symname, "_fbss") == 0
12337 || strcmp (symname, "_fdata") == 0
12338 || strcmp (symname, "_ftext") == 0
12339 || strcmp (symname, "end") == 0
12340 || strcmp (symname, "_gp_disp") == 0))
12342 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12344 #ifndef NO_ECOFF_DEBUGGING
12345 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12346 && (symbol_get_obj (sym)->ecoff_extern_size
12347 <= g_switch_value))
12349 /* We must defer this decision until after the whole
12350 file has been read, since there might be a .extern
12351 after the first use of this symbol. */
12352 || (before_relaxing
12353 #ifndef NO_ECOFF_DEBUGGING
12354 && symbol_get_obj (sym)->ecoff_extern_size == 0
12356 && S_GET_VALUE (sym) == 0)
12357 || (S_GET_VALUE (sym) != 0
12358 && S_GET_VALUE (sym) <= g_switch_value)))
12362 const char *segname;
12364 segname = segment_name (S_GET_SEGMENT (sym));
12365 assert (strcmp (segname, ".lit8") != 0
12366 && strcmp (segname, ".lit4") != 0);
12367 change = (strcmp (segname, ".sdata") != 0
12368 && strcmp (segname, ".sbss") != 0
12369 && strncmp (segname, ".sdata.", 7) != 0
12370 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12375 /* We are not optimizing for the $gp register. */
12380 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12383 pic_need_relax (symbolS *sym, asection *segtype)
12386 bfd_boolean linkonce;
12388 /* Handle the case of a symbol equated to another symbol. */
12389 while (symbol_equated_reloc_p (sym))
12393 /* It's possible to get a loop here in a badly written
12395 n = symbol_get_value_expression (sym)->X_add_symbol;
12401 symsec = S_GET_SEGMENT (sym);
12403 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12405 if (symsec != segtype && ! S_IS_LOCAL (sym))
12407 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12411 /* The GNU toolchain uses an extension for ELF: a section
12412 beginning with the magic string .gnu.linkonce is a linkonce
12414 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12415 sizeof ".gnu.linkonce" - 1) == 0)
12419 /* This must duplicate the test in adjust_reloc_syms. */
12420 return (symsec != &bfd_und_section
12421 && symsec != &bfd_abs_section
12422 && ! bfd_is_com_section (symsec)
12425 /* A global or weak symbol is treated as external. */
12426 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12427 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12433 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12434 extended opcode. SEC is the section the frag is in. */
12437 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12440 register const struct mips16_immed_operand *op;
12442 int mintiny, maxtiny;
12446 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12448 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12451 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12452 op = mips16_immed_operands;
12453 while (op->type != type)
12456 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12461 if (type == '<' || type == '>' || type == '[' || type == ']')
12464 maxtiny = 1 << op->nbits;
12469 maxtiny = (1 << op->nbits) - 1;
12474 mintiny = - (1 << (op->nbits - 1));
12475 maxtiny = (1 << (op->nbits - 1)) - 1;
12478 sym_frag = symbol_get_frag (fragp->fr_symbol);
12479 val = S_GET_VALUE (fragp->fr_symbol);
12480 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12486 /* We won't have the section when we are called from
12487 mips_relax_frag. However, we will always have been called
12488 from md_estimate_size_before_relax first. If this is a
12489 branch to a different section, we mark it as such. If SEC is
12490 NULL, and the frag is not marked, then it must be a branch to
12491 the same section. */
12494 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12499 /* Must have been called from md_estimate_size_before_relax. */
12502 fragp->fr_subtype =
12503 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12505 /* FIXME: We should support this, and let the linker
12506 catch branches and loads that are out of range. */
12507 as_bad_where (fragp->fr_file, fragp->fr_line,
12508 _("unsupported PC relative reference to different section"));
12512 if (fragp != sym_frag && sym_frag->fr_address == 0)
12513 /* Assume non-extended on the first relaxation pass.
12514 The address we have calculated will be bogus if this is
12515 a forward branch to another frag, as the forward frag
12516 will have fr_address == 0. */
12520 /* In this case, we know for sure that the symbol fragment is in
12521 the same section. If the relax_marker of the symbol fragment
12522 differs from the relax_marker of this fragment, we have not
12523 yet adjusted the symbol fragment fr_address. We want to add
12524 in STRETCH in order to get a better estimate of the address.
12525 This particularly matters because of the shift bits. */
12527 && sym_frag->relax_marker != fragp->relax_marker)
12531 /* Adjust stretch for any alignment frag. Note that if have
12532 been expanding the earlier code, the symbol may be
12533 defined in what appears to be an earlier frag. FIXME:
12534 This doesn't handle the fr_subtype field, which specifies
12535 a maximum number of bytes to skip when doing an
12537 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12539 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12542 stretch = - ((- stretch)
12543 & ~ ((1 << (int) f->fr_offset) - 1));
12545 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12554 addr = fragp->fr_address + fragp->fr_fix;
12556 /* The base address rules are complicated. The base address of
12557 a branch is the following instruction. The base address of a
12558 PC relative load or add is the instruction itself, but if it
12559 is in a delay slot (in which case it can not be extended) use
12560 the address of the instruction whose delay slot it is in. */
12561 if (type == 'p' || type == 'q')
12565 /* If we are currently assuming that this frag should be
12566 extended, then, the current address is two bytes
12568 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12571 /* Ignore the low bit in the target, since it will be set
12572 for a text label. */
12573 if ((val & 1) != 0)
12576 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12578 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12581 val -= addr & ~ ((1 << op->shift) - 1);
12583 /* Branch offsets have an implicit 0 in the lowest bit. */
12584 if (type == 'p' || type == 'q')
12587 /* If any of the shifted bits are set, we must use an extended
12588 opcode. If the address depends on the size of this
12589 instruction, this can lead to a loop, so we arrange to always
12590 use an extended opcode. We only check this when we are in
12591 the main relaxation loop, when SEC is NULL. */
12592 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12594 fragp->fr_subtype =
12595 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12599 /* If we are about to mark a frag as extended because the value
12600 is precisely maxtiny + 1, then there is a chance of an
12601 infinite loop as in the following code:
12606 In this case when the la is extended, foo is 0x3fc bytes
12607 away, so the la can be shrunk, but then foo is 0x400 away, so
12608 the la must be extended. To avoid this loop, we mark the
12609 frag as extended if it was small, and is about to become
12610 extended with a value of maxtiny + 1. */
12611 if (val == ((maxtiny + 1) << op->shift)
12612 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12615 fragp->fr_subtype =
12616 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12620 else if (symsec != absolute_section && sec != NULL)
12621 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12623 if ((val & ((1 << op->shift) - 1)) != 0
12624 || val < (mintiny << op->shift)
12625 || val > (maxtiny << op->shift))
12631 /* Compute the length of a branch sequence, and adjust the
12632 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12633 worst-case length is computed, with UPDATE being used to indicate
12634 whether an unconditional (-1), branch-likely (+1) or regular (0)
12635 branch is to be computed. */
12637 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12639 bfd_boolean toofar;
12643 && S_IS_DEFINED (fragp->fr_symbol)
12644 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12649 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12651 addr = fragp->fr_address + fragp->fr_fix + 4;
12655 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12658 /* If the symbol is not defined or it's in a different segment,
12659 assume the user knows what's going on and emit a short
12665 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12667 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12668 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12669 RELAX_BRANCH_LINK (fragp->fr_subtype),
12675 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12678 if (mips_pic != NO_PIC)
12680 /* Additional space for PIC loading of target address. */
12682 if (mips_opts.isa == ISA_MIPS1)
12683 /* Additional space for $at-stabilizing nop. */
12687 /* If branch is conditional. */
12688 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12695 /* Estimate the size of a frag before relaxing. Unless this is the
12696 mips16, we are not really relaxing here, and the final size is
12697 encoded in the subtype information. For the mips16, we have to
12698 decide whether we are using an extended opcode or not. */
12701 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12705 if (RELAX_BRANCH_P (fragp->fr_subtype))
12708 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12710 return fragp->fr_var;
12713 if (RELAX_MIPS16_P (fragp->fr_subtype))
12714 /* We don't want to modify the EXTENDED bit here; it might get us
12715 into infinite loops. We change it only in mips_relax_frag(). */
12716 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12718 if (mips_pic == NO_PIC)
12719 change = nopic_need_relax (fragp->fr_symbol, 0);
12720 else if (mips_pic == SVR4_PIC)
12721 change = pic_need_relax (fragp->fr_symbol, segtype);
12727 fragp->fr_subtype |= RELAX_USE_SECOND;
12728 return -RELAX_FIRST (fragp->fr_subtype);
12731 return -RELAX_SECOND (fragp->fr_subtype);
12734 /* This is called to see whether a reloc against a defined symbol
12735 should be converted into a reloc against a section. */
12738 mips_fix_adjustable (fixS *fixp)
12740 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12741 about the format of the offset in the .o file. */
12742 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12745 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12746 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12749 if (fixp->fx_addsy == NULL)
12752 /* If symbol SYM is in a mergeable section, relocations of the form
12753 SYM + 0 can usually be made section-relative. The mergeable data
12754 is then identified by the section offset rather than by the symbol.
12756 However, if we're generating REL LO16 relocations, the offset is split
12757 between the LO16 and parterning high part relocation. The linker will
12758 need to recalculate the complete offset in order to correctly identify
12761 The linker has traditionally not looked for the parterning high part
12762 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12763 placed anywhere. Rather than break backwards compatibility by changing
12764 this, it seems better not to force the issue, and instead keep the
12765 original symbol. This will work with either linker behavior. */
12766 if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
12767 && HAVE_IN_PLACE_ADDENDS
12768 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
12772 /* Don't adjust relocations against mips16 symbols, so that the linker
12773 can find them if it needs to set up a stub. */
12774 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12775 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12776 && fixp->fx_subsy == NULL)
12783 /* Translate internal representation of relocation info to BFD target
12787 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12789 static arelent *retval[4];
12791 bfd_reloc_code_real_type code;
12793 memset (retval, 0, sizeof(retval));
12794 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
12795 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12796 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12797 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12799 assert (! fixp->fx_pcrel);
12800 reloc->addend = fixp->fx_addnumber;
12802 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12803 entry to be used in the relocation's section offset. */
12804 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12806 reloc->address = reloc->addend;
12810 code = fixp->fx_r_type;
12812 /* To support a PC relative reloc, we used a Cygnus extension.
12813 We check for that here to make sure that we don't let such a
12814 reloc escape normally. (FIXME: This was formerly used by
12815 embedded-PIC support, but is now used by branch handling in
12816 general. That probably should be fixed.) */
12817 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12818 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12819 && code == BFD_RELOC_16_PCREL_S2)
12820 reloc->howto = NULL;
12822 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12824 if (reloc->howto == NULL)
12826 as_bad_where (fixp->fx_file, fixp->fx_line,
12827 _("Can not represent %s relocation in this object file format"),
12828 bfd_get_reloc_code_name (code));
12835 /* Relax a machine dependent frag. This returns the amount by which
12836 the current size of the frag should change. */
12839 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
12841 if (RELAX_BRANCH_P (fragp->fr_subtype))
12843 offsetT old_var = fragp->fr_var;
12845 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
12847 return fragp->fr_var - old_var;
12850 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12853 if (mips16_extended_frag (fragp, NULL, stretch))
12855 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12857 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12862 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12864 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12871 /* Convert a machine dependent frag. */
12874 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
12876 if (RELAX_BRANCH_P (fragp->fr_subtype))
12879 unsigned long insn;
12883 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
12885 if (target_big_endian)
12886 insn = bfd_getb32 (buf);
12888 insn = bfd_getl32 (buf);
12890 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12892 /* We generate a fixup instead of applying it right now
12893 because, if there are linker relaxations, we're going to
12894 need the relocations. */
12895 exp.X_op = O_symbol;
12896 exp.X_add_symbol = fragp->fr_symbol;
12897 exp.X_add_number = fragp->fr_offset;
12899 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
12901 BFD_RELOC_16_PCREL_S2);
12902 fixp->fx_file = fragp->fr_file;
12903 fixp->fx_line = fragp->fr_line;
12905 md_number_to_chars (buf, insn, 4);
12912 as_warn_where (fragp->fr_file, fragp->fr_line,
12913 _("relaxed out-of-range branch into a jump"));
12915 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
12918 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12920 /* Reverse the branch. */
12921 switch ((insn >> 28) & 0xf)
12924 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12925 have the condition reversed by tweaking a single
12926 bit, and their opcodes all have 0x4???????. */
12927 assert ((insn & 0xf1000000) == 0x41000000);
12928 insn ^= 0x00010000;
12932 /* bltz 0x04000000 bgez 0x04010000
12933 bltzal 0x04100000 bgezal 0x04110000 */
12934 assert ((insn & 0xfc0e0000) == 0x04000000);
12935 insn ^= 0x00010000;
12939 /* beq 0x10000000 bne 0x14000000
12940 blez 0x18000000 bgtz 0x1c000000 */
12941 insn ^= 0x04000000;
12949 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
12951 /* Clear the and-link bit. */
12952 assert ((insn & 0xfc1c0000) == 0x04100000);
12954 /* bltzal 0x04100000 bgezal 0x04110000
12955 bltzall 0x04120000 bgezall 0x04130000 */
12956 insn &= ~0x00100000;
12959 /* Branch over the branch (if the branch was likely) or the
12960 full jump (not likely case). Compute the offset from the
12961 current instruction to branch to. */
12962 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12966 /* How many bytes in instructions we've already emitted? */
12967 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12968 /* How many bytes in instructions from here to the end? */
12969 i = fragp->fr_var - i;
12971 /* Convert to instruction count. */
12973 /* Branch counts from the next instruction. */
12976 /* Branch over the jump. */
12977 md_number_to_chars (buf, insn, 4);
12981 md_number_to_chars (buf, 0, 4);
12984 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
12986 /* beql $0, $0, 2f */
12988 /* Compute the PC offset from the current instruction to
12989 the end of the variable frag. */
12990 /* How many bytes in instructions we've already emitted? */
12991 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
12992 /* How many bytes in instructions from here to the end? */
12993 i = fragp->fr_var - i;
12994 /* Convert to instruction count. */
12996 /* Don't decrement i, because we want to branch over the
13000 md_number_to_chars (buf, insn, 4);
13003 md_number_to_chars (buf, 0, 4);
13008 if (mips_pic == NO_PIC)
13011 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13012 ? 0x0c000000 : 0x08000000);
13013 exp.X_op = O_symbol;
13014 exp.X_add_symbol = fragp->fr_symbol;
13015 exp.X_add_number = fragp->fr_offset;
13017 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13018 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13019 fixp->fx_file = fragp->fr_file;
13020 fixp->fx_line = fragp->fr_line;
13022 md_number_to_chars (buf, insn, 4);
13027 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13028 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13029 exp.X_op = O_symbol;
13030 exp.X_add_symbol = fragp->fr_symbol;
13031 exp.X_add_number = fragp->fr_offset;
13033 if (fragp->fr_offset)
13035 exp.X_add_symbol = make_expr_symbol (&exp);
13036 exp.X_add_number = 0;
13039 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13040 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13041 fixp->fx_file = fragp->fr_file;
13042 fixp->fx_line = fragp->fr_line;
13044 md_number_to_chars (buf, insn, 4);
13047 if (mips_opts.isa == ISA_MIPS1)
13050 md_number_to_chars (buf, 0, 4);
13054 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13055 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13057 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13058 4, &exp, 0, BFD_RELOC_LO16);
13059 fixp->fx_file = fragp->fr_file;
13060 fixp->fx_line = fragp->fr_line;
13062 md_number_to_chars (buf, insn, 4);
13066 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13071 md_number_to_chars (buf, insn, 4);
13076 assert (buf == (bfd_byte *)fragp->fr_literal
13077 + fragp->fr_fix + fragp->fr_var);
13079 fragp->fr_fix += fragp->fr_var;
13084 if (RELAX_MIPS16_P (fragp->fr_subtype))
13087 register const struct mips16_immed_operand *op;
13088 bfd_boolean small, ext;
13091 unsigned long insn;
13092 bfd_boolean use_extend;
13093 unsigned short extend;
13095 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13096 op = mips16_immed_operands;
13097 while (op->type != type)
13100 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13111 resolve_symbol_value (fragp->fr_symbol);
13112 val = S_GET_VALUE (fragp->fr_symbol);
13117 addr = fragp->fr_address + fragp->fr_fix;
13119 /* The rules for the base address of a PC relative reloc are
13120 complicated; see mips16_extended_frag. */
13121 if (type == 'p' || type == 'q')
13126 /* Ignore the low bit in the target, since it will be
13127 set for a text label. */
13128 if ((val & 1) != 0)
13131 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13133 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13136 addr &= ~ (addressT) ((1 << op->shift) - 1);
13139 /* Make sure the section winds up with the alignment we have
13142 record_alignment (asec, op->shift);
13146 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13147 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13148 as_warn_where (fragp->fr_file, fragp->fr_line,
13149 _("extended instruction in delay slot"));
13151 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13153 if (target_big_endian)
13154 insn = bfd_getb16 (buf);
13156 insn = bfd_getl16 (buf);
13158 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13159 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13160 small, ext, &insn, &use_extend, &extend);
13164 md_number_to_chars (buf, 0xf000 | extend, 2);
13165 fragp->fr_fix += 2;
13169 md_number_to_chars (buf, insn, 2);
13170 fragp->fr_fix += 2;
13178 first = RELAX_FIRST (fragp->fr_subtype);
13179 second = RELAX_SECOND (fragp->fr_subtype);
13180 fixp = (fixS *) fragp->fr_opcode;
13182 /* Possibly emit a warning if we've chosen the longer option. */
13183 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13184 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13186 const char *msg = macro_warning (fragp->fr_subtype);
13188 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13191 /* Go through all the fixups for the first sequence. Disable them
13192 (by marking them as done) if we're going to use the second
13193 sequence instead. */
13195 && fixp->fx_frag == fragp
13196 && fixp->fx_where < fragp->fr_fix - second)
13198 if (fragp->fr_subtype & RELAX_USE_SECOND)
13200 fixp = fixp->fx_next;
13203 /* Go through the fixups for the second sequence. Disable them if
13204 we're going to use the first sequence, otherwise adjust their
13205 addresses to account for the relaxation. */
13206 while (fixp && fixp->fx_frag == fragp)
13208 if (fragp->fr_subtype & RELAX_USE_SECOND)
13209 fixp->fx_where -= first;
13212 fixp = fixp->fx_next;
13215 /* Now modify the frag contents. */
13216 if (fragp->fr_subtype & RELAX_USE_SECOND)
13220 start = fragp->fr_literal + fragp->fr_fix - first - second;
13221 memmove (start, start + first, second);
13222 fragp->fr_fix -= first;
13225 fragp->fr_fix -= second;
13231 /* This function is called after the relocs have been generated.
13232 We've been storing mips16 text labels as odd. Here we convert them
13233 back to even for the convenience of the debugger. */
13236 mips_frob_file_after_relocs (void)
13239 unsigned int count, i;
13241 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13244 syms = bfd_get_outsymbols (stdoutput);
13245 count = bfd_get_symcount (stdoutput);
13246 for (i = 0; i < count; i++, syms++)
13248 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13249 && ((*syms)->value & 1) != 0)
13251 (*syms)->value &= ~1;
13252 /* If the symbol has an odd size, it was probably computed
13253 incorrectly, so adjust that as well. */
13254 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13255 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13262 /* This function is called whenever a label is defined. It is used
13263 when handling branch delays; if a branch has a label, we assume we
13264 can not move it. */
13267 mips_define_label (symbolS *sym)
13269 struct insn_label_list *l;
13271 if (free_insn_labels == NULL)
13272 l = (struct insn_label_list *) xmalloc (sizeof *l);
13275 l = free_insn_labels;
13276 free_insn_labels = l->next;
13280 l->next = insn_labels;
13284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13286 /* Some special processing for a MIPS ELF file. */
13289 mips_elf_final_processing (void)
13291 /* Write out the register information. */
13292 if (mips_abi != N64_ABI)
13296 s.ri_gprmask = mips_gprmask;
13297 s.ri_cprmask[0] = mips_cprmask[0];
13298 s.ri_cprmask[1] = mips_cprmask[1];
13299 s.ri_cprmask[2] = mips_cprmask[2];
13300 s.ri_cprmask[3] = mips_cprmask[3];
13301 /* The gp_value field is set by the MIPS ELF backend. */
13303 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13304 ((Elf32_External_RegInfo *)
13305 mips_regmask_frag));
13309 Elf64_Internal_RegInfo s;
13311 s.ri_gprmask = mips_gprmask;
13313 s.ri_cprmask[0] = mips_cprmask[0];
13314 s.ri_cprmask[1] = mips_cprmask[1];
13315 s.ri_cprmask[2] = mips_cprmask[2];
13316 s.ri_cprmask[3] = mips_cprmask[3];
13317 /* The gp_value field is set by the MIPS ELF backend. */
13319 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13320 ((Elf64_External_RegInfo *)
13321 mips_regmask_frag));
13324 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13325 sort of BFD interface for this. */
13326 if (mips_any_noreorder)
13327 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13328 if (mips_pic != NO_PIC)
13330 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13331 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13334 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13336 /* Set MIPS ELF flags for ASEs. */
13337 if (file_ase_mips16)
13338 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13339 #if 0 /* XXX FIXME */
13340 if (file_ase_mips3d)
13341 elf_elfheader (stdoutput)->e_flags |= ???;
13344 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13346 /* Set the MIPS ELF ABI flags. */
13347 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13348 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13349 else if (mips_abi == O64_ABI)
13350 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13351 else if (mips_abi == EABI_ABI)
13353 if (!file_mips_gp32)
13354 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13356 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13358 else if (mips_abi == N32_ABI)
13359 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13361 /* Nothing to do for N64_ABI. */
13363 if (mips_32bitmode)
13364 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13367 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13369 typedef struct proc {
13371 unsigned long reg_mask;
13372 unsigned long reg_offset;
13373 unsigned long fpreg_mask;
13374 unsigned long fpreg_offset;
13375 unsigned long frame_offset;
13376 unsigned long frame_reg;
13377 unsigned long pc_reg;
13380 static procS cur_proc;
13381 static procS *cur_proc_ptr;
13382 static int numprocs;
13384 /* Fill in an rs_align_code fragment. */
13387 mips_handle_align (fragS *fragp)
13389 if (fragp->fr_type != rs_align_code)
13392 if (mips_opts.mips16)
13394 static const unsigned char be_nop[] = { 0x65, 0x00 };
13395 static const unsigned char le_nop[] = { 0x00, 0x65 };
13400 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13401 p = fragp->fr_literal + fragp->fr_fix;
13409 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13413 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13417 md_obj_begin (void)
13424 /* check for premature end, nesting errors, etc */
13426 as_warn (_("missing .end at end of assembly"));
13435 if (*input_line_pointer == '-')
13437 ++input_line_pointer;
13440 if (!ISDIGIT (*input_line_pointer))
13441 as_bad (_("expected simple number"));
13442 if (input_line_pointer[0] == '0')
13444 if (input_line_pointer[1] == 'x')
13446 input_line_pointer += 2;
13447 while (ISXDIGIT (*input_line_pointer))
13450 val |= hex_value (*input_line_pointer++);
13452 return negative ? -val : val;
13456 ++input_line_pointer;
13457 while (ISDIGIT (*input_line_pointer))
13460 val |= *input_line_pointer++ - '0';
13462 return negative ? -val : val;
13465 if (!ISDIGIT (*input_line_pointer))
13467 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13468 *input_line_pointer, *input_line_pointer);
13469 as_warn (_("invalid number"));
13472 while (ISDIGIT (*input_line_pointer))
13475 val += *input_line_pointer++ - '0';
13477 return negative ? -val : val;
13480 /* The .file directive; just like the usual .file directive, but there
13481 is an initial number which is the ECOFF file index. In the non-ECOFF
13482 case .file implies DWARF-2. */
13485 s_mips_file (int x ATTRIBUTE_UNUSED)
13487 static int first_file_directive = 0;
13489 if (ECOFF_DEBUGGING)
13498 filename = dwarf2_directive_file (0);
13500 /* Versions of GCC up to 3.1 start files with a ".file"
13501 directive even for stabs output. Make sure that this
13502 ".file" is handled. Note that you need a version of GCC
13503 after 3.1 in order to support DWARF-2 on MIPS. */
13504 if (filename != NULL && ! first_file_directive)
13506 (void) new_logical_line (filename, -1);
13507 s_app_file_string (filename);
13509 first_file_directive = 1;
13513 /* The .loc directive, implying DWARF-2. */
13516 s_mips_loc (int x ATTRIBUTE_UNUSED)
13518 if (!ECOFF_DEBUGGING)
13519 dwarf2_directive_loc (0);
13522 /* The .end directive. */
13525 s_mips_end (int x ATTRIBUTE_UNUSED)
13529 /* Following functions need their own .frame and .cprestore directives. */
13530 mips_frame_reg_valid = 0;
13531 mips_cprestore_valid = 0;
13533 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13536 demand_empty_rest_of_line ();
13541 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13542 as_warn (_(".end not in text section"));
13546 as_warn (_(".end directive without a preceding .ent directive."));
13547 demand_empty_rest_of_line ();
13553 assert (S_GET_NAME (p));
13554 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13555 as_warn (_(".end symbol does not match .ent symbol."));
13557 if (debug_type == DEBUG_STABS)
13558 stabs_generate_asm_endfunc (S_GET_NAME (p),
13562 as_warn (_(".end directive missing or unknown symbol"));
13565 /* Generate a .pdr section. */
13566 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13569 segT saved_seg = now_seg;
13570 subsegT saved_subseg = now_subseg;
13575 dot = frag_now_fix ();
13577 #ifdef md_flush_pending_output
13578 md_flush_pending_output ();
13582 subseg_set (pdr_seg, 0);
13584 /* Write the symbol. */
13585 exp.X_op = O_symbol;
13586 exp.X_add_symbol = p;
13587 exp.X_add_number = 0;
13588 emit_expr (&exp, 4);
13590 fragp = frag_more (7 * 4);
13592 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13593 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13594 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13595 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13596 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13597 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13598 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13600 subseg_set (saved_seg, saved_subseg);
13602 #endif /* OBJ_ELF */
13604 cur_proc_ptr = NULL;
13607 /* The .aent and .ent directives. */
13610 s_mips_ent (int aent)
13614 symbolP = get_symbol ();
13615 if (*input_line_pointer == ',')
13616 ++input_line_pointer;
13617 SKIP_WHITESPACE ();
13618 if (ISDIGIT (*input_line_pointer)
13619 || *input_line_pointer == '-')
13622 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13623 as_warn (_(".ent or .aent not in text section."));
13625 if (!aent && cur_proc_ptr)
13626 as_warn (_("missing .end"));
13630 /* This function needs its own .frame and .cprestore directives. */
13631 mips_frame_reg_valid = 0;
13632 mips_cprestore_valid = 0;
13634 cur_proc_ptr = &cur_proc;
13635 memset (cur_proc_ptr, '\0', sizeof (procS));
13637 cur_proc_ptr->isym = symbolP;
13639 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13643 if (debug_type == DEBUG_STABS)
13644 stabs_generate_asm_func (S_GET_NAME (symbolP),
13645 S_GET_NAME (symbolP));
13648 demand_empty_rest_of_line ();
13651 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13652 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13653 s_mips_frame is used so that we can set the PDR information correctly.
13654 We can't use the ecoff routines because they make reference to the ecoff
13655 symbol table (in the mdebug section). */
13658 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13661 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13665 if (cur_proc_ptr == (procS *) NULL)
13667 as_warn (_(".frame outside of .ent"));
13668 demand_empty_rest_of_line ();
13672 cur_proc_ptr->frame_reg = tc_get_register (1);
13674 SKIP_WHITESPACE ();
13675 if (*input_line_pointer++ != ','
13676 || get_absolute_expression_and_terminator (&val) != ',')
13678 as_warn (_("Bad .frame directive"));
13679 --input_line_pointer;
13680 demand_empty_rest_of_line ();
13684 cur_proc_ptr->frame_offset = val;
13685 cur_proc_ptr->pc_reg = tc_get_register (0);
13687 demand_empty_rest_of_line ();
13690 #endif /* OBJ_ELF */
13694 /* The .fmask and .mask directives. If the mdebug section is present
13695 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13696 embedded targets, s_mips_mask is used so that we can set the PDR
13697 information correctly. We can't use the ecoff routines because they
13698 make reference to the ecoff symbol table (in the mdebug section). */
13701 s_mips_mask (int reg_type)
13704 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13708 if (cur_proc_ptr == (procS *) NULL)
13710 as_warn (_(".mask/.fmask outside of .ent"));
13711 demand_empty_rest_of_line ();
13715 if (get_absolute_expression_and_terminator (&mask) != ',')
13717 as_warn (_("Bad .mask/.fmask directive"));
13718 --input_line_pointer;
13719 demand_empty_rest_of_line ();
13723 off = get_absolute_expression ();
13725 if (reg_type == 'F')
13727 cur_proc_ptr->fpreg_mask = mask;
13728 cur_proc_ptr->fpreg_offset = off;
13732 cur_proc_ptr->reg_mask = mask;
13733 cur_proc_ptr->reg_offset = off;
13736 demand_empty_rest_of_line ();
13739 #endif /* OBJ_ELF */
13740 s_ignore (reg_type);
13743 /* The .loc directive. */
13753 assert (now_seg == text_section);
13755 lineno = get_number ();
13756 addroff = frag_now_fix ();
13758 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13759 S_SET_TYPE (symbolP, N_SLINE);
13760 S_SET_OTHER (symbolP, 0);
13761 S_SET_DESC (symbolP, lineno);
13762 symbolP->sy_segment = now_seg;
13766 /* A table describing all the processors gas knows about. Names are
13767 matched in the order listed.
13769 To ease comparison, please keep this table in the same order as
13770 gcc's mips_cpu_info_table[]. */
13771 static const struct mips_cpu_info mips_cpu_info_table[] =
13773 /* Entries for generic ISAs */
13774 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13775 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13776 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13777 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13778 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13779 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13780 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
13781 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13782 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
13785 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13786 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13787 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13790 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13793 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13794 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13795 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13796 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13797 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
13798 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
13799 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
13800 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13801 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13802 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13803 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13804 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13807 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13808 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13809 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13810 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13811 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
13812 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
13813 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13814 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13815 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13816 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13817 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13818 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
13819 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
13822 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
13823 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13824 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13827 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13828 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13830 /* Broadcom SB-1 CPU core */
13831 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13838 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13839 with a final "000" replaced by "k". Ignore case.
13841 Note: this function is shared between GCC and GAS. */
13844 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13846 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13847 given++, canonical++;
13849 return ((*given == 0 && *canonical == 0)
13850 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13854 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13855 CPU name. We've traditionally allowed a lot of variation here.
13857 Note: this function is shared between GCC and GAS. */
13860 mips_matching_cpu_name_p (const char *canonical, const char *given)
13862 /* First see if the name matches exactly, or with a final "000"
13863 turned into "k". */
13864 if (mips_strict_matching_cpu_name_p (canonical, given))
13867 /* If not, try comparing based on numerical designation alone.
13868 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13869 if (TOLOWER (*given) == 'r')
13871 if (!ISDIGIT (*given))
13874 /* Skip over some well-known prefixes in the canonical name,
13875 hoping to find a number there too. */
13876 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13878 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13880 else if (TOLOWER (canonical[0]) == 'r')
13883 return mips_strict_matching_cpu_name_p (canonical, given);
13887 /* Parse an option that takes the name of a processor as its argument.
13888 OPTION is the name of the option and CPU_STRING is the argument.
13889 Return the corresponding processor enumeration if the CPU_STRING is
13890 recognized, otherwise report an error and return null.
13892 A similar function exists in GCC. */
13894 static const struct mips_cpu_info *
13895 mips_parse_cpu (const char *option, const char *cpu_string)
13897 const struct mips_cpu_info *p;
13899 /* 'from-abi' selects the most compatible architecture for the given
13900 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13901 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13902 version. Look first at the -mgp options, if given, otherwise base
13903 the choice on MIPS_DEFAULT_64BIT.
13905 Treat NO_ABI like the EABIs. One reason to do this is that the
13906 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13907 architecture. This code picks MIPS I for 'mips' and MIPS III for
13908 'mips64', just as we did in the days before 'from-abi'. */
13909 if (strcasecmp (cpu_string, "from-abi") == 0)
13911 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13912 return mips_cpu_info_from_isa (ISA_MIPS1);
13914 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13915 return mips_cpu_info_from_isa (ISA_MIPS3);
13917 if (file_mips_gp32 >= 0)
13918 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13920 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13925 /* 'default' has traditionally been a no-op. Probably not very useful. */
13926 if (strcasecmp (cpu_string, "default") == 0)
13929 for (p = mips_cpu_info_table; p->name != 0; p++)
13930 if (mips_matching_cpu_name_p (p->name, cpu_string))
13933 as_bad ("Bad value (%s) for %s", cpu_string, option);
13937 /* Return the canonical processor information for ISA (a member of the
13938 ISA_MIPS* enumeration). */
13940 static const struct mips_cpu_info *
13941 mips_cpu_info_from_isa (int isa)
13945 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13946 if (mips_cpu_info_table[i].is_isa
13947 && isa == mips_cpu_info_table[i].isa)
13948 return (&mips_cpu_info_table[i]);
13953 static const struct mips_cpu_info *
13954 mips_cpu_info_from_arch (int arch)
13958 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13959 if (arch == mips_cpu_info_table[i].cpu)
13960 return (&mips_cpu_info_table[i]);
13966 show (FILE *stream, const char *string, int *col_p, int *first_p)
13970 fprintf (stream, "%24s", "");
13975 fprintf (stream, ", ");
13979 if (*col_p + strlen (string) > 72)
13981 fprintf (stream, "\n%24s", "");
13985 fprintf (stream, "%s", string);
13986 *col_p += strlen (string);
13992 md_show_usage (FILE *stream)
13997 fprintf (stream, _("\
13999 -EB generate big endian output\n\
14000 -EL generate little endian output\n\
14001 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14002 -G NUM allow referencing objects up to NUM bytes\n\
14003 implicitly with the gp register [default 8]\n"));
14004 fprintf (stream, _("\
14005 -mips1 generate MIPS ISA I instructions\n\
14006 -mips2 generate MIPS ISA II instructions\n\
14007 -mips3 generate MIPS ISA III instructions\n\
14008 -mips4 generate MIPS ISA IV instructions\n\
14009 -mips5 generate MIPS ISA V instructions\n\
14010 -mips32 generate MIPS32 ISA instructions\n\
14011 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14012 -mips64 generate MIPS64 ISA instructions\n\
14013 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14014 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14018 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14019 show (stream, mips_cpu_info_table[i].name, &column, &first);
14020 show (stream, "from-abi", &column, &first);
14021 fputc ('\n', stream);
14023 fprintf (stream, _("\
14024 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14025 -no-mCPU don't generate code specific to CPU.\n\
14026 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14030 show (stream, "3900", &column, &first);
14031 show (stream, "4010", &column, &first);
14032 show (stream, "4100", &column, &first);
14033 show (stream, "4650", &column, &first);
14034 fputc ('\n', stream);
14036 fprintf (stream, _("\
14037 -mips16 generate mips16 instructions\n\
14038 -no-mips16 do not generate mips16 instructions\n"));
14039 fprintf (stream, _("\
14040 -mfix-vr4120 work around certain VR4120 errata\n\
14041 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14042 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14043 -O0 remove unneeded NOPs, do not swap branches\n\
14044 -O remove unneeded NOPs and swap branches\n\
14045 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14046 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14047 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14049 fprintf (stream, _("\
14050 -KPIC, -call_shared generate SVR4 position independent code\n\
14051 -non_shared do not generate position independent code\n\
14052 -xgot assume a 32 bit GOT\n\
14053 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14054 -mabi=ABI create ABI conformant object file for:\n"));
14058 show (stream, "32", &column, &first);
14059 show (stream, "o64", &column, &first);
14060 show (stream, "n32", &column, &first);
14061 show (stream, "64", &column, &first);
14062 show (stream, "eabi", &column, &first);
14064 fputc ('\n', stream);
14066 fprintf (stream, _("\
14067 -32 create o32 ABI object file (default)\n\
14068 -n32 create n32 ABI object file\n\
14069 -64 create 64 ABI object file\n"));
14074 mips_dwarf2_format (void)
14076 if (mips_abi == N64_ABI)
14079 return dwarf2_format_64bit_irix;
14081 return dwarf2_format_64bit;
14085 return dwarf2_format_32bit;
14089 mips_dwarf2_addr_size (void)
14091 if (mips_abi == N64_ABI)