1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
299 /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
300 /* soft_float */ FALSE, /* single_float */ FALSE
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* MIPS ISA we are using for this output file. */
310 static int file_mips_isa = ISA_UNKNOWN;
312 /* True if any MIPS16 code was produced. */
313 static int file_ase_mips16;
315 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
316 || mips_opts.isa == ISA_MIPS32R2 \
317 || mips_opts.isa == ISA_MIPS64 \
318 || mips_opts.isa == ISA_MIPS64R2)
320 /* True if any microMIPS code was produced. */
321 static int file_ase_micromips;
323 /* True if we want to create R_MIPS_JALR for jalr $25. */
325 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
327 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
328 because there's no place for any addend, the only acceptable
329 expression is a bare symbol. */
330 #define MIPS_JALR_HINT_P(EXPR) \
331 (!HAVE_IN_PLACE_ADDENDS \
332 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
335 /* True if -mips3d was passed or implied by arguments passed on the
336 command line (e.g., by -march). */
337 static int file_ase_mips3d;
339 /* True if -mdmx was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mdmx;
343 /* True if -msmartmips was passed or implied by arguments passed on the
344 command line (e.g., by -march). */
345 static int file_ase_smartmips;
347 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
348 || mips_opts.isa == ISA_MIPS32R2)
350 /* True if -mdsp was passed or implied by arguments passed on the
351 command line (e.g., by -march). */
352 static int file_ase_dsp;
354 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
355 || mips_opts.isa == ISA_MIPS64R2 \
356 || mips_opts.micromips)
358 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
360 /* True if -mdspr2 was passed or implied by arguments passed on the
361 command line (e.g., by -march). */
362 static int file_ase_dspr2;
364 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
365 || mips_opts.isa == ISA_MIPS64R2 \
366 || mips_opts.micromips)
368 /* True if -mmt was passed or implied by arguments passed on the
369 command line (e.g., by -march). */
370 static int file_ase_mt;
372 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
376 || mips_opts.isa == ISA_MIPS64R2 \
377 || mips_opts.micromips)
379 /* True if -mvirt was passed or implied by arguments passed on the
380 command line (e.g., by -march). */
381 static int file_ase_virt;
383 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
384 || mips_opts.isa == ISA_MIPS64R2 \
385 || mips_opts.micromips)
387 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \
388 || (mips_opts.micromips \
389 && ISA_HAS_64BIT_REGS (mips_opts.isa)))
391 /* The argument of the -march= flag. The architecture we are assembling. */
392 static int file_mips_arch = CPU_UNKNOWN;
393 static const char *mips_arch_string;
395 /* The argument of the -mtune= flag. The architecture for which we
397 static int mips_tune = CPU_UNKNOWN;
398 static const char *mips_tune_string;
400 /* True when generating 32-bit code for a 64-bit processor. */
401 static int mips_32bitmode = 0;
403 /* True if the given ABI requires 32-bit registers. */
404 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
406 /* Likewise 64-bit registers. */
407 #define ABI_NEEDS_64BIT_REGS(ABI) \
409 || (ABI) == N64_ABI \
412 /* Return true if ISA supports 64 bit wide gp registers. */
413 #define ISA_HAS_64BIT_REGS(ISA) \
414 ((ISA) == ISA_MIPS3 \
415 || (ISA) == ISA_MIPS4 \
416 || (ISA) == ISA_MIPS5 \
417 || (ISA) == ISA_MIPS64 \
418 || (ISA) == ISA_MIPS64R2)
420 /* Return true if ISA supports 64 bit wide float registers. */
421 #define ISA_HAS_64BIT_FPRS(ISA) \
422 ((ISA) == ISA_MIPS3 \
423 || (ISA) == ISA_MIPS4 \
424 || (ISA) == ISA_MIPS5 \
425 || (ISA) == ISA_MIPS32R2 \
426 || (ISA) == ISA_MIPS64 \
427 || (ISA) == ISA_MIPS64R2)
429 /* Return true if ISA supports 64-bit right rotate (dror et al.)
431 #define ISA_HAS_DROR(ISA) \
432 ((ISA) == ISA_MIPS64R2 \
433 || (mips_opts.micromips \
434 && ISA_HAS_64BIT_REGS (ISA)) \
437 /* Return true if ISA supports 32-bit right rotate (ror et al.)
439 #define ISA_HAS_ROR(ISA) \
440 ((ISA) == ISA_MIPS32R2 \
441 || (ISA) == ISA_MIPS64R2 \
442 || mips_opts.ase_smartmips \
443 || mips_opts.micromips \
446 /* Return true if ISA supports single-precision floats in odd registers. */
447 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
448 ((ISA) == ISA_MIPS32 \
449 || (ISA) == ISA_MIPS32R2 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2)
453 /* Return true if ISA supports move to/from high part of a 64-bit
454 floating-point register. */
455 #define ISA_HAS_MXHC1(ISA) \
456 ((ISA) == ISA_MIPS32R2 \
457 || (ISA) == ISA_MIPS64R2)
459 #define HAVE_32BIT_GPRS \
460 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
462 #define HAVE_32BIT_FPRS \
463 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
465 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
466 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
468 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
470 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
472 /* True if relocations are stored in-place. */
473 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
475 /* The ABI-derived address size. */
476 #define HAVE_64BIT_ADDRESSES \
477 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
478 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
480 /* The size of symbolic constants (i.e., expressions of the form
481 "SYMBOL" or "SYMBOL + OFFSET"). */
482 #define HAVE_32BIT_SYMBOLS \
483 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
484 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
486 /* Addresses are loaded in different ways, depending on the address size
487 in use. The n32 ABI Documentation also mandates the use of additions
488 with overflow checking, but existing implementations don't follow it. */
489 #define ADDRESS_ADD_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
492 #define ADDRESS_ADDI_INSN \
493 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
495 #define ADDRESS_LOAD_INSN \
496 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
498 #define ADDRESS_STORE_INSN \
499 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
501 /* Return true if the given CPU supports the MIPS16 ASE. */
502 #define CPU_HAS_MIPS16(cpu) \
503 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
504 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
506 /* Return true if the given CPU supports the microMIPS ASE. */
507 #define CPU_HAS_MICROMIPS(cpu) 0
509 /* True if CPU has a dror instruction. */
510 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
512 /* True if CPU has a ror instruction. */
513 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
515 /* True if CPU is in the Octeon family */
516 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
518 /* True if CPU has seq/sne and seqi/snei instructions. */
519 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
521 /* True, if CPU has support for ldc1 and sdc1. */
522 #define CPU_HAS_LDC1_SDC1(CPU) \
523 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
525 /* True if mflo and mfhi can be immediately followed by instructions
526 which write to the HI and LO registers.
528 According to MIPS specifications, MIPS ISAs I, II, and III need
529 (at least) two instructions between the reads of HI/LO and
530 instructions which write them, and later ISAs do not. Contradicting
531 the MIPS specifications, some MIPS IV processor user manuals (e.g.
532 the UM for the NEC Vr5000) document needing the instructions between
533 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
534 MIPS64 and later ISAs to have the interlocks, plus any specific
535 earlier-ISA CPUs for which CPU documentation declares that the
536 instructions are really interlocked. */
537 #define hilo_interlocks \
538 (mips_opts.isa == ISA_MIPS32 \
539 || mips_opts.isa == ISA_MIPS32R2 \
540 || mips_opts.isa == ISA_MIPS64 \
541 || mips_opts.isa == ISA_MIPS64R2 \
542 || mips_opts.arch == CPU_R4010 \
543 || mips_opts.arch == CPU_R5900 \
544 || mips_opts.arch == CPU_R10000 \
545 || mips_opts.arch == CPU_R12000 \
546 || mips_opts.arch == CPU_R14000 \
547 || mips_opts.arch == CPU_R16000 \
548 || mips_opts.arch == CPU_RM7000 \
549 || mips_opts.arch == CPU_VR5500 \
550 || mips_opts.micromips \
553 /* Whether the processor uses hardware interlocks to protect reads
554 from the GPRs after they are loaded from memory, and thus does not
555 require nops to be inserted. This applies to instructions marked
556 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
557 level I and microMIPS mode instructions are always interlocked. */
558 #define gpr_interlocks \
559 (mips_opts.isa != ISA_MIPS1 \
560 || mips_opts.arch == CPU_R3900 \
561 || mips_opts.arch == CPU_R5900 \
562 || mips_opts.micromips \
565 /* Whether the processor uses hardware interlocks to avoid delays
566 required by coprocessor instructions, and thus does not require
567 nops to be inserted. This applies to instructions marked
568 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
569 between instructions marked INSN_WRITE_COND_CODE and ones marked
570 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
571 levels I, II, and III and microMIPS mode instructions are always
573 /* Itbl support may require additional care here. */
574 #define cop_interlocks \
575 ((mips_opts.isa != ISA_MIPS1 \
576 && mips_opts.isa != ISA_MIPS2 \
577 && mips_opts.isa != ISA_MIPS3) \
578 || mips_opts.arch == CPU_R4300 \
579 || mips_opts.micromips \
582 /* Whether the processor uses hardware interlocks to protect reads
583 from coprocessor registers after they are loaded from memory, and
584 thus does not require nops to be inserted. This applies to
585 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
586 requires at MIPS ISA level I and microMIPS mode instructions are
587 always interlocked. */
588 #define cop_mem_interlocks \
589 (mips_opts.isa != ISA_MIPS1 \
590 || mips_opts.micromips \
593 /* Is this a mfhi or mflo instruction? */
594 #define MF_HILO_INSN(PINFO) \
595 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
597 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
598 has been selected. This implies, in particular, that addresses of text
599 labels have their LSB set. */
600 #define HAVE_CODE_COMPRESSION \
601 ((mips_opts.mips16 | mips_opts.micromips) != 0)
603 /* MIPS PIC level. */
605 enum mips_pic_level mips_pic;
607 /* 1 if we should generate 32 bit offsets from the $gp register in
608 SVR4_PIC mode. Currently has no meaning in other modes. */
609 static int mips_big_got = 0;
611 /* 1 if trap instructions should used for overflow rather than break
613 static int mips_trap = 0;
615 /* 1 if double width floating point constants should not be constructed
616 by assembling two single width halves into two single width floating
617 point registers which just happen to alias the double width destination
618 register. On some architectures this aliasing can be disabled by a bit
619 in the status register, and the setting of this bit cannot be determined
620 automatically at assemble time. */
621 static int mips_disable_float_construction;
623 /* Non-zero if any .set noreorder directives were used. */
625 static int mips_any_noreorder;
627 /* Non-zero if nops should be inserted when the register referenced in
628 an mfhi/mflo instruction is read in the next two instructions. */
629 static int mips_7000_hilo_fix;
631 /* The size of objects in the small data section. */
632 static unsigned int g_switch_value = 8;
633 /* Whether the -G option was used. */
634 static int g_switch_seen = 0;
639 /* If we can determine in advance that GP optimization won't be
640 possible, we can skip the relaxation stuff that tries to produce
641 GP-relative references. This makes delay slot optimization work
644 This function can only provide a guess, but it seems to work for
645 gcc output. It needs to guess right for gcc, otherwise gcc
646 will put what it thinks is a GP-relative instruction in a branch
649 I don't know if a fix is needed for the SVR4_PIC mode. I've only
650 fixed it for the non-PIC mode. KR 95/04/07 */
651 static int nopic_need_relax (symbolS *, int);
653 /* handle of the OPCODE hash table */
654 static struct hash_control *op_hash = NULL;
656 /* The opcode hash table we use for the mips16. */
657 static struct hash_control *mips16_op_hash = NULL;
659 /* The opcode hash table we use for the microMIPS ASE. */
660 static struct hash_control *micromips_op_hash = NULL;
662 /* This array holds the chars that always start a comment. If the
663 pre-processor is disabled, these aren't very useful */
664 const char comment_chars[] = "#";
666 /* This array holds the chars that only start a comment at the beginning of
667 a line. If the line seems to have the form '# 123 filename'
668 .line and .file directives will appear in the pre-processed output */
669 /* Note that input_file.c hand checks for '#' at the beginning of the
670 first line of the input file. This is because the compiler outputs
671 #NO_APP at the beginning of its output. */
672 /* Also note that C style comments are always supported. */
673 const char line_comment_chars[] = "#";
675 /* This array holds machine specific line separator characters. */
676 const char line_separator_chars[] = ";";
678 /* Chars that can be used to separate mant from exp in floating point nums */
679 const char EXP_CHARS[] = "eE";
681 /* Chars that mean this number is a floating point constant */
684 const char FLT_CHARS[] = "rRsSfFdDxXpP";
686 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
687 changed in read.c . Ideally it shouldn't have to know about it at all,
688 but nothing is ideal around here.
691 static char *insn_error;
693 static int auto_align = 1;
695 /* When outputting SVR4 PIC code, the assembler needs to know the
696 offset in the stack frame from which to restore the $gp register.
697 This is set by the .cprestore pseudo-op, and saved in this
699 static offsetT mips_cprestore_offset = -1;
701 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
702 more optimizations, it can use a register value instead of a memory-saved
703 offset and even an other register than $gp as global pointer. */
704 static offsetT mips_cpreturn_offset = -1;
705 static int mips_cpreturn_register = -1;
706 static int mips_gp_register = GP;
707 static int mips_gprel_offset = 0;
709 /* Whether mips_cprestore_offset has been set in the current function
710 (or whether it has already been warned about, if not). */
711 static int mips_cprestore_valid = 0;
713 /* This is the register which holds the stack frame, as set by the
714 .frame pseudo-op. This is needed to implement .cprestore. */
715 static int mips_frame_reg = SP;
717 /* Whether mips_frame_reg has been set in the current function
718 (or whether it has already been warned about, if not). */
719 static int mips_frame_reg_valid = 0;
721 /* To output NOP instructions correctly, we need to keep information
722 about the previous two instructions. */
724 /* Whether we are optimizing. The default value of 2 means to remove
725 unneeded NOPs and swap branch instructions when possible. A value
726 of 1 means to not swap branches. A value of 0 means to always
728 static int mips_optimize = 2;
730 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
731 equivalent to seeing no -g option at all. */
732 static int mips_debug = 0;
734 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
735 #define MAX_VR4130_NOPS 4
737 /* The maximum number of NOPs needed to fill delay slots. */
738 #define MAX_DELAY_NOPS 2
740 /* The maximum number of NOPs needed for any purpose. */
743 /* A list of previous instructions, with index 0 being the most recent.
744 We need to look back MAX_NOPS instructions when filling delay slots
745 or working around processor errata. We need to look back one
746 instruction further if we're thinking about using history[0] to
747 fill a branch delay slot. */
748 static struct mips_cl_insn history[1 + MAX_NOPS];
750 /* Nop instructions used by emit_nop. */
751 static struct mips_cl_insn nop_insn;
752 static struct mips_cl_insn mips16_nop_insn;
753 static struct mips_cl_insn micromips_nop16_insn;
754 static struct mips_cl_insn micromips_nop32_insn;
756 /* The appropriate nop for the current mode. */
757 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
758 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
760 /* The size of NOP_INSN in bytes. */
761 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
763 /* If this is set, it points to a frag holding nop instructions which
764 were inserted before the start of a noreorder section. If those
765 nops turn out to be unnecessary, the size of the frag can be
767 static fragS *prev_nop_frag;
769 /* The number of nop instructions we created in prev_nop_frag. */
770 static int prev_nop_frag_holds;
772 /* The number of nop instructions that we know we need in
774 static int prev_nop_frag_required;
776 /* The number of instructions we've seen since prev_nop_frag. */
777 static int prev_nop_frag_since;
779 /* For ECOFF and ELF, relocations against symbols are done in two
780 parts, with a HI relocation and a LO relocation. Each relocation
781 has only 16 bits of space to store an addend. This means that in
782 order for the linker to handle carries correctly, it must be able
783 to locate both the HI and the LO relocation. This means that the
784 relocations must appear in order in the relocation table.
786 In order to implement this, we keep track of each unmatched HI
787 relocation. We then sort them so that they immediately precede the
788 corresponding LO relocation. */
793 struct mips_hi_fixup *next;
796 /* The section this fixup is in. */
800 /* The list of unmatched HI relocs. */
802 static struct mips_hi_fixup *mips_hi_fixup_list;
804 /* The frag containing the last explicit relocation operator.
805 Null if explicit relocations have not been used. */
807 static fragS *prev_reloc_op_frag;
809 /* Map normal MIPS register numbers to mips16 register numbers. */
811 #define X ILLEGAL_REG
812 static const int mips32_to_16_reg_map[] =
814 X, X, 2, 3, 4, 5, 6, 7,
815 X, X, X, X, X, X, X, X,
816 0, 1, X, X, X, X, X, X,
817 X, X, X, X, X, X, X, X
821 /* Map mips16 register numbers to normal MIPS register numbers. */
823 static const unsigned int mips16_to_32_reg_map[] =
825 16, 17, 2, 3, 4, 5, 6, 7
828 /* Map normal MIPS register numbers to microMIPS register numbers. */
830 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
831 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
832 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
833 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
834 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
835 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
836 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
838 #define X ILLEGAL_REG
839 /* reg type h: 4, 5, 6. */
840 static const int mips32_to_micromips_reg_h_map[] =
842 X, X, X, X, 4, 5, 6, X,
843 X, X, X, X, X, X, X, X,
844 X, X, X, X, X, X, X, X,
845 X, X, X, X, X, X, X, X
848 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
849 static const int mips32_to_micromips_reg_m_map[] =
851 0, X, 2, 3, X, X, X, X,
852 X, X, X, X, X, X, X, X,
853 4, 1, 5, 6, 7, X, X, X,
854 X, X, X, X, X, X, X, X
857 /* reg type q: 0, 2-7. 17. */
858 static const int mips32_to_micromips_reg_q_map[] =
860 0, X, 2, 3, 4, 5, 6, 7,
861 X, X, X, X, X, X, X, X,
862 X, 1, X, X, X, X, X, X,
863 X, X, X, X, X, X, X, X
866 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
869 /* Map microMIPS register numbers to normal MIPS register numbers. */
871 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
872 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
873 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
874 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
875 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
876 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
878 /* The microMIPS registers with type h. */
879 static const unsigned int micromips_to_32_reg_h_map[] =
881 5, 5, 6, 4, 4, 4, 4, 4
884 /* The microMIPS registers with type i. */
885 static const unsigned int micromips_to_32_reg_i_map[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
892 /* The microMIPS registers with type m. */
893 static const unsigned int micromips_to_32_reg_m_map[] =
895 0, 17, 2, 3, 16, 18, 19, 20
898 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
900 /* The microMIPS registers with type q. */
901 static const unsigned int micromips_to_32_reg_q_map[] =
903 0, 17, 2, 3, 4, 5, 6, 7
906 /* microMIPS imm type B. */
907 static const int micromips_imm_b_map[] =
909 1, 4, 8, 12, 16, 20, 24, -1
912 /* microMIPS imm type C. */
913 static const int micromips_imm_c_map[] =
915 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
918 /* Classifies the kind of instructions we're interested in when
919 implementing -mfix-vr4120. */
920 enum fix_vr4120_class
928 NUM_FIX_VR4120_CLASSES
931 /* ...likewise -mfix-loongson2f-jump. */
932 static bfd_boolean mips_fix_loongson2f_jump;
934 /* ...likewise -mfix-loongson2f-nop. */
935 static bfd_boolean mips_fix_loongson2f_nop;
937 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
938 static bfd_boolean mips_fix_loongson2f;
940 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
941 there must be at least one other instruction between an instruction
942 of type X and an instruction of type Y. */
943 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
945 /* True if -mfix-vr4120 is in force. */
946 static int mips_fix_vr4120;
948 /* ...likewise -mfix-vr4130. */
949 static int mips_fix_vr4130;
951 /* ...likewise -mfix-24k. */
952 static int mips_fix_24k;
954 /* ...likewise -mfix-cn63xxp1 */
955 static bfd_boolean mips_fix_cn63xxp1;
957 /* We don't relax branches by default, since this causes us to expand
958 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
959 fail to compute the offset before expanding the macro to the most
960 efficient expansion. */
962 static int mips_relax_branch;
964 /* The expansion of many macros depends on the type of symbol that
965 they refer to. For example, when generating position-dependent code,
966 a macro that refers to a symbol may have two different expansions,
967 one which uses GP-relative addresses and one which uses absolute
968 addresses. When generating SVR4-style PIC, a macro may have
969 different expansions for local and global symbols.
971 We handle these situations by generating both sequences and putting
972 them in variant frags. In position-dependent code, the first sequence
973 will be the GP-relative one and the second sequence will be the
974 absolute one. In SVR4 PIC, the first sequence will be for global
975 symbols and the second will be for local symbols.
977 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
978 SECOND are the lengths of the two sequences in bytes. These fields
979 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
980 the subtype has the following flags:
983 Set if it has been decided that we should use the second
984 sequence instead of the first.
987 Set in the first variant frag if the macro's second implementation
988 is longer than its first. This refers to the macro as a whole,
989 not an individual relaxation.
992 Set in the first variant frag if the macro appeared in a .set nomacro
993 block and if one alternative requires a warning but the other does not.
996 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
999 RELAX_DELAY_SLOT_16BIT
1000 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1003 RELAX_DELAY_SLOT_SIZE_FIRST
1004 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1005 the macro is of the wrong size for the branch delay slot.
1007 RELAX_DELAY_SLOT_SIZE_SECOND
1008 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1009 the macro is of the wrong size for the branch delay slot.
1011 The frag's "opcode" points to the first fixup for relaxable code.
1013 Relaxable macros are generated using a sequence such as:
1015 relax_start (SYMBOL);
1016 ... generate first expansion ...
1018 ... generate second expansion ...
1021 The code and fixups for the unwanted alternative are discarded
1022 by md_convert_frag. */
1023 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1025 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1026 #define RELAX_SECOND(X) ((X) & 0xff)
1027 #define RELAX_USE_SECOND 0x10000
1028 #define RELAX_SECOND_LONGER 0x20000
1029 #define RELAX_NOMACRO 0x40000
1030 #define RELAX_DELAY_SLOT 0x80000
1031 #define RELAX_DELAY_SLOT_16BIT 0x100000
1032 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1033 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1035 /* Branch without likely bit. If label is out of range, we turn:
1037 beq reg1, reg2, label
1047 with the following opcode replacements:
1054 bltzal <-> bgezal (with jal label instead of j label)
1056 Even though keeping the delay slot instruction in the delay slot of
1057 the branch would be more efficient, it would be very tricky to do
1058 correctly, because we'd have to introduce a variable frag *after*
1059 the delay slot instruction, and expand that instead. Let's do it
1060 the easy way for now, even if the branch-not-taken case now costs
1061 one additional instruction. Out-of-range branches are not supposed
1062 to be common, anyway.
1064 Branch likely. If label is out of range, we turn:
1066 beql reg1, reg2, label
1067 delay slot (annulled if branch not taken)
1076 delay slot (executed only if branch taken)
1079 It would be possible to generate a shorter sequence by losing the
1080 likely bit, generating something like:
1085 delay slot (executed only if branch taken)
1097 bltzall -> bgezal (with jal label instead of j label)
1098 bgezall -> bltzal (ditto)
1101 but it's not clear that it would actually improve performance. */
1102 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1103 ((relax_substateT) \
1106 | ((toofar) ? 0x20 : 0) \
1107 | ((link) ? 0x40 : 0) \
1108 | ((likely) ? 0x80 : 0) \
1109 | ((uncond) ? 0x100 : 0)))
1110 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1111 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1112 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1113 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1114 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1115 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1117 /* For mips16 code, we use an entirely different form of relaxation.
1118 mips16 supports two versions of most instructions which take
1119 immediate values: a small one which takes some small value, and a
1120 larger one which takes a 16 bit value. Since branches also follow
1121 this pattern, relaxing these values is required.
1123 We can assemble both mips16 and normal MIPS code in a single
1124 object. Therefore, we need to support this type of relaxation at
1125 the same time that we support the relaxation described above. We
1126 use the high bit of the subtype field to distinguish these cases.
1128 The information we store for this type of relaxation is the
1129 argument code found in the opcode file for this relocation, whether
1130 the user explicitly requested a small or extended form, and whether
1131 the relocation is in a jump or jal delay slot. That tells us the
1132 size of the value, and how it should be stored. We also store
1133 whether the fragment is considered to be extended or not. We also
1134 store whether this is known to be a branch to a different section,
1135 whether we have tried to relax this frag yet, and whether we have
1136 ever extended a PC relative fragment because of a shift count. */
1137 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1140 | ((small) ? 0x100 : 0) \
1141 | ((ext) ? 0x200 : 0) \
1142 | ((dslot) ? 0x400 : 0) \
1143 | ((jal_dslot) ? 0x800 : 0))
1144 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1145 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1146 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1147 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1148 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1149 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1150 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1151 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1152 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1153 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1155 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1157 /* For microMIPS code, we use relaxation similar to one we use for
1158 MIPS16 code. Some instructions that take immediate values support
1159 two encodings: a small one which takes some small value, and a
1160 larger one which takes a 16 bit value. As some branches also follow
1161 this pattern, relaxing these values is required.
1163 We can assemble both microMIPS and normal MIPS code in a single
1164 object. Therefore, we need to support this type of relaxation at
1165 the same time that we support the relaxation described above. We
1166 use one of the high bits of the subtype field to distinguish these
1169 The information we store for this type of relaxation is the argument
1170 code found in the opcode file for this relocation, the register
1171 selected as the assembler temporary, whether the branch is
1172 unconditional, whether it is compact, whether it stores the link
1173 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1174 branches to a sequence of instructions is enabled, and whether the
1175 displacement of a branch is too large to fit as an immediate argument
1176 of a 16-bit and a 32-bit branch, respectively. */
1177 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1178 relax32, toofar16, toofar32) \
1181 | (((at) & 0x1f) << 8) \
1182 | ((uncond) ? 0x2000 : 0) \
1183 | ((compact) ? 0x4000 : 0) \
1184 | ((link) ? 0x8000 : 0) \
1185 | ((relax32) ? 0x10000 : 0) \
1186 | ((toofar16) ? 0x20000 : 0) \
1187 | ((toofar32) ? 0x40000 : 0))
1188 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1189 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1190 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1191 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1192 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1193 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1194 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1196 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1197 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1198 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1199 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1200 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1201 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1203 /* Sign-extend 16-bit value X. */
1204 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1206 /* Is the given value a sign-extended 32-bit value? */
1207 #define IS_SEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1209 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1211 /* Is the given value a sign-extended 16-bit value? */
1212 #define IS_SEXT_16BIT_NUM(x) \
1213 (((x) &~ (offsetT) 0x7fff) == 0 \
1214 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1216 /* Is the given value a sign-extended 12-bit value? */
1217 #define IS_SEXT_12BIT_NUM(x) \
1218 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1220 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1221 #define IS_ZEXT_32BIT_NUM(x) \
1222 (((x) &~ (offsetT) 0xffffffff) == 0 \
1223 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1225 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1226 VALUE << SHIFT. VALUE is evaluated exactly once. */
1227 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1228 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1229 | (((VALUE) & (MASK)) << (SHIFT)))
1231 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1233 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1234 (((STRUCT) >> (SHIFT)) & (MASK))
1236 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1237 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1239 include/opcode/mips.h specifies operand fields using the macros
1240 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1241 with "MIPS16OP" instead of "OP". */
1242 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1245 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1246 OP_MASK_##FIELD, OP_SH_##FIELD); \
1248 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1249 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1251 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1252 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1253 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1255 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1256 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1258 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1259 : EXTRACT_BITS ((INSN).insn_opcode, \
1260 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1261 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1262 EXTRACT_BITS ((INSN).insn_opcode, \
1263 MIPS16OP_MASK_##FIELD, \
1264 MIPS16OP_SH_##FIELD)
1266 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1267 #define MIPS16_EXTEND (0xf000U << 16)
1269 /* Whether or not we are emitting a branch-likely macro. */
1270 static bfd_boolean emit_branch_likely_macro = FALSE;
1272 /* Global variables used when generating relaxable macros. See the
1273 comment above RELAX_ENCODE for more details about how relaxation
1276 /* 0 if we're not emitting a relaxable macro.
1277 1 if we're emitting the first of the two relaxation alternatives.
1278 2 if we're emitting the second alternative. */
1281 /* The first relaxable fixup in the current frag. (In other words,
1282 the first fixup that refers to relaxable code.) */
1285 /* sizes[0] says how many bytes of the first alternative are stored in
1286 the current frag. Likewise sizes[1] for the second alternative. */
1287 unsigned int sizes[2];
1289 /* The symbol on which the choice of sequence depends. */
1293 /* Global variables used to decide whether a macro needs a warning. */
1295 /* True if the macro is in a branch delay slot. */
1296 bfd_boolean delay_slot_p;
1298 /* Set to the length in bytes required if the macro is in a delay slot
1299 that requires a specific length of instruction, otherwise zero. */
1300 unsigned int delay_slot_length;
1302 /* For relaxable macros, sizes[0] is the length of the first alternative
1303 in bytes and sizes[1] is the length of the second alternative.
1304 For non-relaxable macros, both elements give the length of the
1306 unsigned int sizes[2];
1308 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1309 instruction of the first alternative in bytes and first_insn_sizes[1]
1310 is the length of the first instruction of the second alternative.
1311 For non-relaxable macros, both elements give the length of the first
1312 instruction in bytes.
1314 Set to zero if we haven't yet seen the first instruction. */
1315 unsigned int first_insn_sizes[2];
1317 /* For relaxable macros, insns[0] is the number of instructions for the
1318 first alternative and insns[1] is the number of instructions for the
1321 For non-relaxable macros, both elements give the number of
1322 instructions for the macro. */
1323 unsigned int insns[2];
1325 /* The first variant frag for this macro. */
1327 } mips_macro_warning;
1329 /* Prototypes for static functions. */
1331 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1333 static void append_insn
1334 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1335 bfd_boolean expansionp);
1336 static void mips_no_prev_insn (void);
1337 static void macro_build (expressionS *, const char *, const char *, ...);
1338 static void mips16_macro_build
1339 (expressionS *, const char *, const char *, va_list *);
1340 static void load_register (int, expressionS *, int);
1341 static void macro_start (void);
1342 static void macro_end (void);
1343 static void macro (struct mips_cl_insn * ip);
1344 static void mips16_macro (struct mips_cl_insn * ip);
1345 static void mips_ip (char *str, struct mips_cl_insn * ip);
1346 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1347 static void mips16_immed
1348 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS *, bfd_reloc_code_real_type *, char *);
1352 static void my_getExpression (expressionS *, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void md_obj_begin (void);
1378 static void md_obj_end (void);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean pic_need_relax (symbolS *, asection *);
1388 static int relaxed_branch_length (fragS *, asection *, int);
1389 static int validate_mips_insn (const struct mips_opcode *);
1390 static int validate_micromips_insn (const struct mips_opcode *);
1391 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1392 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1394 /* Table and functions used to map between CPU/ISA names, and
1395 ISA levels, and CPU numbers. */
1397 struct mips_cpu_info
1399 const char *name; /* CPU or ISA name. */
1400 int flags; /* ASEs available, or ISA flag. */
1401 int isa; /* ISA level. */
1402 int cpu; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1406 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1407 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1408 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1409 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1410 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1411 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1412 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1413 #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
1415 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1416 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1417 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1421 The following pseudo-ops from the Kane and Heinrich MIPS book
1422 should be defined here, but are currently unsupported: .alias,
1423 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1425 The following pseudo-ops from the Kane and Heinrich MIPS book are
1426 specific to the type of debugging information being generated, and
1427 should be defined by the object format: .aent, .begin, .bend,
1428 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1431 The following pseudo-ops from the Kane and Heinrich MIPS book are
1432 not MIPS CPU specific, but are also not specific to the object file
1433 format. This file is probably the best place to define them, but
1434 they are not currently supported: .asm0, .endr, .lab, .struct. */
1436 static const pseudo_typeS mips_pseudo_table[] =
1438 /* MIPS specific pseudo-ops. */
1439 {"option", s_option, 0},
1440 {"set", s_mipsset, 0},
1441 {"rdata", s_change_sec, 'r'},
1442 {"sdata", s_change_sec, 's'},
1443 {"livereg", s_ignore, 0},
1444 {"abicalls", s_abicalls, 0},
1445 {"cpload", s_cpload, 0},
1446 {"cpsetup", s_cpsetup, 0},
1447 {"cplocal", s_cplocal, 0},
1448 {"cprestore", s_cprestore, 0},
1449 {"cpreturn", s_cpreturn, 0},
1450 {"dtprelword", s_dtprelword, 0},
1451 {"dtpreldword", s_dtpreldword, 0},
1452 {"tprelword", s_tprelword, 0},
1453 {"tpreldword", s_tpreldword, 0},
1454 {"gpvalue", s_gpvalue, 0},
1455 {"gpword", s_gpword, 0},
1456 {"gpdword", s_gpdword, 0},
1457 {"ehword", s_ehword, 0},
1458 {"cpadd", s_cpadd, 0},
1459 {"insn", s_insn, 0},
1461 /* Relatively generic pseudo-ops that happen to be used on MIPS
1463 {"asciiz", stringer, 8 + 1},
1464 {"bss", s_change_sec, 'b'},
1466 {"half", s_cons, 1},
1467 {"dword", s_cons, 3},
1468 {"weakext", s_mips_weakext, 0},
1469 {"origin", s_org, 0},
1470 {"repeat", s_rept, 0},
1472 /* For MIPS this is non-standard, but we define it for consistency. */
1473 {"sbss", s_change_sec, 'B'},
1475 /* These pseudo-ops are defined in read.c, but must be overridden
1476 here for one reason or another. */
1477 {"align", s_align, 0},
1478 {"byte", s_cons, 0},
1479 {"data", s_change_sec, 'd'},
1480 {"double", s_float_cons, 'd'},
1481 {"float", s_float_cons, 'f'},
1482 {"globl", s_mips_globl, 0},
1483 {"global", s_mips_globl, 0},
1484 {"hword", s_cons, 1},
1486 {"long", s_cons, 2},
1487 {"octa", s_cons, 4},
1488 {"quad", s_cons, 3},
1489 {"section", s_change_section, 0},
1490 {"short", s_cons, 1},
1491 {"single", s_float_cons, 'f'},
1492 {"stabd", s_mips_stab, 'd'},
1493 {"stabn", s_mips_stab, 'n'},
1494 {"stabs", s_mips_stab, 's'},
1495 {"text", s_change_sec, 't'},
1496 {"word", s_cons, 2},
1498 { "extern", ecoff_directive_extern, 0},
1503 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1505 /* These pseudo-ops should be defined by the object file format.
1506 However, a.out doesn't support them, so we have versions here. */
1507 {"aent", s_mips_ent, 1},
1508 {"bgnb", s_ignore, 0},
1509 {"end", s_mips_end, 0},
1510 {"endb", s_ignore, 0},
1511 {"ent", s_mips_ent, 0},
1512 {"file", s_mips_file, 0},
1513 {"fmask", s_mips_mask, 'F'},
1514 {"frame", s_mips_frame, 0},
1515 {"loc", s_mips_loc, 0},
1516 {"mask", s_mips_mask, 'R'},
1517 {"verstamp", s_ignore, 0},
1521 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1522 purpose of the `.dc.a' internal pseudo-op. */
1525 mips_address_bytes (void)
1527 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1530 extern void pop_insert (const pseudo_typeS *);
1533 mips_pop_insert (void)
1535 pop_insert (mips_pseudo_table);
1536 if (! ECOFF_DEBUGGING)
1537 pop_insert (mips_nonecoff_pseudo_table);
1540 /* Symbols labelling the current insn. */
1542 struct insn_label_list
1544 struct insn_label_list *next;
1548 static struct insn_label_list *free_insn_labels;
1549 #define label_list tc_segment_info_data.labels
1551 static void mips_clear_insn_labels (void);
1552 static void mips_mark_labels (void);
1553 static void mips_compressed_mark_labels (void);
1556 mips_clear_insn_labels (void)
1558 register struct insn_label_list **pl;
1559 segment_info_type *si;
1563 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1566 si = seg_info (now_seg);
1567 *pl = si->label_list;
1568 si->label_list = NULL;
1572 /* Mark instruction labels in MIPS16/microMIPS mode. */
1575 mips_mark_labels (void)
1577 if (HAVE_CODE_COMPRESSION)
1578 mips_compressed_mark_labels ();
1581 static char *expr_end;
1583 /* Expressions which appear in instructions. These are set by
1586 static expressionS imm_expr;
1587 static expressionS imm2_expr;
1588 static expressionS offset_expr;
1590 /* Relocs associated with imm_expr and offset_expr. */
1592 static bfd_reloc_code_real_type imm_reloc[3]
1593 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1594 static bfd_reloc_code_real_type offset_reloc[3]
1595 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1597 /* This is set to the resulting size of the instruction to be produced
1598 by mips16_ip if an explicit extension is used or by mips_ip if an
1599 explicit size is supplied. */
1601 static unsigned int forced_insn_length;
1603 /* True if we are assembling an instruction. All dot symbols defined during
1604 this time should be treated as code labels. */
1606 static bfd_boolean mips_assembling_insn;
1609 /* The pdr segment for per procedure frame/regmask info. Not used for
1612 static segT pdr_seg;
1615 /* The default target format to use. */
1617 #if defined (TE_FreeBSD)
1618 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1619 #elif defined (TE_TMIPS)
1620 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1622 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1626 mips_target_format (void)
1628 switch (OUTPUT_FLAVOR)
1630 case bfd_target_ecoff_flavour:
1631 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1632 case bfd_target_coff_flavour:
1634 case bfd_target_elf_flavour:
1636 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1637 return (target_big_endian
1638 ? "elf32-bigmips-vxworks"
1639 : "elf32-littlemips-vxworks");
1641 return (target_big_endian
1642 ? (HAVE_64BIT_OBJECTS
1643 ? ELF_TARGET ("elf64-", "big")
1645 ? ELF_TARGET ("elf32-n", "big")
1646 : ELF_TARGET ("elf32-", "big")))
1647 : (HAVE_64BIT_OBJECTS
1648 ? ELF_TARGET ("elf64-", "little")
1650 ? ELF_TARGET ("elf32-n", "little")
1651 : ELF_TARGET ("elf32-", "little"))));
1658 /* Return the length of a microMIPS instruction in bytes. If bits of
1659 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1660 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1661 major opcode) will require further modifications to the opcode
1664 static inline unsigned int
1665 micromips_insn_length (const struct mips_opcode *mo)
1667 return (mo->mask >> 16) == 0 ? 2 : 4;
1670 /* Return the length of MIPS16 instruction OPCODE. */
1672 static inline unsigned int
1673 mips16_opcode_length (unsigned long opcode)
1675 return (opcode >> 16) == 0 ? 2 : 4;
1678 /* Return the length of instruction INSN. */
1680 static inline unsigned int
1681 insn_length (const struct mips_cl_insn *insn)
1683 if (mips_opts.micromips)
1684 return micromips_insn_length (insn->insn_mo);
1685 else if (mips_opts.mips16)
1686 return mips16_opcode_length (insn->insn_opcode);
1691 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1694 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1699 insn->insn_opcode = mo->match;
1702 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1703 insn->fixp[i] = NULL;
1704 insn->fixed_p = (mips_opts.noreorder > 0);
1705 insn->noreorder_p = (mips_opts.noreorder > 0);
1706 insn->mips16_absolute_jump_p = 0;
1707 insn->complete_p = 0;
1708 insn->cleared_p = 0;
1711 /* Record the current MIPS16/microMIPS mode in now_seg. */
1714 mips_record_compressed_mode (void)
1716 segment_info_type *si;
1718 si = seg_info (now_seg);
1719 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1720 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1721 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1722 si->tc_segment_info_data.micromips = mips_opts.micromips;
1725 /* Read a standard MIPS instruction from BUF. */
1727 static unsigned long
1728 read_insn (char *buf)
1730 if (target_big_endian)
1731 return bfd_getb32 ((bfd_byte *) buf);
1733 return bfd_getl32 ((bfd_byte *) buf);
1736 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1740 write_insn (char *buf, unsigned int insn)
1742 md_number_to_chars (buf, insn, 4);
1746 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1747 has length LENGTH. */
1749 static unsigned long
1750 read_compressed_insn (char *buf, unsigned int length)
1756 for (i = 0; i < length; i += 2)
1759 if (target_big_endian)
1760 insn |= bfd_getb16 ((char *) buf);
1762 insn |= bfd_getl16 ((char *) buf);
1768 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1769 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1772 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1776 for (i = 0; i < length; i += 2)
1777 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1778 return buf + length;
1781 /* Install INSN at the location specified by its "frag" and "where" fields. */
1784 install_insn (const struct mips_cl_insn *insn)
1786 char *f = insn->frag->fr_literal + insn->where;
1787 if (HAVE_CODE_COMPRESSION)
1788 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1790 write_insn (f, insn->insn_opcode);
1791 mips_record_compressed_mode ();
1794 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1795 and install the opcode in the new location. */
1798 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1803 insn->where = where;
1804 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1805 if (insn->fixp[i] != NULL)
1807 insn->fixp[i]->fx_frag = frag;
1808 insn->fixp[i]->fx_where = where;
1810 install_insn (insn);
1813 /* Add INSN to the end of the output. */
1816 add_fixed_insn (struct mips_cl_insn *insn)
1818 char *f = frag_more (insn_length (insn));
1819 move_insn (insn, frag_now, f - frag_now->fr_literal);
1822 /* Start a variant frag and move INSN to the start of the variant part,
1823 marking it as fixed. The other arguments are as for frag_var. */
1826 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1827 relax_substateT subtype, symbolS *symbol, offsetT offset)
1829 frag_grow (max_chars);
1830 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1832 frag_var (rs_machine_dependent, max_chars, var,
1833 subtype, symbol, offset, NULL);
1836 /* Insert N copies of INSN into the history buffer, starting at
1837 position FIRST. Neither FIRST nor N need to be clipped. */
1840 insert_into_history (unsigned int first, unsigned int n,
1841 const struct mips_cl_insn *insn)
1843 if (mips_relax.sequence != 2)
1847 for (i = ARRAY_SIZE (history); i-- > first;)
1849 history[i] = history[i - n];
1855 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1856 the idea is to make it obvious at a glance that each errata is
1860 init_vr4120_conflicts (void)
1862 #define CONFLICT(FIRST, SECOND) \
1863 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1865 /* Errata 21 - [D]DIV[U] after [D]MACC */
1866 CONFLICT (MACC, DIV);
1867 CONFLICT (DMACC, DIV);
1869 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1870 CONFLICT (DMULT, DMULT);
1871 CONFLICT (DMULT, DMACC);
1872 CONFLICT (DMACC, DMULT);
1873 CONFLICT (DMACC, DMACC);
1875 /* Errata 24 - MT{LO,HI} after [D]MACC */
1876 CONFLICT (MACC, MTHILO);
1877 CONFLICT (DMACC, MTHILO);
1879 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1880 instruction is executed immediately after a MACC or DMACC
1881 instruction, the result of [either instruction] is incorrect." */
1882 CONFLICT (MACC, MULT);
1883 CONFLICT (MACC, DMULT);
1884 CONFLICT (DMACC, MULT);
1885 CONFLICT (DMACC, DMULT);
1887 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1888 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1889 DDIV or DDIVU instruction, the result of the MACC or
1890 DMACC instruction is incorrect.". */
1891 CONFLICT (DMULT, MACC);
1892 CONFLICT (DMULT, DMACC);
1893 CONFLICT (DIV, MACC);
1894 CONFLICT (DIV, DMACC);
1904 #define RTYPE_MASK 0x1ff00
1905 #define RTYPE_NUM 0x00100
1906 #define RTYPE_FPU 0x00200
1907 #define RTYPE_FCC 0x00400
1908 #define RTYPE_VEC 0x00800
1909 #define RTYPE_GP 0x01000
1910 #define RTYPE_CP0 0x02000
1911 #define RTYPE_PC 0x04000
1912 #define RTYPE_ACC 0x08000
1913 #define RTYPE_CCC 0x10000
1914 #define RNUM_MASK 0x000ff
1915 #define RWARN 0x80000
1917 #define GENERIC_REGISTER_NUMBERS \
1918 {"$0", RTYPE_NUM | 0}, \
1919 {"$1", RTYPE_NUM | 1}, \
1920 {"$2", RTYPE_NUM | 2}, \
1921 {"$3", RTYPE_NUM | 3}, \
1922 {"$4", RTYPE_NUM | 4}, \
1923 {"$5", RTYPE_NUM | 5}, \
1924 {"$6", RTYPE_NUM | 6}, \
1925 {"$7", RTYPE_NUM | 7}, \
1926 {"$8", RTYPE_NUM | 8}, \
1927 {"$9", RTYPE_NUM | 9}, \
1928 {"$10", RTYPE_NUM | 10}, \
1929 {"$11", RTYPE_NUM | 11}, \
1930 {"$12", RTYPE_NUM | 12}, \
1931 {"$13", RTYPE_NUM | 13}, \
1932 {"$14", RTYPE_NUM | 14}, \
1933 {"$15", RTYPE_NUM | 15}, \
1934 {"$16", RTYPE_NUM | 16}, \
1935 {"$17", RTYPE_NUM | 17}, \
1936 {"$18", RTYPE_NUM | 18}, \
1937 {"$19", RTYPE_NUM | 19}, \
1938 {"$20", RTYPE_NUM | 20}, \
1939 {"$21", RTYPE_NUM | 21}, \
1940 {"$22", RTYPE_NUM | 22}, \
1941 {"$23", RTYPE_NUM | 23}, \
1942 {"$24", RTYPE_NUM | 24}, \
1943 {"$25", RTYPE_NUM | 25}, \
1944 {"$26", RTYPE_NUM | 26}, \
1945 {"$27", RTYPE_NUM | 27}, \
1946 {"$28", RTYPE_NUM | 28}, \
1947 {"$29", RTYPE_NUM | 29}, \
1948 {"$30", RTYPE_NUM | 30}, \
1949 {"$31", RTYPE_NUM | 31}
1951 #define FPU_REGISTER_NAMES \
1952 {"$f0", RTYPE_FPU | 0}, \
1953 {"$f1", RTYPE_FPU | 1}, \
1954 {"$f2", RTYPE_FPU | 2}, \
1955 {"$f3", RTYPE_FPU | 3}, \
1956 {"$f4", RTYPE_FPU | 4}, \
1957 {"$f5", RTYPE_FPU | 5}, \
1958 {"$f6", RTYPE_FPU | 6}, \
1959 {"$f7", RTYPE_FPU | 7}, \
1960 {"$f8", RTYPE_FPU | 8}, \
1961 {"$f9", RTYPE_FPU | 9}, \
1962 {"$f10", RTYPE_FPU | 10}, \
1963 {"$f11", RTYPE_FPU | 11}, \
1964 {"$f12", RTYPE_FPU | 12}, \
1965 {"$f13", RTYPE_FPU | 13}, \
1966 {"$f14", RTYPE_FPU | 14}, \
1967 {"$f15", RTYPE_FPU | 15}, \
1968 {"$f16", RTYPE_FPU | 16}, \
1969 {"$f17", RTYPE_FPU | 17}, \
1970 {"$f18", RTYPE_FPU | 18}, \
1971 {"$f19", RTYPE_FPU | 19}, \
1972 {"$f20", RTYPE_FPU | 20}, \
1973 {"$f21", RTYPE_FPU | 21}, \
1974 {"$f22", RTYPE_FPU | 22}, \
1975 {"$f23", RTYPE_FPU | 23}, \
1976 {"$f24", RTYPE_FPU | 24}, \
1977 {"$f25", RTYPE_FPU | 25}, \
1978 {"$f26", RTYPE_FPU | 26}, \
1979 {"$f27", RTYPE_FPU | 27}, \
1980 {"$f28", RTYPE_FPU | 28}, \
1981 {"$f29", RTYPE_FPU | 29}, \
1982 {"$f30", RTYPE_FPU | 30}, \
1983 {"$f31", RTYPE_FPU | 31}
1985 #define FPU_CONDITION_CODE_NAMES \
1986 {"$fcc0", RTYPE_FCC | 0}, \
1987 {"$fcc1", RTYPE_FCC | 1}, \
1988 {"$fcc2", RTYPE_FCC | 2}, \
1989 {"$fcc3", RTYPE_FCC | 3}, \
1990 {"$fcc4", RTYPE_FCC | 4}, \
1991 {"$fcc5", RTYPE_FCC | 5}, \
1992 {"$fcc6", RTYPE_FCC | 6}, \
1993 {"$fcc7", RTYPE_FCC | 7}
1995 #define COPROC_CONDITION_CODE_NAMES \
1996 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1997 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1998 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1999 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2000 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2001 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2002 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2003 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2005 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2006 {"$a4", RTYPE_GP | 8}, \
2007 {"$a5", RTYPE_GP | 9}, \
2008 {"$a6", RTYPE_GP | 10}, \
2009 {"$a7", RTYPE_GP | 11}, \
2010 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2011 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2012 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2013 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2014 {"$t0", RTYPE_GP | 12}, \
2015 {"$t1", RTYPE_GP | 13}, \
2016 {"$t2", RTYPE_GP | 14}, \
2017 {"$t3", RTYPE_GP | 15}
2019 #define O32_SYMBOLIC_REGISTER_NAMES \
2020 {"$t0", RTYPE_GP | 8}, \
2021 {"$t1", RTYPE_GP | 9}, \
2022 {"$t2", RTYPE_GP | 10}, \
2023 {"$t3", RTYPE_GP | 11}, \
2024 {"$t4", RTYPE_GP | 12}, \
2025 {"$t5", RTYPE_GP | 13}, \
2026 {"$t6", RTYPE_GP | 14}, \
2027 {"$t7", RTYPE_GP | 15}, \
2028 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2029 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2030 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2031 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2033 /* Remaining symbolic register names */
2034 #define SYMBOLIC_REGISTER_NAMES \
2035 {"$zero", RTYPE_GP | 0}, \
2036 {"$at", RTYPE_GP | 1}, \
2037 {"$AT", RTYPE_GP | 1}, \
2038 {"$v0", RTYPE_GP | 2}, \
2039 {"$v1", RTYPE_GP | 3}, \
2040 {"$a0", RTYPE_GP | 4}, \
2041 {"$a1", RTYPE_GP | 5}, \
2042 {"$a2", RTYPE_GP | 6}, \
2043 {"$a3", RTYPE_GP | 7}, \
2044 {"$s0", RTYPE_GP | 16}, \
2045 {"$s1", RTYPE_GP | 17}, \
2046 {"$s2", RTYPE_GP | 18}, \
2047 {"$s3", RTYPE_GP | 19}, \
2048 {"$s4", RTYPE_GP | 20}, \
2049 {"$s5", RTYPE_GP | 21}, \
2050 {"$s6", RTYPE_GP | 22}, \
2051 {"$s7", RTYPE_GP | 23}, \
2052 {"$t8", RTYPE_GP | 24}, \
2053 {"$t9", RTYPE_GP | 25}, \
2054 {"$k0", RTYPE_GP | 26}, \
2055 {"$kt0", RTYPE_GP | 26}, \
2056 {"$k1", RTYPE_GP | 27}, \
2057 {"$kt1", RTYPE_GP | 27}, \
2058 {"$gp", RTYPE_GP | 28}, \
2059 {"$sp", RTYPE_GP | 29}, \
2060 {"$s8", RTYPE_GP | 30}, \
2061 {"$fp", RTYPE_GP | 30}, \
2062 {"$ra", RTYPE_GP | 31}
2064 #define MIPS16_SPECIAL_REGISTER_NAMES \
2065 {"$pc", RTYPE_PC | 0}
2067 #define MDMX_VECTOR_REGISTER_NAMES \
2068 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2069 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2070 {"$v2", RTYPE_VEC | 2}, \
2071 {"$v3", RTYPE_VEC | 3}, \
2072 {"$v4", RTYPE_VEC | 4}, \
2073 {"$v5", RTYPE_VEC | 5}, \
2074 {"$v6", RTYPE_VEC | 6}, \
2075 {"$v7", RTYPE_VEC | 7}, \
2076 {"$v8", RTYPE_VEC | 8}, \
2077 {"$v9", RTYPE_VEC | 9}, \
2078 {"$v10", RTYPE_VEC | 10}, \
2079 {"$v11", RTYPE_VEC | 11}, \
2080 {"$v12", RTYPE_VEC | 12}, \
2081 {"$v13", RTYPE_VEC | 13}, \
2082 {"$v14", RTYPE_VEC | 14}, \
2083 {"$v15", RTYPE_VEC | 15}, \
2084 {"$v16", RTYPE_VEC | 16}, \
2085 {"$v17", RTYPE_VEC | 17}, \
2086 {"$v18", RTYPE_VEC | 18}, \
2087 {"$v19", RTYPE_VEC | 19}, \
2088 {"$v20", RTYPE_VEC | 20}, \
2089 {"$v21", RTYPE_VEC | 21}, \
2090 {"$v22", RTYPE_VEC | 22}, \
2091 {"$v23", RTYPE_VEC | 23}, \
2092 {"$v24", RTYPE_VEC | 24}, \
2093 {"$v25", RTYPE_VEC | 25}, \
2094 {"$v26", RTYPE_VEC | 26}, \
2095 {"$v27", RTYPE_VEC | 27}, \
2096 {"$v28", RTYPE_VEC | 28}, \
2097 {"$v29", RTYPE_VEC | 29}, \
2098 {"$v30", RTYPE_VEC | 30}, \
2099 {"$v31", RTYPE_VEC | 31}
2101 #define MIPS_DSP_ACCUMULATOR_NAMES \
2102 {"$ac0", RTYPE_ACC | 0}, \
2103 {"$ac1", RTYPE_ACC | 1}, \
2104 {"$ac2", RTYPE_ACC | 2}, \
2105 {"$ac3", RTYPE_ACC | 3}
2107 static const struct regname reg_names[] = {
2108 GENERIC_REGISTER_NUMBERS,
2110 FPU_CONDITION_CODE_NAMES,
2111 COPROC_CONDITION_CODE_NAMES,
2113 /* The $txx registers depends on the abi,
2114 these will be added later into the symbol table from
2115 one of the tables below once mips_abi is set after
2116 parsing of arguments from the command line. */
2117 SYMBOLIC_REGISTER_NAMES,
2119 MIPS16_SPECIAL_REGISTER_NAMES,
2120 MDMX_VECTOR_REGISTER_NAMES,
2121 MIPS_DSP_ACCUMULATOR_NAMES,
2125 static const struct regname reg_names_o32[] = {
2126 O32_SYMBOLIC_REGISTER_NAMES,
2130 static const struct regname reg_names_n32n64[] = {
2131 N32N64_SYMBOLIC_REGISTER_NAMES,
2135 /* Check if S points at a valid register specifier according to TYPES.
2136 If so, then return 1, advance S to consume the specifier and store
2137 the register's number in REGNOP, otherwise return 0. */
2140 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2147 /* Find end of name. */
2149 if (is_name_beginner (*e))
2151 while (is_part_of_name (*e))
2154 /* Terminate name. */
2158 /* Look for a register symbol. */
2159 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2161 int r = S_GET_VALUE (symbolP);
2163 reg = r & RNUM_MASK;
2164 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2165 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2166 reg = (r & RNUM_MASK) - 2;
2168 /* Else see if this is a register defined in an itbl entry. */
2169 else if ((types & RTYPE_GP) && itbl_have_entries)
2176 if (itbl_get_reg_val (n, &r))
2177 reg = r & RNUM_MASK;
2180 /* Advance to next token if a register was recognised. */
2183 else if (types & RWARN)
2184 as_warn (_("Unrecognized register name `%s'"), *s);
2192 /* Check if S points at a valid register list according to TYPES.
2193 If so, then return 1, advance S to consume the list and store
2194 the registers present on the list as a bitmask of ones in REGLISTP,
2195 otherwise return 0. A valid list comprises a comma-separated
2196 enumeration of valid single registers and/or dash-separated
2197 contiguous register ranges as determined by their numbers.
2199 As a special exception if one of s0-s7 registers is specified as
2200 the range's lower delimiter and s8 (fp) is its upper one, then no
2201 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2202 are selected; they have to be listed separately if needed. */
2205 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2207 unsigned int reglist = 0;
2208 unsigned int lastregno;
2209 bfd_boolean ok = TRUE;
2210 unsigned int regmask;
2211 char *s_endlist = *s;
2215 while (reg_lookup (s, types, ®no))
2221 ok = reg_lookup (s, types, &lastregno);
2222 if (ok && lastregno < regno)
2228 if (lastregno == FP && regno >= S0 && regno <= S7)
2233 regmask = 1 << lastregno;
2234 regmask = (regmask << 1) - 1;
2235 regmask ^= (1 << regno) - 1;
2249 *reglistp = reglist;
2250 return ok && reglist != 0;
2253 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2254 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2257 is_opcode_valid (const struct mips_opcode *mo)
2259 int isa = mips_opts.isa;
2263 if (mips_opts.ase_mdmx)
2265 if (mips_opts.ase_dsp)
2267 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2269 if (mips_opts.ase_dspr2)
2271 if (mips_opts.ase_mt)
2273 if (mips_opts.ase_mips3d)
2275 if (mips_opts.ase_smartmips)
2276 ase |= ASE_SMARTMIPS;
2277 if (mips_opts.ase_mcu)
2279 if (mips_opts.ase_virt)
2281 if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
2284 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2287 /* Check whether the instruction or macro requires single-precision or
2288 double-precision floating-point support. Note that this information is
2289 stored differently in the opcode table for insns and macros. */
2290 if (mo->pinfo == INSN_MACRO)
2292 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2293 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2297 fp_s = mo->pinfo & FP_S;
2298 fp_d = mo->pinfo & FP_D;
2301 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2304 if (fp_s && mips_opts.soft_float)
2310 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2311 selected ISA and architecture. */
2314 is_opcode_valid_16 (const struct mips_opcode *mo)
2316 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2319 /* Return TRUE if the size of the microMIPS opcode MO matches one
2320 explicitly requested. Always TRUE in the standard MIPS mode. */
2323 is_size_valid (const struct mips_opcode *mo)
2325 if (!mips_opts.micromips)
2328 if (!forced_insn_length)
2330 if (mo->pinfo == INSN_MACRO)
2332 return forced_insn_length == micromips_insn_length (mo);
2335 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2336 of the preceding instruction. Always TRUE in the standard MIPS mode.
2338 We don't accept macros in 16-bit delay slots to avoid a case where
2339 a macro expansion fails because it relies on a preceding 32-bit real
2340 instruction to have matched and does not handle the operands correctly.
2341 The only macros that may expand to 16-bit instructions are JAL that
2342 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2343 and BGT (that likewise cannot be placed in a delay slot) that decay to
2344 a NOP. In all these cases the macros precede any corresponding real
2345 instruction definitions in the opcode table, so they will match in the
2346 second pass where the size of the delay slot is ignored and therefore
2347 produce correct code. */
2350 is_delay_slot_valid (const struct mips_opcode *mo)
2352 if (!mips_opts.micromips)
2355 if (mo->pinfo == INSN_MACRO)
2356 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2357 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2358 && micromips_insn_length (mo) != 4)
2360 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2361 && micromips_insn_length (mo) != 2)
2367 /* This function is called once, at assembler startup time. It should set up
2368 all the tables, etc. that the MD part of the assembler will need. */
2373 const char *retval = NULL;
2377 if (mips_pic != NO_PIC)
2379 if (g_switch_seen && g_switch_value != 0)
2380 as_bad (_("-G may not be used in position-independent code"));
2384 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2385 as_warn (_("Could not set architecture and machine"));
2387 op_hash = hash_new ();
2389 for (i = 0; i < NUMOPCODES;)
2391 const char *name = mips_opcodes[i].name;
2393 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2396 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2397 mips_opcodes[i].name, retval);
2398 /* Probably a memory allocation problem? Give up now. */
2399 as_fatal (_("Broken assembler. No assembly attempted."));
2403 if (mips_opcodes[i].pinfo != INSN_MACRO)
2405 if (!validate_mips_insn (&mips_opcodes[i]))
2407 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2409 create_insn (&nop_insn, mips_opcodes + i);
2410 if (mips_fix_loongson2f_nop)
2411 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2412 nop_insn.fixed_p = 1;
2417 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2420 mips16_op_hash = hash_new ();
2423 while (i < bfd_mips16_num_opcodes)
2425 const char *name = mips16_opcodes[i].name;
2427 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2429 as_fatal (_("internal: can't hash `%s': %s"),
2430 mips16_opcodes[i].name, retval);
2433 if (mips16_opcodes[i].pinfo != INSN_MACRO
2434 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2435 != mips16_opcodes[i].match))
2437 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2438 mips16_opcodes[i].name, mips16_opcodes[i].args);
2441 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2443 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2444 mips16_nop_insn.fixed_p = 1;
2448 while (i < bfd_mips16_num_opcodes
2449 && strcmp (mips16_opcodes[i].name, name) == 0);
2452 micromips_op_hash = hash_new ();
2455 while (i < bfd_micromips_num_opcodes)
2457 const char *name = micromips_opcodes[i].name;
2459 retval = hash_insert (micromips_op_hash, name,
2460 (void *) µmips_opcodes[i]);
2462 as_fatal (_("internal: can't hash `%s': %s"),
2463 micromips_opcodes[i].name, retval);
2465 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2467 struct mips_cl_insn *micromips_nop_insn;
2469 if (!validate_micromips_insn (µmips_opcodes[i]))
2472 if (micromips_insn_length (micromips_opcodes + i) == 2)
2473 micromips_nop_insn = µmips_nop16_insn;
2474 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2475 micromips_nop_insn = µmips_nop32_insn;
2479 if (micromips_nop_insn->insn_mo == NULL
2480 && strcmp (name, "nop") == 0)
2482 create_insn (micromips_nop_insn, micromips_opcodes + i);
2483 micromips_nop_insn->fixed_p = 1;
2486 while (++i < bfd_micromips_num_opcodes
2487 && strcmp (micromips_opcodes[i].name, name) == 0);
2491 as_fatal (_("Broken assembler. No assembly attempted."));
2493 /* We add all the general register names to the symbol table. This
2494 helps us detect invalid uses of them. */
2495 for (i = 0; reg_names[i].name; i++)
2496 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2497 reg_names[i].num, /* & RNUM_MASK, */
2498 &zero_address_frag));
2500 for (i = 0; reg_names_n32n64[i].name; i++)
2501 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2502 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2503 &zero_address_frag));
2505 for (i = 0; reg_names_o32[i].name; i++)
2506 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2507 reg_names_o32[i].num, /* & RNUM_MASK, */
2508 &zero_address_frag));
2510 mips_no_prev_insn ();
2513 mips_cprmask[0] = 0;
2514 mips_cprmask[1] = 0;
2515 mips_cprmask[2] = 0;
2516 mips_cprmask[3] = 0;
2518 /* set the default alignment for the text section (2**2) */
2519 record_alignment (text_section, 2);
2521 bfd_set_gp_size (stdoutput, g_switch_value);
2526 /* On a native system other than VxWorks, sections must be aligned
2527 to 16 byte boundaries. When configured for an embedded ELF
2528 target, we don't bother. */
2529 if (strncmp (TARGET_OS, "elf", 3) != 0
2530 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2532 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2533 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2534 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2537 /* Create a .reginfo section for register masks and a .mdebug
2538 section for debugging information. */
2546 subseg = now_subseg;
2548 /* The ABI says this section should be loaded so that the
2549 running program can access it. However, we don't load it
2550 if we are configured for an embedded target */
2551 flags = SEC_READONLY | SEC_DATA;
2552 if (strncmp (TARGET_OS, "elf", 3) != 0)
2553 flags |= SEC_ALLOC | SEC_LOAD;
2555 if (mips_abi != N64_ABI)
2557 sec = subseg_new (".reginfo", (subsegT) 0);
2559 bfd_set_section_flags (stdoutput, sec, flags);
2560 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2562 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2566 /* The 64-bit ABI uses a .MIPS.options section rather than
2567 .reginfo section. */
2568 sec = subseg_new (".MIPS.options", (subsegT) 0);
2569 bfd_set_section_flags (stdoutput, sec, flags);
2570 bfd_set_section_alignment (stdoutput, sec, 3);
2572 /* Set up the option header. */
2574 Elf_Internal_Options opthdr;
2577 opthdr.kind = ODK_REGINFO;
2578 opthdr.size = (sizeof (Elf_External_Options)
2579 + sizeof (Elf64_External_RegInfo));
2582 f = frag_more (sizeof (Elf_External_Options));
2583 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2584 (Elf_External_Options *) f);
2586 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2590 if (ECOFF_DEBUGGING)
2592 sec = subseg_new (".mdebug", (subsegT) 0);
2593 (void) bfd_set_section_flags (stdoutput, sec,
2594 SEC_HAS_CONTENTS | SEC_READONLY);
2595 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2597 else if (mips_flag_pdr)
2599 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2600 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2601 SEC_READONLY | SEC_RELOC
2603 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2606 subseg_set (seg, subseg);
2609 #endif /* OBJ_ELF */
2611 if (! ECOFF_DEBUGGING)
2614 if (mips_fix_vr4120)
2615 init_vr4120_conflicts ();
2621 mips_emit_delays ();
2622 if (! ECOFF_DEBUGGING)
2627 md_assemble (char *str)
2629 struct mips_cl_insn insn;
2630 bfd_reloc_code_real_type unused_reloc[3]
2631 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2633 imm_expr.X_op = O_absent;
2634 imm2_expr.X_op = O_absent;
2635 offset_expr.X_op = O_absent;
2636 imm_reloc[0] = BFD_RELOC_UNUSED;
2637 imm_reloc[1] = BFD_RELOC_UNUSED;
2638 imm_reloc[2] = BFD_RELOC_UNUSED;
2639 offset_reloc[0] = BFD_RELOC_UNUSED;
2640 offset_reloc[1] = BFD_RELOC_UNUSED;
2641 offset_reloc[2] = BFD_RELOC_UNUSED;
2643 mips_mark_labels ();
2644 mips_assembling_insn = TRUE;
2646 if (mips_opts.mips16)
2647 mips16_ip (str, &insn);
2650 mips_ip (str, &insn);
2651 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2652 str, insn.insn_opcode));
2656 as_bad ("%s `%s'", insn_error, str);
2657 else if (insn.insn_mo->pinfo == INSN_MACRO)
2660 if (mips_opts.mips16)
2661 mips16_macro (&insn);
2668 if (imm_expr.X_op != O_absent)
2669 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2670 else if (offset_expr.X_op != O_absent)
2671 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2673 append_insn (&insn, NULL, unused_reloc, FALSE);
2676 mips_assembling_insn = FALSE;
2679 /* Convenience functions for abstracting away the differences between
2680 MIPS16 and non-MIPS16 relocations. */
2682 static inline bfd_boolean
2683 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2687 case BFD_RELOC_MIPS16_JMP:
2688 case BFD_RELOC_MIPS16_GPREL:
2689 case BFD_RELOC_MIPS16_GOT16:
2690 case BFD_RELOC_MIPS16_CALL16:
2691 case BFD_RELOC_MIPS16_HI16_S:
2692 case BFD_RELOC_MIPS16_HI16:
2693 case BFD_RELOC_MIPS16_LO16:
2701 static inline bfd_boolean
2702 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2706 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2707 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2708 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2709 case BFD_RELOC_MICROMIPS_GPREL16:
2710 case BFD_RELOC_MICROMIPS_JMP:
2711 case BFD_RELOC_MICROMIPS_HI16:
2712 case BFD_RELOC_MICROMIPS_HI16_S:
2713 case BFD_RELOC_MICROMIPS_LO16:
2714 case BFD_RELOC_MICROMIPS_LITERAL:
2715 case BFD_RELOC_MICROMIPS_GOT16:
2716 case BFD_RELOC_MICROMIPS_CALL16:
2717 case BFD_RELOC_MICROMIPS_GOT_HI16:
2718 case BFD_RELOC_MICROMIPS_GOT_LO16:
2719 case BFD_RELOC_MICROMIPS_CALL_HI16:
2720 case BFD_RELOC_MICROMIPS_CALL_LO16:
2721 case BFD_RELOC_MICROMIPS_SUB:
2722 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2723 case BFD_RELOC_MICROMIPS_GOT_OFST:
2724 case BFD_RELOC_MICROMIPS_GOT_DISP:
2725 case BFD_RELOC_MICROMIPS_HIGHEST:
2726 case BFD_RELOC_MICROMIPS_HIGHER:
2727 case BFD_RELOC_MICROMIPS_SCN_DISP:
2728 case BFD_RELOC_MICROMIPS_JALR:
2736 static inline bfd_boolean
2737 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2739 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2742 static inline bfd_boolean
2743 got16_reloc_p (bfd_reloc_code_real_type reloc)
2745 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2746 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2749 static inline bfd_boolean
2750 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2752 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2753 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2756 static inline bfd_boolean
2757 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2759 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2760 || reloc == BFD_RELOC_MICROMIPS_LO16);
2763 static inline bfd_boolean
2764 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2766 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2769 /* Return true if RELOC is a PC-relative relocation that does not have
2770 full address range. */
2772 static inline bfd_boolean
2773 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
2777 case BFD_RELOC_16_PCREL_S2:
2778 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2779 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2780 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2783 case BFD_RELOC_32_PCREL:
2784 return HAVE_64BIT_ADDRESSES;
2791 /* Return true if the given relocation might need a matching %lo().
2792 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2793 need a matching %lo() when applied to local symbols. */
2795 static inline bfd_boolean
2796 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2798 return (HAVE_IN_PLACE_ADDENDS
2799 && (hi16_reloc_p (reloc)
2800 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2801 all GOT16 relocations evaluate to "G". */
2802 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2805 /* Return the type of %lo() reloc needed by RELOC, given that
2806 reloc_needs_lo_p. */
2808 static inline bfd_reloc_code_real_type
2809 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2811 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2812 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2816 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2819 static inline bfd_boolean
2820 fixup_has_matching_lo_p (fixS *fixp)
2822 return (fixp->fx_next != NULL
2823 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2824 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2825 && fixp->fx_offset == fixp->fx_next->fx_offset);
2828 /* This function returns true if modifying a register requires a
2832 reg_needs_delay (unsigned int reg)
2834 unsigned long prev_pinfo;
2836 prev_pinfo = history[0].insn_mo->pinfo;
2837 if (! mips_opts.noreorder
2838 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2839 && ! gpr_interlocks)
2840 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2841 && ! cop_interlocks)))
2843 /* A load from a coprocessor or from memory. All load delays
2844 delay the use of general register rt for one instruction. */
2845 /* Itbl support may require additional care here. */
2846 know (prev_pinfo & INSN_WRITE_GPR_T);
2847 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2854 /* Move all labels in LABELS to the current insertion point. TEXT_P
2855 says whether the labels refer to text or data. */
2858 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2860 struct insn_label_list *l;
2863 for (l = labels; l != NULL; l = l->next)
2865 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2866 symbol_set_frag (l->label, frag_now);
2867 val = (valueT) frag_now_fix ();
2868 /* MIPS16/microMIPS text labels are stored as odd. */
2869 if (text_p && HAVE_CODE_COMPRESSION)
2871 S_SET_VALUE (l->label, val);
2875 /* Move all labels in insn_labels to the current insertion point
2876 and treat them as text labels. */
2879 mips_move_text_labels (void)
2881 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2885 s_is_linkonce (symbolS *sym, segT from_seg)
2887 bfd_boolean linkonce = FALSE;
2888 segT symseg = S_GET_SEGMENT (sym);
2890 if (symseg != from_seg && !S_IS_LOCAL (sym))
2892 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2895 /* The GNU toolchain uses an extension for ELF: a section
2896 beginning with the magic string .gnu.linkonce is a
2897 linkonce section. */
2898 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2899 sizeof ".gnu.linkonce" - 1) == 0)
2906 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2907 linker to handle them specially, such as generating jalx instructions
2908 when needed. We also make them odd for the duration of the assembly,
2909 in order to generate the right sort of code. We will make them even
2910 in the adjust_symtab routine, while leaving them marked. This is
2911 convenient for the debugger and the disassembler. The linker knows
2912 to make them odd again. */
2915 mips_compressed_mark_label (symbolS *label)
2917 gas_assert (HAVE_CODE_COMPRESSION);
2919 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2922 if (mips_opts.mips16)
2923 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2925 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2928 if ((S_GET_VALUE (label) & 1) == 0
2929 /* Don't adjust the address if the label is global or weak, or
2930 in a link-once section, since we'll be emitting symbol reloc
2931 references to it which will be patched up by the linker, and
2932 the final value of the symbol may or may not be MIPS16/microMIPS. */
2933 && !S_IS_WEAK (label)
2934 && !S_IS_EXTERNAL (label)
2935 && !s_is_linkonce (label, now_seg))
2936 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2939 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2942 mips_compressed_mark_labels (void)
2944 struct insn_label_list *l;
2946 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2947 mips_compressed_mark_label (l->label);
2950 /* End the current frag. Make it a variant frag and record the
2954 relax_close_frag (void)
2956 mips_macro_warning.first_frag = frag_now;
2957 frag_var (rs_machine_dependent, 0, 0,
2958 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2959 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2961 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2962 mips_relax.first_fixup = 0;
2965 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2966 See the comment above RELAX_ENCODE for more details. */
2969 relax_start (symbolS *symbol)
2971 gas_assert (mips_relax.sequence == 0);
2972 mips_relax.sequence = 1;
2973 mips_relax.symbol = symbol;
2976 /* Start generating the second version of a relaxable sequence.
2977 See the comment above RELAX_ENCODE for more details. */
2982 gas_assert (mips_relax.sequence == 1);
2983 mips_relax.sequence = 2;
2986 /* End the current relaxable sequence. */
2991 gas_assert (mips_relax.sequence == 2);
2992 relax_close_frag ();
2993 mips_relax.sequence = 0;
2996 /* Return true if IP is a delayed branch or jump. */
2998 static inline bfd_boolean
2999 delayed_branch_p (const struct mips_cl_insn *ip)
3001 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3002 | INSN_COND_BRANCH_DELAY
3003 | INSN_COND_BRANCH_LIKELY)) != 0;
3006 /* Return true if IP is a compact branch or jump. */
3008 static inline bfd_boolean
3009 compact_branch_p (const struct mips_cl_insn *ip)
3011 if (mips_opts.mips16)
3012 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3013 | MIPS16_INSN_COND_BRANCH)) != 0;
3015 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3016 | INSN2_COND_BRANCH)) != 0;
3019 /* Return true if IP is an unconditional branch or jump. */
3021 static inline bfd_boolean
3022 uncond_branch_p (const struct mips_cl_insn *ip)
3024 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3025 || (mips_opts.mips16
3026 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3027 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3030 /* Return true if IP is a branch-likely instruction. */
3032 static inline bfd_boolean
3033 branch_likely_p (const struct mips_cl_insn *ip)
3035 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3038 /* Return the type of nop that should be used to fill the delay slot
3039 of delayed branch IP. */
3041 static struct mips_cl_insn *
3042 get_delay_slot_nop (const struct mips_cl_insn *ip)
3044 if (mips_opts.micromips
3045 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3046 return µmips_nop32_insn;
3050 /* Return the mask of core registers that IP reads or writes. */
3053 gpr_mod_mask (const struct mips_cl_insn *ip)
3055 unsigned long pinfo2;
3059 pinfo2 = ip->insn_mo->pinfo2;
3060 if (mips_opts.micromips)
3062 if (pinfo2 & INSN2_MOD_GPR_MD)
3063 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3064 if (pinfo2 & INSN2_MOD_GPR_MF)
3065 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3066 if (pinfo2 & INSN2_MOD_SP)
3072 /* Return the mask of core registers that IP reads. */
3075 gpr_read_mask (const struct mips_cl_insn *ip)
3077 unsigned long pinfo, pinfo2;
3080 mask = gpr_mod_mask (ip);
3081 pinfo = ip->insn_mo->pinfo;
3082 pinfo2 = ip->insn_mo->pinfo2;
3083 if (mips_opts.mips16)
3085 if (pinfo & MIPS16_INSN_READ_X)
3086 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3087 if (pinfo & MIPS16_INSN_READ_Y)
3088 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3089 if (pinfo & MIPS16_INSN_READ_T)
3091 if (pinfo & MIPS16_INSN_READ_SP)
3093 if (pinfo & MIPS16_INSN_READ_31)
3095 if (pinfo & MIPS16_INSN_READ_Z)
3096 mask |= 1 << (mips16_to_32_reg_map
3097 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3098 if (pinfo & MIPS16_INSN_READ_GPR_X)
3099 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3103 if (pinfo2 & INSN2_READ_GPR_D)
3104 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3105 if (pinfo & INSN_READ_GPR_T)
3106 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3107 if (pinfo & INSN_READ_GPR_S)
3108 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3109 if (pinfo2 & INSN2_READ_GP)
3111 if (pinfo2 & INSN2_READ_GPR_31)
3113 if (pinfo2 & INSN2_READ_GPR_Z)
3114 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3116 if (mips_opts.micromips)
3118 if (pinfo2 & INSN2_READ_GPR_MC)
3119 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3120 if (pinfo2 & INSN2_READ_GPR_ME)
3121 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3122 if (pinfo2 & INSN2_READ_GPR_MG)
3123 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3124 if (pinfo2 & INSN2_READ_GPR_MJ)
3125 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3126 if (pinfo2 & INSN2_READ_GPR_MMN)
3128 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3129 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3131 if (pinfo2 & INSN2_READ_GPR_MP)
3132 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3133 if (pinfo2 & INSN2_READ_GPR_MQ)
3134 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3136 /* Don't include register 0. */
3140 /* Return the mask of core registers that IP writes. */
3143 gpr_write_mask (const struct mips_cl_insn *ip)
3145 unsigned long pinfo, pinfo2;
3148 mask = gpr_mod_mask (ip);
3149 pinfo = ip->insn_mo->pinfo;
3150 pinfo2 = ip->insn_mo->pinfo2;
3151 if (mips_opts.mips16)
3153 if (pinfo & MIPS16_INSN_WRITE_X)
3154 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3155 if (pinfo & MIPS16_INSN_WRITE_Y)
3156 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3157 if (pinfo & MIPS16_INSN_WRITE_Z)
3158 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3159 if (pinfo & MIPS16_INSN_WRITE_T)
3161 if (pinfo & MIPS16_INSN_WRITE_SP)
3163 if (pinfo & MIPS16_INSN_WRITE_31)
3165 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3166 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3170 if (pinfo & INSN_WRITE_GPR_D)
3171 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3172 if (pinfo & INSN_WRITE_GPR_T)
3173 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3174 if (pinfo & INSN_WRITE_GPR_S)
3175 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3176 if (pinfo & INSN_WRITE_GPR_31)
3178 if (pinfo2 & INSN2_WRITE_GPR_Z)
3179 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3181 if (mips_opts.micromips)
3183 if (pinfo2 & INSN2_WRITE_GPR_MB)
3184 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3185 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3187 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3188 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3190 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3191 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3192 if (pinfo2 & INSN2_WRITE_GPR_MP)
3193 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3195 /* Don't include register 0. */
3199 /* Return the mask of floating-point registers that IP reads. */
3202 fpr_read_mask (const struct mips_cl_insn *ip)
3204 unsigned long pinfo, pinfo2;
3208 pinfo = ip->insn_mo->pinfo;
3209 pinfo2 = ip->insn_mo->pinfo2;
3210 if (!mips_opts.mips16)
3212 if (pinfo2 & INSN2_READ_FPR_D)
3213 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3214 if (pinfo & INSN_READ_FPR_S)
3215 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3216 if (pinfo & INSN_READ_FPR_T)
3217 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3218 if (pinfo & INSN_READ_FPR_R)
3219 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3220 if (pinfo2 & INSN2_READ_FPR_Z)
3221 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3223 /* Conservatively treat all operands to an FP_D instruction are doubles.
3224 (This is overly pessimistic for things like cvt.d.s.) */
3225 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3230 /* Return the mask of floating-point registers that IP writes. */
3233 fpr_write_mask (const struct mips_cl_insn *ip)
3235 unsigned long pinfo, pinfo2;
3239 pinfo = ip->insn_mo->pinfo;
3240 pinfo2 = ip->insn_mo->pinfo2;
3241 if (!mips_opts.mips16)
3243 if (pinfo & INSN_WRITE_FPR_D)
3244 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3245 if (pinfo & INSN_WRITE_FPR_S)
3246 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3247 if (pinfo & INSN_WRITE_FPR_T)
3248 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3249 if (pinfo2 & INSN2_WRITE_FPR_Z)
3250 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3252 /* Conservatively treat all operands to an FP_D instruction are doubles.
3253 (This is overly pessimistic for things like cvt.s.d.) */
3254 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3259 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3260 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3261 by VR4120 errata. */
3264 classify_vr4120_insn (const char *name)
3266 if (strncmp (name, "macc", 4) == 0)
3267 return FIX_VR4120_MACC;
3268 if (strncmp (name, "dmacc", 5) == 0)
3269 return FIX_VR4120_DMACC;
3270 if (strncmp (name, "mult", 4) == 0)
3271 return FIX_VR4120_MULT;
3272 if (strncmp (name, "dmult", 5) == 0)
3273 return FIX_VR4120_DMULT;
3274 if (strstr (name, "div"))
3275 return FIX_VR4120_DIV;
3276 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3277 return FIX_VR4120_MTHILO;
3278 return NUM_FIX_VR4120_CLASSES;
3281 #define INSN_ERET 0x42000018
3282 #define INSN_DERET 0x4200001f
3284 /* Return the number of instructions that must separate INSN1 and INSN2,
3285 where INSN1 is the earlier instruction. Return the worst-case value
3286 for any INSN2 if INSN2 is null. */
3289 insns_between (const struct mips_cl_insn *insn1,
3290 const struct mips_cl_insn *insn2)
3292 unsigned long pinfo1, pinfo2;
3295 /* This function needs to know which pinfo flags are set for INSN2
3296 and which registers INSN2 uses. The former is stored in PINFO2 and
3297 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3298 will have every flag set and INSN2_USES_GPR will always return true. */
3299 pinfo1 = insn1->insn_mo->pinfo;
3300 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3302 #define INSN2_USES_GPR(REG) \
3303 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3305 /* For most targets, write-after-read dependencies on the HI and LO
3306 registers must be separated by at least two instructions. */
3307 if (!hilo_interlocks)
3309 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3311 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3315 /* If we're working around r7000 errata, there must be two instructions
3316 between an mfhi or mflo and any instruction that uses the result. */
3317 if (mips_7000_hilo_fix
3318 && !mips_opts.micromips
3319 && MF_HILO_INSN (pinfo1)
3320 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3323 /* If we're working around 24K errata, one instruction is required
3324 if an ERET or DERET is followed by a branch instruction. */
3325 if (mips_fix_24k && !mips_opts.micromips)
3327 if (insn1->insn_opcode == INSN_ERET
3328 || insn1->insn_opcode == INSN_DERET)
3331 || insn2->insn_opcode == INSN_ERET
3332 || insn2->insn_opcode == INSN_DERET
3333 || delayed_branch_p (insn2))
3338 /* If working around VR4120 errata, check for combinations that need
3339 a single intervening instruction. */
3340 if (mips_fix_vr4120 && !mips_opts.micromips)
3342 unsigned int class1, class2;
3344 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3345 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3349 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3350 if (vr4120_conflicts[class1] & (1 << class2))
3355 if (!HAVE_CODE_COMPRESSION)
3357 /* Check for GPR or coprocessor load delays. All such delays
3358 are on the RT register. */
3359 /* Itbl support may require additional care here. */
3360 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3361 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3363 know (pinfo1 & INSN_WRITE_GPR_T);
3364 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3368 /* Check for generic coprocessor hazards.
3370 This case is not handled very well. There is no special
3371 knowledge of CP0 handling, and the coprocessors other than
3372 the floating point unit are not distinguished at all. */
3373 /* Itbl support may require additional care here. FIXME!
3374 Need to modify this to include knowledge about
3375 user specified delays! */
3376 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3377 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3379 /* Handle cases where INSN1 writes to a known general coprocessor
3380 register. There must be a one instruction delay before INSN2
3381 if INSN2 reads that register, otherwise no delay is needed. */
3382 mask = fpr_write_mask (insn1);
3385 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3390 /* Read-after-write dependencies on the control registers
3391 require a two-instruction gap. */
3392 if ((pinfo1 & INSN_WRITE_COND_CODE)
3393 && (pinfo2 & INSN_READ_COND_CODE))
3396 /* We don't know exactly what INSN1 does. If INSN2 is
3397 also a coprocessor instruction, assume there must be
3398 a one instruction gap. */
3399 if (pinfo2 & INSN_COP)
3404 /* Check for read-after-write dependencies on the coprocessor
3405 control registers in cases where INSN1 does not need a general
3406 coprocessor delay. This means that INSN1 is a floating point
3407 comparison instruction. */
3408 /* Itbl support may require additional care here. */
3409 else if (!cop_interlocks
3410 && (pinfo1 & INSN_WRITE_COND_CODE)
3411 && (pinfo2 & INSN_READ_COND_CODE))
3415 #undef INSN2_USES_GPR
3420 /* Return the number of nops that would be needed to work around the
3421 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3422 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3423 that are contained within the first IGNORE instructions of HIST. */
3426 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3427 const struct mips_cl_insn *insn)
3432 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3433 are not affected by the errata. */
3435 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3436 || strcmp (insn->insn_mo->name, "mtlo") == 0
3437 || strcmp (insn->insn_mo->name, "mthi") == 0))
3440 /* Search for the first MFLO or MFHI. */
3441 for (i = 0; i < MAX_VR4130_NOPS; i++)
3442 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3444 /* Extract the destination register. */
3445 mask = gpr_write_mask (&hist[i]);
3447 /* No nops are needed if INSN reads that register. */
3448 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3451 /* ...or if any of the intervening instructions do. */
3452 for (j = 0; j < i; j++)
3453 if (gpr_read_mask (&hist[j]) & mask)
3457 return MAX_VR4130_NOPS - i;
3462 #define BASE_REG_EQ(INSN1, INSN2) \
3463 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3464 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3466 /* Return the minimum alignment for this store instruction. */
3469 fix_24k_align_to (const struct mips_opcode *mo)
3471 if (strcmp (mo->name, "sh") == 0)
3474 if (strcmp (mo->name, "swc1") == 0
3475 || strcmp (mo->name, "swc2") == 0
3476 || strcmp (mo->name, "sw") == 0
3477 || strcmp (mo->name, "sc") == 0
3478 || strcmp (mo->name, "s.s") == 0)
3481 if (strcmp (mo->name, "sdc1") == 0
3482 || strcmp (mo->name, "sdc2") == 0
3483 || strcmp (mo->name, "s.d") == 0)
3490 struct fix_24k_store_info
3492 /* Immediate offset, if any, for this store instruction. */
3494 /* Alignment required by this store instruction. */
3496 /* True for register offsets. */
3497 int register_offset;
3500 /* Comparison function used by qsort. */
3503 fix_24k_sort (const void *a, const void *b)
3505 const struct fix_24k_store_info *pos1 = a;
3506 const struct fix_24k_store_info *pos2 = b;
3508 return (pos1->off - pos2->off);
3511 /* INSN is a store instruction. Try to record the store information
3512 in STINFO. Return false if the information isn't known. */
3515 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3516 const struct mips_cl_insn *insn)
3518 /* The instruction must have a known offset. */
3519 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3522 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3523 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3527 /* Return the number of nops that would be needed to work around the 24k
3528 "lost data on stores during refill" errata if instruction INSN
3529 immediately followed the 2 instructions described by HIST.
3530 Ignore hazards that are contained within the first IGNORE
3531 instructions of HIST.
3533 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3534 for the data cache refills and store data. The following describes
3535 the scenario where the store data could be lost.
3537 * A data cache miss, due to either a load or a store, causing fill
3538 data to be supplied by the memory subsystem
3539 * The first three doublewords of fill data are returned and written
3541 * A sequence of four stores occurs in consecutive cycles around the
3542 final doubleword of the fill:
3546 * Zero, One or more instructions
3549 The four stores A-D must be to different doublewords of the line that
3550 is being filled. The fourth instruction in the sequence above permits
3551 the fill of the final doubleword to be transferred from the FSB into
3552 the cache. In the sequence above, the stores may be either integer
3553 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3554 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3555 different doublewords on the line. If the floating point unit is
3556 running in 1:2 mode, it is not possible to create the sequence above
3557 using only floating point store instructions.
3559 In this case, the cache line being filled is incorrectly marked
3560 invalid, thereby losing the data from any store to the line that
3561 occurs between the original miss and the completion of the five
3562 cycle sequence shown above.
3564 The workarounds are:
3566 * Run the data cache in write-through mode.
3567 * Insert a non-store instruction between
3568 Store A and Store B or Store B and Store C. */
3571 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3572 const struct mips_cl_insn *insn)
3574 struct fix_24k_store_info pos[3];
3575 int align, i, base_offset;
3580 /* If the previous instruction wasn't a store, there's nothing to
3582 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3585 /* If the instructions after the previous one are unknown, we have
3586 to assume the worst. */
3590 /* Check whether we are dealing with three consecutive stores. */
3591 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3592 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3595 /* If we don't know the relationship between the store addresses,
3596 assume the worst. */
3597 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3598 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3601 if (!fix_24k_record_store_info (&pos[0], insn)
3602 || !fix_24k_record_store_info (&pos[1], &hist[0])
3603 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3606 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3608 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3609 X bytes and such that the base register + X is known to be aligned
3612 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3616 align = pos[0].align_to;
3617 base_offset = pos[0].off;
3618 for (i = 1; i < 3; i++)
3619 if (align < pos[i].align_to)
3621 align = pos[i].align_to;
3622 base_offset = pos[i].off;
3624 for (i = 0; i < 3; i++)
3625 pos[i].off -= base_offset;
3628 pos[0].off &= ~align + 1;
3629 pos[1].off &= ~align + 1;
3630 pos[2].off &= ~align + 1;
3632 /* If any two stores write to the same chunk, they also write to the
3633 same doubleword. The offsets are still sorted at this point. */
3634 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3637 /* A range of at least 9 bytes is needed for the stores to be in
3638 non-overlapping doublewords. */
3639 if (pos[2].off - pos[0].off <= 8)
3642 if (pos[2].off - pos[1].off >= 24
3643 || pos[1].off - pos[0].off >= 24
3644 || pos[2].off - pos[0].off >= 32)
3650 /* Return the number of nops that would be needed if instruction INSN
3651 immediately followed the MAX_NOPS instructions given by HIST,
3652 where HIST[0] is the most recent instruction. Ignore hazards
3653 between INSN and the first IGNORE instructions in HIST.
3655 If INSN is null, return the worse-case number of nops for any
3659 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3660 const struct mips_cl_insn *insn)
3662 int i, nops, tmp_nops;
3665 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3667 tmp_nops = insns_between (hist + i, insn) - i;
3668 if (tmp_nops > nops)
3672 if (mips_fix_vr4130 && !mips_opts.micromips)
3674 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3675 if (tmp_nops > nops)
3679 if (mips_fix_24k && !mips_opts.micromips)
3681 tmp_nops = nops_for_24k (ignore, hist, insn);
3682 if (tmp_nops > nops)
3689 /* The variable arguments provide NUM_INSNS extra instructions that
3690 might be added to HIST. Return the largest number of nops that
3691 would be needed after the extended sequence, ignoring hazards
3692 in the first IGNORE instructions. */
3695 nops_for_sequence (int num_insns, int ignore,
3696 const struct mips_cl_insn *hist, ...)
3699 struct mips_cl_insn buffer[MAX_NOPS];
3700 struct mips_cl_insn *cursor;
3703 va_start (args, hist);
3704 cursor = buffer + num_insns;
3705 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3706 while (cursor > buffer)
3707 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3709 nops = nops_for_insn (ignore, buffer, NULL);
3714 /* Like nops_for_insn, but if INSN is a branch, take into account the
3715 worst-case delay for the branch target. */
3718 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3719 const struct mips_cl_insn *insn)
3723 nops = nops_for_insn (ignore, hist, insn);
3724 if (delayed_branch_p (insn))
3726 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3727 hist, insn, get_delay_slot_nop (insn));
3728 if (tmp_nops > nops)
3731 else if (compact_branch_p (insn))
3733 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3734 if (tmp_nops > nops)
3740 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3743 fix_loongson2f_nop (struct mips_cl_insn * ip)
3745 gas_assert (!HAVE_CODE_COMPRESSION);
3746 if (strcmp (ip->insn_mo->name, "nop") == 0)
3747 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3750 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3751 jr target pc &= 'hffff_ffff_cfff_ffff. */
3754 fix_loongson2f_jump (struct mips_cl_insn * ip)
3756 gas_assert (!HAVE_CODE_COMPRESSION);
3757 if (strcmp (ip->insn_mo->name, "j") == 0
3758 || strcmp (ip->insn_mo->name, "jr") == 0
3759 || strcmp (ip->insn_mo->name, "jalr") == 0)
3767 sreg = EXTRACT_OPERAND (0, RS, *ip);
3768 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3771 ep.X_op = O_constant;
3772 ep.X_add_number = 0xcfff0000;
3773 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3774 ep.X_add_number = 0xffff;
3775 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3776 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3781 fix_loongson2f (struct mips_cl_insn * ip)
3783 if (mips_fix_loongson2f_nop)
3784 fix_loongson2f_nop (ip);
3786 if (mips_fix_loongson2f_jump)
3787 fix_loongson2f_jump (ip);
3790 /* IP is a branch that has a delay slot, and we need to fill it
3791 automatically. Return true if we can do that by swapping IP
3792 with the previous instruction.
3793 ADDRESS_EXPR is an operand of the instruction to be used with
3797 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3798 bfd_reloc_code_real_type *reloc_type)
3800 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3801 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3803 /* -O2 and above is required for this optimization. */
3804 if (mips_optimize < 2)
3807 /* If we have seen .set volatile or .set nomove, don't optimize. */
3808 if (mips_opts.nomove)
3811 /* We can't swap if the previous instruction's position is fixed. */
3812 if (history[0].fixed_p)
3815 /* If the previous previous insn was in a .set noreorder, we can't
3816 swap. Actually, the MIPS assembler will swap in this situation.
3817 However, gcc configured -with-gnu-as will generate code like
3825 in which we can not swap the bne and INSN. If gcc is not configured
3826 -with-gnu-as, it does not output the .set pseudo-ops. */
3827 if (history[1].noreorder_p)
3830 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3831 This means that the previous instruction was a 4-byte one anyhow. */
3832 if (mips_opts.mips16 && history[0].fixp[0])
3835 /* If the branch is itself the target of a branch, we can not swap.
3836 We cheat on this; all we check for is whether there is a label on
3837 this instruction. If there are any branches to anything other than
3838 a label, users must use .set noreorder. */
3839 if (seg_info (now_seg)->label_list)
3842 /* If the previous instruction is in a variant frag other than this
3843 branch's one, we cannot do the swap. This does not apply to
3844 MIPS16 code, which uses variant frags for different purposes. */
3845 if (!mips_opts.mips16
3847 && history[0].frag->fr_type == rs_machine_dependent)
3850 /* We do not swap with instructions that cannot architecturally
3851 be placed in a branch delay slot, such as SYNC or ERET. We
3852 also refrain from swapping with a trap instruction, since it
3853 complicates trap handlers to have the trap instruction be in
3855 prev_pinfo = history[0].insn_mo->pinfo;
3856 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3859 /* Check for conflicts between the branch and the instructions
3860 before the candidate delay slot. */
3861 if (nops_for_insn (0, history + 1, ip) > 0)
3864 /* Check for conflicts between the swapped sequence and the
3865 target of the branch. */
3866 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3869 /* If the branch reads a register that the previous
3870 instruction sets, we can not swap. */
3871 gpr_read = gpr_read_mask (ip);
3872 prev_gpr_write = gpr_write_mask (&history[0]);
3873 if (gpr_read & prev_gpr_write)
3876 /* If the branch writes a register that the previous
3877 instruction sets, we can not swap. */
3878 gpr_write = gpr_write_mask (ip);
3879 if (gpr_write & prev_gpr_write)
3882 /* If the branch writes a register that the previous
3883 instruction reads, we can not swap. */
3884 prev_gpr_read = gpr_read_mask (&history[0]);
3885 if (gpr_write & prev_gpr_read)
3888 /* If one instruction sets a condition code and the
3889 other one uses a condition code, we can not swap. */
3890 pinfo = ip->insn_mo->pinfo;
3891 if ((pinfo & INSN_READ_COND_CODE)
3892 && (prev_pinfo & INSN_WRITE_COND_CODE))
3894 if ((pinfo & INSN_WRITE_COND_CODE)
3895 && (prev_pinfo & INSN_READ_COND_CODE))
3898 /* If the previous instruction uses the PC, we can not swap. */
3899 prev_pinfo2 = history[0].insn_mo->pinfo2;
3900 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3902 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3905 /* If the previous instruction has an incorrect size for a fixed
3906 branch delay slot in microMIPS mode, we cannot swap. */
3907 pinfo2 = ip->insn_mo->pinfo2;
3908 if (mips_opts.micromips
3909 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3910 && insn_length (history) != 2)
3912 if (mips_opts.micromips
3913 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3914 && insn_length (history) != 4)
3917 /* On R5900 short loops need to be fixed by inserting a nop in
3918 the branch delay slots.
3919 A short loop can be terminated too early. */
3920 if (mips_opts.arch == CPU_R5900
3921 /* Check if instruction has a parameter, ignore "j $31". */
3922 && (address_expr != NULL)
3923 /* Parameter must be 16 bit. */
3924 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3925 /* Branch to same segment. */
3926 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3927 /* Branch to same code fragment. */
3928 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3929 /* Can only calculate branch offset if value is known. */
3930 && symbol_constant_p(address_expr->X_add_symbol)
3931 /* Check if branch is really conditional. */
3932 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3933 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3934 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3937 /* Check if loop is shorter than 6 instructions including
3938 branch and delay slot. */
3939 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3946 /* When the loop includes branches or jumps,
3947 it is not a short loop. */
3948 for (i = 0; i < (distance / 4); i++)
3950 if ((history[i].cleared_p)
3951 || delayed_branch_p(&history[i]))
3959 /* Insert nop after branch to fix short loop. */
3968 /* Decide how we should add IP to the instruction stream.
3969 ADDRESS_EXPR is an operand of the instruction to be used with
3972 static enum append_method
3973 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3974 bfd_reloc_code_real_type *reloc_type)
3976 unsigned long pinfo;
3978 /* The relaxed version of a macro sequence must be inherently
3980 if (mips_relax.sequence == 2)
3983 /* We must not dabble with instructions in a ".set norerorder" block. */
3984 if (mips_opts.noreorder)
3987 /* Otherwise, it's our responsibility to fill branch delay slots. */
3988 if (delayed_branch_p (ip))
3990 if (!branch_likely_p (ip)
3991 && can_swap_branch_p (ip, address_expr, reloc_type))
3994 pinfo = ip->insn_mo->pinfo;
3995 if (mips_opts.mips16
3996 && ISA_SUPPORTS_MIPS16E
3997 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3998 return APPEND_ADD_COMPACT;
4000 return APPEND_ADD_WITH_NOP;
4006 /* IP is a MIPS16 instruction whose opcode we have just changed.
4007 Point IP->insn_mo to the new opcode's definition. */
4010 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4012 const struct mips_opcode *mo, *end;
4014 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4015 for (mo = ip->insn_mo; mo < end; mo++)
4016 if ((ip->insn_opcode & mo->mask) == mo->match)
4024 /* For microMIPS macros, we need to generate a local number label
4025 as the target of branches. */
4026 #define MICROMIPS_LABEL_CHAR '\037'
4027 static unsigned long micromips_target_label;
4028 static char micromips_target_name[32];
4031 micromips_label_name (void)
4033 char *p = micromips_target_name;
4034 char symbol_name_temporary[24];
4042 l = micromips_target_label;
4043 #ifdef LOCAL_LABEL_PREFIX
4044 *p++ = LOCAL_LABEL_PREFIX;
4047 *p++ = MICROMIPS_LABEL_CHAR;
4050 symbol_name_temporary[i++] = l % 10 + '0';
4055 *p++ = symbol_name_temporary[--i];
4058 return micromips_target_name;
4062 micromips_label_expr (expressionS *label_expr)
4064 label_expr->X_op = O_symbol;
4065 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4066 label_expr->X_add_number = 0;
4070 micromips_label_inc (void)
4072 micromips_target_label++;
4073 *micromips_target_name = '\0';
4077 micromips_add_label (void)
4081 s = colon (micromips_label_name ());
4082 micromips_label_inc ();
4083 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4085 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4091 /* If assembling microMIPS code, then return the microMIPS reloc
4092 corresponding to the requested one if any. Otherwise return
4093 the reloc unchanged. */
4095 static bfd_reloc_code_real_type
4096 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4098 static const bfd_reloc_code_real_type relocs[][2] =
4100 /* Keep sorted incrementally by the left-hand key. */
4101 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4102 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4103 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4104 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4105 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4106 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4107 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4108 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4109 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4110 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4111 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4112 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4113 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4114 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4115 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4116 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4117 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4118 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4119 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4120 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4121 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4122 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4123 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4124 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4125 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4126 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4127 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4129 bfd_reloc_code_real_type r;
4132 if (!mips_opts.micromips)
4134 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4140 return relocs[i][1];
4145 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4146 Return true on success, storing the resolved value in RESULT. */
4149 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4154 case BFD_RELOC_MIPS_HIGHEST:
4155 case BFD_RELOC_MICROMIPS_HIGHEST:
4156 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4159 case BFD_RELOC_MIPS_HIGHER:
4160 case BFD_RELOC_MICROMIPS_HIGHER:
4161 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4164 case BFD_RELOC_HI16_S:
4165 case BFD_RELOC_MICROMIPS_HI16_S:
4166 case BFD_RELOC_MIPS16_HI16_S:
4167 *result = ((operand + 0x8000) >> 16) & 0xffff;
4170 case BFD_RELOC_HI16:
4171 case BFD_RELOC_MICROMIPS_HI16:
4172 case BFD_RELOC_MIPS16_HI16:
4173 *result = (operand >> 16) & 0xffff;
4176 case BFD_RELOC_LO16:
4177 case BFD_RELOC_MICROMIPS_LO16:
4178 case BFD_RELOC_MIPS16_LO16:
4179 *result = operand & 0xffff;
4182 case BFD_RELOC_UNUSED:
4191 /* Output an instruction. IP is the instruction information.
4192 ADDRESS_EXPR is an operand of the instruction to be used with
4193 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4194 a macro expansion. */
4197 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4198 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4200 unsigned long prev_pinfo2, pinfo;
4201 bfd_boolean relaxed_branch = FALSE;
4202 enum append_method method;
4203 bfd_boolean relax32;
4206 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4207 fix_loongson2f (ip);
4209 file_ase_mips16 |= mips_opts.mips16;
4210 file_ase_micromips |= mips_opts.micromips;
4212 prev_pinfo2 = history[0].insn_mo->pinfo2;
4213 pinfo = ip->insn_mo->pinfo;
4215 if (mips_opts.micromips
4217 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4218 && micromips_insn_length (ip->insn_mo) != 2)
4219 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4220 && micromips_insn_length (ip->insn_mo) != 4)))
4221 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4222 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4224 if (address_expr == NULL)
4226 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4227 && reloc_type[1] == BFD_RELOC_UNUSED
4228 && reloc_type[2] == BFD_RELOC_UNUSED
4229 && address_expr->X_op == O_constant)
4231 switch (*reloc_type)
4233 case BFD_RELOC_MIPS_JMP:
4237 shift = mips_opts.micromips ? 1 : 2;
4238 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4239 as_bad (_("jump to misaligned address (0x%lx)"),
4240 (unsigned long) address_expr->X_add_number);
4241 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4247 case BFD_RELOC_MIPS16_JMP:
4248 if ((address_expr->X_add_number & 3) != 0)
4249 as_bad (_("jump to misaligned address (0x%lx)"),
4250 (unsigned long) address_expr->X_add_number);
4252 (((address_expr->X_add_number & 0x7c0000) << 3)
4253 | ((address_expr->X_add_number & 0xf800000) >> 7)
4254 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4258 case BFD_RELOC_16_PCREL_S2:
4262 shift = mips_opts.micromips ? 1 : 2;
4263 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4264 as_bad (_("branch to misaligned address (0x%lx)"),
4265 (unsigned long) address_expr->X_add_number);
4266 if (!mips_relax_branch)
4268 if ((address_expr->X_add_number + (1 << (shift + 15)))
4269 & ~((1 << (shift + 16)) - 1))
4270 as_bad (_("branch address range overflow (0x%lx)"),
4271 (unsigned long) address_expr->X_add_number);
4272 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4282 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4285 ip->insn_opcode |= value & 0xffff;
4293 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4295 /* There are a lot of optimizations we could do that we don't.
4296 In particular, we do not, in general, reorder instructions.
4297 If you use gcc with optimization, it will reorder
4298 instructions and generally do much more optimization then we
4299 do here; repeating all that work in the assembler would only
4300 benefit hand written assembly code, and does not seem worth
4302 int nops = (mips_optimize == 0
4303 ? nops_for_insn (0, history, NULL)
4304 : nops_for_insn_or_target (0, history, ip));
4308 unsigned long old_frag_offset;
4311 old_frag = frag_now;
4312 old_frag_offset = frag_now_fix ();
4314 for (i = 0; i < nops; i++)
4315 add_fixed_insn (NOP_INSN);
4316 insert_into_history (0, nops, NOP_INSN);
4320 listing_prev_line ();
4321 /* We may be at the start of a variant frag. In case we
4322 are, make sure there is enough space for the frag
4323 after the frags created by listing_prev_line. The
4324 argument to frag_grow here must be at least as large
4325 as the argument to all other calls to frag_grow in
4326 this file. We don't have to worry about being in the
4327 middle of a variant frag, because the variants insert
4328 all needed nop instructions themselves. */
4332 mips_move_text_labels ();
4334 #ifndef NO_ECOFF_DEBUGGING
4335 if (ECOFF_DEBUGGING)
4336 ecoff_fix_loc (old_frag, old_frag_offset);
4340 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4344 /* Work out how many nops in prev_nop_frag are needed by IP,
4345 ignoring hazards generated by the first prev_nop_frag_since
4347 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4348 gas_assert (nops <= prev_nop_frag_holds);
4350 /* Enforce NOPS as a minimum. */
4351 if (nops > prev_nop_frag_required)
4352 prev_nop_frag_required = nops;
4354 if (prev_nop_frag_holds == prev_nop_frag_required)
4356 /* Settle for the current number of nops. Update the history
4357 accordingly (for the benefit of any future .set reorder code). */
4358 prev_nop_frag = NULL;
4359 insert_into_history (prev_nop_frag_since,
4360 prev_nop_frag_holds, NOP_INSN);
4364 /* Allow this instruction to replace one of the nops that was
4365 tentatively added to prev_nop_frag. */
4366 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4367 prev_nop_frag_holds--;
4368 prev_nop_frag_since++;
4372 method = get_append_method (ip, address_expr, reloc_type);
4373 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4376 dwarf2_emit_insn (0);
4377 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4378 so "move" the instruction address accordingly.
4380 Also, it doesn't seem appropriate for the assembler to reorder .loc
4381 entries. If this instruction is a branch that we are going to swap
4382 with the previous instruction, the two instructions should be
4383 treated as a unit, and the debug information for both instructions
4384 should refer to the start of the branch sequence. Using the
4385 current position is certainly wrong when swapping a 32-bit branch
4386 and a 16-bit delay slot, since the current position would then be
4387 in the middle of a branch. */
4388 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4391 relax32 = (mips_relax_branch
4392 /* Don't try branch relaxation within .set nomacro, or within
4393 .set noat if we use $at for PIC computations. If it turns
4394 out that the branch was out-of-range, we'll get an error. */
4395 && !mips_opts.warn_about_macros
4396 && (mips_opts.at || mips_pic == NO_PIC)
4397 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4398 as they have no complementing branches. */
4399 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4401 if (!HAVE_CODE_COMPRESSION
4404 && *reloc_type == BFD_RELOC_16_PCREL_S2
4405 && delayed_branch_p (ip))
4407 relaxed_branch = TRUE;
4408 add_relaxed_insn (ip, (relaxed_branch_length
4410 uncond_branch_p (ip) ? -1
4411 : branch_likely_p (ip) ? 1
4415 uncond_branch_p (ip),
4416 branch_likely_p (ip),
4417 pinfo & INSN_WRITE_GPR_31,
4419 address_expr->X_add_symbol,
4420 address_expr->X_add_number);
4421 *reloc_type = BFD_RELOC_UNUSED;
4423 else if (mips_opts.micromips
4425 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4426 || *reloc_type > BFD_RELOC_UNUSED)
4427 && (delayed_branch_p (ip) || compact_branch_p (ip))
4428 /* Don't try branch relaxation when users specify
4429 16-bit/32-bit instructions. */
4430 && !forced_insn_length)
4432 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4433 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4434 int uncond = uncond_branch_p (ip) ? -1 : 0;
4435 int compact = compact_branch_p (ip);
4436 int al = pinfo & INSN_WRITE_GPR_31;
4439 gas_assert (address_expr != NULL);
4440 gas_assert (!mips_relax.sequence);
4442 relaxed_branch = TRUE;
4443 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4444 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4445 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4447 address_expr->X_add_symbol,
4448 address_expr->X_add_number);
4449 *reloc_type = BFD_RELOC_UNUSED;
4451 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4453 /* We need to set up a variant frag. */
4454 gas_assert (address_expr != NULL);
4455 add_relaxed_insn (ip, 4, 0,
4457 (*reloc_type - BFD_RELOC_UNUSED,
4458 forced_insn_length == 2, forced_insn_length == 4,
4459 delayed_branch_p (&history[0]),
4460 history[0].mips16_absolute_jump_p),
4461 make_expr_symbol (address_expr), 0);
4463 else if (mips_opts.mips16 && insn_length (ip) == 2)
4465 if (!delayed_branch_p (ip))
4466 /* Make sure there is enough room to swap this instruction with
4467 a following jump instruction. */
4469 add_fixed_insn (ip);
4473 if (mips_opts.mips16
4474 && mips_opts.noreorder
4475 && delayed_branch_p (&history[0]))
4476 as_warn (_("extended instruction in delay slot"));
4478 if (mips_relax.sequence)
4480 /* If we've reached the end of this frag, turn it into a variant
4481 frag and record the information for the instructions we've
4483 if (frag_room () < 4)
4484 relax_close_frag ();
4485 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4488 if (mips_relax.sequence != 2)
4490 if (mips_macro_warning.first_insn_sizes[0] == 0)
4491 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4492 mips_macro_warning.sizes[0] += insn_length (ip);
4493 mips_macro_warning.insns[0]++;
4495 if (mips_relax.sequence != 1)
4497 if (mips_macro_warning.first_insn_sizes[1] == 0)
4498 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4499 mips_macro_warning.sizes[1] += insn_length (ip);
4500 mips_macro_warning.insns[1]++;
4503 if (mips_opts.mips16)
4506 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4508 add_fixed_insn (ip);
4511 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4513 bfd_reloc_code_real_type final_type[3];
4514 reloc_howto_type *howto0;
4515 reloc_howto_type *howto;
4518 /* Perform any necessary conversion to microMIPS relocations
4519 and find out how many relocations there actually are. */
4520 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4521 final_type[i] = micromips_map_reloc (reloc_type[i]);
4523 /* In a compound relocation, it is the final (outermost)
4524 operator that determines the relocated field. */
4525 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4529 /* To reproduce this failure try assembling gas/testsuites/
4530 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4532 as_bad (_("Unsupported MIPS relocation number %d"),
4534 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4538 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4539 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4540 bfd_get_reloc_size (howto),
4542 howto0 && howto0->pc_relative,
4545 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4546 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4547 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4549 /* These relocations can have an addend that won't fit in
4550 4 octets for 64bit assembly. */
4552 && ! howto->partial_inplace
4553 && (reloc_type[0] == BFD_RELOC_16
4554 || reloc_type[0] == BFD_RELOC_32
4555 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4556 || reloc_type[0] == BFD_RELOC_GPREL16
4557 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4558 || reloc_type[0] == BFD_RELOC_GPREL32
4559 || reloc_type[0] == BFD_RELOC_64
4560 || reloc_type[0] == BFD_RELOC_CTOR
4561 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4562 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4563 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4564 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4565 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4566 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4567 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4568 || hi16_reloc_p (reloc_type[0])
4569 || lo16_reloc_p (reloc_type[0])))
4570 ip->fixp[0]->fx_no_overflow = 1;
4572 /* These relocations can have an addend that won't fit in 2 octets. */
4573 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4574 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4575 ip->fixp[0]->fx_no_overflow = 1;
4577 if (mips_relax.sequence)
4579 if (mips_relax.first_fixup == 0)
4580 mips_relax.first_fixup = ip->fixp[0];
4582 else if (reloc_needs_lo_p (*reloc_type))
4584 struct mips_hi_fixup *hi_fixup;
4586 /* Reuse the last entry if it already has a matching %lo. */
4587 hi_fixup = mips_hi_fixup_list;
4589 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4591 hi_fixup = ((struct mips_hi_fixup *)
4592 xmalloc (sizeof (struct mips_hi_fixup)));
4593 hi_fixup->next = mips_hi_fixup_list;
4594 mips_hi_fixup_list = hi_fixup;
4596 hi_fixup->fixp = ip->fixp[0];
4597 hi_fixup->seg = now_seg;
4600 /* Add fixups for the second and third relocations, if given.
4601 Note that the ABI allows the second relocation to be
4602 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4603 moment we only use RSS_UNDEF, but we could add support
4604 for the others if it ever becomes necessary. */
4605 for (i = 1; i < 3; i++)
4606 if (reloc_type[i] != BFD_RELOC_UNUSED)
4608 ip->fixp[i] = fix_new (ip->frag, ip->where,
4609 ip->fixp[0]->fx_size, NULL, 0,
4610 FALSE, final_type[i]);
4612 /* Use fx_tcbit to mark compound relocs. */
4613 ip->fixp[0]->fx_tcbit = 1;
4614 ip->fixp[i]->fx_tcbit = 1;
4619 /* Update the register mask information. */
4620 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4621 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4626 insert_into_history (0, 1, ip);
4629 case APPEND_ADD_WITH_NOP:
4631 struct mips_cl_insn *nop;
4633 insert_into_history (0, 1, ip);
4634 nop = get_delay_slot_nop (ip);
4635 add_fixed_insn (nop);
4636 insert_into_history (0, 1, nop);
4637 if (mips_relax.sequence)
4638 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4642 case APPEND_ADD_COMPACT:
4643 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4644 gas_assert (mips_opts.mips16);
4645 ip->insn_opcode |= 0x0080;
4646 find_altered_mips16_opcode (ip);
4648 insert_into_history (0, 1, ip);
4653 struct mips_cl_insn delay = history[0];
4654 if (mips_opts.mips16)
4656 know (delay.frag == ip->frag);
4657 move_insn (ip, delay.frag, delay.where);
4658 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4660 else if (relaxed_branch || delay.frag != ip->frag)
4662 /* Add the delay slot instruction to the end of the
4663 current frag and shrink the fixed part of the
4664 original frag. If the branch occupies the tail of
4665 the latter, move it backwards to cover the gap. */
4666 delay.frag->fr_fix -= branch_disp;
4667 if (delay.frag == ip->frag)
4668 move_insn (ip, ip->frag, ip->where - branch_disp);
4669 add_fixed_insn (&delay);
4673 move_insn (&delay, ip->frag,
4674 ip->where - branch_disp + insn_length (ip));
4675 move_insn (ip, history[0].frag, history[0].where);
4679 insert_into_history (0, 1, &delay);
4684 /* If we have just completed an unconditional branch, clear the history. */
4685 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4686 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4690 mips_no_prev_insn ();
4692 for (i = 0; i < ARRAY_SIZE (history); i++)
4693 history[i].cleared_p = 1;
4696 /* We need to emit a label at the end of branch-likely macros. */
4697 if (emit_branch_likely_macro)
4699 emit_branch_likely_macro = FALSE;
4700 micromips_add_label ();
4703 /* We just output an insn, so the next one doesn't have a label. */
4704 mips_clear_insn_labels ();
4707 /* Forget that there was any previous instruction or label.
4708 When BRANCH is true, the branch history is also flushed. */
4711 mips_no_prev_insn (void)
4713 prev_nop_frag = NULL;
4714 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4715 mips_clear_insn_labels ();
4718 /* This function must be called before we emit something other than
4719 instructions. It is like mips_no_prev_insn except that it inserts
4720 any NOPS that might be needed by previous instructions. */
4723 mips_emit_delays (void)
4725 if (! mips_opts.noreorder)
4727 int nops = nops_for_insn (0, history, NULL);
4731 add_fixed_insn (NOP_INSN);
4732 mips_move_text_labels ();
4735 mips_no_prev_insn ();
4738 /* Start a (possibly nested) noreorder block. */
4741 start_noreorder (void)
4743 if (mips_opts.noreorder == 0)
4748 /* None of the instructions before the .set noreorder can be moved. */
4749 for (i = 0; i < ARRAY_SIZE (history); i++)
4750 history[i].fixed_p = 1;
4752 /* Insert any nops that might be needed between the .set noreorder
4753 block and the previous instructions. We will later remove any
4754 nops that turn out not to be needed. */
4755 nops = nops_for_insn (0, history, NULL);
4758 if (mips_optimize != 0)
4760 /* Record the frag which holds the nop instructions, so
4761 that we can remove them if we don't need them. */
4762 frag_grow (nops * NOP_INSN_SIZE);
4763 prev_nop_frag = frag_now;
4764 prev_nop_frag_holds = nops;
4765 prev_nop_frag_required = 0;
4766 prev_nop_frag_since = 0;
4769 for (; nops > 0; --nops)
4770 add_fixed_insn (NOP_INSN);
4772 /* Move on to a new frag, so that it is safe to simply
4773 decrease the size of prev_nop_frag. */
4774 frag_wane (frag_now);
4776 mips_move_text_labels ();
4778 mips_mark_labels ();
4779 mips_clear_insn_labels ();
4781 mips_opts.noreorder++;
4782 mips_any_noreorder = 1;
4785 /* End a nested noreorder block. */
4788 end_noreorder (void)
4790 mips_opts.noreorder--;
4791 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4793 /* Commit to inserting prev_nop_frag_required nops and go back to
4794 handling nop insertion the .set reorder way. */
4795 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4797 insert_into_history (prev_nop_frag_since,
4798 prev_nop_frag_required, NOP_INSN);
4799 prev_nop_frag = NULL;
4803 /* Set up global variables for the start of a new macro. */
4808 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4809 memset (&mips_macro_warning.first_insn_sizes, 0,
4810 sizeof (mips_macro_warning.first_insn_sizes));
4811 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4812 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4813 && delayed_branch_p (&history[0]));
4814 switch (history[0].insn_mo->pinfo2
4815 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4817 case INSN2_BRANCH_DELAY_32BIT:
4818 mips_macro_warning.delay_slot_length = 4;
4820 case INSN2_BRANCH_DELAY_16BIT:
4821 mips_macro_warning.delay_slot_length = 2;
4824 mips_macro_warning.delay_slot_length = 0;
4827 mips_macro_warning.first_frag = NULL;
4830 /* Given that a macro is longer than one instruction or of the wrong size,
4831 return the appropriate warning for it. Return null if no warning is
4832 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4833 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4834 and RELAX_NOMACRO. */
4837 macro_warning (relax_substateT subtype)
4839 if (subtype & RELAX_DELAY_SLOT)
4840 return _("Macro instruction expanded into multiple instructions"
4841 " in a branch delay slot");
4842 else if (subtype & RELAX_NOMACRO)
4843 return _("Macro instruction expanded into multiple instructions");
4844 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4845 | RELAX_DELAY_SLOT_SIZE_SECOND))
4846 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4847 ? _("Macro instruction expanded into a wrong size instruction"
4848 " in a 16-bit branch delay slot")
4849 : _("Macro instruction expanded into a wrong size instruction"
4850 " in a 32-bit branch delay slot"));
4855 /* Finish up a macro. Emit warnings as appropriate. */
4860 /* Relaxation warning flags. */
4861 relax_substateT subtype = 0;
4863 /* Check delay slot size requirements. */
4864 if (mips_macro_warning.delay_slot_length == 2)
4865 subtype |= RELAX_DELAY_SLOT_16BIT;
4866 if (mips_macro_warning.delay_slot_length != 0)
4868 if (mips_macro_warning.delay_slot_length
4869 != mips_macro_warning.first_insn_sizes[0])
4870 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4871 if (mips_macro_warning.delay_slot_length
4872 != mips_macro_warning.first_insn_sizes[1])
4873 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4876 /* Check instruction count requirements. */
4877 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4879 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4880 subtype |= RELAX_SECOND_LONGER;
4881 if (mips_opts.warn_about_macros)
4882 subtype |= RELAX_NOMACRO;
4883 if (mips_macro_warning.delay_slot_p)
4884 subtype |= RELAX_DELAY_SLOT;
4887 /* If both alternatives fail to fill a delay slot correctly,
4888 emit the warning now. */
4889 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4890 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4895 s = subtype & (RELAX_DELAY_SLOT_16BIT
4896 | RELAX_DELAY_SLOT_SIZE_FIRST
4897 | RELAX_DELAY_SLOT_SIZE_SECOND);
4898 msg = macro_warning (s);
4900 as_warn ("%s", msg);
4904 /* If both implementations are longer than 1 instruction, then emit the
4906 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4911 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4912 msg = macro_warning (s);
4914 as_warn ("%s", msg);
4918 /* If any flags still set, then one implementation might need a warning
4919 and the other either will need one of a different kind or none at all.
4920 Pass any remaining flags over to relaxation. */
4921 if (mips_macro_warning.first_frag != NULL)
4922 mips_macro_warning.first_frag->fr_subtype |= subtype;
4925 /* Instruction operand formats used in macros that vary between
4926 standard MIPS and microMIPS code. */
4928 static const char * const brk_fmt[2] = { "c", "mF" };
4929 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4930 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4931 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4932 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4933 static const char * const mfhl_fmt[2] = { "d", "mj" };
4934 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4935 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4937 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4938 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4939 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4940 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4941 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4942 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4943 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4944 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4946 /* Read a macro's relocation codes from *ARGS and store them in *R.
4947 The first argument in *ARGS will be either the code for a single
4948 relocation or -1 followed by the three codes that make up a
4949 composite relocation. */
4952 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4956 next = va_arg (*args, int);
4958 r[0] = (bfd_reloc_code_real_type) next;
4960 for (i = 0; i < 3; i++)
4961 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4964 /* Build an instruction created by a macro expansion. This is passed
4965 a pointer to the count of instructions created so far, an
4966 expression, the name of the instruction to build, an operand format
4967 string, and corresponding arguments. */
4970 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4972 const struct mips_opcode *mo = NULL;
4973 bfd_reloc_code_real_type r[3];
4974 const struct mips_opcode *amo;
4975 struct hash_control *hash;
4976 struct mips_cl_insn insn;
4979 va_start (args, fmt);
4981 if (mips_opts.mips16)
4983 mips16_macro_build (ep, name, fmt, &args);
4988 r[0] = BFD_RELOC_UNUSED;
4989 r[1] = BFD_RELOC_UNUSED;
4990 r[2] = BFD_RELOC_UNUSED;
4991 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4992 amo = (struct mips_opcode *) hash_find (hash, name);
4994 gas_assert (strcmp (name, amo->name) == 0);
4998 /* Search until we get a match for NAME. It is assumed here that
4999 macros will never generate MDMX, MIPS-3D, or MT instructions.
5000 We try to match an instruction that fulfils the branch delay
5001 slot instruction length requirement (if any) of the previous
5002 instruction. While doing this we record the first instruction
5003 seen that matches all the other conditions and use it anyway
5004 if the requirement cannot be met; we will issue an appropriate
5005 warning later on. */
5006 if (strcmp (fmt, amo->args) == 0
5007 && amo->pinfo != INSN_MACRO
5008 && is_opcode_valid (amo)
5009 && is_size_valid (amo))
5011 if (is_delay_slot_valid (amo))
5021 gas_assert (amo->name);
5023 while (strcmp (name, amo->name) == 0);
5026 create_insn (&insn, mo);
5044 INSERT_OPERAND (mips_opts.micromips,
5045 EXTLSB, insn, va_arg (args, int));
5050 /* Note that in the macro case, these arguments are already
5051 in MSB form. (When handling the instruction in the
5052 non-macro case, these arguments are sizes from which
5053 MSB values must be calculated.) */
5054 INSERT_OPERAND (mips_opts.micromips,
5055 INSMSB, insn, va_arg (args, int));
5059 gas_assert (!mips_opts.micromips);
5060 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5066 /* Note that in the macro case, these arguments are already
5067 in MSBD form. (When handling the instruction in the
5068 non-macro case, these arguments are sizes from which
5069 MSBD values must be calculated.) */
5070 INSERT_OPERAND (mips_opts.micromips,
5071 EXTMSBD, insn, va_arg (args, int));
5075 gas_assert (!mips_opts.micromips);
5076 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5085 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5089 gas_assert (mips_opts.micromips);
5093 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5097 gas_assert (!mips_opts.micromips);
5098 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5102 gas_assert (!mips_opts.micromips);
5104 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5108 if (mips_opts.micromips)
5109 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5111 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5115 gas_assert (!mips_opts.micromips);
5117 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5121 gas_assert (!mips_opts.micromips);
5123 int tmp = va_arg (args, int);
5125 INSERT_OPERAND (0, RT, insn, tmp);
5126 INSERT_OPERAND (0, RD, insn, tmp);
5132 gas_assert (!mips_opts.micromips);
5133 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5140 INSERT_OPERAND (mips_opts.micromips,
5141 SHAMT, insn, va_arg (args, int));
5145 gas_assert (!mips_opts.micromips);
5146 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5150 gas_assert (!mips_opts.micromips);
5151 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5155 gas_assert (!mips_opts.micromips);
5156 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5160 gas_assert (!mips_opts.micromips);
5161 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5168 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5173 macro_read_relocs (&args, r);
5174 gas_assert (*r == BFD_RELOC_GPREL16
5175 || *r == BFD_RELOC_MIPS_HIGHER
5176 || *r == BFD_RELOC_HI16_S
5177 || *r == BFD_RELOC_LO16
5178 || *r == BFD_RELOC_MIPS_GOT_OFST);
5182 macro_read_relocs (&args, r);
5186 macro_read_relocs (&args, r);
5187 gas_assert (ep != NULL
5188 && (ep->X_op == O_constant
5189 || (ep->X_op == O_symbol
5190 && (*r == BFD_RELOC_MIPS_HIGHEST
5191 || *r == BFD_RELOC_HI16_S
5192 || *r == BFD_RELOC_HI16
5193 || *r == BFD_RELOC_GPREL16
5194 || *r == BFD_RELOC_MIPS_GOT_HI16
5195 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5199 gas_assert (ep != NULL);
5202 * This allows macro() to pass an immediate expression for
5203 * creating short branches without creating a symbol.
5205 * We don't allow branch relaxation for these branches, as
5206 * they should only appear in ".set nomacro" anyway.
5208 if (ep->X_op == O_constant)
5210 /* For microMIPS we always use relocations for branches.
5211 So we should not resolve immediate values. */
5212 gas_assert (!mips_opts.micromips);
5214 if ((ep->X_add_number & 3) != 0)
5215 as_bad (_("branch to misaligned address (0x%lx)"),
5216 (unsigned long) ep->X_add_number);
5217 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5218 as_bad (_("branch address range overflow (0x%lx)"),
5219 (unsigned long) ep->X_add_number);
5220 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5224 *r = BFD_RELOC_16_PCREL_S2;
5228 gas_assert (ep != NULL);
5229 *r = BFD_RELOC_MIPS_JMP;
5233 gas_assert (!mips_opts.micromips);
5234 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5238 INSERT_OPERAND (mips_opts.micromips,
5239 CACHE, insn, va_arg (args, unsigned long));
5243 gas_assert (mips_opts.micromips);
5244 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5248 gas_assert (mips_opts.micromips);
5249 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5253 INSERT_OPERAND (mips_opts.micromips,
5254 3BITPOS, insn, va_arg (args, unsigned int));
5258 INSERT_OPERAND (mips_opts.micromips,
5259 OFFSET12, insn, va_arg (args, unsigned long));
5263 gas_assert (mips_opts.micromips);
5264 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5267 case 'm': /* Opcode extension character. */
5268 gas_assert (mips_opts.micromips);
5272 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5276 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5280 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5294 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5296 append_insn (&insn, ep, r, TRUE);
5300 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5303 struct mips_opcode *mo;
5304 struct mips_cl_insn insn;
5305 bfd_reloc_code_real_type r[3]
5306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5308 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5310 gas_assert (strcmp (name, mo->name) == 0);
5312 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5315 gas_assert (mo->name);
5316 gas_assert (strcmp (name, mo->name) == 0);
5319 create_insn (&insn, mo);
5337 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5342 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5346 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5350 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5360 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5367 regno = va_arg (*args, int);
5368 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5369 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5392 gas_assert (ep != NULL);
5394 if (ep->X_op != O_constant)
5395 *r = (int) BFD_RELOC_UNUSED + c;
5396 else if (calculate_reloc (*r, ep->X_add_number, &value))
5398 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5400 *r = BFD_RELOC_UNUSED;
5406 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5413 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5415 append_insn (&insn, ep, r, TRUE);
5419 * Sign-extend 32-bit mode constants that have bit 31 set and all
5420 * higher bits unset.
5423 normalize_constant_expr (expressionS *ex)
5425 if (ex->X_op == O_constant
5426 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5427 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5432 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5433 * all higher bits unset.
5436 normalize_address_expr (expressionS *ex)
5438 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5439 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5440 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5441 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5446 * Generate a "jalr" instruction with a relocation hint to the called
5447 * function. This occurs in NewABI PIC code.
5450 macro_build_jalr (expressionS *ep, int cprestore)
5452 static const bfd_reloc_code_real_type jalr_relocs[2]
5453 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5454 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5458 if (MIPS_JALR_HINT_P (ep))
5463 if (mips_opts.micromips)
5465 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5466 if (MIPS_JALR_HINT_P (ep)
5467 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5468 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5470 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5473 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5474 if (MIPS_JALR_HINT_P (ep))
5475 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5479 * Generate a "lui" instruction.
5482 macro_build_lui (expressionS *ep, int regnum)
5484 gas_assert (! mips_opts.mips16);
5486 if (ep->X_op != O_constant)
5488 gas_assert (ep->X_op == O_symbol);
5489 /* _gp_disp is a special case, used from s_cpload.
5490 __gnu_local_gp is used if mips_no_shared. */
5491 gas_assert (mips_pic == NO_PIC
5493 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5494 || (! mips_in_shared
5495 && strcmp (S_GET_NAME (ep->X_add_symbol),
5496 "__gnu_local_gp") == 0));
5499 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5502 /* Generate a sequence of instructions to do a load or store from a constant
5503 offset off of a base register (breg) into/from a target register (treg),
5504 using AT if necessary. */
5506 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5507 int treg, int breg, int dbl)
5509 gas_assert (ep->X_op == O_constant);
5511 /* Sign-extending 32-bit constants makes their handling easier. */
5513 normalize_constant_expr (ep);
5515 /* Right now, this routine can only handle signed 32-bit constants. */
5516 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5517 as_warn (_("operand overflow"));
5519 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5521 /* Signed 16-bit offset will fit in the op. Easy! */
5522 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5526 /* 32-bit offset, need multiple instructions and AT, like:
5527 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5528 addu $tempreg,$tempreg,$breg
5529 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5530 to handle the complete offset. */
5531 macro_build_lui (ep, AT);
5532 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5533 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5536 as_bad (_("Macro used $at after \".set noat\""));
5541 * Generates code to set the $at register to true (one)
5542 * if reg is less than the immediate expression.
5545 set_at (int reg, int unsignedp)
5547 if (imm_expr.X_op == O_constant
5548 && imm_expr.X_add_number >= -0x8000
5549 && imm_expr.X_add_number < 0x8000)
5550 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5551 AT, reg, BFD_RELOC_LO16);
5554 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5555 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5559 /* Warn if an expression is not a constant. */
5562 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5564 if (ex->X_op == O_big)
5565 as_bad (_("unsupported large constant"));
5566 else if (ex->X_op != O_constant)
5567 as_bad (_("Instruction %s requires absolute expression"),
5570 if (HAVE_32BIT_GPRS)
5571 normalize_constant_expr (ex);
5574 /* Count the leading zeroes by performing a binary chop. This is a
5575 bulky bit of source, but performance is a LOT better for the
5576 majority of values than a simple loop to count the bits:
5577 for (lcnt = 0; (lcnt < 32); lcnt++)
5578 if ((v) & (1 << (31 - lcnt)))
5580 However it is not code size friendly, and the gain will drop a bit
5581 on certain cached systems.
5583 #define COUNT_TOP_ZEROES(v) \
5584 (((v) & ~0xffff) == 0 \
5585 ? ((v) & ~0xff) == 0 \
5586 ? ((v) & ~0xf) == 0 \
5587 ? ((v) & ~0x3) == 0 \
5588 ? ((v) & ~0x1) == 0 \
5593 : ((v) & ~0x7) == 0 \
5596 : ((v) & ~0x3f) == 0 \
5597 ? ((v) & ~0x1f) == 0 \
5600 : ((v) & ~0x7f) == 0 \
5603 : ((v) & ~0xfff) == 0 \
5604 ? ((v) & ~0x3ff) == 0 \
5605 ? ((v) & ~0x1ff) == 0 \
5608 : ((v) & ~0x7ff) == 0 \
5611 : ((v) & ~0x3fff) == 0 \
5612 ? ((v) & ~0x1fff) == 0 \
5615 : ((v) & ~0x7fff) == 0 \
5618 : ((v) & ~0xffffff) == 0 \
5619 ? ((v) & ~0xfffff) == 0 \
5620 ? ((v) & ~0x3ffff) == 0 \
5621 ? ((v) & ~0x1ffff) == 0 \
5624 : ((v) & ~0x7ffff) == 0 \
5627 : ((v) & ~0x3fffff) == 0 \
5628 ? ((v) & ~0x1fffff) == 0 \
5631 : ((v) & ~0x7fffff) == 0 \
5634 : ((v) & ~0xfffffff) == 0 \
5635 ? ((v) & ~0x3ffffff) == 0 \
5636 ? ((v) & ~0x1ffffff) == 0 \
5639 : ((v) & ~0x7ffffff) == 0 \
5642 : ((v) & ~0x3fffffff) == 0 \
5643 ? ((v) & ~0x1fffffff) == 0 \
5646 : ((v) & ~0x7fffffff) == 0 \
5651 * This routine generates the least number of instructions necessary to load
5652 * an absolute expression value into a register.
5655 load_register (int reg, expressionS *ep, int dbl)
5658 expressionS hi32, lo32;
5660 if (ep->X_op != O_big)
5662 gas_assert (ep->X_op == O_constant);
5664 /* Sign-extending 32-bit constants makes their handling easier. */
5666 normalize_constant_expr (ep);
5668 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5670 /* We can handle 16 bit signed values with an addiu to
5671 $zero. No need to ever use daddiu here, since $zero and
5672 the result are always correct in 32 bit mode. */
5673 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5676 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5678 /* We can handle 16 bit unsigned values with an ori to
5680 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5683 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5685 /* 32 bit values require an lui. */
5686 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5687 if ((ep->X_add_number & 0xffff) != 0)
5688 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5693 /* The value is larger than 32 bits. */
5695 if (!dbl || HAVE_32BIT_GPRS)
5699 sprintf_vma (value, ep->X_add_number);
5700 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5701 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5705 if (ep->X_op != O_big)
5708 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5709 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5710 hi32.X_add_number &= 0xffffffff;
5712 lo32.X_add_number &= 0xffffffff;
5716 gas_assert (ep->X_add_number > 2);
5717 if (ep->X_add_number == 3)
5718 generic_bignum[3] = 0;
5719 else if (ep->X_add_number > 4)
5720 as_bad (_("Number larger than 64 bits"));
5721 lo32.X_op = O_constant;
5722 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5723 hi32.X_op = O_constant;
5724 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5727 if (hi32.X_add_number == 0)
5732 unsigned long hi, lo;
5734 if (hi32.X_add_number == (offsetT) 0xffffffff)
5736 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5738 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5741 if (lo32.X_add_number & 0x80000000)
5743 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5744 if (lo32.X_add_number & 0xffff)
5745 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5750 /* Check for 16bit shifted constant. We know that hi32 is
5751 non-zero, so start the mask on the first bit of the hi32
5756 unsigned long himask, lomask;
5760 himask = 0xffff >> (32 - shift);
5761 lomask = (0xffff << shift) & 0xffffffff;
5765 himask = 0xffff << (shift - 32);
5768 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5769 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5773 tmp.X_op = O_constant;
5775 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5776 | (lo32.X_add_number >> shift));
5778 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5779 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5780 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5781 reg, reg, (shift >= 32) ? shift - 32 : shift);
5786 while (shift <= (64 - 16));
5788 /* Find the bit number of the lowest one bit, and store the
5789 shifted value in hi/lo. */
5790 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5791 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5795 while ((lo & 1) == 0)
5800 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5806 while ((hi & 1) == 0)
5815 /* Optimize if the shifted value is a (power of 2) - 1. */
5816 if ((hi == 0 && ((lo + 1) & lo) == 0)
5817 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5819 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5824 /* This instruction will set the register to be all
5826 tmp.X_op = O_constant;
5827 tmp.X_add_number = (offsetT) -1;
5828 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5832 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5833 reg, reg, (bit >= 32) ? bit - 32 : bit);
5835 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5836 reg, reg, (shift >= 32) ? shift - 32 : shift);
5841 /* Sign extend hi32 before calling load_register, because we can
5842 generally get better code when we load a sign extended value. */
5843 if ((hi32.X_add_number & 0x80000000) != 0)
5844 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5845 load_register (reg, &hi32, 0);
5848 if ((lo32.X_add_number & 0xffff0000) == 0)
5852 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5860 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5862 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5863 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5869 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5873 mid16.X_add_number >>= 16;
5874 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5875 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5878 if ((lo32.X_add_number & 0xffff) != 0)
5879 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5883 load_delay_nop (void)
5885 if (!gpr_interlocks)
5886 macro_build (NULL, "nop", "");
5889 /* Load an address into a register. */
5892 load_address (int reg, expressionS *ep, int *used_at)
5894 if (ep->X_op != O_constant
5895 && ep->X_op != O_symbol)
5897 as_bad (_("expression too complex"));
5898 ep->X_op = O_constant;
5901 if (ep->X_op == O_constant)
5903 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5907 if (mips_pic == NO_PIC)
5909 /* If this is a reference to a GP relative symbol, we want
5910 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5912 lui $reg,<sym> (BFD_RELOC_HI16_S)
5913 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5914 If we have an addend, we always use the latter form.
5916 With 64bit address space and a usable $at we want
5917 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5918 lui $at,<sym> (BFD_RELOC_HI16_S)
5919 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5920 daddiu $at,<sym> (BFD_RELOC_LO16)
5924 If $at is already in use, we use a path which is suboptimal
5925 on superscalar processors.
5926 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5927 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5929 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5931 daddiu $reg,<sym> (BFD_RELOC_LO16)
5933 For GP relative symbols in 64bit address space we can use
5934 the same sequence as in 32bit address space. */
5935 if (HAVE_64BIT_SYMBOLS)
5937 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5938 && !nopic_need_relax (ep->X_add_symbol, 1))
5940 relax_start (ep->X_add_symbol);
5941 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5942 mips_gp_register, BFD_RELOC_GPREL16);
5946 if (*used_at == 0 && mips_opts.at)
5948 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5949 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5950 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5951 BFD_RELOC_MIPS_HIGHER);
5952 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5953 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5954 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5959 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5960 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5961 BFD_RELOC_MIPS_HIGHER);
5962 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5963 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5964 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5965 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5968 if (mips_relax.sequence)
5973 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5974 && !nopic_need_relax (ep->X_add_symbol, 1))
5976 relax_start (ep->X_add_symbol);
5977 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5978 mips_gp_register, BFD_RELOC_GPREL16);
5981 macro_build_lui (ep, reg);
5982 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5983 reg, reg, BFD_RELOC_LO16);
5984 if (mips_relax.sequence)
5988 else if (!mips_big_got)
5992 /* If this is a reference to an external symbol, we want
5993 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5995 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5997 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5998 If there is a constant, it must be added in after.
6000 If we have NewABI, we want
6001 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6002 unless we're referencing a global symbol with a non-zero
6003 offset, in which case cst must be added separately. */
6006 if (ep->X_add_number)
6008 ex.X_add_number = ep->X_add_number;
6009 ep->X_add_number = 0;
6010 relax_start (ep->X_add_symbol);
6011 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6012 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6013 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6014 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6015 ex.X_op = O_constant;
6016 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6017 reg, reg, BFD_RELOC_LO16);
6018 ep->X_add_number = ex.X_add_number;
6021 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6022 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6023 if (mips_relax.sequence)
6028 ex.X_add_number = ep->X_add_number;
6029 ep->X_add_number = 0;
6030 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6031 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6033 relax_start (ep->X_add_symbol);
6035 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6039 if (ex.X_add_number != 0)
6041 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6042 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6043 ex.X_op = O_constant;
6044 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6045 reg, reg, BFD_RELOC_LO16);
6049 else if (mips_big_got)
6053 /* This is the large GOT case. If this is a reference to an
6054 external symbol, we want
6055 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6057 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6059 Otherwise, for a reference to a local symbol in old ABI, we want
6060 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6062 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6063 If there is a constant, it must be added in after.
6065 In the NewABI, for local symbols, with or without offsets, we want:
6066 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6067 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6071 ex.X_add_number = ep->X_add_number;
6072 ep->X_add_number = 0;
6073 relax_start (ep->X_add_symbol);
6074 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6076 reg, reg, mips_gp_register);
6077 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6078 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6079 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6080 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6081 else if (ex.X_add_number)
6083 ex.X_op = O_constant;
6084 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6088 ep->X_add_number = ex.X_add_number;
6090 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6091 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6092 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6093 BFD_RELOC_MIPS_GOT_OFST);
6098 ex.X_add_number = ep->X_add_number;
6099 ep->X_add_number = 0;
6100 relax_start (ep->X_add_symbol);
6101 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6102 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6103 reg, reg, mips_gp_register);
6104 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6105 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6107 if (reg_needs_delay (mips_gp_register))
6109 /* We need a nop before loading from $gp. This special
6110 check is required because the lui which starts the main
6111 instruction stream does not refer to $gp, and so will not
6112 insert the nop which may be required. */
6113 macro_build (NULL, "nop", "");
6115 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6116 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6118 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6122 if (ex.X_add_number != 0)
6124 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6125 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6126 ex.X_op = O_constant;
6127 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6135 if (!mips_opts.at && *used_at == 1)
6136 as_bad (_("Macro used $at after \".set noat\""));
6139 /* Move the contents of register SOURCE into register DEST. */
6142 move_register (int dest, int source)
6144 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6145 instruction specifically requires a 32-bit one. */
6146 if (mips_opts.micromips
6147 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6148 macro_build (NULL, "move", "mp,mj", dest, source);
6150 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6154 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6155 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6156 The two alternatives are:
6158 Global symbol Local sybmol
6159 ------------- ------------
6160 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6162 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6164 load_got_offset emits the first instruction and add_got_offset
6165 emits the second for a 16-bit offset or add_got_offset_hilo emits
6166 a sequence to add a 32-bit offset using a scratch register. */
6169 load_got_offset (int dest, expressionS *local)
6174 global.X_add_number = 0;
6176 relax_start (local->X_add_symbol);
6177 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6178 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6180 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6181 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6186 add_got_offset (int dest, expressionS *local)
6190 global.X_op = O_constant;
6191 global.X_op_symbol = NULL;
6192 global.X_add_symbol = NULL;
6193 global.X_add_number = local->X_add_number;
6195 relax_start (local->X_add_symbol);
6196 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6197 dest, dest, BFD_RELOC_LO16);
6199 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6204 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6207 int hold_mips_optimize;
6209 global.X_op = O_constant;
6210 global.X_op_symbol = NULL;
6211 global.X_add_symbol = NULL;
6212 global.X_add_number = local->X_add_number;
6214 relax_start (local->X_add_symbol);
6215 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6217 /* Set mips_optimize around the lui instruction to avoid
6218 inserting an unnecessary nop after the lw. */
6219 hold_mips_optimize = mips_optimize;
6221 macro_build_lui (&global, tmp);
6222 mips_optimize = hold_mips_optimize;
6223 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6229 /* Emit a sequence of instructions to emulate a branch likely operation.
6230 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6231 is its complementing branch with the original condition negated.
6232 CALL is set if the original branch specified the link operation.
6233 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6235 Code like this is produced in the noreorder mode:
6240 delay slot (executed only if branch taken)
6248 delay slot (executed only if branch taken)
6251 In the reorder mode the delay slot would be filled with a nop anyway,
6252 so code produced is simply:
6257 This function is used when producing code for the microMIPS ASE that
6258 does not implement branch likely instructions in hardware. */
6261 macro_build_branch_likely (const char *br, const char *brneg,
6262 int call, expressionS *ep, const char *fmt,
6263 unsigned int sreg, unsigned int treg)
6265 int noreorder = mips_opts.noreorder;
6268 gas_assert (mips_opts.micromips);
6272 micromips_label_expr (&expr1);
6273 macro_build (&expr1, brneg, fmt, sreg, treg);
6274 macro_build (NULL, "nop", "");
6275 macro_build (ep, call ? "bal" : "b", "p");
6277 /* Set to true so that append_insn adds a label. */
6278 emit_branch_likely_macro = TRUE;
6282 macro_build (ep, br, fmt, sreg, treg);
6283 macro_build (NULL, "nop", "");
6288 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6289 the condition code tested. EP specifies the branch target. */
6292 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6319 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6322 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6323 the register tested. EP specifies the branch target. */
6326 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6328 const char *brneg = NULL;
6338 br = mips_opts.micromips ? "bgez" : "bgezl";
6342 gas_assert (mips_opts.micromips);
6351 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6358 br = mips_opts.micromips ? "blez" : "blezl";
6365 br = mips_opts.micromips ? "bltz" : "bltzl";
6369 gas_assert (mips_opts.micromips);
6377 if (mips_opts.micromips && brneg)
6378 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6380 macro_build (ep, br, "s,p", sreg);
6383 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6384 TREG as the registers tested. EP specifies the branch target. */
6387 macro_build_branch_rsrt (int type, expressionS *ep,
6388 unsigned int sreg, unsigned int treg)
6390 const char *brneg = NULL;
6402 br = mips_opts.micromips ? "beq" : "beql";
6411 br = mips_opts.micromips ? "bne" : "bnel";
6417 if (mips_opts.micromips && brneg)
6418 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6420 macro_build (ep, br, "s,t,p", sreg, treg);
6425 * This routine implements the seemingly endless macro or synthesized
6426 * instructions and addressing modes in the mips assembly language. Many
6427 * of these macros are simple and are similar to each other. These could
6428 * probably be handled by some kind of table or grammar approach instead of
6429 * this verbose method. Others are not simple macros but are more like
6430 * optimizing code generation.
6431 * One interesting optimization is when several store macros appear
6432 * consecutively that would load AT with the upper half of the same address.
6433 * The ensuing load upper instructions are ommited. This implies some kind
6434 * of global optimization. We currently only optimize within a single macro.
6435 * For many of the load and store macros if the address is specified as a
6436 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6437 * first load register 'at' with zero and use it as the base register. The
6438 * mips assembler simply uses register $zero. Just one tiny optimization
6442 macro (struct mips_cl_insn *ip)
6444 unsigned int treg, sreg, dreg, breg;
6445 unsigned int tempreg;
6448 expressionS label_expr;
6467 bfd_reloc_code_real_type r;
6468 int hold_mips_optimize;
6470 gas_assert (! mips_opts.mips16);
6472 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6473 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6474 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6475 mask = ip->insn_mo->mask;
6477 label_expr.X_op = O_constant;
6478 label_expr.X_op_symbol = NULL;
6479 label_expr.X_add_symbol = NULL;
6480 label_expr.X_add_number = 0;
6482 expr1.X_op = O_constant;
6483 expr1.X_op_symbol = NULL;
6484 expr1.X_add_symbol = NULL;
6485 expr1.X_add_number = 1;
6500 if (mips_opts.micromips)
6501 micromips_label_expr (&label_expr);
6503 label_expr.X_add_number = 8;
6504 macro_build (&label_expr, "bgez", "s,p", sreg);
6506 macro_build (NULL, "nop", "");
6508 move_register (dreg, sreg);
6509 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6510 if (mips_opts.micromips)
6511 micromips_add_label ();
6528 if (!mips_opts.micromips)
6530 if (imm_expr.X_op == O_constant
6531 && imm_expr.X_add_number >= -0x200
6532 && imm_expr.X_add_number < 0x200)
6534 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6543 if (imm_expr.X_op == O_constant
6544 && imm_expr.X_add_number >= -0x8000
6545 && imm_expr.X_add_number < 0x8000)
6547 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6552 load_register (AT, &imm_expr, dbl);
6553 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6572 if (imm_expr.X_op == O_constant
6573 && imm_expr.X_add_number >= 0
6574 && imm_expr.X_add_number < 0x10000)
6576 if (mask != M_NOR_I)
6577 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6580 macro_build (&imm_expr, "ori", "t,r,i",
6581 treg, sreg, BFD_RELOC_LO16);
6582 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6588 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6589 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6593 switch (imm_expr.X_add_number)
6596 macro_build (NULL, "nop", "");
6599 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6603 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6604 (int) imm_expr.X_add_number);
6607 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6608 (unsigned long) imm_expr.X_add_number);
6617 gas_assert (mips_opts.micromips);
6618 macro_build_branch_ccl (mask, &offset_expr,
6619 EXTRACT_OPERAND (1, BCC, *ip));
6626 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6632 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6637 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6644 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6646 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6650 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6651 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6652 &offset_expr, AT, ZERO);
6662 macro_build_branch_rs (mask, &offset_expr, sreg);
6668 /* Check for > max integer. */
6669 maxnum = 0x7fffffff;
6670 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6677 if (imm_expr.X_op == O_constant
6678 && imm_expr.X_add_number >= maxnum
6679 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6682 /* Result is always false. */
6684 macro_build (NULL, "nop", "");
6686 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6689 if (imm_expr.X_op != O_constant)
6690 as_bad (_("Unsupported large constant"));
6691 ++imm_expr.X_add_number;
6695 if (mask == M_BGEL_I)
6697 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6699 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6700 &offset_expr, sreg);
6703 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6705 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6706 &offset_expr, sreg);
6709 maxnum = 0x7fffffff;
6710 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6717 maxnum = - maxnum - 1;
6718 if (imm_expr.X_op == O_constant
6719 && imm_expr.X_add_number <= maxnum
6720 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6723 /* result is always true */
6724 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6725 macro_build (&offset_expr, "b", "p");
6730 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6731 &offset_expr, AT, ZERO);
6740 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6741 &offset_expr, ZERO, treg);
6745 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6746 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6747 &offset_expr, AT, ZERO);
6756 && imm_expr.X_op == O_constant
6757 && imm_expr.X_add_number == -1))
6759 if (imm_expr.X_op != O_constant)
6760 as_bad (_("Unsupported large constant"));
6761 ++imm_expr.X_add_number;
6765 if (mask == M_BGEUL_I)
6767 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6769 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6770 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6771 &offset_expr, sreg, ZERO);
6776 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6777 &offset_expr, AT, ZERO);
6785 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6787 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6791 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6792 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6793 &offset_expr, AT, ZERO);
6801 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6802 &offset_expr, sreg, ZERO);
6808 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6809 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6810 &offset_expr, AT, ZERO);
6818 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6820 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6824 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6825 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6826 &offset_expr, AT, ZERO);
6833 maxnum = 0x7fffffff;
6834 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6841 if (imm_expr.X_op == O_constant
6842 && imm_expr.X_add_number >= maxnum
6843 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6845 if (imm_expr.X_op != O_constant)
6846 as_bad (_("Unsupported large constant"));
6847 ++imm_expr.X_add_number;
6851 if (mask == M_BLTL_I)
6853 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6854 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6855 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6856 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6861 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6862 &offset_expr, AT, ZERO);
6870 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6871 &offset_expr, sreg, ZERO);
6877 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6878 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6879 &offset_expr, AT, ZERO);
6888 && imm_expr.X_op == O_constant
6889 && imm_expr.X_add_number == -1))
6891 if (imm_expr.X_op != O_constant)
6892 as_bad (_("Unsupported large constant"));
6893 ++imm_expr.X_add_number;
6897 if (mask == M_BLTUL_I)
6899 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6901 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6902 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6903 &offset_expr, sreg, ZERO);
6908 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6909 &offset_expr, AT, ZERO);
6917 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6919 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6923 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6924 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6925 &offset_expr, AT, ZERO);
6935 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6936 &offset_expr, ZERO, treg);
6940 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6941 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6942 &offset_expr, AT, ZERO);
6948 /* Use unsigned arithmetic. */
6952 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6954 as_bad (_("Unsupported large constant"));
6959 pos = imm_expr.X_add_number;
6960 size = imm2_expr.X_add_number;
6965 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6968 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6970 as_bad (_("Improper extract size (%lu, position %lu)"),
6971 (unsigned long) size, (unsigned long) pos);
6975 if (size <= 32 && pos < 32)
6980 else if (size <= 32)
6990 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6997 /* Use unsigned arithmetic. */
7001 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7003 as_bad (_("Unsupported large constant"));
7008 pos = imm_expr.X_add_number;
7009 size = imm2_expr.X_add_number;
7014 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7017 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7019 as_bad (_("Improper insert size (%lu, position %lu)"),
7020 (unsigned long) size, (unsigned long) pos);
7024 if (pos < 32 && (pos + size - 1) < 32)
7039 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7040 (int) (pos + size - 1));
7056 as_warn (_("Divide by zero."));
7058 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7060 macro_build (NULL, "break", BRK_FMT, 7);
7067 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7068 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7072 if (mips_opts.micromips)
7073 micromips_label_expr (&label_expr);
7075 label_expr.X_add_number = 8;
7076 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7077 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7078 macro_build (NULL, "break", BRK_FMT, 7);
7079 if (mips_opts.micromips)
7080 micromips_add_label ();
7082 expr1.X_add_number = -1;
7084 load_register (AT, &expr1, dbl);
7085 if (mips_opts.micromips)
7086 micromips_label_expr (&label_expr);
7088 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7089 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7092 expr1.X_add_number = 1;
7093 load_register (AT, &expr1, dbl);
7094 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7098 expr1.X_add_number = 0x80000000;
7099 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7103 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7104 /* We want to close the noreorder block as soon as possible, so
7105 that later insns are available for delay slot filling. */
7110 if (mips_opts.micromips)
7111 micromips_label_expr (&label_expr);
7113 label_expr.X_add_number = 8;
7114 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7115 macro_build (NULL, "nop", "");
7117 /* We want to close the noreorder block as soon as possible, so
7118 that later insns are available for delay slot filling. */
7121 macro_build (NULL, "break", BRK_FMT, 6);
7123 if (mips_opts.micromips)
7124 micromips_add_label ();
7125 macro_build (NULL, s, MFHL_FMT, dreg);
7164 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7166 as_warn (_("Divide by zero."));
7168 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7170 macro_build (NULL, "break", BRK_FMT, 7);
7173 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7175 if (strcmp (s2, "mflo") == 0)
7176 move_register (dreg, sreg);
7178 move_register (dreg, ZERO);
7181 if (imm_expr.X_op == O_constant
7182 && imm_expr.X_add_number == -1
7183 && s[strlen (s) - 1] != 'u')
7185 if (strcmp (s2, "mflo") == 0)
7187 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7190 move_register (dreg, ZERO);
7195 load_register (AT, &imm_expr, dbl);
7196 macro_build (NULL, s, "z,s,t", sreg, AT);
7197 macro_build (NULL, s2, MFHL_FMT, dreg);
7219 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7220 macro_build (NULL, s, "z,s,t", sreg, treg);
7221 /* We want to close the noreorder block as soon as possible, so
7222 that later insns are available for delay slot filling. */
7227 if (mips_opts.micromips)
7228 micromips_label_expr (&label_expr);
7230 label_expr.X_add_number = 8;
7231 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7232 macro_build (NULL, s, "z,s,t", sreg, treg);
7234 /* We want to close the noreorder block as soon as possible, so
7235 that later insns are available for delay slot filling. */
7237 macro_build (NULL, "break", BRK_FMT, 7);
7238 if (mips_opts.micromips)
7239 micromips_add_label ();
7241 macro_build (NULL, s2, MFHL_FMT, dreg);
7253 /* Load the address of a symbol into a register. If breg is not
7254 zero, we then add a base register to it. */
7256 if (dbl && HAVE_32BIT_GPRS)
7257 as_warn (_("dla used to load 32-bit register"));
7259 if (!dbl && HAVE_64BIT_OBJECTS)
7260 as_warn (_("la used to load 64-bit address"));
7262 if (offset_expr.X_op == O_constant
7263 && offset_expr.X_add_number >= -0x8000
7264 && offset_expr.X_add_number < 0x8000)
7266 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7267 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7271 if (mips_opts.at && (treg == breg))
7281 if (offset_expr.X_op != O_symbol
7282 && offset_expr.X_op != O_constant)
7284 as_bad (_("Expression too complex"));
7285 offset_expr.X_op = O_constant;
7288 if (offset_expr.X_op == O_constant)
7289 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7290 else if (mips_pic == NO_PIC)
7292 /* If this is a reference to a GP relative symbol, we want
7293 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7295 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7296 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7297 If we have a constant, we need two instructions anyhow,
7298 so we may as well always use the latter form.
7300 With 64bit address space and a usable $at we want
7301 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7302 lui $at,<sym> (BFD_RELOC_HI16_S)
7303 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7304 daddiu $at,<sym> (BFD_RELOC_LO16)
7306 daddu $tempreg,$tempreg,$at
7308 If $at is already in use, we use a path which is suboptimal
7309 on superscalar processors.
7310 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7311 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7313 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7315 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7317 For GP relative symbols in 64bit address space we can use
7318 the same sequence as in 32bit address space. */
7319 if (HAVE_64BIT_SYMBOLS)
7321 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7322 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7324 relax_start (offset_expr.X_add_symbol);
7325 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7326 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7330 if (used_at == 0 && mips_opts.at)
7332 macro_build (&offset_expr, "lui", LUI_FMT,
7333 tempreg, BFD_RELOC_MIPS_HIGHEST);
7334 macro_build (&offset_expr, "lui", LUI_FMT,
7335 AT, BFD_RELOC_HI16_S);
7336 macro_build (&offset_expr, "daddiu", "t,r,j",
7337 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7338 macro_build (&offset_expr, "daddiu", "t,r,j",
7339 AT, AT, BFD_RELOC_LO16);
7340 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7341 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7346 macro_build (&offset_expr, "lui", LUI_FMT,
7347 tempreg, BFD_RELOC_MIPS_HIGHEST);
7348 macro_build (&offset_expr, "daddiu", "t,r,j",
7349 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7350 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7351 macro_build (&offset_expr, "daddiu", "t,r,j",
7352 tempreg, tempreg, BFD_RELOC_HI16_S);
7353 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7354 macro_build (&offset_expr, "daddiu", "t,r,j",
7355 tempreg, tempreg, BFD_RELOC_LO16);
7358 if (mips_relax.sequence)
7363 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7364 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7366 relax_start (offset_expr.X_add_symbol);
7367 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7368 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7371 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7372 as_bad (_("Offset too large"));
7373 macro_build_lui (&offset_expr, tempreg);
7374 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7375 tempreg, tempreg, BFD_RELOC_LO16);
7376 if (mips_relax.sequence)
7380 else if (!mips_big_got && !HAVE_NEWABI)
7382 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7384 /* If this is a reference to an external symbol, and there
7385 is no constant, we want
7386 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7387 or for lca or if tempreg is PIC_CALL_REG
7388 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7389 For a local symbol, we want
7390 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7392 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7394 If we have a small constant, and this is a reference to
7395 an external symbol, we want
7396 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7398 addiu $tempreg,$tempreg,<constant>
7399 For a local symbol, we want the same instruction
7400 sequence, but we output a BFD_RELOC_LO16 reloc on the
7403 If we have a large constant, and this is a reference to
7404 an external symbol, we want
7405 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7406 lui $at,<hiconstant>
7407 addiu $at,$at,<loconstant>
7408 addu $tempreg,$tempreg,$at
7409 For a local symbol, we want the same instruction
7410 sequence, but we output a BFD_RELOC_LO16 reloc on the
7414 if (offset_expr.X_add_number == 0)
7416 if (mips_pic == SVR4_PIC
7418 && (call || tempreg == PIC_CALL_REG))
7419 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7421 relax_start (offset_expr.X_add_symbol);
7422 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7423 lw_reloc_type, mips_gp_register);
7426 /* We're going to put in an addu instruction using
7427 tempreg, so we may as well insert the nop right
7432 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7433 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7435 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7436 tempreg, tempreg, BFD_RELOC_LO16);
7438 /* FIXME: If breg == 0, and the next instruction uses
7439 $tempreg, then if this variant case is used an extra
7440 nop will be generated. */
7442 else if (offset_expr.X_add_number >= -0x8000
7443 && offset_expr.X_add_number < 0x8000)
7445 load_got_offset (tempreg, &offset_expr);
7447 add_got_offset (tempreg, &offset_expr);
7451 expr1.X_add_number = offset_expr.X_add_number;
7452 offset_expr.X_add_number =
7453 SEXT_16BIT (offset_expr.X_add_number);
7454 load_got_offset (tempreg, &offset_expr);
7455 offset_expr.X_add_number = expr1.X_add_number;
7456 /* If we are going to add in a base register, and the
7457 target register and the base register are the same,
7458 then we are using AT as a temporary register. Since
7459 we want to load the constant into AT, we add our
7460 current AT (from the global offset table) and the
7461 register into the register now, and pretend we were
7462 not using a base register. */
7466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7471 add_got_offset_hilo (tempreg, &offset_expr, AT);
7475 else if (!mips_big_got && HAVE_NEWABI)
7477 int add_breg_early = 0;
7479 /* If this is a reference to an external, and there is no
7480 constant, or local symbol (*), with or without a
7482 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7483 or for lca or if tempreg is PIC_CALL_REG
7484 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7486 If we have a small constant, and this is a reference to
7487 an external symbol, we want
7488 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7489 addiu $tempreg,$tempreg,<constant>
7491 If we have a large constant, and this is a reference to
7492 an external symbol, we want
7493 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7494 lui $at,<hiconstant>
7495 addiu $at,$at,<loconstant>
7496 addu $tempreg,$tempreg,$at
7498 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7499 local symbols, even though it introduces an additional
7502 if (offset_expr.X_add_number)
7504 expr1.X_add_number = offset_expr.X_add_number;
7505 offset_expr.X_add_number = 0;
7507 relax_start (offset_expr.X_add_symbol);
7508 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7509 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7511 if (expr1.X_add_number >= -0x8000
7512 && expr1.X_add_number < 0x8000)
7514 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7515 tempreg, tempreg, BFD_RELOC_LO16);
7517 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7519 /* If we are going to add in a base register, and the
7520 target register and the base register are the same,
7521 then we are using AT as a temporary register. Since
7522 we want to load the constant into AT, we add our
7523 current AT (from the global offset table) and the
7524 register into the register now, and pretend we were
7525 not using a base register. */
7530 gas_assert (tempreg == AT);
7531 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7537 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7538 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7544 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7547 offset_expr.X_add_number = expr1.X_add_number;
7549 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7550 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7554 treg, tempreg, breg);
7560 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7562 relax_start (offset_expr.X_add_symbol);
7563 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7564 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7567 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7573 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7576 else if (mips_big_got && !HAVE_NEWABI)
7579 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7580 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7581 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7583 /* This is the large GOT case. If this is a reference to an
7584 external symbol, and there is no constant, we want
7585 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7586 addu $tempreg,$tempreg,$gp
7587 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7588 or for lca or if tempreg is PIC_CALL_REG
7589 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7590 addu $tempreg,$tempreg,$gp
7591 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7592 For a local symbol, we want
7593 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7595 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7597 If we have a small constant, and this is a reference to
7598 an external symbol, we want
7599 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7600 addu $tempreg,$tempreg,$gp
7601 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7603 addiu $tempreg,$tempreg,<constant>
7604 For a local symbol, we want
7605 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7607 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7609 If we have a large constant, and this is a reference to
7610 an external symbol, we want
7611 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7612 addu $tempreg,$tempreg,$gp
7613 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7614 lui $at,<hiconstant>
7615 addiu $at,$at,<loconstant>
7616 addu $tempreg,$tempreg,$at
7617 For a local symbol, we want
7618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7619 lui $at,<hiconstant>
7620 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7621 addu $tempreg,$tempreg,$at
7624 expr1.X_add_number = offset_expr.X_add_number;
7625 offset_expr.X_add_number = 0;
7626 relax_start (offset_expr.X_add_symbol);
7627 gpdelay = reg_needs_delay (mips_gp_register);
7628 if (expr1.X_add_number == 0 && breg == 0
7629 && (call || tempreg == PIC_CALL_REG))
7631 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7632 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7634 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7635 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7636 tempreg, tempreg, mips_gp_register);
7637 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7638 tempreg, lw_reloc_type, tempreg);
7639 if (expr1.X_add_number == 0)
7643 /* We're going to put in an addu instruction using
7644 tempreg, so we may as well insert the nop right
7649 else if (expr1.X_add_number >= -0x8000
7650 && expr1.X_add_number < 0x8000)
7653 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7654 tempreg, tempreg, BFD_RELOC_LO16);
7658 /* If we are going to add in a base register, and the
7659 target register and the base register are the same,
7660 then we are using AT as a temporary register. Since
7661 we want to load the constant into AT, we add our
7662 current AT (from the global offset table) and the
7663 register into the register now, and pretend we were
7664 not using a base register. */
7669 gas_assert (tempreg == AT);
7671 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7676 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7677 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7681 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7686 /* This is needed because this instruction uses $gp, but
7687 the first instruction on the main stream does not. */
7688 macro_build (NULL, "nop", "");
7691 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7692 local_reloc_type, mips_gp_register);
7693 if (expr1.X_add_number >= -0x8000
7694 && expr1.X_add_number < 0x8000)
7697 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7698 tempreg, tempreg, BFD_RELOC_LO16);
7699 /* FIXME: If add_number is 0, and there was no base
7700 register, the external symbol case ended with a load,
7701 so if the symbol turns out to not be external, and
7702 the next instruction uses tempreg, an unnecessary nop
7703 will be inserted. */
7709 /* We must add in the base register now, as in the
7710 external symbol case. */
7711 gas_assert (tempreg == AT);
7713 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7716 /* We set breg to 0 because we have arranged to add
7717 it in in both cases. */
7721 macro_build_lui (&expr1, AT);
7722 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7723 AT, AT, BFD_RELOC_LO16);
7724 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7725 tempreg, tempreg, AT);
7730 else if (mips_big_got && HAVE_NEWABI)
7732 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7733 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7734 int add_breg_early = 0;
7736 /* This is the large GOT case. If this is a reference to an
7737 external symbol, and there is no constant, we want
7738 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7739 add $tempreg,$tempreg,$gp
7740 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7741 or for lca or if tempreg is PIC_CALL_REG
7742 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7743 add $tempreg,$tempreg,$gp
7744 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7746 If we have a small constant, and this is a reference to
7747 an external symbol, we want
7748 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7749 add $tempreg,$tempreg,$gp
7750 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7751 addi $tempreg,$tempreg,<constant>
7753 If we have a large constant, and this is a reference to
7754 an external symbol, we want
7755 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7756 addu $tempreg,$tempreg,$gp
7757 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7758 lui $at,<hiconstant>
7759 addi $at,$at,<loconstant>
7760 add $tempreg,$tempreg,$at
7762 If we have NewABI, and we know it's a local symbol, we want
7763 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7764 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7765 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7767 relax_start (offset_expr.X_add_symbol);
7769 expr1.X_add_number = offset_expr.X_add_number;
7770 offset_expr.X_add_number = 0;
7772 if (expr1.X_add_number == 0 && breg == 0
7773 && (call || tempreg == PIC_CALL_REG))
7775 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7776 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7778 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7779 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7780 tempreg, tempreg, mips_gp_register);
7781 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7782 tempreg, lw_reloc_type, tempreg);
7784 if (expr1.X_add_number == 0)
7786 else if (expr1.X_add_number >= -0x8000
7787 && expr1.X_add_number < 0x8000)
7789 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7790 tempreg, tempreg, BFD_RELOC_LO16);
7792 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7794 /* If we are going to add in a base register, and the
7795 target register and the base register are the same,
7796 then we are using AT as a temporary register. Since
7797 we want to load the constant into AT, we add our
7798 current AT (from the global offset table) and the
7799 register into the register now, and pretend we were
7800 not using a base register. */
7805 gas_assert (tempreg == AT);
7806 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7812 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7813 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7818 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7821 offset_expr.X_add_number = expr1.X_add_number;
7822 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7823 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7824 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7825 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7829 treg, tempreg, breg);
7839 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7843 gas_assert (!mips_opts.micromips);
7845 unsigned long temp = (treg << 16) | (0x01);
7846 macro_build (NULL, "c2", "C", temp);
7851 gas_assert (!mips_opts.micromips);
7853 unsigned long temp = (0x02);
7854 macro_build (NULL, "c2", "C", temp);
7859 gas_assert (!mips_opts.micromips);
7861 unsigned long temp = (treg << 16) | (0x02);
7862 macro_build (NULL, "c2", "C", temp);
7867 gas_assert (!mips_opts.micromips);
7868 macro_build (NULL, "c2", "C", 3);
7872 gas_assert (!mips_opts.micromips);
7874 unsigned long temp = (treg << 16) | 0x03;
7875 macro_build (NULL, "c2", "C", temp);
7880 /* The j instruction may not be used in PIC code, since it
7881 requires an absolute address. We convert it to a b
7883 if (mips_pic == NO_PIC)
7884 macro_build (&offset_expr, "j", "a");
7886 macro_build (&offset_expr, "b", "p");
7889 /* The jal instructions must be handled as macros because when
7890 generating PIC code they expand to multi-instruction
7891 sequences. Normally they are simple instructions. */
7896 gas_assert (mips_opts.micromips);
7904 if (mips_pic == NO_PIC)
7906 s = jals ? "jalrs" : "jalr";
7907 if (mips_opts.micromips
7909 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7910 macro_build (NULL, s, "mj", sreg);
7912 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7916 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7917 && mips_cprestore_offset >= 0);
7919 if (sreg != PIC_CALL_REG)
7920 as_warn (_("MIPS PIC call to register other than $25"));
7922 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7923 ? "jalrs" : "jalr");
7924 if (mips_opts.micromips
7926 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7927 macro_build (NULL, s, "mj", sreg);
7929 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7930 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7932 if (mips_cprestore_offset < 0)
7933 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7936 if (!mips_frame_reg_valid)
7938 as_warn (_("No .frame pseudo-op used in PIC code"));
7939 /* Quiet this warning. */
7940 mips_frame_reg_valid = 1;
7942 if (!mips_cprestore_valid)
7944 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7945 /* Quiet this warning. */
7946 mips_cprestore_valid = 1;
7948 if (mips_opts.noreorder)
7949 macro_build (NULL, "nop", "");
7950 expr1.X_add_number = mips_cprestore_offset;
7951 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7954 HAVE_64BIT_ADDRESSES);
7962 gas_assert (mips_opts.micromips);
7966 if (mips_pic == NO_PIC)
7967 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7968 else if (mips_pic == SVR4_PIC)
7970 /* If this is a reference to an external symbol, and we are
7971 using a small GOT, we want
7972 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7976 lw $gp,cprestore($sp)
7977 The cprestore value is set using the .cprestore
7978 pseudo-op. If we are using a big GOT, we want
7979 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7981 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7985 lw $gp,cprestore($sp)
7986 If the symbol is not external, we want
7987 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7989 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7992 lw $gp,cprestore($sp)
7994 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7995 sequences above, minus nops, unless the symbol is local,
7996 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8002 relax_start (offset_expr.X_add_symbol);
8003 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8004 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8007 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8008 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8014 relax_start (offset_expr.X_add_symbol);
8015 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8016 BFD_RELOC_MIPS_CALL_HI16);
8017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8018 PIC_CALL_REG, mips_gp_register);
8019 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8020 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8024 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8026 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8027 PIC_CALL_REG, PIC_CALL_REG,
8028 BFD_RELOC_MIPS_GOT_OFST);
8032 macro_build_jalr (&offset_expr, 0);
8036 relax_start (offset_expr.X_add_symbol);
8039 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8040 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8049 gpdelay = reg_needs_delay (mips_gp_register);
8050 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8051 BFD_RELOC_MIPS_CALL_HI16);
8052 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8053 PIC_CALL_REG, mips_gp_register);
8054 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8055 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8060 macro_build (NULL, "nop", "");
8062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8063 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8066 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8067 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8069 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8071 if (mips_cprestore_offset < 0)
8072 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8075 if (!mips_frame_reg_valid)
8077 as_warn (_("No .frame pseudo-op used in PIC code"));
8078 /* Quiet this warning. */
8079 mips_frame_reg_valid = 1;
8081 if (!mips_cprestore_valid)
8083 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8084 /* Quiet this warning. */
8085 mips_cprestore_valid = 1;
8087 if (mips_opts.noreorder)
8088 macro_build (NULL, "nop", "");
8089 expr1.X_add_number = mips_cprestore_offset;
8090 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8093 HAVE_64BIT_ADDRESSES);
8097 else if (mips_pic == VXWORKS_PIC)
8098 as_bad (_("Non-PIC jump used in PIC library"));
8108 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8116 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8147 gas_assert (!mips_opts.micromips);
8150 /* Itbl support may require additional care here. */
8157 /* Itbl support may require additional care here. */
8165 off12 = mips_opts.micromips;
8166 /* Itbl support may require additional care here. */
8171 gas_assert (!mips_opts.micromips);
8174 /* Itbl support may require additional care here. */
8182 off12 = mips_opts.micromips;
8189 off12 = mips_opts.micromips;
8195 /* Itbl support may require additional care here. */
8203 off12 = mips_opts.micromips;
8204 /* Itbl support may require additional care here. */
8211 /* Itbl support may require additional care here. */
8218 /* Itbl support may require additional care here. */
8226 off12 = mips_opts.micromips;
8233 off12 = mips_opts.micromips;
8240 off12 = mips_opts.micromips;
8247 off12 = mips_opts.micromips;
8254 off12 = mips_opts.micromips;
8259 gas_assert (mips_opts.micromips);
8268 gas_assert (mips_opts.micromips);
8277 gas_assert (mips_opts.micromips);
8285 gas_assert (mips_opts.micromips);
8292 /* We don't want to use $0 as tempreg. */
8293 if (breg == treg + lp || treg + lp == ZERO)
8296 tempreg = treg + lp;
8316 gas_assert (!mips_opts.micromips);
8319 /* Itbl support may require additional care here. */
8326 /* Itbl support may require additional care here. */
8334 off12 = mips_opts.micromips;
8335 /* Itbl support may require additional care here. */
8340 gas_assert (!mips_opts.micromips);
8343 /* Itbl support may require additional care here. */
8351 off12 = mips_opts.micromips;
8358 off12 = mips_opts.micromips;
8365 off12 = mips_opts.micromips;
8372 off12 = mips_opts.micromips;
8378 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8379 off12 = mips_opts.micromips;
8385 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8386 off12 = mips_opts.micromips;
8393 /* Itbl support may require additional care here. */
8400 off12 = mips_opts.micromips;
8401 /* Itbl support may require additional care here. */
8408 /* Itbl support may require additional care here. */
8413 gas_assert (!mips_opts.micromips);
8416 /* Itbl support may require additional care here. */
8424 off12 = mips_opts.micromips;
8431 off12 = mips_opts.micromips;
8436 gas_assert (mips_opts.micromips);
8444 gas_assert (mips_opts.micromips);
8452 gas_assert (mips_opts.micromips);
8460 gas_assert (mips_opts.micromips);
8469 if (offset_expr.X_op != O_constant
8470 && offset_expr.X_op != O_symbol)
8472 as_bad (_("Expression too complex"));
8473 offset_expr.X_op = O_constant;
8476 if (HAVE_32BIT_ADDRESSES
8477 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8481 sprintf_vma (value, offset_expr.X_add_number);
8482 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8485 /* A constant expression in PIC code can be handled just as it
8486 is in non PIC code. */
8487 if (offset_expr.X_op == O_constant)
8491 expr1.X_add_number = offset_expr.X_add_number;
8492 normalize_address_expr (&expr1);
8493 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8495 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8496 & ~(bfd_vma) 0xffff);
8499 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8501 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8502 & ~(bfd_vma) 0xfff);
8507 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8509 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8510 tempreg, tempreg, breg);
8515 if (offset_expr.X_add_number == 0)
8518 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8519 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8520 macro_build (NULL, s, fmt, treg, tempreg);
8523 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8525 macro_build (NULL, s, fmt,
8526 treg, (unsigned long) offset_expr.X_add_number, breg);
8528 else if (off12 || off0)
8530 /* A 12-bit or 0-bit offset field is too narrow to be used
8531 for a low-part relocation, so load the whole address into
8532 the auxillary register. In the case of "A(b)" addresses,
8533 we first load absolute address "A" into the register and
8534 then add base register "b". In the case of "o(b)" addresses,
8535 we simply need to add 16-bit offset "o" to base register "b", and
8536 offset_reloc already contains the relocations associated
8540 load_address (tempreg, &offset_expr, &used_at);
8542 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8543 tempreg, tempreg, breg);
8546 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8548 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8549 expr1.X_add_number = 0;
8551 macro_build (NULL, s, fmt, treg, tempreg);
8553 macro_build (NULL, s, fmt,
8554 treg, (unsigned long) expr1.X_add_number, tempreg);
8556 else if (mips_pic == NO_PIC)
8558 /* If this is a reference to a GP relative symbol, and there
8559 is no base register, we want
8560 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8561 Otherwise, if there is no base register, we want
8562 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8563 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8564 If we have a constant, we need two instructions anyhow,
8565 so we always use the latter form.
8567 If we have a base register, and this is a reference to a
8568 GP relative symbol, we want
8569 addu $tempreg,$breg,$gp
8570 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8572 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8573 addu $tempreg,$tempreg,$breg
8574 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8575 With a constant we always use the latter case.
8577 With 64bit address space and no base register and $at usable,
8579 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8580 lui $at,<sym> (BFD_RELOC_HI16_S)
8581 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8584 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8585 If we have a base register, we want
8586 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8587 lui $at,<sym> (BFD_RELOC_HI16_S)
8588 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8592 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8594 Without $at we can't generate the optimal path for superscalar
8595 processors here since this would require two temporary registers.
8596 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8597 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8599 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8601 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8602 If we have a base register, we want
8603 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8604 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8606 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8608 daddu $tempreg,$tempreg,$breg
8609 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8611 For GP relative symbols in 64bit address space we can use
8612 the same sequence as in 32bit address space. */
8613 if (HAVE_64BIT_SYMBOLS)
8615 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8616 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8618 relax_start (offset_expr.X_add_symbol);
8621 macro_build (&offset_expr, s, fmt, treg,
8622 BFD_RELOC_GPREL16, mips_gp_register);
8626 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8627 tempreg, breg, mips_gp_register);
8628 macro_build (&offset_expr, s, fmt, treg,
8629 BFD_RELOC_GPREL16, tempreg);
8634 if (used_at == 0 && mips_opts.at)
8636 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8637 BFD_RELOC_MIPS_HIGHEST);
8638 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8640 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8641 tempreg, BFD_RELOC_MIPS_HIGHER);
8643 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8644 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8645 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8646 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8652 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8653 BFD_RELOC_MIPS_HIGHEST);
8654 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8655 tempreg, BFD_RELOC_MIPS_HIGHER);
8656 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8657 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8658 tempreg, BFD_RELOC_HI16_S);
8659 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8661 macro_build (NULL, "daddu", "d,v,t",
8662 tempreg, tempreg, breg);
8663 macro_build (&offset_expr, s, fmt, treg,
8664 BFD_RELOC_LO16, tempreg);
8667 if (mips_relax.sequence)
8674 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8675 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8677 relax_start (offset_expr.X_add_symbol);
8678 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8682 macro_build_lui (&offset_expr, tempreg);
8683 macro_build (&offset_expr, s, fmt, treg,
8684 BFD_RELOC_LO16, tempreg);
8685 if (mips_relax.sequence)
8690 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8691 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8693 relax_start (offset_expr.X_add_symbol);
8694 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8695 tempreg, breg, mips_gp_register);
8696 macro_build (&offset_expr, s, fmt, treg,
8697 BFD_RELOC_GPREL16, tempreg);
8700 macro_build_lui (&offset_expr, tempreg);
8701 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8702 tempreg, tempreg, breg);
8703 macro_build (&offset_expr, s, fmt, treg,
8704 BFD_RELOC_LO16, tempreg);
8705 if (mips_relax.sequence)
8709 else if (!mips_big_got)
8711 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8713 /* If this is a reference to an external symbol, we want
8714 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8716 <op> $treg,0($tempreg)
8718 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8720 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8721 <op> $treg,0($tempreg)
8724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8725 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8727 If there is a base register, we add it to $tempreg before
8728 the <op>. If there is a constant, we stick it in the
8729 <op> instruction. We don't handle constants larger than
8730 16 bits, because we have no way to load the upper 16 bits
8731 (actually, we could handle them for the subset of cases
8732 in which we are not using $at). */
8733 gas_assert (offset_expr.X_op == O_symbol);
8736 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8737 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8739 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8740 tempreg, tempreg, breg);
8741 macro_build (&offset_expr, s, fmt, treg,
8742 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8745 expr1.X_add_number = offset_expr.X_add_number;
8746 offset_expr.X_add_number = 0;
8747 if (expr1.X_add_number < -0x8000
8748 || expr1.X_add_number >= 0x8000)
8749 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8750 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8751 lw_reloc_type, mips_gp_register);
8753 relax_start (offset_expr.X_add_symbol);
8755 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8756 tempreg, BFD_RELOC_LO16);
8759 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8760 tempreg, tempreg, breg);
8761 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8763 else if (mips_big_got && !HAVE_NEWABI)
8767 /* If this is a reference to an external symbol, we want
8768 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8769 addu $tempreg,$tempreg,$gp
8770 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8771 <op> $treg,0($tempreg)
8773 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8775 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8776 <op> $treg,0($tempreg)
8777 If there is a base register, we add it to $tempreg before
8778 the <op>. If there is a constant, we stick it in the
8779 <op> instruction. We don't handle constants larger than
8780 16 bits, because we have no way to load the upper 16 bits
8781 (actually, we could handle them for the subset of cases
8782 in which we are not using $at). */
8783 gas_assert (offset_expr.X_op == O_symbol);
8784 expr1.X_add_number = offset_expr.X_add_number;
8785 offset_expr.X_add_number = 0;
8786 if (expr1.X_add_number < -0x8000
8787 || expr1.X_add_number >= 0x8000)
8788 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8789 gpdelay = reg_needs_delay (mips_gp_register);
8790 relax_start (offset_expr.X_add_symbol);
8791 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8792 BFD_RELOC_MIPS_GOT_HI16);
8793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8795 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8796 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8799 macro_build (NULL, "nop", "");
8800 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8801 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8803 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8804 tempreg, BFD_RELOC_LO16);
8808 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8809 tempreg, tempreg, breg);
8810 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8812 else if (mips_big_got && HAVE_NEWABI)
8814 /* If this is a reference to an external symbol, we want
8815 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8816 add $tempreg,$tempreg,$gp
8817 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8818 <op> $treg,<ofst>($tempreg)
8819 Otherwise, for local symbols, we want:
8820 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8821 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8822 gas_assert (offset_expr.X_op == O_symbol);
8823 expr1.X_add_number = offset_expr.X_add_number;
8824 offset_expr.X_add_number = 0;
8825 if (expr1.X_add_number < -0x8000
8826 || expr1.X_add_number >= 0x8000)
8827 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8828 relax_start (offset_expr.X_add_symbol);
8829 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8830 BFD_RELOC_MIPS_GOT_HI16);
8831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8833 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8834 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8836 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8837 tempreg, tempreg, breg);
8838 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8841 offset_expr.X_add_number = expr1.X_add_number;
8842 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8843 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8845 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8846 tempreg, tempreg, breg);
8847 macro_build (&offset_expr, s, fmt, treg,
8848 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8858 load_register (treg, &imm_expr, 0);
8862 load_register (treg, &imm_expr, 1);
8866 if (imm_expr.X_op == O_constant)
8869 load_register (AT, &imm_expr, 0);
8870 macro_build (NULL, "mtc1", "t,G", AT, treg);
8875 gas_assert (offset_expr.X_op == O_symbol
8876 && strcmp (segment_name (S_GET_SEGMENT
8877 (offset_expr.X_add_symbol)),
8879 && offset_expr.X_add_number == 0);
8880 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8881 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8886 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8887 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8888 order 32 bits of the value and the low order 32 bits are either
8889 zero or in OFFSET_EXPR. */
8890 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8892 if (HAVE_64BIT_GPRS)
8893 load_register (treg, &imm_expr, 1);
8898 if (target_big_endian)
8910 load_register (hreg, &imm_expr, 0);
8913 if (offset_expr.X_op == O_absent)
8914 move_register (lreg, 0);
8917 gas_assert (offset_expr.X_op == O_constant);
8918 load_register (lreg, &offset_expr, 0);
8925 /* We know that sym is in the .rdata section. First we get the
8926 upper 16 bits of the address. */
8927 if (mips_pic == NO_PIC)
8929 macro_build_lui (&offset_expr, AT);
8934 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8935 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8939 /* Now we load the register(s). */
8940 if (HAVE_64BIT_GPRS)
8943 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8948 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8951 /* FIXME: How in the world do we deal with the possible
8953 offset_expr.X_add_number += 4;
8954 macro_build (&offset_expr, "lw", "t,o(b)",
8955 treg + 1, BFD_RELOC_LO16, AT);
8961 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8962 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8963 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8964 the value and the low order 32 bits are either zero or in
8966 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8969 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8970 if (HAVE_64BIT_FPRS)
8972 gas_assert (HAVE_64BIT_GPRS);
8973 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8977 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8978 if (offset_expr.X_op == O_absent)
8979 macro_build (NULL, "mtc1", "t,G", 0, treg);
8982 gas_assert (offset_expr.X_op == O_constant);
8983 load_register (AT, &offset_expr, 0);
8984 macro_build (NULL, "mtc1", "t,G", AT, treg);
8990 gas_assert (offset_expr.X_op == O_symbol
8991 && offset_expr.X_add_number == 0);
8992 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8993 if (strcmp (s, ".lit8") == 0)
8995 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
8997 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8998 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9001 breg = mips_gp_register;
9002 r = BFD_RELOC_MIPS_LITERAL;
9007 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9009 if (mips_pic != NO_PIC)
9010 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9011 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9014 /* FIXME: This won't work for a 64 bit address. */
9015 macro_build_lui (&offset_expr, AT);
9018 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9020 macro_build (&offset_expr, "ldc1", "T,o(b)",
9021 treg, BFD_RELOC_LO16, AT);
9030 /* Even on a big endian machine $fn comes before $fn+1. We have
9031 to adjust when loading from memory. */
9034 gas_assert (!mips_opts.micromips);
9035 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9036 macro_build (&offset_expr, "lwc1", "T,o(b)",
9037 target_big_endian ? treg + 1 : treg, r, breg);
9038 /* FIXME: A possible overflow which I don't know how to deal
9040 offset_expr.X_add_number += 4;
9041 macro_build (&offset_expr, "lwc1", "T,o(b)",
9042 target_big_endian ? treg : treg + 1, r, breg);
9046 gas_assert (!mips_opts.micromips);
9047 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9048 /* Even on a big endian machine $fn comes before $fn+1. We have
9049 to adjust when storing to memory. */
9050 macro_build (&offset_expr, "swc1", "T,o(b)",
9051 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
9052 offset_expr.X_add_number += 4;
9053 macro_build (&offset_expr, "swc1", "T,o(b)",
9054 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
9058 gas_assert (!mips_opts.micromips);
9060 * The MIPS assembler seems to check for X_add_number not
9061 * being double aligned and generating:
9064 * addiu at,at,%lo(foo+1)
9067 * But, the resulting address is the same after relocation so why
9068 * generate the extra instruction?
9070 /* Itbl support may require additional care here. */
9073 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9082 gas_assert (!mips_opts.micromips);
9083 /* Itbl support may require additional care here. */
9086 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9106 if (HAVE_64BIT_GPRS)
9116 if (HAVE_64BIT_GPRS)
9124 if (offset_expr.X_op != O_symbol
9125 && offset_expr.X_op != O_constant)
9127 as_bad (_("Expression too complex"));
9128 offset_expr.X_op = O_constant;
9131 if (HAVE_32BIT_ADDRESSES
9132 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9136 sprintf_vma (value, offset_expr.X_add_number);
9137 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9140 /* Even on a big endian machine $fn comes before $fn+1. We have
9141 to adjust when loading from memory. We set coproc if we must
9142 load $fn+1 first. */
9143 /* Itbl support may require additional care here. */
9144 if (!target_big_endian)
9147 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9149 /* If this is a reference to a GP relative symbol, we want
9150 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9151 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9152 If we have a base register, we use this
9154 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9156 If this is not a GP relative symbol, we want
9157 lui $at,<sym> (BFD_RELOC_HI16_S)
9158 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9159 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9160 If there is a base register, we add it to $at after the
9161 lui instruction. If there is a constant, we always use
9163 if (offset_expr.X_op == O_symbol
9164 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9165 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9167 relax_start (offset_expr.X_add_symbol);
9170 tempreg = mips_gp_register;
9174 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9175 AT, breg, mips_gp_register);
9180 /* Itbl support may require additional care here. */
9181 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9182 BFD_RELOC_GPREL16, tempreg);
9183 offset_expr.X_add_number += 4;
9185 /* Set mips_optimize to 2 to avoid inserting an
9187 hold_mips_optimize = mips_optimize;
9189 /* Itbl support may require additional care here. */
9190 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9191 BFD_RELOC_GPREL16, tempreg);
9192 mips_optimize = hold_mips_optimize;
9196 offset_expr.X_add_number -= 4;
9199 macro_build_lui (&offset_expr, AT);
9201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9202 /* Itbl support may require additional care here. */
9203 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9204 BFD_RELOC_LO16, AT);
9205 /* FIXME: How do we handle overflow here? */
9206 offset_expr.X_add_number += 4;
9207 /* Itbl support may require additional care here. */
9208 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9209 BFD_RELOC_LO16, AT);
9210 if (mips_relax.sequence)
9213 else if (!mips_big_got)
9215 /* If this is a reference to an external symbol, we want
9216 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9221 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9223 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9224 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9225 If there is a base register we add it to $at before the
9226 lwc1 instructions. If there is a constant we include it
9227 in the lwc1 instructions. */
9229 expr1.X_add_number = offset_expr.X_add_number;
9230 if (expr1.X_add_number < -0x8000
9231 || expr1.X_add_number >= 0x8000 - 4)
9232 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9233 load_got_offset (AT, &offset_expr);
9236 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9238 /* Set mips_optimize to 2 to avoid inserting an undesired
9240 hold_mips_optimize = mips_optimize;
9243 /* Itbl support may require additional care here. */
9244 relax_start (offset_expr.X_add_symbol);
9245 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9246 BFD_RELOC_LO16, AT);
9247 expr1.X_add_number += 4;
9248 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9249 BFD_RELOC_LO16, AT);
9251 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9252 BFD_RELOC_LO16, AT);
9253 offset_expr.X_add_number += 4;
9254 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9255 BFD_RELOC_LO16, AT);
9258 mips_optimize = hold_mips_optimize;
9260 else if (mips_big_got)
9264 /* If this is a reference to an external symbol, we want
9265 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9267 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9272 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9274 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9275 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9276 If there is a base register we add it to $at before the
9277 lwc1 instructions. If there is a constant we include it
9278 in the lwc1 instructions. */
9280 expr1.X_add_number = offset_expr.X_add_number;
9281 offset_expr.X_add_number = 0;
9282 if (expr1.X_add_number < -0x8000
9283 || expr1.X_add_number >= 0x8000 - 4)
9284 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9285 gpdelay = reg_needs_delay (mips_gp_register);
9286 relax_start (offset_expr.X_add_symbol);
9287 macro_build (&offset_expr, "lui", LUI_FMT,
9288 AT, BFD_RELOC_MIPS_GOT_HI16);
9289 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9290 AT, AT, mips_gp_register);
9291 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9292 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9295 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9296 /* Itbl support may require additional care here. */
9297 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9298 BFD_RELOC_LO16, AT);
9299 expr1.X_add_number += 4;
9301 /* Set mips_optimize to 2 to avoid inserting an undesired
9303 hold_mips_optimize = mips_optimize;
9305 /* Itbl support may require additional care here. */
9306 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9307 BFD_RELOC_LO16, AT);
9308 mips_optimize = hold_mips_optimize;
9309 expr1.X_add_number -= 4;
9312 offset_expr.X_add_number = expr1.X_add_number;
9314 macro_build (NULL, "nop", "");
9315 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9316 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9320 /* Itbl support may require additional care here. */
9321 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9322 BFD_RELOC_LO16, AT);
9323 offset_expr.X_add_number += 4;
9325 /* Set mips_optimize to 2 to avoid inserting an undesired
9327 hold_mips_optimize = mips_optimize;
9329 /* Itbl support may require additional care here. */
9330 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9331 BFD_RELOC_LO16, AT);
9332 mips_optimize = hold_mips_optimize;
9341 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9344 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9346 macro_build (&offset_expr, s, "t,o(b)", treg,
9347 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9349 if (!HAVE_64BIT_GPRS)
9351 offset_expr.X_add_number += 4;
9352 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9353 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9374 /* New code added to support COPZ instructions.
9375 This code builds table entries out of the macros in mip_opcodes.
9376 R4000 uses interlocks to handle coproc delays.
9377 Other chips (like the R3000) require nops to be inserted for delays.
9379 FIXME: Currently, we require that the user handle delays.
9380 In order to fill delay slots for non-interlocked chips,
9381 we must have a way to specify delays based on the coprocessor.
9382 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9383 What are the side-effects of the cop instruction?
9384 What cache support might we have and what are its effects?
9385 Both coprocessor & memory require delays. how long???
9386 What registers are read/set/modified?
9388 If an itbl is provided to interpret cop instructions,
9389 this knowledge can be encoded in the itbl spec. */
9403 gas_assert (!mips_opts.micromips);
9404 /* For now we just do C (same as Cz). The parameter will be
9405 stored in insn_opcode by mips_ip. */
9406 macro_build (NULL, s, "C", ip->insn_opcode);
9410 move_register (dreg, sreg);
9416 if (mips_opts.arch == CPU_R5900)
9418 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9422 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9423 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9430 /* The MIPS assembler some times generates shifts and adds. I'm
9431 not trying to be that fancy. GCC should do this for us
9434 load_register (AT, &imm_expr, dbl);
9435 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9436 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9452 load_register (AT, &imm_expr, dbl);
9453 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9454 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9455 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9456 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9458 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9461 if (mips_opts.micromips)
9462 micromips_label_expr (&label_expr);
9464 label_expr.X_add_number = 8;
9465 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9466 macro_build (NULL, "nop", "");
9467 macro_build (NULL, "break", BRK_FMT, 6);
9468 if (mips_opts.micromips)
9469 micromips_add_label ();
9472 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9488 load_register (AT, &imm_expr, dbl);
9489 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9490 sreg, imm ? AT : treg);
9491 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9492 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9494 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9497 if (mips_opts.micromips)
9498 micromips_label_expr (&label_expr);
9500 label_expr.X_add_number = 8;
9501 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9502 macro_build (NULL, "nop", "");
9503 macro_build (NULL, "break", BRK_FMT, 6);
9504 if (mips_opts.micromips)
9505 micromips_add_label ();
9511 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9522 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9523 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9527 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9528 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9529 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9530 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9534 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9545 macro_build (NULL, "negu", "d,w", tempreg, treg);
9546 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9550 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9551 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9552 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9553 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9562 if (imm_expr.X_op != O_constant)
9563 as_bad (_("Improper rotate count"));
9564 rot = imm_expr.X_add_number & 0x3f;
9565 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9567 rot = (64 - rot) & 0x3f;
9569 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9571 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9576 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9579 l = (rot < 0x20) ? "dsll" : "dsll32";
9580 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9583 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9584 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9585 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9593 if (imm_expr.X_op != O_constant)
9594 as_bad (_("Improper rotate count"));
9595 rot = imm_expr.X_add_number & 0x1f;
9596 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9598 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9603 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9607 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9608 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9609 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9614 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9616 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9620 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9621 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9622 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9623 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9627 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9629 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9633 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9634 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9635 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9636 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9645 if (imm_expr.X_op != O_constant)
9646 as_bad (_("Improper rotate count"));
9647 rot = imm_expr.X_add_number & 0x3f;
9648 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9651 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9653 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9658 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9661 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9662 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9665 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9666 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9667 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9675 if (imm_expr.X_op != O_constant)
9676 as_bad (_("Improper rotate count"));
9677 rot = imm_expr.X_add_number & 0x1f;
9678 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9680 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9685 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9689 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9690 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9691 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9697 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9699 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9702 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9703 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9708 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9710 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9715 as_warn (_("Instruction %s: result is always false"),
9717 move_register (dreg, 0);
9720 if (CPU_HAS_SEQ (mips_opts.arch)
9721 && -512 <= imm_expr.X_add_number
9722 && imm_expr.X_add_number < 512)
9724 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9725 (int) imm_expr.X_add_number);
9728 if (imm_expr.X_op == O_constant
9729 && imm_expr.X_add_number >= 0
9730 && imm_expr.X_add_number < 0x10000)
9732 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9734 else if (imm_expr.X_op == O_constant
9735 && imm_expr.X_add_number > -0x8000
9736 && imm_expr.X_add_number < 0)
9738 imm_expr.X_add_number = -imm_expr.X_add_number;
9739 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9740 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9742 else if (CPU_HAS_SEQ (mips_opts.arch))
9745 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9746 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9751 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9752 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9755 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9758 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9764 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9765 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9768 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9770 if (imm_expr.X_op == O_constant
9771 && imm_expr.X_add_number >= -0x8000
9772 && imm_expr.X_add_number < 0x8000)
9774 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9775 dreg, sreg, BFD_RELOC_LO16);
9779 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9780 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9784 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9787 case M_SGT: /* sreg > treg <==> treg < sreg */
9793 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9796 case M_SGT_I: /* sreg > I <==> I < sreg */
9803 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9804 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9807 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9813 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9814 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9817 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9824 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9825 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9826 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9830 if (imm_expr.X_op == O_constant
9831 && imm_expr.X_add_number >= -0x8000
9832 && imm_expr.X_add_number < 0x8000)
9834 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9838 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9839 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9843 if (imm_expr.X_op == O_constant
9844 && imm_expr.X_add_number >= -0x8000
9845 && imm_expr.X_add_number < 0x8000)
9847 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9852 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9853 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9858 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9860 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9863 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9864 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9869 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9871 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9876 as_warn (_("Instruction %s: result is always true"),
9878 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9879 dreg, 0, BFD_RELOC_LO16);
9882 if (CPU_HAS_SEQ (mips_opts.arch)
9883 && -512 <= imm_expr.X_add_number
9884 && imm_expr.X_add_number < 512)
9886 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9887 (int) imm_expr.X_add_number);
9890 if (imm_expr.X_op == O_constant
9891 && imm_expr.X_add_number >= 0
9892 && imm_expr.X_add_number < 0x10000)
9894 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9896 else if (imm_expr.X_op == O_constant
9897 && imm_expr.X_add_number > -0x8000
9898 && imm_expr.X_add_number < 0)
9900 imm_expr.X_add_number = -imm_expr.X_add_number;
9901 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9902 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9904 else if (CPU_HAS_SEQ (mips_opts.arch))
9907 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9908 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9913 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9914 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9917 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9932 if (!mips_opts.micromips)
9934 if (imm_expr.X_op == O_constant
9935 && imm_expr.X_add_number > -0x200
9936 && imm_expr.X_add_number <= 0x200)
9938 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9947 if (imm_expr.X_op == O_constant
9948 && imm_expr.X_add_number > -0x8000
9949 && imm_expr.X_add_number <= 0x8000)
9951 imm_expr.X_add_number = -imm_expr.X_add_number;
9952 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9957 load_register (AT, &imm_expr, dbl);
9958 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9980 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9981 macro_build (NULL, s, "s,t", sreg, AT);
9986 gas_assert (!mips_opts.micromips);
9987 gas_assert (mips_opts.isa == ISA_MIPS1);
9989 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9990 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9993 * Is the double cfc1 instruction a bug in the mips assembler;
9994 * or is there a reason for it?
9997 macro_build (NULL, "cfc1", "t,G", treg, RA);
9998 macro_build (NULL, "cfc1", "t,G", treg, RA);
9999 macro_build (NULL, "nop", "");
10000 expr1.X_add_number = 3;
10001 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10002 expr1.X_add_number = 2;
10003 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10004 macro_build (NULL, "ctc1", "t,G", AT, RA);
10005 macro_build (NULL, "nop", "");
10006 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10008 macro_build (NULL, "ctc1", "t,G", treg, RA);
10009 macro_build (NULL, "nop", "");
10032 off12 = mips_opts.micromips;
10040 off12 = mips_opts.micromips;
10056 off12 = mips_opts.micromips;
10065 off12 = mips_opts.micromips;
10070 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10071 as_bad (_("Operand overflow"));
10074 expr1.X_add_number = 0;
10079 load_address (tempreg, ep, &used_at);
10081 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10082 tempreg, tempreg, breg);
10088 && (offset_expr.X_op != O_constant
10089 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10090 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10094 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10095 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10100 else if (!ust && treg == breg)
10111 if (!target_big_endian)
10112 ep->X_add_number += off;
10114 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10116 macro_build (NULL, s, "t,~(b)",
10117 tempreg, (unsigned long) ep->X_add_number, breg);
10119 if (!target_big_endian)
10120 ep->X_add_number -= off;
10122 ep->X_add_number += off;
10124 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10126 macro_build (NULL, s2, "t,~(b)",
10127 tempreg, (unsigned long) ep->X_add_number, breg);
10129 /* If necessary, move the result in tempreg to the final destination. */
10130 if (!ust && treg != tempreg)
10132 /* Protect second load's delay slot. */
10134 move_register (treg, tempreg);
10140 if (target_big_endian == ust)
10141 ep->X_add_number += off;
10142 tempreg = ust || ab ? treg : AT;
10143 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10145 /* For halfword transfers we need a temporary register to shuffle
10146 bytes. Unfortunately for M_USH_A we have none available before
10147 the next store as AT holds the base address. We deal with this
10148 case by clobbering TREG and then restoring it as with ULH. */
10149 tempreg = ust == ab ? treg : AT;
10151 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10153 if (target_big_endian == ust)
10154 ep->X_add_number -= off;
10156 ep->X_add_number += off;
10157 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10159 /* For M_USH_A re-retrieve the LSB. */
10162 if (target_big_endian)
10163 ep->X_add_number += off;
10165 ep->X_add_number -= off;
10166 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10168 /* For ULH and M_USH_A OR the LSB in. */
10171 tempreg = !ab ? AT : treg;
10172 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10173 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10178 /* FIXME: Check if this is one of the itbl macros, since they
10179 are added dynamically. */
10180 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10183 if (!mips_opts.at && used_at)
10184 as_bad (_("Macro used $at after \".set noat\""));
10187 /* Implement macros in mips16 mode. */
10190 mips16_macro (struct mips_cl_insn *ip)
10193 int xreg, yreg, zreg, tmp;
10196 const char *s, *s2, *s3;
10198 mask = ip->insn_mo->mask;
10200 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10201 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10202 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10204 expr1.X_op = O_constant;
10205 expr1.X_op_symbol = NULL;
10206 expr1.X_add_symbol = NULL;
10207 expr1.X_add_number = 1;
10226 start_noreorder ();
10227 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10228 expr1.X_add_number = 2;
10229 macro_build (&expr1, "bnez", "x,p", yreg);
10230 macro_build (NULL, "break", "6", 7);
10232 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10233 since that causes an overflow. We should do that as well,
10234 but I don't see how to do the comparisons without a temporary
10237 macro_build (NULL, s, "x", zreg);
10256 start_noreorder ();
10257 macro_build (NULL, s, "0,x,y", xreg, yreg);
10258 expr1.X_add_number = 2;
10259 macro_build (&expr1, "bnez", "x,p", yreg);
10260 macro_build (NULL, "break", "6", 7);
10262 macro_build (NULL, s2, "x", zreg);
10268 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10269 macro_build (NULL, "mflo", "x", zreg);
10277 if (imm_expr.X_op != O_constant)
10278 as_bad (_("Unsupported large constant"));
10279 imm_expr.X_add_number = -imm_expr.X_add_number;
10280 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10284 if (imm_expr.X_op != O_constant)
10285 as_bad (_("Unsupported large constant"));
10286 imm_expr.X_add_number = -imm_expr.X_add_number;
10287 macro_build (&imm_expr, "addiu", "x,k", xreg);
10291 if (imm_expr.X_op != O_constant)
10292 as_bad (_("Unsupported large constant"));
10293 imm_expr.X_add_number = -imm_expr.X_add_number;
10294 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10316 goto do_reverse_branch;
10320 goto do_reverse_branch;
10332 goto do_reverse_branch;
10343 macro_build (NULL, s, "x,y", xreg, yreg);
10344 macro_build (&offset_expr, s2, "p");
10371 goto do_addone_branch_i;
10376 goto do_addone_branch_i;
10391 goto do_addone_branch_i;
10397 do_addone_branch_i:
10398 if (imm_expr.X_op != O_constant)
10399 as_bad (_("Unsupported large constant"));
10400 ++imm_expr.X_add_number;
10403 macro_build (&imm_expr, s, s3, xreg);
10404 macro_build (&offset_expr, s2, "p");
10408 expr1.X_add_number = 0;
10409 macro_build (&expr1, "slti", "x,8", yreg);
10411 move_register (xreg, yreg);
10412 expr1.X_add_number = 2;
10413 macro_build (&expr1, "bteqz", "p");
10414 macro_build (NULL, "neg", "x,w", xreg, xreg);
10418 /* For consistency checking, verify that all bits are specified either
10419 by the match/mask part of the instruction definition, or by the
10422 validate_mips_insn (const struct mips_opcode *opc)
10424 const char *p = opc->args;
10426 unsigned long used_bits = opc->mask;
10428 if ((used_bits & opc->match) != opc->match)
10430 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10431 opc->name, opc->args);
10434 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10444 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10445 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10446 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10447 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10448 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10449 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10450 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10451 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10452 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10453 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10454 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10455 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10456 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10458 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10459 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10460 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10461 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10462 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10463 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10464 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10465 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10466 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10467 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10468 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10469 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10470 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10471 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10472 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10473 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10476 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10477 c, opc->name, opc->args);
10481 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10482 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10484 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10485 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10486 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10487 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10489 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10490 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10492 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10493 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10495 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10496 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10497 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10498 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10499 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10500 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10501 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10502 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10503 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10504 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10505 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10506 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10507 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10508 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10509 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10510 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10511 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10513 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10514 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10515 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10516 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10518 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10519 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10520 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10521 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10522 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10523 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10524 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10525 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10526 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10529 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10530 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10531 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10532 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10533 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10536 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10537 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10538 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10539 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10540 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10541 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10542 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10543 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10544 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10545 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10546 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10547 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10548 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10549 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10550 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10551 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10552 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10553 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10554 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10555 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10557 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10558 c, opc->name, opc->args);
10562 if (used_bits != 0xffffffff)
10564 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10565 ~used_bits & 0xffffffff, opc->name, opc->args);
10571 /* For consistency checking, verify that the length implied matches the
10572 major opcode and that all bits are specified either by the match/mask
10573 part of the instruction definition, or by the operand list. */
10576 validate_micromips_insn (const struct mips_opcode *opc)
10578 unsigned long match = opc->match;
10579 unsigned long mask = opc->mask;
10580 const char *p = opc->args;
10581 unsigned long insn_bits;
10582 unsigned long used_bits;
10583 unsigned long major;
10584 unsigned int length;
10588 if ((mask & match) != match)
10590 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10591 opc->name, opc->args);
10594 length = micromips_insn_length (opc);
10595 if (length != 2 && length != 4)
10597 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10598 "%s %s"), length, opc->name, opc->args);
10601 major = match >> (10 + 8 * (length - 2));
10602 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10603 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10605 as_bad (_("Internal error: bad microMIPS opcode "
10606 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10610 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10611 insn_bits = 1 << 4 * length;
10612 insn_bits <<= 4 * length;
10615 #define USE_BITS(field) \
10616 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10627 case 'A': USE_BITS (EXTLSB); break;
10628 case 'B': USE_BITS (INSMSB); break;
10629 case 'C': USE_BITS (EXTMSBD); break;
10630 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10631 case 'E': USE_BITS (EXTLSB); break;
10632 case 'F': USE_BITS (INSMSB); break;
10633 case 'G': USE_BITS (EXTMSBD); break;
10634 case 'H': USE_BITS (EXTMSBD); break;
10636 as_bad (_("Internal error: bad mips opcode "
10637 "(unknown extension operand type `%c%c'): %s %s"),
10638 e, c, opc->name, opc->args);
10646 case 'A': USE_BITS (IMMA); break;
10647 case 'B': USE_BITS (IMMB); break;
10648 case 'C': USE_BITS (IMMC); break;
10649 case 'D': USE_BITS (IMMD); break;
10650 case 'E': USE_BITS (IMME); break;
10651 case 'F': USE_BITS (IMMF); break;
10652 case 'G': USE_BITS (IMMG); break;
10653 case 'H': USE_BITS (IMMH); break;
10654 case 'I': USE_BITS (IMMI); break;
10655 case 'J': USE_BITS (IMMJ); break;
10656 case 'L': USE_BITS (IMML); break;
10657 case 'M': USE_BITS (IMMM); break;
10658 case 'N': USE_BITS (IMMN); break;
10659 case 'O': USE_BITS (IMMO); break;
10660 case 'P': USE_BITS (IMMP); break;
10661 case 'Q': USE_BITS (IMMQ); break;
10662 case 'U': USE_BITS (IMMU); break;
10663 case 'W': USE_BITS (IMMW); break;
10664 case 'X': USE_BITS (IMMX); break;
10665 case 'Y': USE_BITS (IMMY); break;
10668 case 'b': USE_BITS (MB); break;
10669 case 'c': USE_BITS (MC); break;
10670 case 'd': USE_BITS (MD); break;
10671 case 'e': USE_BITS (ME); break;
10672 case 'f': USE_BITS (MF); break;
10673 case 'g': USE_BITS (MG); break;
10674 case 'h': USE_BITS (MH); break;
10675 case 'i': USE_BITS (MI); break;
10676 case 'j': USE_BITS (MJ); break;
10677 case 'l': USE_BITS (ML); break;
10678 case 'm': USE_BITS (MM); break;
10679 case 'n': USE_BITS (MN); break;
10680 case 'p': USE_BITS (MP); break;
10681 case 'q': USE_BITS (MQ); break;
10689 as_bad (_("Internal error: bad mips opcode "
10690 "(unknown extension operand type `%c%c'): %s %s"),
10691 e, c, opc->name, opc->args);
10695 case '.': USE_BITS (OFFSET10); break;
10696 case '1': USE_BITS (STYPE); break;
10697 case '2': USE_BITS (BP); break;
10698 case '3': USE_BITS (SA3); break;
10699 case '4': USE_BITS (SA4); break;
10700 case '5': USE_BITS (IMM8); break;
10701 case '6': USE_BITS (RS); break;
10702 case '7': USE_BITS (DSPACC); break;
10703 case '8': USE_BITS (WRDSP); break;
10704 case '0': USE_BITS (DSPSFT); break;
10705 case '<': USE_BITS (SHAMT); break;
10706 case '>': USE_BITS (SHAMT); break;
10707 case '@': USE_BITS (IMM10); break;
10708 case 'B': USE_BITS (CODE10); break;
10709 case 'C': USE_BITS (COPZ); break;
10710 case 'D': USE_BITS (FD); break;
10711 case 'E': USE_BITS (RT); break;
10712 case 'G': USE_BITS (RS); break;
10713 case 'H': USE_BITS (SEL); break;
10714 case 'K': USE_BITS (RS); break;
10715 case 'M': USE_BITS (CCC); break;
10716 case 'N': USE_BITS (BCC); break;
10717 case 'R': USE_BITS (FR); break;
10718 case 'S': USE_BITS (FS); break;
10719 case 'T': USE_BITS (FT); break;
10720 case 'V': USE_BITS (FS); break;
10721 case '\\': USE_BITS (3BITPOS); break;
10722 case '^': USE_BITS (RD); break;
10723 case 'a': USE_BITS (TARGET); break;
10724 case 'b': USE_BITS (RS); break;
10725 case 'c': USE_BITS (CODE); break;
10726 case 'd': USE_BITS (RD); break;
10727 case 'h': USE_BITS (PREFX); break;
10728 case 'i': USE_BITS (IMMEDIATE); break;
10729 case 'j': USE_BITS (DELTA); break;
10730 case 'k': USE_BITS (CACHE); break;
10731 case 'n': USE_BITS (RT); break;
10732 case 'o': USE_BITS (DELTA); break;
10733 case 'p': USE_BITS (DELTA); break;
10734 case 'q': USE_BITS (CODE2); break;
10735 case 'r': USE_BITS (RS); break;
10736 case 's': USE_BITS (RS); break;
10737 case 't': USE_BITS (RT); break;
10738 case 'u': USE_BITS (IMMEDIATE); break;
10739 case 'v': USE_BITS (RS); break;
10740 case 'w': USE_BITS (RT); break;
10741 case 'y': USE_BITS (RS3); break;
10743 case '|': USE_BITS (TRAP); break;
10744 case '~': USE_BITS (OFFSET12); break;
10746 as_bad (_("Internal error: bad microMIPS opcode "
10747 "(unknown operand type `%c'): %s %s"),
10748 c, opc->name, opc->args);
10752 if (used_bits != insn_bits)
10754 if (~used_bits & insn_bits)
10755 as_bad (_("Internal error: bad microMIPS opcode "
10756 "(bits 0x%lx undefined): %s %s"),
10757 ~used_bits & insn_bits, opc->name, opc->args);
10758 if (used_bits & ~insn_bits)
10759 as_bad (_("Internal error: bad microMIPS opcode "
10760 "(bits 0x%lx defined): %s %s"),
10761 used_bits & ~insn_bits, opc->name, opc->args);
10767 /* UDI immediates. */
10768 struct mips_immed {
10770 unsigned int shift;
10771 unsigned long mask;
10775 static const struct mips_immed mips_immed[] = {
10776 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10777 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10778 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10779 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10783 /* Check whether an odd floating-point register is allowed. */
10785 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10787 const char *s = insn->name;
10789 if (insn->pinfo == INSN_MACRO)
10790 /* Let a macro pass, we'll catch it later when it is expanded. */
10793 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10795 /* Allow odd registers for single-precision ops. */
10796 switch (insn->pinfo & (FP_S | FP_D))
10800 return 1; /* both single precision - ok */
10802 return 0; /* both double precision - fail */
10807 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10808 s = strchr (insn->name, '.');
10810 s = s != NULL ? strchr (s + 1, '.') : NULL;
10811 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10814 /* Single-precision coprocessor loads and moves are OK too. */
10815 if ((insn->pinfo & FP_S)
10816 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10817 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10823 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10824 taking bits from BIT up. */
10826 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10828 return (ep->X_op == O_constant
10829 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10830 && ep->X_add_number >= min << bit
10831 && ep->X_add_number < max << bit);
10834 /* This routine assembles an instruction into its binary format. As a
10835 side effect, it sets one of the global variables imm_reloc or
10836 offset_reloc to the type of relocation to do if one of the operands
10837 is an address expression. */
10840 mips_ip (char *str, struct mips_cl_insn *ip)
10842 bfd_boolean wrong_delay_slot_insns = FALSE;
10843 bfd_boolean need_delay_slot_ok = TRUE;
10844 struct mips_opcode *firstinsn = NULL;
10845 const struct mips_opcode *past;
10846 struct hash_control *hash;
10850 struct mips_opcode *insn;
10852 unsigned int regno;
10853 unsigned int lastregno;
10854 unsigned int destregno = 0;
10855 unsigned int lastpos = 0;
10856 unsigned int limlo, limhi;
10859 offsetT min_range, max_range;
10863 unsigned int rtype;
10869 if (mips_opts.micromips)
10871 hash = micromips_op_hash;
10872 past = µmips_opcodes[bfd_micromips_num_opcodes];
10877 past = &mips_opcodes[NUMOPCODES];
10879 forced_insn_length = 0;
10882 /* We first try to match an instruction up to a space or to the end. */
10883 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10886 /* Make a copy of the instruction so that we can fiddle with it. */
10887 name = alloca (end + 1);
10888 memcpy (name, str, end);
10893 insn = (struct mips_opcode *) hash_find (hash, name);
10895 if (insn != NULL || !mips_opts.micromips)
10897 if (forced_insn_length)
10900 /* See if there's an instruction size override suffix,
10901 either `16' or `32', at the end of the mnemonic proper,
10902 that defines the operation, i.e. before the first `.'
10903 character if any. Strip it and retry. */
10904 dot = strchr (name, '.');
10905 opend = dot != NULL ? dot - name : end;
10908 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10909 forced_insn_length = 2;
10910 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10911 forced_insn_length = 4;
10914 memcpy (name + opend - 2, name + opend, end - opend + 1);
10918 insn_error = _("Unrecognized opcode");
10922 /* For microMIPS instructions placed in a fixed-length branch delay slot
10923 we make up to two passes over the relevant fragment of the opcode
10924 table. First we try instructions that meet the delay slot's length
10925 requirement. If none matched, then we retry with the remaining ones
10926 and if one matches, then we use it and then issue an appropriate
10927 warning later on. */
10928 argsStart = s = str + end;
10931 bfd_boolean delay_slot_ok;
10932 bfd_boolean size_ok;
10935 gas_assert (strcmp (insn->name, name) == 0);
10937 ok = is_opcode_valid (insn);
10938 size_ok = is_size_valid (insn);
10939 delay_slot_ok = is_delay_slot_valid (insn);
10940 if (!delay_slot_ok && !wrong_delay_slot_insns)
10943 wrong_delay_slot_insns = TRUE;
10945 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10947 static char buf[256];
10949 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10954 if (wrong_delay_slot_insns && need_delay_slot_ok)
10956 gas_assert (firstinsn);
10957 need_delay_slot_ok = FALSE;
10967 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10968 mips_cpu_info_from_arch (mips_opts.arch)->name,
10969 mips_cpu_info_from_isa (mips_opts.isa)->name);
10971 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10972 8 * forced_insn_length);
10978 create_insn (ip, insn);
10981 lastregno = 0xffffffff;
10982 for (args = insn->args;; ++args)
10986 s += strspn (s, " \t");
10990 case '\0': /* end of args */
10996 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10997 code) or 14 (for microMIPS code). */
10998 my_getExpression (&imm_expr, s);
10999 check_absolute_expr (ip, &imm_expr);
11000 if ((unsigned long) imm_expr.X_add_number != 1
11001 && (unsigned long) imm_expr.X_add_number != 3)
11003 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11004 (unsigned long) imm_expr.X_add_number);
11006 INSERT_OPERAND (mips_opts.micromips,
11007 BP, *ip, imm_expr.X_add_number);
11008 imm_expr.X_op = O_absent;
11013 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11014 code) or 21 (for microMIPS code). */
11016 unsigned long mask = (mips_opts.micromips
11017 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11019 my_getExpression (&imm_expr, s);
11020 check_absolute_expr (ip, &imm_expr);
11021 if ((unsigned long) imm_expr.X_add_number > mask)
11022 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11023 mask, (unsigned long) imm_expr.X_add_number);
11024 INSERT_OPERAND (mips_opts.micromips,
11025 SA3, *ip, imm_expr.X_add_number);
11026 imm_expr.X_op = O_absent;
11032 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11033 code) or 21 (for microMIPS code). */
11035 unsigned long mask = (mips_opts.micromips
11036 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11038 my_getExpression (&imm_expr, s);
11039 check_absolute_expr (ip, &imm_expr);
11040 if ((unsigned long) imm_expr.X_add_number > mask)
11041 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11042 mask, (unsigned long) imm_expr.X_add_number);
11043 INSERT_OPERAND (mips_opts.micromips,
11044 SA4, *ip, imm_expr.X_add_number);
11045 imm_expr.X_op = O_absent;
11051 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11052 code) or 16 (for microMIPS code). */
11054 unsigned long mask = (mips_opts.micromips
11055 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11057 my_getExpression (&imm_expr, s);
11058 check_absolute_expr (ip, &imm_expr);
11059 if ((unsigned long) imm_expr.X_add_number > mask)
11060 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11061 mask, (unsigned long) imm_expr.X_add_number);
11062 INSERT_OPERAND (mips_opts.micromips,
11063 IMM8, *ip, imm_expr.X_add_number);
11064 imm_expr.X_op = O_absent;
11070 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11071 code) or 21 (for microMIPS code). */
11073 unsigned long mask = (mips_opts.micromips
11074 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11076 my_getExpression (&imm_expr, s);
11077 check_absolute_expr (ip, &imm_expr);
11078 if ((unsigned long) imm_expr.X_add_number > mask)
11079 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11080 mask, (unsigned long) imm_expr.X_add_number);
11081 INSERT_OPERAND (mips_opts.micromips,
11082 RS, *ip, imm_expr.X_add_number);
11083 imm_expr.X_op = O_absent;
11088 case '7': /* Four DSP accumulators in bits 11,12. */
11089 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11090 && s[3] >= '0' && s[3] <= '3')
11092 regno = s[3] - '0';
11094 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11098 as_bad (_("Invalid dsp acc register"));
11102 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11103 code) or 14 (for microMIPS code). */
11105 unsigned long mask = (mips_opts.micromips
11106 ? MICROMIPSOP_MASK_WRDSP
11109 my_getExpression (&imm_expr, s);
11110 check_absolute_expr (ip, &imm_expr);
11111 if ((unsigned long) imm_expr.X_add_number > mask)
11112 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11113 mask, (unsigned long) imm_expr.X_add_number);
11114 INSERT_OPERAND (mips_opts.micromips,
11115 WRDSP, *ip, imm_expr.X_add_number);
11116 imm_expr.X_op = O_absent;
11121 case '9': /* Four DSP accumulators in bits 21,22. */
11122 gas_assert (!mips_opts.micromips);
11123 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11124 && s[3] >= '0' && s[3] <= '3')
11126 regno = s[3] - '0';
11128 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11132 as_bad (_("Invalid dsp acc register"));
11136 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11137 code) or 20 (for microMIPS code). */
11139 long mask = (mips_opts.micromips
11140 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11142 my_getExpression (&imm_expr, s);
11143 check_absolute_expr (ip, &imm_expr);
11144 min_range = -((mask + 1) >> 1);
11145 max_range = ((mask + 1) >> 1) - 1;
11146 if (imm_expr.X_add_number < min_range
11147 || imm_expr.X_add_number > max_range)
11148 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11149 (long) min_range, (long) max_range,
11150 (long) imm_expr.X_add_number);
11151 INSERT_OPERAND (mips_opts.micromips,
11152 DSPSFT, *ip, imm_expr.X_add_number);
11153 imm_expr.X_op = O_absent;
11158 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11159 gas_assert (!mips_opts.micromips);
11160 my_getExpression (&imm_expr, s);
11161 check_absolute_expr (ip, &imm_expr);
11162 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11164 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11166 (unsigned long) imm_expr.X_add_number);
11168 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11169 imm_expr.X_op = O_absent;
11173 case ':': /* DSP 7-bit signed immediate in bit 19. */
11174 gas_assert (!mips_opts.micromips);
11175 my_getExpression (&imm_expr, s);
11176 check_absolute_expr (ip, &imm_expr);
11177 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11178 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11179 if (imm_expr.X_add_number < min_range ||
11180 imm_expr.X_add_number > max_range)
11182 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11183 (long) min_range, (long) max_range,
11184 (long) imm_expr.X_add_number);
11186 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11187 imm_expr.X_op = O_absent;
11191 case '@': /* DSP 10-bit signed immediate in bit 16. */
11193 long mask = (mips_opts.micromips
11194 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11196 my_getExpression (&imm_expr, s);
11197 check_absolute_expr (ip, &imm_expr);
11198 min_range = -((mask + 1) >> 1);
11199 max_range = ((mask + 1) >> 1) - 1;
11200 if (imm_expr.X_add_number < min_range
11201 || imm_expr.X_add_number > max_range)
11202 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11203 (long) min_range, (long) max_range,
11204 (long) imm_expr.X_add_number);
11205 INSERT_OPERAND (mips_opts.micromips,
11206 IMM10, *ip, imm_expr.X_add_number);
11207 imm_expr.X_op = O_absent;
11212 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11213 gas_assert (mips_opts.micromips);
11214 my_getExpression (&imm_expr, s);
11215 check_absolute_expr (ip, &imm_expr);
11216 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11217 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11218 MICROMIPSOP_MASK_RD,
11219 (unsigned long) imm_expr.X_add_number);
11220 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11221 imm_expr.X_op = O_absent;
11225 case '!': /* MT usermode flag bit. */
11226 gas_assert (!mips_opts.micromips);
11227 my_getExpression (&imm_expr, s);
11228 check_absolute_expr (ip, &imm_expr);
11229 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11230 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11231 (unsigned long) imm_expr.X_add_number);
11232 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11233 imm_expr.X_op = O_absent;
11237 case '$': /* MT load high flag bit. */
11238 gas_assert (!mips_opts.micromips);
11239 my_getExpression (&imm_expr, s);
11240 check_absolute_expr (ip, &imm_expr);
11241 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11242 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11243 (unsigned long) imm_expr.X_add_number);
11244 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11245 imm_expr.X_op = O_absent;
11249 case '*': /* Four DSP accumulators in bits 18,19. */
11250 gas_assert (!mips_opts.micromips);
11251 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11252 s[3] >= '0' && s[3] <= '3')
11254 regno = s[3] - '0';
11256 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11260 as_bad (_("Invalid dsp/smartmips acc register"));
11263 case '&': /* Four DSP accumulators in bits 13,14. */
11264 gas_assert (!mips_opts.micromips);
11265 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11266 s[3] >= '0' && s[3] <= '3')
11268 regno = s[3] - '0';
11270 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11274 as_bad (_("Invalid dsp/smartmips acc register"));
11277 case '\\': /* 3-bit bit position. */
11279 unsigned long mask = (mips_opts.micromips
11280 ? MICROMIPSOP_MASK_3BITPOS
11281 : OP_MASK_3BITPOS);
11283 my_getExpression (&imm_expr, s);
11284 check_absolute_expr (ip, &imm_expr);
11285 if ((unsigned long) imm_expr.X_add_number > mask)
11286 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11288 mask, (unsigned long) imm_expr.X_add_number);
11289 INSERT_OPERAND (mips_opts.micromips,
11290 3BITPOS, *ip, imm_expr.X_add_number);
11291 imm_expr.X_op = O_absent;
11305 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11309 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11313 gas_assert (!mips_opts.micromips);
11314 INSERT_OPERAND (0, FT, *ip, lastregno);
11318 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11324 /* Handle optional base register.
11325 Either the base register is omitted or
11326 we must have a left paren. */
11327 /* This is dependent on the next operand specifier
11328 is a base register specification. */
11329 gas_assert (args[1] == 'b'
11330 || (mips_opts.micromips
11332 && (args[2] == 'l' || args[2] == 'n'
11333 || args[2] == 's' || args[2] == 'a')));
11334 if (*s == '\0' && args[1] == 'b')
11336 /* Fall through. */
11338 case ')': /* These must match exactly. */
11343 case '[': /* These must match exactly. */
11345 gas_assert (!mips_opts.micromips);
11350 case '+': /* Opcode extension character. */
11353 case '1': /* UDI immediates. */
11357 gas_assert (!mips_opts.micromips);
11359 const struct mips_immed *imm = mips_immed;
11361 while (imm->type && imm->type != *args)
11365 my_getExpression (&imm_expr, s);
11366 check_absolute_expr (ip, &imm_expr);
11367 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11369 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11370 imm->desc ? imm->desc : ip->insn_mo->name,
11371 (unsigned long) imm_expr.X_add_number,
11372 (unsigned long) imm_expr.X_add_number);
11373 imm_expr.X_add_number &= imm->mask;
11375 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11377 imm_expr.X_op = O_absent;
11382 case 'J': /* 10-bit hypcall code. */
11383 gas_assert (!mips_opts.micromips);
11385 unsigned long mask = OP_MASK_CODE10;
11387 my_getExpression (&imm_expr, s);
11388 check_absolute_expr (ip, &imm_expr);
11389 if ((unsigned long) imm_expr.X_add_number > mask)
11390 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11392 mask, (unsigned long) imm_expr.X_add_number);
11393 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11394 imm_expr.X_op = O_absent;
11399 case 'A': /* ins/ext position, becomes LSB. */
11408 my_getExpression (&imm_expr, s);
11409 check_absolute_expr (ip, &imm_expr);
11410 if ((unsigned long) imm_expr.X_add_number < limlo
11411 || (unsigned long) imm_expr.X_add_number > limhi)
11413 as_bad (_("Improper position (%lu)"),
11414 (unsigned long) imm_expr.X_add_number);
11415 imm_expr.X_add_number = limlo;
11417 lastpos = imm_expr.X_add_number;
11418 INSERT_OPERAND (mips_opts.micromips,
11419 EXTLSB, *ip, imm_expr.X_add_number);
11420 imm_expr.X_op = O_absent;
11424 case 'B': /* ins size, becomes MSB. */
11433 my_getExpression (&imm_expr, s);
11434 check_absolute_expr (ip, &imm_expr);
11435 /* Check for negative input so that small negative numbers
11436 will not succeed incorrectly. The checks against
11437 (pos+size) transitively check "size" itself,
11438 assuming that "pos" is reasonable. */
11439 if ((long) imm_expr.X_add_number < 0
11440 || ((unsigned long) imm_expr.X_add_number
11442 || ((unsigned long) imm_expr.X_add_number
11443 + lastpos) > limhi)
11445 as_bad (_("Improper insert size (%lu, position %lu)"),
11446 (unsigned long) imm_expr.X_add_number,
11447 (unsigned long) lastpos);
11448 imm_expr.X_add_number = limlo - lastpos;
11450 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11451 lastpos + imm_expr.X_add_number - 1);
11452 imm_expr.X_op = O_absent;
11456 case 'C': /* ext size, becomes MSBD. */
11472 my_getExpression (&imm_expr, s);
11473 check_absolute_expr (ip, &imm_expr);
11474 /* The checks against (pos+size) don't transitively check
11475 "size" itself, assuming that "pos" is reasonable.
11476 We also need to check the lower bound of "size". */
11477 if ((long) imm_expr.X_add_number < sizelo
11478 || ((unsigned long) imm_expr.X_add_number
11480 || ((unsigned long) imm_expr.X_add_number
11481 + lastpos) > limhi)
11483 as_bad (_("Improper extract size (%lu, position %lu)"),
11484 (unsigned long) imm_expr.X_add_number,
11485 (unsigned long) lastpos);
11486 imm_expr.X_add_number = limlo - lastpos;
11488 INSERT_OPERAND (mips_opts.micromips,
11489 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11490 imm_expr.X_op = O_absent;
11495 /* +D is for disassembly only; never match. */
11499 /* "+I" is like "I", except that imm2_expr is used. */
11500 my_getExpression (&imm2_expr, s);
11501 if (imm2_expr.X_op != O_big
11502 && imm2_expr.X_op != O_constant)
11503 insn_error = _("absolute expression required");
11504 if (HAVE_32BIT_GPRS)
11505 normalize_constant_expr (&imm2_expr);
11509 case 'T': /* Coprocessor register. */
11510 gas_assert (!mips_opts.micromips);
11511 /* +T is for disassembly only; never match. */
11514 case 't': /* Coprocessor register number. */
11515 gas_assert (!mips_opts.micromips);
11516 if (s[0] == '$' && ISDIGIT (s[1]))
11526 while (ISDIGIT (*s));
11528 as_bad (_("Invalid register number (%d)"), regno);
11531 INSERT_OPERAND (0, RT, *ip, regno);
11536 as_bad (_("Invalid coprocessor 0 register number"));
11540 /* bbit[01] and bbit[01]32 bit index. Give error if index
11541 is not in the valid range. */
11542 gas_assert (!mips_opts.micromips);
11543 my_getExpression (&imm_expr, s);
11544 check_absolute_expr (ip, &imm_expr);
11545 if ((unsigned) imm_expr.X_add_number > 31)
11547 as_bad (_("Improper bit index (%lu)"),
11548 (unsigned long) imm_expr.X_add_number);
11549 imm_expr.X_add_number = 0;
11551 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11552 imm_expr.X_op = O_absent;
11557 /* bbit[01] bit index when bbit is used but we generate
11558 bbit[01]32 because the index is over 32. Move to the
11559 next candidate if index is not in the valid range. */
11560 gas_assert (!mips_opts.micromips);
11561 my_getExpression (&imm_expr, s);
11562 check_absolute_expr (ip, &imm_expr);
11563 if ((unsigned) imm_expr.X_add_number < 32
11564 || (unsigned) imm_expr.X_add_number > 63)
11566 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11567 imm_expr.X_op = O_absent;
11572 /* cins, cins32, exts and exts32 position field. Give error
11573 if it's not in the valid range. */
11574 gas_assert (!mips_opts.micromips);
11575 my_getExpression (&imm_expr, s);
11576 check_absolute_expr (ip, &imm_expr);
11577 if ((unsigned) imm_expr.X_add_number > 31)
11579 as_bad (_("Improper position (%lu)"),
11580 (unsigned long) imm_expr.X_add_number);
11581 imm_expr.X_add_number = 0;
11583 /* Make the pos explicit to simplify +S. */
11584 lastpos = imm_expr.X_add_number + 32;
11585 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11586 imm_expr.X_op = O_absent;
11591 /* cins, cins32, exts and exts32 position field. Move to
11592 the next candidate if it's not in the valid range. */
11593 gas_assert (!mips_opts.micromips);
11594 my_getExpression (&imm_expr, s);
11595 check_absolute_expr (ip, &imm_expr);
11596 if ((unsigned) imm_expr.X_add_number < 32
11597 || (unsigned) imm_expr.X_add_number > 63)
11599 lastpos = imm_expr.X_add_number;
11600 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11601 imm_expr.X_op = O_absent;
11606 /* cins and exts length-minus-one field. */
11607 gas_assert (!mips_opts.micromips);
11608 my_getExpression (&imm_expr, s);
11609 check_absolute_expr (ip, &imm_expr);
11610 if ((unsigned long) imm_expr.X_add_number > 31)
11612 as_bad (_("Improper size (%lu)"),
11613 (unsigned long) imm_expr.X_add_number);
11614 imm_expr.X_add_number = 0;
11616 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11617 imm_expr.X_op = O_absent;
11622 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11623 length-minus-one field. */
11624 gas_assert (!mips_opts.micromips);
11625 my_getExpression (&imm_expr, s);
11626 check_absolute_expr (ip, &imm_expr);
11627 if ((long) imm_expr.X_add_number < 0
11628 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11630 as_bad (_("Improper size (%lu)"),
11631 (unsigned long) imm_expr.X_add_number);
11632 imm_expr.X_add_number = 0;
11634 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11635 imm_expr.X_op = O_absent;
11640 /* seqi/snei immediate field. */
11641 gas_assert (!mips_opts.micromips);
11642 my_getExpression (&imm_expr, s);
11643 check_absolute_expr (ip, &imm_expr);
11644 if ((long) imm_expr.X_add_number < -512
11645 || (long) imm_expr.X_add_number >= 512)
11647 as_bad (_("Improper immediate (%ld)"),
11648 (long) imm_expr.X_add_number);
11649 imm_expr.X_add_number = 0;
11651 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11652 imm_expr.X_op = O_absent;
11656 case 'a': /* 8-bit signed offset in bit 6 */
11657 gas_assert (!mips_opts.micromips);
11658 my_getExpression (&imm_expr, s);
11659 check_absolute_expr (ip, &imm_expr);
11660 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11661 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11662 if (imm_expr.X_add_number < min_range
11663 || imm_expr.X_add_number > max_range)
11665 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11666 (long) min_range, (long) max_range,
11667 (long) imm_expr.X_add_number);
11669 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11670 imm_expr.X_op = O_absent;
11674 case 'b': /* 8-bit signed offset in bit 3 */
11675 gas_assert (!mips_opts.micromips);
11676 my_getExpression (&imm_expr, s);
11677 check_absolute_expr (ip, &imm_expr);
11678 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11679 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11680 if (imm_expr.X_add_number < min_range
11681 || imm_expr.X_add_number > max_range)
11683 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11684 (long) min_range, (long) max_range,
11685 (long) imm_expr.X_add_number);
11687 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11688 imm_expr.X_op = O_absent;
11692 case 'c': /* 9-bit signed offset in bit 6 */
11693 gas_assert (!mips_opts.micromips);
11694 my_getExpression (&imm_expr, s);
11695 check_absolute_expr (ip, &imm_expr);
11696 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11697 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11698 /* We check the offset range before adjusted. */
11701 if (imm_expr.X_add_number < min_range
11702 || imm_expr.X_add_number > max_range)
11704 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11705 (long) min_range, (long) max_range,
11706 (long) imm_expr.X_add_number);
11708 if (imm_expr.X_add_number & 0xf)
11710 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11711 (long) imm_expr.X_add_number);
11713 /* Right shift 4 bits to adjust the offset operand. */
11714 INSERT_OPERAND (0, OFFSET_C, *ip,
11715 imm_expr.X_add_number >> 4);
11716 imm_expr.X_op = O_absent;
11721 gas_assert (!mips_opts.micromips);
11722 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11724 if (regno == AT && mips_opts.at)
11726 if (mips_opts.at == ATREG)
11727 as_warn (_("used $at without \".set noat\""));
11729 as_warn (_("used $%u with \".set at=$%u\""),
11730 regno, mips_opts.at);
11732 INSERT_OPERAND (0, RZ, *ip, regno);
11736 gas_assert (!mips_opts.micromips);
11737 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11739 INSERT_OPERAND (0, FZ, *ip, regno);
11743 as_bad (_("Internal error: bad %s opcode "
11744 "(unknown extension operand type `+%c'): %s %s"),
11745 mips_opts.micromips ? "microMIPS" : "MIPS",
11746 *args, insn->name, insn->args);
11747 /* Further processing is fruitless. */
11752 case '.': /* 10-bit offset. */
11753 gas_assert (mips_opts.micromips);
11754 case '~': /* 12-bit offset. */
11756 int shift = *args == '.' ? 9 : 11;
11759 /* Check whether there is only a single bracketed expression
11760 left. If so, it must be the base register and the
11761 constant must be zero. */
11762 if (*s == '(' && strchr (s + 1, '(') == 0)
11765 /* If this value won't fit into the offset, then go find
11766 a macro that will generate a 16- or 32-bit offset code
11768 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11769 if ((i == 0 && (imm_expr.X_op != O_constant
11770 || imm_expr.X_add_number >= 1 << shift
11771 || imm_expr.X_add_number < -1 << shift))
11774 imm_expr.X_op = O_absent;
11778 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11780 INSERT_OPERAND (mips_opts.micromips,
11781 OFFSET12, *ip, imm_expr.X_add_number);
11782 imm_expr.X_op = O_absent;
11787 case '<': /* must be at least one digit */
11789 * According to the manual, if the shift amount is greater
11790 * than 31 or less than 0, then the shift amount should be
11791 * mod 32. In reality the mips assembler issues an error.
11792 * We issue a warning and mask out all but the low 5 bits.
11794 my_getExpression (&imm_expr, s);
11795 check_absolute_expr (ip, &imm_expr);
11796 if ((unsigned long) imm_expr.X_add_number > 31)
11797 as_warn (_("Improper shift amount (%lu)"),
11798 (unsigned long) imm_expr.X_add_number);
11799 INSERT_OPERAND (mips_opts.micromips,
11800 SHAMT, *ip, imm_expr.X_add_number);
11801 imm_expr.X_op = O_absent;
11805 case '>': /* shift amount minus 32 */
11806 my_getExpression (&imm_expr, s);
11807 check_absolute_expr (ip, &imm_expr);
11808 if ((unsigned long) imm_expr.X_add_number < 32
11809 || (unsigned long) imm_expr.X_add_number > 63)
11811 INSERT_OPERAND (mips_opts.micromips,
11812 SHAMT, *ip, imm_expr.X_add_number - 32);
11813 imm_expr.X_op = O_absent;
11817 case 'k': /* CACHE code. */
11818 case 'h': /* PREFX code. */
11819 case '1': /* SYNC type. */
11820 my_getExpression (&imm_expr, s);
11821 check_absolute_expr (ip, &imm_expr);
11822 if ((unsigned long) imm_expr.X_add_number > 31)
11823 as_warn (_("Invalid value for `%s' (%lu)"),
11825 (unsigned long) imm_expr.X_add_number);
11829 if (mips_fix_cn63xxp1
11830 && !mips_opts.micromips
11831 && strcmp ("pref", insn->name) == 0)
11832 switch (imm_expr.X_add_number)
11841 case 31: /* These are ok. */
11844 default: /* The rest must be changed to 28. */
11845 imm_expr.X_add_number = 28;
11848 INSERT_OPERAND (mips_opts.micromips,
11849 CACHE, *ip, imm_expr.X_add_number);
11852 INSERT_OPERAND (mips_opts.micromips,
11853 PREFX, *ip, imm_expr.X_add_number);
11856 INSERT_OPERAND (mips_opts.micromips,
11857 STYPE, *ip, imm_expr.X_add_number);
11860 imm_expr.X_op = O_absent;
11864 case 'c': /* BREAK code. */
11866 unsigned long mask = (mips_opts.micromips
11867 ? MICROMIPSOP_MASK_CODE
11870 my_getExpression (&imm_expr, s);
11871 check_absolute_expr (ip, &imm_expr);
11872 if ((unsigned long) imm_expr.X_add_number > mask)
11873 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11875 mask, (unsigned long) imm_expr.X_add_number);
11876 INSERT_OPERAND (mips_opts.micromips,
11877 CODE, *ip, imm_expr.X_add_number);
11878 imm_expr.X_op = O_absent;
11883 case 'q': /* Lower BREAK code. */
11885 unsigned long mask = (mips_opts.micromips
11886 ? MICROMIPSOP_MASK_CODE2
11889 my_getExpression (&imm_expr, s);
11890 check_absolute_expr (ip, &imm_expr);
11891 if ((unsigned long) imm_expr.X_add_number > mask)
11892 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11894 mask, (unsigned long) imm_expr.X_add_number);
11895 INSERT_OPERAND (mips_opts.micromips,
11896 CODE2, *ip, imm_expr.X_add_number);
11897 imm_expr.X_op = O_absent;
11902 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11904 unsigned long mask = (mips_opts.micromips
11905 ? MICROMIPSOP_MASK_CODE10
11908 my_getExpression (&imm_expr, s);
11909 check_absolute_expr (ip, &imm_expr);
11910 if ((unsigned long) imm_expr.X_add_number > mask)
11911 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11913 mask, (unsigned long) imm_expr.X_add_number);
11914 if (mips_opts.micromips)
11915 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11917 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11918 imm_expr.X_op = O_absent;
11923 case 'C': /* 25- or 23-bit coprocessor code. */
11925 unsigned long mask = (mips_opts.micromips
11926 ? MICROMIPSOP_MASK_COPZ
11929 my_getExpression (&imm_expr, s);
11930 check_absolute_expr (ip, &imm_expr);
11931 if ((unsigned long) imm_expr.X_add_number > mask)
11932 as_warn (_("Coproccesor code > %u bits (%lu)"),
11933 mips_opts.micromips ? 23U : 25U,
11934 (unsigned long) imm_expr.X_add_number);
11935 INSERT_OPERAND (mips_opts.micromips,
11936 COPZ, *ip, imm_expr.X_add_number);
11937 imm_expr.X_op = O_absent;
11942 case 'J': /* 19-bit WAIT code. */
11943 gas_assert (!mips_opts.micromips);
11944 my_getExpression (&imm_expr, s);
11945 check_absolute_expr (ip, &imm_expr);
11946 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11948 as_warn (_("Illegal 19-bit code (%lu)"),
11949 (unsigned long) imm_expr.X_add_number);
11950 imm_expr.X_add_number &= OP_MASK_CODE19;
11952 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11953 imm_expr.X_op = O_absent;
11957 case 'P': /* Performance register. */
11958 gas_assert (!mips_opts.micromips);
11959 my_getExpression (&imm_expr, s);
11960 check_absolute_expr (ip, &imm_expr);
11961 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11962 as_warn (_("Invalid performance register (%lu)"),
11963 (unsigned long) imm_expr.X_add_number);
11964 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
11965 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
11966 as_warn (_("Invalid performance register (%lu)"),
11967 (unsigned long) imm_expr.X_add_number);
11968 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11969 imm_expr.X_op = O_absent;
11973 case 'G': /* Coprocessor destination register. */
11975 unsigned long opcode = ip->insn_opcode;
11976 unsigned long mask;
11977 unsigned int types;
11980 if (mips_opts.micromips)
11982 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11983 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11984 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11988 case 0x000000fc: /* mfc0 */
11989 case 0x000002fc: /* mtc0 */
11990 case 0x580000fc: /* dmfc0 */
11991 case 0x580002fc: /* dmtc0 */
12001 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12002 cop0 = opcode == OP_OP_COP0;
12004 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12005 ok = reg_lookup (&s, types, ®no);
12006 if (mips_opts.micromips)
12007 INSERT_OPERAND (1, RS, *ip, regno);
12009 INSERT_OPERAND (0, RD, *ip, regno);
12018 case 'y': /* ALNV.PS source register. */
12019 gas_assert (mips_opts.micromips);
12021 case 'x': /* Ignore register name. */
12022 case 'U': /* Destination register (CLO/CLZ). */
12023 case 'g': /* Coprocessor destination register. */
12024 gas_assert (!mips_opts.micromips);
12025 case 'b': /* Base register. */
12026 case 'd': /* Destination register. */
12027 case 's': /* Source register. */
12028 case 't': /* Target register. */
12029 case 'r': /* Both target and source. */
12030 case 'v': /* Both dest and source. */
12031 case 'w': /* Both dest and target. */
12032 case 'E': /* Coprocessor target register. */
12033 case 'K': /* RDHWR destination register. */
12034 case 'z': /* Must be zero register. */
12037 if (*args == 'E' || *args == 'K')
12038 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12041 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12042 if (regno == AT && mips_opts.at)
12044 if (mips_opts.at == ATREG)
12045 as_warn (_("Used $at without \".set noat\""));
12047 as_warn (_("Used $%u with \".set at=$%u\""),
12048 regno, mips_opts.at);
12058 if (c == 'r' || c == 'v' || c == 'w')
12065 /* 'z' only matches $0. */
12066 if (c == 'z' && regno != 0)
12069 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12071 if (regno == lastregno)
12074 = _("Source and destination must be different");
12077 if (regno == 31 && lastregno == 0xffffffff)
12080 = _("A destination register must be supplied");
12084 /* Now that we have assembled one operand, we use the args
12085 string to figure out where it goes in the instruction. */
12092 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12096 if (mips_opts.micromips)
12097 INSERT_OPERAND (1, RS, *ip, regno);
12099 INSERT_OPERAND (0, RD, *ip, regno);
12104 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12108 gas_assert (!mips_opts.micromips);
12109 INSERT_OPERAND (0, RD, *ip, regno);
12110 INSERT_OPERAND (0, RT, *ip, regno);
12116 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12120 gas_assert (mips_opts.micromips);
12121 INSERT_OPERAND (1, RS3, *ip, regno);
12125 /* This case exists because on the r3000 trunc
12126 expands into a macro which requires a gp
12127 register. On the r6000 or r4000 it is
12128 assembled into a single instruction which
12129 ignores the register. Thus the insn version
12130 is MIPS_ISA2 and uses 'x', and the macro
12131 version is MIPS_ISA1 and uses 't'. */
12135 /* This case is for the div instruction, which
12136 acts differently if the destination argument
12137 is $0. This only matches $0, and is checked
12138 outside the switch. */
12148 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12152 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12157 case 'O': /* MDMX alignment immediate constant. */
12158 gas_assert (!mips_opts.micromips);
12159 my_getExpression (&imm_expr, s);
12160 check_absolute_expr (ip, &imm_expr);
12161 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12162 as_warn (_("Improper align amount (%ld), using low bits"),
12163 (long) imm_expr.X_add_number);
12164 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12165 imm_expr.X_op = O_absent;
12169 case 'Q': /* MDMX vector, element sel, or const. */
12172 /* MDMX Immediate. */
12173 gas_assert (!mips_opts.micromips);
12174 my_getExpression (&imm_expr, s);
12175 check_absolute_expr (ip, &imm_expr);
12176 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12177 as_warn (_("Invalid MDMX Immediate (%ld)"),
12178 (long) imm_expr.X_add_number);
12179 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12180 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12181 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12183 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12184 imm_expr.X_op = O_absent;
12188 /* Not MDMX Immediate. Fall through. */
12189 case 'X': /* MDMX destination register. */
12190 case 'Y': /* MDMX source register. */
12191 case 'Z': /* MDMX target register. */
12194 gas_assert (!mips_opts.micromips);
12195 case 'D': /* Floating point destination register. */
12196 case 'S': /* Floating point source register. */
12197 case 'T': /* Floating point target register. */
12198 case 'R': /* Floating point source register. */
12202 || (mips_opts.ase_mdmx
12203 && (ip->insn_mo->pinfo & FP_D)
12204 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12205 | INSN_COPROC_MEMORY_DELAY
12206 | INSN_LOAD_COPROC_DELAY
12207 | INSN_LOAD_MEMORY_DELAY
12208 | INSN_STORE_MEMORY))))
12209 rtype |= RTYPE_VEC;
12211 if (reg_lookup (&s, rtype, ®no))
12213 if ((regno & 1) != 0
12215 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12216 as_warn (_("Float register should be even, was %d"),
12224 if (c == 'V' || c == 'W')
12235 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12241 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12245 /* This is like 'Z', but also needs to fix the MDMX
12246 vector/scalar select bits. Note that the
12247 scalar immediate case is handled above. */
12250 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12251 int max_el = (is_qh ? 3 : 7);
12253 my_getExpression(&imm_expr, s);
12254 check_absolute_expr (ip, &imm_expr);
12256 if (imm_expr.X_add_number > max_el)
12257 as_bad (_("Bad element selector %ld"),
12258 (long) imm_expr.X_add_number);
12259 imm_expr.X_add_number &= max_el;
12260 ip->insn_opcode |= (imm_expr.X_add_number
12263 imm_expr.X_op = O_absent;
12265 as_warn (_("Expecting ']' found '%s'"), s);
12271 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12272 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12275 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12278 /* Fall through. */
12282 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12286 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12296 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12300 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12306 my_getExpression (&imm_expr, s);
12307 if (imm_expr.X_op != O_big
12308 && imm_expr.X_op != O_constant)
12309 insn_error = _("absolute expression required");
12310 if (HAVE_32BIT_GPRS)
12311 normalize_constant_expr (&imm_expr);
12316 my_getExpression (&offset_expr, s);
12317 normalize_address_expr (&offset_expr);
12318 *imm_reloc = BFD_RELOC_32;
12331 unsigned char temp[8];
12333 unsigned int length;
12338 /* These only appear as the last operand in an
12339 instruction, and every instruction that accepts
12340 them in any variant accepts them in all variants.
12341 This means we don't have to worry about backing out
12342 any changes if the instruction does not match.
12344 The difference between them is the size of the
12345 floating point constant and where it goes. For 'F'
12346 and 'L' the constant is 64 bits; for 'f' and 'l' it
12347 is 32 bits. Where the constant is placed is based
12348 on how the MIPS assembler does things:
12351 f -- immediate value
12354 The .lit4 and .lit8 sections are only used if
12355 permitted by the -G argument.
12357 The code below needs to know whether the target register
12358 is 32 or 64 bits wide. It relies on the fact 'f' and
12359 'F' are used with GPR-based instructions and 'l' and
12360 'L' are used with FPR-based instructions. */
12362 f64 = *args == 'F' || *args == 'L';
12363 using_gprs = *args == 'F' || *args == 'f';
12365 save_in = input_line_pointer;
12366 input_line_pointer = s;
12367 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12369 s = input_line_pointer;
12370 input_line_pointer = save_in;
12371 if (err != NULL && *err != '\0')
12373 as_bad (_("Bad floating point constant: %s"), err);
12374 memset (temp, '\0', sizeof temp);
12375 length = f64 ? 8 : 4;
12378 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12382 && (g_switch_value < 4
12383 || (temp[0] == 0 && temp[1] == 0)
12384 || (temp[2] == 0 && temp[3] == 0))))
12386 imm_expr.X_op = O_constant;
12387 if (!target_big_endian)
12388 imm_expr.X_add_number = bfd_getl32 (temp);
12390 imm_expr.X_add_number = bfd_getb32 (temp);
12392 else if (length > 4
12393 && !mips_disable_float_construction
12394 /* Constants can only be constructed in GPRs and
12395 copied to FPRs if the GPRs are at least as wide
12396 as the FPRs. Force the constant into memory if
12397 we are using 64-bit FPRs but the GPRs are only
12400 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12401 && ((temp[0] == 0 && temp[1] == 0)
12402 || (temp[2] == 0 && temp[3] == 0))
12403 && ((temp[4] == 0 && temp[5] == 0)
12404 || (temp[6] == 0 && temp[7] == 0)))
12406 /* The value is simple enough to load with a couple of
12407 instructions. If using 32-bit registers, set
12408 imm_expr to the high order 32 bits and offset_expr to
12409 the low order 32 bits. Otherwise, set imm_expr to
12410 the entire 64 bit constant. */
12411 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12413 imm_expr.X_op = O_constant;
12414 offset_expr.X_op = O_constant;
12415 if (!target_big_endian)
12417 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12418 offset_expr.X_add_number = bfd_getl32 (temp);
12422 imm_expr.X_add_number = bfd_getb32 (temp);
12423 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12425 if (offset_expr.X_add_number == 0)
12426 offset_expr.X_op = O_absent;
12428 else if (sizeof (imm_expr.X_add_number) > 4)
12430 imm_expr.X_op = O_constant;
12431 if (!target_big_endian)
12432 imm_expr.X_add_number = bfd_getl64 (temp);
12434 imm_expr.X_add_number = bfd_getb64 (temp);
12438 imm_expr.X_op = O_big;
12439 imm_expr.X_add_number = 4;
12440 if (!target_big_endian)
12442 generic_bignum[0] = bfd_getl16 (temp);
12443 generic_bignum[1] = bfd_getl16 (temp + 2);
12444 generic_bignum[2] = bfd_getl16 (temp + 4);
12445 generic_bignum[3] = bfd_getl16 (temp + 6);
12449 generic_bignum[0] = bfd_getb16 (temp + 6);
12450 generic_bignum[1] = bfd_getb16 (temp + 4);
12451 generic_bignum[2] = bfd_getb16 (temp + 2);
12452 generic_bignum[3] = bfd_getb16 (temp);
12458 const char *newname;
12461 /* Switch to the right section. */
12463 subseg = now_subseg;
12466 default: /* unused default case avoids warnings. */
12468 newname = RDATA_SECTION_NAME;
12469 if (g_switch_value >= 8)
12473 newname = RDATA_SECTION_NAME;
12476 gas_assert (g_switch_value >= 4);
12480 new_seg = subseg_new (newname, (subsegT) 0);
12482 bfd_set_section_flags (stdoutput, new_seg,
12487 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12488 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12489 record_alignment (new_seg, 4);
12491 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12492 if (seg == now_seg)
12493 as_bad (_("Can't use floating point insn in this section"));
12495 /* Set the argument to the current address in the
12497 offset_expr.X_op = O_symbol;
12498 offset_expr.X_add_symbol = symbol_temp_new_now ();
12499 offset_expr.X_add_number = 0;
12501 /* Put the floating point number into the section. */
12502 p = frag_more ((int) length);
12503 memcpy (p, temp, length);
12505 /* Switch back to the original section. */
12506 subseg_set (seg, subseg);
12511 case 'i': /* 16-bit unsigned immediate. */
12512 case 'j': /* 16-bit signed immediate. */
12513 *imm_reloc = BFD_RELOC_LO16;
12514 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12517 offsetT minval, maxval;
12519 more = (insn + 1 < past
12520 && strcmp (insn->name, insn[1].name) == 0);
12522 /* If the expression was written as an unsigned number,
12523 only treat it as signed if there are no more
12527 && sizeof (imm_expr.X_add_number) <= 4
12528 && imm_expr.X_op == O_constant
12529 && imm_expr.X_add_number < 0
12530 && imm_expr.X_unsigned
12531 && HAVE_64BIT_GPRS)
12534 /* For compatibility with older assemblers, we accept
12535 0x8000-0xffff as signed 16-bit numbers when only
12536 signed numbers are allowed. */
12538 minval = 0, maxval = 0xffff;
12540 minval = -0x8000, maxval = 0x7fff;
12542 minval = -0x8000, maxval = 0xffff;
12544 if (imm_expr.X_op != O_constant
12545 || imm_expr.X_add_number < minval
12546 || imm_expr.X_add_number > maxval)
12550 if (imm_expr.X_op == O_constant
12551 || imm_expr.X_op == O_big)
12552 as_bad (_("Expression out of range"));
12558 case 'o': /* 16-bit offset. */
12559 offset_reloc[0] = BFD_RELOC_LO16;
12560 offset_reloc[1] = BFD_RELOC_UNUSED;
12561 offset_reloc[2] = BFD_RELOC_UNUSED;
12563 /* Check whether there is only a single bracketed expression
12564 left. If so, it must be the base register and the
12565 constant must be zero. */
12566 if (*s == '(' && strchr (s + 1, '(') == 0)
12568 offset_expr.X_op = O_constant;
12569 offset_expr.X_add_number = 0;
12573 /* If this value won't fit into a 16 bit offset, then go
12574 find a macro that will generate the 32 bit offset
12576 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12577 && (offset_expr.X_op != O_constant
12578 || offset_expr.X_add_number >= 0x8000
12579 || offset_expr.X_add_number < -0x8000))
12585 case 'p': /* PC-relative offset. */
12586 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12587 my_getExpression (&offset_expr, s);
12591 case 'u': /* Upper 16 bits. */
12592 *imm_reloc = BFD_RELOC_LO16;
12593 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12594 && imm_expr.X_op == O_constant
12595 && (imm_expr.X_add_number < 0
12596 || imm_expr.X_add_number >= 0x10000))
12597 as_bad (_("lui expression (%lu) not in range 0..65535"),
12598 (unsigned long) imm_expr.X_add_number);
12602 case 'a': /* 26-bit address. */
12603 *offset_reloc = BFD_RELOC_MIPS_JMP;
12604 my_getExpression (&offset_expr, s);
12608 case 'N': /* 3-bit branch condition code. */
12609 case 'M': /* 3-bit compare condition code. */
12611 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12612 rtype |= RTYPE_FCC;
12613 if (!reg_lookup (&s, rtype, ®no))
12615 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12616 || strcmp (str + strlen (str) - 5, "any2f") == 0
12617 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12618 && (regno & 1) != 0)
12619 as_warn (_("Condition code register should be even for %s, "
12622 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12623 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12624 && (regno & 3) != 0)
12625 as_warn (_("Condition code register should be 0 or 4 for %s, "
12629 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12631 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12635 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12646 while (ISDIGIT (*s));
12649 c = 8; /* Invalid sel value. */
12652 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12653 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12657 gas_assert (!mips_opts.micromips);
12658 /* Must be at least one digit. */
12659 my_getExpression (&imm_expr, s);
12660 check_absolute_expr (ip, &imm_expr);
12662 if ((unsigned long) imm_expr.X_add_number
12663 > (unsigned long) OP_MASK_VECBYTE)
12665 as_bad (_("bad byte vector index (%ld)"),
12666 (long) imm_expr.X_add_number);
12667 imm_expr.X_add_number = 0;
12670 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12671 imm_expr.X_op = O_absent;
12676 gas_assert (!mips_opts.micromips);
12677 my_getExpression (&imm_expr, s);
12678 check_absolute_expr (ip, &imm_expr);
12680 if ((unsigned long) imm_expr.X_add_number
12681 > (unsigned long) OP_MASK_VECALIGN)
12683 as_bad (_("bad byte vector index (%ld)"),
12684 (long) imm_expr.X_add_number);
12685 imm_expr.X_add_number = 0;
12688 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12689 imm_expr.X_op = O_absent;
12693 case 'm': /* Opcode extension character. */
12694 gas_assert (mips_opts.micromips);
12699 if (strncmp (s, "$pc", 3) == 0)
12727 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12728 if (regno == AT && mips_opts.at)
12730 if (mips_opts.at == ATREG)
12731 as_warn (_("Used $at without \".set noat\""));
12733 as_warn (_("Used $%u with \".set at=$%u\""),
12734 regno, mips_opts.at);
12740 gas_assert (args[1] == ',');
12746 gas_assert (args[1] == ',');
12748 continue; /* Nothing to do. */
12754 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12756 if (regno == lastregno)
12759 = _("Source and destination must be different");
12762 if (regno == 31 && lastregno == 0xffffffff)
12765 = _("A destination register must be supplied");
12776 gas_assert (args[1] == ',');
12783 gas_assert (args[1] == ',');
12786 continue; /* Nothing to do. */
12790 /* Make sure regno is the same as lastregno. */
12791 if (c == 't' && regno != lastregno)
12794 /* Make sure regno is the same as destregno. */
12795 if (c == 'x' && regno != destregno)
12798 /* We need to save regno, before regno maps to the
12799 microMIPS register encoding. */
12809 regno = ILLEGAL_REG;
12813 regno = mips32_to_micromips_reg_b_map[regno];
12817 regno = mips32_to_micromips_reg_c_map[regno];
12821 regno = mips32_to_micromips_reg_d_map[regno];
12825 regno = mips32_to_micromips_reg_e_map[regno];
12829 regno = mips32_to_micromips_reg_f_map[regno];
12833 regno = mips32_to_micromips_reg_g_map[regno];
12837 regno = mips32_to_micromips_reg_h_map[regno];
12841 switch (EXTRACT_OPERAND (1, MI, *ip))
12846 else if (regno == 22)
12848 else if (regno == 5)
12850 else if (regno == 6)
12852 else if (regno == 7)
12855 regno = ILLEGAL_REG;
12861 else if (regno == 7)
12864 regno = ILLEGAL_REG;
12871 regno = ILLEGAL_REG;
12875 regno = ILLEGAL_REG;
12881 regno = mips32_to_micromips_reg_l_map[regno];
12885 regno = mips32_to_micromips_reg_m_map[regno];
12889 regno = mips32_to_micromips_reg_n_map[regno];
12893 regno = mips32_to_micromips_reg_q_map[regno];
12898 regno = ILLEGAL_REG;
12903 regno = ILLEGAL_REG;
12908 regno = ILLEGAL_REG;
12911 case 'j': /* Do nothing. */
12921 if (regno == ILLEGAL_REG)
12927 INSERT_OPERAND (1, MB, *ip, regno);
12931 INSERT_OPERAND (1, MC, *ip, regno);
12935 INSERT_OPERAND (1, MD, *ip, regno);
12939 INSERT_OPERAND (1, ME, *ip, regno);
12943 INSERT_OPERAND (1, MF, *ip, regno);
12947 INSERT_OPERAND (1, MG, *ip, regno);
12951 INSERT_OPERAND (1, MH, *ip, regno);
12955 INSERT_OPERAND (1, MI, *ip, regno);
12959 INSERT_OPERAND (1, MJ, *ip, regno);
12963 INSERT_OPERAND (1, ML, *ip, regno);
12967 INSERT_OPERAND (1, MM, *ip, regno);
12971 INSERT_OPERAND (1, MN, *ip, regno);
12975 INSERT_OPERAND (1, MP, *ip, regno);
12979 INSERT_OPERAND (1, MQ, *ip, regno);
12982 case 'a': /* Do nothing. */
12983 case 's': /* Do nothing. */
12984 case 't': /* Do nothing. */
12985 case 'x': /* Do nothing. */
12986 case 'y': /* Do nothing. */
12987 case 'z': /* Do nothing. */
12997 bfd_reloc_code_real_type r[3];
13001 /* Check whether there is only a single bracketed
13002 expression left. If so, it must be the base register
13003 and the constant must be zero. */
13004 if (*s == '(' && strchr (s + 1, '(') == 0)
13006 INSERT_OPERAND (1, IMMA, *ip, 0);
13010 if (my_getSmallExpression (&ep, r, s) > 0
13011 || !expr_const_in_range (&ep, -64, 64, 2))
13014 imm = ep.X_add_number >> 2;
13015 INSERT_OPERAND (1, IMMA, *ip, imm);
13022 bfd_reloc_code_real_type r[3];
13026 if (my_getSmallExpression (&ep, r, s) > 0
13027 || ep.X_op != O_constant)
13030 for (imm = 0; imm < 8; imm++)
13031 if (micromips_imm_b_map[imm] == ep.X_add_number)
13036 INSERT_OPERAND (1, IMMB, *ip, imm);
13043 bfd_reloc_code_real_type r[3];
13047 if (my_getSmallExpression (&ep, r, s) > 0
13048 || ep.X_op != O_constant)
13051 for (imm = 0; imm < 16; imm++)
13052 if (micromips_imm_c_map[imm] == ep.X_add_number)
13057 INSERT_OPERAND (1, IMMC, *ip, imm);
13062 case 'D': /* pc relative offset */
13063 case 'E': /* pc relative offset */
13064 my_getExpression (&offset_expr, s);
13065 if (offset_expr.X_op == O_register)
13068 if (!forced_insn_length)
13069 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13071 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13073 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13079 bfd_reloc_code_real_type r[3];
13083 if (my_getSmallExpression (&ep, r, s) > 0
13084 || !expr_const_in_range (&ep, 0, 16, 0))
13087 imm = ep.X_add_number;
13088 INSERT_OPERAND (1, IMMF, *ip, imm);
13095 bfd_reloc_code_real_type r[3];
13099 /* Check whether there is only a single bracketed
13100 expression left. If so, it must be the base register
13101 and the constant must be zero. */
13102 if (*s == '(' && strchr (s + 1, '(') == 0)
13104 INSERT_OPERAND (1, IMMG, *ip, 0);
13108 if (my_getSmallExpression (&ep, r, s) > 0
13109 || !expr_const_in_range (&ep, -1, 15, 0))
13112 imm = ep.X_add_number & 15;
13113 INSERT_OPERAND (1, IMMG, *ip, imm);
13120 bfd_reloc_code_real_type r[3];
13124 /* Check whether there is only a single bracketed
13125 expression left. If so, it must be the base register
13126 and the constant must be zero. */
13127 if (*s == '(' && strchr (s + 1, '(') == 0)
13129 INSERT_OPERAND (1, IMMH, *ip, 0);
13133 if (my_getSmallExpression (&ep, r, s) > 0
13134 || !expr_const_in_range (&ep, 0, 16, 1))
13137 imm = ep.X_add_number >> 1;
13138 INSERT_OPERAND (1, IMMH, *ip, imm);
13145 bfd_reloc_code_real_type r[3];
13149 if (my_getSmallExpression (&ep, r, s) > 0
13150 || !expr_const_in_range (&ep, -1, 127, 0))
13153 imm = ep.X_add_number & 127;
13154 INSERT_OPERAND (1, IMMI, *ip, imm);
13161 bfd_reloc_code_real_type r[3];
13165 /* Check whether there is only a single bracketed
13166 expression left. If so, it must be the base register
13167 and the constant must be zero. */
13168 if (*s == '(' && strchr (s + 1, '(') == 0)
13170 INSERT_OPERAND (1, IMMJ, *ip, 0);
13174 if (my_getSmallExpression (&ep, r, s) > 0
13175 || !expr_const_in_range (&ep, 0, 16, 2))
13178 imm = ep.X_add_number >> 2;
13179 INSERT_OPERAND (1, IMMJ, *ip, imm);
13186 bfd_reloc_code_real_type r[3];
13190 /* Check whether there is only a single bracketed
13191 expression left. If so, it must be the base register
13192 and the constant must be zero. */
13193 if (*s == '(' && strchr (s + 1, '(') == 0)
13195 INSERT_OPERAND (1, IMML, *ip, 0);
13199 if (my_getSmallExpression (&ep, r, s) > 0
13200 || !expr_const_in_range (&ep, 0, 16, 0))
13203 imm = ep.X_add_number;
13204 INSERT_OPERAND (1, IMML, *ip, imm);
13211 bfd_reloc_code_real_type r[3];
13215 if (my_getSmallExpression (&ep, r, s) > 0
13216 || !expr_const_in_range (&ep, 1, 9, 0))
13219 imm = ep.X_add_number & 7;
13220 INSERT_OPERAND (1, IMMM, *ip, imm);
13225 case 'N': /* Register list for lwm and swm. */
13227 /* A comma-separated list of registers and/or
13228 dash-separated contiguous ranges including
13229 both ra and a set of one or more registers
13230 starting at s0 up to s3 which have to be
13237 and any permutations of these. */
13238 unsigned int reglist;
13241 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13244 if ((reglist & 0xfff1ffff) != 0x80010000)
13247 reglist = (reglist >> 17) & 7;
13249 if ((reglist & -reglist) != reglist)
13252 imm = ffs (reglist) - 1;
13253 INSERT_OPERAND (1, IMMN, *ip, imm);
13257 case 'O': /* sdbbp 4-bit code. */
13259 bfd_reloc_code_real_type r[3];
13263 if (my_getSmallExpression (&ep, r, s) > 0
13264 || !expr_const_in_range (&ep, 0, 16, 0))
13267 imm = ep.X_add_number;
13268 INSERT_OPERAND (1, IMMO, *ip, imm);
13275 bfd_reloc_code_real_type r[3];
13279 if (my_getSmallExpression (&ep, r, s) > 0
13280 || !expr_const_in_range (&ep, 0, 32, 2))
13283 imm = ep.X_add_number >> 2;
13284 INSERT_OPERAND (1, IMMP, *ip, imm);
13291 bfd_reloc_code_real_type r[3];
13295 if (my_getSmallExpression (&ep, r, s) > 0
13296 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13299 imm = ep.X_add_number >> 2;
13300 INSERT_OPERAND (1, IMMQ, *ip, imm);
13307 bfd_reloc_code_real_type r[3];
13311 /* Check whether there is only a single bracketed
13312 expression left. If so, it must be the base register
13313 and the constant must be zero. */
13314 if (*s == '(' && strchr (s + 1, '(') == 0)
13316 INSERT_OPERAND (1, IMMU, *ip, 0);
13320 if (my_getSmallExpression (&ep, r, s) > 0
13321 || !expr_const_in_range (&ep, 0, 32, 2))
13324 imm = ep.X_add_number >> 2;
13325 INSERT_OPERAND (1, IMMU, *ip, imm);
13332 bfd_reloc_code_real_type r[3];
13336 if (my_getSmallExpression (&ep, r, s) > 0
13337 || !expr_const_in_range (&ep, 0, 64, 2))
13340 imm = ep.X_add_number >> 2;
13341 INSERT_OPERAND (1, IMMW, *ip, imm);
13348 bfd_reloc_code_real_type r[3];
13352 if (my_getSmallExpression (&ep, r, s) > 0
13353 || !expr_const_in_range (&ep, -8, 8, 0))
13356 imm = ep.X_add_number;
13357 INSERT_OPERAND (1, IMMX, *ip, imm);
13364 bfd_reloc_code_real_type r[3];
13368 if (my_getSmallExpression (&ep, r, s) > 0
13369 || expr_const_in_range (&ep, -2, 2, 2)
13370 || !expr_const_in_range (&ep, -258, 258, 2))
13373 imm = ep.X_add_number >> 2;
13374 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13375 INSERT_OPERAND (1, IMMY, *ip, imm);
13382 bfd_reloc_code_real_type r[3];
13385 if (my_getSmallExpression (&ep, r, s) > 0
13386 || !expr_const_in_range (&ep, 0, 1, 0))
13393 as_bad (_("Internal error: bad microMIPS opcode "
13394 "(unknown extension operand type `m%c'): %s %s"),
13395 *args, insn->name, insn->args);
13396 /* Further processing is fruitless. */
13401 case 'n': /* Register list for 32-bit lwm and swm. */
13402 gas_assert (mips_opts.micromips);
13404 /* A comma-separated list of registers and/or
13405 dash-separated contiguous ranges including
13406 at least one of ra and a set of one or more
13407 registers starting at s0 up to s7 and then
13408 s8 which have to be consecutive, e.g.:
13416 and any permutations of these. */
13417 unsigned int reglist;
13421 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13424 if ((reglist & 0x3f00ffff) != 0)
13427 ra = (reglist >> 27) & 0x10;
13428 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13430 if ((reglist & -reglist) != reglist)
13433 imm = (ffs (reglist) - 1) | ra;
13434 INSERT_OPERAND (1, RT, *ip, imm);
13435 imm_expr.X_op = O_absent;
13439 case '|': /* 4-bit trap code. */
13440 gas_assert (mips_opts.micromips);
13441 my_getExpression (&imm_expr, s);
13442 check_absolute_expr (ip, &imm_expr);
13443 if ((unsigned long) imm_expr.X_add_number
13444 > MICROMIPSOP_MASK_TRAP)
13445 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13446 (unsigned long) imm_expr.X_add_number,
13447 ip->insn_mo->name);
13448 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13449 imm_expr.X_op = O_absent;
13454 as_bad (_("Bad char = '%c'\n"), *args);
13459 /* Args don't match. */
13461 insn_error = _("Illegal operands");
13462 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13467 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13469 gas_assert (firstinsn);
13470 need_delay_slot_ok = FALSE;
13479 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13481 /* This routine assembles an instruction into its binary format when
13482 assembling for the mips16. As a side effect, it sets one of the
13483 global variables imm_reloc or offset_reloc to the type of relocation
13484 to do if one of the operands is an address expression. It also sets
13485 forced_insn_length to the resulting instruction size in bytes if the
13486 user explicitly requested a small or extended instruction. */
13489 mips16_ip (char *str, struct mips_cl_insn *ip)
13493 struct mips_opcode *insn;
13495 unsigned int regno;
13496 unsigned int lastregno = 0;
13502 forced_insn_length = 0;
13504 for (s = str; ISLOWER (*s); ++s)
13516 if (s[1] == 't' && s[2] == ' ')
13519 forced_insn_length = 2;
13523 else if (s[1] == 'e' && s[2] == ' ')
13526 forced_insn_length = 4;
13530 /* Fall through. */
13532 insn_error = _("unknown opcode");
13536 if (mips_opts.noautoextend && !forced_insn_length)
13537 forced_insn_length = 2;
13539 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13541 insn_error = _("unrecognized opcode");
13550 gas_assert (strcmp (insn->name, str) == 0);
13552 ok = is_opcode_valid_16 (insn);
13555 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13556 && strcmp (insn->name, insn[1].name) == 0)
13565 static char buf[100];
13567 _("Opcode not supported on this processor: %s (%s)"),
13568 mips_cpu_info_from_arch (mips_opts.arch)->name,
13569 mips_cpu_info_from_isa (mips_opts.isa)->name);
13576 create_insn (ip, insn);
13577 imm_expr.X_op = O_absent;
13578 imm_reloc[0] = BFD_RELOC_UNUSED;
13579 imm_reloc[1] = BFD_RELOC_UNUSED;
13580 imm_reloc[2] = BFD_RELOC_UNUSED;
13581 imm2_expr.X_op = O_absent;
13582 offset_expr.X_op = O_absent;
13583 offset_reloc[0] = BFD_RELOC_UNUSED;
13584 offset_reloc[1] = BFD_RELOC_UNUSED;
13585 offset_reloc[2] = BFD_RELOC_UNUSED;
13586 for (args = insn->args; 1; ++args)
13593 /* In this switch statement we call break if we did not find
13594 a match, continue if we did find a match, or return if we
13605 /* Stuff the immediate value in now, if we can. */
13606 if (imm_expr.X_op == O_constant
13607 && *imm_reloc > BFD_RELOC_UNUSED
13608 && insn->pinfo != INSN_MACRO
13609 && calculate_reloc (*offset_reloc,
13610 imm_expr.X_add_number, &value))
13612 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13613 *offset_reloc, value, forced_insn_length,
13615 imm_expr.X_op = O_absent;
13616 *imm_reloc = BFD_RELOC_UNUSED;
13617 *offset_reloc = BFD_RELOC_UNUSED;
13631 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13634 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13650 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13652 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13656 /* Fall through. */
13667 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13669 if (c == 'v' || c == 'w')
13672 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13674 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13685 if (c == 'v' || c == 'w')
13687 regno = mips16_to_32_reg_map[lastregno];
13701 regno = mips32_to_16_reg_map[regno];
13706 regno = ILLEGAL_REG;
13711 regno = ILLEGAL_REG;
13716 regno = ILLEGAL_REG;
13721 if (regno == AT && mips_opts.at)
13723 if (mips_opts.at == ATREG)
13724 as_warn (_("used $at without \".set noat\""));
13726 as_warn (_("used $%u with \".set at=$%u\""),
13727 regno, mips_opts.at);
13735 if (regno == ILLEGAL_REG)
13742 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13746 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13749 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13752 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13758 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13761 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13762 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13772 if (strncmp (s, "$pc", 3) == 0)
13789 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13792 if (imm_expr.X_op != O_constant)
13794 forced_insn_length = 4;
13795 ip->insn_opcode |= MIPS16_EXTEND;
13799 /* We need to relax this instruction. */
13800 *offset_reloc = *imm_reloc;
13801 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13806 *imm_reloc = BFD_RELOC_UNUSED;
13807 /* Fall through. */
13814 my_getExpression (&imm_expr, s);
13815 if (imm_expr.X_op == O_register)
13817 /* What we thought was an expression turned out to
13820 if (s[0] == '(' && args[1] == '(')
13822 /* It looks like the expression was omitted
13823 before a register indirection, which means
13824 that the expression is implicitly zero. We
13825 still set up imm_expr, so that we handle
13826 explicit extensions correctly. */
13827 imm_expr.X_op = O_constant;
13828 imm_expr.X_add_number = 0;
13829 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13836 /* We need to relax this instruction. */
13837 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13846 /* We use offset_reloc rather than imm_reloc for the PC
13847 relative operands. This lets macros with both
13848 immediate and address operands work correctly. */
13849 my_getExpression (&offset_expr, s);
13851 if (offset_expr.X_op == O_register)
13854 /* We need to relax this instruction. */
13855 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13859 case '6': /* break code */
13860 my_getExpression (&imm_expr, s);
13861 check_absolute_expr (ip, &imm_expr);
13862 if ((unsigned long) imm_expr.X_add_number > 63)
13863 as_warn (_("Invalid value for `%s' (%lu)"),
13865 (unsigned long) imm_expr.X_add_number);
13866 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13867 imm_expr.X_op = O_absent;
13871 case 'a': /* 26 bit address */
13872 my_getExpression (&offset_expr, s);
13874 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13875 ip->insn_opcode <<= 16;
13878 case 'l': /* register list for entry macro */
13879 case 'L': /* register list for exit macro */
13889 unsigned int freg, reg1, reg2;
13891 while (*s == ' ' || *s == ',')
13893 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13895 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13899 as_bad (_("can't parse register list"));
13909 if (!reg_lookup (&s, freg ? RTYPE_FPU
13910 : (RTYPE_GP | RTYPE_NUM), ®2))
13912 as_bad (_("invalid register list"));
13916 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13918 mask &= ~ (7 << 3);
13921 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13923 mask &= ~ (7 << 3);
13926 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13927 mask |= (reg2 - 3) << 3;
13928 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13929 mask |= (reg2 - 15) << 1;
13930 else if (reg1 == RA && reg2 == RA)
13934 as_bad (_("invalid register list"));
13938 /* The mask is filled in in the opcode table for the
13939 benefit of the disassembler. We remove it before
13940 applying the actual mask. */
13941 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13942 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13946 case 'm': /* Register list for save insn. */
13947 case 'M': /* Register list for restore insn. */
13949 int opcode = ip->insn_opcode;
13950 int framesz = 0, seen_framesz = 0;
13951 int nargs = 0, statics = 0, sregs = 0;
13955 unsigned int reg1, reg2;
13957 SKIP_SPACE_TABS (s);
13960 SKIP_SPACE_TABS (s);
13962 my_getExpression (&imm_expr, s);
13963 if (imm_expr.X_op == O_constant)
13965 /* Handle the frame size. */
13968 as_bad (_("more than one frame size in list"));
13972 framesz = imm_expr.X_add_number;
13973 imm_expr.X_op = O_absent;
13978 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13980 as_bad (_("can't parse register list"));
13992 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13995 as_bad (_("can't parse register list"));
14000 while (reg1 <= reg2)
14002 if (reg1 >= 4 && reg1 <= 7)
14006 nargs |= 1 << (reg1 - 4);
14008 /* statics $a0-$a3 */
14009 statics |= 1 << (reg1 - 4);
14011 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14014 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14016 else if (reg1 == 31)
14018 /* Add $ra to insn. */
14023 as_bad (_("unexpected register in list"));
14031 /* Encode args/statics combination. */
14032 if (nargs & statics)
14033 as_bad (_("arg/static registers overlap"));
14034 else if (nargs == 0xf)
14035 /* All $a0-$a3 are args. */
14036 opcode |= MIPS16_ALL_ARGS << 16;
14037 else if (statics == 0xf)
14038 /* All $a0-$a3 are statics. */
14039 opcode |= MIPS16_ALL_STATICS << 16;
14042 int narg = 0, nstat = 0;
14044 /* Count arg registers. */
14045 while (nargs & 0x1)
14051 as_bad (_("invalid arg register list"));
14053 /* Count static registers. */
14054 while (statics & 0x8)
14056 statics = (statics << 1) & 0xf;
14060 as_bad (_("invalid static register list"));
14062 /* Encode args/statics. */
14063 opcode |= ((narg << 2) | nstat) << 16;
14066 /* Encode $s0/$s1. */
14067 if (sregs & (1 << 0)) /* $s0 */
14069 if (sregs & (1 << 1)) /* $s1 */
14075 /* Count regs $s2-$s8. */
14083 as_bad (_("invalid static register list"));
14084 /* Encode $s2-$s8. */
14085 opcode |= nsreg << 24;
14088 /* Encode frame size. */
14090 as_bad (_("missing frame size"));
14091 else if ((framesz & 7) != 0 || framesz < 0
14092 || framesz > 0xff * 8)
14093 as_bad (_("invalid frame size"));
14094 else if (framesz != 128 || (opcode >> 16) != 0)
14097 opcode |= (((framesz & 0xf0) << 16)
14098 | (framesz & 0x0f));
14101 /* Finally build the instruction. */
14102 if ((opcode >> 16) != 0 || framesz == 0)
14103 opcode |= MIPS16_EXTEND;
14104 ip->insn_opcode = opcode;
14108 case 'e': /* extend code */
14109 my_getExpression (&imm_expr, s);
14110 check_absolute_expr (ip, &imm_expr);
14111 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14113 as_warn (_("Invalid value for `%s' (%lu)"),
14115 (unsigned long) imm_expr.X_add_number);
14116 imm_expr.X_add_number &= 0x7ff;
14118 ip->insn_opcode |= imm_expr.X_add_number;
14119 imm_expr.X_op = O_absent;
14129 /* Args don't match. */
14130 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14131 strcmp (insn->name, insn[1].name) == 0)
14138 insn_error = _("illegal operands");
14144 /* This structure holds information we know about a mips16 immediate
14147 struct mips16_immed_operand
14149 /* The type code used in the argument string in the opcode table. */
14151 /* The number of bits in the short form of the opcode. */
14153 /* The number of bits in the extended form of the opcode. */
14155 /* The amount by which the short form is shifted when it is used;
14156 for example, the sw instruction has a shift count of 2. */
14158 /* The amount by which the short form is shifted when it is stored
14159 into the instruction code. */
14161 /* Non-zero if the short form is unsigned. */
14163 /* Non-zero if the extended form is unsigned. */
14165 /* Non-zero if the value is PC relative. */
14169 /* The mips16 immediate operand types. */
14171 static const struct mips16_immed_operand mips16_immed_operands[] =
14173 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14174 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14175 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14176 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14177 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14178 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14179 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14180 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14181 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14182 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14183 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14184 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14185 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14186 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14187 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14188 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14189 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14190 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14191 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14192 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14193 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14196 #define MIPS16_NUM_IMMED \
14197 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14199 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14200 NBITS is the number of significant bits in VAL. */
14202 static unsigned long
14203 mips16_immed_extend (offsetT val, unsigned int nbits)
14208 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14211 else if (nbits == 15)
14213 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14218 extval = ((val & 0x1f) << 6) | (val & 0x20);
14221 return (extval << 16) | val;
14224 /* Install immediate value VAL into MIPS16 instruction *INSN,
14225 extending it if necessary. The instruction in *INSN may
14226 already be extended.
14228 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14229 if none. In the former case, VAL is a 16-bit number with no
14230 defined signedness.
14232 TYPE is the type of the immediate field. USER_INSN_LENGTH
14233 is the length that the user requested, or 0 if none. */
14236 mips16_immed (char *file, unsigned int line, int type,
14237 bfd_reloc_code_real_type reloc, offsetT val,
14238 unsigned int user_insn_length, unsigned long *insn)
14240 const struct mips16_immed_operand *op;
14241 int mintiny, maxtiny;
14243 op = mips16_immed_operands;
14244 while (op->type != type)
14247 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14252 if (type == '<' || type == '>' || type == '[' || type == ']')
14255 maxtiny = 1 << op->nbits;
14260 maxtiny = (1 << op->nbits) - 1;
14262 if (reloc != BFD_RELOC_UNUSED)
14267 mintiny = - (1 << (op->nbits - 1));
14268 maxtiny = (1 << (op->nbits - 1)) - 1;
14269 if (reloc != BFD_RELOC_UNUSED)
14270 val = SEXT_16BIT (val);
14273 /* Branch offsets have an implicit 0 in the lowest bit. */
14274 if (type == 'p' || type == 'q')
14277 if ((val & ((1 << op->shift) - 1)) != 0
14278 || val < (mintiny << op->shift)
14279 || val > (maxtiny << op->shift))
14281 /* We need an extended instruction. */
14282 if (user_insn_length == 2)
14283 as_bad_where (file, line, _("invalid unextended operand value"));
14285 *insn |= MIPS16_EXTEND;
14287 else if (user_insn_length == 4)
14289 /* The operand doesn't force an unextended instruction to be extended.
14290 Warn if the user wanted an extended instruction anyway. */
14291 *insn |= MIPS16_EXTEND;
14292 as_warn_where (file, line,
14293 _("extended operand requested but not required"));
14296 if (mips16_opcode_length (*insn) == 2)
14300 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14301 insnval <<= op->op_shift;
14306 long minext, maxext;
14308 if (reloc == BFD_RELOC_UNUSED)
14313 maxext = (1 << op->extbits) - 1;
14317 minext = - (1 << (op->extbits - 1));
14318 maxext = (1 << (op->extbits - 1)) - 1;
14320 if (val < minext || val > maxext)
14321 as_bad_where (file, line,
14322 _("operand value out of range for instruction"));
14325 *insn |= mips16_immed_extend (val, op->extbits);
14329 struct percent_op_match
14332 bfd_reloc_code_real_type reloc;
14335 static const struct percent_op_match mips_percent_op[] =
14337 {"%lo", BFD_RELOC_LO16},
14339 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14340 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14341 {"%call16", BFD_RELOC_MIPS_CALL16},
14342 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14343 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14344 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14345 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14346 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14347 {"%got", BFD_RELOC_MIPS_GOT16},
14348 {"%gp_rel", BFD_RELOC_GPREL16},
14349 {"%half", BFD_RELOC_16},
14350 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14351 {"%higher", BFD_RELOC_MIPS_HIGHER},
14352 {"%neg", BFD_RELOC_MIPS_SUB},
14353 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14354 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14355 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14356 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14357 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14358 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14359 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14361 {"%hi", BFD_RELOC_HI16_S}
14364 static const struct percent_op_match mips16_percent_op[] =
14366 {"%lo", BFD_RELOC_MIPS16_LO16},
14367 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14368 {"%got", BFD_RELOC_MIPS16_GOT16},
14369 {"%call16", BFD_RELOC_MIPS16_CALL16},
14370 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14371 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14372 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14373 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14374 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14375 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14376 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14377 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14381 /* Return true if *STR points to a relocation operator. When returning true,
14382 move *STR over the operator and store its relocation code in *RELOC.
14383 Leave both *STR and *RELOC alone when returning false. */
14386 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14388 const struct percent_op_match *percent_op;
14391 if (mips_opts.mips16)
14393 percent_op = mips16_percent_op;
14394 limit = ARRAY_SIZE (mips16_percent_op);
14398 percent_op = mips_percent_op;
14399 limit = ARRAY_SIZE (mips_percent_op);
14402 for (i = 0; i < limit; i++)
14403 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14405 int len = strlen (percent_op[i].str);
14407 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14410 *str += strlen (percent_op[i].str);
14411 *reloc = percent_op[i].reloc;
14413 /* Check whether the output BFD supports this relocation.
14414 If not, issue an error and fall back on something safe. */
14415 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14417 as_bad (_("relocation %s isn't supported by the current ABI"),
14418 percent_op[i].str);
14419 *reloc = BFD_RELOC_UNUSED;
14427 /* Parse string STR as a 16-bit relocatable operand. Store the
14428 expression in *EP and the relocations in the array starting
14429 at RELOC. Return the number of relocation operators used.
14431 On exit, EXPR_END points to the first character after the expression. */
14434 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14437 bfd_reloc_code_real_type reversed_reloc[3];
14438 size_t reloc_index, i;
14439 int crux_depth, str_depth;
14442 /* Search for the start of the main expression, recoding relocations
14443 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14444 of the main expression and with CRUX_DEPTH containing the number
14445 of open brackets at that point. */
14452 crux_depth = str_depth;
14454 /* Skip over whitespace and brackets, keeping count of the number
14456 while (*str == ' ' || *str == '\t' || *str == '(')
14461 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14462 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14464 my_getExpression (ep, crux);
14467 /* Match every open bracket. */
14468 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14472 if (crux_depth > 0)
14473 as_bad (_("unclosed '('"));
14477 if (reloc_index != 0)
14479 prev_reloc_op_frag = frag_now;
14480 for (i = 0; i < reloc_index; i++)
14481 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14484 return reloc_index;
14488 my_getExpression (expressionS *ep, char *str)
14492 save_in = input_line_pointer;
14493 input_line_pointer = str;
14495 expr_end = input_line_pointer;
14496 input_line_pointer = save_in;
14500 md_atof (int type, char *litP, int *sizeP)
14502 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14506 md_number_to_chars (char *buf, valueT val, int n)
14508 if (target_big_endian)
14509 number_to_chars_bigendian (buf, val, n);
14511 number_to_chars_littleendian (buf, val, n);
14515 static int support_64bit_objects(void)
14517 const char **list, **l;
14520 list = bfd_target_list ();
14521 for (l = list; *l != NULL; l++)
14522 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14523 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14525 yes = (*l != NULL);
14529 #endif /* OBJ_ELF */
14531 const char *md_shortopts = "O::g::G:";
14535 OPTION_MARCH = OPTION_MD_BASE,
14559 OPTION_NO_SMARTMIPS,
14563 OPTION_NO_MICROMIPS,
14566 OPTION_COMPAT_ARCH_BASE,
14575 OPTION_M7000_HILO_FIX,
14576 OPTION_MNO_7000_HILO_FIX,
14579 OPTION_FIX_LOONGSON2F_JUMP,
14580 OPTION_NO_FIX_LOONGSON2F_JUMP,
14581 OPTION_FIX_LOONGSON2F_NOP,
14582 OPTION_NO_FIX_LOONGSON2F_NOP,
14584 OPTION_NO_FIX_VR4120,
14586 OPTION_NO_FIX_VR4130,
14587 OPTION_FIX_CN63XXP1,
14588 OPTION_NO_FIX_CN63XXP1,
14595 OPTION_CONSTRUCT_FLOATS,
14596 OPTION_NO_CONSTRUCT_FLOATS,
14599 OPTION_RELAX_BRANCH,
14600 OPTION_NO_RELAX_BRANCH,
14607 OPTION_SINGLE_FLOAT,
14608 OPTION_DOUBLE_FLOAT,
14611 OPTION_CALL_SHARED,
14612 OPTION_CALL_NONPIC,
14622 OPTION_MVXWORKS_PIC,
14623 #endif /* OBJ_ELF */
14627 struct option md_longopts[] =
14629 /* Options which specify architecture. */
14630 {"march", required_argument, NULL, OPTION_MARCH},
14631 {"mtune", required_argument, NULL, OPTION_MTUNE},
14632 {"mips0", no_argument, NULL, OPTION_MIPS1},
14633 {"mips1", no_argument, NULL, OPTION_MIPS1},
14634 {"mips2", no_argument, NULL, OPTION_MIPS2},
14635 {"mips3", no_argument, NULL, OPTION_MIPS3},
14636 {"mips4", no_argument, NULL, OPTION_MIPS4},
14637 {"mips5", no_argument, NULL, OPTION_MIPS5},
14638 {"mips32", no_argument, NULL, OPTION_MIPS32},
14639 {"mips64", no_argument, NULL, OPTION_MIPS64},
14640 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14641 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14643 /* Options which specify Application Specific Extensions (ASEs). */
14644 {"mips16", no_argument, NULL, OPTION_MIPS16},
14645 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14646 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14647 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14648 {"mdmx", no_argument, NULL, OPTION_MDMX},
14649 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14650 {"mdsp", no_argument, NULL, OPTION_DSP},
14651 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14652 {"mmt", no_argument, NULL, OPTION_MT},
14653 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14654 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14655 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14656 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14657 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14658 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14659 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14660 {"mmcu", no_argument, NULL, OPTION_MCU},
14661 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14662 {"mvirt", no_argument, NULL, OPTION_VIRT},
14663 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
14665 /* Old-style architecture options. Don't add more of these. */
14666 {"m4650", no_argument, NULL, OPTION_M4650},
14667 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14668 {"m4010", no_argument, NULL, OPTION_M4010},
14669 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14670 {"m4100", no_argument, NULL, OPTION_M4100},
14671 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14672 {"m3900", no_argument, NULL, OPTION_M3900},
14673 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14675 /* Options which enable bug fixes. */
14676 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14677 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14678 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14679 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14680 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14681 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14682 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14683 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14684 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14685 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14686 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14687 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14688 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14689 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14690 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14692 /* Miscellaneous options. */
14693 {"trap", no_argument, NULL, OPTION_TRAP},
14694 {"no-break", no_argument, NULL, OPTION_TRAP},
14695 {"break", no_argument, NULL, OPTION_BREAK},
14696 {"no-trap", no_argument, NULL, OPTION_BREAK},
14697 {"EB", no_argument, NULL, OPTION_EB},
14698 {"EL", no_argument, NULL, OPTION_EL},
14699 {"mfp32", no_argument, NULL, OPTION_FP32},
14700 {"mgp32", no_argument, NULL, OPTION_GP32},
14701 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14702 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14703 {"mfp64", no_argument, NULL, OPTION_FP64},
14704 {"mgp64", no_argument, NULL, OPTION_GP64},
14705 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14706 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14707 {"mshared", no_argument, NULL, OPTION_MSHARED},
14708 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14709 {"msym32", no_argument, NULL, OPTION_MSYM32},
14710 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14711 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14712 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14713 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14714 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14716 /* Strictly speaking this next option is ELF specific,
14717 but we allow it for other ports as well in order to
14718 make testing easier. */
14719 {"32", no_argument, NULL, OPTION_32},
14721 /* ELF-specific options. */
14723 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14724 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14725 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14726 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14727 {"xgot", no_argument, NULL, OPTION_XGOT},
14728 {"mabi", required_argument, NULL, OPTION_MABI},
14729 {"n32", no_argument, NULL, OPTION_N32},
14730 {"64", no_argument, NULL, OPTION_64},
14731 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14732 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14733 {"mpdr", no_argument, NULL, OPTION_PDR},
14734 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14735 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14736 #endif /* OBJ_ELF */
14738 {NULL, no_argument, NULL, 0}
14740 size_t md_longopts_size = sizeof (md_longopts);
14742 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14743 NEW_VALUE. Warn if another value was already specified. Note:
14744 we have to defer parsing the -march and -mtune arguments in order
14745 to handle 'from-abi' correctly, since the ABI might be specified
14746 in a later argument. */
14749 mips_set_option_string (const char **string_ptr, const char *new_value)
14751 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14752 as_warn (_("A different %s was already specified, is now %s"),
14753 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14756 *string_ptr = new_value;
14760 md_parse_option (int c, char *arg)
14764 case OPTION_CONSTRUCT_FLOATS:
14765 mips_disable_float_construction = 0;
14768 case OPTION_NO_CONSTRUCT_FLOATS:
14769 mips_disable_float_construction = 1;
14781 target_big_endian = 1;
14785 target_big_endian = 0;
14791 else if (arg[0] == '0')
14793 else if (arg[0] == '1')
14803 mips_debug = atoi (arg);
14807 file_mips_isa = ISA_MIPS1;
14811 file_mips_isa = ISA_MIPS2;
14815 file_mips_isa = ISA_MIPS3;
14819 file_mips_isa = ISA_MIPS4;
14823 file_mips_isa = ISA_MIPS5;
14826 case OPTION_MIPS32:
14827 file_mips_isa = ISA_MIPS32;
14830 case OPTION_MIPS32R2:
14831 file_mips_isa = ISA_MIPS32R2;
14834 case OPTION_MIPS64R2:
14835 file_mips_isa = ISA_MIPS64R2;
14838 case OPTION_MIPS64:
14839 file_mips_isa = ISA_MIPS64;
14843 mips_set_option_string (&mips_tune_string, arg);
14847 mips_set_option_string (&mips_arch_string, arg);
14851 mips_set_option_string (&mips_arch_string, "4650");
14852 mips_set_option_string (&mips_tune_string, "4650");
14855 case OPTION_NO_M4650:
14859 mips_set_option_string (&mips_arch_string, "4010");
14860 mips_set_option_string (&mips_tune_string, "4010");
14863 case OPTION_NO_M4010:
14867 mips_set_option_string (&mips_arch_string, "4100");
14868 mips_set_option_string (&mips_tune_string, "4100");
14871 case OPTION_NO_M4100:
14875 mips_set_option_string (&mips_arch_string, "3900");
14876 mips_set_option_string (&mips_tune_string, "3900");
14879 case OPTION_NO_M3900:
14883 mips_opts.ase_mdmx = 1;
14886 case OPTION_NO_MDMX:
14887 mips_opts.ase_mdmx = 0;
14891 mips_opts.ase_dsp = 1;
14892 mips_opts.ase_dspr2 = 0;
14895 case OPTION_NO_DSP:
14896 mips_opts.ase_dsp = 0;
14897 mips_opts.ase_dspr2 = 0;
14901 mips_opts.ase_dspr2 = 1;
14902 mips_opts.ase_dsp = 1;
14905 case OPTION_NO_DSPR2:
14906 mips_opts.ase_dspr2 = 0;
14907 mips_opts.ase_dsp = 0;
14911 mips_opts.ase_mt = 1;
14915 mips_opts.ase_mt = 0;
14919 mips_opts.ase_mcu = 1;
14922 case OPTION_NO_MCU:
14923 mips_opts.ase_mcu = 0;
14926 case OPTION_MICROMIPS:
14927 if (mips_opts.mips16 == 1)
14929 as_bad (_("-mmicromips cannot be used with -mips16"));
14932 mips_opts.micromips = 1;
14933 mips_no_prev_insn ();
14936 case OPTION_NO_MICROMIPS:
14937 mips_opts.micromips = 0;
14938 mips_no_prev_insn ();
14942 mips_opts.ase_virt = 1;
14945 case OPTION_NO_VIRT:
14946 mips_opts.ase_virt = 0;
14949 case OPTION_MIPS16:
14950 if (mips_opts.micromips == 1)
14952 as_bad (_("-mips16 cannot be used with -micromips"));
14955 mips_opts.mips16 = 1;
14956 mips_no_prev_insn ();
14959 case OPTION_NO_MIPS16:
14960 mips_opts.mips16 = 0;
14961 mips_no_prev_insn ();
14964 case OPTION_MIPS3D:
14965 mips_opts.ase_mips3d = 1;
14968 case OPTION_NO_MIPS3D:
14969 mips_opts.ase_mips3d = 0;
14972 case OPTION_SMARTMIPS:
14973 mips_opts.ase_smartmips = 1;
14976 case OPTION_NO_SMARTMIPS:
14977 mips_opts.ase_smartmips = 0;
14980 case OPTION_FIX_24K:
14984 case OPTION_NO_FIX_24K:
14988 case OPTION_FIX_LOONGSON2F_JUMP:
14989 mips_fix_loongson2f_jump = TRUE;
14992 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14993 mips_fix_loongson2f_jump = FALSE;
14996 case OPTION_FIX_LOONGSON2F_NOP:
14997 mips_fix_loongson2f_nop = TRUE;
15000 case OPTION_NO_FIX_LOONGSON2F_NOP:
15001 mips_fix_loongson2f_nop = FALSE;
15004 case OPTION_FIX_VR4120:
15005 mips_fix_vr4120 = 1;
15008 case OPTION_NO_FIX_VR4120:
15009 mips_fix_vr4120 = 0;
15012 case OPTION_FIX_VR4130:
15013 mips_fix_vr4130 = 1;
15016 case OPTION_NO_FIX_VR4130:
15017 mips_fix_vr4130 = 0;
15020 case OPTION_FIX_CN63XXP1:
15021 mips_fix_cn63xxp1 = TRUE;
15024 case OPTION_NO_FIX_CN63XXP1:
15025 mips_fix_cn63xxp1 = FALSE;
15028 case OPTION_RELAX_BRANCH:
15029 mips_relax_branch = 1;
15032 case OPTION_NO_RELAX_BRANCH:
15033 mips_relax_branch = 0;
15036 case OPTION_MSHARED:
15037 mips_in_shared = TRUE;
15040 case OPTION_MNO_SHARED:
15041 mips_in_shared = FALSE;
15044 case OPTION_MSYM32:
15045 mips_opts.sym32 = TRUE;
15048 case OPTION_MNO_SYM32:
15049 mips_opts.sym32 = FALSE;
15053 /* When generating ELF code, we permit -KPIC and -call_shared to
15054 select SVR4_PIC, and -non_shared to select no PIC. This is
15055 intended to be compatible with Irix 5. */
15056 case OPTION_CALL_SHARED:
15059 as_bad (_("-call_shared is supported only for ELF format"));
15062 mips_pic = SVR4_PIC;
15063 mips_abicalls = TRUE;
15066 case OPTION_CALL_NONPIC:
15069 as_bad (_("-call_nonpic is supported only for ELF format"));
15073 mips_abicalls = TRUE;
15076 case OPTION_NON_SHARED:
15079 as_bad (_("-non_shared is supported only for ELF format"));
15083 mips_abicalls = FALSE;
15086 /* The -xgot option tells the assembler to use 32 bit offsets
15087 when accessing the got in SVR4_PIC mode. It is for Irix
15092 #endif /* OBJ_ELF */
15095 g_switch_value = atoi (arg);
15099 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15103 mips_abi = O32_ABI;
15104 /* We silently ignore -32 for non-ELF targets. This greatly
15105 simplifies the construction of the MIPS GAS test cases. */
15112 as_bad (_("-n32 is supported for ELF format only"));
15115 mips_abi = N32_ABI;
15121 as_bad (_("-64 is supported for ELF format only"));
15124 mips_abi = N64_ABI;
15125 if (!support_64bit_objects())
15126 as_fatal (_("No compiled in support for 64 bit object file format"));
15128 #endif /* OBJ_ELF */
15131 file_mips_gp32 = 1;
15135 file_mips_gp32 = 0;
15139 file_mips_fp32 = 1;
15143 file_mips_fp32 = 0;
15146 case OPTION_SINGLE_FLOAT:
15147 file_mips_single_float = 1;
15150 case OPTION_DOUBLE_FLOAT:
15151 file_mips_single_float = 0;
15154 case OPTION_SOFT_FLOAT:
15155 file_mips_soft_float = 1;
15158 case OPTION_HARD_FLOAT:
15159 file_mips_soft_float = 0;
15166 as_bad (_("-mabi is supported for ELF format only"));
15169 if (strcmp (arg, "32") == 0)
15170 mips_abi = O32_ABI;
15171 else if (strcmp (arg, "o64") == 0)
15172 mips_abi = O64_ABI;
15173 else if (strcmp (arg, "n32") == 0)
15174 mips_abi = N32_ABI;
15175 else if (strcmp (arg, "64") == 0)
15177 mips_abi = N64_ABI;
15178 if (! support_64bit_objects())
15179 as_fatal (_("No compiled in support for 64 bit object file "
15182 else if (strcmp (arg, "eabi") == 0)
15183 mips_abi = EABI_ABI;
15186 as_fatal (_("invalid abi -mabi=%s"), arg);
15190 #endif /* OBJ_ELF */
15192 case OPTION_M7000_HILO_FIX:
15193 mips_7000_hilo_fix = TRUE;
15196 case OPTION_MNO_7000_HILO_FIX:
15197 mips_7000_hilo_fix = FALSE;
15201 case OPTION_MDEBUG:
15202 mips_flag_mdebug = TRUE;
15205 case OPTION_NO_MDEBUG:
15206 mips_flag_mdebug = FALSE;
15210 mips_flag_pdr = TRUE;
15213 case OPTION_NO_PDR:
15214 mips_flag_pdr = FALSE;
15217 case OPTION_MVXWORKS_PIC:
15218 mips_pic = VXWORKS_PIC;
15220 #endif /* OBJ_ELF */
15226 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15231 /* Set up globals to generate code for the ISA or processor
15232 described by INFO. */
15235 mips_set_architecture (const struct mips_cpu_info *info)
15239 file_mips_arch = info->cpu;
15240 mips_opts.arch = info->cpu;
15241 mips_opts.isa = info->isa;
15246 /* Likewise for tuning. */
15249 mips_set_tune (const struct mips_cpu_info *info)
15252 mips_tune = info->cpu;
15257 mips_after_parse_args (void)
15259 const struct mips_cpu_info *arch_info = 0;
15260 const struct mips_cpu_info *tune_info = 0;
15262 /* GP relative stuff not working for PE */
15263 if (strncmp (TARGET_OS, "pe", 2) == 0)
15265 if (g_switch_seen && g_switch_value != 0)
15266 as_bad (_("-G not supported in this configuration."));
15267 g_switch_value = 0;
15270 if (mips_abi == NO_ABI)
15271 mips_abi = MIPS_DEFAULT_ABI;
15273 /* The following code determines the architecture and register size.
15274 Similar code was added to GCC 3.3 (see override_options() in
15275 config/mips/mips.c). The GAS and GCC code should be kept in sync
15276 as much as possible. */
15278 if (mips_arch_string != 0)
15279 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15281 if (file_mips_isa != ISA_UNKNOWN)
15283 /* Handle -mipsN. At this point, file_mips_isa contains the
15284 ISA level specified by -mipsN, while arch_info->isa contains
15285 the -march selection (if any). */
15286 if (arch_info != 0)
15288 /* -march takes precedence over -mipsN, since it is more descriptive.
15289 There's no harm in specifying both as long as the ISA levels
15291 if (file_mips_isa != arch_info->isa)
15292 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15293 mips_cpu_info_from_isa (file_mips_isa)->name,
15294 mips_cpu_info_from_isa (arch_info->isa)->name);
15297 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15300 if (arch_info == 0)
15302 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15303 gas_assert (arch_info);
15306 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15307 as_bad (_("-march=%s is not compatible with the selected ABI"),
15310 mips_set_architecture (arch_info);
15312 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15313 if (mips_tune_string != 0)
15314 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15316 if (tune_info == 0)
15317 mips_set_tune (arch_info);
15319 mips_set_tune (tune_info);
15321 if (file_mips_gp32 >= 0)
15323 /* The user specified the size of the integer registers. Make sure
15324 it agrees with the ABI and ISA. */
15325 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15326 as_bad (_("-mgp64 used with a 32-bit processor"));
15327 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15328 as_bad (_("-mgp32 used with a 64-bit ABI"));
15329 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15330 as_bad (_("-mgp64 used with a 32-bit ABI"));
15334 /* Infer the integer register size from the ABI and processor.
15335 Restrict ourselves to 32-bit registers if that's all the
15336 processor has, or if the ABI cannot handle 64-bit registers. */
15337 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15338 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15341 switch (file_mips_fp32)
15345 /* No user specified float register size.
15346 ??? GAS treats single-float processors as though they had 64-bit
15347 float registers (although it complains when double-precision
15348 instructions are used). As things stand, saying they have 32-bit
15349 registers would lead to spurious "register must be even" messages.
15350 So here we assume float registers are never smaller than the
15352 if (file_mips_gp32 == 0)
15353 /* 64-bit integer registers implies 64-bit float registers. */
15354 file_mips_fp32 = 0;
15355 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15356 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15357 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15358 file_mips_fp32 = 0;
15360 /* 32-bit float registers. */
15361 file_mips_fp32 = 1;
15364 /* The user specified the size of the float registers. Check if it
15365 agrees with the ABI and ISA. */
15367 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15368 as_bad (_("-mfp64 used with a 32-bit fpu"));
15369 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15370 && !ISA_HAS_MXHC1 (mips_opts.isa))
15371 as_warn (_("-mfp64 used with a 32-bit ABI"));
15374 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15375 as_warn (_("-mfp32 used with a 64-bit ABI"));
15379 /* End of GCC-shared inference code. */
15381 /* This flag is set when we have a 64-bit capable CPU but use only
15382 32-bit wide registers. Note that EABI does not use it. */
15383 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15384 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15385 || mips_abi == O32_ABI))
15386 mips_32bitmode = 1;
15388 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15389 as_bad (_("trap exception not supported at ISA 1"));
15391 /* If the selected architecture includes support for ASEs, enable
15392 generation of code for them. */
15393 if (mips_opts.mips16 == -1)
15394 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15395 if (mips_opts.micromips == -1)
15396 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15397 if (mips_opts.ase_mips3d == -1)
15398 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15399 && file_mips_fp32 == 0) ? 1 : 0;
15400 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15401 as_bad (_("-mfp32 used with -mips3d"));
15403 if (mips_opts.ase_mdmx == -1)
15404 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15405 && file_mips_fp32 == 0) ? 1 : 0;
15406 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15407 as_bad (_("-mfp32 used with -mdmx"));
15409 if (mips_opts.ase_smartmips == -1)
15410 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15411 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15412 as_warn (_("%s ISA does not support SmartMIPS"),
15413 mips_cpu_info_from_isa (mips_opts.isa)->name);
15415 if (mips_opts.ase_dsp == -1)
15416 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15417 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15418 as_warn (_("%s ISA does not support DSP ASE"),
15419 mips_cpu_info_from_isa (mips_opts.isa)->name);
15421 if (mips_opts.ase_dspr2 == -1)
15423 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15424 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15426 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15427 as_warn (_("%s ISA does not support DSP R2 ASE"),
15428 mips_cpu_info_from_isa (mips_opts.isa)->name);
15430 if (mips_opts.ase_mt == -1)
15431 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15432 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15433 as_warn (_("%s ISA does not support MT ASE"),
15434 mips_cpu_info_from_isa (mips_opts.isa)->name);
15436 if (mips_opts.ase_mcu == -1)
15437 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15438 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15439 as_warn (_("%s ISA does not support MCU ASE"),
15440 mips_cpu_info_from_isa (mips_opts.isa)->name);
15442 if (mips_opts.ase_virt == -1)
15443 mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0;
15444 if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE)
15445 as_warn (_("%s ISA does not support Virtualization ASE"),
15446 mips_cpu_info_from_isa (mips_opts.isa)->name);
15448 file_mips_isa = mips_opts.isa;
15449 file_ase_mips3d = mips_opts.ase_mips3d;
15450 file_ase_mdmx = mips_opts.ase_mdmx;
15451 file_ase_smartmips = mips_opts.ase_smartmips;
15452 file_ase_dsp = mips_opts.ase_dsp;
15453 file_ase_dspr2 = mips_opts.ase_dspr2;
15454 file_ase_mt = mips_opts.ase_mt;
15455 file_ase_virt = mips_opts.ase_virt;
15456 mips_opts.gp32 = file_mips_gp32;
15457 mips_opts.fp32 = file_mips_fp32;
15458 mips_opts.soft_float = file_mips_soft_float;
15459 mips_opts.single_float = file_mips_single_float;
15461 if (mips_flag_mdebug < 0)
15463 #ifdef OBJ_MAYBE_ECOFF
15464 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15465 mips_flag_mdebug = 1;
15467 #endif /* OBJ_MAYBE_ECOFF */
15468 mips_flag_mdebug = 0;
15473 mips_init_after_args (void)
15475 /* initialize opcodes */
15476 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15477 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15481 md_pcrel_from (fixS *fixP)
15483 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15484 switch (fixP->fx_r_type)
15486 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15487 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15488 /* Return the address of the delay slot. */
15491 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15492 case BFD_RELOC_MICROMIPS_JMP:
15493 case BFD_RELOC_16_PCREL_S2:
15494 case BFD_RELOC_MIPS_JMP:
15495 /* Return the address of the delay slot. */
15498 case BFD_RELOC_32_PCREL:
15502 /* We have no relocation type for PC relative MIPS16 instructions. */
15503 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15504 as_bad_where (fixP->fx_file, fixP->fx_line,
15505 _("PC relative MIPS16 instruction references a different section"));
15510 /* This is called before the symbol table is processed. In order to
15511 work with gcc when using mips-tfile, we must keep all local labels.
15512 However, in other cases, we want to discard them. If we were
15513 called with -g, but we didn't see any debugging information, it may
15514 mean that gcc is smuggling debugging information through to
15515 mips-tfile, in which case we must generate all local labels. */
15518 mips_frob_file_before_adjust (void)
15520 #ifndef NO_ECOFF_DEBUGGING
15521 if (ECOFF_DEBUGGING
15523 && ! ecoff_debugging_seen)
15524 flag_keep_locals = 1;
15528 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15529 the corresponding LO16 reloc. This is called before md_apply_fix and
15530 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15531 relocation operators.
15533 For our purposes, a %lo() expression matches a %got() or %hi()
15536 (a) it refers to the same symbol; and
15537 (b) the offset applied in the %lo() expression is no lower than
15538 the offset applied in the %got() or %hi().
15540 (b) allows us to cope with code like:
15543 lh $4,%lo(foo+2)($4)
15545 ...which is legal on RELA targets, and has a well-defined behaviour
15546 if the user knows that adding 2 to "foo" will not induce a carry to
15549 When several %lo()s match a particular %got() or %hi(), we use the
15550 following rules to distinguish them:
15552 (1) %lo()s with smaller offsets are a better match than %lo()s with
15555 (2) %lo()s with no matching %got() or %hi() are better than those
15556 that already have a matching %got() or %hi().
15558 (3) later %lo()s are better than earlier %lo()s.
15560 These rules are applied in order.
15562 (1) means, among other things, that %lo()s with identical offsets are
15563 chosen if they exist.
15565 (2) means that we won't associate several high-part relocations with
15566 the same low-part relocation unless there's no alternative. Having
15567 several high parts for the same low part is a GNU extension; this rule
15568 allows careful users to avoid it.
15570 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15571 with the last high-part relocation being at the front of the list.
15572 It therefore makes sense to choose the last matching low-part
15573 relocation, all other things being equal. It's also easier
15574 to code that way. */
15577 mips_frob_file (void)
15579 struct mips_hi_fixup *l;
15580 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15582 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15584 segment_info_type *seginfo;
15585 bfd_boolean matched_lo_p;
15586 fixS **hi_pos, **lo_pos, **pos;
15588 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15590 /* If a GOT16 relocation turns out to be against a global symbol,
15591 there isn't supposed to be a matching LO. Ignore %gots against
15592 constants; we'll report an error for those later. */
15593 if (got16_reloc_p (l->fixp->fx_r_type)
15594 && !(l->fixp->fx_addsy
15595 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15598 /* Check quickly whether the next fixup happens to be a matching %lo. */
15599 if (fixup_has_matching_lo_p (l->fixp))
15602 seginfo = seg_info (l->seg);
15604 /* Set HI_POS to the position of this relocation in the chain.
15605 Set LO_POS to the position of the chosen low-part relocation.
15606 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15607 relocation that matches an immediately-preceding high-part
15611 matched_lo_p = FALSE;
15612 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15614 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15616 if (*pos == l->fixp)
15619 if ((*pos)->fx_r_type == looking_for_rtype
15620 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15621 && (*pos)->fx_offset >= l->fixp->fx_offset
15623 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15625 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15628 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15629 && fixup_has_matching_lo_p (*pos));
15632 /* If we found a match, remove the high-part relocation from its
15633 current position and insert it before the low-part relocation.
15634 Make the offsets match so that fixup_has_matching_lo_p()
15637 We don't warn about unmatched high-part relocations since some
15638 versions of gcc have been known to emit dead "lui ...%hi(...)"
15640 if (lo_pos != NULL)
15642 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15643 if (l->fixp->fx_next != *lo_pos)
15645 *hi_pos = l->fixp->fx_next;
15646 l->fixp->fx_next = *lo_pos;
15654 mips_force_relocation (fixS *fixp)
15656 if (generic_force_reloc (fixp))
15659 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15660 so that the linker relaxation can update targets. */
15661 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15662 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15663 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15669 /* Read the instruction associated with RELOC from BUF. */
15671 static unsigned int
15672 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15674 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15675 return read_compressed_insn (buf, 4);
15677 return read_insn (buf);
15680 /* Write instruction INSN to BUF, given that it has been relocated
15684 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15685 unsigned long insn)
15687 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15688 write_compressed_insn (buf, insn, 4);
15690 write_insn (buf, insn);
15693 /* Apply a fixup to the object file. */
15696 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15699 unsigned long insn;
15700 reloc_howto_type *howto;
15702 /* We ignore generic BFD relocations we don't know about. */
15703 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15707 gas_assert (fixP->fx_size == 2
15708 || fixP->fx_size == 4
15709 || fixP->fx_r_type == BFD_RELOC_16
15710 || fixP->fx_r_type == BFD_RELOC_64
15711 || fixP->fx_r_type == BFD_RELOC_CTOR
15712 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15713 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15714 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15715 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15716 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15718 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15720 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15721 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15722 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15723 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15724 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15726 /* Don't treat parts of a composite relocation as done. There are two
15729 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15730 should nevertheless be emitted if the first part is.
15732 (2) In normal usage, composite relocations are never assembly-time
15733 constants. The easiest way of dealing with the pathological
15734 exceptions is to generate a relocation against STN_UNDEF and
15735 leave everything up to the linker. */
15736 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15739 switch (fixP->fx_r_type)
15741 case BFD_RELOC_MIPS_TLS_GD:
15742 case BFD_RELOC_MIPS_TLS_LDM:
15743 case BFD_RELOC_MIPS_TLS_DTPREL32:
15744 case BFD_RELOC_MIPS_TLS_DTPREL64:
15745 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15746 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15747 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15748 case BFD_RELOC_MIPS_TLS_TPREL32:
15749 case BFD_RELOC_MIPS_TLS_TPREL64:
15750 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15751 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15752 case BFD_RELOC_MICROMIPS_TLS_GD:
15753 case BFD_RELOC_MICROMIPS_TLS_LDM:
15754 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15755 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15756 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15757 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15758 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15759 case BFD_RELOC_MIPS16_TLS_GD:
15760 case BFD_RELOC_MIPS16_TLS_LDM:
15761 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15762 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15763 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15764 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15765 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15766 if (!fixP->fx_addsy)
15768 as_bad_where (fixP->fx_file, fixP->fx_line,
15769 _("TLS relocation against a constant"));
15772 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15775 case BFD_RELOC_MIPS_JMP:
15776 case BFD_RELOC_MIPS_SHIFT5:
15777 case BFD_RELOC_MIPS_SHIFT6:
15778 case BFD_RELOC_MIPS_GOT_DISP:
15779 case BFD_RELOC_MIPS_GOT_PAGE:
15780 case BFD_RELOC_MIPS_GOT_OFST:
15781 case BFD_RELOC_MIPS_SUB:
15782 case BFD_RELOC_MIPS_INSERT_A:
15783 case BFD_RELOC_MIPS_INSERT_B:
15784 case BFD_RELOC_MIPS_DELETE:
15785 case BFD_RELOC_MIPS_HIGHEST:
15786 case BFD_RELOC_MIPS_HIGHER:
15787 case BFD_RELOC_MIPS_SCN_DISP:
15788 case BFD_RELOC_MIPS_REL16:
15789 case BFD_RELOC_MIPS_RELGOT:
15790 case BFD_RELOC_MIPS_JALR:
15791 case BFD_RELOC_HI16:
15792 case BFD_RELOC_HI16_S:
15793 case BFD_RELOC_LO16:
15794 case BFD_RELOC_GPREL16:
15795 case BFD_RELOC_MIPS_LITERAL:
15796 case BFD_RELOC_MIPS_CALL16:
15797 case BFD_RELOC_MIPS_GOT16:
15798 case BFD_RELOC_GPREL32:
15799 case BFD_RELOC_MIPS_GOT_HI16:
15800 case BFD_RELOC_MIPS_GOT_LO16:
15801 case BFD_RELOC_MIPS_CALL_HI16:
15802 case BFD_RELOC_MIPS_CALL_LO16:
15803 case BFD_RELOC_MIPS16_GPREL:
15804 case BFD_RELOC_MIPS16_GOT16:
15805 case BFD_RELOC_MIPS16_CALL16:
15806 case BFD_RELOC_MIPS16_HI16:
15807 case BFD_RELOC_MIPS16_HI16_S:
15808 case BFD_RELOC_MIPS16_LO16:
15809 case BFD_RELOC_MIPS16_JMP:
15810 case BFD_RELOC_MICROMIPS_JMP:
15811 case BFD_RELOC_MICROMIPS_GOT_DISP:
15812 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15813 case BFD_RELOC_MICROMIPS_GOT_OFST:
15814 case BFD_RELOC_MICROMIPS_SUB:
15815 case BFD_RELOC_MICROMIPS_HIGHEST:
15816 case BFD_RELOC_MICROMIPS_HIGHER:
15817 case BFD_RELOC_MICROMIPS_SCN_DISP:
15818 case BFD_RELOC_MICROMIPS_JALR:
15819 case BFD_RELOC_MICROMIPS_HI16:
15820 case BFD_RELOC_MICROMIPS_HI16_S:
15821 case BFD_RELOC_MICROMIPS_LO16:
15822 case BFD_RELOC_MICROMIPS_GPREL16:
15823 case BFD_RELOC_MICROMIPS_LITERAL:
15824 case BFD_RELOC_MICROMIPS_CALL16:
15825 case BFD_RELOC_MICROMIPS_GOT16:
15826 case BFD_RELOC_MICROMIPS_GOT_HI16:
15827 case BFD_RELOC_MICROMIPS_GOT_LO16:
15828 case BFD_RELOC_MICROMIPS_CALL_HI16:
15829 case BFD_RELOC_MICROMIPS_CALL_LO16:
15830 case BFD_RELOC_MIPS_EH:
15835 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15837 insn = read_reloc_insn (buf, fixP->fx_r_type);
15838 if (mips16_reloc_p (fixP->fx_r_type))
15839 insn |= mips16_immed_extend (value, 16);
15841 insn |= (value & 0xffff);
15842 write_reloc_insn (buf, fixP->fx_r_type, insn);
15845 as_bad_where (fixP->fx_file, fixP->fx_line,
15846 _("Unsupported constant in relocation"));
15851 /* This is handled like BFD_RELOC_32, but we output a sign
15852 extended value if we are only 32 bits. */
15855 if (8 <= sizeof (valueT))
15856 md_number_to_chars (buf, *valP, 8);
15861 if ((*valP & 0x80000000) != 0)
15865 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15866 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15871 case BFD_RELOC_RVA:
15873 case BFD_RELOC_32_PCREL:
15875 /* If we are deleting this reloc entry, we must fill in the
15876 value now. This can happen if we have a .word which is not
15877 resolved when it appears but is later defined. */
15879 md_number_to_chars (buf, *valP, fixP->fx_size);
15882 case BFD_RELOC_16_PCREL_S2:
15883 if ((*valP & 0x3) != 0)
15884 as_bad_where (fixP->fx_file, fixP->fx_line,
15885 _("Branch to misaligned address (%lx)"), (long) *valP);
15887 /* We need to save the bits in the instruction since fixup_segment()
15888 might be deleting the relocation entry (i.e., a branch within
15889 the current segment). */
15890 if (! fixP->fx_done)
15893 /* Update old instruction data. */
15894 insn = read_insn (buf);
15896 if (*valP + 0x20000 <= 0x3ffff)
15898 insn |= (*valP >> 2) & 0xffff;
15899 write_insn (buf, insn);
15901 else if (mips_pic == NO_PIC
15903 && fixP->fx_frag->fr_address >= text_section->vma
15904 && (fixP->fx_frag->fr_address
15905 < text_section->vma + bfd_get_section_size (text_section))
15906 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15907 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15908 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15910 /* The branch offset is too large. If this is an
15911 unconditional branch, and we are not generating PIC code,
15912 we can convert it to an absolute jump instruction. */
15913 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15914 insn = 0x0c000000; /* jal */
15916 insn = 0x08000000; /* j */
15917 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15919 fixP->fx_addsy = section_symbol (text_section);
15920 *valP += md_pcrel_from (fixP);
15921 write_insn (buf, insn);
15925 /* If we got here, we have branch-relaxation disabled,
15926 and there's nothing we can do to fix this instruction
15927 without turning it into a longer sequence. */
15928 as_bad_where (fixP->fx_file, fixP->fx_line,
15929 _("Branch out of range"));
15933 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15934 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15935 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15936 /* We adjust the offset back to even. */
15937 if ((*valP & 0x1) != 0)
15940 if (! fixP->fx_done)
15943 /* Should never visit here, because we keep the relocation. */
15947 case BFD_RELOC_VTABLE_INHERIT:
15950 && !S_IS_DEFINED (fixP->fx_addsy)
15951 && !S_IS_WEAK (fixP->fx_addsy))
15952 S_SET_WEAK (fixP->fx_addsy);
15955 case BFD_RELOC_VTABLE_ENTRY:
15963 /* Remember value for tc_gen_reloc. */
15964 fixP->fx_addnumber = *valP;
15974 name = input_line_pointer;
15975 c = get_symbol_end ();
15976 p = (symbolS *) symbol_find_or_make (name);
15977 *input_line_pointer = c;
15981 /* Align the current frag to a given power of two. If a particular
15982 fill byte should be used, FILL points to an integer that contains
15983 that byte, otherwise FILL is null.
15985 This function used to have the comment:
15987 The MIPS assembler also automatically adjusts any preceding label.
15989 The implementation therefore applied the adjustment to a maximum of
15990 one label. However, other label adjustments are applied to batches
15991 of labels, and adjusting just one caused problems when new labels
15992 were added for the sake of debugging or unwind information.
15993 We therefore adjust all preceding labels (given as LABELS) instead. */
15996 mips_align (int to, int *fill, struct insn_label_list *labels)
15998 mips_emit_delays ();
15999 mips_record_compressed_mode ();
16000 if (fill == NULL && subseg_text_p (now_seg))
16001 frag_align_code (to, 0);
16003 frag_align (to, fill ? *fill : 0, 0);
16004 record_alignment (now_seg, to);
16005 mips_move_labels (labels, FALSE);
16008 /* Align to a given power of two. .align 0 turns off the automatic
16009 alignment used by the data creating pseudo-ops. */
16012 s_align (int x ATTRIBUTE_UNUSED)
16014 int temp, fill_value, *fill_ptr;
16015 long max_alignment = 28;
16017 /* o Note that the assembler pulls down any immediately preceding label
16018 to the aligned address.
16019 o It's not documented but auto alignment is reinstated by
16020 a .align pseudo instruction.
16021 o Note also that after auto alignment is turned off the mips assembler
16022 issues an error on attempt to assemble an improperly aligned data item.
16025 temp = get_absolute_expression ();
16026 if (temp > max_alignment)
16027 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16030 as_warn (_("Alignment negative: 0 assumed."));
16033 if (*input_line_pointer == ',')
16035 ++input_line_pointer;
16036 fill_value = get_absolute_expression ();
16037 fill_ptr = &fill_value;
16043 segment_info_type *si = seg_info (now_seg);
16044 struct insn_label_list *l = si->label_list;
16045 /* Auto alignment should be switched on by next section change. */
16047 mips_align (temp, fill_ptr, l);
16054 demand_empty_rest_of_line ();
16058 s_change_sec (int sec)
16063 /* The ELF backend needs to know that we are changing sections, so
16064 that .previous works correctly. We could do something like check
16065 for an obj_section_change_hook macro, but that might be confusing
16066 as it would not be appropriate to use it in the section changing
16067 functions in read.c, since obj-elf.c intercepts those. FIXME:
16068 This should be cleaner, somehow. */
16070 obj_elf_section_change_hook ();
16073 mips_emit_delays ();
16084 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16085 demand_empty_rest_of_line ();
16089 seg = subseg_new (RDATA_SECTION_NAME,
16090 (subsegT) get_absolute_expression ());
16093 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16094 | SEC_READONLY | SEC_RELOC
16096 if (strncmp (TARGET_OS, "elf", 3) != 0)
16097 record_alignment (seg, 4);
16099 demand_empty_rest_of_line ();
16103 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16106 bfd_set_section_flags (stdoutput, seg,
16107 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16108 if (strncmp (TARGET_OS, "elf", 3) != 0)
16109 record_alignment (seg, 4);
16111 demand_empty_rest_of_line ();
16115 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16118 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16119 if (strncmp (TARGET_OS, "elf", 3) != 0)
16120 record_alignment (seg, 4);
16122 demand_empty_rest_of_line ();
16130 s_change_section (int ignore ATTRIBUTE_UNUSED)
16133 char *section_name;
16138 int section_entry_size;
16139 int section_alignment;
16144 section_name = input_line_pointer;
16145 c = get_symbol_end ();
16147 next_c = *(input_line_pointer + 1);
16149 /* Do we have .section Name<,"flags">? */
16150 if (c != ',' || (c == ',' && next_c == '"'))
16152 /* just after name is now '\0'. */
16153 *input_line_pointer = c;
16154 input_line_pointer = section_name;
16155 obj_elf_section (ignore);
16158 input_line_pointer++;
16160 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16162 section_type = get_absolute_expression ();
16165 if (*input_line_pointer++ == ',')
16166 section_flag = get_absolute_expression ();
16169 if (*input_line_pointer++ == ',')
16170 section_entry_size = get_absolute_expression ();
16172 section_entry_size = 0;
16173 if (*input_line_pointer++ == ',')
16174 section_alignment = get_absolute_expression ();
16176 section_alignment = 0;
16177 /* FIXME: really ignore? */
16178 (void) section_alignment;
16180 section_name = xstrdup (section_name);
16182 /* When using the generic form of .section (as implemented by obj-elf.c),
16183 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16184 traditionally had to fall back on the more common @progbits instead.
16186 There's nothing really harmful in this, since bfd will correct
16187 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16188 means that, for backwards compatibility, the special_section entries
16189 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16191 Even so, we shouldn't force users of the MIPS .section syntax to
16192 incorrectly label the sections as SHT_PROGBITS. The best compromise
16193 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16194 generic type-checking code. */
16195 if (section_type == SHT_MIPS_DWARF)
16196 section_type = SHT_PROGBITS;
16198 obj_elf_change_section (section_name, section_type, section_flag,
16199 section_entry_size, 0, 0, 0);
16201 if (now_seg->name != section_name)
16202 free (section_name);
16203 #endif /* OBJ_ELF */
16207 mips_enable_auto_align (void)
16213 s_cons (int log_size)
16215 segment_info_type *si = seg_info (now_seg);
16216 struct insn_label_list *l = si->label_list;
16218 mips_emit_delays ();
16219 if (log_size > 0 && auto_align)
16220 mips_align (log_size, 0, l);
16221 cons (1 << log_size);
16222 mips_clear_insn_labels ();
16226 s_float_cons (int type)
16228 segment_info_type *si = seg_info (now_seg);
16229 struct insn_label_list *l = si->label_list;
16231 mips_emit_delays ();
16236 mips_align (3, 0, l);
16238 mips_align (2, 0, l);
16242 mips_clear_insn_labels ();
16245 /* Handle .globl. We need to override it because on Irix 5 you are
16248 where foo is an undefined symbol, to mean that foo should be
16249 considered to be the address of a function. */
16252 s_mips_globl (int x ATTRIBUTE_UNUSED)
16261 name = input_line_pointer;
16262 c = get_symbol_end ();
16263 symbolP = symbol_find_or_make (name);
16264 S_SET_EXTERNAL (symbolP);
16266 *input_line_pointer = c;
16267 SKIP_WHITESPACE ();
16269 /* On Irix 5, every global symbol that is not explicitly labelled as
16270 being a function is apparently labelled as being an object. */
16273 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16274 && (*input_line_pointer != ','))
16279 secname = input_line_pointer;
16280 c = get_symbol_end ();
16281 sec = bfd_get_section_by_name (stdoutput, secname);
16283 as_bad (_("%s: no such section"), secname);
16284 *input_line_pointer = c;
16286 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16287 flag = BSF_FUNCTION;
16290 symbol_get_bfdsym (symbolP)->flags |= flag;
16292 c = *input_line_pointer;
16295 input_line_pointer++;
16296 SKIP_WHITESPACE ();
16297 if (is_end_of_line[(unsigned char) *input_line_pointer])
16303 demand_empty_rest_of_line ();
16307 s_option (int x ATTRIBUTE_UNUSED)
16312 opt = input_line_pointer;
16313 c = get_symbol_end ();
16317 /* FIXME: What does this mean? */
16319 else if (strncmp (opt, "pic", 3) == 0)
16323 i = atoi (opt + 3);
16328 mips_pic = SVR4_PIC;
16329 mips_abicalls = TRUE;
16332 as_bad (_(".option pic%d not supported"), i);
16334 if (mips_pic == SVR4_PIC)
16336 if (g_switch_seen && g_switch_value != 0)
16337 as_warn (_("-G may not be used with SVR4 PIC code"));
16338 g_switch_value = 0;
16339 bfd_set_gp_size (stdoutput, 0);
16343 as_warn (_("Unrecognized option \"%s\""), opt);
16345 *input_line_pointer = c;
16346 demand_empty_rest_of_line ();
16349 /* This structure is used to hold a stack of .set values. */
16351 struct mips_option_stack
16353 struct mips_option_stack *next;
16354 struct mips_set_options options;
16357 static struct mips_option_stack *mips_opts_stack;
16359 /* Handle the .set pseudo-op. */
16362 s_mipsset (int x ATTRIBUTE_UNUSED)
16364 char *name = input_line_pointer, ch;
16366 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16367 ++input_line_pointer;
16368 ch = *input_line_pointer;
16369 *input_line_pointer = '\0';
16371 if (strcmp (name, "reorder") == 0)
16373 if (mips_opts.noreorder)
16376 else if (strcmp (name, "noreorder") == 0)
16378 if (!mips_opts.noreorder)
16379 start_noreorder ();
16381 else if (strncmp (name, "at=", 3) == 0)
16383 char *s = name + 3;
16385 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16386 as_bad (_("Unrecognized register name `%s'"), s);
16388 else if (strcmp (name, "at") == 0)
16390 mips_opts.at = ATREG;
16392 else if (strcmp (name, "noat") == 0)
16394 mips_opts.at = ZERO;
16396 else if (strcmp (name, "macro") == 0)
16398 mips_opts.warn_about_macros = 0;
16400 else if (strcmp (name, "nomacro") == 0)
16402 if (mips_opts.noreorder == 0)
16403 as_bad (_("`noreorder' must be set before `nomacro'"));
16404 mips_opts.warn_about_macros = 1;
16406 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16408 mips_opts.nomove = 0;
16410 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16412 mips_opts.nomove = 1;
16414 else if (strcmp (name, "bopt") == 0)
16416 mips_opts.nobopt = 0;
16418 else if (strcmp (name, "nobopt") == 0)
16420 mips_opts.nobopt = 1;
16422 else if (strcmp (name, "gp=default") == 0)
16423 mips_opts.gp32 = file_mips_gp32;
16424 else if (strcmp (name, "gp=32") == 0)
16425 mips_opts.gp32 = 1;
16426 else if (strcmp (name, "gp=64") == 0)
16428 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16429 as_warn (_("%s isa does not support 64-bit registers"),
16430 mips_cpu_info_from_isa (mips_opts.isa)->name);
16431 mips_opts.gp32 = 0;
16433 else if (strcmp (name, "fp=default") == 0)
16434 mips_opts.fp32 = file_mips_fp32;
16435 else if (strcmp (name, "fp=32") == 0)
16436 mips_opts.fp32 = 1;
16437 else if (strcmp (name, "fp=64") == 0)
16439 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16440 as_warn (_("%s isa does not support 64-bit floating point registers"),
16441 mips_cpu_info_from_isa (mips_opts.isa)->name);
16442 mips_opts.fp32 = 0;
16444 else if (strcmp (name, "softfloat") == 0)
16445 mips_opts.soft_float = 1;
16446 else if (strcmp (name, "hardfloat") == 0)
16447 mips_opts.soft_float = 0;
16448 else if (strcmp (name, "singlefloat") == 0)
16449 mips_opts.single_float = 1;
16450 else if (strcmp (name, "doublefloat") == 0)
16451 mips_opts.single_float = 0;
16452 else if (strcmp (name, "mips16") == 0
16453 || strcmp (name, "MIPS-16") == 0)
16455 if (mips_opts.micromips == 1)
16456 as_fatal (_("`mips16' cannot be used with `micromips'"));
16457 mips_opts.mips16 = 1;
16459 else if (strcmp (name, "nomips16") == 0
16460 || strcmp (name, "noMIPS-16") == 0)
16461 mips_opts.mips16 = 0;
16462 else if (strcmp (name, "micromips") == 0)
16464 if (mips_opts.mips16 == 1)
16465 as_fatal (_("`micromips' cannot be used with `mips16'"));
16466 mips_opts.micromips = 1;
16468 else if (strcmp (name, "nomicromips") == 0)
16469 mips_opts.micromips = 0;
16470 else if (strcmp (name, "smartmips") == 0)
16472 if (!ISA_SUPPORTS_SMARTMIPS)
16473 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16474 mips_cpu_info_from_isa (mips_opts.isa)->name);
16475 mips_opts.ase_smartmips = 1;
16477 else if (strcmp (name, "nosmartmips") == 0)
16478 mips_opts.ase_smartmips = 0;
16479 else if (strcmp (name, "mips3d") == 0)
16480 mips_opts.ase_mips3d = 1;
16481 else if (strcmp (name, "nomips3d") == 0)
16482 mips_opts.ase_mips3d = 0;
16483 else if (strcmp (name, "mdmx") == 0)
16484 mips_opts.ase_mdmx = 1;
16485 else if (strcmp (name, "nomdmx") == 0)
16486 mips_opts.ase_mdmx = 0;
16487 else if (strcmp (name, "dsp") == 0)
16489 if (!ISA_SUPPORTS_DSP_ASE)
16490 as_warn (_("%s ISA does not support DSP ASE"),
16491 mips_cpu_info_from_isa (mips_opts.isa)->name);
16492 mips_opts.ase_dsp = 1;
16493 mips_opts.ase_dspr2 = 0;
16495 else if (strcmp (name, "nodsp") == 0)
16497 mips_opts.ase_dsp = 0;
16498 mips_opts.ase_dspr2 = 0;
16500 else if (strcmp (name, "dspr2") == 0)
16502 if (!ISA_SUPPORTS_DSPR2_ASE)
16503 as_warn (_("%s ISA does not support DSP R2 ASE"),
16504 mips_cpu_info_from_isa (mips_opts.isa)->name);
16505 mips_opts.ase_dspr2 = 1;
16506 mips_opts.ase_dsp = 1;
16508 else if (strcmp (name, "nodspr2") == 0)
16510 mips_opts.ase_dspr2 = 0;
16511 mips_opts.ase_dsp = 0;
16513 else if (strcmp (name, "mt") == 0)
16515 if (!ISA_SUPPORTS_MT_ASE)
16516 as_warn (_("%s ISA does not support MT ASE"),
16517 mips_cpu_info_from_isa (mips_opts.isa)->name);
16518 mips_opts.ase_mt = 1;
16520 else if (strcmp (name, "nomt") == 0)
16521 mips_opts.ase_mt = 0;
16522 else if (strcmp (name, "mcu") == 0)
16523 mips_opts.ase_mcu = 1;
16524 else if (strcmp (name, "nomcu") == 0)
16525 mips_opts.ase_mcu = 0;
16526 else if (strcmp (name, "virt") == 0)
16528 if (!ISA_SUPPORTS_VIRT_ASE)
16529 as_warn (_("%s ISA does not support Virtualization ASE"),
16530 mips_cpu_info_from_isa (mips_opts.isa)->name);
16531 mips_opts.ase_virt = 1;
16533 else if (strcmp (name, "novirt") == 0)
16534 mips_opts.ase_virt = 0;
16535 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16539 /* Permit the user to change the ISA and architecture on the fly.
16540 Needless to say, misuse can cause serious problems. */
16541 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16544 mips_opts.isa = file_mips_isa;
16545 mips_opts.arch = file_mips_arch;
16547 else if (strncmp (name, "arch=", 5) == 0)
16549 const struct mips_cpu_info *p;
16551 p = mips_parse_cpu("internal use", name + 5);
16553 as_bad (_("unknown architecture %s"), name + 5);
16556 mips_opts.arch = p->cpu;
16557 mips_opts.isa = p->isa;
16560 else if (strncmp (name, "mips", 4) == 0)
16562 const struct mips_cpu_info *p;
16564 p = mips_parse_cpu("internal use", name);
16566 as_bad (_("unknown ISA level %s"), name + 4);
16569 mips_opts.arch = p->cpu;
16570 mips_opts.isa = p->isa;
16574 as_bad (_("unknown ISA or architecture %s"), name);
16576 switch (mips_opts.isa)
16584 mips_opts.gp32 = 1;
16585 mips_opts.fp32 = 1;
16592 mips_opts.gp32 = 0;
16593 if (mips_opts.arch == CPU_R5900)
16595 mips_opts.fp32 = 1;
16599 mips_opts.fp32 = 0;
16603 as_bad (_("unknown ISA level %s"), name + 4);
16608 mips_opts.gp32 = file_mips_gp32;
16609 mips_opts.fp32 = file_mips_fp32;
16612 else if (strcmp (name, "autoextend") == 0)
16613 mips_opts.noautoextend = 0;
16614 else if (strcmp (name, "noautoextend") == 0)
16615 mips_opts.noautoextend = 1;
16616 else if (strcmp (name, "push") == 0)
16618 struct mips_option_stack *s;
16620 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16621 s->next = mips_opts_stack;
16622 s->options = mips_opts;
16623 mips_opts_stack = s;
16625 else if (strcmp (name, "pop") == 0)
16627 struct mips_option_stack *s;
16629 s = mips_opts_stack;
16631 as_bad (_(".set pop with no .set push"));
16634 /* If we're changing the reorder mode we need to handle
16635 delay slots correctly. */
16636 if (s->options.noreorder && ! mips_opts.noreorder)
16637 start_noreorder ();
16638 else if (! s->options.noreorder && mips_opts.noreorder)
16641 mips_opts = s->options;
16642 mips_opts_stack = s->next;
16646 else if (strcmp (name, "sym32") == 0)
16647 mips_opts.sym32 = TRUE;
16648 else if (strcmp (name, "nosym32") == 0)
16649 mips_opts.sym32 = FALSE;
16650 else if (strchr (name, ','))
16652 /* Generic ".set" directive; use the generic handler. */
16653 *input_line_pointer = ch;
16654 input_line_pointer = name;
16660 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16662 *input_line_pointer = ch;
16663 demand_empty_rest_of_line ();
16666 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16667 .option pic2. It means to generate SVR4 PIC calls. */
16670 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16672 mips_pic = SVR4_PIC;
16673 mips_abicalls = TRUE;
16675 if (g_switch_seen && g_switch_value != 0)
16676 as_warn (_("-G may not be used with SVR4 PIC code"));
16677 g_switch_value = 0;
16679 bfd_set_gp_size (stdoutput, 0);
16680 demand_empty_rest_of_line ();
16683 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16684 PIC code. It sets the $gp register for the function based on the
16685 function address, which is in the register named in the argument.
16686 This uses a relocation against _gp_disp, which is handled specially
16687 by the linker. The result is:
16688 lui $gp,%hi(_gp_disp)
16689 addiu $gp,$gp,%lo(_gp_disp)
16690 addu $gp,$gp,.cpload argument
16691 The .cpload argument is normally $25 == $t9.
16693 The -mno-shared option changes this to:
16694 lui $gp,%hi(__gnu_local_gp)
16695 addiu $gp,$gp,%lo(__gnu_local_gp)
16696 and the argument is ignored. This saves an instruction, but the
16697 resulting code is not position independent; it uses an absolute
16698 address for __gnu_local_gp. Thus code assembled with -mno-shared
16699 can go into an ordinary executable, but not into a shared library. */
16702 s_cpload (int ignore ATTRIBUTE_UNUSED)
16708 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16709 .cpload is ignored. */
16710 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16716 if (mips_opts.mips16)
16718 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16719 ignore_rest_of_line ();
16723 /* .cpload should be in a .set noreorder section. */
16724 if (mips_opts.noreorder == 0)
16725 as_warn (_(".cpload not in noreorder section"));
16727 reg = tc_get_register (0);
16729 /* If we need to produce a 64-bit address, we are better off using
16730 the default instruction sequence. */
16731 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16733 ex.X_op = O_symbol;
16734 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16736 ex.X_op_symbol = NULL;
16737 ex.X_add_number = 0;
16739 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16740 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16742 mips_mark_labels ();
16743 mips_assembling_insn = TRUE;
16746 macro_build_lui (&ex, mips_gp_register);
16747 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16748 mips_gp_register, BFD_RELOC_LO16);
16750 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16751 mips_gp_register, reg);
16754 mips_assembling_insn = FALSE;
16755 demand_empty_rest_of_line ();
16758 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16759 .cpsetup $reg1, offset|$reg2, label
16761 If offset is given, this results in:
16762 sd $gp, offset($sp)
16763 lui $gp, %hi(%neg(%gp_rel(label)))
16764 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16765 daddu $gp, $gp, $reg1
16767 If $reg2 is given, this results in:
16768 daddu $reg2, $gp, $0
16769 lui $gp, %hi(%neg(%gp_rel(label)))
16770 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16771 daddu $gp, $gp, $reg1
16772 $reg1 is normally $25 == $t9.
16774 The -mno-shared option replaces the last three instructions with
16776 addiu $gp,$gp,%lo(_gp) */
16779 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16781 expressionS ex_off;
16782 expressionS ex_sym;
16785 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16786 We also need NewABI support. */
16787 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16793 if (mips_opts.mips16)
16795 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16796 ignore_rest_of_line ();
16800 reg1 = tc_get_register (0);
16801 SKIP_WHITESPACE ();
16802 if (*input_line_pointer != ',')
16804 as_bad (_("missing argument separator ',' for .cpsetup"));
16808 ++input_line_pointer;
16809 SKIP_WHITESPACE ();
16810 if (*input_line_pointer == '$')
16812 mips_cpreturn_register = tc_get_register (0);
16813 mips_cpreturn_offset = -1;
16817 mips_cpreturn_offset = get_absolute_expression ();
16818 mips_cpreturn_register = -1;
16820 SKIP_WHITESPACE ();
16821 if (*input_line_pointer != ',')
16823 as_bad (_("missing argument separator ',' for .cpsetup"));
16827 ++input_line_pointer;
16828 SKIP_WHITESPACE ();
16829 expression (&ex_sym);
16831 mips_mark_labels ();
16832 mips_assembling_insn = TRUE;
16835 if (mips_cpreturn_register == -1)
16837 ex_off.X_op = O_constant;
16838 ex_off.X_add_symbol = NULL;
16839 ex_off.X_op_symbol = NULL;
16840 ex_off.X_add_number = mips_cpreturn_offset;
16842 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16843 BFD_RELOC_LO16, SP);
16846 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16847 mips_gp_register, 0);
16849 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16851 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16852 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16855 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16856 mips_gp_register, -1, BFD_RELOC_GPREL16,
16857 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16859 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16860 mips_gp_register, reg1);
16866 ex.X_op = O_symbol;
16867 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16868 ex.X_op_symbol = NULL;
16869 ex.X_add_number = 0;
16871 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16872 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16874 macro_build_lui (&ex, mips_gp_register);
16875 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16876 mips_gp_register, BFD_RELOC_LO16);
16881 mips_assembling_insn = FALSE;
16882 demand_empty_rest_of_line ();
16886 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16888 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16889 .cplocal is ignored. */
16890 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16896 if (mips_opts.mips16)
16898 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16899 ignore_rest_of_line ();
16903 mips_gp_register = tc_get_register (0);
16904 demand_empty_rest_of_line ();
16907 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16908 offset from $sp. The offset is remembered, and after making a PIC
16909 call $gp is restored from that location. */
16912 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16916 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16917 .cprestore is ignored. */
16918 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16924 if (mips_opts.mips16)
16926 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16927 ignore_rest_of_line ();
16931 mips_cprestore_offset = get_absolute_expression ();
16932 mips_cprestore_valid = 1;
16934 ex.X_op = O_constant;
16935 ex.X_add_symbol = NULL;
16936 ex.X_op_symbol = NULL;
16937 ex.X_add_number = mips_cprestore_offset;
16939 mips_mark_labels ();
16940 mips_assembling_insn = TRUE;
16943 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16944 SP, HAVE_64BIT_ADDRESSES);
16947 mips_assembling_insn = FALSE;
16948 demand_empty_rest_of_line ();
16951 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16952 was given in the preceding .cpsetup, it results in:
16953 ld $gp, offset($sp)
16955 If a register $reg2 was given there, it results in:
16956 daddu $gp, $reg2, $0 */
16959 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16963 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16964 We also need NewABI support. */
16965 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16971 if (mips_opts.mips16)
16973 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16974 ignore_rest_of_line ();
16978 mips_mark_labels ();
16979 mips_assembling_insn = TRUE;
16982 if (mips_cpreturn_register == -1)
16984 ex.X_op = O_constant;
16985 ex.X_add_symbol = NULL;
16986 ex.X_op_symbol = NULL;
16987 ex.X_add_number = mips_cpreturn_offset;
16989 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16992 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16993 mips_cpreturn_register, 0);
16996 mips_assembling_insn = FALSE;
16997 demand_empty_rest_of_line ();
17000 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17001 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17002 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17003 debug information or MIPS16 TLS. */
17006 s_tls_rel_directive (const size_t bytes, const char *dirstr,
17007 bfd_reloc_code_real_type rtype)
17014 if (ex.X_op != O_symbol)
17016 as_bad (_("Unsupported use of %s"), dirstr);
17017 ignore_rest_of_line ();
17020 p = frag_more (bytes);
17021 md_number_to_chars (p, 0, bytes);
17022 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
17023 demand_empty_rest_of_line ();
17024 mips_clear_insn_labels ();
17027 /* Handle .dtprelword. */
17030 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
17032 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
17035 /* Handle .dtpreldword. */
17038 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
17040 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
17043 /* Handle .tprelword. */
17046 s_tprelword (int ignore ATTRIBUTE_UNUSED)
17048 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
17051 /* Handle .tpreldword. */
17054 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17056 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17059 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17060 code. It sets the offset to use in gp_rel relocations. */
17063 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17065 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17066 We also need NewABI support. */
17067 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17073 mips_gprel_offset = get_absolute_expression ();
17075 demand_empty_rest_of_line ();
17078 /* Handle the .gpword pseudo-op. This is used when generating PIC
17079 code. It generates a 32 bit GP relative reloc. */
17082 s_gpword (int ignore ATTRIBUTE_UNUSED)
17084 segment_info_type *si;
17085 struct insn_label_list *l;
17089 /* When not generating PIC code, this is treated as .word. */
17090 if (mips_pic != SVR4_PIC)
17096 si = seg_info (now_seg);
17097 l = si->label_list;
17098 mips_emit_delays ();
17100 mips_align (2, 0, l);
17103 mips_clear_insn_labels ();
17105 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17107 as_bad (_("Unsupported use of .gpword"));
17108 ignore_rest_of_line ();
17112 md_number_to_chars (p, 0, 4);
17113 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17114 BFD_RELOC_GPREL32);
17116 demand_empty_rest_of_line ();
17120 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17122 segment_info_type *si;
17123 struct insn_label_list *l;
17127 /* When not generating PIC code, this is treated as .dword. */
17128 if (mips_pic != SVR4_PIC)
17134 si = seg_info (now_seg);
17135 l = si->label_list;
17136 mips_emit_delays ();
17138 mips_align (3, 0, l);
17141 mips_clear_insn_labels ();
17143 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17145 as_bad (_("Unsupported use of .gpdword"));
17146 ignore_rest_of_line ();
17150 md_number_to_chars (p, 0, 8);
17151 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17152 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17154 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17155 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17156 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17158 demand_empty_rest_of_line ();
17161 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17162 tables. It generates a R_MIPS_EH reloc. */
17165 s_ehword (int ignore ATTRIBUTE_UNUSED)
17170 mips_emit_delays ();
17173 mips_clear_insn_labels ();
17175 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17177 as_bad (_("Unsupported use of .ehword"));
17178 ignore_rest_of_line ();
17182 md_number_to_chars (p, 0, 4);
17183 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17184 BFD_RELOC_MIPS_EH);
17186 demand_empty_rest_of_line ();
17189 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17190 tables in SVR4 PIC code. */
17193 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17197 /* This is ignored when not generating SVR4 PIC code. */
17198 if (mips_pic != SVR4_PIC)
17204 mips_mark_labels ();
17205 mips_assembling_insn = TRUE;
17207 /* Add $gp to the register named as an argument. */
17209 reg = tc_get_register (0);
17210 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17213 mips_assembling_insn = FALSE;
17214 demand_empty_rest_of_line ();
17217 /* Handle the .insn pseudo-op. This marks instruction labels in
17218 mips16/micromips mode. This permits the linker to handle them specially,
17219 such as generating jalx instructions when needed. We also make
17220 them odd for the duration of the assembly, in order to generate the
17221 right sort of code. We will make them even in the adjust_symtab
17222 routine, while leaving them marked. This is convenient for the
17223 debugger and the disassembler. The linker knows to make them odd
17227 s_insn (int ignore ATTRIBUTE_UNUSED)
17229 mips_mark_labels ();
17231 demand_empty_rest_of_line ();
17234 /* Handle a .stab[snd] directive. Ideally these directives would be
17235 implemented in a transparent way, so that removing them would not
17236 have any effect on the generated instructions. However, s_stab
17237 internally changes the section, so in practice we need to decide
17238 now whether the preceding label marks compressed code. We do not
17239 support changing the compression mode of a label after a .stab*
17240 directive, such as in:
17246 so the current mode wins. */
17249 s_mips_stab (int type)
17251 mips_mark_labels ();
17255 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17258 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17265 name = input_line_pointer;
17266 c = get_symbol_end ();
17267 symbolP = symbol_find_or_make (name);
17268 S_SET_WEAK (symbolP);
17269 *input_line_pointer = c;
17271 SKIP_WHITESPACE ();
17273 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17275 if (S_IS_DEFINED (symbolP))
17277 as_bad (_("ignoring attempt to redefine symbol %s"),
17278 S_GET_NAME (symbolP));
17279 ignore_rest_of_line ();
17283 if (*input_line_pointer == ',')
17285 ++input_line_pointer;
17286 SKIP_WHITESPACE ();
17290 if (exp.X_op != O_symbol)
17292 as_bad (_("bad .weakext directive"));
17293 ignore_rest_of_line ();
17296 symbol_set_value_expression (symbolP, &exp);
17299 demand_empty_rest_of_line ();
17302 /* Parse a register string into a number. Called from the ECOFF code
17303 to parse .frame. The argument is non-zero if this is the frame
17304 register, so that we can record it in mips_frame_reg. */
17307 tc_get_register (int frame)
17311 SKIP_WHITESPACE ();
17312 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17316 mips_frame_reg = reg != 0 ? reg : SP;
17317 mips_frame_reg_valid = 1;
17318 mips_cprestore_valid = 0;
17324 md_section_align (asection *seg, valueT addr)
17326 int align = bfd_get_section_alignment (stdoutput, seg);
17330 /* We don't need to align ELF sections to the full alignment.
17331 However, Irix 5 may prefer that we align them at least to a 16
17332 byte boundary. We don't bother to align the sections if we
17333 are targeted for an embedded system. */
17334 if (strncmp (TARGET_OS, "elf", 3) == 0)
17340 return ((addr + (1 << align) - 1) & (-1 << align));
17343 /* Utility routine, called from above as well. If called while the
17344 input file is still being read, it's only an approximation. (For
17345 example, a symbol may later become defined which appeared to be
17346 undefined earlier.) */
17349 nopic_need_relax (symbolS *sym, int before_relaxing)
17354 if (g_switch_value > 0)
17356 const char *symname;
17359 /* Find out whether this symbol can be referenced off the $gp
17360 register. It can be if it is smaller than the -G size or if
17361 it is in the .sdata or .sbss section. Certain symbols can
17362 not be referenced off the $gp, although it appears as though
17364 symname = S_GET_NAME (sym);
17365 if (symname != (const char *) NULL
17366 && (strcmp (symname, "eprol") == 0
17367 || strcmp (symname, "etext") == 0
17368 || strcmp (symname, "_gp") == 0
17369 || strcmp (symname, "edata") == 0
17370 || strcmp (symname, "_fbss") == 0
17371 || strcmp (symname, "_fdata") == 0
17372 || strcmp (symname, "_ftext") == 0
17373 || strcmp (symname, "end") == 0
17374 || strcmp (symname, "_gp_disp") == 0))
17376 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17378 #ifndef NO_ECOFF_DEBUGGING
17379 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17380 && (symbol_get_obj (sym)->ecoff_extern_size
17381 <= g_switch_value))
17383 /* We must defer this decision until after the whole
17384 file has been read, since there might be a .extern
17385 after the first use of this symbol. */
17386 || (before_relaxing
17387 #ifndef NO_ECOFF_DEBUGGING
17388 && symbol_get_obj (sym)->ecoff_extern_size == 0
17390 && S_GET_VALUE (sym) == 0)
17391 || (S_GET_VALUE (sym) != 0
17392 && S_GET_VALUE (sym) <= g_switch_value)))
17396 const char *segname;
17398 segname = segment_name (S_GET_SEGMENT (sym));
17399 gas_assert (strcmp (segname, ".lit8") != 0
17400 && strcmp (segname, ".lit4") != 0);
17401 change = (strcmp (segname, ".sdata") != 0
17402 && strcmp (segname, ".sbss") != 0
17403 && strncmp (segname, ".sdata.", 7) != 0
17404 && strncmp (segname, ".sbss.", 6) != 0
17405 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17406 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17411 /* We are not optimizing for the $gp register. */
17416 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17419 pic_need_relax (symbolS *sym, asection *segtype)
17423 /* Handle the case of a symbol equated to another symbol. */
17424 while (symbol_equated_reloc_p (sym))
17428 /* It's possible to get a loop here in a badly written program. */
17429 n = symbol_get_value_expression (sym)->X_add_symbol;
17435 if (symbol_section_p (sym))
17438 symsec = S_GET_SEGMENT (sym);
17440 /* This must duplicate the test in adjust_reloc_syms. */
17441 return (!bfd_is_und_section (symsec)
17442 && !bfd_is_abs_section (symsec)
17443 && !bfd_is_com_section (symsec)
17444 && !s_is_linkonce (sym, segtype)
17446 /* A global or weak symbol is treated as external. */
17447 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17453 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17454 extended opcode. SEC is the section the frag is in. */
17457 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17460 const struct mips16_immed_operand *op;
17462 int mintiny, maxtiny;
17466 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17468 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17471 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17472 op = mips16_immed_operands;
17473 while (op->type != type)
17476 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17481 if (type == '<' || type == '>' || type == '[' || type == ']')
17484 maxtiny = 1 << op->nbits;
17489 maxtiny = (1 << op->nbits) - 1;
17494 mintiny = - (1 << (op->nbits - 1));
17495 maxtiny = (1 << (op->nbits - 1)) - 1;
17498 sym_frag = symbol_get_frag (fragp->fr_symbol);
17499 val = S_GET_VALUE (fragp->fr_symbol);
17500 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17506 /* We won't have the section when we are called from
17507 mips_relax_frag. However, we will always have been called
17508 from md_estimate_size_before_relax first. If this is a
17509 branch to a different section, we mark it as such. If SEC is
17510 NULL, and the frag is not marked, then it must be a branch to
17511 the same section. */
17514 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17519 /* Must have been called from md_estimate_size_before_relax. */
17522 fragp->fr_subtype =
17523 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17525 /* FIXME: We should support this, and let the linker
17526 catch branches and loads that are out of range. */
17527 as_bad_where (fragp->fr_file, fragp->fr_line,
17528 _("unsupported PC relative reference to different section"));
17532 if (fragp != sym_frag && sym_frag->fr_address == 0)
17533 /* Assume non-extended on the first relaxation pass.
17534 The address we have calculated will be bogus if this is
17535 a forward branch to another frag, as the forward frag
17536 will have fr_address == 0. */
17540 /* In this case, we know for sure that the symbol fragment is in
17541 the same section. If the relax_marker of the symbol fragment
17542 differs from the relax_marker of this fragment, we have not
17543 yet adjusted the symbol fragment fr_address. We want to add
17544 in STRETCH in order to get a better estimate of the address.
17545 This particularly matters because of the shift bits. */
17547 && sym_frag->relax_marker != fragp->relax_marker)
17551 /* Adjust stretch for any alignment frag. Note that if have
17552 been expanding the earlier code, the symbol may be
17553 defined in what appears to be an earlier frag. FIXME:
17554 This doesn't handle the fr_subtype field, which specifies
17555 a maximum number of bytes to skip when doing an
17557 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17559 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17562 stretch = - ((- stretch)
17563 & ~ ((1 << (int) f->fr_offset) - 1));
17565 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17574 addr = fragp->fr_address + fragp->fr_fix;
17576 /* The base address rules are complicated. The base address of
17577 a branch is the following instruction. The base address of a
17578 PC relative load or add is the instruction itself, but if it
17579 is in a delay slot (in which case it can not be extended) use
17580 the address of the instruction whose delay slot it is in. */
17581 if (type == 'p' || type == 'q')
17585 /* If we are currently assuming that this frag should be
17586 extended, then, the current address is two bytes
17588 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17591 /* Ignore the low bit in the target, since it will be set
17592 for a text label. */
17593 if ((val & 1) != 0)
17596 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17598 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17601 val -= addr & ~ ((1 << op->shift) - 1);
17603 /* Branch offsets have an implicit 0 in the lowest bit. */
17604 if (type == 'p' || type == 'q')
17607 /* If any of the shifted bits are set, we must use an extended
17608 opcode. If the address depends on the size of this
17609 instruction, this can lead to a loop, so we arrange to always
17610 use an extended opcode. We only check this when we are in
17611 the main relaxation loop, when SEC is NULL. */
17612 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17614 fragp->fr_subtype =
17615 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17619 /* If we are about to mark a frag as extended because the value
17620 is precisely maxtiny + 1, then there is a chance of an
17621 infinite loop as in the following code:
17626 In this case when the la is extended, foo is 0x3fc bytes
17627 away, so the la can be shrunk, but then foo is 0x400 away, so
17628 the la must be extended. To avoid this loop, we mark the
17629 frag as extended if it was small, and is about to become
17630 extended with a value of maxtiny + 1. */
17631 if (val == ((maxtiny + 1) << op->shift)
17632 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17635 fragp->fr_subtype =
17636 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17640 else if (symsec != absolute_section && sec != NULL)
17641 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17643 if ((val & ((1 << op->shift) - 1)) != 0
17644 || val < (mintiny << op->shift)
17645 || val > (maxtiny << op->shift))
17651 /* Compute the length of a branch sequence, and adjust the
17652 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17653 worst-case length is computed, with UPDATE being used to indicate
17654 whether an unconditional (-1), branch-likely (+1) or regular (0)
17655 branch is to be computed. */
17657 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17659 bfd_boolean toofar;
17663 && S_IS_DEFINED (fragp->fr_symbol)
17664 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17669 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17671 addr = fragp->fr_address + fragp->fr_fix + 4;
17675 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17678 /* If the symbol is not defined or it's in a different segment,
17679 assume the user knows what's going on and emit a short
17685 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17687 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17688 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17689 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17690 RELAX_BRANCH_LINK (fragp->fr_subtype),
17696 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17699 if (mips_pic != NO_PIC)
17701 /* Additional space for PIC loading of target address. */
17703 if (mips_opts.isa == ISA_MIPS1)
17704 /* Additional space for $at-stabilizing nop. */
17708 /* If branch is conditional. */
17709 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17716 /* Compute the length of a branch sequence, and adjust the
17717 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17718 worst-case length is computed, with UPDATE being used to indicate
17719 whether an unconditional (-1), or regular (0) branch is to be
17723 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17725 bfd_boolean toofar;
17729 && S_IS_DEFINED (fragp->fr_symbol)
17730 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17735 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17736 /* Ignore the low bit in the target, since it will be set
17737 for a text label. */
17738 if ((val & 1) != 0)
17741 addr = fragp->fr_address + fragp->fr_fix + 4;
17745 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17748 /* If the symbol is not defined or it's in a different segment,
17749 assume the user knows what's going on and emit a short
17755 if (fragp && update
17756 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17757 fragp->fr_subtype = (toofar
17758 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17759 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17764 bfd_boolean compact_known = fragp != NULL;
17765 bfd_boolean compact = FALSE;
17766 bfd_boolean uncond;
17769 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17771 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17773 uncond = update < 0;
17775 /* If label is out of range, we turn branch <br>:
17777 <br> label # 4 bytes
17783 nop # 2 bytes if compact && !PIC
17786 if (mips_pic == NO_PIC && (!compact_known || compact))
17789 /* If assembling PIC code, we further turn:
17795 lw/ld at, %got(label)(gp) # 4 bytes
17796 d/addiu at, %lo(label) # 4 bytes
17799 if (mips_pic != NO_PIC)
17802 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17804 <brneg> 0f # 4 bytes
17805 nop # 2 bytes if !compact
17808 length += (compact_known && compact) ? 4 : 6;
17814 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17815 bit accordingly. */
17818 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17820 bfd_boolean toofar;
17823 && S_IS_DEFINED (fragp->fr_symbol)
17824 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17830 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17831 /* Ignore the low bit in the target, since it will be set
17832 for a text label. */
17833 if ((val & 1) != 0)
17836 /* Assume this is a 2-byte branch. */
17837 addr = fragp->fr_address + fragp->fr_fix + 2;
17839 /* We try to avoid the infinite loop by not adding 2 more bytes for
17844 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17846 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17847 else if (type == 'E')
17848 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17853 /* If the symbol is not defined or it's in a different segment,
17854 we emit a normal 32-bit branch. */
17857 if (fragp && update
17858 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17860 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17861 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17869 /* Estimate the size of a frag before relaxing. Unless this is the
17870 mips16, we are not really relaxing here, and the final size is
17871 encoded in the subtype information. For the mips16, we have to
17872 decide whether we are using an extended opcode or not. */
17875 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17879 if (RELAX_BRANCH_P (fragp->fr_subtype))
17882 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17884 return fragp->fr_var;
17887 if (RELAX_MIPS16_P (fragp->fr_subtype))
17888 /* We don't want to modify the EXTENDED bit here; it might get us
17889 into infinite loops. We change it only in mips_relax_frag(). */
17890 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17892 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17896 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17897 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17898 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17899 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17900 fragp->fr_var = length;
17905 if (mips_pic == NO_PIC)
17906 change = nopic_need_relax (fragp->fr_symbol, 0);
17907 else if (mips_pic == SVR4_PIC)
17908 change = pic_need_relax (fragp->fr_symbol, segtype);
17909 else if (mips_pic == VXWORKS_PIC)
17910 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17917 fragp->fr_subtype |= RELAX_USE_SECOND;
17918 return -RELAX_FIRST (fragp->fr_subtype);
17921 return -RELAX_SECOND (fragp->fr_subtype);
17924 /* This is called to see whether a reloc against a defined symbol
17925 should be converted into a reloc against a section. */
17928 mips_fix_adjustable (fixS *fixp)
17930 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17931 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17934 if (fixp->fx_addsy == NULL)
17937 /* If symbol SYM is in a mergeable section, relocations of the form
17938 SYM + 0 can usually be made section-relative. The mergeable data
17939 is then identified by the section offset rather than by the symbol.
17941 However, if we're generating REL LO16 relocations, the offset is split
17942 between the LO16 and parterning high part relocation. The linker will
17943 need to recalculate the complete offset in order to correctly identify
17946 The linker has traditionally not looked for the parterning high part
17947 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17948 placed anywhere. Rather than break backwards compatibility by changing
17949 this, it seems better not to force the issue, and instead keep the
17950 original symbol. This will work with either linker behavior. */
17951 if ((lo16_reloc_p (fixp->fx_r_type)
17952 || reloc_needs_lo_p (fixp->fx_r_type))
17953 && HAVE_IN_PLACE_ADDENDS
17954 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17957 /* There is no place to store an in-place offset for JALR relocations.
17958 Likewise an in-range offset of limited PC-relative relocations may
17959 overflow the in-place relocatable field if recalculated against the
17960 start address of the symbol's containing section. */
17961 if (HAVE_IN_PLACE_ADDENDS
17962 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17963 || jalr_reloc_p (fixp->fx_r_type)))
17967 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17968 to a floating-point stub. The same is true for non-R_MIPS16_26
17969 relocations against MIPS16 functions; in this case, the stub becomes
17970 the function's canonical address.
17972 Floating-point stubs are stored in unique .mips16.call.* or
17973 .mips16.fn.* sections. If a stub T for function F is in section S,
17974 the first relocation in section S must be against F; this is how the
17975 linker determines the target function. All relocations that might
17976 resolve to T must also be against F. We therefore have the following
17977 restrictions, which are given in an intentionally-redundant way:
17979 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17982 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17983 if that stub might be used.
17985 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17988 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17989 that stub might be used.
17991 There is a further restriction:
17993 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17994 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17995 targets with in-place addends; the relocation field cannot
17996 encode the low bit.
17998 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17999 against a MIPS16 symbol. We deal with (5) by by not reducing any
18000 such relocations on REL targets.
18002 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18003 relocation against some symbol R, no relocation against R may be
18004 reduced. (Note that this deals with (2) as well as (1) because
18005 relocations against global symbols will never be reduced on ELF
18006 targets.) This approach is a little simpler than trying to detect
18007 stub sections, and gives the "all or nothing" per-symbol consistency
18008 that we have for MIPS16 symbols. */
18010 && fixp->fx_subsy == NULL
18011 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18012 || *symbol_get_tc (fixp->fx_addsy)
18013 || (HAVE_IN_PLACE_ADDENDS
18014 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18015 && jmp_reloc_p (fixp->fx_r_type))))
18022 /* Translate internal representation of relocation info to BFD target
18026 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18028 static arelent *retval[4];
18030 bfd_reloc_code_real_type code;
18032 memset (retval, 0, sizeof(retval));
18033 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
18034 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
18035 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18036 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18038 if (fixp->fx_pcrel)
18040 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18041 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18042 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18043 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18044 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18046 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18047 Relocations want only the symbol offset. */
18048 reloc->addend = fixp->fx_addnumber + reloc->address;
18051 /* A gruesome hack which is a result of the gruesome gas
18052 reloc handling. What's worse, for COFF (as opposed to
18053 ECOFF), we might need yet another copy of reloc->address.
18054 See bfd_install_relocation. */
18055 reloc->addend += reloc->address;
18059 reloc->addend = fixp->fx_addnumber;
18061 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18062 entry to be used in the relocation's section offset. */
18063 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18065 reloc->address = reloc->addend;
18069 code = fixp->fx_r_type;
18071 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18072 if (reloc->howto == NULL)
18074 as_bad_where (fixp->fx_file, fixp->fx_line,
18075 _("Can not represent %s relocation in this object file format"),
18076 bfd_get_reloc_code_name (code));
18083 /* Relax a machine dependent frag. This returns the amount by which
18084 the current size of the frag should change. */
18087 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18089 if (RELAX_BRANCH_P (fragp->fr_subtype))
18091 offsetT old_var = fragp->fr_var;
18093 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18095 return fragp->fr_var - old_var;
18098 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18100 offsetT old_var = fragp->fr_var;
18101 offsetT new_var = 4;
18103 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18104 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18105 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18106 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18107 fragp->fr_var = new_var;
18109 return new_var - old_var;
18112 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18115 if (mips16_extended_frag (fragp, NULL, stretch))
18117 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18119 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18124 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18126 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18133 /* Convert a machine dependent frag. */
18136 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18138 if (RELAX_BRANCH_P (fragp->fr_subtype))
18141 unsigned long insn;
18145 buf = fragp->fr_literal + fragp->fr_fix;
18146 insn = read_insn (buf);
18148 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18150 /* We generate a fixup instead of applying it right now
18151 because, if there are linker relaxations, we're going to
18152 need the relocations. */
18153 exp.X_op = O_symbol;
18154 exp.X_add_symbol = fragp->fr_symbol;
18155 exp.X_add_number = fragp->fr_offset;
18157 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18158 BFD_RELOC_16_PCREL_S2);
18159 fixp->fx_file = fragp->fr_file;
18160 fixp->fx_line = fragp->fr_line;
18162 buf = write_insn (buf, insn);
18168 as_warn_where (fragp->fr_file, fragp->fr_line,
18169 _("Relaxed out-of-range branch into a jump"));
18171 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18174 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18176 /* Reverse the branch. */
18177 switch ((insn >> 28) & 0xf)
18180 /* bc[0-3][tf]l? instructions can have the condition
18181 reversed by tweaking a single TF bit, and their
18182 opcodes all have 0x4???????. */
18183 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18184 insn ^= 0x00010000;
18188 /* bltz 0x04000000 bgez 0x04010000
18189 bltzal 0x04100000 bgezal 0x04110000 */
18190 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18191 insn ^= 0x00010000;
18195 /* beq 0x10000000 bne 0x14000000
18196 blez 0x18000000 bgtz 0x1c000000 */
18197 insn ^= 0x04000000;
18205 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18207 /* Clear the and-link bit. */
18208 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18210 /* bltzal 0x04100000 bgezal 0x04110000
18211 bltzall 0x04120000 bgezall 0x04130000 */
18212 insn &= ~0x00100000;
18215 /* Branch over the branch (if the branch was likely) or the
18216 full jump (not likely case). Compute the offset from the
18217 current instruction to branch to. */
18218 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18222 /* How many bytes in instructions we've already emitted? */
18223 i = buf - fragp->fr_literal - fragp->fr_fix;
18224 /* How many bytes in instructions from here to the end? */
18225 i = fragp->fr_var - i;
18227 /* Convert to instruction count. */
18229 /* Branch counts from the next instruction. */
18232 /* Branch over the jump. */
18233 buf = write_insn (buf, insn);
18236 buf = write_insn (buf, 0);
18238 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18240 /* beql $0, $0, 2f */
18242 /* Compute the PC offset from the current instruction to
18243 the end of the variable frag. */
18244 /* How many bytes in instructions we've already emitted? */
18245 i = buf - fragp->fr_literal - fragp->fr_fix;
18246 /* How many bytes in instructions from here to the end? */
18247 i = fragp->fr_var - i;
18248 /* Convert to instruction count. */
18250 /* Don't decrement i, because we want to branch over the
18254 buf = write_insn (buf, insn);
18255 buf = write_insn (buf, 0);
18259 if (mips_pic == NO_PIC)
18262 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18263 ? 0x0c000000 : 0x08000000);
18264 exp.X_op = O_symbol;
18265 exp.X_add_symbol = fragp->fr_symbol;
18266 exp.X_add_number = fragp->fr_offset;
18268 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18269 FALSE, BFD_RELOC_MIPS_JMP);
18270 fixp->fx_file = fragp->fr_file;
18271 fixp->fx_line = fragp->fr_line;
18273 buf = write_insn (buf, insn);
18277 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18279 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18280 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18281 insn |= at << OP_SH_RT;
18282 exp.X_op = O_symbol;
18283 exp.X_add_symbol = fragp->fr_symbol;
18284 exp.X_add_number = fragp->fr_offset;
18286 if (fragp->fr_offset)
18288 exp.X_add_symbol = make_expr_symbol (&exp);
18289 exp.X_add_number = 0;
18292 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18293 FALSE, BFD_RELOC_MIPS_GOT16);
18294 fixp->fx_file = fragp->fr_file;
18295 fixp->fx_line = fragp->fr_line;
18297 buf = write_insn (buf, insn);
18299 if (mips_opts.isa == ISA_MIPS1)
18301 buf = write_insn (buf, 0);
18303 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18304 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18305 insn |= at << OP_SH_RS | at << OP_SH_RT;
18307 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18308 FALSE, BFD_RELOC_LO16);
18309 fixp->fx_file = fragp->fr_file;
18310 fixp->fx_line = fragp->fr_line;
18312 buf = write_insn (buf, insn);
18315 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18319 insn |= at << OP_SH_RS;
18321 buf = write_insn (buf, insn);
18325 fragp->fr_fix += fragp->fr_var;
18326 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18330 /* Relax microMIPS branches. */
18331 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18333 char *buf = fragp->fr_literal + fragp->fr_fix;
18334 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18335 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18336 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18337 bfd_boolean short_ds;
18338 unsigned long insn;
18342 exp.X_op = O_symbol;
18343 exp.X_add_symbol = fragp->fr_symbol;
18344 exp.X_add_number = fragp->fr_offset;
18346 fragp->fr_fix += fragp->fr_var;
18348 /* Handle 16-bit branches that fit or are forced to fit. */
18349 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18351 /* We generate a fixup instead of applying it right now,
18352 because if there is linker relaxation, we're going to
18353 need the relocations. */
18355 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18356 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18357 else if (type == 'E')
18358 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18359 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18363 fixp->fx_file = fragp->fr_file;
18364 fixp->fx_line = fragp->fr_line;
18366 /* These relocations can have an addend that won't fit in
18368 fixp->fx_no_overflow = 1;
18373 /* Handle 32-bit branches that fit or are forced to fit. */
18374 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18375 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18377 /* We generate a fixup instead of applying it right now,
18378 because if there is linker relaxation, we're going to
18379 need the relocations. */
18380 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18381 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18382 fixp->fx_file = fragp->fr_file;
18383 fixp->fx_line = fragp->fr_line;
18389 /* Relax 16-bit branches to 32-bit branches. */
18392 insn = read_compressed_insn (buf, 2);
18394 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18395 insn = 0x94000000; /* beq */
18396 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18398 unsigned long regno;
18400 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18401 regno = micromips_to_32_reg_d_map [regno];
18402 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18403 insn |= regno << MICROMIPSOP_SH_RS;
18408 /* Nothing else to do, just write it out. */
18409 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18410 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18412 buf = write_compressed_insn (buf, insn, 4);
18413 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18418 insn = read_compressed_insn (buf, 4);
18420 /* Relax 32-bit branches to a sequence of instructions. */
18421 as_warn_where (fragp->fr_file, fragp->fr_line,
18422 _("Relaxed out-of-range branch into a jump"));
18424 /* Set the short-delay-slot bit. */
18425 short_ds = al && (insn & 0x02000000) != 0;
18427 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18431 /* Reverse the branch. */
18432 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18433 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18434 insn ^= 0x20000000;
18435 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18436 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18437 || (insn & 0xffe00000) == 0x40800000 /* blez */
18438 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18439 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18440 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18441 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18442 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18443 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18444 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18445 insn ^= 0x00400000;
18446 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18447 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18448 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18449 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18450 insn ^= 0x00200000;
18456 /* Clear the and-link and short-delay-slot bits. */
18457 gas_assert ((insn & 0xfda00000) == 0x40200000);
18459 /* bltzal 0x40200000 bgezal 0x40600000 */
18460 /* bltzals 0x42200000 bgezals 0x42600000 */
18461 insn &= ~0x02200000;
18464 /* Make a label at the end for use with the branch. */
18465 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18466 micromips_label_inc ();
18467 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18469 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18473 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18474 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18475 fixp->fx_file = fragp->fr_file;
18476 fixp->fx_line = fragp->fr_line;
18478 /* Branch over the jump. */
18479 buf = write_compressed_insn (buf, insn, 4);
18482 buf = write_compressed_insn (buf, 0x0c00, 2);
18485 if (mips_pic == NO_PIC)
18487 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18489 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18490 insn = al ? jal : 0xd4000000;
18492 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18493 BFD_RELOC_MICROMIPS_JMP);
18494 fixp->fx_file = fragp->fr_file;
18495 fixp->fx_line = fragp->fr_line;
18497 buf = write_compressed_insn (buf, insn, 4);
18500 buf = write_compressed_insn (buf, 0x0c00, 2);
18504 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18505 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18506 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18508 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18509 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18510 insn |= at << MICROMIPSOP_SH_RT;
18512 if (exp.X_add_number)
18514 exp.X_add_symbol = make_expr_symbol (&exp);
18515 exp.X_add_number = 0;
18518 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18519 BFD_RELOC_MICROMIPS_GOT16);
18520 fixp->fx_file = fragp->fr_file;
18521 fixp->fx_line = fragp->fr_line;
18523 buf = write_compressed_insn (buf, insn, 4);
18525 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18526 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18527 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18529 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18530 BFD_RELOC_MICROMIPS_LO16);
18531 fixp->fx_file = fragp->fr_file;
18532 fixp->fx_line = fragp->fr_line;
18534 buf = write_compressed_insn (buf, insn, 4);
18536 /* jr/jrc/jalr/jalrs $at */
18537 insn = al ? jalr : jr;
18538 insn |= at << MICROMIPSOP_SH_MJ;
18540 buf = write_compressed_insn (buf, insn, 2);
18543 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18547 if (RELAX_MIPS16_P (fragp->fr_subtype))
18550 const struct mips16_immed_operand *op;
18553 unsigned int user_length, length;
18554 unsigned long insn;
18557 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18558 op = mips16_immed_operands;
18559 while (op->type != type)
18562 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18563 val = resolve_symbol_value (fragp->fr_symbol);
18568 addr = fragp->fr_address + fragp->fr_fix;
18570 /* The rules for the base address of a PC relative reloc are
18571 complicated; see mips16_extended_frag. */
18572 if (type == 'p' || type == 'q')
18577 /* Ignore the low bit in the target, since it will be
18578 set for a text label. */
18579 if ((val & 1) != 0)
18582 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18584 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18587 addr &= ~ (addressT) ((1 << op->shift) - 1);
18590 /* Make sure the section winds up with the alignment we have
18593 record_alignment (asec, op->shift);
18597 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18598 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18599 as_warn_where (fragp->fr_file, fragp->fr_line,
18600 _("extended instruction in delay slot"));
18602 buf = fragp->fr_literal + fragp->fr_fix;
18604 insn = read_compressed_insn (buf, 2);
18606 insn |= MIPS16_EXTEND;
18608 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18610 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18615 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18616 BFD_RELOC_UNUSED, val, user_length, &insn);
18618 length = (ext ? 4 : 2);
18619 gas_assert (mips16_opcode_length (insn) == length);
18620 write_compressed_insn (buf, insn, length);
18621 fragp->fr_fix += length;
18625 relax_substateT subtype = fragp->fr_subtype;
18626 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18627 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18631 first = RELAX_FIRST (subtype);
18632 second = RELAX_SECOND (subtype);
18633 fixp = (fixS *) fragp->fr_opcode;
18635 /* If the delay slot chosen does not match the size of the instruction,
18636 then emit a warning. */
18637 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18638 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18643 s = subtype & (RELAX_DELAY_SLOT_16BIT
18644 | RELAX_DELAY_SLOT_SIZE_FIRST
18645 | RELAX_DELAY_SLOT_SIZE_SECOND);
18646 msg = macro_warning (s);
18648 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18652 /* Possibly emit a warning if we've chosen the longer option. */
18653 if (use_second == second_longer)
18659 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18660 msg = macro_warning (s);
18662 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18666 /* Go through all the fixups for the first sequence. Disable them
18667 (by marking them as done) if we're going to use the second
18668 sequence instead. */
18670 && fixp->fx_frag == fragp
18671 && fixp->fx_where < fragp->fr_fix - second)
18673 if (subtype & RELAX_USE_SECOND)
18675 fixp = fixp->fx_next;
18678 /* Go through the fixups for the second sequence. Disable them if
18679 we're going to use the first sequence, otherwise adjust their
18680 addresses to account for the relaxation. */
18681 while (fixp && fixp->fx_frag == fragp)
18683 if (subtype & RELAX_USE_SECOND)
18684 fixp->fx_where -= first;
18687 fixp = fixp->fx_next;
18690 /* Now modify the frag contents. */
18691 if (subtype & RELAX_USE_SECOND)
18695 start = fragp->fr_literal + fragp->fr_fix - first - second;
18696 memmove (start, start + first, second);
18697 fragp->fr_fix -= first;
18700 fragp->fr_fix -= second;
18706 /* This function is called after the relocs have been generated.
18707 We've been storing mips16 text labels as odd. Here we convert them
18708 back to even for the convenience of the debugger. */
18711 mips_frob_file_after_relocs (void)
18714 unsigned int count, i;
18719 syms = bfd_get_outsymbols (stdoutput);
18720 count = bfd_get_symcount (stdoutput);
18721 for (i = 0; i < count; i++, syms++)
18722 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18723 && ((*syms)->value & 1) != 0)
18725 (*syms)->value &= ~1;
18726 /* If the symbol has an odd size, it was probably computed
18727 incorrectly, so adjust that as well. */
18728 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18729 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18735 /* This function is called whenever a label is defined, including fake
18736 labels instantiated off the dot special symbol. It is used when
18737 handling branch delays; if a branch has a label, we assume we cannot
18738 move it. This also bumps the value of the symbol by 1 in compressed
18742 mips_record_label (symbolS *sym)
18744 segment_info_type *si = seg_info (now_seg);
18745 struct insn_label_list *l;
18747 if (free_insn_labels == NULL)
18748 l = (struct insn_label_list *) xmalloc (sizeof *l);
18751 l = free_insn_labels;
18752 free_insn_labels = l->next;
18756 l->next = si->label_list;
18757 si->label_list = l;
18760 /* This function is called as tc_frob_label() whenever a label is defined
18761 and adds a DWARF-2 record we only want for true labels. */
18764 mips_define_label (symbolS *sym)
18766 mips_record_label (sym);
18768 dwarf2_emit_label (sym);
18772 /* This function is called by tc_new_dot_label whenever a new dot symbol
18776 mips_add_dot_label (symbolS *sym)
18778 mips_record_label (sym);
18779 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18780 mips_compressed_mark_label (sym);
18783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18785 /* Some special processing for a MIPS ELF file. */
18788 mips_elf_final_processing (void)
18790 /* Write out the register information. */
18791 if (mips_abi != N64_ABI)
18795 s.ri_gprmask = mips_gprmask;
18796 s.ri_cprmask[0] = mips_cprmask[0];
18797 s.ri_cprmask[1] = mips_cprmask[1];
18798 s.ri_cprmask[2] = mips_cprmask[2];
18799 s.ri_cprmask[3] = mips_cprmask[3];
18800 /* The gp_value field is set by the MIPS ELF backend. */
18802 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18803 ((Elf32_External_RegInfo *)
18804 mips_regmask_frag));
18808 Elf64_Internal_RegInfo s;
18810 s.ri_gprmask = mips_gprmask;
18812 s.ri_cprmask[0] = mips_cprmask[0];
18813 s.ri_cprmask[1] = mips_cprmask[1];
18814 s.ri_cprmask[2] = mips_cprmask[2];
18815 s.ri_cprmask[3] = mips_cprmask[3];
18816 /* The gp_value field is set by the MIPS ELF backend. */
18818 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18819 ((Elf64_External_RegInfo *)
18820 mips_regmask_frag));
18823 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18824 sort of BFD interface for this. */
18825 if (mips_any_noreorder)
18826 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18827 if (mips_pic != NO_PIC)
18829 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18830 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18833 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18835 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18836 defined at present; this might need to change in future. */
18837 if (file_ase_mips16)
18838 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18839 if (file_ase_micromips)
18840 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18841 #if 0 /* XXX FIXME */
18842 if (file_ase_mips3d)
18843 elf_elfheader (stdoutput)->e_flags |= ???;
18846 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18848 /* Set the MIPS ELF ABI flags. */
18849 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18850 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18851 else if (mips_abi == O64_ABI)
18852 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18853 else if (mips_abi == EABI_ABI)
18855 if (!file_mips_gp32)
18856 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18858 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18860 else if (mips_abi == N32_ABI)
18861 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18863 /* Nothing to do for N64_ABI. */
18865 if (mips_32bitmode)
18866 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18868 #if 0 /* XXX FIXME */
18869 /* 32 bit code with 64 bit FP registers. */
18870 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18871 elf_elfheader (stdoutput)->e_flags |= ???;
18875 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18877 typedef struct proc {
18879 symbolS *func_end_sym;
18880 unsigned long reg_mask;
18881 unsigned long reg_offset;
18882 unsigned long fpreg_mask;
18883 unsigned long fpreg_offset;
18884 unsigned long frame_offset;
18885 unsigned long frame_reg;
18886 unsigned long pc_reg;
18889 static procS cur_proc;
18890 static procS *cur_proc_ptr;
18891 static int numprocs;
18893 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18894 as "2", and a normal nop as "0". */
18896 #define NOP_OPCODE_MIPS 0
18897 #define NOP_OPCODE_MIPS16 1
18898 #define NOP_OPCODE_MICROMIPS 2
18901 mips_nop_opcode (void)
18903 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18904 return NOP_OPCODE_MICROMIPS;
18905 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18906 return NOP_OPCODE_MIPS16;
18908 return NOP_OPCODE_MIPS;
18911 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18912 32-bit microMIPS NOPs here (if applicable). */
18915 mips_handle_align (fragS *fragp)
18919 int bytes, size, excess;
18922 if (fragp->fr_type != rs_align_code)
18925 p = fragp->fr_literal + fragp->fr_fix;
18927 switch (nop_opcode)
18929 case NOP_OPCODE_MICROMIPS:
18930 opcode = micromips_nop32_insn.insn_opcode;
18933 case NOP_OPCODE_MIPS16:
18934 opcode = mips16_nop_insn.insn_opcode;
18937 case NOP_OPCODE_MIPS:
18939 opcode = nop_insn.insn_opcode;
18944 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18945 excess = bytes % size;
18947 /* Handle the leading part if we're not inserting a whole number of
18948 instructions, and make it the end of the fixed part of the frag.
18949 Try to fit in a short microMIPS NOP if applicable and possible,
18950 and use zeroes otherwise. */
18951 gas_assert (excess < 4);
18952 fragp->fr_fix += excess;
18957 /* Fall through. */
18959 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18961 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18965 /* Fall through. */
18968 /* Fall through. */
18973 md_number_to_chars (p, opcode, size);
18974 fragp->fr_var = size;
18978 md_obj_begin (void)
18985 /* Check for premature end, nesting errors, etc. */
18987 as_warn (_("missing .end at end of assembly"));
18996 if (*input_line_pointer == '-')
18998 ++input_line_pointer;
19001 if (!ISDIGIT (*input_line_pointer))
19002 as_bad (_("expected simple number"));
19003 if (input_line_pointer[0] == '0')
19005 if (input_line_pointer[1] == 'x')
19007 input_line_pointer += 2;
19008 while (ISXDIGIT (*input_line_pointer))
19011 val |= hex_value (*input_line_pointer++);
19013 return negative ? -val : val;
19017 ++input_line_pointer;
19018 while (ISDIGIT (*input_line_pointer))
19021 val |= *input_line_pointer++ - '0';
19023 return negative ? -val : val;
19026 if (!ISDIGIT (*input_line_pointer))
19028 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19029 *input_line_pointer, *input_line_pointer);
19030 as_warn (_("invalid number"));
19033 while (ISDIGIT (*input_line_pointer))
19036 val += *input_line_pointer++ - '0';
19038 return negative ? -val : val;
19041 /* The .file directive; just like the usual .file directive, but there
19042 is an initial number which is the ECOFF file index. In the non-ECOFF
19043 case .file implies DWARF-2. */
19046 s_mips_file (int x ATTRIBUTE_UNUSED)
19048 static int first_file_directive = 0;
19050 if (ECOFF_DEBUGGING)
19059 filename = dwarf2_directive_file (0);
19061 /* Versions of GCC up to 3.1 start files with a ".file"
19062 directive even for stabs output. Make sure that this
19063 ".file" is handled. Note that you need a version of GCC
19064 after 3.1 in order to support DWARF-2 on MIPS. */
19065 if (filename != NULL && ! first_file_directive)
19067 (void) new_logical_line (filename, -1);
19068 s_app_file_string (filename, 0);
19070 first_file_directive = 1;
19074 /* The .loc directive, implying DWARF-2. */
19077 s_mips_loc (int x ATTRIBUTE_UNUSED)
19079 if (!ECOFF_DEBUGGING)
19080 dwarf2_directive_loc (0);
19083 /* The .end directive. */
19086 s_mips_end (int x ATTRIBUTE_UNUSED)
19090 /* Following functions need their own .frame and .cprestore directives. */
19091 mips_frame_reg_valid = 0;
19092 mips_cprestore_valid = 0;
19094 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19097 demand_empty_rest_of_line ();
19102 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19103 as_warn (_(".end not in text section"));
19107 as_warn (_(".end directive without a preceding .ent directive."));
19108 demand_empty_rest_of_line ();
19114 gas_assert (S_GET_NAME (p));
19115 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19116 as_warn (_(".end symbol does not match .ent symbol."));
19118 if (debug_type == DEBUG_STABS)
19119 stabs_generate_asm_endfunc (S_GET_NAME (p),
19123 as_warn (_(".end directive missing or unknown symbol"));
19126 /* Create an expression to calculate the size of the function. */
19127 if (p && cur_proc_ptr)
19129 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19130 expressionS *exp = xmalloc (sizeof (expressionS));
19133 exp->X_op = O_subtract;
19134 exp->X_add_symbol = symbol_temp_new_now ();
19135 exp->X_op_symbol = p;
19136 exp->X_add_number = 0;
19138 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19141 /* Generate a .pdr section. */
19142 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
19144 segT saved_seg = now_seg;
19145 subsegT saved_subseg = now_subseg;
19149 #ifdef md_flush_pending_output
19150 md_flush_pending_output ();
19153 gas_assert (pdr_seg);
19154 subseg_set (pdr_seg, 0);
19156 /* Write the symbol. */
19157 exp.X_op = O_symbol;
19158 exp.X_add_symbol = p;
19159 exp.X_add_number = 0;
19160 emit_expr (&exp, 4);
19162 fragp = frag_more (7 * 4);
19164 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19165 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19166 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19167 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19168 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19169 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19170 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19172 subseg_set (saved_seg, saved_subseg);
19174 #endif /* OBJ_ELF */
19176 cur_proc_ptr = NULL;
19179 /* The .aent and .ent directives. */
19182 s_mips_ent (int aent)
19186 symbolP = get_symbol ();
19187 if (*input_line_pointer == ',')
19188 ++input_line_pointer;
19189 SKIP_WHITESPACE ();
19190 if (ISDIGIT (*input_line_pointer)
19191 || *input_line_pointer == '-')
19194 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19195 as_warn (_(".ent or .aent not in text section."));
19197 if (!aent && cur_proc_ptr)
19198 as_warn (_("missing .end"));
19202 /* This function needs its own .frame and .cprestore directives. */
19203 mips_frame_reg_valid = 0;
19204 mips_cprestore_valid = 0;
19206 cur_proc_ptr = &cur_proc;
19207 memset (cur_proc_ptr, '\0', sizeof (procS));
19209 cur_proc_ptr->func_sym = symbolP;
19213 if (debug_type == DEBUG_STABS)
19214 stabs_generate_asm_func (S_GET_NAME (symbolP),
19215 S_GET_NAME (symbolP));
19218 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19220 demand_empty_rest_of_line ();
19223 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19224 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19225 s_mips_frame is used so that we can set the PDR information correctly.
19226 We can't use the ecoff routines because they make reference to the ecoff
19227 symbol table (in the mdebug section). */
19230 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19233 if (IS_ELF && !ECOFF_DEBUGGING)
19237 if (cur_proc_ptr == (procS *) NULL)
19239 as_warn (_(".frame outside of .ent"));
19240 demand_empty_rest_of_line ();
19244 cur_proc_ptr->frame_reg = tc_get_register (1);
19246 SKIP_WHITESPACE ();
19247 if (*input_line_pointer++ != ','
19248 || get_absolute_expression_and_terminator (&val) != ',')
19250 as_warn (_("Bad .frame directive"));
19251 --input_line_pointer;
19252 demand_empty_rest_of_line ();
19256 cur_proc_ptr->frame_offset = val;
19257 cur_proc_ptr->pc_reg = tc_get_register (0);
19259 demand_empty_rest_of_line ();
19262 #endif /* OBJ_ELF */
19266 /* The .fmask and .mask directives. If the mdebug section is present
19267 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19268 embedded targets, s_mips_mask is used so that we can set the PDR
19269 information correctly. We can't use the ecoff routines because they
19270 make reference to the ecoff symbol table (in the mdebug section). */
19273 s_mips_mask (int reg_type)
19276 if (IS_ELF && !ECOFF_DEBUGGING)
19280 if (cur_proc_ptr == (procS *) NULL)
19282 as_warn (_(".mask/.fmask outside of .ent"));
19283 demand_empty_rest_of_line ();
19287 if (get_absolute_expression_and_terminator (&mask) != ',')
19289 as_warn (_("Bad .mask/.fmask directive"));
19290 --input_line_pointer;
19291 demand_empty_rest_of_line ();
19295 off = get_absolute_expression ();
19297 if (reg_type == 'F')
19299 cur_proc_ptr->fpreg_mask = mask;
19300 cur_proc_ptr->fpreg_offset = off;
19304 cur_proc_ptr->reg_mask = mask;
19305 cur_proc_ptr->reg_offset = off;
19308 demand_empty_rest_of_line ();
19311 #endif /* OBJ_ELF */
19312 s_ignore (reg_type);
19315 /* A table describing all the processors gas knows about. Names are
19316 matched in the order listed.
19318 To ease comparison, please keep this table in the same order as
19319 gcc's mips_cpu_info_table[]. */
19320 static const struct mips_cpu_info mips_cpu_info_table[] =
19322 /* Entries for generic ISAs */
19323 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19324 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19325 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19326 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19327 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19328 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19329 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19330 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19331 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19334 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19335 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19336 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19339 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19342 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19343 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19344 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19345 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19346 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19347 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19348 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19349 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19350 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19351 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19352 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19353 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19354 { "r5900", 0, ISA_MIPS3, CPU_R5900 },
19355 /* ST Microelectronics Loongson 2E and 2F cores */
19356 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19357 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19360 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19361 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19362 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19363 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19364 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19365 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19366 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19367 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19368 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19369 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19370 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19371 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19372 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19373 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19374 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19377 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19378 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19379 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19380 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19382 /* MIPS 32 Release 2 */
19383 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19384 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19385 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19386 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19387 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19388 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19389 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19390 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19391 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19392 ISA_MIPS32R2, CPU_MIPS32R2 },
19393 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19394 ISA_MIPS32R2, CPU_MIPS32R2 },
19395 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19396 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19397 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19398 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19399 /* Deprecated forms of the above. */
19400 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19401 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19402 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19403 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19404 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19405 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19406 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19407 /* Deprecated forms of the above. */
19408 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19409 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19410 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19411 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19412 ISA_MIPS32R2, CPU_MIPS32R2 },
19413 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19414 ISA_MIPS32R2, CPU_MIPS32R2 },
19415 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19416 ISA_MIPS32R2, CPU_MIPS32R2 },
19417 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19418 ISA_MIPS32R2, CPU_MIPS32R2 },
19419 /* Deprecated forms of the above. */
19420 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19421 ISA_MIPS32R2, CPU_MIPS32R2 },
19422 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19423 ISA_MIPS32R2, CPU_MIPS32R2 },
19424 /* 34Kn is a 34kc without DSP. */
19425 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19426 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19427 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19428 ISA_MIPS32R2, CPU_MIPS32R2 },
19429 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19430 ISA_MIPS32R2, CPU_MIPS32R2 },
19431 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19432 ISA_MIPS32R2, CPU_MIPS32R2 },
19433 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19434 ISA_MIPS32R2, CPU_MIPS32R2 },
19435 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19436 ISA_MIPS32R2, CPU_MIPS32R2 },
19437 /* Deprecated forms of the above. */
19438 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19439 ISA_MIPS32R2, CPU_MIPS32R2 },
19440 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19441 ISA_MIPS32R2, CPU_MIPS32R2 },
19442 /* 1004K cores are multiprocessor versions of the 34K. */
19443 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19444 ISA_MIPS32R2, CPU_MIPS32R2 },
19445 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19446 ISA_MIPS32R2, CPU_MIPS32R2 },
19447 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19448 ISA_MIPS32R2, CPU_MIPS32R2 },
19449 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19450 ISA_MIPS32R2, CPU_MIPS32R2 },
19453 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19454 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19455 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19456 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19458 /* Broadcom SB-1 CPU core */
19459 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19460 ISA_MIPS64, CPU_SB1 },
19461 /* Broadcom SB-1A CPU core */
19462 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19463 ISA_MIPS64, CPU_SB1 },
19465 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19467 /* MIPS 64 Release 2 */
19469 /* Cavium Networks Octeon CPU core */
19470 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19471 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19472 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19475 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19478 XLP is mostly like XLR, with the prominent exception that it is
19479 MIPS64R2 rather than MIPS64. */
19480 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19487 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19488 with a final "000" replaced by "k". Ignore case.
19490 Note: this function is shared between GCC and GAS. */
19493 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19495 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19496 given++, canonical++;
19498 return ((*given == 0 && *canonical == 0)
19499 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19503 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19504 CPU name. We've traditionally allowed a lot of variation here.
19506 Note: this function is shared between GCC and GAS. */
19509 mips_matching_cpu_name_p (const char *canonical, const char *given)
19511 /* First see if the name matches exactly, or with a final "000"
19512 turned into "k". */
19513 if (mips_strict_matching_cpu_name_p (canonical, given))
19516 /* If not, try comparing based on numerical designation alone.
19517 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19518 if (TOLOWER (*given) == 'r')
19520 if (!ISDIGIT (*given))
19523 /* Skip over some well-known prefixes in the canonical name,
19524 hoping to find a number there too. */
19525 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19527 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19529 else if (TOLOWER (canonical[0]) == 'r')
19532 return mips_strict_matching_cpu_name_p (canonical, given);
19536 /* Parse an option that takes the name of a processor as its argument.
19537 OPTION is the name of the option and CPU_STRING is the argument.
19538 Return the corresponding processor enumeration if the CPU_STRING is
19539 recognized, otherwise report an error and return null.
19541 A similar function exists in GCC. */
19543 static const struct mips_cpu_info *
19544 mips_parse_cpu (const char *option, const char *cpu_string)
19546 const struct mips_cpu_info *p;
19548 /* 'from-abi' selects the most compatible architecture for the given
19549 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19550 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19551 version. Look first at the -mgp options, if given, otherwise base
19552 the choice on MIPS_DEFAULT_64BIT.
19554 Treat NO_ABI like the EABIs. One reason to do this is that the
19555 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19556 architecture. This code picks MIPS I for 'mips' and MIPS III for
19557 'mips64', just as we did in the days before 'from-abi'. */
19558 if (strcasecmp (cpu_string, "from-abi") == 0)
19560 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19561 return mips_cpu_info_from_isa (ISA_MIPS1);
19563 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19564 return mips_cpu_info_from_isa (ISA_MIPS3);
19566 if (file_mips_gp32 >= 0)
19567 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19569 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19574 /* 'default' has traditionally been a no-op. Probably not very useful. */
19575 if (strcasecmp (cpu_string, "default") == 0)
19578 for (p = mips_cpu_info_table; p->name != 0; p++)
19579 if (mips_matching_cpu_name_p (p->name, cpu_string))
19582 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19586 /* Return the canonical processor information for ISA (a member of the
19587 ISA_MIPS* enumeration). */
19589 static const struct mips_cpu_info *
19590 mips_cpu_info_from_isa (int isa)
19594 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19595 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19596 && isa == mips_cpu_info_table[i].isa)
19597 return (&mips_cpu_info_table[i]);
19602 static const struct mips_cpu_info *
19603 mips_cpu_info_from_arch (int arch)
19607 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19608 if (arch == mips_cpu_info_table[i].cpu)
19609 return (&mips_cpu_info_table[i]);
19615 show (FILE *stream, const char *string, int *col_p, int *first_p)
19619 fprintf (stream, "%24s", "");
19624 fprintf (stream, ", ");
19628 if (*col_p + strlen (string) > 72)
19630 fprintf (stream, "\n%24s", "");
19634 fprintf (stream, "%s", string);
19635 *col_p += strlen (string);
19641 md_show_usage (FILE *stream)
19646 fprintf (stream, _("\
19648 -EB generate big endian output\n\
19649 -EL generate little endian output\n\
19650 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19651 -G NUM allow referencing objects up to NUM bytes\n\
19652 implicitly with the gp register [default 8]\n"));
19653 fprintf (stream, _("\
19654 -mips1 generate MIPS ISA I instructions\n\
19655 -mips2 generate MIPS ISA II instructions\n\
19656 -mips3 generate MIPS ISA III instructions\n\
19657 -mips4 generate MIPS ISA IV instructions\n\
19658 -mips5 generate MIPS ISA V instructions\n\
19659 -mips32 generate MIPS32 ISA instructions\n\
19660 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19661 -mips64 generate MIPS64 ISA instructions\n\
19662 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19663 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19667 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19668 show (stream, mips_cpu_info_table[i].name, &column, &first);
19669 show (stream, "from-abi", &column, &first);
19670 fputc ('\n', stream);
19672 fprintf (stream, _("\
19673 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19674 -no-mCPU don't generate code specific to CPU.\n\
19675 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19679 show (stream, "3900", &column, &first);
19680 show (stream, "4010", &column, &first);
19681 show (stream, "4100", &column, &first);
19682 show (stream, "4650", &column, &first);
19683 fputc ('\n', stream);
19685 fprintf (stream, _("\
19686 -mips16 generate mips16 instructions\n\
19687 -no-mips16 do not generate mips16 instructions\n"));
19688 fprintf (stream, _("\
19689 -mmicromips generate microMIPS instructions\n\
19690 -mno-micromips do not generate microMIPS instructions\n"));
19691 fprintf (stream, _("\
19692 -msmartmips generate smartmips instructions\n\
19693 -mno-smartmips do not generate smartmips instructions\n"));
19694 fprintf (stream, _("\
19695 -mdsp generate DSP instructions\n\
19696 -mno-dsp do not generate DSP instructions\n"));
19697 fprintf (stream, _("\
19698 -mdspr2 generate DSP R2 instructions\n\
19699 -mno-dspr2 do not generate DSP R2 instructions\n"));
19700 fprintf (stream, _("\
19701 -mmt generate MT instructions\n\
19702 -mno-mt do not generate MT instructions\n"));
19703 fprintf (stream, _("\
19704 -mmcu generate MCU instructions\n\
19705 -mno-mcu do not generate MCU instructions\n"));
19706 fprintf (stream, _("\
19707 -mvirt generate Virtualization instructions\n\
19708 -mno-virt do not generate Virtualization instructions\n"));
19709 fprintf (stream, _("\
19710 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19711 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19712 -mfix-vr4120 work around certain VR4120 errata\n\
19713 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19714 -mfix-24k insert a nop after ERET and DERET instructions\n\
19715 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19716 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19717 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19718 -msym32 assume all symbols have 32-bit values\n\
19719 -O0 remove unneeded NOPs, do not swap branches\n\
19720 -O remove unneeded NOPs and swap branches\n\
19721 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19722 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19723 fprintf (stream, _("\
19724 -mhard-float allow floating-point instructions\n\
19725 -msoft-float do not allow floating-point instructions\n\
19726 -msingle-float only allow 32-bit floating-point operations\n\
19727 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19728 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19729 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19732 fprintf (stream, _("\
19733 -KPIC, -call_shared generate SVR4 position independent code\n\
19734 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19735 -mvxworks-pic generate VxWorks position independent code\n\
19736 -non_shared do not generate code that can operate with DSOs\n\
19737 -xgot assume a 32 bit GOT\n\
19738 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19739 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19740 position dependent (non shared) code\n\
19741 -mabi=ABI create ABI conformant object file for:\n"));
19745 show (stream, "32", &column, &first);
19746 show (stream, "o64", &column, &first);
19747 show (stream, "n32", &column, &first);
19748 show (stream, "64", &column, &first);
19749 show (stream, "eabi", &column, &first);
19751 fputc ('\n', stream);
19753 fprintf (stream, _("\
19754 -32 create o32 ABI object file (default)\n\
19755 -n32 create n32 ABI object file\n\
19756 -64 create 64 ABI object file\n"));
19762 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19764 if (HAVE_64BIT_SYMBOLS)
19765 return dwarf2_format_64bit_irix;
19767 return dwarf2_format_32bit;
19772 mips_dwarf2_addr_size (void)
19774 if (HAVE_64BIT_OBJECTS)
19780 /* Standard calling conventions leave the CFA at SP on entry. */
19782 mips_cfi_frame_initial_instructions (void)
19784 cfi_add_CFA_def_cfa_register (SP);
19788 tc_mips_regname_to_dw2regnum (char *regname)
19790 unsigned int regnum = -1;
19793 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))