1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
112 struct label_line *next;
119 /* The list of labels. */
121 static struct label_line *labels;
123 /* The current label. */
125 static struct label_line *current_label;
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
138 /* Case `g' except when BCC68000 is applicable. */
140 /* Coprocessor branches. */
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
154 /* Not currently used? */
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 const char *m_operands;
163 unsigned long m_opcode;
167 struct m68k_incant *m_next;
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
197 #define cpu32_control_regs m68010_control_regs
199 static const enum m68k_register *control_regs;
201 /* internal form of a 68020 instruction */
205 const char *args; /* list of opcode info */
208 int numo; /* Number of shorts in opcode */
211 struct m68k_op operands[6];
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
216 int nfrag; /* Number of frags we have to produce */
219 int fragoff; /* Where in the current opcode the frag ends */
226 int nrel; /* Num of reloc strucs in use */
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
242 /* Whether this expression needs special pic relocation, and if
244 enum pic_relocation pic_reloc;
247 reloc[5]; /* Five is enough??? */
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
257 static struct m68k_it the_ins; /* the instruction being assembled */
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
264 /* Macros for adding things to the m68k_it struct */
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
268 /* Static functions. */
270 static void insop PARAMS ((int, struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
274 /* Like addword, but goes BEFORE general operands */
278 struct m68k_incant *opcode;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
294 add_fix (width, exp, pc_rel, pc_fix)
296 struct m68k_exp *exp;
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
325 add_frag (add, off, type)
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
337 (op (ex) != O_constant && op (ex) != O_big)
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
375 static int current_architecture;
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
396 { m68020, "68k", 1 },
397 { m68000, "68008", 1 },
398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
409 { m68060, "68ec060", 1 },
410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
416 { cpu32, "68340", 1 },
417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
423 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
440 relax_typeS md_relax_table[] =
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
495 const pseudo_typeS md_pseudo_table[] =
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
501 {"skip", s_space, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes, 0},
507 {"swbeg", s_ignore, 0},
509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
512 /* The following pseudo-ops are supported for MRI compatibility. */
514 {"comline", s_space, 1},
516 {"mask2", s_ignore, 0},
519 {"restore", s_restore, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
561 extern void obj_coff_section PARAMS ((int));
564 CONST pseudo_typeS mote_pseudo_table[] =
577 {"xdef", s_globl, 0},
579 {"align", s_align_bytes, 0},
581 {"align", s_align_ptwo, 0},
584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
599 extern char *input_line_pointer;
601 static char mklower_table[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table[256];
604 static char alt_notend_table[256];
606 (! (notend_table[(unsigned char) *s] \
608 && alt_notend_table[(unsigned char) s[1]])))
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
612 #ifdef NO_PCREL_RELOCS
615 make_pcrel_absolute(fixP, add_number)
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
636 as_fatal ("Unknown PC relative instruction");
641 #endif /* NO_PCREL_RELOCS */
644 tc_coff_fix2rtype (fixP)
647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
676 static bfd_reloc_code_real_type
677 get_reloc_code (size, pcrel, pic)
680 enum pic_relocation pic;
688 return BFD_RELOC_8_GOT_PCREL;
690 return BFD_RELOC_16_GOT_PCREL;
692 return BFD_RELOC_32_GOT_PCREL;
700 return BFD_RELOC_8_GOTOFF;
702 return BFD_RELOC_16_GOTOFF;
704 return BFD_RELOC_32_GOTOFF;
712 return BFD_RELOC_8_PLT_PCREL;
714 return BFD_RELOC_16_PLT_PCREL;
716 return BFD_RELOC_32_PLT_PCREL;
724 return BFD_RELOC_8_PLTOFF;
726 return BFD_RELOC_16_PLTOFF;
728 return BFD_RELOC_32_PLTOFF;
738 return BFD_RELOC_8_PCREL;
740 return BFD_RELOC_16_PCREL;
742 return BFD_RELOC_32_PCREL;
759 as_bad ("Can not do %d byte %s%srelocation", size,
760 pcrel ? "pc-relative " : "",
761 pic == pic_none ? "" : "pic ");
762 return BFD_RELOC_NONE;
765 /* Here we decide which fixups can be adjusted to make them relative
766 to the beginning of the section instead of the symbol. Basically
767 we need to make sure that the dynamic relocations are done
768 correctly, so in some cases we force the original symbol to be
771 tc_m68k_fix_adjustable (fixP)
774 /* Prevent all adjustments to global symbols. */
775 if (S_IS_EXTERNAL (fixP->fx_addsy))
778 /* adjust_reloc_syms doesn't know about the GOT */
779 switch (fixP->fx_r_type)
781 case BFD_RELOC_8_GOT_PCREL:
782 case BFD_RELOC_16_GOT_PCREL:
783 case BFD_RELOC_32_GOT_PCREL:
784 case BFD_RELOC_8_GOTOFF:
785 case BFD_RELOC_16_GOTOFF:
786 case BFD_RELOC_32_GOTOFF:
787 case BFD_RELOC_8_PLT_PCREL:
788 case BFD_RELOC_16_PLT_PCREL:
789 case BFD_RELOC_32_PLT_PCREL:
790 case BFD_RELOC_8_PLTOFF:
791 case BFD_RELOC_16_PLTOFF:
792 case BFD_RELOC_32_PLTOFF:
802 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
809 tc_gen_reloc (section, fixp)
814 bfd_reloc_code_real_type code;
819 if (fixp->fx_r_type != BFD_RELOC_NONE)
821 code = fixp->fx_r_type;
823 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
824 that fixup_segment converted a non-PC relative reloc into a
825 PC relative reloc. In such a case, we need to convert the
832 code = BFD_RELOC_8_PCREL;
835 code = BFD_RELOC_16_PCREL;
838 code = BFD_RELOC_32_PCREL;
840 case BFD_RELOC_8_PCREL:
841 case BFD_RELOC_16_PCREL:
842 case BFD_RELOC_32_PCREL:
843 case BFD_RELOC_8_GOT_PCREL:
844 case BFD_RELOC_16_GOT_PCREL:
845 case BFD_RELOC_32_GOT_PCREL:
846 case BFD_RELOC_8_GOTOFF:
847 case BFD_RELOC_16_GOTOFF:
848 case BFD_RELOC_32_GOTOFF:
849 case BFD_RELOC_8_PLT_PCREL:
850 case BFD_RELOC_16_PLT_PCREL:
851 case BFD_RELOC_32_PLT_PCREL:
852 case BFD_RELOC_8_PLTOFF:
853 case BFD_RELOC_16_PLTOFF:
854 case BFD_RELOC_32_PLTOFF:
857 as_bad_where (fixp->fx_file, fixp->fx_line,
858 "Cannot make %s relocation PC relative",
859 bfd_get_reloc_code_name (code));
865 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
866 switch (F (fixp->fx_size, fixp->fx_pcrel))
868 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
869 MAP (1, 0, BFD_RELOC_8);
870 MAP (2, 0, BFD_RELOC_16);
871 MAP (4, 0, BFD_RELOC_32);
872 MAP (1, 1, BFD_RELOC_8_PCREL);
873 MAP (2, 1, BFD_RELOC_16_PCREL);
874 MAP (4, 1, BFD_RELOC_32_PCREL);
882 reloc = (arelent *) xmalloc (sizeof (arelent));
883 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
884 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
887 reloc->addend = fixp->fx_addnumber;
892 reloc->addend = fixp->fx_addnumber;
894 reloc->addend = (section->vma
895 + (fixp->fx_pcrel_adjust == 64
896 ? -1 : fixp->fx_pcrel_adjust)
898 + md_pcrel_from (fixp));
901 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
902 assert (reloc->howto != 0);
907 #endif /* BFD_ASSEMBLER */
909 /* Handle of the OPCODE hash table. NULL means any use before
910 m68k_ip_begin() will crash. */
911 static struct hash_control *op_hash;
913 /* Assemble an m68k instruction. */
920 register struct m68k_op *opP;
921 register struct m68k_incant *opcode;
922 register const char *s;
923 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
924 char *pdot, *pdotmove;
925 enum m68k_size siz1, siz2;
929 LITTLENUM_TYPE words[6];
930 LITTLENUM_TYPE *wordp;
931 unsigned long ok_arch = 0;
933 if (*instring == ' ')
934 instring++; /* skip leading whitespace */
936 /* Scan up to end of operation-code, which MUST end in end-of-string
937 or exactly 1 space. */
939 for (p = instring; *p != '\0'; p++)
949 the_ins.error = "No operator";
953 /* p now points to the end of the opcode name, probably whitespace.
954 Make sure the name is null terminated by clobbering the
955 whitespace, look it up in the hash table, then fix it back.
956 Remove a dot, first, since the opcode tables have none. */
959 for (pdotmove = pdot; pdotmove < p; pdotmove++)
960 *pdotmove = pdotmove[1];
966 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
971 for (pdotmove = p; pdotmove > pdot; pdotmove--)
972 *pdotmove = pdotmove[-1];
979 the_ins.error = "Unknown operator";
983 /* found a legitimate opcode, start matching operands */
987 if (opcode->m_operands == 0)
989 char *old = input_line_pointer;
991 input_line_pointer = p;
992 /* Ahh - it's a motorola style psuedo op */
993 mote_pseudo_table[opcode->m_opnum].poc_handler
994 (mote_pseudo_table[opcode->m_opnum].poc_val);
995 input_line_pointer = old;
1001 if (flag_mri && opcode->m_opnum == 0)
1003 /* In MRI mode, random garbage is allowed after an instruction
1004 which accepts no operands. */
1005 the_ins.args = opcode->m_operands;
1006 the_ins.numargs = opcode->m_opnum;
1007 the_ins.numo = opcode->m_codenum;
1008 the_ins.opcode[0] = getone (opcode);
1009 the_ins.opcode[1] = gettwo (opcode);
1013 for (opP = &the_ins.operands[0]; *p; opP++)
1015 p = crack_operand (p, opP);
1019 the_ins.error = opP->error;
1024 opsfound = opP - &the_ins.operands[0];
1026 /* This ugly hack is to support the floating pt opcodes in their
1027 standard form. Essentially, we fake a first enty of type COP#1 */
1028 if (opcode->m_operands[0] == 'I')
1032 for (n = opsfound; n > 0; --n)
1033 the_ins.operands[n] = the_ins.operands[n - 1];
1035 memset ((char *) (&the_ins.operands[0]), '\0',
1036 sizeof (the_ins.operands[0]));
1037 the_ins.operands[0].mode = CONTROL;
1038 the_ins.operands[0].reg = m68k_float_copnum;
1042 /* We've got the operands. Find an opcode that'll accept them */
1045 /* If we didn't get the right number of ops, or we have no
1046 common model with this pattern then reject this pattern. */
1048 ok_arch |= opcode->m_arch;
1049 if (opsfound != opcode->m_opnum
1050 || ((opcode->m_arch & current_architecture) == 0))
1054 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1058 /* Warning: this switch is huge! */
1059 /* I've tried to organize the cases into this order:
1060 non-alpha first, then alpha by letter. Lower-case
1061 goes directly before uppercase counterpart. */
1062 /* Code with multiple case ...: gets sorted by the lowest
1063 case ... it belongs to. I hope this makes sense. */
1169 if (opP->reg == PC || opP->reg == ZPC)
1186 if (opP->reg == PC || opP->reg == ZPC)
1205 if (opP->reg == PC || opP->reg == ZPC)
1215 if (opP->mode != IMMED)
1217 else if (s[1] == 'b'
1218 && ! isvar (&opP->disp)
1219 && (opP->disp.exp.X_op != O_constant
1220 || ! isbyte (opP->disp.exp.X_add_number)))
1222 else if (s[1] == 'B'
1223 && ! isvar (&opP->disp)
1224 && (opP->disp.exp.X_op != O_constant
1225 || ! issbyte (opP->disp.exp.X_add_number)))
1227 else if (s[1] == 'w'
1228 && ! isvar (&opP->disp)
1229 && (opP->disp.exp.X_op != O_constant
1230 || ! isword (opP->disp.exp.X_add_number)))
1232 else if (s[1] == 'W'
1233 && ! isvar (&opP->disp)
1234 && (opP->disp.exp.X_op != O_constant
1235 || ! issword (opP->disp.exp.X_add_number)))
1241 if (opP->mode != IMMED)
1246 if (opP->mode == AREG
1247 || opP->mode == CONTROL
1248 || opP->mode == FPREG
1249 || opP->mode == IMMED
1250 || opP->mode == REGLST
1251 || (opP->mode != ABSL
1253 || opP->reg == ZPC)))
1258 if (opP->mode == CONTROL
1259 || opP->mode == FPREG
1260 || opP->mode == REGLST
1261 || opP->mode == IMMED
1262 || (opP->mode != ABSL
1264 || opP->reg == ZPC)))
1292 if (opP->mode == CONTROL
1293 || opP->mode == FPREG
1294 || opP->mode == REGLST)
1299 if (opP->mode != AINC)
1304 if (opP->mode != ADEC)
1354 if (opP->reg == PC || opP->reg == ZPC)
1375 case '~': /* For now! (JF FOO is this right?) */
1397 if (opP->mode != CONTROL
1398 || (opP->reg != TT0 && opP->reg != TT1))
1403 if (opP->mode != AREG)
1408 if (opP->mode != AINDR)
1413 if (opP->mode != ABSL
1415 && strncmp (instring, "jbsr", 4) == 0))
1420 if (opP->mode != CONTROL || opP->reg != CCR)
1425 if (opP->mode != DISP
1427 || opP->reg > ADDR7)
1432 if (opP->mode != DREG)
1437 if (opP->mode != FPREG)
1442 if (opP->mode != CONTROL
1449 if (opP->mode != CONTROL
1451 || opP->reg > last_movec_reg)
1455 const enum m68k_register *rp;
1456 for (rp = control_regs; *rp; rp++)
1457 if (*rp == opP->reg)
1465 if (opP->mode != IMMED)
1471 if (opP->mode == DREG
1472 || opP->mode == AREG
1473 || opP->mode == FPREG)
1482 opP->mask = 1 << (opP->reg - DATA0);
1485 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1488 opP->mask = 1 << (opP->reg - FP0 + 16);
1496 else if (opP->mode == CONTROL)
1505 opP->mask = 1 << 24;
1508 opP->mask = 1 << 25;
1511 opP->mask = 1 << 26;
1520 else if (opP->mode == ABSL
1521 && opP->disp.size == SIZE_UNSPEC
1522 && opP->disp.exp.X_op == O_constant)
1524 /* This is what the MRI REG pseudo-op generates. */
1526 opP->mask = opP->disp.exp.X_add_number;
1528 else if (opP->mode != REGLST)
1530 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1532 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1537 if (opP->mode != IMMED)
1539 else if (opP->disp.exp.X_op != O_constant
1540 || ! issbyte (opP->disp.exp.X_add_number))
1542 else if (! m68k_quick
1543 && instring[3] != 'q'
1544 && instring[4] != 'q')
1549 if (opP->mode != DREG
1550 && opP->mode != IMMED
1551 && opP->mode != ABSL)
1556 if (opP->mode != IMMED)
1558 else if (opP->disp.exp.X_op != O_constant
1559 || opP->disp.exp.X_add_number < 1
1560 || opP->disp.exp.X_add_number > 8)
1562 else if (! m68k_quick
1563 && (strncmp (instring, "add", 3) == 0
1564 || strncmp (instring, "sub", 3) == 0)
1565 && instring[3] != 'q')
1570 if (opP->mode != DREG && opP->mode != AREG)
1575 if (opP->mode != AINDR
1576 && (opP->mode != BASE
1578 && opP->reg != ZADDR0)
1579 || opP->disp.exp.X_op != O_absent
1580 || ((opP->index.reg < DATA0
1581 || opP->index.reg > DATA7)
1582 && (opP->index.reg < ADDR0
1583 || opP->index.reg > ADDR7))
1584 || opP->index.size != SIZE_UNSPEC
1585 || opP->index.scale != 1))
1590 if (opP->mode != CONTROL
1591 || ! (opP->reg == FPI
1593 || opP->reg == FPC))
1598 if (opP->mode != CONTROL || opP->reg != SR)
1603 if (opP->mode != IMMED)
1605 else if (opP->disp.exp.X_op != O_constant
1606 || opP->disp.exp.X_add_number < 0
1607 || opP->disp.exp.X_add_number > 7)
1612 if (opP->mode != CONTROL || opP->reg != USP)
1616 /* JF these are out of order. We could put them
1617 in order if we were willing to put up with
1618 bunches of #ifdef m68851s in the code.
1620 Don't forget that you need these operands
1621 to use 68030 MMU instructions. */
1623 /* Memory addressing mode used by pflushr */
1625 if (opP->mode == CONTROL
1626 || opP->mode == FPREG
1627 || opP->mode == DREG
1628 || opP->mode == AREG
1629 || opP->mode == REGLST)
1631 /* We should accept immediate operands, but they
1632 supposedly have to be quad word, and we don't
1633 handle that. I would like to see what a Motorola
1634 assembler does before doing something here. */
1635 if (opP->mode == IMMED)
1640 if (opP->mode != CONTROL
1641 || (opP->reg != SFC && opP->reg != DFC))
1646 if (opP->mode != CONTROL || opP->reg != TC)
1651 if (opP->mode != CONTROL || opP->reg != AC)
1656 if (opP->mode != CONTROL
1659 && opP->reg != SCC))
1664 if (opP->mode != CONTROL
1670 if (opP->mode != CONTROL
1673 && opP->reg != CRP))
1678 if (opP->mode != CONTROL
1679 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1680 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1685 if (opP->mode != CONTROL || opP->reg != PSR)
1690 if (opP->mode != CONTROL || opP->reg != PCSR)
1695 if (opP->mode != CONTROL
1702 } /* not a cache specifier. */
1706 if (opP->mode != ABSL)
1712 } /* switch on type of operand */
1716 } /* for each operand */
1717 } /* if immediately wrong */
1724 opcode = opcode->m_next;
1729 && !(ok_arch & current_architecture))
1734 "invalid instruction for this architecture; needs ");
1735 cp = buf + strlen (buf);
1739 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1742 strcpy (cp, "mmu (68030 or 68851)");
1745 strcpy (cp, "68020 or higher");
1748 strcpy (cp, "68000 or higher");
1751 strcpy (cp, "68010 or higher");
1755 int got_one = 0, idx;
1756 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1759 if ((archs[idx].arch & ok_arch)
1760 && ! archs[idx].alias)
1764 strcpy (cp, " or ");
1768 strcpy (cp, archs[idx].name);
1774 cp = xmalloc (strlen (buf) + 1);
1779 the_ins.error = "operands mismatch";
1781 } /* Fell off the end */
1786 /* now assemble it */
1788 the_ins.args = opcode->m_operands;
1789 the_ins.numargs = opcode->m_opnum;
1790 the_ins.numo = opcode->m_codenum;
1791 the_ins.opcode[0] = getone (opcode);
1792 the_ins.opcode[1] = gettwo (opcode);
1794 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1796 /* This switch is a doozy.
1797 Watch the first step; its a big one! */
1825 tmpreg = 0x3c; /* 7.4 */
1826 if (strchr ("bwl", s[1]))
1827 nextword = get_num (&opP->disp, 80);
1829 nextword = get_num (&opP->disp, 0);
1830 if (isvar (&opP->disp))
1831 add_fix (s[1], &opP->disp, 0, 0);
1835 if (!isbyte (nextword))
1836 opP->error = "operand out of range";
1841 if (!isword (nextword))
1842 opP->error = "operand out of range";
1847 if (!issword (nextword))
1848 opP->error = "operand out of range";
1853 addword (nextword >> 16);
1880 /* We gotta put out some float */
1881 if (op (&opP->disp) != O_big)
1886 /* Can other cases happen here? */
1887 if (op (&opP->disp) != O_constant)
1890 val = (valueT) offs (&opP->disp);
1894 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1895 val >>= LITTLENUM_NUMBER_OF_BITS;
1899 offs (&opP->disp) = gencnt;
1901 if (offs (&opP->disp) > 0)
1903 if (offs (&opP->disp) > baseo)
1905 as_warn ("Bignum too big for %c format; truncated",
1907 offs (&opP->disp) = baseo;
1909 baseo -= offs (&opP->disp);
1912 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1913 offs (&opP->disp)--;
1918 gen_to_words (words, baseo, (long) outro);
1919 for (wordp = words; baseo--; wordp++)
1923 tmpreg = opP->reg - DATA; /* 0.dreg */
1926 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1929 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1932 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1935 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1939 nextword = get_num (&opP->disp, 80);
1942 && ! isvar (&opP->disp)
1945 opP->disp.exp.X_op = O_symbol;
1946 #ifndef BFD_ASSEMBLER
1947 opP->disp.exp.X_add_symbol = &abs_symbol;
1949 opP->disp.exp.X_add_symbol =
1950 section_symbol (absolute_section);
1954 /* Force into index mode. Hope this works */
1956 /* We do the first bit for 32-bit displacements, and the
1957 second bit for 16 bit ones. It is possible that we
1958 should make the default be WORD instead of LONG, but
1959 I think that'd break GCC, so we put up with a little
1960 inefficiency for the sake of working output. */
1962 if (!issword (nextword)
1963 || (isvar (&opP->disp)
1964 && ((opP->disp.size == SIZE_UNSPEC
1965 && flag_short_refs == 0
1966 && cpu_of_arch (current_architecture) >= m68020)
1967 || opP->disp.size == SIZE_LONG)))
1969 if (cpu_of_arch (current_architecture) < m68020)
1971 "displacement too large for this architecture; needs 68020 or higher";
1973 tmpreg = 0x3B; /* 7.3 */
1975 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1976 if (isvar (&opP->disp))
1980 if (opP->disp.size == SIZE_LONG
1982 /* If the displacement needs pic
1983 relocation it cannot be relaxed. */
1984 || opP->disp.pic_reloc != pic_none
1989 add_fix ('l', &opP->disp, 1, 2);
1993 add_frag (adds (&opP->disp),
1995 TAB (PCLEA, SZ_UNDEF));
2002 add_fix ('l', &opP->disp, 0, 0);
2007 addword (nextword >> 16);
2012 tmpreg = 0x3A; /* 7.2 */
2014 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2016 if (isvar (&opP->disp))
2020 add_fix ('w', &opP->disp, 1, 0);
2023 add_fix ('w', &opP->disp, 0, 0);
2033 baseo = get_num (&opP->disp, 80);
2034 if (opP->mode == POST || opP->mode == PRE)
2035 outro = get_num (&opP->odisp, 80);
2036 /* Figure out the `addressing mode'.
2037 Also turn on the BASE_DISABLE bit, if needed. */
2038 if (opP->reg == PC || opP->reg == ZPC)
2040 tmpreg = 0x3b; /* 7.3 */
2041 if (opP->reg == ZPC)
2044 else if (opP->reg == 0)
2047 tmpreg = 0x30; /* 6.garbage */
2049 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2052 tmpreg = 0x30 + opP->reg - ZADDR0;
2055 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2057 siz1 = opP->disp.size;
2058 if (opP->mode == POST || opP->mode == PRE)
2059 siz2 = opP->odisp.size;
2063 /* Index register stuff */
2064 if (opP->index.reg != 0
2065 && opP->index.reg >= DATA
2066 && opP->index.reg <= ADDR7)
2068 nextword |= (opP->index.reg - DATA) << 12;
2070 if (opP->index.size == SIZE_LONG
2071 || (opP->index.size == SIZE_UNSPEC
2072 && m68k_index_width_default == SIZE_LONG))
2075 if ((opP->index.scale != 1
2076 && cpu_of_arch (current_architecture) < m68020)
2077 || (opP->index.scale == 8
2078 && current_architecture == mcf5200))
2081 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2084 switch (opP->index.scale)
2101 GET US OUT OF HERE! */
2103 /* Must be INDEX, with an index register. Address
2104 register cannot be ZERO-PC, and either :b was
2105 forced, or we know it will fit. For a 68000 or
2106 68010, force this mode anyways, because the
2107 larger modes aren't supported. */
2108 if (opP->mode == BASE
2109 && ((opP->reg >= ADDR0
2110 && opP->reg <= ADDR7)
2113 if (siz1 == SIZE_BYTE
2114 || cpu_of_arch (current_architecture) < m68020
2115 || (siz1 == SIZE_UNSPEC
2116 && ! isvar (&opP->disp)
2117 && issbyte (baseo)))
2119 nextword += baseo & 0xff;
2121 if (isvar (&opP->disp))
2123 /* Do a byte relocation. If it doesn't
2124 fit (possible on m68000) let the
2125 fixup processing complain later. */
2127 add_fix ('B', &opP->disp, 1, 1);
2129 add_fix ('B', &opP->disp, 0, 0);
2131 else if (siz1 != SIZE_BYTE)
2133 if (siz1 != SIZE_UNSPEC)
2134 as_warn ("Forcing byte displacement");
2135 if (! issbyte (baseo))
2136 opP->error = "byte displacement out of range";
2141 else if (siz1 == SIZE_UNSPEC
2143 && isvar (&opP->disp)
2144 && subs (&opP->disp) == NULL
2146 /* If the displacement needs pic
2147 relocation it cannot be relaxed. */
2148 && opP->disp.pic_reloc == pic_none
2152 /* The code in md_convert_frag_1 needs to be
2153 able to adjust nextword. Call frag_grow
2154 to ensure that we have enough space in
2155 the frag obstack to make all the bytes
2158 nextword += baseo & 0xff;
2160 add_frag (adds (&opP->disp), offs (&opP->disp),
2161 TAB (PCINDEX, SZ_UNDEF));
2169 nextword |= 0x40; /* No index reg */
2170 if (opP->index.reg >= ZDATA0
2171 && opP->index.reg <= ZDATA7)
2172 nextword |= (opP->index.reg - ZDATA0) << 12;
2173 else if (opP->index.reg >= ZADDR0
2174 || opP->index.reg <= ZADDR7)
2175 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2178 /* It isn't simple. */
2180 if (cpu_of_arch (current_architecture) < m68020)
2182 "invalid operand mode for this architecture; needs 68020 or higher";
2185 /* If the guy specified a width, we assume that it is
2186 wide enough. Maybe it isn't. If so, we lose. */
2190 if (isvar (&opP->disp)
2192 : ! issword (baseo))
2197 else if (! isvar (&opP->disp) && baseo == 0)
2206 as_warn (":b not permitted; defaulting to :w");
2216 /* Figure out innner displacement stuff */
2217 if (opP->mode == POST || opP->mode == PRE)
2219 if (cpu_of_arch (current_architecture) & cpu32)
2220 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2224 if (isvar (&opP->odisp)
2226 : ! issword (outro))
2231 else if (! isvar (&opP->odisp) && outro == 0)
2240 as_warn (":b not permitted; defaulting to :w");
2249 if (opP->mode == POST
2250 && (nextword & 0x40) == 0)
2255 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2257 if (opP->reg == PC || opP->reg == ZPC)
2258 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2260 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2262 if (siz1 == SIZE_LONG)
2263 addword (baseo >> 16);
2264 if (siz1 != SIZE_UNSPEC)
2267 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2268 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2269 if (siz2 == SIZE_LONG)
2270 addword (outro >> 16);
2271 if (siz2 != SIZE_UNSPEC)
2277 nextword = get_num (&opP->disp, 80);
2278 switch (opP->disp.size)
2283 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2285 tmpreg = 0x38; /* 7.0 */
2289 /* Don't generate pc relative code on 68010 and
2291 if (isvar (&opP->disp)
2292 && !subs (&opP->disp)
2293 && adds (&opP->disp)
2295 /* If the displacement needs pic relocation it
2296 cannot be relaxed. */
2297 && opP->disp.pic_reloc == pic_none
2299 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2300 && HAVE_LONG_BRANCH(current_architecture)
2302 && !strchr ("~%&$?", s[0]))
2304 tmpreg = 0x3A; /* 7.2 */
2305 add_frag (adds (&opP->disp),
2307 TAB (PCREL, SZ_UNDEF));
2310 /* Fall through into long */
2312 if (isvar (&opP->disp))
2313 add_fix ('l', &opP->disp, 0, 0);
2315 tmpreg = 0x39;/* 7.1 mode */
2316 addword (nextword >> 16);
2321 as_bad ("unsupported byte value; use a different suffix");
2323 case SIZE_WORD: /* Word */
2324 if (isvar (&opP->disp))
2325 add_fix ('w', &opP->disp, 0, 0);
2327 tmpreg = 0x38;/* 7.0 mode */
2335 as_bad ("unknown/incorrect operand");
2338 install_gen_operand (s[1], tmpreg);
2344 { /* JF: I hate floating point! */
2359 tmpreg = get_num (&opP->disp, tmpreg);
2360 if (isvar (&opP->disp))
2361 add_fix (s[1], &opP->disp, 0, 0);
2364 case 'b': /* Danger: These do no check for
2365 certain types of overflow.
2367 if (!isbyte (tmpreg))
2368 opP->error = "out of range";
2369 insop (tmpreg, opcode);
2370 if (isvar (&opP->disp))
2371 the_ins.reloc[the_ins.nrel - 1].n =
2372 (opcode->m_codenum) * 2 + 1;
2375 if (!issbyte (tmpreg))
2376 opP->error = "out of range";
2377 opcode->m_opcode |= tmpreg;
2378 if (isvar (&opP->disp))
2379 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2382 if (!isword (tmpreg))
2383 opP->error = "out of range";
2384 insop (tmpreg, opcode);
2385 if (isvar (&opP->disp))
2386 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2389 if (!issword (tmpreg))
2390 opP->error = "out of range";
2391 insop (tmpreg, opcode);
2392 if (isvar (&opP->disp))
2393 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2396 /* Because of the way insop works, we put these two out
2398 insop (tmpreg, opcode);
2399 insop (tmpreg >> 16, opcode);
2400 if (isvar (&opP->disp))
2401 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2408 install_operand (s[1], tmpreg);
2419 install_operand (s[1], opP->reg - ADDR);
2423 tmpreg = get_num (&opP->disp, 80);
2427 /* The pc_fix argument winds up in fx_pcrel_adjust,
2428 which is a char, and may therefore be unsigned. We
2429 want to pass -1, but we pass 64 instead, and convert
2430 back in md_pcrel_from. */
2431 add_fix ('B', &opP->disp, 1, 64);
2434 add_fix ('w', &opP->disp, 1, 0);
2439 if (!HAVE_LONG_BRANCH(current_architecture))
2440 as_warn ("Can't use long branches on 68000/68010/5200");
2441 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2442 add_fix ('l', &opP->disp, 1, 0);
2447 if (subs (&opP->disp)) /* We can't relax it */
2451 /* If the displacement needs pic relocation it cannot be
2453 if (opP->disp.pic_reloc != pic_none)
2457 /* This could either be a symbol, or an absolute
2458 address. No matter, the frag hacking will finger it
2459 out. Not quite: it can't switch from BRANCH to
2460 BCC68000 for the case where opnd is absolute (it
2461 needs to use the 68000 hack since no conditional abs
2463 if (( !HAVE_LONG_BRANCH(current_architecture)
2464 || (0 == adds (&opP->disp)))
2465 && (the_ins.opcode[0] >= 0x6200)
2466 && (the_ins.opcode[0] <= 0x6f00))
2467 add_frag (adds (&opP->disp), offs (&opP->disp),
2468 TAB (BCC68000, SZ_UNDEF));
2470 add_frag (adds (&opP->disp), offs (&opP->disp),
2471 TAB (ABRANCH, SZ_UNDEF));
2474 if (isvar (&opP->disp))
2477 /* check for DBcc instruction */
2478 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2480 /* size varies if patch */
2481 /* needed for long form */
2482 add_frag (adds (&opP->disp), offs (&opP->disp),
2483 TAB (DBCC, SZ_UNDEF));
2487 add_fix ('w', &opP->disp, 1, 0);
2491 case 'C': /* Fixed size LONG coproc branches */
2492 add_fix ('l', &opP->disp, 1, 0);
2496 case 'c': /* Var size Coprocesssor branches */
2497 if (subs (&opP->disp))
2499 add_fix ('l', &opP->disp, 1, 0);
2500 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2502 else if (adds (&opP->disp))
2503 add_frag (adds (&opP->disp), offs (&opP->disp),
2504 TAB (FBRANCH, SZ_UNDEF));
2507 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2508 TAB(FBRANCH,SHORT)); */
2509 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2510 add_fix ('l', &opP->disp, 1, 0);
2520 case 'C': /* Ignore it */
2523 case 'd': /* JF this is a kludge */
2524 install_operand ('s', opP->reg - ADDR);
2525 tmpreg = get_num (&opP->disp, 80);
2526 if (!issword (tmpreg))
2528 as_warn ("Expression out of range, using 0");
2535 install_operand (s[1], opP->reg - DATA);
2539 install_operand (s[1], opP->reg - FP0);
2543 tmpreg = opP->reg - COP0;
2544 install_operand (s[1], tmpreg);
2547 case 'J': /* JF foo */
2620 install_operand (s[1], tmpreg);
2624 tmpreg = get_num (&opP->disp, 55);
2625 install_operand (s[1], tmpreg & 0x7f);
2632 if (tmpreg & 0x7FF0000)
2633 as_bad ("Floating point register in register list");
2634 insop (reverse_16_bits (tmpreg), opcode);
2638 if (tmpreg & 0x700FFFF)
2639 as_bad ("Wrong register in floating-point reglist");
2640 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2648 if (tmpreg & 0x7FF0000)
2649 as_bad ("Floating point register in register list");
2650 insop (tmpreg, opcode);
2652 else if (s[1] == '8')
2654 if (tmpreg & 0x0FFFFFF)
2655 as_bad ("incorrect register in reglist");
2656 install_operand (s[1], tmpreg >> 24);
2660 if (tmpreg & 0x700FFFF)
2661 as_bad ("wrong register in floating-point reglist");
2663 install_operand (s[1], tmpreg >> 16);
2668 install_operand (s[1], get_num (&opP->disp, 60));
2672 tmpreg = ((opP->mode == DREG)
2673 ? 0x20 + opP->reg - DATA
2674 : (get_num (&opP->disp, 40) & 0x1F));
2675 install_operand (s[1], tmpreg);
2679 tmpreg = get_num (&opP->disp, 10);
2682 install_operand (s[1], tmpreg);
2686 /* This depends on the fact that ADDR registers are eight
2687 more than their corresponding DATA regs, so the result
2688 will have the ADDR_REG bit set */
2689 install_operand (s[1], opP->reg - DATA);
2693 if (opP->mode == AINDR)
2694 install_operand (s[1], opP->reg - DATA);
2696 install_operand (s[1], opP->index.reg - DATA);
2700 if (opP->reg == FPI)
2702 else if (opP->reg == FPS)
2704 else if (opP->reg == FPC)
2708 install_operand (s[1], tmpreg);
2711 case 'S': /* Ignore it */
2715 install_operand (s[1], get_num (&opP->disp, 30));
2718 case 'U': /* Ignore it */
2737 as_fatal ("failed sanity check");
2738 } /* switch on cache token */
2739 install_operand (s[1], tmpreg);
2742 /* JF: These are out of order, I fear. */
2755 install_operand (s[1], tmpreg);
2781 install_operand (s[1], tmpreg);
2785 if (opP->reg == VAL)
2804 install_operand (s[1], tmpreg);
2818 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2829 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2835 install_operand (s[1], tmpreg);
2838 know (opP->reg == PSR);
2841 know (opP->reg == PCSR);
2856 install_operand (s[1], tmpreg);
2859 tmpreg = get_num (&opP->disp, 20);
2860 install_operand (s[1], tmpreg);
2862 case '_': /* used only for move16 absolute 32-bit address */
2863 tmpreg = get_num (&opP->disp, 80);
2864 addword (tmpreg >> 16);
2865 addword (tmpreg & 0xFFFF);
2872 /* By the time whe get here (FINALLY) the_ins contains the complete
2873 instruction, ready to be emitted. . . */
2877 reverse_16_bits (in)
2883 static int mask[16] =
2885 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2886 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2888 for (n = 0; n < 16; n++)
2891 out |= mask[15 - n];
2894 } /* reverse_16_bits() */
2903 static int mask[8] =
2905 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2908 for (n = 0; n < 8; n++)
2914 } /* reverse_8_bits() */
2916 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2917 (that value is chosen in the frag_var call in md_assemble). TYPE
2918 is the subtype of the frag to be generated; its primary type is
2919 rs_machine_dependent.
2921 The TYPE parameter is also used by md_convert_frag_1 and
2922 md_estimate_size_before_relax. The appropriate type of fixup will
2923 be emitted by md_convert_frag_1.
2925 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2927 install_operand (mode, val)
2934 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2937 the_ins.opcode[0] |= val << 9;
2940 the_ins.opcode[1] |= val << 12;
2943 the_ins.opcode[1] |= val << 6;
2946 the_ins.opcode[1] |= val;
2949 the_ins.opcode[2] |= val << 12;
2952 the_ins.opcode[2] |= val << 6;
2955 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2956 three words long! */
2958 the_ins.opcode[2] |= val;
2961 the_ins.opcode[1] |= val << 7;
2964 the_ins.opcode[1] |= val << 10;
2968 the_ins.opcode[1] |= val << 5;
2973 the_ins.opcode[1] |= (val << 10) | (val << 7);
2976 the_ins.opcode[1] |= (val << 12) | val;
2979 the_ins.opcode[0] |= val = 0xff;
2982 the_ins.opcode[0] |= val << 9;
2985 the_ins.opcode[1] |= val;
2988 the_ins.opcode[1] |= val;
2989 the_ins.numo++; /* What a hack */
2992 the_ins.opcode[1] |= val << 4;
3000 the_ins.opcode[0] |= (val << 6);
3003 the_ins.opcode[1] = (val >> 16);
3004 the_ins.opcode[2] = val & 0xffff;
3008 as_fatal ("failed sanity check.");
3010 } /* install_operand() */
3013 install_gen_operand (mode, val)
3020 the_ins.opcode[0] |= val;
3023 /* This is a kludge!!! */
3024 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3033 the_ins.opcode[0] |= val;
3035 /* more stuff goes here */
3037 as_fatal ("failed sanity check.");
3039 } /* install_gen_operand() */
3042 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3043 * then deal with the bitfield hack.
3047 crack_operand (str, opP)
3049 register struct m68k_op *opP;
3051 register int parens;
3053 register char *beg_str;
3061 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3067 else if (*str == ')')
3071 opP->error = "Extra )";
3077 if (flag_mri && *str == '\'')
3078 inquote = ! inquote;
3080 if (!*str && parens)
3082 opP->error = "Missing )";
3087 if (m68k_ip_op (beg_str, opP) != 0)
3094 c = *++str; /* JF bitfield hack */
3099 as_bad ("Missing operand");
3104 /* This is the guts of the machine-dependent assembler. STR points to a
3105 machine dependent instruction. This function is supposed to emit
3106 the frags/bytes it assembles to.
3110 insert_reg (regname, regnum)
3111 const char *regname;
3117 #ifdef REGISTER_PREFIX
3118 if (!flag_reg_prefix_optional)
3120 buf[0] = REGISTER_PREFIX;
3121 strcpy (buf + 1, regname);
3126 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3127 &zero_address_frag));
3129 for (i = 0; regname[i]; i++)
3130 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3133 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3134 &zero_address_frag));
3143 static const struct init_entry init_table[] =
3198 /* control registers */
3199 { "sfc", SFC }, /* Source Function Code */
3201 { "dfc", DFC }, /* Destination Function Code */
3203 { "cacr", CACR }, /* Cache Control Register */
3204 { "caar", CAAR }, /* Cache Address Register */
3206 { "usp", USP }, /* User Stack Pointer */
3207 { "vbr", VBR }, /* Vector Base Register */
3208 { "msp", MSP }, /* Master Stack Pointer */
3209 { "isp", ISP }, /* Interrupt Stack Pointer */
3211 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3212 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3213 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3214 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3216 /* 68ec040 versions of same */
3217 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3218 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3219 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3220 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3222 /* mcf5200 versions of same. The ColdFire programmer's reference
3223 manual indicated that the order is 2,3,0,1, but Ken Rose
3224 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3225 { "acr0", ITT0 }, /* Access Control Unit 0 */
3226 { "acr1", ITT1 }, /* Access Control Unit 1 */
3227 { "acr2", DTT0 }, /* Access Control Unit 2 */
3228 { "acr3", DTT1 }, /* Access Control Unit 3 */
3230 { "tc", TC }, /* MMU Translation Control Register */
3233 { "mmusr", MMUSR }, /* MMU Status Register */
3234 { "srp", SRP }, /* User Root Pointer */
3235 { "urp", URP }, /* Supervisor Root Pointer */
3240 { "rombar", ROMBAR }, /* ROM Base Address Register */
3241 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3242 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3243 { "mbar", MBAR }, /* Module Base Address Register */
3244 /* end of control registers */
3278 /* 68ec030 versions of same */
3281 /* 68ec030 access control unit, identical to 030 MMU status reg */
3284 /* Suppressed data and address registers. */
3309 for (i = 0; init_table[i].name; i++)
3310 insert_reg (init_table[i].name, init_table[i].number);
3313 static int no_68851, no_68881;
3316 /* a.out machine type. Default to 68020. */
3317 int m68k_aout_machtype = 2;
3329 int shorts_this_frag;
3332 /* In MRI mode, the instruction and operands are separated by a
3333 space. Anything following the operands is a comment. The label
3334 has already been removed. */
3342 for (s = str; *s != '\0'; s++)
3344 if ((*s == ' ' || *s == '\t') && ! inquote)
3362 inquote = ! inquote;
3367 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3372 for (n = 0; n < the_ins.numargs; n++)
3373 if (the_ins.operands[n].error)
3375 er = the_ins.operands[n].error;
3381 as_bad ("%s -- statement `%s' ignored", er, str);
3385 /* If there is a current label, record that it marks an instruction. */
3386 if (current_label != NULL)
3388 current_label->text = 1;
3389 current_label = NULL;
3392 if (the_ins.nfrag == 0)
3394 /* No frag hacking involved; just put it out */
3395 toP = frag_more (2 * the_ins.numo);
3396 fromP = &the_ins.opcode[0];
3397 for (m = the_ins.numo; m; --m)
3399 md_number_to_chars (toP, (long) (*fromP), 2);
3403 /* put out symbol-dependent info */
3404 for (m = 0; m < the_ins.nrel; m++)
3406 switch (the_ins.reloc[m].wid)
3425 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3426 the_ins.reloc[m].wid);
3429 fixP = fix_new_exp (frag_now,
3430 ((toP - frag_now->fr_literal)
3431 - the_ins.numo * 2 + the_ins.reloc[m].n),
3433 &the_ins.reloc[m].exp,
3434 the_ins.reloc[m].pcrel,
3435 get_reloc_code (n, the_ins.reloc[m].pcrel,
3436 the_ins.reloc[m].pic_reloc));
3437 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3438 if (the_ins.reloc[m].wid == 'B')
3439 fixP->fx_signed = 1;
3444 /* There's some frag hacking */
3445 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3450 wid = 2 * the_ins.fragb[n].fragoff;
3452 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3453 toP = frag_more (wid);
3455 shorts_this_frag = 0;
3456 for (m = wid / 2; m; --m)
3458 md_number_to_chars (toP, (long) (*fromP), 2);
3463 for (m = 0; m < the_ins.nrel; m++)
3465 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3467 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3470 wid = the_ins.reloc[m].wid;
3473 the_ins.reloc[m].wid = 0;
3474 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3476 fixP = fix_new_exp (frag_now,
3477 ((toP - frag_now->fr_literal)
3478 - the_ins.numo * 2 + the_ins.reloc[m].n),
3480 &the_ins.reloc[m].exp,
3481 the_ins.reloc[m].pcrel,
3482 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3483 the_ins.reloc[m].pic_reloc));
3484 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3486 (void) frag_var (rs_machine_dependent, 10, 0,
3487 (relax_substateT) (the_ins.fragb[n].fragty),
3488 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3490 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3491 shorts_this_frag = 0;
3494 toP = frag_more (n * sizeof (short));
3497 md_number_to_chars (toP, (long) (*fromP), 2);
3503 for (m = 0; m < the_ins.nrel; m++)
3507 wid = the_ins.reloc[m].wid;
3510 the_ins.reloc[m].wid = 0;
3511 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3513 fixP = fix_new_exp (frag_now,
3514 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3515 - shorts_this_frag * 2),
3517 &the_ins.reloc[m].exp,
3518 the_ins.reloc[m].pcrel,
3519 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3520 the_ins.reloc[m].pic_reloc));
3521 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3529 * md_begin -- set up hash tables with 68000 instructions.
3530 * similar to what the vax assembler does. ---phr
3532 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3533 a copy of it at runtime, adding in the information we want but isn't
3534 there. I think it'd be better to have an awk script hack the table
3535 at compile time. Or even just xstr the table and use it as-is. But
3536 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3539 register const struct m68k_opcode *ins;
3540 register struct m68k_incant *hack, *slak;
3541 register const char *retval = 0; /* empty string, or error msg text */
3542 register unsigned int i;
3547 flag_reg_prefix_optional = 1;
3549 if (! m68k_rel32_from_cmdline)
3553 op_hash = hash_new ();
3555 obstack_begin (&robyn, 4000);
3556 for (i = 0; i < m68k_numopcodes; i++)
3558 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3561 ins = &m68k_opcodes[i];
3562 /* We *could* ignore insns that don't match our arch here
3563 but just leaving them out of the hash. */
3564 slak->m_operands = ins->args;
3565 slak->m_opnum = strlen (slak->m_operands) / 2;
3566 slak->m_arch = ins->arch;
3567 slak->m_opcode = ins->opcode;
3568 /* This is kludgey */
3569 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3570 if (i + 1 != m68k_numopcodes
3571 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3573 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3578 slak = slak->m_next;
3582 retval = hash_insert (op_hash, ins->name, (char *) hack);
3584 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3587 for (i = 0; i < m68k_numaliases; i++)
3589 const char *name = m68k_opcode_aliases[i].primary;
3590 const char *alias = m68k_opcode_aliases[i].alias;
3591 PTR val = hash_find (op_hash, name);
3593 as_fatal ("Internal Error: Can't find %s in hash table", name);
3594 retval = hash_insert (op_hash, alias, val);
3596 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3599 /* In MRI mode, all unsized branches are variable sized. Normally,
3600 they are word sized. */
3603 static struct m68k_opcode_alias mri_aliases[] =
3623 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3625 const char *name = mri_aliases[i].primary;
3626 const char *alias = mri_aliases[i].alias;
3627 PTR val = hash_find (op_hash, name);
3629 as_fatal ("Internal Error: Can't find %s in hash table", name);
3630 retval = hash_jam (op_hash, alias, val);
3632 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3636 for (i = 0; i < sizeof (mklower_table); i++)
3637 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3639 for (i = 0; i < sizeof (notend_table); i++)
3641 notend_table[i] = 0;
3642 alt_notend_table[i] = 0;
3644 notend_table[','] = 1;
3645 notend_table['{'] = 1;
3646 notend_table['}'] = 1;
3647 alt_notend_table['a'] = 1;
3648 alt_notend_table['A'] = 1;
3649 alt_notend_table['d'] = 1;
3650 alt_notend_table['D'] = 1;
3651 alt_notend_table['#'] = 1;
3652 alt_notend_table['&'] = 1;
3653 alt_notend_table['f'] = 1;
3654 alt_notend_table['F'] = 1;
3655 #ifdef REGISTER_PREFIX
3656 alt_notend_table[REGISTER_PREFIX] = 1;
3659 /* We need to put '(' in alt_notend_table to handle
3660 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3662 alt_notend_table['('] = 1;
3664 /* We need to put '@' in alt_notend_table to handle
3665 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3667 alt_notend_table['@'] = 1;
3669 /* We need to put digits in alt_notend_table to handle
3670 bfextu %d0{24:1},%d0
3672 alt_notend_table['0'] = 1;
3673 alt_notend_table['1'] = 1;
3674 alt_notend_table['2'] = 1;
3675 alt_notend_table['3'] = 1;
3676 alt_notend_table['4'] = 1;
3677 alt_notend_table['5'] = 1;
3678 alt_notend_table['6'] = 1;
3679 alt_notend_table['7'] = 1;
3680 alt_notend_table['8'] = 1;
3681 alt_notend_table['9'] = 1;
3683 #ifndef MIT_SYNTAX_ONLY
3684 /* Insert pseudo ops, these have to go into the opcode table since
3685 gas expects pseudo ops to start with a dot */
3688 while (mote_pseudo_table[n].poc_name)
3690 hack = (struct m68k_incant *)
3691 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3692 hash_insert (op_hash,
3693 mote_pseudo_table[n].poc_name, (char *) hack);
3694 hack->m_operands = 0;
3704 record_alignment (text_section, 2);
3705 record_alignment (data_section, 2);
3706 record_alignment (bss_section, 2);
3711 select_control_regs ()
3713 /* Note which set of "movec" control registers is available. */
3714 switch (cpu_of_arch (current_architecture))
3717 control_regs = m68000_control_regs;
3720 control_regs = m68010_control_regs;
3724 control_regs = m68020_control_regs;
3727 control_regs = m68040_control_regs;
3730 control_regs = m68060_control_regs;
3733 control_regs = cpu32_control_regs;
3736 control_regs = mcf5200_control_regs;
3744 m68k_init_after_args ()
3746 if (cpu_of_arch (current_architecture) == 0)
3749 const char *default_cpu = TARGET_CPU;
3751 if (*default_cpu == 'm')
3753 for (i = 0; i < n_archs; i++)
3754 if (strcasecmp (default_cpu, archs[i].name) == 0)
3758 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3759 current_architecture |= m68020;
3762 current_architecture |= archs[i].arch;
3764 /* Permit m68881 specification with all cpus; those that can't work
3765 with a coprocessor could be doing emulation. */
3766 if (current_architecture & m68851)
3768 if (current_architecture & m68040)
3770 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3773 /* What other incompatibilities could we check for? */
3775 /* Toss in some default assumptions about coprocessors. */
3777 && (cpu_of_arch (current_architecture)
3778 /* Can CPU32 have a 68881 coprocessor?? */
3779 & (m68020 | m68030 | cpu32)))
3781 current_architecture |= m68881;
3784 && (cpu_of_arch (current_architecture) & m68020up) != 0
3785 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3787 current_architecture |= m68851;
3789 if (no_68881 && (current_architecture & m68881))
3790 as_bad ("options for 68881 and no-68881 both given");
3791 if (no_68851 && (current_architecture & m68851))
3792 as_bad ("options for 68851 and no-68851 both given");
3795 /* Work out the magic number. This isn't very general. */
3796 if (current_architecture & m68000)
3797 m68k_aout_machtype = 0;
3798 else if (current_architecture & m68010)
3799 m68k_aout_machtype = 1;
3800 else if (current_architecture & m68020)
3801 m68k_aout_machtype = 2;
3803 m68k_aout_machtype = 2;
3806 /* Note which set of "movec" control registers is available. */
3807 select_control_regs ();
3809 if (cpu_of_arch (current_architecture) < m68020)
3810 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3813 /* This is called when a label is defined. */
3816 m68k_frob_label (sym)
3819 struct label_line *n;
3821 n = (struct label_line *) xmalloc (sizeof *n);
3824 as_where (&n->file, &n->line);
3830 /* This is called when a value that is not an instruction is emitted. */
3833 m68k_flush_pending_output ()
3835 current_label = NULL;
3838 /* This is called at the end of the assembly, when the final value of
3839 the label is known. We warn if this is a text symbol aligned at an
3843 m68k_frob_symbol (sym)
3846 if ((S_GET_VALUE (sym) & 1) != 0)
3848 struct label_line *l;
3850 for (l = labels; l != NULL; l = l->next)
3852 if (l->label == sym)
3855 as_warn_where (l->file, l->line,
3856 "text label `%s' aligned to odd boundary",
3864 /* This is called if we go in or out of MRI mode because of the .mri
3868 m68k_mri_mode_change (on)
3873 if (! flag_reg_prefix_optional)
3875 flag_reg_prefix_optional = 1;
3876 #ifdef REGISTER_PREFIX
3881 if (! m68k_rel32_from_cmdline)
3886 if (! reg_prefix_optional_seen)
3888 #ifdef REGISTER_PREFIX_OPTIONAL
3889 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3891 flag_reg_prefix_optional = 0;
3893 #ifdef REGISTER_PREFIX
3898 if (! m68k_rel32_from_cmdline)
3903 /* Equal to MAX_PRECISION in atof-ieee.c */
3904 #define MAX_LITTLENUMS 6
3906 /* Turn a string in input_line_pointer into a floating point constant
3907 of type type, and store the appropriate bytes in *litP. The number
3908 of LITTLENUMS emitted is stored in *sizeP . An error message is
3909 returned, or NULL on OK. */
3912 md_atof (type, litP, sizeP)
3918 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3919 LITTLENUM_TYPE *wordP;
3950 return "Bad call to MD_ATOF()";
3952 t = atof_ieee (input_line_pointer, type, words);
3954 input_line_pointer = t;
3956 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3957 for (wordP = words; prec--;)
3959 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3960 litP += sizeof (LITTLENUM_TYPE);
3966 md_number_to_chars (buf, val, n)
3971 number_to_chars_bigendian (buf, val, n);
3975 md_apply_fix_2 (fixP, val)
3979 addressT upper_limit;
3980 offsetT lower_limit;
3982 /* This is unnecessary but it convinces the native rs6000 compiler
3983 to generate the code we want. */
3984 char *buf = fixP->fx_frag->fr_literal;
3985 buf += fixP->fx_where;
3986 /* end ibm compiler workaround */
3988 if (val & 0x80000000)
3989 val |= ~(addressT)0x7fffffff;
3996 memset (buf, 0, fixP->fx_size);
3997 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4002 switch (fixP->fx_size)
4004 /* The cast to offsetT below are necessary to make code correct for
4005 machines where ints are smaller than offsetT */
4009 lower_limit = - (offsetT) 0x80;
4012 *buf++ = (val >> 8);
4014 upper_limit = 0x7fff;
4015 lower_limit = - (offsetT) 0x8000;
4018 *buf++ = (val >> 24);
4019 *buf++ = (val >> 16);
4020 *buf++ = (val >> 8);
4022 upper_limit = 0x7fffffff;
4023 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4026 BAD_CASE (fixP->fx_size);
4029 /* Fix up a negative reloc. */
4030 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4032 fixP->fx_addsy = fixP->fx_subsy;
4033 fixP->fx_subsy = NULL;
4037 /* For non-pc-relative values, it's conceivable we might get something
4038 like "0xff" for a byte field. So extend the upper part of the range
4039 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4040 so that we can do any range checking at all. */
4041 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4042 upper_limit = upper_limit * 2 + 1;
4044 if ((addressT) val > upper_limit
4045 && (val > 0 || val < lower_limit))
4046 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4048 /* A one byte PC-relative reloc means a short branch. We can't use
4049 a short branch with a value of 0 or -1, because those indicate
4050 different opcodes (branches with longer offsets). fixup_segment
4051 in write.c may have clobbered fx_pcrel, so we need to examine the
4054 #ifdef BFD_ASSEMBLER
4055 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4058 && fixP->fx_size == 1
4059 && (fixP->fx_addsy == NULL
4060 || S_IS_DEFINED (fixP->fx_addsy))
4061 && (val == 0 || val == -1))
4062 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4065 #ifdef BFD_ASSEMBLER
4067 md_apply_fix (fixP, valp)
4071 md_apply_fix_2 (fixP, (addressT) *valp);
4075 void md_apply_fix (fixP, val)
4079 md_apply_fix_2 (fixP, (addressT) val);
4083 /* *fragP has been relaxed to its final size, and now needs to have
4084 the bytes inside it modified to conform to the new size There is UGLY
4088 md_convert_frag_1 (fragP)
4089 register fragS *fragP;
4095 /* Address in object code of the displacement. */
4096 register int object_address = fragP->fr_fix + fragP->fr_address;
4098 /* Address in gas core of the place to store the displacement. */
4099 /* This convinces the native rs6000 compiler to generate the code we
4101 register char *buffer_address = fragP->fr_literal;
4102 buffer_address += fragP->fr_fix;
4103 /* end ibm compiler workaround */
4105 /* The displacement of the address, from current location. */
4106 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4107 disp = (disp + fragP->fr_offset) - object_address;
4109 #ifdef BFD_ASSEMBLER
4110 disp += fragP->fr_symbol->sy_frag->fr_address;
4113 switch (fragP->fr_subtype)
4115 case TAB (BCC68000, BYTE):
4116 case TAB (ABRANCH, BYTE):
4117 know (issbyte (disp));
4119 as_bad ("short branch with zero offset: use :w");
4120 fragP->fr_opcode[1] = disp;
4123 case TAB (DBCC, SHORT):
4124 know (issword (disp));
4127 case TAB (BCC68000, SHORT):
4128 case TAB (ABRANCH, SHORT):
4129 know (issword (disp));
4130 fragP->fr_opcode[1] = 0x00;
4133 case TAB (ABRANCH, LONG):
4134 if (!HAVE_LONG_BRANCH(current_architecture))
4136 if (fragP->fr_opcode[0] == 0x61)
4139 fragP->fr_opcode[0] = 0x4E;
4140 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4154 else if (fragP->fr_opcode[0] == 0x60)
4156 fragP->fr_opcode[0] = 0x4E;
4157 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4158 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4159 fragP->fr_offset, 0, NO_RELOC);
4165 as_bad ("Long branch offset not supported.");
4170 fragP->fr_opcode[1] = (char) 0xff;
4174 case TAB (BCC68000, LONG):
4175 /* only Bcc 68000 instructions can come here */
4176 /* change bcc into b!cc/jmp absl long */
4177 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4178 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4180 /* JF: these used to be fr_opcode[2,3], but they may be in a
4181 different frag, in which case refering to them is a no-no.
4182 Only fr_opcode[0,1] are guaranteed to work. */
4183 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4184 *buffer_address++ = (char) 0xf9;
4185 fragP->fr_fix += 2; /* account for jmp instruction */
4186 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4187 fragP->fr_offset, 0, NO_RELOC);
4191 case TAB (DBCC, LONG):
4192 /* only DBcc 68000 instructions can come here */
4193 /* change dbcc into dbcc/jmp absl long */
4194 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4195 *buffer_address++ = 0x00; /* branch offset = 4 */
4196 *buffer_address++ = 0x04;
4197 *buffer_address++ = 0x60; /* put in bra pc+6 */
4198 *buffer_address++ = 0x06;
4199 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4200 *buffer_address++ = (char) 0xf9;
4202 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4203 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4204 fragP->fr_offset, 0, NO_RELOC);
4208 case TAB (FBRANCH, SHORT):
4209 know ((fragP->fr_opcode[1] & 0x40) == 0);
4212 case TAB (FBRANCH, LONG):
4213 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4216 case TAB (PCREL, SHORT):
4219 case TAB (PCREL, LONG):
4220 /* The thing to do here is force it to ABSOLUTE LONG, since
4221 PCREL is really trying to shorten an ABSOLUTE address anyway */
4222 /* JF FOO This code has not been tested */
4223 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4225 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4226 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4227 (unsigned) fragP->fr_opcode[0],
4228 (unsigned long) fragP->fr_address);
4229 fragP->fr_opcode[1] &= ~0x3F;
4230 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4234 case TAB (PCLEA, SHORT):
4235 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4236 fragP->fr_offset, 1, NO_RELOC);
4237 fragP->fr_opcode[1] &= ~0x3F;
4238 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4241 case TAB (PCLEA, LONG):
4242 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4243 fragP->fr_offset, 1, NO_RELOC);
4244 fixP->fx_pcrel_adjust = 2;
4245 /* Already set to mode 7.3; this indicates: PC indirect with
4246 suppressed index, 32-bit displacement. */
4247 *buffer_address++ = 0x01;
4248 *buffer_address++ = 0x70;
4253 case TAB (PCINDEX, BYTE):
4255 if (!issbyte (disp))
4257 as_bad ("displacement doesn't fit in one byte");
4260 assert (fragP->fr_fix >= 2);
4261 buffer_address[-2] &= ~1;
4262 buffer_address[-1] = disp;
4265 case TAB (PCINDEX, SHORT):
4267 assert (issword (disp));
4268 assert (fragP->fr_fix >= 2);
4269 buffer_address[-2] |= 0x1;
4270 buffer_address[-1] = 0x20;
4271 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4272 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4274 fixP->fx_pcrel_adjust = 2;
4277 case TAB (PCINDEX, LONG):
4279 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4280 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4282 fixP->fx_pcrel_adjust = 2;
4283 assert (fragP->fr_fix >= 2);
4284 buffer_address[-2] |= 0x1;
4285 buffer_address[-1] = 0x30;
4292 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4293 fragP->fr_fix += ext;
4297 #ifndef BFD_ASSEMBLER
4300 md_convert_frag (headers, sec, fragP)
4301 object_headers *headers;
4305 md_convert_frag_1 (fragP);
4311 md_convert_frag (abfd, sec, fragP)
4316 md_convert_frag_1 (fragP);
4320 /* Force truly undefined symbols to their maximum size, and generally set up
4321 the frag list to be relaxed
4324 md_estimate_size_before_relax (fragP, segment)
4325 register fragS *fragP;
4329 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4331 old_fix = fragP->fr_fix;
4333 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4334 switch (fragP->fr_subtype)
4337 case TAB (ABRANCH, SZ_UNDEF):
4339 if ((fragP->fr_symbol != NULL) /* Not absolute */
4340 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4342 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4345 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4347 /* On 68000, or for absolute value, switch to abs long */
4348 /* FIXME, we should check abs val, pick short or long */
4349 if (fragP->fr_opcode[0] == 0x61)
4351 fragP->fr_opcode[0] = 0x4E;
4352 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4353 fix_new (fragP, fragP->fr_fix, 4,
4354 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4358 else if (fragP->fr_opcode[0] == 0x60)
4360 fragP->fr_opcode[0] = 0x4E;
4361 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4362 fix_new (fragP, fragP->fr_fix, 4,
4363 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4369 as_warn ("Long branch offset to extern symbol not supported.");
4373 { /* Symbol is still undefined. Make it simple */
4374 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4375 fragP->fr_offset, 1, NO_RELOC);
4377 fragP->fr_opcode[1] = (char) 0xff;
4383 } /* case TAB(ABRANCH,SZ_UNDEF) */
4385 case TAB (FBRANCH, SZ_UNDEF):
4387 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4389 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4394 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4395 fragP->fr_offset, 1, NO_RELOC);
4397 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4401 } /* TAB(FBRANCH,SZ_UNDEF) */
4403 case TAB (PCREL, SZ_UNDEF):
4405 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4407 || cpu_of_arch (current_architecture) < m68020)
4409 fragP->fr_subtype = TAB (PCREL, SHORT);
4414 fragP->fr_subtype = TAB (PCREL, LONG);
4418 } /* TAB(PCREL,SZ_UNDEF) */
4420 case TAB (BCC68000, SZ_UNDEF):
4422 if ((fragP->fr_symbol != NULL)
4423 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4425 fragP->fr_subtype = TAB (BCC68000, BYTE);
4428 /* only Bcc 68000 instructions can come here */
4429 /* change bcc into b!cc/jmp absl long */
4430 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4431 if (flag_short_refs)
4433 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4434 /* JF: these were fr_opcode[2,3] */
4435 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4436 buffer_address[1] = (char) 0xf8;
4437 fragP->fr_fix += 2; /* account for jmp instruction */
4438 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4439 fragP->fr_offset, 0, NO_RELOC);
4444 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4445 /* JF: these were fr_opcode[2,3] */
4446 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4447 buffer_address[1] = (char) 0xf9;
4448 fragP->fr_fix += 2; /* account for jmp instruction */
4449 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4450 fragP->fr_offset, 0, NO_RELOC);
4455 } /* case TAB(BCC68000,SZ_UNDEF) */
4457 case TAB (DBCC, SZ_UNDEF):
4459 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4461 fragP->fr_subtype = TAB (DBCC, SHORT);
4465 /* only DBcc 68000 instructions can come here */
4466 /* change dbcc into dbcc/jmp absl long */
4467 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4468 buffer_address[0] = 0x00; /* branch offset = 4 */
4469 buffer_address[1] = 0x04;
4470 buffer_address[2] = 0x60; /* put in bra pc + ... */
4472 if (flag_short_refs)
4474 /* JF: these were fr_opcode[5-7] */
4475 buffer_address[3] = 0x04; /* plus 4 */
4476 buffer_address[4] = 0x4e; /* Put in Jump Word */
4477 buffer_address[5] = (char) 0xf8;
4478 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4479 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4480 fragP->fr_offset, 0, NO_RELOC);
4485 /* JF: these were fr_opcode[5-7] */
4486 buffer_address[3] = 0x06; /* Plus 6 */
4487 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4488 buffer_address[5] = (char) 0xf9;
4489 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4490 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4491 fragP->fr_offset, 0, NO_RELOC);
4497 } /* case TAB(DBCC,SZ_UNDEF) */
4499 case TAB (PCLEA, SZ_UNDEF):
4501 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4503 || cpu_of_arch (current_architecture) < m68020)
4505 fragP->fr_subtype = TAB (PCLEA, SHORT);
4510 fragP->fr_subtype = TAB (PCLEA, LONG);
4514 } /* TAB(PCLEA,SZ_UNDEF) */
4516 case TAB (PCINDEX, SZ_UNDEF):
4517 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4518 || cpu_of_arch (current_architecture) < m68020)
4520 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4524 fragP->fr_subtype = TAB (PCINDEX, LONG);
4533 /* now that SZ_UNDEF are taken care of, check others */
4534 switch (fragP->fr_subtype)
4536 case TAB (BCC68000, BYTE):
4537 case TAB (ABRANCH, BYTE):
4538 /* We can't do a short jump to the next instruction, so in that
4539 case we force word mode. At this point S_GET_VALUE should
4540 return the offset of the symbol within its frag. If the
4541 symbol is at the start of a frag, and it is the next frag
4542 with any data in it (usually this is just the next frag, but
4543 assembler listings may introduce empty frags), we must use
4545 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4549 for (l = fragP->fr_next;
4550 l != fragP->fr_symbol->sy_frag;
4552 if (l->fr_fix + l->fr_var != 0)
4554 if (l == fragP->fr_symbol->sy_frag)
4556 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4564 return fragP->fr_var + fragP->fr_fix - old_fix;
4567 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4568 /* the bit-field entries in the relocation_info struct plays hell
4569 with the byte-order problems of cross-assembly. So as a hack,
4570 I added this mach. dependent ri twiddler. Ugly, but it gets
4572 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4573 are symbolnum, most sig. byte first. Last byte is broken up with
4574 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4575 nibble as nuthin. (on Sun 3 at least) */
4576 /* Translate the internal relocation information into target-specific
4580 md_ri_to_chars (the_bytes, ri)
4582 struct reloc_info_generic *ri;
4585 md_number_to_chars (the_bytes, ri->r_address, 4);
4586 /* now the fun stuff */
4587 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4588 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4589 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4590 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4591 ((ri->r_extern << 4) & 0x10));
4594 #endif /* comment */
4596 #ifndef BFD_ASSEMBLER
4598 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4601 relax_addressT segment_address_in_file;
4604 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4605 * Out: GNU LD relocation length code: 0, 1, or 2.
4608 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4611 know (fixP->fx_addsy != NULL);
4613 md_number_to_chars (where,
4614 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4617 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4618 ? S_GET_TYPE (fixP->fx_addsy)
4619 : fixP->fx_addsy->sy_number);
4621 where[4] = (r_symbolnum >> 16) & 0x0ff;
4622 where[5] = (r_symbolnum >> 8) & 0x0ff;
4623 where[6] = r_symbolnum & 0x0ff;
4624 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4625 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4629 #endif /* OBJ_AOUT or OBJ_BOUT */
4631 #ifndef WORKING_DOT_WORD
4632 CONST int md_short_jump_size = 4;
4633 CONST int md_long_jump_size = 6;
4636 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4638 addressT from_addr, to_addr;
4644 offset = to_addr - (from_addr + 2);
4646 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4647 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4651 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4653 addressT from_addr, to_addr;
4659 if (!HAVE_LONG_BRANCH(current_architecture))
4661 offset = to_addr - S_GET_VALUE (to_symbol);
4662 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4663 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4664 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4669 offset = to_addr - (from_addr + 2);
4670 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4671 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4677 /* Different values of OK tell what its OK to return. Things that
4678 aren't OK are an error (what a shock, no?)
4681 10: Absolute 1:8 only
4682 20: Absolute 0:7 only
4683 30: absolute 0:15 only
4684 40: Absolute 0:31 only
4685 50: absolute 0:127 only
4686 55: absolute -64:63 only
4687 60: absolute -128:127 only
4688 70: absolute 0:4095 only
4695 struct m68k_exp *exp;
4698 if (exp->exp.X_op == O_absent)
4700 /* Do the same thing the VAX asm does */
4701 op (exp) = O_constant;
4707 as_warn ("expression out of range: defaulting to 1");
4711 else if (exp->exp.X_op == O_constant)
4716 if (offs (exp) < 1 || offs (exp) > 8)
4718 as_warn ("expression out of range: defaulting to 1");
4723 if (offs (exp) < 0 || offs (exp) > 7)
4727 if (offs (exp) < 0 || offs (exp) > 15)
4731 if (offs (exp) < 0 || offs (exp) > 32)
4735 if (offs (exp) < 0 || offs (exp) > 127)
4739 if (offs (exp) < -64 || offs (exp) > 63)
4743 if (offs (exp) < -128 || offs (exp) > 127)
4747 if (offs (exp) < 0 || offs (exp) > 4095)
4750 as_warn ("expression out of range: defaulting to 0");
4758 else if (exp->exp.X_op == O_big)
4760 if (offs (exp) <= 0 /* flonum */
4761 && (ok == 80 /* no bignums */
4762 || (ok > 10 /* small-int ranges including 0 ok */
4763 /* If we have a flonum zero, a zero integer should
4764 do as well (e.g., in moveq). */
4765 && generic_floating_point_number.exponent == 0
4766 && generic_floating_point_number.low[0] == 0)))
4768 /* HACK! Turn it into a long */
4769 LITTLENUM_TYPE words[6];
4771 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4772 op (exp) = O_constant;
4775 offs (exp) = words[1] | (words[0] << 16);
4779 op (exp) = O_constant;
4782 offs (exp) = (ok == 10) ? 1 : 0;
4783 as_warn ("Can't deal with expression; defaulting to %ld",
4789 if (ok >= 10 && ok <= 70)
4791 op (exp) = O_constant;
4794 offs (exp) = (ok == 10) ? 1 : 0;
4795 as_warn ("Can't deal with expression; defaulting to %ld",
4800 if (exp->size != SIZE_UNSPEC)
4808 if (!isbyte (offs (exp)))
4809 as_warn ("expression doesn't fit in BYTE");
4812 if (!isword (offs (exp)))
4813 as_warn ("expression doesn't fit in WORD");
4821 /* These are the back-ends for the various machine dependent pseudo-ops. */
4827 subseg_set (data_section, 1);
4828 demand_empty_rest_of_line ();
4835 subseg_set (data_section, 2);
4836 demand_empty_rest_of_line ();
4843 /* We don't support putting frags in the BSS segment, we fake it
4844 by marking in_bss, then looking at s_skip for clues. */
4846 subseg_set (bss_section, 0);
4847 demand_empty_rest_of_line ();
4855 register long temp_fill;
4857 temp = 1; /* JF should be 2? */
4858 temp_fill = get_absolute_expression ();
4859 if (!need_pass_2) /* Never make frag if expect extra pass. */
4860 frag_align (temp, (int) temp_fill, 0);
4861 demand_empty_rest_of_line ();
4862 record_alignment (now_seg, temp);
4869 demand_empty_rest_of_line ();
4872 /* Pseudo-ops handled for MRI compatibility. */
4874 /* This function returns non-zero if the argument is a conditional
4875 pseudo-op. This is called when checking whether a pending
4876 alignment is needed. */
4879 m68k_conditional_pseudoop (pop)
4882 return (pop->poc_handler == s_mri_if
4883 || pop->poc_handler == s_mri_else);
4886 /* Handle an MRI style chip specification. */
4895 s = input_line_pointer;
4896 /* We can't use get_symbol_end since the processor names are not proper
4898 while (is_part_of_name (c = *input_line_pointer++))
4900 *--input_line_pointer = 0;
4901 for (i = 0; i < n_archs; i++)
4902 if (strcasecmp (s, archs[i].name) == 0)
4906 as_bad ("%s: unrecognized processor name", s);
4907 *input_line_pointer = c;
4908 ignore_rest_of_line ();
4911 *input_line_pointer = c;
4913 if (*input_line_pointer == '/')
4914 current_architecture = 0;
4916 current_architecture &= m68881 | m68851;
4917 current_architecture |= archs[i].arch;
4919 while (*input_line_pointer == '/')
4921 ++input_line_pointer;
4922 s = input_line_pointer;
4923 /* We can't use get_symbol_end since the processor names are not
4925 while (is_part_of_name (c = *input_line_pointer++))
4927 *--input_line_pointer = 0;
4928 if (strcmp (s, "68881") == 0)
4929 current_architecture |= m68881;
4930 else if (strcmp (s, "68851") == 0)
4931 current_architecture |= m68851;
4932 *input_line_pointer = c;
4935 /* Update info about available control registers. */
4936 select_control_regs ();
4939 /* The MRI CHIP pseudo-op. */
4949 stop = mri_comment_field (&stopc);
4952 mri_comment_end (stop, stopc);
4953 demand_empty_rest_of_line ();
4956 /* The MRI FOPT pseudo-op. */
4964 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4968 input_line_pointer += 3;
4969 temp = get_absolute_expression ();
4970 if (temp < 0 || temp > 7)
4971 as_bad ("bad coprocessor id");
4973 m68k_float_copnum = COP0 + temp;
4977 as_bad ("unrecognized fopt option");
4978 ignore_rest_of_line ();
4982 demand_empty_rest_of_line ();
4985 /* The structure used to handle the MRI OPT pseudo-op. */
4989 /* The name of the option. */
4992 /* If this is not NULL, just call this function. The first argument
4993 is the ARG field of this structure, the second argument is
4994 whether the option was negated. */
4995 void (*pfn) PARAMS ((int arg, int on));
4997 /* If this is not NULL, and the PFN field is NULL, set the variable
4998 this points to. Set it to the ARG field if the option was not
4999 negated, and the NOTARG field otherwise. */
5002 /* The value to pass to PFN or to assign to *PVAR. */
5005 /* The value to assign to *PVAR if the option is negated. If PFN is
5006 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5007 the option may not be negated. */
5011 /* The table used to handle the MRI OPT pseudo-op. */
5013 static void skip_to_comma PARAMS ((int, int));
5014 static void opt_nest PARAMS ((int, int));
5015 static void opt_chip PARAMS ((int, int));
5016 static void opt_list PARAMS ((int, int));
5017 static void opt_list_symbols PARAMS ((int, int));
5019 static const struct opt_action opt_table[] =
5021 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5023 /* We do relaxing, so there is little use for these options. */
5024 { "b", 0, 0, 0, 0 },
5025 { "brs", 0, 0, 0, 0 },
5026 { "brb", 0, 0, 0, 0 },
5027 { "brl", 0, 0, 0, 0 },
5028 { "brw", 0, 0, 0, 0 },
5030 { "c", 0, 0, 0, 0 },
5031 { "cex", 0, 0, 0, 0 },
5032 { "case", 0, &symbols_case_sensitive, 1, 0 },
5033 { "cl", 0, 0, 0, 0 },
5034 { "cre", 0, 0, 0, 0 },
5035 { "d", 0, &flag_keep_locals, 1, 0 },
5036 { "e", 0, 0, 0, 0 },
5037 { "f", 0, &flag_short_refs, 1, 0 },
5038 { "frs", 0, &flag_short_refs, 1, 0 },
5039 { "frl", 0, &flag_short_refs, 0, 1 },
5040 { "g", 0, 0, 0, 0 },
5041 { "i", 0, 0, 0, 0 },
5042 { "m", 0, 0, 0, 0 },
5043 { "mex", 0, 0, 0, 0 },
5044 { "mc", 0, 0, 0, 0 },
5045 { "md", 0, 0, 0, 0 },
5046 { "nest", opt_nest, 0, 0, 0 },
5047 { "next", skip_to_comma, 0, 0, 0 },
5048 { "o", 0, 0, 0, 0 },
5049 { "old", 0, 0, 0, 0 },
5050 { "op", skip_to_comma, 0, 0, 0 },
5051 { "pco", 0, 0, 0, 0 },
5052 { "p", opt_chip, 0, 0, 0 },
5053 { "pcr", 0, 0, 0, 0 },
5054 { "pcs", 0, 0, 0, 0 },
5055 { "r", 0, 0, 0, 0 },
5056 { "quick", 0, &m68k_quick, 1, 0 },
5057 { "rel32", 0, &m68k_rel32, 1, 0 },
5058 { "s", opt_list, 0, 0, 0 },
5059 { "t", opt_list_symbols, 0, 0, 0 },
5060 { "w", 0, &flag_no_warnings, 0, 1 },
5064 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5066 /* The MRI OPT pseudo-op. */
5078 const struct opt_action *o;
5083 if (*input_line_pointer == '-')
5085 ++input_line_pointer;
5088 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5090 input_line_pointer += 2;
5094 s = input_line_pointer;
5095 c = get_symbol_end ();
5097 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5099 if (strcasecmp (s, o->name) == 0)
5103 /* Restore input_line_pointer now in case the option
5105 *input_line_pointer = c;
5106 (*o->pfn) (o->arg, t);
5108 else if (o->pvar != NULL)
5110 if (! t && o->arg == o->notarg)
5111 as_bad ("option `%s' may not be negated", s);
5112 *input_line_pointer = c;
5113 *o->pvar = t ? o->arg : o->notarg;
5116 *input_line_pointer = c;
5122 as_bad ("option `%s' not recognized", s);
5123 *input_line_pointer = c;
5126 while (*input_line_pointer++ == ',');
5128 /* Move back to terminating character. */
5129 --input_line_pointer;
5130 demand_empty_rest_of_line ();
5133 /* Skip ahead to a comma. This is used for OPT options which we do
5134 not suppor tand which take arguments. */
5137 skip_to_comma (arg, on)
5141 while (*input_line_pointer != ','
5142 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5143 ++input_line_pointer;
5146 /* Handle the OPT NEST=depth option. */
5153 if (*input_line_pointer != '=')
5155 as_bad ("bad format of OPT NEST=depth");
5159 ++input_line_pointer;
5160 max_macro_nest = get_absolute_expression ();
5163 /* Handle the OPT P=chip option. */
5170 if (*input_line_pointer != '=')
5172 /* This is just OPT P, which we do not support. */
5176 ++input_line_pointer;
5180 /* Handle the OPT S option. */
5190 /* Handle the OPT T option. */
5193 opt_list_symbols (arg, on)
5198 listing |= LISTING_SYMBOLS;
5200 listing &=~ LISTING_SYMBOLS;
5203 /* Handle the MRI REG pseudo-op. */
5216 if (line_label == NULL)
5218 as_bad ("missing label");
5219 ignore_rest_of_line ();
5224 stop = mri_comment_field (&stopc);
5228 s = input_line_pointer;
5229 while (isalnum ((unsigned char) *input_line_pointer)
5230 #ifdef REGISTER_PREFIX
5231 || *input_line_pointer == REGISTER_PREFIX
5233 || *input_line_pointer == '/'
5234 || *input_line_pointer == '-')
5235 ++input_line_pointer;
5236 c = *input_line_pointer;
5237 *input_line_pointer = '\0';
5239 if (m68k_ip_op (s, &rop) != 0)
5241 if (rop.error == NULL)
5242 as_bad ("bad register list");
5244 as_bad ("bad register list: %s", rop.error);
5245 *input_line_pointer = c;
5246 ignore_rest_of_line ();
5250 *input_line_pointer = c;
5252 if (rop.mode == REGLST)
5254 else if (rop.mode == DREG)
5255 mask = 1 << (rop.reg - DATA0);
5256 else if (rop.mode == AREG)
5257 mask = 1 << (rop.reg - ADDR0 + 8);
5258 else if (rop.mode == FPREG)
5259 mask = 1 << (rop.reg - FP0 + 16);
5260 else if (rop.mode == CONTROL
5263 else if (rop.mode == CONTROL
5266 else if (rop.mode == CONTROL
5271 as_bad ("bad register list");
5272 ignore_rest_of_line ();
5276 S_SET_SEGMENT (line_label, absolute_section);
5277 S_SET_VALUE (line_label, mask);
5278 line_label->sy_frag = &zero_address_frag;
5281 mri_comment_end (stop, stopc);
5283 demand_empty_rest_of_line ();
5286 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5290 struct save_opts *next;
5292 int symbols_case_sensitive;
5300 /* FIXME: We don't save OPT S. */
5303 /* This variable holds the stack of saved options. */
5305 static struct save_opts *save_stack;
5307 /* The MRI SAVE pseudo-op. */
5313 struct save_opts *s;
5315 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5316 s->abspcadd = m68k_abspcadd;
5317 s->symbols_case_sensitive = symbols_case_sensitive;
5318 s->keep_locals = flag_keep_locals;
5319 s->short_refs = flag_short_refs;
5320 s->architecture = current_architecture;
5321 s->quick = m68k_quick;
5322 s->rel32 = m68k_rel32;
5323 s->listing = listing;
5324 s->no_warnings = flag_no_warnings;
5326 s->next = save_stack;
5329 demand_empty_rest_of_line ();
5332 /* The MRI RESTORE pseudo-op. */
5338 struct save_opts *s;
5340 if (save_stack == NULL)
5342 as_bad ("restore without save");
5343 ignore_rest_of_line ();
5348 save_stack = s->next;
5350 m68k_abspcadd = s->abspcadd;
5351 symbols_case_sensitive = s->symbols_case_sensitive;
5352 flag_keep_locals = s->keep_locals;
5353 flag_short_refs = s->short_refs;
5354 current_architecture = s->architecture;
5355 m68k_quick = s->quick;
5356 m68k_rel32 = s->rel32;
5357 listing = s->listing;
5358 flag_no_warnings = s->no_warnings;
5362 demand_empty_rest_of_line ();
5365 /* Types of MRI structured control directives. */
5367 enum mri_control_type
5375 /* This structure is used to stack the MRI structured control
5378 struct mri_control_info
5380 /* The directive within which this one is enclosed. */
5381 struct mri_control_info *outer;
5383 /* The type of directive. */
5384 enum mri_control_type type;
5386 /* Whether an ELSE has been in an IF. */
5389 /* The add or sub statement at the end of a FOR. */
5392 /* The label of the top of a FOR or REPEAT loop. */
5395 /* The label to jump to for the next iteration, or the else
5396 expression of a conditional. */
5399 /* The label to jump to to break out of the loop, or the label past
5400 the end of a conditional. */
5404 /* The stack of MRI structured control directives. */
5406 static struct mri_control_info *mri_control_stack;
5408 /* The current MRI structured control directive index number, used to
5409 generate label names. */
5411 static int mri_control_index;
5413 /* Some function prototypes. */
5415 static char *mri_control_label PARAMS ((void));
5416 static struct mri_control_info *push_mri_control
5417 PARAMS ((enum mri_control_type));
5418 static void pop_mri_control PARAMS ((void));
5419 static int parse_mri_condition PARAMS ((int *));
5420 static int parse_mri_control_operand
5421 PARAMS ((int *, char **, char **, char **, char **));
5422 static int swap_mri_condition PARAMS ((int));
5423 static int reverse_mri_condition PARAMS ((int));
5424 static void build_mri_control_operand
5425 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5426 const char *, int));
5427 static void parse_mri_control_expression
5428 PARAMS ((char *, int, const char *, const char *, int));
5430 /* Generate a new MRI label structured control directive label name. */
5433 mri_control_label ()
5437 n = (char *) xmalloc (20);
5438 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5439 ++mri_control_index;
5443 /* Create a new MRI structured control directive. */
5445 static struct mri_control_info *
5446 push_mri_control (type)
5447 enum mri_control_type type;
5449 struct mri_control_info *n;
5451 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5455 if (type == mri_if || type == mri_while)
5458 n->top = mri_control_label ();
5459 n->next = mri_control_label ();
5460 n->bottom = mri_control_label ();
5462 n->outer = mri_control_stack;
5463 mri_control_stack = n;
5468 /* Pop off the stack of MRI structured control directives. */
5473 struct mri_control_info *n;
5475 n = mri_control_stack;
5476 mri_control_stack = n->outer;
5484 /* Recognize a condition code in an MRI structured control expression. */
5487 parse_mri_condition (pcc)
5492 know (*input_line_pointer == '<');
5494 ++input_line_pointer;
5495 c1 = *input_line_pointer++;
5496 c2 = *input_line_pointer++;
5498 if (*input_line_pointer != '>')
5500 as_bad ("syntax error in structured control directive");
5504 ++input_line_pointer;
5512 *pcc = (c1 << 8) | c2;
5517 /* Parse a single operand in an MRI structured control expression. */
5520 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5537 if (*input_line_pointer == '<')
5539 /* It's just a condition code. */
5540 return parse_mri_condition (pcc);
5543 /* Look ahead for the condition code. */
5544 for (s = input_line_pointer; *s != '\0'; ++s)
5546 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5551 as_bad ("missing condition code in structured control directive");
5555 *leftstart = input_line_pointer;
5557 if (*leftstop > *leftstart
5558 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5561 input_line_pointer = s;
5562 if (! parse_mri_condition (pcc))
5565 /* Look ahead for AND or OR or end of line. */
5566 for (s = input_line_pointer; *s != '\0'; ++s)
5568 if ((strncasecmp (s, "AND", 3) == 0
5569 && (s[3] == '.' || ! is_part_of_name (s[3])))
5570 || (strncasecmp (s, "OR", 2) == 0
5571 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5575 *rightstart = input_line_pointer;
5577 if (*rightstop > *rightstart
5578 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5581 input_line_pointer = s;
5586 #define MCC(b1, b2) (((b1) << 8) | (b2))
5588 /* Swap the sense of a condition. This changes the condition so that
5589 it generates the same result when the operands are swapped. */
5592 swap_mri_condition (cc)
5597 case MCC ('h', 'i'): return MCC ('c', 's');
5598 case MCC ('l', 's'): return MCC ('c', 'c');
5599 case MCC ('c', 'c'): return MCC ('l', 's');
5600 case MCC ('c', 's'): return MCC ('h', 'i');
5601 case MCC ('p', 'l'): return MCC ('m', 'i');
5602 case MCC ('m', 'i'): return MCC ('p', 'l');
5603 case MCC ('g', 'e'): return MCC ('l', 'e');
5604 case MCC ('l', 't'): return MCC ('g', 't');
5605 case MCC ('g', 't'): return MCC ('l', 't');
5606 case MCC ('l', 'e'): return MCC ('g', 'e');
5611 /* Reverse the sense of a condition. */
5614 reverse_mri_condition (cc)
5619 case MCC ('h', 'i'): return MCC ('l', 's');
5620 case MCC ('l', 's'): return MCC ('h', 'i');
5621 case MCC ('c', 'c'): return MCC ('c', 's');
5622 case MCC ('c', 's'): return MCC ('c', 'c');
5623 case MCC ('n', 'e'): return MCC ('e', 'q');
5624 case MCC ('e', 'q'): return MCC ('n', 'e');
5625 case MCC ('v', 'c'): return MCC ('v', 's');
5626 case MCC ('v', 's'): return MCC ('v', 'c');
5627 case MCC ('p', 'l'): return MCC ('m', 'i');
5628 case MCC ('m', 'i'): return MCC ('p', 'l');
5629 case MCC ('g', 'e'): return MCC ('l', 't');
5630 case MCC ('l', 't'): return MCC ('g', 'e');
5631 case MCC ('g', 't'): return MCC ('l', 'e');
5632 case MCC ('l', 'e'): return MCC ('g', 't');
5637 /* Build an MRI structured control expression. This generates test
5638 and branch instructions. It goes to TRUELAB if the condition is
5639 true, and to FALSELAB if the condition is false. Exactly one of
5640 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5641 is the size qualifier for the expression. EXTENT is the size to
5642 use for the branch. */
5645 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5646 rightstop, truelab, falselab, extent)
5653 const char *truelab;
5654 const char *falselab;
5660 if (leftstart != NULL)
5662 struct m68k_op leftop, rightop;
5665 /* Swap the compare operands, if necessary, to produce a legal
5666 m68k compare instruction. Comparing a register operand with
5667 a non-register operand requires the register to be on the
5668 right (cmp, cmpa). Comparing an immediate value with
5669 anything requires the immediate value to be on the left
5674 (void) m68k_ip_op (leftstart, &leftop);
5679 (void) m68k_ip_op (rightstart, &rightop);
5682 if (rightop.mode == IMMED
5683 || ((leftop.mode == DREG || leftop.mode == AREG)
5684 && (rightop.mode != DREG && rightop.mode != AREG)))
5688 cc = swap_mri_condition (cc);
5690 leftstart = rightstart;
5693 leftstop = rightstop;
5698 if (truelab == NULL)
5700 cc = reverse_mri_condition (cc);
5704 if (leftstart != NULL)
5706 buf = (char *) xmalloc (20
5707 + (leftstop - leftstart)
5708 + (rightstop - rightstart));
5716 memcpy (s, leftstart, leftstop - leftstart);
5717 s += leftstop - leftstart;
5719 memcpy (s, rightstart, rightstop - rightstart);
5720 s += rightstop - rightstart;
5726 buf = (char *) xmalloc (20 + strlen (truelab));
5734 strcpy (s, truelab);
5739 /* Parse an MRI structured control expression. This generates test
5740 and branch instructions. STOP is where the expression ends. It
5741 goes to TRUELAB if the condition is true, and to FALSELAB if the
5742 condition is false. Exactly one of TRUELAB and FALSELAB will be
5743 NULL, meaning to fall through. QUAL is the size qualifier for the
5744 expression. EXTENT is the size to use for the branch. */
5747 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5750 const char *truelab;
5751 const char *falselab;
5764 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5765 &rightstart, &rightstop))
5771 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5775 if (falselab != NULL)
5778 flab = mri_control_label ();
5780 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5781 rightstop, (const char *) NULL, flab, extent);
5783 input_line_pointer += 3;
5784 if (*input_line_pointer != '.'
5785 || input_line_pointer[1] == '\0')
5789 qual = input_line_pointer[1];
5790 input_line_pointer += 2;
5793 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5794 &rightstart, &rightstop))
5800 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5801 rightstop, truelab, falselab, extent);
5803 if (falselab == NULL)
5806 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5810 if (truelab != NULL)
5813 tlab = mri_control_label ();
5815 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5816 rightstop, tlab, (const char *) NULL, extent);
5818 input_line_pointer += 2;
5819 if (*input_line_pointer != '.'
5820 || input_line_pointer[1] == '\0')
5824 qual = input_line_pointer[1];
5825 input_line_pointer += 2;
5828 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5829 &rightstart, &rightstop))
5835 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5836 rightstop, truelab, falselab, extent);
5838 if (truelab == NULL)
5843 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5844 rightstop, truelab, falselab, extent);
5848 if (input_line_pointer != stop)
5849 as_bad ("syntax error in structured control directive");
5852 /* Handle the MRI IF pseudo-op. This may be a structured control
5853 directive, or it may be a regular assembler conditional, depending
5862 struct mri_control_info *n;
5864 /* A structured control directive must end with THEN with an
5865 optional qualifier. */
5866 s = input_line_pointer;
5867 while (! is_end_of_line[(unsigned char) *s]
5868 && (! flag_mri || *s != '*'))
5871 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5874 if (s - input_line_pointer > 1
5878 if (s - input_line_pointer < 3
5879 || strncasecmp (s - 3, "THEN", 4) != 0)
5883 as_bad ("missing then");
5884 ignore_rest_of_line ();
5888 /* It's a conditional. */
5893 /* Since this might be a conditional if, this pseudo-op will be
5894 called even if we are supported to be ignoring input. Double
5895 check now. Clobber *input_line_pointer so that ignore_input
5896 thinks that this is not a special pseudo-op. */
5897 c = *input_line_pointer;
5898 *input_line_pointer = 0;
5899 if (ignore_input ())
5901 *input_line_pointer = c;
5902 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5903 ++input_line_pointer;
5904 demand_empty_rest_of_line ();
5907 *input_line_pointer = c;
5909 n = push_mri_control (mri_if);
5911 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5912 n->next, s[1] == '.' ? s[2] : '\0');
5915 input_line_pointer = s + 3;
5917 input_line_pointer = s + 1;
5921 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5922 ++input_line_pointer;
5925 demand_empty_rest_of_line ();
5928 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5929 structured IF, associate the ELSE with the IF. Otherwise, assume
5930 it is a conditional else. */
5941 && (mri_control_stack == NULL
5942 || mri_control_stack->type != mri_if
5943 || mri_control_stack->else_seen))
5949 c = *input_line_pointer;
5950 *input_line_pointer = 0;
5951 if (ignore_input ())
5953 *input_line_pointer = c;
5954 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5955 ++input_line_pointer;
5956 demand_empty_rest_of_line ();
5959 *input_line_pointer = c;
5961 if (mri_control_stack == NULL
5962 || mri_control_stack->type != mri_if
5963 || mri_control_stack->else_seen)
5965 as_bad ("else without matching if");
5966 ignore_rest_of_line ();
5970 mri_control_stack->else_seen = 1;
5972 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5975 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5979 colon (mri_control_stack->next);
5983 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5984 ++input_line_pointer;
5987 demand_empty_rest_of_line ();
5990 /* Handle the MRI ENDI pseudo-op. */
5996 if (mri_control_stack == NULL
5997 || mri_control_stack->type != mri_if)
5999 as_bad ("endi without matching if");
6000 ignore_rest_of_line ();
6004 /* ignore_input will not return true for ENDI, so we don't need to
6005 worry about checking it again here. */
6007 if (! mri_control_stack->else_seen)
6008 colon (mri_control_stack->next);
6009 colon (mri_control_stack->bottom);
6015 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6016 ++input_line_pointer;
6019 demand_empty_rest_of_line ();
6022 /* Handle the MRI BREAK pseudo-op. */
6025 s_mri_break (extent)
6028 struct mri_control_info *n;
6032 n = mri_control_stack;
6034 && n->type != mri_for
6035 && n->type != mri_repeat
6036 && n->type != mri_while)
6040 as_bad ("break outside of structured loop");
6041 ignore_rest_of_line ();
6045 buf = (char *) xmalloc (20 + strlen (n->bottom));
6048 sprintf (buf, "bra%s %s", ex, n->bottom);
6054 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6055 ++input_line_pointer;
6058 demand_empty_rest_of_line ();
6061 /* Handle the MRI NEXT pseudo-op. */
6067 struct mri_control_info *n;
6071 n = mri_control_stack;
6073 && n->type != mri_for
6074 && n->type != mri_repeat
6075 && n->type != mri_while)
6079 as_bad ("next outside of structured loop");
6080 ignore_rest_of_line ();
6084 buf = (char *) xmalloc (20 + strlen (n->next));
6087 sprintf (buf, "bra%s %s", ex, n->next);
6093 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6094 ++input_line_pointer;
6097 demand_empty_rest_of_line ();
6100 /* Handle the MRI FOR pseudo-op. */
6106 const char *varstart, *varstop;
6107 const char *initstart, *initstop;
6108 const char *endstart, *endstop;
6109 const char *bystart, *bystop;
6113 struct mri_control_info *n;
6119 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6123 varstart = input_line_pointer;
6125 /* Look for the '='. */
6126 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6127 && *input_line_pointer != '=')
6128 ++input_line_pointer;
6129 if (*input_line_pointer != '=')
6131 as_bad ("missing =");
6132 ignore_rest_of_line ();
6136 varstop = input_line_pointer;
6137 if (varstop > varstart
6138 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6141 ++input_line_pointer;
6143 initstart = input_line_pointer;
6145 /* Look for TO or DOWNTO. */
6148 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6150 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6151 && ! is_part_of_name (input_line_pointer[2]))
6153 initstop = input_line_pointer;
6154 input_line_pointer += 2;
6157 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6158 && ! is_part_of_name (input_line_pointer[6]))
6160 initstop = input_line_pointer;
6162 input_line_pointer += 6;
6165 ++input_line_pointer;
6167 if (initstop == NULL)
6169 as_bad ("missing to or downto");
6170 ignore_rest_of_line ();
6173 if (initstop > initstart
6174 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6178 endstart = input_line_pointer;
6180 /* Look for BY or DO. */
6183 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6185 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6186 && ! is_part_of_name (input_line_pointer[2]))
6188 endstop = input_line_pointer;
6190 input_line_pointer += 2;
6193 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6194 && (input_line_pointer[2] == '.'
6195 || ! is_part_of_name (input_line_pointer[2])))
6197 endstop = input_line_pointer;
6198 input_line_pointer += 2;
6201 ++input_line_pointer;
6203 if (endstop == NULL)
6205 as_bad ("missing do");
6206 ignore_rest_of_line ();
6209 if (endstop > endstart
6210 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6216 bystop = bystart + 2;
6221 bystart = input_line_pointer;
6225 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6227 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6228 && (input_line_pointer[2] == '.'
6229 || ! is_part_of_name (input_line_pointer[2])))
6231 bystop = input_line_pointer;
6232 input_line_pointer += 2;
6235 ++input_line_pointer;
6239 as_bad ("missing do");
6240 ignore_rest_of_line ();
6243 if (bystop > bystart
6244 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6248 if (*input_line_pointer != '.')
6252 extent = input_line_pointer[1];
6253 input_line_pointer += 2;
6256 /* We have fully parsed the FOR operands. Now build the loop. */
6258 n = push_mri_control (mri_for);
6260 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6271 memcpy (s, initstart, initstop - initstart);
6272 s += initstop - initstart;
6274 memcpy (s, varstart, varstop - varstart);
6275 s += varstop - varstart;
6289 memcpy (s, endstart, endstop - endstart);
6290 s += endstop - endstart;
6292 memcpy (s, varstart, varstop - varstart);
6293 s += varstop - varstart;
6301 sprintf (buf, "blt%s %s", ex, n->bottom);
6303 sprintf (buf, "bgt%s %s", ex, n->bottom);
6306 /* Put together the add or sub instruction used by ENDF. */
6316 memcpy (s, bystart, bystop - bystart);
6317 s += bystop - bystart;
6319 memcpy (s, varstart, varstop - varstart);
6320 s += varstop - varstart;
6326 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6327 ++input_line_pointer;
6330 demand_empty_rest_of_line ();
6333 /* Handle the MRI ENDF pseudo-op. */
6339 if (mri_control_stack == NULL
6340 || mri_control_stack->type != mri_for)
6342 as_bad ("endf without for");
6343 ignore_rest_of_line ();
6347 colon (mri_control_stack->next);
6349 md_assemble (mri_control_stack->incr);
6351 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6352 md_assemble (mri_control_stack->incr);
6354 free (mri_control_stack->incr);
6356 colon (mri_control_stack->bottom);
6362 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6363 ++input_line_pointer;
6366 demand_empty_rest_of_line ();
6369 /* Handle the MRI REPEAT pseudo-op. */
6372 s_mri_repeat (ignore)
6375 struct mri_control_info *n;
6377 n = push_mri_control (mri_repeat);
6381 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6382 ++input_line_pointer;
6384 demand_empty_rest_of_line ();
6387 /* Handle the MRI UNTIL pseudo-op. */
6395 if (mri_control_stack == NULL
6396 || mri_control_stack->type != mri_repeat)
6398 as_bad ("until without repeat");
6399 ignore_rest_of_line ();
6403 colon (mri_control_stack->next);
6405 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6408 parse_mri_control_expression (s, qual, (const char *) NULL,
6409 mri_control_stack->top, '\0');
6411 colon (mri_control_stack->bottom);
6413 input_line_pointer = s;
6419 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6420 ++input_line_pointer;
6423 demand_empty_rest_of_line ();
6426 /* Handle the MRI WHILE pseudo-op. */
6434 struct mri_control_info *n;
6436 s = input_line_pointer;
6437 while (! is_end_of_line[(unsigned char) *s]
6438 && (! flag_mri || *s != '*'))
6441 while (*s == ' ' || *s == '\t')
6443 if (s - input_line_pointer > 1
6446 if (s - input_line_pointer < 2
6447 || strncasecmp (s - 1, "DO", 2) != 0)
6449 as_bad ("missing do");
6450 ignore_rest_of_line ();
6454 n = push_mri_control (mri_while);
6458 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6459 s[1] == '.' ? s[2] : '\0');
6461 input_line_pointer = s + 1;
6462 if (*input_line_pointer == '.')
6463 input_line_pointer += 2;
6467 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6468 ++input_line_pointer;
6471 demand_empty_rest_of_line ();
6474 /* Handle the MRI ENDW pseudo-op. */
6482 if (mri_control_stack == NULL
6483 || mri_control_stack->type != mri_while)
6485 as_bad ("endw without while");
6486 ignore_rest_of_line ();
6490 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6491 sprintf (buf, "bra %s", mri_control_stack->next);
6495 colon (mri_control_stack->bottom);
6501 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6502 ++input_line_pointer;
6505 demand_empty_rest_of_line ();
6510 * Invocation line includes a switch not recognized by the base assembler.
6511 * See if it's a processor-specific option. These are:
6513 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6514 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6515 * Select the architecture. Instructions or features not
6516 * supported by the selected architecture cause fatal
6517 * errors. More than one may be specified. The default is
6518 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6519 * for -m68000, and -m68882 is a synonym for -m68881.
6520 * -[A]m[c]no-68851, -[A]m[c]no-68881
6521 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6522 * so don't use or document it, but that's the way the parsing
6525 * -pic Indicates PIC.
6526 * -k Indicates PIC. (Sun 3 only.)
6529 * Permit `|' to be used in expressions.
6534 CONST char *md_shortopts = "lSA:m:kQ:V";
6536 CONST char *md_shortopts = "lSA:m:k";
6539 struct option md_longopts[] = {
6540 #define OPTION_PIC (OPTION_MD_BASE)
6541 {"pic", no_argument, NULL, OPTION_PIC},
6542 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6543 {"register-prefix-optional", no_argument, NULL,
6544 OPTION_REGISTER_PREFIX_OPTIONAL},
6545 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6546 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6547 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6548 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6549 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6550 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6551 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6552 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6553 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6554 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6555 {NULL, no_argument, NULL, 0}
6557 size_t md_longopts_size = sizeof(md_longopts);
6560 md_parse_option (c, arg)
6566 case 'l': /* -l means keep external to 2 bit offset
6567 rather than 16 bit one */
6568 flag_short_refs = 1;
6571 case 'S': /* -S means that jbsr's always turn into
6573 flag_long_jumps = 1;
6579 /* intentional fall-through */
6582 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6586 const char *oarg = arg;
6592 if (arg[0] == 'c' && arg[1] == '6')
6595 for (i = 0; i < n_archs; i++)
6596 if (!strcmp (arg, archs[i].name))
6601 as_bad ("unrecognized option `%s'", oarg);
6604 arch = archs[i].arch;
6607 else if (arch == m68851)
6616 if (arg[0] == 'c' && arg[1] == '6')
6619 for (i = 0; i < n_archs; i++)
6620 if (!strcmp (arg, archs[i].name))
6622 unsigned long arch = archs[i].arch;
6623 if (cpu_of_arch (arch))
6624 /* It's a cpu spec. */
6626 current_architecture &= ~m68000up;
6627 current_architecture |= arch;
6629 else if (arch == m68881)
6631 current_architecture |= m68881;
6634 else if (arch == m68851)
6636 current_architecture |= m68851;
6646 as_bad ("unrecognized architecture specification `%s'", arg);
6655 break; /* -pic, Position Independent Code */
6657 case OPTION_REGISTER_PREFIX_OPTIONAL:
6658 flag_reg_prefix_optional = 1;
6659 reg_prefix_optional_seen = 1;
6662 /* -V: SVR4 argument to print version ID. */
6664 print_version_id ();
6667 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6668 should be emitted or not. FIXME: Not implemented. */
6672 case OPTION_BITWISE_OR:
6677 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6679 for (s = m68k_comment_chars; *s != '\0'; s++)
6683 m68k_comment_chars = n;
6687 case OPTION_BASE_SIZE_DEFAULT_16:
6688 m68k_index_width_default = SIZE_WORD;
6691 case OPTION_BASE_SIZE_DEFAULT_32:
6692 m68k_index_width_default = SIZE_LONG;
6695 case OPTION_DISP_SIZE_DEFAULT_16:
6697 m68k_rel32_from_cmdline = 1;
6700 case OPTION_DISP_SIZE_DEFAULT_32:
6702 m68k_rel32_from_cmdline = 1;
6713 md_show_usage (stream)
6718 -l use 1 word for refs to undefined symbols [default 2]\n\
6719 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6720 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6721 | -mcpu32 | -m5200\n\
6722 specify variant of 680X0 architecture [default 68020]\n\
6723 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6724 target has/lacks floating-point coprocessor\n\
6725 [default yes for 68020, 68030, and cpu32]\n");
6727 -m68851 | -mno-68851\n\
6728 target has/lacks memory-management unit coprocessor\n\
6729 [default yes for 68020 and up]\n\
6730 -pic, -k generate position independent code\n\
6731 -S turn jbsr into jsr\n\
6732 --register-prefix-optional\n\
6733 recognize register names without prefix character\n\
6734 --bitwise-or do not treat `|' as a comment character\n");
6736 --base-size-default-16 base reg without size is 16 bits\n\
6737 --base-size-default-32 base reg without size is 32 bits (default)\n\
6738 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6739 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6744 /* TEST2: Test md_assemble() */
6745 /* Warning, this routine probably doesn't work anymore */
6749 struct m68k_it the_ins;
6757 if (!gets (buf) || !*buf)
6759 if (buf[0] == '|' || buf[1] == '.')
6761 for (cp = buf; *cp; cp++)
6766 memset (&the_ins, '\0', sizeof (the_ins));
6767 m68k_ip (&the_ins, buf);
6770 printf ("Error %s in %s\n", the_ins.error, buf);
6774 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6775 for (n = 0; n < the_ins.numo; n++)
6776 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6778 print_the_insn (&the_ins.opcode[0], stdout);
6779 (void) putchar ('\n');
6781 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6783 if (the_ins.operands[n].error)
6785 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6788 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6789 if (the_ins.operands[n].b_const)
6790 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6791 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6792 if (the_ins.operands[n].b_iadd)
6793 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6794 (void) putchar ('\n');
6806 while (*str && *str != ' ')
6808 if (str[-1] == ':' || str[1] == '=')
6815 /* Possible states for relaxation:
6817 0 0 branch offset byte (bra, etc)
6821 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6825 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6832 /* We have no need to default values of symbols. */
6836 md_undefined_symbol (name)
6842 /* Round up a section size to the appropriate boundary. */
6844 md_section_align (segment, size)
6849 #ifdef BFD_ASSEMBLER
6850 /* For a.out, force the section size to be aligned. If we don't do
6851 this, BFD will align it for us, but it will not write out the
6852 final bytes of the section. This may be a bug in BFD, but it is
6853 easier to fix it here since that is how the other a.out targets
6857 align = bfd_get_section_alignment (stdoutput, segment);
6858 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6865 /* Exactly what point is a PC-relative offset relative TO?
6866 On the 68k, it is relative to the address of the first extension
6867 word. The difference between the addresses of the offset and the
6868 first extension word is stored in fx_pcrel_adjust. */
6870 md_pcrel_from (fixP)
6875 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6877 adjust = fixP->fx_pcrel_adjust;
6880 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6883 #ifndef BFD_ASSEMBLER
6888 tc_coff_symbol_emit_hook (ignore)
6894 tc_coff_sizemachdep (frag)
6897 switch (frag->fr_subtype & 0x3)
6914 /* end of tc-m68k.c */