1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
86 int flag_reg_prefix_optional;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32 = 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line *next;
127 /* The list of labels. */
129 static struct label_line *labels;
131 /* The current label. */
133 static struct label_line *current_label;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn;
144 const char *m_operands;
145 unsigned long m_opcode;
149 struct m68k_incant *m_next;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
179 static const enum m68k_register mcf51qe_ctrl[] = {
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, FLASHBAR, RAMBAR, RAMBAR1,
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
223 static const enum m68k_register mcf5250_ctrl[] = {
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
275 static const enum m68k_register mcf54455_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
277 VBR, PC, RAMBAR1, MBAR,
279 TC /* ASID */, BUSCR /* MMUBAR */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
284 static const enum m68k_register mcf5475_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
293 static const enum m68k_register mcf5485_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
302 static const enum m68k_register fido_ctrl[] = {
303 SFC, DFC, USP, VBR, CAC, MBB,
306 #define cpu32_ctrl m68010_ctrl
308 static const enum m68k_register *control_regs;
310 /* Internal form of a 68020 instruction. */
314 const char *args; /* List of opcode info. */
317 int numo; /* Number of shorts in opcode. */
320 struct m68k_op operands[6];
322 int nexp; /* Number of exprs in use. */
323 struct m68k_exp exprs[4];
325 int nfrag; /* Number of frags we have to produce. */
328 int fragoff; /* Where in the current opcode the frag ends. */
335 int nrel; /* Num of reloc strucs in use. */
342 /* In a pc relative address the difference between the address
343 of the offset and the address that the offset is relative
344 to. This depends on the addressing mode. Basically this
345 is the value to put in the offset field to address the
346 first byte of the offset, without regarding the special
347 significance of some values (in the branch instruction, for
351 /* Whether this expression needs special pic relocation, and if
353 enum pic_relocation pic_reloc;
356 reloc[5]; /* Five is enough??? */
359 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
360 #define float_of_arch(x) ((x) & mfloat)
361 #define mmu_of_arch(x) ((x) & mmmu)
362 #define arch_coldfire_p(x) ((x) & mcfisa_a)
363 #define arch_coldfire_fpu(x) ((x) & cfloat)
365 /* Macros for determining if cpu supports a specific addressing mode. */
366 #define HAVE_LONG_DISP(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368 #define HAVE_LONG_CALL(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
370 #define HAVE_LONG_COND(x) \
371 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
372 #define HAVE_LONG_BRANCH(x) \
373 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
375 static struct m68k_it the_ins; /* The instruction being assembled. */
377 #define op(ex) ((ex)->exp.X_op)
378 #define adds(ex) ((ex)->exp.X_add_symbol)
379 #define subs(ex) ((ex)->exp.X_op_symbol)
380 #define offs(ex) ((ex)->exp.X_add_number)
382 /* Macros for adding things to the m68k_it struct. */
383 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
385 /* Like addword, but goes BEFORE general operands. */
388 insop (int w, const struct m68k_incant *opcode)
391 for (z = the_ins.numo; z > opcode->m_codenum; --z)
392 the_ins.opcode[z] = the_ins.opcode[z - 1];
393 for (z = 0; z < the_ins.nrel; z++)
394 the_ins.reloc[z].n += 2;
395 for (z = 0; z < the_ins.nfrag; z++)
396 the_ins.fragb[z].fragoff++;
397 the_ins.opcode[opcode->m_codenum] = w;
401 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
404 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
406 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
407 ? the_ins.numo * 2 - 1
409 ? the_ins.numo * 2 + 1
410 : the_ins.numo * 2));
411 the_ins.reloc[the_ins.nrel].exp = exp->exp;
412 the_ins.reloc[the_ins.nrel].wid = width;
413 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
415 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
417 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
420 /* Cause an extra frag to be generated here, inserting up to 10 bytes
421 (that value is chosen in the frag_var call in md_assemble). TYPE
422 is the subtype of the frag to be generated; its primary type is
423 rs_machine_dependent.
425 The TYPE parameter is also used by md_convert_frag_1 and
426 md_estimate_size_before_relax. The appropriate type of fixup will
427 be emitted by md_convert_frag_1.
429 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
431 add_frag (symbolS *add, offsetT off, int type)
433 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
434 the_ins.fragb[the_ins.nfrag].fadd = add;
435 the_ins.fragb[the_ins.nfrag].foff = off;
436 the_ins.fragb[the_ins.nfrag++].fragty = type;
440 (op (ex) != O_constant && op (ex) != O_big)
442 static char *crack_operand (char *str, struct m68k_op *opP);
443 static int get_num (struct m68k_exp *exp, int ok);
444 static int reverse_16_bits (int in);
445 static int reverse_8_bits (int in);
446 static void install_gen_operand (int mode, int val);
447 static void install_operand (int mode, int val);
448 static void s_bss (int);
449 static void s_data1 (int);
450 static void s_data2 (int);
451 static void s_even (int);
452 static void s_proc (int);
453 static void s_chip (int);
454 static void s_fopt (int);
455 static void s_opt (int);
456 static void s_reg (int);
457 static void s_restore (int);
458 static void s_save (int);
459 static void s_mri_if (int);
460 static void s_mri_else (int);
461 static void s_mri_endi (int);
462 static void s_mri_break (int);
463 static void s_mri_next (int);
464 static void s_mri_for (int);
465 static void s_mri_endf (int);
466 static void s_mri_repeat (int);
467 static void s_mri_until (int);
468 static void s_mri_while (int);
469 static void s_mri_endw (int);
470 static void s_m68k_cpu (int);
471 static void s_m68k_arch (int);
475 unsigned long arch; /* Architecture features. */
476 const enum m68k_register *control_regs; /* Control regs on chip */
477 const char *name; /* Name */
478 int alias; /* Alias for a cannonical name. If 1, then
479 succeeds canonical name, if -1 then
480 succeeds canonical name, if <-1 ||>1 this is a
481 deprecated name, and the next/previous name
485 /* We hold flags for features explicitly enabled and explicitly
487 static int current_architecture;
488 static int not_current_architecture;
489 static const struct m68k_cpu *selected_arch;
490 static const struct m68k_cpu *selected_cpu;
491 static int initialized;
493 /* Architecture models. */
494 static const struct m68k_cpu m68k_archs[] =
496 {m68000, m68000_ctrl, "68000", 0},
497 {m68010, m68010_ctrl, "68010", 0},
498 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
499 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
500 {m68040, m68040_ctrl, "68040", 0},
501 {m68060, m68060_ctrl, "68060", 0},
502 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
503 {fido_a, fido_ctrl, "fidoa", 0},
504 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
506 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
507 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
508 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
509 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
513 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
515 static const struct m68k_cpu m68k_extensions[] =
517 {m68851, NULL, "68851", -1},
518 {m68881, NULL, "68881", -1},
519 {m68881, NULL, "68882", -1},
521 {cfloat|m68881, NULL, "float", 0},
523 {mcfhwdiv, NULL, "div", 1},
524 {mcfusp, NULL, "usp", 1},
525 {mcfmac, NULL, "mac", 1},
526 {mcfemac, NULL, "emac", 1},
532 static const struct m68k_cpu m68k_cpus[] =
534 {m68000, m68000_ctrl, "68000", 0},
535 {m68000, m68000_ctrl, "68ec000", 1},
536 {m68000, m68000_ctrl, "68hc000", 1},
537 {m68000, m68000_ctrl, "68hc001", 1},
538 {m68000, m68000_ctrl, "68008", 1},
539 {m68000, m68000_ctrl, "68302", 1},
540 {m68000, m68000_ctrl, "68306", 1},
541 {m68000, m68000_ctrl, "68307", 1},
542 {m68000, m68000_ctrl, "68322", 1},
543 {m68000, m68000_ctrl, "68356", 1},
544 {m68010, m68010_ctrl, "68010", 0},
545 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
546 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
547 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
548 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
549 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
550 {m68040, m68040_ctrl, "68040", 0},
551 {m68040, m68040_ctrl, "68ec040", 1},
552 {m68060, m68060_ctrl, "68060", 0},
553 {m68060, m68060_ctrl, "68ec060", 1},
555 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
556 {cpu32|m68881, cpu32_ctrl, "68330", 1},
557 {cpu32|m68881, cpu32_ctrl, "68331", 1},
558 {cpu32|m68881, cpu32_ctrl, "68332", 1},
559 {cpu32|m68881, cpu32_ctrl, "68333", 1},
560 {cpu32|m68881, cpu32_ctrl, "68334", 1},
561 {cpu32|m68881, cpu32_ctrl, "68336", 1},
562 {cpu32|m68881, cpu32_ctrl, "68340", 1},
563 {cpu32|m68881, cpu32_ctrl, "68341", 1},
564 {cpu32|m68881, cpu32_ctrl, "68349", 1},
565 {cpu32|m68881, cpu32_ctrl, "68360", 1},
567 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
569 {mcfisa_a, mcf_ctrl, "5200", 0},
570 {mcfisa_a, mcf_ctrl, "5202", 1},
571 {mcfisa_a, mcf_ctrl, "5204", 1},
572 {mcfisa_a, mcf5206_ctrl, "5206", 1},
574 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
583 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
607 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
608 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
609 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
614 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
635 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
637 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
638 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
639 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
640 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
641 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
642 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
653 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
660 {fido_a, fido_ctrl, "fidoa", 0},
661 {fido_a, fido_ctrl, "fido", 1},
666 static const struct m68k_cpu *m68k_lookup_cpu
667 (const char *, const struct m68k_cpu *, int, int *);
668 static int m68k_set_arch (const char *, int, int);
669 static int m68k_set_cpu (const char *, int, int);
670 static int m68k_set_extension (const char *, int, int);
671 static void m68k_init_arch (void);
673 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
674 architecture and we have a lot of relaxation modes. */
676 /* Macros used in the relaxation code. */
677 #define TAB(x,y) (((x) << 2) + (y))
678 #define TABTYPE(x) ((x) >> 2)
680 /* Relaxation states. */
686 /* Here are all the relaxation modes we support. First we can relax ordinary
687 branches. On 68020 and higher and on CPU32 all branch instructions take
688 three forms, so on these CPUs all branches always remain as such. When we
689 have to expand to the LONG form on a 68000, though, we substitute an
690 absolute jump instead. This is a direct replacement for unconditional
691 branches and a branch over a jump for conditional branches. However, if the
692 user requires PIC and disables this with --pcrel, we can only relax between
693 BYTE and SHORT forms, punting if that isn't enough. This gives us four
694 different relaxation modes for branches: */
696 #define BRANCHBWL 0 /* Branch byte, word, or long. */
697 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
698 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
699 #define BRANCHBW 3 /* Branch byte or word. */
701 /* We also relax coprocessor branches and DBcc's. All CPUs that support
702 coprocessor branches support them in word and long forms, so we have only
703 one relaxation mode for them. DBcc's are word only on all CPUs. We can
704 relax them to the LONG form with a branch-around sequence. This sequence
705 can use a long branch (if available) or an absolute jump (if acceptable).
706 This gives us two relaxation modes. If long branches are not available and
707 absolute jumps are not acceptable, we don't relax DBcc's. */
709 #define FBRANCH 4 /* Coprocessor branch. */
710 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
711 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
713 /* That's all for instruction relaxation. However, we also relax PC-relative
714 operands. Specifically, we have three operand relaxation modes. On the
715 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
716 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
717 two. Also PC+displacement+index operands in their simple form (with a non-
718 suppressed index without memory indirection) are supported on all CPUs, but
719 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
720 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
721 form of the PC+displacement+index operand. Finally, some absolute operands
722 can be relaxed down to 16-bit PC-relative. */
724 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
725 #define PCINDEX 8 /* PC + displacement + index. */
726 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
728 /* Note that calls to frag_var need to specify the maximum expansion
729 needed; this is currently 10 bytes for DBCC. */
732 How far Forward this mode will reach:
733 How far Backward this mode will reach:
734 How many bytes this mode will add to the size of the frag
735 Which mode to go to if the offset won't fit in this one
737 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
738 relax_typeS md_relax_table[] =
740 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
741 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
745 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
746 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
750 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
751 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
755 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
760 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
761 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
765 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
766 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
770 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
771 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
775 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
776 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
780 { 125, -130, 0, TAB (PCINDEX, SHORT) },
781 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
785 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
786 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
791 /* These are the machine dependent pseudo-ops. These are included so
792 the assembler can work on the output from the SUN C compiler, which
795 /* This table describes all the machine specific pseudo-ops the assembler
796 has to support. The fields are:
797 pseudo-op name without dot
798 function to call to execute this pseudo-op
799 Integer arg to pass to the function. */
800 const pseudo_typeS md_pseudo_table[] =
802 {"data1", s_data1, 0},
803 {"data2", s_data2, 0},
806 {"skip", s_space, 0},
808 #if defined (TE_SUN3) || defined (OBJ_ELF)
809 {"align", s_align_bytes, 0},
812 {"swbeg", s_ignore, 0},
814 {"extend", float_cons, 'x'},
815 {"ldouble", float_cons, 'x'},
817 {"arch", s_m68k_arch, 0},
818 {"cpu", s_m68k_cpu, 0},
820 /* The following pseudo-ops are supported for MRI compatibility. */
822 {"comline", s_space, 1},
824 {"mask2", s_ignore, 0},
827 {"restore", s_restore, 0},
831 {"if.b", s_mri_if, 'b'},
832 {"if.w", s_mri_if, 'w'},
833 {"if.l", s_mri_if, 'l'},
834 {"else", s_mri_else, 0},
835 {"else.s", s_mri_else, 's'},
836 {"else.l", s_mri_else, 'l'},
837 {"endi", s_mri_endi, 0},
838 {"break", s_mri_break, 0},
839 {"break.s", s_mri_break, 's'},
840 {"break.l", s_mri_break, 'l'},
841 {"next", s_mri_next, 0},
842 {"next.s", s_mri_next, 's'},
843 {"next.l", s_mri_next, 'l'},
844 {"for", s_mri_for, 0},
845 {"for.b", s_mri_for, 'b'},
846 {"for.w", s_mri_for, 'w'},
847 {"for.l", s_mri_for, 'l'},
848 {"endf", s_mri_endf, 0},
849 {"repeat", s_mri_repeat, 0},
850 {"until", s_mri_until, 0},
851 {"until.b", s_mri_until, 'b'},
852 {"until.w", s_mri_until, 'w'},
853 {"until.l", s_mri_until, 'l'},
854 {"while", s_mri_while, 0},
855 {"while.b", s_mri_while, 'b'},
856 {"while.w", s_mri_while, 'w'},
857 {"while.l", s_mri_while, 'l'},
858 {"endw", s_mri_endw, 0},
863 /* The mote pseudo ops are put into the opcode table, since they
864 don't start with a . they look like opcodes to gas. */
866 const pseudo_typeS mote_pseudo_table[] =
879 {"xdef", s_globl, 0},
881 {"align", s_align_bytes, 0},
883 {"align", s_align_ptwo, 0},
886 {"sect", obj_coff_section, 0},
887 {"section", obj_coff_section, 0},
892 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
893 gives identical results to a 32-bit host. */
894 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
895 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
897 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
898 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
899 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
900 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
902 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
903 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
904 #define islong(x) (1)
906 static char notend_table[256];
907 static char alt_notend_table[256];
909 (! (notend_table[(unsigned char) *s] \
911 && alt_notend_table[(unsigned char) s[1]])))
915 /* Return zero if the reference to SYMBOL from within the same segment may
918 /* On an ELF system, we can't relax an externally visible symbol,
919 because it may be overridden by a shared library. However, if
920 TARGET_OS is "elf", then we presume that we are assembling for an
921 embedded system, in which case we don't have to worry about shared
922 libraries, and we can relax any external sym. */
924 #define relaxable_symbol(symbol) \
925 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
926 || S_IS_WEAK (symbol)))
928 /* Compute the relocation code for a fixup of SIZE bytes, using pc
929 relative relocation if PCREL is non-zero. PIC says whether a special
930 pic relocation was requested. */
932 static bfd_reloc_code_real_type
933 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
941 return BFD_RELOC_8_GOT_PCREL;
943 return BFD_RELOC_16_GOT_PCREL;
945 return BFD_RELOC_32_GOT_PCREL;
953 return BFD_RELOC_8_GOTOFF;
955 return BFD_RELOC_16_GOTOFF;
957 return BFD_RELOC_32_GOTOFF;
965 return BFD_RELOC_8_PLT_PCREL;
967 return BFD_RELOC_16_PLT_PCREL;
969 return BFD_RELOC_32_PLT_PCREL;
977 return BFD_RELOC_8_PLTOFF;
979 return BFD_RELOC_16_PLTOFF;
981 return BFD_RELOC_32_PLTOFF;
991 return BFD_RELOC_8_PCREL;
993 return BFD_RELOC_16_PCREL;
995 return BFD_RELOC_32_PCREL;
1005 return BFD_RELOC_16;
1007 return BFD_RELOC_32;
1014 if (pic == pic_none)
1015 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1017 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1021 if (pic == pic_none)
1022 as_bad (_("Can not do %d byte relocation"), size);
1024 as_bad (_("Can not do %d byte pic relocation"), size);
1027 return BFD_RELOC_NONE;
1030 /* Here we decide which fixups can be adjusted to make them relative
1031 to the beginning of the section instead of the symbol. Basically
1032 we need to make sure that the dynamic relocations are done
1033 correctly, so in some cases we force the original symbol to be
1036 tc_m68k_fix_adjustable (fixS *fixP)
1038 /* Adjust_reloc_syms doesn't know about the GOT. */
1039 switch (fixP->fx_r_type)
1041 case BFD_RELOC_8_GOT_PCREL:
1042 case BFD_RELOC_16_GOT_PCREL:
1043 case BFD_RELOC_32_GOT_PCREL:
1044 case BFD_RELOC_8_GOTOFF:
1045 case BFD_RELOC_16_GOTOFF:
1046 case BFD_RELOC_32_GOTOFF:
1047 case BFD_RELOC_8_PLT_PCREL:
1048 case BFD_RELOC_16_PLT_PCREL:
1049 case BFD_RELOC_32_PLT_PCREL:
1050 case BFD_RELOC_8_PLTOFF:
1051 case BFD_RELOC_16_PLTOFF:
1052 case BFD_RELOC_32_PLTOFF:
1055 case BFD_RELOC_VTABLE_INHERIT:
1056 case BFD_RELOC_VTABLE_ENTRY:
1064 #else /* !OBJ_ELF */
1066 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1068 /* PR gas/3041 Weak symbols are not relaxable
1069 because they must be treated as extern. */
1070 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1072 #endif /* OBJ_ELF */
1075 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1078 bfd_reloc_code_real_type code;
1080 /* If the tcbit is set, then this was a fixup of a negative value
1081 that was never resolved. We do not have a reloc to handle this,
1082 so just return. We assume that other code will have detected this
1083 situation and produced a helpful error message, so we just tell the
1084 user that the reloc cannot be produced. */
1088 as_bad_where (fixp->fx_file, fixp->fx_line,
1089 _("Unable to produce reloc against symbol '%s'"),
1090 S_GET_NAME (fixp->fx_addsy));
1094 if (fixp->fx_r_type != BFD_RELOC_NONE)
1096 code = fixp->fx_r_type;
1098 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1099 that fixup_segment converted a non-PC relative reloc into a
1100 PC relative reloc. In such a case, we need to convert the
1107 code = BFD_RELOC_8_PCREL;
1110 code = BFD_RELOC_16_PCREL;
1113 code = BFD_RELOC_32_PCREL;
1115 case BFD_RELOC_8_PCREL:
1116 case BFD_RELOC_16_PCREL:
1117 case BFD_RELOC_32_PCREL:
1118 case BFD_RELOC_8_GOT_PCREL:
1119 case BFD_RELOC_16_GOT_PCREL:
1120 case BFD_RELOC_32_GOT_PCREL:
1121 case BFD_RELOC_8_GOTOFF:
1122 case BFD_RELOC_16_GOTOFF:
1123 case BFD_RELOC_32_GOTOFF:
1124 case BFD_RELOC_8_PLT_PCREL:
1125 case BFD_RELOC_16_PLT_PCREL:
1126 case BFD_RELOC_32_PLT_PCREL:
1127 case BFD_RELOC_8_PLTOFF:
1128 case BFD_RELOC_16_PLTOFF:
1129 case BFD_RELOC_32_PLTOFF:
1132 as_bad_where (fixp->fx_file, fixp->fx_line,
1133 _("Cannot make %s relocation PC relative"),
1134 bfd_get_reloc_code_name (code));
1140 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1141 switch (F (fixp->fx_size, fixp->fx_pcrel))
1143 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1144 MAP (1, 0, BFD_RELOC_8);
1145 MAP (2, 0, BFD_RELOC_16);
1146 MAP (4, 0, BFD_RELOC_32);
1147 MAP (1, 1, BFD_RELOC_8_PCREL);
1148 MAP (2, 1, BFD_RELOC_16_PCREL);
1149 MAP (4, 1, BFD_RELOC_32_PCREL);
1157 reloc = (arelent *) xmalloc (sizeof (arelent));
1158 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1159 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1160 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1163 reloc->addend = fixp->fx_addnumber;
1164 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1166 && S_IS_WEAK (fixp->fx_addsy)
1167 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1168 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1169 to put the symbol offset into frags referencing a weak symbol. */
1170 reloc->addend = fixp->fx_addnumber
1171 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1175 if (!fixp->fx_pcrel)
1176 reloc->addend = fixp->fx_addnumber;
1178 reloc->addend = (section->vma
1179 /* Explicit sign extension in case char is
1181 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1182 + fixp->fx_addnumber
1183 + md_pcrel_from (fixp));
1186 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1187 assert (reloc->howto != 0);
1192 /* Handle of the OPCODE hash table. NULL means any use before
1193 m68k_ip_begin() will crash. */
1194 static struct hash_control *op_hash;
1196 /* Assemble an m68k instruction. */
1199 m68k_ip (char *instring)
1202 register struct m68k_op *opP;
1203 register const struct m68k_incant *opcode;
1204 register const char *s;
1205 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1206 char *pdot, *pdotmove;
1207 enum m68k_size siz1, siz2;
1211 struct m68k_op operands_backup[6];
1212 LITTLENUM_TYPE words[6];
1213 LITTLENUM_TYPE *wordp;
1214 unsigned long ok_arch = 0;
1216 if (*instring == ' ')
1217 instring++; /* Skip leading whitespace. */
1219 /* Scan up to end of operation-code, which MUST end in end-of-string
1220 or exactly 1 space. */
1222 for (p = instring; *p != '\0'; p++)
1232 the_ins.error = _("No operator");
1236 /* p now points to the end of the opcode name, probably whitespace.
1237 Make sure the name is null terminated by clobbering the
1238 whitespace, look it up in the hash table, then fix it back.
1239 Remove a dot, first, since the opcode tables have none. */
1242 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1243 *pdotmove = pdotmove[1];
1249 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1254 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1255 *pdotmove = pdotmove[-1];
1262 the_ins.error = _("Unknown operator");
1266 /* Found a legitimate opcode, start matching operands. */
1270 if (opcode->m_operands == 0)
1272 char *old = input_line_pointer;
1274 input_line_pointer = p;
1275 /* Ahh - it's a motorola style psuedo op. */
1276 mote_pseudo_table[opcode->m_opnum].poc_handler
1277 (mote_pseudo_table[opcode->m_opnum].poc_val);
1278 input_line_pointer = old;
1284 if (flag_mri && opcode->m_opnum == 0)
1286 /* In MRI mode, random garbage is allowed after an instruction
1287 which accepts no operands. */
1288 the_ins.args = opcode->m_operands;
1289 the_ins.numargs = opcode->m_opnum;
1290 the_ins.numo = opcode->m_codenum;
1291 the_ins.opcode[0] = getone (opcode);
1292 the_ins.opcode[1] = gettwo (opcode);
1296 for (opP = &the_ins.operands[0]; *p; opP++)
1298 p = crack_operand (p, opP);
1302 the_ins.error = opP->error;
1307 opsfound = opP - &the_ins.operands[0];
1309 /* This ugly hack is to support the floating pt opcodes in their
1310 standard form. Essentially, we fake a first enty of type COP#1 */
1311 if (opcode->m_operands[0] == 'I')
1315 for (n = opsfound; n > 0; --n)
1316 the_ins.operands[n] = the_ins.operands[n - 1];
1318 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1319 the_ins.operands[0].mode = CONTROL;
1320 the_ins.operands[0].reg = m68k_float_copnum;
1324 /* We've got the operands. Find an opcode that'll accept them. */
1327 /* If we didn't get the right number of ops, or we have no
1328 common model with this pattern then reject this pattern. */
1330 ok_arch |= opcode->m_arch;
1331 if (opsfound != opcode->m_opnum
1332 || ((opcode->m_arch & current_architecture) == 0))
1338 /* Make a copy of the operands of this insn so that
1339 we can modify them safely, should we want to. */
1340 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1341 for (i = 0; i < opsfound; i++)
1342 operands_backup[i] = the_ins.operands[i];
1344 for (s = opcode->m_operands, opP = &operands_backup[0];
1348 /* Warning: this switch is huge! */
1349 /* I've tried to organize the cases into this order:
1350 non-alpha first, then alpha by letter. Lower-case
1351 goes directly before uppercase counterpart. */
1352 /* Code with multiple case ...: gets sorted by the lowest
1353 case ... it belongs to. I hope this makes sense. */
1459 if (opP->reg == PC || opP->reg == ZPC)
1476 if (opP->reg == PC || opP->reg == ZPC)
1495 if (opP->reg == PC || opP->reg == ZPC)
1505 if (opP->mode != IMMED)
1507 else if (s[1] == 'b'
1508 && ! isvar (&opP->disp)
1509 && (opP->disp.exp.X_op != O_constant
1510 || ! isbyte (opP->disp.exp.X_add_number)))
1512 else if (s[1] == 'B'
1513 && ! isvar (&opP->disp)
1514 && (opP->disp.exp.X_op != O_constant
1515 || ! issbyte (opP->disp.exp.X_add_number)))
1517 else if (s[1] == 'w'
1518 && ! isvar (&opP->disp)
1519 && (opP->disp.exp.X_op != O_constant
1520 || ! isword (opP->disp.exp.X_add_number)))
1522 else if (s[1] == 'W'
1523 && ! isvar (&opP->disp)
1524 && (opP->disp.exp.X_op != O_constant
1525 || ! issword (opP->disp.exp.X_add_number)))
1531 if (opP->mode != IMMED)
1536 if (opP->mode == AREG
1537 || opP->mode == CONTROL
1538 || opP->mode == FPREG
1539 || opP->mode == IMMED
1540 || opP->mode == REGLST
1541 || (opP->mode != ABSL
1543 || opP->reg == ZPC)))
1548 if (opP->mode == CONTROL
1549 || opP->mode == FPREG
1550 || opP->mode == REGLST
1551 || opP->mode == IMMED
1552 || (opP->mode != ABSL
1554 || opP->reg == ZPC)))
1582 if (opP->mode == CONTROL
1583 || opP->mode == FPREG
1584 || opP->mode == REGLST)
1589 if (opP->mode != AINC)
1594 if (opP->mode != ADEC)
1644 if (opP->reg == PC || opP->reg == ZPC)
1665 case '~': /* For now! (JF FOO is this right?) */
1687 if (opP->mode != CONTROL
1688 || (opP->reg != TT0 && opP->reg != TT1))
1693 if (opP->mode != AREG)
1698 if (opP->mode != AINDR)
1703 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1704 && (opP->mode != DISP
1706 || opP->reg > ADDR7))
1711 if (opP->mode != ABSL
1713 && strncmp (instring, "jbsr", 4) == 0))
1736 if (opP->mode != CONTROL || opP->reg != CCR)
1741 if (opP->mode != DISP
1743 || opP->reg > ADDR7)
1748 if (opP->mode != DREG)
1753 if (opP->reg != ACC)
1758 if (opP->reg != ACC && opP->reg != ACC1
1759 && opP->reg != ACC2 && opP->reg != ACC3)
1764 if (opP->mode != FPREG)
1769 if (opP->reg != MACSR)
1774 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1779 if (opP->reg != MASK)
1784 if (opP->mode != CONTROL
1791 if (opP->mode != LSH && opP->mode != RSH)
1796 if (opP->mode != CONTROL
1798 || opP->reg > last_movec_reg
1803 const enum m68k_register *rp;
1805 for (rp = control_regs; *rp; rp++)
1807 if (*rp == opP->reg)
1809 /* In most CPUs RAMBAR refers to control reg
1810 c05 (RAMBAR1), but a few CPUs have it
1811 refer to c04 (RAMBAR0). */
1812 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1814 opP->reg = RAMBAR_ALT;
1824 if (opP->mode != IMMED)
1830 if (opP->mode == DREG
1831 || opP->mode == AREG
1832 || opP->mode == FPREG)
1841 opP->mask = 1 << (opP->reg - DATA0);
1844 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1847 opP->mask = 1 << (opP->reg - FP0 + 16);
1855 else if (opP->mode == CONTROL)
1864 opP->mask = 1 << 24;
1867 opP->mask = 1 << 25;
1870 opP->mask = 1 << 26;
1879 else if (opP->mode != REGLST)
1881 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1883 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1888 if (opP->mode != IMMED)
1890 else if (opP->disp.exp.X_op != O_constant
1891 || ! issbyte (opP->disp.exp.X_add_number))
1893 else if (! m68k_quick
1894 && instring[3] != 'q'
1895 && instring[4] != 'q')
1900 if (opP->mode != DREG
1901 && opP->mode != IMMED
1902 && opP->mode != ABSL)
1907 if (opP->mode != IMMED)
1909 else if (opP->disp.exp.X_op != O_constant
1910 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1912 else if (! m68k_quick
1913 && (strncmp (instring, "add", 3) == 0
1914 || strncmp (instring, "sub", 3) == 0)
1915 && instring[3] != 'q')
1920 if (opP->mode != DREG && opP->mode != AREG)
1925 if (opP->mode != AINDR
1926 && (opP->mode != BASE
1928 && opP->reg != ZADDR0)
1929 || opP->disp.exp.X_op != O_absent
1930 || ((opP->index.reg < DATA0
1931 || opP->index.reg > DATA7)
1932 && (opP->index.reg < ADDR0
1933 || opP->index.reg > ADDR7))
1934 || opP->index.size != SIZE_UNSPEC
1935 || opP->index.scale != 1))
1940 if (opP->mode != CONTROL
1941 || ! (opP->reg == FPI
1943 || opP->reg == FPC))
1948 if (opP->mode != CONTROL || opP->reg != SR)
1953 if (opP->mode != IMMED)
1955 else if (opP->disp.exp.X_op != O_constant
1956 || TRUNC (opP->disp.exp.X_add_number) > 7)
1961 if (opP->mode != CONTROL || opP->reg != USP)
1966 if (opP->mode != IMMED)
1968 else if (opP->disp.exp.X_op != O_constant
1969 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1970 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1975 if (opP->mode != IMMED)
1977 else if (opP->disp.exp.X_op != O_constant
1978 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1983 if (opP->mode != IMMED)
1985 else if (opP->disp.exp.X_op != O_constant
1986 || TRUNC (opP->disp.exp.X_add_number) > 511)
1990 /* JF these are out of order. We could put them
1991 in order if we were willing to put up with
1992 bunches of #ifdef m68851s in the code.
1994 Don't forget that you need these operands
1995 to use 68030 MMU instructions. */
1997 /* Memory addressing mode used by pflushr. */
1999 if (opP->mode == CONTROL
2000 || opP->mode == FPREG
2001 || opP->mode == DREG
2002 || opP->mode == AREG
2003 || opP->mode == REGLST)
2005 /* We should accept immediate operands, but they
2006 supposedly have to be quad word, and we don't
2007 handle that. I would like to see what a Motorola
2008 assembler does before doing something here. */
2009 if (opP->mode == IMMED)
2014 if (opP->mode != CONTROL
2015 || (opP->reg != SFC && opP->reg != DFC))
2020 if (opP->mode != CONTROL || opP->reg != TC)
2025 if (opP->mode != CONTROL || opP->reg != AC)
2030 if (opP->mode != CONTROL
2033 && opP->reg != SCC))
2038 if (opP->mode != CONTROL
2044 if (opP->mode != CONTROL
2047 && opP->reg != CRP))
2071 if (opP->mode != CONTROL
2072 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2073 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2078 if (opP->mode != CONTROL || opP->reg != PSR)
2083 if (opP->mode != CONTROL || opP->reg != PCSR)
2088 if (opP->mode != CONTROL
2097 if (opP->mode != ABSL)
2102 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2104 /* FIXME: kludge instead of fixing parser:
2105 upper/lower registers are *not* CONTROL
2106 registers, but ordinary ones. */
2107 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2108 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2115 if (!(opP->mode == AINDR
2116 || (opP->mode == DISP
2117 && !(opP->reg == PC || opP->reg == ZPC))))
2122 if (!(opP->mode == AINDR || opP->mode == DISP))
2134 /* Since we have found the correct instruction, copy
2135 in the modifications that we may have made. */
2137 for (i = 0; i < opsfound; i++)
2138 the_ins.operands[i] = operands_backup[i];
2144 opcode = opcode->m_next;
2149 && !(ok_arch & current_architecture))
2151 const struct m68k_cpu *cpu;
2154 char *buf = xmalloc (space + 1);
2158 the_ins.error = buf;
2159 /* Make sure there's a NUL at the end of the buffer -- strncpy
2160 won't write one when it runs out of buffer */
2162 #define APPEND(STRING) \
2163 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2165 APPEND (_("invalid instruction for this architecture; needs "));
2169 APPEND (_("ColdFire ISA_A"));
2172 APPEND (_("ColdFire hardware divide"));
2175 APPEND (_("ColdFire ISA_A+"));
2178 APPEND (_("ColdFire ISA_B"));
2181 APPEND (_("ColdFire fpu"));
2184 APPEND (_("M68K fpu"));
2187 APPEND (_("M68K mmu"));
2190 APPEND (_("68020 or higher"));
2193 APPEND (_("68000 or higher"));
2196 APPEND (_("68010 or higher"));
2204 for (cpu = m68k_cpus; cpu->name; cpu++)
2205 if (!cpu->alias && (cpu->arch & ok_arch))
2207 const struct m68k_cpu *alias;
2208 int seen_master = 0;
2214 for (alias = cpu; alias != m68k_cpus; alias--)
2215 if (alias[-1].alias >= 0)
2217 for (; !seen_master || alias->alias > 0; alias++)
2227 APPEND (alias->name);
2240 /* we ran out of space, so replace the end of the list
2245 strcpy (buf, " ...");
2249 the_ins.error = _("operands mismatch");
2256 /* Now assemble it. */
2257 the_ins.args = opcode->m_operands;
2258 the_ins.numargs = opcode->m_opnum;
2259 the_ins.numo = opcode->m_codenum;
2260 the_ins.opcode[0] = getone (opcode);
2261 the_ins.opcode[1] = gettwo (opcode);
2263 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2267 /* This switch is a doozy.
2268 Watch the first step; its a big one! */
2301 tmpreg = 0x3c; /* 7.4 */
2302 if (strchr ("bwl", s[1]))
2303 nextword = get_num (&opP->disp, 90);
2305 nextword = get_num (&opP->disp, 0);
2306 if (isvar (&opP->disp))
2307 add_fix (s[1], &opP->disp, 0, 0);
2311 if (!isbyte (nextword))
2312 opP->error = _("operand out of range");
2317 if (!isword (nextword))
2318 opP->error = _("operand out of range");
2323 if (!issword (nextword))
2324 opP->error = _("operand out of range");
2329 addword (nextword >> 16);
2356 /* We gotta put out some float. */
2357 if (op (&opP->disp) != O_big)
2362 /* Can other cases happen here? */
2363 if (op (&opP->disp) != O_constant)
2366 val = (valueT) offs (&opP->disp);
2370 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2371 val >>= LITTLENUM_NUMBER_OF_BITS;
2375 offs (&opP->disp) = gencnt;
2377 if (offs (&opP->disp) > 0)
2379 if (offs (&opP->disp) > baseo)
2381 as_warn (_("Bignum too big for %c format; truncated"),
2383 offs (&opP->disp) = baseo;
2385 baseo -= offs (&opP->disp);
2388 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2389 offs (&opP->disp)--;
2394 gen_to_words (words, baseo, (long) outro);
2395 for (wordp = words; baseo--; wordp++)
2399 tmpreg = opP->reg - DATA; /* 0.dreg */
2402 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2405 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2408 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2411 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2415 nextword = get_num (&opP->disp, 90);
2417 /* Convert mode 5 addressing with a zero offset into
2418 mode 2 addressing to reduce the instruction size by a
2420 if (! isvar (&opP->disp)
2422 && (opP->disp.size == SIZE_UNSPEC)
2423 && (opP->reg >= ADDR0)
2424 && (opP->reg <= ADDR7))
2426 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2431 && ! isvar (&opP->disp)
2434 opP->disp.exp.X_op = O_symbol;
2435 opP->disp.exp.X_add_symbol =
2436 section_symbol (absolute_section);
2439 /* Force into index mode. Hope this works. */
2441 /* We do the first bit for 32-bit displacements, and the
2442 second bit for 16 bit ones. It is possible that we
2443 should make the default be WORD instead of LONG, but
2444 I think that'd break GCC, so we put up with a little
2445 inefficiency for the sake of working output. */
2447 if (!issword (nextword)
2448 || (isvar (&opP->disp)
2449 && ((opP->disp.size == SIZE_UNSPEC
2450 && flag_short_refs == 0
2451 && cpu_of_arch (current_architecture) >= m68020
2452 && ! arch_coldfire_p (current_architecture))
2453 || opP->disp.size == SIZE_LONG)))
2455 if (cpu_of_arch (current_architecture) < m68020
2456 || arch_coldfire_p (current_architecture))
2458 _("displacement too large for this architecture; needs 68020 or higher");
2460 tmpreg = 0x3B; /* 7.3 */
2462 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2463 if (isvar (&opP->disp))
2467 if (opP->disp.size == SIZE_LONG
2469 /* If the displacement needs pic
2470 relocation it cannot be relaxed. */
2471 || opP->disp.pic_reloc != pic_none
2476 add_fix ('l', &opP->disp, 1, 2);
2480 add_frag (adds (&opP->disp),
2481 SEXT (offs (&opP->disp)),
2482 TAB (PCREL1632, SZ_UNDEF));
2489 add_fix ('l', &opP->disp, 0, 0);
2494 addword (nextword >> 16);
2499 tmpreg = 0x3A; /* 7.2 */
2501 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2503 if (isvar (&opP->disp))
2507 add_fix ('w', &opP->disp, 1, 0);
2510 add_fix ('w', &opP->disp, 0, 0);
2520 baseo = get_num (&opP->disp, 90);
2521 if (opP->mode == POST || opP->mode == PRE)
2522 outro = get_num (&opP->odisp, 90);
2523 /* Figure out the `addressing mode'.
2524 Also turn on the BASE_DISABLE bit, if needed. */
2525 if (opP->reg == PC || opP->reg == ZPC)
2527 tmpreg = 0x3b; /* 7.3 */
2528 if (opP->reg == ZPC)
2531 else if (opP->reg == 0)
2534 tmpreg = 0x30; /* 6.garbage */
2536 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2539 tmpreg = 0x30 + opP->reg - ZADDR0;
2542 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2544 siz1 = opP->disp.size;
2545 if (opP->mode == POST || opP->mode == PRE)
2546 siz2 = opP->odisp.size;
2550 /* Index register stuff. */
2551 if (opP->index.reg != 0
2552 && opP->index.reg >= DATA
2553 && opP->index.reg <= ADDR7)
2555 nextword |= (opP->index.reg - DATA) << 12;
2557 if (opP->index.size == SIZE_LONG
2558 || (opP->index.size == SIZE_UNSPEC
2559 && m68k_index_width_default == SIZE_LONG))
2562 if ((opP->index.scale != 1
2563 && cpu_of_arch (current_architecture) < m68020)
2564 || (opP->index.scale == 8
2565 && (arch_coldfire_p (current_architecture)
2566 && !arch_coldfire_fpu (current_architecture))))
2569 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2572 if (arch_coldfire_p (current_architecture)
2573 && opP->index.size == SIZE_WORD)
2574 opP->error = _("invalid index size for coldfire");
2576 switch (opP->index.scale)
2593 GET US OUT OF HERE! */
2595 /* Must be INDEX, with an index register. Address
2596 register cannot be ZERO-PC, and either :b was
2597 forced, or we know it will fit. For a 68000 or
2598 68010, force this mode anyways, because the
2599 larger modes aren't supported. */
2600 if (opP->mode == BASE
2601 && ((opP->reg >= ADDR0
2602 && opP->reg <= ADDR7)
2605 if (siz1 == SIZE_BYTE
2606 || cpu_of_arch (current_architecture) < m68020
2607 || arch_coldfire_p (current_architecture)
2608 || (siz1 == SIZE_UNSPEC
2609 && ! isvar (&opP->disp)
2610 && issbyte (baseo)))
2612 nextword += baseo & 0xff;
2614 if (isvar (&opP->disp))
2616 /* Do a byte relocation. If it doesn't
2617 fit (possible on m68000) let the
2618 fixup processing complain later. */
2620 add_fix ('B', &opP->disp, 1, 1);
2622 add_fix ('B', &opP->disp, 0, 0);
2624 else if (siz1 != SIZE_BYTE)
2626 if (siz1 != SIZE_UNSPEC)
2627 as_warn (_("Forcing byte displacement"));
2628 if (! issbyte (baseo))
2629 opP->error = _("byte displacement out of range");
2634 else if (siz1 == SIZE_UNSPEC
2636 && isvar (&opP->disp)
2637 && subs (&opP->disp) == NULL
2639 /* If the displacement needs pic
2640 relocation it cannot be relaxed. */
2641 && opP->disp.pic_reloc == pic_none
2645 /* The code in md_convert_frag_1 needs to be
2646 able to adjust nextword. Call frag_grow
2647 to ensure that we have enough space in
2648 the frag obstack to make all the bytes
2651 nextword += baseo & 0xff;
2653 add_frag (adds (&opP->disp),
2654 SEXT (offs (&opP->disp)),
2655 TAB (PCINDEX, SZ_UNDEF));
2663 nextword |= 0x40; /* No index reg. */
2664 if (opP->index.reg >= ZDATA0
2665 && opP->index.reg <= ZDATA7)
2666 nextword |= (opP->index.reg - ZDATA0) << 12;
2667 else if (opP->index.reg >= ZADDR0
2668 || opP->index.reg <= ZADDR7)
2669 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2672 /* It isn't simple. */
2674 if (cpu_of_arch (current_architecture) < m68020
2675 || arch_coldfire_p (current_architecture))
2677 _("invalid operand mode for this architecture; needs 68020 or higher");
2680 /* If the guy specified a width, we assume that it is
2681 wide enough. Maybe it isn't. If so, we lose. */
2685 if (isvar (&opP->disp)
2687 : ! issword (baseo))
2692 else if (! isvar (&opP->disp) && baseo == 0)
2701 as_warn (_(":b not permitted; defaulting to :w"));
2711 /* Figure out inner displacement stuff. */
2712 if (opP->mode == POST || opP->mode == PRE)
2714 if (cpu_of_arch (current_architecture) & cpu32)
2715 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2719 if (isvar (&opP->odisp)
2721 : ! issword (outro))
2726 else if (! isvar (&opP->odisp) && outro == 0)
2735 as_warn (_(":b not permitted; defaulting to :w"));
2744 if (opP->mode == POST
2745 && (nextword & 0x40) == 0)
2750 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2752 if (opP->reg == PC || opP->reg == ZPC)
2753 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2755 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2757 if (siz1 == SIZE_LONG)
2758 addword (baseo >> 16);
2759 if (siz1 != SIZE_UNSPEC)
2762 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2763 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2764 if (siz2 == SIZE_LONG)
2765 addword (outro >> 16);
2766 if (siz2 != SIZE_UNSPEC)
2772 nextword = get_num (&opP->disp, 90);
2773 switch (opP->disp.size)
2778 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2780 tmpreg = 0x38; /* 7.0 */
2784 if (isvar (&opP->disp)
2785 && !subs (&opP->disp)
2786 && adds (&opP->disp)
2788 /* If the displacement needs pic relocation it
2789 cannot be relaxed. */
2790 && opP->disp.pic_reloc == pic_none
2793 && !strchr ("~%&$?", s[0]))
2795 tmpreg = 0x3A; /* 7.2 */
2796 add_frag (adds (&opP->disp),
2797 SEXT (offs (&opP->disp)),
2798 TAB (ABSTOPCREL, SZ_UNDEF));
2801 /* Fall through into long. */
2803 if (isvar (&opP->disp))
2804 add_fix ('l', &opP->disp, 0, 0);
2806 tmpreg = 0x39;/* 7.1 mode */
2807 addword (nextword >> 16);
2812 as_bad (_("unsupported byte value; use a different suffix"));
2816 if (isvar (&opP->disp))
2817 add_fix ('w', &opP->disp, 0, 0);
2819 tmpreg = 0x38;/* 7.0 mode */
2827 as_bad (_("unknown/incorrect operand"));
2831 /* If s[0] is '4', then this is for the mac instructions
2832 that can have a trailing_ampersand set. If so, set 0x100
2833 bit on tmpreg so install_gen_operand can check for it and
2834 set the appropriate bit (word2, bit 5). */
2837 if (opP->trailing_ampersand)
2840 install_gen_operand (s[1], tmpreg);
2846 { /* JF: I hate floating point! */
2861 tmpreg = get_num (&opP->disp, tmpreg);
2862 if (isvar (&opP->disp))
2863 add_fix (s[1], &opP->disp, 0, 0);
2866 case 'b': /* Danger: These do no check for
2867 certain types of overflow.
2869 if (!isbyte (tmpreg))
2870 opP->error = _("out of range");
2871 insop (tmpreg, opcode);
2872 if (isvar (&opP->disp))
2873 the_ins.reloc[the_ins.nrel - 1].n =
2874 (opcode->m_codenum) * 2 + 1;
2877 if (!issbyte (tmpreg))
2878 opP->error = _("out of range");
2879 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2880 if (isvar (&opP->disp))
2881 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2884 if (!isword (tmpreg))
2885 opP->error = _("out of range");
2886 insop (tmpreg, opcode);
2887 if (isvar (&opP->disp))
2888 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2891 if (!issword (tmpreg))
2892 opP->error = _("out of range");
2893 insop (tmpreg, opcode);
2894 if (isvar (&opP->disp))
2895 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2898 /* Because of the way insop works, we put these two out
2900 insop (tmpreg, opcode);
2901 insop (tmpreg >> 16, opcode);
2902 if (isvar (&opP->disp))
2903 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2910 install_operand (s[1], tmpreg);
2921 install_operand (s[1], opP->reg - ADDR);
2925 tmpreg = get_num (&opP->disp, 90);
2930 add_fix ('B', &opP->disp, 1, -1);
2933 add_fix ('w', &opP->disp, 1, 0);
2938 the_ins.opcode[0] |= 0xff;
2939 add_fix ('l', &opP->disp, 1, 0);
2943 case 'g': /* Conditional branch */
2944 have_disp = HAVE_LONG_CALL (current_architecture);
2947 case 'b': /* Unconditional branch */
2948 have_disp = HAVE_LONG_BRANCH (current_architecture);
2951 case 's': /* Unconditional subroutine */
2952 have_disp = HAVE_LONG_CALL (current_architecture);
2955 if (subs (&opP->disp) /* We can't relax it. */
2957 /* If the displacement needs pic relocation it cannot be
2959 || opP->disp.pic_reloc != pic_none
2964 as_warn (_("Can't use long branches on this architecture"));
2968 /* This could either be a symbol, or an absolute
2969 address. If it's an absolute address, turn it into
2970 an absolute jump right here and keep it out of the
2972 if (adds (&opP->disp) == 0)
2974 if (the_ins.opcode[0] == 0x6000) /* jbra */
2975 the_ins.opcode[0] = 0x4EF9;
2976 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2977 the_ins.opcode[0] = 0x4EB9;
2980 the_ins.opcode[0] ^= 0x0100;
2981 the_ins.opcode[0] |= 0x0006;
2984 add_fix ('l', &opP->disp, 0, 0);
2990 /* Now we know it's going into the relaxer. Now figure
2991 out which mode. We try in this order of preference:
2992 long branch, absolute jump, byte/word branches only. */
2994 add_frag (adds (&opP->disp),
2995 SEXT (offs (&opP->disp)),
2996 TAB (BRANCHBWL, SZ_UNDEF));
2997 else if (! flag_keep_pcrel)
2999 if ((the_ins.opcode[0] == 0x6000)
3000 || (the_ins.opcode[0] == 0x6100))
3001 add_frag (adds (&opP->disp),
3002 SEXT (offs (&opP->disp)),
3003 TAB (BRABSJUNC, SZ_UNDEF));
3005 add_frag (adds (&opP->disp),
3006 SEXT (offs (&opP->disp)),
3007 TAB (BRABSJCOND, SZ_UNDEF));
3010 add_frag (adds (&opP->disp),
3011 SEXT (offs (&opP->disp)),
3012 TAB (BRANCHBW, SZ_UNDEF));
3015 if (isvar (&opP->disp))
3017 /* Check for DBcc instructions. We can relax them,
3018 but only if we have long branches and/or absolute
3020 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3021 && (HAVE_LONG_BRANCH (current_architecture)
3022 || ! flag_keep_pcrel))
3024 if (HAVE_LONG_BRANCH (current_architecture))
3025 add_frag (adds (&opP->disp),
3026 SEXT (offs (&opP->disp)),
3027 TAB (DBCCLBR, SZ_UNDEF));
3029 add_frag (adds (&opP->disp),
3030 SEXT (offs (&opP->disp)),
3031 TAB (DBCCABSJ, SZ_UNDEF));
3034 add_fix ('w', &opP->disp, 1, 0);
3038 case 'C': /* Fixed size LONG coproc branches. */
3039 add_fix ('l', &opP->disp, 1, 0);
3043 case 'c': /* Var size Coprocesssor branches. */
3044 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3046 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3047 add_fix ('l', &opP->disp, 1, 0);
3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
3054 TAB (FBRANCH, SZ_UNDEF));
3061 case 'C': /* Ignore it. */
3064 case 'd': /* JF this is a kludge. */
3065 install_operand ('s', opP->reg - ADDR);
3066 tmpreg = get_num (&opP->disp, 90);
3067 if (!issword (tmpreg))
3069 as_warn (_("Expression out of range, using 0"));
3076 install_operand (s[1], opP->reg - DATA);
3079 case 'e': /* EMAC ACCx, reg/reg. */
3080 install_operand (s[1], opP->reg - ACC);
3083 case 'E': /* Ignore it. */
3087 install_operand (s[1], opP->reg - FP0);
3090 case 'g': /* EMAC ACCEXTx. */
3091 install_operand (s[1], opP->reg - ACCEXT01);
3094 case 'G': /* Ignore it. */
3099 tmpreg = opP->reg - COP0;
3100 install_operand (s[1], tmpreg);
3103 case 'i': /* MAC/EMAC scale factor. */
3104 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3107 case 'J': /* JF foo. */
3247 install_operand (s[1], tmpreg);
3251 tmpreg = get_num (&opP->disp, 55);
3252 install_operand (s[1], tmpreg & 0x7f);
3259 if (tmpreg & 0x7FF0000)
3260 as_bad (_("Floating point register in register list"));
3261 insop (reverse_16_bits (tmpreg), opcode);
3265 if (tmpreg & 0x700FFFF)
3266 as_bad (_("Wrong register in floating-point reglist"));
3267 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3275 if (tmpreg & 0x7FF0000)
3276 as_bad (_("Floating point register in register list"));
3277 insop (tmpreg, opcode);
3279 else if (s[1] == '8')
3281 if (tmpreg & 0x0FFFFFF)
3282 as_bad (_("incorrect register in reglist"));
3283 install_operand (s[1], tmpreg >> 24);
3287 if (tmpreg & 0x700FFFF)
3288 as_bad (_("wrong register in floating-point reglist"));
3290 install_operand (s[1], tmpreg >> 16);
3295 install_operand (s[1], get_num (&opP->disp, 60));
3299 tmpreg = ((opP->mode == DREG)
3300 ? 0x20 + (int) (opP->reg - DATA)
3301 : (get_num (&opP->disp, 40) & 0x1F));
3302 install_operand (s[1], tmpreg);
3306 tmpreg = get_num (&opP->disp, 10);
3309 install_operand (s[1], tmpreg);
3313 /* This depends on the fact that ADDR registers are eight
3314 more than their corresponding DATA regs, so the result
3315 will have the ADDR_REG bit set. */
3316 install_operand (s[1], opP->reg - DATA);
3320 if (opP->mode == AINDR)
3321 install_operand (s[1], opP->reg - DATA);
3323 install_operand (s[1], opP->index.reg - DATA);
3327 if (opP->reg == FPI)
3329 else if (opP->reg == FPS)
3331 else if (opP->reg == FPC)
3335 install_operand (s[1], tmpreg);
3338 case 'S': /* Ignore it. */
3342 install_operand (s[1], get_num (&opP->disp, 30));
3345 case 'U': /* Ignore it. */
3364 as_fatal (_("failed sanity check"));
3365 } /* switch on cache token. */
3366 install_operand (s[1], tmpreg);
3369 /* JF: These are out of order, I fear. */
3382 install_operand (s[1], tmpreg);
3408 install_operand (s[1], tmpreg);
3412 if (opP->reg == VAL)
3431 install_operand (s[1], tmpreg);
3445 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3456 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3462 install_operand (s[1], tmpreg);
3465 know (opP->reg == PSR);
3468 know (opP->reg == PCSR);
3483 install_operand (s[1], tmpreg);
3486 tmpreg = get_num (&opP->disp, 20);
3487 install_operand (s[1], tmpreg);
3489 case '_': /* used only for move16 absolute 32-bit address. */
3490 if (isvar (&opP->disp))
3491 add_fix ('l', &opP->disp, 0, 0);
3492 tmpreg = get_num (&opP->disp, 90);
3493 addword (tmpreg >> 16);
3494 addword (tmpreg & 0xFFFF);
3497 install_operand (s[1], opP->reg - DATA0L);
3498 opP->reg -= (DATA0L);
3499 opP->reg &= 0x0F; /* remove upper/lower bit. */
3502 tmpreg = get_num (&opP->disp, 80);
3505 install_operand (s[1], tmpreg);
3508 tmpreg = get_num (&opP->disp, 10);
3509 install_operand (s[1], tmpreg - 1);
3512 tmpreg = get_num (&opP->disp, 65);
3513 install_operand (s[1], tmpreg);
3520 /* By the time whe get here (FINALLY) the_ins contains the complete
3521 instruction, ready to be emitted. . . */
3525 reverse_16_bits (int in)
3530 static int mask[16] =
3532 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3533 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3535 for (n = 0; n < 16; n++)
3538 out |= mask[15 - n];
3541 } /* reverse_16_bits() */
3544 reverse_8_bits (int in)
3549 static int mask[8] =
3551 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3554 for (n = 0; n < 8; n++)
3560 } /* reverse_8_bits() */
3562 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3563 (that value is chosen in the frag_var call in md_assemble). TYPE
3564 is the subtype of the frag to be generated; its primary type is
3565 rs_machine_dependent.
3567 The TYPE parameter is also used by md_convert_frag_1 and
3568 md_estimate_size_before_relax. The appropriate type of fixup will
3569 be emitted by md_convert_frag_1.
3571 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3573 install_operand (int mode, int val)
3578 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3581 the_ins.opcode[0] |= val << 9;
3584 the_ins.opcode[1] |= val << 9;
3587 the_ins.opcode[1] |= val << 12;
3590 the_ins.opcode[1] |= val << 6;
3593 the_ins.opcode[1] |= val;
3596 the_ins.opcode[2] |= val << 12;
3599 the_ins.opcode[2] |= val << 6;
3602 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3603 three words long! */
3605 the_ins.opcode[2] |= val;
3608 the_ins.opcode[1] |= val << 7;
3611 the_ins.opcode[1] |= val << 10;
3615 the_ins.opcode[1] |= val << 5;
3620 the_ins.opcode[1] |= (val << 10) | (val << 7);
3623 the_ins.opcode[1] |= (val << 12) | val;
3626 the_ins.opcode[0] |= val = 0xff;
3629 the_ins.opcode[0] |= val << 9;
3632 the_ins.opcode[1] |= val;
3635 the_ins.opcode[1] |= val;
3636 the_ins.numo++; /* What a hack. */
3639 the_ins.opcode[1] |= val << 4;
3647 the_ins.opcode[0] |= (val << 6);
3650 the_ins.opcode[1] = (val >> 16);
3651 the_ins.opcode[2] = val & 0xffff;
3654 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3655 the_ins.opcode[0] |= ((val & 0x7) << 9);
3656 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3658 case 'n': /* MAC/EMAC Rx on !load. */
3659 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3660 the_ins.opcode[0] |= ((val & 0x7) << 9);
3661 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3663 case 'o': /* MAC/EMAC Rx on load. */
3664 the_ins.opcode[1] |= val << 12;
3665 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3667 case 'M': /* MAC/EMAC Ry on !load. */
3668 the_ins.opcode[0] |= (val & 0xF);
3669 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3671 case 'N': /* MAC/EMAC Ry on load. */
3672 the_ins.opcode[1] |= (val & 0xF);
3673 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3676 the_ins.opcode[1] |= ((val != 1) << 10);
3679 the_ins.opcode[0] |= ((val & 0x3) << 9);
3682 the_ins.opcode[0] |= ((val & 0x3) << 0);
3684 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3685 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3686 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3688 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3689 the_ins.opcode[0] |= ((val & 0x1) << 7);
3690 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3693 the_ins.opcode[1] |= ((val & 0x3) << 9);
3696 the_ins.opcode[0] |= (val & 0x1) <<10;
3700 as_fatal (_("failed sanity check."));
3705 install_gen_operand (int mode, int val)
3709 case '/': /* Special for mask loads for mac/msac insns with
3710 possible mask; trailing_ampersend set in bit 8. */
3711 the_ins.opcode[0] |= (val & 0x3f);
3712 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3715 the_ins.opcode[0] |= val;
3718 /* This is a kludge!!! */
3719 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3728 the_ins.opcode[0] |= val;
3730 /* more stuff goes here. */
3732 as_fatal (_("failed sanity check."));
3736 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3737 then deal with the bitfield hack. */
3740 crack_operand (char *str, struct m68k_op *opP)
3742 register int parens;
3744 register char *beg_str;
3752 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3758 else if (*str == ')')
3762 opP->error = _("Extra )");
3768 if (flag_mri && *str == '\'')
3769 inquote = ! inquote;
3771 if (!*str && parens)
3773 opP->error = _("Missing )");
3778 if (m68k_ip_op (beg_str, opP) != 0)
3785 c = *++str; /* JF bitfield hack. */
3790 as_bad (_("Missing operand"));
3793 /* Detect MRI REG symbols and convert them to REGLSTs. */
3794 if (opP->mode == CONTROL && (int)opP->reg < 0)
3797 opP->mask = ~(int)opP->reg;
3804 /* This is the guts of the machine-dependent assembler. STR points to a
3805 machine dependent instruction. This function is supposed to emit
3806 the frags/bytes it assembles to.
3810 insert_reg (const char *regname, int regnum)
3815 #ifdef REGISTER_PREFIX
3816 if (!flag_reg_prefix_optional)
3818 buf[0] = REGISTER_PREFIX;
3819 strcpy (buf + 1, regname);
3824 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3825 &zero_address_frag));
3827 for (i = 0; regname[i]; i++)
3828 buf[i] = TOUPPER (regname[i]);
3831 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3832 &zero_address_frag));
3841 static const struct init_entry init_table[] =
3901 { "accext01", ACCEXT01 },
3902 { "accext23", ACCEXT23 },
3906 /* Control registers. */
3907 { "sfc", SFC }, /* Source Function Code. */
3909 { "dfc", DFC }, /* Destination Function Code. */
3911 { "cacr", CACR }, /* Cache Control Register. */
3912 { "caar", CAAR }, /* Cache Address Register. */
3914 { "usp", USP }, /* User Stack Pointer. */
3915 { "vbr", VBR }, /* Vector Base Register. */
3916 { "msp", MSP }, /* Master Stack Pointer. */
3917 { "isp", ISP }, /* Interrupt Stack Pointer. */
3919 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3920 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3921 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3922 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3924 /* 68ec040 versions of same */
3925 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3926 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3927 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3928 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3930 /* Coldfire versions of same. The ColdFire programmer's reference
3931 manual indicated that the order is 2,3,0,1, but Ken Rose
3932 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3933 { "acr0", ACR0 }, /* Access Control Unit 0. */
3934 { "acr1", ACR1 }, /* Access Control Unit 1. */
3935 { "acr2", ACR2 }, /* Access Control Unit 2. */
3936 { "acr3", ACR3 }, /* Access Control Unit 3. */
3938 { "tc", TC }, /* MMU Translation Control Register. */
3942 { "mmusr", MMUSR }, /* MMU Status Register. */
3943 { "srp", SRP }, /* User Root Pointer. */
3944 { "urp", URP }, /* Supervisor Root Pointer. */
3947 { "mmubar", MMUBAR },
3950 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3951 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3952 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3953 { "mbar", MBAR }, /* Module Base Address Register. */
3955 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3956 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3957 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3958 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3959 { "mpcr", MPCR }, /* mcfv4e registers. */
3960 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3961 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3962 { "asid", TC }, /* mcfv4e registers. */
3963 { "mmubar", BUSCR }, /* mcfv4e registers. */
3964 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3965 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3966 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3967 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3968 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3969 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3970 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3971 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3972 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3973 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3974 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3975 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3977 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3978 { "rambar", RAMBAR }, /* mcf528x registers. */
3980 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3982 { "cac", CAC }, /* fido registers. */
3983 { "mbb", MBB }, /* fido registers. */
3984 /* End of control registers. */
4018 /* 68ec030 versions of same. */
4021 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4024 /* Suppressed data and address registers. */
4042 /* Upper and lower data and address registers, used by macw and msacw. */
4083 init_regtable (void)
4086 for (i = 0; init_table[i].name; i++)
4087 insert_reg (init_table[i].name, init_table[i].number);
4091 md_assemble (char *str)
4098 int shorts_this_frag;
4101 if (!selected_cpu && !selected_arch)
4103 /* We've not selected an architecture yet. Set the default
4104 now. We do this lazily so that an initial .cpu or .arch directive
4106 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4107 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4112 /* In MRI mode, the instruction and operands are separated by a
4113 space. Anything following the operands is a comment. The label
4114 has already been removed. */
4122 for (s = str; *s != '\0'; s++)
4124 if ((*s == ' ' || *s == '\t') && ! inquote)
4142 inquote = ! inquote;
4147 memset (&the_ins, '\0', sizeof (the_ins));
4152 for (n = 0; n < the_ins.numargs; n++)
4153 if (the_ins.operands[n].error)
4155 er = the_ins.operands[n].error;
4161 as_bad (_("%s -- statement `%s' ignored"), er, str);
4165 /* If there is a current label, record that it marks an instruction. */
4166 if (current_label != NULL)
4168 current_label->text = 1;
4169 current_label = NULL;
4173 /* Tie dwarf2 debug info to the address at the start of the insn. */
4174 dwarf2_emit_insn (0);
4177 if (the_ins.nfrag == 0)
4179 /* No frag hacking involved; just put it out. */
4180 toP = frag_more (2 * the_ins.numo);
4181 fromP = &the_ins.opcode[0];
4182 for (m = the_ins.numo; m; --m)
4184 md_number_to_chars (toP, (long) (*fromP), 2);
4188 /* Put out symbol-dependent info. */
4189 for (m = 0; m < the_ins.nrel; m++)
4191 switch (the_ins.reloc[m].wid)
4210 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4211 the_ins.reloc[m].wid);
4214 fixP = fix_new_exp (frag_now,
4215 ((toP - frag_now->fr_literal)
4216 - the_ins.numo * 2 + the_ins.reloc[m].n),
4218 &the_ins.reloc[m].exp,
4219 the_ins.reloc[m].pcrel,
4220 get_reloc_code (n, the_ins.reloc[m].pcrel,
4221 the_ins.reloc[m].pic_reloc));
4222 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4223 if (the_ins.reloc[m].wid == 'B')
4224 fixP->fx_signed = 1;
4229 /* There's some frag hacking. */
4231 /* Calculate the max frag size. */
4234 wid = 2 * the_ins.fragb[0].fragoff;
4235 for (n = 1; n < the_ins.nfrag; n++)
4236 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4237 /* frag_var part. */
4239 /* Make sure the whole insn fits in one chunk, in particular that
4240 the var part is attached, as we access one byte before the
4241 variable frag for byte branches. */
4245 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4250 wid = 2 * the_ins.fragb[n].fragoff;
4252 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4253 toP = frag_more (wid);
4255 shorts_this_frag = 0;
4256 for (m = wid / 2; m; --m)
4258 md_number_to_chars (toP, (long) (*fromP), 2);
4263 for (m = 0; m < the_ins.nrel; m++)
4265 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4267 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4270 wid = the_ins.reloc[m].wid;
4273 the_ins.reloc[m].wid = 0;
4274 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4276 fixP = fix_new_exp (frag_now,
4277 ((toP - frag_now->fr_literal)
4278 - the_ins.numo * 2 + the_ins.reloc[m].n),
4280 &the_ins.reloc[m].exp,
4281 the_ins.reloc[m].pcrel,
4282 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4283 the_ins.reloc[m].pic_reloc));
4284 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4286 (void) frag_var (rs_machine_dependent, 10, 0,
4287 (relax_substateT) (the_ins.fragb[n].fragty),
4288 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4290 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4291 shorts_this_frag = 0;
4294 toP = frag_more (n * 2);
4297 md_number_to_chars (toP, (long) (*fromP), 2);
4303 for (m = 0; m < the_ins.nrel; m++)
4307 wid = the_ins.reloc[m].wid;
4310 the_ins.reloc[m].wid = 0;
4311 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4313 fixP = fix_new_exp (frag_now,
4314 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4315 - shorts_this_frag * 2),
4317 &the_ins.reloc[m].exp,
4318 the_ins.reloc[m].pcrel,
4319 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4320 the_ins.reloc[m].pic_reloc));
4321 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4325 /* Comparison function used by qsort to rank the opcode entries by name. */
4328 m68k_compare_opcode (const void * v1, const void * v2)
4330 struct m68k_opcode * op1, * op2;
4336 op1 = *(struct m68k_opcode **) v1;
4337 op2 = *(struct m68k_opcode **) v2;
4339 /* Compare the two names. If different, return the comparison.
4340 If the same, return the order they are in the opcode table. */
4341 ret = strcmp (op1->name, op2->name);
4352 const struct m68k_opcode *ins;
4353 struct m68k_incant *hack, *slak;
4354 const char *retval = 0; /* Empty string, or error msg text. */
4357 /* Set up hash tables with 68000 instructions.
4358 similar to what the vax assembler does. */
4359 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4360 a copy of it at runtime, adding in the information we want but isn't
4361 there. I think it'd be better to have an awk script hack the table
4362 at compile time. Or even just xstr the table and use it as-is. But
4363 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4368 flag_reg_prefix_optional = 1;
4370 if (! m68k_rel32_from_cmdline)
4374 /* First sort the opcode table into alphabetical order to seperate
4375 the order that the assembler wants to see the opcodes from the
4376 order that the disassembler wants to see them. */
4377 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4378 if (!m68k_sorted_opcodes)
4379 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4380 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4382 for (i = m68k_numopcodes; i--;)
4383 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4385 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4386 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4388 op_hash = hash_new ();
4390 obstack_begin (&robyn, 4000);
4391 for (i = 0; i < m68k_numopcodes; i++)
4393 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4396 ins = m68k_sorted_opcodes[i];
4398 /* We must enter all insns into the table, because .arch and
4399 .cpu directives can change things. */
4400 slak->m_operands = ins->args;
4401 slak->m_arch = ins->arch;
4402 slak->m_opcode = ins->opcode;
4404 /* In most cases we can determine the number of opcode words
4405 by checking the second word of the mask. Unfortunately
4406 some instructions have 2 opcode words, but no fixed bits
4407 in the second word. A leading dot in the operands
4408 string also indicates 2 opcodes. */
4409 if (*slak->m_operands == '.')
4412 slak->m_codenum = 2;
4414 else if (ins->match & 0xffffL)
4415 slak->m_codenum = 2;
4417 slak->m_codenum = 1;
4418 slak->m_opnum = strlen (slak->m_operands) / 2;
4420 if (i + 1 != m68k_numopcodes
4421 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4423 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4428 slak = slak->m_next;
4432 retval = hash_insert (op_hash, ins->name, (char *) hack);
4434 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4437 for (i = 0; i < m68k_numaliases; i++)
4439 const char *name = m68k_opcode_aliases[i].primary;
4440 const char *alias = m68k_opcode_aliases[i].alias;
4441 PTR val = hash_find (op_hash, name);
4444 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4445 retval = hash_insert (op_hash, alias, val);
4447 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4450 /* In MRI mode, all unsized branches are variable sized. Normally,
4451 they are word sized. */
4454 static struct m68k_opcode_alias mri_aliases[] =
4475 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4478 const char *name = mri_aliases[i].primary;
4479 const char *alias = mri_aliases[i].alias;
4480 PTR val = hash_find (op_hash, name);
4483 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4484 retval = hash_jam (op_hash, alias, val);
4486 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4490 for (i = 0; i < (int) sizeof (notend_table); i++)
4492 notend_table[i] = 0;
4493 alt_notend_table[i] = 0;
4496 notend_table[','] = 1;
4497 notend_table['{'] = 1;
4498 notend_table['}'] = 1;
4499 alt_notend_table['a'] = 1;
4500 alt_notend_table['A'] = 1;
4501 alt_notend_table['d'] = 1;
4502 alt_notend_table['D'] = 1;
4503 alt_notend_table['#'] = 1;
4504 alt_notend_table['&'] = 1;
4505 alt_notend_table['f'] = 1;
4506 alt_notend_table['F'] = 1;
4507 #ifdef REGISTER_PREFIX
4508 alt_notend_table[REGISTER_PREFIX] = 1;
4511 /* We need to put '(' in alt_notend_table to handle
4512 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4513 alt_notend_table['('] = 1;
4515 /* We need to put '@' in alt_notend_table to handle
4516 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4517 alt_notend_table['@'] = 1;
4519 /* We need to put digits in alt_notend_table to handle
4520 bfextu %d0{24:1},%d0 */
4521 alt_notend_table['0'] = 1;
4522 alt_notend_table['1'] = 1;
4523 alt_notend_table['2'] = 1;
4524 alt_notend_table['3'] = 1;
4525 alt_notend_table['4'] = 1;
4526 alt_notend_table['5'] = 1;
4527 alt_notend_table['6'] = 1;
4528 alt_notend_table['7'] = 1;
4529 alt_notend_table['8'] = 1;
4530 alt_notend_table['9'] = 1;
4532 #ifndef MIT_SYNTAX_ONLY
4533 /* Insert pseudo ops, these have to go into the opcode table since
4534 gas expects pseudo ops to start with a dot. */
4538 while (mote_pseudo_table[n].poc_name)
4540 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4541 hash_insert (op_hash,
4542 mote_pseudo_table[n].poc_name, (char *) hack);
4543 hack->m_operands = 0;
4553 record_alignment (text_section, 2);
4554 record_alignment (data_section, 2);
4555 record_alignment (bss_section, 2);
4560 /* This is called when a label is defined. */
4563 m68k_frob_label (symbolS *sym)
4565 struct label_line *n;
4567 n = (struct label_line *) xmalloc (sizeof *n);
4570 as_where (&n->file, &n->line);
4576 dwarf2_emit_label (sym);
4580 /* This is called when a value that is not an instruction is emitted. */
4583 m68k_flush_pending_output (void)
4585 current_label = NULL;
4588 /* This is called at the end of the assembly, when the final value of
4589 the label is known. We warn if this is a text symbol aligned at an
4593 m68k_frob_symbol (symbolS *sym)
4595 if (S_GET_SEGMENT (sym) == reg_section
4596 && (int) S_GET_VALUE (sym) < 0)
4598 S_SET_SEGMENT (sym, absolute_section);
4599 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4601 else if ((S_GET_VALUE (sym) & 1) != 0)
4603 struct label_line *l;
4605 for (l = labels; l != NULL; l = l->next)
4607 if (l->label == sym)
4610 as_warn_where (l->file, l->line,
4611 _("text label `%s' aligned to odd boundary"),
4619 /* This is called if we go in or out of MRI mode because of the .mri
4623 m68k_mri_mode_change (int on)
4627 if (! flag_reg_prefix_optional)
4629 flag_reg_prefix_optional = 1;
4630 #ifdef REGISTER_PREFIX
4635 if (! m68k_rel32_from_cmdline)
4640 if (! reg_prefix_optional_seen)
4642 #ifdef REGISTER_PREFIX_OPTIONAL
4643 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4645 flag_reg_prefix_optional = 0;
4647 #ifdef REGISTER_PREFIX
4652 if (! m68k_rel32_from_cmdline)
4657 /* Equal to MAX_PRECISION in atof-ieee.c. */
4658 #define MAX_LITTLENUMS 6
4660 /* Turn a string in input_line_pointer into a floating point constant
4661 of type TYPE, and store the appropriate bytes in *LITP. The number
4662 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4663 returned, or NULL on OK. */
4666 md_atof (int type, char *litP, int *sizeP)
4669 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4670 LITTLENUM_TYPE *wordP;
4701 return _("Bad call to MD_ATOF()");
4703 t = atof_ieee (input_line_pointer, type, words);
4705 input_line_pointer = t;
4707 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4708 for (wordP = words; prec--;)
4710 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4711 litP += sizeof (LITTLENUM_TYPE);
4717 md_number_to_chars (char *buf, valueT val, int n)
4719 number_to_chars_bigendian (buf, val, n);
4723 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4725 offsetT val = *valP;
4726 addressT upper_limit;
4727 offsetT lower_limit;
4729 /* This is unnecessary but it convinces the native rs6000 compiler
4730 to generate the code we want. */
4731 char *buf = fixP->fx_frag->fr_literal;
4732 buf += fixP->fx_where;
4733 /* End ibm compiler workaround. */
4737 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4743 memset (buf, 0, fixP->fx_size);
4744 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4746 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4747 && !S_IS_DEFINED (fixP->fx_addsy)
4748 && !S_IS_WEAK (fixP->fx_addsy))
4749 S_SET_WEAK (fixP->fx_addsy);
4752 #elif defined(OBJ_AOUT)
4753 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4754 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4756 memset (buf, 0, fixP->fx_size);
4757 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4762 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4763 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4766 switch (fixP->fx_size)
4768 /* The cast to offsetT below are necessary to make code
4769 correct for machines where ints are smaller than offsetT. */
4773 lower_limit = - (offsetT) 0x80;
4776 *buf++ = (val >> 8);
4778 upper_limit = 0x7fff;
4779 lower_limit = - (offsetT) 0x8000;
4782 *buf++ = (val >> 24);
4783 *buf++ = (val >> 16);
4784 *buf++ = (val >> 8);
4786 upper_limit = 0x7fffffff;
4787 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4790 BAD_CASE (fixP->fx_size);
4793 /* Fix up a negative reloc. */
4794 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4796 fixP->fx_addsy = fixP->fx_subsy;
4797 fixP->fx_subsy = NULL;
4801 /* For non-pc-relative values, it's conceivable we might get something
4802 like "0xff" for a byte field. So extend the upper part of the range
4803 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4804 so that we can do any range checking at all. */
4805 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4806 upper_limit = upper_limit * 2 + 1;
4808 if ((addressT) val > upper_limit
4809 && (val > 0 || val < lower_limit))
4810 as_bad_where (fixP->fx_file, fixP->fx_line,
4811 _("value %ld out of range"), (long)val);
4813 /* A one byte PC-relative reloc means a short branch. We can't use
4814 a short branch with a value of 0 or -1, because those indicate
4815 different opcodes (branches with longer offsets). fixup_segment
4816 in write.c may have clobbered fx_pcrel, so we need to examine the
4819 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4820 && fixP->fx_size == 1
4821 && (fixP->fx_addsy == NULL
4822 || S_IS_DEFINED (fixP->fx_addsy))
4823 && (val == 0 || val == -1))
4824 as_bad_where (fixP->fx_file, fixP->fx_line,
4825 _("invalid byte branch offset"));
4828 /* *fragP has been relaxed to its final size, and now needs to have
4829 the bytes inside it modified to conform to the new size There is UGLY
4833 md_convert_frag_1 (fragS *fragP)
4838 /* Address in object code of the displacement. */
4839 register int object_address = fragP->fr_fix + fragP->fr_address;
4841 /* Address in gas core of the place to store the displacement. */
4842 /* This convinces the native rs6000 compiler to generate the code we
4844 register char *buffer_address = fragP->fr_literal;
4845 buffer_address += fragP->fr_fix;
4846 /* End ibm compiler workaround. */
4848 /* The displacement of the address, from current location. */
4849 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4850 disp = (disp + fragP->fr_offset) - object_address;
4852 switch (fragP->fr_subtype)
4854 case TAB (BRANCHBWL, BYTE):
4855 case TAB (BRABSJUNC, BYTE):
4856 case TAB (BRABSJCOND, BYTE):
4857 case TAB (BRANCHBW, BYTE):
4858 know (issbyte (disp));
4860 as_bad_where (fragP->fr_file, fragP->fr_line,
4861 _("short branch with zero offset: use :w"));
4862 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4863 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4864 fixP->fx_pcrel_adjust = -1;
4866 case TAB (BRANCHBWL, SHORT):
4867 case TAB (BRABSJUNC, SHORT):
4868 case TAB (BRABSJCOND, SHORT):
4869 case TAB (BRANCHBW, SHORT):
4870 fragP->fr_opcode[1] = 0x00;
4871 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4872 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4875 case TAB (BRANCHBWL, LONG):
4876 fragP->fr_opcode[1] = (char) 0xFF;
4877 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4878 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4881 case TAB (BRABSJUNC, LONG):
4882 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4884 if (flag_keep_pcrel)
4885 as_bad_where (fragP->fr_file, fragP->fr_line,
4886 _("Conversion of PC relative BSR to absolute JSR"));
4887 fragP->fr_opcode[0] = 0x4E;
4888 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4889 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4890 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4893 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4895 if (flag_keep_pcrel)
4896 as_bad_where (fragP->fr_file, fragP->fr_line,
4897 _("Conversion of PC relative branch to absolute jump"));
4898 fragP->fr_opcode[0] = 0x4E;
4899 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4900 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4901 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4906 /* This cannot happen, because jbsr and jbra are the only two
4907 unconditional branches. */
4911 case TAB (BRABSJCOND, LONG):
4912 if (flag_keep_pcrel)
4913 as_bad_where (fragP->fr_file, fragP->fr_line,
4914 _("Conversion of PC relative conditional branch to absolute jump"));
4916 /* Only Bcc 68000 instructions can come here
4917 Change bcc into b!cc/jmp absl long. */
4918 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4919 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4921 /* JF: these used to be fr_opcode[2,3], but they may be in a
4922 different frag, in which case referring to them is a no-no.
4923 Only fr_opcode[0,1] are guaranteed to work. */
4924 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4925 *buffer_address++ = (char) 0xf9;
4926 fragP->fr_fix += 2; /* Account for jmp instruction. */
4927 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4928 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4931 case TAB (FBRANCH, SHORT):
4932 know ((fragP->fr_opcode[1] & 0x40) == 0);
4933 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4934 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4937 case TAB (FBRANCH, LONG):
4938 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4939 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4940 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4943 case TAB (DBCCLBR, SHORT):
4944 case TAB (DBCCABSJ, SHORT):
4945 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4946 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4949 case TAB (DBCCLBR, LONG):
4950 /* Only DBcc instructions can come here.
4951 Change dbcc into dbcc/bral.
4952 JF: these used to be fr_opcode[2-7], but that's wrong. */
4953 if (flag_keep_pcrel)
4954 as_bad_where (fragP->fr_file, fragP->fr_line,
4955 _("Conversion of DBcc to absolute jump"));
4957 *buffer_address++ = 0x00; /* Branch offset = 4. */
4958 *buffer_address++ = 0x04;
4959 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4960 *buffer_address++ = 0x06;
4961 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4962 *buffer_address++ = (char) 0xff;
4964 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4965 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4966 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4969 case TAB (DBCCABSJ, LONG):
4970 /* Only DBcc instructions can come here.
4971 Change dbcc into dbcc/jmp.
4972 JF: these used to be fr_opcode[2-7], but that's wrong. */
4973 if (flag_keep_pcrel)
4974 as_bad_where (fragP->fr_file, fragP->fr_line,
4975 _("Conversion of PC relative conditional branch to absolute jump"));
4977 *buffer_address++ = 0x00; /* Branch offset = 4. */
4978 *buffer_address++ = 0x04;
4979 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4980 *buffer_address++ = 0x06;
4981 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4982 *buffer_address++ = (char) 0xf9;
4984 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4985 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4986 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4989 case TAB (PCREL1632, SHORT):
4990 fragP->fr_opcode[1] &= ~0x3F;
4991 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4992 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4993 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4996 case TAB (PCREL1632, LONG):
4997 /* Already set to mode 7.3; this indicates: PC indirect with
4998 suppressed index, 32-bit displacement. */
4999 *buffer_address++ = 0x01;
5000 *buffer_address++ = 0x70;
5002 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5003 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5004 fixP->fx_pcrel_adjust = 2;
5007 case TAB (PCINDEX, BYTE):
5008 assert (fragP->fr_fix >= 2);
5009 buffer_address[-2] &= ~1;
5010 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5011 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5012 fixP->fx_pcrel_adjust = 1;
5014 case TAB (PCINDEX, SHORT):
5015 assert (fragP->fr_fix >= 2);
5016 buffer_address[-2] |= 0x1;
5017 buffer_address[-1] = 0x20;
5018 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5019 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5020 fixP->fx_pcrel_adjust = 2;
5023 case TAB (PCINDEX, LONG):
5024 assert (fragP->fr_fix >= 2);
5025 buffer_address[-2] |= 0x1;
5026 buffer_address[-1] = 0x30;
5027 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5029 fixP->fx_pcrel_adjust = 2;
5032 case TAB (ABSTOPCREL, SHORT):
5033 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5034 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5037 case TAB (ABSTOPCREL, LONG):
5038 if (flag_keep_pcrel)
5039 as_fatal (_("Conversion of PC relative displacement to absolute"));
5040 /* The thing to do here is force it to ABSOLUTE LONG, since
5041 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5042 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5044 fragP->fr_opcode[1] &= ~0x3F;
5045 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5046 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5047 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5053 fixP->fx_file = fragP->fr_file;
5054 fixP->fx_line = fragP->fr_line;
5059 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5060 segT sec ATTRIBUTE_UNUSED,
5063 md_convert_frag_1 (fragP);
5066 /* Force truly undefined symbols to their maximum size, and generally set up
5067 the frag list to be relaxed
5070 md_estimate_size_before_relax (fragS *fragP, segT segment)
5072 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5073 switch (fragP->fr_subtype)
5075 case TAB (BRANCHBWL, SZ_UNDEF):
5076 case TAB (BRABSJUNC, SZ_UNDEF):
5077 case TAB (BRABSJCOND, SZ_UNDEF):
5079 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5080 && relaxable_symbol (fragP->fr_symbol))
5082 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5084 else if (flag_short_refs)
5086 /* Symbol is undefined and we want short ref. */
5087 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5091 /* Symbol is still undefined. Make it LONG. */
5092 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5097 case TAB (BRANCHBW, SZ_UNDEF):
5099 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5100 && relaxable_symbol (fragP->fr_symbol))
5102 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5106 /* Symbol is undefined and we don't have long branches. */
5107 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5112 case TAB (FBRANCH, SZ_UNDEF):
5113 case TAB (DBCCLBR, SZ_UNDEF):
5114 case TAB (DBCCABSJ, SZ_UNDEF):
5115 case TAB (PCREL1632, SZ_UNDEF):
5117 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5118 && relaxable_symbol (fragP->fr_symbol))
5121 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5125 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5130 case TAB (PCINDEX, SZ_UNDEF):
5131 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5132 && relaxable_symbol (fragP->fr_symbol)))
5134 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5138 fragP->fr_subtype = TAB (PCINDEX, LONG);
5142 case TAB (ABSTOPCREL, SZ_UNDEF):
5144 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5145 && relaxable_symbol (fragP->fr_symbol)))
5147 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5151 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5160 /* Now that SZ_UNDEF are taken care of, check others. */
5161 switch (fragP->fr_subtype)
5163 case TAB (BRANCHBWL, BYTE):
5164 case TAB (BRABSJUNC, BYTE):
5165 case TAB (BRABSJCOND, BYTE):
5166 case TAB (BRANCHBW, BYTE):
5167 /* We can't do a short jump to the next instruction, so in that
5168 case we force word mode. If the symbol is at the start of a
5169 frag, and it is the next frag with any data in it (usually
5170 this is just the next frag, but assembler listings may
5171 introduce empty frags), we must use word mode. */
5172 if (fragP->fr_symbol)
5176 sym_frag = symbol_get_frag (fragP->fr_symbol);
5177 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5181 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5185 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5192 return md_relax_table[fragP->fr_subtype].rlx_length;
5195 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5196 /* the bit-field entries in the relocation_info struct plays hell
5197 with the byte-order problems of cross-assembly. So as a hack,
5198 I added this mach. dependent ri twiddler. Ugly, but it gets
5200 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5201 are symbolnum, most sig. byte first. Last byte is broken up with
5202 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5203 nibble as nuthin. (on Sun 3 at least) */
5204 /* Translate the internal relocation information into target-specific
5208 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5211 md_number_to_chars (the_bytes, ri->r_address, 4);
5212 /* Now the fun stuff. */
5213 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5214 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5215 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5216 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5217 | ((ri->r_length << 5) & 0x60)
5218 | ((ri->r_extern << 4) & 0x10));
5223 #endif /* OBJ_AOUT or OBJ_BOUT */
5225 #ifndef WORKING_DOT_WORD
5226 int md_short_jump_size = 4;
5227 int md_long_jump_size = 6;
5230 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5231 fragS *frag ATTRIBUTE_UNUSED,
5232 symbolS *to_symbol ATTRIBUTE_UNUSED)
5236 offset = to_addr - (from_addr + 2);
5238 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5239 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5243 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5244 fragS *frag, symbolS *to_symbol)
5248 if (!HAVE_LONG_BRANCH (current_architecture))
5250 if (flag_keep_pcrel)
5251 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5252 offset = to_addr - S_GET_VALUE (to_symbol);
5253 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5254 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5255 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5260 offset = to_addr - (from_addr + 2);
5261 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5262 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5268 /* Different values of OK tell what its OK to return. Things that
5269 aren't OK are an error (what a shock, no?)
5272 10: Absolute 1:8 only
5273 20: Absolute 0:7 only
5274 30: absolute 0:15 only
5275 40: Absolute 0:31 only
5276 50: absolute 0:127 only
5277 55: absolute -64:63 only
5278 60: absolute -128:127 only
5279 65: absolute 0:511 only
5280 70: absolute 0:4095 only
5281 80: absolute -1, 1:7 only
5285 get_num (struct m68k_exp *exp, int ok)
5287 if (exp->exp.X_op == O_absent)
5289 /* Do the same thing the VAX asm does. */
5290 op (exp) = O_constant;
5296 as_warn (_("expression out of range: defaulting to 1"));
5300 else if (exp->exp.X_op == O_constant)
5305 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5307 as_warn (_("expression out of range: defaulting to 1"));
5312 if ((valueT) TRUNC (offs (exp)) > 7)
5316 if ((valueT) TRUNC (offs (exp)) > 15)
5320 if ((valueT) TRUNC (offs (exp)) > 32)
5324 if ((valueT) TRUNC (offs (exp)) > 127)
5328 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5332 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5336 if ((valueT) TRUNC (offs (exp)) > 511)
5340 if ((valueT) TRUNC (offs (exp)) > 4095)
5343 as_warn (_("expression out of range: defaulting to 0"));
5348 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5349 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5351 as_warn (_("expression out of range: defaulting to 1"));
5359 else if (exp->exp.X_op == O_big)
5361 if (offs (exp) <= 0 /* flonum. */
5362 && (ok == 90 /* no bignums */
5363 || (ok > 10 /* Small-int ranges including 0 ok. */
5364 /* If we have a flonum zero, a zero integer should
5365 do as well (e.g., in moveq). */
5366 && generic_floating_point_number.exponent == 0
5367 && generic_floating_point_number.low[0] == 0)))
5369 /* HACK! Turn it into a long. */
5370 LITTLENUM_TYPE words[6];
5372 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5373 op (exp) = O_constant;
5376 offs (exp) = words[1] | (words[0] << 16);
5380 op (exp) = O_constant;
5383 offs (exp) = (ok == 10) ? 1 : 0;
5384 as_warn (_("Can't deal with expression; defaulting to %ld"),
5390 if (ok >= 10 && ok <= 80)
5392 op (exp) = O_constant;
5395 offs (exp) = (ok == 10) ? 1 : 0;
5396 as_warn (_("Can't deal with expression; defaulting to %ld"),
5401 if (exp->size != SIZE_UNSPEC)
5409 if (!isbyte (offs (exp)))
5410 as_warn (_("expression doesn't fit in BYTE"));
5413 if (!isword (offs (exp)))
5414 as_warn (_("expression doesn't fit in WORD"));
5422 /* These are the back-ends for the various machine dependent pseudo-ops. */
5425 s_data1 (int ignore ATTRIBUTE_UNUSED)
5427 subseg_set (data_section, 1);
5428 demand_empty_rest_of_line ();
5432 s_data2 (int ignore ATTRIBUTE_UNUSED)
5434 subseg_set (data_section, 2);
5435 demand_empty_rest_of_line ();
5439 s_bss (int ignore ATTRIBUTE_UNUSED)
5441 /* We don't support putting frags in the BSS segment, we fake it
5442 by marking in_bss, then looking at s_skip for clues. */
5444 subseg_set (bss_section, 0);
5445 demand_empty_rest_of_line ();
5449 s_even (int ignore ATTRIBUTE_UNUSED)
5452 register long temp_fill;
5454 temp = 1; /* JF should be 2? */
5455 temp_fill = get_absolute_expression ();
5456 if (!need_pass_2) /* Never make frag if expect extra pass. */
5457 frag_align (temp, (int) temp_fill, 0);
5458 demand_empty_rest_of_line ();
5459 record_alignment (now_seg, temp);
5463 s_proc (int ignore ATTRIBUTE_UNUSED)
5465 demand_empty_rest_of_line ();
5468 /* Pseudo-ops handled for MRI compatibility. */
5470 /* This function returns non-zero if the argument is a conditional
5471 pseudo-op. This is called when checking whether a pending
5472 alignment is needed. */
5475 m68k_conditional_pseudoop (pseudo_typeS *pop)
5477 return (pop->poc_handler == s_mri_if
5478 || pop->poc_handler == s_mri_else);
5481 /* Handle an MRI style chip specification. */
5490 s = input_line_pointer;
5491 /* We can't use get_symbol_end since the processor names are not proper
5493 while (is_part_of_name (c = *input_line_pointer++))
5495 *--input_line_pointer = 0;
5496 for (i = 0; m68k_cpus[i].name; i++)
5497 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5499 if (!m68k_cpus[i].name)
5501 as_bad (_("%s: unrecognized processor name"), s);
5502 *input_line_pointer = c;
5503 ignore_rest_of_line ();
5506 *input_line_pointer = c;
5508 if (*input_line_pointer == '/')
5509 current_architecture = 0;
5511 current_architecture &= m68881 | m68851;
5512 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5513 control_regs = m68k_cpus[i].control_regs;
5515 while (*input_line_pointer == '/')
5517 ++input_line_pointer;
5518 s = input_line_pointer;
5519 /* We can't use get_symbol_end since the processor names are not
5521 while (is_part_of_name (c = *input_line_pointer++))
5523 *--input_line_pointer = 0;
5524 if (strcmp (s, "68881") == 0)
5525 current_architecture |= m68881;
5526 else if (strcmp (s, "68851") == 0)
5527 current_architecture |= m68851;
5528 *input_line_pointer = c;
5532 /* The MRI CHIP pseudo-op. */
5535 s_chip (int ignore ATTRIBUTE_UNUSED)
5541 stop = mri_comment_field (&stopc);
5544 mri_comment_end (stop, stopc);
5545 demand_empty_rest_of_line ();
5548 /* The MRI FOPT pseudo-op. */
5551 s_fopt (int ignore ATTRIBUTE_UNUSED)
5555 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5559 input_line_pointer += 3;
5560 temp = get_absolute_expression ();
5561 if (temp < 0 || temp > 7)
5562 as_bad (_("bad coprocessor id"));
5564 m68k_float_copnum = COP0 + temp;
5568 as_bad (_("unrecognized fopt option"));
5569 ignore_rest_of_line ();
5573 demand_empty_rest_of_line ();
5576 /* The structure used to handle the MRI OPT pseudo-op. */
5580 /* The name of the option. */
5583 /* If this is not NULL, just call this function. The first argument
5584 is the ARG field of this structure, the second argument is
5585 whether the option was negated. */
5586 void (*pfn) (int arg, int on);
5588 /* If this is not NULL, and the PFN field is NULL, set the variable
5589 this points to. Set it to the ARG field if the option was not
5590 negated, and the NOTARG field otherwise. */
5593 /* The value to pass to PFN or to assign to *PVAR. */
5596 /* The value to assign to *PVAR if the option is negated. If PFN is
5597 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5598 the option may not be negated. */
5602 /* The table used to handle the MRI OPT pseudo-op. */
5604 static void skip_to_comma (int, int);
5605 static void opt_nest (int, int);
5606 static void opt_chip (int, int);
5607 static void opt_list (int, int);
5608 static void opt_list_symbols (int, int);
5610 static const struct opt_action opt_table[] =
5612 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5614 /* We do relaxing, so there is little use for these options. */
5615 { "b", 0, 0, 0, 0 },
5616 { "brs", 0, 0, 0, 0 },
5617 { "brb", 0, 0, 0, 0 },
5618 { "brl", 0, 0, 0, 0 },
5619 { "brw", 0, 0, 0, 0 },
5621 { "c", 0, 0, 0, 0 },
5622 { "cex", 0, 0, 0, 0 },
5623 { "case", 0, &symbols_case_sensitive, 1, 0 },
5624 { "cl", 0, 0, 0, 0 },
5625 { "cre", 0, 0, 0, 0 },
5626 { "d", 0, &flag_keep_locals, 1, 0 },
5627 { "e", 0, 0, 0, 0 },
5628 { "f", 0, &flag_short_refs, 1, 0 },
5629 { "frs", 0, &flag_short_refs, 1, 0 },
5630 { "frl", 0, &flag_short_refs, 0, 1 },
5631 { "g", 0, 0, 0, 0 },
5632 { "i", 0, 0, 0, 0 },
5633 { "m", 0, 0, 0, 0 },
5634 { "mex", 0, 0, 0, 0 },
5635 { "mc", 0, 0, 0, 0 },
5636 { "md", 0, 0, 0, 0 },
5637 { "nest", opt_nest, 0, 0, 0 },
5638 { "next", skip_to_comma, 0, 0, 0 },
5639 { "o", 0, 0, 0, 0 },
5640 { "old", 0, 0, 0, 0 },
5641 { "op", skip_to_comma, 0, 0, 0 },
5642 { "pco", 0, 0, 0, 0 },
5643 { "p", opt_chip, 0, 0, 0 },
5644 { "pcr", 0, 0, 0, 0 },
5645 { "pcs", 0, 0, 0, 0 },
5646 { "r", 0, 0, 0, 0 },
5647 { "quick", 0, &m68k_quick, 1, 0 },
5648 { "rel32", 0, &m68k_rel32, 1, 0 },
5649 { "s", opt_list, 0, 0, 0 },
5650 { "t", opt_list_symbols, 0, 0, 0 },
5651 { "w", 0, &flag_no_warnings, 0, 1 },
5655 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5657 /* The MRI OPT pseudo-op. */
5660 s_opt (int ignore ATTRIBUTE_UNUSED)
5668 const struct opt_action *o;
5673 if (*input_line_pointer == '-')
5675 ++input_line_pointer;
5678 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5680 input_line_pointer += 2;
5684 s = input_line_pointer;
5685 c = get_symbol_end ();
5687 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5689 if (strcasecmp (s, o->name) == 0)
5693 /* Restore input_line_pointer now in case the option
5695 *input_line_pointer = c;
5696 (*o->pfn) (o->arg, t);
5698 else if (o->pvar != NULL)
5700 if (! t && o->arg == o->notarg)
5701 as_bad (_("option `%s' may not be negated"), s);
5702 *input_line_pointer = c;
5703 *o->pvar = t ? o->arg : o->notarg;
5706 *input_line_pointer = c;
5712 as_bad (_("option `%s' not recognized"), s);
5713 *input_line_pointer = c;
5716 while (*input_line_pointer++ == ',');
5718 /* Move back to terminating character. */
5719 --input_line_pointer;
5720 demand_empty_rest_of_line ();
5723 /* Skip ahead to a comma. This is used for OPT options which we do
5724 not support and which take arguments. */
5727 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5729 while (*input_line_pointer != ','
5730 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5731 ++input_line_pointer;
5734 /* Handle the OPT NEST=depth option. */
5737 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5739 if (*input_line_pointer != '=')
5741 as_bad (_("bad format of OPT NEST=depth"));
5745 ++input_line_pointer;
5746 max_macro_nest = get_absolute_expression ();
5749 /* Handle the OPT P=chip option. */
5752 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5754 if (*input_line_pointer != '=')
5756 /* This is just OPT P, which we do not support. */
5760 ++input_line_pointer;
5764 /* Handle the OPT S option. */
5767 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5772 /* Handle the OPT T option. */
5775 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5778 listing |= LISTING_SYMBOLS;
5780 listing &= ~LISTING_SYMBOLS;
5783 /* Handle the MRI REG pseudo-op. */
5786 s_reg (int ignore ATTRIBUTE_UNUSED)
5795 if (line_label == NULL)
5797 as_bad (_("missing label"));
5798 ignore_rest_of_line ();
5803 stop = mri_comment_field (&stopc);
5807 s = input_line_pointer;
5808 while (ISALNUM (*input_line_pointer)
5809 #ifdef REGISTER_PREFIX
5810 || *input_line_pointer == REGISTER_PREFIX
5812 || *input_line_pointer == '/'
5813 || *input_line_pointer == '-')
5814 ++input_line_pointer;
5815 c = *input_line_pointer;
5816 *input_line_pointer = '\0';
5818 if (m68k_ip_op (s, &rop) != 0)
5820 if (rop.error == NULL)
5821 as_bad (_("bad register list"));
5823 as_bad (_("bad register list: %s"), rop.error);
5824 *input_line_pointer = c;
5825 ignore_rest_of_line ();
5829 *input_line_pointer = c;
5831 if (rop.mode == REGLST)
5833 else if (rop.mode == DREG)
5834 mask = 1 << (rop.reg - DATA0);
5835 else if (rop.mode == AREG)
5836 mask = 1 << (rop.reg - ADDR0 + 8);
5837 else if (rop.mode == FPREG)
5838 mask = 1 << (rop.reg - FP0 + 16);
5839 else if (rop.mode == CONTROL
5842 else if (rop.mode == CONTROL
5845 else if (rop.mode == CONTROL
5850 as_bad (_("bad register list"));
5851 ignore_rest_of_line ();
5855 S_SET_SEGMENT (line_label, reg_section);
5856 S_SET_VALUE (line_label, ~mask);
5857 symbol_set_frag (line_label, &zero_address_frag);
5860 mri_comment_end (stop, stopc);
5862 demand_empty_rest_of_line ();
5865 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5869 struct save_opts *next;
5871 int symbols_case_sensitive;
5875 const enum m68k_register *control_regs;
5880 /* FIXME: We don't save OPT S. */
5883 /* This variable holds the stack of saved options. */
5885 static struct save_opts *save_stack;
5887 /* The MRI SAVE pseudo-op. */
5890 s_save (int ignore ATTRIBUTE_UNUSED)
5892 struct save_opts *s;
5894 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5895 s->abspcadd = m68k_abspcadd;
5896 s->symbols_case_sensitive = symbols_case_sensitive;
5897 s->keep_locals = flag_keep_locals;
5898 s->short_refs = flag_short_refs;
5899 s->architecture = current_architecture;
5900 s->control_regs = control_regs;
5901 s->quick = m68k_quick;
5902 s->rel32 = m68k_rel32;
5903 s->listing = listing;
5904 s->no_warnings = flag_no_warnings;
5906 s->next = save_stack;
5909 demand_empty_rest_of_line ();
5912 /* The MRI RESTORE pseudo-op. */
5915 s_restore (int ignore ATTRIBUTE_UNUSED)
5917 struct save_opts *s;
5919 if (save_stack == NULL)
5921 as_bad (_("restore without save"));
5922 ignore_rest_of_line ();
5927 save_stack = s->next;
5929 m68k_abspcadd = s->abspcadd;
5930 symbols_case_sensitive = s->symbols_case_sensitive;
5931 flag_keep_locals = s->keep_locals;
5932 flag_short_refs = s->short_refs;
5933 current_architecture = s->architecture;
5934 control_regs = s->control_regs;
5935 m68k_quick = s->quick;
5936 m68k_rel32 = s->rel32;
5937 listing = s->listing;
5938 flag_no_warnings = s->no_warnings;
5942 demand_empty_rest_of_line ();
5945 /* Types of MRI structured control directives. */
5947 enum mri_control_type
5955 /* This structure is used to stack the MRI structured control
5958 struct mri_control_info
5960 /* The directive within which this one is enclosed. */
5961 struct mri_control_info *outer;
5963 /* The type of directive. */
5964 enum mri_control_type type;
5966 /* Whether an ELSE has been in an IF. */
5969 /* The add or sub statement at the end of a FOR. */
5972 /* The label of the top of a FOR or REPEAT loop. */
5975 /* The label to jump to for the next iteration, or the else
5976 expression of a conditional. */
5979 /* The label to jump to to break out of the loop, or the label past
5980 the end of a conditional. */
5984 /* The stack of MRI structured control directives. */
5986 static struct mri_control_info *mri_control_stack;
5988 /* The current MRI structured control directive index number, used to
5989 generate label names. */
5991 static int mri_control_index;
5993 /* Assemble an instruction for an MRI structured control directive. */
5996 mri_assemble (char *str)
6000 /* md_assemble expects the opcode to be in lower case. */
6001 for (s = str; *s != ' ' && *s != '\0'; s++)
6007 /* Generate a new MRI label structured control directive label name. */
6010 mri_control_label (void)
6014 n = (char *) xmalloc (20);
6015 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6016 ++mri_control_index;
6020 /* Create a new MRI structured control directive. */
6022 static struct mri_control_info *
6023 push_mri_control (enum mri_control_type type)
6025 struct mri_control_info *n;
6027 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6031 if (type == mri_if || type == mri_while)
6034 n->top = mri_control_label ();
6035 n->next = mri_control_label ();
6036 n->bottom = mri_control_label ();
6038 n->outer = mri_control_stack;
6039 mri_control_stack = n;
6044 /* Pop off the stack of MRI structured control directives. */
6047 pop_mri_control (void)
6049 struct mri_control_info *n;
6051 n = mri_control_stack;
6052 mri_control_stack = n->outer;
6060 /* Recognize a condition code in an MRI structured control expression. */
6063 parse_mri_condition (int *pcc)
6067 know (*input_line_pointer == '<');
6069 ++input_line_pointer;
6070 c1 = *input_line_pointer++;
6071 c2 = *input_line_pointer++;
6073 if (*input_line_pointer != '>')
6075 as_bad (_("syntax error in structured control directive"));
6079 ++input_line_pointer;
6085 *pcc = (c1 << 8) | c2;
6090 /* Parse a single operand in an MRI structured control expression. */
6093 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6094 char **rightstart, char **rightstop)
6106 if (*input_line_pointer == '<')
6108 /* It's just a condition code. */
6109 return parse_mri_condition (pcc);
6112 /* Look ahead for the condition code. */
6113 for (s = input_line_pointer; *s != '\0'; ++s)
6115 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6120 as_bad (_("missing condition code in structured control directive"));
6124 *leftstart = input_line_pointer;
6126 if (*leftstop > *leftstart
6127 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6130 input_line_pointer = s;
6131 if (! parse_mri_condition (pcc))
6134 /* Look ahead for AND or OR or end of line. */
6135 for (s = input_line_pointer; *s != '\0'; ++s)
6137 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6138 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6140 if ((s == input_line_pointer
6143 && ((strncasecmp (s, "AND", 3) == 0
6144 && (s[3] == '.' || ! is_part_of_name (s[3])))
6145 || (strncasecmp (s, "OR", 2) == 0
6146 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6150 *rightstart = input_line_pointer;
6152 if (*rightstop > *rightstart
6153 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6156 input_line_pointer = s;
6161 #define MCC(b1, b2) (((b1) << 8) | (b2))
6163 /* Swap the sense of a condition. This changes the condition so that
6164 it generates the same result when the operands are swapped. */
6167 swap_mri_condition (int cc)
6171 case MCC ('h', 'i'): return MCC ('c', 's');
6172 case MCC ('l', 's'): return MCC ('c', 'c');
6173 /* <HS> is an alias for <CC>. */
6174 case MCC ('h', 's'):
6175 case MCC ('c', 'c'): return MCC ('l', 's');
6176 /* <LO> is an alias for <CS>. */
6177 case MCC ('l', 'o'):
6178 case MCC ('c', 's'): return MCC ('h', 'i');
6179 case MCC ('p', 'l'): return MCC ('m', 'i');
6180 case MCC ('m', 'i'): return MCC ('p', 'l');
6181 case MCC ('g', 'e'): return MCC ('l', 'e');
6182 case MCC ('l', 't'): return MCC ('g', 't');
6183 case MCC ('g', 't'): return MCC ('l', 't');
6184 case MCC ('l', 'e'): return MCC ('g', 'e');
6185 /* Issue a warning for conditions we can not swap. */
6186 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6187 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6188 case MCC ('v', 'c'):
6189 case MCC ('v', 's'):
6191 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6192 (char) (cc >> 8), (char) (cc));
6198 /* Reverse the sense of a condition. */
6201 reverse_mri_condition (int cc)
6205 case MCC ('h', 'i'): return MCC ('l', 's');
6206 case MCC ('l', 's'): return MCC ('h', 'i');
6207 /* <HS> is an alias for <CC> */
6208 case MCC ('h', 's'): return MCC ('l', 'o');
6209 case MCC ('c', 'c'): return MCC ('c', 's');
6210 /* <LO> is an alias for <CS> */
6211 case MCC ('l', 'o'): return MCC ('h', 's');
6212 case MCC ('c', 's'): return MCC ('c', 'c');
6213 case MCC ('n', 'e'): return MCC ('e', 'q');
6214 case MCC ('e', 'q'): return MCC ('n', 'e');
6215 case MCC ('v', 'c'): return MCC ('v', 's');
6216 case MCC ('v', 's'): return MCC ('v', 'c');
6217 case MCC ('p', 'l'): return MCC ('m', 'i');
6218 case MCC ('m', 'i'): return MCC ('p', 'l');
6219 case MCC ('g', 'e'): return MCC ('l', 't');
6220 case MCC ('l', 't'): return MCC ('g', 'e');
6221 case MCC ('g', 't'): return MCC ('l', 'e');
6222 case MCC ('l', 'e'): return MCC ('g', 't');
6227 /* Build an MRI structured control expression. This generates test
6228 and branch instructions. It goes to TRUELAB if the condition is
6229 true, and to FALSELAB if the condition is false. Exactly one of
6230 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6231 is the size qualifier for the expression. EXTENT is the size to
6232 use for the branch. */
6235 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6236 char *rightstart, char *rightstop,
6237 const char *truelab, const char *falselab,
6243 if (leftstart != NULL)
6245 struct m68k_op leftop, rightop;
6248 /* Swap the compare operands, if necessary, to produce a legal
6249 m68k compare instruction. Comparing a register operand with
6250 a non-register operand requires the register to be on the
6251 right (cmp, cmpa). Comparing an immediate value with
6252 anything requires the immediate value to be on the left
6257 (void) m68k_ip_op (leftstart, &leftop);
6262 (void) m68k_ip_op (rightstart, &rightop);
6265 if (rightop.mode == IMMED
6266 || ((leftop.mode == DREG || leftop.mode == AREG)
6267 && (rightop.mode != DREG && rightop.mode != AREG)))
6271 /* Correct conditional handling:
6272 if #1 <lt> d0 then ;means if (1 < d0)
6278 cmp #1,d0 if we do *not* swap the operands
6279 bgt true we need the swapped condition!
6286 leftstart = rightstart;
6289 leftstop = rightstop;
6294 cc = swap_mri_condition (cc);
6298 if (truelab == NULL)
6300 cc = reverse_mri_condition (cc);
6304 if (leftstart != NULL)
6306 buf = (char *) xmalloc (20
6307 + (leftstop - leftstart)
6308 + (rightstop - rightstart));
6314 *s++ = TOLOWER (qual);
6316 memcpy (s, leftstart, leftstop - leftstart);
6317 s += leftstop - leftstart;
6319 memcpy (s, rightstart, rightstop - rightstart);
6320 s += rightstop - rightstart;
6326 buf = (char *) xmalloc (20 + strlen (truelab));
6332 *s++ = TOLOWER (extent);
6334 strcpy (s, truelab);
6339 /* Parse an MRI structured control expression. This generates test
6340 and branch instructions. STOP is where the expression ends. It
6341 goes to TRUELAB if the condition is true, and to FALSELAB if the
6342 condition is false. Exactly one of TRUELAB and FALSELAB will be
6343 NULL, meaning to fall through. QUAL is the size qualifier for the
6344 expression. EXTENT is the size to use for the branch. */
6347 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6348 const char *falselab, int extent)
6360 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361 &rightstart, &rightstop))
6367 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6371 if (falselab != NULL)
6374 flab = mri_control_label ();
6376 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6377 rightstop, (const char *) NULL, flab, extent);
6379 input_line_pointer += 3;
6380 if (*input_line_pointer != '.'
6381 || input_line_pointer[1] == '\0')
6385 qual = input_line_pointer[1];
6386 input_line_pointer += 2;
6389 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6390 &rightstart, &rightstop))
6396 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6397 rightstop, truelab, falselab, extent);
6399 if (falselab == NULL)
6402 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6406 if (truelab != NULL)
6409 tlab = mri_control_label ();
6411 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6412 rightstop, tlab, (const char *) NULL, extent);
6414 input_line_pointer += 2;
6415 if (*input_line_pointer != '.'
6416 || input_line_pointer[1] == '\0')
6420 qual = input_line_pointer[1];
6421 input_line_pointer += 2;
6424 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6425 &rightstart, &rightstop))
6431 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6432 rightstop, truelab, falselab, extent);
6434 if (truelab == NULL)
6439 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6440 rightstop, truelab, falselab, extent);
6444 if (input_line_pointer != stop)
6445 as_bad (_("syntax error in structured control directive"));
6448 /* Handle the MRI IF pseudo-op. This may be a structured control
6449 directive, or it may be a regular assembler conditional, depending
6457 struct mri_control_info *n;
6459 /* A structured control directive must end with THEN with an
6460 optional qualifier. */
6461 s = input_line_pointer;
6462 /* We only accept '*' as introduction of comments if preceded by white space
6463 or at first column of a line (I think this can't actually happen here?)
6464 This is important when assembling:
6465 if d0 <ne> 12(a0,d0*2) then
6466 if d0 <ne> #CONST*20 then. */
6467 while (! (is_end_of_line[(unsigned char) *s]
6470 && (s == input_line_pointer
6472 || *(s-1) == '\t'))))
6475 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6478 if (s - input_line_pointer > 1
6482 if (s - input_line_pointer < 3
6483 || strncasecmp (s - 3, "THEN", 4) != 0)
6487 as_bad (_("missing then"));
6488 ignore_rest_of_line ();
6492 /* It's a conditional. */
6497 /* Since this might be a conditional if, this pseudo-op will be
6498 called even if we are supported to be ignoring input. Double
6499 check now. Clobber *input_line_pointer so that ignore_input
6500 thinks that this is not a special pseudo-op. */
6501 c = *input_line_pointer;
6502 *input_line_pointer = 0;
6503 if (ignore_input ())
6505 *input_line_pointer = c;
6506 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6507 ++input_line_pointer;
6508 demand_empty_rest_of_line ();
6511 *input_line_pointer = c;
6513 n = push_mri_control (mri_if);
6515 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6516 n->next, s[1] == '.' ? s[2] : '\0');
6519 input_line_pointer = s + 3;
6521 input_line_pointer = s + 1;
6525 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6526 ++input_line_pointer;
6529 demand_empty_rest_of_line ();
6532 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6533 structured IF, associate the ELSE with the IF. Otherwise, assume
6534 it is a conditional else. */
6537 s_mri_else (int qual)
6544 && (mri_control_stack == NULL
6545 || mri_control_stack->type != mri_if
6546 || mri_control_stack->else_seen))
6552 c = *input_line_pointer;
6553 *input_line_pointer = 0;
6554 if (ignore_input ())
6556 *input_line_pointer = c;
6557 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6558 ++input_line_pointer;
6559 demand_empty_rest_of_line ();
6562 *input_line_pointer = c;
6564 if (mri_control_stack == NULL
6565 || mri_control_stack->type != mri_if
6566 || mri_control_stack->else_seen)
6568 as_bad (_("else without matching if"));
6569 ignore_rest_of_line ();
6573 mri_control_stack->else_seen = 1;
6575 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6576 q[0] = TOLOWER (qual);
6578 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6582 colon (mri_control_stack->next);
6586 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6587 ++input_line_pointer;
6590 demand_empty_rest_of_line ();
6593 /* Handle the MRI ENDI pseudo-op. */
6596 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6598 if (mri_control_stack == NULL
6599 || mri_control_stack->type != mri_if)
6601 as_bad (_("endi without matching if"));
6602 ignore_rest_of_line ();
6606 /* ignore_input will not return true for ENDI, so we don't need to
6607 worry about checking it again here. */
6609 if (! mri_control_stack->else_seen)
6610 colon (mri_control_stack->next);
6611 colon (mri_control_stack->bottom);
6617 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6618 ++input_line_pointer;
6621 demand_empty_rest_of_line ();
6624 /* Handle the MRI BREAK pseudo-op. */
6627 s_mri_break (int extent)
6629 struct mri_control_info *n;
6633 n = mri_control_stack;
6635 && n->type != mri_for
6636 && n->type != mri_repeat
6637 && n->type != mri_while)
6641 as_bad (_("break outside of structured loop"));
6642 ignore_rest_of_line ();
6646 buf = (char *) xmalloc (20 + strlen (n->bottom));
6647 ex[0] = TOLOWER (extent);
6649 sprintf (buf, "bra%s %s", ex, n->bottom);
6655 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6656 ++input_line_pointer;
6659 demand_empty_rest_of_line ();
6662 /* Handle the MRI NEXT pseudo-op. */
6665 s_mri_next (int extent)
6667 struct mri_control_info *n;
6671 n = mri_control_stack;
6673 && n->type != mri_for
6674 && n->type != mri_repeat
6675 && n->type != mri_while)
6679 as_bad (_("next outside of structured loop"));
6680 ignore_rest_of_line ();
6684 buf = (char *) xmalloc (20 + strlen (n->next));
6685 ex[0] = TOLOWER (extent);
6687 sprintf (buf, "bra%s %s", ex, n->next);
6693 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6694 ++input_line_pointer;
6697 demand_empty_rest_of_line ();
6700 /* Handle the MRI FOR pseudo-op. */
6703 s_mri_for (int qual)
6705 const char *varstart, *varstop;
6706 const char *initstart, *initstop;
6707 const char *endstart, *endstop;
6708 const char *bystart, *bystop;
6712 struct mri_control_info *n;
6718 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6722 varstart = input_line_pointer;
6724 /* Look for the '='. */
6725 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6726 && *input_line_pointer != '=')
6727 ++input_line_pointer;
6728 if (*input_line_pointer != '=')
6730 as_bad (_("missing ="));
6731 ignore_rest_of_line ();
6735 varstop = input_line_pointer;
6736 if (varstop > varstart
6737 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6740 ++input_line_pointer;
6742 initstart = input_line_pointer;
6744 /* Look for TO or DOWNTO. */
6747 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6749 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6750 && ! is_part_of_name (input_line_pointer[2]))
6752 initstop = input_line_pointer;
6753 input_line_pointer += 2;
6756 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6757 && ! is_part_of_name (input_line_pointer[6]))
6759 initstop = input_line_pointer;
6761 input_line_pointer += 6;
6764 ++input_line_pointer;
6766 if (initstop == NULL)
6768 as_bad (_("missing to or downto"));
6769 ignore_rest_of_line ();
6772 if (initstop > initstart
6773 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6777 endstart = input_line_pointer;
6779 /* Look for BY or DO. */
6782 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6784 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6785 && ! is_part_of_name (input_line_pointer[2]))
6787 endstop = input_line_pointer;
6789 input_line_pointer += 2;
6792 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6793 && (input_line_pointer[2] == '.'
6794 || ! is_part_of_name (input_line_pointer[2])))
6796 endstop = input_line_pointer;
6797 input_line_pointer += 2;
6800 ++input_line_pointer;
6802 if (endstop == NULL)
6804 as_bad (_("missing do"));
6805 ignore_rest_of_line ();
6808 if (endstop > endstart
6809 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6815 bystop = bystart + 2;
6820 bystart = input_line_pointer;
6824 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6826 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6827 && (input_line_pointer[2] == '.'
6828 || ! is_part_of_name (input_line_pointer[2])))
6830 bystop = input_line_pointer;
6831 input_line_pointer += 2;
6834 ++input_line_pointer;
6838 as_bad (_("missing do"));
6839 ignore_rest_of_line ();
6842 if (bystop > bystart
6843 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6847 if (*input_line_pointer != '.')
6851 extent = input_line_pointer[1];
6852 input_line_pointer += 2;
6855 /* We have fully parsed the FOR operands. Now build the loop. */
6856 n = push_mri_control (mri_for);
6858 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6860 /* Move init,var. */
6867 *s++ = TOLOWER (qual);
6869 memcpy (s, initstart, initstop - initstart);
6870 s += initstop - initstart;
6872 memcpy (s, varstart, varstop - varstart);
6873 s += varstop - varstart;
6885 *s++ = TOLOWER (qual);
6887 memcpy (s, endstart, endstop - endstart);
6888 s += endstop - endstart;
6890 memcpy (s, varstart, varstop - varstart);
6891 s += varstop - varstart;
6896 ex[0] = TOLOWER (extent);
6899 sprintf (buf, "blt%s %s", ex, n->bottom);
6901 sprintf (buf, "bgt%s %s", ex, n->bottom);
6904 /* Put together the add or sub instruction used by ENDF. */
6912 *s++ = TOLOWER (qual);
6914 memcpy (s, bystart, bystop - bystart);
6915 s += bystop - bystart;
6917 memcpy (s, varstart, varstop - varstart);
6918 s += varstop - varstart;
6924 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6925 ++input_line_pointer;
6928 demand_empty_rest_of_line ();
6931 /* Handle the MRI ENDF pseudo-op. */
6934 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6936 if (mri_control_stack == NULL
6937 || mri_control_stack->type != mri_for)
6939 as_bad (_("endf without for"));
6940 ignore_rest_of_line ();
6944 colon (mri_control_stack->next);
6946 mri_assemble (mri_control_stack->incr);
6948 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6949 mri_assemble (mri_control_stack->incr);
6951 free (mri_control_stack->incr);
6953 colon (mri_control_stack->bottom);
6959 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6960 ++input_line_pointer;
6963 demand_empty_rest_of_line ();
6966 /* Handle the MRI REPEAT pseudo-op. */
6969 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6971 struct mri_control_info *n;
6973 n = push_mri_control (mri_repeat);
6977 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6978 ++input_line_pointer;
6980 demand_empty_rest_of_line ();
6983 /* Handle the MRI UNTIL pseudo-op. */
6986 s_mri_until (int qual)
6990 if (mri_control_stack == NULL
6991 || mri_control_stack->type != mri_repeat)
6993 as_bad (_("until without repeat"));
6994 ignore_rest_of_line ();
6998 colon (mri_control_stack->next);
7000 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7003 parse_mri_control_expression (s, qual, (const char *) NULL,
7004 mri_control_stack->top, '\0');
7006 colon (mri_control_stack->bottom);
7008 input_line_pointer = s;
7014 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7015 ++input_line_pointer;
7018 demand_empty_rest_of_line ();
7021 /* Handle the MRI WHILE pseudo-op. */
7024 s_mri_while (int qual)
7028 struct mri_control_info *n;
7030 s = input_line_pointer;
7031 /* We only accept '*' as introduction of comments if preceded by white space
7032 or at first column of a line (I think this can't actually happen here?)
7033 This is important when assembling:
7034 while d0 <ne> 12(a0,d0*2) do
7035 while d0 <ne> #CONST*20 do. */
7036 while (! (is_end_of_line[(unsigned char) *s]
7039 && (s == input_line_pointer
7041 || *(s-1) == '\t'))))
7044 while (*s == ' ' || *s == '\t')
7046 if (s - input_line_pointer > 1
7049 if (s - input_line_pointer < 2
7050 || strncasecmp (s - 1, "DO", 2) != 0)
7052 as_bad (_("missing do"));
7053 ignore_rest_of_line ();
7057 n = push_mri_control (mri_while);
7061 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7062 s[1] == '.' ? s[2] : '\0');
7064 input_line_pointer = s + 1;
7065 if (*input_line_pointer == '.')
7066 input_line_pointer += 2;
7070 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7071 ++input_line_pointer;
7074 demand_empty_rest_of_line ();
7077 /* Handle the MRI ENDW pseudo-op. */
7080 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7084 if (mri_control_stack == NULL
7085 || mri_control_stack->type != mri_while)
7087 as_bad (_("endw without while"));
7088 ignore_rest_of_line ();
7092 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7093 sprintf (buf, "bra %s", mri_control_stack->next);
7097 colon (mri_control_stack->bottom);
7103 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7104 ++input_line_pointer;
7107 demand_empty_rest_of_line ();
7110 /* Parse a .cpu directive. */
7113 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7120 as_bad (_("already assembled instructions"));
7121 ignore_rest_of_line ();
7125 name = input_line_pointer;
7126 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7127 input_line_pointer++;
7128 saved_char = *input_line_pointer;
7129 *input_line_pointer = 0;
7131 m68k_set_cpu (name, 1, 0);
7133 *input_line_pointer = saved_char;
7134 demand_empty_rest_of_line ();
7138 /* Parse a .arch directive. */
7141 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7148 as_bad (_("already assembled instructions"));
7149 ignore_rest_of_line ();
7153 name = input_line_pointer;
7154 while (*input_line_pointer && *input_line_pointer != ','
7155 && !ISSPACE (*input_line_pointer))
7156 input_line_pointer++;
7157 saved_char = *input_line_pointer;
7158 *input_line_pointer = 0;
7160 if (m68k_set_arch (name, 1, 0))
7162 /* Scan extensions. */
7165 *input_line_pointer++ = saved_char;
7166 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7168 name = input_line_pointer;
7169 while (*input_line_pointer && *input_line_pointer != ','
7170 && !ISSPACE (*input_line_pointer))
7171 input_line_pointer++;
7172 saved_char = *input_line_pointer;
7173 *input_line_pointer = 0;
7175 while (m68k_set_extension (name, 1, 0));
7178 *input_line_pointer = saved_char;
7179 demand_empty_rest_of_line ();
7183 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7184 if none is found, the caller is responsible for emitting an error
7185 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7186 cpu name, if it begins with a '6' (possibly skipping an intervening
7187 'c'. We also allow a 'c' in the same place. if NEGATED is
7188 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7189 the option is indeed negated. */
7191 static const struct m68k_cpu *
7192 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7193 int allow_m, int *negated)
7195 /* allow negated value? */
7200 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7207 /* Remove 'm' or 'mc' prefix from 68k variants. */
7214 else if (arg[1] == 'c' && arg[2] == '6')
7218 else if (arg[0] == 'c' && arg[1] == '6')
7221 for (; table->name; table++)
7222 if (!strcmp (arg, table->name))
7224 if (table->alias < -1 || table->alias > 1)
7225 as_bad (_("`%s' is deprecated, use `%s'"),
7226 table->name, table[table->alias < 0 ? 1 : -1].name);
7232 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7235 m68k_set_cpu (char const *name, int allow_m, int silent)
7237 const struct m68k_cpu *cpu;
7239 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7244 as_bad (_("cpu `%s' unrecognized"), name);
7248 if (selected_cpu && selected_cpu != cpu)
7250 as_bad (_("already selected `%s' processor"),
7251 selected_cpu->name);
7258 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7261 m68k_set_arch (char const *name, int allow_m, int silent)
7263 const struct m68k_cpu *arch;
7265 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7270 as_bad (_("architecture `%s' unrecognized"), name);
7274 if (selected_arch && selected_arch != arch)
7276 as_bad (_("already selected `%s' architecture"),
7277 selected_arch->name);
7281 selected_arch = arch;
7285 /* Set the architecture extension, issuing errors if it is
7286 unrecognized, or invalid */
7289 m68k_set_extension (char const *name, int allow_m, int silent)
7292 const struct m68k_cpu *ext;
7294 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7299 as_bad (_("extension `%s' unrecognized"), name);
7304 not_current_architecture |= ext->arch;
7306 current_architecture |= ext->arch;
7311 Invocation line includes a switch not recognized by the base assembler.
7315 const char *md_shortopts = "lSA:m:kQ:V";
7317 const char *md_shortopts = "lSA:m:k";
7320 struct option md_longopts[] = {
7321 #define OPTION_PIC (OPTION_MD_BASE)
7322 {"pic", no_argument, NULL, OPTION_PIC},
7323 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7324 {"register-prefix-optional", no_argument, NULL,
7325 OPTION_REGISTER_PREFIX_OPTIONAL},
7326 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7327 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7328 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7329 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7330 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7331 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7332 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7333 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7334 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7335 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7336 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7337 {"pcrel", no_argument, NULL, OPTION_PCREL},
7338 {NULL, no_argument, NULL, 0}
7340 size_t md_longopts_size = sizeof (md_longopts);
7343 md_parse_option (int c, char *arg)
7347 case 'l': /* -l means keep external to 2 bit offset
7348 rather than 16 bit one. */
7349 flag_short_refs = 1;
7352 case 'S': /* -S means that jbsr's always turn into
7354 flag_long_jumps = 1;
7357 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7358 branches into absolute jumps. */
7359 flag_keep_pcrel = 1;
7365 break; /* -pic, Position Independent Code. */
7367 case OPTION_REGISTER_PREFIX_OPTIONAL:
7368 flag_reg_prefix_optional = 1;
7369 reg_prefix_optional_seen = 1;
7372 /* -V: SVR4 argument to print version ID. */
7374 print_version_id ();
7377 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7378 should be emitted or not. FIXME: Not implemented. */
7382 case OPTION_BITWISE_OR:
7387 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7389 for (s = m68k_comment_chars; *s != '\0'; s++)
7393 m68k_comment_chars = n;
7397 case OPTION_BASE_SIZE_DEFAULT_16:
7398 m68k_index_width_default = SIZE_WORD;
7401 case OPTION_BASE_SIZE_DEFAULT_32:
7402 m68k_index_width_default = SIZE_LONG;
7405 case OPTION_DISP_SIZE_DEFAULT_16:
7407 m68k_rel32_from_cmdline = 1;
7410 case OPTION_DISP_SIZE_DEFAULT_32:
7412 m68k_rel32_from_cmdline = 1;
7417 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7420 /* Intentional fall-through. */
7422 if (!strncmp (arg, "arch=", 5))
7423 m68k_set_arch (arg + 5, 1, 0);
7424 else if (!strncmp (arg, "cpu=", 4))
7425 m68k_set_cpu (arg + 4, 1, 0);
7426 else if (m68k_set_extension (arg, 0, 1))
7428 else if (m68k_set_arch (arg, 0, 1))
7430 else if (m68k_set_cpu (arg, 0, 1))
7443 /* Setup tables from the selected arch and/or cpu */
7446 m68k_init_arch (void)
7448 if (not_current_architecture & current_architecture)
7450 as_bad (_("architecture features both enabled and disabled"));
7451 not_current_architecture &= ~current_architecture;
7455 current_architecture |= selected_arch->arch;
7456 control_regs = selected_arch->control_regs;
7459 current_architecture |= selected_cpu->arch;
7461 current_architecture &= ~not_current_architecture;
7463 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7465 /* Determine which float is really meant. */
7466 if (current_architecture & (m68k_mask & ~m68881))
7467 current_architecture ^= cfloat;
7469 current_architecture ^= m68881;
7474 control_regs = selected_cpu->control_regs;
7475 if (current_architecture & ~selected_cpu->arch)
7477 as_bad (_("selected processor does not have all features of selected architecture"));
7478 current_architecture
7479 = selected_cpu->arch & ~not_current_architecture;
7483 if ((current_architecture & m68k_mask)
7484 && (current_architecture & ~m68k_mask))
7486 as_bad (_ ("m68k and cf features both selected"));
7487 if (current_architecture & m68k_mask)
7488 current_architecture &= m68k_mask;
7490 current_architecture &= ~m68k_mask;
7493 /* Permit m68881 specification with all cpus; those that can't work
7494 with a coprocessor could be doing emulation. */
7495 if (current_architecture & m68851)
7497 if (current_architecture & m68040)
7498 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7500 /* What other incompatibilities could we check for? */
7502 if (cpu_of_arch (current_architecture) < m68020
7503 || arch_coldfire_p (current_architecture))
7504 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7510 md_show_usage (FILE *stream)
7512 const char *default_cpu = TARGET_CPU;
7514 unsigned int default_arch;
7516 /* Get the canonical name for the default target CPU. */
7517 if (*default_cpu == 'm')
7519 for (i = 0; m68k_cpus[i].name; i++)
7521 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7523 default_arch = m68k_cpus[i].arch;
7524 while (m68k_cpus[i].alias > 0)
7526 while (m68k_cpus[i].alias < 0)
7528 default_cpu = m68k_cpus[i].name;
7532 fprintf (stream, _("\
7533 -march=<arch> set architecture\n\
7534 -mcpu=<cpu> set cpu [default %s]\n\
7536 for (i = 0; m68k_extensions[i].name; i++)
7537 fprintf (stream, _("\
7538 -m[no-]%-16s enable/disable%s architecture extension\n\
7539 "), m68k_extensions[i].name,
7540 m68k_extensions[i].alias > 0 ? " ColdFire"
7541 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7543 fprintf (stream, _("\
7544 -l use 1 word for refs to undefined symbols [default 2]\n\
7545 -pic, -k generate position independent code\n\
7546 -S turn jbsr into jsr\n\
7547 --pcrel never turn PC-relative branches into absolute jumps\n\
7548 --register-prefix-optional\n\
7549 recognize register names without prefix character\n\
7550 --bitwise-or do not treat `|' as a comment character\n\
7551 --base-size-default-16 base reg without size is 16 bits\n\
7552 --base-size-default-32 base reg without size is 32 bits (default)\n\
7553 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7554 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7557 fprintf (stream, _("Architecture variants are: "));
7558 for (i = 0; m68k_archs[i].name; i++)
7561 fprintf (stream, " | ");
7562 fprintf (stream, m68k_archs[i].name);
7564 fprintf (stream, "\n");
7566 fprintf (stream, _("Processor variants are: "));
7567 for (i = 0; m68k_cpus[i].name; i++)
7570 fprintf (stream, " | ");
7571 fprintf (stream, m68k_cpus[i].name);
7573 fprintf (stream, _("\n"));
7578 /* TEST2: Test md_assemble() */
7579 /* Warning, this routine probably doesn't work anymore. */
7583 struct m68k_it the_ins;
7591 if (!gets (buf) || !*buf)
7593 if (buf[0] == '|' || buf[1] == '.')
7595 for (cp = buf; *cp; cp++)
7600 memset (&the_ins, '\0', sizeof (the_ins));
7601 m68k_ip (&the_ins, buf);
7604 printf (_("Error %s in %s\n"), the_ins.error, buf);
7608 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7609 for (n = 0; n < the_ins.numo; n++)
7610 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7612 print_the_insn (&the_ins.opcode[0], stdout);
7613 (void) putchar ('\n');
7615 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7617 if (the_ins.operands[n].error)
7619 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7622 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7623 the_ins.operands[n].reg);
7624 if (the_ins.operands[n].b_const)
7625 printf ("Constant: '%.*s', ",
7626 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7627 the_ins.operands[n].b_const);
7628 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7629 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7630 if (the_ins.operands[n].b_iadd)
7631 printf ("Iadd: '%.*s',",
7632 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7633 the_ins.operands[n].b_iadd);
7642 is_label (char *str)
7646 while (*str && *str != ' ')
7648 if (str[-1] == ':' || str[1] == '=')
7655 /* Possible states for relaxation:
7657 0 0 branch offset byte (bra, etc)
7661 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7665 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7672 /* We have no need to default values of symbols. */
7675 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7680 /* Round up a section size to the appropriate boundary. */
7682 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7685 /* For a.out, force the section size to be aligned. If we don't do
7686 this, BFD will align it for us, but it will not write out the
7687 final bytes of the section. This may be a bug in BFD, but it is
7688 easier to fix it here since that is how the other a.out targets
7692 align = bfd_get_section_alignment (stdoutput, segment);
7693 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7699 /* Exactly what point is a PC-relative offset relative TO?
7700 On the 68k, it is relative to the address of the first extension
7701 word. The difference between the addresses of the offset and the
7702 first extension word is stored in fx_pcrel_adjust. */
7704 md_pcrel_from (fixS *fixP)
7708 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7709 sign extend the value here. */
7710 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7713 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7718 m68k_elf_final_processing (void)
7722 if (arch_coldfire_fpu (current_architecture))
7723 flags |= EF_M68K_CFV4E;
7724 /* Set file-specific flags if this is a cpu32 processor. */
7725 if (cpu_of_arch (current_architecture) & cpu32)
7726 flags |= EF_M68K_CPU32;
7727 else if (cpu_of_arch (current_architecture) & fido_a)
7728 flags |= EF_M68K_FIDO;
7729 else if ((cpu_of_arch (current_architecture) & m68000up)
7730 && !(cpu_of_arch (current_architecture) & m68020up))
7731 flags |= EF_M68K_M68000;
7733 if (current_architecture & mcfisa_a)
7735 static const unsigned isa_features[][2] =
7737 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7738 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7739 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7740 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7741 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7742 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7745 static const unsigned mac_features[][2] =
7747 {EF_M68K_CF_MAC, mcfmac},
7748 {EF_M68K_CF_EMAC, mcfemac},
7754 pattern = (current_architecture
7755 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7756 for (ix = 0; isa_features[ix][1]; ix++)
7758 if (pattern == isa_features[ix][1])
7760 flags |= isa_features[ix][0];
7764 if (!isa_features[ix][1])
7767 as_warn (_("Not a defined coldfire architecture"));
7771 if (current_architecture & cfloat)
7772 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7774 pattern = current_architecture & (mcfmac|mcfemac);
7777 for (ix = 0; mac_features[ix][1]; ix++)
7779 if (pattern == mac_features[ix][1])
7781 flags |= mac_features[ix][0];
7785 if (!mac_features[ix][1])
7790 elf_elfheader (stdoutput)->e_flags |= flags;
7795 tc_m68k_regname_to_dw2regnum (char *regname)
7797 unsigned int regnum;
7798 static const char *const regnames[] =
7800 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7801 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7802 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7806 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7807 if (strcmp (regname, regnames[regnum]) == 0)
7814 tc_m68k_frame_initial_instructions (void)
7816 static int sp_regno = -1;
7819 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7821 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7822 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);