1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
112 struct label_line *next;
119 /* The list of labels. */
121 static struct label_line *labels;
123 /* The current label. */
125 static struct label_line *current_label;
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
138 /* Case `g' except when BCC68000 is applicable. */
140 /* Coprocessor branches. */
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
154 /* Not currently used? */
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 const char *m_operands;
163 unsigned long m_opcode;
167 struct m68k_incant *m_next;
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
197 #define cpu32_control_regs m68010_control_regs
199 static const enum m68k_register *control_regs;
201 /* internal form of a 68020 instruction */
205 const char *args; /* list of opcode info */
208 int numo; /* Number of shorts in opcode */
211 struct m68k_op operands[6];
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
216 int nfrag; /* Number of frags we have to produce */
219 int fragoff; /* Where in the current opcode the frag ends */
226 int nrel; /* Num of reloc strucs in use */
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
242 /* Whether this expression needs special pic relocation, and if
244 enum pic_relocation pic_reloc;
247 reloc[5]; /* Five is enough??? */
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
254 static struct m68k_it the_ins; /* the instruction being assembled */
256 #define op(ex) ((ex)->exp.X_op)
257 #define adds(ex) ((ex)->exp.X_add_symbol)
258 #define subs(ex) ((ex)->exp.X_op_symbol)
259 #define offs(ex) ((ex)->exp.X_add_number)
261 /* Macros for adding things to the m68k_it struct */
263 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
265 /* Like addword, but goes BEFORE general operands */
269 struct m68k_incant *opcode;
272 for(z=the_ins.numo;z>opcode->m_codenum;--z)
273 the_ins.opcode[z]=the_ins.opcode[z-1];
274 for(z=0;z<the_ins.nrel;z++)
275 the_ins.reloc[z].n+=2;
276 for (z = 0; z < the_ins.nfrag; z++)
277 the_ins.fragb[z].fragoff++;
278 the_ins.opcode[opcode->m_codenum]=w;
282 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
285 add_fix (width, exp, pc_rel, pc_fix)
287 struct m68k_exp *exp;
291 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
295 : (the_ins.numo*2)));
296 the_ins.reloc[the_ins.nrel].exp = exp->exp;
297 the_ins.reloc[the_ins.nrel].wid = width;
298 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
300 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
302 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
305 /* Cause an extra frag to be generated here, inserting up to 10 bytes
306 (that value is chosen in the frag_var call in md_assemble). TYPE
307 is the subtype of the frag to be generated; its primary type is
308 rs_machine_dependent.
310 The TYPE parameter is also used by md_convert_frag_1 and
311 md_estimate_size_before_relax. The appropriate type of fixup will
312 be emitted by md_convert_frag_1.
314 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
316 add_frag(add,off,type)
321 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
322 the_ins.fragb[the_ins.nfrag].fadd=add;
323 the_ins.fragb[the_ins.nfrag].foff=off;
324 the_ins.fragb[the_ins.nfrag++].fragty=type;
328 (op (ex) != O_constant && op (ex) != O_big)
330 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
331 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
332 static int reverse_16_bits PARAMS ((int in));
333 static int reverse_8_bits PARAMS ((int in));
334 static void install_gen_operand PARAMS ((int mode, int val));
335 static void install_operand PARAMS ((int mode, int val));
336 static void s_bss PARAMS ((int));
337 static void s_data1 PARAMS ((int));
338 static void s_data2 PARAMS ((int));
339 static void s_even PARAMS ((int));
340 static void s_proc PARAMS ((int));
341 static void mri_chip PARAMS ((void));
342 static void s_chip PARAMS ((int));
343 static void s_fopt PARAMS ((int));
344 static void s_opt PARAMS ((int));
345 static void s_reg PARAMS ((int));
346 static void s_restore PARAMS ((int));
347 static void s_save PARAMS ((int));
348 static void s_mri_if PARAMS ((int));
349 static void s_mri_else PARAMS ((int));
350 static void s_mri_endi PARAMS ((int));
351 static void s_mri_break PARAMS ((int));
352 static void s_mri_next PARAMS ((int));
353 static void s_mri_for PARAMS ((int));
354 static void s_mri_endf PARAMS ((int));
355 static void s_mri_repeat PARAMS ((int));
356 static void s_mri_until PARAMS ((int));
357 static void s_mri_while PARAMS ((int));
358 static void s_mri_endw PARAMS ((int));
360 static int current_architecture;
368 static const struct m68k_cpu archs[] = {
369 { m68000, "68000", 0 },
370 { m68010, "68010", 0 },
371 { m68020, "68020", 0 },
372 { m68030, "68030", 0 },
373 { m68040, "68040", 0 },
374 { m68060, "68060", 0 },
375 { cpu32, "cpu32", 0 },
376 { m68881, "68881", 0 },
377 { m68851, "68851", 0 },
378 { mcf5200, "5200", 0 },
379 /* Aliases (effectively, so far as gas is concerned) for the above
381 { m68020, "68k", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68008", 1 },
384 { m68000, "68ec000", 1 },
385 { m68000, "68hc000", 1 },
386 { m68000, "68hc001", 1 },
387 { m68020, "68ec020", 1 },
388 { m68030, "68ec030", 1 },
389 { m68040, "68ec040", 1 },
390 { m68060, "68ec060", 1 },
391 { cpu32, "68330", 1 },
392 { cpu32, "68331", 1 },
393 { cpu32, "68332", 1 },
394 { cpu32, "68333", 1 },
395 { cpu32, "68340", 1 },
396 { cpu32, "68360", 1 },
397 { m68881, "68882", 1 },
400 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
402 /* BCC68000 is for patching in an extra jmp instruction for long offsets
403 on the 68000. The 68000 doesn't support long branches with branchs */
405 /* This table desribes how you change sizes for the various types of variable
406 size expressions. This version only supports two kinds. */
408 /* Note that calls to frag_var need to specify the maximum expansion
409 needed; this is currently 10 bytes for DBCC. */
412 How far Forward this mode will reach:
413 How far Backward this mode will reach:
414 How many bytes this mode will add to the size of the frag
415 Which mode to go to if the offset won't fit in this one
417 relax_typeS md_relax_table[] =
419 {1, 1, 0, 0}, /* First entries aren't used */
420 {1, 1, 0, 0}, /* For no good reason except */
421 {1, 1, 0, 0}, /* that the VAX doesn't either */
424 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
425 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
429 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
430 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
434 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
435 {(32767), (-32768), 2, TAB (PCREL, LONG)},
439 {(127), (-128), 0, TAB (BCC68000, SHORT)},
440 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
441 {0, 0, 6, 0}, /* jmp long space */
444 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
445 {(32767), (-32768), 2, TAB (DBCC, LONG)},
446 {0, 0, 10, 0}, /* bra/jmp long space */
449 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
450 {32767, -32768, 2, TAB (PCLEA, LONG)},
454 /* For, e.g., jmp pcrel indexed. */
455 {125, -130, 0, TAB (PCINDEX, SHORT)},
456 {32765, -32770, 2, TAB (PCINDEX, LONG)},
461 /* These are the machine dependent pseudo-ops. These are included so
462 the assembler can work on the output from the SUN C compiler, which
466 /* This table describes all the machine specific pseudo-ops the assembler
467 has to support. The fields are:
468 pseudo-op name without dot
469 function to call to execute this pseudo-op
470 Integer arg to pass to the function
472 const pseudo_typeS md_pseudo_table[] =
474 {"data1", s_data1, 0},
475 {"data2", s_data2, 0},
478 {"skip", s_space, 0},
480 #if defined (TE_SUN3) || defined (OBJ_ELF)
481 {"align", s_align_bytes, 0},
484 {"swbeg", s_ignore, 0},
486 {"extend", float_cons, 'x'},
487 {"ldouble", float_cons, 'x'},
489 /* The following pseudo-ops are supported for MRI compatibility. */
491 {"comline", s_space, 1},
493 {"mask2", s_ignore, 0},
496 {"restore", s_restore, 0},
500 {"if.b", s_mri_if, 'b'},
501 {"if.w", s_mri_if, 'w'},
502 {"if.l", s_mri_if, 'l'},
503 {"else", s_mri_else, 0},
504 {"else.s", s_mri_else, 's'},
505 {"else.l", s_mri_else, 'l'},
506 {"endi", s_mri_endi, 0},
507 {"break", s_mri_break, 0},
508 {"break.s", s_mri_break, 's'},
509 {"break.l", s_mri_break, 'l'},
510 {"next", s_mri_next, 0},
511 {"next.s", s_mri_next, 's'},
512 {"next.l", s_mri_next, 'l'},
513 {"for", s_mri_for, 0},
514 {"for.b", s_mri_for, 'b'},
515 {"for.w", s_mri_for, 'w'},
516 {"for.l", s_mri_for, 'l'},
517 {"endf", s_mri_endf, 0},
518 {"repeat", s_mri_repeat, 0},
519 {"until", s_mri_until, 0},
520 {"until.b", s_mri_until, 'b'},
521 {"until.w", s_mri_until, 'w'},
522 {"until.l", s_mri_until, 'l'},
523 {"while", s_mri_while, 0},
524 {"while.b", s_mri_while, 'b'},
525 {"while.w", s_mri_while, 'w'},
526 {"while.l", s_mri_while, 'l'},
527 {"endw", s_mri_endw, 0},
533 /* The mote pseudo ops are put into the opcode table, since they
534 don't start with a . they look like opcodes to gas.
536 extern void obj_coff_section ();
538 CONST pseudo_typeS mote_pseudo_table[] =
551 {"xdef", s_globl, 0},
553 {"align", s_align_bytes, 0},
555 {"align", s_align_ptwo, 0},
558 {"sect", obj_coff_section, 0},
559 {"section", obj_coff_section, 0},
564 #define issbyte(x) ((x)>=-128 && (x)<=127)
565 #define isubyte(x) ((x)>=0 && (x)<=255)
566 #define issword(x) ((x)>=-32768 && (x)<=32767)
567 #define isuword(x) ((x)>=0 && (x)<=65535)
569 #define isbyte(x) ((x)>= -255 && (x)<=255)
570 #define isword(x) ((x)>=-65536 && (x)<=65535)
571 #define islong(x) (1)
573 extern char *input_line_pointer;
575 static char mklower_table[256];
576 #define mklower(c) (mklower_table[(unsigned char)(c)])
577 static char notend_table[256];
578 static char alt_notend_table[256];
580 (! (notend_table[(unsigned char) *s] \
582 && alt_notend_table[(unsigned char) s[1]])))
584 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
586 #ifdef NO_PCREL_RELOCS
589 make_pcrel_absolute(fixP, add_number)
593 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
595 /* rewrite the PC relative instructions to absolute address ones.
596 * these are rumoured to be faster, and the apollo linker refuses
597 * to deal with the PC relative relocations.
599 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
604 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
610 as_fatal ("Unknown PC relative instruction");
615 #endif /* NO_PCREL_RELOCS */
618 tc_coff_fix2rtype (fixP)
621 if (fixP->fx_tcbit && fixP->fx_size == 4)
622 return R_RELLONG_NEG;
623 #ifdef NO_PCREL_RELOCS
624 know (fixP->fx_pcrel == 0);
625 return (fixP->fx_size == 1 ? R_RELBYTE
626 : fixP->fx_size == 2 ? R_DIR16
629 return (fixP->fx_pcrel ?
630 (fixP->fx_size == 1 ? R_PCRBYTE :
631 fixP->fx_size == 2 ? R_PCRWORD :
633 (fixP->fx_size == 1 ? R_RELBYTE :
634 fixP->fx_size == 2 ? R_RELWORD :
643 /* Compute the relocation code for a fixup of SIZE bytes, using pc
644 relative relocation if PCREL is non-zero. PIC says whether a special
645 pic relocation was requested. */
647 static bfd_reloc_code_real_type get_reloc_code
648 PARAMS ((int, int, enum pic_relocation));
650 static bfd_reloc_code_real_type
651 get_reloc_code (size, pcrel, pic)
654 enum pic_relocation pic;
662 return BFD_RELOC_8_GOT_PCREL;
664 return BFD_RELOC_16_GOT_PCREL;
666 return BFD_RELOC_32_GOT_PCREL;
674 return BFD_RELOC_8_GOTOFF;
676 return BFD_RELOC_16_GOTOFF;
678 return BFD_RELOC_32_GOTOFF;
686 return BFD_RELOC_8_PLT_PCREL;
688 return BFD_RELOC_16_PLT_PCREL;
690 return BFD_RELOC_32_PLT_PCREL;
698 return BFD_RELOC_8_PLTOFF;
700 return BFD_RELOC_16_PLTOFF;
702 return BFD_RELOC_32_PLTOFF;
712 return BFD_RELOC_8_PCREL;
714 return BFD_RELOC_16_PCREL;
716 return BFD_RELOC_32_PCREL;
733 as_bad ("Can not do %d byte %s%srelocation", size,
734 pcrel ? "pc-relative " : "",
735 pic == pic_none ? "" : "pic ");
736 return BFD_RELOC_NONE;
739 /* Here we decide which fixups can be adjusted to make them relative
740 to the beginning of the section instead of the symbol. Basically
741 we need to make sure that the dynamic relocations are done
742 correctly, so in some cases we force the original symbol to be
745 tc_m68k_fix_adjustable (fixP)
748 /* Prevent all adjustments to global symbols. */
749 if (S_IS_EXTERNAL (fixP->fx_addsy))
752 /* adjust_reloc_syms doesn't know about the GOT */
753 switch (fixP->fx_r_type)
755 case BFD_RELOC_8_GOT_PCREL:
756 case BFD_RELOC_16_GOT_PCREL:
757 case BFD_RELOC_32_GOT_PCREL:
758 case BFD_RELOC_8_GOTOFF:
759 case BFD_RELOC_16_GOTOFF:
760 case BFD_RELOC_32_GOTOFF:
761 case BFD_RELOC_8_PLT_PCREL:
762 case BFD_RELOC_16_PLT_PCREL:
763 case BFD_RELOC_32_PLT_PCREL:
764 case BFD_RELOC_8_PLTOFF:
765 case BFD_RELOC_16_PLTOFF:
766 case BFD_RELOC_32_PLTOFF:
776 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
783 tc_gen_reloc (section, fixp)
788 bfd_reloc_code_real_type code;
793 if (fixp->fx_r_type != BFD_RELOC_NONE)
795 code = fixp->fx_r_type;
797 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
798 that fixup_segment converted a non-PC relative reloc into a
799 PC relative reloc. In such a case, we need to convert the
806 code = BFD_RELOC_8_PCREL;
809 code = BFD_RELOC_16_PCREL;
812 code = BFD_RELOC_32_PCREL;
814 case BFD_RELOC_8_PCREL:
815 case BFD_RELOC_16_PCREL:
816 case BFD_RELOC_32_PCREL:
817 case BFD_RELOC_8_GOT_PCREL:
818 case BFD_RELOC_16_GOT_PCREL:
819 case BFD_RELOC_32_GOT_PCREL:
820 case BFD_RELOC_8_GOTOFF:
821 case BFD_RELOC_16_GOTOFF:
822 case BFD_RELOC_32_GOTOFF:
823 case BFD_RELOC_8_PLT_PCREL:
824 case BFD_RELOC_16_PLT_PCREL:
825 case BFD_RELOC_32_PLT_PCREL:
826 case BFD_RELOC_8_PLTOFF:
827 case BFD_RELOC_16_PLTOFF:
828 case BFD_RELOC_32_PLTOFF:
831 as_bad_where (fixp->fx_file, fixp->fx_line,
832 "Cannot make %s relocation PC relative",
833 bfd_get_reloc_code_name (code));
839 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
840 switch (F (fixp->fx_size, fixp->fx_pcrel))
842 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
843 MAP (1, 0, BFD_RELOC_8);
844 MAP (2, 0, BFD_RELOC_16);
845 MAP (4, 0, BFD_RELOC_32);
846 MAP (1, 1, BFD_RELOC_8_PCREL);
847 MAP (2, 1, BFD_RELOC_16_PCREL);
848 MAP (4, 1, BFD_RELOC_32_PCREL);
856 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
858 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
859 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
862 reloc->addend = fixp->fx_addnumber;
867 reloc->addend = fixp->fx_addnumber;
869 reloc->addend = (section->vma
870 + (fixp->fx_pcrel_adjust == 64
871 ? -1 : fixp->fx_pcrel_adjust)
873 + md_pcrel_from (fixp));
876 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
877 assert (reloc->howto != 0);
882 #endif /* BFD_ASSEMBLER */
884 /* Handle of the OPCODE hash table. NULL means any use before
885 m68k_ip_begin() will crash. */
886 static struct hash_control *op_hash;
888 /* Assemble an m68k instruction. */
895 register struct m68k_op *opP;
896 register struct m68k_incant *opcode;
897 register const char *s;
898 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
899 char *pdot, *pdotmove;
900 enum m68k_size siz1, siz2;
904 char *crack_operand ();
905 LITTLENUM_TYPE words[6];
906 LITTLENUM_TYPE *wordp;
907 unsigned long ok_arch = 0;
909 if (*instring == ' ')
910 instring++; /* skip leading whitespace */
912 /* Scan up to end of operation-code, which MUST end in end-of-string
913 or exactly 1 space. */
915 for (p = instring; *p != '\0'; p++)
925 the_ins.error = "No operator";
929 /* p now points to the end of the opcode name, probably whitespace.
930 Make sure the name is null terminated by clobbering the
931 whitespace, look it up in the hash table, then fix it back.
932 Remove a dot, first, since the opcode tables have none. */
935 for (pdotmove = pdot; pdotmove < p; pdotmove++)
936 *pdotmove = pdotmove[1];
942 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
947 for (pdotmove = p; pdotmove > pdot; pdotmove--)
948 *pdotmove = pdotmove[-1];
955 the_ins.error = "Unknown operator";
959 /* found a legitimate opcode, start matching operands */
963 if (opcode->m_operands == 0)
965 char *old = input_line_pointer;
967 input_line_pointer = p;
968 /* Ahh - it's a motorola style psuedo op */
969 mote_pseudo_table[opcode->m_opnum].poc_handler
970 (mote_pseudo_table[opcode->m_opnum].poc_val);
971 input_line_pointer = old;
977 if (flag_mri && opcode->m_opnum == 0)
979 /* In MRI mode, random garbage is allowed after an instruction
980 which accepts no operands. */
981 the_ins.args = opcode->m_operands;
982 the_ins.numargs = opcode->m_opnum;
983 the_ins.numo = opcode->m_codenum;
984 the_ins.opcode[0] = getone (opcode);
985 the_ins.opcode[1] = gettwo (opcode);
989 for (opP = &the_ins.operands[0]; *p; opP++)
991 p = crack_operand (p, opP);
995 the_ins.error = opP->error;
1000 opsfound = opP - &the_ins.operands[0];
1002 /* This ugly hack is to support the floating pt opcodes in their
1003 standard form. Essentially, we fake a first enty of type COP#1 */
1004 if (opcode->m_operands[0] == 'I')
1008 for (n = opsfound; n > 0; --n)
1009 the_ins.operands[n] = the_ins.operands[n - 1];
1011 memset ((char *) (&the_ins.operands[0]), '\0',
1012 sizeof (the_ins.operands[0]));
1013 the_ins.operands[0].mode = CONTROL;
1014 the_ins.operands[0].reg = m68k_float_copnum;
1018 /* We've got the operands. Find an opcode that'll accept them */
1021 /* If we didn't get the right number of ops, or we have no
1022 common model with this pattern then reject this pattern. */
1024 ok_arch |= opcode->m_arch;
1025 if (opsfound != opcode->m_opnum
1026 || ((opcode->m_arch & current_architecture) == 0))
1030 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1034 /* Warning: this switch is huge! */
1035 /* I've tried to organize the cases into this order:
1036 non-alpha first, then alpha by letter. Lower-case
1037 goes directly before uppercase counterpart. */
1038 /* Code with multiple case ...: gets sorted by the lowest
1039 case ... it belongs to. I hope this makes sense. */
1169 if (opP->mode != IMMED)
1171 else if (s[1] == 'b'
1172 && ! isvar (&opP->disp)
1173 && (opP->disp.exp.X_op != O_constant
1174 || ! isbyte (opP->disp.exp.X_add_number)))
1176 else if (s[1] == 'B'
1177 && ! isvar (&opP->disp)
1178 && (opP->disp.exp.X_op != O_constant
1179 || ! issbyte (opP->disp.exp.X_add_number)))
1181 else if (s[1] == 'w'
1182 && ! isvar (&opP->disp)
1183 && (opP->disp.exp.X_op != O_constant
1184 || ! isword (opP->disp.exp.X_add_number)))
1186 else if (s[1] == 'W'
1187 && ! isvar (&opP->disp)
1188 && (opP->disp.exp.X_op != O_constant
1189 || ! issword (opP->disp.exp.X_add_number)))
1195 if (opP->mode != IMMED)
1200 if (opP->mode == AREG
1201 || opP->mode == CONTROL
1202 || opP->mode == FPREG
1203 || opP->mode == IMMED
1204 || opP->mode == REGLST
1205 || (opP->mode != ABSL
1207 || opP->reg == ZPC)))
1212 if (opP->mode == CONTROL
1213 || opP->mode == FPREG
1214 || opP->mode == REGLST
1215 || opP->mode == IMMED
1216 || (opP->mode != ABSL
1218 || opP->reg == ZPC)))
1246 if (opP->mode == CONTROL
1247 || opP->mode == FPREG
1248 || opP->mode == REGLST)
1253 if (opP->mode != AINC)
1258 if (opP->mode != ADEC)
1308 if (opP->reg == PC || opP->reg == ZPC)
1329 case '~': /* For now! (JF FOO is this right?) */
1351 if (opP->mode != CONTROL
1352 || (opP->reg != TT0 && opP->reg != TT1))
1357 if (opP->mode != AREG)
1362 if (opP->mode != AINDR)
1367 if (opP->mode != ABSL
1369 && strncmp (instring, "jbsr", 4) == 0))
1374 if (opP->mode != CONTROL || opP->reg != CCR)
1379 if (opP->mode != DISP
1381 || opP->reg > ADDR7)
1386 if (opP->mode != DREG)
1391 if (opP->mode != FPREG)
1396 if (opP->mode != CONTROL
1403 if (opP->mode != CONTROL
1405 || opP->reg > last_movec_reg)
1409 const enum m68k_register *rp;
1410 for (rp = control_regs; *rp; rp++)
1411 if (*rp == opP->reg)
1419 if (opP->mode != IMMED)
1425 if (opP->mode == DREG
1426 || opP->mode == AREG
1427 || opP->mode == FPREG)
1436 opP->mask = 1 << (opP->reg - DATA0);
1439 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1442 opP->mask = 1 << (opP->reg - FP0 + 16);
1450 else if (opP->mode == CONTROL)
1459 opP->mask = 1 << 24;
1462 opP->mask = 1 << 25;
1465 opP->mask = 1 << 26;
1474 else if (opP->mode == ABSL
1475 && opP->disp.size == SIZE_UNSPEC
1476 && opP->disp.exp.X_op == O_constant)
1478 /* This is what the MRI REG pseudo-op generates. */
1480 opP->mask = opP->disp.exp.X_add_number;
1482 else if (opP->mode != REGLST)
1484 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1486 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1491 if (opP->mode != IMMED)
1493 else if (opP->disp.exp.X_op != O_constant
1494 || ! issbyte (opP->disp.exp.X_add_number))
1496 else if (! m68k_quick
1497 && instring[3] != 'q'
1498 && instring[4] != 'q')
1503 if (opP->mode != DREG
1504 && opP->mode != IMMED
1505 && opP->mode != ABSL)
1510 if (opP->mode != IMMED)
1512 else if (opP->disp.exp.X_op != O_constant
1513 || opP->disp.exp.X_add_number < 1
1514 || opP->disp.exp.X_add_number > 8)
1516 else if (! m68k_quick
1517 && (strncmp (instring, "add", 3) == 0
1518 || strncmp (instring, "sub", 3) == 0)
1519 && instring[3] != 'q')
1524 if (opP->mode != DREG && opP->mode != AREG)
1529 if (opP->mode != AINDR
1530 && (opP->mode != BASE
1532 && opP->reg != ZADDR0)
1533 || opP->disp.exp.X_op != O_absent
1534 || ((opP->index.reg < DATA0
1535 || opP->index.reg > DATA7)
1536 && (opP->index.reg < ADDR0
1537 || opP->index.reg > ADDR7))
1538 || opP->index.size != SIZE_UNSPEC
1539 || opP->index.scale != 1))
1544 if (opP->mode != CONTROL
1545 || ! (opP->reg == FPI
1547 || opP->reg == FPC))
1552 if (opP->mode != CONTROL || opP->reg != SR)
1557 if (opP->mode != IMMED)
1559 else if (opP->disp.exp.X_op != O_constant
1560 || opP->disp.exp.X_add_number < 0
1561 || opP->disp.exp.X_add_number > 7)
1566 if (opP->mode != CONTROL || opP->reg != USP)
1570 /* JF these are out of order. We could put them
1571 in order if we were willing to put up with
1572 bunches of #ifdef m68851s in the code.
1574 Don't forget that you need these operands
1575 to use 68030 MMU instructions. */
1577 /* Memory addressing mode used by pflushr */
1579 if (opP->mode == CONTROL
1580 || opP->mode == FPREG
1581 || opP->mode == DREG
1582 || opP->mode == AREG
1583 || opP->mode == REGLST)
1585 /* We should accept immediate operands, but they
1586 supposedly have to be quad word, and we don't
1587 handle that. I would like to see what a Motorola
1588 assembler does before doing something here. */
1589 if (opP->mode == IMMED)
1594 if (opP->mode != CONTROL
1595 || (opP->reg != SFC && opP->reg != DFC))
1600 if (opP->mode != CONTROL || opP->reg != TC)
1605 if (opP->mode != CONTROL || opP->reg != AC)
1610 if (opP->mode != CONTROL
1613 && opP->reg != SCC))
1618 if (opP->mode != CONTROL
1624 if (opP->mode != CONTROL
1627 && opP->reg != CRP))
1632 if (opP->mode != CONTROL
1633 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1634 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1639 if (opP->mode != CONTROL || opP->reg != PSR)
1644 if (opP->mode != CONTROL || opP->reg != PCSR)
1649 if (opP->mode != CONTROL
1656 } /* not a cache specifier. */
1660 if (opP->mode != ABSL)
1666 } /* switch on type of operand */
1670 } /* for each operand */
1671 } /* if immediately wrong */
1678 opcode = opcode->m_next;
1683 && !(ok_arch & current_architecture))
1688 "invalid instruction for this architecture; needs ");
1689 cp = buf + strlen (buf);
1693 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1696 strcpy (cp, "mmu (68030 or 68851)");
1699 strcpy (cp, "68020 or higher");
1702 strcpy (cp, "68000 or higher");
1705 strcpy (cp, "68010 or higher");
1709 int got_one = 0, idx;
1710 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1713 if ((archs[idx].arch & ok_arch)
1714 && ! archs[idx].alias)
1718 strcpy (cp, " or ");
1722 strcpy (cp, archs[idx].name);
1728 cp = xmalloc (strlen (buf) + 1);
1733 the_ins.error = "operands mismatch";
1735 } /* Fell off the end */
1740 /* now assemble it */
1742 the_ins.args = opcode->m_operands;
1743 the_ins.numargs = opcode->m_opnum;
1744 the_ins.numo = opcode->m_codenum;
1745 the_ins.opcode[0] = getone (opcode);
1746 the_ins.opcode[1] = gettwo (opcode);
1748 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1750 /* This switch is a doozy.
1751 Watch the first step; its a big one! */
1778 tmpreg = 0x3c; /* 7.4 */
1779 if (strchr ("bwl", s[1]))
1780 nextword = get_num (&opP->disp, 80);
1782 nextword = get_num (&opP->disp, 0);
1783 if (isvar (&opP->disp))
1784 add_fix (s[1], &opP->disp, 0, 0);
1788 if (!isbyte (nextword))
1789 opP->error = "operand out of range";
1794 if (!isword (nextword))
1795 opP->error = "operand out of range";
1800 if (!issword (nextword))
1801 opP->error = "operand out of range";
1806 addword (nextword >> 16);
1833 /* We gotta put out some float */
1834 if (op (&opP->disp) != O_big)
1839 /* Can other cases happen here? */
1840 if (op (&opP->disp) != O_constant)
1843 val = (valueT) offs (&opP->disp);
1847 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1848 val >>= LITTLENUM_NUMBER_OF_BITS;
1852 offs (&opP->disp) = gencnt;
1854 if (offs (&opP->disp) > 0)
1856 if (offs (&opP->disp) > baseo)
1858 as_warn ("Bignum too big for %c format; truncated",
1860 offs (&opP->disp) = baseo;
1862 baseo -= offs (&opP->disp);
1865 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1866 offs (&opP->disp)--;
1871 gen_to_words (words, baseo, (long) outro);
1872 for (wordp = words; baseo--; wordp++)
1876 tmpreg = opP->reg - DATA; /* 0.dreg */
1879 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1882 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1885 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1888 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1892 nextword = get_num (&opP->disp, 80);
1895 && ! isvar (&opP->disp)
1898 opP->disp.exp.X_op = O_symbol;
1899 #ifndef BFD_ASSEMBLER
1900 opP->disp.exp.X_add_symbol = &abs_symbol;
1902 opP->disp.exp.X_add_symbol =
1903 section_symbol (absolute_section);
1907 /* Force into index mode. Hope this works */
1909 /* We do the first bit for 32-bit displacements, and the
1910 second bit for 16 bit ones. It is possible that we
1911 should make the default be WORD instead of LONG, but
1912 I think that'd break GCC, so we put up with a little
1913 inefficiency for the sake of working output. */
1915 if (!issword (nextword)
1916 || (isvar (&opP->disp)
1917 && ((opP->disp.size == SIZE_UNSPEC
1918 && flag_short_refs == 0
1919 && cpu_of_arch (current_architecture) >= m68020)
1920 || opP->disp.size == SIZE_LONG)))
1922 if (cpu_of_arch (current_architecture) < m68020)
1924 "displacement too large for this architecture; needs 68020 or higher";
1926 tmpreg = 0x3B; /* 7.3 */
1928 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1929 if (isvar (&opP->disp))
1933 if (opP->disp.size == SIZE_LONG
1935 /* If the displacement needs pic
1936 relocation it cannot be relaxed. */
1937 || opP->disp.pic_reloc != pic_none
1942 add_fix ('l', &opP->disp, 1, 2);
1946 add_frag (adds (&opP->disp),
1948 TAB (PCLEA, SZ_UNDEF));
1955 add_fix ('l', &opP->disp, 0, 0);
1960 addword (nextword >> 16);
1965 tmpreg = 0x3A; /* 7.2 */
1967 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1969 if (isvar (&opP->disp))
1973 add_fix ('w', &opP->disp, 1, 0);
1976 add_fix ('w', &opP->disp, 0, 0);
1986 baseo = get_num (&opP->disp, 80);
1987 if (opP->mode == POST || opP->mode == PRE)
1988 outro = get_num (&opP->odisp, 80);
1989 /* Figure out the `addressing mode'.
1990 Also turn on the BASE_DISABLE bit, if needed. */
1991 if (opP->reg == PC || opP->reg == ZPC)
1993 tmpreg = 0x3b; /* 7.3 */
1994 if (opP->reg == ZPC)
1997 else if (opP->reg == 0)
2000 tmpreg = 0x30; /* 6.garbage */
2002 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2005 tmpreg = 0x30 + opP->reg - ZADDR0;
2008 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2010 siz1 = opP->disp.size;
2011 if (opP->mode == POST || opP->mode == PRE)
2012 siz2 = opP->odisp.size;
2016 /* Index register stuff */
2017 if (opP->index.reg != 0
2018 && opP->index.reg >= DATA
2019 && opP->index.reg <= ADDR7)
2021 nextword |= (opP->index.reg - DATA) << 12;
2023 if (opP->index.size == SIZE_LONG
2024 || (opP->index.size == SIZE_UNSPEC
2025 && m68k_index_width_default == SIZE_LONG))
2028 if ((opP->index.scale != 1
2029 && cpu_of_arch (current_architecture) < m68020)
2030 || (opP->index.scale == 8
2031 && current_architecture == mcf5200))
2034 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2037 switch (opP->index.scale)
2054 GET US OUT OF HERE! */
2056 /* Must be INDEX, with an index register. Address
2057 register cannot be ZERO-PC, and either :b was
2058 forced, or we know it will fit. For a 68000 or
2059 68010, force this mode anyways, because the
2060 larger modes aren't supported. */
2061 if (opP->mode == BASE
2062 && ((opP->reg >= ADDR0
2063 && opP->reg <= ADDR7)
2066 if (siz1 == SIZE_BYTE
2067 || cpu_of_arch (current_architecture) < m68020
2068 || (siz1 == SIZE_UNSPEC
2069 && ! isvar (&opP->disp)
2070 && issbyte (baseo)))
2072 nextword += baseo & 0xff;
2074 if (isvar (&opP->disp))
2076 /* Do a byte relocation. If it doesn't
2077 fit (possible on m68000) let the
2078 fixup processing complain later. */
2080 add_fix ('B', &opP->disp, 1, 1);
2082 add_fix ('B', &opP->disp, 0, 0);
2084 else if (siz1 != SIZE_BYTE)
2086 if (siz1 != SIZE_UNSPEC)
2087 as_warn ("Forcing byte displacement");
2088 if (! issbyte (baseo))
2089 opP->error = "byte displacement out of range";
2094 else if (siz1 == SIZE_UNSPEC
2096 && isvar (&opP->disp)
2097 && subs (&opP->disp) == NULL
2099 /* If the displacement needs pic
2100 relocation it cannot be relaxed. */
2101 && opP->disp.pic_reloc == pic_none
2105 /* The code in md_convert_frag_1 needs to be
2106 able to adjust nextword. Call frag_grow
2107 to ensure that we have enough space in
2108 the frag obstack to make all the bytes
2111 nextword += baseo & 0xff;
2113 add_frag (adds (&opP->disp), offs (&opP->disp),
2114 TAB (PCINDEX, SZ_UNDEF));
2122 nextword |= 0x40; /* No index reg */
2123 if (opP->index.reg >= ZDATA0
2124 && opP->index.reg <= ZDATA7)
2125 nextword |= (opP->index.reg - ZDATA0) << 12;
2126 else if (opP->index.reg >= ZADDR0
2127 || opP->index.reg <= ZADDR7)
2128 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2131 /* It isn't simple. */
2133 if (cpu_of_arch (current_architecture) < m68020)
2135 "invalid operand mode for this architecture; needs 68020 or higher";
2138 /* If the guy specified a width, we assume that it is
2139 wide enough. Maybe it isn't. If so, we lose. */
2143 if (isvar (&opP->disp)
2145 : ! issword (baseo))
2150 else if (! isvar (&opP->disp) && baseo == 0)
2159 as_warn (":b not permitted; defaulting to :w");
2169 /* Figure out innner displacement stuff */
2170 if (opP->mode == POST || opP->mode == PRE)
2172 if (cpu_of_arch (current_architecture) & cpu32)
2173 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2177 if (isvar (&opP->odisp)
2179 : ! issword (outro))
2184 else if (! isvar (&opP->odisp) && outro == 0)
2193 as_warn (":b not permitted; defaulting to :w");
2202 if (opP->mode == POST
2203 && (nextword & 0x40) == 0)
2208 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2210 if (opP->reg == PC || opP->reg == ZPC)
2211 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2213 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2215 if (siz1 == SIZE_LONG)
2216 addword (baseo >> 16);
2217 if (siz1 != SIZE_UNSPEC)
2220 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2221 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2222 if (siz2 == SIZE_LONG)
2223 addword (outro >> 16);
2224 if (siz2 != SIZE_UNSPEC)
2230 nextword = get_num (&opP->disp, 80);
2231 switch (opP->disp.size)
2236 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2238 tmpreg = 0x38; /* 7.0 */
2242 /* Don't generate pc relative code on 68010 and
2244 if (isvar (&opP->disp)
2245 && !subs (&opP->disp)
2246 && adds (&opP->disp)
2248 /* If the displacement needs pic relocation it
2249 cannot be relaxed. */
2250 && opP->disp.pic_reloc == pic_none
2252 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2253 && cpu_of_arch (current_architecture) >= m68020
2255 && !strchr ("~%&$?", s[0]))
2257 tmpreg = 0x3A; /* 7.2 */
2258 add_frag (adds (&opP->disp),
2260 TAB (PCREL, SZ_UNDEF));
2263 /* Fall through into long */
2265 if (isvar (&opP->disp))
2266 add_fix ('l', &opP->disp, 0, 0);
2268 tmpreg = 0x39;/* 7.1 mode */
2269 addword (nextword >> 16);
2273 case SIZE_WORD: /* Word */
2274 if (isvar (&opP->disp))
2275 add_fix ('w', &opP->disp, 0, 0);
2277 tmpreg = 0x38;/* 7.0 mode */
2285 as_bad ("unknown/incorrect operand");
2288 install_gen_operand (s[1], tmpreg);
2294 { /* JF: I hate floating point! */
2309 tmpreg = get_num (&opP->disp, tmpreg);
2310 if (isvar (&opP->disp))
2311 add_fix (s[1], &opP->disp, 0, 0);
2314 case 'b': /* Danger: These do no check for
2315 certain types of overflow.
2317 if (!isbyte (tmpreg))
2318 opP->error = "out of range";
2319 insop (tmpreg, opcode);
2320 if (isvar (&opP->disp))
2321 the_ins.reloc[the_ins.nrel - 1].n =
2322 (opcode->m_codenum) * 2 + 1;
2325 if (!issbyte (tmpreg))
2326 opP->error = "out of range";
2327 opcode->m_opcode |= tmpreg;
2328 if (isvar (&opP->disp))
2329 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2332 if (!isword (tmpreg))
2333 opP->error = "out of range";
2334 insop (tmpreg, opcode);
2335 if (isvar (&opP->disp))
2336 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2339 if (!issword (tmpreg))
2340 opP->error = "out of range";
2341 insop (tmpreg, opcode);
2342 if (isvar (&opP->disp))
2343 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2346 /* Because of the way insop works, we put these two out
2348 insop (tmpreg, opcode);
2349 insop (tmpreg >> 16, opcode);
2350 if (isvar (&opP->disp))
2351 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2357 install_operand (s[1], tmpreg);
2368 install_operand (s[1], opP->reg - ADDR);
2372 tmpreg = get_num (&opP->disp, 80);
2376 /* The pc_fix argument winds up in fx_pcrel_adjust,
2377 which is a char, and may therefore be unsigned. We
2378 want to pass -1, but we pass 64 instead, and convert
2379 back in md_pcrel_from. */
2380 add_fix ('B', &opP->disp, 1, 64);
2383 add_fix ('w', &opP->disp, 1, 0);
2388 if (cpu_of_arch (current_architecture) < m68020)
2389 as_warn ("Can't use long branches on 68000/68010");
2390 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2391 add_fix ('l', &opP->disp, 1, 0);
2396 if (subs (&opP->disp)) /* We can't relax it */
2400 /* If the displacement needs pic relocation it cannot be
2402 if (opP->disp.pic_reloc != pic_none)
2406 /* This could either be a symbol, or an absolute
2407 address. No matter, the frag hacking will finger it
2408 out. Not quite: it can't switch from BRANCH to
2409 BCC68000 for the case where opnd is absolute (it
2410 needs to use the 68000 hack since no conditional abs
2412 if (((cpu_of_arch (current_architecture) < m68020)
2413 || (0 == adds (&opP->disp)))
2414 && (the_ins.opcode[0] >= 0x6200)
2415 && (the_ins.opcode[0] <= 0x6f00))
2416 add_frag (adds (&opP->disp), offs (&opP->disp),
2417 TAB (BCC68000, SZ_UNDEF));
2419 add_frag (adds (&opP->disp), offs (&opP->disp),
2420 TAB (ABRANCH, SZ_UNDEF));
2423 if (isvar (&opP->disp))
2426 /* check for DBcc instruction */
2427 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2429 /* size varies if patch */
2430 /* needed for long form */
2431 add_frag (adds (&opP->disp), offs (&opP->disp),
2432 TAB (DBCC, SZ_UNDEF));
2436 add_fix ('w', &opP->disp, 1, 0);
2440 case 'C': /* Fixed size LONG coproc branches */
2441 add_fix ('l', &opP->disp, 1, 0);
2445 case 'c': /* Var size Coprocesssor branches */
2446 if (subs (&opP->disp))
2448 add_fix ('l', &opP->disp, 1, 0);
2449 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2451 else if (adds (&opP->disp))
2452 add_frag (adds (&opP->disp), offs (&opP->disp),
2453 TAB (FBRANCH, SZ_UNDEF));
2456 /* add_frag((symbolS *) 0, offs(&opP->disp),
2457 TAB(FBRANCH,SHORT)); */
2458 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2459 add_fix ('l', &opP->disp, 1, 0);
2469 case 'C': /* Ignore it */
2472 case 'd': /* JF this is a kludge */
2473 install_operand ('s', opP->reg - ADDR);
2474 tmpreg = get_num (&opP->disp, 80);
2475 if (!issword (tmpreg))
2477 as_warn ("Expression out of range, using 0");
2484 install_operand (s[1], opP->reg - DATA);
2488 install_operand (s[1], opP->reg - FP0);
2492 tmpreg = opP->reg - COP0;
2493 install_operand (s[1], tmpreg);
2496 case 'J': /* JF foo */
2569 install_operand (s[1], tmpreg);
2573 tmpreg = get_num (&opP->disp, 55);
2574 install_operand (s[1], tmpreg & 0x7f);
2581 if (tmpreg & 0x7FF0000)
2582 as_bad ("Floating point register in register list");
2583 insop (reverse_16_bits (tmpreg), opcode);
2587 if (tmpreg & 0x700FFFF)
2588 as_bad ("Wrong register in floating-point reglist");
2589 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2597 if (tmpreg & 0x7FF0000)
2598 as_bad ("Floating point register in register list");
2599 insop (tmpreg, opcode);
2601 else if (s[1] == '8')
2603 if (tmpreg & 0x0FFFFFF)
2604 as_bad ("incorrect register in reglist");
2605 install_operand (s[1], tmpreg >> 24);
2609 if (tmpreg & 0x700FFFF)
2610 as_bad ("wrong register in floating-point reglist");
2612 install_operand (s[1], tmpreg >> 16);
2617 install_operand (s[1], get_num (&opP->disp, 60));
2621 tmpreg = ((opP->mode == DREG)
2622 ? 0x20 + opP->reg - DATA
2623 : (get_num (&opP->disp, 40) & 0x1F));
2624 install_operand (s[1], tmpreg);
2628 tmpreg = get_num (&opP->disp, 10);
2631 install_operand (s[1], tmpreg);
2635 /* This depends on the fact that ADDR registers are eight
2636 more than their corresponding DATA regs, so the result
2637 will have the ADDR_REG bit set */
2638 install_operand (s[1], opP->reg - DATA);
2642 if (opP->mode == AINDR)
2643 install_operand (s[1], opP->reg - DATA);
2645 install_operand (s[1], opP->index.reg - DATA);
2649 if (opP->reg == FPI)
2651 else if (opP->reg == FPS)
2653 else if (opP->reg == FPC)
2657 install_operand (s[1], tmpreg);
2660 case 'S': /* Ignore it */
2664 install_operand (s[1], get_num (&opP->disp, 30));
2667 case 'U': /* Ignore it */
2686 as_fatal ("failed sanity check");
2687 } /* switch on cache token */
2688 install_operand (s[1], tmpreg);
2691 /* JF: These are out of order, I fear. */
2704 install_operand (s[1], tmpreg);
2730 install_operand (s[1], tmpreg);
2734 if (opP->reg == VAL)
2753 install_operand (s[1], tmpreg);
2767 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2778 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2784 install_operand (s[1], tmpreg);
2787 know (opP->reg == PSR);
2790 know (opP->reg == PCSR);
2805 install_operand (s[1], tmpreg);
2808 tmpreg = get_num (&opP->disp, 20);
2809 install_operand (s[1], tmpreg);
2811 case '_': /* used only for move16 absolute 32-bit address */
2812 tmpreg = get_num (&opP->disp, 80);
2813 addword (tmpreg >> 16);
2814 addword (tmpreg & 0xFFFF);
2821 /* By the time whe get here (FINALLY) the_ins contains the complete
2822 instruction, ready to be emitted. . . */
2826 reverse_16_bits (in)
2832 static int mask[16] =
2834 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2835 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2837 for (n = 0; n < 16; n++)
2840 out |= mask[15 - n];
2843 } /* reverse_16_bits() */
2852 static int mask[8] =
2854 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2857 for (n = 0; n < 8; n++)
2863 } /* reverse_8_bits() */
2865 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2866 (that value is chosen in the frag_var call in md_assemble). TYPE
2867 is the subtype of the frag to be generated; its primary type is
2868 rs_machine_dependent.
2870 The TYPE parameter is also used by md_convert_frag_1 and
2871 md_estimate_size_before_relax. The appropriate type of fixup will
2872 be emitted by md_convert_frag_1.
2874 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2876 install_operand (mode, val)
2883 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2886 the_ins.opcode[0] |= val << 9;
2889 the_ins.opcode[1] |= val << 12;
2892 the_ins.opcode[1] |= val << 6;
2895 the_ins.opcode[1] |= val;
2898 the_ins.opcode[2] |= val << 12;
2901 the_ins.opcode[2] |= val << 6;
2904 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2905 three words long! */
2907 the_ins.opcode[2] |= val;
2910 the_ins.opcode[1] |= val << 7;
2913 the_ins.opcode[1] |= val << 10;
2917 the_ins.opcode[1] |= val << 5;
2922 the_ins.opcode[1] |= (val << 10) | (val << 7);
2925 the_ins.opcode[1] |= (val << 12) | val;
2928 the_ins.opcode[0] |= val = 0xff;
2931 the_ins.opcode[0] |= val << 9;
2934 the_ins.opcode[1] |= val;
2937 the_ins.opcode[1] |= val;
2938 the_ins.numo++; /* What a hack */
2941 the_ins.opcode[1] |= val << 4;
2949 the_ins.opcode[0] |= (val << 6);
2952 the_ins.opcode[1] = (val >> 16);
2953 the_ins.opcode[2] = val & 0xffff;
2957 as_fatal ("failed sanity check.");
2959 } /* install_operand() */
2962 install_gen_operand (mode, val)
2969 the_ins.opcode[0] |= val;
2972 /* This is a kludge!!! */
2973 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2982 the_ins.opcode[0] |= val;
2984 /* more stuff goes here */
2986 as_fatal ("failed sanity check.");
2988 } /* install_gen_operand() */
2991 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2992 * then deal with the bitfield hack.
2996 crack_operand (str, opP)
2998 register struct m68k_op *opP;
3000 register int parens;
3002 register char *beg_str;
3010 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3016 else if (*str == ')')
3020 opP->error = "Extra )";
3026 if (flag_mri && *str == '\'')
3027 inquote = ! inquote;
3029 if (!*str && parens)
3031 opP->error = "Missing )";
3036 if (m68k_ip_op (beg_str, opP) != 0)
3043 c = *++str; /* JF bitfield hack */
3048 as_bad ("Missing operand");
3053 /* This is the guts of the machine-dependent assembler. STR points to a
3054 machine dependent instruction. This function is supposed to emit
3055 the frags/bytes it assembles to.
3059 insert_reg (regname, regnum)
3066 #ifdef REGISTER_PREFIX
3067 if (!flag_reg_prefix_optional)
3069 buf[0] = REGISTER_PREFIX;
3070 strcpy (buf + 1, regname);
3075 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3076 &zero_address_frag));
3078 for (i = 0; regname[i]; i++)
3079 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3082 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3083 &zero_address_frag));
3092 static const struct init_entry init_table[] =
3147 /* control registers */
3148 { "sfc", SFC }, /* Source Function Code */
3150 { "dfc", DFC }, /* Destination Function Code */
3152 { "cacr", CACR }, /* Cache Control Register */
3153 { "caar", CAAR }, /* Cache Address Register */
3155 { "usp", USP }, /* User Stack Pointer */
3156 { "vbr", VBR }, /* Vector Base Register */
3157 { "msp", MSP }, /* Master Stack Pointer */
3158 { "isp", ISP }, /* Interrupt Stack Pointer */
3160 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3161 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3162 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3163 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3165 /* 68ec040 versions of same */
3166 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3167 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3168 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3169 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3171 /* mcf5200 versions of same. The ColdFire programmer's reference
3172 manual indicated that the order is 2,3,0,1, but Ken Rose
3173 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3174 { "acr0", ITT0 }, /* Access Control Unit 0 */
3175 { "acr1", ITT1 }, /* Access Control Unit 1 */
3176 { "acr2", DTT0 }, /* Access Control Unit 2 */
3177 { "acr3", DTT1 }, /* Access Control Unit 3 */
3179 { "tc", TC }, /* MMU Translation Control Register */
3182 { "mmusr", MMUSR }, /* MMU Status Register */
3183 { "srp", SRP }, /* User Root Pointer */
3184 { "urp", URP }, /* Supervisor Root Pointer */
3189 { "rombar", ROMBAR }, /* ROM Base Address Register */
3190 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3191 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3192 { "mbar", MBAR }, /* Module Base Address Register */
3193 /* end of control registers */
3227 /* 68ec030 versions of same */
3230 /* 68ec030 access control unit, identical to 030 MMU status reg */
3233 /* Suppressed data and address registers. */
3258 for (i = 0; init_table[i].name; i++)
3259 insert_reg (init_table[i].name, init_table[i].number);
3262 static int no_68851, no_68881;
3265 /* a.out machine type. Default to 68020. */
3266 int m68k_aout_machtype = 2;
3278 int shorts_this_frag;
3281 /* In MRI mode, the instruction and operands are separated by a
3282 space. Anything following the operands is a comment. The label
3283 has already been removed. */
3291 for (s = str; *s != '\0'; s++)
3293 if ((*s == ' ' || *s == '\t') && ! inquote)
3311 inquote = ! inquote;
3316 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3321 for (n = 0; n < the_ins.numargs; n++)
3322 if (the_ins.operands[n].error)
3324 er = the_ins.operands[n].error;
3330 as_bad ("%s -- statement `%s' ignored", er, str);
3334 /* If there is a current label, record that it marks an instruction. */
3335 if (current_label != NULL)
3337 current_label->text = 1;
3338 current_label = NULL;
3341 if (the_ins.nfrag == 0)
3343 /* No frag hacking involved; just put it out */
3344 toP = frag_more (2 * the_ins.numo);
3345 fromP = &the_ins.opcode[0];
3346 for (m = the_ins.numo; m; --m)
3348 md_number_to_chars (toP, (long) (*fromP), 2);
3352 /* put out symbol-dependent info */
3353 for (m = 0; m < the_ins.nrel; m++)
3355 switch (the_ins.reloc[m].wid)
3373 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3374 the_ins.reloc[m].wid);
3377 fixP = fix_new_exp (frag_now,
3378 ((toP - frag_now->fr_literal)
3379 - the_ins.numo * 2 + the_ins.reloc[m].n),
3381 &the_ins.reloc[m].exp,
3382 the_ins.reloc[m].pcrel,
3383 get_reloc_code (n, the_ins.reloc[m].pcrel,
3384 the_ins.reloc[m].pic_reloc));
3385 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3386 if (the_ins.reloc[m].wid == 'B')
3387 fixP->fx_signed = 1;
3392 /* There's some frag hacking */
3393 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3398 wid = 2 * the_ins.fragb[n].fragoff;
3400 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3401 toP = frag_more (wid);
3403 shorts_this_frag = 0;
3404 for (m = wid / 2; m; --m)
3406 md_number_to_chars (toP, (long) (*fromP), 2);
3411 for (m = 0; m < the_ins.nrel; m++)
3413 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3415 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3418 wid = the_ins.reloc[m].wid;
3421 the_ins.reloc[m].wid = 0;
3422 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3424 fixP = fix_new_exp (frag_now,
3425 ((toP - frag_now->fr_literal)
3426 - the_ins.numo * 2 + the_ins.reloc[m].n),
3428 &the_ins.reloc[m].exp,
3429 the_ins.reloc[m].pcrel,
3430 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3431 the_ins.reloc[m].pic_reloc));
3432 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3434 (void) frag_var (rs_machine_dependent, 10, 0,
3435 (relax_substateT) (the_ins.fragb[n].fragty),
3436 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3438 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3439 shorts_this_frag = 0;
3442 toP = frag_more (n * sizeof (short));
3445 md_number_to_chars (toP, (long) (*fromP), 2);
3451 for (m = 0; m < the_ins.nrel; m++)
3455 wid = the_ins.reloc[m].wid;
3458 the_ins.reloc[m].wid = 0;
3459 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3461 fixP = fix_new_exp (frag_now,
3462 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3463 - shorts_this_frag * 2),
3465 &the_ins.reloc[m].exp,
3466 the_ins.reloc[m].pcrel,
3467 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3468 the_ins.reloc[m].pic_reloc));
3469 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3477 * md_begin -- set up hash tables with 68000 instructions.
3478 * similar to what the vax assembler does. ---phr
3480 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3481 a copy of it at runtime, adding in the information we want but isn't
3482 there. I think it'd be better to have an awk script hack the table
3483 at compile time. Or even just xstr the table and use it as-is. But
3484 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3487 register const struct m68k_opcode *ins;
3488 register struct m68k_incant *hack, *slak;
3489 register const char *retval = 0; /* empty string, or error msg text */
3490 register unsigned int i;
3495 flag_reg_prefix_optional = 1;
3497 if (! m68k_rel32_from_cmdline)
3501 op_hash = hash_new ();
3503 obstack_begin (&robyn, 4000);
3504 for (i = 0; i < m68k_numopcodes; i++)
3506 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3509 ins = &m68k_opcodes[i];
3510 /* We *could* ignore insns that don't match our arch here
3511 but just leaving them out of the hash. */
3512 slak->m_operands = ins->args;
3513 slak->m_opnum = strlen (slak->m_operands) / 2;
3514 slak->m_arch = ins->arch;
3515 slak->m_opcode = ins->opcode;
3516 /* This is kludgey */
3517 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3518 if (i + 1 != m68k_numopcodes
3519 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3521 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3526 slak = slak->m_next;
3530 retval = hash_insert (op_hash, ins->name, (char *) hack);
3532 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3535 for (i = 0; i < m68k_numaliases; i++)
3537 const char *name = m68k_opcode_aliases[i].primary;
3538 const char *alias = m68k_opcode_aliases[i].alias;
3539 PTR val = hash_find (op_hash, name);
3541 as_fatal ("Internal Error: Can't find %s in hash table", name);
3542 retval = hash_insert (op_hash, alias, val);
3544 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3547 /* In MRI mode, all unsized branches are variable sized. Normally,
3548 they are word sized. */
3551 static struct m68k_opcode_alias mri_aliases[] =
3571 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3573 const char *name = mri_aliases[i].primary;
3574 const char *alias = mri_aliases[i].alias;
3575 PTR val = hash_find (op_hash, name);
3577 as_fatal ("Internal Error: Can't find %s in hash table", name);
3578 retval = hash_jam (op_hash, alias, val);
3580 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3584 for (i = 0; i < sizeof (mklower_table); i++)
3585 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3587 for (i = 0; i < sizeof (notend_table); i++)
3589 notend_table[i] = 0;
3590 alt_notend_table[i] = 0;
3592 notend_table[','] = 1;
3593 notend_table['{'] = 1;
3594 notend_table['}'] = 1;
3595 alt_notend_table['a'] = 1;
3596 alt_notend_table['A'] = 1;
3597 alt_notend_table['d'] = 1;
3598 alt_notend_table['D'] = 1;
3599 alt_notend_table['#'] = 1;
3600 alt_notend_table['&'] = 1;
3601 alt_notend_table['f'] = 1;
3602 alt_notend_table['F'] = 1;
3603 #ifdef REGISTER_PREFIX
3604 alt_notend_table[REGISTER_PREFIX] = 1;
3607 /* We need to put '(' in alt_notend_table to handle
3608 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3610 alt_notend_table['('] = 1;
3612 /* We need to put '@' in alt_notend_table to handle
3613 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3615 alt_notend_table['@'] = 1;
3617 /* We need to put digits in alt_notend_table to handle
3618 bfextu %d0{24:1},%d0
3620 alt_notend_table['0'] = 1;
3621 alt_notend_table['1'] = 1;
3622 alt_notend_table['2'] = 1;
3623 alt_notend_table['3'] = 1;
3624 alt_notend_table['4'] = 1;
3625 alt_notend_table['5'] = 1;
3626 alt_notend_table['6'] = 1;
3627 alt_notend_table['7'] = 1;
3628 alt_notend_table['8'] = 1;
3629 alt_notend_table['9'] = 1;
3631 #ifndef MIT_SYNTAX_ONLY
3632 /* Insert pseudo ops, these have to go into the opcode table since
3633 gas expects pseudo ops to start with a dot */
3636 while (mote_pseudo_table[n].poc_name)
3638 hack = (struct m68k_incant *)
3639 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3640 hash_insert (op_hash,
3641 mote_pseudo_table[n].poc_name, (char *) hack);
3642 hack->m_operands = 0;
3652 record_alignment (text_section, 2);
3653 record_alignment (data_section, 2);
3654 record_alignment (bss_section, 2);
3659 select_control_regs ()
3661 /* Note which set of "movec" control registers is available. */
3662 switch (cpu_of_arch (current_architecture))
3665 control_regs = m68000_control_regs;
3668 control_regs = m68010_control_regs;
3672 control_regs = m68020_control_regs;
3675 control_regs = m68040_control_regs;
3678 control_regs = m68060_control_regs;
3681 control_regs = cpu32_control_regs;
3684 control_regs = mcf5200_control_regs;
3692 m68k_init_after_args ()
3694 if (cpu_of_arch (current_architecture) == 0)
3697 const char *default_cpu = TARGET_CPU;
3699 if (*default_cpu == 'm')
3701 for (i = 0; i < n_archs; i++)
3702 if (strcasecmp (default_cpu, archs[i].name) == 0)
3706 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3707 current_architecture |= m68020;
3710 current_architecture |= archs[i].arch;
3712 /* Permit m68881 specification with all cpus; those that can't work
3713 with a coprocessor could be doing emulation. */
3714 if (current_architecture & m68851)
3716 if (current_architecture & m68040)
3718 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3721 /* What other incompatibilities could we check for? */
3723 /* Toss in some default assumptions about coprocessors. */
3725 && (cpu_of_arch (current_architecture)
3726 /* Can CPU32 have a 68881 coprocessor?? */
3727 & (m68020 | m68030 | cpu32)))
3729 current_architecture |= m68881;
3732 && (cpu_of_arch (current_architecture) & m68020up) != 0
3733 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3735 current_architecture |= m68851;
3737 if (no_68881 && (current_architecture & m68881))
3738 as_bad ("options for 68881 and no-68881 both given");
3739 if (no_68851 && (current_architecture & m68851))
3740 as_bad ("options for 68851 and no-68851 both given");
3743 /* Work out the magic number. This isn't very general. */
3744 if (current_architecture & m68000)
3745 m68k_aout_machtype = 0;
3746 else if (current_architecture & m68010)
3747 m68k_aout_machtype = 1;
3748 else if (current_architecture & m68020)
3749 m68k_aout_machtype = 2;
3751 m68k_aout_machtype = 2;
3754 /* Note which set of "movec" control registers is available. */
3755 select_control_regs ();
3757 if (cpu_of_arch (current_architecture) < m68020)
3758 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3761 /* This is called when a label is defined. */
3764 m68k_frob_label (sym)
3767 struct label_line *n;
3769 n = (struct label_line *) xmalloc (sizeof *n);
3772 as_where (&n->file, &n->line);
3777 /* This is called when a value that is not an instruction is emitted. */
3780 m68k_flush_pending_output ()
3782 current_label = NULL;
3785 /* This is called at the end of the assembly, when the final value of
3786 the label is known. We warn if this is a text symbol aligned at an
3790 m68k_frob_symbol (sym)
3793 if ((S_GET_VALUE (sym) & 1) != 0)
3795 struct label_line *l;
3797 for (l = labels; l != NULL; l = l->next)
3799 if (l->label == sym)
3802 as_warn_where (l->file, l->line,
3803 "text label `%s' aligned to odd boundary",
3811 /* This is called if we go in or out of MRI mode because of the .mri
3815 m68k_mri_mode_change (on)
3820 if (! flag_reg_prefix_optional)
3822 flag_reg_prefix_optional = 1;
3823 #ifdef REGISTER_PREFIX
3828 if (! m68k_rel32_from_cmdline)
3833 if (! reg_prefix_optional_seen)
3835 #ifdef REGISTER_PREFIX_OPTIONAL
3836 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3838 flag_reg_prefix_optional = 0;
3840 #ifdef REGISTER_PREFIX
3845 if (! m68k_rel32_from_cmdline)
3850 /* Equal to MAX_PRECISION in atof-ieee.c */
3851 #define MAX_LITTLENUMS 6
3853 /* Turn a string in input_line_pointer into a floating point constant
3854 of type type, and store the appropriate bytes in *litP. The number
3855 of LITTLENUMS emitted is stored in *sizeP . An error message is
3856 returned, or NULL on OK. */
3859 md_atof (type, litP, sizeP)
3865 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3866 LITTLENUM_TYPE *wordP;
3898 return "Bad call to MD_ATOF()";
3900 t = atof_ieee (input_line_pointer, type, words);
3902 input_line_pointer = t;
3904 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3905 for (wordP = words; prec--;)
3907 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3908 litP += sizeof (LITTLENUM_TYPE);
3914 md_number_to_chars (buf, val, n)
3919 number_to_chars_bigendian (buf, val, n);
3923 md_apply_fix_2 (fixP, val)
3927 addressT upper_limit;
3928 offsetT lower_limit;
3930 /* This is unnecessary but it convinces the native rs6000 compiler
3931 to generate the code we want. */
3932 char *buf = fixP->fx_frag->fr_literal;
3933 buf += fixP->fx_where;
3934 /* end ibm compiler workaround */
3936 if (val & 0x80000000)
3937 val |= ~(addressT)0x7fffffff;
3944 memset (buf, 0, fixP->fx_size);
3945 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3950 switch (fixP->fx_size)
3952 /* The cast to offsetT below are necessary to make code correct for
3953 machines where ints are smaller than offsetT */
3957 lower_limit = - (offsetT) 0x80;
3960 *buf++ = (val >> 8);
3962 upper_limit = 0x7fff;
3963 lower_limit = - (offsetT) 0x8000;
3966 *buf++ = (val >> 24);
3967 *buf++ = (val >> 16);
3968 *buf++ = (val >> 8);
3970 upper_limit = 0x7fffffff;
3971 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3974 BAD_CASE (fixP->fx_size);
3977 /* Fix up a negative reloc. */
3978 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3980 fixP->fx_addsy = fixP->fx_subsy;
3981 fixP->fx_subsy = NULL;
3985 /* For non-pc-relative values, it's conceivable we might get something
3986 like "0xff" for a byte field. So extend the upper part of the range
3987 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3988 so that we can do any range checking at all. */
3989 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3990 upper_limit = upper_limit * 2 + 1;
3992 if ((addressT) val > upper_limit
3993 && (val > 0 || val < lower_limit))
3994 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3996 /* A one byte PC-relative reloc means a short branch. We can't use
3997 a short branch with a value of 0 or -1, because those indicate
3998 different opcodes (branches with longer offsets). */
4000 && fixP->fx_size == 1
4001 && (fixP->fx_addsy == NULL
4002 || S_IS_DEFINED (fixP->fx_addsy))
4003 && (val == 0 || val == -1))
4004 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4007 #ifdef BFD_ASSEMBLER
4009 md_apply_fix (fixP, valp)
4013 md_apply_fix_2 (fixP, (addressT) *valp);
4017 void md_apply_fix (fixP, val)
4021 md_apply_fix_2 (fixP, (addressT) val);
4025 /* *fragP has been relaxed to its final size, and now needs to have
4026 the bytes inside it modified to conform to the new size There is UGLY
4030 md_convert_frag_1 (fragP)
4031 register fragS *fragP;
4037 /* Address in object code of the displacement. */
4038 register int object_address = fragP->fr_fix + fragP->fr_address;
4040 /* Address in gas core of the place to store the displacement. */
4041 /* This convinces the native rs6000 compiler to generate the code we
4043 register char *buffer_address = fragP->fr_literal;
4044 buffer_address += fragP->fr_fix;
4045 /* end ibm compiler workaround */
4047 /* The displacement of the address, from current location. */
4048 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4049 disp = (disp + fragP->fr_offset) - object_address;
4051 #ifdef BFD_ASSEMBLER
4052 disp += fragP->fr_symbol->sy_frag->fr_address;
4055 switch (fragP->fr_subtype)
4057 case TAB (BCC68000, BYTE):
4058 case TAB (ABRANCH, BYTE):
4059 know (issbyte (disp));
4061 as_bad ("short branch with zero offset: use :w");
4062 fragP->fr_opcode[1] = disp;
4065 case TAB (DBCC, SHORT):
4066 know (issword (disp));
4069 case TAB (BCC68000, SHORT):
4070 case TAB (ABRANCH, SHORT):
4071 know (issword (disp));
4072 fragP->fr_opcode[1] = 0x00;
4075 case TAB (ABRANCH, LONG):
4076 if (cpu_of_arch (current_architecture) < m68020)
4078 if (fragP->fr_opcode[0] == 0x61)
4081 fragP->fr_opcode[0] = 0x4E;
4082 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4096 else if (fragP->fr_opcode[0] == 0x60)
4098 fragP->fr_opcode[0] = 0x4E;
4099 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4100 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4101 fragP->fr_offset, 0, NO_RELOC);
4107 as_bad ("Long branch offset not supported.");
4112 fragP->fr_opcode[1] = (char) 0xff;
4116 case TAB (BCC68000, LONG):
4117 /* only Bcc 68000 instructions can come here */
4118 /* change bcc into b!cc/jmp absl long */
4119 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4120 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4122 /* JF: these used to be fr_opcode[2,3], but they may be in a
4123 different frag, in which case refering to them is a no-no.
4124 Only fr_opcode[0,1] are guaranteed to work. */
4125 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4126 *buffer_address++ = (char) 0xf9;
4127 fragP->fr_fix += 2; /* account for jmp instruction */
4128 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4129 fragP->fr_offset, 0, NO_RELOC);
4133 case TAB (DBCC, LONG):
4134 /* only DBcc 68000 instructions can come here */
4135 /* change dbcc into dbcc/jmp absl long */
4136 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4137 *buffer_address++ = 0x00; /* branch offset = 4 */
4138 *buffer_address++ = 0x04;
4139 *buffer_address++ = 0x60; /* put in bra pc+6 */
4140 *buffer_address++ = 0x06;
4141 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4142 *buffer_address++ = (char) 0xf9;
4144 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4145 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4146 fragP->fr_offset, 0, NO_RELOC);
4150 case TAB (FBRANCH, SHORT):
4151 know ((fragP->fr_opcode[1] & 0x40) == 0);
4154 case TAB (FBRANCH, LONG):
4155 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4158 case TAB (PCREL, SHORT):
4161 case TAB (PCREL, LONG):
4162 /* The thing to do here is force it to ABSOLUTE LONG, since
4163 PCREL is really trying to shorten an ABSOLUTE address anyway */
4164 /* JF FOO This code has not been tested */
4165 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4167 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4168 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4169 (unsigned) fragP->fr_opcode[0],
4170 (unsigned long) fragP->fr_address);
4171 fragP->fr_opcode[1] &= ~0x3F;
4172 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4176 case TAB (PCLEA, SHORT):
4177 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4178 fragP->fr_offset, 1, NO_RELOC);
4179 fragP->fr_opcode[1] &= ~0x3F;
4180 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4183 case TAB (PCLEA, LONG):
4184 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4185 fragP->fr_offset, 1, NO_RELOC);
4186 fixP->fx_pcrel_adjust = 2;
4187 /* Already set to mode 7.3; this indicates: PC indirect with
4188 suppressed index, 32-bit displacement. */
4189 *buffer_address++ = 0x01;
4190 *buffer_address++ = 0x70;
4195 case TAB (PCINDEX, BYTE):
4197 if (!issbyte (disp))
4199 as_bad ("displacement doesn't fit in one byte");
4202 assert (fragP->fr_fix >= 2);
4203 buffer_address[-2] &= ~1;
4204 buffer_address[-1] = disp;
4207 case TAB (PCINDEX, SHORT):
4209 assert (issword (disp));
4210 assert (fragP->fr_fix >= 2);
4211 buffer_address[-2] |= 0x1;
4212 buffer_address[-1] = 0x20;
4213 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4214 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4216 fixP->fx_pcrel_adjust = 2;
4219 case TAB (PCINDEX, LONG):
4221 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4222 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4224 fixP->fx_pcrel_adjust = 2;
4225 assert (fragP->fr_fix >= 2);
4226 buffer_address[-2] |= 0x1;
4227 buffer_address[-1] = 0x30;
4234 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4235 fragP->fr_fix += ext;
4239 #ifndef BFD_ASSEMBLER
4242 md_convert_frag (headers, sec, fragP)
4243 object_headers *headers;
4247 md_convert_frag_1 (fragP);
4253 md_convert_frag (abfd, sec, fragP)
4258 md_convert_frag_1 (fragP);
4262 /* Force truly undefined symbols to their maximum size, and generally set up
4263 the frag list to be relaxed
4266 md_estimate_size_before_relax (fragP, segment)
4267 register fragS *fragP;
4271 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4273 old_fix = fragP->fr_fix;
4275 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4276 switch (fragP->fr_subtype)
4279 case TAB (ABRANCH, SZ_UNDEF):
4281 if ((fragP->fr_symbol != NULL) /* Not absolute */
4282 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4284 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4287 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4289 /* On 68000, or for absolute value, switch to abs long */
4290 /* FIXME, we should check abs val, pick short or long */
4291 if (fragP->fr_opcode[0] == 0x61)
4293 fragP->fr_opcode[0] = 0x4E;
4294 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4295 fix_new (fragP, fragP->fr_fix, 4,
4296 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4300 else if (fragP->fr_opcode[0] == 0x60)
4302 fragP->fr_opcode[0] = 0x4E;
4303 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4304 fix_new (fragP, fragP->fr_fix, 4,
4305 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4311 as_warn ("Long branch offset to extern symbol not supported.");
4315 { /* Symbol is still undefined. Make it simple */
4316 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4317 fragP->fr_offset, 1, NO_RELOC);
4319 fragP->fr_opcode[1] = (char) 0xff;
4325 } /* case TAB(ABRANCH,SZ_UNDEF) */
4327 case TAB (FBRANCH, SZ_UNDEF):
4329 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4331 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4336 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4337 fragP->fr_offset, 1, NO_RELOC);
4339 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4343 } /* TAB(FBRANCH,SZ_UNDEF) */
4345 case TAB (PCREL, SZ_UNDEF):
4347 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4349 || cpu_of_arch (current_architecture) < m68020)
4351 fragP->fr_subtype = TAB (PCREL, SHORT);
4356 fragP->fr_subtype = TAB (PCREL, LONG);
4360 } /* TAB(PCREL,SZ_UNDEF) */
4362 case TAB (BCC68000, SZ_UNDEF):
4364 if ((fragP->fr_symbol != NULL)
4365 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4367 fragP->fr_subtype = TAB (BCC68000, BYTE);
4370 /* only Bcc 68000 instructions can come here */
4371 /* change bcc into b!cc/jmp absl long */
4372 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4373 if (flag_short_refs)
4375 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4376 /* JF: these were fr_opcode[2,3] */
4377 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4378 buffer_address[1] = (char) 0xf8;
4379 fragP->fr_fix += 2; /* account for jmp instruction */
4380 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4381 fragP->fr_offset, 0, NO_RELOC);
4386 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4387 /* JF: these were fr_opcode[2,3] */
4388 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4389 buffer_address[1] = (char) 0xf9;
4390 fragP->fr_fix += 2; /* account for jmp instruction */
4391 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4392 fragP->fr_offset, 0, NO_RELOC);
4397 } /* case TAB(BCC68000,SZ_UNDEF) */
4399 case TAB (DBCC, SZ_UNDEF):
4401 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4403 fragP->fr_subtype = TAB (DBCC, SHORT);
4407 /* only DBcc 68000 instructions can come here */
4408 /* change dbcc into dbcc/jmp absl long */
4409 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4410 buffer_address[0] = 0x00; /* branch offset = 4 */
4411 buffer_address[1] = 0x04;
4412 buffer_address[2] = 0x60; /* put in bra pc + ... */
4414 if (flag_short_refs)
4416 /* JF: these were fr_opcode[5-7] */
4417 buffer_address[3] = 0x04; /* plus 4 */
4418 buffer_address[4] = 0x4e; /* Put in Jump Word */
4419 buffer_address[5] = (char) 0xf8;
4420 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4421 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4422 fragP->fr_offset, 0, NO_RELOC);
4427 /* JF: these were fr_opcode[5-7] */
4428 buffer_address[3] = 0x06; /* Plus 6 */
4429 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4430 buffer_address[5] = (char) 0xf9;
4431 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4432 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4433 fragP->fr_offset, 0, NO_RELOC);
4439 } /* case TAB(DBCC,SZ_UNDEF) */
4441 case TAB (PCLEA, SZ_UNDEF):
4443 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4445 || cpu_of_arch (current_architecture) < m68020)
4447 fragP->fr_subtype = TAB (PCLEA, SHORT);
4452 fragP->fr_subtype = TAB (PCLEA, LONG);
4456 } /* TAB(PCLEA,SZ_UNDEF) */
4458 case TAB (PCINDEX, SZ_UNDEF):
4459 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4460 || cpu_of_arch (current_architecture) < m68020)
4462 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4466 fragP->fr_subtype = TAB (PCINDEX, LONG);
4475 /* now that SZ_UNDEF are taken care of, check others */
4476 switch (fragP->fr_subtype)
4478 case TAB (BCC68000, BYTE):
4479 case TAB (ABRANCH, BYTE):
4480 /* We can't do a short jump to the next instruction, so in that
4481 case we force word mode. At this point S_GET_VALUE should
4482 return the offset of the symbol within its frag. If the
4483 symbol is at the start of a frag, and it is the next frag
4484 with any data in it (usually this is just the next frag, but
4485 assembler listings may introduce empty frags), we must use
4487 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4491 for (l = fragP->fr_next;
4492 l != fragP->fr_symbol->sy_frag;
4494 if (l->fr_fix + l->fr_var != 0)
4496 if (l == fragP->fr_symbol->sy_frag)
4498 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4506 return fragP->fr_var + fragP->fr_fix - old_fix;
4509 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4510 /* the bit-field entries in the relocation_info struct plays hell
4511 with the byte-order problems of cross-assembly. So as a hack,
4512 I added this mach. dependent ri twiddler. Ugly, but it gets
4514 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4515 are symbolnum, most sig. byte first. Last byte is broken up with
4516 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4517 nibble as nuthin. (on Sun 3 at least) */
4518 /* Translate the internal relocation information into target-specific
4522 md_ri_to_chars (the_bytes, ri)
4524 struct reloc_info_generic *ri;
4527 md_number_to_chars (the_bytes, ri->r_address, 4);
4528 /* now the fun stuff */
4529 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4530 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4531 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4532 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4533 ((ri->r_extern << 4) & 0x10));
4536 #endif /* comment */
4538 #ifndef BFD_ASSEMBLER
4540 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4543 relax_addressT segment_address_in_file;
4546 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4547 * Out: GNU LD relocation length code: 0, 1, or 2.
4550 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4553 know (fixP->fx_addsy != NULL);
4555 md_number_to_chars (where,
4556 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4559 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4560 ? S_GET_TYPE (fixP->fx_addsy)
4561 : fixP->fx_addsy->sy_number);
4563 where[4] = (r_symbolnum >> 16) & 0x0ff;
4564 where[5] = (r_symbolnum >> 8) & 0x0ff;
4565 where[6] = r_symbolnum & 0x0ff;
4566 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4567 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4571 #endif /* OBJ_AOUT or OBJ_BOUT */
4573 #ifndef WORKING_DOT_WORD
4574 CONST int md_short_jump_size = 4;
4575 CONST int md_long_jump_size = 6;
4578 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4580 addressT from_addr, to_addr;
4586 offset = to_addr - (from_addr + 2);
4588 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4589 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4593 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4595 addressT from_addr, to_addr;
4601 if (cpu_of_arch (current_architecture) < m68020)
4603 offset = to_addr - S_GET_VALUE (to_symbol);
4604 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4605 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4606 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4611 offset = to_addr - (from_addr + 2);
4612 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4613 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4619 /* Different values of OK tell what its OK to return. Things that
4620 aren't OK are an error (what a shock, no?)
4623 10: Absolute 1:8 only
4624 20: Absolute 0:7 only
4625 30: absolute 0:15 only
4626 40: Absolute 0:31 only
4627 50: absolute 0:127 only
4628 55: absolute -64:63 only
4629 60: absolute -128:127 only
4630 70: absolute 0:4095 only
4637 struct m68k_exp *exp;
4640 if (exp->exp.X_op == O_absent)
4642 /* Do the same thing the VAX asm does */
4643 op (exp) = O_constant;
4649 as_warn ("expression out of range: defaulting to 1");
4653 else if (exp->exp.X_op == O_constant)
4658 if (offs (exp) < 1 || offs (exp) > 8)
4660 as_warn ("expression out of range: defaulting to 1");
4665 if (offs (exp) < 0 || offs (exp) > 7)
4669 if (offs (exp) < 0 || offs (exp) > 15)
4673 if (offs (exp) < 0 || offs (exp) > 32)
4677 if (offs (exp) < 0 || offs (exp) > 127)
4681 if (offs (exp) < -64 || offs (exp) > 63)
4685 if (offs (exp) < -128 || offs (exp) > 127)
4689 if (offs (exp) < 0 || offs (exp) > 4095)
4692 as_warn ("expression out of range: defaulting to 0");
4700 else if (exp->exp.X_op == O_big)
4702 if (offs (exp) <= 0 /* flonum */
4703 && (ok == 80 /* no bignums */
4704 || (ok > 10 /* small-int ranges including 0 ok */
4705 /* If we have a flonum zero, a zero integer should
4706 do as well (e.g., in moveq). */
4707 && generic_floating_point_number.exponent == 0
4708 && generic_floating_point_number.low[0] == 0)))
4710 /* HACK! Turn it into a long */
4711 LITTLENUM_TYPE words[6];
4713 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4714 op (exp) = O_constant;
4717 offs (exp) = words[1] | (words[0] << 16);
4721 op (exp) = O_constant;
4724 offs (exp) = (ok == 10) ? 1 : 0;
4725 as_warn ("Can't deal with expression; defaulting to %ld",
4731 if (ok >= 10 && ok <= 70)
4733 op (exp) = O_constant;
4736 offs (exp) = (ok == 10) ? 1 : 0;
4737 as_warn ("Can't deal with expression; defaulting to %ld",
4742 if (exp->size != SIZE_UNSPEC)
4750 if (!isbyte (offs (exp)))
4751 as_warn ("expression doesn't fit in BYTE");
4754 if (!isword (offs (exp)))
4755 as_warn ("expression doesn't fit in WORD");
4763 /* These are the back-ends for the various machine dependent pseudo-ops. */
4764 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4770 subseg_set (data_section, 1);
4771 demand_empty_rest_of_line ();
4778 subseg_set (data_section, 2);
4779 demand_empty_rest_of_line ();
4786 /* We don't support putting frags in the BSS segment, we fake it
4787 by marking in_bss, then looking at s_skip for clues. */
4789 subseg_set (bss_section, 0);
4790 demand_empty_rest_of_line ();
4798 register long temp_fill;
4800 temp = 1; /* JF should be 2? */
4801 temp_fill = get_absolute_expression ();
4802 if (!need_pass_2) /* Never make frag if expect extra pass. */
4803 frag_align (temp, (int) temp_fill);
4804 demand_empty_rest_of_line ();
4805 record_alignment (now_seg, temp);
4812 demand_empty_rest_of_line ();
4815 /* Pseudo-ops handled for MRI compatibility. */
4817 /* This function returns non-zero if the argument is a conditional
4818 pseudo-op. This is called when checking whether a pending
4819 alignment is needed. */
4822 m68k_conditional_pseudoop (pop)
4825 return (pop->poc_handler == s_mri_if
4826 || pop->poc_handler == s_mri_else);
4829 /* Handle an MRI style chip specification. */
4838 s = input_line_pointer;
4839 c = get_symbol_end ();
4840 for (i = 0; i < n_archs; i++)
4841 if (strcasecmp (s, archs[i].name) == 0)
4845 as_bad ("%s: unrecognized processor name", s);
4846 *input_line_pointer = c;
4847 ignore_rest_of_line ();
4850 *input_line_pointer = c;
4852 if (*input_line_pointer == '/')
4853 current_architecture = 0;
4855 current_architecture &= m68881 | m68851;
4856 current_architecture |= archs[i].arch;
4858 while (*input_line_pointer == '/')
4860 ++input_line_pointer;
4861 s = input_line_pointer;
4862 c = get_symbol_end ();
4863 if (strcmp (s, "68881") == 0)
4864 current_architecture |= m68881;
4865 else if (strcmp (s, "68851") == 0)
4866 current_architecture |= m68851;
4867 *input_line_pointer = c;
4870 /* Update info about available control registers. */
4871 select_control_regs ();
4874 /* The MRI CHIP pseudo-op. */
4884 stop = mri_comment_field (&stopc);
4887 mri_comment_end (stop, stopc);
4888 demand_empty_rest_of_line ();
4891 /* The MRI FOPT pseudo-op. */
4899 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4903 input_line_pointer += 3;
4904 temp = get_absolute_expression ();
4905 if (temp < 0 || temp > 7)
4906 as_bad ("bad coprocessor id");
4908 m68k_float_copnum = COP0 + temp;
4912 as_bad ("unrecognized fopt option");
4913 ignore_rest_of_line ();
4917 demand_empty_rest_of_line ();
4920 /* The structure used to handle the MRI OPT pseudo-op. */
4924 /* The name of the option. */
4927 /* If this is not NULL, just call this function. The first argument
4928 is the ARG field of this structure, the second argument is
4929 whether the option was negated. */
4930 void (*pfn) PARAMS ((int arg, int on));
4932 /* If this is not NULL, and the PFN field is NULL, set the variable
4933 this points to. Set it to the ARG field if the option was not
4934 negated, and the NOTARG field otherwise. */
4937 /* The value to pass to PFN or to assign to *PVAR. */
4940 /* The value to assign to *PVAR if the option is negated. If PFN is
4941 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4942 the option may not be negated. */
4946 /* The table used to handle the MRI OPT pseudo-op. */
4948 static void skip_to_comma PARAMS ((int, int));
4949 static void opt_nest PARAMS ((int, int));
4950 static void opt_chip PARAMS ((int, int));
4951 static void opt_list PARAMS ((int, int));
4952 static void opt_list_symbols PARAMS ((int, int));
4954 static const struct opt_action opt_table[] =
4956 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4958 /* We do relaxing, so there is little use for these options. */
4959 { "b", 0, 0, 0, 0 },
4960 { "brs", 0, 0, 0, 0 },
4961 { "brb", 0, 0, 0, 0 },
4962 { "brl", 0, 0, 0, 0 },
4963 { "brw", 0, 0, 0, 0 },
4965 { "c", 0, 0, 0, 0 },
4966 { "cex", 0, 0, 0, 0 },
4967 { "case", 0, &symbols_case_sensitive, 1, 0 },
4968 { "cl", 0, 0, 0, 0 },
4969 { "cre", 0, 0, 0, 0 },
4970 { "d", 0, &flag_keep_locals, 1, 0 },
4971 { "e", 0, 0, 0, 0 },
4972 { "f", 0, &flag_short_refs, 1, 0 },
4973 { "frs", 0, &flag_short_refs, 1, 0 },
4974 { "frl", 0, &flag_short_refs, 0, 1 },
4975 { "g", 0, 0, 0, 0 },
4976 { "i", 0, 0, 0, 0 },
4977 { "m", 0, 0, 0, 0 },
4978 { "mex", 0, 0, 0, 0 },
4979 { "mc", 0, 0, 0, 0 },
4980 { "md", 0, 0, 0, 0 },
4981 { "nest", opt_nest, 0, 0, 0 },
4982 { "next", skip_to_comma, 0, 0, 0 },
4983 { "o", 0, 0, 0, 0 },
4984 { "old", 0, 0, 0, 0 },
4985 { "op", skip_to_comma, 0, 0, 0 },
4986 { "pco", 0, 0, 0, 0 },
4987 { "p", opt_chip, 0, 0, 0 },
4988 { "pcr", 0, 0, 0, 0 },
4989 { "pcs", 0, 0, 0, 0 },
4990 { "r", 0, 0, 0, 0 },
4991 { "quick", 0, &m68k_quick, 1, 0 },
4992 { "rel32", 0, &m68k_rel32, 1, 0 },
4993 { "s", opt_list, 0, 0, 0 },
4994 { "t", opt_list_symbols, 0, 0, 0 },
4995 { "w", 0, &flag_no_warnings, 0, 1 },
4999 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5001 /* The MRI OPT pseudo-op. */
5013 const struct opt_action *o;
5018 if (*input_line_pointer == '-')
5020 ++input_line_pointer;
5023 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5025 input_line_pointer += 2;
5029 s = input_line_pointer;
5030 c = get_symbol_end ();
5032 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5034 if (strcasecmp (s, o->name) == 0)
5038 /* Restore input_line_pointer now in case the option
5040 *input_line_pointer = c;
5041 (*o->pfn) (o->arg, t);
5043 else if (o->pvar != NULL)
5045 if (! t && o->arg == o->notarg)
5046 as_bad ("option `%s' may not be negated", s);
5047 *input_line_pointer = c;
5048 *o->pvar = t ? o->arg : o->notarg;
5051 *input_line_pointer = c;
5057 as_bad ("option `%s' not recognized", s);
5058 *input_line_pointer = c;
5061 while (*input_line_pointer++ == ',');
5063 /* Move back to terminating character. */
5064 --input_line_pointer;
5065 demand_empty_rest_of_line ();
5068 /* Skip ahead to a comma. This is used for OPT options which we do
5069 not suppor tand which take arguments. */
5072 skip_to_comma (arg, on)
5076 while (*input_line_pointer != ','
5077 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5078 ++input_line_pointer;
5081 /* Handle the OPT NEST=depth option. */
5088 if (*input_line_pointer != '=')
5090 as_bad ("bad format of OPT NEST=depth");
5094 ++input_line_pointer;
5095 max_macro_nest = get_absolute_expression ();
5098 /* Handle the OPT P=chip option. */
5105 if (*input_line_pointer != '=')
5107 /* This is just OPT P, which we do not support. */
5111 ++input_line_pointer;
5115 /* Handle the OPT S option. */
5125 /* Handle the OPT T option. */
5128 opt_list_symbols (arg, on)
5133 listing |= LISTING_SYMBOLS;
5135 listing &=~ LISTING_SYMBOLS;
5138 /* Handle the MRI REG pseudo-op. */
5151 if (line_label == NULL)
5153 as_bad ("missing label");
5154 ignore_rest_of_line ();
5159 stop = mri_comment_field (&stopc);
5163 s = input_line_pointer;
5164 while (isalnum ((unsigned char) *input_line_pointer)
5165 #ifdef REGISTER_PREFIX
5166 || *input_line_pointer == REGISTER_PREFIX
5168 || *input_line_pointer == '/'
5169 || *input_line_pointer == '-')
5170 ++input_line_pointer;
5171 c = *input_line_pointer;
5172 *input_line_pointer = '\0';
5174 if (m68k_ip_op (s, &rop) != 0)
5176 if (rop.error == NULL)
5177 as_bad ("bad register list");
5179 as_bad ("bad register list: %s", rop.error);
5180 *input_line_pointer = c;
5181 ignore_rest_of_line ();
5185 *input_line_pointer = c;
5187 if (rop.mode == REGLST)
5189 else if (rop.mode == DREG)
5190 mask = 1 << (rop.reg - DATA0);
5191 else if (rop.mode == AREG)
5192 mask = 1 << (rop.reg - ADDR0 + 8);
5193 else if (rop.mode == FPREG)
5194 mask = 1 << (rop.reg - FP0 + 16);
5195 else if (rop.mode == CONTROL
5198 else if (rop.mode == CONTROL
5201 else if (rop.mode == CONTROL
5206 as_bad ("bad register list");
5207 ignore_rest_of_line ();
5211 S_SET_SEGMENT (line_label, absolute_section);
5212 S_SET_VALUE (line_label, mask);
5213 line_label->sy_frag = &zero_address_frag;
5216 mri_comment_end (stop, stopc);
5218 demand_empty_rest_of_line ();
5221 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5225 struct save_opts *next;
5227 int symbols_case_sensitive;
5235 /* FIXME: We don't save OPT S. */
5238 /* This variable holds the stack of saved options. */
5240 static struct save_opts *save_stack;
5242 /* The MRI SAVE pseudo-op. */
5248 struct save_opts *s;
5250 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5251 s->abspcadd = m68k_abspcadd;
5252 s->symbols_case_sensitive = symbols_case_sensitive;
5253 s->keep_locals = flag_keep_locals;
5254 s->short_refs = flag_short_refs;
5255 s->architecture = current_architecture;
5256 s->quick = m68k_quick;
5257 s->rel32 = m68k_rel32;
5258 s->listing = listing;
5259 s->no_warnings = flag_no_warnings;
5261 s->next = save_stack;
5264 demand_empty_rest_of_line ();
5267 /* The MRI RESTORE pseudo-op. */
5273 struct save_opts *s;
5275 if (save_stack == NULL)
5277 as_bad ("restore without save");
5278 ignore_rest_of_line ();
5283 save_stack = s->next;
5285 m68k_abspcadd = s->abspcadd;
5286 symbols_case_sensitive = s->symbols_case_sensitive;
5287 flag_keep_locals = s->keep_locals;
5288 flag_short_refs = s->short_refs;
5289 current_architecture = s->architecture;
5290 m68k_quick = s->quick;
5291 m68k_rel32 = s->rel32;
5292 listing = s->listing;
5293 flag_no_warnings = s->no_warnings;
5297 demand_empty_rest_of_line ();
5300 /* Types of MRI structured control directives. */
5302 enum mri_control_type
5310 /* This structure is used to stack the MRI structured control
5313 struct mri_control_info
5315 /* The directive within which this one is enclosed. */
5316 struct mri_control_info *outer;
5318 /* The type of directive. */
5319 enum mri_control_type type;
5321 /* Whether an ELSE has been in an IF. */
5324 /* The add or sub statement at the end of a FOR. */
5327 /* The label of the top of a FOR or REPEAT loop. */
5330 /* The label to jump to for the next iteration, or the else
5331 expression of a conditional. */
5334 /* The label to jump to to break out of the loop, or the label past
5335 the end of a conditional. */
5339 /* The stack of MRI structured control directives. */
5341 static struct mri_control_info *mri_control_stack;
5343 /* The current MRI structured control directive index number, used to
5344 generate label names. */
5346 static int mri_control_index;
5348 /* Some function prototypes. */
5350 static char *mri_control_label PARAMS ((void));
5351 static struct mri_control_info *push_mri_control
5352 PARAMS ((enum mri_control_type));
5353 static void pop_mri_control PARAMS ((void));
5354 static int parse_mri_condition PARAMS ((int *));
5355 static int parse_mri_control_operand
5356 PARAMS ((int *, char **, char **, char **, char **));
5357 static int swap_mri_condition PARAMS ((int));
5358 static int reverse_mri_condition PARAMS ((int));
5359 static void build_mri_control_operand
5360 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5361 const char *, int));
5362 static void parse_mri_control_expression
5363 PARAMS ((char *, int, const char *, const char *, int));
5365 /* Generate a new MRI label structured control directive label name. */
5368 mri_control_label ()
5372 n = (char *) xmalloc (20);
5373 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5374 ++mri_control_index;
5378 /* Create a new MRI structured control directive. */
5380 static struct mri_control_info *
5381 push_mri_control (type)
5382 enum mri_control_type type;
5384 struct mri_control_info *n;
5386 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5390 if (type == mri_if || type == mri_while)
5393 n->top = mri_control_label ();
5394 n->next = mri_control_label ();
5395 n->bottom = mri_control_label ();
5397 n->outer = mri_control_stack;
5398 mri_control_stack = n;
5403 /* Pop off the stack of MRI structured control directives. */
5408 struct mri_control_info *n;
5410 n = mri_control_stack;
5411 mri_control_stack = n->outer;
5419 /* Recognize a condition code in an MRI structured control expression. */
5422 parse_mri_condition (pcc)
5427 know (*input_line_pointer == '<');
5429 ++input_line_pointer;
5430 c1 = *input_line_pointer++;
5431 c2 = *input_line_pointer++;
5433 if (*input_line_pointer != '>')
5435 as_bad ("syntax error in structured control directive");
5439 ++input_line_pointer;
5447 *pcc = (c1 << 8) | c2;
5452 /* Parse a single operand in an MRI structured control expression. */
5455 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5472 if (*input_line_pointer == '<')
5474 /* It's just a condition code. */
5475 return parse_mri_condition (pcc);
5478 /* Look ahead for the condition code. */
5479 for (s = input_line_pointer; *s != '\0'; ++s)
5481 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5486 as_bad ("missing condition code in structured control directive");
5490 *leftstart = input_line_pointer;
5492 if (*leftstop > *leftstart
5493 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5496 input_line_pointer = s;
5497 if (! parse_mri_condition (pcc))
5500 /* Look ahead for AND or OR or end of line. */
5501 for (s = input_line_pointer; *s != '\0'; ++s)
5503 if ((strncasecmp (s, "AND", 3) == 0
5504 && (s[3] == '.' || ! is_part_of_name (s[3])))
5505 || (strncasecmp (s, "OR", 2) == 0
5506 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5510 *rightstart = input_line_pointer;
5512 if (*rightstop > *rightstart
5513 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5516 input_line_pointer = s;
5521 #define MCC(b1, b2) (((b1) << 8) | (b2))
5523 /* Swap the sense of a condition. This changes the condition so that
5524 it generates the same result when the operands are swapped. */
5527 swap_mri_condition (cc)
5532 case MCC ('h', 'i'): return MCC ('c', 's');
5533 case MCC ('l', 's'): return MCC ('c', 'c');
5534 case MCC ('c', 'c'): return MCC ('l', 's');
5535 case MCC ('c', 's'): return MCC ('h', 'i');
5536 case MCC ('p', 'l'): return MCC ('m', 'i');
5537 case MCC ('m', 'i'): return MCC ('p', 'l');
5538 case MCC ('g', 'e'): return MCC ('l', 'e');
5539 case MCC ('l', 't'): return MCC ('g', 't');
5540 case MCC ('g', 't'): return MCC ('l', 't');
5541 case MCC ('l', 'e'): return MCC ('g', 'e');
5546 /* Reverse the sense of a condition. */
5549 reverse_mri_condition (cc)
5554 case MCC ('h', 'i'): return MCC ('l', 's');
5555 case MCC ('l', 's'): return MCC ('h', 'i');
5556 case MCC ('c', 'c'): return MCC ('c', 's');
5557 case MCC ('c', 's'): return MCC ('c', 'c');
5558 case MCC ('n', 'e'): return MCC ('e', 'q');
5559 case MCC ('e', 'q'): return MCC ('n', 'e');
5560 case MCC ('v', 'c'): return MCC ('v', 's');
5561 case MCC ('v', 's'): return MCC ('v', 'c');
5562 case MCC ('p', 'l'): return MCC ('m', 'i');
5563 case MCC ('m', 'i'): return MCC ('p', 'l');
5564 case MCC ('g', 'e'): return MCC ('l', 't');
5565 case MCC ('l', 't'): return MCC ('g', 'e');
5566 case MCC ('g', 't'): return MCC ('l', 'e');
5567 case MCC ('l', 'e'): return MCC ('g', 't');
5572 /* Build an MRI structured control expression. This generates test
5573 and branch instructions. It goes to TRUELAB if the condition is
5574 true, and to FALSELAB if the condition is false. Exactly one of
5575 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5576 is the size qualifier for the expression. EXTENT is the size to
5577 use for the branch. */
5580 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5581 rightstop, truelab, falselab, extent)
5588 const char *truelab;
5589 const char *falselab;
5595 if (leftstart != NULL)
5597 struct m68k_op leftop, rightop;
5600 /* Swap the compare operands, if necessary, to produce a legal
5601 m68k compare instruction. Comparing a register operand with
5602 a non-register operand requires the register to be on the
5603 right (cmp, cmpa). Comparing an immediate value with
5604 anything requires the immediate value to be on the left
5609 (void) m68k_ip_op (leftstart, &leftop);
5614 (void) m68k_ip_op (rightstart, &rightop);
5617 if (rightop.mode == IMMED
5618 || ((leftop.mode == DREG || leftop.mode == AREG)
5619 && (rightop.mode != DREG && rightop.mode != AREG)))
5623 cc = swap_mri_condition (cc);
5625 leftstart = rightstart;
5628 leftstop = rightstop;
5633 if (truelab == NULL)
5635 cc = reverse_mri_condition (cc);
5639 if (leftstart != NULL)
5641 buf = (char *) xmalloc (20
5642 + (leftstop - leftstart)
5643 + (rightstop - rightstart));
5651 memcpy (s, leftstart, leftstop - leftstart);
5652 s += leftstop - leftstart;
5654 memcpy (s, rightstart, rightstop - rightstart);
5655 s += rightstop - rightstart;
5661 buf = (char *) xmalloc (20 + strlen (truelab));
5669 strcpy (s, truelab);
5674 /* Parse an MRI structured control expression. This generates test
5675 and branch instructions. STOP is where the expression ends. It
5676 goes to TRUELAB if the condition is true, and to FALSELAB if the
5677 condition is false. Exactly one of TRUELAB and FALSELAB will be
5678 NULL, meaning to fall through. QUAL is the size qualifier for the
5679 expression. EXTENT is the size to use for the branch. */
5682 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5685 const char *truelab;
5686 const char *falselab;
5699 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5700 &rightstart, &rightstop))
5706 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5710 if (falselab != NULL)
5713 flab = mri_control_label ();
5715 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5716 rightstop, (const char *) NULL, flab, extent);
5718 input_line_pointer += 3;
5719 if (*input_line_pointer != '.'
5720 || input_line_pointer[1] == '\0')
5724 qual = input_line_pointer[1];
5725 input_line_pointer += 2;
5728 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5729 &rightstart, &rightstop))
5735 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5736 rightstop, truelab, falselab, extent);
5738 if (falselab == NULL)
5741 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5745 if (truelab != NULL)
5748 tlab = mri_control_label ();
5750 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5751 rightstop, tlab, (const char *) NULL, extent);
5753 input_line_pointer += 2;
5754 if (*input_line_pointer != '.'
5755 || input_line_pointer[1] == '\0')
5759 qual = input_line_pointer[1];
5760 input_line_pointer += 2;
5763 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5764 &rightstart, &rightstop))
5770 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5771 rightstop, truelab, falselab, extent);
5773 if (truelab == NULL)
5778 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5779 rightstop, truelab, falselab, extent);
5783 if (input_line_pointer != stop)
5784 as_bad ("syntax error in structured control directive");
5787 /* Handle the MRI IF pseudo-op. This may be a structured control
5788 directive, or it may be a regular assembler conditional, depending
5797 struct mri_control_info *n;
5799 /* A structured control directive must end with THEN with an
5800 optional qualifier. */
5801 s = input_line_pointer;
5802 while (! is_end_of_line[(unsigned char) *s]
5803 && (! flag_mri || *s != '*'))
5806 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5809 if (s - input_line_pointer > 1
5813 if (s - input_line_pointer < 3
5814 || strncasecmp (s - 3, "THEN", 4) != 0)
5818 as_bad ("missing then");
5819 ignore_rest_of_line ();
5823 /* It's a conditional. */
5828 /* Since this might be a conditional if, this pseudo-op will be
5829 called even if we are supported to be ignoring input. Double
5830 check now. Clobber *input_line_pointer so that ignore_input
5831 thinks that this is not a special pseudo-op. */
5832 c = *input_line_pointer;
5833 *input_line_pointer = 0;
5834 if (ignore_input ())
5836 *input_line_pointer = c;
5837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5838 ++input_line_pointer;
5839 demand_empty_rest_of_line ();
5842 *input_line_pointer = c;
5844 n = push_mri_control (mri_if);
5846 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5847 n->next, s[1] == '.' ? s[2] : '\0');
5850 input_line_pointer = s + 3;
5852 input_line_pointer = s + 1;
5856 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5857 ++input_line_pointer;
5860 demand_empty_rest_of_line ();
5863 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5864 structured IF, associate the ELSE with the IF. Otherwise, assume
5865 it is a conditional else. */
5876 && (mri_control_stack == NULL
5877 || mri_control_stack->type != mri_if
5878 || mri_control_stack->else_seen))
5884 c = *input_line_pointer;
5885 *input_line_pointer = 0;
5886 if (ignore_input ())
5888 *input_line_pointer = c;
5889 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5890 ++input_line_pointer;
5891 demand_empty_rest_of_line ();
5894 *input_line_pointer = c;
5896 if (mri_control_stack == NULL
5897 || mri_control_stack->type != mri_if
5898 || mri_control_stack->else_seen)
5900 as_bad ("else without matching if");
5901 ignore_rest_of_line ();
5905 mri_control_stack->else_seen = 1;
5907 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5910 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5914 colon (mri_control_stack->next);
5918 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5919 ++input_line_pointer;
5922 demand_empty_rest_of_line ();
5925 /* Handle the MRI ENDI pseudo-op. */
5931 if (mri_control_stack == NULL
5932 || mri_control_stack->type != mri_if)
5934 as_bad ("endi without matching if");
5935 ignore_rest_of_line ();
5939 /* ignore_input will not return true for ENDI, so we don't need to
5940 worry about checking it again here. */
5942 if (! mri_control_stack->else_seen)
5943 colon (mri_control_stack->next);
5944 colon (mri_control_stack->bottom);
5950 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5951 ++input_line_pointer;
5954 demand_empty_rest_of_line ();
5957 /* Handle the MRI BREAK pseudo-op. */
5960 s_mri_break (extent)
5963 struct mri_control_info *n;
5967 n = mri_control_stack;
5969 && n->type != mri_for
5970 && n->type != mri_repeat
5971 && n->type != mri_while)
5975 as_bad ("break outside of structured loop");
5976 ignore_rest_of_line ();
5980 buf = (char *) xmalloc (20 + strlen (n->bottom));
5983 sprintf (buf, "bra%s %s", ex, n->bottom);
5989 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5990 ++input_line_pointer;
5993 demand_empty_rest_of_line ();
5996 /* Handle the MRI NEXT pseudo-op. */
6002 struct mri_control_info *n;
6006 n = mri_control_stack;
6008 && n->type != mri_for
6009 && n->type != mri_repeat
6010 && n->type != mri_while)
6014 as_bad ("next outside of structured loop");
6015 ignore_rest_of_line ();
6019 buf = (char *) xmalloc (20 + strlen (n->next));
6022 sprintf (buf, "bra%s %s", ex, n->next);
6028 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6029 ++input_line_pointer;
6032 demand_empty_rest_of_line ();
6035 /* Handle the MRI FOR pseudo-op. */
6041 const char *varstart, *varstop;
6042 const char *initstart, *initstop;
6043 const char *endstart, *endstop;
6044 const char *bystart, *bystop;
6048 struct mri_control_info *n;
6054 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6058 varstart = input_line_pointer;
6060 /* Look for the '='. */
6061 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6062 && *input_line_pointer != '=')
6063 ++input_line_pointer;
6064 if (*input_line_pointer != '=')
6066 as_bad ("missing =");
6067 ignore_rest_of_line ();
6071 varstop = input_line_pointer;
6072 if (varstop > varstart
6073 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6076 ++input_line_pointer;
6078 initstart = input_line_pointer;
6080 /* Look for TO or DOWNTO. */
6083 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6085 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6086 && ! is_part_of_name (input_line_pointer[2]))
6088 initstop = input_line_pointer;
6089 input_line_pointer += 2;
6092 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6093 && ! is_part_of_name (input_line_pointer[6]))
6095 initstop = input_line_pointer;
6097 input_line_pointer += 6;
6100 ++input_line_pointer;
6102 if (initstop == NULL)
6104 as_bad ("missing to or downto");
6105 ignore_rest_of_line ();
6108 if (initstop > initstart
6109 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6113 endstart = input_line_pointer;
6115 /* Look for BY or DO. */
6118 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6120 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6121 && ! is_part_of_name (input_line_pointer[2]))
6123 endstop = input_line_pointer;
6125 input_line_pointer += 2;
6128 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6129 && (input_line_pointer[2] == '.'
6130 || ! is_part_of_name (input_line_pointer[2])))
6132 endstop = input_line_pointer;
6133 input_line_pointer += 2;
6136 ++input_line_pointer;
6138 if (endstop == NULL)
6140 as_bad ("missing do");
6141 ignore_rest_of_line ();
6144 if (endstop > endstart
6145 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6151 bystop = bystart + 2;
6156 bystart = input_line_pointer;
6160 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6162 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6163 && (input_line_pointer[2] == '.'
6164 || ! is_part_of_name (input_line_pointer[2])))
6166 bystop = input_line_pointer;
6167 input_line_pointer += 2;
6170 ++input_line_pointer;
6174 as_bad ("missing do");
6175 ignore_rest_of_line ();
6178 if (bystop > bystart
6179 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6183 if (*input_line_pointer != '.')
6187 extent = input_line_pointer[1];
6188 input_line_pointer += 2;
6191 /* We have fully parsed the FOR operands. Now build the loop. */
6193 n = push_mri_control (mri_for);
6195 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6206 memcpy (s, initstart, initstop - initstart);
6207 s += initstop - initstart;
6209 memcpy (s, varstart, varstop - varstart);
6210 s += varstop - varstart;
6224 memcpy (s, endstart, endstop - endstart);
6225 s += endstop - endstart;
6227 memcpy (s, varstart, varstop - varstart);
6228 s += varstop - varstart;
6236 sprintf (buf, "blt%s %s", ex, n->bottom);
6238 sprintf (buf, "bgt%s %s", ex, n->bottom);
6241 /* Put together the add or sub instruction used by ENDF. */
6251 memcpy (s, bystart, bystop - bystart);
6252 s += bystop - bystart;
6254 memcpy (s, varstart, varstop - varstart);
6255 s += varstop - varstart;
6261 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6262 ++input_line_pointer;
6265 demand_empty_rest_of_line ();
6268 /* Handle the MRI ENDF pseudo-op. */
6274 if (mri_control_stack == NULL
6275 || mri_control_stack->type != mri_for)
6277 as_bad ("endf without for");
6278 ignore_rest_of_line ();
6282 colon (mri_control_stack->next);
6284 md_assemble (mri_control_stack->incr);
6286 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6287 md_assemble (mri_control_stack->incr);
6289 free (mri_control_stack->incr);
6291 colon (mri_control_stack->bottom);
6297 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6298 ++input_line_pointer;
6301 demand_empty_rest_of_line ();
6304 /* Handle the MRI REPEAT pseudo-op. */
6307 s_mri_repeat (ignore)
6310 struct mri_control_info *n;
6312 n = push_mri_control (mri_repeat);
6316 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6317 ++input_line_pointer;
6319 demand_empty_rest_of_line ();
6322 /* Handle the MRI UNTIL pseudo-op. */
6330 if (mri_control_stack == NULL
6331 || mri_control_stack->type != mri_repeat)
6333 as_bad ("until without repeat");
6334 ignore_rest_of_line ();
6338 colon (mri_control_stack->next);
6340 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6343 parse_mri_control_expression (s, qual, (const char *) NULL,
6344 mri_control_stack->top, '\0');
6346 colon (mri_control_stack->bottom);
6348 input_line_pointer = s;
6354 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6355 ++input_line_pointer;
6358 demand_empty_rest_of_line ();
6361 /* Handle the MRI WHILE pseudo-op. */
6369 struct mri_control_info *n;
6371 s = input_line_pointer;
6372 while (! is_end_of_line[(unsigned char) *s]
6373 && (! flag_mri || *s != '*'))
6376 while (*s == ' ' || *s == '\t')
6378 if (s - input_line_pointer > 1
6381 if (s - input_line_pointer < 2
6382 || strncasecmp (s - 1, "DO", 2) != 0)
6384 as_bad ("missing do");
6385 ignore_rest_of_line ();
6389 n = push_mri_control (mri_while);
6393 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6394 s[1] == '.' ? s[2] : '\0');
6396 input_line_pointer = s + 1;
6397 if (*input_line_pointer == '.')
6398 input_line_pointer += 2;
6402 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6403 ++input_line_pointer;
6406 demand_empty_rest_of_line ();
6409 /* Handle the MRI ENDW pseudo-op. */
6417 if (mri_control_stack == NULL
6418 || mri_control_stack->type != mri_while)
6420 as_bad ("endw without while");
6421 ignore_rest_of_line ();
6425 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6426 sprintf (buf, "bra %s", mri_control_stack->next);
6430 colon (mri_control_stack->bottom);
6436 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6437 ++input_line_pointer;
6440 demand_empty_rest_of_line ();
6445 * Invocation line includes a switch not recognized by the base assembler.
6446 * See if it's a processor-specific option. These are:
6448 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6449 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6450 * Select the architecture. Instructions or features not
6451 * supported by the selected architecture cause fatal
6452 * errors. More than one may be specified. The default is
6453 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6454 * for -m68000, and -m68882 is a synonym for -m68881.
6455 * -[A]m[c]no-68851, -[A]m[c]no-68881
6456 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6457 * so don't use or document it, but that's the way the parsing
6460 * -pic Indicates PIC.
6461 * -k Indicates PIC. (Sun 3 only.)
6464 * Permit `|' to be used in expressions.
6469 CONST char *md_shortopts = "lSA:m:kQ:V";
6471 CONST char *md_shortopts = "lSA:m:k";
6474 struct option md_longopts[] = {
6475 #define OPTION_PIC (OPTION_MD_BASE)
6476 {"pic", no_argument, NULL, OPTION_PIC},
6477 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6478 {"register-prefix-optional", no_argument, NULL,
6479 OPTION_REGISTER_PREFIX_OPTIONAL},
6480 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6481 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6482 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6483 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6484 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6485 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6486 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6487 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6488 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6489 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6490 {NULL, no_argument, NULL, 0}
6492 size_t md_longopts_size = sizeof(md_longopts);
6495 md_parse_option (c, arg)
6501 case 'l': /* -l means keep external to 2 bit offset
6502 rather than 16 bit one */
6503 flag_short_refs = 1;
6506 case 'S': /* -S means that jbsr's always turn into
6508 flag_long_jumps = 1;
6514 /* intentional fall-through */
6517 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6521 const char *oarg = arg;
6527 if (arg[0] == 'c' && arg[1] == '6')
6530 for (i = 0; i < n_archs; i++)
6531 if (!strcmp (arg, archs[i].name))
6536 as_bad ("unrecognized option `%s'", oarg);
6539 arch = archs[i].arch;
6542 else if (arch == m68851)
6551 if (arg[0] == 'c' && arg[1] == '6')
6554 for (i = 0; i < n_archs; i++)
6555 if (!strcmp (arg, archs[i].name))
6557 unsigned long arch = archs[i].arch;
6558 if (cpu_of_arch (arch))
6559 /* It's a cpu spec. */
6561 current_architecture &= ~m68000up;
6562 current_architecture |= arch;
6564 else if (arch == m68881)
6566 current_architecture |= m68881;
6569 else if (arch == m68851)
6571 current_architecture |= m68851;
6581 as_bad ("unrecognized architecture specification `%s'", arg);
6590 break; /* -pic, Position Independent Code */
6592 case OPTION_REGISTER_PREFIX_OPTIONAL:
6593 flag_reg_prefix_optional = 1;
6594 reg_prefix_optional_seen = 1;
6597 /* -V: SVR4 argument to print version ID. */
6599 print_version_id ();
6602 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6603 should be emitted or not. FIXME: Not implemented. */
6607 case OPTION_BITWISE_OR:
6612 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6614 for (s = m68k_comment_chars; *s != '\0'; s++)
6618 m68k_comment_chars = n;
6622 case OPTION_BASE_SIZE_DEFAULT_16:
6623 m68k_index_width_default = SIZE_WORD;
6626 case OPTION_BASE_SIZE_DEFAULT_32:
6627 m68k_index_width_default = SIZE_LONG;
6630 case OPTION_DISP_SIZE_DEFAULT_16:
6632 m68k_rel32_from_cmdline = 1;
6635 case OPTION_DISP_SIZE_DEFAULT_32:
6637 m68k_rel32_from_cmdline = 1;
6648 md_show_usage (stream)
6653 -l use 1 word for refs to undefined symbols [default 2]\n\
6654 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6655 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6656 | -mcpu32 | -m5200\n\
6657 specify variant of 680X0 architecture [default 68020]\n\
6658 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6659 target has/lacks floating-point coprocessor\n\
6660 [default yes for 68020, 68030, and cpu32]\n");
6662 -m68851 | -mno-68851\n\
6663 target has/lacks memory-management unit coprocessor\n\
6664 [default yes for 68020 and up]\n\
6665 -pic, -k generate position independent code\n\
6666 -S turn jbsr into jsr\n\
6667 --register-prefix-optional\n\
6668 recognize register names without prefix character\n\
6669 --bitwise-or do not treat `|' as a comment character\n");
6671 --base-size-default-16 base reg without size is 16 bits\n\
6672 --base-size-default-32 base reg without size is 32 bits (default)\n\
6673 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6674 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6679 /* TEST2: Test md_assemble() */
6680 /* Warning, this routine probably doesn't work anymore */
6684 struct m68k_it the_ins;
6692 if (!gets (buf) || !*buf)
6694 if (buf[0] == '|' || buf[1] == '.')
6696 for (cp = buf; *cp; cp++)
6701 memset (&the_ins, '\0', sizeof (the_ins));
6702 m68k_ip (&the_ins, buf);
6705 printf ("Error %s in %s\n", the_ins.error, buf);
6709 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6710 for (n = 0; n < the_ins.numo; n++)
6711 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6713 print_the_insn (&the_ins.opcode[0], stdout);
6714 (void) putchar ('\n');
6716 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6718 if (the_ins.operands[n].error)
6720 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6723 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6724 if (the_ins.operands[n].b_const)
6725 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6726 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6727 if (the_ins.operands[n].b_iadd)
6728 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6729 (void) putchar ('\n');
6741 while (*str && *str != ' ')
6743 if (str[-1] == ':' || str[1] == '=')
6750 /* Possible states for relaxation:
6752 0 0 branch offset byte (bra, etc)
6756 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6760 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6767 /* We have no need to default values of symbols. */
6771 md_undefined_symbol (name)
6777 /* Round up a section size to the appropriate boundary. */
6779 md_section_align (segment, size)
6783 return size; /* Byte alignment is fine */
6786 /* Exactly what point is a PC-relative offset relative TO?
6787 On the 68k, it is relative to the address of the first extension
6788 word. The difference between the addresses of the offset and the
6789 first extension word is stored in fx_pcrel_adjust. */
6791 md_pcrel_from (fixP)
6796 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6798 adjust = fixP->fx_pcrel_adjust;
6801 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6804 #ifndef BFD_ASSEMBLER
6807 tc_coff_symbol_emit_hook (ignore)
6813 tc_coff_sizemachdep (frag)
6816 switch (frag->fr_subtype & 0x3)
6831 /* end of tc-m68k.c */