1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
86 int flag_reg_prefix_optional;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32 = 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line *next;
127 /* The list of labels. */
129 static struct label_line *labels;
131 /* The current label. */
133 static struct label_line *current_label;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn;
144 const char *m_operands;
145 unsigned long m_opcode;
149 struct m68k_incant *m_next;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
199 static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
203 static const enum m68k_register mcf52235_ctrl[] = {
204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
207 static const enum m68k_register mcf5225_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
211 static const enum m68k_register mcf5235_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
215 static const enum m68k_register mcf5249_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
219 static const enum m68k_register mcf5250_ctrl[] = {
223 static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
227 static const enum m68k_register mcf5271_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
231 static const enum m68k_register mcf5272_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
235 static const enum m68k_register mcf5275_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
239 static const enum m68k_register mcf5282_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
243 static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
271 static const enum m68k_register mcf5475_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
280 static const enum m68k_register mcf5485_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
289 static const enum m68k_register fido_ctrl[] = {
290 SFC, DFC, USP, VBR, CAC, MBB,
293 #define cpu32_ctrl m68010_ctrl
295 static const enum m68k_register *control_regs;
297 /* Internal form of a 68020 instruction. */
301 const char *args; /* List of opcode info. */
304 int numo; /* Number of shorts in opcode. */
307 struct m68k_op operands[6];
309 int nexp; /* Number of exprs in use. */
310 struct m68k_exp exprs[4];
312 int nfrag; /* Number of frags we have to produce. */
315 int fragoff; /* Where in the current opcode the frag ends. */
322 int nrel; /* Num of reloc strucs in use. */
329 /* In a pc relative address the difference between the address
330 of the offset and the address that the offset is relative
331 to. This depends on the addressing mode. Basically this
332 is the value to put in the offset field to address the
333 first byte of the offset, without regarding the special
334 significance of some values (in the branch instruction, for
338 /* Whether this expression needs special pic relocation, and if
340 enum pic_relocation pic_reloc;
343 reloc[5]; /* Five is enough??? */
346 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
347 #define float_of_arch(x) ((x) & mfloat)
348 #define mmu_of_arch(x) ((x) & mmmu)
349 #define arch_coldfire_p(x) ((x) & mcfisa_a)
350 #define arch_coldfire_fpu(x) ((x) & cfloat)
352 /* Macros for determining if cpu supports a specific addressing mode. */
353 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
355 static struct m68k_it the_ins; /* The instruction being assembled. */
357 #define op(ex) ((ex)->exp.X_op)
358 #define adds(ex) ((ex)->exp.X_add_symbol)
359 #define subs(ex) ((ex)->exp.X_op_symbol)
360 #define offs(ex) ((ex)->exp.X_add_number)
362 /* Macros for adding things to the m68k_it struct. */
363 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
365 /* Like addword, but goes BEFORE general operands. */
368 insop (int w, const struct m68k_incant *opcode)
371 for (z = the_ins.numo; z > opcode->m_codenum; --z)
372 the_ins.opcode[z] = the_ins.opcode[z - 1];
373 for (z = 0; z < the_ins.nrel; z++)
374 the_ins.reloc[z].n += 2;
375 for (z = 0; z < the_ins.nfrag; z++)
376 the_ins.fragb[z].fragoff++;
377 the_ins.opcode[opcode->m_codenum] = w;
381 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
384 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
386 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
387 ? the_ins.numo * 2 - 1
389 ? the_ins.numo * 2 + 1
390 : the_ins.numo * 2));
391 the_ins.reloc[the_ins.nrel].exp = exp->exp;
392 the_ins.reloc[the_ins.nrel].wid = width;
393 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
395 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
397 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
400 /* Cause an extra frag to be generated here, inserting up to 10 bytes
401 (that value is chosen in the frag_var call in md_assemble). TYPE
402 is the subtype of the frag to be generated; its primary type is
403 rs_machine_dependent.
405 The TYPE parameter is also used by md_convert_frag_1 and
406 md_estimate_size_before_relax. The appropriate type of fixup will
407 be emitted by md_convert_frag_1.
409 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
411 add_frag (symbolS *add, offsetT off, int type)
413 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
414 the_ins.fragb[the_ins.nfrag].fadd = add;
415 the_ins.fragb[the_ins.nfrag].foff = off;
416 the_ins.fragb[the_ins.nfrag++].fragty = type;
420 (op (ex) != O_constant && op (ex) != O_big)
422 static char *crack_operand (char *str, struct m68k_op *opP);
423 static int get_num (struct m68k_exp *exp, int ok);
424 static int reverse_16_bits (int in);
425 static int reverse_8_bits (int in);
426 static void install_gen_operand (int mode, int val);
427 static void install_operand (int mode, int val);
428 static void s_bss (int);
429 static void s_data1 (int);
430 static void s_data2 (int);
431 static void s_even (int);
432 static void s_proc (int);
433 static void s_chip (int);
434 static void s_fopt (int);
435 static void s_opt (int);
436 static void s_reg (int);
437 static void s_restore (int);
438 static void s_save (int);
439 static void s_mri_if (int);
440 static void s_mri_else (int);
441 static void s_mri_endi (int);
442 static void s_mri_break (int);
443 static void s_mri_next (int);
444 static void s_mri_for (int);
445 static void s_mri_endf (int);
446 static void s_mri_repeat (int);
447 static void s_mri_until (int);
448 static void s_mri_while (int);
449 static void s_mri_endw (int);
450 static void s_m68k_cpu (int);
451 static void s_m68k_arch (int);
455 unsigned long arch; /* Architecture features. */
456 const enum m68k_register *control_regs; /* Control regs on chip */
457 const char *name; /* Name */
458 int alias; /* Alias for a cannonical name. If 1, then
459 succeeds canonical name, if -1 then
460 succeeds canonical name, if <-1 ||>1 this is a
461 deprecated name, and the next/previous name
465 /* We hold flags for features explicitly enabled and explicitly
467 static int current_architecture;
468 static int not_current_architecture;
469 static const struct m68k_cpu *selected_arch;
470 static const struct m68k_cpu *selected_cpu;
471 static int initialized;
473 /* Architecture models. */
474 static const struct m68k_cpu m68k_archs[] =
476 {m68000, m68000_ctrl, "68000", 0},
477 {m68010, m68010_ctrl, "68010", 0},
478 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
479 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
480 {m68040, m68040_ctrl, "68040", 0},
481 {m68060, m68060_ctrl, "68060", 0},
482 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
483 {fido_a, fido_ctrl, "fidoa", 0},
484 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
485 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
486 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
487 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
488 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
492 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
494 static const struct m68k_cpu m68k_extensions[] =
496 {m68851, NULL, "68851", -1},
497 {m68881, NULL, "68881", -1},
498 {m68881, NULL, "68882", -1},
500 {cfloat|m68881, NULL, "float", 0},
502 {mcfhwdiv, NULL, "div", 1},
503 {mcfusp, NULL, "usp", 1},
504 {mcfmac, NULL, "mac", 1},
505 {mcfemac, NULL, "emac", 1},
511 static const struct m68k_cpu m68k_cpus[] =
513 {m68000, m68000_ctrl, "68000", 0},
514 {m68000, m68000_ctrl, "68ec000", 1},
515 {m68000, m68000_ctrl, "68hc000", 1},
516 {m68000, m68000_ctrl, "68hc001", 1},
517 {m68000, m68000_ctrl, "68008", 1},
518 {m68000, m68000_ctrl, "68302", 1},
519 {m68000, m68000_ctrl, "68306", 1},
520 {m68000, m68000_ctrl, "68307", 1},
521 {m68000, m68000_ctrl, "68322", 1},
522 {m68000, m68000_ctrl, "68356", 1},
523 {m68010, m68010_ctrl, "68010", 0},
524 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
525 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
526 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
527 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
528 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
529 {m68040, m68040_ctrl, "68040", 0},
530 {m68040, m68040_ctrl, "68ec040", 1},
531 {m68060, m68060_ctrl, "68060", 0},
532 {m68060, m68060_ctrl, "68ec060", 1},
534 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
535 {cpu32|m68881, cpu32_ctrl, "68330", 1},
536 {cpu32|m68881, cpu32_ctrl, "68331", 1},
537 {cpu32|m68881, cpu32_ctrl, "68332", 1},
538 {cpu32|m68881, cpu32_ctrl, "68333", 1},
539 {cpu32|m68881, cpu32_ctrl, "68334", 1},
540 {cpu32|m68881, cpu32_ctrl, "68336", 1},
541 {cpu32|m68881, cpu32_ctrl, "68340", 1},
542 {cpu32|m68881, cpu32_ctrl, "68341", 1},
543 {cpu32|m68881, cpu32_ctrl, "68349", 1},
544 {cpu32|m68881, cpu32_ctrl, "68360", 1},
546 {mcfisa_a, mcf_ctrl, "5200", 0},
547 {mcfisa_a, mcf_ctrl, "5202", 1},
548 {mcfisa_a, mcf_ctrl, "5204", 1},
549 {mcfisa_a, mcf5206_ctrl, "5206", 1},
551 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
563 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
564 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
565 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
567 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
572 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
575 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
584 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
585 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
586 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
591 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
601 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
612 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
614 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
615 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
616 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
617 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
618 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
619 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
620 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
622 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
623 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
624 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
625 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
626 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
627 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
628 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
630 {fido_a, fido_ctrl, "fidoa", 0},
631 {fido_a, fido_ctrl, "fido", 1},
636 static const struct m68k_cpu *m68k_lookup_cpu
637 (const char *, const struct m68k_cpu *, int, int *);
638 static int m68k_set_arch (const char *, int, int);
639 static int m68k_set_cpu (const char *, int, int);
640 static int m68k_set_extension (const char *, int, int);
641 static void m68k_init_arch (void);
643 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
644 architecture and we have a lot of relaxation modes. */
646 /* Macros used in the relaxation code. */
647 #define TAB(x,y) (((x) << 2) + (y))
648 #define TABTYPE(x) ((x) >> 2)
650 /* Relaxation states. */
656 /* Here are all the relaxation modes we support. First we can relax ordinary
657 branches. On 68020 and higher and on CPU32 all branch instructions take
658 three forms, so on these CPUs all branches always remain as such. When we
659 have to expand to the LONG form on a 68000, though, we substitute an
660 absolute jump instead. This is a direct replacement for unconditional
661 branches and a branch over a jump for conditional branches. However, if the
662 user requires PIC and disables this with --pcrel, we can only relax between
663 BYTE and SHORT forms, punting if that isn't enough. This gives us four
664 different relaxation modes for branches: */
666 #define BRANCHBWL 0 /* Branch byte, word, or long. */
667 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
668 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
669 #define BRANCHBW 3 /* Branch byte or word. */
671 /* We also relax coprocessor branches and DBcc's. All CPUs that support
672 coprocessor branches support them in word and long forms, so we have only
673 one relaxation mode for them. DBcc's are word only on all CPUs. We can
674 relax them to the LONG form with a branch-around sequence. This sequence
675 can use a long branch (if available) or an absolute jump (if acceptable).
676 This gives us two relaxation modes. If long branches are not available and
677 absolute jumps are not acceptable, we don't relax DBcc's. */
679 #define FBRANCH 4 /* Coprocessor branch. */
680 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
681 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
683 /* That's all for instruction relaxation. However, we also relax PC-relative
684 operands. Specifically, we have three operand relaxation modes. On the
685 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
686 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
687 two. Also PC+displacement+index operands in their simple form (with a non-
688 suppressed index without memory indirection) are supported on all CPUs, but
689 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
690 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
691 form of the PC+displacement+index operand. Finally, some absolute operands
692 can be relaxed down to 16-bit PC-relative. */
694 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
695 #define PCINDEX 8 /* PC + displacement + index. */
696 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
698 /* Note that calls to frag_var need to specify the maximum expansion
699 needed; this is currently 10 bytes for DBCC. */
702 How far Forward this mode will reach:
703 How far Backward this mode will reach:
704 How many bytes this mode will add to the size of the frag
705 Which mode to go to if the offset won't fit in this one
707 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
708 relax_typeS md_relax_table[] =
710 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
711 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
715 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
716 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
720 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
721 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
725 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
730 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
731 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
735 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
736 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
740 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
741 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
745 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
746 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
750 { 125, -130, 0, TAB (PCINDEX, SHORT) },
751 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
755 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
756 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
761 /* These are the machine dependent pseudo-ops. These are included so
762 the assembler can work on the output from the SUN C compiler, which
765 /* This table describes all the machine specific pseudo-ops the assembler
766 has to support. The fields are:
767 pseudo-op name without dot
768 function to call to execute this pseudo-op
769 Integer arg to pass to the function. */
770 const pseudo_typeS md_pseudo_table[] =
772 {"data1", s_data1, 0},
773 {"data2", s_data2, 0},
776 {"skip", s_space, 0},
778 #if defined (TE_SUN3) || defined (OBJ_ELF)
779 {"align", s_align_bytes, 0},
782 {"swbeg", s_ignore, 0},
784 {"extend", float_cons, 'x'},
785 {"ldouble", float_cons, 'x'},
787 {"arch", s_m68k_arch, 0},
788 {"cpu", s_m68k_cpu, 0},
790 /* The following pseudo-ops are supported for MRI compatibility. */
792 {"comline", s_space, 1},
794 {"mask2", s_ignore, 0},
797 {"restore", s_restore, 0},
801 {"if.b", s_mri_if, 'b'},
802 {"if.w", s_mri_if, 'w'},
803 {"if.l", s_mri_if, 'l'},
804 {"else", s_mri_else, 0},
805 {"else.s", s_mri_else, 's'},
806 {"else.l", s_mri_else, 'l'},
807 {"endi", s_mri_endi, 0},
808 {"break", s_mri_break, 0},
809 {"break.s", s_mri_break, 's'},
810 {"break.l", s_mri_break, 'l'},
811 {"next", s_mri_next, 0},
812 {"next.s", s_mri_next, 's'},
813 {"next.l", s_mri_next, 'l'},
814 {"for", s_mri_for, 0},
815 {"for.b", s_mri_for, 'b'},
816 {"for.w", s_mri_for, 'w'},
817 {"for.l", s_mri_for, 'l'},
818 {"endf", s_mri_endf, 0},
819 {"repeat", s_mri_repeat, 0},
820 {"until", s_mri_until, 0},
821 {"until.b", s_mri_until, 'b'},
822 {"until.w", s_mri_until, 'w'},
823 {"until.l", s_mri_until, 'l'},
824 {"while", s_mri_while, 0},
825 {"while.b", s_mri_while, 'b'},
826 {"while.w", s_mri_while, 'w'},
827 {"while.l", s_mri_while, 'l'},
828 {"endw", s_mri_endw, 0},
833 /* The mote pseudo ops are put into the opcode table, since they
834 don't start with a . they look like opcodes to gas. */
836 const pseudo_typeS mote_pseudo_table[] =
849 {"xdef", s_globl, 0},
851 {"align", s_align_bytes, 0},
853 {"align", s_align_ptwo, 0},
856 {"sect", obj_coff_section, 0},
857 {"section", obj_coff_section, 0},
862 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
863 gives identical results to a 32-bit host. */
864 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
865 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
867 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
868 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
869 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
870 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
872 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
873 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
874 #define islong(x) (1)
876 static char notend_table[256];
877 static char alt_notend_table[256];
879 (! (notend_table[(unsigned char) *s] \
881 && alt_notend_table[(unsigned char) s[1]])))
885 /* Return zero if the reference to SYMBOL from within the same segment may
888 /* On an ELF system, we can't relax an externally visible symbol,
889 because it may be overridden by a shared library. However, if
890 TARGET_OS is "elf", then we presume that we are assembling for an
891 embedded system, in which case we don't have to worry about shared
892 libraries, and we can relax any external sym. */
894 #define relaxable_symbol(symbol) \
895 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
896 || S_IS_WEAK (symbol)))
898 /* Compute the relocation code for a fixup of SIZE bytes, using pc
899 relative relocation if PCREL is non-zero. PIC says whether a special
900 pic relocation was requested. */
902 static bfd_reloc_code_real_type
903 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
911 return BFD_RELOC_8_GOT_PCREL;
913 return BFD_RELOC_16_GOT_PCREL;
915 return BFD_RELOC_32_GOT_PCREL;
923 return BFD_RELOC_8_GOTOFF;
925 return BFD_RELOC_16_GOTOFF;
927 return BFD_RELOC_32_GOTOFF;
935 return BFD_RELOC_8_PLT_PCREL;
937 return BFD_RELOC_16_PLT_PCREL;
939 return BFD_RELOC_32_PLT_PCREL;
947 return BFD_RELOC_8_PLTOFF;
949 return BFD_RELOC_16_PLTOFF;
951 return BFD_RELOC_32_PLTOFF;
961 return BFD_RELOC_8_PCREL;
963 return BFD_RELOC_16_PCREL;
965 return BFD_RELOC_32_PCREL;
985 as_bad (_("Can not do %d byte pc-relative relocation"), size);
987 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
992 as_bad (_("Can not do %d byte relocation"), size);
994 as_bad (_("Can not do %d byte pic relocation"), size);
997 return BFD_RELOC_NONE;
1000 /* Here we decide which fixups can be adjusted to make them relative
1001 to the beginning of the section instead of the symbol. Basically
1002 we need to make sure that the dynamic relocations are done
1003 correctly, so in some cases we force the original symbol to be
1006 tc_m68k_fix_adjustable (fixS *fixP)
1008 /* Adjust_reloc_syms doesn't know about the GOT. */
1009 switch (fixP->fx_r_type)
1011 case BFD_RELOC_8_GOT_PCREL:
1012 case BFD_RELOC_16_GOT_PCREL:
1013 case BFD_RELOC_32_GOT_PCREL:
1014 case BFD_RELOC_8_GOTOFF:
1015 case BFD_RELOC_16_GOTOFF:
1016 case BFD_RELOC_32_GOTOFF:
1017 case BFD_RELOC_8_PLT_PCREL:
1018 case BFD_RELOC_16_PLT_PCREL:
1019 case BFD_RELOC_32_PLT_PCREL:
1020 case BFD_RELOC_8_PLTOFF:
1021 case BFD_RELOC_16_PLTOFF:
1022 case BFD_RELOC_32_PLTOFF:
1025 case BFD_RELOC_VTABLE_INHERIT:
1026 case BFD_RELOC_VTABLE_ENTRY:
1034 #else /* !OBJ_ELF */
1036 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1038 #define relaxable_symbol(symbol) 1
1040 #endif /* OBJ_ELF */
1043 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1046 bfd_reloc_code_real_type code;
1048 /* If the tcbit is set, then this was a fixup of a negative value
1049 that was never resolved. We do not have a reloc to handle this,
1050 so just return. We assume that other code will have detected this
1051 situation and produced a helpful error message, so we just tell the
1052 user that the reloc cannot be produced. */
1056 as_bad_where (fixp->fx_file, fixp->fx_line,
1057 _("Unable to produce reloc against symbol '%s'"),
1058 S_GET_NAME (fixp->fx_addsy));
1062 if (fixp->fx_r_type != BFD_RELOC_NONE)
1064 code = fixp->fx_r_type;
1066 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1067 that fixup_segment converted a non-PC relative reloc into a
1068 PC relative reloc. In such a case, we need to convert the
1075 code = BFD_RELOC_8_PCREL;
1078 code = BFD_RELOC_16_PCREL;
1081 code = BFD_RELOC_32_PCREL;
1083 case BFD_RELOC_8_PCREL:
1084 case BFD_RELOC_16_PCREL:
1085 case BFD_RELOC_32_PCREL:
1086 case BFD_RELOC_8_GOT_PCREL:
1087 case BFD_RELOC_16_GOT_PCREL:
1088 case BFD_RELOC_32_GOT_PCREL:
1089 case BFD_RELOC_8_GOTOFF:
1090 case BFD_RELOC_16_GOTOFF:
1091 case BFD_RELOC_32_GOTOFF:
1092 case BFD_RELOC_8_PLT_PCREL:
1093 case BFD_RELOC_16_PLT_PCREL:
1094 case BFD_RELOC_32_PLT_PCREL:
1095 case BFD_RELOC_8_PLTOFF:
1096 case BFD_RELOC_16_PLTOFF:
1097 case BFD_RELOC_32_PLTOFF:
1100 as_bad_where (fixp->fx_file, fixp->fx_line,
1101 _("Cannot make %s relocation PC relative"),
1102 bfd_get_reloc_code_name (code));
1108 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1109 switch (F (fixp->fx_size, fixp->fx_pcrel))
1111 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1112 MAP (1, 0, BFD_RELOC_8);
1113 MAP (2, 0, BFD_RELOC_16);
1114 MAP (4, 0, BFD_RELOC_32);
1115 MAP (1, 1, BFD_RELOC_8_PCREL);
1116 MAP (2, 1, BFD_RELOC_16_PCREL);
1117 MAP (4, 1, BFD_RELOC_32_PCREL);
1125 reloc = (arelent *) xmalloc (sizeof (arelent));
1126 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1127 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1128 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1131 reloc->addend = fixp->fx_addnumber;
1135 if (!fixp->fx_pcrel)
1136 reloc->addend = fixp->fx_addnumber;
1138 reloc->addend = (section->vma
1139 /* Explicit sign extension in case char is
1141 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1142 + fixp->fx_addnumber
1143 + md_pcrel_from (fixp));
1146 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1147 assert (reloc->howto != 0);
1152 /* Handle of the OPCODE hash table. NULL means any use before
1153 m68k_ip_begin() will crash. */
1154 static struct hash_control *op_hash;
1156 /* Assemble an m68k instruction. */
1159 m68k_ip (char *instring)
1162 register struct m68k_op *opP;
1163 register const struct m68k_incant *opcode;
1164 register const char *s;
1165 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1166 char *pdot, *pdotmove;
1167 enum m68k_size siz1, siz2;
1171 struct m68k_op operands_backup[6];
1172 LITTLENUM_TYPE words[6];
1173 LITTLENUM_TYPE *wordp;
1174 unsigned long ok_arch = 0;
1176 if (*instring == ' ')
1177 instring++; /* Skip leading whitespace. */
1179 /* Scan up to end of operation-code, which MUST end in end-of-string
1180 or exactly 1 space. */
1182 for (p = instring; *p != '\0'; p++)
1192 the_ins.error = _("No operator");
1196 /* p now points to the end of the opcode name, probably whitespace.
1197 Make sure the name is null terminated by clobbering the
1198 whitespace, look it up in the hash table, then fix it back.
1199 Remove a dot, first, since the opcode tables have none. */
1202 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1203 *pdotmove = pdotmove[1];
1209 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1214 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1215 *pdotmove = pdotmove[-1];
1222 the_ins.error = _("Unknown operator");
1226 /* Found a legitimate opcode, start matching operands. */
1230 if (opcode->m_operands == 0)
1232 char *old = input_line_pointer;
1234 input_line_pointer = p;
1235 /* Ahh - it's a motorola style psuedo op. */
1236 mote_pseudo_table[opcode->m_opnum].poc_handler
1237 (mote_pseudo_table[opcode->m_opnum].poc_val);
1238 input_line_pointer = old;
1244 if (flag_mri && opcode->m_opnum == 0)
1246 /* In MRI mode, random garbage is allowed after an instruction
1247 which accepts no operands. */
1248 the_ins.args = opcode->m_operands;
1249 the_ins.numargs = opcode->m_opnum;
1250 the_ins.numo = opcode->m_codenum;
1251 the_ins.opcode[0] = getone (opcode);
1252 the_ins.opcode[1] = gettwo (opcode);
1256 for (opP = &the_ins.operands[0]; *p; opP++)
1258 p = crack_operand (p, opP);
1262 the_ins.error = opP->error;
1267 opsfound = opP - &the_ins.operands[0];
1269 /* This ugly hack is to support the floating pt opcodes in their
1270 standard form. Essentially, we fake a first enty of type COP#1 */
1271 if (opcode->m_operands[0] == 'I')
1275 for (n = opsfound; n > 0; --n)
1276 the_ins.operands[n] = the_ins.operands[n - 1];
1278 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1279 the_ins.operands[0].mode = CONTROL;
1280 the_ins.operands[0].reg = m68k_float_copnum;
1284 /* We've got the operands. Find an opcode that'll accept them. */
1287 /* If we didn't get the right number of ops, or we have no
1288 common model with this pattern then reject this pattern. */
1290 ok_arch |= opcode->m_arch;
1291 if (opsfound != opcode->m_opnum
1292 || ((opcode->m_arch & current_architecture) == 0))
1298 /* Make a copy of the operands of this insn so that
1299 we can modify them safely, should we want to. */
1300 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1301 for (i = 0; i < opsfound; i++)
1302 operands_backup[i] = the_ins.operands[i];
1304 for (s = opcode->m_operands, opP = &operands_backup[0];
1308 /* Warning: this switch is huge! */
1309 /* I've tried to organize the cases into this order:
1310 non-alpha first, then alpha by letter. Lower-case
1311 goes directly before uppercase counterpart. */
1312 /* Code with multiple case ...: gets sorted by the lowest
1313 case ... it belongs to. I hope this makes sense. */
1419 if (opP->reg == PC || opP->reg == ZPC)
1436 if (opP->reg == PC || opP->reg == ZPC)
1455 if (opP->reg == PC || opP->reg == ZPC)
1465 if (opP->mode != IMMED)
1467 else if (s[1] == 'b'
1468 && ! isvar (&opP->disp)
1469 && (opP->disp.exp.X_op != O_constant
1470 || ! isbyte (opP->disp.exp.X_add_number)))
1472 else if (s[1] == 'B'
1473 && ! isvar (&opP->disp)
1474 && (opP->disp.exp.X_op != O_constant
1475 || ! issbyte (opP->disp.exp.X_add_number)))
1477 else if (s[1] == 'w'
1478 && ! isvar (&opP->disp)
1479 && (opP->disp.exp.X_op != O_constant
1480 || ! isword (opP->disp.exp.X_add_number)))
1482 else if (s[1] == 'W'
1483 && ! isvar (&opP->disp)
1484 && (opP->disp.exp.X_op != O_constant
1485 || ! issword (opP->disp.exp.X_add_number)))
1491 if (opP->mode != IMMED)
1496 if (opP->mode == AREG
1497 || opP->mode == CONTROL
1498 || opP->mode == FPREG
1499 || opP->mode == IMMED
1500 || opP->mode == REGLST
1501 || (opP->mode != ABSL
1503 || opP->reg == ZPC)))
1508 if (opP->mode == CONTROL
1509 || opP->mode == FPREG
1510 || opP->mode == REGLST
1511 || opP->mode == IMMED
1512 || (opP->mode != ABSL
1514 || opP->reg == ZPC)))
1542 if (opP->mode == CONTROL
1543 || opP->mode == FPREG
1544 || opP->mode == REGLST)
1549 if (opP->mode != AINC)
1554 if (opP->mode != ADEC)
1604 if (opP->reg == PC || opP->reg == ZPC)
1625 case '~': /* For now! (JF FOO is this right?) */
1647 if (opP->mode != CONTROL
1648 || (opP->reg != TT0 && opP->reg != TT1))
1653 if (opP->mode != AREG)
1658 if (opP->mode != AINDR)
1663 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1664 && (opP->mode != DISP
1666 || opP->reg > ADDR7))
1671 if (opP->mode != ABSL
1673 && strncmp (instring, "jbsr", 4) == 0))
1696 if (opP->mode != CONTROL || opP->reg != CCR)
1701 if (opP->mode != DISP
1703 || opP->reg > ADDR7)
1708 if (opP->mode != DREG)
1713 if (opP->reg != ACC)
1718 if (opP->reg != ACC && opP->reg != ACC1
1719 && opP->reg != ACC2 && opP->reg != ACC3)
1724 if (opP->mode != FPREG)
1729 if (opP->reg != MACSR)
1734 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1739 if (opP->reg != MASK)
1744 if (opP->mode != CONTROL
1751 if (opP->mode != LSH && opP->mode != RSH)
1756 if (opP->mode != CONTROL
1758 || opP->reg > last_movec_reg
1763 const enum m68k_register *rp;
1765 for (rp = control_regs; *rp; rp++)
1767 if (*rp == opP->reg)
1769 /* In most CPUs RAMBAR refers to control reg
1770 c05 (RAMBAR1), but a few CPUs have it
1771 refer to c04 (RAMBAR0). */
1772 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1774 opP->reg = RAMBAR_ALT;
1784 if (opP->mode != IMMED)
1790 if (opP->mode == DREG
1791 || opP->mode == AREG
1792 || opP->mode == FPREG)
1801 opP->mask = 1 << (opP->reg - DATA0);
1804 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1807 opP->mask = 1 << (opP->reg - FP0 + 16);
1815 else if (opP->mode == CONTROL)
1824 opP->mask = 1 << 24;
1827 opP->mask = 1 << 25;
1830 opP->mask = 1 << 26;
1839 else if (opP->mode != REGLST)
1841 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1843 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1848 if (opP->mode != IMMED)
1850 else if (opP->disp.exp.X_op != O_constant
1851 || ! issbyte (opP->disp.exp.X_add_number))
1853 else if (! m68k_quick
1854 && instring[3] != 'q'
1855 && instring[4] != 'q')
1860 if (opP->mode != DREG
1861 && opP->mode != IMMED
1862 && opP->mode != ABSL)
1867 if (opP->mode != IMMED)
1869 else if (opP->disp.exp.X_op != O_constant
1870 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1872 else if (! m68k_quick
1873 && (strncmp (instring, "add", 3) == 0
1874 || strncmp (instring, "sub", 3) == 0)
1875 && instring[3] != 'q')
1880 if (opP->mode != DREG && opP->mode != AREG)
1885 if (opP->mode != AINDR
1886 && (opP->mode != BASE
1888 && opP->reg != ZADDR0)
1889 || opP->disp.exp.X_op != O_absent
1890 || ((opP->index.reg < DATA0
1891 || opP->index.reg > DATA7)
1892 && (opP->index.reg < ADDR0
1893 || opP->index.reg > ADDR7))
1894 || opP->index.size != SIZE_UNSPEC
1895 || opP->index.scale != 1))
1900 if (opP->mode != CONTROL
1901 || ! (opP->reg == FPI
1903 || opP->reg == FPC))
1908 if (opP->mode != CONTROL || opP->reg != SR)
1913 if (opP->mode != IMMED)
1915 else if (opP->disp.exp.X_op != O_constant
1916 || TRUNC (opP->disp.exp.X_add_number) > 7)
1921 if (opP->mode != CONTROL || opP->reg != USP)
1926 if (opP->mode != IMMED)
1928 else if (opP->disp.exp.X_op != O_constant
1929 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1930 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1934 /* JF these are out of order. We could put them
1935 in order if we were willing to put up with
1936 bunches of #ifdef m68851s in the code.
1938 Don't forget that you need these operands
1939 to use 68030 MMU instructions. */
1941 /* Memory addressing mode used by pflushr. */
1943 if (opP->mode == CONTROL
1944 || opP->mode == FPREG
1945 || opP->mode == DREG
1946 || opP->mode == AREG
1947 || opP->mode == REGLST)
1949 /* We should accept immediate operands, but they
1950 supposedly have to be quad word, and we don't
1951 handle that. I would like to see what a Motorola
1952 assembler does before doing something here. */
1953 if (opP->mode == IMMED)
1958 if (opP->mode != CONTROL
1959 || (opP->reg != SFC && opP->reg != DFC))
1964 if (opP->mode != CONTROL || opP->reg != TC)
1969 if (opP->mode != CONTROL || opP->reg != AC)
1974 if (opP->mode != CONTROL
1977 && opP->reg != SCC))
1982 if (opP->mode != CONTROL
1988 if (opP->mode != CONTROL
1991 && opP->reg != CRP))
2015 if (opP->mode != CONTROL
2016 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2017 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2022 if (opP->mode != CONTROL || opP->reg != PSR)
2027 if (opP->mode != CONTROL || opP->reg != PCSR)
2032 if (opP->mode != CONTROL
2041 if (opP->mode != ABSL)
2046 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2048 /* FIXME: kludge instead of fixing parser:
2049 upper/lower registers are *not* CONTROL
2050 registers, but ordinary ones. */
2051 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2052 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2059 if (!(opP->mode == AINDR
2060 || (opP->mode == DISP
2061 && !(opP->reg == PC || opP->reg == ZPC))))
2066 if (!(opP->mode == AINDR || opP->mode == DISP))
2078 /* Since we have found the correct instruction, copy
2079 in the modifications that we may have made. */
2081 for (i = 0; i < opsfound; i++)
2082 the_ins.operands[i] = operands_backup[i];
2088 opcode = opcode->m_next;
2093 && !(ok_arch & current_architecture))
2095 const struct m68k_cpu *cpu;
2098 char *buf = xmalloc (space + 1);
2102 the_ins.error = buf;
2103 /* Make sure there's a NUL at the end of the buffer -- strncpy
2104 won't write one when it runs out of buffer */
2106 #define APPEND(STRING) \
2107 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2109 APPEND (_("invalid instruction for this architecture; needs "));
2113 APPEND (_("ColdFire ISA_A"));
2116 APPEND (_("ColdFire hardware divide"));
2119 APPEND (_("ColdFire ISA_A+"));
2122 APPEND (_("ColdFire ISA_B"));
2125 APPEND (_("ColdFire fpu"));
2128 APPEND (_("M68K fpu"));
2131 APPEND (_("M68K mmu"));
2134 APPEND (_("68020 or higher"));
2137 APPEND (_("68000 or higher"));
2140 APPEND (_("68010 or higher"));
2148 for (cpu = m68k_cpus; cpu->name; cpu++)
2149 if (!cpu->alias && (cpu->arch & ok_arch))
2151 const struct m68k_cpu *alias;
2152 int seen_master = 0;
2158 for (alias = cpu; alias != m68k_cpus; alias--)
2159 if (alias[-1].alias >= 0)
2161 for (; !seen_master || alias->alias > 0; alias++)
2171 APPEND (alias->name);
2184 /* we ran out of space, so replace the end of the list
2189 strcpy (buf, " ...");
2193 the_ins.error = _("operands mismatch");
2200 /* Now assemble it. */
2201 the_ins.args = opcode->m_operands;
2202 the_ins.numargs = opcode->m_opnum;
2203 the_ins.numo = opcode->m_codenum;
2204 the_ins.opcode[0] = getone (opcode);
2205 the_ins.opcode[1] = gettwo (opcode);
2207 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2209 /* This switch is a doozy.
2210 Watch the first step; its a big one! */
2243 tmpreg = 0x3c; /* 7.4 */
2244 if (strchr ("bwl", s[1]))
2245 nextword = get_num (&opP->disp, 90);
2247 nextword = get_num (&opP->disp, 0);
2248 if (isvar (&opP->disp))
2249 add_fix (s[1], &opP->disp, 0, 0);
2253 if (!isbyte (nextword))
2254 opP->error = _("operand out of range");
2259 if (!isword (nextword))
2260 opP->error = _("operand out of range");
2265 if (!issword (nextword))
2266 opP->error = _("operand out of range");
2271 addword (nextword >> 16);
2298 /* We gotta put out some float. */
2299 if (op (&opP->disp) != O_big)
2304 /* Can other cases happen here? */
2305 if (op (&opP->disp) != O_constant)
2308 val = (valueT) offs (&opP->disp);
2312 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2313 val >>= LITTLENUM_NUMBER_OF_BITS;
2317 offs (&opP->disp) = gencnt;
2319 if (offs (&opP->disp) > 0)
2321 if (offs (&opP->disp) > baseo)
2323 as_warn (_("Bignum too big for %c format; truncated"),
2325 offs (&opP->disp) = baseo;
2327 baseo -= offs (&opP->disp);
2330 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2331 offs (&opP->disp)--;
2336 gen_to_words (words, baseo, (long) outro);
2337 for (wordp = words; baseo--; wordp++)
2341 tmpreg = opP->reg - DATA; /* 0.dreg */
2344 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2347 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2350 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2353 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2357 nextword = get_num (&opP->disp, 90);
2359 /* Convert mode 5 addressing with a zero offset into
2360 mode 2 addressing to reduce the instruction size by a
2362 if (! isvar (&opP->disp)
2364 && (opP->disp.size == SIZE_UNSPEC)
2365 && (opP->reg >= ADDR0)
2366 && (opP->reg <= ADDR7))
2368 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2373 && ! isvar (&opP->disp)
2376 opP->disp.exp.X_op = O_symbol;
2377 opP->disp.exp.X_add_symbol =
2378 section_symbol (absolute_section);
2381 /* Force into index mode. Hope this works. */
2383 /* We do the first bit for 32-bit displacements, and the
2384 second bit for 16 bit ones. It is possible that we
2385 should make the default be WORD instead of LONG, but
2386 I think that'd break GCC, so we put up with a little
2387 inefficiency for the sake of working output. */
2389 if (!issword (nextword)
2390 || (isvar (&opP->disp)
2391 && ((opP->disp.size == SIZE_UNSPEC
2392 && flag_short_refs == 0
2393 && cpu_of_arch (current_architecture) >= m68020
2394 && ! arch_coldfire_p (current_architecture))
2395 || opP->disp.size == SIZE_LONG)))
2397 if (cpu_of_arch (current_architecture) < m68020
2398 || arch_coldfire_p (current_architecture))
2400 _("displacement too large for this architecture; needs 68020 or higher");
2402 tmpreg = 0x3B; /* 7.3 */
2404 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2405 if (isvar (&opP->disp))
2409 if (opP->disp.size == SIZE_LONG
2411 /* If the displacement needs pic
2412 relocation it cannot be relaxed. */
2413 || opP->disp.pic_reloc != pic_none
2418 add_fix ('l', &opP->disp, 1, 2);
2422 add_frag (adds (&opP->disp),
2423 SEXT (offs (&opP->disp)),
2424 TAB (PCREL1632, SZ_UNDEF));
2431 add_fix ('l', &opP->disp, 0, 0);
2436 addword (nextword >> 16);
2441 tmpreg = 0x3A; /* 7.2 */
2443 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2445 if (isvar (&opP->disp))
2449 add_fix ('w', &opP->disp, 1, 0);
2452 add_fix ('w', &opP->disp, 0, 0);
2462 baseo = get_num (&opP->disp, 90);
2463 if (opP->mode == POST || opP->mode == PRE)
2464 outro = get_num (&opP->odisp, 90);
2465 /* Figure out the `addressing mode'.
2466 Also turn on the BASE_DISABLE bit, if needed. */
2467 if (opP->reg == PC || opP->reg == ZPC)
2469 tmpreg = 0x3b; /* 7.3 */
2470 if (opP->reg == ZPC)
2473 else if (opP->reg == 0)
2476 tmpreg = 0x30; /* 6.garbage */
2478 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2481 tmpreg = 0x30 + opP->reg - ZADDR0;
2484 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2486 siz1 = opP->disp.size;
2487 if (opP->mode == POST || opP->mode == PRE)
2488 siz2 = opP->odisp.size;
2492 /* Index register stuff. */
2493 if (opP->index.reg != 0
2494 && opP->index.reg >= DATA
2495 && opP->index.reg <= ADDR7)
2497 nextword |= (opP->index.reg - DATA) << 12;
2499 if (opP->index.size == SIZE_LONG
2500 || (opP->index.size == SIZE_UNSPEC
2501 && m68k_index_width_default == SIZE_LONG))
2504 if ((opP->index.scale != 1
2505 && cpu_of_arch (current_architecture) < m68020)
2506 || (opP->index.scale == 8
2507 && (arch_coldfire_p (current_architecture)
2508 && !arch_coldfire_fpu (current_architecture))))
2511 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2514 if (arch_coldfire_p (current_architecture)
2515 && opP->index.size == SIZE_WORD)
2516 opP->error = _("invalid index size for coldfire");
2518 switch (opP->index.scale)
2535 GET US OUT OF HERE! */
2537 /* Must be INDEX, with an index register. Address
2538 register cannot be ZERO-PC, and either :b was
2539 forced, or we know it will fit. For a 68000 or
2540 68010, force this mode anyways, because the
2541 larger modes aren't supported. */
2542 if (opP->mode == BASE
2543 && ((opP->reg >= ADDR0
2544 && opP->reg <= ADDR7)
2547 if (siz1 == SIZE_BYTE
2548 || cpu_of_arch (current_architecture) < m68020
2549 || arch_coldfire_p (current_architecture)
2550 || (siz1 == SIZE_UNSPEC
2551 && ! isvar (&opP->disp)
2552 && issbyte (baseo)))
2554 nextword += baseo & 0xff;
2556 if (isvar (&opP->disp))
2558 /* Do a byte relocation. If it doesn't
2559 fit (possible on m68000) let the
2560 fixup processing complain later. */
2562 add_fix ('B', &opP->disp, 1, 1);
2564 add_fix ('B', &opP->disp, 0, 0);
2566 else if (siz1 != SIZE_BYTE)
2568 if (siz1 != SIZE_UNSPEC)
2569 as_warn (_("Forcing byte displacement"));
2570 if (! issbyte (baseo))
2571 opP->error = _("byte displacement out of range");
2576 else if (siz1 == SIZE_UNSPEC
2578 && isvar (&opP->disp)
2579 && subs (&opP->disp) == NULL
2581 /* If the displacement needs pic
2582 relocation it cannot be relaxed. */
2583 && opP->disp.pic_reloc == pic_none
2587 /* The code in md_convert_frag_1 needs to be
2588 able to adjust nextword. Call frag_grow
2589 to ensure that we have enough space in
2590 the frag obstack to make all the bytes
2593 nextword += baseo & 0xff;
2595 add_frag (adds (&opP->disp),
2596 SEXT (offs (&opP->disp)),
2597 TAB (PCINDEX, SZ_UNDEF));
2605 nextword |= 0x40; /* No index reg. */
2606 if (opP->index.reg >= ZDATA0
2607 && opP->index.reg <= ZDATA7)
2608 nextword |= (opP->index.reg - ZDATA0) << 12;
2609 else if (opP->index.reg >= ZADDR0
2610 || opP->index.reg <= ZADDR7)
2611 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2614 /* It isn't simple. */
2616 if (cpu_of_arch (current_architecture) < m68020
2617 || arch_coldfire_p (current_architecture))
2619 _("invalid operand mode for this architecture; needs 68020 or higher");
2622 /* If the guy specified a width, we assume that it is
2623 wide enough. Maybe it isn't. If so, we lose. */
2627 if (isvar (&opP->disp)
2629 : ! issword (baseo))
2634 else if (! isvar (&opP->disp) && baseo == 0)
2643 as_warn (_(":b not permitted; defaulting to :w"));
2653 /* Figure out inner displacement stuff. */
2654 if (opP->mode == POST || opP->mode == PRE)
2656 if (cpu_of_arch (current_architecture) & cpu32)
2657 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2661 if (isvar (&opP->odisp)
2663 : ! issword (outro))
2668 else if (! isvar (&opP->odisp) && outro == 0)
2677 as_warn (_(":b not permitted; defaulting to :w"));
2686 if (opP->mode == POST
2687 && (nextword & 0x40) == 0)
2692 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2694 if (opP->reg == PC || opP->reg == ZPC)
2695 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2697 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2699 if (siz1 == SIZE_LONG)
2700 addword (baseo >> 16);
2701 if (siz1 != SIZE_UNSPEC)
2704 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2705 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2706 if (siz2 == SIZE_LONG)
2707 addword (outro >> 16);
2708 if (siz2 != SIZE_UNSPEC)
2714 nextword = get_num (&opP->disp, 90);
2715 switch (opP->disp.size)
2720 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2722 tmpreg = 0x38; /* 7.0 */
2726 if (isvar (&opP->disp)
2727 && !subs (&opP->disp)
2728 && adds (&opP->disp)
2730 /* If the displacement needs pic relocation it
2731 cannot be relaxed. */
2732 && opP->disp.pic_reloc == pic_none
2735 && !strchr ("~%&$?", s[0]))
2737 tmpreg = 0x3A; /* 7.2 */
2738 add_frag (adds (&opP->disp),
2739 SEXT (offs (&opP->disp)),
2740 TAB (ABSTOPCREL, SZ_UNDEF));
2743 /* Fall through into long. */
2745 if (isvar (&opP->disp))
2746 add_fix ('l', &opP->disp, 0, 0);
2748 tmpreg = 0x39;/* 7.1 mode */
2749 addword (nextword >> 16);
2754 as_bad (_("unsupported byte value; use a different suffix"));
2758 if (isvar (&opP->disp))
2759 add_fix ('w', &opP->disp, 0, 0);
2761 tmpreg = 0x38;/* 7.0 mode */
2769 as_bad (_("unknown/incorrect operand"));
2773 /* If s[0] is '4', then this is for the mac instructions
2774 that can have a trailing_ampersand set. If so, set 0x100
2775 bit on tmpreg so install_gen_operand can check for it and
2776 set the appropriate bit (word2, bit 5). */
2779 if (opP->trailing_ampersand)
2782 install_gen_operand (s[1], tmpreg);
2788 { /* JF: I hate floating point! */
2803 tmpreg = get_num (&opP->disp, tmpreg);
2804 if (isvar (&opP->disp))
2805 add_fix (s[1], &opP->disp, 0, 0);
2808 case 'b': /* Danger: These do no check for
2809 certain types of overflow.
2811 if (!isbyte (tmpreg))
2812 opP->error = _("out of range");
2813 insop (tmpreg, opcode);
2814 if (isvar (&opP->disp))
2815 the_ins.reloc[the_ins.nrel - 1].n =
2816 (opcode->m_codenum) * 2 + 1;
2819 if (!issbyte (tmpreg))
2820 opP->error = _("out of range");
2821 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2822 if (isvar (&opP->disp))
2823 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2826 if (!isword (tmpreg))
2827 opP->error = _("out of range");
2828 insop (tmpreg, opcode);
2829 if (isvar (&opP->disp))
2830 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2833 if (!issword (tmpreg))
2834 opP->error = _("out of range");
2835 insop (tmpreg, opcode);
2836 if (isvar (&opP->disp))
2837 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2840 /* Because of the way insop works, we put these two out
2842 insop (tmpreg, opcode);
2843 insop (tmpreg >> 16, opcode);
2844 if (isvar (&opP->disp))
2845 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2852 install_operand (s[1], tmpreg);
2863 install_operand (s[1], opP->reg - ADDR);
2867 tmpreg = get_num (&opP->disp, 90);
2871 add_fix ('B', &opP->disp, 1, -1);
2874 add_fix ('w', &opP->disp, 1, 0);
2879 if (! HAVE_LONG_BRANCH (current_architecture))
2880 as_warn (_("Can't use long branches on 68000/68010/5200"));
2881 the_ins.opcode[0] |= 0xff;
2882 add_fix ('l', &opP->disp, 1, 0);
2887 if (subs (&opP->disp)) /* We can't relax it. */
2891 /* If the displacement needs pic relocation it cannot be
2893 if (opP->disp.pic_reloc != pic_none)
2896 /* This could either be a symbol, or an absolute
2897 address. If it's an absolute address, turn it into
2898 an absolute jump right here and keep it out of the
2900 if (adds (&opP->disp) == 0)
2902 if (the_ins.opcode[0] == 0x6000) /* jbra */
2903 the_ins.opcode[0] = 0x4EF9;
2904 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2905 the_ins.opcode[0] = 0x4EB9;
2908 the_ins.opcode[0] ^= 0x0100;
2909 the_ins.opcode[0] |= 0x0006;
2912 add_fix ('l', &opP->disp, 0, 0);
2918 /* Now we know it's going into the relaxer. Now figure
2919 out which mode. We try in this order of preference:
2920 long branch, absolute jump, byte/word branches only. */
2921 if (HAVE_LONG_BRANCH (current_architecture))
2922 add_frag (adds (&opP->disp),
2923 SEXT (offs (&opP->disp)),
2924 TAB (BRANCHBWL, SZ_UNDEF));
2925 else if (! flag_keep_pcrel)
2927 if ((the_ins.opcode[0] == 0x6000)
2928 || (the_ins.opcode[0] == 0x6100))
2929 add_frag (adds (&opP->disp),
2930 SEXT (offs (&opP->disp)),
2931 TAB (BRABSJUNC, SZ_UNDEF));
2933 add_frag (adds (&opP->disp),
2934 SEXT (offs (&opP->disp)),
2935 TAB (BRABSJCOND, SZ_UNDEF));
2938 add_frag (adds (&opP->disp),
2939 SEXT (offs (&opP->disp)),
2940 TAB (BRANCHBW, SZ_UNDEF));
2943 if (isvar (&opP->disp))
2945 /* Check for DBcc instructions. We can relax them,
2946 but only if we have long branches and/or absolute
2948 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2949 && (HAVE_LONG_BRANCH (current_architecture)
2950 || (! flag_keep_pcrel)))
2952 if (HAVE_LONG_BRANCH (current_architecture))
2953 add_frag (adds (&opP->disp),
2954 SEXT (offs (&opP->disp)),
2955 TAB (DBCCLBR, SZ_UNDEF));
2957 add_frag (adds (&opP->disp),
2958 SEXT (offs (&opP->disp)),
2959 TAB (DBCCABSJ, SZ_UNDEF));
2962 add_fix ('w', &opP->disp, 1, 0);
2966 case 'C': /* Fixed size LONG coproc branches. */
2967 add_fix ('l', &opP->disp, 1, 0);
2971 case 'c': /* Var size Coprocesssor branches. */
2972 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2974 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2975 add_fix ('l', &opP->disp, 1, 0);
2980 add_frag (adds (&opP->disp),
2981 SEXT (offs (&opP->disp)),
2982 TAB (FBRANCH, SZ_UNDEF));
2989 case 'C': /* Ignore it. */
2992 case 'd': /* JF this is a kludge. */
2993 install_operand ('s', opP->reg - ADDR);
2994 tmpreg = get_num (&opP->disp, 90);
2995 if (!issword (tmpreg))
2997 as_warn (_("Expression out of range, using 0"));
3004 install_operand (s[1], opP->reg - DATA);
3007 case 'e': /* EMAC ACCx, reg/reg. */
3008 install_operand (s[1], opP->reg - ACC);
3011 case 'E': /* Ignore it. */
3015 install_operand (s[1], opP->reg - FP0);
3018 case 'g': /* EMAC ACCEXTx. */
3019 install_operand (s[1], opP->reg - ACCEXT01);
3022 case 'G': /* Ignore it. */
3027 tmpreg = opP->reg - COP0;
3028 install_operand (s[1], tmpreg);
3031 case 'i': /* MAC/EMAC scale factor. */
3032 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3035 case 'J': /* JF foo. */
3175 install_operand (s[1], tmpreg);
3179 tmpreg = get_num (&opP->disp, 55);
3180 install_operand (s[1], tmpreg & 0x7f);
3187 if (tmpreg & 0x7FF0000)
3188 as_bad (_("Floating point register in register list"));
3189 insop (reverse_16_bits (tmpreg), opcode);
3193 if (tmpreg & 0x700FFFF)
3194 as_bad (_("Wrong register in floating-point reglist"));
3195 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3203 if (tmpreg & 0x7FF0000)
3204 as_bad (_("Floating point register in register list"));
3205 insop (tmpreg, opcode);
3207 else if (s[1] == '8')
3209 if (tmpreg & 0x0FFFFFF)
3210 as_bad (_("incorrect register in reglist"));
3211 install_operand (s[1], tmpreg >> 24);
3215 if (tmpreg & 0x700FFFF)
3216 as_bad (_("wrong register in floating-point reglist"));
3218 install_operand (s[1], tmpreg >> 16);
3223 install_operand (s[1], get_num (&opP->disp, 60));
3227 tmpreg = ((opP->mode == DREG)
3228 ? 0x20 + (int) (opP->reg - DATA)
3229 : (get_num (&opP->disp, 40) & 0x1F));
3230 install_operand (s[1], tmpreg);
3234 tmpreg = get_num (&opP->disp, 10);
3237 install_operand (s[1], tmpreg);
3241 /* This depends on the fact that ADDR registers are eight
3242 more than their corresponding DATA regs, so the result
3243 will have the ADDR_REG bit set. */
3244 install_operand (s[1], opP->reg - DATA);
3248 if (opP->mode == AINDR)
3249 install_operand (s[1], opP->reg - DATA);
3251 install_operand (s[1], opP->index.reg - DATA);
3255 if (opP->reg == FPI)
3257 else if (opP->reg == FPS)
3259 else if (opP->reg == FPC)
3263 install_operand (s[1], tmpreg);
3266 case 'S': /* Ignore it. */
3270 install_operand (s[1], get_num (&opP->disp, 30));
3273 case 'U': /* Ignore it. */
3292 as_fatal (_("failed sanity check"));
3293 } /* switch on cache token. */
3294 install_operand (s[1], tmpreg);
3297 /* JF: These are out of order, I fear. */
3310 install_operand (s[1], tmpreg);
3336 install_operand (s[1], tmpreg);
3340 if (opP->reg == VAL)
3359 install_operand (s[1], tmpreg);
3373 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3384 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3390 install_operand (s[1], tmpreg);
3393 know (opP->reg == PSR);
3396 know (opP->reg == PCSR);
3411 install_operand (s[1], tmpreg);
3414 tmpreg = get_num (&opP->disp, 20);
3415 install_operand (s[1], tmpreg);
3417 case '_': /* used only for move16 absolute 32-bit address. */
3418 if (isvar (&opP->disp))
3419 add_fix ('l', &opP->disp, 0, 0);
3420 tmpreg = get_num (&opP->disp, 90);
3421 addword (tmpreg >> 16);
3422 addword (tmpreg & 0xFFFF);
3425 install_operand (s[1], opP->reg - DATA0L);
3426 opP->reg -= (DATA0L);
3427 opP->reg &= 0x0F; /* remove upper/lower bit. */
3430 tmpreg = get_num (&opP->disp, 80);
3433 install_operand (s[1], tmpreg);
3440 /* By the time whe get here (FINALLY) the_ins contains the complete
3441 instruction, ready to be emitted. . . */
3445 reverse_16_bits (int in)
3450 static int mask[16] =
3452 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3453 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3455 for (n = 0; n < 16; n++)
3458 out |= mask[15 - n];
3461 } /* reverse_16_bits() */
3464 reverse_8_bits (int in)
3469 static int mask[8] =
3471 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3474 for (n = 0; n < 8; n++)
3480 } /* reverse_8_bits() */
3482 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3483 (that value is chosen in the frag_var call in md_assemble). TYPE
3484 is the subtype of the frag to be generated; its primary type is
3485 rs_machine_dependent.
3487 The TYPE parameter is also used by md_convert_frag_1 and
3488 md_estimate_size_before_relax. The appropriate type of fixup will
3489 be emitted by md_convert_frag_1.
3491 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3493 install_operand (int mode, int val)
3498 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3501 the_ins.opcode[0] |= val << 9;
3504 the_ins.opcode[1] |= val << 12;
3507 the_ins.opcode[1] |= val << 6;
3510 the_ins.opcode[1] |= val;
3513 the_ins.opcode[2] |= val << 12;
3516 the_ins.opcode[2] |= val << 6;
3519 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3520 three words long! */
3522 the_ins.opcode[2] |= val;
3525 the_ins.opcode[1] |= val << 7;
3528 the_ins.opcode[1] |= val << 10;
3532 the_ins.opcode[1] |= val << 5;
3537 the_ins.opcode[1] |= (val << 10) | (val << 7);
3540 the_ins.opcode[1] |= (val << 12) | val;
3543 the_ins.opcode[0] |= val = 0xff;
3546 the_ins.opcode[0] |= val << 9;
3549 the_ins.opcode[1] |= val;
3552 the_ins.opcode[1] |= val;
3553 the_ins.numo++; /* What a hack. */
3556 the_ins.opcode[1] |= val << 4;
3564 the_ins.opcode[0] |= (val << 6);
3567 the_ins.opcode[1] = (val >> 16);
3568 the_ins.opcode[2] = val & 0xffff;
3571 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3572 the_ins.opcode[0] |= ((val & 0x7) << 9);
3573 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3575 case 'n': /* MAC/EMAC Rx on !load. */
3576 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3577 the_ins.opcode[0] |= ((val & 0x7) << 9);
3578 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3580 case 'o': /* MAC/EMAC Rx on load. */
3581 the_ins.opcode[1] |= val << 12;
3582 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3584 case 'M': /* MAC/EMAC Ry on !load. */
3585 the_ins.opcode[0] |= (val & 0xF);
3586 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3588 case 'N': /* MAC/EMAC Ry on load. */
3589 the_ins.opcode[1] |= (val & 0xF);
3590 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3593 the_ins.opcode[1] |= ((val != 1) << 10);
3596 the_ins.opcode[0] |= ((val & 0x3) << 9);
3599 the_ins.opcode[0] |= ((val & 0x3) << 0);
3601 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3602 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3603 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3605 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3606 the_ins.opcode[0] |= ((val & 0x1) << 7);
3607 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3610 the_ins.opcode[1] |= ((val & 0x3) << 9);
3613 the_ins.opcode[0] |= (val & 0x1) <<10;
3617 as_fatal (_("failed sanity check."));
3622 install_gen_operand (int mode, int val)
3626 case '/': /* Special for mask loads for mac/msac insns with
3627 possible mask; trailing_ampersend set in bit 8. */
3628 the_ins.opcode[0] |= (val & 0x3f);
3629 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3632 the_ins.opcode[0] |= val;
3635 /* This is a kludge!!! */
3636 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3645 the_ins.opcode[0] |= val;
3647 /* more stuff goes here. */
3649 as_fatal (_("failed sanity check."));
3653 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3654 then deal with the bitfield hack. */
3657 crack_operand (char *str, struct m68k_op *opP)
3659 register int parens;
3661 register char *beg_str;
3669 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3675 else if (*str == ')')
3679 opP->error = _("Extra )");
3685 if (flag_mri && *str == '\'')
3686 inquote = ! inquote;
3688 if (!*str && parens)
3690 opP->error = _("Missing )");
3695 if (m68k_ip_op (beg_str, opP) != 0)
3702 c = *++str; /* JF bitfield hack. */
3707 as_bad (_("Missing operand"));
3710 /* Detect MRI REG symbols and convert them to REGLSTs. */
3711 if (opP->mode == CONTROL && (int)opP->reg < 0)
3714 opP->mask = ~(int)opP->reg;
3721 /* This is the guts of the machine-dependent assembler. STR points to a
3722 machine dependent instruction. This function is supposed to emit
3723 the frags/bytes it assembles to.
3727 insert_reg (const char *regname, int regnum)
3732 #ifdef REGISTER_PREFIX
3733 if (!flag_reg_prefix_optional)
3735 buf[0] = REGISTER_PREFIX;
3736 strcpy (buf + 1, regname);
3741 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3742 &zero_address_frag));
3744 for (i = 0; regname[i]; i++)
3745 buf[i] = TOUPPER (regname[i]);
3748 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3749 &zero_address_frag));
3758 static const struct init_entry init_table[] =
3818 { "accext01", ACCEXT01 },
3819 { "accext23", ACCEXT23 },
3823 /* Control registers. */
3824 { "sfc", SFC }, /* Source Function Code. */
3826 { "dfc", DFC }, /* Destination Function Code. */
3828 { "cacr", CACR }, /* Cache Control Register. */
3829 { "caar", CAAR }, /* Cache Address Register. */
3831 { "usp", USP }, /* User Stack Pointer. */
3832 { "vbr", VBR }, /* Vector Base Register. */
3833 { "msp", MSP }, /* Master Stack Pointer. */
3834 { "isp", ISP }, /* Interrupt Stack Pointer. */
3836 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3837 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3838 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3839 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3841 /* 68ec040 versions of same */
3842 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3843 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3844 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3845 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3847 /* Coldfire versions of same. The ColdFire programmer's reference
3848 manual indicated that the order is 2,3,0,1, but Ken Rose
3849 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3850 { "acr0", ACR0 }, /* Access Control Unit 0. */
3851 { "acr1", ACR1 }, /* Access Control Unit 1. */
3852 { "acr2", ACR2 }, /* Access Control Unit 2. */
3853 { "acr3", ACR3 }, /* Access Control Unit 3. */
3855 { "tc", TC }, /* MMU Translation Control Register. */
3859 { "mmusr", MMUSR }, /* MMU Status Register. */
3860 { "srp", SRP }, /* User Root Pointer. */
3861 { "urp", URP }, /* Supervisor Root Pointer. */
3864 { "mmubar", MMUBAR },
3867 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3868 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3869 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3870 { "mbar", MBAR }, /* Module Base Address Register. */
3872 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3873 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3874 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3875 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3876 { "mpcr", MPCR }, /* mcfv4e registers. */
3877 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3878 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3879 { "asid", TC }, /* mcfv4e registers. */
3880 { "mmubar", BUSCR }, /* mcfv4e registers. */
3881 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3882 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3883 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3884 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3885 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3886 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3887 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3888 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3889 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3890 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3891 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3892 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3894 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3895 { "rambar", RAMBAR }, /* mcf528x registers. */
3897 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3899 { "cac", CAC }, /* fido registers. */
3900 { "mbb", MBB }, /* fido registers. */
3901 /* End of control registers. */
3935 /* 68ec030 versions of same. */
3938 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3941 /* Suppressed data and address registers. */
3959 /* Upper and lower data and address registers, used by macw and msacw. */
4000 init_regtable (void)
4003 for (i = 0; init_table[i].name; i++)
4004 insert_reg (init_table[i].name, init_table[i].number);
4008 md_assemble (char *str)
4015 int shorts_this_frag;
4018 if (!selected_cpu && !selected_arch)
4020 /* We've not selected an architecture yet. Set the default
4021 now. We do this lazily so that an initial .cpu or .arch directive
4023 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4024 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4029 /* In MRI mode, the instruction and operands are separated by a
4030 space. Anything following the operands is a comment. The label
4031 has already been removed. */
4039 for (s = str; *s != '\0'; s++)
4041 if ((*s == ' ' || *s == '\t') && ! inquote)
4059 inquote = ! inquote;
4064 memset (&the_ins, '\0', sizeof (the_ins));
4069 for (n = 0; n < the_ins.numargs; n++)
4070 if (the_ins.operands[n].error)
4072 er = the_ins.operands[n].error;
4078 as_bad (_("%s -- statement `%s' ignored"), er, str);
4082 /* If there is a current label, record that it marks an instruction. */
4083 if (current_label != NULL)
4085 current_label->text = 1;
4086 current_label = NULL;
4090 /* Tie dwarf2 debug info to the address at the start of the insn. */
4091 dwarf2_emit_insn (0);
4094 if (the_ins.nfrag == 0)
4096 /* No frag hacking involved; just put it out. */
4097 toP = frag_more (2 * the_ins.numo);
4098 fromP = &the_ins.opcode[0];
4099 for (m = the_ins.numo; m; --m)
4101 md_number_to_chars (toP, (long) (*fromP), 2);
4105 /* Put out symbol-dependent info. */
4106 for (m = 0; m < the_ins.nrel; m++)
4108 switch (the_ins.reloc[m].wid)
4127 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4128 the_ins.reloc[m].wid);
4131 fixP = fix_new_exp (frag_now,
4132 ((toP - frag_now->fr_literal)
4133 - the_ins.numo * 2 + the_ins.reloc[m].n),
4135 &the_ins.reloc[m].exp,
4136 the_ins.reloc[m].pcrel,
4137 get_reloc_code (n, the_ins.reloc[m].pcrel,
4138 the_ins.reloc[m].pic_reloc));
4139 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4140 if (the_ins.reloc[m].wid == 'B')
4141 fixP->fx_signed = 1;
4146 /* There's some frag hacking. */
4148 /* Calculate the max frag size. */
4151 wid = 2 * the_ins.fragb[0].fragoff;
4152 for (n = 1; n < the_ins.nfrag; n++)
4153 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4154 /* frag_var part. */
4156 /* Make sure the whole insn fits in one chunk, in particular that
4157 the var part is attached, as we access one byte before the
4158 variable frag for byte branches. */
4162 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4167 wid = 2 * the_ins.fragb[n].fragoff;
4169 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4170 toP = frag_more (wid);
4172 shorts_this_frag = 0;
4173 for (m = wid / 2; m; --m)
4175 md_number_to_chars (toP, (long) (*fromP), 2);
4180 for (m = 0; m < the_ins.nrel; m++)
4182 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4184 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4187 wid = the_ins.reloc[m].wid;
4190 the_ins.reloc[m].wid = 0;
4191 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4193 fixP = fix_new_exp (frag_now,
4194 ((toP - frag_now->fr_literal)
4195 - the_ins.numo * 2 + the_ins.reloc[m].n),
4197 &the_ins.reloc[m].exp,
4198 the_ins.reloc[m].pcrel,
4199 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4200 the_ins.reloc[m].pic_reloc));
4201 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4203 (void) frag_var (rs_machine_dependent, 10, 0,
4204 (relax_substateT) (the_ins.fragb[n].fragty),
4205 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4207 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4208 shorts_this_frag = 0;
4211 toP = frag_more (n * 2);
4214 md_number_to_chars (toP, (long) (*fromP), 2);
4220 for (m = 0; m < the_ins.nrel; m++)
4224 wid = the_ins.reloc[m].wid;
4227 the_ins.reloc[m].wid = 0;
4228 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4230 fixP = fix_new_exp (frag_now,
4231 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4232 - shorts_this_frag * 2),
4234 &the_ins.reloc[m].exp,
4235 the_ins.reloc[m].pcrel,
4236 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4237 the_ins.reloc[m].pic_reloc));
4238 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4242 /* Comparison function used by qsort to rank the opcode entries by name. */
4245 m68k_compare_opcode (const void * v1, const void * v2)
4247 struct m68k_opcode * op1, * op2;
4253 op1 = *(struct m68k_opcode **) v1;
4254 op2 = *(struct m68k_opcode **) v2;
4256 /* Compare the two names. If different, return the comparison.
4257 If the same, return the order they are in the opcode table. */
4258 ret = strcmp (op1->name, op2->name);
4269 const struct m68k_opcode *ins;
4270 struct m68k_incant *hack, *slak;
4271 const char *retval = 0; /* Empty string, or error msg text. */
4274 /* Set up hash tables with 68000 instructions.
4275 similar to what the vax assembler does. */
4276 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4277 a copy of it at runtime, adding in the information we want but isn't
4278 there. I think it'd be better to have an awk script hack the table
4279 at compile time. Or even just xstr the table and use it as-is. But
4280 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4285 flag_reg_prefix_optional = 1;
4287 if (! m68k_rel32_from_cmdline)
4291 /* First sort the opcode table into alphabetical order to seperate
4292 the order that the assembler wants to see the opcodes from the
4293 order that the disassembler wants to see them. */
4294 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4295 if (!m68k_sorted_opcodes)
4296 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4297 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4299 for (i = m68k_numopcodes; i--;)
4300 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4302 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4303 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4305 op_hash = hash_new ();
4307 obstack_begin (&robyn, 4000);
4308 for (i = 0; i < m68k_numopcodes; i++)
4310 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4313 ins = m68k_sorted_opcodes[i];
4315 /* We *could* ignore insns that don't match our
4316 arch here by just leaving them out of the hash. */
4317 slak->m_operands = ins->args;
4318 slak->m_opnum = strlen (slak->m_operands) / 2;
4319 slak->m_arch = ins->arch;
4320 slak->m_opcode = ins->opcode;
4321 /* This is kludgey. */
4322 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4323 if (i + 1 != m68k_numopcodes
4324 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4326 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4331 slak = slak->m_next;
4335 retval = hash_insert (op_hash, ins->name, (char *) hack);
4337 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4340 for (i = 0; i < m68k_numaliases; i++)
4342 const char *name = m68k_opcode_aliases[i].primary;
4343 const char *alias = m68k_opcode_aliases[i].alias;
4344 PTR val = hash_find (op_hash, name);
4347 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4348 retval = hash_insert (op_hash, alias, val);
4350 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4353 /* In MRI mode, all unsized branches are variable sized. Normally,
4354 they are word sized. */
4357 static struct m68k_opcode_alias mri_aliases[] =
4378 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4381 const char *name = mri_aliases[i].primary;
4382 const char *alias = mri_aliases[i].alias;
4383 PTR val = hash_find (op_hash, name);
4386 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4387 retval = hash_jam (op_hash, alias, val);
4389 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4393 for (i = 0; i < (int) sizeof (notend_table); i++)
4395 notend_table[i] = 0;
4396 alt_notend_table[i] = 0;
4399 notend_table[','] = 1;
4400 notend_table['{'] = 1;
4401 notend_table['}'] = 1;
4402 alt_notend_table['a'] = 1;
4403 alt_notend_table['A'] = 1;
4404 alt_notend_table['d'] = 1;
4405 alt_notend_table['D'] = 1;
4406 alt_notend_table['#'] = 1;
4407 alt_notend_table['&'] = 1;
4408 alt_notend_table['f'] = 1;
4409 alt_notend_table['F'] = 1;
4410 #ifdef REGISTER_PREFIX
4411 alt_notend_table[REGISTER_PREFIX] = 1;
4414 /* We need to put '(' in alt_notend_table to handle
4415 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4416 alt_notend_table['('] = 1;
4418 /* We need to put '@' in alt_notend_table to handle
4419 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4420 alt_notend_table['@'] = 1;
4422 /* We need to put digits in alt_notend_table to handle
4423 bfextu %d0{24:1},%d0 */
4424 alt_notend_table['0'] = 1;
4425 alt_notend_table['1'] = 1;
4426 alt_notend_table['2'] = 1;
4427 alt_notend_table['3'] = 1;
4428 alt_notend_table['4'] = 1;
4429 alt_notend_table['5'] = 1;
4430 alt_notend_table['6'] = 1;
4431 alt_notend_table['7'] = 1;
4432 alt_notend_table['8'] = 1;
4433 alt_notend_table['9'] = 1;
4435 #ifndef MIT_SYNTAX_ONLY
4436 /* Insert pseudo ops, these have to go into the opcode table since
4437 gas expects pseudo ops to start with a dot. */
4441 while (mote_pseudo_table[n].poc_name)
4443 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4444 hash_insert (op_hash,
4445 mote_pseudo_table[n].poc_name, (char *) hack);
4446 hack->m_operands = 0;
4456 record_alignment (text_section, 2);
4457 record_alignment (data_section, 2);
4458 record_alignment (bss_section, 2);
4463 /* This is called when a label is defined. */
4466 m68k_frob_label (symbolS *sym)
4468 struct label_line *n;
4470 n = (struct label_line *) xmalloc (sizeof *n);
4473 as_where (&n->file, &n->line);
4479 dwarf2_emit_label (sym);
4483 /* This is called when a value that is not an instruction is emitted. */
4486 m68k_flush_pending_output (void)
4488 current_label = NULL;
4491 /* This is called at the end of the assembly, when the final value of
4492 the label is known. We warn if this is a text symbol aligned at an
4496 m68k_frob_symbol (symbolS *sym)
4498 if (S_GET_SEGMENT (sym) == reg_section
4499 && (int) S_GET_VALUE (sym) < 0)
4501 S_SET_SEGMENT (sym, absolute_section);
4502 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4504 else if ((S_GET_VALUE (sym) & 1) != 0)
4506 struct label_line *l;
4508 for (l = labels; l != NULL; l = l->next)
4510 if (l->label == sym)
4513 as_warn_where (l->file, l->line,
4514 _("text label `%s' aligned to odd boundary"),
4522 /* This is called if we go in or out of MRI mode because of the .mri
4526 m68k_mri_mode_change (int on)
4530 if (! flag_reg_prefix_optional)
4532 flag_reg_prefix_optional = 1;
4533 #ifdef REGISTER_PREFIX
4538 if (! m68k_rel32_from_cmdline)
4543 if (! reg_prefix_optional_seen)
4545 #ifdef REGISTER_PREFIX_OPTIONAL
4546 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4548 flag_reg_prefix_optional = 0;
4550 #ifdef REGISTER_PREFIX
4555 if (! m68k_rel32_from_cmdline)
4560 /* Equal to MAX_PRECISION in atof-ieee.c. */
4561 #define MAX_LITTLENUMS 6
4563 /* Turn a string in input_line_pointer into a floating point constant
4564 of type TYPE, and store the appropriate bytes in *LITP. The number
4565 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4566 returned, or NULL on OK. */
4569 md_atof (int type, char *litP, int *sizeP)
4572 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4573 LITTLENUM_TYPE *wordP;
4604 return _("Bad call to MD_ATOF()");
4606 t = atof_ieee (input_line_pointer, type, words);
4608 input_line_pointer = t;
4610 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4611 for (wordP = words; prec--;)
4613 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4614 litP += sizeof (LITTLENUM_TYPE);
4620 md_number_to_chars (char *buf, valueT val, int n)
4622 number_to_chars_bigendian (buf, val, n);
4626 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4628 offsetT val = *valP;
4629 addressT upper_limit;
4630 offsetT lower_limit;
4632 /* This is unnecessary but it convinces the native rs6000 compiler
4633 to generate the code we want. */
4634 char *buf = fixP->fx_frag->fr_literal;
4635 buf += fixP->fx_where;
4636 /* End ibm compiler workaround. */
4640 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4646 memset (buf, 0, fixP->fx_size);
4647 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4649 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4650 && !S_IS_DEFINED (fixP->fx_addsy)
4651 && !S_IS_WEAK (fixP->fx_addsy))
4652 S_SET_WEAK (fixP->fx_addsy);
4657 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4658 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4661 switch (fixP->fx_size)
4663 /* The cast to offsetT below are necessary to make code
4664 correct for machines where ints are smaller than offsetT. */
4668 lower_limit = - (offsetT) 0x80;
4671 *buf++ = (val >> 8);
4673 upper_limit = 0x7fff;
4674 lower_limit = - (offsetT) 0x8000;
4677 *buf++ = (val >> 24);
4678 *buf++ = (val >> 16);
4679 *buf++ = (val >> 8);
4681 upper_limit = 0x7fffffff;
4682 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4685 BAD_CASE (fixP->fx_size);
4688 /* Fix up a negative reloc. */
4689 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4691 fixP->fx_addsy = fixP->fx_subsy;
4692 fixP->fx_subsy = NULL;
4696 /* For non-pc-relative values, it's conceivable we might get something
4697 like "0xff" for a byte field. So extend the upper part of the range
4698 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4699 so that we can do any range checking at all. */
4700 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4701 upper_limit = upper_limit * 2 + 1;
4703 if ((addressT) val > upper_limit
4704 && (val > 0 || val < lower_limit))
4705 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4707 /* A one byte PC-relative reloc means a short branch. We can't use
4708 a short branch with a value of 0 or -1, because those indicate
4709 different opcodes (branches with longer offsets). fixup_segment
4710 in write.c may have clobbered fx_pcrel, so we need to examine the
4713 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4714 && fixP->fx_size == 1
4715 && (fixP->fx_addsy == NULL
4716 || S_IS_DEFINED (fixP->fx_addsy))
4717 && (val == 0 || val == -1))
4718 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4721 /* *fragP has been relaxed to its final size, and now needs to have
4722 the bytes inside it modified to conform to the new size There is UGLY
4726 md_convert_frag_1 (fragS *fragP)
4731 /* Address in object code of the displacement. */
4732 register int object_address = fragP->fr_fix + fragP->fr_address;
4734 /* Address in gas core of the place to store the displacement. */
4735 /* This convinces the native rs6000 compiler to generate the code we
4737 register char *buffer_address = fragP->fr_literal;
4738 buffer_address += fragP->fr_fix;
4739 /* End ibm compiler workaround. */
4741 /* The displacement of the address, from current location. */
4742 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4743 disp = (disp + fragP->fr_offset) - object_address;
4745 switch (fragP->fr_subtype)
4747 case TAB (BRANCHBWL, BYTE):
4748 case TAB (BRABSJUNC, BYTE):
4749 case TAB (BRABSJCOND, BYTE):
4750 case TAB (BRANCHBW, BYTE):
4751 know (issbyte (disp));
4753 as_bad_where (fragP->fr_file, fragP->fr_line,
4754 _("short branch with zero offset: use :w"));
4755 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4756 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4757 fixP->fx_pcrel_adjust = -1;
4759 case TAB (BRANCHBWL, SHORT):
4760 case TAB (BRABSJUNC, SHORT):
4761 case TAB (BRABSJCOND, SHORT):
4762 case TAB (BRANCHBW, SHORT):
4763 fragP->fr_opcode[1] = 0x00;
4764 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4765 1, RELAX_RELOC_PC16);
4768 case TAB (BRANCHBWL, LONG):
4769 fragP->fr_opcode[1] = (char) 0xFF;
4770 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4771 1, RELAX_RELOC_PC32);
4774 case TAB (BRABSJUNC, LONG):
4775 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4777 if (flag_keep_pcrel)
4778 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4779 fragP->fr_opcode[0] = 0x4E;
4780 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4781 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4782 0, RELAX_RELOC_ABS32);
4785 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4787 if (flag_keep_pcrel)
4788 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4789 fragP->fr_opcode[0] = 0x4E;
4790 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4791 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4792 0, RELAX_RELOC_ABS32);
4797 /* This cannot happen, because jbsr and jbra are the only two
4798 unconditional branches. */
4802 case TAB (BRABSJCOND, LONG):
4803 if (flag_keep_pcrel)
4804 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4806 /* Only Bcc 68000 instructions can come here
4807 Change bcc into b!cc/jmp absl long. */
4808 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4809 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4811 /* JF: these used to be fr_opcode[2,3], but they may be in a
4812 different frag, in which case referring to them is a no-no.
4813 Only fr_opcode[0,1] are guaranteed to work. */
4814 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4815 *buffer_address++ = (char) 0xf9;
4816 fragP->fr_fix += 2; /* Account for jmp instruction. */
4817 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4818 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4821 case TAB (FBRANCH, SHORT):
4822 know ((fragP->fr_opcode[1] & 0x40) == 0);
4823 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4824 1, RELAX_RELOC_PC16);
4827 case TAB (FBRANCH, LONG):
4828 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4829 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4830 1, RELAX_RELOC_PC32);
4833 case TAB (DBCCLBR, SHORT):
4834 case TAB (DBCCABSJ, SHORT):
4835 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4836 1, RELAX_RELOC_PC16);
4839 case TAB (DBCCLBR, LONG):
4840 /* Only DBcc instructions can come here.
4841 Change dbcc into dbcc/bral.
4842 JF: these used to be fr_opcode[2-7], but that's wrong. */
4843 if (flag_keep_pcrel)
4844 as_fatal (_("Tried to convert DBcc to absolute jump"));
4846 *buffer_address++ = 0x00; /* Branch offset = 4. */
4847 *buffer_address++ = 0x04;
4848 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4849 *buffer_address++ = 0x06;
4850 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4851 *buffer_address++ = (char) 0xff;
4853 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4854 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4858 case TAB (DBCCABSJ, LONG):
4859 /* Only DBcc instructions can come here.
4860 Change dbcc into dbcc/jmp.
4861 JF: these used to be fr_opcode[2-7], but that's wrong. */
4862 if (flag_keep_pcrel)
4863 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4865 *buffer_address++ = 0x00; /* Branch offset = 4. */
4866 *buffer_address++ = 0x04;
4867 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4868 *buffer_address++ = 0x06;
4869 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4870 *buffer_address++ = (char) 0xf9;
4872 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4873 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4877 case TAB (PCREL1632, SHORT):
4878 fragP->fr_opcode[1] &= ~0x3F;
4879 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4880 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4881 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4884 case TAB (PCREL1632, LONG):
4885 /* Already set to mode 7.3; this indicates: PC indirect with
4886 suppressed index, 32-bit displacement. */
4887 *buffer_address++ = 0x01;
4888 *buffer_address++ = 0x70;
4890 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4891 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4892 fixP->fx_pcrel_adjust = 2;
4895 case TAB (PCINDEX, BYTE):
4896 assert (fragP->fr_fix >= 2);
4897 buffer_address[-2] &= ~1;
4898 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4899 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4900 fixP->fx_pcrel_adjust = 1;
4902 case TAB (PCINDEX, SHORT):
4903 assert (fragP->fr_fix >= 2);
4904 buffer_address[-2] |= 0x1;
4905 buffer_address[-1] = 0x20;
4906 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4907 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4908 fixP->fx_pcrel_adjust = 2;
4911 case TAB (PCINDEX, LONG):
4912 assert (fragP->fr_fix >= 2);
4913 buffer_address[-2] |= 0x1;
4914 buffer_address[-1] = 0x30;
4915 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4916 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4917 fixP->fx_pcrel_adjust = 2;
4920 case TAB (ABSTOPCREL, SHORT):
4921 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4922 1, RELAX_RELOC_PC16);
4925 case TAB (ABSTOPCREL, LONG):
4926 if (flag_keep_pcrel)
4927 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4928 /* The thing to do here is force it to ABSOLUTE LONG, since
4929 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4930 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4932 fragP->fr_opcode[1] &= ~0x3F;
4933 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4934 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4935 0, RELAX_RELOC_ABS32);
4942 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4943 segT sec ATTRIBUTE_UNUSED,
4946 md_convert_frag_1 (fragP);
4949 /* Force truly undefined symbols to their maximum size, and generally set up
4950 the frag list to be relaxed
4953 md_estimate_size_before_relax (fragS *fragP, segT segment)
4955 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4956 switch (fragP->fr_subtype)
4958 case TAB (BRANCHBWL, SZ_UNDEF):
4959 case TAB (BRABSJUNC, SZ_UNDEF):
4960 case TAB (BRABSJCOND, SZ_UNDEF):
4962 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4963 && relaxable_symbol (fragP->fr_symbol))
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4967 else if (flag_short_refs)
4969 /* Symbol is undefined and we want short ref. */
4970 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4974 /* Symbol is still undefined. Make it LONG. */
4975 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4980 case TAB (BRANCHBW, SZ_UNDEF):
4982 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4983 && relaxable_symbol (fragP->fr_symbol))
4985 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4989 /* Symbol is undefined and we don't have long branches. */
4990 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4995 case TAB (FBRANCH, SZ_UNDEF):
4996 case TAB (DBCCLBR, SZ_UNDEF):
4997 case TAB (DBCCABSJ, SZ_UNDEF):
4998 case TAB (PCREL1632, SZ_UNDEF):
5000 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5001 && relaxable_symbol (fragP->fr_symbol))
5004 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5008 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5013 case TAB (PCINDEX, SZ_UNDEF):
5014 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5015 && relaxable_symbol (fragP->fr_symbol)))
5017 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5021 fragP->fr_subtype = TAB (PCINDEX, LONG);
5025 case TAB (ABSTOPCREL, SZ_UNDEF):
5027 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5028 && relaxable_symbol (fragP->fr_symbol)))
5030 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5034 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5043 /* Now that SZ_UNDEF are taken care of, check others. */
5044 switch (fragP->fr_subtype)
5046 case TAB (BRANCHBWL, BYTE):
5047 case TAB (BRABSJUNC, BYTE):
5048 case TAB (BRABSJCOND, BYTE):
5049 case TAB (BRANCHBW, BYTE):
5050 /* We can't do a short jump to the next instruction, so in that
5051 case we force word mode. If the symbol is at the start of a
5052 frag, and it is the next frag with any data in it (usually
5053 this is just the next frag, but assembler listings may
5054 introduce empty frags), we must use word mode. */
5055 if (fragP->fr_symbol)
5059 sym_frag = symbol_get_frag (fragP->fr_symbol);
5060 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5064 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5068 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5075 return md_relax_table[fragP->fr_subtype].rlx_length;
5078 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5079 /* the bit-field entries in the relocation_info struct plays hell
5080 with the byte-order problems of cross-assembly. So as a hack,
5081 I added this mach. dependent ri twiddler. Ugly, but it gets
5083 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5084 are symbolnum, most sig. byte first. Last byte is broken up with
5085 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5086 nibble as nuthin. (on Sun 3 at least) */
5087 /* Translate the internal relocation information into target-specific
5091 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5094 md_number_to_chars (the_bytes, ri->r_address, 4);
5095 /* Now the fun stuff. */
5096 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5097 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5098 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5099 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5100 | ((ri->r_length << 5) & 0x60)
5101 | ((ri->r_extern << 4) & 0x10));
5106 #endif /* OBJ_AOUT or OBJ_BOUT */
5108 #ifndef WORKING_DOT_WORD
5109 int md_short_jump_size = 4;
5110 int md_long_jump_size = 6;
5113 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5114 fragS *frag ATTRIBUTE_UNUSED,
5115 symbolS *to_symbol ATTRIBUTE_UNUSED)
5119 offset = to_addr - (from_addr + 2);
5121 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5122 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5126 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5127 fragS *frag, symbolS *to_symbol)
5131 if (!HAVE_LONG_BRANCH (current_architecture))
5133 if (flag_keep_pcrel)
5134 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5135 offset = to_addr - S_GET_VALUE (to_symbol);
5136 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5137 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5138 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5143 offset = to_addr - (from_addr + 2);
5144 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5145 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5151 /* Different values of OK tell what its OK to return. Things that
5152 aren't OK are an error (what a shock, no?)
5155 10: Absolute 1:8 only
5156 20: Absolute 0:7 only
5157 30: absolute 0:15 only
5158 40: Absolute 0:31 only
5159 50: absolute 0:127 only
5160 55: absolute -64:63 only
5161 60: absolute -128:127 only
5162 70: absolute 0:4095 only
5163 80: absolute -1, 1:7 only
5167 get_num (struct m68k_exp *exp, int ok)
5169 if (exp->exp.X_op == O_absent)
5171 /* Do the same thing the VAX asm does. */
5172 op (exp) = O_constant;
5178 as_warn (_("expression out of range: defaulting to 1"));
5182 else if (exp->exp.X_op == O_constant)
5187 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5189 as_warn (_("expression out of range: defaulting to 1"));
5194 if ((valueT) TRUNC (offs (exp)) > 7)
5198 if ((valueT) TRUNC (offs (exp)) > 15)
5202 if ((valueT) TRUNC (offs (exp)) > 32)
5206 if ((valueT) TRUNC (offs (exp)) > 127)
5210 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5214 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5218 if ((valueT) TRUNC (offs (exp)) > 4095)
5221 as_warn (_("expression out of range: defaulting to 0"));
5226 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5227 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5229 as_warn (_("expression out of range: defaulting to 1"));
5237 else if (exp->exp.X_op == O_big)
5239 if (offs (exp) <= 0 /* flonum. */
5240 && (ok == 90 /* no bignums */
5241 || (ok > 10 /* Small-int ranges including 0 ok. */
5242 /* If we have a flonum zero, a zero integer should
5243 do as well (e.g., in moveq). */
5244 && generic_floating_point_number.exponent == 0
5245 && generic_floating_point_number.low[0] == 0)))
5247 /* HACK! Turn it into a long. */
5248 LITTLENUM_TYPE words[6];
5250 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5251 op (exp) = O_constant;
5254 offs (exp) = words[1] | (words[0] << 16);
5258 op (exp) = O_constant;
5261 offs (exp) = (ok == 10) ? 1 : 0;
5262 as_warn (_("Can't deal with expression; defaulting to %ld"),
5268 if (ok >= 10 && ok <= 80)
5270 op (exp) = O_constant;
5273 offs (exp) = (ok == 10) ? 1 : 0;
5274 as_warn (_("Can't deal with expression; defaulting to %ld"),
5279 if (exp->size != SIZE_UNSPEC)
5287 if (!isbyte (offs (exp)))
5288 as_warn (_("expression doesn't fit in BYTE"));
5291 if (!isword (offs (exp)))
5292 as_warn (_("expression doesn't fit in WORD"));
5300 /* These are the back-ends for the various machine dependent pseudo-ops. */
5303 s_data1 (int ignore ATTRIBUTE_UNUSED)
5305 subseg_set (data_section, 1);
5306 demand_empty_rest_of_line ();
5310 s_data2 (int ignore ATTRIBUTE_UNUSED)
5312 subseg_set (data_section, 2);
5313 demand_empty_rest_of_line ();
5317 s_bss (int ignore ATTRIBUTE_UNUSED)
5319 /* We don't support putting frags in the BSS segment, we fake it
5320 by marking in_bss, then looking at s_skip for clues. */
5322 subseg_set (bss_section, 0);
5323 demand_empty_rest_of_line ();
5327 s_even (int ignore ATTRIBUTE_UNUSED)
5330 register long temp_fill;
5332 temp = 1; /* JF should be 2? */
5333 temp_fill = get_absolute_expression ();
5334 if (!need_pass_2) /* Never make frag if expect extra pass. */
5335 frag_align (temp, (int) temp_fill, 0);
5336 demand_empty_rest_of_line ();
5337 record_alignment (now_seg, temp);
5341 s_proc (int ignore ATTRIBUTE_UNUSED)
5343 demand_empty_rest_of_line ();
5346 /* Pseudo-ops handled for MRI compatibility. */
5348 /* This function returns non-zero if the argument is a conditional
5349 pseudo-op. This is called when checking whether a pending
5350 alignment is needed. */
5353 m68k_conditional_pseudoop (pseudo_typeS *pop)
5355 return (pop->poc_handler == s_mri_if
5356 || pop->poc_handler == s_mri_else);
5359 /* Handle an MRI style chip specification. */
5368 s = input_line_pointer;
5369 /* We can't use get_symbol_end since the processor names are not proper
5371 while (is_part_of_name (c = *input_line_pointer++))
5373 *--input_line_pointer = 0;
5374 for (i = 0; m68k_cpus[i].name; i++)
5375 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5377 if (!m68k_cpus[i].name)
5379 as_bad (_("%s: unrecognized processor name"), s);
5380 *input_line_pointer = c;
5381 ignore_rest_of_line ();
5384 *input_line_pointer = c;
5386 if (*input_line_pointer == '/')
5387 current_architecture = 0;
5389 current_architecture &= m68881 | m68851;
5390 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5391 control_regs = m68k_cpus[i].control_regs;
5393 while (*input_line_pointer == '/')
5395 ++input_line_pointer;
5396 s = input_line_pointer;
5397 /* We can't use get_symbol_end since the processor names are not
5399 while (is_part_of_name (c = *input_line_pointer++))
5401 *--input_line_pointer = 0;
5402 if (strcmp (s, "68881") == 0)
5403 current_architecture |= m68881;
5404 else if (strcmp (s, "68851") == 0)
5405 current_architecture |= m68851;
5406 *input_line_pointer = c;
5410 /* The MRI CHIP pseudo-op. */
5413 s_chip (int ignore ATTRIBUTE_UNUSED)
5419 stop = mri_comment_field (&stopc);
5422 mri_comment_end (stop, stopc);
5423 demand_empty_rest_of_line ();
5426 /* The MRI FOPT pseudo-op. */
5429 s_fopt (int ignore ATTRIBUTE_UNUSED)
5433 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5437 input_line_pointer += 3;
5438 temp = get_absolute_expression ();
5439 if (temp < 0 || temp > 7)
5440 as_bad (_("bad coprocessor id"));
5442 m68k_float_copnum = COP0 + temp;
5446 as_bad (_("unrecognized fopt option"));
5447 ignore_rest_of_line ();
5451 demand_empty_rest_of_line ();
5454 /* The structure used to handle the MRI OPT pseudo-op. */
5458 /* The name of the option. */
5461 /* If this is not NULL, just call this function. The first argument
5462 is the ARG field of this structure, the second argument is
5463 whether the option was negated. */
5464 void (*pfn) (int arg, int on);
5466 /* If this is not NULL, and the PFN field is NULL, set the variable
5467 this points to. Set it to the ARG field if the option was not
5468 negated, and the NOTARG field otherwise. */
5471 /* The value to pass to PFN or to assign to *PVAR. */
5474 /* The value to assign to *PVAR if the option is negated. If PFN is
5475 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5476 the option may not be negated. */
5480 /* The table used to handle the MRI OPT pseudo-op. */
5482 static void skip_to_comma (int, int);
5483 static void opt_nest (int, int);
5484 static void opt_chip (int, int);
5485 static void opt_list (int, int);
5486 static void opt_list_symbols (int, int);
5488 static const struct opt_action opt_table[] =
5490 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5492 /* We do relaxing, so there is little use for these options. */
5493 { "b", 0, 0, 0, 0 },
5494 { "brs", 0, 0, 0, 0 },
5495 { "brb", 0, 0, 0, 0 },
5496 { "brl", 0, 0, 0, 0 },
5497 { "brw", 0, 0, 0, 0 },
5499 { "c", 0, 0, 0, 0 },
5500 { "cex", 0, 0, 0, 0 },
5501 { "case", 0, &symbols_case_sensitive, 1, 0 },
5502 { "cl", 0, 0, 0, 0 },
5503 { "cre", 0, 0, 0, 0 },
5504 { "d", 0, &flag_keep_locals, 1, 0 },
5505 { "e", 0, 0, 0, 0 },
5506 { "f", 0, &flag_short_refs, 1, 0 },
5507 { "frs", 0, &flag_short_refs, 1, 0 },
5508 { "frl", 0, &flag_short_refs, 0, 1 },
5509 { "g", 0, 0, 0, 0 },
5510 { "i", 0, 0, 0, 0 },
5511 { "m", 0, 0, 0, 0 },
5512 { "mex", 0, 0, 0, 0 },
5513 { "mc", 0, 0, 0, 0 },
5514 { "md", 0, 0, 0, 0 },
5515 { "nest", opt_nest, 0, 0, 0 },
5516 { "next", skip_to_comma, 0, 0, 0 },
5517 { "o", 0, 0, 0, 0 },
5518 { "old", 0, 0, 0, 0 },
5519 { "op", skip_to_comma, 0, 0, 0 },
5520 { "pco", 0, 0, 0, 0 },
5521 { "p", opt_chip, 0, 0, 0 },
5522 { "pcr", 0, 0, 0, 0 },
5523 { "pcs", 0, 0, 0, 0 },
5524 { "r", 0, 0, 0, 0 },
5525 { "quick", 0, &m68k_quick, 1, 0 },
5526 { "rel32", 0, &m68k_rel32, 1, 0 },
5527 { "s", opt_list, 0, 0, 0 },
5528 { "t", opt_list_symbols, 0, 0, 0 },
5529 { "w", 0, &flag_no_warnings, 0, 1 },
5533 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5535 /* The MRI OPT pseudo-op. */
5538 s_opt (int ignore ATTRIBUTE_UNUSED)
5546 const struct opt_action *o;
5551 if (*input_line_pointer == '-')
5553 ++input_line_pointer;
5556 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5558 input_line_pointer += 2;
5562 s = input_line_pointer;
5563 c = get_symbol_end ();
5565 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5567 if (strcasecmp (s, o->name) == 0)
5571 /* Restore input_line_pointer now in case the option
5573 *input_line_pointer = c;
5574 (*o->pfn) (o->arg, t);
5576 else if (o->pvar != NULL)
5578 if (! t && o->arg == o->notarg)
5579 as_bad (_("option `%s' may not be negated"), s);
5580 *input_line_pointer = c;
5581 *o->pvar = t ? o->arg : o->notarg;
5584 *input_line_pointer = c;
5590 as_bad (_("option `%s' not recognized"), s);
5591 *input_line_pointer = c;
5594 while (*input_line_pointer++ == ',');
5596 /* Move back to terminating character. */
5597 --input_line_pointer;
5598 demand_empty_rest_of_line ();
5601 /* Skip ahead to a comma. This is used for OPT options which we do
5602 not support and which take arguments. */
5605 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5607 while (*input_line_pointer != ','
5608 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5609 ++input_line_pointer;
5612 /* Handle the OPT NEST=depth option. */
5615 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5617 if (*input_line_pointer != '=')
5619 as_bad (_("bad format of OPT NEST=depth"));
5623 ++input_line_pointer;
5624 max_macro_nest = get_absolute_expression ();
5627 /* Handle the OPT P=chip option. */
5630 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5632 if (*input_line_pointer != '=')
5634 /* This is just OPT P, which we do not support. */
5638 ++input_line_pointer;
5642 /* Handle the OPT S option. */
5645 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5650 /* Handle the OPT T option. */
5653 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5656 listing |= LISTING_SYMBOLS;
5658 listing &= ~LISTING_SYMBOLS;
5661 /* Handle the MRI REG pseudo-op. */
5664 s_reg (int ignore ATTRIBUTE_UNUSED)
5673 if (line_label == NULL)
5675 as_bad (_("missing label"));
5676 ignore_rest_of_line ();
5681 stop = mri_comment_field (&stopc);
5685 s = input_line_pointer;
5686 while (ISALNUM (*input_line_pointer)
5687 #ifdef REGISTER_PREFIX
5688 || *input_line_pointer == REGISTER_PREFIX
5690 || *input_line_pointer == '/'
5691 || *input_line_pointer == '-')
5692 ++input_line_pointer;
5693 c = *input_line_pointer;
5694 *input_line_pointer = '\0';
5696 if (m68k_ip_op (s, &rop) != 0)
5698 if (rop.error == NULL)
5699 as_bad (_("bad register list"));
5701 as_bad (_("bad register list: %s"), rop.error);
5702 *input_line_pointer = c;
5703 ignore_rest_of_line ();
5707 *input_line_pointer = c;
5709 if (rop.mode == REGLST)
5711 else if (rop.mode == DREG)
5712 mask = 1 << (rop.reg - DATA0);
5713 else if (rop.mode == AREG)
5714 mask = 1 << (rop.reg - ADDR0 + 8);
5715 else if (rop.mode == FPREG)
5716 mask = 1 << (rop.reg - FP0 + 16);
5717 else if (rop.mode == CONTROL
5720 else if (rop.mode == CONTROL
5723 else if (rop.mode == CONTROL
5728 as_bad (_("bad register list"));
5729 ignore_rest_of_line ();
5733 S_SET_SEGMENT (line_label, reg_section);
5734 S_SET_VALUE (line_label, ~mask);
5735 symbol_set_frag (line_label, &zero_address_frag);
5738 mri_comment_end (stop, stopc);
5740 demand_empty_rest_of_line ();
5743 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5747 struct save_opts *next;
5749 int symbols_case_sensitive;
5753 const enum m68k_register *control_regs;
5758 /* FIXME: We don't save OPT S. */
5761 /* This variable holds the stack of saved options. */
5763 static struct save_opts *save_stack;
5765 /* The MRI SAVE pseudo-op. */
5768 s_save (int ignore ATTRIBUTE_UNUSED)
5770 struct save_opts *s;
5772 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5773 s->abspcadd = m68k_abspcadd;
5774 s->symbols_case_sensitive = symbols_case_sensitive;
5775 s->keep_locals = flag_keep_locals;
5776 s->short_refs = flag_short_refs;
5777 s->architecture = current_architecture;
5778 s->control_regs = control_regs;
5779 s->quick = m68k_quick;
5780 s->rel32 = m68k_rel32;
5781 s->listing = listing;
5782 s->no_warnings = flag_no_warnings;
5784 s->next = save_stack;
5787 demand_empty_rest_of_line ();
5790 /* The MRI RESTORE pseudo-op. */
5793 s_restore (int ignore ATTRIBUTE_UNUSED)
5795 struct save_opts *s;
5797 if (save_stack == NULL)
5799 as_bad (_("restore without save"));
5800 ignore_rest_of_line ();
5805 save_stack = s->next;
5807 m68k_abspcadd = s->abspcadd;
5808 symbols_case_sensitive = s->symbols_case_sensitive;
5809 flag_keep_locals = s->keep_locals;
5810 flag_short_refs = s->short_refs;
5811 current_architecture = s->architecture;
5812 control_regs = s->control_regs;
5813 m68k_quick = s->quick;
5814 m68k_rel32 = s->rel32;
5815 listing = s->listing;
5816 flag_no_warnings = s->no_warnings;
5820 demand_empty_rest_of_line ();
5823 /* Types of MRI structured control directives. */
5825 enum mri_control_type
5833 /* This structure is used to stack the MRI structured control
5836 struct mri_control_info
5838 /* The directive within which this one is enclosed. */
5839 struct mri_control_info *outer;
5841 /* The type of directive. */
5842 enum mri_control_type type;
5844 /* Whether an ELSE has been in an IF. */
5847 /* The add or sub statement at the end of a FOR. */
5850 /* The label of the top of a FOR or REPEAT loop. */
5853 /* The label to jump to for the next iteration, or the else
5854 expression of a conditional. */
5857 /* The label to jump to to break out of the loop, or the label past
5858 the end of a conditional. */
5862 /* The stack of MRI structured control directives. */
5864 static struct mri_control_info *mri_control_stack;
5866 /* The current MRI structured control directive index number, used to
5867 generate label names. */
5869 static int mri_control_index;
5871 /* Assemble an instruction for an MRI structured control directive. */
5874 mri_assemble (char *str)
5878 /* md_assemble expects the opcode to be in lower case. */
5879 for (s = str; *s != ' ' && *s != '\0'; s++)
5885 /* Generate a new MRI label structured control directive label name. */
5888 mri_control_label (void)
5892 n = (char *) xmalloc (20);
5893 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5894 ++mri_control_index;
5898 /* Create a new MRI structured control directive. */
5900 static struct mri_control_info *
5901 push_mri_control (enum mri_control_type type)
5903 struct mri_control_info *n;
5905 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5909 if (type == mri_if || type == mri_while)
5912 n->top = mri_control_label ();
5913 n->next = mri_control_label ();
5914 n->bottom = mri_control_label ();
5916 n->outer = mri_control_stack;
5917 mri_control_stack = n;
5922 /* Pop off the stack of MRI structured control directives. */
5925 pop_mri_control (void)
5927 struct mri_control_info *n;
5929 n = mri_control_stack;
5930 mri_control_stack = n->outer;
5938 /* Recognize a condition code in an MRI structured control expression. */
5941 parse_mri_condition (int *pcc)
5945 know (*input_line_pointer == '<');
5947 ++input_line_pointer;
5948 c1 = *input_line_pointer++;
5949 c2 = *input_line_pointer++;
5951 if (*input_line_pointer != '>')
5953 as_bad (_("syntax error in structured control directive"));
5957 ++input_line_pointer;
5963 *pcc = (c1 << 8) | c2;
5968 /* Parse a single operand in an MRI structured control expression. */
5971 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5972 char **rightstart, char **rightstop)
5984 if (*input_line_pointer == '<')
5986 /* It's just a condition code. */
5987 return parse_mri_condition (pcc);
5990 /* Look ahead for the condition code. */
5991 for (s = input_line_pointer; *s != '\0'; ++s)
5993 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5998 as_bad (_("missing condition code in structured control directive"));
6002 *leftstart = input_line_pointer;
6004 if (*leftstop > *leftstart
6005 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6008 input_line_pointer = s;
6009 if (! parse_mri_condition (pcc))
6012 /* Look ahead for AND or OR or end of line. */
6013 for (s = input_line_pointer; *s != '\0'; ++s)
6015 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6016 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6018 if ((s == input_line_pointer
6021 && ((strncasecmp (s, "AND", 3) == 0
6022 && (s[3] == '.' || ! is_part_of_name (s[3])))
6023 || (strncasecmp (s, "OR", 2) == 0
6024 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6028 *rightstart = input_line_pointer;
6030 if (*rightstop > *rightstart
6031 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6034 input_line_pointer = s;
6039 #define MCC(b1, b2) (((b1) << 8) | (b2))
6041 /* Swap the sense of a condition. This changes the condition so that
6042 it generates the same result when the operands are swapped. */
6045 swap_mri_condition (int cc)
6049 case MCC ('h', 'i'): return MCC ('c', 's');
6050 case MCC ('l', 's'): return MCC ('c', 'c');
6051 /* <HS> is an alias for <CC>. */
6052 case MCC ('h', 's'):
6053 case MCC ('c', 'c'): return MCC ('l', 's');
6054 /* <LO> is an alias for <CS>. */
6055 case MCC ('l', 'o'):
6056 case MCC ('c', 's'): return MCC ('h', 'i');
6057 case MCC ('p', 'l'): return MCC ('m', 'i');
6058 case MCC ('m', 'i'): return MCC ('p', 'l');
6059 case MCC ('g', 'e'): return MCC ('l', 'e');
6060 case MCC ('l', 't'): return MCC ('g', 't');
6061 case MCC ('g', 't'): return MCC ('l', 't');
6062 case MCC ('l', 'e'): return MCC ('g', 'e');
6063 /* Issue a warning for conditions we can not swap. */
6064 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6065 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6066 case MCC ('v', 'c'):
6067 case MCC ('v', 's'):
6069 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6070 (char) (cc >> 8), (char) (cc));
6076 /* Reverse the sense of a condition. */
6079 reverse_mri_condition (int cc)
6083 case MCC ('h', 'i'): return MCC ('l', 's');
6084 case MCC ('l', 's'): return MCC ('h', 'i');
6085 /* <HS> is an alias for <CC> */
6086 case MCC ('h', 's'): return MCC ('l', 'o');
6087 case MCC ('c', 'c'): return MCC ('c', 's');
6088 /* <LO> is an alias for <CS> */
6089 case MCC ('l', 'o'): return MCC ('h', 's');
6090 case MCC ('c', 's'): return MCC ('c', 'c');
6091 case MCC ('n', 'e'): return MCC ('e', 'q');
6092 case MCC ('e', 'q'): return MCC ('n', 'e');
6093 case MCC ('v', 'c'): return MCC ('v', 's');
6094 case MCC ('v', 's'): return MCC ('v', 'c');
6095 case MCC ('p', 'l'): return MCC ('m', 'i');
6096 case MCC ('m', 'i'): return MCC ('p', 'l');
6097 case MCC ('g', 'e'): return MCC ('l', 't');
6098 case MCC ('l', 't'): return MCC ('g', 'e');
6099 case MCC ('g', 't'): return MCC ('l', 'e');
6100 case MCC ('l', 'e'): return MCC ('g', 't');
6105 /* Build an MRI structured control expression. This generates test
6106 and branch instructions. It goes to TRUELAB if the condition is
6107 true, and to FALSELAB if the condition is false. Exactly one of
6108 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6109 is the size qualifier for the expression. EXTENT is the size to
6110 use for the branch. */
6113 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6114 char *rightstart, char *rightstop,
6115 const char *truelab, const char *falselab,
6121 if (leftstart != NULL)
6123 struct m68k_op leftop, rightop;
6126 /* Swap the compare operands, if necessary, to produce a legal
6127 m68k compare instruction. Comparing a register operand with
6128 a non-register operand requires the register to be on the
6129 right (cmp, cmpa). Comparing an immediate value with
6130 anything requires the immediate value to be on the left
6135 (void) m68k_ip_op (leftstart, &leftop);
6140 (void) m68k_ip_op (rightstart, &rightop);
6143 if (rightop.mode == IMMED
6144 || ((leftop.mode == DREG || leftop.mode == AREG)
6145 && (rightop.mode != DREG && rightop.mode != AREG)))
6149 /* Correct conditional handling:
6150 if #1 <lt> d0 then ;means if (1 < d0)
6156 cmp #1,d0 if we do *not* swap the operands
6157 bgt true we need the swapped condition!
6164 leftstart = rightstart;
6167 leftstop = rightstop;
6172 cc = swap_mri_condition (cc);
6176 if (truelab == NULL)
6178 cc = reverse_mri_condition (cc);
6182 if (leftstart != NULL)
6184 buf = (char *) xmalloc (20
6185 + (leftstop - leftstart)
6186 + (rightstop - rightstart));
6192 *s++ = TOLOWER (qual);
6194 memcpy (s, leftstart, leftstop - leftstart);
6195 s += leftstop - leftstart;
6197 memcpy (s, rightstart, rightstop - rightstart);
6198 s += rightstop - rightstart;
6204 buf = (char *) xmalloc (20 + strlen (truelab));
6210 *s++ = TOLOWER (extent);
6212 strcpy (s, truelab);
6217 /* Parse an MRI structured control expression. This generates test
6218 and branch instructions. STOP is where the expression ends. It
6219 goes to TRUELAB if the condition is true, and to FALSELAB if the
6220 condition is false. Exactly one of TRUELAB and FALSELAB will be
6221 NULL, meaning to fall through. QUAL is the size qualifier for the
6222 expression. EXTENT is the size to use for the branch. */
6225 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6226 const char *falselab, int extent)
6238 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6239 &rightstart, &rightstop))
6245 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6249 if (falselab != NULL)
6252 flab = mri_control_label ();
6254 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6255 rightstop, (const char *) NULL, flab, extent);
6257 input_line_pointer += 3;
6258 if (*input_line_pointer != '.'
6259 || input_line_pointer[1] == '\0')
6263 qual = input_line_pointer[1];
6264 input_line_pointer += 2;
6267 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6268 &rightstart, &rightstop))
6274 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6275 rightstop, truelab, falselab, extent);
6277 if (falselab == NULL)
6280 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6284 if (truelab != NULL)
6287 tlab = mri_control_label ();
6289 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6290 rightstop, tlab, (const char *) NULL, extent);
6292 input_line_pointer += 2;
6293 if (*input_line_pointer != '.'
6294 || input_line_pointer[1] == '\0')
6298 qual = input_line_pointer[1];
6299 input_line_pointer += 2;
6302 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6303 &rightstart, &rightstop))
6309 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6310 rightstop, truelab, falselab, extent);
6312 if (truelab == NULL)
6317 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6318 rightstop, truelab, falselab, extent);
6322 if (input_line_pointer != stop)
6323 as_bad (_("syntax error in structured control directive"));
6326 /* Handle the MRI IF pseudo-op. This may be a structured control
6327 directive, or it may be a regular assembler conditional, depending
6335 struct mri_control_info *n;
6337 /* A structured control directive must end with THEN with an
6338 optional qualifier. */
6339 s = input_line_pointer;
6340 /* We only accept '*' as introduction of comments if preceded by white space
6341 or at first column of a line (I think this can't actually happen here?)
6342 This is important when assembling:
6343 if d0 <ne> 12(a0,d0*2) then
6344 if d0 <ne> #CONST*20 then. */
6345 while (! (is_end_of_line[(unsigned char) *s]
6348 && (s == input_line_pointer
6350 || *(s-1) == '\t'))))
6353 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6356 if (s - input_line_pointer > 1
6360 if (s - input_line_pointer < 3
6361 || strncasecmp (s - 3, "THEN", 4) != 0)
6365 as_bad (_("missing then"));
6366 ignore_rest_of_line ();
6370 /* It's a conditional. */
6375 /* Since this might be a conditional if, this pseudo-op will be
6376 called even if we are supported to be ignoring input. Double
6377 check now. Clobber *input_line_pointer so that ignore_input
6378 thinks that this is not a special pseudo-op. */
6379 c = *input_line_pointer;
6380 *input_line_pointer = 0;
6381 if (ignore_input ())
6383 *input_line_pointer = c;
6384 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6385 ++input_line_pointer;
6386 demand_empty_rest_of_line ();
6389 *input_line_pointer = c;
6391 n = push_mri_control (mri_if);
6393 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6394 n->next, s[1] == '.' ? s[2] : '\0');
6397 input_line_pointer = s + 3;
6399 input_line_pointer = s + 1;
6403 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6404 ++input_line_pointer;
6407 demand_empty_rest_of_line ();
6410 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6411 structured IF, associate the ELSE with the IF. Otherwise, assume
6412 it is a conditional else. */
6415 s_mri_else (int qual)
6422 && (mri_control_stack == NULL
6423 || mri_control_stack->type != mri_if
6424 || mri_control_stack->else_seen))
6430 c = *input_line_pointer;
6431 *input_line_pointer = 0;
6432 if (ignore_input ())
6434 *input_line_pointer = c;
6435 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6436 ++input_line_pointer;
6437 demand_empty_rest_of_line ();
6440 *input_line_pointer = c;
6442 if (mri_control_stack == NULL
6443 || mri_control_stack->type != mri_if
6444 || mri_control_stack->else_seen)
6446 as_bad (_("else without matching if"));
6447 ignore_rest_of_line ();
6451 mri_control_stack->else_seen = 1;
6453 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6454 q[0] = TOLOWER (qual);
6456 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6460 colon (mri_control_stack->next);
6464 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6465 ++input_line_pointer;
6468 demand_empty_rest_of_line ();
6471 /* Handle the MRI ENDI pseudo-op. */
6474 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6476 if (mri_control_stack == NULL
6477 || mri_control_stack->type != mri_if)
6479 as_bad (_("endi without matching if"));
6480 ignore_rest_of_line ();
6484 /* ignore_input will not return true for ENDI, so we don't need to
6485 worry about checking it again here. */
6487 if (! mri_control_stack->else_seen)
6488 colon (mri_control_stack->next);
6489 colon (mri_control_stack->bottom);
6495 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6496 ++input_line_pointer;
6499 demand_empty_rest_of_line ();
6502 /* Handle the MRI BREAK pseudo-op. */
6505 s_mri_break (int extent)
6507 struct mri_control_info *n;
6511 n = mri_control_stack;
6513 && n->type != mri_for
6514 && n->type != mri_repeat
6515 && n->type != mri_while)
6519 as_bad (_("break outside of structured loop"));
6520 ignore_rest_of_line ();
6524 buf = (char *) xmalloc (20 + strlen (n->bottom));
6525 ex[0] = TOLOWER (extent);
6527 sprintf (buf, "bra%s %s", ex, n->bottom);
6533 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6534 ++input_line_pointer;
6537 demand_empty_rest_of_line ();
6540 /* Handle the MRI NEXT pseudo-op. */
6543 s_mri_next (int extent)
6545 struct mri_control_info *n;
6549 n = mri_control_stack;
6551 && n->type != mri_for
6552 && n->type != mri_repeat
6553 && n->type != mri_while)
6557 as_bad (_("next outside of structured loop"));
6558 ignore_rest_of_line ();
6562 buf = (char *) xmalloc (20 + strlen (n->next));
6563 ex[0] = TOLOWER (extent);
6565 sprintf (buf, "bra%s %s", ex, n->next);
6571 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6572 ++input_line_pointer;
6575 demand_empty_rest_of_line ();
6578 /* Handle the MRI FOR pseudo-op. */
6581 s_mri_for (int qual)
6583 const char *varstart, *varstop;
6584 const char *initstart, *initstop;
6585 const char *endstart, *endstop;
6586 const char *bystart, *bystop;
6590 struct mri_control_info *n;
6596 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6600 varstart = input_line_pointer;
6602 /* Look for the '='. */
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6604 && *input_line_pointer != '=')
6605 ++input_line_pointer;
6606 if (*input_line_pointer != '=')
6608 as_bad (_("missing ="));
6609 ignore_rest_of_line ();
6613 varstop = input_line_pointer;
6614 if (varstop > varstart
6615 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6618 ++input_line_pointer;
6620 initstart = input_line_pointer;
6622 /* Look for TO or DOWNTO. */
6625 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6627 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6628 && ! is_part_of_name (input_line_pointer[2]))
6630 initstop = input_line_pointer;
6631 input_line_pointer += 2;
6634 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6635 && ! is_part_of_name (input_line_pointer[6]))
6637 initstop = input_line_pointer;
6639 input_line_pointer += 6;
6642 ++input_line_pointer;
6644 if (initstop == NULL)
6646 as_bad (_("missing to or downto"));
6647 ignore_rest_of_line ();
6650 if (initstop > initstart
6651 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6655 endstart = input_line_pointer;
6657 /* Look for BY or DO. */
6660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6662 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6663 && ! is_part_of_name (input_line_pointer[2]))
6665 endstop = input_line_pointer;
6667 input_line_pointer += 2;
6670 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6671 && (input_line_pointer[2] == '.'
6672 || ! is_part_of_name (input_line_pointer[2])))
6674 endstop = input_line_pointer;
6675 input_line_pointer += 2;
6678 ++input_line_pointer;
6680 if (endstop == NULL)
6682 as_bad (_("missing do"));
6683 ignore_rest_of_line ();
6686 if (endstop > endstart
6687 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6693 bystop = bystart + 2;
6698 bystart = input_line_pointer;
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6704 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6705 && (input_line_pointer[2] == '.'
6706 || ! is_part_of_name (input_line_pointer[2])))
6708 bystop = input_line_pointer;
6709 input_line_pointer += 2;
6712 ++input_line_pointer;
6716 as_bad (_("missing do"));
6717 ignore_rest_of_line ();
6720 if (bystop > bystart
6721 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6725 if (*input_line_pointer != '.')
6729 extent = input_line_pointer[1];
6730 input_line_pointer += 2;
6733 /* We have fully parsed the FOR operands. Now build the loop. */
6734 n = push_mri_control (mri_for);
6736 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6738 /* Move init,var. */
6745 *s++ = TOLOWER (qual);
6747 memcpy (s, initstart, initstop - initstart);
6748 s += initstop - initstart;
6750 memcpy (s, varstart, varstop - varstart);
6751 s += varstop - varstart;
6763 *s++ = TOLOWER (qual);
6765 memcpy (s, endstart, endstop - endstart);
6766 s += endstop - endstart;
6768 memcpy (s, varstart, varstop - varstart);
6769 s += varstop - varstart;
6774 ex[0] = TOLOWER (extent);
6777 sprintf (buf, "blt%s %s", ex, n->bottom);
6779 sprintf (buf, "bgt%s %s", ex, n->bottom);
6782 /* Put together the add or sub instruction used by ENDF. */
6790 *s++ = TOLOWER (qual);
6792 memcpy (s, bystart, bystop - bystart);
6793 s += bystop - bystart;
6795 memcpy (s, varstart, varstop - varstart);
6796 s += varstop - varstart;
6802 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6803 ++input_line_pointer;
6806 demand_empty_rest_of_line ();
6809 /* Handle the MRI ENDF pseudo-op. */
6812 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6814 if (mri_control_stack == NULL
6815 || mri_control_stack->type != mri_for)
6817 as_bad (_("endf without for"));
6818 ignore_rest_of_line ();
6822 colon (mri_control_stack->next);
6824 mri_assemble (mri_control_stack->incr);
6826 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6827 mri_assemble (mri_control_stack->incr);
6829 free (mri_control_stack->incr);
6831 colon (mri_control_stack->bottom);
6837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6838 ++input_line_pointer;
6841 demand_empty_rest_of_line ();
6844 /* Handle the MRI REPEAT pseudo-op. */
6847 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6849 struct mri_control_info *n;
6851 n = push_mri_control (mri_repeat);
6855 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6856 ++input_line_pointer;
6858 demand_empty_rest_of_line ();
6861 /* Handle the MRI UNTIL pseudo-op. */
6864 s_mri_until (int qual)
6868 if (mri_control_stack == NULL
6869 || mri_control_stack->type != mri_repeat)
6871 as_bad (_("until without repeat"));
6872 ignore_rest_of_line ();
6876 colon (mri_control_stack->next);
6878 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6881 parse_mri_control_expression (s, qual, (const char *) NULL,
6882 mri_control_stack->top, '\0');
6884 colon (mri_control_stack->bottom);
6886 input_line_pointer = s;
6892 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6893 ++input_line_pointer;
6896 demand_empty_rest_of_line ();
6899 /* Handle the MRI WHILE pseudo-op. */
6902 s_mri_while (int qual)
6906 struct mri_control_info *n;
6908 s = input_line_pointer;
6909 /* We only accept '*' as introduction of comments if preceded by white space
6910 or at first column of a line (I think this can't actually happen here?)
6911 This is important when assembling:
6912 while d0 <ne> 12(a0,d0*2) do
6913 while d0 <ne> #CONST*20 do. */
6914 while (! (is_end_of_line[(unsigned char) *s]
6917 && (s == input_line_pointer
6919 || *(s-1) == '\t'))))
6922 while (*s == ' ' || *s == '\t')
6924 if (s - input_line_pointer > 1
6927 if (s - input_line_pointer < 2
6928 || strncasecmp (s - 1, "DO", 2) != 0)
6930 as_bad (_("missing do"));
6931 ignore_rest_of_line ();
6935 n = push_mri_control (mri_while);
6939 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6940 s[1] == '.' ? s[2] : '\0');
6942 input_line_pointer = s + 1;
6943 if (*input_line_pointer == '.')
6944 input_line_pointer += 2;
6948 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6949 ++input_line_pointer;
6952 demand_empty_rest_of_line ();
6955 /* Handle the MRI ENDW pseudo-op. */
6958 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6962 if (mri_control_stack == NULL
6963 || mri_control_stack->type != mri_while)
6965 as_bad (_("endw without while"));
6966 ignore_rest_of_line ();
6970 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6971 sprintf (buf, "bra %s", mri_control_stack->next);
6975 colon (mri_control_stack->bottom);
6981 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6982 ++input_line_pointer;
6985 demand_empty_rest_of_line ();
6988 /* Parse a .cpu directive. */
6991 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6998 as_bad (_("already assembled instructions"));
6999 ignore_rest_of_line ();
7003 name = input_line_pointer;
7004 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7005 input_line_pointer++;
7006 saved_char = *input_line_pointer;
7007 *input_line_pointer = 0;
7009 m68k_set_cpu (name, 1, 0);
7011 *input_line_pointer = saved_char;
7012 demand_empty_rest_of_line ();
7016 /* Parse a .arch directive. */
7019 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7026 as_bad (_("already assembled instructions"));
7027 ignore_rest_of_line ();
7031 name = input_line_pointer;
7032 while (*input_line_pointer && *input_line_pointer != ','
7033 && !ISSPACE (*input_line_pointer))
7034 input_line_pointer++;
7035 saved_char = *input_line_pointer;
7036 *input_line_pointer = 0;
7038 if (m68k_set_arch (name, 1, 0))
7040 /* Scan extensions. */
7043 *input_line_pointer++ = saved_char;
7044 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7046 name = input_line_pointer;
7047 while (*input_line_pointer && *input_line_pointer != ','
7048 && !ISSPACE (*input_line_pointer))
7049 input_line_pointer++;
7050 saved_char = *input_line_pointer;
7051 *input_line_pointer = 0;
7053 while (m68k_set_extension (name, 1, 0));
7056 *input_line_pointer = saved_char;
7057 demand_empty_rest_of_line ();
7061 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7062 if none is found, the caller is responsible for emitting an error
7063 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7064 cpu name, if it begins with a '6' (possibly skipping an intervening
7065 'c'. We also allow a 'c' in the same place. if NEGATED is
7066 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7067 the option is indeed negated. */
7069 static const struct m68k_cpu *
7070 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7071 int allow_m, int *negated)
7073 /* allow negated value? */
7078 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7085 /* Remove 'm' or 'mc' prefix from 68k variants. */
7092 else if (arg[1] == 'c' && arg[2] == '6')
7096 else if (arg[0] == 'c' && arg[1] == '6')
7099 for (; table->name; table++)
7100 if (!strcmp (arg, table->name))
7102 if (table->alias < -1 || table->alias > 1)
7103 as_bad (_("`%s' is deprecated, use `%s'"),
7104 table->name, table[table->alias < 0 ? 1 : -1].name);
7110 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7113 m68k_set_cpu (char const *name, int allow_m, int silent)
7115 const struct m68k_cpu *cpu;
7117 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7122 as_bad (_("cpu `%s' unrecognized"), name);
7126 if (selected_cpu && selected_cpu != cpu)
7128 as_bad (_("already selected `%s' processor"),
7129 selected_cpu->name);
7136 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7139 m68k_set_arch (char const *name, int allow_m, int silent)
7141 const struct m68k_cpu *arch;
7143 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7148 as_bad (_("architecture `%s' unrecognized"), name);
7152 if (selected_arch && selected_arch != arch)
7154 as_bad (_("already selected `%s' architecture"),
7155 selected_arch->name);
7159 selected_arch = arch;
7163 /* Set the architecture extension, issuing errors if it is
7164 unrecognized, or invalid */
7167 m68k_set_extension (char const *name, int allow_m, int silent)
7170 const struct m68k_cpu *ext;
7172 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7177 as_bad (_("extension `%s' unrecognized"), name);
7182 not_current_architecture |= ext->arch;
7184 current_architecture |= ext->arch;
7189 Invocation line includes a switch not recognized by the base assembler.
7193 const char *md_shortopts = "lSA:m:kQ:V";
7195 const char *md_shortopts = "lSA:m:k";
7198 struct option md_longopts[] = {
7199 #define OPTION_PIC (OPTION_MD_BASE)
7200 {"pic", no_argument, NULL, OPTION_PIC},
7201 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7202 {"register-prefix-optional", no_argument, NULL,
7203 OPTION_REGISTER_PREFIX_OPTIONAL},
7204 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7205 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7206 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7207 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7208 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7209 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7210 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7211 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7212 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7213 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7214 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7215 {"pcrel", no_argument, NULL, OPTION_PCREL},
7216 {NULL, no_argument, NULL, 0}
7218 size_t md_longopts_size = sizeof (md_longopts);
7221 md_parse_option (int c, char *arg)
7225 case 'l': /* -l means keep external to 2 bit offset
7226 rather than 16 bit one. */
7227 flag_short_refs = 1;
7230 case 'S': /* -S means that jbsr's always turn into
7232 flag_long_jumps = 1;
7235 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7236 branches into absolute jumps. */
7237 flag_keep_pcrel = 1;
7243 break; /* -pic, Position Independent Code. */
7245 case OPTION_REGISTER_PREFIX_OPTIONAL:
7246 flag_reg_prefix_optional = 1;
7247 reg_prefix_optional_seen = 1;
7250 /* -V: SVR4 argument to print version ID. */
7252 print_version_id ();
7255 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7256 should be emitted or not. FIXME: Not implemented. */
7260 case OPTION_BITWISE_OR:
7265 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7267 for (s = m68k_comment_chars; *s != '\0'; s++)
7271 m68k_comment_chars = n;
7275 case OPTION_BASE_SIZE_DEFAULT_16:
7276 m68k_index_width_default = SIZE_WORD;
7279 case OPTION_BASE_SIZE_DEFAULT_32:
7280 m68k_index_width_default = SIZE_LONG;
7283 case OPTION_DISP_SIZE_DEFAULT_16:
7285 m68k_rel32_from_cmdline = 1;
7288 case OPTION_DISP_SIZE_DEFAULT_32:
7290 m68k_rel32_from_cmdline = 1;
7295 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7298 /* Intentional fall-through. */
7300 if (!strncmp (arg, "arch=", 5))
7301 m68k_set_arch (arg + 5, 1, 0);
7302 else if (!strncmp (arg, "cpu=", 4))
7303 m68k_set_cpu (arg + 4, 1, 0);
7304 else if (m68k_set_extension (arg, 0, 1))
7306 else if (m68k_set_arch (arg, 0, 1))
7308 else if (m68k_set_cpu (arg, 0, 1))
7321 /* Setup tables from the selected arch and/or cpu */
7324 m68k_init_arch (void)
7326 if (not_current_architecture & current_architecture)
7328 as_bad (_("architecture features both enabled and disabled"));
7329 not_current_architecture &= ~current_architecture;
7333 current_architecture |= selected_arch->arch;
7334 control_regs = selected_arch->control_regs;
7337 current_architecture |= selected_cpu->arch;
7339 current_architecture &= ~not_current_architecture;
7341 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7343 /* Determine which float is really meant. */
7344 if (current_architecture & (m68k_mask & ~m68881))
7345 current_architecture ^= cfloat;
7347 current_architecture ^= m68881;
7352 control_regs = selected_cpu->control_regs;
7353 if (current_architecture & ~selected_cpu->arch)
7355 as_bad (_("selected processor does not have all features of selected architecture"));
7356 current_architecture
7357 = selected_cpu->arch & ~not_current_architecture;
7361 if ((current_architecture & m68k_mask)
7362 && (current_architecture & ~m68k_mask))
7364 as_bad (_ ("m68k and cf features both selected"));
7365 if (current_architecture & m68k_mask)
7366 current_architecture &= m68k_mask;
7368 current_architecture &= ~m68k_mask;
7371 /* Permit m68881 specification with all cpus; those that can't work
7372 with a coprocessor could be doing emulation. */
7373 if (current_architecture & m68851)
7375 if (current_architecture & m68040)
7376 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7378 /* What other incompatibilities could we check for? */
7380 if (cpu_of_arch (current_architecture) < m68020
7381 || arch_coldfire_p (current_architecture))
7382 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7388 md_show_usage (FILE *stream)
7390 const char *default_cpu = TARGET_CPU;
7392 unsigned int default_arch;
7394 /* Get the canonical name for the default target CPU. */
7395 if (*default_cpu == 'm')
7397 for (i = 0; m68k_cpus[i].name; i++)
7399 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7401 default_arch = m68k_cpus[i].arch;
7402 while (m68k_cpus[i].alias > 0)
7404 while (m68k_cpus[i].alias < 0)
7406 default_cpu = m68k_cpus[i].name;
7410 fprintf (stream, _("\
7411 -march=<arch> set architecture\n\
7412 -mcpu=<cpu> set cpu [default %s]\n\
7414 for (i = 0; m68k_extensions[i].name; i++)
7415 fprintf (stream, _("\
7416 -m[no-]%-16s enable/disable%s architecture extension\n\
7417 "), m68k_extensions[i].name,
7418 m68k_extensions[i].alias > 0 ? " ColdFire"
7419 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7421 fprintf (stream, _("\
7422 -l use 1 word for refs to undefined symbols [default 2]\n\
7423 -pic, -k generate position independent code\n\
7424 -S turn jbsr into jsr\n\
7425 --pcrel never turn PC-relative branches into absolute jumps\n\
7426 --register-prefix-optional\n\
7427 recognize register names without prefix character\n\
7428 --bitwise-or do not treat `|' as a comment character\n\
7429 --base-size-default-16 base reg without size is 16 bits\n\
7430 --base-size-default-32 base reg without size is 32 bits (default)\n\
7431 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7432 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7435 fprintf (stream, _("Architecture variants are: "));
7436 for (i = 0; m68k_archs[i].name; i++)
7439 fprintf (stream, " | ");
7440 fprintf (stream, m68k_archs[i].name);
7442 fprintf (stream, "\n");
7444 fprintf (stream, _("Processor variants are: "));
7445 for (i = 0; m68k_cpus[i].name; i++)
7448 fprintf (stream, " | ");
7449 fprintf (stream, m68k_cpus[i].name);
7451 fprintf (stream, _("\n"));
7456 /* TEST2: Test md_assemble() */
7457 /* Warning, this routine probably doesn't work anymore. */
7461 struct m68k_it the_ins;
7469 if (!gets (buf) || !*buf)
7471 if (buf[0] == '|' || buf[1] == '.')
7473 for (cp = buf; *cp; cp++)
7478 memset (&the_ins, '\0', sizeof (the_ins));
7479 m68k_ip (&the_ins, buf);
7482 printf (_("Error %s in %s\n"), the_ins.error, buf);
7486 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7487 for (n = 0; n < the_ins.numo; n++)
7488 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7490 print_the_insn (&the_ins.opcode[0], stdout);
7491 (void) putchar ('\n');
7493 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7495 if (the_ins.operands[n].error)
7497 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7500 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7501 the_ins.operands[n].reg);
7502 if (the_ins.operands[n].b_const)
7503 printf ("Constant: '%.*s', ",
7504 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7505 the_ins.operands[n].b_const);
7506 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7507 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7508 if (the_ins.operands[n].b_iadd)
7509 printf ("Iadd: '%.*s',",
7510 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7511 the_ins.operands[n].b_iadd);
7520 is_label (char *str)
7524 while (*str && *str != ' ')
7526 if (str[-1] == ':' || str[1] == '=')
7533 /* Possible states for relaxation:
7535 0 0 branch offset byte (bra, etc)
7539 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7543 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7550 /* We have no need to default values of symbols. */
7553 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7558 /* Round up a section size to the appropriate boundary. */
7560 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7563 /* For a.out, force the section size to be aligned. If we don't do
7564 this, BFD will align it for us, but it will not write out the
7565 final bytes of the section. This may be a bug in BFD, but it is
7566 easier to fix it here since that is how the other a.out targets
7570 align = bfd_get_section_alignment (stdoutput, segment);
7571 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7577 /* Exactly what point is a PC-relative offset relative TO?
7578 On the 68k, it is relative to the address of the first extension
7579 word. The difference between the addresses of the offset and the
7580 first extension word is stored in fx_pcrel_adjust. */
7582 md_pcrel_from (fixS *fixP)
7586 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7587 sign extend the value here. */
7588 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7591 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7596 m68k_elf_final_processing (void)
7600 if (arch_coldfire_fpu (current_architecture))
7601 flags |= EF_M68K_CFV4E;
7602 /* Set file-specific flags if this is a cpu32 processor. */
7603 if (cpu_of_arch (current_architecture) & cpu32)
7604 flags |= EF_M68K_CPU32;
7605 else if (cpu_of_arch (current_architecture) & fido_a)
7606 flags |= EF_M68K_FIDO;
7607 else if ((cpu_of_arch (current_architecture) & m68000up)
7608 && !(cpu_of_arch (current_architecture) & m68020up))
7609 flags |= EF_M68K_M68000;
7611 if (current_architecture & mcfisa_a)
7613 static const unsigned isa_features[][2] =
7615 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7616 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7617 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7618 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7619 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7622 static const unsigned mac_features[][2] =
7624 {EF_M68K_CF_MAC, mcfmac},
7625 {EF_M68K_CF_EMAC, mcfemac},
7631 pattern = (current_architecture
7632 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7633 for (ix = 0; isa_features[ix][1]; ix++)
7635 if (pattern == isa_features[ix][1])
7637 flags |= isa_features[ix][0];
7641 if (!isa_features[ix][1])
7644 as_warn (_("Not a defined coldfire architecture"));
7648 if (current_architecture & cfloat)
7649 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7651 pattern = current_architecture & (mcfmac|mcfemac);
7654 for (ix = 0; mac_features[ix][1]; ix++)
7656 if (pattern == mac_features[ix][1])
7658 flags |= mac_features[ix][0];
7662 if (!mac_features[ix][1])
7667 elf_elfheader (stdoutput)->e_flags |= flags;
7672 tc_m68k_regname_to_dw2regnum (char *regname)
7674 unsigned int regnum;
7675 static const char *const regnames[] =
7677 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7678 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7679 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7683 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7684 if (strcmp (regname, regnames[regnum]) == 0)
7691 tc_m68k_frame_initial_instructions (void)
7693 static int sp_regno = -1;
7696 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7698 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7699 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);