1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
86 int flag_reg_prefix_optional;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32 = 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line *next;
127 /* The list of labels. */
129 static struct label_line *labels;
131 /* The current label. */
133 static struct label_line *current_label;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn;
144 const char *m_operands;
145 unsigned long m_opcode;
149 struct m68k_incant *m_next;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
179 static const enum m68k_register mcf51qe_ctrl[] = {
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
223 static const enum m68k_register mcf5250_ctrl[] = {
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBB,
315 #define cpu32_ctrl m68010_ctrl
317 static const enum m68k_register *control_regs;
319 /* Internal form of a 68020 instruction. */
323 const char *args; /* List of opcode info. */
326 int numo; /* Number of shorts in opcode. */
329 struct m68k_op operands[6];
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
334 int nfrag; /* Number of frags we have to produce. */
337 int fragoff; /* Where in the current opcode the frag ends. */
344 int nrel; /* Num of reloc strucs in use. */
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
360 /* Whether this expression needs special pic relocation, and if
362 enum pic_relocation pic_reloc;
365 reloc[5]; /* Five is enough??? */
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
385 static struct m68k_it the_ins; /* The instruction being assembled. */
387 #define op(ex) ((ex)->exp.X_op)
388 #define adds(ex) ((ex)->exp.X_add_symbol)
389 #define subs(ex) ((ex)->exp.X_op_symbol)
390 #define offs(ex) ((ex)->exp.X_add_number)
392 /* Macros for adding things to the m68k_it struct. */
393 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
395 /* Like addword, but goes BEFORE general operands. */
398 insop (int w, const struct m68k_incant *opcode)
401 for (z = the_ins.numo; z > opcode->m_codenum; --z)
402 the_ins.opcode[z] = the_ins.opcode[z - 1];
403 for (z = 0; z < the_ins.nrel; z++)
404 the_ins.reloc[z].n += 2;
405 for (z = 0; z < the_ins.nfrag; z++)
406 the_ins.fragb[z].fragoff++;
407 the_ins.opcode[opcode->m_codenum] = w;
411 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
414 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
416 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
417 ? the_ins.numo * 2 - 1
419 ? the_ins.numo * 2 + 1
420 : the_ins.numo * 2));
421 the_ins.reloc[the_ins.nrel].exp = exp->exp;
422 the_ins.reloc[the_ins.nrel].wid = width;
423 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
425 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
430 /* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
441 add_frag (symbolS *add, offsetT off, int type)
443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444 the_ins.fragb[the_ins.nfrag].fadd = add;
445 the_ins.fragb[the_ins.nfrag].foff = off;
446 the_ins.fragb[the_ins.nfrag++].fragty = type;
450 (op (ex) != O_constant && op (ex) != O_big)
452 static char *crack_operand (char *str, struct m68k_op *opP);
453 static int get_num (struct m68k_exp *exp, int ok);
454 static int reverse_16_bits (int in);
455 static int reverse_8_bits (int in);
456 static void install_gen_operand (int mode, int val);
457 static void install_operand (int mode, int val);
458 static void s_bss (int);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
485 unsigned long arch; /* Architecture features. */
486 const enum m68k_register *control_regs; /* Control regs on chip */
487 const char *name; /* Name */
488 int alias; /* Alias for a cannonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
495 /* We hold flags for features explicitly enabled and explicitly
497 static int current_architecture;
498 static int not_current_architecture;
499 static const struct m68k_cpu *selected_arch;
500 static const struct m68k_cpu *selected_cpu;
501 static int initialized;
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs[] =
506 {m68000, m68000_ctrl, "68000", 0},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
510 {m68040, m68040_ctrl, "68040", 0},
511 {m68060, m68060_ctrl, "68060", 0},
512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
513 {fido_a, fido_ctrl, "fidoa", 0},
514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
523 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
525 static const struct m68k_cpu m68k_extensions[] =
527 {m68851, NULL, "68851", -1},
528 {m68881, NULL, "68881", -1},
529 {m68881, NULL, "68882", -1},
531 {cfloat|m68881, NULL, "float", 0},
533 {mcfhwdiv, NULL, "div", 1},
534 {mcfusp, NULL, "usp", 1},
535 {mcfmac, NULL, "mac", 1},
536 {mcfemac, NULL, "emac", 1},
542 static const struct m68k_cpu m68k_cpus[] =
544 {m68000, m68000_ctrl, "68000", 0},
545 {m68000, m68000_ctrl, "68ec000", 1},
546 {m68000, m68000_ctrl, "68hc000", 1},
547 {m68000, m68000_ctrl, "68hc001", 1},
548 {m68000, m68000_ctrl, "68008", 1},
549 {m68000, m68000_ctrl, "68302", 1},
550 {m68000, m68000_ctrl, "68306", 1},
551 {m68000, m68000_ctrl, "68307", 1},
552 {m68000, m68000_ctrl, "68322", 1},
553 {m68000, m68000_ctrl, "68356", 1},
554 {m68010, m68010_ctrl, "68010", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
556 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
557 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
558 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
559 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
560 {m68040, m68040_ctrl, "68040", 0},
561 {m68040, m68040_ctrl, "68ec040", 1},
562 {m68060, m68060_ctrl, "68060", 0},
563 {m68060, m68060_ctrl, "68ec060", 1},
565 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
566 {cpu32|m68881, cpu32_ctrl, "68330", 1},
567 {cpu32|m68881, cpu32_ctrl, "68331", 1},
568 {cpu32|m68881, cpu32_ctrl, "68332", 1},
569 {cpu32|m68881, cpu32_ctrl, "68333", 1},
570 {cpu32|m68881, cpu32_ctrl, "68334", 1},
571 {cpu32|m68881, cpu32_ctrl, "68336", 1},
572 {cpu32|m68881, cpu32_ctrl, "68340", 1},
573 {cpu32|m68881, cpu32_ctrl, "68341", 1},
574 {cpu32|m68881, cpu32_ctrl, "68349", 1},
575 {cpu32|m68881, cpu32_ctrl, "68360", 1},
577 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
579 {mcfisa_a, mcf_ctrl, "5200", 0},
580 {mcfisa_a, mcf_ctrl, "5202", 1},
581 {mcfisa_a, mcf_ctrl, "5204", 1},
582 {mcfisa_a, mcf5206_ctrl, "5206", 1},
584 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
619 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
634 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
670 {fido_a, fido_ctrl, "fidoa", 0},
671 {fido_a, fido_ctrl, "fido", 1},
676 static const struct m68k_cpu *m68k_lookup_cpu
677 (const char *, const struct m68k_cpu *, int, int *);
678 static int m68k_set_arch (const char *, int, int);
679 static int m68k_set_cpu (const char *, int, int);
680 static int m68k_set_extension (const char *, int, int);
681 static void m68k_init_arch (void);
683 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
684 architecture and we have a lot of relaxation modes. */
686 /* Macros used in the relaxation code. */
687 #define TAB(x,y) (((x) << 2) + (y))
688 #define TABTYPE(x) ((x) >> 2)
690 /* Relaxation states. */
696 /* Here are all the relaxation modes we support. First we can relax ordinary
697 branches. On 68020 and higher and on CPU32 all branch instructions take
698 three forms, so on these CPUs all branches always remain as such. When we
699 have to expand to the LONG form on a 68000, though, we substitute an
700 absolute jump instead. This is a direct replacement for unconditional
701 branches and a branch over a jump for conditional branches. However, if the
702 user requires PIC and disables this with --pcrel, we can only relax between
703 BYTE and SHORT forms, punting if that isn't enough. This gives us four
704 different relaxation modes for branches: */
706 #define BRANCHBWL 0 /* Branch byte, word, or long. */
707 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
708 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
709 #define BRANCHBW 3 /* Branch byte or word. */
711 /* We also relax coprocessor branches and DBcc's. All CPUs that support
712 coprocessor branches support them in word and long forms, so we have only
713 one relaxation mode for them. DBcc's are word only on all CPUs. We can
714 relax them to the LONG form with a branch-around sequence. This sequence
715 can use a long branch (if available) or an absolute jump (if acceptable).
716 This gives us two relaxation modes. If long branches are not available and
717 absolute jumps are not acceptable, we don't relax DBcc's. */
719 #define FBRANCH 4 /* Coprocessor branch. */
720 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
721 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
723 /* That's all for instruction relaxation. However, we also relax PC-relative
724 operands. Specifically, we have three operand relaxation modes. On the
725 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
726 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
727 two. Also PC+displacement+index operands in their simple form (with a non-
728 suppressed index without memory indirection) are supported on all CPUs, but
729 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
730 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
731 form of the PC+displacement+index operand. Finally, some absolute operands
732 can be relaxed down to 16-bit PC-relative. */
734 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
735 #define PCINDEX 8 /* PC + displacement + index. */
736 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
738 /* This relaxation is required for branches where there is no long
739 branch and we are in pcrel mode. We generate a bne/beq pair. */
740 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
743 /* Note that calls to frag_var need to specify the maximum expansion
744 needed; this is currently 12 bytes for bne/beq pair. */
745 #define FRAG_VAR_SIZE 12
748 How far Forward this mode will reach:
749 How far Backward this mode will reach:
750 How many bytes this mode will add to the size of the frag
751 Which mode to go to if the offset won't fit in this one
753 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
754 relax_typeS md_relax_table[] =
756 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
757 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
761 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
762 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
766 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
767 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
771 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
776 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
777 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
781 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
782 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
786 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
787 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
791 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
792 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
796 { 125, -130, 0, TAB (PCINDEX, SHORT) },
797 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
801 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
802 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
806 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
807 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
812 /* These are the machine dependent pseudo-ops. These are included so
813 the assembler can work on the output from the SUN C compiler, which
816 /* This table describes all the machine specific pseudo-ops the assembler
817 has to support. The fields are:
818 pseudo-op name without dot
819 function to call to execute this pseudo-op
820 Integer arg to pass to the function. */
821 const pseudo_typeS md_pseudo_table[] =
823 {"data1", s_data1, 0},
824 {"data2", s_data2, 0},
827 {"skip", s_space, 0},
829 #if defined (TE_SUN3) || defined (OBJ_ELF)
830 {"align", s_align_bytes, 0},
833 {"swbeg", s_ignore, 0},
835 {"extend", float_cons, 'x'},
836 {"ldouble", float_cons, 'x'},
838 {"arch", s_m68k_arch, 0},
839 {"cpu", s_m68k_cpu, 0},
841 /* The following pseudo-ops are supported for MRI compatibility. */
843 {"comline", s_space, 1},
845 {"mask2", s_ignore, 0},
848 {"restore", s_restore, 0},
852 {"if.b", s_mri_if, 'b'},
853 {"if.w", s_mri_if, 'w'},
854 {"if.l", s_mri_if, 'l'},
855 {"else", s_mri_else, 0},
856 {"else.s", s_mri_else, 's'},
857 {"else.l", s_mri_else, 'l'},
858 {"endi", s_mri_endi, 0},
859 {"break", s_mri_break, 0},
860 {"break.s", s_mri_break, 's'},
861 {"break.l", s_mri_break, 'l'},
862 {"next", s_mri_next, 0},
863 {"next.s", s_mri_next, 's'},
864 {"next.l", s_mri_next, 'l'},
865 {"for", s_mri_for, 0},
866 {"for.b", s_mri_for, 'b'},
867 {"for.w", s_mri_for, 'w'},
868 {"for.l", s_mri_for, 'l'},
869 {"endf", s_mri_endf, 0},
870 {"repeat", s_mri_repeat, 0},
871 {"until", s_mri_until, 0},
872 {"until.b", s_mri_until, 'b'},
873 {"until.w", s_mri_until, 'w'},
874 {"until.l", s_mri_until, 'l'},
875 {"while", s_mri_while, 0},
876 {"while.b", s_mri_while, 'b'},
877 {"while.w", s_mri_while, 'w'},
878 {"while.l", s_mri_while, 'l'},
879 {"endw", s_mri_endw, 0},
884 /* The mote pseudo ops are put into the opcode table, since they
885 don't start with a . they look like opcodes to gas. */
887 const pseudo_typeS mote_pseudo_table[] =
900 {"xdef", s_globl, 0},
902 {"align", s_align_bytes, 0},
904 {"align", s_align_ptwo, 0},
907 {"sect", obj_coff_section, 0},
908 {"section", obj_coff_section, 0},
913 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
914 gives identical results to a 32-bit host. */
915 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
916 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
918 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
919 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
920 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
921 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
923 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
924 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
925 #define islong(x) (1)
927 static char notend_table[256];
928 static char alt_notend_table[256];
930 (! (notend_table[(unsigned char) *s] \
932 && alt_notend_table[(unsigned char) s[1]])))
936 /* Return zero if the reference to SYMBOL from within the same segment may
939 /* On an ELF system, we can't relax an externally visible symbol,
940 because it may be overridden by a shared library. However, if
941 TARGET_OS is "elf", then we presume that we are assembling for an
942 embedded system, in which case we don't have to worry about shared
943 libraries, and we can relax any external sym. */
945 #define relaxable_symbol(symbol) \
946 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
947 || S_IS_WEAK (symbol)))
949 /* Compute the relocation code for a fixup of SIZE bytes, using pc
950 relative relocation if PCREL is non-zero. PIC says whether a special
951 pic relocation was requested. */
953 static bfd_reloc_code_real_type
954 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
962 return BFD_RELOC_8_GOT_PCREL;
964 return BFD_RELOC_16_GOT_PCREL;
966 return BFD_RELOC_32_GOT_PCREL;
974 return BFD_RELOC_8_GOTOFF;
976 return BFD_RELOC_16_GOTOFF;
978 return BFD_RELOC_32_GOTOFF;
986 return BFD_RELOC_8_PLT_PCREL;
988 return BFD_RELOC_16_PLT_PCREL;
990 return BFD_RELOC_32_PLT_PCREL;
998 return BFD_RELOC_8_PLTOFF;
1000 return BFD_RELOC_16_PLTOFF;
1002 return BFD_RELOC_32_PLTOFF;
1012 return BFD_RELOC_8_PCREL;
1014 return BFD_RELOC_16_PCREL;
1016 return BFD_RELOC_32_PCREL;
1026 return BFD_RELOC_16;
1028 return BFD_RELOC_32;
1035 if (pic == pic_none)
1036 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1038 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1042 if (pic == pic_none)
1043 as_bad (_("Can not do %d byte relocation"), size);
1045 as_bad (_("Can not do %d byte pic relocation"), size);
1048 return BFD_RELOC_NONE;
1051 /* Here we decide which fixups can be adjusted to make them relative
1052 to the beginning of the section instead of the symbol. Basically
1053 we need to make sure that the dynamic relocations are done
1054 correctly, so in some cases we force the original symbol to be
1057 tc_m68k_fix_adjustable (fixS *fixP)
1059 /* Adjust_reloc_syms doesn't know about the GOT. */
1060 switch (fixP->fx_r_type)
1062 case BFD_RELOC_8_GOT_PCREL:
1063 case BFD_RELOC_16_GOT_PCREL:
1064 case BFD_RELOC_32_GOT_PCREL:
1065 case BFD_RELOC_8_GOTOFF:
1066 case BFD_RELOC_16_GOTOFF:
1067 case BFD_RELOC_32_GOTOFF:
1068 case BFD_RELOC_8_PLT_PCREL:
1069 case BFD_RELOC_16_PLT_PCREL:
1070 case BFD_RELOC_32_PLT_PCREL:
1071 case BFD_RELOC_8_PLTOFF:
1072 case BFD_RELOC_16_PLTOFF:
1073 case BFD_RELOC_32_PLTOFF:
1076 case BFD_RELOC_VTABLE_INHERIT:
1077 case BFD_RELOC_VTABLE_ENTRY:
1085 #else /* !OBJ_ELF */
1087 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1089 /* PR gas/3041 Weak symbols are not relaxable
1090 because they must be treated as extern. */
1091 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1093 #endif /* OBJ_ELF */
1096 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1099 bfd_reloc_code_real_type code;
1101 /* If the tcbit is set, then this was a fixup of a negative value
1102 that was never resolved. We do not have a reloc to handle this,
1103 so just return. We assume that other code will have detected this
1104 situation and produced a helpful error message, so we just tell the
1105 user that the reloc cannot be produced. */
1109 as_bad_where (fixp->fx_file, fixp->fx_line,
1110 _("Unable to produce reloc against symbol '%s'"),
1111 S_GET_NAME (fixp->fx_addsy));
1115 if (fixp->fx_r_type != BFD_RELOC_NONE)
1117 code = fixp->fx_r_type;
1119 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1120 that fixup_segment converted a non-PC relative reloc into a
1121 PC relative reloc. In such a case, we need to convert the
1128 code = BFD_RELOC_8_PCREL;
1131 code = BFD_RELOC_16_PCREL;
1134 code = BFD_RELOC_32_PCREL;
1136 case BFD_RELOC_8_PCREL:
1137 case BFD_RELOC_16_PCREL:
1138 case BFD_RELOC_32_PCREL:
1139 case BFD_RELOC_8_GOT_PCREL:
1140 case BFD_RELOC_16_GOT_PCREL:
1141 case BFD_RELOC_32_GOT_PCREL:
1142 case BFD_RELOC_8_GOTOFF:
1143 case BFD_RELOC_16_GOTOFF:
1144 case BFD_RELOC_32_GOTOFF:
1145 case BFD_RELOC_8_PLT_PCREL:
1146 case BFD_RELOC_16_PLT_PCREL:
1147 case BFD_RELOC_32_PLT_PCREL:
1148 case BFD_RELOC_8_PLTOFF:
1149 case BFD_RELOC_16_PLTOFF:
1150 case BFD_RELOC_32_PLTOFF:
1153 as_bad_where (fixp->fx_file, fixp->fx_line,
1154 _("Cannot make %s relocation PC relative"),
1155 bfd_get_reloc_code_name (code));
1161 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1162 switch (F (fixp->fx_size, fixp->fx_pcrel))
1164 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1165 MAP (1, 0, BFD_RELOC_8);
1166 MAP (2, 0, BFD_RELOC_16);
1167 MAP (4, 0, BFD_RELOC_32);
1168 MAP (1, 1, BFD_RELOC_8_PCREL);
1169 MAP (2, 1, BFD_RELOC_16_PCREL);
1170 MAP (4, 1, BFD_RELOC_32_PCREL);
1178 reloc = (arelent *) xmalloc (sizeof (arelent));
1179 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1180 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1181 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1184 reloc->addend = fixp->fx_addnumber;
1185 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1187 && S_IS_WEAK (fixp->fx_addsy)
1188 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1189 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1190 to put the symbol offset into frags referencing a weak symbol. */
1191 reloc->addend = fixp->fx_addnumber
1192 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1196 if (!fixp->fx_pcrel)
1197 reloc->addend = fixp->fx_addnumber;
1199 reloc->addend = (section->vma
1200 /* Explicit sign extension in case char is
1202 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1203 + fixp->fx_addnumber
1204 + md_pcrel_from (fixp));
1207 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1208 assert (reloc->howto != 0);
1213 /* Handle of the OPCODE hash table. NULL means any use before
1214 m68k_ip_begin() will crash. */
1215 static struct hash_control *op_hash;
1217 /* Assemble an m68k instruction. */
1220 m68k_ip (char *instring)
1223 register struct m68k_op *opP;
1224 register const struct m68k_incant *opcode;
1225 register const char *s;
1226 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1227 char *pdot, *pdotmove;
1228 enum m68k_size siz1, siz2;
1232 struct m68k_op operands_backup[6];
1233 LITTLENUM_TYPE words[6];
1234 LITTLENUM_TYPE *wordp;
1235 unsigned long ok_arch = 0;
1237 if (*instring == ' ')
1238 instring++; /* Skip leading whitespace. */
1240 /* Scan up to end of operation-code, which MUST end in end-of-string
1241 or exactly 1 space. */
1243 for (p = instring; *p != '\0'; p++)
1253 the_ins.error = _("No operator");
1257 /* p now points to the end of the opcode name, probably whitespace.
1258 Make sure the name is null terminated by clobbering the
1259 whitespace, look it up in the hash table, then fix it back.
1260 Remove a dot, first, since the opcode tables have none. */
1263 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1264 *pdotmove = pdotmove[1];
1270 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1275 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1276 *pdotmove = pdotmove[-1];
1283 the_ins.error = _("Unknown operator");
1287 /* Found a legitimate opcode, start matching operands. */
1291 if (opcode->m_operands == 0)
1293 char *old = input_line_pointer;
1295 input_line_pointer = p;
1296 /* Ahh - it's a motorola style psuedo op. */
1297 mote_pseudo_table[opcode->m_opnum].poc_handler
1298 (mote_pseudo_table[opcode->m_opnum].poc_val);
1299 input_line_pointer = old;
1305 if (flag_mri && opcode->m_opnum == 0)
1307 /* In MRI mode, random garbage is allowed after an instruction
1308 which accepts no operands. */
1309 the_ins.args = opcode->m_operands;
1310 the_ins.numargs = opcode->m_opnum;
1311 the_ins.numo = opcode->m_codenum;
1312 the_ins.opcode[0] = getone (opcode);
1313 the_ins.opcode[1] = gettwo (opcode);
1317 for (opP = &the_ins.operands[0]; *p; opP++)
1319 p = crack_operand (p, opP);
1323 the_ins.error = opP->error;
1328 opsfound = opP - &the_ins.operands[0];
1330 /* This ugly hack is to support the floating pt opcodes in their
1331 standard form. Essentially, we fake a first enty of type COP#1 */
1332 if (opcode->m_operands[0] == 'I')
1336 for (n = opsfound; n > 0; --n)
1337 the_ins.operands[n] = the_ins.operands[n - 1];
1339 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1340 the_ins.operands[0].mode = CONTROL;
1341 the_ins.operands[0].reg = m68k_float_copnum;
1345 /* We've got the operands. Find an opcode that'll accept them. */
1348 /* If we didn't get the right number of ops, or we have no
1349 common model with this pattern then reject this pattern. */
1351 ok_arch |= opcode->m_arch;
1352 if (opsfound != opcode->m_opnum
1353 || ((opcode->m_arch & current_architecture) == 0))
1359 /* Make a copy of the operands of this insn so that
1360 we can modify them safely, should we want to. */
1361 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1362 for (i = 0; i < opsfound; i++)
1363 operands_backup[i] = the_ins.operands[i];
1365 for (s = opcode->m_operands, opP = &operands_backup[0];
1369 /* Warning: this switch is huge! */
1370 /* I've tried to organize the cases into this order:
1371 non-alpha first, then alpha by letter. Lower-case
1372 goes directly before uppercase counterpart. */
1373 /* Code with multiple case ...: gets sorted by the lowest
1374 case ... it belongs to. I hope this makes sense. */
1480 if (opP->reg == PC || opP->reg == ZPC)
1497 if (opP->reg == PC || opP->reg == ZPC)
1516 if (opP->reg == PC || opP->reg == ZPC)
1526 if (opP->mode != IMMED)
1528 else if (s[1] == 'b'
1529 && ! isvar (&opP->disp)
1530 && (opP->disp.exp.X_op != O_constant
1531 || ! isbyte (opP->disp.exp.X_add_number)))
1533 else if (s[1] == 'B'
1534 && ! isvar (&opP->disp)
1535 && (opP->disp.exp.X_op != O_constant
1536 || ! issbyte (opP->disp.exp.X_add_number)))
1538 else if (s[1] == 'w'
1539 && ! isvar (&opP->disp)
1540 && (opP->disp.exp.X_op != O_constant
1541 || ! isword (opP->disp.exp.X_add_number)))
1543 else if (s[1] == 'W'
1544 && ! isvar (&opP->disp)
1545 && (opP->disp.exp.X_op != O_constant
1546 || ! issword (opP->disp.exp.X_add_number)))
1552 if (opP->mode != IMMED)
1557 if (opP->mode == AREG
1558 || opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == IMMED
1561 || opP->mode == REGLST
1562 || (opP->mode != ABSL
1564 || opP->reg == ZPC)))
1569 if (opP->mode == CONTROL
1570 || opP->mode == FPREG
1571 || opP->mode == REGLST
1572 || opP->mode == IMMED
1573 || (opP->mode != ABSL
1575 || opP->reg == ZPC)))
1603 if (opP->mode == CONTROL
1604 || opP->mode == FPREG
1605 || opP->mode == REGLST)
1610 if (opP->mode != AINC)
1615 if (opP->mode != ADEC)
1665 if (opP->reg == PC || opP->reg == ZPC)
1686 case '~': /* For now! (JF FOO is this right?) */
1708 if (opP->mode != CONTROL
1709 || (opP->reg != TT0 && opP->reg != TT1))
1714 if (opP->mode != AREG)
1719 if (opP->mode != AINDR)
1724 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1725 && (opP->mode != DISP
1727 || opP->reg > ADDR7))
1732 if (opP->mode != ABSL
1734 && strncmp (instring, "jbsr", 4) == 0))
1757 if (opP->mode != CONTROL || opP->reg != CCR)
1762 if (opP->mode != DISP
1764 || opP->reg > ADDR7)
1769 if (opP->mode != DREG)
1774 if (opP->reg != ACC)
1779 if (opP->reg != ACC && opP->reg != ACC1
1780 && opP->reg != ACC2 && opP->reg != ACC3)
1785 if (opP->mode != FPREG)
1790 if (opP->reg != MACSR)
1795 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1800 if (opP->reg != MASK)
1805 if (opP->mode != CONTROL
1812 if (opP->mode != LSH && opP->mode != RSH)
1817 if (opP->mode != CONTROL
1819 || opP->reg > last_movec_reg
1824 const enum m68k_register *rp;
1826 for (rp = control_regs; *rp; rp++)
1828 if (*rp == opP->reg)
1830 /* In most CPUs RAMBAR refers to control reg
1831 c05 (RAMBAR1), but a few CPUs have it
1832 refer to c04 (RAMBAR0). */
1833 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1835 opP->reg = RAMBAR_ALT;
1845 if (opP->mode != IMMED)
1851 if (opP->mode == DREG
1852 || opP->mode == AREG
1853 || opP->mode == FPREG)
1862 opP->mask = 1 << (opP->reg - DATA0);
1865 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1868 opP->mask = 1 << (opP->reg - FP0 + 16);
1876 else if (opP->mode == CONTROL)
1885 opP->mask = 1 << 24;
1888 opP->mask = 1 << 25;
1891 opP->mask = 1 << 26;
1900 else if (opP->mode != REGLST)
1902 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1904 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1909 if (opP->mode != IMMED)
1911 else if (opP->disp.exp.X_op != O_constant
1912 || ! issbyte (opP->disp.exp.X_add_number))
1914 else if (! m68k_quick
1915 && instring[3] != 'q'
1916 && instring[4] != 'q')
1921 if (opP->mode != DREG
1922 && opP->mode != IMMED
1923 && opP->mode != ABSL)
1928 if (opP->mode != IMMED)
1930 else if (opP->disp.exp.X_op != O_constant
1931 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1933 else if (! m68k_quick
1934 && (strncmp (instring, "add", 3) == 0
1935 || strncmp (instring, "sub", 3) == 0)
1936 && instring[3] != 'q')
1941 if (opP->mode != DREG && opP->mode != AREG)
1946 if (opP->mode != AINDR
1947 && (opP->mode != BASE
1949 && opP->reg != ZADDR0)
1950 || opP->disp.exp.X_op != O_absent
1951 || ((opP->index.reg < DATA0
1952 || opP->index.reg > DATA7)
1953 && (opP->index.reg < ADDR0
1954 || opP->index.reg > ADDR7))
1955 || opP->index.size != SIZE_UNSPEC
1956 || opP->index.scale != 1))
1961 if (opP->mode != CONTROL
1962 || ! (opP->reg == FPI
1964 || opP->reg == FPC))
1969 if (opP->mode != CONTROL || opP->reg != SR)
1974 if (opP->mode != IMMED)
1976 else if (opP->disp.exp.X_op != O_constant
1977 || TRUNC (opP->disp.exp.X_add_number) > 7)
1982 if (opP->mode != CONTROL || opP->reg != USP)
1987 if (opP->mode != IMMED)
1989 else if (opP->disp.exp.X_op != O_constant
1990 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1991 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1996 if (opP->mode != IMMED)
1998 else if (opP->disp.exp.X_op != O_constant
1999 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2004 if (opP->mode != IMMED)
2006 else if (opP->disp.exp.X_op != O_constant
2007 || TRUNC (opP->disp.exp.X_add_number) > 511)
2011 /* JF these are out of order. We could put them
2012 in order if we were willing to put up with
2013 bunches of #ifdef m68851s in the code.
2015 Don't forget that you need these operands
2016 to use 68030 MMU instructions. */
2018 /* Memory addressing mode used by pflushr. */
2020 if (opP->mode == CONTROL
2021 || opP->mode == FPREG
2022 || opP->mode == DREG
2023 || opP->mode == AREG
2024 || opP->mode == REGLST)
2026 /* We should accept immediate operands, but they
2027 supposedly have to be quad word, and we don't
2028 handle that. I would like to see what a Motorola
2029 assembler does before doing something here. */
2030 if (opP->mode == IMMED)
2035 if (opP->mode != CONTROL
2036 || (opP->reg != SFC && opP->reg != DFC))
2041 if (opP->mode != CONTROL || opP->reg != TC)
2046 if (opP->mode != CONTROL || opP->reg != AC)
2051 if (opP->mode != CONTROL
2054 && opP->reg != SCC))
2059 if (opP->mode != CONTROL
2065 if (opP->mode != CONTROL
2068 && opP->reg != CRP))
2092 if (opP->mode != CONTROL
2093 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2094 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2099 if (opP->mode != CONTROL || opP->reg != PSR)
2104 if (opP->mode != CONTROL || opP->reg != PCSR)
2109 if (opP->mode != CONTROL
2118 if (opP->mode != ABSL)
2123 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2125 /* FIXME: kludge instead of fixing parser:
2126 upper/lower registers are *not* CONTROL
2127 registers, but ordinary ones. */
2128 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2129 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2136 if (!(opP->mode == AINDR
2137 || (opP->mode == DISP
2138 && !(opP->reg == PC || opP->reg == ZPC))))
2143 if (!(opP->mode == AINDR || opP->mode == DISP))
2155 /* Since we have found the correct instruction, copy
2156 in the modifications that we may have made. */
2158 for (i = 0; i < opsfound; i++)
2159 the_ins.operands[i] = operands_backup[i];
2165 opcode = opcode->m_next;
2170 && !(ok_arch & current_architecture))
2172 const struct m68k_cpu *cpu;
2175 char *buf = xmalloc (space + 1);
2179 the_ins.error = buf;
2180 /* Make sure there's a NUL at the end of the buffer -- strncpy
2181 won't write one when it runs out of buffer */
2183 #define APPEND(STRING) \
2184 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2186 APPEND (_("invalid instruction for this architecture; needs "));
2190 APPEND (_("ColdFire ISA_A"));
2193 APPEND (_("ColdFire hardware divide"));
2196 APPEND (_("ColdFire ISA_A+"));
2199 APPEND (_("ColdFire ISA_B"));
2202 APPEND (_("ColdFire ISA_C"));
2205 APPEND (_("ColdFire fpu"));
2208 APPEND (_("M68K fpu"));
2211 APPEND (_("M68K mmu"));
2214 APPEND (_("68020 or higher"));
2217 APPEND (_("68000 or higher"));
2220 APPEND (_("68010 or higher"));
2228 for (cpu = m68k_cpus; cpu->name; cpu++)
2229 if (!cpu->alias && (cpu->arch & ok_arch))
2231 const struct m68k_cpu *alias;
2232 int seen_master = 0;
2238 for (alias = cpu; alias != m68k_cpus; alias--)
2239 if (alias[-1].alias >= 0)
2241 for (; !seen_master || alias->alias > 0; alias++)
2251 APPEND (alias->name);
2264 /* we ran out of space, so replace the end of the list
2269 strcpy (buf, " ...");
2273 the_ins.error = _("operands mismatch");
2280 /* Now assemble it. */
2281 the_ins.args = opcode->m_operands;
2282 the_ins.numargs = opcode->m_opnum;
2283 the_ins.numo = opcode->m_codenum;
2284 the_ins.opcode[0] = getone (opcode);
2285 the_ins.opcode[1] = gettwo (opcode);
2287 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2292 /* This switch is a doozy.
2293 Watch the first step; its a big one! */
2326 tmpreg = 0x3c; /* 7.4 */
2327 if (strchr ("bwl", s[1]))
2328 nextword = get_num (&opP->disp, 90);
2330 nextword = get_num (&opP->disp, 0);
2331 if (isvar (&opP->disp))
2332 add_fix (s[1], &opP->disp, 0, 0);
2336 if (!isbyte (nextword))
2337 opP->error = _("operand out of range");
2342 if (!isword (nextword))
2343 opP->error = _("operand out of range");
2348 if (!issword (nextword))
2349 opP->error = _("operand out of range");
2354 addword (nextword >> 16);
2381 /* We gotta put out some float. */
2382 if (op (&opP->disp) != O_big)
2387 /* Can other cases happen here? */
2388 if (op (&opP->disp) != O_constant)
2391 val = (valueT) offs (&opP->disp);
2395 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2396 val >>= LITTLENUM_NUMBER_OF_BITS;
2400 offs (&opP->disp) = gencnt;
2402 if (offs (&opP->disp) > 0)
2404 if (offs (&opP->disp) > baseo)
2406 as_warn (_("Bignum too big for %c format; truncated"),
2408 offs (&opP->disp) = baseo;
2410 baseo -= offs (&opP->disp);
2413 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2414 offs (&opP->disp)--;
2419 gen_to_words (words, baseo, (long) outro);
2420 for (wordp = words; baseo--; wordp++)
2424 tmpreg = opP->reg - DATA; /* 0.dreg */
2427 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2430 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2433 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2436 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2440 nextword = get_num (&opP->disp, 90);
2442 /* Convert mode 5 addressing with a zero offset into
2443 mode 2 addressing to reduce the instruction size by a
2445 if (! isvar (&opP->disp)
2447 && (opP->disp.size == SIZE_UNSPEC)
2448 && (opP->reg >= ADDR0)
2449 && (opP->reg <= ADDR7))
2451 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2456 && ! isvar (&opP->disp)
2459 opP->disp.exp.X_op = O_symbol;
2460 opP->disp.exp.X_add_symbol =
2461 section_symbol (absolute_section);
2464 /* Force into index mode. Hope this works. */
2466 /* We do the first bit for 32-bit displacements, and the
2467 second bit for 16 bit ones. It is possible that we
2468 should make the default be WORD instead of LONG, but
2469 I think that'd break GCC, so we put up with a little
2470 inefficiency for the sake of working output. */
2472 if (!issword (nextword)
2473 || (isvar (&opP->disp)
2474 && ((opP->disp.size == SIZE_UNSPEC
2475 && flag_short_refs == 0
2476 && cpu_of_arch (current_architecture) >= m68020
2477 && ! arch_coldfire_p (current_architecture))
2478 || opP->disp.size == SIZE_LONG)))
2480 if (cpu_of_arch (current_architecture) < m68020
2481 || arch_coldfire_p (current_architecture))
2483 _("displacement too large for this architecture; needs 68020 or higher");
2485 tmpreg = 0x3B; /* 7.3 */
2487 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2488 if (isvar (&opP->disp))
2492 if (opP->disp.size == SIZE_LONG
2494 /* If the displacement needs pic
2495 relocation it cannot be relaxed. */
2496 || opP->disp.pic_reloc != pic_none
2501 add_fix ('l', &opP->disp, 1, 2);
2505 add_frag (adds (&opP->disp),
2506 SEXT (offs (&opP->disp)),
2507 TAB (PCREL1632, SZ_UNDEF));
2514 add_fix ('l', &opP->disp, 0, 0);
2519 addword (nextword >> 16);
2524 tmpreg = 0x3A; /* 7.2 */
2526 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2528 if (isvar (&opP->disp))
2532 add_fix ('w', &opP->disp, 1, 0);
2535 add_fix ('w', &opP->disp, 0, 0);
2545 baseo = get_num (&opP->disp, 90);
2546 if (opP->mode == POST || opP->mode == PRE)
2547 outro = get_num (&opP->odisp, 90);
2548 /* Figure out the `addressing mode'.
2549 Also turn on the BASE_DISABLE bit, if needed. */
2550 if (opP->reg == PC || opP->reg == ZPC)
2552 tmpreg = 0x3b; /* 7.3 */
2553 if (opP->reg == ZPC)
2556 else if (opP->reg == 0)
2559 tmpreg = 0x30; /* 6.garbage */
2561 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2564 tmpreg = 0x30 + opP->reg - ZADDR0;
2567 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2569 siz1 = opP->disp.size;
2570 if (opP->mode == POST || opP->mode == PRE)
2571 siz2 = opP->odisp.size;
2575 /* Index register stuff. */
2576 if (opP->index.reg != 0
2577 && opP->index.reg >= DATA
2578 && opP->index.reg <= ADDR7)
2580 nextword |= (opP->index.reg - DATA) << 12;
2582 if (opP->index.size == SIZE_LONG
2583 || (opP->index.size == SIZE_UNSPEC
2584 && m68k_index_width_default == SIZE_LONG))
2587 if ((opP->index.scale != 1
2588 && cpu_of_arch (current_architecture) < m68020)
2589 || (opP->index.scale == 8
2590 && (arch_coldfire_p (current_architecture)
2591 && !arch_coldfire_fpu (current_architecture))))
2594 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2597 if (arch_coldfire_p (current_architecture)
2598 && opP->index.size == SIZE_WORD)
2599 opP->error = _("invalid index size for coldfire");
2601 switch (opP->index.scale)
2618 GET US OUT OF HERE! */
2620 /* Must be INDEX, with an index register. Address
2621 register cannot be ZERO-PC, and either :b was
2622 forced, or we know it will fit. For a 68000 or
2623 68010, force this mode anyways, because the
2624 larger modes aren't supported. */
2625 if (opP->mode == BASE
2626 && ((opP->reg >= ADDR0
2627 && opP->reg <= ADDR7)
2630 if (siz1 == SIZE_BYTE
2631 || cpu_of_arch (current_architecture) < m68020
2632 || arch_coldfire_p (current_architecture)
2633 || (siz1 == SIZE_UNSPEC
2634 && ! isvar (&opP->disp)
2635 && issbyte (baseo)))
2637 nextword += baseo & 0xff;
2639 if (isvar (&opP->disp))
2641 /* Do a byte relocation. If it doesn't
2642 fit (possible on m68000) let the
2643 fixup processing complain later. */
2645 add_fix ('B', &opP->disp, 1, 1);
2647 add_fix ('B', &opP->disp, 0, 0);
2649 else if (siz1 != SIZE_BYTE)
2651 if (siz1 != SIZE_UNSPEC)
2652 as_warn (_("Forcing byte displacement"));
2653 if (! issbyte (baseo))
2654 opP->error = _("byte displacement out of range");
2659 else if (siz1 == SIZE_UNSPEC
2661 && isvar (&opP->disp)
2662 && subs (&opP->disp) == NULL
2664 /* If the displacement needs pic
2665 relocation it cannot be relaxed. */
2666 && opP->disp.pic_reloc == pic_none
2670 /* The code in md_convert_frag_1 needs to be
2671 able to adjust nextword. Call frag_grow
2672 to ensure that we have enough space in
2673 the frag obstack to make all the bytes
2676 nextword += baseo & 0xff;
2678 add_frag (adds (&opP->disp),
2679 SEXT (offs (&opP->disp)),
2680 TAB (PCINDEX, SZ_UNDEF));
2688 nextword |= 0x40; /* No index reg. */
2689 if (opP->index.reg >= ZDATA0
2690 && opP->index.reg <= ZDATA7)
2691 nextword |= (opP->index.reg - ZDATA0) << 12;
2692 else if (opP->index.reg >= ZADDR0
2693 || opP->index.reg <= ZADDR7)
2694 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2697 /* It isn't simple. */
2699 if (cpu_of_arch (current_architecture) < m68020
2700 || arch_coldfire_p (current_architecture))
2702 _("invalid operand mode for this architecture; needs 68020 or higher");
2705 /* If the guy specified a width, we assume that it is
2706 wide enough. Maybe it isn't. If so, we lose. */
2710 if (isvar (&opP->disp)
2712 : ! issword (baseo))
2717 else if (! isvar (&opP->disp) && baseo == 0)
2726 as_warn (_(":b not permitted; defaulting to :w"));
2736 /* Figure out inner displacement stuff. */
2737 if (opP->mode == POST || opP->mode == PRE)
2739 if (cpu_of_arch (current_architecture) & cpu32)
2740 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2744 if (isvar (&opP->odisp)
2746 : ! issword (outro))
2751 else if (! isvar (&opP->odisp) && outro == 0)
2760 as_warn (_(":b not permitted; defaulting to :w"));
2769 if (opP->mode == POST
2770 && (nextword & 0x40) == 0)
2775 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2777 if (opP->reg == PC || opP->reg == ZPC)
2778 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2780 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2782 if (siz1 == SIZE_LONG)
2783 addword (baseo >> 16);
2784 if (siz1 != SIZE_UNSPEC)
2787 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2788 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2789 if (siz2 == SIZE_LONG)
2790 addword (outro >> 16);
2791 if (siz2 != SIZE_UNSPEC)
2797 nextword = get_num (&opP->disp, 90);
2798 switch (opP->disp.size)
2803 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2805 tmpreg = 0x38; /* 7.0 */
2809 if (isvar (&opP->disp)
2810 && !subs (&opP->disp)
2811 && adds (&opP->disp)
2813 /* If the displacement needs pic relocation it
2814 cannot be relaxed. */
2815 && opP->disp.pic_reloc == pic_none
2818 && !strchr ("~%&$?", s[0]))
2820 tmpreg = 0x3A; /* 7.2 */
2821 add_frag (adds (&opP->disp),
2822 SEXT (offs (&opP->disp)),
2823 TAB (ABSTOPCREL, SZ_UNDEF));
2826 /* Fall through into long. */
2828 if (isvar (&opP->disp))
2829 add_fix ('l', &opP->disp, 0, 0);
2831 tmpreg = 0x39;/* 7.1 mode */
2832 addword (nextword >> 16);
2837 as_bad (_("unsupported byte value; use a different suffix"));
2841 if (isvar (&opP->disp))
2842 add_fix ('w', &opP->disp, 0, 0);
2844 tmpreg = 0x38;/* 7.0 mode */
2852 as_bad (_("unknown/incorrect operand"));
2856 /* If s[0] is '4', then this is for the mac instructions
2857 that can have a trailing_ampersand set. If so, set 0x100
2858 bit on tmpreg so install_gen_operand can check for it and
2859 set the appropriate bit (word2, bit 5). */
2862 if (opP->trailing_ampersand)
2865 install_gen_operand (s[1], tmpreg);
2871 { /* JF: I hate floating point! */
2886 tmpreg = get_num (&opP->disp, tmpreg);
2887 if (isvar (&opP->disp))
2888 add_fix (s[1], &opP->disp, 0, 0);
2891 case 'b': /* Danger: These do no check for
2892 certain types of overflow.
2894 if (!isbyte (tmpreg))
2895 opP->error = _("out of range");
2896 insop (tmpreg, opcode);
2897 if (isvar (&opP->disp))
2898 the_ins.reloc[the_ins.nrel - 1].n =
2899 (opcode->m_codenum) * 2 + 1;
2902 if (!issbyte (tmpreg))
2903 opP->error = _("out of range");
2904 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2905 if (isvar (&opP->disp))
2906 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2909 if (!isword (tmpreg))
2910 opP->error = _("out of range");
2911 insop (tmpreg, opcode);
2912 if (isvar (&opP->disp))
2913 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2916 if (!issword (tmpreg))
2917 opP->error = _("out of range");
2918 insop (tmpreg, opcode);
2919 if (isvar (&opP->disp))
2920 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2923 /* Because of the way insop works, we put these two out
2925 insop (tmpreg, opcode);
2926 insop (tmpreg >> 16, opcode);
2927 if (isvar (&opP->disp))
2928 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2935 install_operand (s[1], tmpreg);
2946 install_operand (s[1], opP->reg - ADDR);
2950 tmpreg = get_num (&opP->disp, 90);
2955 add_fix ('B', &opP->disp, 1, -1);
2958 add_fix ('w', &opP->disp, 1, 0);
2963 the_ins.opcode[0] |= 0xff;
2964 add_fix ('l', &opP->disp, 1, 0);
2968 case 'g': /* Conditional branch */
2969 have_disp = HAVE_LONG_CALL (current_architecture);
2972 case 'b': /* Unconditional branch */
2973 have_disp = HAVE_LONG_BRANCH (current_architecture);
2974 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2977 case 's': /* Unconditional subroutine */
2978 have_disp = HAVE_LONG_CALL (current_architecture);
2981 if (subs (&opP->disp) /* We can't relax it. */
2983 /* If the displacement needs pic relocation it cannot be
2985 || opP->disp.pic_reloc != pic_none
2990 as_warn (_("Can't use long branches on this architecture"));
2994 /* This could either be a symbol, or an absolute
2995 address. If it's an absolute address, turn it into
2996 an absolute jump right here and keep it out of the
2998 if (adds (&opP->disp) == 0)
3000 if (the_ins.opcode[0] == 0x6000) /* jbra */
3001 the_ins.opcode[0] = 0x4EF9;
3002 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3003 the_ins.opcode[0] = 0x4EB9;
3006 the_ins.opcode[0] ^= 0x0100;
3007 the_ins.opcode[0] |= 0x0006;
3010 add_fix ('l', &opP->disp, 0, 0);
3016 /* Now we know it's going into the relaxer. Now figure
3017 out which mode. We try in this order of preference:
3018 long branch, absolute jump, byte/word branches only. */
3020 add_frag (adds (&opP->disp),
3021 SEXT (offs (&opP->disp)),
3022 TAB (BRANCHBWL, SZ_UNDEF));
3023 else if (! flag_keep_pcrel)
3025 if ((the_ins.opcode[0] == 0x6000)
3026 || (the_ins.opcode[0] == 0x6100))
3027 add_frag (adds (&opP->disp),
3028 SEXT (offs (&opP->disp)),
3029 TAB (BRABSJUNC, SZ_UNDEF));
3031 add_frag (adds (&opP->disp),
3032 SEXT (offs (&opP->disp)),
3033 TAB (BRABSJCOND, SZ_UNDEF));
3036 add_frag (adds (&opP->disp),
3037 SEXT (offs (&opP->disp)),
3038 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3039 : TAB (BRANCHBW, SZ_UNDEF)));
3042 if (isvar (&opP->disp))
3044 /* Check for DBcc instructions. We can relax them,
3045 but only if we have long branches and/or absolute
3047 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3048 && (HAVE_LONG_BRANCH (current_architecture)
3049 || ! flag_keep_pcrel))
3051 if (HAVE_LONG_BRANCH (current_architecture))
3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
3054 TAB (DBCCLBR, SZ_UNDEF));
3056 add_frag (adds (&opP->disp),
3057 SEXT (offs (&opP->disp)),
3058 TAB (DBCCABSJ, SZ_UNDEF));
3061 add_fix ('w', &opP->disp, 1, 0);
3065 case 'C': /* Fixed size LONG coproc branches. */
3066 add_fix ('l', &opP->disp, 1, 0);
3070 case 'c': /* Var size Coprocesssor branches. */
3071 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3073 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3074 add_fix ('l', &opP->disp, 1, 0);
3079 add_frag (adds (&opP->disp),
3080 SEXT (offs (&opP->disp)),
3081 TAB (FBRANCH, SZ_UNDEF));
3088 case 'C': /* Ignore it. */
3091 case 'd': /* JF this is a kludge. */
3092 install_operand ('s', opP->reg - ADDR);
3093 tmpreg = get_num (&opP->disp, 90);
3094 if (!issword (tmpreg))
3096 as_warn (_("Expression out of range, using 0"));
3103 install_operand (s[1], opP->reg - DATA);
3106 case 'e': /* EMAC ACCx, reg/reg. */
3107 install_operand (s[1], opP->reg - ACC);
3110 case 'E': /* Ignore it. */
3114 install_operand (s[1], opP->reg - FP0);
3117 case 'g': /* EMAC ACCEXTx. */
3118 install_operand (s[1], opP->reg - ACCEXT01);
3121 case 'G': /* Ignore it. */
3126 tmpreg = opP->reg - COP0;
3127 install_operand (s[1], tmpreg);
3130 case 'i': /* MAC/EMAC scale factor. */
3131 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3134 case 'J': /* JF foo. */
3274 install_operand (s[1], tmpreg);
3278 tmpreg = get_num (&opP->disp, 55);
3279 install_operand (s[1], tmpreg & 0x7f);
3286 if (tmpreg & 0x7FF0000)
3287 as_bad (_("Floating point register in register list"));
3288 insop (reverse_16_bits (tmpreg), opcode);
3292 if (tmpreg & 0x700FFFF)
3293 as_bad (_("Wrong register in floating-point reglist"));
3294 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3302 if (tmpreg & 0x7FF0000)
3303 as_bad (_("Floating point register in register list"));
3304 insop (tmpreg, opcode);
3306 else if (s[1] == '8')
3308 if (tmpreg & 0x0FFFFFF)
3309 as_bad (_("incorrect register in reglist"));
3310 install_operand (s[1], tmpreg >> 24);
3314 if (tmpreg & 0x700FFFF)
3315 as_bad (_("wrong register in floating-point reglist"));
3317 install_operand (s[1], tmpreg >> 16);
3322 install_operand (s[1], get_num (&opP->disp, 60));
3326 tmpreg = ((opP->mode == DREG)
3327 ? 0x20 + (int) (opP->reg - DATA)
3328 : (get_num (&opP->disp, 40) & 0x1F));
3329 install_operand (s[1], tmpreg);
3333 tmpreg = get_num (&opP->disp, 10);
3336 install_operand (s[1], tmpreg);
3340 /* This depends on the fact that ADDR registers are eight
3341 more than their corresponding DATA regs, so the result
3342 will have the ADDR_REG bit set. */
3343 install_operand (s[1], opP->reg - DATA);
3347 if (opP->mode == AINDR)
3348 install_operand (s[1], opP->reg - DATA);
3350 install_operand (s[1], opP->index.reg - DATA);
3354 if (opP->reg == FPI)
3356 else if (opP->reg == FPS)
3358 else if (opP->reg == FPC)
3362 install_operand (s[1], tmpreg);
3365 case 'S': /* Ignore it. */
3369 install_operand (s[1], get_num (&opP->disp, 30));
3372 case 'U': /* Ignore it. */
3391 as_fatal (_("failed sanity check"));
3392 } /* switch on cache token. */
3393 install_operand (s[1], tmpreg);
3396 /* JF: These are out of order, I fear. */
3409 install_operand (s[1], tmpreg);
3435 install_operand (s[1], tmpreg);
3439 if (opP->reg == VAL)
3458 install_operand (s[1], tmpreg);
3472 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3483 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3489 install_operand (s[1], tmpreg);
3492 know (opP->reg == PSR);
3495 know (opP->reg == PCSR);
3510 install_operand (s[1], tmpreg);
3513 tmpreg = get_num (&opP->disp, 20);
3514 install_operand (s[1], tmpreg);
3516 case '_': /* used only for move16 absolute 32-bit address. */
3517 if (isvar (&opP->disp))
3518 add_fix ('l', &opP->disp, 0, 0);
3519 tmpreg = get_num (&opP->disp, 90);
3520 addword (tmpreg >> 16);
3521 addword (tmpreg & 0xFFFF);
3524 install_operand (s[1], opP->reg - DATA0L);
3525 opP->reg -= (DATA0L);
3526 opP->reg &= 0x0F; /* remove upper/lower bit. */
3529 tmpreg = get_num (&opP->disp, 80);
3532 install_operand (s[1], tmpreg);
3535 tmpreg = get_num (&opP->disp, 10);
3536 install_operand (s[1], tmpreg - 1);
3539 tmpreg = get_num (&opP->disp, 65);
3540 install_operand (s[1], tmpreg);
3547 /* By the time whe get here (FINALLY) the_ins contains the complete
3548 instruction, ready to be emitted. . . */
3552 reverse_16_bits (int in)
3557 static int mask[16] =
3559 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3560 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3562 for (n = 0; n < 16; n++)
3565 out |= mask[15 - n];
3568 } /* reverse_16_bits() */
3571 reverse_8_bits (int in)
3576 static int mask[8] =
3578 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3581 for (n = 0; n < 8; n++)
3587 } /* reverse_8_bits() */
3589 /* Cause an extra frag to be generated here, inserting up to
3590 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3591 generated; its primary type is rs_machine_dependent.
3593 The TYPE parameter is also used by md_convert_frag_1 and
3594 md_estimate_size_before_relax. The appropriate type of fixup will
3595 be emitted by md_convert_frag_1.
3597 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3599 install_operand (int mode, int val)
3604 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3607 the_ins.opcode[0] |= val << 9;
3610 the_ins.opcode[1] |= val << 9;
3613 the_ins.opcode[1] |= val << 12;
3616 the_ins.opcode[1] |= val << 6;
3619 the_ins.opcode[1] |= val;
3622 the_ins.opcode[2] |= val << 12;
3625 the_ins.opcode[2] |= val << 6;
3628 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3629 three words long! */
3631 the_ins.opcode[2] |= val;
3634 the_ins.opcode[1] |= val << 7;
3637 the_ins.opcode[1] |= val << 10;
3641 the_ins.opcode[1] |= val << 5;
3646 the_ins.opcode[1] |= (val << 10) | (val << 7);
3649 the_ins.opcode[1] |= (val << 12) | val;
3652 the_ins.opcode[0] |= val = 0xff;
3655 the_ins.opcode[0] |= val << 9;
3658 the_ins.opcode[1] |= val;
3661 the_ins.opcode[1] |= val;
3662 the_ins.numo++; /* What a hack. */
3665 the_ins.opcode[1] |= val << 4;
3673 the_ins.opcode[0] |= (val << 6);
3676 the_ins.opcode[1] = (val >> 16);
3677 the_ins.opcode[2] = val & 0xffff;
3680 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3681 the_ins.opcode[0] |= ((val & 0x7) << 9);
3682 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3684 case 'n': /* MAC/EMAC Rx on !load. */
3685 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3686 the_ins.opcode[0] |= ((val & 0x7) << 9);
3687 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3689 case 'o': /* MAC/EMAC Rx on load. */
3690 the_ins.opcode[1] |= val << 12;
3691 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3693 case 'M': /* MAC/EMAC Ry on !load. */
3694 the_ins.opcode[0] |= (val & 0xF);
3695 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3697 case 'N': /* MAC/EMAC Ry on load. */
3698 the_ins.opcode[1] |= (val & 0xF);
3699 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3702 the_ins.opcode[1] |= ((val != 1) << 10);
3705 the_ins.opcode[0] |= ((val & 0x3) << 9);
3708 the_ins.opcode[0] |= ((val & 0x3) << 0);
3710 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3711 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3712 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3714 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3715 the_ins.opcode[0] |= ((val & 0x1) << 7);
3716 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3719 the_ins.opcode[1] |= ((val & 0x3) << 9);
3722 the_ins.opcode[0] |= (val & 0x1) <<10;
3726 as_fatal (_("failed sanity check."));
3731 install_gen_operand (int mode, int val)
3735 case '/': /* Special for mask loads for mac/msac insns with
3736 possible mask; trailing_ampersend set in bit 8. */
3737 the_ins.opcode[0] |= (val & 0x3f);
3738 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3741 the_ins.opcode[0] |= val;
3744 /* This is a kludge!!! */
3745 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3754 the_ins.opcode[0] |= val;
3756 /* more stuff goes here. */
3758 as_fatal (_("failed sanity check."));
3762 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3763 then deal with the bitfield hack. */
3766 crack_operand (char *str, struct m68k_op *opP)
3768 register int parens;
3770 register char *beg_str;
3778 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3784 else if (*str == ')')
3788 opP->error = _("Extra )");
3794 if (flag_mri && *str == '\'')
3795 inquote = ! inquote;
3797 if (!*str && parens)
3799 opP->error = _("Missing )");
3804 if (m68k_ip_op (beg_str, opP) != 0)
3811 c = *++str; /* JF bitfield hack. */
3816 as_bad (_("Missing operand"));
3819 /* Detect MRI REG symbols and convert them to REGLSTs. */
3820 if (opP->mode == CONTROL && (int)opP->reg < 0)
3823 opP->mask = ~(int)opP->reg;
3830 /* This is the guts of the machine-dependent assembler. STR points to a
3831 machine dependent instruction. This function is supposed to emit
3832 the frags/bytes it assembles to.
3836 insert_reg (const char *regname, int regnum)
3841 #ifdef REGISTER_PREFIX
3842 if (!flag_reg_prefix_optional)
3844 buf[0] = REGISTER_PREFIX;
3845 strcpy (buf + 1, regname);
3850 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3851 &zero_address_frag));
3853 for (i = 0; regname[i]; i++)
3854 buf[i] = TOUPPER (regname[i]);
3857 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3858 &zero_address_frag));
3867 static const struct init_entry init_table[] =
3927 { "accext01", ACCEXT01 },
3928 { "accext23", ACCEXT23 },
3932 /* Control registers. */
3933 { "sfc", SFC }, /* Source Function Code. */
3935 { "dfc", DFC }, /* Destination Function Code. */
3937 { "cacr", CACR }, /* Cache Control Register. */
3938 { "caar", CAAR }, /* Cache Address Register. */
3940 { "usp", USP }, /* User Stack Pointer. */
3941 { "vbr", VBR }, /* Vector Base Register. */
3942 { "msp", MSP }, /* Master Stack Pointer. */
3943 { "isp", ISP }, /* Interrupt Stack Pointer. */
3945 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3946 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3947 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3948 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3950 /* 68ec040 versions of same */
3951 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3952 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3953 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3954 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3956 /* Coldfire versions of same. The ColdFire programmer's reference
3957 manual indicated that the order is 2,3,0,1, but Ken Rose
3958 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3959 { "acr0", ACR0 }, /* Access Control Unit 0. */
3960 { "acr1", ACR1 }, /* Access Control Unit 1. */
3961 { "acr2", ACR2 }, /* Access Control Unit 2. */
3962 { "acr3", ACR3 }, /* Access Control Unit 3. */
3964 { "tc", TC }, /* MMU Translation Control Register. */
3968 { "mmusr", MMUSR }, /* MMU Status Register. */
3969 { "srp", SRP }, /* User Root Pointer. */
3970 { "urp", URP }, /* Supervisor Root Pointer. */
3973 { "mmubar", MMUBAR },
3976 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3977 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3978 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3979 { "mbar", MBAR }, /* Module Base Address Register. */
3981 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3982 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3983 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3984 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3985 { "mpcr", MPCR }, /* mcfv4e registers. */
3986 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3987 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3988 { "asid", TC }, /* mcfv4e registers. */
3989 { "mmubar", BUSCR }, /* mcfv4e registers. */
3990 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3991 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3992 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3993 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3994 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3995 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3996 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3997 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3998 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3999 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4000 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4001 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4003 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4004 { "rambar", RAMBAR }, /* mcf528x registers. */
4006 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4008 { "cac", CAC }, /* fido registers. */
4009 { "mbb", MBB }, /* fido registers. */
4010 /* End of control registers. */
4044 /* 68ec030 versions of same. */
4047 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4050 /* Suppressed data and address registers. */
4068 /* Upper and lower data and address registers, used by macw and msacw. */
4109 init_regtable (void)
4112 for (i = 0; init_table[i].name; i++)
4113 insert_reg (init_table[i].name, init_table[i].number);
4117 md_assemble (char *str)
4124 int shorts_this_frag;
4127 if (!selected_cpu && !selected_arch)
4129 /* We've not selected an architecture yet. Set the default
4130 now. We do this lazily so that an initial .cpu or .arch directive
4132 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4133 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4138 /* In MRI mode, the instruction and operands are separated by a
4139 space. Anything following the operands is a comment. The label
4140 has already been removed. */
4148 for (s = str; *s != '\0'; s++)
4150 if ((*s == ' ' || *s == '\t') && ! inquote)
4168 inquote = ! inquote;
4173 memset (&the_ins, '\0', sizeof (the_ins));
4178 for (n = 0; n < the_ins.numargs; n++)
4179 if (the_ins.operands[n].error)
4181 er = the_ins.operands[n].error;
4187 as_bad (_("%s -- statement `%s' ignored"), er, str);
4191 /* If there is a current label, record that it marks an instruction. */
4192 if (current_label != NULL)
4194 current_label->text = 1;
4195 current_label = NULL;
4199 /* Tie dwarf2 debug info to the address at the start of the insn. */
4200 dwarf2_emit_insn (0);
4203 if (the_ins.nfrag == 0)
4205 /* No frag hacking involved; just put it out. */
4206 toP = frag_more (2 * the_ins.numo);
4207 fromP = &the_ins.opcode[0];
4208 for (m = the_ins.numo; m; --m)
4210 md_number_to_chars (toP, (long) (*fromP), 2);
4214 /* Put out symbol-dependent info. */
4215 for (m = 0; m < the_ins.nrel; m++)
4217 switch (the_ins.reloc[m].wid)
4236 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4237 the_ins.reloc[m].wid);
4240 fixP = fix_new_exp (frag_now,
4241 ((toP - frag_now->fr_literal)
4242 - the_ins.numo * 2 + the_ins.reloc[m].n),
4244 &the_ins.reloc[m].exp,
4245 the_ins.reloc[m].pcrel,
4246 get_reloc_code (n, the_ins.reloc[m].pcrel,
4247 the_ins.reloc[m].pic_reloc));
4248 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4249 if (the_ins.reloc[m].wid == 'B')
4250 fixP->fx_signed = 1;
4255 /* There's some frag hacking. */
4257 /* Calculate the max frag size. */
4260 wid = 2 * the_ins.fragb[0].fragoff;
4261 for (n = 1; n < the_ins.nfrag; n++)
4262 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4263 /* frag_var part. */
4264 wid += FRAG_VAR_SIZE;
4265 /* Make sure the whole insn fits in one chunk, in particular that
4266 the var part is attached, as we access one byte before the
4267 variable frag for byte branches. */
4271 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4276 wid = 2 * the_ins.fragb[n].fragoff;
4278 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4279 toP = frag_more (wid);
4281 shorts_this_frag = 0;
4282 for (m = wid / 2; m; --m)
4284 md_number_to_chars (toP, (long) (*fromP), 2);
4289 for (m = 0; m < the_ins.nrel; m++)
4291 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4293 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4296 wid = the_ins.reloc[m].wid;
4299 the_ins.reloc[m].wid = 0;
4300 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4302 fixP = fix_new_exp (frag_now,
4303 ((toP - frag_now->fr_literal)
4304 - the_ins.numo * 2 + the_ins.reloc[m].n),
4306 &the_ins.reloc[m].exp,
4307 the_ins.reloc[m].pcrel,
4308 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4309 the_ins.reloc[m].pic_reloc));
4310 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4312 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4313 (relax_substateT) (the_ins.fragb[n].fragty),
4314 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4316 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4317 shorts_this_frag = 0;
4320 toP = frag_more (n * 2);
4323 md_number_to_chars (toP, (long) (*fromP), 2);
4329 for (m = 0; m < the_ins.nrel; m++)
4333 wid = the_ins.reloc[m].wid;
4336 the_ins.reloc[m].wid = 0;
4337 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4339 fixP = fix_new_exp (frag_now,
4340 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4341 - shorts_this_frag * 2),
4343 &the_ins.reloc[m].exp,
4344 the_ins.reloc[m].pcrel,
4345 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4346 the_ins.reloc[m].pic_reloc));
4347 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4351 /* Comparison function used by qsort to rank the opcode entries by name. */
4354 m68k_compare_opcode (const void * v1, const void * v2)
4356 struct m68k_opcode * op1, * op2;
4362 op1 = *(struct m68k_opcode **) v1;
4363 op2 = *(struct m68k_opcode **) v2;
4365 /* Compare the two names. If different, return the comparison.
4366 If the same, return the order they are in the opcode table. */
4367 ret = strcmp (op1->name, op2->name);
4378 const struct m68k_opcode *ins;
4379 struct m68k_incant *hack, *slak;
4380 const char *retval = 0; /* Empty string, or error msg text. */
4383 /* Set up hash tables with 68000 instructions.
4384 similar to what the vax assembler does. */
4385 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4386 a copy of it at runtime, adding in the information we want but isn't
4387 there. I think it'd be better to have an awk script hack the table
4388 at compile time. Or even just xstr the table and use it as-is. But
4389 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4394 flag_reg_prefix_optional = 1;
4396 if (! m68k_rel32_from_cmdline)
4400 /* First sort the opcode table into alphabetical order to seperate
4401 the order that the assembler wants to see the opcodes from the
4402 order that the disassembler wants to see them. */
4403 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4404 if (!m68k_sorted_opcodes)
4405 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4406 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4408 for (i = m68k_numopcodes; i--;)
4409 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4411 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4412 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4414 op_hash = hash_new ();
4416 obstack_begin (&robyn, 4000);
4417 for (i = 0; i < m68k_numopcodes; i++)
4419 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4422 ins = m68k_sorted_opcodes[i];
4424 /* We must enter all insns into the table, because .arch and
4425 .cpu directives can change things. */
4426 slak->m_operands = ins->args;
4427 slak->m_arch = ins->arch;
4428 slak->m_opcode = ins->opcode;
4430 /* In most cases we can determine the number of opcode words
4431 by checking the second word of the mask. Unfortunately
4432 some instructions have 2 opcode words, but no fixed bits
4433 in the second word. A leading dot in the operands
4434 string also indicates 2 opcodes. */
4435 if (*slak->m_operands == '.')
4438 slak->m_codenum = 2;
4440 else if (ins->match & 0xffffL)
4441 slak->m_codenum = 2;
4443 slak->m_codenum = 1;
4444 slak->m_opnum = strlen (slak->m_operands) / 2;
4446 if (i + 1 != m68k_numopcodes
4447 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4449 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4454 slak = slak->m_next;
4458 retval = hash_insert (op_hash, ins->name, (char *) hack);
4460 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4463 for (i = 0; i < m68k_numaliases; i++)
4465 const char *name = m68k_opcode_aliases[i].primary;
4466 const char *alias = m68k_opcode_aliases[i].alias;
4467 PTR val = hash_find (op_hash, name);
4470 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4471 retval = hash_insert (op_hash, alias, val);
4473 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4476 /* In MRI mode, all unsized branches are variable sized. Normally,
4477 they are word sized. */
4480 static struct m68k_opcode_alias mri_aliases[] =
4501 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4504 const char *name = mri_aliases[i].primary;
4505 const char *alias = mri_aliases[i].alias;
4506 PTR val = hash_find (op_hash, name);
4509 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4510 retval = hash_jam (op_hash, alias, val);
4512 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4516 for (i = 0; i < (int) sizeof (notend_table); i++)
4518 notend_table[i] = 0;
4519 alt_notend_table[i] = 0;
4522 notend_table[','] = 1;
4523 notend_table['{'] = 1;
4524 notend_table['}'] = 1;
4525 alt_notend_table['a'] = 1;
4526 alt_notend_table['A'] = 1;
4527 alt_notend_table['d'] = 1;
4528 alt_notend_table['D'] = 1;
4529 alt_notend_table['#'] = 1;
4530 alt_notend_table['&'] = 1;
4531 alt_notend_table['f'] = 1;
4532 alt_notend_table['F'] = 1;
4533 #ifdef REGISTER_PREFIX
4534 alt_notend_table[REGISTER_PREFIX] = 1;
4537 /* We need to put '(' in alt_notend_table to handle
4538 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4539 alt_notend_table['('] = 1;
4541 /* We need to put '@' in alt_notend_table to handle
4542 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4543 alt_notend_table['@'] = 1;
4545 /* We need to put digits in alt_notend_table to handle
4546 bfextu %d0{24:1},%d0 */
4547 alt_notend_table['0'] = 1;
4548 alt_notend_table['1'] = 1;
4549 alt_notend_table['2'] = 1;
4550 alt_notend_table['3'] = 1;
4551 alt_notend_table['4'] = 1;
4552 alt_notend_table['5'] = 1;
4553 alt_notend_table['6'] = 1;
4554 alt_notend_table['7'] = 1;
4555 alt_notend_table['8'] = 1;
4556 alt_notend_table['9'] = 1;
4558 #ifndef MIT_SYNTAX_ONLY
4559 /* Insert pseudo ops, these have to go into the opcode table since
4560 gas expects pseudo ops to start with a dot. */
4564 while (mote_pseudo_table[n].poc_name)
4566 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4567 hash_insert (op_hash,
4568 mote_pseudo_table[n].poc_name, (char *) hack);
4569 hack->m_operands = 0;
4579 record_alignment (text_section, 2);
4580 record_alignment (data_section, 2);
4581 record_alignment (bss_section, 2);
4586 /* This is called when a label is defined. */
4589 m68k_frob_label (symbolS *sym)
4591 struct label_line *n;
4593 n = (struct label_line *) xmalloc (sizeof *n);
4596 as_where (&n->file, &n->line);
4602 dwarf2_emit_label (sym);
4606 /* This is called when a value that is not an instruction is emitted. */
4609 m68k_flush_pending_output (void)
4611 current_label = NULL;
4614 /* This is called at the end of the assembly, when the final value of
4615 the label is known. We warn if this is a text symbol aligned at an
4619 m68k_frob_symbol (symbolS *sym)
4621 if (S_GET_SEGMENT (sym) == reg_section
4622 && (int) S_GET_VALUE (sym) < 0)
4624 S_SET_SEGMENT (sym, absolute_section);
4625 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4627 else if ((S_GET_VALUE (sym) & 1) != 0)
4629 struct label_line *l;
4631 for (l = labels; l != NULL; l = l->next)
4633 if (l->label == sym)
4636 as_warn_where (l->file, l->line,
4637 _("text label `%s' aligned to odd boundary"),
4645 /* This is called if we go in or out of MRI mode because of the .mri
4649 m68k_mri_mode_change (int on)
4653 if (! flag_reg_prefix_optional)
4655 flag_reg_prefix_optional = 1;
4656 #ifdef REGISTER_PREFIX
4661 if (! m68k_rel32_from_cmdline)
4666 if (! reg_prefix_optional_seen)
4668 #ifdef REGISTER_PREFIX_OPTIONAL
4669 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4671 flag_reg_prefix_optional = 0;
4673 #ifdef REGISTER_PREFIX
4678 if (! m68k_rel32_from_cmdline)
4683 /* Equal to MAX_PRECISION in atof-ieee.c. */
4684 #define MAX_LITTLENUMS 6
4686 /* Turn a string in input_line_pointer into a floating point constant
4687 of type TYPE, and store the appropriate bytes in *LITP. The number
4688 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4689 returned, or NULL on OK. */
4692 md_atof (int type, char *litP, int *sizeP)
4695 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4696 LITTLENUM_TYPE *wordP;
4727 return _("Bad call to MD_ATOF()");
4729 t = atof_ieee (input_line_pointer, type, words);
4731 input_line_pointer = t;
4733 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4734 for (wordP = words; prec--;)
4736 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4737 litP += sizeof (LITTLENUM_TYPE);
4743 md_number_to_chars (char *buf, valueT val, int n)
4745 number_to_chars_bigendian (buf, val, n);
4749 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4751 offsetT val = *valP;
4752 addressT upper_limit;
4753 offsetT lower_limit;
4755 /* This is unnecessary but it convinces the native rs6000 compiler
4756 to generate the code we want. */
4757 char *buf = fixP->fx_frag->fr_literal;
4758 buf += fixP->fx_where;
4759 /* End ibm compiler workaround. */
4763 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4769 memset (buf, 0, fixP->fx_size);
4770 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4772 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4773 && !S_IS_DEFINED (fixP->fx_addsy)
4774 && !S_IS_WEAK (fixP->fx_addsy))
4775 S_SET_WEAK (fixP->fx_addsy);
4778 #elif defined(OBJ_AOUT)
4779 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4780 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4782 memset (buf, 0, fixP->fx_size);
4783 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4788 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4789 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4792 switch (fixP->fx_size)
4794 /* The cast to offsetT below are necessary to make code
4795 correct for machines where ints are smaller than offsetT. */
4799 lower_limit = - (offsetT) 0x80;
4802 *buf++ = (val >> 8);
4804 upper_limit = 0x7fff;
4805 lower_limit = - (offsetT) 0x8000;
4808 *buf++ = (val >> 24);
4809 *buf++ = (val >> 16);
4810 *buf++ = (val >> 8);
4812 upper_limit = 0x7fffffff;
4813 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4816 BAD_CASE (fixP->fx_size);
4819 /* Fix up a negative reloc. */
4820 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4822 fixP->fx_addsy = fixP->fx_subsy;
4823 fixP->fx_subsy = NULL;
4827 /* For non-pc-relative values, it's conceivable we might get something
4828 like "0xff" for a byte field. So extend the upper part of the range
4829 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4830 so that we can do any range checking at all. */
4831 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4832 upper_limit = upper_limit * 2 + 1;
4834 if ((addressT) val > upper_limit
4835 && (val > 0 || val < lower_limit))
4836 as_bad_where (fixP->fx_file, fixP->fx_line,
4837 _("value %ld out of range"), (long)val);
4839 /* A one byte PC-relative reloc means a short branch. We can't use
4840 a short branch with a value of 0 or -1, because those indicate
4841 different opcodes (branches with longer offsets). fixup_segment
4842 in write.c may have clobbered fx_pcrel, so we need to examine the
4845 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4846 && fixP->fx_size == 1
4847 && (fixP->fx_addsy == NULL
4848 || S_IS_DEFINED (fixP->fx_addsy))
4849 && (val == 0 || val == -1))
4850 as_bad_where (fixP->fx_file, fixP->fx_line,
4851 _("invalid byte branch offset"));
4854 /* *fragP has been relaxed to its final size, and now needs to have
4855 the bytes inside it modified to conform to the new size There is UGLY
4859 md_convert_frag_1 (fragS *fragP)
4864 /* Address in object code of the displacement. */
4865 register int object_address = fragP->fr_fix + fragP->fr_address;
4867 /* Address in gas core of the place to store the displacement. */
4868 /* This convinces the native rs6000 compiler to generate the code we
4870 register char *buffer_address = fragP->fr_literal;
4871 buffer_address += fragP->fr_fix;
4872 /* End ibm compiler workaround. */
4874 /* The displacement of the address, from current location. */
4875 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4876 disp = (disp + fragP->fr_offset) - object_address;
4878 switch (fragP->fr_subtype)
4880 case TAB (BRANCHBWL, BYTE):
4881 case TAB (BRABSJUNC, BYTE):
4882 case TAB (BRABSJCOND, BYTE):
4883 case TAB (BRANCHBW, BYTE):
4884 case TAB (BRANCHBWPL, BYTE):
4885 know (issbyte (disp));
4887 as_bad_where (fragP->fr_file, fragP->fr_line,
4888 _("short branch with zero offset: use :w"));
4889 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4890 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4891 fixP->fx_pcrel_adjust = -1;
4893 case TAB (BRANCHBWL, SHORT):
4894 case TAB (BRABSJUNC, SHORT):
4895 case TAB (BRABSJCOND, SHORT):
4896 case TAB (BRANCHBW, SHORT):
4897 case TAB (BRANCHBWPL, SHORT):
4898 fragP->fr_opcode[1] = 0x00;
4899 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4900 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4903 case TAB (BRANCHBWL, LONG):
4904 fragP->fr_opcode[1] = (char) 0xFF;
4905 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4906 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4909 case TAB (BRANCHBWPL, LONG):
4910 /* Here we are converting an unconditional branch into a pair of
4911 conditional branches, in order to get the range. */
4912 fragP->fr_opcode[0] = 0x66; /* bne */
4913 fragP->fr_opcode[1] = 0xFF;
4914 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4915 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4916 fixP->fx_file = fragP->fr_file;
4917 fixP->fx_line = fragP->fr_line;
4918 fragP->fr_fix += 4; /* Skip first offset */
4919 buffer_address += 4;
4920 *buffer_address++ = 0x67; /* beq */
4921 *buffer_address++ = 0xff;
4922 fragP->fr_fix += 2; /* Skip second branch opcode */
4923 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4924 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4927 case TAB (BRABSJUNC, LONG):
4928 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4930 if (flag_keep_pcrel)
4931 as_bad_where (fragP->fr_file, fragP->fr_line,
4932 _("Conversion of PC relative BSR to absolute JSR"));
4933 fragP->fr_opcode[0] = 0x4E;
4934 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4935 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4936 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4939 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4941 if (flag_keep_pcrel)
4942 as_bad_where (fragP->fr_file, fragP->fr_line,
4943 _("Conversion of PC relative branch to absolute jump"));
4944 fragP->fr_opcode[0] = 0x4E;
4945 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4946 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4947 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4952 /* This cannot happen, because jbsr and jbra are the only two
4953 unconditional branches. */
4957 case TAB (BRABSJCOND, LONG):
4958 if (flag_keep_pcrel)
4959 as_bad_where (fragP->fr_file, fragP->fr_line,
4960 _("Conversion of PC relative conditional branch to absolute jump"));
4962 /* Only Bcc 68000 instructions can come here
4963 Change bcc into b!cc/jmp absl long. */
4964 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4965 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4967 /* JF: these used to be fr_opcode[2,3], but they may be in a
4968 different frag, in which case referring to them is a no-no.
4969 Only fr_opcode[0,1] are guaranteed to work. */
4970 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4971 *buffer_address++ = (char) 0xf9;
4972 fragP->fr_fix += 2; /* Account for jmp instruction. */
4973 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4974 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4977 case TAB (FBRANCH, SHORT):
4978 know ((fragP->fr_opcode[1] & 0x40) == 0);
4979 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4980 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4983 case TAB (FBRANCH, LONG):
4984 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4985 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4986 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4989 case TAB (DBCCLBR, SHORT):
4990 case TAB (DBCCABSJ, SHORT):
4991 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4992 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4995 case TAB (DBCCLBR, LONG):
4996 /* Only DBcc instructions can come here.
4997 Change dbcc into dbcc/bral.
4998 JF: these used to be fr_opcode[2-7], but that's wrong. */
4999 if (flag_keep_pcrel)
5000 as_bad_where (fragP->fr_file, fragP->fr_line,
5001 _("Conversion of DBcc to absolute jump"));
5003 *buffer_address++ = 0x00; /* Branch offset = 4. */
5004 *buffer_address++ = 0x04;
5005 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5006 *buffer_address++ = 0x06;
5007 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5008 *buffer_address++ = (char) 0xff;
5010 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5011 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5012 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5015 case TAB (DBCCABSJ, LONG):
5016 /* Only DBcc instructions can come here.
5017 Change dbcc into dbcc/jmp.
5018 JF: these used to be fr_opcode[2-7], but that's wrong. */
5019 if (flag_keep_pcrel)
5020 as_bad_where (fragP->fr_file, fragP->fr_line,
5021 _("Conversion of PC relative conditional branch to absolute jump"));
5023 *buffer_address++ = 0x00; /* Branch offset = 4. */
5024 *buffer_address++ = 0x04;
5025 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5026 *buffer_address++ = 0x06;
5027 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5028 *buffer_address++ = (char) 0xf9;
5030 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5031 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5032 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5035 case TAB (PCREL1632, SHORT):
5036 fragP->fr_opcode[1] &= ~0x3F;
5037 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5038 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5039 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5042 case TAB (PCREL1632, LONG):
5043 /* Already set to mode 7.3; this indicates: PC indirect with
5044 suppressed index, 32-bit displacement. */
5045 *buffer_address++ = 0x01;
5046 *buffer_address++ = 0x70;
5048 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5049 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5050 fixP->fx_pcrel_adjust = 2;
5053 case TAB (PCINDEX, BYTE):
5054 assert (fragP->fr_fix >= 2);
5055 buffer_address[-2] &= ~1;
5056 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5057 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5058 fixP->fx_pcrel_adjust = 1;
5060 case TAB (PCINDEX, SHORT):
5061 assert (fragP->fr_fix >= 2);
5062 buffer_address[-2] |= 0x1;
5063 buffer_address[-1] = 0x20;
5064 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5065 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5066 fixP->fx_pcrel_adjust = 2;
5069 case TAB (PCINDEX, LONG):
5070 assert (fragP->fr_fix >= 2);
5071 buffer_address[-2] |= 0x1;
5072 buffer_address[-1] = 0x30;
5073 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5074 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5075 fixP->fx_pcrel_adjust = 2;
5078 case TAB (ABSTOPCREL, SHORT):
5079 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5080 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5083 case TAB (ABSTOPCREL, LONG):
5084 if (flag_keep_pcrel)
5085 as_fatal (_("Conversion of PC relative displacement to absolute"));
5086 /* The thing to do here is force it to ABSOLUTE LONG, since
5087 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5088 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5090 fragP->fr_opcode[1] &= ~0x3F;
5091 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5092 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5093 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5099 fixP->fx_file = fragP->fr_file;
5100 fixP->fx_line = fragP->fr_line;
5105 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5106 segT sec ATTRIBUTE_UNUSED,
5109 md_convert_frag_1 (fragP);
5112 /* Force truly undefined symbols to their maximum size, and generally set up
5113 the frag list to be relaxed
5116 md_estimate_size_before_relax (fragS *fragP, segT segment)
5118 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5119 switch (fragP->fr_subtype)
5121 case TAB (BRANCHBWL, SZ_UNDEF):
5122 case TAB (BRANCHBWPL, SZ_UNDEF):
5123 case TAB (BRABSJUNC, SZ_UNDEF):
5124 case TAB (BRABSJCOND, SZ_UNDEF):
5126 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5127 && relaxable_symbol (fragP->fr_symbol))
5129 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5131 else if (flag_short_refs)
5133 /* Symbol is undefined and we want short ref. */
5134 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5138 /* Symbol is still undefined. Make it LONG. */
5139 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5144 case TAB (BRANCHBW, SZ_UNDEF):
5146 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5147 && relaxable_symbol (fragP->fr_symbol))
5149 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5153 /* Symbol is undefined and we don't have long branches. */
5154 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5159 case TAB (FBRANCH, SZ_UNDEF):
5160 case TAB (DBCCLBR, SZ_UNDEF):
5161 case TAB (DBCCABSJ, SZ_UNDEF):
5162 case TAB (PCREL1632, SZ_UNDEF):
5164 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5165 && relaxable_symbol (fragP->fr_symbol))
5168 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5172 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5177 case TAB (PCINDEX, SZ_UNDEF):
5178 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5179 && relaxable_symbol (fragP->fr_symbol)))
5181 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5185 fragP->fr_subtype = TAB (PCINDEX, LONG);
5189 case TAB (ABSTOPCREL, SZ_UNDEF):
5191 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5192 && relaxable_symbol (fragP->fr_symbol)))
5194 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5198 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5207 /* Now that SZ_UNDEF are taken care of, check others. */
5208 switch (fragP->fr_subtype)
5210 case TAB (BRANCHBWL, BYTE):
5211 case TAB (BRABSJUNC, BYTE):
5212 case TAB (BRABSJCOND, BYTE):
5213 case TAB (BRANCHBW, BYTE):
5214 /* We can't do a short jump to the next instruction, so in that
5215 case we force word mode. If the symbol is at the start of a
5216 frag, and it is the next frag with any data in it (usually
5217 this is just the next frag, but assembler listings may
5218 introduce empty frags), we must use word mode. */
5219 if (fragP->fr_symbol)
5223 sym_frag = symbol_get_frag (fragP->fr_symbol);
5224 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5228 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5232 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5239 return md_relax_table[fragP->fr_subtype].rlx_length;
5242 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5243 /* the bit-field entries in the relocation_info struct plays hell
5244 with the byte-order problems of cross-assembly. So as a hack,
5245 I added this mach. dependent ri twiddler. Ugly, but it gets
5247 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5248 are symbolnum, most sig. byte first. Last byte is broken up with
5249 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5250 nibble as nuthin. (on Sun 3 at least) */
5251 /* Translate the internal relocation information into target-specific
5255 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5258 md_number_to_chars (the_bytes, ri->r_address, 4);
5259 /* Now the fun stuff. */
5260 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5261 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5262 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5263 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5264 | ((ri->r_length << 5) & 0x60)
5265 | ((ri->r_extern << 4) & 0x10));
5270 #endif /* OBJ_AOUT or OBJ_BOUT */
5272 #ifndef WORKING_DOT_WORD
5273 int md_short_jump_size = 4;
5274 int md_long_jump_size = 6;
5277 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5278 fragS *frag ATTRIBUTE_UNUSED,
5279 symbolS *to_symbol ATTRIBUTE_UNUSED)
5283 offset = to_addr - (from_addr + 2);
5285 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5286 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5290 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5291 fragS *frag, symbolS *to_symbol)
5295 if (!HAVE_LONG_BRANCH (current_architecture))
5297 if (flag_keep_pcrel)
5298 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5299 offset = to_addr - S_GET_VALUE (to_symbol);
5300 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5301 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5302 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5307 offset = to_addr - (from_addr + 2);
5308 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5309 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5315 /* Different values of OK tell what its OK to return. Things that
5316 aren't OK are an error (what a shock, no?)
5319 10: Absolute 1:8 only
5320 20: Absolute 0:7 only
5321 30: absolute 0:15 only
5322 40: Absolute 0:31 only
5323 50: absolute 0:127 only
5324 55: absolute -64:63 only
5325 60: absolute -128:127 only
5326 65: absolute 0:511 only
5327 70: absolute 0:4095 only
5328 80: absolute -1, 1:7 only
5332 get_num (struct m68k_exp *exp, int ok)
5334 if (exp->exp.X_op == O_absent)
5336 /* Do the same thing the VAX asm does. */
5337 op (exp) = O_constant;
5343 as_warn (_("expression out of range: defaulting to 1"));
5347 else if (exp->exp.X_op == O_constant)
5352 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5354 as_warn (_("expression out of range: defaulting to 1"));
5359 if ((valueT) TRUNC (offs (exp)) > 7)
5363 if ((valueT) TRUNC (offs (exp)) > 15)
5367 if ((valueT) TRUNC (offs (exp)) > 32)
5371 if ((valueT) TRUNC (offs (exp)) > 127)
5375 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5379 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5383 if ((valueT) TRUNC (offs (exp)) > 511)
5387 if ((valueT) TRUNC (offs (exp)) > 4095)
5390 as_warn (_("expression out of range: defaulting to 0"));
5395 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5396 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5398 as_warn (_("expression out of range: defaulting to 1"));
5406 else if (exp->exp.X_op == O_big)
5408 if (offs (exp) <= 0 /* flonum. */
5409 && (ok == 90 /* no bignums */
5410 || (ok > 10 /* Small-int ranges including 0 ok. */
5411 /* If we have a flonum zero, a zero integer should
5412 do as well (e.g., in moveq). */
5413 && generic_floating_point_number.exponent == 0
5414 && generic_floating_point_number.low[0] == 0)))
5416 /* HACK! Turn it into a long. */
5417 LITTLENUM_TYPE words[6];
5419 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5420 op (exp) = O_constant;
5423 offs (exp) = words[1] | (words[0] << 16);
5427 op (exp) = O_constant;
5430 offs (exp) = (ok == 10) ? 1 : 0;
5431 as_warn (_("Can't deal with expression; defaulting to %ld"),
5437 if (ok >= 10 && ok <= 80)
5439 op (exp) = O_constant;
5442 offs (exp) = (ok == 10) ? 1 : 0;
5443 as_warn (_("Can't deal with expression; defaulting to %ld"),
5448 if (exp->size != SIZE_UNSPEC)
5456 if (!isbyte (offs (exp)))
5457 as_warn (_("expression doesn't fit in BYTE"));
5460 if (!isword (offs (exp)))
5461 as_warn (_("expression doesn't fit in WORD"));
5469 /* These are the back-ends for the various machine dependent pseudo-ops. */
5472 s_data1 (int ignore ATTRIBUTE_UNUSED)
5474 subseg_set (data_section, 1);
5475 demand_empty_rest_of_line ();
5479 s_data2 (int ignore ATTRIBUTE_UNUSED)
5481 subseg_set (data_section, 2);
5482 demand_empty_rest_of_line ();
5486 s_bss (int ignore ATTRIBUTE_UNUSED)
5488 /* We don't support putting frags in the BSS segment, we fake it
5489 by marking in_bss, then looking at s_skip for clues. */
5491 subseg_set (bss_section, 0);
5492 demand_empty_rest_of_line ();
5496 s_even (int ignore ATTRIBUTE_UNUSED)
5499 register long temp_fill;
5501 temp = 1; /* JF should be 2? */
5502 temp_fill = get_absolute_expression ();
5503 if (!need_pass_2) /* Never make frag if expect extra pass. */
5504 frag_align (temp, (int) temp_fill, 0);
5505 demand_empty_rest_of_line ();
5506 record_alignment (now_seg, temp);
5510 s_proc (int ignore ATTRIBUTE_UNUSED)
5512 demand_empty_rest_of_line ();
5515 /* Pseudo-ops handled for MRI compatibility. */
5517 /* This function returns non-zero if the argument is a conditional
5518 pseudo-op. This is called when checking whether a pending
5519 alignment is needed. */
5522 m68k_conditional_pseudoop (pseudo_typeS *pop)
5524 return (pop->poc_handler == s_mri_if
5525 || pop->poc_handler == s_mri_else);
5528 /* Handle an MRI style chip specification. */
5537 s = input_line_pointer;
5538 /* We can't use get_symbol_end since the processor names are not proper
5540 while (is_part_of_name (c = *input_line_pointer++))
5542 *--input_line_pointer = 0;
5543 for (i = 0; m68k_cpus[i].name; i++)
5544 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5546 if (!m68k_cpus[i].name)
5548 as_bad (_("%s: unrecognized processor name"), s);
5549 *input_line_pointer = c;
5550 ignore_rest_of_line ();
5553 *input_line_pointer = c;
5555 if (*input_line_pointer == '/')
5556 current_architecture = 0;
5558 current_architecture &= m68881 | m68851;
5559 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5560 control_regs = m68k_cpus[i].control_regs;
5562 while (*input_line_pointer == '/')
5564 ++input_line_pointer;
5565 s = input_line_pointer;
5566 /* We can't use get_symbol_end since the processor names are not
5568 while (is_part_of_name (c = *input_line_pointer++))
5570 *--input_line_pointer = 0;
5571 if (strcmp (s, "68881") == 0)
5572 current_architecture |= m68881;
5573 else if (strcmp (s, "68851") == 0)
5574 current_architecture |= m68851;
5575 *input_line_pointer = c;
5579 /* The MRI CHIP pseudo-op. */
5582 s_chip (int ignore ATTRIBUTE_UNUSED)
5588 stop = mri_comment_field (&stopc);
5591 mri_comment_end (stop, stopc);
5592 demand_empty_rest_of_line ();
5595 /* The MRI FOPT pseudo-op. */
5598 s_fopt (int ignore ATTRIBUTE_UNUSED)
5602 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5606 input_line_pointer += 3;
5607 temp = get_absolute_expression ();
5608 if (temp < 0 || temp > 7)
5609 as_bad (_("bad coprocessor id"));
5611 m68k_float_copnum = COP0 + temp;
5615 as_bad (_("unrecognized fopt option"));
5616 ignore_rest_of_line ();
5620 demand_empty_rest_of_line ();
5623 /* The structure used to handle the MRI OPT pseudo-op. */
5627 /* The name of the option. */
5630 /* If this is not NULL, just call this function. The first argument
5631 is the ARG field of this structure, the second argument is
5632 whether the option was negated. */
5633 void (*pfn) (int arg, int on);
5635 /* If this is not NULL, and the PFN field is NULL, set the variable
5636 this points to. Set it to the ARG field if the option was not
5637 negated, and the NOTARG field otherwise. */
5640 /* The value to pass to PFN or to assign to *PVAR. */
5643 /* The value to assign to *PVAR if the option is negated. If PFN is
5644 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5645 the option may not be negated. */
5649 /* The table used to handle the MRI OPT pseudo-op. */
5651 static void skip_to_comma (int, int);
5652 static void opt_nest (int, int);
5653 static void opt_chip (int, int);
5654 static void opt_list (int, int);
5655 static void opt_list_symbols (int, int);
5657 static const struct opt_action opt_table[] =
5659 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5661 /* We do relaxing, so there is little use for these options. */
5662 { "b", 0, 0, 0, 0 },
5663 { "brs", 0, 0, 0, 0 },
5664 { "brb", 0, 0, 0, 0 },
5665 { "brl", 0, 0, 0, 0 },
5666 { "brw", 0, 0, 0, 0 },
5668 { "c", 0, 0, 0, 0 },
5669 { "cex", 0, 0, 0, 0 },
5670 { "case", 0, &symbols_case_sensitive, 1, 0 },
5671 { "cl", 0, 0, 0, 0 },
5672 { "cre", 0, 0, 0, 0 },
5673 { "d", 0, &flag_keep_locals, 1, 0 },
5674 { "e", 0, 0, 0, 0 },
5675 { "f", 0, &flag_short_refs, 1, 0 },
5676 { "frs", 0, &flag_short_refs, 1, 0 },
5677 { "frl", 0, &flag_short_refs, 0, 1 },
5678 { "g", 0, 0, 0, 0 },
5679 { "i", 0, 0, 0, 0 },
5680 { "m", 0, 0, 0, 0 },
5681 { "mex", 0, 0, 0, 0 },
5682 { "mc", 0, 0, 0, 0 },
5683 { "md", 0, 0, 0, 0 },
5684 { "nest", opt_nest, 0, 0, 0 },
5685 { "next", skip_to_comma, 0, 0, 0 },
5686 { "o", 0, 0, 0, 0 },
5687 { "old", 0, 0, 0, 0 },
5688 { "op", skip_to_comma, 0, 0, 0 },
5689 { "pco", 0, 0, 0, 0 },
5690 { "p", opt_chip, 0, 0, 0 },
5691 { "pcr", 0, 0, 0, 0 },
5692 { "pcs", 0, 0, 0, 0 },
5693 { "r", 0, 0, 0, 0 },
5694 { "quick", 0, &m68k_quick, 1, 0 },
5695 { "rel32", 0, &m68k_rel32, 1, 0 },
5696 { "s", opt_list, 0, 0, 0 },
5697 { "t", opt_list_symbols, 0, 0, 0 },
5698 { "w", 0, &flag_no_warnings, 0, 1 },
5702 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5704 /* The MRI OPT pseudo-op. */
5707 s_opt (int ignore ATTRIBUTE_UNUSED)
5715 const struct opt_action *o;
5720 if (*input_line_pointer == '-')
5722 ++input_line_pointer;
5725 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5727 input_line_pointer += 2;
5731 s = input_line_pointer;
5732 c = get_symbol_end ();
5734 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5736 if (strcasecmp (s, o->name) == 0)
5740 /* Restore input_line_pointer now in case the option
5742 *input_line_pointer = c;
5743 (*o->pfn) (o->arg, t);
5745 else if (o->pvar != NULL)
5747 if (! t && o->arg == o->notarg)
5748 as_bad (_("option `%s' may not be negated"), s);
5749 *input_line_pointer = c;
5750 *o->pvar = t ? o->arg : o->notarg;
5753 *input_line_pointer = c;
5759 as_bad (_("option `%s' not recognized"), s);
5760 *input_line_pointer = c;
5763 while (*input_line_pointer++ == ',');
5765 /* Move back to terminating character. */
5766 --input_line_pointer;
5767 demand_empty_rest_of_line ();
5770 /* Skip ahead to a comma. This is used for OPT options which we do
5771 not support and which take arguments. */
5774 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5776 while (*input_line_pointer != ','
5777 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5778 ++input_line_pointer;
5781 /* Handle the OPT NEST=depth option. */
5784 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5786 if (*input_line_pointer != '=')
5788 as_bad (_("bad format of OPT NEST=depth"));
5792 ++input_line_pointer;
5793 max_macro_nest = get_absolute_expression ();
5796 /* Handle the OPT P=chip option. */
5799 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5801 if (*input_line_pointer != '=')
5803 /* This is just OPT P, which we do not support. */
5807 ++input_line_pointer;
5811 /* Handle the OPT S option. */
5814 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5819 /* Handle the OPT T option. */
5822 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5825 listing |= LISTING_SYMBOLS;
5827 listing &= ~LISTING_SYMBOLS;
5830 /* Handle the MRI REG pseudo-op. */
5833 s_reg (int ignore ATTRIBUTE_UNUSED)
5842 if (line_label == NULL)
5844 as_bad (_("missing label"));
5845 ignore_rest_of_line ();
5850 stop = mri_comment_field (&stopc);
5854 s = input_line_pointer;
5855 while (ISALNUM (*input_line_pointer)
5856 #ifdef REGISTER_PREFIX
5857 || *input_line_pointer == REGISTER_PREFIX
5859 || *input_line_pointer == '/'
5860 || *input_line_pointer == '-')
5861 ++input_line_pointer;
5862 c = *input_line_pointer;
5863 *input_line_pointer = '\0';
5865 if (m68k_ip_op (s, &rop) != 0)
5867 if (rop.error == NULL)
5868 as_bad (_("bad register list"));
5870 as_bad (_("bad register list: %s"), rop.error);
5871 *input_line_pointer = c;
5872 ignore_rest_of_line ();
5876 *input_line_pointer = c;
5878 if (rop.mode == REGLST)
5880 else if (rop.mode == DREG)
5881 mask = 1 << (rop.reg - DATA0);
5882 else if (rop.mode == AREG)
5883 mask = 1 << (rop.reg - ADDR0 + 8);
5884 else if (rop.mode == FPREG)
5885 mask = 1 << (rop.reg - FP0 + 16);
5886 else if (rop.mode == CONTROL
5889 else if (rop.mode == CONTROL
5892 else if (rop.mode == CONTROL
5897 as_bad (_("bad register list"));
5898 ignore_rest_of_line ();
5902 S_SET_SEGMENT (line_label, reg_section);
5903 S_SET_VALUE (line_label, ~mask);
5904 symbol_set_frag (line_label, &zero_address_frag);
5907 mri_comment_end (stop, stopc);
5909 demand_empty_rest_of_line ();
5912 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5916 struct save_opts *next;
5918 int symbols_case_sensitive;
5922 const enum m68k_register *control_regs;
5927 /* FIXME: We don't save OPT S. */
5930 /* This variable holds the stack of saved options. */
5932 static struct save_opts *save_stack;
5934 /* The MRI SAVE pseudo-op. */
5937 s_save (int ignore ATTRIBUTE_UNUSED)
5939 struct save_opts *s;
5941 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5942 s->abspcadd = m68k_abspcadd;
5943 s->symbols_case_sensitive = symbols_case_sensitive;
5944 s->keep_locals = flag_keep_locals;
5945 s->short_refs = flag_short_refs;
5946 s->architecture = current_architecture;
5947 s->control_regs = control_regs;
5948 s->quick = m68k_quick;
5949 s->rel32 = m68k_rel32;
5950 s->listing = listing;
5951 s->no_warnings = flag_no_warnings;
5953 s->next = save_stack;
5956 demand_empty_rest_of_line ();
5959 /* The MRI RESTORE pseudo-op. */
5962 s_restore (int ignore ATTRIBUTE_UNUSED)
5964 struct save_opts *s;
5966 if (save_stack == NULL)
5968 as_bad (_("restore without save"));
5969 ignore_rest_of_line ();
5974 save_stack = s->next;
5976 m68k_abspcadd = s->abspcadd;
5977 symbols_case_sensitive = s->symbols_case_sensitive;
5978 flag_keep_locals = s->keep_locals;
5979 flag_short_refs = s->short_refs;
5980 current_architecture = s->architecture;
5981 control_regs = s->control_regs;
5982 m68k_quick = s->quick;
5983 m68k_rel32 = s->rel32;
5984 listing = s->listing;
5985 flag_no_warnings = s->no_warnings;
5989 demand_empty_rest_of_line ();
5992 /* Types of MRI structured control directives. */
5994 enum mri_control_type
6002 /* This structure is used to stack the MRI structured control
6005 struct mri_control_info
6007 /* The directive within which this one is enclosed. */
6008 struct mri_control_info *outer;
6010 /* The type of directive. */
6011 enum mri_control_type type;
6013 /* Whether an ELSE has been in an IF. */
6016 /* The add or sub statement at the end of a FOR. */
6019 /* The label of the top of a FOR or REPEAT loop. */
6022 /* The label to jump to for the next iteration, or the else
6023 expression of a conditional. */
6026 /* The label to jump to to break out of the loop, or the label past
6027 the end of a conditional. */
6031 /* The stack of MRI structured control directives. */
6033 static struct mri_control_info *mri_control_stack;
6035 /* The current MRI structured control directive index number, used to
6036 generate label names. */
6038 static int mri_control_index;
6040 /* Assemble an instruction for an MRI structured control directive. */
6043 mri_assemble (char *str)
6047 /* md_assemble expects the opcode to be in lower case. */
6048 for (s = str; *s != ' ' && *s != '\0'; s++)
6054 /* Generate a new MRI label structured control directive label name. */
6057 mri_control_label (void)
6061 n = (char *) xmalloc (20);
6062 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6063 ++mri_control_index;
6067 /* Create a new MRI structured control directive. */
6069 static struct mri_control_info *
6070 push_mri_control (enum mri_control_type type)
6072 struct mri_control_info *n;
6074 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6078 if (type == mri_if || type == mri_while)
6081 n->top = mri_control_label ();
6082 n->next = mri_control_label ();
6083 n->bottom = mri_control_label ();
6085 n->outer = mri_control_stack;
6086 mri_control_stack = n;
6091 /* Pop off the stack of MRI structured control directives. */
6094 pop_mri_control (void)
6096 struct mri_control_info *n;
6098 n = mri_control_stack;
6099 mri_control_stack = n->outer;
6107 /* Recognize a condition code in an MRI structured control expression. */
6110 parse_mri_condition (int *pcc)
6114 know (*input_line_pointer == '<');
6116 ++input_line_pointer;
6117 c1 = *input_line_pointer++;
6118 c2 = *input_line_pointer++;
6120 if (*input_line_pointer != '>')
6122 as_bad (_("syntax error in structured control directive"));
6126 ++input_line_pointer;
6132 *pcc = (c1 << 8) | c2;
6137 /* Parse a single operand in an MRI structured control expression. */
6140 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6141 char **rightstart, char **rightstop)
6153 if (*input_line_pointer == '<')
6155 /* It's just a condition code. */
6156 return parse_mri_condition (pcc);
6159 /* Look ahead for the condition code. */
6160 for (s = input_line_pointer; *s != '\0'; ++s)
6162 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6167 as_bad (_("missing condition code in structured control directive"));
6171 *leftstart = input_line_pointer;
6173 if (*leftstop > *leftstart
6174 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6177 input_line_pointer = s;
6178 if (! parse_mri_condition (pcc))
6181 /* Look ahead for AND or OR or end of line. */
6182 for (s = input_line_pointer; *s != '\0'; ++s)
6184 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6185 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6187 if ((s == input_line_pointer
6190 && ((strncasecmp (s, "AND", 3) == 0
6191 && (s[3] == '.' || ! is_part_of_name (s[3])))
6192 || (strncasecmp (s, "OR", 2) == 0
6193 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6197 *rightstart = input_line_pointer;
6199 if (*rightstop > *rightstart
6200 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6203 input_line_pointer = s;
6208 #define MCC(b1, b2) (((b1) << 8) | (b2))
6210 /* Swap the sense of a condition. This changes the condition so that
6211 it generates the same result when the operands are swapped. */
6214 swap_mri_condition (int cc)
6218 case MCC ('h', 'i'): return MCC ('c', 's');
6219 case MCC ('l', 's'): return MCC ('c', 'c');
6220 /* <HS> is an alias for <CC>. */
6221 case MCC ('h', 's'):
6222 case MCC ('c', 'c'): return MCC ('l', 's');
6223 /* <LO> is an alias for <CS>. */
6224 case MCC ('l', 'o'):
6225 case MCC ('c', 's'): return MCC ('h', 'i');
6226 case MCC ('p', 'l'): return MCC ('m', 'i');
6227 case MCC ('m', 'i'): return MCC ('p', 'l');
6228 case MCC ('g', 'e'): return MCC ('l', 'e');
6229 case MCC ('l', 't'): return MCC ('g', 't');
6230 case MCC ('g', 't'): return MCC ('l', 't');
6231 case MCC ('l', 'e'): return MCC ('g', 'e');
6232 /* Issue a warning for conditions we can not swap. */
6233 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6234 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6235 case MCC ('v', 'c'):
6236 case MCC ('v', 's'):
6238 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6239 (char) (cc >> 8), (char) (cc));
6245 /* Reverse the sense of a condition. */
6248 reverse_mri_condition (int cc)
6252 case MCC ('h', 'i'): return MCC ('l', 's');
6253 case MCC ('l', 's'): return MCC ('h', 'i');
6254 /* <HS> is an alias for <CC> */
6255 case MCC ('h', 's'): return MCC ('l', 'o');
6256 case MCC ('c', 'c'): return MCC ('c', 's');
6257 /* <LO> is an alias for <CS> */
6258 case MCC ('l', 'o'): return MCC ('h', 's');
6259 case MCC ('c', 's'): return MCC ('c', 'c');
6260 case MCC ('n', 'e'): return MCC ('e', 'q');
6261 case MCC ('e', 'q'): return MCC ('n', 'e');
6262 case MCC ('v', 'c'): return MCC ('v', 's');
6263 case MCC ('v', 's'): return MCC ('v', 'c');
6264 case MCC ('p', 'l'): return MCC ('m', 'i');
6265 case MCC ('m', 'i'): return MCC ('p', 'l');
6266 case MCC ('g', 'e'): return MCC ('l', 't');
6267 case MCC ('l', 't'): return MCC ('g', 'e');
6268 case MCC ('g', 't'): return MCC ('l', 'e');
6269 case MCC ('l', 'e'): return MCC ('g', 't');
6274 /* Build an MRI structured control expression. This generates test
6275 and branch instructions. It goes to TRUELAB if the condition is
6276 true, and to FALSELAB if the condition is false. Exactly one of
6277 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6278 is the size qualifier for the expression. EXTENT is the size to
6279 use for the branch. */
6282 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6283 char *rightstart, char *rightstop,
6284 const char *truelab, const char *falselab,
6290 if (leftstart != NULL)
6292 struct m68k_op leftop, rightop;
6295 /* Swap the compare operands, if necessary, to produce a legal
6296 m68k compare instruction. Comparing a register operand with
6297 a non-register operand requires the register to be on the
6298 right (cmp, cmpa). Comparing an immediate value with
6299 anything requires the immediate value to be on the left
6304 (void) m68k_ip_op (leftstart, &leftop);
6309 (void) m68k_ip_op (rightstart, &rightop);
6312 if (rightop.mode == IMMED
6313 || ((leftop.mode == DREG || leftop.mode == AREG)
6314 && (rightop.mode != DREG && rightop.mode != AREG)))
6318 /* Correct conditional handling:
6319 if #1 <lt> d0 then ;means if (1 < d0)
6325 cmp #1,d0 if we do *not* swap the operands
6326 bgt true we need the swapped condition!
6333 leftstart = rightstart;
6336 leftstop = rightstop;
6341 cc = swap_mri_condition (cc);
6345 if (truelab == NULL)
6347 cc = reverse_mri_condition (cc);
6351 if (leftstart != NULL)
6353 buf = (char *) xmalloc (20
6354 + (leftstop - leftstart)
6355 + (rightstop - rightstart));
6361 *s++ = TOLOWER (qual);
6363 memcpy (s, leftstart, leftstop - leftstart);
6364 s += leftstop - leftstart;
6366 memcpy (s, rightstart, rightstop - rightstart);
6367 s += rightstop - rightstart;
6373 buf = (char *) xmalloc (20 + strlen (truelab));
6379 *s++ = TOLOWER (extent);
6381 strcpy (s, truelab);
6386 /* Parse an MRI structured control expression. This generates test
6387 and branch instructions. STOP is where the expression ends. It
6388 goes to TRUELAB if the condition is true, and to FALSELAB if the
6389 condition is false. Exactly one of TRUELAB and FALSELAB will be
6390 NULL, meaning to fall through. QUAL is the size qualifier for the
6391 expression. EXTENT is the size to use for the branch. */
6394 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6395 const char *falselab, int extent)
6407 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6408 &rightstart, &rightstop))
6414 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6418 if (falselab != NULL)
6421 flab = mri_control_label ();
6423 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6424 rightstop, (const char *) NULL, flab, extent);
6426 input_line_pointer += 3;
6427 if (*input_line_pointer != '.'
6428 || input_line_pointer[1] == '\0')
6432 qual = input_line_pointer[1];
6433 input_line_pointer += 2;
6436 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6437 &rightstart, &rightstop))
6443 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6444 rightstop, truelab, falselab, extent);
6446 if (falselab == NULL)
6449 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6453 if (truelab != NULL)
6456 tlab = mri_control_label ();
6458 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6459 rightstop, tlab, (const char *) NULL, extent);
6461 input_line_pointer += 2;
6462 if (*input_line_pointer != '.'
6463 || input_line_pointer[1] == '\0')
6467 qual = input_line_pointer[1];
6468 input_line_pointer += 2;
6471 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6472 &rightstart, &rightstop))
6478 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6479 rightstop, truelab, falselab, extent);
6481 if (truelab == NULL)
6486 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6487 rightstop, truelab, falselab, extent);
6491 if (input_line_pointer != stop)
6492 as_bad (_("syntax error in structured control directive"));
6495 /* Handle the MRI IF pseudo-op. This may be a structured control
6496 directive, or it may be a regular assembler conditional, depending
6504 struct mri_control_info *n;
6506 /* A structured control directive must end with THEN with an
6507 optional qualifier. */
6508 s = input_line_pointer;
6509 /* We only accept '*' as introduction of comments if preceded by white space
6510 or at first column of a line (I think this can't actually happen here?)
6511 This is important when assembling:
6512 if d0 <ne> 12(a0,d0*2) then
6513 if d0 <ne> #CONST*20 then. */
6514 while (! (is_end_of_line[(unsigned char) *s]
6517 && (s == input_line_pointer
6519 || *(s-1) == '\t'))))
6522 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6525 if (s - input_line_pointer > 1
6529 if (s - input_line_pointer < 3
6530 || strncasecmp (s - 3, "THEN", 4) != 0)
6534 as_bad (_("missing then"));
6535 ignore_rest_of_line ();
6539 /* It's a conditional. */
6544 /* Since this might be a conditional if, this pseudo-op will be
6545 called even if we are supported to be ignoring input. Double
6546 check now. Clobber *input_line_pointer so that ignore_input
6547 thinks that this is not a special pseudo-op. */
6548 c = *input_line_pointer;
6549 *input_line_pointer = 0;
6550 if (ignore_input ())
6552 *input_line_pointer = c;
6553 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6554 ++input_line_pointer;
6555 demand_empty_rest_of_line ();
6558 *input_line_pointer = c;
6560 n = push_mri_control (mri_if);
6562 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6563 n->next, s[1] == '.' ? s[2] : '\0');
6566 input_line_pointer = s + 3;
6568 input_line_pointer = s + 1;
6572 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6573 ++input_line_pointer;
6576 demand_empty_rest_of_line ();
6579 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6580 structured IF, associate the ELSE with the IF. Otherwise, assume
6581 it is a conditional else. */
6584 s_mri_else (int qual)
6591 && (mri_control_stack == NULL
6592 || mri_control_stack->type != mri_if
6593 || mri_control_stack->else_seen))
6599 c = *input_line_pointer;
6600 *input_line_pointer = 0;
6601 if (ignore_input ())
6603 *input_line_pointer = c;
6604 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6605 ++input_line_pointer;
6606 demand_empty_rest_of_line ();
6609 *input_line_pointer = c;
6611 if (mri_control_stack == NULL
6612 || mri_control_stack->type != mri_if
6613 || mri_control_stack->else_seen)
6615 as_bad (_("else without matching if"));
6616 ignore_rest_of_line ();
6620 mri_control_stack->else_seen = 1;
6622 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6623 q[0] = TOLOWER (qual);
6625 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6629 colon (mri_control_stack->next);
6633 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6634 ++input_line_pointer;
6637 demand_empty_rest_of_line ();
6640 /* Handle the MRI ENDI pseudo-op. */
6643 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6645 if (mri_control_stack == NULL
6646 || mri_control_stack->type != mri_if)
6648 as_bad (_("endi without matching if"));
6649 ignore_rest_of_line ();
6653 /* ignore_input will not return true for ENDI, so we don't need to
6654 worry about checking it again here. */
6656 if (! mri_control_stack->else_seen)
6657 colon (mri_control_stack->next);
6658 colon (mri_control_stack->bottom);
6664 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6665 ++input_line_pointer;
6668 demand_empty_rest_of_line ();
6671 /* Handle the MRI BREAK pseudo-op. */
6674 s_mri_break (int extent)
6676 struct mri_control_info *n;
6680 n = mri_control_stack;
6682 && n->type != mri_for
6683 && n->type != mri_repeat
6684 && n->type != mri_while)
6688 as_bad (_("break outside of structured loop"));
6689 ignore_rest_of_line ();
6693 buf = (char *) xmalloc (20 + strlen (n->bottom));
6694 ex[0] = TOLOWER (extent);
6696 sprintf (buf, "bra%s %s", ex, n->bottom);
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6706 demand_empty_rest_of_line ();
6709 /* Handle the MRI NEXT pseudo-op. */
6712 s_mri_next (int extent)
6714 struct mri_control_info *n;
6718 n = mri_control_stack;
6720 && n->type != mri_for
6721 && n->type != mri_repeat
6722 && n->type != mri_while)
6726 as_bad (_("next outside of structured loop"));
6727 ignore_rest_of_line ();
6731 buf = (char *) xmalloc (20 + strlen (n->next));
6732 ex[0] = TOLOWER (extent);
6734 sprintf (buf, "bra%s %s", ex, n->next);
6740 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6741 ++input_line_pointer;
6744 demand_empty_rest_of_line ();
6747 /* Handle the MRI FOR pseudo-op. */
6750 s_mri_for (int qual)
6752 const char *varstart, *varstop;
6753 const char *initstart, *initstop;
6754 const char *endstart, *endstop;
6755 const char *bystart, *bystop;
6759 struct mri_control_info *n;
6765 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6769 varstart = input_line_pointer;
6771 /* Look for the '='. */
6772 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6773 && *input_line_pointer != '=')
6774 ++input_line_pointer;
6775 if (*input_line_pointer != '=')
6777 as_bad (_("missing ="));
6778 ignore_rest_of_line ();
6782 varstop = input_line_pointer;
6783 if (varstop > varstart
6784 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6787 ++input_line_pointer;
6789 initstart = input_line_pointer;
6791 /* Look for TO or DOWNTO. */
6794 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6796 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6797 && ! is_part_of_name (input_line_pointer[2]))
6799 initstop = input_line_pointer;
6800 input_line_pointer += 2;
6803 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6804 && ! is_part_of_name (input_line_pointer[6]))
6806 initstop = input_line_pointer;
6808 input_line_pointer += 6;
6811 ++input_line_pointer;
6813 if (initstop == NULL)
6815 as_bad (_("missing to or downto"));
6816 ignore_rest_of_line ();
6819 if (initstop > initstart
6820 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6824 endstart = input_line_pointer;
6826 /* Look for BY or DO. */
6829 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6831 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6832 && ! is_part_of_name (input_line_pointer[2]))
6834 endstop = input_line_pointer;
6836 input_line_pointer += 2;
6839 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6840 && (input_line_pointer[2] == '.'
6841 || ! is_part_of_name (input_line_pointer[2])))
6843 endstop = input_line_pointer;
6844 input_line_pointer += 2;
6847 ++input_line_pointer;
6849 if (endstop == NULL)
6851 as_bad (_("missing do"));
6852 ignore_rest_of_line ();
6855 if (endstop > endstart
6856 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6862 bystop = bystart + 2;
6867 bystart = input_line_pointer;
6871 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6873 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6874 && (input_line_pointer[2] == '.'
6875 || ! is_part_of_name (input_line_pointer[2])))
6877 bystop = input_line_pointer;
6878 input_line_pointer += 2;
6881 ++input_line_pointer;
6885 as_bad (_("missing do"));
6886 ignore_rest_of_line ();
6889 if (bystop > bystart
6890 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6894 if (*input_line_pointer != '.')
6898 extent = input_line_pointer[1];
6899 input_line_pointer += 2;
6902 /* We have fully parsed the FOR operands. Now build the loop. */
6903 n = push_mri_control (mri_for);
6905 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6907 /* Move init,var. */
6914 *s++ = TOLOWER (qual);
6916 memcpy (s, initstart, initstop - initstart);
6917 s += initstop - initstart;
6919 memcpy (s, varstart, varstop - varstart);
6920 s += varstop - varstart;
6932 *s++ = TOLOWER (qual);
6934 memcpy (s, endstart, endstop - endstart);
6935 s += endstop - endstart;
6937 memcpy (s, varstart, varstop - varstart);
6938 s += varstop - varstart;
6943 ex[0] = TOLOWER (extent);
6946 sprintf (buf, "blt%s %s", ex, n->bottom);
6948 sprintf (buf, "bgt%s %s", ex, n->bottom);
6951 /* Put together the add or sub instruction used by ENDF. */
6959 *s++ = TOLOWER (qual);
6961 memcpy (s, bystart, bystop - bystart);
6962 s += bystop - bystart;
6964 memcpy (s, varstart, varstop - varstart);
6965 s += varstop - varstart;
6971 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6972 ++input_line_pointer;
6975 demand_empty_rest_of_line ();
6978 /* Handle the MRI ENDF pseudo-op. */
6981 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6983 if (mri_control_stack == NULL
6984 || mri_control_stack->type != mri_for)
6986 as_bad (_("endf without for"));
6987 ignore_rest_of_line ();
6991 colon (mri_control_stack->next);
6993 mri_assemble (mri_control_stack->incr);
6995 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6996 mri_assemble (mri_control_stack->incr);
6998 free (mri_control_stack->incr);
7000 colon (mri_control_stack->bottom);
7006 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7007 ++input_line_pointer;
7010 demand_empty_rest_of_line ();
7013 /* Handle the MRI REPEAT pseudo-op. */
7016 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7018 struct mri_control_info *n;
7020 n = push_mri_control (mri_repeat);
7024 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7025 ++input_line_pointer;
7027 demand_empty_rest_of_line ();
7030 /* Handle the MRI UNTIL pseudo-op. */
7033 s_mri_until (int qual)
7037 if (mri_control_stack == NULL
7038 || mri_control_stack->type != mri_repeat)
7040 as_bad (_("until without repeat"));
7041 ignore_rest_of_line ();
7045 colon (mri_control_stack->next);
7047 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7050 parse_mri_control_expression (s, qual, (const char *) NULL,
7051 mri_control_stack->top, '\0');
7053 colon (mri_control_stack->bottom);
7055 input_line_pointer = s;
7061 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7062 ++input_line_pointer;
7065 demand_empty_rest_of_line ();
7068 /* Handle the MRI WHILE pseudo-op. */
7071 s_mri_while (int qual)
7075 struct mri_control_info *n;
7077 s = input_line_pointer;
7078 /* We only accept '*' as introduction of comments if preceded by white space
7079 or at first column of a line (I think this can't actually happen here?)
7080 This is important when assembling:
7081 while d0 <ne> 12(a0,d0*2) do
7082 while d0 <ne> #CONST*20 do. */
7083 while (! (is_end_of_line[(unsigned char) *s]
7086 && (s == input_line_pointer
7088 || *(s-1) == '\t'))))
7091 while (*s == ' ' || *s == '\t')
7093 if (s - input_line_pointer > 1
7096 if (s - input_line_pointer < 2
7097 || strncasecmp (s - 1, "DO", 2) != 0)
7099 as_bad (_("missing do"));
7100 ignore_rest_of_line ();
7104 n = push_mri_control (mri_while);
7108 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7109 s[1] == '.' ? s[2] : '\0');
7111 input_line_pointer = s + 1;
7112 if (*input_line_pointer == '.')
7113 input_line_pointer += 2;
7117 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7118 ++input_line_pointer;
7121 demand_empty_rest_of_line ();
7124 /* Handle the MRI ENDW pseudo-op. */
7127 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7131 if (mri_control_stack == NULL
7132 || mri_control_stack->type != mri_while)
7134 as_bad (_("endw without while"));
7135 ignore_rest_of_line ();
7139 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7140 sprintf (buf, "bra %s", mri_control_stack->next);
7144 colon (mri_control_stack->bottom);
7150 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7151 ++input_line_pointer;
7154 demand_empty_rest_of_line ();
7157 /* Parse a .cpu directive. */
7160 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7167 as_bad (_("already assembled instructions"));
7168 ignore_rest_of_line ();
7172 name = input_line_pointer;
7173 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7174 input_line_pointer++;
7175 saved_char = *input_line_pointer;
7176 *input_line_pointer = 0;
7178 m68k_set_cpu (name, 1, 0);
7180 *input_line_pointer = saved_char;
7181 demand_empty_rest_of_line ();
7185 /* Parse a .arch directive. */
7188 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7195 as_bad (_("already assembled instructions"));
7196 ignore_rest_of_line ();
7200 name = input_line_pointer;
7201 while (*input_line_pointer && *input_line_pointer != ','
7202 && !ISSPACE (*input_line_pointer))
7203 input_line_pointer++;
7204 saved_char = *input_line_pointer;
7205 *input_line_pointer = 0;
7207 if (m68k_set_arch (name, 1, 0))
7209 /* Scan extensions. */
7212 *input_line_pointer++ = saved_char;
7213 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7215 name = input_line_pointer;
7216 while (*input_line_pointer && *input_line_pointer != ','
7217 && !ISSPACE (*input_line_pointer))
7218 input_line_pointer++;
7219 saved_char = *input_line_pointer;
7220 *input_line_pointer = 0;
7222 while (m68k_set_extension (name, 1, 0));
7225 *input_line_pointer = saved_char;
7226 demand_empty_rest_of_line ();
7230 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7231 if none is found, the caller is responsible for emitting an error
7232 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7233 cpu name, if it begins with a '6' (possibly skipping an intervening
7234 'c'. We also allow a 'c' in the same place. if NEGATED is
7235 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7236 the option is indeed negated. */
7238 static const struct m68k_cpu *
7239 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7240 int allow_m, int *negated)
7242 /* allow negated value? */
7247 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7254 /* Remove 'm' or 'mc' prefix from 68k variants. */
7261 else if (arg[1] == 'c' && arg[2] == '6')
7265 else if (arg[0] == 'c' && arg[1] == '6')
7268 for (; table->name; table++)
7269 if (!strcmp (arg, table->name))
7271 if (table->alias < -1 || table->alias > 1)
7272 as_bad (_("`%s' is deprecated, use `%s'"),
7273 table->name, table[table->alias < 0 ? 1 : -1].name);
7279 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7282 m68k_set_cpu (char const *name, int allow_m, int silent)
7284 const struct m68k_cpu *cpu;
7286 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7291 as_bad (_("cpu `%s' unrecognized"), name);
7295 if (selected_cpu && selected_cpu != cpu)
7297 as_bad (_("already selected `%s' processor"),
7298 selected_cpu->name);
7305 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7308 m68k_set_arch (char const *name, int allow_m, int silent)
7310 const struct m68k_cpu *arch;
7312 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7317 as_bad (_("architecture `%s' unrecognized"), name);
7321 if (selected_arch && selected_arch != arch)
7323 as_bad (_("already selected `%s' architecture"),
7324 selected_arch->name);
7328 selected_arch = arch;
7332 /* Set the architecture extension, issuing errors if it is
7333 unrecognized, or invalid */
7336 m68k_set_extension (char const *name, int allow_m, int silent)
7339 const struct m68k_cpu *ext;
7341 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7346 as_bad (_("extension `%s' unrecognized"), name);
7351 not_current_architecture |= ext->arch;
7353 current_architecture |= ext->arch;
7358 Invocation line includes a switch not recognized by the base assembler.
7362 const char *md_shortopts = "lSA:m:kQ:V";
7364 const char *md_shortopts = "lSA:m:k";
7367 struct option md_longopts[] = {
7368 #define OPTION_PIC (OPTION_MD_BASE)
7369 {"pic", no_argument, NULL, OPTION_PIC},
7370 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7371 {"register-prefix-optional", no_argument, NULL,
7372 OPTION_REGISTER_PREFIX_OPTIONAL},
7373 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7374 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7375 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7376 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7377 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7378 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7379 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7380 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7381 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7382 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7383 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7384 {"pcrel", no_argument, NULL, OPTION_PCREL},
7385 {NULL, no_argument, NULL, 0}
7387 size_t md_longopts_size = sizeof (md_longopts);
7390 md_parse_option (int c, char *arg)
7394 case 'l': /* -l means keep external to 2 bit offset
7395 rather than 16 bit one. */
7396 flag_short_refs = 1;
7399 case 'S': /* -S means that jbsr's always turn into
7401 flag_long_jumps = 1;
7404 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7405 branches into absolute jumps. */
7406 flag_keep_pcrel = 1;
7412 break; /* -pic, Position Independent Code. */
7414 case OPTION_REGISTER_PREFIX_OPTIONAL:
7415 flag_reg_prefix_optional = 1;
7416 reg_prefix_optional_seen = 1;
7419 /* -V: SVR4 argument to print version ID. */
7421 print_version_id ();
7424 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7425 should be emitted or not. FIXME: Not implemented. */
7429 case OPTION_BITWISE_OR:
7434 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7436 for (s = m68k_comment_chars; *s != '\0'; s++)
7440 m68k_comment_chars = n;
7444 case OPTION_BASE_SIZE_DEFAULT_16:
7445 m68k_index_width_default = SIZE_WORD;
7448 case OPTION_BASE_SIZE_DEFAULT_32:
7449 m68k_index_width_default = SIZE_LONG;
7452 case OPTION_DISP_SIZE_DEFAULT_16:
7454 m68k_rel32_from_cmdline = 1;
7457 case OPTION_DISP_SIZE_DEFAULT_32:
7459 m68k_rel32_from_cmdline = 1;
7464 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7467 /* Intentional fall-through. */
7469 if (!strncmp (arg, "arch=", 5))
7470 m68k_set_arch (arg + 5, 1, 0);
7471 else if (!strncmp (arg, "cpu=", 4))
7472 m68k_set_cpu (arg + 4, 1, 0);
7473 else if (m68k_set_extension (arg, 0, 1))
7475 else if (m68k_set_arch (arg, 0, 1))
7477 else if (m68k_set_cpu (arg, 0, 1))
7490 /* Setup tables from the selected arch and/or cpu */
7493 m68k_init_arch (void)
7495 if (not_current_architecture & current_architecture)
7497 as_bad (_("architecture features both enabled and disabled"));
7498 not_current_architecture &= ~current_architecture;
7502 current_architecture |= selected_arch->arch;
7503 control_regs = selected_arch->control_regs;
7506 current_architecture |= selected_cpu->arch;
7508 current_architecture &= ~not_current_architecture;
7510 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7512 /* Determine which float is really meant. */
7513 if (current_architecture & (m68k_mask & ~m68881))
7514 current_architecture ^= cfloat;
7516 current_architecture ^= m68881;
7521 control_regs = selected_cpu->control_regs;
7522 if (current_architecture & ~selected_cpu->arch)
7524 as_bad (_("selected processor does not have all features of selected architecture"));
7525 current_architecture
7526 = selected_cpu->arch & ~not_current_architecture;
7530 if ((current_architecture & m68k_mask)
7531 && (current_architecture & ~m68k_mask))
7533 as_bad (_ ("m68k and cf features both selected"));
7534 if (current_architecture & m68k_mask)
7535 current_architecture &= m68k_mask;
7537 current_architecture &= ~m68k_mask;
7540 /* Permit m68881 specification with all cpus; those that can't work
7541 with a coprocessor could be doing emulation. */
7542 if (current_architecture & m68851)
7544 if (current_architecture & m68040)
7545 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7547 /* What other incompatibilities could we check for? */
7549 if (cpu_of_arch (current_architecture) < m68020
7550 || arch_coldfire_p (current_architecture))
7551 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7557 md_show_usage (FILE *stream)
7559 const char *default_cpu = TARGET_CPU;
7561 unsigned int default_arch;
7563 /* Get the canonical name for the default target CPU. */
7564 if (*default_cpu == 'm')
7566 for (i = 0; m68k_cpus[i].name; i++)
7568 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7570 default_arch = m68k_cpus[i].arch;
7571 while (m68k_cpus[i].alias > 0)
7573 while (m68k_cpus[i].alias < 0)
7575 default_cpu = m68k_cpus[i].name;
7579 fprintf (stream, _("\
7580 -march=<arch> set architecture\n\
7581 -mcpu=<cpu> set cpu [default %s]\n\
7583 for (i = 0; m68k_extensions[i].name; i++)
7584 fprintf (stream, _("\
7585 -m[no-]%-16s enable/disable%s architecture extension\n\
7586 "), m68k_extensions[i].name,
7587 m68k_extensions[i].alias > 0 ? " ColdFire"
7588 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7590 fprintf (stream, _("\
7591 -l use 1 word for refs to undefined symbols [default 2]\n\
7592 -pic, -k generate position independent code\n\
7593 -S turn jbsr into jsr\n\
7594 --pcrel never turn PC-relative branches into absolute jumps\n\
7595 --register-prefix-optional\n\
7596 recognize register names without prefix character\n\
7597 --bitwise-or do not treat `|' as a comment character\n\
7598 --base-size-default-16 base reg without size is 16 bits\n\
7599 --base-size-default-32 base reg without size is 32 bits (default)\n\
7600 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7601 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7604 fprintf (stream, _("Architecture variants are: "));
7605 for (i = 0; m68k_archs[i].name; i++)
7608 fprintf (stream, " | ");
7609 fprintf (stream, m68k_archs[i].name);
7611 fprintf (stream, "\n");
7613 fprintf (stream, _("Processor variants are: "));
7614 for (i = 0; m68k_cpus[i].name; i++)
7617 fprintf (stream, " | ");
7618 fprintf (stream, m68k_cpus[i].name);
7620 fprintf (stream, _("\n"));
7625 /* TEST2: Test md_assemble() */
7626 /* Warning, this routine probably doesn't work anymore. */
7630 struct m68k_it the_ins;
7638 if (!gets (buf) || !*buf)
7640 if (buf[0] == '|' || buf[1] == '.')
7642 for (cp = buf; *cp; cp++)
7647 memset (&the_ins, '\0', sizeof (the_ins));
7648 m68k_ip (&the_ins, buf);
7651 printf (_("Error %s in %s\n"), the_ins.error, buf);
7655 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7656 for (n = 0; n < the_ins.numo; n++)
7657 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7659 print_the_insn (&the_ins.opcode[0], stdout);
7660 (void) putchar ('\n');
7662 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7664 if (the_ins.operands[n].error)
7666 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7669 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7670 the_ins.operands[n].reg);
7671 if (the_ins.operands[n].b_const)
7672 printf ("Constant: '%.*s', ",
7673 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7674 the_ins.operands[n].b_const);
7675 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7676 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7677 if (the_ins.operands[n].b_iadd)
7678 printf ("Iadd: '%.*s',",
7679 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7680 the_ins.operands[n].b_iadd);
7689 is_label (char *str)
7693 while (*str && *str != ' ')
7695 if (str[-1] == ':' || str[1] == '=')
7702 /* Possible states for relaxation:
7704 0 0 branch offset byte (bra, etc)
7708 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7712 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7719 /* We have no need to default values of symbols. */
7722 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7727 /* Round up a section size to the appropriate boundary. */
7729 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7732 /* For a.out, force the section size to be aligned. If we don't do
7733 this, BFD will align it for us, but it will not write out the
7734 final bytes of the section. This may be a bug in BFD, but it is
7735 easier to fix it here since that is how the other a.out targets
7739 align = bfd_get_section_alignment (stdoutput, segment);
7740 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7746 /* Exactly what point is a PC-relative offset relative TO?
7747 On the 68k, it is relative to the address of the first extension
7748 word. The difference between the addresses of the offset and the
7749 first extension word is stored in fx_pcrel_adjust. */
7751 md_pcrel_from (fixS *fixP)
7755 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7756 sign extend the value here. */
7757 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7760 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7765 m68k_elf_final_processing (void)
7769 if (arch_coldfire_fpu (current_architecture))
7770 flags |= EF_M68K_CFV4E;
7771 /* Set file-specific flags if this is a cpu32 processor. */
7772 if (cpu_of_arch (current_architecture) & cpu32)
7773 flags |= EF_M68K_CPU32;
7774 else if (cpu_of_arch (current_architecture) & fido_a)
7775 flags |= EF_M68K_FIDO;
7776 else if ((cpu_of_arch (current_architecture) & m68000up)
7777 && !(cpu_of_arch (current_architecture) & m68020up))
7778 flags |= EF_M68K_M68000;
7780 if (current_architecture & mcfisa_a)
7782 static const unsigned isa_features[][2] =
7784 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7785 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7786 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7787 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7788 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7789 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7790 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7793 static const unsigned mac_features[][2] =
7795 {EF_M68K_CF_MAC, mcfmac},
7796 {EF_M68K_CF_EMAC, mcfemac},
7802 pattern = (current_architecture
7803 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7804 for (ix = 0; isa_features[ix][1]; ix++)
7806 if (pattern == isa_features[ix][1])
7808 flags |= isa_features[ix][0];
7812 if (!isa_features[ix][1])
7815 as_warn (_("Not a defined coldfire architecture"));
7819 if (current_architecture & cfloat)
7820 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7822 pattern = current_architecture & (mcfmac|mcfemac);
7825 for (ix = 0; mac_features[ix][1]; ix++)
7827 if (pattern == mac_features[ix][1])
7829 flags |= mac_features[ix][0];
7833 if (!mac_features[ix][1])
7838 elf_elfheader (stdoutput)->e_flags |= flags;
7843 tc_m68k_regname_to_dw2regnum (char *regname)
7845 unsigned int regnum;
7846 static const char *const regnames[] =
7848 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7849 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7850 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7854 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7855 if (strcmp (regname, regnames[regnum]) == 0)
7862 tc_m68k_frame_initial_instructions (void)
7864 static int sp_regno = -1;
7867 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7869 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7870 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);