1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* The default width to use for an index register when using a base
101 static enum m68k_size m68k_index_width_default = SIZE_LONG;
103 /* Its an arbitrary name: This means I don't approve of it */
104 /* See flames below */
105 static struct obstack robyn;
107 #define TAB(x,y) (((x)<<2)+(y))
108 #define TABTYPE(xy) ((xy) >> 2)
114 /* Case `g' except when BCC68000 is applicable. */
116 /* Coprocessor branches. */
118 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
119 supported on all cpus. Widens to 32-bit absolute. */
121 /* For inserting an extra jmp instruction with long offset on 68000,
122 for expanding conditional branches. (Not bsr or bra.) Since the
123 68000 doesn't support 32-bit displacements for conditional
124 branches, we fake it by reversing the condition and branching
125 around a jmp with an absolute long operand. */
127 /* For the DBcc "instructions". If the displacement requires 32 bits,
128 the branch-around-a-jump game is played here too. */
130 /* Not currently used? */
132 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
138 const char *m_operands;
139 unsigned long m_opcode;
143 struct m68k_incant *m_next;
146 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147 #define gettwo(x) (((x)->m_opcode)&0xffff)
149 static const enum m68k_register m68000_control_regs[] = { 0 };
150 static const enum m68k_register m68010_control_regs[] = {
154 static const enum m68k_register m68020_control_regs[] = {
155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 static const enum m68k_register m68040_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 static const enum m68k_register m68060_control_regs[] = {
164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
168 static const enum m68k_register mcf5200_control_regs[] = {
169 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
170 RAMBAR0, RAMBAR1, MBAR,
173 #define cpu32_control_regs m68010_control_regs
175 static const enum m68k_register *control_regs;
177 /* internal form of a 68020 instruction */
181 const char *args; /* list of opcode info */
184 int numo; /* Number of shorts in opcode */
187 struct m68k_op operands[6];
189 int nexp; /* number of exprs in use */
190 struct m68k_exp exprs[4];
192 int nfrag; /* Number of frags we have to produce */
195 int fragoff; /* Where in the current opcode the frag ends */
202 int nrel; /* Num of reloc strucs in use */
209 /* In a pc relative address the difference between the address
210 of the offset and the address that the offset is relative
211 to. This depends on the addressing mode. Basically this
212 is the value to put in the offset field to address the
213 first byte of the offset, without regarding the special
214 significance of some values (in the branch instruction, for
218 /* Whether this expression needs special pic relocation, and if
220 enum pic_relocation pic_reloc;
223 reloc[5]; /* Five is enough??? */
226 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
227 #define float_of_arch(x) ((x) & mfloat)
228 #define mmu_of_arch(x) ((x) & mmmu)
230 static struct m68k_it the_ins; /* the instruction being assembled */
232 #define op(ex) ((ex)->exp.X_op)
233 #define adds(ex) ((ex)->exp.X_add_symbol)
234 #define subs(ex) ((ex)->exp.X_op_symbol)
235 #define offs(ex) ((ex)->exp.X_add_number)
237 /* Macros for adding things to the m68k_it struct */
239 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
241 /* Like addword, but goes BEFORE general operands */
245 struct m68k_incant *opcode;
248 for(z=the_ins.numo;z>opcode->m_codenum;--z)
249 the_ins.opcode[z]=the_ins.opcode[z-1];
250 for(z=0;z<the_ins.nrel;z++)
251 the_ins.reloc[z].n+=2;
252 for (z = 0; z < the_ins.nfrag; z++)
253 the_ins.fragb[z].fragoff++;
254 the_ins.opcode[opcode->m_codenum]=w;
258 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
261 add_fix (width, exp, pc_rel, pc_fix)
263 struct m68k_exp *exp;
267 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
271 : (the_ins.numo*2)));
272 the_ins.reloc[the_ins.nrel].exp = exp->exp;
273 the_ins.reloc[the_ins.nrel].wid = width;
274 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
276 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
278 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
281 /* Cause an extra frag to be generated here, inserting up to 10 bytes
282 (that value is chosen in the frag_var call in md_assemble). TYPE
283 is the subtype of the frag to be generated; its primary type is
284 rs_machine_dependent.
286 The TYPE parameter is also used by md_convert_frag_1 and
287 md_estimate_size_before_relax. The appropriate type of fixup will
288 be emitted by md_convert_frag_1.
290 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
292 add_frag(add,off,type)
297 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
298 the_ins.fragb[the_ins.nfrag].fadd=add;
299 the_ins.fragb[the_ins.nfrag].foff=off;
300 the_ins.fragb[the_ins.nfrag++].fragty=type;
304 (op (ex) != O_constant && op (ex) != O_big)
306 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
307 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
308 static int reverse_16_bits PARAMS ((int in));
309 static int reverse_8_bits PARAMS ((int in));
310 static void install_gen_operand PARAMS ((int mode, int val));
311 static void install_operand PARAMS ((int mode, int val));
312 static void s_bss PARAMS ((int));
313 static void s_data1 PARAMS ((int));
314 static void s_data2 PARAMS ((int));
315 static void s_even PARAMS ((int));
316 static void s_proc PARAMS ((int));
317 static void mri_chip PARAMS ((void));
318 static void s_chip PARAMS ((int));
319 static void s_fopt PARAMS ((int));
320 static void s_opt PARAMS ((int));
321 static void s_reg PARAMS ((int));
322 static void s_restore PARAMS ((int));
323 static void s_save PARAMS ((int));
324 static void s_mri_if PARAMS ((int));
325 static void s_mri_else PARAMS ((int));
326 static void s_mri_endi PARAMS ((int));
327 static void s_mri_break PARAMS ((int));
328 static void s_mri_next PARAMS ((int));
329 static void s_mri_for PARAMS ((int));
330 static void s_mri_endf PARAMS ((int));
331 static void s_mri_repeat PARAMS ((int));
332 static void s_mri_until PARAMS ((int));
333 static void s_mri_while PARAMS ((int));
334 static void s_mri_endw PARAMS ((int));
336 static int current_architecture;
344 static const struct m68k_cpu archs[] = {
345 { m68000, "68000", 0 },
346 { m68010, "68010", 0 },
347 { m68020, "68020", 0 },
348 { m68030, "68030", 0 },
349 { m68040, "68040", 0 },
350 { m68060, "68060", 0 },
351 { cpu32, "cpu32", 0 },
352 { m68881, "68881", 0 },
353 { m68851, "68851", 0 },
354 { mcf5200, "5200", 0 },
355 /* Aliases (effectively, so far as gas is concerned) for the above
357 { m68020, "68k", 1 },
358 { m68000, "68302", 1 },
359 { m68000, "68008", 1 },
360 { m68000, "68ec000", 1 },
361 { m68000, "68hc000", 1 },
362 { m68000, "68hc001", 1 },
363 { m68020, "68ec020", 1 },
364 { m68030, "68ec030", 1 },
365 { m68040, "68ec040", 1 },
366 { m68060, "68ec060", 1 },
367 { cpu32, "68330", 1 },
368 { cpu32, "68331", 1 },
369 { cpu32, "68332", 1 },
370 { cpu32, "68333", 1 },
371 { cpu32, "68340", 1 },
372 { cpu32, "68360", 1 },
373 { m68881, "68882", 1 },
376 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
378 /* BCC68000 is for patching in an extra jmp instruction for long offsets
379 on the 68000. The 68000 doesn't support long branches with branchs */
381 /* This table desribes how you change sizes for the various types of variable
382 size expressions. This version only supports two kinds. */
384 /* Note that calls to frag_var need to specify the maximum expansion
385 needed; this is currently 10 bytes for DBCC. */
388 How far Forward this mode will reach:
389 How far Backward this mode will reach:
390 How many bytes this mode will add to the size of the frag
391 Which mode to go to if the offset won't fit in this one
393 relax_typeS md_relax_table[] =
395 {1, 1, 0, 0}, /* First entries aren't used */
396 {1, 1, 0, 0}, /* For no good reason except */
397 {1, 1, 0, 0}, /* that the VAX doesn't either */
400 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
401 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
405 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
406 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
410 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
411 {(32767), (-32768), 2, TAB (PCREL, LONG)},
415 {(127), (-128), 0, TAB (BCC68000, SHORT)},
416 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
417 {0, 0, 6, 0}, /* jmp long space */
420 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
421 {(32767), (-32768), 2, TAB (DBCC, LONG)},
422 {0, 0, 10, 0}, /* bra/jmp long space */
425 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
426 {32767, -32768, 2, TAB (PCLEA, LONG)},
430 /* For, e.g., jmp pcrel indexed. */
431 {125, -130, 0, TAB (PCINDEX, SHORT)},
432 {32765, -32770, 2, TAB (PCINDEX, LONG)},
437 /* These are the machine dependent pseudo-ops. These are included so
438 the assembler can work on the output from the SUN C compiler, which
442 /* This table describes all the machine specific pseudo-ops the assembler
443 has to support. The fields are:
444 pseudo-op name without dot
445 function to call to execute this pseudo-op
446 Integer arg to pass to the function
448 const pseudo_typeS md_pseudo_table[] =
450 {"data1", s_data1, 0},
451 {"data2", s_data2, 0},
454 {"skip", s_space, 0},
456 #if defined (TE_SUN3) || defined (OBJ_ELF)
457 {"align", s_align_bytes, 0},
460 {"swbeg", s_ignore, 0},
462 {"extend", float_cons, 'x'},
463 {"ldouble", float_cons, 'x'},
465 /* The following pseudo-ops are supported for MRI compatibility. */
467 {"comline", s_space, 1},
469 {"mask2", s_ignore, 0},
472 {"restore", s_restore, 0},
476 {"if.b", s_mri_if, 'b'},
477 {"if.w", s_mri_if, 'w'},
478 {"if.l", s_mri_if, 'l'},
479 {"else", s_mri_else, 0},
480 {"else.s", s_mri_else, 's'},
481 {"else.l", s_mri_else, 'l'},
482 {"endi", s_mri_endi, 0},
483 {"break", s_mri_break, 0},
484 {"break.s", s_mri_break, 's'},
485 {"break.l", s_mri_break, 'l'},
486 {"next", s_mri_next, 0},
487 {"next.s", s_mri_next, 's'},
488 {"next.l", s_mri_next, 'l'},
489 {"for", s_mri_for, 0},
490 {"for.b", s_mri_for, 'b'},
491 {"for.w", s_mri_for, 'w'},
492 {"for.l", s_mri_for, 'l'},
493 {"endf", s_mri_endf, 0},
494 {"repeat", s_mri_repeat, 0},
495 {"until", s_mri_until, 0},
496 {"until.b", s_mri_until, 'b'},
497 {"until.w", s_mri_until, 'w'},
498 {"until.l", s_mri_until, 'l'},
499 {"while", s_mri_while, 0},
500 {"while.b", s_mri_while, 'b'},
501 {"while.w", s_mri_while, 'w'},
502 {"while.l", s_mri_while, 'l'},
503 {"endw", s_mri_endw, 0},
509 /* The mote pseudo ops are put into the opcode table, since they
510 don't start with a . they look like opcodes to gas.
512 extern void obj_coff_section ();
514 CONST pseudo_typeS mote_pseudo_table[] =
527 {"xdef", s_globl, 0},
529 {"align", s_align_bytes, 0},
531 {"align", s_align_ptwo, 0},
534 {"sect", obj_coff_section, 0},
535 {"section", obj_coff_section, 0},
540 #define issbyte(x) ((x)>=-128 && (x)<=127)
541 #define isubyte(x) ((x)>=0 && (x)<=255)
542 #define issword(x) ((x)>=-32768 && (x)<=32767)
543 #define isuword(x) ((x)>=0 && (x)<=65535)
545 #define isbyte(x) ((x)>= -255 && (x)<=255)
546 #define isword(x) ((x)>=-65536 && (x)<=65535)
547 #define islong(x) (1)
549 extern char *input_line_pointer;
551 static char mklower_table[256];
552 #define mklower(c) (mklower_table[(unsigned char)(c)])
553 static char notend_table[256];
554 static char alt_notend_table[256];
556 (! (notend_table[(unsigned char) *s] \
558 && alt_notend_table[(unsigned char) s[1]])))
560 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
562 #ifdef NO_PCREL_RELOCS
565 make_pcrel_absolute(fixP, add_number)
569 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
571 /* rewrite the PC relative instructions to absolute address ones.
572 * these are rumoured to be faster, and the apollo linker refuses
573 * to deal with the PC relative relocations.
575 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
580 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
586 as_fatal ("Unknown PC relative instruction");
591 #endif /* NO_PCREL_RELOCS */
594 tc_coff_fix2rtype (fixP)
597 if (fixP->fx_tcbit && fixP->fx_size == 4)
598 return R_RELLONG_NEG;
599 #ifdef NO_PCREL_RELOCS
600 know (fixP->fx_pcrel == 0);
601 return (fixP->fx_size == 1 ? R_RELBYTE
602 : fixP->fx_size == 2 ? R_DIR16
605 return (fixP->fx_pcrel ?
606 (fixP->fx_size == 1 ? R_PCRBYTE :
607 fixP->fx_size == 2 ? R_PCRWORD :
609 (fixP->fx_size == 1 ? R_RELBYTE :
610 fixP->fx_size == 2 ? R_RELWORD :
619 /* Compute the relocation code for a fixup of SIZE bytes, using pc
620 relative relocation if PCREL is non-zero. PIC says whether a special
621 pic relocation was requested. */
623 static bfd_reloc_code_real_type get_reloc_code
624 PARAMS ((int, int, enum pic_relocation));
626 static bfd_reloc_code_real_type
627 get_reloc_code (size, pcrel, pic)
630 enum pic_relocation pic;
638 return BFD_RELOC_8_GOT_PCREL;
640 return BFD_RELOC_16_GOT_PCREL;
642 return BFD_RELOC_32_GOT_PCREL;
650 return BFD_RELOC_8_GOTOFF;
652 return BFD_RELOC_16_GOTOFF;
654 return BFD_RELOC_32_GOTOFF;
662 return BFD_RELOC_8_PLT_PCREL;
664 return BFD_RELOC_16_PLT_PCREL;
666 return BFD_RELOC_32_PLT_PCREL;
674 return BFD_RELOC_8_PLTOFF;
676 return BFD_RELOC_16_PLTOFF;
678 return BFD_RELOC_32_PLTOFF;
688 return BFD_RELOC_8_PCREL;
690 return BFD_RELOC_16_PCREL;
692 return BFD_RELOC_32_PCREL;
709 as_bad ("Can not do %d byte %s%srelocation", size,
710 pcrel ? "pc-relative " : "",
711 pic == pic_none ? "" : "pic ");
712 return BFD_RELOC_NONE;
715 /* Here we decide which fixups can be adjusted to make them relative
716 to the beginning of the section instead of the symbol. Basically
717 we need to make sure that the dynamic relocations are done
718 correctly, so in some cases we force the original symbol to be
721 tc_m68k_fix_adjustable (fixP)
724 /* Prevent all adjustments to global symbols. */
725 if (S_IS_EXTERNAL (fixP->fx_addsy))
728 /* adjust_reloc_syms doesn't know about the GOT */
729 switch (fixP->fx_r_type)
731 case BFD_RELOC_8_GOT_PCREL:
732 case BFD_RELOC_16_GOT_PCREL:
733 case BFD_RELOC_32_GOT_PCREL:
734 case BFD_RELOC_8_GOTOFF:
735 case BFD_RELOC_16_GOTOFF:
736 case BFD_RELOC_32_GOTOFF:
737 case BFD_RELOC_8_PLT_PCREL:
738 case BFD_RELOC_16_PLT_PCREL:
739 case BFD_RELOC_32_PLT_PCREL:
740 case BFD_RELOC_8_PLTOFF:
741 case BFD_RELOC_16_PLTOFF:
742 case BFD_RELOC_32_PLTOFF:
752 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
759 tc_gen_reloc (section, fixp)
764 bfd_reloc_code_real_type code;
769 if (fixp->fx_r_type != BFD_RELOC_NONE)
771 code = fixp->fx_r_type;
773 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
774 that fixup_segment converted a non-PC relative reloc into a
775 PC relative reloc. In such a case, we need to convert the
782 code = BFD_RELOC_8_PCREL;
785 code = BFD_RELOC_16_PCREL;
788 code = BFD_RELOC_32_PCREL;
790 case BFD_RELOC_8_PCREL:
791 case BFD_RELOC_16_PCREL:
792 case BFD_RELOC_32_PCREL:
793 case BFD_RELOC_8_GOT_PCREL:
794 case BFD_RELOC_16_GOT_PCREL:
795 case BFD_RELOC_32_GOT_PCREL:
796 case BFD_RELOC_8_GOTOFF:
797 case BFD_RELOC_16_GOTOFF:
798 case BFD_RELOC_32_GOTOFF:
799 case BFD_RELOC_8_PLT_PCREL:
800 case BFD_RELOC_16_PLT_PCREL:
801 case BFD_RELOC_32_PLT_PCREL:
802 case BFD_RELOC_8_PLTOFF:
803 case BFD_RELOC_16_PLTOFF:
804 case BFD_RELOC_32_PLTOFF:
807 as_bad_where (fixp->fx_file, fixp->fx_line,
808 "Cannot make %s relocation PC relative",
809 bfd_get_reloc_code_name (code));
815 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
816 switch (F (fixp->fx_size, fixp->fx_pcrel))
818 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
819 MAP (1, 0, BFD_RELOC_8);
820 MAP (2, 0, BFD_RELOC_16);
821 MAP (4, 0, BFD_RELOC_32);
822 MAP (1, 1, BFD_RELOC_8_PCREL);
823 MAP (2, 1, BFD_RELOC_16_PCREL);
824 MAP (4, 1, BFD_RELOC_32_PCREL);
832 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
834 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
835 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
838 reloc->addend = fixp->fx_addnumber;
843 reloc->addend = fixp->fx_addnumber;
845 reloc->addend = (section->vma
846 + (fixp->fx_pcrel_adjust == 64
847 ? -1 : fixp->fx_pcrel_adjust)
849 + md_pcrel_from (fixp));
852 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
853 assert (reloc->howto != 0);
858 #endif /* BFD_ASSEMBLER */
860 /* Handle of the OPCODE hash table. NULL means any use before
861 m68k_ip_begin() will crash. */
862 static struct hash_control *op_hash;
864 /* Assemble an m68k instruction. */
871 register struct m68k_op *opP;
872 register struct m68k_incant *opcode;
873 register const char *s;
874 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
875 char *pdot, *pdotmove;
876 enum m68k_size siz1, siz2;
880 char *crack_operand ();
881 LITTLENUM_TYPE words[6];
882 LITTLENUM_TYPE *wordp;
883 unsigned long ok_arch = 0;
885 if (*instring == ' ')
886 instring++; /* skip leading whitespace */
888 /* Scan up to end of operation-code, which MUST end in end-of-string
889 or exactly 1 space. */
891 for (p = instring; *p != '\0'; p++)
901 the_ins.error = "No operator";
905 /* p now points to the end of the opcode name, probably whitespace.
906 Make sure the name is null terminated by clobbering the
907 whitespace, look it up in the hash table, then fix it back.
908 Remove a dot, first, since the opcode tables have none. */
911 for (pdotmove = pdot; pdotmove < p; pdotmove++)
912 *pdotmove = pdotmove[1];
918 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
923 for (pdotmove = p; pdotmove > pdot; pdotmove--)
924 *pdotmove = pdotmove[-1];
931 the_ins.error = "Unknown operator";
935 /* found a legitimate opcode, start matching operands */
939 if (opcode->m_operands == 0)
941 char *old = input_line_pointer;
943 input_line_pointer = p;
944 /* Ahh - it's a motorola style psuedo op */
945 mote_pseudo_table[opcode->m_opnum].poc_handler
946 (mote_pseudo_table[opcode->m_opnum].poc_val);
947 input_line_pointer = old;
953 if (flag_mri && opcode->m_opnum == 0)
955 /* In MRI mode, random garbage is allowed after an instruction
956 which accepts no operands. */
957 the_ins.args = opcode->m_operands;
958 the_ins.numargs = opcode->m_opnum;
959 the_ins.numo = opcode->m_codenum;
960 the_ins.opcode[0] = getone (opcode);
961 the_ins.opcode[1] = gettwo (opcode);
965 for (opP = &the_ins.operands[0]; *p; opP++)
967 p = crack_operand (p, opP);
971 the_ins.error = opP->error;
976 opsfound = opP - &the_ins.operands[0];
978 /* This ugly hack is to support the floating pt opcodes in their
979 standard form. Essentially, we fake a first enty of type COP#1 */
980 if (opcode->m_operands[0] == 'I')
984 for (n = opsfound; n > 0; --n)
985 the_ins.operands[n] = the_ins.operands[n - 1];
987 memset ((char *) (&the_ins.operands[0]), '\0',
988 sizeof (the_ins.operands[0]));
989 the_ins.operands[0].mode = CONTROL;
990 the_ins.operands[0].reg = m68k_float_copnum;
994 /* We've got the operands. Find an opcode that'll accept them */
997 /* If we didn't get the right number of ops, or we have no
998 common model with this pattern then reject this pattern. */
1000 ok_arch |= opcode->m_arch;
1001 if (opsfound != opcode->m_opnum
1002 || ((opcode->m_arch & current_architecture) == 0))
1006 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1010 /* Warning: this switch is huge! */
1011 /* I've tried to organize the cases into this order:
1012 non-alpha first, then alpha by letter. Lower-case
1013 goes directly before uppercase counterpart. */
1014 /* Code with multiple case ...: gets sorted by the lowest
1015 case ... it belongs to. I hope this makes sense. */
1145 if (opP->mode != IMMED)
1147 else if (s[1] == 'b'
1148 && ! isvar (&opP->disp)
1149 && (opP->disp.exp.X_op != O_constant
1150 || ! isbyte (opP->disp.exp.X_add_number)))
1152 else if (s[1] == 'w'
1153 && ! isvar (&opP->disp)
1154 && (opP->disp.exp.X_op != O_constant
1155 || ! isword (opP->disp.exp.X_add_number)))
1157 else if (s[1] == 'W'
1158 && ! isvar (&opP->disp)
1159 && (opP->disp.exp.X_op != O_constant
1160 || ! issword (opP->disp.exp.X_add_number)))
1166 if (opP->mode != IMMED)
1171 if (opP->mode == AREG
1172 || opP->mode == CONTROL
1173 || opP->mode == FPREG
1174 || opP->mode == IMMED
1175 || opP->mode == REGLST
1176 || (opP->mode != ABSL
1178 || opP->reg == ZPC)))
1183 if (opP->mode == CONTROL
1184 || opP->mode == FPREG
1185 || opP->mode == REGLST
1186 || opP->mode == IMMED
1187 || (opP->mode != ABSL
1189 || opP->reg == ZPC)))
1217 if (opP->mode == CONTROL
1218 || opP->mode == FPREG
1219 || opP->mode == REGLST)
1224 if (opP->mode != AINC)
1229 if (opP->mode != ADEC)
1279 if (opP->reg == PC || opP->reg == ZPC)
1300 case '~': /* For now! (JF FOO is this right?) */
1322 if (opP->mode != CONTROL
1323 || (opP->reg != TT0 && opP->reg != TT1))
1328 if (opP->mode != AREG)
1333 if (opP->mode != AINDR)
1338 if (opP->mode != ABSL
1340 && strncmp (instring, "jbsr", 4) == 0))
1345 if (opP->mode != CONTROL || opP->reg != CCR)
1350 if (opP->mode != DISP
1352 || opP->reg > ADDR7)
1357 if (opP->mode != DREG)
1362 if (opP->mode != FPREG)
1367 if (opP->mode != CONTROL
1374 if (opP->mode != CONTROL
1376 || opP->reg > last_movec_reg)
1380 const enum m68k_register *rp;
1381 for (rp = control_regs; *rp; rp++)
1382 if (*rp == opP->reg)
1390 if (opP->mode != IMMED)
1396 if (opP->mode == DREG
1397 || opP->mode == AREG
1398 || opP->mode == FPREG)
1407 opP->mask = 1 << (opP->reg - DATA0);
1410 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1413 opP->mask = 1 << (opP->reg - FP0 + 16);
1421 else if (opP->mode == CONTROL)
1430 opP->mask = 1 << 24;
1433 opP->mask = 1 << 25;
1436 opP->mask = 1 << 26;
1445 else if (opP->mode == ABSL
1446 && opP->disp.size == SIZE_UNSPEC
1447 && opP->disp.exp.X_op == O_constant)
1449 /* This is what the MRI REG pseudo-op generates. */
1451 opP->mask = opP->disp.exp.X_add_number;
1453 else if (opP->mode != REGLST)
1455 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1457 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1462 if (opP->mode != IMMED)
1464 else if (opP->disp.exp.X_op != O_constant
1465 || ! issbyte (opP->disp.exp.X_add_number))
1467 else if (! m68k_quick
1468 && instring[3] != 'q'
1469 && instring[4] != 'q')
1474 if (opP->mode != DREG
1475 && opP->mode != IMMED
1476 && opP->mode != ABSL)
1481 if (opP->mode != IMMED)
1483 else if (opP->disp.exp.X_op != O_constant
1484 || opP->disp.exp.X_add_number < 1
1485 || opP->disp.exp.X_add_number > 8)
1487 else if (! m68k_quick
1488 && (strncmp (instring, "add", 3) == 0
1489 || strncmp (instring, "sub", 3) == 0)
1490 && instring[3] != 'q')
1495 if (opP->mode != DREG && opP->mode != AREG)
1500 if (opP->mode != AINDR
1501 && (opP->mode != BASE
1503 && opP->reg != ZADDR0)
1504 || opP->disp.exp.X_op != O_absent
1505 || ((opP->index.reg < DATA0
1506 || opP->index.reg > DATA7)
1507 && (opP->index.reg < ADDR0
1508 || opP->index.reg > ADDR7))
1509 || opP->index.size != SIZE_UNSPEC
1510 || opP->index.scale != 1))
1515 if (opP->mode != CONTROL
1516 || ! (opP->reg == FPI
1518 || opP->reg == FPC))
1523 if (opP->mode != CONTROL || opP->reg != SR)
1528 if (opP->mode != IMMED)
1530 else if (opP->disp.exp.X_op != O_constant
1531 || opP->disp.exp.X_add_number < 0
1532 || opP->disp.exp.X_add_number > 7)
1537 if (opP->mode != CONTROL || opP->reg != USP)
1541 /* JF these are out of order. We could put them
1542 in order if we were willing to put up with
1543 bunches of #ifdef m68851s in the code.
1545 Don't forget that you need these operands
1546 to use 68030 MMU instructions. */
1548 /* Memory addressing mode used by pflushr */
1550 if (opP->mode == CONTROL
1551 || opP->mode == FPREG
1552 || opP->mode == DREG
1553 || opP->mode == AREG
1554 || opP->mode == REGLST)
1556 /* We should accept immediate operands, but they
1557 supposedly have to be quad word, and we don't
1558 handle that. I would like to see what a Motorola
1559 assembler does before doing something here. */
1560 if (opP->mode == IMMED)
1565 if (opP->mode != CONTROL
1566 || (opP->reg != SFC && opP->reg != DFC))
1571 if (opP->mode != CONTROL || opP->reg != TC)
1576 if (opP->mode != CONTROL || opP->reg != AC)
1581 if (opP->mode != CONTROL
1584 && opP->reg != SCC))
1589 if (opP->mode != CONTROL
1595 if (opP->mode != CONTROL
1598 && opP->reg != CRP))
1603 if (opP->mode != CONTROL
1604 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1605 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1610 if (opP->mode != CONTROL || opP->reg != PSR)
1615 if (opP->mode != CONTROL || opP->reg != PCSR)
1620 if (opP->mode != CONTROL
1627 } /* not a cache specifier. */
1631 if (opP->mode != ABSL)
1637 } /* switch on type of operand */
1641 } /* for each operand */
1642 } /* if immediately wrong */
1649 opcode = opcode->m_next;
1654 && !(ok_arch & current_architecture))
1659 "invalid instruction for this architecture; needs ");
1660 cp = buf + strlen (buf);
1664 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1667 strcpy (cp, "mmu (68030 or 68851)");
1670 strcpy (cp, "68020 or higher");
1673 strcpy (cp, "68000 or higher");
1676 strcpy (cp, "68010 or higher");
1680 int got_one = 0, idx;
1681 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1684 if ((archs[idx].arch & ok_arch)
1685 && ! archs[idx].alias)
1689 strcpy (cp, " or ");
1693 strcpy (cp, archs[idx].name);
1699 cp = xmalloc (strlen (buf) + 1);
1704 the_ins.error = "operands mismatch";
1706 } /* Fell off the end */
1711 /* now assemble it */
1713 the_ins.args = opcode->m_operands;
1714 the_ins.numargs = opcode->m_opnum;
1715 the_ins.numo = opcode->m_codenum;
1716 the_ins.opcode[0] = getone (opcode);
1717 the_ins.opcode[1] = gettwo (opcode);
1719 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1721 /* This switch is a doozy.
1722 Watch the first step; its a big one! */
1749 tmpreg = 0x3c; /* 7.4 */
1750 if (strchr ("bwl", s[1]))
1751 nextword = get_num (&opP->disp, 80);
1753 nextword = get_num (&opP->disp, 0);
1754 if (isvar (&opP->disp))
1755 add_fix (s[1], &opP->disp, 0, 0);
1759 if (!isbyte (nextword))
1760 opP->error = "operand out of range";
1765 if (!isword (nextword))
1766 opP->error = "operand out of range";
1771 if (!issword (nextword))
1772 opP->error = "operand out of range";
1777 addword (nextword >> 16);
1804 /* We gotta put out some float */
1805 if (op (&opP->disp) != O_big)
1810 /* Can other cases happen here? */
1811 if (op (&opP->disp) != O_constant)
1814 val = (valueT) offs (&opP->disp);
1818 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1819 val >>= LITTLENUM_NUMBER_OF_BITS;
1823 offs (&opP->disp) = gencnt;
1825 if (offs (&opP->disp) > 0)
1827 if (offs (&opP->disp) > baseo)
1829 as_warn ("Bignum too big for %c format; truncated",
1831 offs (&opP->disp) = baseo;
1833 baseo -= offs (&opP->disp);
1836 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1837 offs (&opP->disp)--;
1842 gen_to_words (words, baseo, (long) outro);
1843 for (wordp = words; baseo--; wordp++)
1847 tmpreg = opP->reg - DATA; /* 0.dreg */
1850 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1853 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1856 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1859 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1863 nextword = get_num (&opP->disp, 80);
1866 && ! isvar (&opP->disp)
1869 opP->disp.exp.X_op = O_symbol;
1870 #ifndef BFD_ASSEMBLER
1871 opP->disp.exp.X_add_symbol = &abs_symbol;
1873 opP->disp.exp.X_add_symbol =
1874 section_symbol (absolute_section);
1878 /* Force into index mode. Hope this works */
1880 /* We do the first bit for 32-bit displacements, and the
1881 second bit for 16 bit ones. It is possible that we
1882 should make the default be WORD instead of LONG, but
1883 I think that'd break GCC, so we put up with a little
1884 inefficiency for the sake of working output. */
1886 if (!issword (nextword)
1887 || (isvar (&opP->disp)
1888 && ((opP->disp.size == SIZE_UNSPEC
1889 && flag_short_refs == 0
1890 && cpu_of_arch (current_architecture) >= m68020)
1891 || opP->disp.size == SIZE_LONG)))
1893 if (cpu_of_arch (current_architecture) < m68020)
1895 "displacement too large for this architecture; needs 68020 or higher";
1897 tmpreg = 0x3B; /* 7.3 */
1899 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1900 if (isvar (&opP->disp))
1904 if (opP->disp.size == SIZE_LONG
1906 /* If the displacement needs pic
1907 relocation it cannot be relaxed. */
1908 || opP->disp.pic_reloc != pic_none
1913 add_fix ('l', &opP->disp, 1, 2);
1917 add_frag (adds (&opP->disp),
1919 TAB (PCLEA, SZ_UNDEF));
1926 add_fix ('l', &opP->disp, 0, 0);
1931 addword (nextword >> 16);
1936 tmpreg = 0x3A; /* 7.2 */
1938 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1940 if (isvar (&opP->disp))
1944 add_fix ('w', &opP->disp, 1, 0);
1947 add_fix ('w', &opP->disp, 0, 0);
1957 baseo = get_num (&opP->disp, 80);
1958 if (opP->mode == POST || opP->mode == PRE)
1959 outro = get_num (&opP->odisp, 80);
1960 /* Figure out the `addressing mode'.
1961 Also turn on the BASE_DISABLE bit, if needed. */
1962 if (opP->reg == PC || opP->reg == ZPC)
1964 tmpreg = 0x3b; /* 7.3 */
1965 if (opP->reg == ZPC)
1968 else if (opP->reg == 0)
1971 tmpreg = 0x30; /* 6.garbage */
1973 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1976 tmpreg = 0x30 + opP->reg - ZADDR0;
1979 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1981 siz1 = opP->disp.size;
1982 if (opP->mode == POST || opP->mode == PRE)
1983 siz2 = opP->odisp.size;
1987 /* Index register stuff */
1988 if (opP->index.reg != 0
1989 && opP->index.reg >= DATA
1990 && opP->index.reg <= ADDR7)
1992 nextword |= (opP->index.reg - DATA) << 12;
1994 if (opP->index.size == SIZE_LONG
1995 || (opP->index.size == SIZE_UNSPEC
1996 && m68k_index_width_default == SIZE_LONG))
1999 if ((opP->index.scale != 1
2000 && cpu_of_arch (current_architecture) < m68020)
2001 || (opP->index.scale == 8
2002 && current_architecture == mcf5200))
2005 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2008 switch (opP->index.scale)
2025 GET US OUT OF HERE! */
2027 /* Must be INDEX, with an index register. Address
2028 register cannot be ZERO-PC, and either :b was
2029 forced, or we know it will fit. For a 68000 or
2030 68010, force this mode anyways, because the
2031 larger modes aren't supported. */
2032 if (opP->mode == BASE
2033 && ((opP->reg >= ADDR0
2034 && opP->reg <= ADDR7)
2037 if (siz1 == SIZE_BYTE
2038 || cpu_of_arch (current_architecture) < m68020
2039 || (siz1 == SIZE_UNSPEC
2040 && ! isvar (&opP->disp)
2041 && issbyte (baseo)))
2043 nextword += baseo & 0xff;
2045 if (isvar (&opP->disp))
2047 /* Do a byte relocation. If it doesn't
2048 fit (possible on m68000) let the
2049 fixup processing complain later. */
2051 add_fix ('B', &opP->disp, 1, 1);
2053 add_fix ('B', &opP->disp, 0, 0);
2055 else if (siz1 != SIZE_BYTE)
2057 if (siz1 != SIZE_UNSPEC)
2058 as_warn ("Forcing byte displacement");
2059 if (! issbyte (baseo))
2060 opP->error = "byte displacement out of range";
2065 else if (siz1 == SIZE_UNSPEC
2067 && isvar (&opP->disp)
2068 && subs (&opP->disp) == NULL
2070 /* If the displacement needs pic
2071 relocation it cannot be relaxed. */
2072 && opP->disp.pic_reloc == pic_none
2076 nextword += baseo & 0xff;
2078 add_frag (adds (&opP->disp), offs (&opP->disp),
2079 TAB (PCINDEX, SZ_UNDEF));
2087 nextword |= 0x40; /* No index reg */
2088 if (opP->index.reg >= ZDATA0
2089 && opP->index.reg <= ZDATA7)
2090 nextword |= (opP->index.reg - ZDATA0) << 12;
2091 else if (opP->index.reg >= ZADDR0
2092 || opP->index.reg <= ZADDR7)
2093 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2096 /* It isn't simple. */
2098 if (cpu_of_arch (current_architecture) < m68020)
2100 "invalid operand mode for this architecture; needs 68020 or higher";
2103 /* If the guy specified a width, we assume that it is
2104 wide enough. Maybe it isn't. If so, we lose. */
2108 if (isvar (&opP->disp)
2110 : ! issword (baseo))
2115 else if (! isvar (&opP->disp) && baseo == 0)
2124 as_warn (":b not permitted; defaulting to :w");
2134 /* Figure out innner displacement stuff */
2135 if (opP->mode == POST || opP->mode == PRE)
2137 if (cpu_of_arch (current_architecture) & cpu32)
2138 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2142 if (isvar (&opP->odisp)
2144 : ! issword (outro))
2149 else if (! isvar (&opP->odisp) && outro == 0)
2158 as_warn (":b not permitted; defaulting to :w");
2167 if (opP->mode == POST
2168 && (nextword & 0x40) == 0)
2173 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2175 if (opP->reg == PC || opP->reg == ZPC)
2176 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2178 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2180 if (siz1 == SIZE_LONG)
2181 addword (baseo >> 16);
2182 if (siz1 != SIZE_UNSPEC)
2185 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2186 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2187 if (siz2 == SIZE_LONG)
2188 addword (outro >> 16);
2189 if (siz2 != SIZE_UNSPEC)
2195 nextword = get_num (&opP->disp, 80);
2196 switch (opP->disp.size)
2201 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2203 tmpreg = 0x38; /* 7.0 */
2207 /* Don't generate pc relative code on 68010 and
2209 if (isvar (&opP->disp)
2210 && !subs (&opP->disp)
2211 && adds (&opP->disp)
2213 /* If the displacement needs pic relocation it
2214 cannot be relaxed. */
2215 && opP->disp.pic_reloc == pic_none
2217 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2218 && cpu_of_arch (current_architecture) >= m68020
2220 && !strchr ("~%&$?", s[0]))
2222 tmpreg = 0x3A; /* 7.2 */
2223 add_frag (adds (&opP->disp),
2225 TAB (PCREL, SZ_UNDEF));
2228 /* Fall through into long */
2230 if (isvar (&opP->disp))
2231 add_fix ('l', &opP->disp, 0, 0);
2233 tmpreg = 0x39;/* 7.1 mode */
2234 addword (nextword >> 16);
2238 case SIZE_WORD: /* Word */
2239 if (isvar (&opP->disp))
2240 add_fix ('w', &opP->disp, 0, 0);
2242 tmpreg = 0x38;/* 7.0 mode */
2250 as_bad ("unknown/incorrect operand");
2253 install_gen_operand (s[1], tmpreg);
2259 { /* JF: I hate floating point! */
2274 tmpreg = get_num (&opP->disp, tmpreg);
2275 if (isvar (&opP->disp))
2276 add_fix (s[1], &opP->disp, 0, 0);
2279 case 'b': /* Danger: These do no check for
2280 certain types of overflow.
2282 if (!isbyte (tmpreg))
2283 opP->error = "out of range";
2284 insop (tmpreg, opcode);
2285 if (isvar (&opP->disp))
2286 the_ins.reloc[the_ins.nrel - 1].n =
2287 (opcode->m_codenum) * 2 + 1;
2290 if (!isword (tmpreg))
2291 opP->error = "out of range";
2292 insop (tmpreg, opcode);
2293 if (isvar (&opP->disp))
2294 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2297 if (!issword (tmpreg))
2298 opP->error = "out of range";
2299 insop (tmpreg, opcode);
2300 if (isvar (&opP->disp))
2301 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2304 /* Because of the way insop works, we put these two out
2306 insop (tmpreg, opcode);
2307 insop (tmpreg >> 16, opcode);
2308 if (isvar (&opP->disp))
2309 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2315 install_operand (s[1], tmpreg);
2326 install_operand (s[1], opP->reg - ADDR);
2330 tmpreg = get_num (&opP->disp, 80);
2334 /* The pc_fix argument winds up in fx_pcrel_adjust,
2335 which is a char, and may therefore be unsigned. We
2336 want to pass -1, but we pass 64 instead, and convert
2337 back in md_pcrel_from. */
2338 add_fix ('B', &opP->disp, 1, 64);
2341 add_fix ('w', &opP->disp, 1, 0);
2346 if (cpu_of_arch (current_architecture) < m68020)
2347 as_warn ("Can't use long branches on 68000/68010");
2348 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2349 add_fix ('l', &opP->disp, 1, 0);
2354 if (subs (&opP->disp)) /* We can't relax it */
2358 /* If the displacement needs pic relocation it cannot be
2360 if (opP->disp.pic_reloc != pic_none)
2364 /* This could either be a symbol, or an absolute
2365 address. No matter, the frag hacking will finger it
2366 out. Not quite: it can't switch from BRANCH to
2367 BCC68000 for the case where opnd is absolute (it
2368 needs to use the 68000 hack since no conditional abs
2370 if (((cpu_of_arch (current_architecture) < m68020)
2371 || (0 == adds (&opP->disp)))
2372 && (the_ins.opcode[0] >= 0x6200)
2373 && (the_ins.opcode[0] <= 0x6f00))
2374 add_frag (adds (&opP->disp), offs (&opP->disp),
2375 TAB (BCC68000, SZ_UNDEF));
2377 add_frag (adds (&opP->disp), offs (&opP->disp),
2378 TAB (ABRANCH, SZ_UNDEF));
2381 if (isvar (&opP->disp))
2384 /* check for DBcc instruction */
2385 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2387 /* size varies if patch */
2388 /* needed for long form */
2389 add_frag (adds (&opP->disp), offs (&opP->disp),
2390 TAB (DBCC, SZ_UNDEF));
2394 add_fix ('w', &opP->disp, 1, 0);
2398 case 'C': /* Fixed size LONG coproc branches */
2399 add_fix ('l', &opP->disp, 1, 0);
2403 case 'c': /* Var size Coprocesssor branches */
2404 if (subs (&opP->disp))
2406 add_fix ('l', &opP->disp, 1, 0);
2407 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2409 else if (adds (&opP->disp))
2410 add_frag (adds (&opP->disp), offs (&opP->disp),
2411 TAB (FBRANCH, SZ_UNDEF));
2414 /* add_frag((symbolS *) 0, offs(&opP->disp),
2415 TAB(FBRANCH,SHORT)); */
2416 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2417 add_fix ('l', &opP->disp, 1, 0);
2427 case 'C': /* Ignore it */
2430 case 'd': /* JF this is a kludge */
2431 install_operand ('s', opP->reg - ADDR);
2432 tmpreg = get_num (&opP->disp, 80);
2433 if (!issword (tmpreg))
2435 as_warn ("Expression out of range, using 0");
2442 install_operand (s[1], opP->reg - DATA);
2446 install_operand (s[1], opP->reg - FP0);
2450 tmpreg = opP->reg - COP0;
2451 install_operand (s[1], tmpreg);
2454 case 'J': /* JF foo */
2527 install_operand (s[1], tmpreg);
2531 tmpreg = get_num (&opP->disp, 55);
2532 install_operand (s[1], tmpreg & 0x7f);
2539 if (tmpreg & 0x7FF0000)
2540 as_bad ("Floating point register in register list");
2541 insop (reverse_16_bits (tmpreg), opcode);
2545 if (tmpreg & 0x700FFFF)
2546 as_bad ("Wrong register in floating-point reglist");
2547 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2555 if (tmpreg & 0x7FF0000)
2556 as_bad ("Floating point register in register list");
2557 insop (tmpreg, opcode);
2559 else if (s[1] == '8')
2561 if (tmpreg & 0x0FFFFFF)
2562 as_bad ("incorrect register in reglist");
2563 install_operand (s[1], tmpreg >> 24);
2567 if (tmpreg & 0x700FFFF)
2568 as_bad ("wrong register in floating-point reglist");
2570 install_operand (s[1], tmpreg >> 16);
2575 install_operand (s[1], get_num (&opP->disp, 60));
2579 tmpreg = ((opP->mode == DREG)
2580 ? 0x20 + opP->reg - DATA
2581 : (get_num (&opP->disp, 40) & 0x1F));
2582 install_operand (s[1], tmpreg);
2586 tmpreg = get_num (&opP->disp, 10);
2589 install_operand (s[1], tmpreg);
2593 /* This depends on the fact that ADDR registers are eight
2594 more than their corresponding DATA regs, so the result
2595 will have the ADDR_REG bit set */
2596 install_operand (s[1], opP->reg - DATA);
2600 if (opP->mode == AINDR)
2601 install_operand (s[1], opP->reg - DATA);
2603 install_operand (s[1], opP->index.reg - DATA);
2607 if (opP->reg == FPI)
2609 else if (opP->reg == FPS)
2611 else if (opP->reg == FPC)
2615 install_operand (s[1], tmpreg);
2618 case 'S': /* Ignore it */
2622 install_operand (s[1], get_num (&opP->disp, 30));
2625 case 'U': /* Ignore it */
2644 as_fatal ("failed sanity check");
2645 } /* switch on cache token */
2646 install_operand (s[1], tmpreg);
2649 /* JF: These are out of order, I fear. */
2662 install_operand (s[1], tmpreg);
2688 install_operand (s[1], tmpreg);
2692 if (opP->reg == VAL)
2711 install_operand (s[1], tmpreg);
2725 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2736 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2742 install_operand (s[1], tmpreg);
2745 know (opP->reg == PSR);
2748 know (opP->reg == PCSR);
2763 install_operand (s[1], tmpreg);
2766 tmpreg = get_num (&opP->disp, 20);
2767 install_operand (s[1], tmpreg);
2769 case '_': /* used only for move16 absolute 32-bit address */
2770 tmpreg = get_num (&opP->disp, 80);
2771 addword (tmpreg >> 16);
2772 addword (tmpreg & 0xFFFF);
2779 /* By the time whe get here (FINALLY) the_ins contains the complete
2780 instruction, ready to be emitted. . . */
2784 reverse_16_bits (in)
2790 static int mask[16] =
2792 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2793 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2795 for (n = 0; n < 16; n++)
2798 out |= mask[15 - n];
2801 } /* reverse_16_bits() */
2810 static int mask[8] =
2812 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2815 for (n = 0; n < 8; n++)
2821 } /* reverse_8_bits() */
2823 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2824 (that value is chosen in the frag_var call in md_assemble). TYPE
2825 is the subtype of the frag to be generated; its primary type is
2826 rs_machine_dependent.
2828 The TYPE parameter is also used by md_convert_frag_1 and
2829 md_estimate_size_before_relax. The appropriate type of fixup will
2830 be emitted by md_convert_frag_1.
2832 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2834 install_operand (mode, val)
2841 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2844 the_ins.opcode[0] |= val << 9;
2847 the_ins.opcode[1] |= val << 12;
2850 the_ins.opcode[1] |= val << 6;
2853 the_ins.opcode[1] |= val;
2856 the_ins.opcode[2] |= val << 12;
2859 the_ins.opcode[2] |= val << 6;
2862 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2863 three words long! */
2865 the_ins.opcode[2] |= val;
2868 the_ins.opcode[1] |= val << 7;
2871 the_ins.opcode[1] |= val << 10;
2875 the_ins.opcode[1] |= val << 5;
2880 the_ins.opcode[1] |= (val << 10) | (val << 7);
2883 the_ins.opcode[1] |= (val << 12) | val;
2886 the_ins.opcode[0] |= val = 0xff;
2889 the_ins.opcode[0] |= val << 9;
2892 the_ins.opcode[1] |= val;
2895 the_ins.opcode[1] |= val;
2896 the_ins.numo++; /* What a hack */
2899 the_ins.opcode[1] |= val << 4;
2907 the_ins.opcode[0] |= (val << 6);
2910 the_ins.opcode[1] = (val >> 16);
2911 the_ins.opcode[2] = val & 0xffff;
2915 as_fatal ("failed sanity check.");
2917 } /* install_operand() */
2920 install_gen_operand (mode, val)
2927 the_ins.opcode[0] |= val;
2930 /* This is a kludge!!! */
2931 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2940 the_ins.opcode[0] |= val;
2942 /* more stuff goes here */
2944 as_fatal ("failed sanity check.");
2946 } /* install_gen_operand() */
2949 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2950 * then deal with the bitfield hack.
2954 crack_operand (str, opP)
2956 register struct m68k_op *opP;
2958 register int parens;
2960 register char *beg_str;
2968 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2974 else if (*str == ')')
2978 opP->error = "Extra )";
2984 if (flag_mri && *str == '\'')
2985 inquote = ! inquote;
2987 if (!*str && parens)
2989 opP->error = "Missing )";
2994 if (m68k_ip_op (beg_str, opP) != 0)
3001 c = *++str; /* JF bitfield hack */
3006 as_bad ("Missing operand");
3011 /* This is the guts of the machine-dependent assembler. STR points to a
3012 machine dependent instruction. This function is supposed to emit
3013 the frags/bytes it assembles to.
3017 insert_reg (regname, regnum)
3024 #ifdef REGISTER_PREFIX
3025 if (!flag_reg_prefix_optional)
3027 buf[0] = REGISTER_PREFIX;
3028 strcpy (buf + 1, regname);
3033 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3034 &zero_address_frag));
3036 for (i = 0; regname[i]; i++)
3037 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3040 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3041 &zero_address_frag));
3050 static const struct init_entry init_table[] =
3105 /* control registers */
3106 { "sfc", SFC }, /* Source Function Code */
3108 { "dfc", DFC }, /* Destination Function Code */
3110 { "cacr", CACR }, /* Cache Control Register */
3111 { "caar", CAAR }, /* Cache Address Register */
3113 { "usp", USP }, /* User Stack Pointer */
3114 { "vbr", VBR }, /* Vector Base Register */
3115 { "msp", MSP }, /* Master Stack Pointer */
3116 { "isp", ISP }, /* Interrupt Stack Pointer */
3118 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3119 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3120 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3121 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3123 /* 68ec040 versions of same */
3124 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3125 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3126 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3127 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3129 /* mcf5200 versions of same. The ColdFire programmer's reference
3130 manual indicated that the order is 2,3,0,1, but Ken Rose
3131 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3132 { "acr0", ITT0 }, /* Access Control Unit 0 */
3133 { "acr1", ITT1 }, /* Access Control Unit 1 */
3134 { "acr2", DTT0 }, /* Access Control Unit 2 */
3135 { "acr3", DTT1 }, /* Access Control Unit 3 */
3137 { "tc", TC }, /* MMU Translation Control Register */
3140 { "mmusr", MMUSR }, /* MMU Status Register */
3141 { "srp", SRP }, /* User Root Pointer */
3142 { "urp", URP }, /* Supervisor Root Pointer */
3147 { "rombar", ROMBAR }, /* ROM Base Address Register */
3148 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3149 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3150 { "mbar", MBAR }, /* Module Base Address Register */
3151 /* end of control registers */
3185 /* 68ec030 versions of same */
3188 /* 68ec030 access control unit, identical to 030 MMU status reg */
3191 /* Suppressed data and address registers. */
3216 for (i = 0; init_table[i].name; i++)
3217 insert_reg (init_table[i].name, init_table[i].number);
3220 static int no_68851, no_68881;
3223 /* a.out machine type. Default to 68020. */
3224 int m68k_aout_machtype = 2;
3236 int shorts_this_frag;
3239 /* In MRI mode, the instruction and operands are separated by a
3240 space. Anything following the operands is a comment. The label
3241 has already been removed. */
3249 for (s = str; *s != '\0'; s++)
3251 if ((*s == ' ' || *s == '\t') && ! inquote)
3269 inquote = ! inquote;
3274 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3279 for (n = 0; n < the_ins.numargs; n++)
3280 if (the_ins.operands[n].error)
3282 er = the_ins.operands[n].error;
3288 as_bad ("%s -- statement `%s' ignored", er, str);
3292 if (the_ins.nfrag == 0)
3294 /* No frag hacking involved; just put it out */
3295 toP = frag_more (2 * the_ins.numo);
3296 fromP = &the_ins.opcode[0];
3297 for (m = the_ins.numo; m; --m)
3299 md_number_to_chars (toP, (long) (*fromP), 2);
3303 /* put out symbol-dependent info */
3304 for (m = 0; m < the_ins.nrel; m++)
3306 switch (the_ins.reloc[m].wid)
3324 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3325 the_ins.reloc[m].wid);
3328 fixP = fix_new_exp (frag_now,
3329 ((toP - frag_now->fr_literal)
3330 - the_ins.numo * 2 + the_ins.reloc[m].n),
3332 &the_ins.reloc[m].exp,
3333 the_ins.reloc[m].pcrel,
3334 get_reloc_code (n, the_ins.reloc[m].pcrel,
3335 the_ins.reloc[m].pic_reloc));
3336 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3341 /* There's some frag hacking */
3342 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3347 wid = 2 * the_ins.fragb[n].fragoff;
3349 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3350 toP = frag_more (wid);
3352 shorts_this_frag = 0;
3353 for (m = wid / 2; m; --m)
3355 md_number_to_chars (toP, (long) (*fromP), 2);
3360 for (m = 0; m < the_ins.nrel; m++)
3362 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3364 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3367 wid = the_ins.reloc[m].wid;
3370 the_ins.reloc[m].wid = 0;
3371 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3373 fixP = fix_new_exp (frag_now,
3374 ((toP - frag_now->fr_literal)
3375 - the_ins.numo * 2 + the_ins.reloc[m].n),
3377 &the_ins.reloc[m].exp,
3378 the_ins.reloc[m].pcrel,
3379 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3380 the_ins.reloc[m].pic_reloc));
3381 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3383 (void) frag_var (rs_machine_dependent, 10, 0,
3384 (relax_substateT) (the_ins.fragb[n].fragty),
3385 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3387 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3388 shorts_this_frag = 0;
3391 toP = frag_more (n * sizeof (short));
3394 md_number_to_chars (toP, (long) (*fromP), 2);
3400 for (m = 0; m < the_ins.nrel; m++)
3404 wid = the_ins.reloc[m].wid;
3407 the_ins.reloc[m].wid = 0;
3408 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3410 fixP = fix_new_exp (frag_now,
3411 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3412 - shorts_this_frag * 2),
3414 &the_ins.reloc[m].exp,
3415 the_ins.reloc[m].pcrel,
3416 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3417 the_ins.reloc[m].pic_reloc));
3418 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3426 * md_begin -- set up hash tables with 68000 instructions.
3427 * similar to what the vax assembler does. ---phr
3429 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3430 a copy of it at runtime, adding in the information we want but isn't
3431 there. I think it'd be better to have an awk script hack the table
3432 at compile time. Or even just xstr the table and use it as-is. But
3433 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3436 register const struct m68k_opcode *ins;
3437 register struct m68k_incant *hack, *slak;
3438 register const char *retval = 0; /* empty string, or error msg text */
3439 register unsigned int i;
3444 flag_reg_prefix_optional = 1;
3449 op_hash = hash_new ();
3451 obstack_begin (&robyn, 4000);
3452 for (i = 0; i < m68k_numopcodes; i++)
3454 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3457 ins = &m68k_opcodes[i];
3458 /* We *could* ignore insns that don't match our arch here
3459 but just leaving them out of the hash. */
3460 slak->m_operands = ins->args;
3461 slak->m_opnum = strlen (slak->m_operands) / 2;
3462 slak->m_arch = ins->arch;
3463 slak->m_opcode = ins->opcode;
3464 /* This is kludgey */
3465 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3466 if (i + 1 != m68k_numopcodes
3467 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3469 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3474 slak = slak->m_next;
3478 retval = hash_insert (op_hash, ins->name, (char *) hack);
3480 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3483 for (i = 0; i < m68k_numaliases; i++)
3485 const char *name = m68k_opcode_aliases[i].primary;
3486 const char *alias = m68k_opcode_aliases[i].alias;
3487 PTR val = hash_find (op_hash, name);
3489 as_fatal ("Internal Error: Can't find %s in hash table", name);
3490 retval = hash_insert (op_hash, alias, val);
3492 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3495 /* In MRI mode, all unsized branches are variable sized. Normally,
3496 they are word sized. */
3499 static struct m68k_opcode_alias mri_aliases[] =
3519 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3521 const char *name = mri_aliases[i].primary;
3522 const char *alias = mri_aliases[i].alias;
3523 PTR val = hash_find (op_hash, name);
3525 as_fatal ("Internal Error: Can't find %s in hash table", name);
3526 retval = hash_jam (op_hash, alias, val);
3528 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3532 for (i = 0; i < sizeof (mklower_table); i++)
3533 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3535 for (i = 0; i < sizeof (notend_table); i++)
3537 notend_table[i] = 0;
3538 alt_notend_table[i] = 0;
3540 notend_table[','] = 1;
3541 notend_table['{'] = 1;
3542 notend_table['}'] = 1;
3543 alt_notend_table['a'] = 1;
3544 alt_notend_table['A'] = 1;
3545 alt_notend_table['d'] = 1;
3546 alt_notend_table['D'] = 1;
3547 alt_notend_table['#'] = 1;
3548 alt_notend_table['&'] = 1;
3549 alt_notend_table['f'] = 1;
3550 alt_notend_table['F'] = 1;
3551 #ifdef REGISTER_PREFIX
3552 alt_notend_table[REGISTER_PREFIX] = 1;
3555 /* We need to put '(' in alt_notend_table to handle
3556 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3558 alt_notend_table['('] = 1;
3560 /* We need to put '@' in alt_notend_table to handle
3561 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3563 alt_notend_table['@'] = 1;
3565 /* We need to put digits in alt_notend_table to handle
3566 bfextu %d0{24:1},%d0
3568 alt_notend_table['0'] = 1;
3569 alt_notend_table['1'] = 1;
3570 alt_notend_table['2'] = 1;
3571 alt_notend_table['3'] = 1;
3572 alt_notend_table['4'] = 1;
3573 alt_notend_table['5'] = 1;
3574 alt_notend_table['6'] = 1;
3575 alt_notend_table['7'] = 1;
3576 alt_notend_table['8'] = 1;
3577 alt_notend_table['9'] = 1;
3579 #ifndef MIT_SYNTAX_ONLY
3580 /* Insert pseudo ops, these have to go into the opcode table since
3581 gas expects pseudo ops to start with a dot */
3584 while (mote_pseudo_table[n].poc_name)
3586 hack = (struct m68k_incant *)
3587 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3588 hash_insert (op_hash,
3589 mote_pseudo_table[n].poc_name, (char *) hack);
3590 hack->m_operands = 0;
3600 record_alignment (text_section, 2);
3601 record_alignment (data_section, 2);
3602 record_alignment (bss_section, 2);
3607 select_control_regs ()
3609 /* Note which set of "movec" control registers is available. */
3610 switch (cpu_of_arch (current_architecture))
3613 control_regs = m68000_control_regs;
3616 control_regs = m68010_control_regs;
3620 control_regs = m68020_control_regs;
3623 control_regs = m68040_control_regs;
3626 control_regs = m68060_control_regs;
3629 control_regs = cpu32_control_regs;
3632 control_regs = mcf5200_control_regs;
3640 m68k_init_after_args ()
3642 if (cpu_of_arch (current_architecture) == 0)
3645 const char *default_cpu = TARGET_CPU;
3647 if (*default_cpu == 'm')
3649 for (i = 0; i < n_archs; i++)
3650 if (strcasecmp (default_cpu, archs[i].name) == 0)
3654 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3655 current_architecture |= m68020;
3658 current_architecture |= archs[i].arch;
3660 /* Permit m68881 specification with all cpus; those that can't work
3661 with a coprocessor could be doing emulation. */
3662 if (current_architecture & m68851)
3664 if (current_architecture & m68040)
3666 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3669 /* What other incompatibilities could we check for? */
3671 /* Toss in some default assumptions about coprocessors. */
3673 && (cpu_of_arch (current_architecture)
3674 /* Can CPU32 have a 68881 coprocessor?? */
3675 & (m68020 | m68030 | cpu32)))
3677 current_architecture |= m68881;
3680 && (cpu_of_arch (current_architecture) & m68020up) != 0
3681 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3683 current_architecture |= m68851;
3685 if (no_68881 && (current_architecture & m68881))
3686 as_bad ("options for 68881 and no-68881 both given");
3687 if (no_68851 && (current_architecture & m68851))
3688 as_bad ("options for 68851 and no-68851 both given");
3691 /* Work out the magic number. This isn't very general. */
3692 if (current_architecture & m68000)
3693 m68k_aout_machtype = 0;
3694 else if (current_architecture & m68010)
3695 m68k_aout_machtype = 1;
3696 else if (current_architecture & m68020)
3697 m68k_aout_machtype = 2;
3699 m68k_aout_machtype = 2;
3702 /* Note which set of "movec" control registers is available. */
3703 select_control_regs ();
3705 if (cpu_of_arch (current_architecture) < m68020)
3706 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3709 /* This is called if we go in or out of MRI mode because of the .mri
3713 m68k_mri_mode_change (on)
3718 if (! flag_reg_prefix_optional)
3720 flag_reg_prefix_optional = 1;
3721 #ifdef REGISTER_PREFIX
3730 if (! reg_prefix_optional_seen)
3732 #ifdef REGISTER_PREFIX_OPTIONAL
3733 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3735 flag_reg_prefix_optional = 0;
3737 #ifdef REGISTER_PREFIX
3746 /* Equal to MAX_PRECISION in atof-ieee.c */
3747 #define MAX_LITTLENUMS 6
3749 /* Turn a string in input_line_pointer into a floating point constant
3750 of type type, and store the appropriate bytes in *litP. The number
3751 of LITTLENUMS emitted is stored in *sizeP . An error message is
3752 returned, or NULL on OK. */
3755 md_atof (type, litP, sizeP)
3761 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3762 LITTLENUM_TYPE *wordP;
3794 return "Bad call to MD_ATOF()";
3796 t = atof_ieee (input_line_pointer, type, words);
3798 input_line_pointer = t;
3800 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3801 for (wordP = words; prec--;)
3803 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3804 litP += sizeof (LITTLENUM_TYPE);
3810 md_number_to_chars (buf, val, n)
3815 number_to_chars_bigendian (buf, val, n);
3819 md_apply_fix_2 (fixP, val)
3823 addressT upper_limit;
3824 offsetT lower_limit;
3826 /* This is unnecessary but it convinces the native rs6000 compiler
3827 to generate the code we want. */
3828 char *buf = fixP->fx_frag->fr_literal;
3829 buf += fixP->fx_where;
3830 /* end ibm compiler workaround */
3832 if (val & 0x80000000)
3833 val |= ~(addressT)0x7fffffff;
3840 memset (buf, 0, fixP->fx_size);
3841 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3846 switch (fixP->fx_size)
3848 /* The cast to offsetT below are necessary to make code correct for
3849 machines where ints are smaller than offsetT */
3853 lower_limit = - (offsetT) 0x80;
3856 *buf++ = (val >> 8);
3858 upper_limit = 0x7fff;
3859 lower_limit = - (offsetT) 0x8000;
3862 *buf++ = (val >> 24);
3863 *buf++ = (val >> 16);
3864 *buf++ = (val >> 8);
3866 upper_limit = 0x7fffffff;
3867 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3870 BAD_CASE (fixP->fx_size);
3873 /* Fix up a negative reloc. */
3874 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3876 fixP->fx_addsy = fixP->fx_subsy;
3877 fixP->fx_subsy = NULL;
3881 /* For non-pc-relative values, it's conceivable we might get something
3882 like "0xff" for a byte field. So extend the upper part of the range
3883 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3884 so that we can do any range checking at all. */
3885 if (!fixP->fx_pcrel)
3886 upper_limit = upper_limit * 2 + 1;
3888 if ((addressT) val > upper_limit
3889 && (val > 0 || val < lower_limit))
3890 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3892 /* A one byte PC-relative reloc means a short branch. We can't use
3893 a short branch with a value of 0 or -1, because those indicate
3894 different opcodes (branches with longer offsets). */
3896 && fixP->fx_size == 1
3897 && (fixP->fx_addsy == NULL
3898 || S_IS_DEFINED (fixP->fx_addsy))
3899 && (val == 0 || val == -1))
3900 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3903 #ifdef BFD_ASSEMBLER
3905 md_apply_fix (fixP, valp)
3909 md_apply_fix_2 (fixP, (addressT) *valp);
3913 void md_apply_fix (fixP, val)
3917 md_apply_fix_2 (fixP, (addressT) val);
3921 /* *fragP has been relaxed to its final size, and now needs to have
3922 the bytes inside it modified to conform to the new size There is UGLY
3926 md_convert_frag_1 (fragP)
3927 register fragS *fragP;
3933 /* Address in object code of the displacement. */
3934 register int object_address = fragP->fr_fix + fragP->fr_address;
3936 /* Address in gas core of the place to store the displacement. */
3937 /* This convinces the native rs6000 compiler to generate the code we
3939 register char *buffer_address = fragP->fr_literal;
3940 buffer_address += fragP->fr_fix;
3941 /* end ibm compiler workaround */
3943 /* The displacement of the address, from current location. */
3944 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3945 disp = (disp + fragP->fr_offset) - object_address;
3947 #ifdef BFD_ASSEMBLER
3948 disp += fragP->fr_symbol->sy_frag->fr_address;
3951 switch (fragP->fr_subtype)
3953 case TAB (BCC68000, BYTE):
3954 case TAB (ABRANCH, BYTE):
3955 know (issbyte (disp));
3957 as_bad ("short branch with zero offset: use :w");
3958 fragP->fr_opcode[1] = disp;
3961 case TAB (DBCC, SHORT):
3962 know (issword (disp));
3965 case TAB (BCC68000, SHORT):
3966 case TAB (ABRANCH, SHORT):
3967 know (issword (disp));
3968 fragP->fr_opcode[1] = 0x00;
3971 case TAB (ABRANCH, LONG):
3972 if (cpu_of_arch (current_architecture) < m68020)
3974 if (fragP->fr_opcode[0] == 0x61)
3977 fragP->fr_opcode[0] = 0x4E;
3978 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3992 else if (fragP->fr_opcode[0] == 0x60)
3994 fragP->fr_opcode[0] = 0x4E;
3995 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3996 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3997 fragP->fr_offset, 0, NO_RELOC);
4003 as_bad ("Long branch offset not supported.");
4008 fragP->fr_opcode[1] = (char) 0xff;
4012 case TAB (BCC68000, LONG):
4013 /* only Bcc 68000 instructions can come here */
4014 /* change bcc into b!cc/jmp absl long */
4015 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4016 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4018 /* JF: these used to be fr_opcode[2,3], but they may be in a
4019 different frag, in which case refering to them is a no-no.
4020 Only fr_opcode[0,1] are guaranteed to work. */
4021 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4022 *buffer_address++ = (char) 0xf9;
4023 fragP->fr_fix += 2; /* account for jmp instruction */
4024 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4025 fragP->fr_offset, 0, NO_RELOC);
4029 case TAB (DBCC, LONG):
4030 /* only DBcc 68000 instructions can come here */
4031 /* change dbcc into dbcc/jmp absl long */
4032 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4033 *buffer_address++ = 0x00; /* branch offset = 4 */
4034 *buffer_address++ = 0x04;
4035 *buffer_address++ = 0x60; /* put in bra pc+6 */
4036 *buffer_address++ = 0x06;
4037 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4038 *buffer_address++ = (char) 0xf9;
4040 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4041 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4042 fragP->fr_offset, 0, NO_RELOC);
4046 case TAB (FBRANCH, SHORT):
4047 know ((fragP->fr_opcode[1] & 0x40) == 0);
4050 case TAB (FBRANCH, LONG):
4051 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4054 case TAB (PCREL, SHORT):
4057 case TAB (PCREL, LONG):
4058 /* The thing to do here is force it to ABSOLUTE LONG, since
4059 PCREL is really trying to shorten an ABSOLUTE address anyway */
4060 /* JF FOO This code has not been tested */
4061 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4063 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4064 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4065 (unsigned) fragP->fr_opcode[0],
4066 (unsigned long) fragP->fr_address);
4067 fragP->fr_opcode[1] &= ~0x3F;
4068 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4072 case TAB (PCLEA, SHORT):
4073 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4074 fragP->fr_offset, 1, NO_RELOC);
4075 fragP->fr_opcode[1] &= ~0x3F;
4076 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4079 case TAB (PCLEA, LONG):
4080 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4081 fragP->fr_offset, 1, NO_RELOC);
4082 fixP->fx_pcrel_adjust = 2;
4083 /* Already set to mode 7.3; this indicates: PC indirect with
4084 suppressed index, 32-bit displacement. */
4085 *buffer_address++ = 0x01;
4086 *buffer_address++ = 0x70;
4091 case TAB (PCINDEX, BYTE):
4093 if (!issbyte (disp))
4095 as_bad ("displacement doesn't fit in one byte");
4098 assert (fragP->fr_fix >= 2);
4099 buffer_address[-2] &= ~1;
4100 buffer_address[-1] = disp;
4103 case TAB (PCINDEX, SHORT):
4105 assert (issword (disp));
4106 assert (fragP->fr_fix >= 2);
4107 buffer_address[-2] |= 0x1;
4108 buffer_address[-1] = 0x20;
4109 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4110 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4112 fixP->fx_pcrel_adjust = 2;
4115 case TAB (PCINDEX, LONG):
4117 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4118 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4120 fixP->fx_pcrel_adjust = 2;
4121 assert (fragP->fr_fix >= 2);
4122 buffer_address[-2] |= 0x1;
4123 buffer_address[-1] = 0x30;
4130 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4131 fragP->fr_fix += ext;
4135 #ifndef BFD_ASSEMBLER
4138 md_convert_frag (headers, sec, fragP)
4139 object_headers *headers;
4143 md_convert_frag_1 (fragP);
4149 md_convert_frag (abfd, sec, fragP)
4154 md_convert_frag_1 (fragP);
4158 /* Force truly undefined symbols to their maximum size, and generally set up
4159 the frag list to be relaxed
4162 md_estimate_size_before_relax (fragP, segment)
4163 register fragS *fragP;
4167 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4169 old_fix = fragP->fr_fix;
4171 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4172 switch (fragP->fr_subtype)
4175 case TAB (ABRANCH, SZ_UNDEF):
4177 if ((fragP->fr_symbol != NULL) /* Not absolute */
4178 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4180 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4183 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4185 /* On 68000, or for absolute value, switch to abs long */
4186 /* FIXME, we should check abs val, pick short or long */
4187 if (fragP->fr_opcode[0] == 0x61)
4189 fragP->fr_opcode[0] = 0x4E;
4190 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4191 fix_new (fragP, fragP->fr_fix, 4,
4192 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4196 else if (fragP->fr_opcode[0] == 0x60)
4198 fragP->fr_opcode[0] = 0x4E;
4199 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4200 fix_new (fragP, fragP->fr_fix, 4,
4201 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4207 as_warn ("Long branch offset to extern symbol not supported.");
4211 { /* Symbol is still undefined. Make it simple */
4212 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4213 fragP->fr_offset, 1, NO_RELOC);
4215 fragP->fr_opcode[1] = (char) 0xff;
4221 } /* case TAB(ABRANCH,SZ_UNDEF) */
4223 case TAB (FBRANCH, SZ_UNDEF):
4225 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4227 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4232 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4233 fragP->fr_offset, 1, NO_RELOC);
4235 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4239 } /* TAB(FBRANCH,SZ_UNDEF) */
4241 case TAB (PCREL, SZ_UNDEF):
4243 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4245 || cpu_of_arch (current_architecture) < m68020)
4247 fragP->fr_subtype = TAB (PCREL, SHORT);
4252 fragP->fr_subtype = TAB (PCREL, LONG);
4256 } /* TAB(PCREL,SZ_UNDEF) */
4258 case TAB (BCC68000, SZ_UNDEF):
4260 if ((fragP->fr_symbol != NULL)
4261 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4263 fragP->fr_subtype = TAB (BCC68000, BYTE);
4266 /* only Bcc 68000 instructions can come here */
4267 /* change bcc into b!cc/jmp absl long */
4268 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4269 if (flag_short_refs)
4271 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4272 /* JF: these were fr_opcode[2,3] */
4273 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4274 buffer_address[1] = (char) 0xf8;
4275 fragP->fr_fix += 2; /* account for jmp instruction */
4276 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4277 fragP->fr_offset, 0, NO_RELOC);
4282 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4283 /* JF: these were fr_opcode[2,3] */
4284 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4285 buffer_address[1] = (char) 0xf9;
4286 fragP->fr_fix += 2; /* account for jmp instruction */
4287 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4288 fragP->fr_offset, 0, NO_RELOC);
4293 } /* case TAB(BCC68000,SZ_UNDEF) */
4295 case TAB (DBCC, SZ_UNDEF):
4297 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4299 fragP->fr_subtype = TAB (DBCC, SHORT);
4303 /* only DBcc 68000 instructions can come here */
4304 /* change dbcc into dbcc/jmp absl long */
4305 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4306 buffer_address[0] = 0x00; /* branch offset = 4 */
4307 buffer_address[1] = 0x04;
4308 buffer_address[2] = 0x60; /* put in bra pc + ... */
4310 if (flag_short_refs)
4312 /* JF: these were fr_opcode[5-7] */
4313 buffer_address[3] = 0x04; /* plus 4 */
4314 buffer_address[4] = 0x4e; /* Put in Jump Word */
4315 buffer_address[5] = (char) 0xf8;
4316 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4317 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4318 fragP->fr_offset, 0, NO_RELOC);
4323 /* JF: these were fr_opcode[5-7] */
4324 buffer_address[3] = 0x06; /* Plus 6 */
4325 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4326 buffer_address[5] = (char) 0xf9;
4327 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4328 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4329 fragP->fr_offset, 0, NO_RELOC);
4335 } /* case TAB(DBCC,SZ_UNDEF) */
4337 case TAB (PCLEA, SZ_UNDEF):
4339 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4341 || cpu_of_arch (current_architecture) < m68020)
4343 fragP->fr_subtype = TAB (PCLEA, SHORT);
4348 fragP->fr_subtype = TAB (PCLEA, LONG);
4352 } /* TAB(PCLEA,SZ_UNDEF) */
4354 case TAB (PCINDEX, SZ_UNDEF):
4355 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4356 || cpu_of_arch (current_architecture) < m68020)
4358 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4362 fragP->fr_subtype = TAB (PCINDEX, LONG);
4371 /* now that SZ_UNDEF are taken care of, check others */
4372 switch (fragP->fr_subtype)
4374 case TAB (BCC68000, BYTE):
4375 case TAB (ABRANCH, BYTE):
4376 /* We can't do a short jump to the next instruction, so in that
4377 case we force word mode. At this point S_GET_VALUE should
4378 return the offset of the symbol within its frag. If the
4379 symbol is at the start of a frag, and it is the next frag
4380 with any data in it (usually this is just the next frag, but
4381 assembler listings may introduce empty frags), we must use
4383 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4387 for (l = fragP->fr_next;
4388 l != fragP->fr_symbol->sy_frag;
4390 if (l->fr_fix + l->fr_var != 0)
4392 if (l == fragP->fr_symbol->sy_frag)
4394 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4402 return fragP->fr_var + fragP->fr_fix - old_fix;
4405 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4406 /* the bit-field entries in the relocation_info struct plays hell
4407 with the byte-order problems of cross-assembly. So as a hack,
4408 I added this mach. dependent ri twiddler. Ugly, but it gets
4410 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4411 are symbolnum, most sig. byte first. Last byte is broken up with
4412 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4413 nibble as nuthin. (on Sun 3 at least) */
4414 /* Translate the internal relocation information into target-specific
4418 md_ri_to_chars (the_bytes, ri)
4420 struct reloc_info_generic *ri;
4423 md_number_to_chars (the_bytes, ri->r_address, 4);
4424 /* now the fun stuff */
4425 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4426 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4427 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4428 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4429 ((ri->r_extern << 4) & 0x10));
4432 #endif /* comment */
4434 #ifndef BFD_ASSEMBLER
4436 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4439 relax_addressT segment_address_in_file;
4442 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4443 * Out: GNU LD relocation length code: 0, 1, or 2.
4446 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4449 know (fixP->fx_addsy != NULL);
4451 md_number_to_chars (where,
4452 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4455 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4456 ? S_GET_TYPE (fixP->fx_addsy)
4457 : fixP->fx_addsy->sy_number);
4459 where[4] = (r_symbolnum >> 16) & 0x0ff;
4460 where[5] = (r_symbolnum >> 8) & 0x0ff;
4461 where[6] = r_symbolnum & 0x0ff;
4462 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4463 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4467 #endif /* OBJ_AOUT or OBJ_BOUT */
4469 #ifndef WORKING_DOT_WORD
4470 CONST int md_short_jump_size = 4;
4471 CONST int md_long_jump_size = 6;
4474 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4476 addressT from_addr, to_addr;
4482 offset = to_addr - (from_addr + 2);
4484 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4485 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4489 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4491 addressT from_addr, to_addr;
4497 if (cpu_of_arch (current_architecture) < m68020)
4499 offset = to_addr - S_GET_VALUE (to_symbol);
4500 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4501 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4502 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4507 offset = to_addr - (from_addr + 2);
4508 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4509 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4515 /* Different values of OK tell what its OK to return. Things that
4516 aren't OK are an error (what a shock, no?)
4519 10: Absolute 1:8 only
4520 20: Absolute 0:7 only
4521 30: absolute 0:15 only
4522 40: Absolute 0:31 only
4523 50: absolute 0:127 only
4524 55: absolute -64:63 only
4525 60: absolute -128:127 only
4526 70: absolute 0:4095 only
4533 struct m68k_exp *exp;
4536 if (exp->exp.X_op == O_absent)
4538 /* Do the same thing the VAX asm does */
4539 op (exp) = O_constant;
4545 as_warn ("expression out of range: defaulting to 1");
4549 else if (exp->exp.X_op == O_constant)
4554 if (offs (exp) < 1 || offs (exp) > 8)
4556 as_warn ("expression out of range: defaulting to 1");
4561 if (offs (exp) < 0 || offs (exp) > 7)
4565 if (offs (exp) < 0 || offs (exp) > 15)
4569 if (offs (exp) < 0 || offs (exp) > 32)
4573 if (offs (exp) < 0 || offs (exp) > 127)
4577 if (offs (exp) < -64 || offs (exp) > 63)
4581 if (offs (exp) < -128 || offs (exp) > 127)
4585 if (offs (exp) < 0 || offs (exp) > 4095)
4588 as_warn ("expression out of range: defaulting to 0");
4596 else if (exp->exp.X_op == O_big)
4598 if (offs (exp) <= 0 /* flonum */
4599 && (ok == 80 /* no bignums */
4600 || (ok > 10 /* small-int ranges including 0 ok */
4601 /* If we have a flonum zero, a zero integer should
4602 do as well (e.g., in moveq). */
4603 && generic_floating_point_number.exponent == 0
4604 && generic_floating_point_number.low[0] == 0)))
4606 /* HACK! Turn it into a long */
4607 LITTLENUM_TYPE words[6];
4609 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4610 op (exp) = O_constant;
4613 offs (exp) = words[1] | (words[0] << 16);
4617 op (exp) = O_constant;
4620 offs (exp) = (ok == 10) ? 1 : 0;
4621 as_warn ("Can't deal with expression; defaulting to %ld",
4627 if (ok >= 10 && ok <= 70)
4629 op (exp) = O_constant;
4632 offs (exp) = (ok == 10) ? 1 : 0;
4633 as_warn ("Can't deal with expression; defaulting to %ld",
4638 if (exp->size != SIZE_UNSPEC)
4646 if (!isbyte (offs (exp)))
4647 as_warn ("expression doesn't fit in BYTE");
4650 if (!isword (offs (exp)))
4651 as_warn ("expression doesn't fit in WORD");
4659 /* These are the back-ends for the various machine dependent pseudo-ops. */
4660 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4666 subseg_set (data_section, 1);
4667 demand_empty_rest_of_line ();
4674 subseg_set (data_section, 2);
4675 demand_empty_rest_of_line ();
4682 /* We don't support putting frags in the BSS segment, we fake it
4683 by marking in_bss, then looking at s_skip for clues. */
4685 subseg_set (bss_section, 0);
4686 demand_empty_rest_of_line ();
4694 register long temp_fill;
4696 temp = 1; /* JF should be 2? */
4697 temp_fill = get_absolute_expression ();
4698 if (!need_pass_2) /* Never make frag if expect extra pass. */
4699 frag_align (temp, (int) temp_fill);
4700 demand_empty_rest_of_line ();
4707 demand_empty_rest_of_line ();
4710 /* Pseudo-ops handled for MRI compatibility. */
4712 /* Handle an MRI style chip specification. */
4721 s = input_line_pointer;
4722 c = get_symbol_end ();
4723 for (i = 0; i < n_archs; i++)
4724 if (strcasecmp (s, archs[i].name) == 0)
4728 as_bad ("%s: unrecognized processor name", s);
4729 *input_line_pointer = c;
4730 ignore_rest_of_line ();
4733 *input_line_pointer = c;
4735 if (*input_line_pointer == '/')
4736 current_architecture = 0;
4738 current_architecture &= m68881 | m68851;
4739 current_architecture |= archs[i].arch;
4741 while (*input_line_pointer == '/')
4743 ++input_line_pointer;
4744 s = input_line_pointer;
4745 c = get_symbol_end ();
4746 if (strcmp (s, "68881") == 0)
4747 current_architecture |= m68881;
4748 else if (strcmp (s, "68851") == 0)
4749 current_architecture |= m68851;
4750 *input_line_pointer = c;
4753 /* Update info about available control registers. */
4754 select_control_regs ();
4757 /* The MRI CHIP pseudo-op. */
4767 stop = mri_comment_field (&stopc);
4770 mri_comment_end (stop, stopc);
4771 demand_empty_rest_of_line ();
4774 /* The MRI FOPT pseudo-op. */
4782 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4786 input_line_pointer += 3;
4787 temp = get_absolute_expression ();
4788 if (temp < 0 || temp > 7)
4789 as_bad ("bad coprocessor id");
4791 m68k_float_copnum = COP0 + temp;
4795 as_bad ("unrecognized fopt option");
4796 ignore_rest_of_line ();
4800 demand_empty_rest_of_line ();
4803 /* The structure used to handle the MRI OPT pseudo-op. */
4807 /* The name of the option. */
4810 /* If this is not NULL, just call this function. The first argument
4811 is the ARG field of this structure, the second argument is
4812 whether the option was negated. */
4813 void (*pfn) PARAMS ((int arg, int on));
4815 /* If this is not NULL, and the PFN field is NULL, set the variable
4816 this points to. Set it to the ARG field if the option was not
4817 negated, and the NOTARG field otherwise. */
4820 /* The value to pass to PFN or to assign to *PVAR. */
4823 /* The value to assign to *PVAR if the option is negated. If PFN is
4824 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4825 the option may not be negated. */
4829 /* The table used to handle the MRI OPT pseudo-op. */
4831 static void skip_to_comma PARAMS ((int, int));
4832 static void opt_nest PARAMS ((int, int));
4833 static void opt_chip PARAMS ((int, int));
4834 static void opt_list PARAMS ((int, int));
4835 static void opt_list_symbols PARAMS ((int, int));
4837 static const struct opt_action opt_table[] =
4839 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4841 /* We do relaxing, so there is little use for these options. */
4842 { "b", 0, 0, 0, 0 },
4843 { "brs", 0, 0, 0, 0 },
4844 { "brb", 0, 0, 0, 0 },
4845 { "brl", 0, 0, 0, 0 },
4846 { "brw", 0, 0, 0, 0 },
4848 { "c", 0, 0, 0, 0 },
4849 { "cex", 0, 0, 0, 0 },
4850 { "case", 0, &symbols_case_sensitive, 1, 0 },
4851 { "cl", 0, 0, 0, 0 },
4852 { "cre", 0, 0, 0, 0 },
4853 { "d", 0, &flag_keep_locals, 1, 0 },
4854 { "e", 0, 0, 0, 0 },
4855 { "f", 0, &flag_short_refs, 1, 0 },
4856 { "frs", 0, &flag_short_refs, 1, 0 },
4857 { "frl", 0, &flag_short_refs, 0, 1 },
4858 { "g", 0, 0, 0, 0 },
4859 { "i", 0, 0, 0, 0 },
4860 { "m", 0, 0, 0, 0 },
4861 { "mex", 0, 0, 0, 0 },
4862 { "mc", 0, 0, 0, 0 },
4863 { "md", 0, 0, 0, 0 },
4864 { "nest", opt_nest, 0, 0, 0 },
4865 { "next", skip_to_comma, 0, 0, 0 },
4866 { "o", 0, 0, 0, 0 },
4867 { "old", 0, 0, 0, 0 },
4868 { "op", skip_to_comma, 0, 0, 0 },
4869 { "pco", 0, 0, 0, 0 },
4870 { "p", opt_chip, 0, 0, 0 },
4871 { "pcr", 0, 0, 0, 0 },
4872 { "pcs", 0, 0, 0, 0 },
4873 { "r", 0, 0, 0, 0 },
4874 { "quick", 0, &m68k_quick, 1, 0 },
4875 { "rel32", 0, &m68k_rel32, 1, 0 },
4876 { "s", opt_list, 0, 0, 0 },
4877 { "t", opt_list_symbols, 0, 0, 0 },
4878 { "w", 0, &flag_no_warnings, 0, 1 },
4882 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4884 /* The MRI OPT pseudo-op. */
4896 const struct opt_action *o;
4901 if (*input_line_pointer == '-')
4903 ++input_line_pointer;
4906 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4908 input_line_pointer += 2;
4912 s = input_line_pointer;
4913 c = get_symbol_end ();
4915 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4917 if (strcasecmp (s, o->name) == 0)
4921 /* Restore input_line_pointer now in case the option
4923 *input_line_pointer = c;
4924 (*o->pfn) (o->arg, t);
4926 else if (o->pvar != NULL)
4928 if (! t && o->arg == o->notarg)
4929 as_bad ("option `%s' may not be negated", s);
4930 *input_line_pointer = c;
4931 *o->pvar = t ? o->arg : o->notarg;
4934 *input_line_pointer = c;
4940 as_bad ("option `%s' not recognized", s);
4941 *input_line_pointer = c;
4944 while (*input_line_pointer++ == ',');
4946 /* Move back to terminating character. */
4947 --input_line_pointer;
4948 demand_empty_rest_of_line ();
4951 /* Skip ahead to a comma. This is used for OPT options which we do
4952 not suppor tand which take arguments. */
4955 skip_to_comma (arg, on)
4959 while (*input_line_pointer != ','
4960 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4961 ++input_line_pointer;
4964 /* Handle the OPT NEST=depth option. */
4971 if (*input_line_pointer != '=')
4973 as_bad ("bad format of OPT NEST=depth");
4977 ++input_line_pointer;
4978 max_macro_nest = get_absolute_expression ();
4981 /* Handle the OPT P=chip option. */
4988 if (*input_line_pointer != '=')
4990 /* This is just OPT P, which we do not support. */
4994 ++input_line_pointer;
4998 /* Handle the OPT S option. */
5008 /* Handle the OPT T option. */
5011 opt_list_symbols (arg, on)
5016 listing |= LISTING_SYMBOLS;
5018 listing &=~ LISTING_SYMBOLS;
5021 /* Handle the MRI REG pseudo-op. */
5034 if (line_label == NULL)
5036 as_bad ("missing label");
5037 ignore_rest_of_line ();
5042 stop = mri_comment_field (&stopc);
5046 s = input_line_pointer;
5047 while (isalnum ((unsigned char) *input_line_pointer)
5048 #ifdef REGISTER_PREFIX
5049 || *input_line_pointer == REGISTER_PREFIX
5051 || *input_line_pointer == '/'
5052 || *input_line_pointer == '-')
5053 ++input_line_pointer;
5054 c = *input_line_pointer;
5055 *input_line_pointer = '\0';
5057 if (m68k_ip_op (s, &rop) != 0)
5059 if (rop.error == NULL)
5060 as_bad ("bad register list");
5062 as_bad ("bad register list: %s", rop.error);
5063 *input_line_pointer = c;
5064 ignore_rest_of_line ();
5068 *input_line_pointer = c;
5070 if (rop.mode == REGLST)
5072 else if (rop.mode == DREG)
5073 mask = 1 << (rop.reg - DATA0);
5074 else if (rop.mode == AREG)
5075 mask = 1 << (rop.reg - ADDR0 + 8);
5076 else if (rop.mode == FPREG)
5077 mask = 1 << (rop.reg - FP0 + 16);
5078 else if (rop.mode == CONTROL
5081 else if (rop.mode == CONTROL
5084 else if (rop.mode == CONTROL
5089 as_bad ("bad register list");
5090 ignore_rest_of_line ();
5094 S_SET_SEGMENT (line_label, absolute_section);
5095 S_SET_VALUE (line_label, mask);
5096 line_label->sy_frag = &zero_address_frag;
5099 mri_comment_end (stop, stopc);
5101 demand_empty_rest_of_line ();
5104 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5108 struct save_opts *next;
5110 int symbols_case_sensitive;
5118 /* FIXME: We don't save OPT S. */
5121 /* This variable holds the stack of saved options. */
5123 static struct save_opts *save_stack;
5125 /* The MRI SAVE pseudo-op. */
5131 struct save_opts *s;
5133 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5134 s->abspcadd = m68k_abspcadd;
5135 s->symbols_case_sensitive = symbols_case_sensitive;
5136 s->keep_locals = flag_keep_locals;
5137 s->short_refs = flag_short_refs;
5138 s->architecture = current_architecture;
5139 s->quick = m68k_quick;
5140 s->rel32 = m68k_rel32;
5141 s->listing = listing;
5142 s->no_warnings = flag_no_warnings;
5144 s->next = save_stack;
5147 demand_empty_rest_of_line ();
5150 /* The MRI RESTORE pseudo-op. */
5156 struct save_opts *s;
5158 if (save_stack == NULL)
5160 as_bad ("restore without save");
5161 ignore_rest_of_line ();
5166 save_stack = s->next;
5168 m68k_abspcadd = s->abspcadd;
5169 symbols_case_sensitive = s->symbols_case_sensitive;
5170 flag_keep_locals = s->keep_locals;
5171 flag_short_refs = s->short_refs;
5172 current_architecture = s->architecture;
5173 m68k_quick = s->quick;
5174 m68k_rel32 = s->rel32;
5175 listing = s->listing;
5176 flag_no_warnings = s->no_warnings;
5180 demand_empty_rest_of_line ();
5183 /* Types of MRI structured control directives. */
5185 enum mri_control_type
5193 /* This structure is used to stack the MRI structured control
5196 struct mri_control_info
5198 /* The directive within which this one is enclosed. */
5199 struct mri_control_info *outer;
5201 /* The type of directive. */
5202 enum mri_control_type type;
5204 /* Whether an ELSE has been in an IF. */
5207 /* The add or sub statement at the end of a FOR. */
5210 /* The label of the top of a FOR or REPEAT loop. */
5213 /* The label to jump to for the next iteration, or the else
5214 expression of a conditional. */
5217 /* The label to jump to to break out of the loop, or the label past
5218 the end of a conditional. */
5222 /* The stack of MRI structured control directives. */
5224 static struct mri_control_info *mri_control_stack;
5226 /* The current MRI structured control directive index number, used to
5227 generate label names. */
5229 static int mri_control_index;
5231 /* Some function prototypes. */
5233 static char *mri_control_label PARAMS ((void));
5234 static struct mri_control_info *push_mri_control
5235 PARAMS ((enum mri_control_type));
5236 static void pop_mri_control PARAMS ((void));
5237 static int parse_mri_condition PARAMS ((int *));
5238 static int parse_mri_control_operand
5239 PARAMS ((int *, char **, char **, char **, char **));
5240 static int swap_mri_condition PARAMS ((int));
5241 static int reverse_mri_condition PARAMS ((int));
5242 static void build_mri_control_operand
5243 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5244 const char *, int));
5245 static void parse_mri_control_expression
5246 PARAMS ((char *, int, const char *, const char *, int));
5248 /* Generate a new MRI label structured control directive label name. */
5251 mri_control_label ()
5255 n = (char *) xmalloc (20);
5256 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5257 ++mri_control_index;
5261 /* Create a new MRI structured control directive. */
5263 static struct mri_control_info *
5264 push_mri_control (type)
5265 enum mri_control_type type;
5267 struct mri_control_info *n;
5269 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5273 if (type == mri_if || type == mri_while)
5276 n->top = mri_control_label ();
5277 n->next = mri_control_label ();
5278 n->bottom = mri_control_label ();
5280 n->outer = mri_control_stack;
5281 mri_control_stack = n;
5286 /* Pop off the stack of MRI structured control directives. */
5291 struct mri_control_info *n;
5293 n = mri_control_stack;
5294 mri_control_stack = n->outer;
5302 /* Recognize a condition code in an MRI structured control expression. */
5305 parse_mri_condition (pcc)
5310 know (*input_line_pointer == '<');
5312 ++input_line_pointer;
5313 c1 = *input_line_pointer++;
5314 c2 = *input_line_pointer++;
5316 if (*input_line_pointer != '>')
5318 as_bad ("syntax error in structured control directive");
5322 ++input_line_pointer;
5330 *pcc = (c1 << 8) | c2;
5335 /* Parse a single operand in an MRI structured control expression. */
5338 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5355 if (*input_line_pointer == '<')
5357 /* It's just a condition code. */
5358 return parse_mri_condition (pcc);
5361 /* Look ahead for the condition code. */
5362 for (s = input_line_pointer; *s != '\0'; ++s)
5364 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5369 as_bad ("missing condition code in structured control directive");
5373 *leftstart = input_line_pointer;
5375 if (*leftstop > *leftstart
5376 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5379 input_line_pointer = s;
5380 if (! parse_mri_condition (pcc))
5383 /* Look ahead for AND or OR or end of line. */
5384 for (s = input_line_pointer; *s != '\0'; ++s)
5386 if ((strncasecmp (s, "AND", 3) == 0
5387 && (s[3] == '.' || ! is_part_of_name (s[3])))
5388 || (strncasecmp (s, "OR", 2) == 0
5389 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5393 *rightstart = input_line_pointer;
5395 if (*rightstop > *rightstart
5396 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5399 input_line_pointer = s;
5404 #define MCC(b1, b2) (((b1) << 8) | (b2))
5406 /* Swap the sense of a condition. This changes the condition so that
5407 it generates the same result when the operands are swapped. */
5410 swap_mri_condition (cc)
5415 case MCC ('h', 'i'): return MCC ('c', 's');
5416 case MCC ('l', 's'): return MCC ('c', 'c');
5417 case MCC ('c', 'c'): return MCC ('l', 's');
5418 case MCC ('c', 's'): return MCC ('h', 'i');
5419 case MCC ('p', 'l'): return MCC ('m', 'i');
5420 case MCC ('m', 'i'): return MCC ('p', 'l');
5421 case MCC ('g', 'e'): return MCC ('l', 'e');
5422 case MCC ('l', 't'): return MCC ('g', 't');
5423 case MCC ('g', 't'): return MCC ('l', 't');
5424 case MCC ('l', 'e'): return MCC ('g', 'e');
5429 /* Reverse the sense of a condition. */
5432 reverse_mri_condition (cc)
5437 case MCC ('h', 'i'): return MCC ('l', 's');
5438 case MCC ('l', 's'): return MCC ('h', 'i');
5439 case MCC ('c', 'c'): return MCC ('c', 's');
5440 case MCC ('c', 's'): return MCC ('c', 'c');
5441 case MCC ('n', 'e'): return MCC ('e', 'q');
5442 case MCC ('e', 'q'): return MCC ('n', 'e');
5443 case MCC ('v', 'c'): return MCC ('v', 's');
5444 case MCC ('v', 's'): return MCC ('v', 'c');
5445 case MCC ('p', 'l'): return MCC ('m', 'i');
5446 case MCC ('m', 'i'): return MCC ('p', 'l');
5447 case MCC ('g', 'e'): return MCC ('l', 't');
5448 case MCC ('l', 't'): return MCC ('g', 'e');
5449 case MCC ('g', 't'): return MCC ('l', 'e');
5450 case MCC ('l', 'e'): return MCC ('g', 't');
5455 /* Build an MRI structured control expression. This generates test
5456 and branch instructions. It goes to TRUELAB if the condition is
5457 true, and to FALSELAB if the condition is false. Exactly one of
5458 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5459 is the size qualifier for the expression. EXTENT is the size to
5460 use for the branch. */
5463 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5464 rightstop, truelab, falselab, extent)
5471 const char *truelab;
5472 const char *falselab;
5478 if (leftstart != NULL)
5480 struct m68k_op leftop, rightop;
5483 /* Swap the compare operands, if necessary, to produce a legal
5484 m68k compare instruction. Comparing a register operand with
5485 a non-register operand requires the register to be on the
5486 right (cmp, cmpa). Comparing an immediate value with
5487 anything requires the immediate value to be on the left
5492 (void) m68k_ip_op (leftstart, &leftop);
5497 (void) m68k_ip_op (rightstart, &rightop);
5500 if (rightop.mode == IMMED
5501 || ((leftop.mode == DREG || leftop.mode == AREG)
5502 && (rightop.mode != DREG && rightop.mode != AREG)))
5506 cc = swap_mri_condition (cc);
5508 leftstart = rightstart;
5511 leftstop = rightstop;
5516 if (truelab == NULL)
5518 cc = reverse_mri_condition (cc);
5522 if (leftstart != NULL)
5524 buf = (char *) xmalloc (20
5525 + (leftstop - leftstart)
5526 + (rightstop - rightstart));
5534 memcpy (s, leftstart, leftstop - leftstart);
5535 s += leftstop - leftstart;
5537 memcpy (s, rightstart, rightstop - rightstart);
5538 s += rightstop - rightstart;
5544 buf = (char *) xmalloc (20 + strlen (truelab));
5552 strcpy (s, truelab);
5557 /* Parse an MRI structured control expression. This generates test
5558 and branch instructions. STOP is where the expression ends. It
5559 goes to TRUELAB if the condition is true, and to FALSELAB if the
5560 condition is false. Exactly one of TRUELAB and FALSELAB will be
5561 NULL, meaning to fall through. QUAL is the size qualifier for the
5562 expression. EXTENT is the size to use for the branch. */
5565 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5568 const char *truelab;
5569 const char *falselab;
5582 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5583 &rightstart, &rightstop))
5589 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5593 if (falselab != NULL)
5596 flab = mri_control_label ();
5598 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5599 rightstop, (const char *) NULL, flab, extent);
5601 input_line_pointer += 3;
5602 if (*input_line_pointer != '.'
5603 || input_line_pointer[1] == '\0')
5607 qual = input_line_pointer[1];
5608 input_line_pointer += 2;
5611 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5612 &rightstart, &rightstop))
5618 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5619 rightstop, truelab, falselab, extent);
5621 if (falselab == NULL)
5624 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5628 if (truelab != NULL)
5631 tlab = mri_control_label ();
5633 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5634 rightstop, tlab, (const char *) NULL, extent);
5636 input_line_pointer += 2;
5637 if (*input_line_pointer != '.'
5638 || input_line_pointer[1] == '\0')
5642 qual = input_line_pointer[1];
5643 input_line_pointer += 2;
5646 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5647 &rightstart, &rightstop))
5653 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5654 rightstop, truelab, falselab, extent);
5656 if (truelab == NULL)
5661 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5662 rightstop, truelab, falselab, extent);
5666 if (input_line_pointer != stop)
5667 as_bad ("syntax error in structured control directive");
5670 /* Handle the MRI IF pseudo-op. This may be a structured control
5671 directive, or it may be a regular assembler conditional, depending
5680 struct mri_control_info *n;
5682 /* A structured control directive must end with THEN with an
5683 optional qualifier. */
5684 s = input_line_pointer;
5685 while (! is_end_of_line[(unsigned char) *s]
5686 && (! flag_mri || *s != '*'))
5689 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5692 if (s - input_line_pointer > 1
5696 if (s - input_line_pointer < 3
5697 || strncasecmp (s - 3, "THEN", 4) != 0)
5701 as_bad ("missing then");
5702 ignore_rest_of_line ();
5706 /* It's a conditional. */
5711 /* Since this might be a conditional if, this pseudo-op will be
5712 called even if we are supported to be ignoring input. Double
5713 check now. Clobber *input_line_pointer so that ignore_input
5714 thinks that this is not a special pseudo-op. */
5715 c = *input_line_pointer;
5716 *input_line_pointer = 0;
5717 if (ignore_input ())
5719 *input_line_pointer = c;
5720 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5721 ++input_line_pointer;
5722 demand_empty_rest_of_line ();
5725 *input_line_pointer = c;
5727 n = push_mri_control (mri_if);
5729 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5730 n->next, s[1] == '.' ? s[2] : '\0');
5733 input_line_pointer = s + 3;
5735 input_line_pointer = s + 1;
5739 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5740 ++input_line_pointer;
5743 demand_empty_rest_of_line ();
5746 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5747 structured IF, associate the ELSE with the IF. Otherwise, assume
5748 it is a conditional else. */
5759 && (mri_control_stack == NULL
5760 || mri_control_stack->type != mri_if
5761 || mri_control_stack->else_seen))
5767 c = *input_line_pointer;
5768 *input_line_pointer = 0;
5769 if (ignore_input ())
5771 *input_line_pointer = c;
5772 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5773 ++input_line_pointer;
5774 demand_empty_rest_of_line ();
5777 *input_line_pointer = c;
5779 if (mri_control_stack == NULL
5780 || mri_control_stack->type != mri_if
5781 || mri_control_stack->else_seen)
5783 as_bad ("else without matching if");
5784 ignore_rest_of_line ();
5788 mri_control_stack->else_seen = 1;
5790 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5793 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5797 colon (mri_control_stack->next);
5801 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5802 ++input_line_pointer;
5805 demand_empty_rest_of_line ();
5808 /* Handle the MRI ENDI pseudo-op. */
5814 if (mri_control_stack == NULL
5815 || mri_control_stack->type != mri_if)
5817 as_bad ("endi without matching if");
5818 ignore_rest_of_line ();
5822 /* ignore_input will not return true for ENDI, so we don't need to
5823 worry about checking it again here. */
5825 if (! mri_control_stack->else_seen)
5826 colon (mri_control_stack->next);
5827 colon (mri_control_stack->bottom);
5833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5834 ++input_line_pointer;
5837 demand_empty_rest_of_line ();
5840 /* Handle the MRI BREAK pseudo-op. */
5843 s_mri_break (extent)
5846 struct mri_control_info *n;
5850 n = mri_control_stack;
5852 && n->type != mri_for
5853 && n->type != mri_repeat
5854 && n->type != mri_while)
5858 as_bad ("break outside of structured loop");
5859 ignore_rest_of_line ();
5863 buf = (char *) xmalloc (20 + strlen (n->bottom));
5866 sprintf (buf, "bra%s %s", ex, n->bottom);
5872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5873 ++input_line_pointer;
5876 demand_empty_rest_of_line ();
5879 /* Handle the MRI NEXT pseudo-op. */
5885 struct mri_control_info *n;
5889 n = mri_control_stack;
5891 && n->type != mri_for
5892 && n->type != mri_repeat
5893 && n->type != mri_while)
5897 as_bad ("next outside of structured loop");
5898 ignore_rest_of_line ();
5902 buf = (char *) xmalloc (20 + strlen (n->next));
5905 sprintf (buf, "bra%s %s", ex, n->next);
5911 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5912 ++input_line_pointer;
5915 demand_empty_rest_of_line ();
5918 /* Handle the MRI FOR pseudo-op. */
5924 const char *varstart, *varstop;
5925 const char *initstart, *initstop;
5926 const char *endstart, *endstop;
5927 const char *bystart, *bystop;
5931 struct mri_control_info *n;
5937 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5941 varstart = input_line_pointer;
5943 /* Look for the '='. */
5944 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5945 && *input_line_pointer != '=')
5946 ++input_line_pointer;
5947 if (*input_line_pointer != '=')
5949 as_bad ("missing =");
5950 ignore_rest_of_line ();
5954 varstop = input_line_pointer;
5955 if (varstop > varstart
5956 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5959 ++input_line_pointer;
5961 initstart = input_line_pointer;
5963 /* Look for TO or DOWNTO. */
5966 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5968 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5969 && ! is_part_of_name (input_line_pointer[2]))
5971 initstop = input_line_pointer;
5972 input_line_pointer += 2;
5975 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5976 && ! is_part_of_name (input_line_pointer[6]))
5978 initstop = input_line_pointer;
5980 input_line_pointer += 6;
5983 ++input_line_pointer;
5985 if (initstop == NULL)
5987 as_bad ("missing to or downto");
5988 ignore_rest_of_line ();
5991 if (initstop > initstart
5992 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5996 endstart = input_line_pointer;
5998 /* Look for BY or DO. */
6001 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6003 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6004 && ! is_part_of_name (input_line_pointer[2]))
6006 endstop = input_line_pointer;
6008 input_line_pointer += 2;
6011 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6012 && (input_line_pointer[2] == '.'
6013 || ! is_part_of_name (input_line_pointer[2])))
6015 endstop = input_line_pointer;
6016 input_line_pointer += 2;
6019 ++input_line_pointer;
6021 if (endstop == NULL)
6023 as_bad ("missing do");
6024 ignore_rest_of_line ();
6027 if (endstop > endstart
6028 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6034 bystop = bystart + 2;
6039 bystart = input_line_pointer;
6043 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6045 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6046 && (input_line_pointer[2] == '.'
6047 || ! is_part_of_name (input_line_pointer[2])))
6049 bystop = input_line_pointer;
6050 input_line_pointer += 2;
6053 ++input_line_pointer;
6057 as_bad ("missing do");
6058 ignore_rest_of_line ();
6061 if (bystop > bystart
6062 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6066 if (*input_line_pointer != '.')
6070 extent = input_line_pointer[1];
6071 input_line_pointer += 2;
6074 /* We have fully parsed the FOR operands. Now build the loop. */
6076 n = push_mri_control (mri_for);
6078 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6089 memcpy (s, initstart, initstop - initstart);
6090 s += initstop - initstart;
6092 memcpy (s, varstart, varstop - varstart);
6093 s += varstop - varstart;
6107 memcpy (s, endstart, endstop - endstart);
6108 s += endstop - endstart;
6110 memcpy (s, varstart, varstop - varstart);
6111 s += varstop - varstart;
6119 sprintf (buf, "blt%s %s", ex, n->bottom);
6121 sprintf (buf, "bgt%s %s", ex, n->bottom);
6124 /* Put together the add or sub instruction used by ENDF. */
6134 memcpy (s, bystart, bystop - bystart);
6135 s += bystop - bystart;
6137 memcpy (s, varstart, varstop - varstart);
6138 s += varstop - varstart;
6144 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6145 ++input_line_pointer;
6148 demand_empty_rest_of_line ();
6151 /* Handle the MRI ENDF pseudo-op. */
6157 if (mri_control_stack == NULL
6158 || mri_control_stack->type != mri_for)
6160 as_bad ("endf without for");
6161 ignore_rest_of_line ();
6165 colon (mri_control_stack->next);
6167 md_assemble (mri_control_stack->incr);
6169 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6170 md_assemble (mri_control_stack->incr);
6172 free (mri_control_stack->incr);
6174 colon (mri_control_stack->bottom);
6180 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6181 ++input_line_pointer;
6184 demand_empty_rest_of_line ();
6187 /* Handle the MRI REPEAT pseudo-op. */
6190 s_mri_repeat (ignore)
6193 struct mri_control_info *n;
6195 n = push_mri_control (mri_repeat);
6199 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6200 ++input_line_pointer;
6202 demand_empty_rest_of_line ();
6205 /* Handle the MRI UNTIL pseudo-op. */
6213 if (mri_control_stack == NULL
6214 || mri_control_stack->type != mri_repeat)
6216 as_bad ("until without repeat");
6217 ignore_rest_of_line ();
6221 colon (mri_control_stack->next);
6223 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6226 parse_mri_control_expression (s, qual, (const char *) NULL,
6227 mri_control_stack->top, '\0');
6229 colon (mri_control_stack->bottom);
6231 input_line_pointer = s;
6237 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6238 ++input_line_pointer;
6241 demand_empty_rest_of_line ();
6244 /* Handle the MRI WHILE pseudo-op. */
6252 struct mri_control_info *n;
6254 s = input_line_pointer;
6255 while (! is_end_of_line[(unsigned char) *s]
6256 && (! flag_mri || *s != '*'))
6259 while (*s == ' ' || *s == '\t')
6261 if (s - input_line_pointer > 1
6264 if (s - input_line_pointer < 2
6265 || strncasecmp (s - 1, "DO", 2) != 0)
6267 as_bad ("missing do");
6268 ignore_rest_of_line ();
6272 n = push_mri_control (mri_while);
6276 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6277 s[1] == '.' ? s[2] : '\0');
6279 input_line_pointer = s + 1;
6280 if (*input_line_pointer == '.')
6281 input_line_pointer += 2;
6285 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6286 ++input_line_pointer;
6289 demand_empty_rest_of_line ();
6292 /* Handle the MRI ENDW pseudo-op. */
6300 if (mri_control_stack == NULL
6301 || mri_control_stack->type != mri_while)
6303 as_bad ("endw without while");
6304 ignore_rest_of_line ();
6308 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6309 sprintf (buf, "bra %s", mri_control_stack->next);
6313 colon (mri_control_stack->bottom);
6319 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6320 ++input_line_pointer;
6323 demand_empty_rest_of_line ();
6328 * Invocation line includes a switch not recognized by the base assembler.
6329 * See if it's a processor-specific option. These are:
6331 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6332 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6333 * Select the architecture. Instructions or features not
6334 * supported by the selected architecture cause fatal
6335 * errors. More than one may be specified. The default is
6336 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6337 * for -m68000, and -m68882 is a synonym for -m68881.
6338 * -[A]m[c]no-68851, -[A]m[c]no-68881
6339 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6340 * so don't use or document it, but that's the way the parsing
6343 * -pic Indicates PIC.
6344 * -k Indicates PIC. (Sun 3 only.)
6347 * Permit `|' to be used in expressions.
6352 CONST char *md_shortopts = "lSA:m:kQ:V";
6354 CONST char *md_shortopts = "lSA:m:k";
6357 struct option md_longopts[] = {
6358 #define OPTION_PIC (OPTION_MD_BASE)
6359 {"pic", no_argument, NULL, OPTION_PIC},
6360 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6361 {"register-prefix-optional", no_argument, NULL,
6362 OPTION_REGISTER_PREFIX_OPTIONAL},
6363 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6364 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6365 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6366 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6367 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6368 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6369 {NULL, no_argument, NULL, 0}
6371 size_t md_longopts_size = sizeof(md_longopts);
6374 md_parse_option (c, arg)
6380 case 'l': /* -l means keep external to 2 bit offset
6381 rather than 16 bit one */
6382 flag_short_refs = 1;
6385 case 'S': /* -S means that jbsr's always turn into
6387 flag_long_jumps = 1;
6393 /* intentional fall-through */
6396 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6400 const char *oarg = arg;
6406 if (arg[0] == 'c' && arg[1] == '6')
6409 for (i = 0; i < n_archs; i++)
6410 if (!strcmp (arg, archs[i].name))
6415 as_bad ("unrecognized option `%s'", oarg);
6418 arch = archs[i].arch;
6421 else if (arch == m68851)
6430 if (arg[0] == 'c' && arg[1] == '6')
6433 for (i = 0; i < n_archs; i++)
6434 if (!strcmp (arg, archs[i].name))
6436 unsigned long arch = archs[i].arch;
6437 if (cpu_of_arch (arch))
6438 /* It's a cpu spec. */
6440 current_architecture &= ~m68000up;
6441 current_architecture |= arch;
6443 else if (arch == m68881)
6445 current_architecture |= m68881;
6448 else if (arch == m68851)
6450 current_architecture |= m68851;
6460 as_bad ("unrecognized architecture specification `%s'", arg);
6469 break; /* -pic, Position Independent Code */
6471 case OPTION_REGISTER_PREFIX_OPTIONAL:
6472 flag_reg_prefix_optional = 1;
6473 reg_prefix_optional_seen = 1;
6476 /* -V: SVR4 argument to print version ID. */
6478 print_version_id ();
6481 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6482 should be emitted or not. FIXME: Not implemented. */
6486 case OPTION_BITWISE_OR:
6491 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6493 for (s = m68k_comment_chars; *s != '\0'; s++)
6497 m68k_comment_chars = n;
6501 case OPTION_BASE_SIZE_DEFAULT_16:
6502 m68k_index_width_default = SIZE_WORD;
6505 case OPTION_BASE_SIZE_DEFAULT_32:
6506 m68k_index_width_default = SIZE_LONG;
6517 md_show_usage (stream)
6522 -l use 1 word for refs to undefined symbols [default 2]\n\
6523 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6524 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6525 | -mcpu32 | -m5200\n\
6526 specify variant of 680X0 architecture [default 68020]\n\
6527 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6528 target has/lacks floating-point coprocessor\n\
6529 [default yes for 68020, 68030, and cpu32]\n");
6531 -m68851 | -mno-68851\n\
6532 target has/lacks memory-management unit coprocessor\n\
6533 [default yes for 68020 and up]\n\
6534 -pic, -k generate position independent code\n\
6535 -S turn jbsr into jsr\n\
6536 --register-prefix-optional\n\
6537 recognize register names without prefix character\n\
6538 --bitwise-or do not treat `|' as a comment character\n");
6540 --base-size-default-16 base reg without size is 16 bits\n\
6541 --base-size-default-32 base reg without size is 32 bits (default)\n");
6546 /* TEST2: Test md_assemble() */
6547 /* Warning, this routine probably doesn't work anymore */
6551 struct m68k_it the_ins;
6559 if (!gets (buf) || !*buf)
6561 if (buf[0] == '|' || buf[1] == '.')
6563 for (cp = buf; *cp; cp++)
6568 memset (&the_ins, '\0', sizeof (the_ins));
6569 m68k_ip (&the_ins, buf);
6572 printf ("Error %s in %s\n", the_ins.error, buf);
6576 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6577 for (n = 0; n < the_ins.numo; n++)
6578 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6580 print_the_insn (&the_ins.opcode[0], stdout);
6581 (void) putchar ('\n');
6583 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6585 if (the_ins.operands[n].error)
6587 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6590 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6591 if (the_ins.operands[n].b_const)
6592 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6593 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6594 if (the_ins.operands[n].b_iadd)
6595 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6596 (void) putchar ('\n');
6608 while (*str && *str != ' ')
6610 if (str[-1] == ':' || str[1] == '=')
6617 /* Possible states for relaxation:
6619 0 0 branch offset byte (bra, etc)
6623 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6627 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6634 /* We have no need to default values of symbols. */
6638 md_undefined_symbol (name)
6644 /* Round up a section size to the appropriate boundary. */
6646 md_section_align (segment, size)
6650 return size; /* Byte alignment is fine */
6653 /* Exactly what point is a PC-relative offset relative TO?
6654 On the 68k, it is relative to the address of the first extension
6655 word. The difference between the addresses of the offset and the
6656 first extension word is stored in fx_pcrel_adjust. */
6658 md_pcrel_from (fixP)
6663 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6665 adjust = fixP->fx_pcrel_adjust;
6668 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6671 #ifndef BFD_ASSEMBLER
6674 tc_coff_symbol_emit_hook (ignore)
6680 tc_coff_sizemachdep (frag)
6683 switch (frag->fr_subtype & 0x3)
6698 /* end of tc-m68k.c */