1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 1999
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
41 const char *m68k_comment_chars = "|";
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
53 const char line_separator_chars[] = "";
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
67 const int md_reloc_size = 8; /* Size of relocation record */
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81 int flag_reg_prefix_optional;
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen;
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum = COP1;
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd;
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick = 1;
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
101 static int m68k_rel32 = 1;
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline;
106 /* The default width to use for an index register when using a base
108 static enum m68k_size m68k_index_width_default = SIZE_LONG;
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
116 struct label_line *next;
123 /* The list of labels. */
125 static struct label_line *labels;
127 /* The current label. */
129 static struct label_line *current_label;
131 /* Its an arbitrary name: This means I don't approve of it */
132 /* See flames below */
133 static struct obstack robyn;
135 #define TAB(x,y) (((x)<<2)+(y))
136 #define TABTYPE(xy) ((xy) >> 2)
142 /* Case `g' except when BCC68000 is applicable. */
144 /* Coprocessor branches. */
146 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
147 supported on all cpus. Widens to 32-bit absolute. */
149 /* For inserting an extra jmp instruction with long offset on 68000,
150 for expanding conditional branches. (Not bsr or bra.) Since the
151 68000 doesn't support 32-bit displacements for conditional
152 branches, we fake it by reversing the condition and branching
153 around a jmp with an absolute long operand. */
155 /* For the DBcc "instructions". If the displacement requires 32 bits,
156 the branch-around-a-jump game is played here too. */
158 /* Not currently used? */
160 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
166 const char *m_operands;
167 unsigned long m_opcode;
171 struct m68k_incant *m_next;
174 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
175 #define gettwo(x) (((x)->m_opcode)&0xffff)
177 static const enum m68k_register m68000_control_regs[] = { 0 };
178 static const enum m68k_register m68010_control_regs[] = {
182 static const enum m68k_register m68020_control_regs[] = {
183 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
186 static const enum m68k_register m68040_control_regs[] = {
187 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
188 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
191 static const enum m68k_register m68060_control_regs[] = {
192 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
193 USP, VBR, URP, SRP, PCR,
196 static const enum m68k_register mcf_control_regs[] = {
197 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
198 RAMBAR0, RAMBAR1, MBAR,
201 #define cpu32_control_regs m68010_control_regs
203 static const enum m68k_register *control_regs;
205 /* internal form of a 68020 instruction */
209 const char *args; /* list of opcode info */
212 int numo; /* Number of shorts in opcode */
215 struct m68k_op operands[6];
217 int nexp; /* number of exprs in use */
218 struct m68k_exp exprs[4];
220 int nfrag; /* Number of frags we have to produce */
223 int fragoff; /* Where in the current opcode the frag ends */
230 int nrel; /* Num of reloc strucs in use */
237 /* In a pc relative address the difference between the address
238 of the offset and the address that the offset is relative
239 to. This depends on the addressing mode. Basically this
240 is the value to put in the offset field to address the
241 first byte of the offset, without regarding the special
242 significance of some values (in the branch instruction, for
246 /* Whether this expression needs special pic relocation, and if
248 enum pic_relocation pic_reloc;
251 reloc[5]; /* Five is enough??? */
254 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
255 #define float_of_arch(x) ((x) & mfloat)
256 #define mmu_of_arch(x) ((x) & mmmu)
257 #define arch_coldfire_p(x) (((x) & mcf) != 0)
259 /* Macros for determining if cpu supports a specific addressing mode */
260 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
262 static struct m68k_it the_ins; /* the instruction being assembled */
264 #define op(ex) ((ex)->exp.X_op)
265 #define adds(ex) ((ex)->exp.X_add_symbol)
266 #define subs(ex) ((ex)->exp.X_op_symbol)
267 #define offs(ex) ((ex)->exp.X_add_number)
269 /* Macros for adding things to the m68k_it struct */
271 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
273 /* Static functions. */
275 static void insop PARAMS ((int, const struct m68k_incant *));
276 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
277 static void add_frag PARAMS ((symbolS *, offsetT, int));
279 /* Like addword, but goes BEFORE general operands */
283 const struct m68k_incant *opcode;
286 for(z=the_ins.numo;z>opcode->m_codenum;--z)
287 the_ins.opcode[z]=the_ins.opcode[z-1];
288 for(z=0;z<the_ins.nrel;z++)
289 the_ins.reloc[z].n+=2;
290 for (z = 0; z < the_ins.nfrag; z++)
291 the_ins.fragb[z].fragoff++;
292 the_ins.opcode[opcode->m_codenum]=w;
296 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
299 add_fix (width, exp, pc_rel, pc_fix)
301 struct m68k_exp *exp;
305 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
309 : (the_ins.numo*2)));
310 the_ins.reloc[the_ins.nrel].exp = exp->exp;
311 the_ins.reloc[the_ins.nrel].wid = width;
312 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
314 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
316 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
319 /* Cause an extra frag to be generated here, inserting up to 10 bytes
320 (that value is chosen in the frag_var call in md_assemble). TYPE
321 is the subtype of the frag to be generated; its primary type is
322 rs_machine_dependent.
324 The TYPE parameter is also used by md_convert_frag_1 and
325 md_estimate_size_before_relax. The appropriate type of fixup will
326 be emitted by md_convert_frag_1.
328 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
330 add_frag (add, off, type)
335 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
336 the_ins.fragb[the_ins.nfrag].fadd=add;
337 the_ins.fragb[the_ins.nfrag].foff=off;
338 the_ins.fragb[the_ins.nfrag++].fragty=type;
342 (op (ex) != O_constant && op (ex) != O_big)
344 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
345 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
346 static void m68k_ip PARAMS ((char *));
347 static void insert_reg PARAMS ((const char *, int));
348 static void select_control_regs PARAMS ((void));
349 static void init_regtable PARAMS ((void));
350 static int reverse_16_bits PARAMS ((int in));
351 static int reverse_8_bits PARAMS ((int in));
352 static void install_gen_operand PARAMS ((int mode, int val));
353 static void install_operand PARAMS ((int mode, int val));
354 static void s_bss PARAMS ((int));
355 static void s_data1 PARAMS ((int));
356 static void s_data2 PARAMS ((int));
357 static void s_even PARAMS ((int));
358 static void s_proc PARAMS ((int));
359 static void mri_chip PARAMS ((void));
360 static void s_chip PARAMS ((int));
361 static void s_fopt PARAMS ((int));
362 static void s_opt PARAMS ((int));
363 static void s_reg PARAMS ((int));
364 static void s_restore PARAMS ((int));
365 static void s_save PARAMS ((int));
366 static void s_mri_if PARAMS ((int));
367 static void s_mri_else PARAMS ((int));
368 static void s_mri_endi PARAMS ((int));
369 static void s_mri_break PARAMS ((int));
370 static void s_mri_next PARAMS ((int));
371 static void s_mri_for PARAMS ((int));
372 static void s_mri_endf PARAMS ((int));
373 static void s_mri_repeat PARAMS ((int));
374 static void s_mri_until PARAMS ((int));
375 static void s_mri_while PARAMS ((int));
376 static void s_mri_endw PARAMS ((int));
377 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
378 static void md_convert_frag_1 PARAMS ((fragS *));
380 static int current_architecture;
388 static const struct m68k_cpu archs[] = {
389 { m68000, "68000", 0 },
390 { m68010, "68010", 0 },
391 { m68020, "68020", 0 },
392 { m68030, "68030", 0 },
393 { m68040, "68040", 0 },
394 { m68060, "68060", 0 },
395 { cpu32, "cpu32", 0 },
396 { m68881, "68881", 0 },
397 { m68851, "68851", 0 },
398 { mcf5200, "5200", 0 },
399 { mcf5206e, "5206e", 0 },
400 { mcf5307, "5307", 0},
401 /* Aliases (effectively, so far as gas is concerned) for the above
403 { m68020, "68k", 1 },
404 { m68000, "68008", 1 },
405 { m68000, "68302", 1 },
406 { m68000, "68306", 1 },
407 { m68000, "68307", 1 },
408 { m68000, "68322", 1 },
409 { m68000, "68356", 1 },
410 { m68000, "68ec000", 1 },
411 { m68000, "68hc000", 1 },
412 { m68000, "68hc001", 1 },
413 { m68020, "68ec020", 1 },
414 { m68030, "68ec030", 1 },
415 { m68040, "68ec040", 1 },
416 { m68060, "68ec060", 1 },
417 { cpu32, "68330", 1 },
418 { cpu32, "68331", 1 },
419 { cpu32, "68332", 1 },
420 { cpu32, "68333", 1 },
421 { cpu32, "68334", 1 },
422 { cpu32, "68336", 1 },
423 { cpu32, "68340", 1 },
424 { cpu32, "68341", 1 },
425 { cpu32, "68349", 1 },
426 { cpu32, "68360", 1 },
427 { m68881, "68882", 1 },
428 { mcf5200, "5202", 1 },
429 { mcf5200, "5204", 1 },
430 { mcf5200, "5206", 1 },
433 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
435 /* BCC68000 is for patching in an extra jmp instruction for long offsets
436 on the 68000. The 68000 doesn't support long branches with branchs */
438 /* This table desribes how you change sizes for the various types of variable
439 size expressions. This version only supports two kinds. */
441 /* Note that calls to frag_var need to specify the maximum expansion
442 needed; this is currently 10 bytes for DBCC. */
445 How far Forward this mode will reach:
446 How far Backward this mode will reach:
447 How many bytes this mode will add to the size of the frag
448 Which mode to go to if the offset won't fit in this one
450 relax_typeS md_relax_table[] =
452 {1, 1, 0, 0}, /* First entries aren't used */
453 {1, 1, 0, 0}, /* For no good reason except */
454 {1, 1, 0, 0}, /* that the VAX doesn't either */
457 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
458 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
462 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
463 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
467 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (PCREL, LONG)},
472 {(127), (-128), 0, TAB (BCC68000, SHORT)},
473 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
474 {0, 0, 6, 0}, /* jmp long space */
477 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (DBCC, LONG)},
479 {0, 0, 10, 0}, /* bra/jmp long space */
482 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
483 {32767, -32768, 2, TAB (PCLEA, LONG)},
487 /* For, e.g., jmp pcrel indexed. */
488 {125, -130, 0, TAB (PCINDEX, SHORT)},
489 {32765, -32770, 2, TAB (PCINDEX, LONG)},
494 /* These are the machine dependent pseudo-ops. These are included so
495 the assembler can work on the output from the SUN C compiler, which
499 /* This table describes all the machine specific pseudo-ops the assembler
500 has to support. The fields are:
501 pseudo-op name without dot
502 function to call to execute this pseudo-op
503 Integer arg to pass to the function
505 const pseudo_typeS md_pseudo_table[] =
507 {"data1", s_data1, 0},
508 {"data2", s_data2, 0},
511 {"skip", s_space, 0},
513 #if defined (TE_SUN3) || defined (OBJ_ELF)
514 {"align", s_align_bytes, 0},
517 {"swbeg", s_ignore, 0},
519 {"extend", float_cons, 'x'},
520 {"ldouble", float_cons, 'x'},
522 /* The following pseudo-ops are supported for MRI compatibility. */
524 {"comline", s_space, 1},
526 {"mask2", s_ignore, 0},
529 {"restore", s_restore, 0},
533 {"if.b", s_mri_if, 'b'},
534 {"if.w", s_mri_if, 'w'},
535 {"if.l", s_mri_if, 'l'},
536 {"else", s_mri_else, 0},
537 {"else.s", s_mri_else, 's'},
538 {"else.l", s_mri_else, 'l'},
539 {"endi", s_mri_endi, 0},
540 {"break", s_mri_break, 0},
541 {"break.s", s_mri_break, 's'},
542 {"break.l", s_mri_break, 'l'},
543 {"next", s_mri_next, 0},
544 {"next.s", s_mri_next, 's'},
545 {"next.l", s_mri_next, 'l'},
546 {"for", s_mri_for, 0},
547 {"for.b", s_mri_for, 'b'},
548 {"for.w", s_mri_for, 'w'},
549 {"for.l", s_mri_for, 'l'},
550 {"endf", s_mri_endf, 0},
551 {"repeat", s_mri_repeat, 0},
552 {"until", s_mri_until, 0},
553 {"until.b", s_mri_until, 'b'},
554 {"until.w", s_mri_until, 'w'},
555 {"until.l", s_mri_until, 'l'},
556 {"while", s_mri_while, 0},
557 {"while.b", s_mri_while, 'b'},
558 {"while.w", s_mri_while, 'w'},
559 {"while.l", s_mri_while, 'l'},
560 {"endw", s_mri_endw, 0},
566 /* The mote pseudo ops are put into the opcode table, since they
567 don't start with a . they look like opcodes to gas.
571 extern void obj_coff_section PARAMS ((int));
574 CONST pseudo_typeS mote_pseudo_table[] =
587 {"xdef", s_globl, 0},
589 {"align", s_align_bytes, 0},
591 {"align", s_align_ptwo, 0},
594 {"sect", obj_coff_section, 0},
595 {"section", obj_coff_section, 0},
600 #define issbyte(x) ((x)>=-128 && (x)<=127)
601 #define isubyte(x) ((x)>=0 && (x)<=255)
602 #define issword(x) ((x)>=-32768 && (x)<=32767)
603 #define isuword(x) ((x)>=0 && (x)<=65535)
605 #define isbyte(x) ((x)>= -255 && (x)<=255)
606 #define isword(x) ((x)>=-65536 && (x)<=65535)
607 #define islong(x) (1)
609 extern char *input_line_pointer;
611 static char mklower_table[256];
612 #define mklower(c) (mklower_table[(unsigned char)(c)])
613 static char notend_table[256];
614 static char alt_notend_table[256];
616 (! (notend_table[(unsigned char) *s] \
618 && alt_notend_table[(unsigned char) s[1]])))
620 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
622 #ifdef NO_PCREL_RELOCS
625 make_pcrel_absolute(fixP, add_number)
629 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
631 /* rewrite the PC relative instructions to absolute address ones.
632 * these are rumoured to be faster, and the apollo linker refuses
633 * to deal with the PC relative relocations.
635 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
640 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
646 as_fatal (_("Unknown PC relative instruction"));
651 #endif /* NO_PCREL_RELOCS */
654 tc_coff_fix2rtype (fixP)
657 if (fixP->fx_tcbit && fixP->fx_size == 4)
658 return R_RELLONG_NEG;
659 #ifdef NO_PCREL_RELOCS
660 know (fixP->fx_pcrel == 0);
661 return (fixP->fx_size == 1 ? R_RELBYTE
662 : fixP->fx_size == 2 ? R_DIR16
665 return (fixP->fx_pcrel ?
666 (fixP->fx_size == 1 ? R_PCRBYTE :
667 fixP->fx_size == 2 ? R_PCRWORD :
669 (fixP->fx_size == 1 ? R_RELBYTE :
670 fixP->fx_size == 2 ? R_RELWORD :
679 /* Compute the relocation code for a fixup of SIZE bytes, using pc
680 relative relocation if PCREL is non-zero. PIC says whether a special
681 pic relocation was requested. */
683 static bfd_reloc_code_real_type get_reloc_code
684 PARAMS ((int, int, enum pic_relocation));
686 static bfd_reloc_code_real_type
687 get_reloc_code (size, pcrel, pic)
690 enum pic_relocation pic;
698 return BFD_RELOC_8_GOT_PCREL;
700 return BFD_RELOC_16_GOT_PCREL;
702 return BFD_RELOC_32_GOT_PCREL;
710 return BFD_RELOC_8_GOTOFF;
712 return BFD_RELOC_16_GOTOFF;
714 return BFD_RELOC_32_GOTOFF;
722 return BFD_RELOC_8_PLT_PCREL;
724 return BFD_RELOC_16_PLT_PCREL;
726 return BFD_RELOC_32_PLT_PCREL;
734 return BFD_RELOC_8_PLTOFF;
736 return BFD_RELOC_16_PLTOFF;
738 return BFD_RELOC_32_PLTOFF;
748 return BFD_RELOC_8_PCREL;
750 return BFD_RELOC_16_PCREL;
752 return BFD_RELOC_32_PCREL;
772 as_bad (_("Can not do %d byte pc-relative relocation"), size);
774 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
779 as_bad (_("Can not do %d byte relocation"), size);
781 as_bad (_("Can not do %d byte pic relocation"), size);
784 return BFD_RELOC_NONE;
787 /* Here we decide which fixups can be adjusted to make them relative
788 to the beginning of the section instead of the symbol. Basically
789 we need to make sure that the dynamic relocations are done
790 correctly, so in some cases we force the original symbol to be
793 tc_m68k_fix_adjustable (fixP)
796 /* Prevent all adjustments to global symbols. */
797 if (S_IS_EXTERNAL (fixP->fx_addsy)
798 || S_IS_WEAK (fixP->fx_addsy))
801 /* adjust_reloc_syms doesn't know about the GOT */
802 switch (fixP->fx_r_type)
804 case BFD_RELOC_8_GOT_PCREL:
805 case BFD_RELOC_16_GOT_PCREL:
806 case BFD_RELOC_32_GOT_PCREL:
807 case BFD_RELOC_8_GOTOFF:
808 case BFD_RELOC_16_GOTOFF:
809 case BFD_RELOC_32_GOTOFF:
810 case BFD_RELOC_8_PLT_PCREL:
811 case BFD_RELOC_16_PLT_PCREL:
812 case BFD_RELOC_32_PLT_PCREL:
813 case BFD_RELOC_8_PLTOFF:
814 case BFD_RELOC_16_PLTOFF:
815 case BFD_RELOC_32_PLTOFF:
818 case BFD_RELOC_VTABLE_INHERIT:
819 case BFD_RELOC_VTABLE_ENTRY:
829 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
836 tc_gen_reloc (section, fixp)
841 bfd_reloc_code_real_type code;
846 if (fixp->fx_r_type != BFD_RELOC_NONE)
848 code = fixp->fx_r_type;
850 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
851 that fixup_segment converted a non-PC relative reloc into a
852 PC relative reloc. In such a case, we need to convert the
859 code = BFD_RELOC_8_PCREL;
862 code = BFD_RELOC_16_PCREL;
865 code = BFD_RELOC_32_PCREL;
867 case BFD_RELOC_8_PCREL:
868 case BFD_RELOC_16_PCREL:
869 case BFD_RELOC_32_PCREL:
870 case BFD_RELOC_8_GOT_PCREL:
871 case BFD_RELOC_16_GOT_PCREL:
872 case BFD_RELOC_32_GOT_PCREL:
873 case BFD_RELOC_8_GOTOFF:
874 case BFD_RELOC_16_GOTOFF:
875 case BFD_RELOC_32_GOTOFF:
876 case BFD_RELOC_8_PLT_PCREL:
877 case BFD_RELOC_16_PLT_PCREL:
878 case BFD_RELOC_32_PLT_PCREL:
879 case BFD_RELOC_8_PLTOFF:
880 case BFD_RELOC_16_PLTOFF:
881 case BFD_RELOC_32_PLTOFF:
884 as_bad_where (fixp->fx_file, fixp->fx_line,
885 _("Cannot make %s relocation PC relative"),
886 bfd_get_reloc_code_name (code));
892 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
893 switch (F (fixp->fx_size, fixp->fx_pcrel))
895 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
896 MAP (1, 0, BFD_RELOC_8);
897 MAP (2, 0, BFD_RELOC_16);
898 MAP (4, 0, BFD_RELOC_32);
899 MAP (1, 1, BFD_RELOC_8_PCREL);
900 MAP (2, 1, BFD_RELOC_16_PCREL);
901 MAP (4, 1, BFD_RELOC_32_PCREL);
909 reloc = (arelent *) xmalloc (sizeof (arelent));
910 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
911 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
912 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
915 reloc->addend = fixp->fx_addnumber;
920 reloc->addend = fixp->fx_addnumber;
922 reloc->addend = (section->vma
923 + (fixp->fx_pcrel_adjust == 64
924 ? -1 : fixp->fx_pcrel_adjust)
926 + md_pcrel_from (fixp));
929 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
930 assert (reloc->howto != 0);
935 #endif /* BFD_ASSEMBLER */
937 /* Return zero if the reference to SYMBOL from within the same segment may
941 /* On an ELF system, we can't relax an externally visible symbol,
942 because it may be overridden by a shared library. However, if
943 TARGET_OS is "elf", then we presume that we are assembling for an
944 embedded system, in which case we don't have to worry about shared
945 libraries, and we can relax anything. */
947 #define relaxable_symbol(symbol) \
948 (strcmp (TARGET_OS, "elf") == 0 \
949 || (! S_IS_EXTERNAL (symbol) \
950 && ! S_IS_WEAK (symbol)))
954 #define relaxable_symbol(symbol) 1
958 /* Handle of the OPCODE hash table. NULL means any use before
959 m68k_ip_begin() will crash. */
960 static struct hash_control *op_hash;
962 /* Assemble an m68k instruction. */
969 register struct m68k_op *opP;
970 register const struct m68k_incant *opcode;
971 register const char *s;
972 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
973 char *pdot, *pdotmove;
974 enum m68k_size siz1, siz2;
978 LITTLENUM_TYPE words[6];
979 LITTLENUM_TYPE *wordp;
980 unsigned long ok_arch = 0;
982 if (*instring == ' ')
983 instring++; /* skip leading whitespace */
985 /* Scan up to end of operation-code, which MUST end in end-of-string
986 or exactly 1 space. */
988 for (p = instring; *p != '\0'; p++)
998 the_ins.error = _("No operator");
1002 /* p now points to the end of the opcode name, probably whitespace.
1003 Make sure the name is null terminated by clobbering the
1004 whitespace, look it up in the hash table, then fix it back.
1005 Remove a dot, first, since the opcode tables have none. */
1008 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1009 *pdotmove = pdotmove[1];
1015 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1020 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1021 *pdotmove = pdotmove[-1];
1028 the_ins.error = _("Unknown operator");
1032 /* found a legitimate opcode, start matching operands */
1036 if (opcode->m_operands == 0)
1038 char *old = input_line_pointer;
1040 input_line_pointer = p;
1041 /* Ahh - it's a motorola style psuedo op */
1042 mote_pseudo_table[opcode->m_opnum].poc_handler
1043 (mote_pseudo_table[opcode->m_opnum].poc_val);
1044 input_line_pointer = old;
1050 if (flag_mri && opcode->m_opnum == 0)
1052 /* In MRI mode, random garbage is allowed after an instruction
1053 which accepts no operands. */
1054 the_ins.args = opcode->m_operands;
1055 the_ins.numargs = opcode->m_opnum;
1056 the_ins.numo = opcode->m_codenum;
1057 the_ins.opcode[0] = getone (opcode);
1058 the_ins.opcode[1] = gettwo (opcode);
1062 for (opP = &the_ins.operands[0]; *p; opP++)
1064 p = crack_operand (p, opP);
1068 the_ins.error = opP->error;
1073 opsfound = opP - &the_ins.operands[0];
1075 /* This ugly hack is to support the floating pt opcodes in their
1076 standard form. Essentially, we fake a first enty of type COP#1 */
1077 if (opcode->m_operands[0] == 'I')
1081 for (n = opsfound; n > 0; --n)
1082 the_ins.operands[n] = the_ins.operands[n - 1];
1084 memset ((char *) (&the_ins.operands[0]), '\0',
1085 sizeof (the_ins.operands[0]));
1086 the_ins.operands[0].mode = CONTROL;
1087 the_ins.operands[0].reg = m68k_float_copnum;
1091 /* We've got the operands. Find an opcode that'll accept them */
1094 /* If we didn't get the right number of ops, or we have no
1095 common model with this pattern then reject this pattern. */
1097 ok_arch |= opcode->m_arch;
1098 if (opsfound != opcode->m_opnum
1099 || ((opcode->m_arch & current_architecture) == 0))
1103 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1107 /* Warning: this switch is huge! */
1108 /* I've tried to organize the cases into this order:
1109 non-alpha first, then alpha by letter. Lower-case
1110 goes directly before uppercase counterpart. */
1111 /* Code with multiple case ...: gets sorted by the lowest
1112 case ... it belongs to. I hope this makes sense. */
1218 if (opP->reg == PC || opP->reg == ZPC)
1235 if (opP->reg == PC || opP->reg == ZPC)
1254 if (opP->reg == PC || opP->reg == ZPC)
1264 if (opP->mode != IMMED)
1266 else if (s[1] == 'b'
1267 && ! isvar (&opP->disp)
1268 && (opP->disp.exp.X_op != O_constant
1269 || ! isbyte (opP->disp.exp.X_add_number)))
1271 else if (s[1] == 'B'
1272 && ! isvar (&opP->disp)
1273 && (opP->disp.exp.X_op != O_constant
1274 || ! issbyte (opP->disp.exp.X_add_number)))
1276 else if (s[1] == 'w'
1277 && ! isvar (&opP->disp)
1278 && (opP->disp.exp.X_op != O_constant
1279 || ! isword (opP->disp.exp.X_add_number)))
1281 else if (s[1] == 'W'
1282 && ! isvar (&opP->disp)
1283 && (opP->disp.exp.X_op != O_constant
1284 || ! issword (opP->disp.exp.X_add_number)))
1290 if (opP->mode != IMMED)
1295 if (opP->mode == AREG
1296 || opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == IMMED
1299 || opP->mode == REGLST
1300 || (opP->mode != ABSL
1302 || opP->reg == ZPC)))
1307 if (opP->mode == CONTROL
1308 || opP->mode == FPREG
1309 || opP->mode == REGLST
1310 || opP->mode == IMMED
1311 || (opP->mode != ABSL
1313 || opP->reg == ZPC)))
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST)
1348 if (opP->mode != AINC)
1353 if (opP->mode != ADEC)
1403 if (opP->reg == PC || opP->reg == ZPC)
1424 case '~': /* For now! (JF FOO is this right?) */
1446 if (opP->mode != CONTROL
1447 || (opP->reg != TT0 && opP->reg != TT1))
1452 if (opP->mode != AREG)
1457 if (opP->mode != AINDR)
1462 if (opP->mode != ABSL
1464 && strncmp (instring, "jbsr", 4) == 0))
1469 if (opP->mode != CONTROL || opP->reg != CCR)
1474 if (opP->mode != DISP
1476 || opP->reg > ADDR7)
1481 if (opP->mode != DREG)
1486 if (opP->reg != ACC)
1491 if (opP->mode != FPREG)
1496 if (opP->reg != MACSR)
1501 if (opP->reg != MASK)
1506 if (opP->mode != CONTROL
1513 if (opP->mode != CONTROL
1515 || opP->reg > last_movec_reg)
1519 const enum m68k_register *rp;
1520 for (rp = control_regs; *rp; rp++)
1521 if (*rp == opP->reg)
1529 if (opP->mode != IMMED)
1535 if (opP->mode == DREG
1536 || opP->mode == AREG
1537 || opP->mode == FPREG)
1546 opP->mask = 1 << (opP->reg - DATA0);
1549 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1552 opP->mask = 1 << (opP->reg - FP0 + 16);
1560 else if (opP->mode == CONTROL)
1569 opP->mask = 1 << 24;
1572 opP->mask = 1 << 25;
1575 opP->mask = 1 << 26;
1584 else if (opP->mode != REGLST)
1586 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1588 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1593 if (opP->mode != IMMED)
1595 else if (opP->disp.exp.X_op != O_constant
1596 || ! issbyte (opP->disp.exp.X_add_number))
1598 else if (! m68k_quick
1599 && instring[3] != 'q'
1600 && instring[4] != 'q')
1605 if (opP->mode != DREG
1606 && opP->mode != IMMED
1607 && opP->mode != ABSL)
1612 if (opP->mode != IMMED)
1614 else if (opP->disp.exp.X_op != O_constant
1615 || opP->disp.exp.X_add_number < 1
1616 || opP->disp.exp.X_add_number > 8)
1618 else if (! m68k_quick
1619 && (strncmp (instring, "add", 3) == 0
1620 || strncmp (instring, "sub", 3) == 0)
1621 && instring[3] != 'q')
1626 if (opP->mode != DREG && opP->mode != AREG)
1631 if (opP->mode != AINDR
1632 && (opP->mode != BASE
1634 && opP->reg != ZADDR0)
1635 || opP->disp.exp.X_op != O_absent
1636 || ((opP->index.reg < DATA0
1637 || opP->index.reg > DATA7)
1638 && (opP->index.reg < ADDR0
1639 || opP->index.reg > ADDR7))
1640 || opP->index.size != SIZE_UNSPEC
1641 || opP->index.scale != 1))
1646 if (opP->mode != CONTROL
1647 || ! (opP->reg == FPI
1649 || opP->reg == FPC))
1654 if (opP->mode != CONTROL || opP->reg != SR)
1659 if (opP->mode != IMMED)
1661 else if (opP->disp.exp.X_op != O_constant
1662 || opP->disp.exp.X_add_number < 0
1663 || opP->disp.exp.X_add_number > 7)
1668 if (opP->mode != CONTROL || opP->reg != USP)
1672 /* JF these are out of order. We could put them
1673 in order if we were willing to put up with
1674 bunches of #ifdef m68851s in the code.
1676 Don't forget that you need these operands
1677 to use 68030 MMU instructions. */
1679 /* Memory addressing mode used by pflushr */
1681 if (opP->mode == CONTROL
1682 || opP->mode == FPREG
1683 || opP->mode == DREG
1684 || opP->mode == AREG
1685 || opP->mode == REGLST)
1687 /* We should accept immediate operands, but they
1688 supposedly have to be quad word, and we don't
1689 handle that. I would like to see what a Motorola
1690 assembler does before doing something here. */
1691 if (opP->mode == IMMED)
1696 if (opP->mode != CONTROL
1697 || (opP->reg != SFC && opP->reg != DFC))
1702 if (opP->mode != CONTROL || opP->reg != TC)
1707 if (opP->mode != CONTROL || opP->reg != AC)
1712 if (opP->mode != CONTROL
1715 && opP->reg != SCC))
1720 if (opP->mode != CONTROL
1726 if (opP->mode != CONTROL
1729 && opP->reg != CRP))
1734 if (opP->mode != CONTROL
1735 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1736 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1741 if (opP->mode != CONTROL || opP->reg != PSR)
1746 if (opP->mode != CONTROL || opP->reg != PCSR)
1751 if (opP->mode != CONTROL
1758 } /* not a cache specifier. */
1762 if (opP->mode != ABSL)
1767 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1769 /* FIXME: kludge instead of fixing parser:
1770 upper/lower registers are *not* CONTROL
1771 registers, but ordinary ones. */
1772 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1773 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1781 } /* switch on type of operand */
1785 } /* for each operand */
1786 } /* if immediately wrong */
1793 opcode = opcode->m_next;
1798 && !(ok_arch & current_architecture))
1803 _("invalid instruction for this architecture; needs "));
1804 cp = buf + strlen (buf);
1808 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1811 strcpy (cp, _("mmu (68030 or 68851)"));
1814 strcpy (cp, _("68020 or higher"));
1817 strcpy (cp, _("68000 or higher"));
1820 strcpy (cp, _("68010 or higher"));
1824 int got_one = 0, idx;
1825 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1828 if ((archs[idx].arch & ok_arch)
1829 && ! archs[idx].alias)
1833 strcpy (cp, " or ");
1837 strcpy (cp, archs[idx].name);
1843 cp = xmalloc (strlen (buf) + 1);
1848 the_ins.error = _("operands mismatch");
1850 } /* Fell off the end */
1855 /* now assemble it */
1857 the_ins.args = opcode->m_operands;
1858 the_ins.numargs = opcode->m_opnum;
1859 the_ins.numo = opcode->m_codenum;
1860 the_ins.opcode[0] = getone (opcode);
1861 the_ins.opcode[1] = gettwo (opcode);
1863 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1865 /* This switch is a doozy.
1866 Watch the first step; its a big one! */
1894 tmpreg = 0x3c; /* 7.4 */
1895 if (strchr ("bwl", s[1]))
1896 nextword = get_num (&opP->disp, 80);
1898 nextword = get_num (&opP->disp, 0);
1899 if (isvar (&opP->disp))
1900 add_fix (s[1], &opP->disp, 0, 0);
1904 if (!isbyte (nextword))
1905 opP->error = _("operand out of range");
1910 if (!isword (nextword))
1911 opP->error = _("operand out of range");
1916 if (!issword (nextword))
1917 opP->error = _("operand out of range");
1922 addword (nextword >> 16);
1949 /* We gotta put out some float */
1950 if (op (&opP->disp) != O_big)
1955 /* Can other cases happen here? */
1956 if (op (&opP->disp) != O_constant)
1959 val = (valueT) offs (&opP->disp);
1963 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1964 val >>= LITTLENUM_NUMBER_OF_BITS;
1968 offs (&opP->disp) = gencnt;
1970 if (offs (&opP->disp) > 0)
1972 if (offs (&opP->disp) > baseo)
1974 as_warn (_("Bignum too big for %c format; truncated"),
1976 offs (&opP->disp) = baseo;
1978 baseo -= offs (&opP->disp);
1981 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1982 offs (&opP->disp)--;
1987 gen_to_words (words, baseo, (long) outro);
1988 for (wordp = words; baseo--; wordp++)
1992 tmpreg = opP->reg - DATA; /* 0.dreg */
1995 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1998 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2001 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2004 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2008 nextword = get_num (&opP->disp, 80);
2011 && ! isvar (&opP->disp)
2014 opP->disp.exp.X_op = O_symbol;
2015 #ifndef BFD_ASSEMBLER
2016 opP->disp.exp.X_add_symbol = &abs_symbol;
2018 opP->disp.exp.X_add_symbol =
2019 section_symbol (absolute_section);
2023 /* Force into index mode. Hope this works */
2025 /* We do the first bit for 32-bit displacements, and the
2026 second bit for 16 bit ones. It is possible that we
2027 should make the default be WORD instead of LONG, but
2028 I think that'd break GCC, so we put up with a little
2029 inefficiency for the sake of working output. */
2031 if (!issword (nextword)
2032 || (isvar (&opP->disp)
2033 && ((opP->disp.size == SIZE_UNSPEC
2034 && flag_short_refs == 0
2035 && cpu_of_arch (current_architecture) >= m68020
2036 && ! arch_coldfire_p (current_architecture))
2037 || opP->disp.size == SIZE_LONG)))
2039 if (cpu_of_arch (current_architecture) < m68020
2040 || arch_coldfire_p (current_architecture))
2042 _("displacement too large for this architecture; needs 68020 or higher");
2044 tmpreg = 0x3B; /* 7.3 */
2046 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2047 if (isvar (&opP->disp))
2051 if (opP->disp.size == SIZE_LONG
2053 /* If the displacement needs pic
2054 relocation it cannot be relaxed. */
2055 || opP->disp.pic_reloc != pic_none
2060 add_fix ('l', &opP->disp, 1, 2);
2064 add_frag (adds (&opP->disp),
2066 TAB (PCLEA, SZ_UNDEF));
2073 add_fix ('l', &opP->disp, 0, 0);
2078 addword (nextword >> 16);
2083 tmpreg = 0x3A; /* 7.2 */
2085 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2087 if (isvar (&opP->disp))
2091 add_fix ('w', &opP->disp, 1, 0);
2094 add_fix ('w', &opP->disp, 0, 0);
2104 baseo = get_num (&opP->disp, 80);
2105 if (opP->mode == POST || opP->mode == PRE)
2106 outro = get_num (&opP->odisp, 80);
2107 /* Figure out the `addressing mode'.
2108 Also turn on the BASE_DISABLE bit, if needed. */
2109 if (opP->reg == PC || opP->reg == ZPC)
2111 tmpreg = 0x3b; /* 7.3 */
2112 if (opP->reg == ZPC)
2115 else if (opP->reg == 0)
2118 tmpreg = 0x30; /* 6.garbage */
2120 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2123 tmpreg = 0x30 + opP->reg - ZADDR0;
2126 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2128 siz1 = opP->disp.size;
2129 if (opP->mode == POST || opP->mode == PRE)
2130 siz2 = opP->odisp.size;
2134 /* Index register stuff */
2135 if (opP->index.reg != 0
2136 && opP->index.reg >= DATA
2137 && opP->index.reg <= ADDR7)
2139 nextword |= (opP->index.reg - DATA) << 12;
2141 if (opP->index.size == SIZE_LONG
2142 || (opP->index.size == SIZE_UNSPEC
2143 && m68k_index_width_default == SIZE_LONG))
2146 if ((opP->index.scale != 1
2147 && cpu_of_arch (current_architecture) < m68020)
2148 || (opP->index.scale == 8
2149 && arch_coldfire_p (current_architecture)))
2152 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2155 if (arch_coldfire_p (current_architecture)
2156 && opP->index.size == SIZE_WORD)
2157 opP->error = _("invalid index size for coldfire");
2159 switch (opP->index.scale)
2176 GET US OUT OF HERE! */
2178 /* Must be INDEX, with an index register. Address
2179 register cannot be ZERO-PC, and either :b was
2180 forced, or we know it will fit. For a 68000 or
2181 68010, force this mode anyways, because the
2182 larger modes aren't supported. */
2183 if (opP->mode == BASE
2184 && ((opP->reg >= ADDR0
2185 && opP->reg <= ADDR7)
2188 if (siz1 == SIZE_BYTE
2189 || cpu_of_arch (current_architecture) < m68020
2190 || arch_coldfire_p (current_architecture)
2191 || (siz1 == SIZE_UNSPEC
2192 && ! isvar (&opP->disp)
2193 && issbyte (baseo)))
2195 nextword += baseo & 0xff;
2197 if (isvar (&opP->disp))
2199 /* Do a byte relocation. If it doesn't
2200 fit (possible on m68000) let the
2201 fixup processing complain later. */
2203 add_fix ('B', &opP->disp, 1, 1);
2205 add_fix ('B', &opP->disp, 0, 0);
2207 else if (siz1 != SIZE_BYTE)
2209 if (siz1 != SIZE_UNSPEC)
2210 as_warn (_("Forcing byte displacement"));
2211 if (! issbyte (baseo))
2212 opP->error = _("byte displacement out of range");
2217 else if (siz1 == SIZE_UNSPEC
2219 && isvar (&opP->disp)
2220 && subs (&opP->disp) == NULL
2222 /* If the displacement needs pic
2223 relocation it cannot be relaxed. */
2224 && opP->disp.pic_reloc == pic_none
2228 /* The code in md_convert_frag_1 needs to be
2229 able to adjust nextword. Call frag_grow
2230 to ensure that we have enough space in
2231 the frag obstack to make all the bytes
2234 nextword += baseo & 0xff;
2236 add_frag (adds (&opP->disp), offs (&opP->disp),
2237 TAB (PCINDEX, SZ_UNDEF));
2245 nextword |= 0x40; /* No index reg */
2246 if (opP->index.reg >= ZDATA0
2247 && opP->index.reg <= ZDATA7)
2248 nextword |= (opP->index.reg - ZDATA0) << 12;
2249 else if (opP->index.reg >= ZADDR0
2250 || opP->index.reg <= ZADDR7)
2251 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2254 /* It isn't simple. */
2256 if (cpu_of_arch (current_architecture) < m68020
2257 || arch_coldfire_p (current_architecture))
2259 _("invalid operand mode for this architecture; needs 68020 or higher");
2262 /* If the guy specified a width, we assume that it is
2263 wide enough. Maybe it isn't. If so, we lose. */
2267 if (isvar (&opP->disp)
2269 : ! issword (baseo))
2274 else if (! isvar (&opP->disp) && baseo == 0)
2283 as_warn (_(":b not permitted; defaulting to :w"));
2293 /* Figure out innner displacement stuff */
2294 if (opP->mode == POST || opP->mode == PRE)
2296 if (cpu_of_arch (current_architecture) & cpu32)
2297 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2301 if (isvar (&opP->odisp)
2303 : ! issword (outro))
2308 else if (! isvar (&opP->odisp) && outro == 0)
2317 as_warn (_(":b not permitted; defaulting to :w"));
2326 if (opP->mode == POST
2327 && (nextword & 0x40) == 0)
2332 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2334 if (opP->reg == PC || opP->reg == ZPC)
2335 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2337 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2339 if (siz1 == SIZE_LONG)
2340 addword (baseo >> 16);
2341 if (siz1 != SIZE_UNSPEC)
2344 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2345 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2346 if (siz2 == SIZE_LONG)
2347 addword (outro >> 16);
2348 if (siz2 != SIZE_UNSPEC)
2354 nextword = get_num (&opP->disp, 80);
2355 switch (opP->disp.size)
2360 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2362 tmpreg = 0x38; /* 7.0 */
2366 /* Don't generate pc relative code on 68010 and
2368 if (isvar (&opP->disp)
2369 && !subs (&opP->disp)
2370 && adds (&opP->disp)
2372 /* If the displacement needs pic relocation it
2373 cannot be relaxed. */
2374 && opP->disp.pic_reloc == pic_none
2376 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2377 && relaxable_symbol (adds (&opP->disp))
2378 && HAVE_LONG_BRANCH(current_architecture)
2380 && !strchr ("~%&$?", s[0]))
2382 tmpreg = 0x3A; /* 7.2 */
2383 add_frag (adds (&opP->disp),
2385 TAB (PCREL, SZ_UNDEF));
2388 /* Fall through into long */
2390 if (isvar (&opP->disp))
2391 add_fix ('l', &opP->disp, 0, 0);
2393 tmpreg = 0x39;/* 7.1 mode */
2394 addword (nextword >> 16);
2399 as_bad (_("unsupported byte value; use a different suffix"));
2401 case SIZE_WORD: /* Word */
2402 if (isvar (&opP->disp))
2403 add_fix ('w', &opP->disp, 0, 0);
2405 tmpreg = 0x38;/* 7.0 mode */
2413 as_bad (_("unknown/incorrect operand"));
2416 install_gen_operand (s[1], tmpreg);
2422 { /* JF: I hate floating point! */
2437 tmpreg = get_num (&opP->disp, tmpreg);
2438 if (isvar (&opP->disp))
2439 add_fix (s[1], &opP->disp, 0, 0);
2442 case 'b': /* Danger: These do no check for
2443 certain types of overflow.
2445 if (!isbyte (tmpreg))
2446 opP->error = _("out of range");
2447 insop (tmpreg, opcode);
2448 if (isvar (&opP->disp))
2449 the_ins.reloc[the_ins.nrel - 1].n =
2450 (opcode->m_codenum) * 2 + 1;
2453 if (!issbyte (tmpreg))
2454 opP->error = _("out of range");
2455 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2456 if (isvar (&opP->disp))
2457 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2460 if (!isword (tmpreg))
2461 opP->error = _("out of range");
2462 insop (tmpreg, opcode);
2463 if (isvar (&opP->disp))
2464 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2467 if (!issword (tmpreg))
2468 opP->error = _("out of range");
2469 insop (tmpreg, opcode);
2470 if (isvar (&opP->disp))
2471 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2474 /* Because of the way insop works, we put these two out
2476 insop (tmpreg, opcode);
2477 insop (tmpreg >> 16, opcode);
2478 if (isvar (&opP->disp))
2479 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2486 install_operand (s[1], tmpreg);
2497 install_operand (s[1], opP->reg - ADDR);
2501 tmpreg = get_num (&opP->disp, 80);
2505 /* The pc_fix argument winds up in fx_pcrel_adjust,
2506 which is a char, and may therefore be unsigned. We
2507 want to pass -1, but we pass 64 instead, and convert
2508 back in md_pcrel_from. */
2509 add_fix ('B', &opP->disp, 1, 64);
2512 add_fix ('w', &opP->disp, 1, 0);
2517 if (!HAVE_LONG_BRANCH(current_architecture))
2518 as_warn (_("Can't use long branches on 68000/68010/5200"));
2519 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2520 add_fix ('l', &opP->disp, 1, 0);
2525 if (subs (&opP->disp)) /* We can't relax it */
2529 /* If the displacement needs pic relocation it cannot be
2531 if (opP->disp.pic_reloc != pic_none)
2535 /* This could either be a symbol, or an absolute
2536 address. No matter, the frag hacking will finger it
2537 out. Not quite: it can't switch from BRANCH to
2538 BCC68000 for the case where opnd is absolute (it
2539 needs to use the 68000 hack since no conditional abs
2541 if (( !HAVE_LONG_BRANCH(current_architecture)
2542 || (0 == adds (&opP->disp)))
2543 && (the_ins.opcode[0] >= 0x6200)
2544 && (the_ins.opcode[0] <= 0x6f00))
2545 add_frag (adds (&opP->disp), offs (&opP->disp),
2546 TAB (BCC68000, SZ_UNDEF));
2548 add_frag (adds (&opP->disp), offs (&opP->disp),
2549 TAB (ABRANCH, SZ_UNDEF));
2552 if (isvar (&opP->disp))
2555 /* check for DBcc instruction */
2556 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2558 /* size varies if patch */
2559 /* needed for long form */
2560 add_frag (adds (&opP->disp), offs (&opP->disp),
2561 TAB (DBCC, SZ_UNDEF));
2565 add_fix ('w', &opP->disp, 1, 0);
2569 case 'C': /* Fixed size LONG coproc branches */
2570 add_fix ('l', &opP->disp, 1, 0);
2574 case 'c': /* Var size Coprocesssor branches */
2575 if (subs (&opP->disp))
2577 add_fix ('l', &opP->disp, 1, 0);
2578 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2580 else if (adds (&opP->disp))
2581 add_frag (adds (&opP->disp), offs (&opP->disp),
2582 TAB (FBRANCH, SZ_UNDEF));
2585 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2586 TAB(FBRANCH,SHORT)); */
2587 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2588 add_fix ('l', &opP->disp, 1, 0);
2598 case 'C': /* Ignore it */
2601 case 'd': /* JF this is a kludge */
2602 install_operand ('s', opP->reg - ADDR);
2603 tmpreg = get_num (&opP->disp, 80);
2604 if (!issword (tmpreg))
2606 as_warn (_("Expression out of range, using 0"));
2613 install_operand (s[1], opP->reg - DATA);
2616 case 'E': /* Ignore it */
2620 install_operand (s[1], opP->reg - FP0);
2623 case 'G': /* Ignore it */
2628 tmpreg = opP->reg - COP0;
2629 install_operand (s[1], tmpreg);
2632 case 'J': /* JF foo */
2705 install_operand (s[1], tmpreg);
2709 tmpreg = get_num (&opP->disp, 55);
2710 install_operand (s[1], tmpreg & 0x7f);
2717 if (tmpreg & 0x7FF0000)
2718 as_bad (_("Floating point register in register list"));
2719 insop (reverse_16_bits (tmpreg), opcode);
2723 if (tmpreg & 0x700FFFF)
2724 as_bad (_("Wrong register in floating-point reglist"));
2725 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2733 if (tmpreg & 0x7FF0000)
2734 as_bad (_("Floating point register in register list"));
2735 insop (tmpreg, opcode);
2737 else if (s[1] == '8')
2739 if (tmpreg & 0x0FFFFFF)
2740 as_bad (_("incorrect register in reglist"));
2741 install_operand (s[1], tmpreg >> 24);
2745 if (tmpreg & 0x700FFFF)
2746 as_bad (_("wrong register in floating-point reglist"));
2748 install_operand (s[1], tmpreg >> 16);
2753 install_operand (s[1], get_num (&opP->disp, 60));
2757 tmpreg = ((opP->mode == DREG)
2758 ? 0x20 + opP->reg - DATA
2759 : (get_num (&opP->disp, 40) & 0x1F));
2760 install_operand (s[1], tmpreg);
2764 tmpreg = get_num (&opP->disp, 10);
2767 install_operand (s[1], tmpreg);
2771 /* This depends on the fact that ADDR registers are eight
2772 more than their corresponding DATA regs, so the result
2773 will have the ADDR_REG bit set */
2774 install_operand (s[1], opP->reg - DATA);
2778 if (opP->mode == AINDR)
2779 install_operand (s[1], opP->reg - DATA);
2781 install_operand (s[1], opP->index.reg - DATA);
2785 if (opP->reg == FPI)
2787 else if (opP->reg == FPS)
2789 else if (opP->reg == FPC)
2793 install_operand (s[1], tmpreg);
2796 case 'S': /* Ignore it */
2800 install_operand (s[1], get_num (&opP->disp, 30));
2803 case 'U': /* Ignore it */
2822 as_fatal (_("failed sanity check"));
2823 } /* switch on cache token */
2824 install_operand (s[1], tmpreg);
2827 /* JF: These are out of order, I fear. */
2840 install_operand (s[1], tmpreg);
2866 install_operand (s[1], tmpreg);
2870 if (opP->reg == VAL)
2889 install_operand (s[1], tmpreg);
2903 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2914 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2920 install_operand (s[1], tmpreg);
2923 know (opP->reg == PSR);
2926 know (opP->reg == PCSR);
2941 install_operand (s[1], tmpreg);
2944 tmpreg = get_num (&opP->disp, 20);
2945 install_operand (s[1], tmpreg);
2947 case '_': /* used only for move16 absolute 32-bit address */
2948 if (isvar (&opP->disp))
2949 add_fix ('l', &opP->disp, 0, 0);
2950 tmpreg = get_num (&opP->disp, 80);
2951 addword (tmpreg >> 16);
2952 addword (tmpreg & 0xFFFF);
2955 install_operand (s[1], opP->reg - DATA0L);
2956 opP->reg -= (DATA0L);
2957 opP->reg &= 0x0F; /* remove upper/lower bit */
2964 /* By the time whe get here (FINALLY) the_ins contains the complete
2965 instruction, ready to be emitted. . . */
2969 reverse_16_bits (in)
2975 static int mask[16] =
2977 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2978 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2980 for (n = 0; n < 16; n++)
2983 out |= mask[15 - n];
2986 } /* reverse_16_bits() */
2995 static int mask[8] =
2997 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3000 for (n = 0; n < 8; n++)
3006 } /* reverse_8_bits() */
3008 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3009 (that value is chosen in the frag_var call in md_assemble). TYPE
3010 is the subtype of the frag to be generated; its primary type is
3011 rs_machine_dependent.
3013 The TYPE parameter is also used by md_convert_frag_1 and
3014 md_estimate_size_before_relax. The appropriate type of fixup will
3015 be emitted by md_convert_frag_1.
3017 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3019 install_operand (mode, val)
3026 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3029 the_ins.opcode[0] |= val << 9;
3032 the_ins.opcode[1] |= val << 12;
3035 the_ins.opcode[1] |= val << 6;
3038 the_ins.opcode[1] |= val;
3041 the_ins.opcode[2] |= val << 12;
3044 the_ins.opcode[2] |= val << 6;
3047 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3048 three words long! */
3050 the_ins.opcode[2] |= val;
3053 the_ins.opcode[1] |= val << 7;
3056 the_ins.opcode[1] |= val << 10;
3060 the_ins.opcode[1] |= val << 5;
3065 the_ins.opcode[1] |= (val << 10) | (val << 7);
3068 the_ins.opcode[1] |= (val << 12) | val;
3071 the_ins.opcode[0] |= val = 0xff;
3074 the_ins.opcode[0] |= val << 9;
3077 the_ins.opcode[1] |= val;
3080 the_ins.opcode[1] |= val;
3081 the_ins.numo++; /* What a hack */
3084 the_ins.opcode[1] |= val << 4;
3092 the_ins.opcode[0] |= (val << 6);
3095 the_ins.opcode[1] = (val >> 16);
3096 the_ins.opcode[2] = val & 0xffff;
3099 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3100 the_ins.opcode[0] |= ((val & 0x7) << 9);
3101 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3104 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3105 the_ins.opcode[0] |= ((val & 0x7) << 9);
3108 the_ins.opcode[1] |= val << 12;
3109 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3112 the_ins.opcode[0] |= (val & 0xF);
3113 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3116 the_ins.opcode[1] |= (val & 0xF);
3117 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3120 the_ins.opcode[1] |= ((val != 1) << 10);
3124 as_fatal (_("failed sanity check."));
3126 } /* install_operand() */
3129 install_gen_operand (mode, val)
3136 the_ins.opcode[0] |= val;
3139 /* This is a kludge!!! */
3140 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3149 the_ins.opcode[0] |= val;
3151 /* more stuff goes here */
3153 as_fatal (_("failed sanity check."));
3155 } /* install_gen_operand() */
3158 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3159 * then deal with the bitfield hack.
3163 crack_operand (str, opP)
3165 register struct m68k_op *opP;
3167 register int parens;
3169 register char *beg_str;
3177 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3183 else if (*str == ')')
3187 opP->error = _("Extra )");
3193 if (flag_mri && *str == '\'')
3194 inquote = ! inquote;
3196 if (!*str && parens)
3198 opP->error = _("Missing )");
3203 if (m68k_ip_op (beg_str, opP) != 0)
3210 c = *++str; /* JF bitfield hack */
3215 as_bad (_("Missing operand"));
3218 /* Detect MRI REG symbols and convert them to REGLSTs. */
3219 if (opP->mode == CONTROL && (int)opP->reg < 0)
3222 opP->mask = ~(int)opP->reg;
3229 /* This is the guts of the machine-dependent assembler. STR points to a
3230 machine dependent instruction. This function is supposed to emit
3231 the frags/bytes it assembles to.
3235 insert_reg (regname, regnum)
3236 const char *regname;
3242 #ifdef REGISTER_PREFIX
3243 if (!flag_reg_prefix_optional)
3245 buf[0] = REGISTER_PREFIX;
3246 strcpy (buf + 1, regname);
3251 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3252 &zero_address_frag));
3254 for (i = 0; regname[i]; i++)
3255 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3258 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3259 &zero_address_frag));
3268 static const struct init_entry init_table[] =
3327 /* control registers */
3328 { "sfc", SFC }, /* Source Function Code */
3330 { "dfc", DFC }, /* Destination Function Code */
3332 { "cacr", CACR }, /* Cache Control Register */
3333 { "caar", CAAR }, /* Cache Address Register */
3335 { "usp", USP }, /* User Stack Pointer */
3336 { "vbr", VBR }, /* Vector Base Register */
3337 { "msp", MSP }, /* Master Stack Pointer */
3338 { "isp", ISP }, /* Interrupt Stack Pointer */
3340 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3341 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3342 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3343 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3345 /* 68ec040 versions of same */
3346 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3347 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3348 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3349 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3351 /* mcf5200 versions of same. The ColdFire programmer's reference
3352 manual indicated that the order is 2,3,0,1, but Ken Rose
3353 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3354 { "acr0", ITT0 }, /* Access Control Unit 0 */
3355 { "acr1", ITT1 }, /* Access Control Unit 1 */
3356 { "acr2", DTT0 }, /* Access Control Unit 2 */
3357 { "acr3", DTT1 }, /* Access Control Unit 3 */
3359 { "tc", TC }, /* MMU Translation Control Register */
3362 { "mmusr", MMUSR }, /* MMU Status Register */
3363 { "srp", SRP }, /* User Root Pointer */
3364 { "urp", URP }, /* Supervisor Root Pointer */
3369 { "rombar", ROMBAR }, /* ROM Base Address Register */
3370 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3371 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3372 { "mbar", MBAR }, /* Module Base Address Register */
3373 /* end of control registers */
3407 /* 68ec030 versions of same */
3410 /* 68ec030 access control unit, identical to 030 MMU status reg */
3413 /* Suppressed data and address registers. */
3431 /* Upper and lower data and address registers, used by macw and msacw. */
3475 for (i = 0; init_table[i].name; i++)
3476 insert_reg (init_table[i].name, init_table[i].number);
3479 static int no_68851, no_68881;
3482 /* a.out machine type. Default to 68020. */
3483 int m68k_aout_machtype = 2;
3495 int shorts_this_frag;
3498 /* In MRI mode, the instruction and operands are separated by a
3499 space. Anything following the operands is a comment. The label
3500 has already been removed. */
3508 for (s = str; *s != '\0'; s++)
3510 if ((*s == ' ' || *s == '\t') && ! inquote)
3528 inquote = ! inquote;
3533 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3538 for (n = 0; n < the_ins.numargs; n++)
3539 if (the_ins.operands[n].error)
3541 er = the_ins.operands[n].error;
3547 as_bad (_("%s -- statement `%s' ignored"), er, str);
3551 /* If there is a current label, record that it marks an instruction. */
3552 if (current_label != NULL)
3554 current_label->text = 1;
3555 current_label = NULL;
3558 if (the_ins.nfrag == 0)
3560 /* No frag hacking involved; just put it out */
3561 toP = frag_more (2 * the_ins.numo);
3562 fromP = &the_ins.opcode[0];
3563 for (m = the_ins.numo; m; --m)
3565 md_number_to_chars (toP, (long) (*fromP), 2);
3569 /* put out symbol-dependent info */
3570 for (m = 0; m < the_ins.nrel; m++)
3572 switch (the_ins.reloc[m].wid)
3591 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3592 the_ins.reloc[m].wid);
3595 fixP = fix_new_exp (frag_now,
3596 ((toP - frag_now->fr_literal)
3597 - the_ins.numo * 2 + the_ins.reloc[m].n),
3599 &the_ins.reloc[m].exp,
3600 the_ins.reloc[m].pcrel,
3601 get_reloc_code (n, the_ins.reloc[m].pcrel,
3602 the_ins.reloc[m].pic_reloc));
3603 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3604 if (the_ins.reloc[m].wid == 'B')
3605 fixP->fx_signed = 1;
3610 /* There's some frag hacking */
3611 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3616 wid = 2 * the_ins.fragb[n].fragoff;
3618 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3619 toP = frag_more (wid);
3621 shorts_this_frag = 0;
3622 for (m = wid / 2; m; --m)
3624 md_number_to_chars (toP, (long) (*fromP), 2);
3629 for (m = 0; m < the_ins.nrel; m++)
3631 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3633 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3636 wid = the_ins.reloc[m].wid;
3639 the_ins.reloc[m].wid = 0;
3640 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3642 fixP = fix_new_exp (frag_now,
3643 ((toP - frag_now->fr_literal)
3644 - the_ins.numo * 2 + the_ins.reloc[m].n),
3646 &the_ins.reloc[m].exp,
3647 the_ins.reloc[m].pcrel,
3648 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3649 the_ins.reloc[m].pic_reloc));
3650 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3652 (void) frag_var (rs_machine_dependent, 10, 0,
3653 (relax_substateT) (the_ins.fragb[n].fragty),
3654 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3656 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3657 shorts_this_frag = 0;
3660 toP = frag_more (n * sizeof (short));
3663 md_number_to_chars (toP, (long) (*fromP), 2);
3669 for (m = 0; m < the_ins.nrel; m++)
3673 wid = the_ins.reloc[m].wid;
3676 the_ins.reloc[m].wid = 0;
3677 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3679 fixP = fix_new_exp (frag_now,
3680 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3681 - shorts_this_frag * 2),
3683 &the_ins.reloc[m].exp,
3684 the_ins.reloc[m].pcrel,
3685 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3686 the_ins.reloc[m].pic_reloc));
3687 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3695 * md_begin -- set up hash tables with 68000 instructions.
3696 * similar to what the vax assembler does. ---phr
3698 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3699 a copy of it at runtime, adding in the information we want but isn't
3700 there. I think it'd be better to have an awk script hack the table
3701 at compile time. Or even just xstr the table and use it as-is. But
3702 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3705 register const struct m68k_opcode *ins;
3706 register struct m68k_incant *hack, *slak;
3707 register const char *retval = 0; /* empty string, or error msg text */
3708 register unsigned int i;
3713 flag_reg_prefix_optional = 1;
3715 if (! m68k_rel32_from_cmdline)
3719 op_hash = hash_new ();
3721 obstack_begin (&robyn, 4000);
3722 for (i = 0; i < m68k_numopcodes; i++)
3724 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3727 ins = &m68k_opcodes[i];
3728 /* We *could* ignore insns that don't match our arch here
3729 but just leaving them out of the hash. */
3730 slak->m_operands = ins->args;
3731 slak->m_opnum = strlen (slak->m_operands) / 2;
3732 slak->m_arch = ins->arch;
3733 slak->m_opcode = ins->opcode;
3734 /* This is kludgey */
3735 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3736 if (i + 1 != m68k_numopcodes
3737 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3739 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3744 slak = slak->m_next;
3748 retval = hash_insert (op_hash, ins->name, (char *) hack);
3750 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3753 for (i = 0; i < m68k_numaliases; i++)
3755 const char *name = m68k_opcode_aliases[i].primary;
3756 const char *alias = m68k_opcode_aliases[i].alias;
3757 PTR val = hash_find (op_hash, name);
3759 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3760 retval = hash_insert (op_hash, alias, val);
3762 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3765 /* In MRI mode, all unsized branches are variable sized. Normally,
3766 they are word sized. */
3769 static struct m68k_opcode_alias mri_aliases[] =
3789 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3791 const char *name = mri_aliases[i].primary;
3792 const char *alias = mri_aliases[i].alias;
3793 PTR val = hash_find (op_hash, name);
3795 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3796 retval = hash_jam (op_hash, alias, val);
3798 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3802 for (i = 0; i < sizeof (mklower_table); i++)
3803 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3805 for (i = 0; i < sizeof (notend_table); i++)
3807 notend_table[i] = 0;
3808 alt_notend_table[i] = 0;
3810 notend_table[','] = 1;
3811 notend_table['{'] = 1;
3812 notend_table['}'] = 1;
3813 alt_notend_table['a'] = 1;
3814 alt_notend_table['A'] = 1;
3815 alt_notend_table['d'] = 1;
3816 alt_notend_table['D'] = 1;
3817 alt_notend_table['#'] = 1;
3818 alt_notend_table['&'] = 1;
3819 alt_notend_table['f'] = 1;
3820 alt_notend_table['F'] = 1;
3821 #ifdef REGISTER_PREFIX
3822 alt_notend_table[REGISTER_PREFIX] = 1;
3825 /* We need to put '(' in alt_notend_table to handle
3826 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3828 alt_notend_table['('] = 1;
3830 /* We need to put '@' in alt_notend_table to handle
3831 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3833 alt_notend_table['@'] = 1;
3835 /* We need to put digits in alt_notend_table to handle
3836 bfextu %d0{24:1},%d0
3838 alt_notend_table['0'] = 1;
3839 alt_notend_table['1'] = 1;
3840 alt_notend_table['2'] = 1;
3841 alt_notend_table['3'] = 1;
3842 alt_notend_table['4'] = 1;
3843 alt_notend_table['5'] = 1;
3844 alt_notend_table['6'] = 1;
3845 alt_notend_table['7'] = 1;
3846 alt_notend_table['8'] = 1;
3847 alt_notend_table['9'] = 1;
3849 #ifndef MIT_SYNTAX_ONLY
3850 /* Insert pseudo ops, these have to go into the opcode table since
3851 gas expects pseudo ops to start with a dot */
3854 while (mote_pseudo_table[n].poc_name)
3856 hack = (struct m68k_incant *)
3857 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3858 hash_insert (op_hash,
3859 mote_pseudo_table[n].poc_name, (char *) hack);
3860 hack->m_operands = 0;
3870 record_alignment (text_section, 2);
3871 record_alignment (data_section, 2);
3872 record_alignment (bss_section, 2);
3877 select_control_regs ()
3879 /* Note which set of "movec" control registers is available. */
3880 switch (cpu_of_arch (current_architecture))
3883 control_regs = m68000_control_regs;
3886 control_regs = m68010_control_regs;
3890 control_regs = m68020_control_regs;
3893 control_regs = m68040_control_regs;
3896 control_regs = m68060_control_regs;
3899 control_regs = cpu32_control_regs;
3904 control_regs = mcf_control_regs;
3912 m68k_init_after_args ()
3914 if (cpu_of_arch (current_architecture) == 0)
3917 const char *default_cpu = TARGET_CPU;
3919 if (*default_cpu == 'm')
3921 for (i = 0; i < n_archs; i++)
3922 if (strcasecmp (default_cpu, archs[i].name) == 0)
3926 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3927 current_architecture |= m68020;
3930 current_architecture |= archs[i].arch;
3932 /* Permit m68881 specification with all cpus; those that can't work
3933 with a coprocessor could be doing emulation. */
3934 if (current_architecture & m68851)
3936 if (current_architecture & m68040)
3938 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3941 /* What other incompatibilities could we check for? */
3943 /* Toss in some default assumptions about coprocessors. */
3945 && (cpu_of_arch (current_architecture)
3946 /* Can CPU32 have a 68881 coprocessor?? */
3947 & (m68020 | m68030 | cpu32)))
3949 current_architecture |= m68881;
3952 && (cpu_of_arch (current_architecture) & m68020up) != 0
3953 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3955 current_architecture |= m68851;
3957 if (no_68881 && (current_architecture & m68881))
3958 as_bad (_("options for 68881 and no-68881 both given"));
3959 if (no_68851 && (current_architecture & m68851))
3960 as_bad (_("options for 68851 and no-68851 both given"));
3963 /* Work out the magic number. This isn't very general. */
3964 if (current_architecture & m68000)
3965 m68k_aout_machtype = 0;
3966 else if (current_architecture & m68010)
3967 m68k_aout_machtype = 1;
3968 else if (current_architecture & m68020)
3969 m68k_aout_machtype = 2;
3971 m68k_aout_machtype = 2;
3974 /* Note which set of "movec" control registers is available. */
3975 select_control_regs ();
3977 if (cpu_of_arch (current_architecture) < m68020
3978 || arch_coldfire_p (current_architecture))
3979 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3982 /* This is called when a label is defined. */
3985 m68k_frob_label (sym)
3988 struct label_line *n;
3990 n = (struct label_line *) xmalloc (sizeof *n);
3993 as_where (&n->file, &n->line);
3999 /* This is called when a value that is not an instruction is emitted. */
4002 m68k_flush_pending_output ()
4004 current_label = NULL;
4007 /* This is called at the end of the assembly, when the final value of
4008 the label is known. We warn if this is a text symbol aligned at an
4012 m68k_frob_symbol (sym)
4015 if (S_GET_SEGMENT (sym) == reg_section
4016 && (int) S_GET_VALUE (sym) < 0)
4018 S_SET_SEGMENT (sym, absolute_section);
4019 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4021 else if ((S_GET_VALUE (sym) & 1) != 0)
4023 struct label_line *l;
4025 for (l = labels; l != NULL; l = l->next)
4027 if (l->label == sym)
4030 as_warn_where (l->file, l->line,
4031 _("text label `%s' aligned to odd boundary"),
4039 /* This is called if we go in or out of MRI mode because of the .mri
4043 m68k_mri_mode_change (on)
4048 if (! flag_reg_prefix_optional)
4050 flag_reg_prefix_optional = 1;
4051 #ifdef REGISTER_PREFIX
4056 if (! m68k_rel32_from_cmdline)
4061 if (! reg_prefix_optional_seen)
4063 #ifdef REGISTER_PREFIX_OPTIONAL
4064 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4066 flag_reg_prefix_optional = 0;
4068 #ifdef REGISTER_PREFIX
4073 if (! m68k_rel32_from_cmdline)
4078 /* Equal to MAX_PRECISION in atof-ieee.c */
4079 #define MAX_LITTLENUMS 6
4081 /* Turn a string in input_line_pointer into a floating point constant
4082 of type type, and store the appropriate bytes in *litP. The number
4083 of LITTLENUMS emitted is stored in *sizeP . An error message is
4084 returned, or NULL on OK. */
4087 md_atof (type, litP, sizeP)
4093 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4094 LITTLENUM_TYPE *wordP;
4125 return _("Bad call to MD_ATOF()");
4127 t = atof_ieee (input_line_pointer, type, words);
4129 input_line_pointer = t;
4131 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4132 for (wordP = words; prec--;)
4134 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4135 litP += sizeof (LITTLENUM_TYPE);
4141 md_number_to_chars (buf, val, n)
4146 number_to_chars_bigendian (buf, val, n);
4150 md_apply_fix_2 (fixP, val)
4154 addressT upper_limit;
4155 offsetT lower_limit;
4157 /* This is unnecessary but it convinces the native rs6000 compiler
4158 to generate the code we want. */
4159 char *buf = fixP->fx_frag->fr_literal;
4160 buf += fixP->fx_where;
4161 /* end ibm compiler workaround */
4163 if (val & 0x80000000)
4164 val |= ~(addressT)0x7fffffff;
4171 memset (buf, 0, fixP->fx_size);
4172 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4174 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4175 && !S_IS_DEFINED (fixP->fx_addsy)
4176 && !S_IS_WEAK (fixP->fx_addsy))
4177 S_SET_WEAK (fixP->fx_addsy);
4182 #ifdef BFD_ASSEMBLER
4183 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4184 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4188 switch (fixP->fx_size)
4190 /* The cast to offsetT below are necessary to make code correct for
4191 machines where ints are smaller than offsetT */
4195 lower_limit = - (offsetT) 0x80;
4198 *buf++ = (val >> 8);
4200 upper_limit = 0x7fff;
4201 lower_limit = - (offsetT) 0x8000;
4204 *buf++ = (val >> 24);
4205 *buf++ = (val >> 16);
4206 *buf++ = (val >> 8);
4208 upper_limit = 0x7fffffff;
4209 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4212 BAD_CASE (fixP->fx_size);
4215 /* Fix up a negative reloc. */
4216 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4218 fixP->fx_addsy = fixP->fx_subsy;
4219 fixP->fx_subsy = NULL;
4223 /* For non-pc-relative values, it's conceivable we might get something
4224 like "0xff" for a byte field. So extend the upper part of the range
4225 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4226 so that we can do any range checking at all. */
4227 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4228 upper_limit = upper_limit * 2 + 1;
4230 if ((addressT) val > upper_limit
4231 && (val > 0 || val < lower_limit))
4232 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4234 /* A one byte PC-relative reloc means a short branch. We can't use
4235 a short branch with a value of 0 or -1, because those indicate
4236 different opcodes (branches with longer offsets). fixup_segment
4237 in write.c may have clobbered fx_pcrel, so we need to examine the
4240 #ifdef BFD_ASSEMBLER
4241 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4244 && fixP->fx_size == 1
4245 && (fixP->fx_addsy == NULL
4246 || S_IS_DEFINED (fixP->fx_addsy))
4247 && (val == 0 || val == -1))
4248 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4251 #ifdef BFD_ASSEMBLER
4253 md_apply_fix (fixP, valp)
4257 md_apply_fix_2 (fixP, (addressT) *valp);
4261 void md_apply_fix (fixP, val)
4265 md_apply_fix_2 (fixP, (addressT) val);
4269 /* *fragP has been relaxed to its final size, and now needs to have
4270 the bytes inside it modified to conform to the new size There is UGLY
4274 md_convert_frag_1 (fragP)
4275 register fragS *fragP;
4281 /* Address in object code of the displacement. */
4282 register int object_address = fragP->fr_fix + fragP->fr_address;
4284 /* Address in gas core of the place to store the displacement. */
4285 /* This convinces the native rs6000 compiler to generate the code we
4287 register char *buffer_address = fragP->fr_literal;
4288 buffer_address += fragP->fr_fix;
4289 /* end ibm compiler workaround */
4291 /* The displacement of the address, from current location. */
4292 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4293 disp = (disp + fragP->fr_offset) - object_address;
4295 #ifdef BFD_ASSEMBLER
4296 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4299 switch (fragP->fr_subtype)
4301 case TAB (BCC68000, BYTE):
4302 case TAB (ABRANCH, BYTE):
4303 know (issbyte (disp));
4305 as_bad (_("short branch with zero offset: use :w"));
4306 fragP->fr_opcode[1] = disp;
4309 case TAB (DBCC, SHORT):
4310 know (issword (disp));
4313 case TAB (BCC68000, SHORT):
4314 case TAB (ABRANCH, SHORT):
4315 know (issword (disp));
4316 fragP->fr_opcode[1] = 0x00;
4319 case TAB (ABRANCH, LONG):
4320 if (!HAVE_LONG_BRANCH(current_architecture))
4322 if (fragP->fr_opcode[0] == 0x61)
4325 fragP->fr_opcode[0] = 0x4E;
4326 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4340 else if (fragP->fr_opcode[0] == 0x60)
4342 fragP->fr_opcode[0] = 0x4E;
4343 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4344 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4345 fragP->fr_offset, 0, NO_RELOC);
4351 as_bad (_("Long branch offset not supported."));
4356 fragP->fr_opcode[1] = (char) 0xff;
4360 case TAB (BCC68000, LONG):
4361 /* only Bcc 68000 instructions can come here */
4362 /* change bcc into b!cc/jmp absl long */
4363 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4364 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4366 /* JF: these used to be fr_opcode[2,3], but they may be in a
4367 different frag, in which case refering to them is a no-no.
4368 Only fr_opcode[0,1] are guaranteed to work. */
4369 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4370 *buffer_address++ = (char) 0xf9;
4371 fragP->fr_fix += 2; /* account for jmp instruction */
4372 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4373 fragP->fr_offset, 0, NO_RELOC);
4377 case TAB (DBCC, LONG):
4378 /* only DBcc 68000 instructions can come here */
4379 /* change dbcc into dbcc/jmp absl long */
4380 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4381 *buffer_address++ = 0x00; /* branch offset = 4 */
4382 *buffer_address++ = 0x04;
4383 *buffer_address++ = 0x60; /* put in bra pc+6 */
4384 *buffer_address++ = 0x06;
4385 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4386 *buffer_address++ = (char) 0xf9;
4388 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4389 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4390 fragP->fr_offset, 0, NO_RELOC);
4394 case TAB (FBRANCH, SHORT):
4395 know ((fragP->fr_opcode[1] & 0x40) == 0);
4398 case TAB (FBRANCH, LONG):
4399 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4402 case TAB (PCREL, SHORT):
4405 case TAB (PCREL, LONG):
4406 /* The thing to do here is force it to ABSOLUTE LONG, since
4407 PCREL is really trying to shorten an ABSOLUTE address anyway */
4408 /* JF FOO This code has not been tested */
4409 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4411 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4412 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4413 (unsigned) fragP->fr_opcode[0],
4414 (unsigned long) fragP->fr_address);
4415 fragP->fr_opcode[1] &= ~0x3F;
4416 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4420 case TAB (PCLEA, SHORT):
4421 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4422 fragP->fr_offset, 1, NO_RELOC);
4423 fragP->fr_opcode[1] &= ~0x3F;
4424 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4427 case TAB (PCLEA, LONG):
4428 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4429 fragP->fr_offset, 1, NO_RELOC);
4430 fixP->fx_pcrel_adjust = 2;
4431 /* Already set to mode 7.3; this indicates: PC indirect with
4432 suppressed index, 32-bit displacement. */
4433 *buffer_address++ = 0x01;
4434 *buffer_address++ = 0x70;
4439 case TAB (PCINDEX, BYTE):
4441 if (!issbyte (disp))
4443 as_bad (_("displacement doesn't fit in one byte"));
4446 assert (fragP->fr_fix >= 2);
4447 buffer_address[-2] &= ~1;
4448 buffer_address[-1] = disp;
4451 case TAB (PCINDEX, SHORT):
4453 assert (issword (disp));
4454 assert (fragP->fr_fix >= 2);
4455 buffer_address[-2] |= 0x1;
4456 buffer_address[-1] = 0x20;
4457 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4458 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4460 fixP->fx_pcrel_adjust = 2;
4463 case TAB (PCINDEX, LONG):
4465 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4466 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4468 fixP->fx_pcrel_adjust = 2;
4469 assert (fragP->fr_fix >= 2);
4470 buffer_address[-2] |= 0x1;
4471 buffer_address[-1] = 0x30;
4478 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4479 fragP->fr_fix += ext;
4483 #ifndef BFD_ASSEMBLER
4486 md_convert_frag (headers, sec, fragP)
4487 object_headers *headers;
4491 md_convert_frag_1 (fragP);
4497 md_convert_frag (abfd, sec, fragP)
4498 bfd *abfd ATTRIBUTE_UNUSED;
4499 segT sec ATTRIBUTE_UNUSED;
4502 md_convert_frag_1 (fragP);
4506 /* Force truly undefined symbols to their maximum size, and generally set up
4507 the frag list to be relaxed
4510 md_estimate_size_before_relax (fragP, segment)
4511 register fragS *fragP;
4515 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4517 old_fix = fragP->fr_fix;
4519 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4520 switch (fragP->fr_subtype)
4523 case TAB (ABRANCH, SZ_UNDEF):
4525 if ((fragP->fr_symbol != NULL) /* Not absolute */
4526 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4527 && relaxable_symbol (fragP->fr_symbol))
4529 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4532 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4534 /* On 68000, or for absolute value, switch to abs long */
4535 /* FIXME, we should check abs val, pick short or long */
4536 if (fragP->fr_opcode[0] == 0x61)
4538 fragP->fr_opcode[0] = 0x4E;
4539 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4540 fix_new (fragP, fragP->fr_fix, 4,
4541 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4545 else if (fragP->fr_opcode[0] == 0x60)
4547 fragP->fr_opcode[0] = 0x4E;
4548 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4549 fix_new (fragP, fragP->fr_fix, 4,
4550 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4556 as_warn (_("Long branch offset to extern symbol not supported."));
4560 { /* Symbol is still undefined. Make it simple */
4561 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4562 fragP->fr_offset, 1, NO_RELOC);
4564 fragP->fr_opcode[1] = (char) 0xff;
4570 } /* case TAB(ABRANCH,SZ_UNDEF) */
4572 case TAB (FBRANCH, SZ_UNDEF):
4574 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4575 && relaxable_symbol (fragP->fr_symbol))
4578 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4583 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4584 fragP->fr_offset, 1, NO_RELOC);
4586 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4590 } /* TAB(FBRANCH,SZ_UNDEF) */
4592 case TAB (PCREL, SZ_UNDEF):
4594 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4595 && relaxable_symbol (fragP->fr_symbol))
4597 || cpu_of_arch (current_architecture) < m68020
4598 || cpu_of_arch (current_architecture) == mcf5200)
4600 fragP->fr_subtype = TAB (PCREL, SHORT);
4605 fragP->fr_subtype = TAB (PCREL, LONG);
4609 } /* TAB(PCREL,SZ_UNDEF) */
4611 case TAB (BCC68000, SZ_UNDEF):
4613 if ((fragP->fr_symbol != NULL)
4614 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4615 && relaxable_symbol (fragP->fr_symbol))
4617 fragP->fr_subtype = TAB (BCC68000, BYTE);
4620 /* only Bcc 68000 instructions can come here */
4621 /* change bcc into b!cc/jmp absl long */
4622 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4623 if (flag_short_refs)
4625 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4626 /* JF: these were fr_opcode[2,3] */
4627 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4628 buffer_address[1] = (char) 0xf8;
4629 fragP->fr_fix += 2; /* account for jmp instruction */
4630 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4631 fragP->fr_offset, 0, NO_RELOC);
4636 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4637 /* JF: these were fr_opcode[2,3] */
4638 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4639 buffer_address[1] = (char) 0xf9;
4640 fragP->fr_fix += 2; /* account for jmp instruction */
4641 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4642 fragP->fr_offset, 0, NO_RELOC);
4647 } /* case TAB(BCC68000,SZ_UNDEF) */
4649 case TAB (DBCC, SZ_UNDEF):
4651 if (fragP->fr_symbol != NULL
4652 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4653 && relaxable_symbol (fragP->fr_symbol))
4655 fragP->fr_subtype = TAB (DBCC, SHORT);
4659 /* only DBcc 68000 instructions can come here */
4660 /* change dbcc into dbcc/jmp absl long */
4661 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4662 buffer_address[0] = 0x00; /* branch offset = 4 */
4663 buffer_address[1] = 0x04;
4664 buffer_address[2] = 0x60; /* put in bra pc + ... */
4666 if (flag_short_refs)
4668 /* JF: these were fr_opcode[5-7] */
4669 buffer_address[3] = 0x04; /* plus 4 */
4670 buffer_address[4] = 0x4e; /* Put in Jump Word */
4671 buffer_address[5] = (char) 0xf8;
4672 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4673 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4674 fragP->fr_offset, 0, NO_RELOC);
4679 /* JF: these were fr_opcode[5-7] */
4680 buffer_address[3] = 0x06; /* Plus 6 */
4681 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4682 buffer_address[5] = (char) 0xf9;
4683 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4684 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4685 fragP->fr_offset, 0, NO_RELOC);
4691 } /* case TAB(DBCC,SZ_UNDEF) */
4693 case TAB (PCLEA, SZ_UNDEF):
4695 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4696 && relaxable_symbol (fragP->fr_symbol))
4698 || cpu_of_arch (current_architecture) < m68020
4699 || cpu_of_arch (current_architecture) == mcf5200)
4701 fragP->fr_subtype = TAB (PCLEA, SHORT);
4706 fragP->fr_subtype = TAB (PCLEA, LONG);
4710 } /* TAB(PCLEA,SZ_UNDEF) */
4712 case TAB (PCINDEX, SZ_UNDEF):
4713 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4714 && relaxable_symbol (fragP->fr_symbol))
4715 || cpu_of_arch (current_architecture) < m68020
4716 || cpu_of_arch (current_architecture) == mcf5200)
4718 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4722 fragP->fr_subtype = TAB (PCINDEX, LONG);
4731 /* now that SZ_UNDEF are taken care of, check others */
4732 switch (fragP->fr_subtype)
4734 case TAB (BCC68000, BYTE):
4735 case TAB (ABRANCH, BYTE):
4736 /* We can't do a short jump to the next instruction, so in that
4737 case we force word mode. At this point S_GET_VALUE should
4738 return the offset of the symbol within its frag. If the
4739 symbol is at the start of a frag, and it is the next frag
4740 with any data in it (usually this is just the next frag, but
4741 assembler listings may introduce empty frags), we must use
4743 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4748 stop = symbol_get_frag (fragP->fr_symbol);
4749 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4750 if (l->fr_fix + l->fr_var != 0)
4754 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4762 return fragP->fr_var + fragP->fr_fix - old_fix;
4765 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4766 /* the bit-field entries in the relocation_info struct plays hell
4767 with the byte-order problems of cross-assembly. So as a hack,
4768 I added this mach. dependent ri twiddler. Ugly, but it gets
4770 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4771 are symbolnum, most sig. byte first. Last byte is broken up with
4772 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4773 nibble as nuthin. (on Sun 3 at least) */
4774 /* Translate the internal relocation information into target-specific
4778 md_ri_to_chars (the_bytes, ri)
4780 struct reloc_info_generic *ri;
4783 md_number_to_chars (the_bytes, ri->r_address, 4);
4784 /* now the fun stuff */
4785 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4786 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4787 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4788 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4789 ((ri->r_extern << 4) & 0x10));
4792 #endif /* comment */
4794 #ifndef BFD_ASSEMBLER
4796 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4799 relax_addressT segment_address_in_file;
4802 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4803 * Out: GNU LD relocation length code: 0, 1, or 2.
4806 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4809 know (fixP->fx_addsy != NULL);
4811 md_number_to_chars (where,
4812 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4815 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4816 ? S_GET_TYPE (fixP->fx_addsy)
4817 : fixP->fx_addsy->sy_number);
4819 where[4] = (r_symbolnum >> 16) & 0x0ff;
4820 where[5] = (r_symbolnum >> 8) & 0x0ff;
4821 where[6] = r_symbolnum & 0x0ff;
4822 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4823 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4827 #endif /* OBJ_AOUT or OBJ_BOUT */
4829 #ifndef WORKING_DOT_WORD
4830 CONST int md_short_jump_size = 4;
4831 CONST int md_long_jump_size = 6;
4834 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4836 addressT from_addr, to_addr;
4837 fragS *frag ATTRIBUTE_UNUSED;
4838 symbolS *to_symbol ATTRIBUTE_UNUSED;
4842 offset = to_addr - (from_addr + 2);
4844 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4845 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4849 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4851 addressT from_addr, to_addr;
4857 if (!HAVE_LONG_BRANCH(current_architecture))
4859 offset = to_addr - S_GET_VALUE (to_symbol);
4860 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4861 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4862 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4867 offset = to_addr - (from_addr + 2);
4868 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4869 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4875 /* Different values of OK tell what its OK to return. Things that
4876 aren't OK are an error (what a shock, no?)
4879 10: Absolute 1:8 only
4880 20: Absolute 0:7 only
4881 30: absolute 0:15 only
4882 40: Absolute 0:31 only
4883 50: absolute 0:127 only
4884 55: absolute -64:63 only
4885 60: absolute -128:127 only
4886 70: absolute 0:4095 only
4893 struct m68k_exp *exp;
4896 if (exp->exp.X_op == O_absent)
4898 /* Do the same thing the VAX asm does */
4899 op (exp) = O_constant;
4905 as_warn (_("expression out of range: defaulting to 1"));
4909 else if (exp->exp.X_op == O_constant)
4914 if (offs (exp) < 1 || offs (exp) > 8)
4916 as_warn (_("expression out of range: defaulting to 1"));
4921 if (offs (exp) < 0 || offs (exp) > 7)
4925 if (offs (exp) < 0 || offs (exp) > 15)
4929 if (offs (exp) < 0 || offs (exp) > 32)
4933 if (offs (exp) < 0 || offs (exp) > 127)
4937 if (offs (exp) < -64 || offs (exp) > 63)
4941 if (offs (exp) < -128 || offs (exp) > 127)
4945 if (offs (exp) < 0 || offs (exp) > 4095)
4948 as_warn (_("expression out of range: defaulting to 0"));
4956 else if (exp->exp.X_op == O_big)
4958 if (offs (exp) <= 0 /* flonum */
4959 && (ok == 80 /* no bignums */
4960 || (ok > 10 /* small-int ranges including 0 ok */
4961 /* If we have a flonum zero, a zero integer should
4962 do as well (e.g., in moveq). */
4963 && generic_floating_point_number.exponent == 0
4964 && generic_floating_point_number.low[0] == 0)))
4966 /* HACK! Turn it into a long */
4967 LITTLENUM_TYPE words[6];
4969 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4970 op (exp) = O_constant;
4973 offs (exp) = words[1] | (words[0] << 16);
4977 op (exp) = O_constant;
4980 offs (exp) = (ok == 10) ? 1 : 0;
4981 as_warn (_("Can't deal with expression; defaulting to %ld"),
4987 if (ok >= 10 && ok <= 70)
4989 op (exp) = O_constant;
4992 offs (exp) = (ok == 10) ? 1 : 0;
4993 as_warn (_("Can't deal with expression; defaulting to %ld"),
4998 if (exp->size != SIZE_UNSPEC)
5006 if (!isbyte (offs (exp)))
5007 as_warn (_("expression doesn't fit in BYTE"));
5010 if (!isword (offs (exp)))
5011 as_warn (_("expression doesn't fit in WORD"));
5019 /* These are the back-ends for the various machine dependent pseudo-ops. */
5023 int ignore ATTRIBUTE_UNUSED;
5025 subseg_set (data_section, 1);
5026 demand_empty_rest_of_line ();
5031 int ignore ATTRIBUTE_UNUSED;
5033 subseg_set (data_section, 2);
5034 demand_empty_rest_of_line ();
5039 int ignore ATTRIBUTE_UNUSED;
5041 /* We don't support putting frags in the BSS segment, we fake it
5042 by marking in_bss, then looking at s_skip for clues. */
5044 subseg_set (bss_section, 0);
5045 demand_empty_rest_of_line ();
5050 int ignore ATTRIBUTE_UNUSED;
5053 register long temp_fill;
5055 temp = 1; /* JF should be 2? */
5056 temp_fill = get_absolute_expression ();
5057 if (!need_pass_2) /* Never make frag if expect extra pass. */
5058 frag_align (temp, (int) temp_fill, 0);
5059 demand_empty_rest_of_line ();
5060 record_alignment (now_seg, temp);
5065 int ignore ATTRIBUTE_UNUSED;
5067 demand_empty_rest_of_line ();
5070 /* Pseudo-ops handled for MRI compatibility. */
5072 /* This function returns non-zero if the argument is a conditional
5073 pseudo-op. This is called when checking whether a pending
5074 alignment is needed. */
5077 m68k_conditional_pseudoop (pop)
5080 return (pop->poc_handler == s_mri_if
5081 || pop->poc_handler == s_mri_else);
5084 /* Handle an MRI style chip specification. */
5093 s = input_line_pointer;
5094 /* We can't use get_symbol_end since the processor names are not proper
5096 while (is_part_of_name (c = *input_line_pointer++))
5098 *--input_line_pointer = 0;
5099 for (i = 0; i < n_archs; i++)
5100 if (strcasecmp (s, archs[i].name) == 0)
5104 as_bad (_("%s: unrecognized processor name"), s);
5105 *input_line_pointer = c;
5106 ignore_rest_of_line ();
5109 *input_line_pointer = c;
5111 if (*input_line_pointer == '/')
5112 current_architecture = 0;
5114 current_architecture &= m68881 | m68851;
5115 current_architecture |= archs[i].arch;
5117 while (*input_line_pointer == '/')
5119 ++input_line_pointer;
5120 s = input_line_pointer;
5121 /* We can't use get_symbol_end since the processor names are not
5123 while (is_part_of_name (c = *input_line_pointer++))
5125 *--input_line_pointer = 0;
5126 if (strcmp (s, "68881") == 0)
5127 current_architecture |= m68881;
5128 else if (strcmp (s, "68851") == 0)
5129 current_architecture |= m68851;
5130 *input_line_pointer = c;
5133 /* Update info about available control registers. */
5134 select_control_regs ();
5137 /* The MRI CHIP pseudo-op. */
5141 int ignore ATTRIBUTE_UNUSED;
5147 stop = mri_comment_field (&stopc);
5150 mri_comment_end (stop, stopc);
5151 demand_empty_rest_of_line ();
5154 /* The MRI FOPT pseudo-op. */
5158 int ignore ATTRIBUTE_UNUSED;
5162 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5166 input_line_pointer += 3;
5167 temp = get_absolute_expression ();
5168 if (temp < 0 || temp > 7)
5169 as_bad (_("bad coprocessor id"));
5171 m68k_float_copnum = COP0 + temp;
5175 as_bad (_("unrecognized fopt option"));
5176 ignore_rest_of_line ();
5180 demand_empty_rest_of_line ();
5183 /* The structure used to handle the MRI OPT pseudo-op. */
5187 /* The name of the option. */
5190 /* If this is not NULL, just call this function. The first argument
5191 is the ARG field of this structure, the second argument is
5192 whether the option was negated. */
5193 void (*pfn) PARAMS ((int arg, int on));
5195 /* If this is not NULL, and the PFN field is NULL, set the variable
5196 this points to. Set it to the ARG field if the option was not
5197 negated, and the NOTARG field otherwise. */
5200 /* The value to pass to PFN or to assign to *PVAR. */
5203 /* The value to assign to *PVAR if the option is negated. If PFN is
5204 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5205 the option may not be negated. */
5209 /* The table used to handle the MRI OPT pseudo-op. */
5211 static void skip_to_comma PARAMS ((int, int));
5212 static void opt_nest PARAMS ((int, int));
5213 static void opt_chip PARAMS ((int, int));
5214 static void opt_list PARAMS ((int, int));
5215 static void opt_list_symbols PARAMS ((int, int));
5217 static const struct opt_action opt_table[] =
5219 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5221 /* We do relaxing, so there is little use for these options. */
5222 { "b", 0, 0, 0, 0 },
5223 { "brs", 0, 0, 0, 0 },
5224 { "brb", 0, 0, 0, 0 },
5225 { "brl", 0, 0, 0, 0 },
5226 { "brw", 0, 0, 0, 0 },
5228 { "c", 0, 0, 0, 0 },
5229 { "cex", 0, 0, 0, 0 },
5230 { "case", 0, &symbols_case_sensitive, 1, 0 },
5231 { "cl", 0, 0, 0, 0 },
5232 { "cre", 0, 0, 0, 0 },
5233 { "d", 0, &flag_keep_locals, 1, 0 },
5234 { "e", 0, 0, 0, 0 },
5235 { "f", 0, &flag_short_refs, 1, 0 },
5236 { "frs", 0, &flag_short_refs, 1, 0 },
5237 { "frl", 0, &flag_short_refs, 0, 1 },
5238 { "g", 0, 0, 0, 0 },
5239 { "i", 0, 0, 0, 0 },
5240 { "m", 0, 0, 0, 0 },
5241 { "mex", 0, 0, 0, 0 },
5242 { "mc", 0, 0, 0, 0 },
5243 { "md", 0, 0, 0, 0 },
5244 { "nest", opt_nest, 0, 0, 0 },
5245 { "next", skip_to_comma, 0, 0, 0 },
5246 { "o", 0, 0, 0, 0 },
5247 { "old", 0, 0, 0, 0 },
5248 { "op", skip_to_comma, 0, 0, 0 },
5249 { "pco", 0, 0, 0, 0 },
5250 { "p", opt_chip, 0, 0, 0 },
5251 { "pcr", 0, 0, 0, 0 },
5252 { "pcs", 0, 0, 0, 0 },
5253 { "r", 0, 0, 0, 0 },
5254 { "quick", 0, &m68k_quick, 1, 0 },
5255 { "rel32", 0, &m68k_rel32, 1, 0 },
5256 { "s", opt_list, 0, 0, 0 },
5257 { "t", opt_list_symbols, 0, 0, 0 },
5258 { "w", 0, &flag_no_warnings, 0, 1 },
5262 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5264 /* The MRI OPT pseudo-op. */
5268 int ignore ATTRIBUTE_UNUSED;
5276 const struct opt_action *o;
5281 if (*input_line_pointer == '-')
5283 ++input_line_pointer;
5286 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5288 input_line_pointer += 2;
5292 s = input_line_pointer;
5293 c = get_symbol_end ();
5295 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5297 if (strcasecmp (s, o->name) == 0)
5301 /* Restore input_line_pointer now in case the option
5303 *input_line_pointer = c;
5304 (*o->pfn) (o->arg, t);
5306 else if (o->pvar != NULL)
5308 if (! t && o->arg == o->notarg)
5309 as_bad (_("option `%s' may not be negated"), s);
5310 *input_line_pointer = c;
5311 *o->pvar = t ? o->arg : o->notarg;
5314 *input_line_pointer = c;
5320 as_bad (_("option `%s' not recognized"), s);
5321 *input_line_pointer = c;
5324 while (*input_line_pointer++ == ',');
5326 /* Move back to terminating character. */
5327 --input_line_pointer;
5328 demand_empty_rest_of_line ();
5331 /* Skip ahead to a comma. This is used for OPT options which we do
5332 not suppor tand which take arguments. */
5335 skip_to_comma (arg, on)
5336 int arg ATTRIBUTE_UNUSED;
5337 int on ATTRIBUTE_UNUSED;
5339 while (*input_line_pointer != ','
5340 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5341 ++input_line_pointer;
5344 /* Handle the OPT NEST=depth option. */
5348 int arg ATTRIBUTE_UNUSED;
5349 int on ATTRIBUTE_UNUSED;
5351 if (*input_line_pointer != '=')
5353 as_bad (_("bad format of OPT NEST=depth"));
5357 ++input_line_pointer;
5358 max_macro_nest = get_absolute_expression ();
5361 /* Handle the OPT P=chip option. */
5365 int arg ATTRIBUTE_UNUSED;
5366 int on ATTRIBUTE_UNUSED;
5368 if (*input_line_pointer != '=')
5370 /* This is just OPT P, which we do not support. */
5374 ++input_line_pointer;
5378 /* Handle the OPT S option. */
5382 int arg ATTRIBUTE_UNUSED;
5388 /* Handle the OPT T option. */
5391 opt_list_symbols (arg, on)
5392 int arg ATTRIBUTE_UNUSED;
5396 listing |= LISTING_SYMBOLS;
5398 listing &=~ LISTING_SYMBOLS;
5401 /* Handle the MRI REG pseudo-op. */
5405 int ignore ATTRIBUTE_UNUSED;
5414 if (line_label == NULL)
5416 as_bad (_("missing label"));
5417 ignore_rest_of_line ();
5422 stop = mri_comment_field (&stopc);
5426 s = input_line_pointer;
5427 while (isalnum ((unsigned char) *input_line_pointer)
5428 #ifdef REGISTER_PREFIX
5429 || *input_line_pointer == REGISTER_PREFIX
5431 || *input_line_pointer == '/'
5432 || *input_line_pointer == '-')
5433 ++input_line_pointer;
5434 c = *input_line_pointer;
5435 *input_line_pointer = '\0';
5437 if (m68k_ip_op (s, &rop) != 0)
5439 if (rop.error == NULL)
5440 as_bad (_("bad register list"));
5442 as_bad (_("bad register list: %s"), rop.error);
5443 *input_line_pointer = c;
5444 ignore_rest_of_line ();
5448 *input_line_pointer = c;
5450 if (rop.mode == REGLST)
5452 else if (rop.mode == DREG)
5453 mask = 1 << (rop.reg - DATA0);
5454 else if (rop.mode == AREG)
5455 mask = 1 << (rop.reg - ADDR0 + 8);
5456 else if (rop.mode == FPREG)
5457 mask = 1 << (rop.reg - FP0 + 16);
5458 else if (rop.mode == CONTROL
5461 else if (rop.mode == CONTROL
5464 else if (rop.mode == CONTROL
5469 as_bad (_("bad register list"));
5470 ignore_rest_of_line ();
5474 S_SET_SEGMENT (line_label, reg_section);
5475 S_SET_VALUE (line_label, ~mask);
5476 symbol_set_frag (line_label, &zero_address_frag);
5479 mri_comment_end (stop, stopc);
5481 demand_empty_rest_of_line ();
5484 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5488 struct save_opts *next;
5490 int symbols_case_sensitive;
5498 /* FIXME: We don't save OPT S. */
5501 /* This variable holds the stack of saved options. */
5503 static struct save_opts *save_stack;
5505 /* The MRI SAVE pseudo-op. */
5509 int ignore ATTRIBUTE_UNUSED;
5511 struct save_opts *s;
5513 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5514 s->abspcadd = m68k_abspcadd;
5515 s->symbols_case_sensitive = symbols_case_sensitive;
5516 s->keep_locals = flag_keep_locals;
5517 s->short_refs = flag_short_refs;
5518 s->architecture = current_architecture;
5519 s->quick = m68k_quick;
5520 s->rel32 = m68k_rel32;
5521 s->listing = listing;
5522 s->no_warnings = flag_no_warnings;
5524 s->next = save_stack;
5527 demand_empty_rest_of_line ();
5530 /* The MRI RESTORE pseudo-op. */
5534 int ignore ATTRIBUTE_UNUSED;
5536 struct save_opts *s;
5538 if (save_stack == NULL)
5540 as_bad (_("restore without save"));
5541 ignore_rest_of_line ();
5546 save_stack = s->next;
5548 m68k_abspcadd = s->abspcadd;
5549 symbols_case_sensitive = s->symbols_case_sensitive;
5550 flag_keep_locals = s->keep_locals;
5551 flag_short_refs = s->short_refs;
5552 current_architecture = s->architecture;
5553 m68k_quick = s->quick;
5554 m68k_rel32 = s->rel32;
5555 listing = s->listing;
5556 flag_no_warnings = s->no_warnings;
5560 demand_empty_rest_of_line ();
5563 /* Types of MRI structured control directives. */
5565 enum mri_control_type
5573 /* This structure is used to stack the MRI structured control
5576 struct mri_control_info
5578 /* The directive within which this one is enclosed. */
5579 struct mri_control_info *outer;
5581 /* The type of directive. */
5582 enum mri_control_type type;
5584 /* Whether an ELSE has been in an IF. */
5587 /* The add or sub statement at the end of a FOR. */
5590 /* The label of the top of a FOR or REPEAT loop. */
5593 /* The label to jump to for the next iteration, or the else
5594 expression of a conditional. */
5597 /* The label to jump to to break out of the loop, or the label past
5598 the end of a conditional. */
5602 /* The stack of MRI structured control directives. */
5604 static struct mri_control_info *mri_control_stack;
5606 /* The current MRI structured control directive index number, used to
5607 generate label names. */
5609 static int mri_control_index;
5611 /* Some function prototypes. */
5613 static void mri_assemble PARAMS ((char *));
5614 static char *mri_control_label PARAMS ((void));
5615 static struct mri_control_info *push_mri_control
5616 PARAMS ((enum mri_control_type));
5617 static void pop_mri_control PARAMS ((void));
5618 static int parse_mri_condition PARAMS ((int *));
5619 static int parse_mri_control_operand
5620 PARAMS ((int *, char **, char **, char **, char **));
5621 static int swap_mri_condition PARAMS ((int));
5622 static int reverse_mri_condition PARAMS ((int));
5623 static void build_mri_control_operand
5624 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5625 const char *, int));
5626 static void parse_mri_control_expression
5627 PARAMS ((char *, int, const char *, const char *, int));
5629 /* Assemble an instruction for an MRI structured control directive. */
5637 /* md_assemble expects the opcode to be in lower case. */
5638 for (s = str; *s != ' ' && *s != '\0'; s++)
5640 if (isupper ((unsigned char) *s))
5641 *s = tolower ((unsigned char) *s);
5647 /* Generate a new MRI label structured control directive label name. */
5650 mri_control_label ()
5654 n = (char *) xmalloc (20);
5655 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5656 ++mri_control_index;
5660 /* Create a new MRI structured control directive. */
5662 static struct mri_control_info *
5663 push_mri_control (type)
5664 enum mri_control_type type;
5666 struct mri_control_info *n;
5668 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5672 if (type == mri_if || type == mri_while)
5675 n->top = mri_control_label ();
5676 n->next = mri_control_label ();
5677 n->bottom = mri_control_label ();
5679 n->outer = mri_control_stack;
5680 mri_control_stack = n;
5685 /* Pop off the stack of MRI structured control directives. */
5690 struct mri_control_info *n;
5692 n = mri_control_stack;
5693 mri_control_stack = n->outer;
5701 /* Recognize a condition code in an MRI structured control expression. */
5704 parse_mri_condition (pcc)
5709 know (*input_line_pointer == '<');
5711 ++input_line_pointer;
5712 c1 = *input_line_pointer++;
5713 c2 = *input_line_pointer++;
5715 if (*input_line_pointer != '>')
5717 as_bad (_("syntax error in structured control directive"));
5721 ++input_line_pointer;
5729 *pcc = (c1 << 8) | c2;
5734 /* Parse a single operand in an MRI structured control expression. */
5737 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5754 if (*input_line_pointer == '<')
5756 /* It's just a condition code. */
5757 return parse_mri_condition (pcc);
5760 /* Look ahead for the condition code. */
5761 for (s = input_line_pointer; *s != '\0'; ++s)
5763 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5768 as_bad (_("missing condition code in structured control directive"));
5772 *leftstart = input_line_pointer;
5774 if (*leftstop > *leftstart
5775 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5778 input_line_pointer = s;
5779 if (! parse_mri_condition (pcc))
5782 /* Look ahead for AND or OR or end of line. */
5783 for (s = input_line_pointer; *s != '\0'; ++s)
5785 if ((strncasecmp (s, "AND", 3) == 0
5786 && (s[3] == '.' || ! is_part_of_name (s[3])))
5787 || (strncasecmp (s, "OR", 2) == 0
5788 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5792 *rightstart = input_line_pointer;
5794 if (*rightstop > *rightstart
5795 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5798 input_line_pointer = s;
5803 #define MCC(b1, b2) (((b1) << 8) | (b2))
5805 /* Swap the sense of a condition. This changes the condition so that
5806 it generates the same result when the operands are swapped. */
5809 swap_mri_condition (cc)
5814 case MCC ('h', 'i'): return MCC ('c', 's');
5815 case MCC ('l', 's'): return MCC ('c', 'c');
5816 case MCC ('c', 'c'): return MCC ('l', 's');
5817 case MCC ('c', 's'): return MCC ('h', 'i');
5818 case MCC ('p', 'l'): return MCC ('m', 'i');
5819 case MCC ('m', 'i'): return MCC ('p', 'l');
5820 case MCC ('g', 'e'): return MCC ('l', 'e');
5821 case MCC ('l', 't'): return MCC ('g', 't');
5822 case MCC ('g', 't'): return MCC ('l', 't');
5823 case MCC ('l', 'e'): return MCC ('g', 'e');
5828 /* Reverse the sense of a condition. */
5831 reverse_mri_condition (cc)
5836 case MCC ('h', 'i'): return MCC ('l', 's');
5837 case MCC ('l', 's'): return MCC ('h', 'i');
5838 case MCC ('c', 'c'): return MCC ('c', 's');
5839 case MCC ('c', 's'): return MCC ('c', 'c');
5840 case MCC ('n', 'e'): return MCC ('e', 'q');
5841 case MCC ('e', 'q'): return MCC ('n', 'e');
5842 case MCC ('v', 'c'): return MCC ('v', 's');
5843 case MCC ('v', 's'): return MCC ('v', 'c');
5844 case MCC ('p', 'l'): return MCC ('m', 'i');
5845 case MCC ('m', 'i'): return MCC ('p', 'l');
5846 case MCC ('g', 'e'): return MCC ('l', 't');
5847 case MCC ('l', 't'): return MCC ('g', 'e');
5848 case MCC ('g', 't'): return MCC ('l', 'e');
5849 case MCC ('l', 'e'): return MCC ('g', 't');
5854 /* Build an MRI structured control expression. This generates test
5855 and branch instructions. It goes to TRUELAB if the condition is
5856 true, and to FALSELAB if the condition is false. Exactly one of
5857 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5858 is the size qualifier for the expression. EXTENT is the size to
5859 use for the branch. */
5862 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5863 rightstop, truelab, falselab, extent)
5870 const char *truelab;
5871 const char *falselab;
5877 if (leftstart != NULL)
5879 struct m68k_op leftop, rightop;
5882 /* Swap the compare operands, if necessary, to produce a legal
5883 m68k compare instruction. Comparing a register operand with
5884 a non-register operand requires the register to be on the
5885 right (cmp, cmpa). Comparing an immediate value with
5886 anything requires the immediate value to be on the left
5891 (void) m68k_ip_op (leftstart, &leftop);
5896 (void) m68k_ip_op (rightstart, &rightop);
5899 if (rightop.mode == IMMED
5900 || ((leftop.mode == DREG || leftop.mode == AREG)
5901 && (rightop.mode != DREG && rightop.mode != AREG)))
5905 cc = swap_mri_condition (cc);
5907 leftstart = rightstart;
5910 leftstop = rightstop;
5915 if (truelab == NULL)
5917 cc = reverse_mri_condition (cc);
5921 if (leftstart != NULL)
5923 buf = (char *) xmalloc (20
5924 + (leftstop - leftstart)
5925 + (rightstop - rightstart));
5933 memcpy (s, leftstart, leftstop - leftstart);
5934 s += leftstop - leftstart;
5936 memcpy (s, rightstart, rightstop - rightstart);
5937 s += rightstop - rightstart;
5943 buf = (char *) xmalloc (20 + strlen (truelab));
5951 strcpy (s, truelab);
5956 /* Parse an MRI structured control expression. This generates test
5957 and branch instructions. STOP is where the expression ends. It
5958 goes to TRUELAB if the condition is true, and to FALSELAB if the
5959 condition is false. Exactly one of TRUELAB and FALSELAB will be
5960 NULL, meaning to fall through. QUAL is the size qualifier for the
5961 expression. EXTENT is the size to use for the branch. */
5964 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5967 const char *truelab;
5968 const char *falselab;
5981 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5982 &rightstart, &rightstop))
5988 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5992 if (falselab != NULL)
5995 flab = mri_control_label ();
5997 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5998 rightstop, (const char *) NULL, flab, extent);
6000 input_line_pointer += 3;
6001 if (*input_line_pointer != '.'
6002 || input_line_pointer[1] == '\0')
6006 qual = input_line_pointer[1];
6007 input_line_pointer += 2;
6010 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6011 &rightstart, &rightstop))
6017 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6018 rightstop, truelab, falselab, extent);
6020 if (falselab == NULL)
6023 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6027 if (truelab != NULL)
6030 tlab = mri_control_label ();
6032 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6033 rightstop, tlab, (const char *) NULL, extent);
6035 input_line_pointer += 2;
6036 if (*input_line_pointer != '.'
6037 || input_line_pointer[1] == '\0')
6041 qual = input_line_pointer[1];
6042 input_line_pointer += 2;
6045 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6046 &rightstart, &rightstop))
6052 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6053 rightstop, truelab, falselab, extent);
6055 if (truelab == NULL)
6060 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6061 rightstop, truelab, falselab, extent);
6065 if (input_line_pointer != stop)
6066 as_bad (_("syntax error in structured control directive"));
6069 /* Handle the MRI IF pseudo-op. This may be a structured control
6070 directive, or it may be a regular assembler conditional, depending
6079 struct mri_control_info *n;
6081 /* A structured control directive must end with THEN with an
6082 optional qualifier. */
6083 s = input_line_pointer;
6084 while (! is_end_of_line[(unsigned char) *s]
6085 && (! flag_mri || *s != '*'))
6088 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6091 if (s - input_line_pointer > 1
6095 if (s - input_line_pointer < 3
6096 || strncasecmp (s - 3, "THEN", 4) != 0)
6100 as_bad (_("missing then"));
6101 ignore_rest_of_line ();
6105 /* It's a conditional. */
6110 /* Since this might be a conditional if, this pseudo-op will be
6111 called even if we are supported to be ignoring input. Double
6112 check now. Clobber *input_line_pointer so that ignore_input
6113 thinks that this is not a special pseudo-op. */
6114 c = *input_line_pointer;
6115 *input_line_pointer = 0;
6116 if (ignore_input ())
6118 *input_line_pointer = c;
6119 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6120 ++input_line_pointer;
6121 demand_empty_rest_of_line ();
6124 *input_line_pointer = c;
6126 n = push_mri_control (mri_if);
6128 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6129 n->next, s[1] == '.' ? s[2] : '\0');
6132 input_line_pointer = s + 3;
6134 input_line_pointer = s + 1;
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6142 demand_empty_rest_of_line ();
6145 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6146 structured IF, associate the ELSE with the IF. Otherwise, assume
6147 it is a conditional else. */
6158 && (mri_control_stack == NULL
6159 || mri_control_stack->type != mri_if
6160 || mri_control_stack->else_seen))
6166 c = *input_line_pointer;
6167 *input_line_pointer = 0;
6168 if (ignore_input ())
6170 *input_line_pointer = c;
6171 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6172 ++input_line_pointer;
6173 demand_empty_rest_of_line ();
6176 *input_line_pointer = c;
6178 if (mri_control_stack == NULL
6179 || mri_control_stack->type != mri_if
6180 || mri_control_stack->else_seen)
6182 as_bad (_("else without matching if"));
6183 ignore_rest_of_line ();
6187 mri_control_stack->else_seen = 1;
6189 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6192 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6196 colon (mri_control_stack->next);
6200 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6201 ++input_line_pointer;
6204 demand_empty_rest_of_line ();
6207 /* Handle the MRI ENDI pseudo-op. */
6211 int ignore ATTRIBUTE_UNUSED;
6213 if (mri_control_stack == NULL
6214 || mri_control_stack->type != mri_if)
6216 as_bad (_("endi without matching if"));
6217 ignore_rest_of_line ();
6221 /* ignore_input will not return true for ENDI, so we don't need to
6222 worry about checking it again here. */
6224 if (! mri_control_stack->else_seen)
6225 colon (mri_control_stack->next);
6226 colon (mri_control_stack->bottom);
6232 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6233 ++input_line_pointer;
6236 demand_empty_rest_of_line ();
6239 /* Handle the MRI BREAK pseudo-op. */
6242 s_mri_break (extent)
6245 struct mri_control_info *n;
6249 n = mri_control_stack;
6251 && n->type != mri_for
6252 && n->type != mri_repeat
6253 && n->type != mri_while)
6257 as_bad (_("break outside of structured loop"));
6258 ignore_rest_of_line ();
6262 buf = (char *) xmalloc (20 + strlen (n->bottom));
6265 sprintf (buf, "bra%s %s", ex, n->bottom);
6271 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6272 ++input_line_pointer;
6275 demand_empty_rest_of_line ();
6278 /* Handle the MRI NEXT pseudo-op. */
6284 struct mri_control_info *n;
6288 n = mri_control_stack;
6290 && n->type != mri_for
6291 && n->type != mri_repeat
6292 && n->type != mri_while)
6296 as_bad (_("next outside of structured loop"));
6297 ignore_rest_of_line ();
6301 buf = (char *) xmalloc (20 + strlen (n->next));
6304 sprintf (buf, "bra%s %s", ex, n->next);
6310 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6311 ++input_line_pointer;
6314 demand_empty_rest_of_line ();
6317 /* Handle the MRI FOR pseudo-op. */
6323 const char *varstart, *varstop;
6324 const char *initstart, *initstop;
6325 const char *endstart, *endstop;
6326 const char *bystart, *bystop;
6330 struct mri_control_info *n;
6336 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6340 varstart = input_line_pointer;
6342 /* Look for the '='. */
6343 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6344 && *input_line_pointer != '=')
6345 ++input_line_pointer;
6346 if (*input_line_pointer != '=')
6348 as_bad (_("missing ="));
6349 ignore_rest_of_line ();
6353 varstop = input_line_pointer;
6354 if (varstop > varstart
6355 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6358 ++input_line_pointer;
6360 initstart = input_line_pointer;
6362 /* Look for TO or DOWNTO. */
6365 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6367 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6368 && ! is_part_of_name (input_line_pointer[2]))
6370 initstop = input_line_pointer;
6371 input_line_pointer += 2;
6374 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6375 && ! is_part_of_name (input_line_pointer[6]))
6377 initstop = input_line_pointer;
6379 input_line_pointer += 6;
6382 ++input_line_pointer;
6384 if (initstop == NULL)
6386 as_bad (_("missing to or downto"));
6387 ignore_rest_of_line ();
6390 if (initstop > initstart
6391 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6395 endstart = input_line_pointer;
6397 /* Look for BY or DO. */
6400 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6402 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6403 && ! is_part_of_name (input_line_pointer[2]))
6405 endstop = input_line_pointer;
6407 input_line_pointer += 2;
6410 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6411 && (input_line_pointer[2] == '.'
6412 || ! is_part_of_name (input_line_pointer[2])))
6414 endstop = input_line_pointer;
6415 input_line_pointer += 2;
6418 ++input_line_pointer;
6420 if (endstop == NULL)
6422 as_bad (_("missing do"));
6423 ignore_rest_of_line ();
6426 if (endstop > endstart
6427 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6433 bystop = bystart + 2;
6438 bystart = input_line_pointer;
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6444 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6445 && (input_line_pointer[2] == '.'
6446 || ! is_part_of_name (input_line_pointer[2])))
6448 bystop = input_line_pointer;
6449 input_line_pointer += 2;
6452 ++input_line_pointer;
6456 as_bad (_("missing do"));
6457 ignore_rest_of_line ();
6460 if (bystop > bystart
6461 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6465 if (*input_line_pointer != '.')
6469 extent = input_line_pointer[1];
6470 input_line_pointer += 2;
6473 /* We have fully parsed the FOR operands. Now build the loop. */
6475 n = push_mri_control (mri_for);
6477 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6488 memcpy (s, initstart, initstop - initstart);
6489 s += initstop - initstart;
6491 memcpy (s, varstart, varstop - varstart);
6492 s += varstop - varstart;
6506 memcpy (s, endstart, endstop - endstart);
6507 s += endstop - endstart;
6509 memcpy (s, varstart, varstop - varstart);
6510 s += varstop - varstart;
6518 sprintf (buf, "blt%s %s", ex, n->bottom);
6520 sprintf (buf, "bgt%s %s", ex, n->bottom);
6523 /* Put together the add or sub instruction used by ENDF. */
6533 memcpy (s, bystart, bystop - bystart);
6534 s += bystop - bystart;
6536 memcpy (s, varstart, varstop - varstart);
6537 s += varstop - varstart;
6543 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6544 ++input_line_pointer;
6547 demand_empty_rest_of_line ();
6550 /* Handle the MRI ENDF pseudo-op. */
6554 int ignore ATTRIBUTE_UNUSED;
6556 if (mri_control_stack == NULL
6557 || mri_control_stack->type != mri_for)
6559 as_bad (_("endf without for"));
6560 ignore_rest_of_line ();
6564 colon (mri_control_stack->next);
6566 mri_assemble (mri_control_stack->incr);
6568 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6569 mri_assemble (mri_control_stack->incr);
6571 free (mri_control_stack->incr);
6573 colon (mri_control_stack->bottom);
6579 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6580 ++input_line_pointer;
6583 demand_empty_rest_of_line ();
6586 /* Handle the MRI REPEAT pseudo-op. */
6589 s_mri_repeat (ignore)
6590 int ignore ATTRIBUTE_UNUSED;
6592 struct mri_control_info *n;
6594 n = push_mri_control (mri_repeat);
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 ++input_line_pointer;
6601 demand_empty_rest_of_line ();
6604 /* Handle the MRI UNTIL pseudo-op. */
6612 if (mri_control_stack == NULL
6613 || mri_control_stack->type != mri_repeat)
6615 as_bad (_("until without repeat"));
6616 ignore_rest_of_line ();
6620 colon (mri_control_stack->next);
6622 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6625 parse_mri_control_expression (s, qual, (const char *) NULL,
6626 mri_control_stack->top, '\0');
6628 colon (mri_control_stack->bottom);
6630 input_line_pointer = s;
6636 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6637 ++input_line_pointer;
6640 demand_empty_rest_of_line ();
6643 /* Handle the MRI WHILE pseudo-op. */
6651 struct mri_control_info *n;
6653 s = input_line_pointer;
6654 while (! is_end_of_line[(unsigned char) *s]
6655 && (! flag_mri || *s != '*'))
6658 while (*s == ' ' || *s == '\t')
6660 if (s - input_line_pointer > 1
6663 if (s - input_line_pointer < 2
6664 || strncasecmp (s - 1, "DO", 2) != 0)
6666 as_bad (_("missing do"));
6667 ignore_rest_of_line ();
6671 n = push_mri_control (mri_while);
6675 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6676 s[1] == '.' ? s[2] : '\0');
6678 input_line_pointer = s + 1;
6679 if (*input_line_pointer == '.')
6680 input_line_pointer += 2;
6684 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6685 ++input_line_pointer;
6688 demand_empty_rest_of_line ();
6691 /* Handle the MRI ENDW pseudo-op. */
6695 int ignore ATTRIBUTE_UNUSED;
6699 if (mri_control_stack == NULL
6700 || mri_control_stack->type != mri_while)
6702 as_bad (_("endw without while"));
6703 ignore_rest_of_line ();
6707 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6708 sprintf (buf, "bra %s", mri_control_stack->next);
6712 colon (mri_control_stack->bottom);
6718 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6719 ++input_line_pointer;
6722 demand_empty_rest_of_line ();
6727 * Invocation line includes a switch not recognized by the base assembler.
6728 * See if it's a processor-specific option. These are:
6730 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6731 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6732 * Select the architecture. Instructions or features not
6733 * supported by the selected architecture cause fatal
6734 * errors. More than one may be specified. The default is
6735 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6736 * for -m68000, and -m68882 is a synonym for -m68881.
6737 * -[A]m[c]no-68851, -[A]m[c]no-68881
6738 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6739 * so don't use or document it, but that's the way the parsing
6742 * -pic Indicates PIC.
6743 * -k Indicates PIC. (Sun 3 only.)
6746 * Permit `|' to be used in expressions.
6751 CONST char *md_shortopts = "lSA:m:kQ:V";
6753 CONST char *md_shortopts = "lSA:m:k";
6756 struct option md_longopts[] = {
6757 #define OPTION_PIC (OPTION_MD_BASE)
6758 {"pic", no_argument, NULL, OPTION_PIC},
6759 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6760 {"register-prefix-optional", no_argument, NULL,
6761 OPTION_REGISTER_PREFIX_OPTIONAL},
6762 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6763 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6764 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6765 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6766 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6767 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6768 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6769 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6770 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6771 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6772 {NULL, no_argument, NULL, 0}
6774 size_t md_longopts_size = sizeof(md_longopts);
6777 md_parse_option (c, arg)
6783 case 'l': /* -l means keep external to 2 bit offset
6784 rather than 16 bit one */
6785 flag_short_refs = 1;
6788 case 'S': /* -S means that jbsr's always turn into
6790 flag_long_jumps = 1;
6796 /* intentional fall-through */
6799 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6803 const char *oarg = arg;
6809 if (arg[0] == 'c' && arg[1] == '6')
6812 for (i = 0; i < n_archs; i++)
6813 if (!strcmp (arg, archs[i].name))
6818 as_bad (_("unrecognized option `%s'"), oarg);
6821 arch = archs[i].arch;
6824 else if (arch == m68851)
6833 if (arg[0] == 'c' && arg[1] == '6')
6836 for (i = 0; i < n_archs; i++)
6837 if (!strcmp (arg, archs[i].name))
6839 unsigned long arch = archs[i].arch;
6840 if (cpu_of_arch (arch))
6841 /* It's a cpu spec. */
6843 current_architecture &= ~m68000up;
6844 current_architecture |= arch;
6846 else if (arch == m68881)
6848 current_architecture |= m68881;
6851 else if (arch == m68851)
6853 current_architecture |= m68851;
6863 as_bad (_("unrecognized architecture specification `%s'"), arg);
6872 break; /* -pic, Position Independent Code */
6874 case OPTION_REGISTER_PREFIX_OPTIONAL:
6875 flag_reg_prefix_optional = 1;
6876 reg_prefix_optional_seen = 1;
6879 /* -V: SVR4 argument to print version ID. */
6881 print_version_id ();
6884 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6885 should be emitted or not. FIXME: Not implemented. */
6889 case OPTION_BITWISE_OR:
6894 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6896 for (s = m68k_comment_chars; *s != '\0'; s++)
6900 m68k_comment_chars = n;
6904 case OPTION_BASE_SIZE_DEFAULT_16:
6905 m68k_index_width_default = SIZE_WORD;
6908 case OPTION_BASE_SIZE_DEFAULT_32:
6909 m68k_index_width_default = SIZE_LONG;
6912 case OPTION_DISP_SIZE_DEFAULT_16:
6914 m68k_rel32_from_cmdline = 1;
6917 case OPTION_DISP_SIZE_DEFAULT_32:
6919 m68k_rel32_from_cmdline = 1;
6930 md_show_usage (stream)
6933 fprintf(stream, _("\
6935 -l use 1 word for refs to undefined symbols [default 2]\n\
6936 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6937 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6938 | -mcpu32 | -m5200\n\
6939 specify variant of 680X0 architecture [default 68020]\n\
6940 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6941 target has/lacks floating-point coprocessor\n\
6942 [default yes for 68020, 68030, and cpu32]\n"));
6943 fprintf(stream, _("\
6944 -m68851 | -mno-68851\n\
6945 target has/lacks memory-management unit coprocessor\n\
6946 [default yes for 68020 and up]\n\
6947 -pic, -k generate position independent code\n\
6948 -S turn jbsr into jsr\n\
6949 --register-prefix-optional\n\
6950 recognize register names without prefix character\n\
6951 --bitwise-or do not treat `|' as a comment character\n"));
6952 fprintf (stream, _("\
6953 --base-size-default-16 base reg without size is 16 bits\n\
6954 --base-size-default-32 base reg without size is 32 bits (default)\n\
6955 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6956 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6961 /* TEST2: Test md_assemble() */
6962 /* Warning, this routine probably doesn't work anymore */
6966 struct m68k_it the_ins;
6974 if (!gets (buf) || !*buf)
6976 if (buf[0] == '|' || buf[1] == '.')
6978 for (cp = buf; *cp; cp++)
6983 memset (&the_ins, '\0', sizeof (the_ins));
6984 m68k_ip (&the_ins, buf);
6987 printf (_("Error %s in %s\n"), the_ins.error, buf);
6991 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6992 for (n = 0; n < the_ins.numo; n++)
6993 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6995 print_the_insn (&the_ins.opcode[0], stdout);
6996 (void) putchar ('\n');
6998 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7000 if (the_ins.operands[n].error)
7002 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7005 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7006 if (the_ins.operands[n].b_const)
7007 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7008 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7009 if (the_ins.operands[n].b_iadd)
7010 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7011 (void) putchar ('\n');
7023 while (*str && *str != ' ')
7025 if (str[-1] == ':' || str[1] == '=')
7032 /* Possible states for relaxation:
7034 0 0 branch offset byte (bra, etc)
7038 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7042 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7049 /* We have no need to default values of symbols. */
7053 md_undefined_symbol (name)
7054 char *name ATTRIBUTE_UNUSED;
7059 /* Round up a section size to the appropriate boundary. */
7061 md_section_align (segment, size)
7062 segT segment ATTRIBUTE_UNUSED;
7066 #ifdef BFD_ASSEMBLER
7067 /* For a.out, force the section size to be aligned. If we don't do
7068 this, BFD will align it for us, but it will not write out the
7069 final bytes of the section. This may be a bug in BFD, but it is
7070 easier to fix it here since that is how the other a.out targets
7074 align = bfd_get_section_alignment (stdoutput, segment);
7075 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7082 /* Exactly what point is a PC-relative offset relative TO?
7083 On the 68k, it is relative to the address of the first extension
7084 word. The difference between the addresses of the offset and the
7085 first extension word is stored in fx_pcrel_adjust. */
7087 md_pcrel_from (fixP)
7092 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7094 adjust = fixP->fx_pcrel_adjust;
7097 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7100 #ifndef BFD_ASSEMBLER
7105 tc_coff_symbol_emit_hook (ignore)
7111 tc_coff_sizemachdep (frag)
7114 switch (frag->fr_subtype & 0x3)
7131 void m68k_elf_final_processing()
7133 /* Set file-specific flags if this is a cpu32 processor */
7134 if (cpu_of_arch (current_architecture) & cpu32)
7135 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7138 /* end of tc-m68k.c */