1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars = "|#";
43 const char *m68k_comment_chars = "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#*";
55 const char line_separator_chars[] = ";";
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 const char EXP_CHARS[] = "eE";
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
63 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
69 const int md_reloc_size = 8; /* Size of relocation record */
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
77 static int flag_short_refs; /* -l option */
78 static int flag_long_jumps; /* -S option */
79 static int flag_keep_pcrel; /* --pcrel option. */
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
84 int flag_reg_prefix_optional;
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen;
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum = COP1;
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd;
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick = 1;
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
104 static int m68k_rel32 = 1;
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline;
109 /* The default width to use for an index register when using a base
111 static enum m68k_size m68k_index_width_default = SIZE_LONG;
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
119 struct label_line *next;
126 /* The list of labels. */
128 static struct label_line *labels;
130 /* The current label. */
132 static struct label_line *current_label;
134 /* Its an arbitrary name: This means I don't approve of it */
135 /* See flames below */
136 static struct obstack robyn;
140 const char *m_operands;
141 unsigned long m_opcode;
145 struct m68k_incant *m_next;
148 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149 #define gettwo(x) (((x)->m_opcode)&0xffff)
151 static const enum m68k_register m68000_control_regs[] = { 0 };
152 static const enum m68k_register m68010_control_regs[] = {
156 static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
160 static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
165 static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
170 static const enum m68k_register mcf_control_regs[] = {
171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
172 RAMBAR0, RAMBAR1, MBAR,
175 #define cpu32_control_regs m68010_control_regs
177 static const enum m68k_register *control_regs;
179 /* internal form of a 68020 instruction */
183 const char *args; /* list of opcode info */
186 int numo; /* Number of shorts in opcode */
189 struct m68k_op operands[6];
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
194 int nfrag; /* Number of frags we have to produce */
197 int fragoff; /* Where in the current opcode the frag ends */
204 int nrel; /* Num of reloc strucs in use */
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
220 /* Whether this expression needs special pic relocation, and if
222 enum pic_relocation pic_reloc;
225 reloc[5]; /* Five is enough??? */
228 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
229 #define float_of_arch(x) ((x) & mfloat)
230 #define mmu_of_arch(x) ((x) & mmmu)
231 #define arch_coldfire_p(x) (((x) & mcf) != 0)
233 /* Macros for determining if cpu supports a specific addressing mode */
234 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
236 static struct m68k_it the_ins; /* the instruction being assembled */
238 #define op(ex) ((ex)->exp.X_op)
239 #define adds(ex) ((ex)->exp.X_add_symbol)
240 #define subs(ex) ((ex)->exp.X_op_symbol)
241 #define offs(ex) ((ex)->exp.X_add_number)
243 /* Macros for adding things to the m68k_it struct */
245 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
247 /* Static functions. */
249 static void insop PARAMS ((int, const struct m68k_incant *));
250 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251 static void add_frag PARAMS ((symbolS *, offsetT, int));
253 /* Like addword, but goes BEFORE general operands */
257 const struct m68k_incant *opcode;
260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
261 the_ins.opcode[z] = the_ins.opcode[z - 1];
262 for (z = 0; z < the_ins.nrel; z++)
263 the_ins.reloc[z].n += 2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum] = w;
270 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
273 add_fix (width, exp, pc_rel, pc_fix)
275 struct m68k_exp *exp;
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
293 /* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
304 add_frag (add, off, type)
309 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd = add;
311 the_ins.fragb[the_ins.nfrag].foff = off;
312 the_ins.fragb[the_ins.nfrag++].fragty = type;
316 (op (ex) != O_constant && op (ex) != O_big)
318 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320 static void m68k_ip PARAMS ((char *));
321 static void insert_reg PARAMS ((const char *, int));
322 static void select_control_regs PARAMS ((void));
323 static void init_regtable PARAMS ((void));
324 static int reverse_16_bits PARAMS ((int in));
325 static int reverse_8_bits PARAMS ((int in));
326 static void install_gen_operand PARAMS ((int mode, int val));
327 static void install_operand PARAMS ((int mode, int val));
328 static void s_bss PARAMS ((int));
329 static void s_data1 PARAMS ((int));
330 static void s_data2 PARAMS ((int));
331 static void s_even PARAMS ((int));
332 static void s_proc PARAMS ((int));
333 static void mri_chip PARAMS ((void));
334 static void s_chip PARAMS ((int));
335 static void s_fopt PARAMS ((int));
336 static void s_opt PARAMS ((int));
337 static void s_reg PARAMS ((int));
338 static void s_restore PARAMS ((int));
339 static void s_save PARAMS ((int));
340 static void s_mri_if PARAMS ((int));
341 static void s_mri_else PARAMS ((int));
342 static void s_mri_endi PARAMS ((int));
343 static void s_mri_break PARAMS ((int));
344 static void s_mri_next PARAMS ((int));
345 static void s_mri_for PARAMS ((int));
346 static void s_mri_endf PARAMS ((int));
347 static void s_mri_repeat PARAMS ((int));
348 static void s_mri_until PARAMS ((int));
349 static void s_mri_while PARAMS ((int));
350 static void s_mri_endw PARAMS ((int));
351 static void md_convert_frag_1 PARAMS ((fragS *));
353 static int current_architecture;
362 static const struct m68k_cpu archs[] =
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
409 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
414 /* Macros used in the relaxation code. */
415 #define TAB(x,y) (((x) << 2) + (y))
416 #define TABTYPE(x) ((x) >> 2)
418 /* Relaxation states. */
424 /* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
434 #define BRANCHBWL 0 /* branch byte, word, or long */
435 #define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
436 #define BRABSJCOND 2 /* absolute jump for LONG, conditional */
437 #define BRANCHBW 3 /* branch byte or word */
439 /* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
447 #define FBRANCH 4 /* coprocessor branch */
448 #define DBCCLBR 5 /* DBcc relaxable with a long branch */
449 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
451 /* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
462 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
463 #define PCINDEX 8 /* PC+displacement+index */
464 #define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
466 /* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
475 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
476 relax_typeS md_relax_table[] =
478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
529 /* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
534 /* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
540 const pseudo_typeS md_pseudo_table[] =
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
546 {"skip", s_space, 0},
548 #if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
552 {"swbeg", s_ignore, 0},
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
558 /* Dwarf2 support for Gcc. */
559 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
560 {"loc", dwarf2_directive_loc, 0},
563 /* The following pseudo-ops are supported for MRI compatibility. */
565 {"comline", s_space, 1},
567 {"mask2", s_ignore, 0},
570 {"restore", s_restore, 0},
574 {"if.b", s_mri_if, 'b'},
575 {"if.w", s_mri_if, 'w'},
576 {"if.l", s_mri_if, 'l'},
577 {"else", s_mri_else, 0},
578 {"else.s", s_mri_else, 's'},
579 {"else.l", s_mri_else, 'l'},
580 {"endi", s_mri_endi, 0},
581 {"break", s_mri_break, 0},
582 {"break.s", s_mri_break, 's'},
583 {"break.l", s_mri_break, 'l'},
584 {"next", s_mri_next, 0},
585 {"next.s", s_mri_next, 's'},
586 {"next.l", s_mri_next, 'l'},
587 {"for", s_mri_for, 0},
588 {"for.b", s_mri_for, 'b'},
589 {"for.w", s_mri_for, 'w'},
590 {"for.l", s_mri_for, 'l'},
591 {"endf", s_mri_endf, 0},
592 {"repeat", s_mri_repeat, 0},
593 {"until", s_mri_until, 0},
594 {"until.b", s_mri_until, 'b'},
595 {"until.w", s_mri_until, 'w'},
596 {"until.l", s_mri_until, 'l'},
597 {"while", s_mri_while, 0},
598 {"while.b", s_mri_while, 'b'},
599 {"while.w", s_mri_while, 'w'},
600 {"while.l", s_mri_while, 'l'},
601 {"endw", s_mri_endw, 0},
606 /* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
611 extern void obj_coff_section PARAMS ((int));
614 const pseudo_typeS mote_pseudo_table[] =
627 {"xdef", s_globl, 0},
629 {"align", s_align_bytes, 0},
631 {"align", s_align_ptwo, 0},
634 {"sect", obj_coff_section, 0},
635 {"section", obj_coff_section, 0},
640 #define issbyte(x) ((x)>=-128 && (x)<=127)
641 #define isubyte(x) ((x)>=0 && (x)<=255)
642 #define issword(x) ((x)>=-32768 && (x)<=32767)
643 #define isuword(x) ((x)>=0 && (x)<=65535)
645 #define isbyte(x) ((x)>= -255 && (x)<=255)
646 #define isword(x) ((x)>=-65536 && (x)<=65535)
647 #define islong(x) (1)
649 extern char *input_line_pointer;
651 static char notend_table[256];
652 static char alt_notend_table[256];
654 (! (notend_table[(unsigned char) *s] \
656 && alt_notend_table[(unsigned char) s[1]])))
658 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
660 #ifdef NO_PCREL_RELOCS
663 make_pcrel_absolute(fixP, add_number)
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
684 as_fatal (_("Unknown PC relative instruction"));
689 #endif /* NO_PCREL_RELOCS */
692 tc_coff_fix2rtype (fixP)
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697 #ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
717 /* Return zero if the reference to SYMBOL from within the same segment may
720 /* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
726 #define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
730 /* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
734 static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
737 static bfd_reloc_code_real_type
738 get_reloc_code (size, pcrel, pic)
741 enum pic_relocation pic;
749 return BFD_RELOC_8_GOT_PCREL;
751 return BFD_RELOC_16_GOT_PCREL;
753 return BFD_RELOC_32_GOT_PCREL;
761 return BFD_RELOC_8_GOTOFF;
763 return BFD_RELOC_16_GOTOFF;
765 return BFD_RELOC_32_GOTOFF;
773 return BFD_RELOC_8_PLT_PCREL;
775 return BFD_RELOC_16_PLT_PCREL;
777 return BFD_RELOC_32_PLT_PCREL;
785 return BFD_RELOC_8_PLTOFF;
787 return BFD_RELOC_16_PLTOFF;
789 return BFD_RELOC_32_PLTOFF;
799 return BFD_RELOC_8_PCREL;
801 return BFD_RELOC_16_PCREL;
803 return BFD_RELOC_32_PCREL;
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
830 as_bad (_("Can not do %d byte relocation"), size);
832 as_bad (_("Can not do %d byte pic relocation"), size);
835 return BFD_RELOC_NONE;
838 /* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
844 tc_m68k_fix_adjustable (fixP)
847 /* adjust_reloc_syms doesn't know about the GOT */
848 switch (fixP->fx_r_type)
850 case BFD_RELOC_8_GOT_PCREL:
851 case BFD_RELOC_16_GOT_PCREL:
852 case BFD_RELOC_32_GOT_PCREL:
853 case BFD_RELOC_8_GOTOFF:
854 case BFD_RELOC_16_GOTOFF:
855 case BFD_RELOC_32_GOTOFF:
856 case BFD_RELOC_8_PLT_PCREL:
857 case BFD_RELOC_16_PLT_PCREL:
858 case BFD_RELOC_32_PLT_PCREL:
859 case BFD_RELOC_8_PLTOFF:
860 case BFD_RELOC_16_PLTOFF:
861 case BFD_RELOC_32_PLTOFF:
864 case BFD_RELOC_VTABLE_INHERIT:
865 case BFD_RELOC_VTABLE_ENTRY:
875 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
877 #define relaxable_symbol(symbol) 1
884 tc_gen_reloc (section, fixp)
889 bfd_reloc_code_real_type code;
891 /* If the tcbit is set, then this was a fixup of a negative value
892 that was never resolved. We do not have a reloc to handle this,
893 so just return. We assume that other code will have detected this
894 situation and produced a helpful error message, so we just tell the
895 user that the reloc cannot be produced. */
899 as_bad_where (fixp->fx_file, fixp->fx_line,
900 _("Unable to produce reloc against symbol '%s'"),
901 S_GET_NAME (fixp->fx_addsy));
905 if (fixp->fx_r_type != BFD_RELOC_NONE)
907 code = fixp->fx_r_type;
909 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
910 that fixup_segment converted a non-PC relative reloc into a
911 PC relative reloc. In such a case, we need to convert the
918 code = BFD_RELOC_8_PCREL;
921 code = BFD_RELOC_16_PCREL;
924 code = BFD_RELOC_32_PCREL;
926 case BFD_RELOC_8_PCREL:
927 case BFD_RELOC_16_PCREL:
928 case BFD_RELOC_32_PCREL:
929 case BFD_RELOC_8_GOT_PCREL:
930 case BFD_RELOC_16_GOT_PCREL:
931 case BFD_RELOC_32_GOT_PCREL:
932 case BFD_RELOC_8_GOTOFF:
933 case BFD_RELOC_16_GOTOFF:
934 case BFD_RELOC_32_GOTOFF:
935 case BFD_RELOC_8_PLT_PCREL:
936 case BFD_RELOC_16_PLT_PCREL:
937 case BFD_RELOC_32_PLT_PCREL:
938 case BFD_RELOC_8_PLTOFF:
939 case BFD_RELOC_16_PLTOFF:
940 case BFD_RELOC_32_PLTOFF:
943 as_bad_where (fixp->fx_file, fixp->fx_line,
944 _("Cannot make %s relocation PC relative"),
945 bfd_get_reloc_code_name (code));
951 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
952 switch (F (fixp->fx_size, fixp->fx_pcrel))
954 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
955 MAP (1, 0, BFD_RELOC_8);
956 MAP (2, 0, BFD_RELOC_16);
957 MAP (4, 0, BFD_RELOC_32);
958 MAP (1, 1, BFD_RELOC_8_PCREL);
959 MAP (2, 1, BFD_RELOC_16_PCREL);
960 MAP (4, 1, BFD_RELOC_32_PCREL);
968 reloc = (arelent *) xmalloc (sizeof (arelent));
969 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
970 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
971 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
974 reloc->addend = fixp->fx_addnumber;
979 reloc->addend = fixp->fx_addnumber;
981 reloc->addend = (section->vma
982 /* Explicit sign extension in case char is
984 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
986 + md_pcrel_from (fixp));
989 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
990 assert (reloc->howto != 0);
995 #endif /* BFD_ASSEMBLER */
997 /* Handle of the OPCODE hash table. NULL means any use before
998 m68k_ip_begin() will crash. */
999 static struct hash_control *op_hash;
1001 /* Assemble an m68k instruction. */
1008 register struct m68k_op *opP;
1009 register const struct m68k_incant *opcode;
1010 register const char *s;
1011 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1012 char *pdot, *pdotmove;
1013 enum m68k_size siz1, siz2;
1017 LITTLENUM_TYPE words[6];
1018 LITTLENUM_TYPE *wordp;
1019 unsigned long ok_arch = 0;
1021 if (*instring == ' ')
1022 instring++; /* skip leading whitespace */
1024 /* Scan up to end of operation-code, which MUST end in end-of-string
1025 or exactly 1 space. */
1027 for (p = instring; *p != '\0'; p++)
1037 the_ins.error = _("No operator");
1041 /* p now points to the end of the opcode name, probably whitespace.
1042 Make sure the name is null terminated by clobbering the
1043 whitespace, look it up in the hash table, then fix it back.
1044 Remove a dot, first, since the opcode tables have none. */
1047 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1048 *pdotmove = pdotmove[1];
1054 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1059 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1060 *pdotmove = pdotmove[-1];
1067 the_ins.error = _("Unknown operator");
1071 /* found a legitimate opcode, start matching operands */
1075 if (opcode->m_operands == 0)
1077 char *old = input_line_pointer;
1079 input_line_pointer = p;
1080 /* Ahh - it's a motorola style psuedo op */
1081 mote_pseudo_table[opcode->m_opnum].poc_handler
1082 (mote_pseudo_table[opcode->m_opnum].poc_val);
1083 input_line_pointer = old;
1089 if (flag_mri && opcode->m_opnum == 0)
1091 /* In MRI mode, random garbage is allowed after an instruction
1092 which accepts no operands. */
1093 the_ins.args = opcode->m_operands;
1094 the_ins.numargs = opcode->m_opnum;
1095 the_ins.numo = opcode->m_codenum;
1096 the_ins.opcode[0] = getone (opcode);
1097 the_ins.opcode[1] = gettwo (opcode);
1101 for (opP = &the_ins.operands[0]; *p; opP++)
1103 p = crack_operand (p, opP);
1107 the_ins.error = opP->error;
1112 opsfound = opP - &the_ins.operands[0];
1114 /* This ugly hack is to support the floating pt opcodes in their
1115 standard form. Essentially, we fake a first enty of type COP#1 */
1116 if (opcode->m_operands[0] == 'I')
1120 for (n = opsfound; n > 0; --n)
1121 the_ins.operands[n] = the_ins.operands[n - 1];
1123 memset ((char *) (&the_ins.operands[0]), '\0',
1124 sizeof (the_ins.operands[0]));
1125 the_ins.operands[0].mode = CONTROL;
1126 the_ins.operands[0].reg = m68k_float_copnum;
1130 /* We've got the operands. Find an opcode that'll accept them */
1133 /* If we didn't get the right number of ops, or we have no
1134 common model with this pattern then reject this pattern. */
1136 ok_arch |= opcode->m_arch;
1137 if (opsfound != opcode->m_opnum
1138 || ((opcode->m_arch & current_architecture) == 0))
1142 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1146 /* Warning: this switch is huge! */
1147 /* I've tried to organize the cases into this order:
1148 non-alpha first, then alpha by letter. Lower-case
1149 goes directly before uppercase counterpart. */
1150 /* Code with multiple case ...: gets sorted by the lowest
1151 case ... it belongs to. I hope this makes sense. */
1257 if (opP->reg == PC || opP->reg == ZPC)
1274 if (opP->reg == PC || opP->reg == ZPC)
1293 if (opP->reg == PC || opP->reg == ZPC)
1303 if (opP->mode != IMMED)
1305 else if (s[1] == 'b'
1306 && ! isvar (&opP->disp)
1307 && (opP->disp.exp.X_op != O_constant
1308 || ! isbyte (opP->disp.exp.X_add_number)))
1310 else if (s[1] == 'B'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! issbyte (opP->disp.exp.X_add_number)))
1315 else if (s[1] == 'w'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! isword (opP->disp.exp.X_add_number)))
1320 else if (s[1] == 'W'
1321 && ! isvar (&opP->disp)
1322 && (opP->disp.exp.X_op != O_constant
1323 || ! issword (opP->disp.exp.X_add_number)))
1329 if (opP->mode != IMMED)
1334 if (opP->mode == AREG
1335 || opP->mode == CONTROL
1336 || opP->mode == FPREG
1337 || opP->mode == IMMED
1338 || opP->mode == REGLST
1339 || (opP->mode != ABSL
1341 || opP->reg == ZPC)))
1346 if (opP->mode == CONTROL
1347 || opP->mode == FPREG
1348 || opP->mode == REGLST
1349 || opP->mode == IMMED
1350 || (opP->mode != ABSL
1352 || opP->reg == ZPC)))
1380 if (opP->mode == CONTROL
1381 || opP->mode == FPREG
1382 || opP->mode == REGLST)
1387 if (opP->mode != AINC)
1392 if (opP->mode != ADEC)
1442 if (opP->reg == PC || opP->reg == ZPC)
1463 case '~': /* For now! (JF FOO is this right?) */
1485 if (opP->mode != CONTROL
1486 || (opP->reg != TT0 && opP->reg != TT1))
1491 if (opP->mode != AREG)
1496 if (opP->mode != AINDR)
1501 if (opP->mode != ABSL
1503 && strncmp (instring, "jbsr", 4) == 0))
1508 if (opP->mode != CONTROL || opP->reg != CCR)
1513 if (opP->mode != DISP
1515 || opP->reg > ADDR7)
1520 if (opP->mode != DREG)
1525 if (opP->reg != ACC)
1530 if (opP->mode != FPREG)
1535 if (opP->reg != MACSR)
1540 if (opP->reg != MASK)
1545 if (opP->mode != CONTROL
1552 if (opP->mode != CONTROL
1554 || opP->reg > last_movec_reg)
1558 const enum m68k_register *rp;
1559 for (rp = control_regs; *rp; rp++)
1560 if (*rp == opP->reg)
1568 if (opP->mode != IMMED)
1574 if (opP->mode == DREG
1575 || opP->mode == AREG
1576 || opP->mode == FPREG)
1585 opP->mask = 1 << (opP->reg - DATA0);
1588 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1591 opP->mask = 1 << (opP->reg - FP0 + 16);
1599 else if (opP->mode == CONTROL)
1608 opP->mask = 1 << 24;
1611 opP->mask = 1 << 25;
1614 opP->mask = 1 << 26;
1623 else if (opP->mode != REGLST)
1625 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1627 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1632 if (opP->mode != IMMED)
1634 else if (opP->disp.exp.X_op != O_constant
1635 || ! issbyte (opP->disp.exp.X_add_number))
1637 else if (! m68k_quick
1638 && instring[3] != 'q'
1639 && instring[4] != 'q')
1644 if (opP->mode != DREG
1645 && opP->mode != IMMED
1646 && opP->mode != ABSL)
1651 if (opP->mode != IMMED)
1653 else if (opP->disp.exp.X_op != O_constant
1654 || opP->disp.exp.X_add_number < 1
1655 || opP->disp.exp.X_add_number > 8)
1657 else if (! m68k_quick
1658 && (strncmp (instring, "add", 3) == 0
1659 || strncmp (instring, "sub", 3) == 0)
1660 && instring[3] != 'q')
1665 if (opP->mode != DREG && opP->mode != AREG)
1670 if (opP->mode != AINDR
1671 && (opP->mode != BASE
1673 && opP->reg != ZADDR0)
1674 || opP->disp.exp.X_op != O_absent
1675 || ((opP->index.reg < DATA0
1676 || opP->index.reg > DATA7)
1677 && (opP->index.reg < ADDR0
1678 || opP->index.reg > ADDR7))
1679 || opP->index.size != SIZE_UNSPEC
1680 || opP->index.scale != 1))
1685 if (opP->mode != CONTROL
1686 || ! (opP->reg == FPI
1688 || opP->reg == FPC))
1693 if (opP->mode != CONTROL || opP->reg != SR)
1698 if (opP->mode != IMMED)
1700 else if (opP->disp.exp.X_op != O_constant
1701 || opP->disp.exp.X_add_number < 0
1702 || opP->disp.exp.X_add_number > 7)
1707 if (opP->mode != CONTROL || opP->reg != USP)
1711 /* JF these are out of order. We could put them
1712 in order if we were willing to put up with
1713 bunches of #ifdef m68851s in the code.
1715 Don't forget that you need these operands
1716 to use 68030 MMU instructions. */
1718 /* Memory addressing mode used by pflushr */
1720 if (opP->mode == CONTROL
1721 || opP->mode == FPREG
1722 || opP->mode == DREG
1723 || opP->mode == AREG
1724 || opP->mode == REGLST)
1726 /* We should accept immediate operands, but they
1727 supposedly have to be quad word, and we don't
1728 handle that. I would like to see what a Motorola
1729 assembler does before doing something here. */
1730 if (opP->mode == IMMED)
1735 if (opP->mode != CONTROL
1736 || (opP->reg != SFC && opP->reg != DFC))
1741 if (opP->mode != CONTROL || opP->reg != TC)
1746 if (opP->mode != CONTROL || opP->reg != AC)
1751 if (opP->mode != CONTROL
1754 && opP->reg != SCC))
1759 if (opP->mode != CONTROL
1765 if (opP->mode != CONTROL
1768 && opP->reg != CRP))
1773 if (opP->mode != CONTROL
1774 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1775 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1780 if (opP->mode != CONTROL || opP->reg != PSR)
1785 if (opP->mode != CONTROL || opP->reg != PCSR)
1790 if (opP->mode != CONTROL
1797 } /* not a cache specifier. */
1801 if (opP->mode != ABSL)
1806 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1808 /* FIXME: kludge instead of fixing parser:
1809 upper/lower registers are *not* CONTROL
1810 registers, but ordinary ones. */
1811 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1812 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1820 } /* switch on type of operand */
1824 } /* for each operand */
1825 } /* if immediately wrong */
1832 opcode = opcode->m_next;
1837 && !(ok_arch & current_architecture))
1842 _("invalid instruction for this architecture; needs "));
1843 cp = buf + strlen (buf);
1847 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1850 strcpy (cp, _("mmu (68030 or 68851)"));
1853 strcpy (cp, _("68020 or higher"));
1856 strcpy (cp, _("68000 or higher"));
1859 strcpy (cp, _("68010 or higher"));
1863 int got_one = 0, idx;
1865 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1868 if ((archs[idx].arch & ok_arch)
1869 && ! archs[idx].alias)
1873 strcpy (cp, " or ");
1877 strcpy (cp, archs[idx].name);
1883 cp = xmalloc (strlen (buf) + 1);
1888 the_ins.error = _("operands mismatch");
1890 } /* Fell off the end */
1895 /* now assemble it */
1897 the_ins.args = opcode->m_operands;
1898 the_ins.numargs = opcode->m_opnum;
1899 the_ins.numo = opcode->m_codenum;
1900 the_ins.opcode[0] = getone (opcode);
1901 the_ins.opcode[1] = gettwo (opcode);
1903 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1905 /* This switch is a doozy.
1906 Watch the first step; its a big one! */
1934 tmpreg = 0x3c; /* 7.4 */
1935 if (strchr ("bwl", s[1]))
1936 nextword = get_num (&opP->disp, 80);
1938 nextword = get_num (&opP->disp, 0);
1939 if (isvar (&opP->disp))
1940 add_fix (s[1], &opP->disp, 0, 0);
1944 if (!isbyte (nextword))
1945 opP->error = _("operand out of range");
1950 if (!isword (nextword))
1951 opP->error = _("operand out of range");
1956 if (!issword (nextword))
1957 opP->error = _("operand out of range");
1962 addword (nextword >> 16);
1989 /* We gotta put out some float */
1990 if (op (&opP->disp) != O_big)
1995 /* Can other cases happen here? */
1996 if (op (&opP->disp) != O_constant)
1999 val = (valueT) offs (&opP->disp);
2003 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2004 val >>= LITTLENUM_NUMBER_OF_BITS;
2008 offs (&opP->disp) = gencnt;
2010 if (offs (&opP->disp) > 0)
2012 if (offs (&opP->disp) > baseo)
2014 as_warn (_("Bignum too big for %c format; truncated"),
2016 offs (&opP->disp) = baseo;
2018 baseo -= offs (&opP->disp);
2021 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2022 offs (&opP->disp)--;
2027 gen_to_words (words, baseo, (long) outro);
2028 for (wordp = words; baseo--; wordp++)
2032 tmpreg = opP->reg - DATA; /* 0.dreg */
2035 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2038 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2041 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2044 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2048 nextword = get_num (&opP->disp, 80);
2051 && ! isvar (&opP->disp)
2054 opP->disp.exp.X_op = O_symbol;
2055 #ifndef BFD_ASSEMBLER
2056 opP->disp.exp.X_add_symbol = &abs_symbol;
2058 opP->disp.exp.X_add_symbol =
2059 section_symbol (absolute_section);
2063 /* Force into index mode. Hope this works */
2065 /* We do the first bit for 32-bit displacements, and the
2066 second bit for 16 bit ones. It is possible that we
2067 should make the default be WORD instead of LONG, but
2068 I think that'd break GCC, so we put up with a little
2069 inefficiency for the sake of working output. */
2071 if (!issword (nextword)
2072 || (isvar (&opP->disp)
2073 && ((opP->disp.size == SIZE_UNSPEC
2074 && flag_short_refs == 0
2075 && cpu_of_arch (current_architecture) >= m68020
2076 && ! arch_coldfire_p (current_architecture))
2077 || opP->disp.size == SIZE_LONG)))
2079 if (cpu_of_arch (current_architecture) < m68020
2080 || arch_coldfire_p (current_architecture))
2082 _("displacement too large for this architecture; needs 68020 or higher");
2084 tmpreg = 0x3B; /* 7.3 */
2086 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2087 if (isvar (&opP->disp))
2091 if (opP->disp.size == SIZE_LONG
2093 /* If the displacement needs pic
2094 relocation it cannot be relaxed. */
2095 || opP->disp.pic_reloc != pic_none
2100 add_fix ('l', &opP->disp, 1, 2);
2104 add_frag (adds (&opP->disp),
2106 TAB (PCREL1632, SZ_UNDEF));
2113 add_fix ('l', &opP->disp, 0, 0);
2118 addword (nextword >> 16);
2123 tmpreg = 0x3A; /* 7.2 */
2125 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2127 if (isvar (&opP->disp))
2131 add_fix ('w', &opP->disp, 1, 0);
2134 add_fix ('w', &opP->disp, 0, 0);
2144 baseo = get_num (&opP->disp, 80);
2145 if (opP->mode == POST || opP->mode == PRE)
2146 outro = get_num (&opP->odisp, 80);
2147 /* Figure out the `addressing mode'.
2148 Also turn on the BASE_DISABLE bit, if needed. */
2149 if (opP->reg == PC || opP->reg == ZPC)
2151 tmpreg = 0x3b; /* 7.3 */
2152 if (opP->reg == ZPC)
2155 else if (opP->reg == 0)
2158 tmpreg = 0x30; /* 6.garbage */
2160 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2163 tmpreg = 0x30 + opP->reg - ZADDR0;
2166 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2168 siz1 = opP->disp.size;
2169 if (opP->mode == POST || opP->mode == PRE)
2170 siz2 = opP->odisp.size;
2174 /* Index register stuff */
2175 if (opP->index.reg != 0
2176 && opP->index.reg >= DATA
2177 && opP->index.reg <= ADDR7)
2179 nextword |= (opP->index.reg - DATA) << 12;
2181 if (opP->index.size == SIZE_LONG
2182 || (opP->index.size == SIZE_UNSPEC
2183 && m68k_index_width_default == SIZE_LONG))
2186 if ((opP->index.scale != 1
2187 && cpu_of_arch (current_architecture) < m68020)
2188 || (opP->index.scale == 8
2189 && arch_coldfire_p (current_architecture)))
2192 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2195 if (arch_coldfire_p (current_architecture)
2196 && opP->index.size == SIZE_WORD)
2197 opP->error = _("invalid index size for coldfire");
2199 switch (opP->index.scale)
2216 GET US OUT OF HERE! */
2218 /* Must be INDEX, with an index register. Address
2219 register cannot be ZERO-PC, and either :b was
2220 forced, or we know it will fit. For a 68000 or
2221 68010, force this mode anyways, because the
2222 larger modes aren't supported. */
2223 if (opP->mode == BASE
2224 && ((opP->reg >= ADDR0
2225 && opP->reg <= ADDR7)
2228 if (siz1 == SIZE_BYTE
2229 || cpu_of_arch (current_architecture) < m68020
2230 || arch_coldfire_p (current_architecture)
2231 || (siz1 == SIZE_UNSPEC
2232 && ! isvar (&opP->disp)
2233 && issbyte (baseo)))
2235 nextword += baseo & 0xff;
2237 if (isvar (&opP->disp))
2239 /* Do a byte relocation. If it doesn't
2240 fit (possible on m68000) let the
2241 fixup processing complain later. */
2243 add_fix ('B', &opP->disp, 1, 1);
2245 add_fix ('B', &opP->disp, 0, 0);
2247 else if (siz1 != SIZE_BYTE)
2249 if (siz1 != SIZE_UNSPEC)
2250 as_warn (_("Forcing byte displacement"));
2251 if (! issbyte (baseo))
2252 opP->error = _("byte displacement out of range");
2257 else if (siz1 == SIZE_UNSPEC
2259 && isvar (&opP->disp)
2260 && subs (&opP->disp) == NULL
2262 /* If the displacement needs pic
2263 relocation it cannot be relaxed. */
2264 && opP->disp.pic_reloc == pic_none
2268 /* The code in md_convert_frag_1 needs to be
2269 able to adjust nextword. Call frag_grow
2270 to ensure that we have enough space in
2271 the frag obstack to make all the bytes
2274 nextword += baseo & 0xff;
2276 add_frag (adds (&opP->disp), offs (&opP->disp),
2277 TAB (PCINDEX, SZ_UNDEF));
2285 nextword |= 0x40; /* No index reg */
2286 if (opP->index.reg >= ZDATA0
2287 && opP->index.reg <= ZDATA7)
2288 nextword |= (opP->index.reg - ZDATA0) << 12;
2289 else if (opP->index.reg >= ZADDR0
2290 || opP->index.reg <= ZADDR7)
2291 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2294 /* It isn't simple. */
2296 if (cpu_of_arch (current_architecture) < m68020
2297 || arch_coldfire_p (current_architecture))
2299 _("invalid operand mode for this architecture; needs 68020 or higher");
2302 /* If the guy specified a width, we assume that it is
2303 wide enough. Maybe it isn't. If so, we lose. */
2307 if (isvar (&opP->disp)
2309 : ! issword (baseo))
2314 else if (! isvar (&opP->disp) && baseo == 0)
2323 as_warn (_(":b not permitted; defaulting to :w"));
2333 /* Figure out innner displacement stuff */
2334 if (opP->mode == POST || opP->mode == PRE)
2336 if (cpu_of_arch (current_architecture) & cpu32)
2337 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2341 if (isvar (&opP->odisp)
2343 : ! issword (outro))
2348 else if (! isvar (&opP->odisp) && outro == 0)
2357 as_warn (_(":b not permitted; defaulting to :w"));
2366 if (opP->mode == POST
2367 && (nextword & 0x40) == 0)
2372 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2374 if (opP->reg == PC || opP->reg == ZPC)
2375 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2377 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2379 if (siz1 == SIZE_LONG)
2380 addword (baseo >> 16);
2381 if (siz1 != SIZE_UNSPEC)
2384 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2385 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2386 if (siz2 == SIZE_LONG)
2387 addword (outro >> 16);
2388 if (siz2 != SIZE_UNSPEC)
2394 nextword = get_num (&opP->disp, 80);
2395 switch (opP->disp.size)
2400 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2402 tmpreg = 0x38; /* 7.0 */
2406 if (isvar (&opP->disp)
2407 && !subs (&opP->disp)
2408 && adds (&opP->disp)
2410 /* If the displacement needs pic relocation it
2411 cannot be relaxed. */
2412 && opP->disp.pic_reloc == pic_none
2415 && !strchr ("~%&$?", s[0]))
2417 tmpreg = 0x3A; /* 7.2 */
2418 add_frag (adds (&opP->disp),
2420 TAB (ABSTOPCREL, SZ_UNDEF));
2423 /* Fall through into long */
2425 if (isvar (&opP->disp))
2426 add_fix ('l', &opP->disp, 0, 0);
2428 tmpreg = 0x39;/* 7.1 mode */
2429 addword (nextword >> 16);
2434 as_bad (_("unsupported byte value; use a different suffix"));
2436 case SIZE_WORD: /* Word */
2437 if (isvar (&opP->disp))
2438 add_fix ('w', &opP->disp, 0, 0);
2440 tmpreg = 0x38;/* 7.0 mode */
2448 as_bad (_("unknown/incorrect operand"));
2451 install_gen_operand (s[1], tmpreg);
2457 { /* JF: I hate floating point! */
2472 tmpreg = get_num (&opP->disp, tmpreg);
2473 if (isvar (&opP->disp))
2474 add_fix (s[1], &opP->disp, 0, 0);
2477 case 'b': /* Danger: These do no check for
2478 certain types of overflow.
2480 if (!isbyte (tmpreg))
2481 opP->error = _("out of range");
2482 insop (tmpreg, opcode);
2483 if (isvar (&opP->disp))
2484 the_ins.reloc[the_ins.nrel - 1].n =
2485 (opcode->m_codenum) * 2 + 1;
2488 if (!issbyte (tmpreg))
2489 opP->error = _("out of range");
2490 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2491 if (isvar (&opP->disp))
2492 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2495 if (!isword (tmpreg))
2496 opP->error = _("out of range");
2497 insop (tmpreg, opcode);
2498 if (isvar (&opP->disp))
2499 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2502 if (!issword (tmpreg))
2503 opP->error = _("out of range");
2504 insop (tmpreg, opcode);
2505 if (isvar (&opP->disp))
2506 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2509 /* Because of the way insop works, we put these two out
2511 insop (tmpreg, opcode);
2512 insop (tmpreg >> 16, opcode);
2513 if (isvar (&opP->disp))
2514 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2521 install_operand (s[1], tmpreg);
2532 install_operand (s[1], opP->reg - ADDR);
2536 tmpreg = get_num (&opP->disp, 80);
2540 add_fix ('B', &opP->disp, 1, -1);
2543 add_fix ('w', &opP->disp, 1, 0);
2548 if (! HAVE_LONG_BRANCH (current_architecture))
2549 as_warn (_("Can't use long branches on 68000/68010/5200"));
2550 the_ins.opcode[0] |= 0xff;
2551 add_fix ('l', &opP->disp, 1, 0);
2556 if (subs (&opP->disp)) /* We can't relax it */
2560 /* If the displacement needs pic relocation it cannot be
2562 if (opP->disp.pic_reloc != pic_none)
2565 /* This could either be a symbol, or an absolute
2566 address. If it's an absolute address, turn it into
2567 an absolute jump right here and keep it out of the
2569 if (adds (&opP->disp) == 0)
2571 if (the_ins.opcode[0] == 0x6000) /* jbra */
2572 the_ins.opcode[0] = 0x4EF9;
2573 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2574 the_ins.opcode[0] = 0x4EB9;
2577 the_ins.opcode[0] ^= 0x0100;
2578 the_ins.opcode[0] |= 0x0006;
2581 add_fix ('l', &opP->disp, 0, 0);
2587 /* Now we know it's going into the relaxer. Now figure
2588 out which mode. We try in this order of preference:
2589 long branch, absolute jump, byte/word branches only. */
2590 if (HAVE_LONG_BRANCH (current_architecture))
2591 add_frag (adds (&opP->disp), offs (&opP->disp),
2592 TAB (BRANCHBWL, SZ_UNDEF));
2593 else if (! flag_keep_pcrel)
2595 if ((the_ins.opcode[0] == 0x6000)
2596 || (the_ins.opcode[0] == 0x6100))
2597 add_frag (adds (&opP->disp), offs (&opP->disp),
2598 TAB (BRABSJUNC, SZ_UNDEF));
2600 add_frag (adds (&opP->disp), offs (&opP->disp),
2601 TAB (BRABSJCOND, SZ_UNDEF));
2604 add_frag (adds (&opP->disp), offs (&opP->disp),
2605 TAB (BRANCHBW, SZ_UNDEF));
2608 if (isvar (&opP->disp))
2610 /* Check for DBcc instructions. We can relax them,
2611 but only if we have long branches and/or absolute
2613 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2614 && (HAVE_LONG_BRANCH (current_architecture)
2615 || (! flag_keep_pcrel)))
2617 if (HAVE_LONG_BRANCH (current_architecture))
2618 add_frag (adds (&opP->disp), offs (&opP->disp),
2619 TAB (DBCCLBR, SZ_UNDEF));
2621 add_frag (adds (&opP->disp), offs (&opP->disp),
2622 TAB (DBCCABSJ, SZ_UNDEF));
2625 add_fix ('w', &opP->disp, 1, 0);
2629 case 'C': /* Fixed size LONG coproc branches */
2630 add_fix ('l', &opP->disp, 1, 0);
2634 case 'c': /* Var size Coprocesssor branches */
2635 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2637 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2638 add_fix ('l', &opP->disp, 1, 0);
2643 add_frag (adds (&opP->disp), offs (&opP->disp),
2644 TAB (FBRANCH, SZ_UNDEF));
2651 case 'C': /* Ignore it */
2654 case 'd': /* JF this is a kludge */
2655 install_operand ('s', opP->reg - ADDR);
2656 tmpreg = get_num (&opP->disp, 80);
2657 if (!issword (tmpreg))
2659 as_warn (_("Expression out of range, using 0"));
2666 install_operand (s[1], opP->reg - DATA);
2669 case 'E': /* Ignore it */
2673 install_operand (s[1], opP->reg - FP0);
2676 case 'G': /* Ignore it */
2681 tmpreg = opP->reg - COP0;
2682 install_operand (s[1], tmpreg);
2685 case 'J': /* JF foo */
2758 install_operand (s[1], tmpreg);
2762 tmpreg = get_num (&opP->disp, 55);
2763 install_operand (s[1], tmpreg & 0x7f);
2770 if (tmpreg & 0x7FF0000)
2771 as_bad (_("Floating point register in register list"));
2772 insop (reverse_16_bits (tmpreg), opcode);
2776 if (tmpreg & 0x700FFFF)
2777 as_bad (_("Wrong register in floating-point reglist"));
2778 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2786 if (tmpreg & 0x7FF0000)
2787 as_bad (_("Floating point register in register list"));
2788 insop (tmpreg, opcode);
2790 else if (s[1] == '8')
2792 if (tmpreg & 0x0FFFFFF)
2793 as_bad (_("incorrect register in reglist"));
2794 install_operand (s[1], tmpreg >> 24);
2798 if (tmpreg & 0x700FFFF)
2799 as_bad (_("wrong register in floating-point reglist"));
2801 install_operand (s[1], tmpreg >> 16);
2806 install_operand (s[1], get_num (&opP->disp, 60));
2810 tmpreg = ((opP->mode == DREG)
2811 ? 0x20 + (int) (opP->reg - DATA)
2812 : (get_num (&opP->disp, 40) & 0x1F));
2813 install_operand (s[1], tmpreg);
2817 tmpreg = get_num (&opP->disp, 10);
2820 install_operand (s[1], tmpreg);
2824 /* This depends on the fact that ADDR registers are eight
2825 more than their corresponding DATA regs, so the result
2826 will have the ADDR_REG bit set */
2827 install_operand (s[1], opP->reg - DATA);
2831 if (opP->mode == AINDR)
2832 install_operand (s[1], opP->reg - DATA);
2834 install_operand (s[1], opP->index.reg - DATA);
2838 if (opP->reg == FPI)
2840 else if (opP->reg == FPS)
2842 else if (opP->reg == FPC)
2846 install_operand (s[1], tmpreg);
2849 case 'S': /* Ignore it */
2853 install_operand (s[1], get_num (&opP->disp, 30));
2856 case 'U': /* Ignore it */
2875 as_fatal (_("failed sanity check"));
2876 } /* switch on cache token */
2877 install_operand (s[1], tmpreg);
2880 /* JF: These are out of order, I fear. */
2893 install_operand (s[1], tmpreg);
2919 install_operand (s[1], tmpreg);
2923 if (opP->reg == VAL)
2942 install_operand (s[1], tmpreg);
2956 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2967 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2973 install_operand (s[1], tmpreg);
2976 know (opP->reg == PSR);
2979 know (opP->reg == PCSR);
2994 install_operand (s[1], tmpreg);
2997 tmpreg = get_num (&opP->disp, 20);
2998 install_operand (s[1], tmpreg);
3000 case '_': /* used only for move16 absolute 32-bit address */
3001 if (isvar (&opP->disp))
3002 add_fix ('l', &opP->disp, 0, 0);
3003 tmpreg = get_num (&opP->disp, 80);
3004 addword (tmpreg >> 16);
3005 addword (tmpreg & 0xFFFF);
3008 install_operand (s[1], opP->reg - DATA0L);
3009 opP->reg -= (DATA0L);
3010 opP->reg &= 0x0F; /* remove upper/lower bit */
3017 /* By the time whe get here (FINALLY) the_ins contains the complete
3018 instruction, ready to be emitted. . . */
3022 reverse_16_bits (in)
3028 static int mask[16] =
3030 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3031 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3033 for (n = 0; n < 16; n++)
3036 out |= mask[15 - n];
3039 } /* reverse_16_bits() */
3048 static int mask[8] =
3050 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3053 for (n = 0; n < 8; n++)
3059 } /* reverse_8_bits() */
3061 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3062 (that value is chosen in the frag_var call in md_assemble). TYPE
3063 is the subtype of the frag to be generated; its primary type is
3064 rs_machine_dependent.
3066 The TYPE parameter is also used by md_convert_frag_1 and
3067 md_estimate_size_before_relax. The appropriate type of fixup will
3068 be emitted by md_convert_frag_1.
3070 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3072 install_operand (mode, val)
3079 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3082 the_ins.opcode[0] |= val << 9;
3085 the_ins.opcode[1] |= val << 12;
3088 the_ins.opcode[1] |= val << 6;
3091 the_ins.opcode[1] |= val;
3094 the_ins.opcode[2] |= val << 12;
3097 the_ins.opcode[2] |= val << 6;
3100 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3101 three words long! */
3103 the_ins.opcode[2] |= val;
3106 the_ins.opcode[1] |= val << 7;
3109 the_ins.opcode[1] |= val << 10;
3113 the_ins.opcode[1] |= val << 5;
3118 the_ins.opcode[1] |= (val << 10) | (val << 7);
3121 the_ins.opcode[1] |= (val << 12) | val;
3124 the_ins.opcode[0] |= val = 0xff;
3127 the_ins.opcode[0] |= val << 9;
3130 the_ins.opcode[1] |= val;
3133 the_ins.opcode[1] |= val;
3134 the_ins.numo++; /* What a hack */
3137 the_ins.opcode[1] |= val << 4;
3145 the_ins.opcode[0] |= (val << 6);
3148 the_ins.opcode[1] = (val >> 16);
3149 the_ins.opcode[2] = val & 0xffff;
3152 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3153 the_ins.opcode[0] |= ((val & 0x7) << 9);
3154 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3157 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3158 the_ins.opcode[0] |= ((val & 0x7) << 9);
3161 the_ins.opcode[1] |= val << 12;
3162 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3165 the_ins.opcode[0] |= (val & 0xF);
3166 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3169 the_ins.opcode[1] |= (val & 0xF);
3170 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3173 the_ins.opcode[1] |= ((val != 1) << 10);
3177 as_fatal (_("failed sanity check."));
3179 } /* install_operand() */
3182 install_gen_operand (mode, val)
3189 the_ins.opcode[0] |= val;
3192 /* This is a kludge!!! */
3193 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3202 the_ins.opcode[0] |= val;
3204 /* more stuff goes here */
3206 as_fatal (_("failed sanity check."));
3208 } /* install_gen_operand() */
3211 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3212 * then deal with the bitfield hack.
3216 crack_operand (str, opP)
3218 register struct m68k_op *opP;
3220 register int parens;
3222 register char *beg_str;
3230 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3236 else if (*str == ')')
3240 opP->error = _("Extra )");
3246 if (flag_mri && *str == '\'')
3247 inquote = ! inquote;
3249 if (!*str && parens)
3251 opP->error = _("Missing )");
3256 if (m68k_ip_op (beg_str, opP) != 0)
3263 c = *++str; /* JF bitfield hack */
3268 as_bad (_("Missing operand"));
3271 /* Detect MRI REG symbols and convert them to REGLSTs. */
3272 if (opP->mode == CONTROL && (int)opP->reg < 0)
3275 opP->mask = ~(int)opP->reg;
3282 /* This is the guts of the machine-dependent assembler. STR points to a
3283 machine dependent instruction. This function is supposed to emit
3284 the frags/bytes it assembles to.
3288 insert_reg (regname, regnum)
3289 const char *regname;
3295 #ifdef REGISTER_PREFIX
3296 if (!flag_reg_prefix_optional)
3298 buf[0] = REGISTER_PREFIX;
3299 strcpy (buf + 1, regname);
3304 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3305 &zero_address_frag));
3307 for (i = 0; regname[i]; i++)
3308 buf[i] = TOUPPER (regname[i]);
3311 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3312 &zero_address_frag));
3321 static const struct init_entry init_table[] =
3380 /* control registers */
3381 { "sfc", SFC }, /* Source Function Code */
3383 { "dfc", DFC }, /* Destination Function Code */
3385 { "cacr", CACR }, /* Cache Control Register */
3386 { "caar", CAAR }, /* Cache Address Register */
3388 { "usp", USP }, /* User Stack Pointer */
3389 { "vbr", VBR }, /* Vector Base Register */
3390 { "msp", MSP }, /* Master Stack Pointer */
3391 { "isp", ISP }, /* Interrupt Stack Pointer */
3393 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3394 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3395 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3396 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3398 /* 68ec040 versions of same */
3399 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3400 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3401 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3402 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3404 /* mcf5200 versions of same. The ColdFire programmer's reference
3405 manual indicated that the order is 2,3,0,1, but Ken Rose
3406 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3407 { "acr0", ITT0 }, /* Access Control Unit 0 */
3408 { "acr1", ITT1 }, /* Access Control Unit 1 */
3409 { "acr2", DTT0 }, /* Access Control Unit 2 */
3410 { "acr3", DTT1 }, /* Access Control Unit 3 */
3412 { "tc", TC }, /* MMU Translation Control Register */
3415 { "mmusr", MMUSR }, /* MMU Status Register */
3416 { "srp", SRP }, /* User Root Pointer */
3417 { "urp", URP }, /* Supervisor Root Pointer */
3422 { "rombar", ROMBAR }, /* ROM Base Address Register */
3423 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3424 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3425 { "mbar", MBAR }, /* Module Base Address Register */
3426 /* end of control registers */
3460 /* 68ec030 versions of same */
3463 /* 68ec030 access control unit, identical to 030 MMU status reg */
3466 /* Suppressed data and address registers. */
3484 /* Upper and lower data and address registers, used by macw and msacw. */
3528 for (i = 0; init_table[i].name; i++)
3529 insert_reg (init_table[i].name, init_table[i].number);
3532 static int no_68851, no_68881;
3535 /* a.out machine type. Default to 68020. */
3536 int m68k_aout_machtype = 2;
3548 int shorts_this_frag;
3551 /* In MRI mode, the instruction and operands are separated by a
3552 space. Anything following the operands is a comment. The label
3553 has already been removed. */
3561 for (s = str; *s != '\0'; s++)
3563 if ((*s == ' ' || *s == '\t') && ! inquote)
3581 inquote = ! inquote;
3586 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3591 for (n = 0; n < the_ins.numargs; n++)
3592 if (the_ins.operands[n].error)
3594 er = the_ins.operands[n].error;
3600 as_bad (_("%s -- statement `%s' ignored"), er, str);
3604 /* If there is a current label, record that it marks an instruction. */
3605 if (current_label != NULL)
3607 current_label->text = 1;
3608 current_label = NULL;
3612 /* Tie dwarf2 debug info to the address at the start of the insn. */
3613 dwarf2_emit_insn (0);
3616 if (the_ins.nfrag == 0)
3618 /* No frag hacking involved; just put it out */
3619 toP = frag_more (2 * the_ins.numo);
3620 fromP = &the_ins.opcode[0];
3621 for (m = the_ins.numo; m; --m)
3623 md_number_to_chars (toP, (long) (*fromP), 2);
3627 /* put out symbol-dependent info */
3628 for (m = 0; m < the_ins.nrel; m++)
3630 switch (the_ins.reloc[m].wid)
3649 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3650 the_ins.reloc[m].wid);
3653 fixP = fix_new_exp (frag_now,
3654 ((toP - frag_now->fr_literal)
3655 - the_ins.numo * 2 + the_ins.reloc[m].n),
3657 &the_ins.reloc[m].exp,
3658 the_ins.reloc[m].pcrel,
3659 get_reloc_code (n, the_ins.reloc[m].pcrel,
3660 the_ins.reloc[m].pic_reloc));
3661 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3662 if (the_ins.reloc[m].wid == 'B')
3663 fixP->fx_signed = 1;
3668 /* There's some frag hacking */
3670 /* Calculate the max frag size. */
3673 wid = 2 * the_ins.fragb[0].fragoff;
3674 for (n = 1; n < the_ins.nfrag; n++)
3675 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3676 /* frag_var part. */
3678 /* Make sure the whole insn fits in one chunk, in particular that
3679 the var part is attached, as we access one byte before the
3680 variable frag for byte branches. */
3684 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3689 wid = 2 * the_ins.fragb[n].fragoff;
3691 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3692 toP = frag_more (wid);
3694 shorts_this_frag = 0;
3695 for (m = wid / 2; m; --m)
3697 md_number_to_chars (toP, (long) (*fromP), 2);
3702 for (m = 0; m < the_ins.nrel; m++)
3704 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3706 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3709 wid = the_ins.reloc[m].wid;
3712 the_ins.reloc[m].wid = 0;
3713 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3715 fixP = fix_new_exp (frag_now,
3716 ((toP - frag_now->fr_literal)
3717 - the_ins.numo * 2 + the_ins.reloc[m].n),
3719 &the_ins.reloc[m].exp,
3720 the_ins.reloc[m].pcrel,
3721 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3722 the_ins.reloc[m].pic_reloc));
3723 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3725 (void) frag_var (rs_machine_dependent, 10, 0,
3726 (relax_substateT) (the_ins.fragb[n].fragty),
3727 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3729 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3730 shorts_this_frag = 0;
3733 toP = frag_more (n * sizeof (short));
3736 md_number_to_chars (toP, (long) (*fromP), 2);
3742 for (m = 0; m < the_ins.nrel; m++)
3746 wid = the_ins.reloc[m].wid;
3749 the_ins.reloc[m].wid = 0;
3750 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3752 fixP = fix_new_exp (frag_now,
3753 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3754 - shorts_this_frag * 2),
3756 &the_ins.reloc[m].exp,
3757 the_ins.reloc[m].pcrel,
3758 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3759 the_ins.reloc[m].pic_reloc));
3760 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3768 * md_begin -- set up hash tables with 68000 instructions.
3769 * similar to what the vax assembler does. ---phr
3771 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3772 a copy of it at runtime, adding in the information we want but isn't
3773 there. I think it'd be better to have an awk script hack the table
3774 at compile time. Or even just xstr the table and use it as-is. But
3775 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3778 const struct m68k_opcode *ins;
3779 struct m68k_incant *hack, *slak;
3780 const char *retval = 0; /* empty string, or error msg text */
3785 flag_reg_prefix_optional = 1;
3787 if (! m68k_rel32_from_cmdline)
3791 op_hash = hash_new ();
3793 obstack_begin (&robyn, 4000);
3794 for (i = 0; i < m68k_numopcodes; i++)
3796 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3799 ins = &m68k_opcodes[i];
3800 /* We *could* ignore insns that don't match our arch here
3801 but just leaving them out of the hash. */
3802 slak->m_operands = ins->args;
3803 slak->m_opnum = strlen (slak->m_operands) / 2;
3804 slak->m_arch = ins->arch;
3805 slak->m_opcode = ins->opcode;
3806 /* This is kludgey */
3807 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3808 if (i + 1 != m68k_numopcodes
3809 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3811 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3816 slak = slak->m_next;
3820 retval = hash_insert (op_hash, ins->name, (char *) hack);
3822 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3825 for (i = 0; i < m68k_numaliases; i++)
3827 const char *name = m68k_opcode_aliases[i].primary;
3828 const char *alias = m68k_opcode_aliases[i].alias;
3829 PTR val = hash_find (op_hash, name);
3831 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3832 retval = hash_insert (op_hash, alias, val);
3834 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3837 /* In MRI mode, all unsized branches are variable sized. Normally,
3838 they are word sized. */
3841 static struct m68k_opcode_alias mri_aliases[] =
3862 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3865 const char *name = mri_aliases[i].primary;
3866 const char *alias = mri_aliases[i].alias;
3867 PTR val = hash_find (op_hash, name);
3869 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3870 retval = hash_jam (op_hash, alias, val);
3872 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3876 for (i = 0; i < (int) sizeof (notend_table); i++)
3878 notend_table[i] = 0;
3879 alt_notend_table[i] = 0;
3881 notend_table[','] = 1;
3882 notend_table['{'] = 1;
3883 notend_table['}'] = 1;
3884 alt_notend_table['a'] = 1;
3885 alt_notend_table['A'] = 1;
3886 alt_notend_table['d'] = 1;
3887 alt_notend_table['D'] = 1;
3888 alt_notend_table['#'] = 1;
3889 alt_notend_table['&'] = 1;
3890 alt_notend_table['f'] = 1;
3891 alt_notend_table['F'] = 1;
3892 #ifdef REGISTER_PREFIX
3893 alt_notend_table[REGISTER_PREFIX] = 1;
3896 /* We need to put '(' in alt_notend_table to handle
3897 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3899 alt_notend_table['('] = 1;
3901 /* We need to put '@' in alt_notend_table to handle
3902 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3904 alt_notend_table['@'] = 1;
3906 /* We need to put digits in alt_notend_table to handle
3907 bfextu %d0{24:1},%d0
3909 alt_notend_table['0'] = 1;
3910 alt_notend_table['1'] = 1;
3911 alt_notend_table['2'] = 1;
3912 alt_notend_table['3'] = 1;
3913 alt_notend_table['4'] = 1;
3914 alt_notend_table['5'] = 1;
3915 alt_notend_table['6'] = 1;
3916 alt_notend_table['7'] = 1;
3917 alt_notend_table['8'] = 1;
3918 alt_notend_table['9'] = 1;
3920 #ifndef MIT_SYNTAX_ONLY
3921 /* Insert pseudo ops, these have to go into the opcode table since
3922 gas expects pseudo ops to start with a dot */
3925 while (mote_pseudo_table[n].poc_name)
3927 hack = (struct m68k_incant *)
3928 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3929 hash_insert (op_hash,
3930 mote_pseudo_table[n].poc_name, (char *) hack);
3931 hack->m_operands = 0;
3941 record_alignment (text_section, 2);
3942 record_alignment (data_section, 2);
3943 record_alignment (bss_section, 2);
3948 select_control_regs ()
3950 /* Note which set of "movec" control registers is available. */
3951 switch (cpu_of_arch (current_architecture))
3954 control_regs = m68000_control_regs;
3957 control_regs = m68010_control_regs;
3961 control_regs = m68020_control_regs;
3964 control_regs = m68040_control_regs;
3967 control_regs = m68060_control_regs;
3970 control_regs = cpu32_control_regs;
3976 control_regs = mcf_control_regs;
3984 m68k_init_after_args ()
3986 if (cpu_of_arch (current_architecture) == 0)
3989 const char *default_cpu = TARGET_CPU;
3991 if (*default_cpu == 'm')
3993 for (i = 0; i < n_archs; i++)
3994 if (strcasecmp (default_cpu, archs[i].name) == 0)
3998 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3999 current_architecture |= m68020;
4002 current_architecture |= archs[i].arch;
4004 /* Permit m68881 specification with all cpus; those that can't work
4005 with a coprocessor could be doing emulation. */
4006 if (current_architecture & m68851)
4008 if (current_architecture & m68040)
4010 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4013 /* What other incompatibilities could we check for? */
4015 /* Toss in some default assumptions about coprocessors. */
4017 && (cpu_of_arch (current_architecture)
4018 /* Can CPU32 have a 68881 coprocessor?? */
4019 & (m68020 | m68030 | cpu32)))
4021 current_architecture |= m68881;
4024 && (cpu_of_arch (current_architecture) & m68020up) != 0
4025 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4027 current_architecture |= m68851;
4029 if (no_68881 && (current_architecture & m68881))
4030 as_bad (_("options for 68881 and no-68881 both given"));
4031 if (no_68851 && (current_architecture & m68851))
4032 as_bad (_("options for 68851 and no-68851 both given"));
4035 /* Work out the magic number. This isn't very general. */
4036 if (current_architecture & m68000)
4037 m68k_aout_machtype = 0;
4038 else if (current_architecture & m68010)
4039 m68k_aout_machtype = 1;
4040 else if (current_architecture & m68020)
4041 m68k_aout_machtype = 2;
4043 m68k_aout_machtype = 2;
4046 /* Note which set of "movec" control registers is available. */
4047 select_control_regs ();
4049 if (cpu_of_arch (current_architecture) < m68020
4050 || arch_coldfire_p (current_architecture))
4051 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4054 /* This is called when a label is defined. */
4057 m68k_frob_label (sym)
4060 struct label_line *n;
4062 n = (struct label_line *) xmalloc (sizeof *n);
4065 as_where (&n->file, &n->line);
4071 /* This is called when a value that is not an instruction is emitted. */
4074 m68k_flush_pending_output ()
4076 current_label = NULL;
4079 /* This is called at the end of the assembly, when the final value of
4080 the label is known. We warn if this is a text symbol aligned at an
4084 m68k_frob_symbol (sym)
4087 if (S_GET_SEGMENT (sym) == reg_section
4088 && (int) S_GET_VALUE (sym) < 0)
4090 S_SET_SEGMENT (sym, absolute_section);
4091 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4093 else if ((S_GET_VALUE (sym) & 1) != 0)
4095 struct label_line *l;
4097 for (l = labels; l != NULL; l = l->next)
4099 if (l->label == sym)
4102 as_warn_where (l->file, l->line,
4103 _("text label `%s' aligned to odd boundary"),
4111 /* This is called if we go in or out of MRI mode because of the .mri
4115 m68k_mri_mode_change (on)
4120 if (! flag_reg_prefix_optional)
4122 flag_reg_prefix_optional = 1;
4123 #ifdef REGISTER_PREFIX
4128 if (! m68k_rel32_from_cmdline)
4133 if (! reg_prefix_optional_seen)
4135 #ifdef REGISTER_PREFIX_OPTIONAL
4136 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4138 flag_reg_prefix_optional = 0;
4140 #ifdef REGISTER_PREFIX
4145 if (! m68k_rel32_from_cmdline)
4150 /* Equal to MAX_PRECISION in atof-ieee.c */
4151 #define MAX_LITTLENUMS 6
4153 /* Turn a string in input_line_pointer into a floating point constant
4154 of type TYPE, and store the appropriate bytes in *LITP. The number
4155 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4156 returned, or NULL on OK. */
4159 md_atof (type, litP, sizeP)
4165 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4166 LITTLENUM_TYPE *wordP;
4197 return _("Bad call to MD_ATOF()");
4199 t = atof_ieee (input_line_pointer, type, words);
4201 input_line_pointer = t;
4203 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4204 for (wordP = words; prec--;)
4206 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4207 litP += sizeof (LITTLENUM_TYPE);
4213 md_number_to_chars (buf, val, n)
4218 number_to_chars_bigendian (buf, val, n);
4222 md_apply_fix3 (fixP, valP, seg)
4225 segT seg ATTRIBUTE_UNUSED;
4227 offsetT val = *valP;
4228 addressT upper_limit;
4229 offsetT lower_limit;
4231 /* This is unnecessary but it convinces the native rs6000 compiler
4232 to generate the code we want. */
4233 char *buf = fixP->fx_frag->fr_literal;
4234 buf += fixP->fx_where;
4235 /* end ibm compiler workaround */
4237 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4239 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4245 memset (buf, 0, fixP->fx_size);
4246 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4248 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4249 && !S_IS_DEFINED (fixP->fx_addsy)
4250 && !S_IS_WEAK (fixP->fx_addsy))
4251 S_SET_WEAK (fixP->fx_addsy);
4256 #ifdef BFD_ASSEMBLER
4257 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4258 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4262 switch (fixP->fx_size)
4264 /* The cast to offsetT below are necessary to make code
4265 correct for machines where ints are smaller than offsetT. */
4269 lower_limit = - (offsetT) 0x80;
4272 *buf++ = (val >> 8);
4274 upper_limit = 0x7fff;
4275 lower_limit = - (offsetT) 0x8000;
4278 *buf++ = (val >> 24);
4279 *buf++ = (val >> 16);
4280 *buf++ = (val >> 8);
4282 upper_limit = 0x7fffffff;
4283 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4286 BAD_CASE (fixP->fx_size);
4289 /* Fix up a negative reloc. */
4290 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4292 fixP->fx_addsy = fixP->fx_subsy;
4293 fixP->fx_subsy = NULL;
4297 /* For non-pc-relative values, it's conceivable we might get something
4298 like "0xff" for a byte field. So extend the upper part of the range
4299 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4300 so that we can do any range checking at all. */
4301 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4302 upper_limit = upper_limit * 2 + 1;
4304 if ((addressT) val > upper_limit
4305 && (val > 0 || val < lower_limit))
4306 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4308 /* A one byte PC-relative reloc means a short branch. We can't use
4309 a short branch with a value of 0 or -1, because those indicate
4310 different opcodes (branches with longer offsets). fixup_segment
4311 in write.c may have clobbered fx_pcrel, so we need to examine the
4314 #ifdef BFD_ASSEMBLER
4315 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4318 && fixP->fx_size == 1
4319 && (fixP->fx_addsy == NULL
4320 || S_IS_DEFINED (fixP->fx_addsy))
4321 && (val == 0 || val == -1))
4322 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4325 /* *fragP has been relaxed to its final size, and now needs to have
4326 the bytes inside it modified to conform to the new size There is UGLY
4330 md_convert_frag_1 (fragP)
4331 register fragS *fragP;
4336 /* Address in object code of the displacement. */
4337 register int object_address = fragP->fr_fix + fragP->fr_address;
4339 /* Address in gas core of the place to store the displacement. */
4340 /* This convinces the native rs6000 compiler to generate the code we
4342 register char *buffer_address = fragP->fr_literal;
4343 buffer_address += fragP->fr_fix;
4344 /* end ibm compiler workaround */
4346 /* The displacement of the address, from current location. */
4347 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4348 disp = (disp + fragP->fr_offset) - object_address;
4350 switch (fragP->fr_subtype)
4352 case TAB (BRANCHBWL, BYTE):
4353 case TAB (BRABSJUNC, BYTE):
4354 case TAB (BRABSJCOND, BYTE):
4355 case TAB (BRANCHBW, BYTE):
4356 know (issbyte (disp));
4358 as_bad_where (fragP->fr_file, fragP->fr_line,
4359 _("short branch with zero offset: use :w"));
4360 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4361 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4362 fixP->fx_pcrel_adjust = -1;
4364 case TAB (BRANCHBWL, SHORT):
4365 case TAB (BRABSJUNC, SHORT):
4366 case TAB (BRABSJCOND, SHORT):
4367 case TAB (BRANCHBW, SHORT):
4368 fragP->fr_opcode[1] = 0x00;
4369 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4370 1, RELAX_RELOC_PC16);
4373 case TAB (BRANCHBWL, LONG):
4374 fragP->fr_opcode[1] = (char) 0xFF;
4375 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4376 1, RELAX_RELOC_PC32);
4379 case TAB (BRABSJUNC, LONG):
4380 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4382 fragP->fr_opcode[0] = 0x4E;
4383 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4384 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4385 0, RELAX_RELOC_ABS32);
4388 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4390 fragP->fr_opcode[0] = 0x4E;
4391 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4392 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4393 0, RELAX_RELOC_ABS32);
4398 /* This cannot happen, because jbsr and jbra are the only two
4399 unconditional branches. */
4403 case TAB (BRABSJCOND, LONG):
4404 /* Only Bcc 68000 instructions can come here. */
4405 /* Change bcc into b!cc/jmp absl long. */
4407 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4408 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4410 /* JF: these used to be fr_opcode[2,3], but they may be in a
4411 different frag, in which case refering to them is a no-no.
4412 Only fr_opcode[0,1] are guaranteed to work. */
4413 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4414 *buffer_address++ = (char) 0xf9;
4415 fragP->fr_fix += 2; /* account for jmp instruction */
4416 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4417 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4420 case TAB (FBRANCH, SHORT):
4421 know ((fragP->fr_opcode[1] & 0x40) == 0);
4422 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4423 1, RELAX_RELOC_PC16);
4426 case TAB (FBRANCH, LONG):
4427 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4428 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4429 1, RELAX_RELOC_PC32);
4432 case TAB (DBCCLBR, SHORT):
4433 case TAB (DBCCABSJ, SHORT):
4434 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4435 1, RELAX_RELOC_PC16);
4438 case TAB (DBCCLBR, LONG):
4439 /* only DBcc instructions can come here */
4440 /* Change dbcc into dbcc/bral. */
4442 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4443 *buffer_address++ = 0x00; /* branch offset = 4 */
4444 *buffer_address++ = 0x04;
4445 *buffer_address++ = 0x60; /* put in bra pc+6 */
4446 *buffer_address++ = 0x06;
4447 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4448 *buffer_address++ = (char) 0xff;
4450 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4451 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4455 case TAB (DBCCABSJ, LONG):
4456 /* only DBcc instructions can come here */
4457 /* Change dbcc into dbcc/jmp. */
4459 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4460 *buffer_address++ = 0x00; /* branch offset = 4 */
4461 *buffer_address++ = 0x04;
4462 *buffer_address++ = 0x60; /* put in bra pc+6 */
4463 *buffer_address++ = 0x06;
4464 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4465 *buffer_address++ = (char) 0xf9;
4467 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4468 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4472 case TAB (PCREL1632, SHORT):
4473 fragP->fr_opcode[1] &= ~0x3F;
4474 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4475 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4476 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4479 case TAB (PCREL1632, LONG):
4480 /* Already set to mode 7.3; this indicates: PC indirect with
4481 suppressed index, 32-bit displacement. */
4482 *buffer_address++ = 0x01;
4483 *buffer_address++ = 0x70;
4485 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4486 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4487 fixP->fx_pcrel_adjust = 2;
4490 case TAB (PCINDEX, BYTE):
4491 assert (fragP->fr_fix >= 2);
4492 buffer_address[-2] &= ~1;
4493 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4494 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4495 fixP->fx_pcrel_adjust = 1;
4497 case TAB (PCINDEX, SHORT):
4498 assert (fragP->fr_fix >= 2);
4499 buffer_address[-2] |= 0x1;
4500 buffer_address[-1] = 0x20;
4501 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4502 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4503 fixP->fx_pcrel_adjust = 2;
4506 case TAB (PCINDEX, LONG):
4507 assert (fragP->fr_fix >= 2);
4508 buffer_address[-2] |= 0x1;
4509 buffer_address[-1] = 0x30;
4510 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4511 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4512 fixP->fx_pcrel_adjust = 2;
4515 case TAB (ABSTOPCREL, SHORT):
4516 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4517 1, RELAX_RELOC_PC16);
4520 case TAB (ABSTOPCREL, LONG):
4521 /* The thing to do here is force it to ABSOLUTE LONG, since
4522 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4523 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4525 fragP->fr_opcode[1] &= ~0x3F;
4526 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4527 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4528 0, RELAX_RELOC_ABS32);
4534 #ifndef BFD_ASSEMBLER
4537 md_convert_frag (headers, sec, fragP)
4538 object_headers *headers ATTRIBUTE_UNUSED;
4539 segT sec ATTRIBUTE_UNUSED;
4542 md_convert_frag_1 (fragP);
4548 md_convert_frag (abfd, sec, fragP)
4549 bfd *abfd ATTRIBUTE_UNUSED;
4550 segT sec ATTRIBUTE_UNUSED;
4553 md_convert_frag_1 (fragP);
4557 /* Force truly undefined symbols to their maximum size, and generally set up
4558 the frag list to be relaxed
4561 md_estimate_size_before_relax (fragP, segment)
4562 register fragS *fragP;
4565 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4566 switch (fragP->fr_subtype)
4568 case TAB (BRANCHBWL, SZ_UNDEF):
4569 case TAB (BRABSJUNC, SZ_UNDEF):
4570 case TAB (BRABSJCOND, SZ_UNDEF):
4572 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4573 && relaxable_symbol (fragP->fr_symbol))
4575 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4577 else if (flag_short_refs)
4579 /* Symbol is undefined and we want short ref. */
4580 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4584 /* Symbol is still undefined. Make it LONG. */
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4590 case TAB (BRANCHBW, SZ_UNDEF):
4592 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4593 && relaxable_symbol (fragP->fr_symbol))
4595 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4599 /* Symbol is undefined and we don't have long branches. */
4600 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4605 case TAB (FBRANCH, SZ_UNDEF):
4606 case TAB (DBCCLBR, SZ_UNDEF):
4607 case TAB (DBCCABSJ, SZ_UNDEF):
4608 case TAB (PCREL1632, SZ_UNDEF):
4610 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4611 && relaxable_symbol (fragP->fr_symbol))
4614 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4618 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4623 case TAB (PCINDEX, SZ_UNDEF):
4624 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4625 && relaxable_symbol (fragP->fr_symbol)))
4627 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4631 fragP->fr_subtype = TAB (PCINDEX, LONG);
4635 case TAB (ABSTOPCREL, SZ_UNDEF):
4637 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4638 && relaxable_symbol (fragP->fr_symbol)))
4640 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4644 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4653 /* Now that SZ_UNDEF are taken care of, check others. */
4654 switch (fragP->fr_subtype)
4656 case TAB (BRANCHBWL, BYTE):
4657 case TAB (BRABSJUNC, BYTE):
4658 case TAB (BRABSJCOND, BYTE):
4659 case TAB (BRANCHBW, BYTE):
4660 /* We can't do a short jump to the next instruction, so in that
4661 case we force word mode. If the symbol is at the start of a
4662 frag, and it is the next frag with any data in it (usually
4663 this is just the next frag, but assembler listings may
4664 introduce empty frags), we must use word mode. */
4665 if (fragP->fr_symbol)
4669 sym_frag = symbol_get_frag (fragP->fr_symbol);
4670 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4674 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4678 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4685 return md_relax_table[fragP->fr_subtype].rlx_length;
4688 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4689 /* the bit-field entries in the relocation_info struct plays hell
4690 with the byte-order problems of cross-assembly. So as a hack,
4691 I added this mach. dependent ri twiddler. Ugly, but it gets
4693 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4694 are symbolnum, most sig. byte first. Last byte is broken up with
4695 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4696 nibble as nuthin. (on Sun 3 at least) */
4697 /* Translate the internal relocation information into target-specific
4701 md_ri_to_chars (the_bytes, ri)
4703 struct reloc_info_generic *ri;
4706 md_number_to_chars (the_bytes, ri->r_address, 4);
4707 /* now the fun stuff */
4708 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4709 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4710 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4711 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4712 ((ri->r_extern << 4) & 0x10));
4715 #endif /* comment */
4717 #ifndef BFD_ASSEMBLER
4719 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4722 relax_addressT segment_address_in_file;
4725 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4726 * Out: GNU LD relocation length code: 0, 1, or 2.
4729 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4732 know (fixP->fx_addsy != NULL);
4734 md_number_to_chars (where,
4735 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4738 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4739 ? S_GET_TYPE (fixP->fx_addsy)
4740 : fixP->fx_addsy->sy_number);
4742 where[4] = (r_symbolnum >> 16) & 0x0ff;
4743 where[5] = (r_symbolnum >> 8) & 0x0ff;
4744 where[6] = r_symbolnum & 0x0ff;
4745 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4746 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4750 #endif /* OBJ_AOUT or OBJ_BOUT */
4752 #ifndef WORKING_DOT_WORD
4753 const int md_short_jump_size = 4;
4754 const int md_long_jump_size = 6;
4757 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4759 addressT from_addr, to_addr;
4760 fragS *frag ATTRIBUTE_UNUSED;
4761 symbolS *to_symbol ATTRIBUTE_UNUSED;
4765 offset = to_addr - (from_addr + 2);
4767 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4768 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4772 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4774 addressT from_addr, to_addr;
4780 if (!HAVE_LONG_BRANCH(current_architecture))
4782 offset = to_addr - S_GET_VALUE (to_symbol);
4783 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4784 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4785 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4790 offset = to_addr - (from_addr + 2);
4791 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4792 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4798 /* Different values of OK tell what its OK to return. Things that
4799 aren't OK are an error (what a shock, no?)
4802 10: Absolute 1:8 only
4803 20: Absolute 0:7 only
4804 30: absolute 0:15 only
4805 40: Absolute 0:31 only
4806 50: absolute 0:127 only
4807 55: absolute -64:63 only
4808 60: absolute -128:127 only
4809 70: absolute 0:4095 only
4816 struct m68k_exp *exp;
4819 if (exp->exp.X_op == O_absent)
4821 /* Do the same thing the VAX asm does */
4822 op (exp) = O_constant;
4828 as_warn (_("expression out of range: defaulting to 1"));
4832 else if (exp->exp.X_op == O_constant)
4837 if (offs (exp) < 1 || offs (exp) > 8)
4839 as_warn (_("expression out of range: defaulting to 1"));
4844 if (offs (exp) < 0 || offs (exp) > 7)
4848 if (offs (exp) < 0 || offs (exp) > 15)
4852 if (offs (exp) < 0 || offs (exp) > 32)
4856 if (offs (exp) < 0 || offs (exp) > 127)
4860 if (offs (exp) < -64 || offs (exp) > 63)
4864 if (offs (exp) < -128 || offs (exp) > 127)
4868 if (offs (exp) < 0 || offs (exp) > 4095)
4871 as_warn (_("expression out of range: defaulting to 0"));
4879 else if (exp->exp.X_op == O_big)
4881 if (offs (exp) <= 0 /* flonum */
4882 && (ok == 80 /* no bignums */
4883 || (ok > 10 /* small-int ranges including 0 ok */
4884 /* If we have a flonum zero, a zero integer should
4885 do as well (e.g., in moveq). */
4886 && generic_floating_point_number.exponent == 0
4887 && generic_floating_point_number.low[0] == 0)))
4889 /* HACK! Turn it into a long */
4890 LITTLENUM_TYPE words[6];
4892 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4893 op (exp) = O_constant;
4896 offs (exp) = words[1] | (words[0] << 16);
4900 op (exp) = O_constant;
4903 offs (exp) = (ok == 10) ? 1 : 0;
4904 as_warn (_("Can't deal with expression; defaulting to %ld"),
4910 if (ok >= 10 && ok <= 70)
4912 op (exp) = O_constant;
4915 offs (exp) = (ok == 10) ? 1 : 0;
4916 as_warn (_("Can't deal with expression; defaulting to %ld"),
4921 if (exp->size != SIZE_UNSPEC)
4929 if (!isbyte (offs (exp)))
4930 as_warn (_("expression doesn't fit in BYTE"));
4933 if (!isword (offs (exp)))
4934 as_warn (_("expression doesn't fit in WORD"));
4942 /* These are the back-ends for the various machine dependent pseudo-ops. */
4946 int ignore ATTRIBUTE_UNUSED;
4948 subseg_set (data_section, 1);
4949 demand_empty_rest_of_line ();
4954 int ignore ATTRIBUTE_UNUSED;
4956 subseg_set (data_section, 2);
4957 demand_empty_rest_of_line ();
4962 int ignore ATTRIBUTE_UNUSED;
4964 /* We don't support putting frags in the BSS segment, we fake it
4965 by marking in_bss, then looking at s_skip for clues. */
4967 subseg_set (bss_section, 0);
4968 demand_empty_rest_of_line ();
4973 int ignore ATTRIBUTE_UNUSED;
4976 register long temp_fill;
4978 temp = 1; /* JF should be 2? */
4979 temp_fill = get_absolute_expression ();
4980 if (!need_pass_2) /* Never make frag if expect extra pass. */
4981 frag_align (temp, (int) temp_fill, 0);
4982 demand_empty_rest_of_line ();
4983 record_alignment (now_seg, temp);
4988 int ignore ATTRIBUTE_UNUSED;
4990 demand_empty_rest_of_line ();
4993 /* Pseudo-ops handled for MRI compatibility. */
4995 /* This function returns non-zero if the argument is a conditional
4996 pseudo-op. This is called when checking whether a pending
4997 alignment is needed. */
5000 m68k_conditional_pseudoop (pop)
5003 return (pop->poc_handler == s_mri_if
5004 || pop->poc_handler == s_mri_else);
5007 /* Handle an MRI style chip specification. */
5016 s = input_line_pointer;
5017 /* We can't use get_symbol_end since the processor names are not proper
5019 while (is_part_of_name (c = *input_line_pointer++))
5021 *--input_line_pointer = 0;
5022 for (i = 0; i < n_archs; i++)
5023 if (strcasecmp (s, archs[i].name) == 0)
5027 as_bad (_("%s: unrecognized processor name"), s);
5028 *input_line_pointer = c;
5029 ignore_rest_of_line ();
5032 *input_line_pointer = c;
5034 if (*input_line_pointer == '/')
5035 current_architecture = 0;
5037 current_architecture &= m68881 | m68851;
5038 current_architecture |= archs[i].arch;
5040 while (*input_line_pointer == '/')
5042 ++input_line_pointer;
5043 s = input_line_pointer;
5044 /* We can't use get_symbol_end since the processor names are not
5046 while (is_part_of_name (c = *input_line_pointer++))
5048 *--input_line_pointer = 0;
5049 if (strcmp (s, "68881") == 0)
5050 current_architecture |= m68881;
5051 else if (strcmp (s, "68851") == 0)
5052 current_architecture |= m68851;
5053 *input_line_pointer = c;
5056 /* Update info about available control registers. */
5057 select_control_regs ();
5060 /* The MRI CHIP pseudo-op. */
5064 int ignore ATTRIBUTE_UNUSED;
5070 stop = mri_comment_field (&stopc);
5073 mri_comment_end (stop, stopc);
5074 demand_empty_rest_of_line ();
5077 /* The MRI FOPT pseudo-op. */
5081 int ignore ATTRIBUTE_UNUSED;
5085 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5089 input_line_pointer += 3;
5090 temp = get_absolute_expression ();
5091 if (temp < 0 || temp > 7)
5092 as_bad (_("bad coprocessor id"));
5094 m68k_float_copnum = COP0 + temp;
5098 as_bad (_("unrecognized fopt option"));
5099 ignore_rest_of_line ();
5103 demand_empty_rest_of_line ();
5106 /* The structure used to handle the MRI OPT pseudo-op. */
5110 /* The name of the option. */
5113 /* If this is not NULL, just call this function. The first argument
5114 is the ARG field of this structure, the second argument is
5115 whether the option was negated. */
5116 void (*pfn) PARAMS ((int arg, int on));
5118 /* If this is not NULL, and the PFN field is NULL, set the variable
5119 this points to. Set it to the ARG field if the option was not
5120 negated, and the NOTARG field otherwise. */
5123 /* The value to pass to PFN or to assign to *PVAR. */
5126 /* The value to assign to *PVAR if the option is negated. If PFN is
5127 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5128 the option may not be negated. */
5132 /* The table used to handle the MRI OPT pseudo-op. */
5134 static void skip_to_comma PARAMS ((int, int));
5135 static void opt_nest PARAMS ((int, int));
5136 static void opt_chip PARAMS ((int, int));
5137 static void opt_list PARAMS ((int, int));
5138 static void opt_list_symbols PARAMS ((int, int));
5140 static const struct opt_action opt_table[] =
5142 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5144 /* We do relaxing, so there is little use for these options. */
5145 { "b", 0, 0, 0, 0 },
5146 { "brs", 0, 0, 0, 0 },
5147 { "brb", 0, 0, 0, 0 },
5148 { "brl", 0, 0, 0, 0 },
5149 { "brw", 0, 0, 0, 0 },
5151 { "c", 0, 0, 0, 0 },
5152 { "cex", 0, 0, 0, 0 },
5153 { "case", 0, &symbols_case_sensitive, 1, 0 },
5154 { "cl", 0, 0, 0, 0 },
5155 { "cre", 0, 0, 0, 0 },
5156 { "d", 0, &flag_keep_locals, 1, 0 },
5157 { "e", 0, 0, 0, 0 },
5158 { "f", 0, &flag_short_refs, 1, 0 },
5159 { "frs", 0, &flag_short_refs, 1, 0 },
5160 { "frl", 0, &flag_short_refs, 0, 1 },
5161 { "g", 0, 0, 0, 0 },
5162 { "i", 0, 0, 0, 0 },
5163 { "m", 0, 0, 0, 0 },
5164 { "mex", 0, 0, 0, 0 },
5165 { "mc", 0, 0, 0, 0 },
5166 { "md", 0, 0, 0, 0 },
5167 { "nest", opt_nest, 0, 0, 0 },
5168 { "next", skip_to_comma, 0, 0, 0 },
5169 { "o", 0, 0, 0, 0 },
5170 { "old", 0, 0, 0, 0 },
5171 { "op", skip_to_comma, 0, 0, 0 },
5172 { "pco", 0, 0, 0, 0 },
5173 { "p", opt_chip, 0, 0, 0 },
5174 { "pcr", 0, 0, 0, 0 },
5175 { "pcs", 0, 0, 0, 0 },
5176 { "r", 0, 0, 0, 0 },
5177 { "quick", 0, &m68k_quick, 1, 0 },
5178 { "rel32", 0, &m68k_rel32, 1, 0 },
5179 { "s", opt_list, 0, 0, 0 },
5180 { "t", opt_list_symbols, 0, 0, 0 },
5181 { "w", 0, &flag_no_warnings, 0, 1 },
5185 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5187 /* The MRI OPT pseudo-op. */
5191 int ignore ATTRIBUTE_UNUSED;
5199 const struct opt_action *o;
5204 if (*input_line_pointer == '-')
5206 ++input_line_pointer;
5209 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5211 input_line_pointer += 2;
5215 s = input_line_pointer;
5216 c = get_symbol_end ();
5218 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5220 if (strcasecmp (s, o->name) == 0)
5224 /* Restore input_line_pointer now in case the option
5226 *input_line_pointer = c;
5227 (*o->pfn) (o->arg, t);
5229 else if (o->pvar != NULL)
5231 if (! t && o->arg == o->notarg)
5232 as_bad (_("option `%s' may not be negated"), s);
5233 *input_line_pointer = c;
5234 *o->pvar = t ? o->arg : o->notarg;
5237 *input_line_pointer = c;
5243 as_bad (_("option `%s' not recognized"), s);
5244 *input_line_pointer = c;
5247 while (*input_line_pointer++ == ',');
5249 /* Move back to terminating character. */
5250 --input_line_pointer;
5251 demand_empty_rest_of_line ();
5254 /* Skip ahead to a comma. This is used for OPT options which we do
5255 not suppor tand which take arguments. */
5258 skip_to_comma (arg, on)
5259 int arg ATTRIBUTE_UNUSED;
5260 int on ATTRIBUTE_UNUSED;
5262 while (*input_line_pointer != ','
5263 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5264 ++input_line_pointer;
5267 /* Handle the OPT NEST=depth option. */
5271 int arg ATTRIBUTE_UNUSED;
5272 int on ATTRIBUTE_UNUSED;
5274 if (*input_line_pointer != '=')
5276 as_bad (_("bad format of OPT NEST=depth"));
5280 ++input_line_pointer;
5281 max_macro_nest = get_absolute_expression ();
5284 /* Handle the OPT P=chip option. */
5288 int arg ATTRIBUTE_UNUSED;
5289 int on ATTRIBUTE_UNUSED;
5291 if (*input_line_pointer != '=')
5293 /* This is just OPT P, which we do not support. */
5297 ++input_line_pointer;
5301 /* Handle the OPT S option. */
5305 int arg ATTRIBUTE_UNUSED;
5311 /* Handle the OPT T option. */
5314 opt_list_symbols (arg, on)
5315 int arg ATTRIBUTE_UNUSED;
5319 listing |= LISTING_SYMBOLS;
5321 listing &= ~LISTING_SYMBOLS;
5324 /* Handle the MRI REG pseudo-op. */
5328 int ignore ATTRIBUTE_UNUSED;
5337 if (line_label == NULL)
5339 as_bad (_("missing label"));
5340 ignore_rest_of_line ();
5345 stop = mri_comment_field (&stopc);
5349 s = input_line_pointer;
5350 while (ISALNUM (*input_line_pointer)
5351 #ifdef REGISTER_PREFIX
5352 || *input_line_pointer == REGISTER_PREFIX
5354 || *input_line_pointer == '/'
5355 || *input_line_pointer == '-')
5356 ++input_line_pointer;
5357 c = *input_line_pointer;
5358 *input_line_pointer = '\0';
5360 if (m68k_ip_op (s, &rop) != 0)
5362 if (rop.error == NULL)
5363 as_bad (_("bad register list"));
5365 as_bad (_("bad register list: %s"), rop.error);
5366 *input_line_pointer = c;
5367 ignore_rest_of_line ();
5371 *input_line_pointer = c;
5373 if (rop.mode == REGLST)
5375 else if (rop.mode == DREG)
5376 mask = 1 << (rop.reg - DATA0);
5377 else if (rop.mode == AREG)
5378 mask = 1 << (rop.reg - ADDR0 + 8);
5379 else if (rop.mode == FPREG)
5380 mask = 1 << (rop.reg - FP0 + 16);
5381 else if (rop.mode == CONTROL
5384 else if (rop.mode == CONTROL
5387 else if (rop.mode == CONTROL
5392 as_bad (_("bad register list"));
5393 ignore_rest_of_line ();
5397 S_SET_SEGMENT (line_label, reg_section);
5398 S_SET_VALUE (line_label, ~mask);
5399 symbol_set_frag (line_label, &zero_address_frag);
5402 mri_comment_end (stop, stopc);
5404 demand_empty_rest_of_line ();
5407 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5411 struct save_opts *next;
5413 int symbols_case_sensitive;
5421 /* FIXME: We don't save OPT S. */
5424 /* This variable holds the stack of saved options. */
5426 static struct save_opts *save_stack;
5428 /* The MRI SAVE pseudo-op. */
5432 int ignore ATTRIBUTE_UNUSED;
5434 struct save_opts *s;
5436 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5437 s->abspcadd = m68k_abspcadd;
5438 s->symbols_case_sensitive = symbols_case_sensitive;
5439 s->keep_locals = flag_keep_locals;
5440 s->short_refs = flag_short_refs;
5441 s->architecture = current_architecture;
5442 s->quick = m68k_quick;
5443 s->rel32 = m68k_rel32;
5444 s->listing = listing;
5445 s->no_warnings = flag_no_warnings;
5447 s->next = save_stack;
5450 demand_empty_rest_of_line ();
5453 /* The MRI RESTORE pseudo-op. */
5457 int ignore ATTRIBUTE_UNUSED;
5459 struct save_opts *s;
5461 if (save_stack == NULL)
5463 as_bad (_("restore without save"));
5464 ignore_rest_of_line ();
5469 save_stack = s->next;
5471 m68k_abspcadd = s->abspcadd;
5472 symbols_case_sensitive = s->symbols_case_sensitive;
5473 flag_keep_locals = s->keep_locals;
5474 flag_short_refs = s->short_refs;
5475 current_architecture = s->architecture;
5476 m68k_quick = s->quick;
5477 m68k_rel32 = s->rel32;
5478 listing = s->listing;
5479 flag_no_warnings = s->no_warnings;
5483 demand_empty_rest_of_line ();
5486 /* Types of MRI structured control directives. */
5488 enum mri_control_type
5496 /* This structure is used to stack the MRI structured control
5499 struct mri_control_info
5501 /* The directive within which this one is enclosed. */
5502 struct mri_control_info *outer;
5504 /* The type of directive. */
5505 enum mri_control_type type;
5507 /* Whether an ELSE has been in an IF. */
5510 /* The add or sub statement at the end of a FOR. */
5513 /* The label of the top of a FOR or REPEAT loop. */
5516 /* The label to jump to for the next iteration, or the else
5517 expression of a conditional. */
5520 /* The label to jump to to break out of the loop, or the label past
5521 the end of a conditional. */
5525 /* The stack of MRI structured control directives. */
5527 static struct mri_control_info *mri_control_stack;
5529 /* The current MRI structured control directive index number, used to
5530 generate label names. */
5532 static int mri_control_index;
5534 /* Some function prototypes. */
5536 static void mri_assemble PARAMS ((char *));
5537 static char *mri_control_label PARAMS ((void));
5538 static struct mri_control_info *push_mri_control
5539 PARAMS ((enum mri_control_type));
5540 static void pop_mri_control PARAMS ((void));
5541 static int parse_mri_condition PARAMS ((int *));
5542 static int parse_mri_control_operand
5543 PARAMS ((int *, char **, char **, char **, char **));
5544 static int swap_mri_condition PARAMS ((int));
5545 static int reverse_mri_condition PARAMS ((int));
5546 static void build_mri_control_operand
5547 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5548 const char *, int));
5549 static void parse_mri_control_expression
5550 PARAMS ((char *, int, const char *, const char *, int));
5552 /* Assemble an instruction for an MRI structured control directive. */
5560 /* md_assemble expects the opcode to be in lower case. */
5561 for (s = str; *s != ' ' && *s != '\0'; s++)
5567 /* Generate a new MRI label structured control directive label name. */
5570 mri_control_label ()
5574 n = (char *) xmalloc (20);
5575 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5576 ++mri_control_index;
5580 /* Create a new MRI structured control directive. */
5582 static struct mri_control_info *
5583 push_mri_control (type)
5584 enum mri_control_type type;
5586 struct mri_control_info *n;
5588 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5592 if (type == mri_if || type == mri_while)
5595 n->top = mri_control_label ();
5596 n->next = mri_control_label ();
5597 n->bottom = mri_control_label ();
5599 n->outer = mri_control_stack;
5600 mri_control_stack = n;
5605 /* Pop off the stack of MRI structured control directives. */
5610 struct mri_control_info *n;
5612 n = mri_control_stack;
5613 mri_control_stack = n->outer;
5621 /* Recognize a condition code in an MRI structured control expression. */
5624 parse_mri_condition (pcc)
5629 know (*input_line_pointer == '<');
5631 ++input_line_pointer;
5632 c1 = *input_line_pointer++;
5633 c2 = *input_line_pointer++;
5635 if (*input_line_pointer != '>')
5637 as_bad (_("syntax error in structured control directive"));
5641 ++input_line_pointer;
5647 *pcc = (c1 << 8) | c2;
5652 /* Parse a single operand in an MRI structured control expression. */
5655 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5672 if (*input_line_pointer == '<')
5674 /* It's just a condition code. */
5675 return parse_mri_condition (pcc);
5678 /* Look ahead for the condition code. */
5679 for (s = input_line_pointer; *s != '\0'; ++s)
5681 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5686 as_bad (_("missing condition code in structured control directive"));
5690 *leftstart = input_line_pointer;
5692 if (*leftstop > *leftstart
5693 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5696 input_line_pointer = s;
5697 if (! parse_mri_condition (pcc))
5700 /* Look ahead for AND or OR or end of line. */
5701 for (s = input_line_pointer; *s != '\0'; ++s)
5703 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5704 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5706 if ((s == input_line_pointer
5709 && ((strncasecmp (s, "AND", 3) == 0
5710 && (s[3] == '.' || ! is_part_of_name (s[3])))
5711 || (strncasecmp (s, "OR", 2) == 0
5712 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5716 *rightstart = input_line_pointer;
5718 if (*rightstop > *rightstart
5719 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5722 input_line_pointer = s;
5727 #define MCC(b1, b2) (((b1) << 8) | (b2))
5729 /* Swap the sense of a condition. This changes the condition so that
5730 it generates the same result when the operands are swapped. */
5733 swap_mri_condition (cc)
5738 case MCC ('h', 'i'): return MCC ('c', 's');
5739 case MCC ('l', 's'): return MCC ('c', 'c');
5740 /* <HS> is an alias for <CC> */
5741 case MCC ('h', 's'):
5742 case MCC ('c', 'c'): return MCC ('l', 's');
5743 /* <LO> is an alias for <CS> */
5744 case MCC ('l', 'o'):
5745 case MCC ('c', 's'): return MCC ('h', 'i');
5746 case MCC ('p', 'l'): return MCC ('m', 'i');
5747 case MCC ('m', 'i'): return MCC ('p', 'l');
5748 case MCC ('g', 'e'): return MCC ('l', 'e');
5749 case MCC ('l', 't'): return MCC ('g', 't');
5750 case MCC ('g', 't'): return MCC ('l', 't');
5751 case MCC ('l', 'e'): return MCC ('g', 'e');
5752 /* issue a warning for conditions we can not swap */
5753 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5754 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5755 case MCC ('v', 'c'):
5756 case MCC ('v', 's'):
5758 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5759 (char) (cc >> 8), (char) (cc));
5765 /* Reverse the sense of a condition. */
5768 reverse_mri_condition (cc)
5773 case MCC ('h', 'i'): return MCC ('l', 's');
5774 case MCC ('l', 's'): return MCC ('h', 'i');
5775 /* <HS> is an alias for <CC> */
5776 case MCC ('h', 's'): return MCC ('l', 'o');
5777 case MCC ('c', 'c'): return MCC ('c', 's');
5778 /* <LO> is an alias for <CS> */
5779 case MCC ('l', 'o'): return MCC ('h', 's');
5780 case MCC ('c', 's'): return MCC ('c', 'c');
5781 case MCC ('n', 'e'): return MCC ('e', 'q');
5782 case MCC ('e', 'q'): return MCC ('n', 'e');
5783 case MCC ('v', 'c'): return MCC ('v', 's');
5784 case MCC ('v', 's'): return MCC ('v', 'c');
5785 case MCC ('p', 'l'): return MCC ('m', 'i');
5786 case MCC ('m', 'i'): return MCC ('p', 'l');
5787 case MCC ('g', 'e'): return MCC ('l', 't');
5788 case MCC ('l', 't'): return MCC ('g', 'e');
5789 case MCC ('g', 't'): return MCC ('l', 'e');
5790 case MCC ('l', 'e'): return MCC ('g', 't');
5795 /* Build an MRI structured control expression. This generates test
5796 and branch instructions. It goes to TRUELAB if the condition is
5797 true, and to FALSELAB if the condition is false. Exactly one of
5798 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5799 is the size qualifier for the expression. EXTENT is the size to
5800 use for the branch. */
5803 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5804 rightstop, truelab, falselab, extent)
5811 const char *truelab;
5812 const char *falselab;
5818 if (leftstart != NULL)
5820 struct m68k_op leftop, rightop;
5823 /* Swap the compare operands, if necessary, to produce a legal
5824 m68k compare instruction. Comparing a register operand with
5825 a non-register operand requires the register to be on the
5826 right (cmp, cmpa). Comparing an immediate value with
5827 anything requires the immediate value to be on the left
5832 (void) m68k_ip_op (leftstart, &leftop);
5837 (void) m68k_ip_op (rightstart, &rightop);
5840 if (rightop.mode == IMMED
5841 || ((leftop.mode == DREG || leftop.mode == AREG)
5842 && (rightop.mode != DREG && rightop.mode != AREG)))
5846 /* Correct conditional handling:
5847 if #1 <lt> d0 then ;means if (1 < d0)
5853 cmp #1,d0 if we do *not* swap the operands
5854 bgt true we need the swapped condition!
5861 leftstart = rightstart;
5864 leftstop = rightstop;
5869 cc = swap_mri_condition (cc);
5873 if (truelab == NULL)
5875 cc = reverse_mri_condition (cc);
5879 if (leftstart != NULL)
5881 buf = (char *) xmalloc (20
5882 + (leftstop - leftstart)
5883 + (rightstop - rightstart));
5889 *s++ = TOLOWER (qual);
5891 memcpy (s, leftstart, leftstop - leftstart);
5892 s += leftstop - leftstart;
5894 memcpy (s, rightstart, rightstop - rightstart);
5895 s += rightstop - rightstart;
5901 buf = (char *) xmalloc (20 + strlen (truelab));
5907 *s++ = TOLOWER (extent);
5909 strcpy (s, truelab);
5914 /* Parse an MRI structured control expression. This generates test
5915 and branch instructions. STOP is where the expression ends. It
5916 goes to TRUELAB if the condition is true, and to FALSELAB if the
5917 condition is false. Exactly one of TRUELAB and FALSELAB will be
5918 NULL, meaning to fall through. QUAL is the size qualifier for the
5919 expression. EXTENT is the size to use for the branch. */
5922 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5925 const char *truelab;
5926 const char *falselab;
5939 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5940 &rightstart, &rightstop))
5946 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5950 if (falselab != NULL)
5953 flab = mri_control_label ();
5955 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5956 rightstop, (const char *) NULL, flab, extent);
5958 input_line_pointer += 3;
5959 if (*input_line_pointer != '.'
5960 || input_line_pointer[1] == '\0')
5964 qual = input_line_pointer[1];
5965 input_line_pointer += 2;
5968 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5969 &rightstart, &rightstop))
5975 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5976 rightstop, truelab, falselab, extent);
5978 if (falselab == NULL)
5981 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5985 if (truelab != NULL)
5988 tlab = mri_control_label ();
5990 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5991 rightstop, tlab, (const char *) NULL, extent);
5993 input_line_pointer += 2;
5994 if (*input_line_pointer != '.'
5995 || input_line_pointer[1] == '\0')
5999 qual = input_line_pointer[1];
6000 input_line_pointer += 2;
6003 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6004 &rightstart, &rightstop))
6010 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6011 rightstop, truelab, falselab, extent);
6013 if (truelab == NULL)
6018 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6019 rightstop, truelab, falselab, extent);
6023 if (input_line_pointer != stop)
6024 as_bad (_("syntax error in structured control directive"));
6027 /* Handle the MRI IF pseudo-op. This may be a structured control
6028 directive, or it may be a regular assembler conditional, depending
6037 struct mri_control_info *n;
6039 /* A structured control directive must end with THEN with an
6040 optional qualifier. */
6041 s = input_line_pointer;
6042 /* We only accept '*' as introduction of comments if preceded by white space
6043 or at first column of a line (I think this can't actually happen here?)
6044 This is important when assembling:
6045 if d0 <ne> 12(a0,d0*2) then
6046 if d0 <ne> #CONST*20 then */
6047 while ( ! ( is_end_of_line[(unsigned char) *s]
6050 && ( s == input_line_pointer
6052 || *(s-1) == '\t'))))
6055 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6058 if (s - input_line_pointer > 1
6062 if (s - input_line_pointer < 3
6063 || strncasecmp (s - 3, "THEN", 4) != 0)
6067 as_bad (_("missing then"));
6068 ignore_rest_of_line ();
6072 /* It's a conditional. */
6077 /* Since this might be a conditional if, this pseudo-op will be
6078 called even if we are supported to be ignoring input. Double
6079 check now. Clobber *input_line_pointer so that ignore_input
6080 thinks that this is not a special pseudo-op. */
6081 c = *input_line_pointer;
6082 *input_line_pointer = 0;
6083 if (ignore_input ())
6085 *input_line_pointer = c;
6086 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6087 ++input_line_pointer;
6088 demand_empty_rest_of_line ();
6091 *input_line_pointer = c;
6093 n = push_mri_control (mri_if);
6095 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6096 n->next, s[1] == '.' ? s[2] : '\0');
6099 input_line_pointer = s + 3;
6101 input_line_pointer = s + 1;
6105 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6106 ++input_line_pointer;
6109 demand_empty_rest_of_line ();
6112 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6113 structured IF, associate the ELSE with the IF. Otherwise, assume
6114 it is a conditional else. */
6125 && (mri_control_stack == NULL
6126 || mri_control_stack->type != mri_if
6127 || mri_control_stack->else_seen))
6133 c = *input_line_pointer;
6134 *input_line_pointer = 0;
6135 if (ignore_input ())
6137 *input_line_pointer = c;
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6140 demand_empty_rest_of_line ();
6143 *input_line_pointer = c;
6145 if (mri_control_stack == NULL
6146 || mri_control_stack->type != mri_if
6147 || mri_control_stack->else_seen)
6149 as_bad (_("else without matching if"));
6150 ignore_rest_of_line ();
6154 mri_control_stack->else_seen = 1;
6156 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6157 q[0] = TOLOWER (qual);
6159 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6163 colon (mri_control_stack->next);
6167 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6168 ++input_line_pointer;
6171 demand_empty_rest_of_line ();
6174 /* Handle the MRI ENDI pseudo-op. */
6178 int ignore ATTRIBUTE_UNUSED;
6180 if (mri_control_stack == NULL
6181 || mri_control_stack->type != mri_if)
6183 as_bad (_("endi without matching if"));
6184 ignore_rest_of_line ();
6188 /* ignore_input will not return true for ENDI, so we don't need to
6189 worry about checking it again here. */
6191 if (! mri_control_stack->else_seen)
6192 colon (mri_control_stack->next);
6193 colon (mri_control_stack->bottom);
6199 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6200 ++input_line_pointer;
6203 demand_empty_rest_of_line ();
6206 /* Handle the MRI BREAK pseudo-op. */
6209 s_mri_break (extent)
6212 struct mri_control_info *n;
6216 n = mri_control_stack;
6218 && n->type != mri_for
6219 && n->type != mri_repeat
6220 && n->type != mri_while)
6224 as_bad (_("break outside of structured loop"));
6225 ignore_rest_of_line ();
6229 buf = (char *) xmalloc (20 + strlen (n->bottom));
6230 ex[0] = TOLOWER (extent);
6232 sprintf (buf, "bra%s %s", ex, n->bottom);
6238 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6239 ++input_line_pointer;
6242 demand_empty_rest_of_line ();
6245 /* Handle the MRI NEXT pseudo-op. */
6251 struct mri_control_info *n;
6255 n = mri_control_stack;
6257 && n->type != mri_for
6258 && n->type != mri_repeat
6259 && n->type != mri_while)
6263 as_bad (_("next outside of structured loop"));
6264 ignore_rest_of_line ();
6268 buf = (char *) xmalloc (20 + strlen (n->next));
6269 ex[0] = TOLOWER (extent);
6271 sprintf (buf, "bra%s %s", ex, n->next);
6277 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6278 ++input_line_pointer;
6281 demand_empty_rest_of_line ();
6284 /* Handle the MRI FOR pseudo-op. */
6290 const char *varstart, *varstop;
6291 const char *initstart, *initstop;
6292 const char *endstart, *endstop;
6293 const char *bystart, *bystop;
6297 struct mri_control_info *n;
6303 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6307 varstart = input_line_pointer;
6309 /* Look for the '='. */
6310 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6311 && *input_line_pointer != '=')
6312 ++input_line_pointer;
6313 if (*input_line_pointer != '=')
6315 as_bad (_("missing ="));
6316 ignore_rest_of_line ();
6320 varstop = input_line_pointer;
6321 if (varstop > varstart
6322 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6325 ++input_line_pointer;
6327 initstart = input_line_pointer;
6329 /* Look for TO or DOWNTO. */
6332 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6334 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6335 && ! is_part_of_name (input_line_pointer[2]))
6337 initstop = input_line_pointer;
6338 input_line_pointer += 2;
6341 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6342 && ! is_part_of_name (input_line_pointer[6]))
6344 initstop = input_line_pointer;
6346 input_line_pointer += 6;
6349 ++input_line_pointer;
6351 if (initstop == NULL)
6353 as_bad (_("missing to or downto"));
6354 ignore_rest_of_line ();
6357 if (initstop > initstart
6358 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6362 endstart = input_line_pointer;
6364 /* Look for BY or DO. */
6367 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6369 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6370 && ! is_part_of_name (input_line_pointer[2]))
6372 endstop = input_line_pointer;
6374 input_line_pointer += 2;
6377 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6378 && (input_line_pointer[2] == '.'
6379 || ! is_part_of_name (input_line_pointer[2])))
6381 endstop = input_line_pointer;
6382 input_line_pointer += 2;
6385 ++input_line_pointer;
6387 if (endstop == NULL)
6389 as_bad (_("missing do"));
6390 ignore_rest_of_line ();
6393 if (endstop > endstart
6394 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6400 bystop = bystart + 2;
6405 bystart = input_line_pointer;
6409 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6411 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6412 && (input_line_pointer[2] == '.'
6413 || ! is_part_of_name (input_line_pointer[2])))
6415 bystop = input_line_pointer;
6416 input_line_pointer += 2;
6419 ++input_line_pointer;
6423 as_bad (_("missing do"));
6424 ignore_rest_of_line ();
6427 if (bystop > bystart
6428 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6432 if (*input_line_pointer != '.')
6436 extent = input_line_pointer[1];
6437 input_line_pointer += 2;
6440 /* We have fully parsed the FOR operands. Now build the loop. */
6442 n = push_mri_control (mri_for);
6444 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6453 *s++ = TOLOWER (qual);
6455 memcpy (s, initstart, initstop - initstart);
6456 s += initstop - initstart;
6458 memcpy (s, varstart, varstop - varstart);
6459 s += varstop - varstart;
6471 *s++ = TOLOWER (qual);
6473 memcpy (s, endstart, endstop - endstart);
6474 s += endstop - endstart;
6476 memcpy (s, varstart, varstop - varstart);
6477 s += varstop - varstart;
6482 ex[0] = TOLOWER (extent);
6485 sprintf (buf, "blt%s %s", ex, n->bottom);
6487 sprintf (buf, "bgt%s %s", ex, n->bottom);
6490 /* Put together the add or sub instruction used by ENDF. */
6498 *s++ = TOLOWER (qual);
6500 memcpy (s, bystart, bystop - bystart);
6501 s += bystop - bystart;
6503 memcpy (s, varstart, varstop - varstart);
6504 s += varstop - varstart;
6510 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6511 ++input_line_pointer;
6514 demand_empty_rest_of_line ();
6517 /* Handle the MRI ENDF pseudo-op. */
6521 int ignore ATTRIBUTE_UNUSED;
6523 if (mri_control_stack == NULL
6524 || mri_control_stack->type != mri_for)
6526 as_bad (_("endf without for"));
6527 ignore_rest_of_line ();
6531 colon (mri_control_stack->next);
6533 mri_assemble (mri_control_stack->incr);
6535 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6536 mri_assemble (mri_control_stack->incr);
6538 free (mri_control_stack->incr);
6540 colon (mri_control_stack->bottom);
6546 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6547 ++input_line_pointer;
6550 demand_empty_rest_of_line ();
6553 /* Handle the MRI REPEAT pseudo-op. */
6556 s_mri_repeat (ignore)
6557 int ignore ATTRIBUTE_UNUSED;
6559 struct mri_control_info *n;
6561 n = push_mri_control (mri_repeat);
6565 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6566 ++input_line_pointer;
6568 demand_empty_rest_of_line ();
6571 /* Handle the MRI UNTIL pseudo-op. */
6579 if (mri_control_stack == NULL
6580 || mri_control_stack->type != mri_repeat)
6582 as_bad (_("until without repeat"));
6583 ignore_rest_of_line ();
6587 colon (mri_control_stack->next);
6589 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6592 parse_mri_control_expression (s, qual, (const char *) NULL,
6593 mri_control_stack->top, '\0');
6595 colon (mri_control_stack->bottom);
6597 input_line_pointer = s;
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6604 ++input_line_pointer;
6607 demand_empty_rest_of_line ();
6610 /* Handle the MRI WHILE pseudo-op. */
6618 struct mri_control_info *n;
6620 s = input_line_pointer;
6621 /* We only accept '*' as introduction of comments if preceded by white space
6622 or at first column of a line (I think this can't actually happen here?)
6623 This is important when assembling:
6624 while d0 <ne> 12(a0,d0*2) do
6625 while d0 <ne> #CONST*20 do */
6626 while (! (is_end_of_line[(unsigned char) *s]
6629 && (s == input_line_pointer
6631 || *(s-1) == '\t'))))
6634 while (*s == ' ' || *s == '\t')
6636 if (s - input_line_pointer > 1
6639 if (s - input_line_pointer < 2
6640 || strncasecmp (s - 1, "DO", 2) != 0)
6642 as_bad (_("missing do"));
6643 ignore_rest_of_line ();
6647 n = push_mri_control (mri_while);
6651 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6652 s[1] == '.' ? s[2] : '\0');
6654 input_line_pointer = s + 1;
6655 if (*input_line_pointer == '.')
6656 input_line_pointer += 2;
6660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6661 ++input_line_pointer;
6664 demand_empty_rest_of_line ();
6667 /* Handle the MRI ENDW pseudo-op. */
6671 int ignore ATTRIBUTE_UNUSED;
6675 if (mri_control_stack == NULL
6676 || mri_control_stack->type != mri_while)
6678 as_bad (_("endw without while"));
6679 ignore_rest_of_line ();
6683 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6684 sprintf (buf, "bra %s", mri_control_stack->next);
6688 colon (mri_control_stack->bottom);
6694 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6695 ++input_line_pointer;
6698 demand_empty_rest_of_line ();
6703 * Invocation line includes a switch not recognized by the base assembler.
6704 * See if it's a processor-specific option. These are:
6706 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6707 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6708 * Select the architecture. Instructions or features not
6709 * supported by the selected architecture cause fatal
6710 * errors. More than one may be specified. The default is
6711 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6712 * for -m68000, and -m68882 is a synonym for -m68881.
6713 * -[A]m[c]no-68851, -[A]m[c]no-68881
6714 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6715 * so don't use or document it, but that's the way the parsing
6718 * -pic Indicates PIC.
6719 * -k Indicates PIC. (Sun 3 only.)
6720 * --pcrel Never turn PC-relative branches into absolute jumps.
6723 * Permit `|' to be used in expressions.
6728 const char *md_shortopts = "lSA:m:kQ:V";
6730 const char *md_shortopts = "lSA:m:k";
6733 struct option md_longopts[] = {
6734 #define OPTION_PIC (OPTION_MD_BASE)
6735 {"pic", no_argument, NULL, OPTION_PIC},
6736 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6737 {"register-prefix-optional", no_argument, NULL,
6738 OPTION_REGISTER_PREFIX_OPTIONAL},
6739 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6740 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6741 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6742 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6743 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6744 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6745 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6746 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6747 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6748 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6749 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6750 {"pcrel", no_argument, NULL, OPTION_PCREL},
6751 {NULL, no_argument, NULL, 0}
6753 size_t md_longopts_size = sizeof (md_longopts);
6756 md_parse_option (c, arg)
6762 case 'l': /* -l means keep external to 2 bit offset
6763 rather than 16 bit one */
6764 flag_short_refs = 1;
6767 case 'S': /* -S means that jbsr's always turn into
6769 flag_long_jumps = 1;
6772 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6773 branches into absolute jumps. */
6774 flag_keep_pcrel = 1;
6780 /* intentional fall-through */
6783 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6787 const char *oarg = arg;
6793 if (arg[0] == 'c' && arg[1] == '6')
6796 for (i = 0; i < n_archs; i++)
6797 if (!strcmp (arg, archs[i].name))
6802 as_bad (_("unrecognized option `%s'"), oarg);
6805 arch = archs[i].arch;
6808 else if (arch == m68851)
6817 if (arg[0] == 'c' && arg[1] == '6')
6820 for (i = 0; i < n_archs; i++)
6821 if (!strcmp (arg, archs[i].name))
6823 unsigned long arch = archs[i].arch;
6824 if (cpu_of_arch (arch))
6825 /* It's a cpu spec. */
6827 current_architecture &= ~m68000up;
6828 current_architecture |= arch;
6830 else if (arch == m68881)
6832 current_architecture |= m68881;
6835 else if (arch == m68851)
6837 current_architecture |= m68851;
6847 as_bad (_("unrecognized architecture specification `%s'"), arg);
6856 break; /* -pic, Position Independent Code */
6858 case OPTION_REGISTER_PREFIX_OPTIONAL:
6859 flag_reg_prefix_optional = 1;
6860 reg_prefix_optional_seen = 1;
6863 /* -V: SVR4 argument to print version ID. */
6865 print_version_id ();
6868 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6869 should be emitted or not. FIXME: Not implemented. */
6873 case OPTION_BITWISE_OR:
6878 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6880 for (s = m68k_comment_chars; *s != '\0'; s++)
6884 m68k_comment_chars = n;
6888 case OPTION_BASE_SIZE_DEFAULT_16:
6889 m68k_index_width_default = SIZE_WORD;
6892 case OPTION_BASE_SIZE_DEFAULT_32:
6893 m68k_index_width_default = SIZE_LONG;
6896 case OPTION_DISP_SIZE_DEFAULT_16:
6898 m68k_rel32_from_cmdline = 1;
6901 case OPTION_DISP_SIZE_DEFAULT_32:
6903 m68k_rel32_from_cmdline = 1;
6914 md_show_usage (stream)
6917 const char *default_cpu = TARGET_CPU;
6918 int default_arch, i;
6920 /* Get the canonical name for the default target CPU. */
6921 if (*default_cpu == 'm')
6923 for (i = 0; i < n_archs; i++)
6925 if (strcasecmp (default_cpu, archs[i].name) == 0)
6927 default_arch = archs[i].arch;
6928 for (i = 0; i < n_archs; i++)
6930 if (archs[i].arch == default_arch
6933 default_cpu = archs[i].name;
6940 fprintf (stream, _("\
6942 -l use 1 word for refs to undefined symbols [default 2]\n\
6943 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6944 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6945 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6946 specify variant of 680X0 architecture [default %s]\n\
6947 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6948 target has/lacks floating-point coprocessor\n\
6949 [default yes for 68020, 68030, and cpu32]\n"),
6951 fprintf (stream, _("\
6952 -m68851 | -mno-68851\n\
6953 target has/lacks memory-management unit coprocessor\n\
6954 [default yes for 68020 and up]\n\
6955 -pic, -k generate position independent code\n\
6956 -S turn jbsr into jsr\n\
6957 --pcrel never turn PC-relative branches into absolute jumps\n\
6958 --register-prefix-optional\n\
6959 recognize register names without prefix character\n\
6960 --bitwise-or do not treat `|' as a comment character\n"));
6961 fprintf (stream, _("\
6962 --base-size-default-16 base reg without size is 16 bits\n\
6963 --base-size-default-32 base reg without size is 32 bits (default)\n\
6964 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6965 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6970 /* TEST2: Test md_assemble() */
6971 /* Warning, this routine probably doesn't work anymore */
6975 struct m68k_it the_ins;
6983 if (!gets (buf) || !*buf)
6985 if (buf[0] == '|' || buf[1] == '.')
6987 for (cp = buf; *cp; cp++)
6992 memset (&the_ins, '\0', sizeof (the_ins));
6993 m68k_ip (&the_ins, buf);
6996 printf (_("Error %s in %s\n"), the_ins.error, buf);
7000 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7001 for (n = 0; n < the_ins.numo; n++)
7002 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7004 print_the_insn (&the_ins.opcode[0], stdout);
7005 (void) putchar ('\n');
7007 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7009 if (the_ins.operands[n].error)
7011 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7014 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7015 if (the_ins.operands[n].b_const)
7016 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7017 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7018 if (the_ins.operands[n].b_iadd)
7019 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7020 (void) putchar ('\n');
7032 while (*str && *str != ' ')
7034 if (str[-1] == ':' || str[1] == '=')
7041 /* Possible states for relaxation:
7043 0 0 branch offset byte (bra, etc)
7047 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7051 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7058 /* We have no need to default values of symbols. */
7061 md_undefined_symbol (name)
7062 char *name ATTRIBUTE_UNUSED;
7067 /* Round up a section size to the appropriate boundary. */
7069 md_section_align (segment, size)
7070 segT segment ATTRIBUTE_UNUSED;
7074 #ifdef BFD_ASSEMBLER
7075 /* For a.out, force the section size to be aligned. If we don't do
7076 this, BFD will align it for us, but it will not write out the
7077 final bytes of the section. This may be a bug in BFD, but it is
7078 easier to fix it here since that is how the other a.out targets
7082 align = bfd_get_section_alignment (stdoutput, segment);
7083 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7090 /* Exactly what point is a PC-relative offset relative TO?
7091 On the 68k, it is relative to the address of the first extension
7092 word. The difference between the addresses of the offset and the
7093 first extension word is stored in fx_pcrel_adjust. */
7095 md_pcrel_from (fixP)
7100 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7101 sign extend the value here. */
7102 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7105 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7108 #ifndef BFD_ASSEMBLER
7112 tc_coff_symbol_emit_hook (ignore)
7113 symbolS *ignore ATTRIBUTE_UNUSED;
7118 tc_coff_sizemachdep (frag)
7121 switch (frag->fr_subtype & 0x3)
7139 m68k_elf_final_processing ()
7141 /* Set file-specific flags if this is a cpu32 processor */
7142 if (cpu_of_arch (current_architecture) & cpu32)
7143 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7144 else if ((cpu_of_arch (current_architecture) & m68000up)
7145 && !(cpu_of_arch (current_architecture) & m68020up))
7146 elf_elfheader (stdoutput)->e_flags |= EF_M68000;